From 1bb58b15c3b032ca5c2dfdd6419ac7c1c244b729 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 28 Jul 2025 00:05:24 +0530
Subject: [PATCH 001/326] Stabilize `sse4a` and `tbm` target features  - remove
 some stabilized target features from `gate.rs`

---
 crates/core_arch/src/lib.rs | 2 --
 1 file changed, 2 deletions(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index c58580f641..7d3cbd55ad 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -18,8 +18,6 @@
     rustc_attrs,
     staged_api,
     doc_cfg,
-    tbm_target_feature,
-    sse4a_target_feature,
     riscv_target_feature,
     arm_target_feature,
     mips_target_feature,

From 38cebbae0637392e9a7b1b6eefe2afd09b2224f3 Mon Sep 17 00:00:00 2001
From: ltdk <usr@ltdk.xyz>
Date: Wed, 17 Sep 2025 14:07:23 -0400
Subject: [PATCH 002/326] Mark float intrinsics with no preconditions as safe

---
 crates/core_arch/src/aarch64/neon/generated.rs   | 12 ++++++------
 crates/core_arch/src/wasm32/mod.rs               | 16 ++++++++--------
 .../stdarch-gen-arm/spec/neon/aarch64.spec.yml   | 12 ++++++------
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index bc4c438038..40612660d4 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -10183,7 +10183,7 @@ pub fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
-    unsafe { fmaf16(b, c, a) }
+    fmaf16(b, c, a)
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
@@ -23045,7 +23045,7 @@ pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(frinta))]
 pub fn vrndah_f16(a: f16) -> f16 {
-    unsafe { roundf16(a) }
+    roundf16(a)
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"]
@@ -23054,7 +23054,7 @@ pub fn vrndah_f16(a: f16) -> f16 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(frintz))]
 pub fn vrndh_f16(a: f16) -> f16 {
-    unsafe { truncf16(a) }
+    truncf16(a)
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
@@ -23229,7 +23229,7 @@ pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(frintm))]
 pub fn vrndmh_f16(a: f16) -> f16 {
-    unsafe { floorf16(a) }
+    floorf16(a)
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"]
@@ -23356,7 +23356,7 @@ pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(frintp))]
 pub fn vrndph_f16(a: f16) -> f16 {
-    unsafe { ceilf16(a) }
+    ceilf16(a)
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
@@ -24846,7 +24846,7 @@ pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 pub fn vsqrth_f16(a: f16) -> f16 {
-    unsafe { sqrtf16(a) }
+    sqrtf16(a)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
diff --git a/crates/core_arch/src/wasm32/mod.rs b/crates/core_arch/src/wasm32/mod.rs
index 60049c7329..01bf0a7165 100644
--- a/crates/core_arch/src/wasm32/mod.rs
+++ b/crates/core_arch/src/wasm32/mod.rs
@@ -43,7 +43,7 @@ pub fn unreachable() -> ! {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f32_ceil(a: f32) -> f32 {
-    unsafe { crate::intrinsics::ceilf32(a) }
+    crate::intrinsics::ceilf32(a)
 }
 
 /// Generates the [`f32.floor`] instruction, returning the largest integer less than or equal to `a`.
@@ -57,7 +57,7 @@ pub fn f32_ceil(a: f32) -> f32 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f32_floor(a: f32) -> f32 {
-    unsafe { crate::intrinsics::floorf32(a) }
+    crate::intrinsics::floorf32(a)
 }
 
 /// Generates the [`f32.trunc`] instruction, roundinging to the nearest integer towards zero.
@@ -71,7 +71,7 @@ pub fn f32_floor(a: f32) -> f32 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f32_trunc(a: f32) -> f32 {
-    unsafe { crate::intrinsics::truncf32(a) }
+    crate::intrinsics::truncf32(a)
 }
 
 /// Generates the [`f32.nearest`] instruction, roundinging to the nearest integer. Rounds half-way
@@ -100,7 +100,7 @@ pub fn f32_nearest(a: f32) -> f32 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f32_sqrt(a: f32) -> f32 {
-    unsafe { crate::intrinsics::sqrtf32(a) }
+    crate::intrinsics::sqrtf32(a)
 }
 
 /// Generates the [`f64.ceil`] instruction, returning the smallest integer greater than or equal to `a`.
@@ -114,7 +114,7 @@ pub fn f32_sqrt(a: f32) -> f32 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f64_ceil(a: f64) -> f64 {
-    unsafe { crate::intrinsics::ceilf64(a) }
+    crate::intrinsics::ceilf64(a)
 }
 
 /// Generates the [`f64.floor`] instruction, returning the largest integer less than or equal to `a`.
@@ -128,7 +128,7 @@ pub fn f64_ceil(a: f64) -> f64 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f64_floor(a: f64) -> f64 {
-    unsafe { crate::intrinsics::floorf64(a) }
+    crate::intrinsics::floorf64(a)
 }
 
 /// Generates the [`f64.trunc`] instruction, roundinging to the nearest integer towards zero.
@@ -142,7 +142,7 @@ pub fn f64_floor(a: f64) -> f64 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f64_trunc(a: f64) -> f64 {
-    unsafe { crate::intrinsics::truncf64(a) }
+    crate::intrinsics::truncf64(a)
 }
 
 /// Generates the [`f64.nearest`] instruction, roundinging to the nearest integer. Rounds half-way
@@ -171,7 +171,7 @@ pub fn f64_nearest(a: f64) -> f64 {
 #[must_use = "method returns a new number and does not mutate the original value"]
 #[unstable(feature = "wasm_numeric_instr", issue = "133908")]
 pub fn f64_sqrt(a: f64) -> f64 {
-    unsafe { crate::intrinsics::sqrtf64(a) }
+    crate::intrinsics::sqrtf64(a)
 }
 
 unsafe extern "C-unwind" {
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a31613e6b1..ece435870a 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -3054,7 +3054,7 @@ intrinsics:
     types:
       - [f16, 'h_']
     compose:
-      - FnCall: [roundf16, [a], [], true]
+      - FnCall: [roundf16, [a], []]
 
   - name: "vrndn{neon_type.no}"
     doc: "Floating-point round to integral, to nearest with ties to even"
@@ -3151,7 +3151,7 @@ intrinsics:
     types:
       - [f16, 'h_']
     compose:
-      - FnCall: [floorf16, [a], [], true]
+      - FnCall: [floorf16, [a], []]
 
 
 
@@ -3198,7 +3198,7 @@ intrinsics:
     types:
       - [f16, 'h_']
     compose:
-      - FnCall: [ceilf16, [a], [], true]
+      - FnCall: [ceilf16, [a], []]
 
   - name: "vrnd{neon_type.no}"
     doc: "Floating-point round to integral, toward zero"
@@ -3243,7 +3243,7 @@ intrinsics:
     types:
       - [f16, 'h_']
     compose:
-      - FnCall: [truncf16, [a], [], true]
+      - FnCall: [truncf16, [a], []]
 
 
   - name: "vrndi{neon_type.no}"
@@ -8398,7 +8398,7 @@ intrinsics:
     types:
       - [f16, 'h_']
     compose:
-      - FnCall: [sqrtf16, [a], [], true]
+      - FnCall: [sqrtf16, [a], []]
 
   - name: "vrsqrts{type[0]}"
     doc: "Floating-point reciprocal square root step"
@@ -10346,7 +10346,7 @@ intrinsics:
     types:
       - ["f16", "h_f16"]
     compose:
-      - FnCall: [fmaf16, [b, c, a], [], true]
+      - FnCall: [fmaf16, [b, c, a], []]
 
 
   - name: "vfmah_lane{type[2]}"

From d28b44b03d2ada641f0d42f31b9bb1d6c756045b Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 25 Oct 2025 18:36:19 +0200
Subject: [PATCH 003/326] intrinsic test: deduplicate rust constants

---
 crates/intrinsic-test/src/common/argument.rs | 42 +++++++++++++++-----
 crates/intrinsic-test/src/common/gen_rust.rs | 17 +++++++-
 2 files changed, 47 insertions(+), 12 deletions(-)

diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 5fb7d0f210..385cf32d3b 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -60,9 +60,15 @@ where
     }
 
     /// The name (e.g. "A_VALS" or "a_vals") for the array of possible test inputs.
-    fn rust_vals_array_name(&self) -> impl std::fmt::Display {
+    pub(crate) fn rust_vals_array_name(&self) -> impl std::fmt::Display {
         if self.ty.is_rust_vals_array_const() {
-            format!("{}_VALS", self.name.to_uppercase())
+            let loads = crate::common::gen_rust::PASSES;
+            format!(
+                "{}_{ty}_{load_size}",
+                self.name.to_uppercase(),
+                ty = self.ty.rust_scalar_type(),
+                load_size = self.ty.num_lanes() * self.ty.num_vectors() + loads - 1,
+            )
         } else {
             format!("{}_vals", self.name.to_lowercase())
         }
@@ -134,20 +140,34 @@ where
         loads: u32,
     ) -> std::io::Result<()> {
         for arg in self.iter().filter(|&arg| !arg.has_constraint()) {
-            writeln!(
-                w,
-                "{indentation}{bind} {name}: [{ty}; {load_size}] = {values};",
-                bind = arg.rust_vals_array_binding(),
-                name = arg.rust_vals_array_name(),
-                ty = arg.ty.rust_scalar_type(),
-                load_size = arg.ty.num_lanes() * arg.ty.num_vectors() + loads - 1,
-                values = arg.ty.populate_random(indentation, loads, &Language::Rust)
-            )?
+            // Constants are defined globally.
+            if arg.ty.is_rust_vals_array_const() {
+                continue;
+            }
+
+            Self::gen_arg_rust(arg, w, indentation, loads)?;
         }
 
         Ok(())
     }
 
+    pub fn gen_arg_rust(
+        arg: &Argument<T>,
+        w: &mut impl std::io::Write,
+        indentation: Indentation,
+        loads: u32,
+    ) -> std::io::Result<()> {
+        writeln!(
+            w,
+            "{indentation}{bind} {name}: [{ty}; {load_size}] = {values};\n",
+            bind = arg.rust_vals_array_binding(),
+            name = arg.rust_vals_array_name(),
+            ty = arg.ty.rust_scalar_type(),
+            load_size = arg.ty.num_lanes() * arg.ty.num_vectors() + loads - 1,
+            values = arg.ty.populate_random(indentation, loads, &Language::Rust)
+        )
+    }
+
     /// Creates a line for each argument that initializes the argument from an array `[arg]_vals` at
     /// an offset `i` using a load intrinsic, in C.
     /// e.g `uint8x8_t a = vld1_u8(&a_vals[i]);`
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index 27f49a37b1..00bcf04850 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -1,13 +1,14 @@
 use itertools::Itertools;
 use std::process::Command;
 
+use crate::common::argument::ArgumentList;
 use crate::common::intrinsic::Intrinsic;
 
 use super::indentation::Indentation;
 use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
 // The number of times each intrinsic will be called.
-const PASSES: u32 = 20;
+pub(crate) const PASSES: u32 = 20;
 
 fn write_cargo_toml_header(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> {
     writeln!(
@@ -118,6 +119,20 @@ pub fn write_lib_rs<T: IntrinsicTypeDefinition>(
 
     writeln!(w, "{definitions}")?;
 
+    let mut seen = std::collections::HashSet::new();
+
+    for intrinsic in intrinsics {
+        for arg in &intrinsic.arguments.args {
+            if !arg.has_constraint() && arg.ty.is_rust_vals_array_const() {
+                let name = arg.rust_vals_array_name().to_string();
+
+                if seen.insert(name) {
+                    ArgumentList::gen_arg_rust(arg, w, Indentation::default(), PASSES)?;
+                }
+            }
+        }
+    }
+
     for intrinsic in intrinsics {
         crate::common::gen_rust::create_rust_test_module(w, intrinsic)?;
     }

From e02ced7cad4428fdb55ca4ffa0056fac92bc346c Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 25 Oct 2025 18:50:02 +0200
Subject: [PATCH 004/326] intrinsic test: fix formatting (a bit, at least)

---
 crates/intrinsic-test/src/common/gen_rust.rs  | 48 +++++++++++--------
 .../intrinsic-test/src/common/indentation.rs  |  4 ++
 2 files changed, 31 insertions(+), 21 deletions(-)

diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index 00bcf04850..c8d815e46e 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -10,16 +10,22 @@ use super::intrinsic_helpers::IntrinsicTypeDefinition;
 // The number of times each intrinsic will be called.
 pub(crate) const PASSES: u32 = 20;
 
+macro_rules! concatln {
+    ($($lines:expr),* $(,)?) => {
+        concat!($( $lines, "\n" ),*)
+    };
+}
+
 fn write_cargo_toml_header(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> {
     writeln!(
         w,
-        concat!(
-            "[package]\n",
-            "name = \"{name}\"\n",
-            "version = \"{version}\"\n",
-            "authors = [{authors}]\n",
-            "license = \"{license}\"\n",
-            "edition = \"2018\"\n",
+        concatln!(
+            "[package]",
+            "name = \"{name}\"",
+            "version = \"{version}\"",
+            "authors = [{authors}]",
+            "license = \"{license}\"",
+            "edition = \"2018\"",
         ),
         name = name,
         version = env!("CARGO_PKG_VERSION"),
@@ -247,23 +253,23 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
         }
     }
 
-    let indentation2 = indentation.nested();
-    let indentation3 = indentation2.nested();
-    writeln!(
+    write!(
         w,
-        "\
-            for (id, f) in specializations {{\n\
-                for i in 0..{passes} {{\n\
-                    unsafe {{\n\
-                        {loaded_args}\
-                        let __return_value = f({args});\n\
-                        println!(\"Result {{id}}-{{}}: {{:?}}\", i + 1, {return_value});\n\
-                    }}\n\
-                }}\n\
-            }}",
-        loaded_args = intrinsic.arguments.load_values_rust(indentation3),
+        concatln!(
+            "    for (id, f) in specializations {{",
+            "        for i in 0..{passes} {{",
+            "            unsafe {{",
+            "{loaded_args}",
+            "                let __return_value = f({args});",
+            "                println!(\"Result {{id}}-{{}}: {{:?}}\", i + 1, {return_value});",
+            "            }}",
+            "        }}",
+            "    }}",
+        ),
+        loaded_args = intrinsic.arguments.load_values_rust(indentation.nest_by(4)),
         args = intrinsic.arguments.as_call_param_rust(),
         return_value = intrinsic.results.print_result_rust(),
+        passes = passes,
     )
 }
 
diff --git a/crates/intrinsic-test/src/common/indentation.rs b/crates/intrinsic-test/src/common/indentation.rs
index 9ee331d7f7..9c2cc886e6 100644
--- a/crates/intrinsic-test/src/common/indentation.rs
+++ b/crates/intrinsic-test/src/common/indentation.rs
@@ -10,6 +10,10 @@ impl Indentation {
     pub fn nested(self) -> Self {
         Self(self.0 + 1)
     }
+
+    pub fn nest_by(&self, additional_levels: u32) -> Self {
+        Self(self.0 + additional_levels)
+    }
 }
 
 impl std::fmt::Display for Indentation {

From 15466e90e591baff4744495329316108837191df Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 26 Oct 2025 16:38:46 +0100
Subject: [PATCH 005/326] forward `TEST_SAMPLE_INTRINSICS_PERCENTAGE`

---
 ci/intrinsic-test-docker.sh                 |  1 +
 ci/intrinsic-test.sh                        |  9 +++++++--
 crates/intrinsic-test/src/arm/mod.rs        |  8 ++++++--
 crates/intrinsic-test/src/common/compare.rs |  6 +++++-
 crates/intrinsic-test/src/x86/mod.rs        | 15 +++++++--------
 5 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/ci/intrinsic-test-docker.sh b/ci/intrinsic-test-docker.sh
index 038fc4678e..f62d7e484f 100755
--- a/ci/intrinsic-test-docker.sh
+++ b/ci/intrinsic-test-docker.sh
@@ -36,6 +36,7 @@ run() {
       --env NORUN \
       --env RUSTFLAGS \
       --env CARGO_UNSTABLE_BUILD_STD \
+      --env TEST_SAMPLE_INTRINSICS_PERCENTAGE \
       --volume "${HOME}/.cargo":/cargo \
       --volume "$(rustc --print sysroot)":/rust:ro \
       --volume "$(pwd)":/checkout:ro \
diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index e14a824b2a..be309f9e42 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -51,6 +51,7 @@ case ${TARGET} in
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}"
+        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}"
         ;;
 
     aarch64_be-unknown-linux-gnu*)
@@ -58,6 +59,7 @@ case ${TARGET} in
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER}"
+        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}"
         ;;
 
     armv7-unknown-linux-gnueabihf*)
@@ -65,6 +67,7 @@ case ${TARGET} in
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_arm.txt
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}"
+        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}"
         ;;
 
     x86_64-unknown-linux-gnu*)
@@ -72,7 +75,7 @@ case ${TARGET} in
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
-        TEST_SAMPLE_INTRINSICS_PERCENTAGE=5
+        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=5}"
         ;;
     *)
         ;;
@@ -88,7 +91,8 @@ case "${TARGET}" in
             --runner "${TEST_RUNNER}" \
             --cppcompiler "${TEST_CXX_COMPILER}" \
             --skip "${TEST_SKIP_INTRINSICS}" \
-            --target "${TARGET}"
+            --target "${TARGET}" \
+            --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}"
         ;;
 
     aarch64_be-unknown-linux-gnu*)
@@ -99,6 +103,7 @@ case "${TARGET}" in
             --cppcompiler "${TEST_CXX_COMPILER}" \
             --skip "${TEST_SKIP_INTRINSICS}" \
             --target "${TARGET}" \
+            --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" \
             --linker "${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER}" \
             --cxx-toolchain-dir "${AARCH64_BE_TOOLCHAIN}"
         ;;
diff --git a/crates/intrinsic-test/src/arm/mod.rs b/crates/intrinsic-test/src/arm/mod.rs
index 7fa5062e86..99c8da854c 100644
--- a/crates/intrinsic-test/src/arm/mod.rs
+++ b/crates/intrinsic-test/src/arm/mod.rs
@@ -48,8 +48,12 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
             .expect("Error parsing input file");
 
         intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
+        intrinsics.dedup();
+
+        let sample_percentage: usize = cli_options.sample_percentage as usize;
+        let sample_size = (intrinsics.len() * sample_percentage) / 100;
 
-        let mut intrinsics = intrinsics
+        let intrinsics = intrinsics
             .into_iter()
             // Not sure how we would compare intrinsic that returns void.
             .filter(|i| i.results.kind() != TypeKind::Void)
@@ -61,8 +65,8 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
             .filter(|i| !i.arguments.iter().any(|a| a.ty.inner_size() == 128))
             .filter(|i| !cli_options.skip.contains(&i.name))
             .filter(|i| !(a32 && i.arch_tags == vec!["A64".to_string()]))
+            .take(sample_size)
             .collect::<Vec<_>>();
-        intrinsics.dedup();
 
         Self {
             intrinsics,
diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 902df94283..c0459b743a 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -86,6 +86,10 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
             println!("Failed to run rust program for intrinsic {intrinsic}")
         }
     });
-    println!("{} differences found", intrinsics.len());
+    println!(
+        "{} differences found (tested {} intrinsics)",
+        intrinsics.len(),
+        intrinsic_name_list.len()
+    );
     intrinsics.is_empty()
 }
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 956e51836f..4adf85017b 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -11,7 +11,6 @@ use crate::common::compile_c::CppCompilation;
 use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
 use intrinsic::X86IntrinsicType;
-use itertools::Itertools;
 use xml_parser::get_xml_intrinsics;
 
 pub struct X86ArchitectureTest {
@@ -44,12 +43,16 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS;
 
     fn create(cli_options: ProcessedCli) -> Self {
-        let intrinsics =
+        let mut intrinsics =
             get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file");
 
+        intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
+        intrinsics.dedup();
+
         let sample_percentage: usize = cli_options.sample_percentage as usize;
+        let sample_size = (intrinsics.len() * sample_percentage) / 100;
 
-        let mut intrinsics = intrinsics
+        let intrinsics = intrinsics
             .into_iter()
             // Not sure how we would compare intrinsic that returns void.
             .filter(|i| i.results.kind() != TypeKind::Void)
@@ -61,13 +64,9 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             .filter(|i| !i.arguments.iter().any(|a| a.is_ptr()))
             .filter(|i| !i.arguments.iter().any(|a| a.ty.inner_size() == 128))
             .filter(|i| !cli_options.skip.contains(&i.name))
-            .unique_by(|i| i.name.clone())
+            .take(sample_size)
             .collect::<Vec<_>>();
 
-        let sample_size = (intrinsics.len() * sample_percentage) / 100;
-        intrinsics.truncate(sample_size);
-
-        intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
         Self {
             intrinsics: intrinsics,
             cli_options: cli_options,

From 1062fc693c7d35b8c80ae22448a11b51b2c466ce Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 26 Oct 2025 19:28:46 +0100
Subject: [PATCH 006/326] intrinsic-test: display more logs in CI

---
 ci/intrinsic-test.sh                    |  6 +++---
 crates/intrinsic-test/src/common/mod.rs | 12 ++++++++----
 crates/intrinsic-test/src/main.rs       |  2 +-
 crates/intrinsic-test/src/x86/mod.rs    |  2 +-
 4 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index be309f9e42..be63f0c0c6 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -85,7 +85,7 @@ esac
 # Arm specific
 case "${TARGET}" in
     aarch64-unknown-linux-gnu*|armv7-unknown-linux-gnueabihf*)
-        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \
+        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=info \
             cargo run "${INTRINSIC_TEST}" "${PROFILE}" \
             --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \
             --runner "${TEST_RUNNER}" \
@@ -96,7 +96,7 @@ case "${TARGET}" in
         ;;
 
     aarch64_be-unknown-linux-gnu*)
-        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \
+        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=info \
             cargo run "${INTRINSIC_TEST}" "${PROFILE}"  \
             --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \
             --runner "${TEST_RUNNER}" \
@@ -114,7 +114,7 @@ case "${TARGET}" in
         # Hence the use of `env -u`.
         env -u CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER \
             CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" \
-            RUST_LOG=warn RUST_BACKTRACE=1 \
+            RUST_LOG=info RUST_BACKTRACE=1 \
             cargo run "${INTRINSIC_TEST}" "${PROFILE}"  \
             --bin intrinsic-test -- intrinsics_data/x86-intel.xml \
             --runner "${TEST_RUNNER}" \
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index d8f06ae238..8b6bd943a7 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -79,12 +79,16 @@ pub trait SupportedArchitectureTest {
                 trace!("compiling mod_{i}.cpp");
                 if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
                     let compile_output = cpp_compiler
-                        .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"));
+                        .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))
+                        .map_err(|e| format!("Error compiling mod_{i}.cpp: {e:?}"))?;
+
+                    assert!(
+                        compile_output.status.success(),
+                        "{}",
+                        String::from_utf8_lossy(&compile_output.stderr)
+                    );
 
                     trace!("finished compiling mod_{i}.cpp");
-                    if let Err(compile_error) = compile_output {
-                        return Err(format!("Error compiling mod_{i}.cpp: {compile_error:?}"));
-                    }
                 }
                 Ok(())
             })
diff --git a/crates/intrinsic-test/src/main.rs b/crates/intrinsic-test/src/main.rs
index ed3a50067d..3580d80bd1 100644
--- a/crates/intrinsic-test/src/main.rs
+++ b/crates/intrinsic-test/src/main.rs
@@ -34,7 +34,7 @@ fn run(test_environment: impl SupportedArchitectureTest) {
     if !test_environment.build_rust_file() {
         std::process::exit(3);
     }
-    info!("comaparing outputs");
+    info!("comparing outputs");
     if !test_environment.compare_outputs() {
         std::process::exit(1);
     }
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 4adf85017b..f2baf07071 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -47,7 +47,7 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file");
 
         intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
-        intrinsics.dedup();
+        intrinsics.dedup_by(|a, b| a.name == b.name);
 
         let sample_percentage: usize = cli_options.sample_percentage as usize;
         let sample_size = (intrinsics.len() * sample_percentage) / 100;

From 30ac45935f011a0ef20de59eadbb51e4fd472134 Mon Sep 17 00:00:00 2001
From: Alisa Sireneva <me@purplesyringa.moe>
Date: Thu, 30 Oct 2025 12:22:19 +0300
Subject: [PATCH 007/326] Move wasm `throw` intrinsic back to `unwind`

rustc assumes that regular `extern "Rust"` functions unwind only if the
`unwind` panic runtime is linked. `throw` was annotated as such, but
unwound unconditionally. This could cause UB when a crate built with `-C
panic=abort` called `throw` from `core` built with `-C panic=unwind`,
since no terminator was added to handle the panic arising from calling an
allegedly non-unwinding `extern "Rust"` function.

rustc was taught to recognize this condition since
https://github.com/rust-lang/rust/pull/144225 and prevented such
linkage, but this caused regressions in
https://github.com/rust-lang/rust/issues/148246, since this meant that
Emscripten projects could not be built with `-C panic=abort` without
recompiling std.

The most straightforward solution would be to move `throw` into the
`panic_unwind` crate, so that it's only compiled if the panic runtime is
guaranteed to be `unwind`, but this is messy due to our architecture.
Instead, move it into `unwind::wasm`, which is only compiled for
bare-metal targets that default to `panic = "abort"`, rendering the
issue moot.
---
 crates/core_arch/src/wasm32/mod.rs | 32 ------------------------------
 1 file changed, 32 deletions(-)

diff --git a/crates/core_arch/src/wasm32/mod.rs b/crates/core_arch/src/wasm32/mod.rs
index 01bf0a7165..57c9157bed 100644
--- a/crates/core_arch/src/wasm32/mod.rs
+++ b/crates/core_arch/src/wasm32/mod.rs
@@ -173,35 +173,3 @@ pub fn f64_nearest(a: f64) -> f64 {
 pub fn f64_sqrt(a: f64) -> f64 {
     crate::intrinsics::sqrtf64(a)
 }
-
-unsafe extern "C-unwind" {
-    #[link_name = "llvm.wasm.throw"]
-    fn wasm_throw(tag: i32, ptr: *mut u8) -> !;
-}
-
-/// Generates the [`throw`] instruction from the [exception-handling proposal] for WASM.
-///
-/// This function is unlikely to be stabilized until codegen backends have better support.
-///
-/// [`throw`]: https://webassembly.github.io/exception-handling/core/syntax/instructions.html#syntax-instr-control
-/// [exception-handling proposal]: https://github.com/WebAssembly/exception-handling
-// FIXME: wasmtime does not currently support exception-handling, so cannot execute
-//        a wasm module with the throw instruction in it. once it does, we can
-//        reenable this attribute.
-// #[cfg_attr(test, assert_instr(throw, TAG = 0, ptr = core::ptr::null_mut()))]
-#[inline]
-#[unstable(feature = "wasm_exception_handling_intrinsics", issue = "122465")]
-// FIXME: Since this instruction unwinds, `core` built with `-C panic=unwind`
-//        cannot be linked with `-C panic=abort` programs. But that's not
-//        entirely supported anyway, because runtimes without EH support won't
-//        be able to handle `try` blocks in `-C panic=unwind` crates either.
-//        We ship `-C panic=abort` `core`, so this doesn't affect users
-//        directly. Resolving this will likely require patching out both `try`
-//        and `throw` instructions, at which point we can look into whitelisting
-//        this function in the compiler to allow linking.
-//        See https://github.com/rust-lang/rust/issues/118168.
-#[allow(ffi_unwind_calls)]
-pub unsafe fn throw<const TAG: i32>(ptr: *mut u8) -> ! {
-    static_assert!(TAG == 0); // LLVM only supports tag 0 == C++ right now.
-    wasm_throw(TAG, ptr)
-}

From 4bf9a900a46164aa5af0626515ca10b495ed6e1c Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sun, 6 Apr 2025 19:40:15 +0530
Subject: [PATCH 008/326] Add AMX intrinsics

---
 crates/core_arch/src/lib.rs        |   3 +-
 crates/core_arch/src/x86_64/amx.rs | 224 +++++++++++++++++++++++++++++
 2 files changed, 226 insertions(+), 1 deletion(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 26a9cb5899..dcd19186a1 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -34,7 +34,8 @@
     f16,
     aarch64_unstable_target_feature,
     bigint_helper_methods,
-    funnel_shifts
+    funnel_shifts,
+    avx10_target_feature
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]
diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index 4b33c0ab6c..6d896c4918 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -1,3 +1,5 @@
+use crate::core_arch::{simd::*, x86::*};
+
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
@@ -242,6 +244,206 @@ pub unsafe fn _tile_cmmrlfp16ps<const DST: i32, const A: i32, const B: i32>() {
     tcmmrlfp16ps(DST as i8, A as i8, B as i8);
 }
 
+/// Compute dot-product of BF8 (8-bit E5M2) floating-point elements in tile a and BF8 (8-bit E5M2)
+/// floating-point elements in tile b, accumulating the intermediate single-precision
+/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result
+/// back to tile dst.
+#[inline]
+#[rustc_legacy_const_generics(0, 1, 2)]
+#[target_feature(enable = "amx-fp8")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tdpbf8ps, DST = 0, A = 1, B = 2)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_dpbf8ps<const DST: i32, const A: i32, const B: i32>() {
+    static_assert_uimm_bits!(DST, 3);
+    static_assert_uimm_bits!(A, 3);
+    static_assert_uimm_bits!(B, 3);
+    tdpbf8ps(DST as i8, A as i8, B as i8);
+}
+
+/// Compute dot-product of BF8 (8-bit E5M2) floating-point elements in tile a and HF8
+/// (8-bit E4M3) floating-point elements in tile b, accumulating the intermediate single-precision
+/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result
+/// back to tile dst.
+#[inline]
+#[rustc_legacy_const_generics(0, 1, 2)]
+#[target_feature(enable = "amx-fp8")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tdpbhf8ps, DST = 0, A = 1, B = 2)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_dpbhf8ps<const DST: i32, const A: i32, const B: i32>() {
+    static_assert_uimm_bits!(DST, 3);
+    static_assert_uimm_bits!(A, 3);
+    static_assert_uimm_bits!(B, 3);
+    tdpbhf8ps(DST as i8, A as i8, B as i8);
+}
+
+/// Compute dot-product of HF8 (8-bit E4M3) floating-point elements in tile a and BF8
+/// (8-bit E5M2) floating-point elements in tile b, accumulating the intermediate single-precision
+/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result
+/// back to tile dst.
+#[inline]
+#[rustc_legacy_const_generics(0, 1, 2)]
+#[target_feature(enable = "amx-fp8")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tdphbf8ps, DST = 0, A = 1, B = 2)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_dphbf8ps<const DST: i32, const A: i32, const B: i32>() {
+    static_assert_uimm_bits!(DST, 3);
+    static_assert_uimm_bits!(A, 3);
+    static_assert_uimm_bits!(B, 3);
+    tdphbf8ps(DST as i8, A as i8, B as i8);
+}
+
+/// Compute dot-product of HF8 (8-bit E4M3) floating-point elements in tile a and HF8 (8-bit E4M3)
+/// floating-point elements in tile b, accumulating the intermediate single-precision
+/// (32-bit) floating-point elements with elements in dst, and store the 32-bit result
+/// back to tile dst.
+#[inline]
+#[rustc_legacy_const_generics(0, 1, 2)]
+#[target_feature(enable = "amx-fp8")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tdphf8ps, DST = 0, A = 1, B = 2)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_dphf8ps<const DST: i32, const A: i32, const B: i32>() {
+    static_assert_uimm_bits!(DST, 3);
+    static_assert_uimm_bits!(A, 3);
+    static_assert_uimm_bits!(B, 3);
+    tdphf8ps(DST as i8, A as i8, B as i8);
+}
+
+/// Load tile rows from memory specified by base address and stride into destination tile dst
+/// using the tile configuration previously configured via _tile_loadconfig.
+/// Additionally, this intrinsic indicates the source memory location is likely to become
+/// read-shared by multiple processors, i.e., read in the future by at least one other processor
+/// before it is written, assuming it is ever written in the future.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-movrs")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tileloaddrs, DST = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_loaddrs<const DST: i32>(base: *const u8, stride: usize) {
+    static_assert_uimm_bits!(DST, 3);
+    tileloaddrs64(DST as i8, base, stride);
+}
+
+/// Load tile rows from memory specified by base address and stride into destination tile dst
+/// using the tile configuration previously configured via _tile_loadconfig.
+/// Provides a hint to the implementation that the data would be reused but does not need
+/// to be resident in the nearest cache levels.
+/// Additionally, this intrinsic indicates the source memory location is likely to become
+/// read-shared by multiple processors, i.e., read in the future by at least one other processor
+/// before it is written, assuming it is ever written in the future.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-movrs")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tileloaddrst1, DST = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_stream_loaddrs<const DST: i32>(base: *const u8, stride: usize) {
+    static_assert_uimm_bits!(DST, 3);
+    tileloaddrst164(DST as i8, base, stride);
+}
+
+/// Perform matrix multiplication of two tiles a and b, containing packed single precision (32-bit)
+/// floating-point elements, which are converted to TF32 (tensor-float32) format, and accumulate the
+///  results into a packed single precision tile.
+/// For each possible combination of (row of a, column of b), it performs
+///  - convert to TF32
+///  - multiply the corresponding elements of a and b
+///  - accumulate the results into the corresponding row and column of dst using round-to-nearest-even
+/// rounding mode.
+/// Output FP32 denormals are always flushed to zero, input single precision denormals are always
+/// handled and *not* treated as zero.
+#[inline]
+#[rustc_legacy_const_generics(0, 1, 2)]
+#[target_feature(enable = "amx-tf32")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tmmultf32ps, DST = 0, A = 1, B = 2)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_mmultf32ps<const DST: i32, const A: i32, const B: i32>() {
+    static_assert_uimm_bits!(DST, 3);
+    static_assert_uimm_bits!(A, 3);
+    static_assert_uimm_bits!(B, 3);
+    tmmultf32ps(DST as i8, A as i8, B as i8);
+}
+
+/// Moves a row from a tile register to a zmm register, converting the packed 32-bit signed integer
+/// elements to packed single-precision (32-bit) floating-point elements.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowd2ps, TILE = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowd2ps<const TILE: i32>(row: u32) -> __m512 {
+    static_assert_uimm_bits!(TILE, 3);
+    tcvtrowd2ps(TILE as i8, row).as_m512()
+}
+
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2phh, TILE = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2phh<const TILE: i32>(row: u32) -> __m512h {
+    static_assert_uimm_bits!(TILE, 3);
+    tcvtrowps2phh(TILE as i8, row).as_m512h()
+}
+
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2phl, TILE = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2phl<const TILE: i32>(row: u32) -> __m512h {
+    static_assert_uimm_bits!(TILE, 3);
+    tcvtrowps2phl(TILE as i8, row).as_m512h()
+}
+
+/// Moves one row of tile data into a zmm vector register
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tilemovrow, TILE = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_movrow<const TILE: i32>(row: u32) -> __m512i {
+    static_assert_uimm_bits!(TILE, 3);
+    tilemovrow(TILE as i8, row).as_m512i()
+}
+
 #[allow(improper_ctypes)]
 unsafe extern "C" {
     #[link_name = "llvm.x86.ldtilecfg"]
@@ -274,6 +476,28 @@ unsafe extern "C" {
     fn tcmmimfp16ps(dst: i8, a: i8, b: i8);
     #[link_name = "llvm.x86.tcmmrlfp16ps"]
     fn tcmmrlfp16ps(dst: i8, a: i8, b: i8);
+    #[link_name = "llvm.x86.tdpbf8ps"]
+    fn tdpbf8ps(dst: i8, a: i8, b: i8);
+    #[link_name = "llvm.x86.tdpbhf8ps"]
+    fn tdpbhf8ps(dst: i8, a: i8, b: i8);
+    #[link_name = "llvm.x86.tdphbf8ps"]
+    fn tdphbf8ps(dst: i8, a: i8, b: i8);
+    #[link_name = "llvm.x86.tdphf8ps"]
+    fn tdphf8ps(dst: i8, a: i8, b: i8);
+    #[link_name = "llvm.x86.tileloaddrs64"]
+    fn tileloaddrs64(dst: i8, base: *const u8, stride: usize);
+    #[link_name = "llvm.x86.tileloaddrst164"]
+    fn tileloaddrst164(dst: i8, base: *const u8, stride: usize);
+    #[link_name = "llvm.x86.tmmultf32ps"]
+    fn tmmultf32ps(dst: i8, a: i8, b: i8);
+    #[link_name = "llvm.x86.tcvtrowd2ps"]
+    fn tcvtrowd2ps(tile: i8, row: u32) -> f32x16;
+    #[link_name = "llvm.x86.tcvtrowps2phh"]
+    fn tcvtrowps2phh(tile: i8, row: u32) -> f16x32;
+    #[link_name = "llvm.x86.tcvtrowps2phl"]
+    fn tcvtrowps2phl(tile: i8, row: u32) -> f16x32;
+    #[link_name = "llvm.x86.tilemovrow"]
+    fn tilemovrow(tile: i8, row: u32) -> i32x16;
 }
 
 #[cfg(test)]

From 7ea571218318dbc5078907bc59dcb75b9260f857 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 1 Nov 2025 07:51:10 +0530
Subject: [PATCH 009/326] Patch stdarch_verify to not check intel definition
 for new AMX intrinsics

---
 crates/stdarch-verify/tests/x86-intel.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 5a98db980b..4136463f19 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -304,6 +304,14 @@ fn verify_all_signatures() {
             if feature.contains("sse4a") || feature.contains("tbm") {
                 continue;
             }
+
+            // FIXME: these have not been added to Intrinsics Guide yet
+            if ["amx-avx512", "amx-fp8", "amx-movrs", "amx-tf32"]
+                .iter()
+                .any(|f| feature.contains(f))
+            {
+                continue;
+            }
         }
 
         let intel = match map.remove(rust.name) {

From 76b3c7414190639e354bb47b764641618016ebee Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 1 Nov 2025 07:50:36 +0530
Subject: [PATCH 010/326] Add tests for new AMX intrinsics

---
 crates/core_arch/src/x86_64/amx.rs | 228 ++++++++++++++++++++++++++++-
 1 file changed, 227 insertions(+), 1 deletion(-)

diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index 6d896c4918..c87514980d 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -504,7 +504,7 @@ unsafe extern "C" {
 mod tests {
     use crate::core_arch::x86::_mm_cvtness_sbh;
     use crate::core_arch::x86_64::*;
-    use core::mem::transmute;
+    use core::{array, mem::transmute};
     use stdarch_test::simd_test;
     #[cfg(target_os = "linux")]
     use syscalls::{Sysno, syscall};
@@ -843,4 +843,230 @@ mod tests {
         _tile_release();
         assert_eq!(res, [[0f32; 16]; 16]);
     }
+
+    const BF8_ONE: u8 = 0x3c;
+    const BF8_TWO: u8 = 0x40;
+    const HF8_ONE: u8 = 0x38;
+    const HF8_TWO: u8 = 0x40;
+
+    #[simd_test(enable = "amx-fp8")]
+    unsafe fn test_tile_dpbf8ps() {
+        _init_amx();
+        let ones = [BF8_ONE; 1024];
+        let twos = [BF8_TWO; 1024];
+        let mut res = [[0.0_f32; 16]; 16];
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        (0..=2).for_each(|i| {
+            config.colsb[i] = 64;
+            config.rows[i] = 16;
+        });
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        _tile_loadd::<1>(&ones as *const u8, 64);
+        _tile_loadd::<2>(&twos as *const u8, 64);
+        _tile_dpbf8ps::<0, 1, 2>();
+        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+        _tile_release();
+        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    }
+
+    #[simd_test(enable = "amx-fp8")]
+    unsafe fn test_tile_dpbhf8ps() {
+        _init_amx();
+        let ones = [BF8_ONE; 1024];
+        let twos = [HF8_TWO; 1024];
+        let mut res = [[0.0_f32; 16]; 16];
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        (0..=2).for_each(|i| {
+            config.colsb[i] = 64;
+            config.rows[i] = 16;
+        });
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        _tile_loadd::<1>(&ones as *const u8, 64);
+        _tile_loadd::<2>(&twos as *const u8, 64);
+        _tile_dpbhf8ps::<0, 1, 2>();
+        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+        _tile_release();
+        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    }
+
+    #[simd_test(enable = "amx-fp8")]
+    unsafe fn test_tile_dphbf8ps() {
+        _init_amx();
+        let ones = [HF8_ONE; 1024];
+        let twos = [BF8_TWO; 1024];
+        let mut res = [[0.0_f32; 16]; 16];
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        (0..=2).for_each(|i| {
+            config.colsb[i] = 64;
+            config.rows[i] = 16;
+        });
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        _tile_loadd::<1>(&ones as *const u8, 64);
+        _tile_loadd::<2>(&twos as *const u8, 64);
+        _tile_dphbf8ps::<0, 1, 2>();
+        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+        _tile_release();
+        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    }
+
+    #[simd_test(enable = "amx-fp8")]
+    unsafe fn test_tile_dphf8ps() {
+        _init_amx();
+        let ones = [HF8_ONE; 1024];
+        let twos = [HF8_TWO; 1024];
+        let mut res = [[0.0_f32; 16]; 16];
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        (0..=2).for_each(|i| {
+            config.colsb[i] = 64;
+            config.rows[i] = 16;
+        });
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        _tile_loadd::<1>(&ones as *const u8, 64);
+        _tile_loadd::<2>(&twos as *const u8, 64);
+        _tile_dphf8ps::<0, 1, 2>();
+        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+        _tile_release();
+        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    }
+
+    #[simd_test(enable = "amx-tile")]
+    unsafe fn test_tile_loaddrs() {
+        _init_amx();
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        config.colsb[0] = 64;
+        config.rows[0] = 16;
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        let mat = [1_i8; 1024];
+        _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
+        let mut out = [[0_i8; 64]; 16];
+        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+        _tile_release();
+        assert_eq!(out, [[1; 64]; 16]);
+    }
+
+    #[simd_test(enable = "amx-tile")]
+    unsafe fn test_tile_stream_loaddrs() {
+        _init_amx();
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        config.colsb[0] = 64;
+        config.rows[0] = 16;
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        let mat = [1_i8; 1024];
+        _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
+        let mut out = [[0_i8; 64]; 16];
+        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+        _tile_release();
+        assert_eq!(out, [[1; 64]; 16]);
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    unsafe fn test_tile_movrow() {
+        _init_amx();
+        let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]);
+
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        config.colsb[0] = 64;
+        config.rows[0] = 16;
+        _tile_loadconfig(config.as_ptr());
+        _tile_loadd::<0>(array.as_ptr().cast(), 64);
+        for i in 0..16 {
+            let row = _tile_movrow::<0>(i);
+            assert_eq!(*row.as_u8x64().as_array(), [i as _; _]);
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    unsafe fn test_tile_cvtrowd2ps() {
+        _init_amx();
+        let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        config.colsb[0] = 64;
+        config.rows[0] = 16;
+        _tile_loadconfig(config.as_ptr());
+        _tile_loadd::<0>(array.as_ptr().cast(), 64);
+        for i in 0..16 {
+            let row = _tile_cvtrowd2ps::<0>(i);
+            assert_eq!(*row.as_f32x16().as_array(), [i as _; _]);
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    unsafe fn test_tile_cvtrowps2phh() {
+        _init_amx();
+        let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        config.colsb[0] = 64;
+        config.rows[0] = 16;
+        _tile_loadconfig(config.as_ptr());
+        _tile_loadd::<0>(array.as_ptr().cast(), 64);
+        for i in 0..16 {
+            let row = _tile_cvtrowps2phh::<0>(i);
+            assert_eq!(
+                *row.as_f16x32().as_array(),
+                array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ })
+            );
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    unsafe fn test_tile_cvtrowps2phl() {
+        _init_amx();
+        let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        config.colsb[0] = 64;
+        config.rows[0] = 16;
+        _tile_loadconfig(config.as_ptr());
+        _tile_loadd::<0>(array.as_ptr().cast(), 64);
+        for i in 0..16 {
+            let row = _tile_cvtrowps2phl::<0>(i);
+            assert_eq!(
+                *row.as_f16x32().as_array(),
+                array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 })
+            );
+        }
+    }
+
+    #[simd_test(enable = "amx-tf32")]
+    unsafe fn test_tile_mmultf32ps() {
+        _init_amx();
+        let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+        let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _];
+        let mut res = [[0.0; 16]; 16];
+
+        let mut config = __tilecfg::default();
+        config.palette = 1;
+        (0..=2).for_each(|i| {
+            config.colsb[i] = 64;
+            config.rows[i] = 16;
+        });
+        _tile_loadconfig(config.as_ptr());
+        _tile_zero::<0>();
+        _tile_loadd::<1>(a.as_ptr().cast(), 64);
+        _tile_loadd::<2>(b.as_ptr().cast(), 64);
+        _tile_mmultf32ps::<0, 1, 2>();
+        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+        _tile_release();
+
+        let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32));
+        assert_eq!(res, expected);
+    }
 }

From 71b1719e8c1e26facab469fda1824f0bd18229de Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jakub=20Ber=C3=A1nek?= <berykubik@gmail.com>
Date: Sun, 2 Nov 2025 14:44:51 +0100
Subject: [PATCH 011/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to 73e6c9ebd9123154a196300ef58e30ec8928e74e.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index 1ced6098ac..e313eada45 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-32e7a4b92b109c24e9822c862a7c74436b50e564
+73e6c9ebd9123154a196300ef58e30ec8928e74e

From 08d925c4070a4815db9270f3d08f7baf2ae54d3a Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 2 Nov 2025 20:09:54 +0100
Subject: [PATCH 012/326] improve `_mm256_permute2f128` tests

---
 crates/core_arch/src/x86/avx.rs | 33 ++++++++++++++++++++++++---------
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index c2c2febf18..7ea5f1f4ff 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -3928,28 +3928,43 @@ mod tests {
 
     #[simd_test(enable = "avx")]
     unsafe fn test_mm256_permute2f128_ps() {
-        let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
-        let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
-        let r = _mm256_permute2f128_ps::<0x13>(a, b);
-        let e = _mm256_setr_ps(5., 6., 7., 8., 1., 2., 3., 4.);
+        let a = _mm256_setr_ps(11., 12., 13., 14., 15., 16., 17., 18.);
+        let b = _mm256_setr_ps(21., 22., 23., 24., 25., 26., 27., 28.);
+        let r = _mm256_permute2f128_ps::<0b0001_0011>(a, b);
+        let e = _mm256_setr_ps(25., 26., 27., 28., 15., 16., 17., 18.);
         assert_eq_m256(r, e);
+
+        // Setting bits 3 or 7 (zero-indexed) zeroes the corresponding field.
+        let r = _mm256_permute2f128_ps::<0b1001_1011>(a, b);
+        let z = _mm256_setr_ps(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
+        assert_eq_m256(r, z);
     }
 
     #[simd_test(enable = "avx")]
     unsafe fn test_mm256_permute2f128_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
-        let r = _mm256_permute2f128_pd::<0x31>(a, b);
+        let r = _mm256_permute2f128_pd::<0b0011_0001>(a, b);
         let e = _mm256_setr_pd(3., 4., 7., 8.);
         assert_eq_m256d(r, e);
+
+        // Setting bits 3 or 7 (zero-indexed) zeroes the corresponding field.
+        let r = _mm256_permute2f128_pd::<0b1011_1001>(a, b);
+        let e = _mm256_setr_pd(0.0, 0.0, 0.0, 0.0);
+        assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
     unsafe fn test_mm256_permute2f128_si256() {
-        let a = _mm256_setr_epi32(1, 2, 3, 4, 1, 2, 3, 4);
-        let b = _mm256_setr_epi32(5, 6, 7, 8, 5, 6, 7, 8);
-        let r = _mm256_permute2f128_si256::<0x20>(a, b);
-        let e = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+        let a = _mm256_setr_epi32(11, 12, 13, 14, 15, 16, 17, 18);
+        let b = _mm256_setr_epi32(21, 22, 23, 24, 25, 26, 27, 28);
+        let r = _mm256_permute2f128_si256::<0b0010_0000>(a, b);
+        let e = _mm256_setr_epi32(11, 12, 13, 14, 21, 22, 23, 24);
+        assert_eq_m256i(r, e);
+
+        // Setting bits 3 or 7 (zero-indexed) zeroes the corresponding field.
+        let r = _mm256_permute2f128_si256::<0b1010_1000>(a, b);
+        let e = _mm256_setr_epi32(0, 0, 0, 0, 0, 0, 0, 0);
         assert_eq_m256i(r, e);
     }
 

From 05672d82635b16f182620c07ec0fbc02262cf903 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 11 Oct 2025 01:34:25 +0530
Subject: [PATCH 013/326] Use generic SIMD masked load/stores for avx512 masked
 load/stores

---
 crates/core_arch/src/macros.rs       |  14 ++
 crates/core_arch/src/x86/avx512bw.rs |  63 +++----
 crates/core_arch/src/x86/avx512f.rs  | 244 +++++++++++----------------
 3 files changed, 134 insertions(+), 187 deletions(-)

diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index e00b433536..1030d7e974 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -163,3 +163,17 @@ macro_rules! simd_extract {
     ($x:expr, $idx:expr $(,)?) => {{ $crate::intrinsics::simd::simd_extract($x, const { $idx }) }};
     ($x:expr, $idx:expr, $ty:ty $(,)?) => {{ $crate::intrinsics::simd::simd_extract::<_, $ty>($x, const { $idx }) }};
 }
+
+#[allow(unused)]
+macro_rules! simd_masked_load {
+    ($align:expr, $mask:expr, $ptr:expr, $default:expr) => {
+        $crate::intrinsics::simd::simd_masked_load::<_, _, _, { $align }>($mask, $ptr, $default)
+    };
+}
+
+#[allow(unused)]
+macro_rules! simd_masked_store {
+    ($align:expr, $mask:expr, $ptr:expr, $default:expr) => {
+        $crate::intrinsics::simd::simd_masked_store::<_, _, _, { $align }>($mask, $ptr, $default)
+    };
+}
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index fadc0e2cc0..72842f4546 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -5609,7 +5609,8 @@ pub unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) {
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_loadu_epi16(src: __m512i, k: __mmask32, mem_addr: *const i16) -> __m512i {
-    transmute(loaddqu16_512(mem_addr, src.as_i16x32(), k))
+    let mask = simd_select_bitmask(k, i16x32::splat(!0), i16x32::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i16x32()).as_m512i()
 }
 
 /// Load packed 16-bit integers from memory into dst using zeromask k
@@ -5635,7 +5636,8 @@ pub unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_loadu_epi8(src: __m512i, k: __mmask64, mem_addr: *const i8) -> __m512i {
-    transmute(loaddqu8_512(mem_addr, src.as_i8x64(), k))
+    let mask = simd_select_bitmask(k, i8x64::splat(!0), i8x64::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i8x64()).as_m512i()
 }
 
 /// Load packed 8-bit integers from memory into dst using zeromask k
@@ -5661,7 +5663,8 @@ pub unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m5
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_loadu_epi16(src: __m256i, k: __mmask16, mem_addr: *const i16) -> __m256i {
-    transmute(loaddqu16_256(mem_addr, src.as_i16x16(), k))
+    let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i16x16()).as_m256i()
 }
 
 /// Load packed 16-bit integers from memory into dst using zeromask k
@@ -5687,7 +5690,8 @@ pub unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_loadu_epi8(src: __m256i, k: __mmask32, mem_addr: *const i8) -> __m256i {
-    transmute(loaddqu8_256(mem_addr, src.as_i8x32(), k))
+    let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i8x32()).as_m256i()
 }
 
 /// Load packed 8-bit integers from memory into dst using zeromask k
@@ -5713,7 +5717,8 @@ pub unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m2
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_loadu_epi16(src: __m128i, k: __mmask8, mem_addr: *const i16) -> __m128i {
-    transmute(loaddqu16_128(mem_addr, src.as_i16x8(), k))
+    let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i16x8()).as_m128i()
 }
 
 /// Load packed 16-bit integers from memory into dst using zeromask k
@@ -5739,7 +5744,8 @@ pub unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_loadu_epi8(src: __m128i, k: __mmask16, mem_addr: *const i8) -> __m128i {
-    transmute(loaddqu8_128(mem_addr, src.as_i8x16(), k))
+    let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i8x16()).as_m128i()
 }
 
 /// Load packed 8-bit integers from memory into dst using zeromask k
@@ -5764,7 +5770,8 @@ pub unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: __m512i) {
-    storedqu16_512(mem_addr, a.as_i16x32(), mask)
+    let mask = simd_select_bitmask(mask, i16x32::splat(!0), i16x32::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i16x32());
 }
 
 /// Store packed 8-bit integers from a into memory using writemask k.
@@ -5776,7 +5783,8 @@ pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: _
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m512i) {
-    storedqu8_512(mem_addr, a.as_i8x64(), mask)
+    let mask = simd_select_bitmask(mask, i8x64::splat(!0), i8x64::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i8x64());
 }
 
 /// Store packed 16-bit integers from a into memory using writemask k.
@@ -5788,7 +5796,8 @@ pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: __m256i) {
-    storedqu16_256(mem_addr, a.as_i16x16(), mask)
+    let mask = simd_select_bitmask(mask, i16x16::splat(!0), i16x16::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i16x16());
 }
 
 /// Store packed 8-bit integers from a into memory using writemask k.
@@ -5800,7 +5809,8 @@ pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: _
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m256i) {
-    storedqu8_256(mem_addr, a.as_i8x32(), mask)
+    let mask = simd_select_bitmask(mask, i8x32::splat(!0), i8x32::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i8x32());
 }
 
 /// Store packed 16-bit integers from a into memory using writemask k.
@@ -5812,7 +5822,8 @@ pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m128i) {
-    storedqu16_128(mem_addr, a.as_i16x8(), mask)
+    let mask = simd_select_bitmask(mask, i16x8::splat(!0), i16x8::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i16x8());
 }
 
 /// Store packed 8-bit integers from a into memory using writemask k.
@@ -5824,7 +5835,8 @@ pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m12
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128i) {
-    storedqu8_128(mem_addr, a.as_i8x16(), mask)
+    let mask = simd_select_bitmask(mask, i8x16::splat(!0), i8x16::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i8x16());
 }
 
 /// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst.
@@ -11733,33 +11745,6 @@ unsafe extern "C" {
     fn vpmovuswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
     #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.128"]
     fn vpmovuswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
-
-    #[link_name = "llvm.x86.avx512.mask.loadu.b.128"]
-    fn loaddqu8_128(mem_addr: *const i8, a: i8x16, mask: u16) -> i8x16;
-    #[link_name = "llvm.x86.avx512.mask.loadu.w.128"]
-    fn loaddqu16_128(mem_addr: *const i16, a: i16x8, mask: u8) -> i16x8;
-    #[link_name = "llvm.x86.avx512.mask.loadu.b.256"]
-    fn loaddqu8_256(mem_addr: *const i8, a: i8x32, mask: u32) -> i8x32;
-    #[link_name = "llvm.x86.avx512.mask.loadu.w.256"]
-    fn loaddqu16_256(mem_addr: *const i16, a: i16x16, mask: u16) -> i16x16;
-    #[link_name = "llvm.x86.avx512.mask.loadu.b.512"]
-    fn loaddqu8_512(mem_addr: *const i8, a: i8x64, mask: u64) -> i8x64;
-    #[link_name = "llvm.x86.avx512.mask.loadu.w.512"]
-    fn loaddqu16_512(mem_addr: *const i16, a: i16x32, mask: u32) -> i16x32;
-
-    #[link_name = "llvm.x86.avx512.mask.storeu.b.128"]
-    fn storedqu8_128(mem_addr: *mut i8, a: i8x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.storeu.w.128"]
-    fn storedqu16_128(mem_addr: *mut i16, a: i16x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.b.256"]
-    fn storedqu8_256(mem_addr: *mut i8, a: i8x32, mask: u32);
-    #[link_name = "llvm.x86.avx512.mask.storeu.w.256"]
-    fn storedqu16_256(mem_addr: *mut i16, a: i16x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.storeu.b.512"]
-    fn storedqu8_512(mem_addr: *mut i8, a: i8x64, mask: u64);
-    #[link_name = "llvm.x86.avx512.mask.storeu.w.512"]
-    fn storedqu16_512(mem_addr: *mut i16, a: i16x32, mask: u32);
-
 }
 
 #[cfg(test)]
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index b60df7dbc9..d39b741f00 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -34715,7 +34715,8 @@ pub unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) {
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_loadu_epi32(src: __m512i, k: __mmask16, mem_addr: *const i32) -> __m512i {
-    transmute(loaddqu32_512(mem_addr, src.as_i32x16(), k))
+    let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i32x16()).as_m512i()
 }
 
 /// Load packed 32-bit integers from memory into dst using zeromask k
@@ -34741,7 +34742,8 @@ pub unsafe fn _mm512_maskz_loadu_epi32(k: __mmask16, mem_addr: *const i32) -> __
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_loadu_epi64(src: __m512i, k: __mmask8, mem_addr: *const i64) -> __m512i {
-    transmute(loaddqu64_512(mem_addr, src.as_i64x8(), k))
+    let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i64x8()).as_m512i()
 }
 
 /// Load packed 64-bit integers from memory into dst using zeromask k
@@ -34767,7 +34769,8 @@ pub unsafe fn _mm512_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_loadu_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 {
-    transmute(loadups_512(mem_addr, src.as_f32x16(), k))
+    let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f32x16()).as_m512()
 }
 
 /// Load packed single-precision (32-bit) floating-point elements from memory into dst using zeromask k
@@ -34793,7 +34796,8 @@ pub unsafe fn _mm512_maskz_loadu_ps(k: __mmask16, mem_addr: *const f32) -> __m51
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_loadu_pd(src: __m512d, k: __mmask8, mem_addr: *const f64) -> __m512d {
-    transmute(loadupd_512(mem_addr, src.as_f64x8(), k))
+    let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f64x8()).as_m512d()
 }
 
 /// Load packed double-precision (64-bit) floating-point elements from memory into dst using zeromask k
@@ -34819,7 +34823,8 @@ pub unsafe fn _mm512_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_loadu_epi32(src: __m256i, k: __mmask8, mem_addr: *const i32) -> __m256i {
-    transmute(loaddqu32_256(mem_addr, src.as_i32x8(), k))
+    let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i32x8()).as_m256i()
 }
 
 /// Load packed 32-bit integers from memory into dst using zeromask k
@@ -34845,7 +34850,8 @@ pub unsafe fn _mm256_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_loadu_epi64(src: __m256i, k: __mmask8, mem_addr: *const i64) -> __m256i {
-    transmute(loaddqu64_256(mem_addr, src.as_i64x4(), k))
+    let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i64x4()).as_m256i()
 }
 
 /// Load packed 64-bit integers from memory into dst using zeromask k
@@ -34871,7 +34877,8 @@ pub unsafe fn _mm256_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_loadu_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 {
-    transmute(loadups_256(mem_addr, src.as_f32x8(), k))
+    let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f32x8()).as_m256()
 }
 
 /// Load packed single-precision (32-bit) floating-point elements from memory into dst using zeromask k
@@ -34897,7 +34904,8 @@ pub unsafe fn _mm256_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_loadu_pd(src: __m256d, k: __mmask8, mem_addr: *const f64) -> __m256d {
-    transmute(loadupd_256(mem_addr, src.as_f64x4(), k))
+    let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f64x4()).as_m256d()
 }
 
 /// Load packed double-precision (64-bit) floating-point elements from memory into dst using zeromask k
@@ -34923,7 +34931,8 @@ pub unsafe fn _mm256_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_loadu_epi32(src: __m128i, k: __mmask8, mem_addr: *const i32) -> __m128i {
-    transmute(loaddqu32_128(mem_addr, src.as_i32x4(), k))
+    let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i32x4()).as_m128i()
 }
 
 /// Load packed 32-bit integers from memory into dst using zeromask k
@@ -34949,7 +34958,8 @@ pub unsafe fn _mm_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_loadu_epi64(src: __m128i, k: __mmask8, mem_addr: *const i64) -> __m128i {
-    transmute(loaddqu64_128(mem_addr, src.as_i64x2(), k))
+    let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i64x2()).as_m128i()
 }
 
 /// Load packed 64-bit integers from memory into dst using zeromask k
@@ -34975,7 +34985,8 @@ pub unsafe fn _mm_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_loadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
-    transmute(loadups_128(mem_addr, src.as_f32x4(), k))
+    let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f32x4()).as_m128()
 }
 
 /// Load packed single-precision (32-bit) floating-point elements from memory into dst using zeromask k
@@ -35001,7 +35012,8 @@ pub unsafe fn _mm_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_loadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
-    transmute(loadupd_128(mem_addr, src.as_f64x2(), k))
+    let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f64x2()).as_m128d()
 }
 
 /// Load packed double-precision (64-bit) floating-point elements from memory into dst using zeromask k
@@ -35027,7 +35039,8 @@ pub unsafe fn _mm_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_load_epi32(src: __m512i, k: __mmask16, mem_addr: *const i32) -> __m512i {
-    transmute(loaddqa32_512(mem_addr, src.as_i32x16(), k))
+    let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i32x16()).as_m512i()
 }
 
 /// Load packed 32-bit integers from memory into dst using zeromask k
@@ -35053,7 +35066,8 @@ pub unsafe fn _mm512_maskz_load_epi32(k: __mmask16, mem_addr: *const i32) -> __m
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_load_epi64(src: __m512i, k: __mmask8, mem_addr: *const i64) -> __m512i {
-    transmute(loaddqa64_512(mem_addr, src.as_i64x8(), k))
+    let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i64x8()).as_m512i()
 }
 
 /// Load packed 64-bit integers from memory into dst using zeromask k
@@ -35079,7 +35093,8 @@ pub unsafe fn _mm512_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m5
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_load_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 {
-    transmute(loadaps_512(mem_addr, src.as_f32x16(), k))
+    let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f32x16()).as_m512()
 }
 
 /// Load packed single-precision (32-bit) floating-point elements from memory into dst using zeromask k
@@ -35105,7 +35120,8 @@ pub unsafe fn _mm512_maskz_load_ps(k: __mmask16, mem_addr: *const f32) -> __m512
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_load_pd(src: __m512d, k: __mmask8, mem_addr: *const f64) -> __m512d {
-    transmute(loadapd_512(mem_addr, src.as_f64x8(), k))
+    let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f64x8()).as_m512d()
 }
 
 /// Load packed double-precision (64-bit) floating-point elements from memory into dst using zeromask k
@@ -35131,7 +35147,8 @@ pub unsafe fn _mm512_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m512d
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_load_epi32(src: __m256i, k: __mmask8, mem_addr: *const i32) -> __m256i {
-    transmute(loaddqa32_256(mem_addr, src.as_i32x8(), k))
+    let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i32x8()).as_m256i()
 }
 
 /// Load packed 32-bit integers from memory into dst using zeromask k
@@ -35157,7 +35174,8 @@ pub unsafe fn _mm256_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m2
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_load_epi64(src: __m256i, k: __mmask8, mem_addr: *const i64) -> __m256i {
-    transmute(loaddqa64_256(mem_addr, src.as_i64x4(), k))
+    let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i64x4()).as_m256i()
 }
 
 /// Load packed 64-bit integers from memory into dst using zeromask k
@@ -35183,7 +35201,8 @@ pub unsafe fn _mm256_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m2
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_load_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 {
-    transmute(loadaps_256(mem_addr, src.as_f32x8(), k))
+    let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f32x8()).as_m256()
 }
 
 /// Load packed single-precision (32-bit) floating-point elements from memory into dst using zeromask k
@@ -35209,7 +35228,8 @@ pub unsafe fn _mm256_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m256
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_load_pd(src: __m256d, k: __mmask8, mem_addr: *const f64) -> __m256d {
-    transmute(loadapd_256(mem_addr, src.as_f64x4(), k))
+    let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f64x4()).as_m256d()
 }
 
 /// Load packed double-precision (64-bit) floating-point elements from memory into dst using zeromask k
@@ -35235,7 +35255,8 @@ pub unsafe fn _mm256_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m256d
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_load_epi32(src: __m128i, k: __mmask8, mem_addr: *const i32) -> __m128i {
-    transmute(loaddqa32_128(mem_addr, src.as_i32x4(), k))
+    let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i32x4()).as_m128i()
 }
 
 /// Load packed 32-bit integers from memory into dst using zeromask k
@@ -35261,7 +35282,8 @@ pub unsafe fn _mm_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_load_epi64(src: __m128i, k: __mmask8, mem_addr: *const i64) -> __m128i {
-    transmute(loaddqa64_128(mem_addr, src.as_i64x2(), k))
+    let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i64x2()).as_m128i()
 }
 
 /// Load packed 64-bit integers from memory into dst using zeromask k
@@ -35287,7 +35309,8 @@ pub unsafe fn _mm_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_load_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
-    transmute(loadaps_128(mem_addr, src.as_f32x4(), k))
+    let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f32x4()).as_m128()
 }
 
 /// Load packed single-precision (32-bit) floating-point elements from memory into dst using zeromask k
@@ -35313,7 +35336,8 @@ pub unsafe fn _mm_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_load_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
-    transmute(loadapd_128(mem_addr, src.as_f64x2(), k))
+    let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f64x2()).as_m128d()
 }
 
 /// Load packed double-precision (64-bit) floating-point elements from memory into dst using zeromask k
@@ -35426,7 +35450,8 @@ pub unsafe fn _mm_maskz_load_sd(k: __mmask8, mem_addr: *const f64) -> __m128d {
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) {
-    storedqu32_512(mem_addr, a.as_i32x16(), mask)
+    let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x16());
 }
 
 /// Store packed 64-bit integers from a into memory using writemask k.
@@ -35438,7 +35463,8 @@ pub unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: _
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) {
-    storedqu64_512(mem_addr, a.as_i64x8(), mask)
+    let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x8());
 }
 
 /// Store packed single-precision (32-bit) floating-point elements from a into memory using writemask k.
@@ -35450,7 +35476,8 @@ pub unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) {
-    storeups_512(mem_addr, a.as_f32x16(), mask)
+    let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f32x16());
 }
 
 /// Store packed double-precision (64-bit) floating-point elements from a into memory using writemask k.
@@ -35462,7 +35489,8 @@ pub unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m5
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) {
-    storeupd_512(mem_addr, a.as_f64x8(), mask)
+    let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f64x8());
 }
 
 /// Store packed 32-bit integers from a into memory using writemask k.
@@ -35474,7 +35502,8 @@ pub unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m51
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) {
-    storedqu32_256(mem_addr, a.as_i32x8(), mask)
+    let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x8());
 }
 
 /// Store packed 64-bit integers from a into memory using writemask k.
@@ -35486,7 +35515,8 @@ pub unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) {
-    storedqu64_256(mem_addr, a.as_i64x4(), mask)
+    let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x4());
 }
 
 /// Store packed single-precision (32-bit) floating-point elements from a into memory using writemask k.
@@ -35498,7 +35528,8 @@ pub unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) {
-    storeups_256(mem_addr, a.as_f32x8(), mask)
+    let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f32x8());
 }
 
 /// Store packed double-precision (64-bit) floating-point elements from a into memory using writemask k.
@@ -35510,7 +35541,8 @@ pub unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m25
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) {
-    storeupd_256(mem_addr, a.as_f64x4(), mask)
+    let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f64x4());
 }
 
 /// Store packed 32-bit integers from a into memory using writemask k.
@@ -35522,7 +35554,8 @@ pub unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m25
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) {
-    storedqu32_128(mem_addr, a.as_i32x4(), mask)
+    let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x4());
 }
 
 /// Store packed 64-bit integers from a into memory using writemask k.
@@ -35534,7 +35567,8 @@ pub unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m12
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) {
-    storedqu64_128(mem_addr, a.as_i64x2(), mask)
+    let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x2());
 }
 
 /// Store packed single-precision (32-bit) floating-point elements from a into memory using writemask k.
@@ -35546,7 +35580,8 @@ pub unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m12
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
-    storeups_128(mem_addr, a.as_f32x4(), mask)
+    let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f32x4());
 }
 
 /// Store packed double-precision (64-bit) floating-point elements from a into memory using writemask k.
@@ -35558,7 +35593,8 @@ pub unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128)
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) {
-    storeupd_128(mem_addr, a.as_f64x2(), mask)
+    let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f64x2());
 }
 
 /// Store packed 32-bit integers from a into memory using writemask k.
@@ -35570,7 +35606,8 @@ pub unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d)
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) {
-    storedqa32_512(mem_addr, a.as_i32x16(), mask)
+    let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i32x16());
 }
 
 /// Store packed 64-bit integers from a into memory using writemask k.
@@ -35582,7 +35619,8 @@ pub unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) {
-    storedqa64_512(mem_addr, a.as_i64x8(), mask)
+    let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i64x8());
 }
 
 /// Store packed single-precision (32-bit) floating-point elements from a into memory using writemask k.
@@ -35594,7 +35632,8 @@ pub unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) {
-    storeaps_512(mem_addr, a.as_f32x16(), mask)
+    let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f32x16());
 }
 
 /// Store packed double-precision (64-bit) floating-point elements from a into memory using writemask k.
@@ -35606,7 +35645,8 @@ pub unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m51
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) {
-    storeapd_512(mem_addr, a.as_f64x8(), mask)
+    let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f64x8());
 }
 
 /// Store packed 32-bit integers from a into memory using writemask k.
@@ -35618,7 +35658,8 @@ pub unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) {
-    storedqa32_256(mem_addr, a.as_i32x8(), mask)
+    let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i32x8());
 }
 
 /// Store packed 64-bit integers from a into memory using writemask k.
@@ -35630,7 +35671,8 @@ pub unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) {
-    storedqa64_256(mem_addr, a.as_i64x4(), mask)
+    let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i64x4());
 }
 
 /// Store packed single-precision (32-bit) floating-point elements from a into memory using writemask k.
@@ -35642,7 +35684,8 @@ pub unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) {
-    storeaps_256(mem_addr, a.as_f32x8(), mask)
+    let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f32x8());
 }
 
 /// Store packed double-precision (64-bit) floating-point elements from a into memory using writemask k.
@@ -35654,7 +35697,8 @@ pub unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) {
-    storeapd_256(mem_addr, a.as_f64x4(), mask)
+    let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f64x4());
 }
 
 /// Store packed 32-bit integers from a into memory using writemask k.
@@ -35666,7 +35710,8 @@ pub unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) {
-    storedqa32_128(mem_addr, a.as_i32x4(), mask)
+    let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i32x4());
 }
 
 /// Store packed 64-bit integers from a into memory using writemask k.
@@ -35678,7 +35723,8 @@ pub unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) {
-    storedqa64_128(mem_addr, a.as_i64x2(), mask)
+    let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i64x2());
 }
 
 /// Store packed single-precision (32-bit) floating-point elements from a into memory using writemask k.
@@ -35690,7 +35736,8 @@ pub unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
-    storeaps_128(mem_addr, a.as_f32x4(), mask)
+    let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f32x4());
 }
 
 /// Store packed double-precision (64-bit) floating-point elements from a into memory using writemask k.
@@ -35702,7 +35749,8 @@ pub unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub unsafe fn _mm_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) {
-    storeapd_128(mem_addr, a.as_f64x2(), mask)
+    let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
+    simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f64x2());
 }
 
 /// Store a single-precision (32-bit) floating-point element from a into memory using writemask k. mem_addr
@@ -43109,106 +43157,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.vcomi.sd"]
     fn vcomisd(a: f64x2, b: f64x2, imm8: i32, sae: i32) -> i32;
 
-    #[link_name = "llvm.x86.avx512.mask.loadu.d.128"]
-    fn loaddqu32_128(mem_addr: *const i32, a: i32x4, mask: u8) -> i32x4;
-    #[link_name = "llvm.x86.avx512.mask.loadu.q.128"]
-    fn loaddqu64_128(mem_addr: *const i64, a: i64x2, mask: u8) -> i64x2;
-    #[link_name = "llvm.x86.avx512.mask.loadu.ps.128"]
-    fn loadups_128(mem_addr: *const f32, a: f32x4, mask: u8) -> f32x4;
-    #[link_name = "llvm.x86.avx512.mask.loadu.pd.128"]
-    fn loadupd_128(mem_addr: *const f64, a: f64x2, mask: u8) -> f64x2;
-    #[link_name = "llvm.x86.avx512.mask.loadu.d.256"]
-    fn loaddqu32_256(mem_addr: *const i32, a: i32x8, mask: u8) -> i32x8;
-    #[link_name = "llvm.x86.avx512.mask.loadu.q.256"]
-    fn loaddqu64_256(mem_addr: *const i64, a: i64x4, mask: u8) -> i64x4;
-    #[link_name = "llvm.x86.avx512.mask.loadu.ps.256"]
-    fn loadups_256(mem_addr: *const f32, a: f32x8, mask: u8) -> f32x8;
-    #[link_name = "llvm.x86.avx512.mask.loadu.pd.256"]
-    fn loadupd_256(mem_addr: *const f64, a: f64x4, mask: u8) -> f64x4;
-    #[link_name = "llvm.x86.avx512.mask.loadu.d.512"]
-    fn loaddqu32_512(mem_addr: *const i32, a: i32x16, mask: u16) -> i32x16;
-    #[link_name = "llvm.x86.avx512.mask.loadu.q.512"]
-    fn loaddqu64_512(mem_addr: *const i64, a: i64x8, mask: u8) -> i64x8;
-    #[link_name = "llvm.x86.avx512.mask.loadu.ps.512"]
-    fn loadups_512(mem_addr: *const f32, a: f32x16, mask: u16) -> f32x16;
-    #[link_name = "llvm.x86.avx512.mask.loadu.pd.512"]
-    fn loadupd_512(mem_addr: *const f64, a: f64x8, mask: u8) -> f64x8;
-
-    #[link_name = "llvm.x86.avx512.mask.load.d.128"]
-    fn loaddqa32_128(mem_addr: *const i32, a: i32x4, mask: u8) -> i32x4;
-    #[link_name = "llvm.x86.avx512.mask.load.q.128"]
-    fn loaddqa64_128(mem_addr: *const i64, a: i64x2, mask: u8) -> i64x2;
-    #[link_name = "llvm.x86.avx512.mask.load.ps.128"]
-    fn loadaps_128(mem_addr: *const f32, a: f32x4, mask: u8) -> f32x4;
-    #[link_name = "llvm.x86.avx512.mask.load.pd.128"]
-    fn loadapd_128(mem_addr: *const f64, a: f64x2, mask: u8) -> f64x2;
-    #[link_name = "llvm.x86.avx512.mask.load.d.256"]
-    fn loaddqa32_256(mem_addr: *const i32, a: i32x8, mask: u8) -> i32x8;
-    #[link_name = "llvm.x86.avx512.mask.load.q.256"]
-    fn loaddqa64_256(mem_addr: *const i64, a: i64x4, mask: u8) -> i64x4;
-    #[link_name = "llvm.x86.avx512.mask.load.ps.256"]
-    fn loadaps_256(mem_addr: *const f32, a: f32x8, mask: u8) -> f32x8;
-    #[link_name = "llvm.x86.avx512.mask.load.pd.256"]
-    fn loadapd_256(mem_addr: *const f64, a: f64x4, mask: u8) -> f64x4;
-    #[link_name = "llvm.x86.avx512.mask.load.d.512"]
-    fn loaddqa32_512(mem_addr: *const i32, a: i32x16, mask: u16) -> i32x16;
-    #[link_name = "llvm.x86.avx512.mask.load.q.512"]
-    fn loaddqa64_512(mem_addr: *const i64, a: i64x8, mask: u8) -> i64x8;
-    #[link_name = "llvm.x86.avx512.mask.load.ps.512"]
-    fn loadaps_512(mem_addr: *const f32, a: f32x16, mask: u16) -> f32x16;
-    #[link_name = "llvm.x86.avx512.mask.load.pd.512"]
-    fn loadapd_512(mem_addr: *const f64, a: f64x8, mask: u8) -> f64x8;
-
-    #[link_name = "llvm.x86.avx512.mask.storeu.d.128"]
-    fn storedqu32_128(mem_addr: *mut i32, a: i32x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.q.128"]
-    fn storedqu64_128(mem_addr: *mut i64, a: i64x2, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.ps.128"]
-    fn storeups_128(mem_addr: *mut f32, a: f32x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.pd.128"]
-    fn storeupd_128(mem_addr: *mut f64, a: f64x2, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.d.256"]
-    fn storedqu32_256(mem_addr: *mut i32, a: i32x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.q.256"]
-    fn storedqu64_256(mem_addr: *mut i64, a: i64x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.ps.256"]
-    fn storeups_256(mem_addr: *mut f32, a: f32x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.pd.256"]
-    fn storeupd_256(mem_addr: *mut f64, a: f64x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.d.512"]
-    fn storedqu32_512(mem_addr: *mut i32, a: i32x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.storeu.q.512"]
-    fn storedqu64_512(mem_addr: *mut i64, a: i64x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.storeu.ps.512"]
-    fn storeups_512(mem_addr: *mut f32, a: f32x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.storeu.pd.512"]
-    fn storeupd_512(mem_addr: *mut f64, a: f64x8, mask: u8);
-
-    #[link_name = "llvm.x86.avx512.mask.store.d.128"]
-    fn storedqa32_128(mem_addr: *mut i32, a: i32x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.q.128"]
-    fn storedqa64_128(mem_addr: *mut i64, a: i64x2, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.ps.128"]
-    fn storeaps_128(mem_addr: *mut f32, a: f32x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.pd.128"]
-    fn storeapd_128(mem_addr: *mut f64, a: f64x2, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.d.256"]
-    fn storedqa32_256(mem_addr: *mut i32, a: i32x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.q.256"]
-    fn storedqa64_256(mem_addr: *mut i64, a: i64x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.ps.256"]
-    fn storeaps_256(mem_addr: *mut f32, a: f32x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.pd.256"]
-    fn storeapd_256(mem_addr: *mut f64, a: f64x4, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.d.512"]
-    fn storedqa32_512(mem_addr: *mut i32, a: i32x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.store.q.512"]
-    fn storedqa64_512(mem_addr: *mut i64, a: i64x8, mask: u8);
-    #[link_name = "llvm.x86.avx512.mask.store.ps.512"]
-    fn storeaps_512(mem_addr: *mut f32, a: f32x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.store.pd.512"]
-    fn storeapd_512(mem_addr: *mut f64, a: f64x8, mask: u8);
-
     #[link_name = "llvm.x86.avx512.mask.expand.load.d.128"]
     fn expandloadd_128(mem_addr: *const i32, a: i32x4, mask: u8) -> i32x4;
     #[link_name = "llvm.x86.avx512.mask.expand.load.q.128"]

From 6d36d3ded199d888a81161129c938815b5f26b59 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 20 Aug 2025 12:08:27 +0200
Subject: [PATCH 014/326] extract s390x `vector` and friends to their own rust
 feature

---
 crates/core_arch/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 26a9cb5899..7aa71a4983 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -22,7 +22,7 @@
     arm_target_feature,
     mips_target_feature,
     powerpc_target_feature,
-    s390x_target_feature,
+    s390x_target_feature_vector,
     loongarch_target_feature,
     wasm_target_feature,
     abi_unadjusted,

From 5e5ea8263d4e349a7ee83a19c1fdcf32accaaa06 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 20 Aug 2025 12:41:19 +0200
Subject: [PATCH 015/326] stabilize `stdarch_s390x_feature_detection`

---
 crates/core_arch/src/lib.rs | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 7aa71a4983..ed9138f343 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -64,11 +64,7 @@
 )]
 #![cfg_attr(
     test,
-    feature(
-        stdarch_arm_feature_detection,
-        stdarch_powerpc_feature_detection,
-        stdarch_s390x_feature_detection
-    )
+    feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection,)
 )]
 
 #[cfg(test)]

From 97588208ff51eecbcca56fa663bb54c6fd39dc0f Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 20 Aug 2025 13:04:58 +0200
Subject: [PATCH 016/326] stabilize `s390x_target_feature_vector`

---
 crates/core_arch/src/lib.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index ed9138f343..06cbd32d67 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -22,7 +22,6 @@
     arm_target_feature,
     mips_target_feature,
     powerpc_target_feature,
-    s390x_target_feature_vector,
     loongarch_target_feature,
     wasm_target_feature,
     abi_unadjusted,

From b2d746fe2653beccc3d014d763fafe1703f57143 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 6 Nov 2025 06:26:16 +0530
Subject: [PATCH 017/326] Use generic SIMD intrinsics for AVX `maskload` and
 `maskstore` intrinsics

---
 crates/core_arch/src/x86/avx.rs  | 40 +++++++++++++-------------------
 crates/core_arch/src/x86/avx2.rs | 40 +++++++++++++-------------------
 2 files changed, 32 insertions(+), 48 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index 7ea5f1f4ff..c50c83fcaa 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -1675,7 +1675,8 @@ pub unsafe fn _mm256_storeu_si256(mem_addr: *mut __m256i, a: __m256i) {
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskload_pd(mem_addr: *const f64, mask: __m256i) -> __m256d {
-    maskloadpd256(mem_addr as *const i8, mask.as_i64x4())
+    let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm256_setzero_pd())
 }
 
 /// Stores packed double-precision (64-bit) floating-point elements from `a`
@@ -1687,7 +1688,8 @@ pub unsafe fn _mm256_maskload_pd(mem_addr: *const f64, mask: __m256i) -> __m256d
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskstore_pd(mem_addr: *mut f64, mask: __m256i, a: __m256d) {
-    maskstorepd256(mem_addr as *mut i8, mask.as_i64x4(), a);
+    let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
 
 /// Loads packed double-precision (64-bit) floating-point elements from memory
@@ -1700,7 +1702,8 @@ pub unsafe fn _mm256_maskstore_pd(mem_addr: *mut f64, mask: __m256i, a: __m256d)
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskload_pd(mem_addr: *const f64, mask: __m128i) -> __m128d {
-    maskloadpd(mem_addr as *const i8, mask.as_i64x2())
+    let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm_setzero_pd())
 }
 
 /// Stores packed double-precision (64-bit) floating-point elements from `a`
@@ -1712,7 +1715,8 @@ pub unsafe fn _mm_maskload_pd(mem_addr: *const f64, mask: __m128i) -> __m128d {
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskstore_pd(mem_addr: *mut f64, mask: __m128i, a: __m128d) {
-    maskstorepd(mem_addr as *mut i8, mask.as_i64x2(), a);
+    let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
 
 /// Loads packed single-precision (32-bit) floating-point elements from memory
@@ -1725,7 +1729,8 @@ pub unsafe fn _mm_maskstore_pd(mem_addr: *mut f64, mask: __m128i, a: __m128d) {
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskload_ps(mem_addr: *const f32, mask: __m256i) -> __m256 {
-    maskloadps256(mem_addr as *const i8, mask.as_i32x8())
+    let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm256_setzero_ps())
 }
 
 /// Stores packed single-precision (32-bit) floating-point elements from `a`
@@ -1737,7 +1742,8 @@ pub unsafe fn _mm256_maskload_ps(mem_addr: *const f32, mask: __m256i) -> __m256
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskstore_ps(mem_addr: *mut f32, mask: __m256i, a: __m256) {
-    maskstoreps256(mem_addr as *mut i8, mask.as_i32x8(), a);
+    let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
 
 /// Loads packed single-precision (32-bit) floating-point elements from memory
@@ -1750,7 +1756,8 @@ pub unsafe fn _mm256_maskstore_ps(mem_addr: *mut f32, mask: __m256i, a: __m256)
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskload_ps(mem_addr: *const f32, mask: __m128i) -> __m128 {
-    maskloadps(mem_addr as *const i8, mask.as_i32x4())
+    let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm_setzero_ps())
 }
 
 /// Stores packed single-precision (32-bit) floating-point elements from `a`
@@ -1762,7 +1769,8 @@ pub unsafe fn _mm_maskload_ps(mem_addr: *const f32, mask: __m128i) -> __m128 {
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskstore_ps(mem_addr: *mut f32, mask: __m128i, a: __m128) {
-    maskstoreps(mem_addr as *mut i8, mask.as_i32x4(), a);
+    let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
 
 /// Duplicate odd-indexed single-precision (32-bit) floating-point elements
@@ -3147,22 +3155,6 @@ unsafe extern "C" {
     fn vpermilpd256(a: __m256d, b: i64x4) -> __m256d;
     #[link_name = "llvm.x86.avx.vpermilvar.pd"]
     fn vpermilpd(a: __m128d, b: i64x2) -> __m128d;
-    #[link_name = "llvm.x86.avx.maskload.pd.256"]
-    fn maskloadpd256(mem_addr: *const i8, mask: i64x4) -> __m256d;
-    #[link_name = "llvm.x86.avx.maskstore.pd.256"]
-    fn maskstorepd256(mem_addr: *mut i8, mask: i64x4, a: __m256d);
-    #[link_name = "llvm.x86.avx.maskload.pd"]
-    fn maskloadpd(mem_addr: *const i8, mask: i64x2) -> __m128d;
-    #[link_name = "llvm.x86.avx.maskstore.pd"]
-    fn maskstorepd(mem_addr: *mut i8, mask: i64x2, a: __m128d);
-    #[link_name = "llvm.x86.avx.maskload.ps.256"]
-    fn maskloadps256(mem_addr: *const i8, mask: i32x8) -> __m256;
-    #[link_name = "llvm.x86.avx.maskstore.ps.256"]
-    fn maskstoreps256(mem_addr: *mut i8, mask: i32x8, a: __m256);
-    #[link_name = "llvm.x86.avx.maskload.ps"]
-    fn maskloadps(mem_addr: *const i8, mask: i32x4) -> __m128;
-    #[link_name = "llvm.x86.avx.maskstore.ps"]
-    fn maskstoreps(mem_addr: *mut i8, mask: i32x4, a: __m128);
     #[link_name = "llvm.x86.avx.ldu.dq.256"]
     fn vlddqu(mem_addr: *const i8) -> i8x32;
     #[link_name = "llvm.x86.avx.rcp.ps.256"]
diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 91c10638e0..de27ee7b45 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -1786,7 +1786,8 @@ pub fn _mm256_maddubs_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskload_epi32(mem_addr: *const i32, mask: __m128i) -> __m128i {
-    transmute(maskloadd(mem_addr as *const i8, mask.as_i32x4()))
+    let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i32x4::ZERO).as_m128i()
 }
 
 /// Loads packed 32-bit integers from memory pointed by `mem_addr` using `mask`
@@ -1799,7 +1800,8 @@ pub unsafe fn _mm_maskload_epi32(mem_addr: *const i32, mask: __m128i) -> __m128i
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskload_epi32(mem_addr: *const i32, mask: __m256i) -> __m256i {
-    transmute(maskloadd256(mem_addr as *const i8, mask.as_i32x8()))
+    let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i32x8::ZERO).as_m256i()
 }
 
 /// Loads packed 64-bit integers from memory pointed by `mem_addr` using `mask`
@@ -1812,7 +1814,8 @@ pub unsafe fn _mm256_maskload_epi32(mem_addr: *const i32, mask: __m256i) -> __m2
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskload_epi64(mem_addr: *const i64, mask: __m128i) -> __m128i {
-    transmute(maskloadq(mem_addr as *const i8, mask.as_i64x2()))
+    let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i64x2::ZERO).as_m128i()
 }
 
 /// Loads packed 64-bit integers from memory pointed by `mem_addr` using `mask`
@@ -1825,7 +1828,8 @@ pub unsafe fn _mm_maskload_epi64(mem_addr: *const i64, mask: __m128i) -> __m128i
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskload_epi64(mem_addr: *const i64, mask: __m256i) -> __m256i {
-    transmute(maskloadq256(mem_addr as *const i8, mask.as_i64x4()))
+    let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
+    simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i64x4::ZERO).as_m256i()
 }
 
 /// Stores packed 32-bit integers from `a` into memory pointed by `mem_addr`
@@ -1838,7 +1842,8 @@ pub unsafe fn _mm256_maskload_epi64(mem_addr: *const i64, mask: __m256i) -> __m2
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskstore_epi32(mem_addr: *mut i32, mask: __m128i, a: __m128i) {
-    maskstored(mem_addr as *mut i8, mask.as_i32x4(), a.as_i32x4())
+    let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x4())
 }
 
 /// Stores packed 32-bit integers from `a` into memory pointed by `mem_addr`
@@ -1851,7 +1856,8 @@ pub unsafe fn _mm_maskstore_epi32(mem_addr: *mut i32, mask: __m128i, a: __m128i)
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskstore_epi32(mem_addr: *mut i32, mask: __m256i, a: __m256i) {
-    maskstored256(mem_addr as *mut i8, mask.as_i32x8(), a.as_i32x8())
+    let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x8())
 }
 
 /// Stores packed 64-bit integers from `a` into memory pointed by `mem_addr`
@@ -1864,7 +1870,8 @@ pub unsafe fn _mm256_maskstore_epi32(mem_addr: *mut i32, mask: __m256i, a: __m25
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm_maskstore_epi64(mem_addr: *mut i64, mask: __m128i, a: __m128i) {
-    maskstoreq(mem_addr as *mut i8, mask.as_i64x2(), a.as_i64x2())
+    let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x2())
 }
 
 /// Stores packed 64-bit integers from `a` into memory pointed by `mem_addr`
@@ -1877,7 +1884,8 @@ pub unsafe fn _mm_maskstore_epi64(mem_addr: *mut i64, mask: __m128i, a: __m128i)
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_maskstore_epi64(mem_addr: *mut i64, mask: __m256i, a: __m256i) {
-    maskstoreq256(mem_addr as *mut i8, mask.as_i64x4(), a.as_i64x4())
+    let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x4())
 }
 
 /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
@@ -3645,22 +3653,6 @@ unsafe extern "C" {
     fn phsubsw(a: i16x16, b: i16x16) -> i16x16;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
     fn pmaddubsw(a: u8x32, b: u8x32) -> i16x16;
-    #[link_name = "llvm.x86.avx2.maskload.d"]
-    fn maskloadd(mem_addr: *const i8, mask: i32x4) -> i32x4;
-    #[link_name = "llvm.x86.avx2.maskload.d.256"]
-    fn maskloadd256(mem_addr: *const i8, mask: i32x8) -> i32x8;
-    #[link_name = "llvm.x86.avx2.maskload.q"]
-    fn maskloadq(mem_addr: *const i8, mask: i64x2) -> i64x2;
-    #[link_name = "llvm.x86.avx2.maskload.q.256"]
-    fn maskloadq256(mem_addr: *const i8, mask: i64x4) -> i64x4;
-    #[link_name = "llvm.x86.avx2.maskstore.d"]
-    fn maskstored(mem_addr: *mut i8, mask: i32x4, a: i32x4);
-    #[link_name = "llvm.x86.avx2.maskstore.d.256"]
-    fn maskstored256(mem_addr: *mut i8, mask: i32x8, a: i32x8);
-    #[link_name = "llvm.x86.avx2.maskstore.q"]
-    fn maskstoreq(mem_addr: *mut i8, mask: i64x2, a: i64x2);
-    #[link_name = "llvm.x86.avx2.maskstore.q.256"]
-    fn maskstoreq256(mem_addr: *mut i8, mask: i64x4, a: i64x4);
     #[link_name = "llvm.x86.avx2.mpsadbw"]
     fn mpsadbw(a: u8x32, b: u8x32, imm8: i8) -> u16x16;
     #[link_name = "llvm.x86.avx2.pmul.hr.sw"]

From 07d9723d7b3ebab29e2dccf3c0fa20d4819ef1b3 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 10 Nov 2025 04:10:10 +0000
Subject: [PATCH 018/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to 8401398e1f14a24670ee1a3203713dc2f0f8b3a8.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index e313eada45..04d41c96f5 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-73e6c9ebd9123154a196300ef58e30ec8928e74e
+8401398e1f14a24670ee1a3203713dc2f0f8b3a8

From bd215e33f926bb6849376396031aa749ac235b28 Mon Sep 17 00:00:00 2001
From: MarcoIeni <11428655+MarcoIeni@users.noreply.github.com>
Date: Tue, 11 Nov 2025 10:04:15 +0100
Subject: [PATCH 019/326] rename default branch to main

---
 .github/workflows/rustc-pull.yml | 2 +-
 crates/core_arch/README.md       | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/rustc-pull.yml b/.github/workflows/rustc-pull.yml
index 1379bd06b0..ee0c498878 100644
--- a/.github/workflows/rustc-pull.yml
+++ b/.github/workflows/rustc-pull.yml
@@ -16,7 +16,7 @@ jobs:
       # https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782
       zulip-stream-id: 208962
       zulip-bot-email:  "stdarch-ci-bot@rust-lang.zulipchat.com"
-      pr-base-branch: master
+      pr-base-branch: main
       branch-name: rustc-pull
     secrets:
       zulip-api-token: ${{ secrets.ZULIP_API_TOKEN }}
diff --git a/crates/core_arch/README.md b/crates/core_arch/README.md
index fc18a5759d..d341365b98 100644
--- a/crates/core_arch/README.md
+++ b/crates/core_arch/README.md
@@ -3,7 +3,7 @@
 
 The `core::arch` module implements architecture-dependent intrinsics (e.g. SIMD).
 
-# Usage 
+# Usage
 
 `core::arch` is available as part of `libcore` and it is re-exported by
 `libstd`. Prefer using it via `core::arch` or `std::arch` than via this crate.
@@ -17,7 +17,7 @@ are:
   you need to re-compile it for a non-standard target, please prefer using
   `xargo` and re-compiling `libcore`/`libstd` as appropriate instead of using
   this crate.
-  
+
 * using some features that might not be available even behind unstable Rust
   features. We try to keep these to a minimum. If you need to use some of these
   features, please open an issue so that we can expose them in nightly Rust and
@@ -34,7 +34,7 @@ are:
 * [How to get started][contrib]
 * [How to help implement intrinsics][help-implement]
 
-[contrib]: https://github.com/rust-lang/stdarch/blob/master/CONTRIBUTING.md
+[contrib]: https://github.com/rust-lang/stdarch/blob/HEAD/CONTRIBUTING.md
 [help-implement]: https://github.com/rust-lang/stdarch/issues/40
 [i686]: https://rust-lang.github.io/stdarch/i686/core_arch/
 [x86_64]: https://rust-lang.github.io/stdarch/x86_64/core_arch/

From 3fface7dbd8bdf448b4a57daa71d6ffec5c6a490 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 11 Nov 2025 10:55:37 +0100
Subject: [PATCH 020/326] add logic tests for ternarylogic

previously the output would just always be all zeroes
---
 crates/core_arch/src/x86/avx512f.rs | 65 ++++++++++++++++++++++-------
 1 file changed, 50 insertions(+), 15 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index b60df7dbc9..81242fa6fc 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -46240,11 +46240,22 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     unsafe fn test_mm512_ternarylogic_epi32() {
-        let a = _mm512_set1_epi32(1 << 2);
-        let b = _mm512_set1_epi32(1 << 1);
-        let c = _mm512_set1_epi32(1 << 0);
-        let r = _mm512_ternarylogic_epi32::<8>(a, b, c);
-        let e = _mm512_set1_epi32(0);
+        let a = _mm512_set4_epi32(0b100, 0b110, 0b001, 0b101);
+        let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b101);
+        let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b101);
+
+        // Identity of A.
+        let r = _mm512_ternarylogic_epi32::<0b1111_0000>(a, b, c);
+        assert_eq_m512i(r, a);
+
+        // Bitwise or.
+        let r = _mm512_ternarylogic_epi32::<0b1111_1110>(a, b, c);
+        let e = _mm512_set4_epi32(0b111, 0b111, 0b001, 0b101);
+        assert_eq_m512i(r, e);
+
+        // Majority.
+        let r = _mm512_ternarylogic_epi32::<0b1110_1000>(a, b, c);
+        let e = _mm512_set4_epi32(0b000, 0b010, 0b001, 0b101);
         assert_eq_m512i(r, e);
     }
 
@@ -46274,11 +46285,24 @@ mod tests {
 
     #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm256_ternarylogic_epi32() {
-        let a = _mm256_set1_epi32(1 << 2);
-        let b = _mm256_set1_epi32(1 << 1);
-        let c = _mm256_set1_epi32(1 << 0);
-        let r = _mm256_ternarylogic_epi32::<8>(a, b, c);
-        let e = _mm256_set1_epi32(0);
+        let _mm256_set4_epi32 = |a, b, c, d| _mm256_setr_epi32(a, b, c, d, a, b, c, d);
+
+        let a = _mm256_set4_epi32(0b100, 0b110, 0b001, 0b101);
+        let b = _mm256_set4_epi32(0b010, 0b011, 0b001, 0b101);
+        let c = _mm256_set4_epi32(0b001, 0b000, 0b001, 0b101);
+
+        // Identity of A.
+        let r = _mm256_ternarylogic_epi32::<0b1111_0000>(a, b, c);
+        assert_eq_m256i(r, a);
+
+        // Bitwise or.
+        let r = _mm256_ternarylogic_epi32::<0b1111_1110>(a, b, c);
+        let e = _mm256_set4_epi32(0b111, 0b111, 0b001, 0b101);
+        assert_eq_m256i(r, e);
+
+        // Majority.
+        let r = _mm256_ternarylogic_epi32::<0b1110_1000>(a, b, c);
+        let e = _mm256_set4_epi32(0b000, 0b010, 0b001, 0b101);
         assert_eq_m256i(r, e);
     }
 
@@ -46308,11 +46332,22 @@ mod tests {
 
     #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm_ternarylogic_epi32() {
-        let a = _mm_set1_epi32(1 << 2);
-        let b = _mm_set1_epi32(1 << 1);
-        let c = _mm_set1_epi32(1 << 0);
-        let r = _mm_ternarylogic_epi32::<8>(a, b, c);
-        let e = _mm_set1_epi32(0);
+        let a = _mm_setr_epi32(0b100, 0b110, 0b001, 0b101);
+        let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b101);
+        let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b101);
+
+        // Identity of A.
+        let r = _mm_ternarylogic_epi32::<0b1111_0000>(a, b, c);
+        assert_eq_m128i(r, a);
+
+        // Bitwise or.
+        let r = _mm_ternarylogic_epi32::<0b1111_1110>(a, b, c);
+        let e = _mm_setr_epi32(0b111, 0b111, 0b001, 0b101);
+        assert_eq_m128i(r, e);
+
+        // Majority.
+        let r = _mm_ternarylogic_epi32::<0b1110_1000>(a, b, c);
+        let e = _mm_setr_epi32(0b000, 0b010, 0b001, 0b101);
         assert_eq_m128i(r, e);
     }
 

From 9a7039641cacb0b874cfbfc40ed2fe2d3640eb08 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 11 Nov 2025 17:04:11 +0100
Subject: [PATCH 021/326] improve ternary logic tests

---
 crates/core_arch/src/x86/avx512f.rs | 51 +++++++++++++++++------------
 1 file changed, 30 insertions(+), 21 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 81242fa6fc..b5d0daae66 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -46240,22 +46240,25 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     unsafe fn test_mm512_ternarylogic_epi32() {
+        use core::intrinsics::simd::simd_xor;
+
         let a = _mm512_set4_epi32(0b100, 0b110, 0b001, 0b101);
-        let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b101);
-        let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b101);
+        let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b110);
+        let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b111);
 
         // Identity of A.
         let r = _mm512_ternarylogic_epi32::<0b1111_0000>(a, b, c);
         assert_eq_m512i(r, a);
 
-        // Bitwise or.
-        let r = _mm512_ternarylogic_epi32::<0b1111_1110>(a, b, c);
-        let e = _mm512_set4_epi32(0b111, 0b111, 0b001, 0b101);
+        // Bitwise xor.
+        let r = _mm512_ternarylogic_epi32::<0b10010110>(a, b, c);
+        let e = _mm512_set4_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m512i(r, e);
+        assert_eq_m512i(r, simd_xor(simd_xor(a, b), c));
 
-        // Majority.
+        // Majority (2 or more bits set).
         let r = _mm512_ternarylogic_epi32::<0b1110_1000>(a, b, c);
-        let e = _mm512_set4_epi32(0b000, 0b010, 0b001, 0b101);
+        let e = _mm512_set4_epi32(0b000, 0b010, 0b001, 0b111);
         assert_eq_m512i(r, e);
     }
 
@@ -46285,24 +46288,27 @@ mod tests {
 
     #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm256_ternarylogic_epi32() {
+        use core::intrinsics::simd::simd_xor;
+
         let _mm256_set4_epi32 = |a, b, c, d| _mm256_setr_epi32(a, b, c, d, a, b, c, d);
 
         let a = _mm256_set4_epi32(0b100, 0b110, 0b001, 0b101);
-        let b = _mm256_set4_epi32(0b010, 0b011, 0b001, 0b101);
-        let c = _mm256_set4_epi32(0b001, 0b000, 0b001, 0b101);
+        let b = _mm256_set4_epi32(0b010, 0b011, 0b001, 0b110);
+        let c = _mm256_set4_epi32(0b001, 0b000, 0b001, 0b111);
 
         // Identity of A.
         let r = _mm256_ternarylogic_epi32::<0b1111_0000>(a, b, c);
         assert_eq_m256i(r, a);
 
-        // Bitwise or.
-        let r = _mm256_ternarylogic_epi32::<0b1111_1110>(a, b, c);
-        let e = _mm256_set4_epi32(0b111, 0b111, 0b001, 0b101);
+        // Bitwise xor.
+        let r = _mm256_ternarylogic_epi32::<0b10010110>(a, b, c);
+        let e = _mm256_set4_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m256i(r, e);
+        assert_eq_m256i(r, simd_xor(simd_xor(a, b), c));
 
-        // Majority.
+        // Majority (2 or more bits set).
         let r = _mm256_ternarylogic_epi32::<0b1110_1000>(a, b, c);
-        let e = _mm256_set4_epi32(0b000, 0b010, 0b001, 0b101);
+        let e = _mm256_set4_epi32(0b000, 0b010, 0b001, 0b111);
         assert_eq_m256i(r, e);
     }
 
@@ -46332,22 +46338,25 @@ mod tests {
 
     #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm_ternarylogic_epi32() {
+        use core::intrinsics::simd::simd_xor;
+
         let a = _mm_setr_epi32(0b100, 0b110, 0b001, 0b101);
-        let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b101);
-        let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b101);
+        let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b110);
+        let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b111);
 
         // Identity of A.
         let r = _mm_ternarylogic_epi32::<0b1111_0000>(a, b, c);
         assert_eq_m128i(r, a);
 
-        // Bitwise or.
-        let r = _mm_ternarylogic_epi32::<0b1111_1110>(a, b, c);
-        let e = _mm_setr_epi32(0b111, 0b111, 0b001, 0b101);
+        // Bitwise xor.
+        let r = _mm_ternarylogic_epi32::<0b10010110>(a, b, c);
+        let e = _mm_setr_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m128i(r, e);
+        assert_eq_m128i(r, simd_xor(simd_xor(a, b), c));
 
-        // Majority.
+        // Majority (2 or more bits set).
         let r = _mm_ternarylogic_epi32::<0b1110_1000>(a, b, c);
-        let e = _mm_setr_epi32(0b000, 0b010, 0b001, 0b101);
+        let e = _mm_setr_epi32(0b000, 0b010, 0b001, 0b111);
         assert_eq_m128i(r, e);
     }
 

From 102f03d2c410660a45d0231fdafdd347e0d4e77f Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Wed, 12 Nov 2025 07:36:22 +0530
Subject: [PATCH 022/326] Use SIMD intrinsics for vector shifts

---
 crates/core_arch/src/x86/avx2.rs     | 90 ++++++++++++++++++----------
 crates/core_arch/src/x86/avx512bw.rs | 84 ++++++++++++++++----------
 crates/core_arch/src/x86/avx512f.rs  | 75 ++++++++++++++---------
 3 files changed, 162 insertions(+), 87 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index de27ee7b45..2e6e010a21 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -2786,7 +2786,12 @@ pub fn _mm256_bslli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsllvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(psllvd(a.as_i32x4(), count.as_i32x4())) }
+    unsafe {
+        let count = count.as_u32x4();
+        let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
+        let count = simd_select(no_overflow, count, u32x4::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u32x4(), count), u32x4::ZERO).as_m128i()
+    }
 }
 
 /// Shifts packed 32-bit integers in `a` left by the amount
@@ -2799,7 +2804,12 @@ pub fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpsllvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(psllvd256(a.as_i32x8(), count.as_i32x8())) }
+    unsafe {
+        let count = count.as_u32x8();
+        let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
+        let count = simd_select(no_overflow, count, u32x8::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u32x8(), count), u32x8::ZERO).as_m256i()
+    }
 }
 
 /// Shifts packed 64-bit integers in `a` left by the amount
@@ -2812,7 +2822,12 @@ pub fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsllvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(psllvq(a.as_i64x2(), count.as_i64x2())) }
+    unsafe {
+        let count = count.as_u64x2();
+        let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, count, u64x2::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u64x2(), count), u64x2::ZERO).as_m128i()
+    }
 }
 
 /// Shifts packed 64-bit integers in `a` left by the amount
@@ -2825,7 +2840,12 @@ pub fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpsllvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_sllv_epi64(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(psllvq256(a.as_i64x4(), count.as_i64x4())) }
+    unsafe {
+        let count = count.as_u64x4();
+        let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, count, u64x4::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u64x4(), count), u64x4::ZERO).as_m256i()
+    }
 }
 
 /// Shifts packed 16-bit integers in `a` right by `count` while
@@ -2889,7 +2909,12 @@ pub fn _mm256_srai_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsravd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(psravd(a.as_i32x4(), count.as_i32x4())) }
+    unsafe {
+        let count = count.as_u32x4();
+        let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
+        let count = simd_select(no_overflow, transmute(count), i32x4::splat(31));
+        simd_shr(a.as_i32x4(), count).as_m128i()
+    }
 }
 
 /// Shifts packed 32-bit integers in `a` right by the amount specified by the
@@ -2901,7 +2926,12 @@ pub fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpsravd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(psravd256(a.as_i32x8(), count.as_i32x8())) }
+    unsafe {
+        let count = count.as_u32x8();
+        let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
+        let count = simd_select(no_overflow, transmute(count), i32x8::splat(31));
+        simd_shr(a.as_i32x8(), count).as_m256i()
+    }
 }
 
 /// Shifts 128-bit lanes in `a` right by `imm8` bytes while shifting in zeros.
@@ -3084,7 +3114,12 @@ pub fn _mm256_srli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrlvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(psrlvd(a.as_i32x4(), count.as_i32x4())) }
+    unsafe {
+        let count = count.as_u32x4();
+        let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
+        let count = simd_select(no_overflow, count, u32x4::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u32x4(), count), u32x4::ZERO).as_m128i()
+    }
 }
 
 /// Shifts packed 32-bit integers in `a` right by the amount specified by
@@ -3096,7 +3131,12 @@ pub fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpsrlvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(psrlvd256(a.as_i32x8(), count.as_i32x8())) }
+    unsafe {
+        let count = count.as_u32x8();
+        let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
+        let count = simd_select(no_overflow, count, u32x8::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u32x8(), count), u32x8::ZERO).as_m256i()
+    }
 }
 
 /// Shifts packed 64-bit integers in `a` right by the amount specified by
@@ -3108,7 +3148,12 @@ pub fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrlvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(psrlvq(a.as_i64x2(), count.as_i64x2())) }
+    unsafe {
+        let count = count.as_u64x2();
+        let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, count, u64x2::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u64x2(), count), u64x2::ZERO).as_m128i()
+    }
 }
 
 /// Shifts packed 64-bit integers in `a` right by the amount specified by
@@ -3120,7 +3165,12 @@ pub fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpsrlvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(psrlvq256(a.as_i64x4(), count.as_i64x4())) }
+    unsafe {
+        let count = count.as_u64x4();
+        let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, count, u64x4::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u64x4(), count), u64x4::ZERO).as_m256i()
+    }
 }
 
 /// Load 256-bits of integer data from memory into dst using a non-temporal memory hint. mem_addr
@@ -3679,36 +3729,16 @@ unsafe extern "C" {
     fn pslld(a: i32x8, count: i32x4) -> i32x8;
     #[link_name = "llvm.x86.avx2.psll.q"]
     fn psllq(a: i64x4, count: i64x2) -> i64x4;
-    #[link_name = "llvm.x86.avx2.psllv.d"]
-    fn psllvd(a: i32x4, count: i32x4) -> i32x4;
-    #[link_name = "llvm.x86.avx2.psllv.d.256"]
-    fn psllvd256(a: i32x8, count: i32x8) -> i32x8;
-    #[link_name = "llvm.x86.avx2.psllv.q"]
-    fn psllvq(a: i64x2, count: i64x2) -> i64x2;
-    #[link_name = "llvm.x86.avx2.psllv.q.256"]
-    fn psllvq256(a: i64x4, count: i64x4) -> i64x4;
     #[link_name = "llvm.x86.avx2.psra.w"]
     fn psraw(a: i16x16, count: i16x8) -> i16x16;
     #[link_name = "llvm.x86.avx2.psra.d"]
     fn psrad(a: i32x8, count: i32x4) -> i32x8;
-    #[link_name = "llvm.x86.avx2.psrav.d"]
-    fn psravd(a: i32x4, count: i32x4) -> i32x4;
-    #[link_name = "llvm.x86.avx2.psrav.d.256"]
-    fn psravd256(a: i32x8, count: i32x8) -> i32x8;
     #[link_name = "llvm.x86.avx2.psrl.w"]
     fn psrlw(a: i16x16, count: i16x8) -> i16x16;
     #[link_name = "llvm.x86.avx2.psrl.d"]
     fn psrld(a: i32x8, count: i32x4) -> i32x8;
     #[link_name = "llvm.x86.avx2.psrl.q"]
     fn psrlq(a: i64x4, count: i64x2) -> i64x4;
-    #[link_name = "llvm.x86.avx2.psrlv.d"]
-    fn psrlvd(a: i32x4, count: i32x4) -> i32x4;
-    #[link_name = "llvm.x86.avx2.psrlv.d.256"]
-    fn psrlvd256(a: i32x8, count: i32x8) -> i32x8;
-    #[link_name = "llvm.x86.avx2.psrlv.q"]
-    fn psrlvq(a: i64x2, count: i64x2) -> i64x2;
-    #[link_name = "llvm.x86.avx2.psrlv.q.256"]
-    fn psrlvq256(a: i64x4, count: i64x4) -> i64x4;
     #[link_name = "llvm.x86.avx2.pshuf.b"]
     fn pshufb(a: u8x32, b: u8x32) -> u8x32;
     #[link_name = "llvm.x86.avx2.permd"]
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 72842f4546..78f4dd53b9 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6864,7 +6864,12 @@ pub fn _mm_maskz_slli_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
 pub fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsllvw(a.as_i16x32(), count.as_i16x32())) }
+    unsafe {
+        let count = count.as_u16x32();
+        let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, count, u16x32::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u16x32(), count), u16x32::ZERO).as_m512i()
+    }
 }
 
 /// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6903,7 +6908,12 @@ pub fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
 pub fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(vpsllvw256(a.as_i16x16(), count.as_i16x16())) }
+    unsafe {
+        let count = count.as_u16x16();
+        let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, count, u16x16::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u16x16(), count), u16x16::ZERO).as_m256i()
+    }
 }
 
 /// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6942,7 +6952,12 @@ pub fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
 pub fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(vpsllvw128(a.as_i16x8(), count.as_i16x8())) }
+    unsafe {
+        let count = count.as_u16x8();
+        let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, count, u16x8::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u16x8(), count), u16x8::ZERO).as_m128i()
+    }
 }
 
 /// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7200,7 +7215,12 @@ pub fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
 pub fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsrlvw(a.as_i16x32(), count.as_i16x32())) }
+    unsafe {
+        let count = count.as_u16x32();
+        let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, count, u16x32::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u16x32(), count), u16x32::ZERO).as_m512i()
+    }
 }
 
 /// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7239,7 +7259,12 @@ pub fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
 pub fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(vpsrlvw256(a.as_i16x16(), count.as_i16x16())) }
+    unsafe {
+        let count = count.as_u16x16();
+        let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, count, u16x16::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u16x16(), count), u16x16::ZERO).as_m256i()
+    }
 }
 
 /// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7278,7 +7303,12 @@ pub fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
 pub fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(vpsrlvw128(a.as_i16x8(), count.as_i16x8())) }
+    unsafe {
+        let count = count.as_u16x8();
+        let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, count, u16x8::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u16x8(), count), u16x8::ZERO).as_m128i()
+    }
 }
 
 /// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7523,7 +7553,12 @@ pub fn _mm_maskz_srai_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
 pub fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsravw(a.as_i16x32(), count.as_i16x32())) }
+    unsafe {
+        let count = count.as_u16x32();
+        let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, transmute(count), i16x32::splat(15));
+        simd_shr(a.as_i16x32(), count).as_m512i()
+    }
 }
 
 /// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7562,7 +7597,12 @@ pub fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
 pub fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(vpsravw256(a.as_i16x16(), count.as_i16x16())) }
+    unsafe {
+        let count = count.as_u16x16();
+        let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, transmute(count), i16x16::splat(15));
+        simd_shr(a.as_i16x16(), count).as_m256i()
+    }
 }
 
 /// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -7601,7 +7641,12 @@ pub fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
 pub fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(vpsravw128(a.as_i16x8(), count.as_i16x8())) }
+    unsafe {
+        let count = count.as_u16x8();
+        let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
+        let count = simd_select(no_overflow, transmute(count), i16x8::splat(15));
+        simd_shr(a.as_i16x8(), count).as_m128i()
+    }
 }
 
 /// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -11657,33 +11702,12 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.psll.w.512"]
     fn vpsllw(a: i16x32, count: i16x8) -> i16x32;
 
-    #[link_name = "llvm.x86.avx512.psllv.w.512"]
-    fn vpsllvw(a: i16x32, b: i16x32) -> i16x32;
-    #[link_name = "llvm.x86.avx512.psllv.w.256"]
-    fn vpsllvw256(a: i16x16, b: i16x16) -> i16x16;
-    #[link_name = "llvm.x86.avx512.psllv.w.128"]
-    fn vpsllvw128(a: i16x8, b: i16x8) -> i16x8;
-
     #[link_name = "llvm.x86.avx512.psrl.w.512"]
     fn vpsrlw(a: i16x32, count: i16x8) -> i16x32;
 
-    #[link_name = "llvm.x86.avx512.psrlv.w.512"]
-    fn vpsrlvw(a: i16x32, b: i16x32) -> i16x32;
-    #[link_name = "llvm.x86.avx512.psrlv.w.256"]
-    fn vpsrlvw256(a: i16x16, b: i16x16) -> i16x16;
-    #[link_name = "llvm.x86.avx512.psrlv.w.128"]
-    fn vpsrlvw128(a: i16x8, b: i16x8) -> i16x8;
-
     #[link_name = "llvm.x86.avx512.psra.w.512"]
     fn vpsraw(a: i16x32, count: i16x8) -> i16x32;
 
-    #[link_name = "llvm.x86.avx512.psrav.w.512"]
-    fn vpsravw(a: i16x32, count: i16x32) -> i16x32;
-    #[link_name = "llvm.x86.avx512.psrav.w.256"]
-    fn vpsravw256(a: i16x16, count: i16x16) -> i16x16;
-    #[link_name = "llvm.x86.avx512.psrav.w.128"]
-    fn vpsravw128(a: i16x8, count: i16x8) -> i16x8;
-
     #[link_name = "llvm.x86.avx512.vpermi2var.hi.512"]
     fn vpermi2w(a: i16x32, idx: i16x32, b: i16x32) -> i16x32;
     #[link_name = "llvm.x86.avx512.vpermi2var.hi.256"]
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index c87946846e..0ff0e7575c 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -20940,7 +20940,12 @@ pub fn _mm_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
 pub fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsravd(a.as_i32x16(), count.as_i32x16())) }
+    unsafe {
+        let count = count.as_u32x16();
+        let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
+        let count = simd_select(no_overflow, transmute(count), i32x16::splat(31));
+        simd_shr(a.as_i32x16(), count).as_m512i()
+    }
 }
 
 /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21035,7 +21040,12 @@ pub fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
 pub fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsravq(a.as_i64x8(), count.as_i64x8())) }
+    unsafe {
+        let count = count.as_u64x8();
+        let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, transmute(count), i64x8::splat(63));
+        simd_shr(a.as_i64x8(), count).as_m512i()
+    }
 }
 
 /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21074,7 +21084,12 @@ pub fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
 pub fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
-    unsafe { transmute(vpsravq256(a.as_i64x4(), count.as_i64x4())) }
+    unsafe {
+        let count = count.as_u64x4();
+        let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, transmute(count), i64x4::splat(63));
+        simd_shr(a.as_i64x4(), count).as_m256i()
+    }
 }
 
 /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21113,7 +21128,12 @@ pub fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
 pub fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
-    unsafe { transmute(vpsravq128(a.as_i64x2(), count.as_i64x2())) }
+    unsafe {
+        let count = count.as_u64x2();
+        let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, transmute(count), i64x2::splat(63));
+        simd_shr(a.as_i64x2(), count).as_m128i()
+    }
 }
 
 /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21692,7 +21712,12 @@ pub fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
 pub fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsllvd(a.as_i32x16(), count.as_i32x16())) }
+    unsafe {
+        let count = count.as_u32x16();
+        let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
+        let count = simd_select(no_overflow, count, u32x16::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u32x16(), count), u32x16::ZERO).as_m512i()
+    }
 }
 
 /// Shift packed 32-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21787,7 +21812,12 @@ pub fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
 pub fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsrlvd(a.as_i32x16(), count.as_i32x16())) }
+    unsafe {
+        let count = count.as_u32x16();
+        let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
+        let count = simd_select(no_overflow, count, u32x16::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u32x16(), count), u32x16::ZERO).as_m512i()
+    }
 }
 
 /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21882,7 +21912,12 @@ pub fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
 pub fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsllvq(a.as_i64x8(), count.as_i64x8())) }
+    unsafe {
+        let count = count.as_u64x8();
+        let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, count, u64x8::ZERO);
+        simd_select(no_overflow, simd_shl(a.as_u64x8(), count), u64x8::ZERO).as_m512i()
+    }
 }
 
 /// Shift packed 64-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21977,7 +22012,12 @@ pub fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
 pub fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
-    unsafe { transmute(vpsrlvq(a.as_i64x8(), count.as_i64x8())) }
+    unsafe {
+        let count = count.as_u64x8();
+        let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
+        let count = simd_select(no_overflow, count, u64x8::ZERO);
+        simd_select(no_overflow, simd_shr(a.as_u64x8(), count), u64x8::ZERO).as_m512i()
+    }
 }
 
 /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -42881,15 +42921,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.mask.cmp.pd.128"]
     fn vcmppd128(a: f64x2, b: f64x2, op: i32, m: i8) -> i8;
 
-    #[link_name = "llvm.x86.avx512.psllv.d.512"]
-    fn vpsllvd(a: i32x16, b: i32x16) -> i32x16;
-    #[link_name = "llvm.x86.avx512.psrlv.d.512"]
-    fn vpsrlvd(a: i32x16, b: i32x16) -> i32x16;
-    #[link_name = "llvm.x86.avx512.psllv.q.512"]
-    fn vpsllvq(a: i64x8, b: i64x8) -> i64x8;
-    #[link_name = "llvm.x86.avx512.psrlv.q.512"]
-    fn vpsrlvq(a: i64x8, b: i64x8) -> i64x8;
-
     #[link_name = "llvm.x86.avx512.psll.d.512"]
     fn vpslld(a: i32x16, count: i32x4) -> i32x16;
     #[link_name = "llvm.x86.avx512.psrl.d.512"]
@@ -42909,16 +42940,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.psra.q.128"]
     fn vpsraq128(a: i64x2, count: i64x2) -> i64x2;
 
-    #[link_name = "llvm.x86.avx512.psrav.d.512"]
-    fn vpsravd(a: i32x16, count: i32x16) -> i32x16;
-
-    #[link_name = "llvm.x86.avx512.psrav.q.512"]
-    fn vpsravq(a: i64x8, count: i64x8) -> i64x8;
-    #[link_name = "llvm.x86.avx512.psrav.q.256"]
-    fn vpsravq256(a: i64x4, count: i64x4) -> i64x4;
-    #[link_name = "llvm.x86.avx512.psrav.q.128"]
-    fn vpsravq128(a: i64x2, count: i64x2) -> i64x2;
-
     #[link_name = "llvm.x86.avx512.vpermilvar.ps.512"]
     fn vpermilps(a: f32x16, b: i32x16) -> f32x16;
     #[link_name = "llvm.x86.avx512.vpermilvar.pd.512"]

From 230f29b602420efe60c3cd0de124e3b9b1b28ed6 Mon Sep 17 00:00:00 2001
From: Matthew Maurer <mmaurer@google.com>
Date: Fri, 14 Nov 2025 19:25:34 +0000
Subject: [PATCH 023/326] aarch64: Remove withdrawn FEAT_TME

ARM has withdrawn FEAT_TME
https://developer.arm.com/documentation/102105/lb-05/

LLVM has also dropped support for enabling the feature.
---
 .../aarch64-unknown-linux-gnu/Dockerfile      |   3 +-
 .../aarch64_be-unknown-linux-gnu/Dockerfile   |   1 -
 crates/core_arch/src/aarch64/mod.rs           |   4 -
 crates/core_arch/src/aarch64/tme.rs           | 201 ------------------
 crates/stdarch-test/src/disassembly.rs        |   2 +-
 crates/stdarch-verify/tests/arm.rs            |   1 -
 6 files changed, 2 insertions(+), 210 deletions(-)
 delete mode 100644 crates/core_arch/src/aarch64/tme.rs

diff --git a/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
index 70c0650975..2768c521eb 100644
--- a/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
@@ -15,5 +15,4 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
 
 ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \
     CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max -L /usr/aarch64-linux-gnu" \
-    OBJDUMP=aarch64-linux-gnu-objdump \
-    STDARCH_TEST_SKIP_FEATURE=tme
+    OBJDUMP=aarch64-linux-gnu-objdump
diff --git a/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile b/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile
index 56ddbd990b..f85c6a2592 100644
--- a/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile
@@ -27,4 +27,3 @@ ENV AARCH64_BE_LIBC="${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc"
 ENV CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-gcc"
 ENV CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64_be -cpu max -L ${AARCH64_BE_LIBC}"
 ENV OBJDUMP="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-objdump"
-ENV STDARCH_TEST_SKIP_FEATURE=tme
diff --git a/crates/core_arch/src/aarch64/mod.rs b/crates/core_arch/src/aarch64/mod.rs
index f4b9b1c302..b48bdac57e 100644
--- a/crates/core_arch/src/aarch64/mod.rs
+++ b/crates/core_arch/src/aarch64/mod.rs
@@ -21,10 +21,6 @@ mod neon;
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub use self::neon::*;
 
-mod tme;
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub use self::tme::*;
-
 mod prefetch;
 #[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
 pub use self::prefetch::*;
diff --git a/crates/core_arch/src/aarch64/tme.rs b/crates/core_arch/src/aarch64/tme.rs
deleted file mode 100644
index 207633c1f8..0000000000
--- a/crates/core_arch/src/aarch64/tme.rs
+++ /dev/null
@@ -1,201 +0,0 @@
-//! ARM's Transactional Memory Extensions (TME).
-//!
-//! This CPU feature is available on Aarch64 - A architecture profile.
-//! This feature is in the non-neon feature set. TME specific vendor documentation can
-//! be found [TME Intrinsics Introduction][tme_intrinsics_intro].
-//!
-//! The reference is [ACLE Q4 2019][acle_q4_2019_ref].
-//!
-//! ACLE has a section for TME extensions and state masks for aborts and failure codes.
-//! [ARM A64 Architecture Register Datasheet][a_profile_future] also describes possible failure code scenarios.
-//!
-//! [acle_q4_2019_ref]: https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf
-//! [tme_intrinsics_intro]: https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics
-//! [llvm_aarch64_int]: https://github.com/llvm/llvm-project/commit/a36d31478c182903523e04eb271bbf102bfab2cc#diff-ff24e1c35f4d54f1110ce5d90c709319R626-R646
-//! [a_profile_future]: https://static.docs.arm.com/ddi0601/a/SysReg_xml_futureA-2019-04.pdf?_ga=2.116560387.441514988.1590524918-1110153136.1588469296
-
-#[cfg(test)]
-use stdarch_test::assert_instr;
-
-unsafe extern "unadjusted" {
-    #[link_name = "llvm.aarch64.tstart"]
-    fn aarch64_tstart() -> u64;
-    #[link_name = "llvm.aarch64.tcommit"]
-    fn aarch64_tcommit();
-    #[link_name = "llvm.aarch64.tcancel"]
-    fn aarch64_tcancel(imm0: u64);
-    #[link_name = "llvm.aarch64.ttest"]
-    fn aarch64_ttest() -> u64;
-}
-
-/// Transaction successfully started.
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMSTART_SUCCESS: u64 = 0x00_u64;
-
-/// Extraction mask for failure reason
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_REASON: u64 = 0x00007FFF_u64;
-
-/// Transaction retry is possible.
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_RTRY: u64 = 1 << 15;
-
-/// Transaction executed a TCANCEL instruction
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_CNCL: u64 = 1 << 16;
-
-/// Transaction aborted because a conflict occurred
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_MEM: u64 = 1 << 17;
-
-/// Fallback error type for any other reason
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_IMP: u64 = 1 << 18;
-
-/// Transaction aborted because a non-permissible operation was attempted
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_ERR: u64 = 1 << 19;
-
-/// Transaction aborted due to read or write set limit was exceeded
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_SIZE: u64 = 1 << 20;
-
-/// Transaction aborted due to transactional nesting level was exceeded
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_NEST: u64 = 1 << 21;
-
-/// Transaction aborted due to a debug trap.
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_DBG: u64 = 1 << 22;
-
-/// Transaction failed from interrupt
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_INT: u64 = 1 << 23;
-
-/// Indicates a TRIVIAL version of TM is available
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub const _TMFAILURE_TRIVIAL: u64 = 1 << 24;
-
-// NOTE: Tests for these instructions are disabled on MSVC as dumpbin doesn't
-// understand these instructions.
-
-/// Starts a new transaction. When the transaction starts successfully the return value is 0.
-/// If the transaction fails, all state modifications are discarded and a cause of the failure
-/// is encoded in the return value.
-///
-/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
-#[inline]
-#[target_feature(enable = "tme")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(tstart))]
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub unsafe fn __tstart() -> u64 {
-    aarch64_tstart()
-}
-
-/// Commits the current transaction. For a nested transaction, the only effect is that the
-/// transactional nesting depth is decreased. For an outer transaction, the state modifications
-/// performed transactionally are committed to the architectural state.
-///
-/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
-#[inline]
-#[target_feature(enable = "tme")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(tcommit))]
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub unsafe fn __tcommit() {
-    aarch64_tcommit()
-}
-
-/// Cancels the current transaction and discards all state modifications that were performed transactionally.
-///
-/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
-#[inline]
-#[target_feature(enable = "tme")]
-#[cfg_attr(
-    all(test, not(target_env = "msvc")),
-    assert_instr(tcancel, IMM16 = 0x0)
-)]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub unsafe fn __tcancel<const IMM16: u64>() {
-    static_assert!(IMM16 <= 65535);
-    aarch64_tcancel(IMM16);
-}
-
-/// Tests if executing inside a transaction. If no transaction is currently executing,
-/// the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
-///
-/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
-#[inline]
-#[target_feature(enable = "tme")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ttest))]
-#[unstable(feature = "stdarch_aarch64_tme", issue = "117216")]
-pub unsafe fn __ttest() -> u64 {
-    aarch64_ttest()
-}
-
-#[cfg(test)]
-mod tests {
-    use stdarch_test::simd_test;
-
-    use crate::core_arch::aarch64::*;
-
-    const CANCEL_CODE: u64 = (0 | (0x123 & _TMFAILURE_REASON) as u64) as u64;
-
-    #[simd_test(enable = "tme")]
-    unsafe fn test_tstart() {
-        let mut x = 0;
-        for i in 0..10 {
-            let code = tme::__tstart();
-            if code == _TMSTART_SUCCESS {
-                x += 1;
-                assert_eq!(x, i + 1);
-                break;
-            }
-            assert_eq!(x, 0);
-        }
-    }
-
-    #[simd_test(enable = "tme")]
-    unsafe fn test_tcommit() {
-        let mut x = 0;
-        for i in 0..10 {
-            let code = tme::__tstart();
-            if code == _TMSTART_SUCCESS {
-                x += 1;
-                assert_eq!(x, i + 1);
-                tme::__tcommit();
-            }
-            assert_eq!(x, i + 1);
-        }
-    }
-
-    #[simd_test(enable = "tme")]
-    unsafe fn test_tcancel() {
-        let mut x = 0;
-
-        for i in 0..10 {
-            let code = tme::__tstart();
-            if code == _TMSTART_SUCCESS {
-                x += 1;
-                assert_eq!(x, i + 1);
-                tme::__tcancel::<CANCEL_CODE>();
-                break;
-            }
-        }
-
-        assert_eq!(x, 0);
-    }
-
-    #[simd_test(enable = "tme")]
-    unsafe fn test_ttest() {
-        for _ in 0..10 {
-            let code = tme::__tstart();
-            if code == _TMSTART_SUCCESS {
-                if tme::__ttest() == 2 {
-                    tme::__tcancel::<CANCEL_CODE>();
-                    break;
-                }
-            }
-        }
-    }
-}
diff --git a/crates/stdarch-test/src/disassembly.rs b/crates/stdarch-test/src/disassembly.rs
index 4c136cff02..237e8d2dc2 100644
--- a/crates/stdarch-test/src/disassembly.rs
+++ b/crates/stdarch-test/src/disassembly.rs
@@ -78,7 +78,7 @@ pub(crate) fn disassemble_myself() -> HashSet<Function> {
     let objdump = env::var("OBJDUMP").unwrap_or_else(|_| "objdump".to_string());
     let add_args = if cfg!(target_vendor = "apple") && cfg!(target_arch = "aarch64") {
         // Target features need to be enabled for LLVM objdump on Darwin ARM64
-        vec!["--mattr=+v8.6a,+crypto,+tme"]
+        vec!["--mattr=+v8.6a,+crypto"]
     } else if cfg!(any(target_arch = "riscv32", target_arch = "riscv64")) {
         vec!["--mattr=+zk,+zks,+zbc,+zbb"]
     } else {
diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs
index a35b8175fb..86897908e0 100644
--- a/crates/stdarch-verify/tests/arm.rs
+++ b/crates/stdarch-verify/tests/arm.rs
@@ -444,7 +444,6 @@ fn verify_all_signatures() {
                     && !rust.file.ends_with("v6.rs\"")
                     && !rust.file.ends_with("v7.rs\"")
                     && !rust.file.ends_with("v8.rs\"")
-                    && !rust.file.ends_with("tme.rs\"")
                     && !rust.file.ends_with("mte.rs\"")
                     && !rust.file.ends_with("ex.rs\"")
                     && !skip_intrinsic_verify.contains(&rust.name)

From ec160b87abad9ee6a5b8406be45eb85c3ead3b48 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 11 Nov 2025 04:57:42 +0530
Subject: [PATCH 024/326] correct some `#[simd_test]` attributes

---
 crates/core_arch/src/x86/avx2.rs       |   2 +-
 crates/core_arch/src/x86/avx512bw.rs   | 132 ++++++++++++-------------
 crates/core_arch/src/x86/avx512f.rs    |  14 +--
 crates/core_arch/src/x86/avx512fp16.rs |  40 ++++----
 crates/core_arch/src/x86/rdtsc.rs      |  12 +--
 crates/core_arch/src/x86/sse.rs        |   5 +-
 crates/core_arch/src/x86_64/amx.rs     |   4 +-
 crates/core_arch/src/x86_64/avx512f.rs |   6 +-
 8 files changed, 110 insertions(+), 105 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 2e6e010a21..e8213615a2 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -5749,7 +5749,7 @@ mod tests {
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
     }
 
-    #[simd_test(enable = "avx")]
+    #[simd_test(enable = "avx2")]
     unsafe fn test_mm256_extract_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 78f4dd53b9..aee705fb46 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -13335,7 +13335,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13352,7 +13352,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13369,7 +13369,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13380,7 +13380,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13391,7 +13391,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -13402,7 +13402,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -13434,7 +13434,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13462,7 +13462,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13489,7 +13489,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_max_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13506,7 +13506,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_max_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13523,7 +13523,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13534,7 +13534,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13560,7 +13560,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13577,7 +13577,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13594,7 +13594,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13605,7 +13605,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13616,7 +13616,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -13627,7 +13627,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -13659,7 +13659,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13687,7 +13687,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13714,7 +13714,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_max_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13731,7 +13731,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_max_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13748,7 +13748,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13759,7 +13759,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13785,7 +13785,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13802,7 +13802,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13819,7 +13819,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13830,7 +13830,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13841,7 +13841,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -13852,7 +13852,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -13884,7 +13884,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13912,7 +13912,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13939,7 +13939,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_min_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13956,7 +13956,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_min_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13973,7 +13973,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -13984,7 +13984,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -14010,7 +14010,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14027,7 +14027,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14044,7 +14044,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -14055,7 +14055,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -14066,7 +14066,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -14077,7 +14077,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
@@ -14109,7 +14109,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14137,7 +14137,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14164,7 +14164,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_min_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14181,7 +14181,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_min_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14198,7 +14198,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -14209,7 +14209,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
@@ -16326,7 +16326,7 @@ mod tests {
         assert_eq_m128i(r, a);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_loadu_epi16() {
         let src = _mm512_set1_epi16(42);
         let a = &[
@@ -16344,7 +16344,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_loadu_epi16() {
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16361,7 +16361,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_storeu_epi16() {
         let mut r = [42_i16; 32];
         let a = &[
@@ -16379,7 +16379,7 @@ mod tests {
         assert_eq_m512i(_mm512_loadu_epi16(r.as_ptr()), e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_loadu_epi8() {
         let src = _mm512_set1_epi8(42);
         let a = &[
@@ -16399,7 +16399,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16418,7 +16418,7 @@ mod tests {
         assert_eq_m512i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw")]
+    #[simd_test(enable = "avx512bw")]
     unsafe fn test_mm512_mask_storeu_epi8() {
         let mut r = [42_i8; 64];
         let a = &[
@@ -16438,7 +16438,7 @@ mod tests {
         assert_eq_m512i(_mm512_loadu_epi8(r.as_ptr()), e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_loadu_epi16() {
         let src = _mm256_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
@@ -16452,7 +16452,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
@@ -16463,7 +16463,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_storeu_epi16() {
         let mut r = [42_i16; 16];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
@@ -16477,7 +16477,7 @@ mod tests {
         assert_eq_m256i(_mm256_loadu_epi16(r.as_ptr()), e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_loadu_epi8() {
         let src = _mm256_set1_epi8(42);
         let a = &[
@@ -16495,7 +16495,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16512,7 +16512,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm256_mask_storeu_epi8() {
         let mut r = [42_i8; 32];
         let a = &[
@@ -16530,7 +16530,7 @@ mod tests {
         assert_eq_m256i(_mm256_loadu_epi8(r.as_ptr()), e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_loadu_epi16() {
         let src = _mm_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
@@ -16542,7 +16542,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
@@ -16553,7 +16553,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_storeu_epi16() {
         let mut r = [42_i16; 8];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
@@ -16565,7 +16565,7 @@ mod tests {
         assert_eq_m128i(_mm_loadu_epi16(r.as_ptr()), e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_loadu_epi8() {
         let src = _mm_set1_epi8(42);
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
@@ -16579,7 +16579,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_maskz_loadu_epi8() {
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
@@ -16590,7 +16590,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
+    #[simd_test(enable = "avx512bw,avx512vl")]
     unsafe fn test_mm_mask_storeu_epi8() {
         let mut r = [42_i8; 16];
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index ebffb9ac92..f7bf9178db 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -56076,7 +56076,7 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "avx512dq")]
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_kortest_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
@@ -56086,7 +56086,7 @@ mod tests {
         assert_eq!(all_ones, 1);
     }
 
-    #[simd_test(enable = "avx512dq")]
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_kortestc_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
@@ -56094,7 +56094,7 @@ mod tests {
         assert_eq!(r, 1);
     }
 
-    #[simd_test(enable = "avx512dq")]
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_kortestz_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
@@ -56102,7 +56102,7 @@ mod tests {
         assert_eq!(r, 0);
     }
 
-    #[simd_test(enable = "avx512dq")]
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_kshiftli_mask16() {
         let a: __mmask16 = 0b1001011011000011;
         let r = _kshiftli_mask16::<3>(a);
@@ -56122,7 +56122,7 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "avx512dq")]
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_kshiftri_mask16() {
         let a: __mmask16 = 0b1010100100111100;
         let r = _kshiftri_mask16::<3>(a);
@@ -57383,7 +57383,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm256_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm256_maskz_set1_epi32(0, a);
@@ -57404,7 +57404,7 @@ mod tests {
         assert_eq_m128i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm_maskz_set1_epi32(0, a);
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 293fda3064..13cae45d0f 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -20766,7 +20766,7 @@ mod tests {
         assert_eq_m128h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm_mask_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
@@ -20783,7 +20783,7 @@ mod tests {
         assert_eq_m128h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm_mask3_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
@@ -20800,7 +20800,7 @@ mod tests {
         assert_eq_m128h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm_maskz_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
@@ -24529,7 +24529,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_mask_cvtepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
@@ -24542,7 +24542,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_maskz_cvtepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvtepi32_ph(0b0101010101010101, a);
@@ -24552,7 +24552,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_cvt_roundepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
@@ -24562,7 +24562,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_mask_cvt_roundepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
@@ -24579,7 +24579,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_maskz_cvt_roundepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -24658,7 +24658,7 @@ mod tests {
         assert_eq_m128h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_cvtepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvtepu32_ph(a);
@@ -24668,7 +24668,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_mask_cvtepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
@@ -24681,7 +24681,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_maskz_cvtepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvtepu32_ph(0b0101010101010101, a);
@@ -24691,7 +24691,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_cvt_roundepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
@@ -24701,7 +24701,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_mask_cvt_roundepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
@@ -24719,7 +24719,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_maskz_cvt_roundepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -25006,7 +25006,7 @@ mod tests {
         assert_eq_m128h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_cvtxps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
@@ -25018,7 +25018,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_mask_cvtxps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
@@ -25033,7 +25033,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_maskz_cvtxps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
@@ -25045,7 +25045,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_cvtx_roundps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
@@ -25057,7 +25057,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_mask_cvtx_roundps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
@@ -25077,7 +25077,7 @@ mod tests {
         assert_eq_m256h(r, e);
     }
 
-    #[simd_test(enable = "avx512fp16")]
+    #[simd_test(enable = "avx512fp16,avx512vl")]
     unsafe fn test_mm512_maskz_cvtx_roundps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
diff --git a/crates/core_arch/src/x86/rdtsc.rs b/crates/core_arch/src/x86/rdtsc.rs
index 3b348153d6..89292d78af 100644
--- a/crates/core_arch/src/x86/rdtsc.rs
+++ b/crates/core_arch/src/x86/rdtsc.rs
@@ -64,16 +64,16 @@ mod tests {
     use crate::core_arch::x86::*;
     use stdarch_test::simd_test;
 
-    #[simd_test(enable = "sse2")]
-    unsafe fn test_rdtsc() {
-        let r = _rdtsc();
+    #[test]
+    fn test_rdtsc() {
+        let r = unsafe { _rdtsc() };
         assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
     }
 
-    #[simd_test(enable = "sse2")]
-    unsafe fn test_rdtscp() {
+    #[test]
+    fn test_rdtscp() {
         let mut aux = 0;
-        let r = __rdtscp(&mut aux);
+        let r = unsafe { __rdtscp(&mut aux) };
         assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
     }
 }
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 86f743e76d..7dd96dd1c9 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3052,8 +3052,9 @@ mod tests {
         assert_eq_m128(r, _mm_set1_ps(0.0));
     }
 
-    #[simd_test(enable = "sse")]
-    unsafe fn test_MM_SHUFFLE() {
+    #[test]
+    #[allow(non_snake_case)]
+    fn test_MM_SHUFFLE() {
         assert_eq!(_MM_SHUFFLE(0, 1, 1, 3), 0b00_01_01_11);
         assert_eq!(_MM_SHUFFLE(3, 1, 1, 0), 0b11_01_01_00);
         assert_eq!(_MM_SHUFFLE(1, 2, 2, 1), 0b01_10_10_01);
diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index c87514980d..3e0ac8f47c 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -937,7 +937,7 @@ mod tests {
         assert_eq!(res, [[128.0_f32; 16]; 16]);
     }
 
-    #[simd_test(enable = "amx-tile")]
+    #[simd_test(enable = "amx-movrs")]
     unsafe fn test_tile_loaddrs() {
         _init_amx();
         let mut config = __tilecfg::default();
@@ -954,7 +954,7 @@ mod tests {
         assert_eq!(out, [[1; 64]; 16]);
     }
 
-    #[simd_test(enable = "amx-tile")]
+    #[simd_test(enable = "amx-movrs")]
     unsafe fn test_tile_stream_loaddrs() {
         _init_amx();
         let mut config = __tilecfg::default();
diff --git a/crates/core_arch/src/x86_64/avx512f.rs b/crates/core_arch/src/x86_64/avx512f.rs
index 934c9e2812..a2656c8535 100644
--- a/crates/core_arch/src/x86_64/avx512f.rs
+++ b/crates/core_arch/src/x86_64/avx512f.rs
@@ -6453,6 +6453,7 @@ mod tests {
         assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
     }
 
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_mm512_set1_epi64() {
         let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
         assert_eq_m512i(r, _mm512_set1_epi64(2));
@@ -6464,6 +6465,7 @@ mod tests {
         assert_eq_m512d(expected, _mm512_set1_pd(2.));
     }
 
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_mm512_set4_epi64() {
         let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
@@ -6475,6 +6477,7 @@ mod tests {
         assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
     }
 
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_mm512_setr4_epi64() {
         let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
@@ -7335,6 +7338,7 @@ mod tests {
         assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
     }
 
+    #[simd_test(enable = "avx512f")]
     unsafe fn test_mm512_cmpneq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
@@ -9685,7 +9689,7 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test(enable = "avx512f")]
+    #[simd_test(enable = "avx512f,avx512vl")]
     unsafe fn test_mm256_maskz_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);

From 2a98dca7905eaf3e5c70f13e7ba3506ae13f92f9 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 17 Nov 2025 16:01:02 +0100
Subject: [PATCH 025/326] correct signedness of pmadd arguments

---
 crates/core_arch/src/x86/avx2.rs     | 4 ++--
 crates/core_arch/src/x86/avx512bw.rs | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index e8213615a2..8be302cabc 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -1773,7 +1773,7 @@ pub fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaddubsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_maddubs_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(pmaddubsw(a.as_u8x32(), b.as_u8x32())) }
+    unsafe { transmute(pmaddubsw(a.as_u8x32(), b.as_i8x32())) }
 }
 
 /// Loads packed 32-bit integers from memory pointed by `mem_addr` using `mask`
@@ -3702,7 +3702,7 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx2.phsub.sw"]
     fn phsubsw(a: i16x16, b: i16x16) -> i16x16;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
-    fn pmaddubsw(a: u8x32, b: u8x32) -> i16x16;
+    fn pmaddubsw(a: u8x32, b: i8x32) -> i16x16;
     #[link_name = "llvm.x86.avx2.mpsadbw"]
     fn mpsadbw(a: u8x32, b: u8x32, imm8: i8) -> u16x16;
     #[link_name = "llvm.x86.avx2.pmul.hr.sw"]
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index aee705fb46..0e2dd3ad40 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -5955,7 +5955,7 @@ pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddubsw))]
 pub fn _mm512_maddubs_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpmaddubsw(a.as_i8x64(), b.as_i8x64())) }
+    unsafe { transmute(vpmaddubsw(a.as_u8x64(), b.as_i8x64())) }
 }
 
 /// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -11688,7 +11688,7 @@ unsafe extern "C" {
     fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32;
 
     #[link_name = "llvm.x86.avx512.pmaddubs.w.512"]
-    fn vpmaddubsw(a: i8x64, b: i8x64) -> i16x32;
+    fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32;
 
     #[link_name = "llvm.x86.avx512.packssdw.512"]
     fn vpackssdw(a: i32x16, b: i32x16) -> i16x32;

From 5b1fda15f148337f62d5c3b68b369f50a9184f91 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Fri, 24 Oct 2025 10:15:01 +0100
Subject: [PATCH 026/326] Fixes generator, neon intrinics now build in debug

This fixes build issues associated with failing LLVM const param assertions
---
 .../src/arm_shared/neon/generated.rs          | 1128 ++++++-----------
 .../spec/neon/arm_shared.spec.yml             |  335 ++---
 crates/stdarch-gen-arm/src/expression.rs      |   17 +
 crates/stdarch-gen-arm/src/intrinsic.rs       |    3 +-
 4 files changed, 565 insertions(+), 918 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index b5ba792b18..c1bd70175c 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -15137,268 +15137,104 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
 pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
-    transmute(vld1_v2f32(
-        ptr as *const i8,
-        crate::mem::align_of::<f32>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
-pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
-    let ret_val: float32x2_t = transmute(vld1_v2f32(
-        ptr as *const i8,
-        crate::mem::align_of::<f32>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<f32>() as i32;
+    transmute(vld1_v2f32::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
 pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
-    transmute(vld1q_v4f32(
-        ptr as *const i8,
-        crate::mem::align_of::<f32>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
-pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
-    let ret_val: float32x4_t = transmute(vld1q_v4f32(
-        ptr as *const i8,
-        crate::mem::align_of::<f32>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
-pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
-    transmute(vld1_v8i8(
-        ptr as *const i8,
-        crate::mem::align_of::<u8>() as i32,
-    ))
+    const ALIGN: i32 = crate::mem::align_of::<f32>() as i32;
+    transmute(vld1q_v4f32::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
 pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
-    let ret_val: uint8x8_t = transmute(vld1_v8i8(
-        ptr as *const i8,
-        crate::mem::align_of::<u8>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<u8>() as i32;
+    transmute(vld1_v8i8::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
 pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
-    transmute(vld1q_v16i8(
-        ptr as *const i8,
-        crate::mem::align_of::<u8>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
-pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
-    let ret_val: uint8x16_t = transmute(vld1q_v16i8(
-        ptr as *const i8,
-        crate::mem::align_of::<u8>() as i32,
-    ));
-    simd_shuffle!(
-        ret_val,
-        ret_val,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    )
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
-pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
-    transmute(vld1_v4i16(
-        ptr as *const i8,
-        crate::mem::align_of::<u16>() as i32,
-    ))
+    const ALIGN: i32 = crate::mem::align_of::<u8>() as i32;
+    transmute(vld1q_v16i8::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
 pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
-    let ret_val: uint16x4_t = transmute(vld1_v4i16(
-        ptr as *const i8,
-        crate::mem::align_of::<u16>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<u16>() as i32;
+    transmute(vld1_v4i16::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
 pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
-    transmute(vld1q_v8i16(
-        ptr as *const i8,
-        crate::mem::align_of::<u16>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
-pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
-    let ret_val: uint16x8_t = transmute(vld1q_v8i16(
-        ptr as *const i8,
-        crate::mem::align_of::<u16>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
-pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
-    transmute(vld1_v2i32(
-        ptr as *const i8,
-        crate::mem::align_of::<u32>() as i32,
-    ))
+    const ALIGN: i32 = crate::mem::align_of::<u16>() as i32;
+    transmute(vld1q_v8i16::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
 pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
-    let ret_val: uint32x2_t = transmute(vld1_v2i32(
-        ptr as *const i8,
-        crate::mem::align_of::<u32>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<u32>() as i32;
+    transmute(vld1_v2i32::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
 pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
-    transmute(vld1q_v4i32(
-        ptr as *const i8,
-        crate::mem::align_of::<u32>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
-pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
-    let ret_val: uint32x4_t = transmute(vld1q_v4i32(
-        ptr as *const i8,
-        crate::mem::align_of::<u32>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<u32>() as i32;
+    transmute(vld1q_v4i32::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
@@ -15410,212 +15246,86 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
 pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
-    transmute(vld1_v1i64(
-        ptr as *const i8,
-        crate::mem::align_of::<u64>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
-pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
-    transmute(vld1q_v2i64(
-        ptr as *const i8,
-        crate::mem::align_of::<u64>() as i32,
-    ))
+    const ALIGN: i32 = crate::mem::align_of::<u64>() as i32;
+    transmute(vld1_v1i64::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
 pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
-    let ret_val: uint64x2_t = transmute(vld1q_v2i64(
-        ptr as *const i8,
-        crate::mem::align_of::<u64>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<u64>() as i32;
+    transmute(vld1q_v2i64::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
 pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
-    transmute(vld1_v8i8(
-        ptr as *const i8,
-        crate::mem::align_of::<p8>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
-pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
-    let ret_val: poly8x8_t = transmute(vld1_v8i8(
-        ptr as *const i8,
-        crate::mem::align_of::<p8>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
-pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
-    transmute(vld1q_v16i8(
-        ptr as *const i8,
-        crate::mem::align_of::<p8>() as i32,
-    ))
+    const ALIGN: i32 = crate::mem::align_of::<p8>() as i32;
+    transmute(vld1_v8i8::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
 pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
-    let ret_val: poly8x16_t = transmute(vld1q_v16i8(
-        ptr as *const i8,
-        crate::mem::align_of::<p8>() as i32,
-    ));
-    simd_shuffle!(
-        ret_val,
-        ret_val,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p8>() as i32;
+    transmute(vld1q_v16i8::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
 pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
-    transmute(vld1_v4i16(
-        ptr as *const i8,
-        crate::mem::align_of::<p16>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
-pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
-    let ret_val: poly16x4_t = transmute(vld1_v4i16(
-        ptr as *const i8,
-        crate::mem::align_of::<p16>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
-pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
-    transmute(vld1q_v8i16(
-        ptr as *const i8,
-        crate::mem::align_of::<p16>() as i32,
-    ))
+    const ALIGN: i32 = crate::mem::align_of::<p16>() as i32;
+    transmute(vld1_v4i16::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
 pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
-    let ret_val: poly16x8_t = transmute(vld1q_v8i16(
-        ptr as *const i8,
-        crate::mem::align_of::<p16>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<p16>() as i32;
+    transmute(vld1q_v8i16::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
 pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
-    transmute(vld1q_v2i64(
-        ptr as *const i8,
-        crate::mem::align_of::<p64>() as i32,
-    ))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,aes")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
-pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
-    let ret_val: poly64x2_t = transmute(vld1q_v2i64(
-        ptr as *const i8,
-        crate::mem::align_of::<p64>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [1, 0])
+    const ALIGN: i32 = crate::mem::align_of::<p64>() as i32;
+    transmute(vld1q_v2i64::<ALIGN>(ptr as *const i8))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
@@ -16694,7 +16404,8 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
 pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
-    vld1_v8i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i8>() as i32;
+    vld1_v8i8::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
@@ -16706,7 +16417,8 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
 pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
-    vld1q_v16i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i8>() as i32;
+    vld1q_v16i8::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
@@ -16718,7 +16430,8 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
 pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
-    vld1_v4i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i16>() as i32;
+    vld1_v4i16::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
@@ -16730,7 +16443,8 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
 pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
-    vld1q_v8i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i16>() as i32;
+    vld1q_v8i16::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
@@ -16742,7 +16456,8 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
 pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
-    vld1_v2i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i32>() as i32;
+    vld1_v2i32::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
@@ -16754,7 +16469,8 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
 pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
-    vld1q_v4i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i32>() as i32;
+    vld1q_v4i32::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
@@ -16766,7 +16482,8 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
 pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
-    vld1_v1i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i64>() as i32;
+    vld1_v1i64::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
@@ -16778,7 +16495,8 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
 pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
-    vld1q_v2i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i64>() as i32;
+    vld1q_v2i64::<ALIGN>(ptr as *const i8)
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
@@ -19417,160 +19135,136 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
     ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
     ret_val
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v1i64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1_v1i64(a: *const i8, b: i32) -> int64x1_t {
+unsafe fn vld1_v1i64<const ALIGN: i32>(a: *const i8) -> int64x1_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
         fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
     }
-    _vld1_v1i64(a, b)
+    _vld1_v1i64(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1_v2f32(a: *const i8, b: i32) -> float32x2_t {
+unsafe fn vld1_v2f32<const ALIGN: i32>(a: *const i8) -> float32x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")]
         fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t;
     }
-    _vld1_v2f32(a, b)
+    _vld1_v2f32(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2i32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1_v2i32(a: *const i8, b: i32) -> int32x2_t {
+unsafe fn vld1_v2i32<const ALIGN: i32>(a: *const i8) -> int32x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")]
         fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t;
     }
-    _vld1_v2i32(a, b)
+    _vld1_v2i32(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4i16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1_v4i16(a: *const i8, b: i32) -> int16x4_t {
+unsafe fn vld1_v4i16<const ALIGN: i32>(a: *const i8) -> int16x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")]
         fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t;
     }
-    _vld1_v4i16(a, b)
+    _vld1_v4i16(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v8i8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1_v8i8(a: *const i8, b: i32) -> int8x8_t {
+unsafe fn vld1_v8i8<const ALIGN: i32>(a: *const i8) -> int8x8_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")]
         fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t;
     }
-    _vld1_v8i8(a, b)
+    _vld1_v8i8(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v16i8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t {
+unsafe fn vld1q_v16i8<const ALIGN: i32>(a: *const i8) -> int8x16_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")]
         fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t;
     }
-    _vld1q_v16i8(a, b)
+    _vld1q_v16i8(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v2i64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t {
+unsafe fn vld1q_v2i64<const ALIGN: i32>(a: *const i8) -> int64x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")]
         fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t;
     }
-    _vld1q_v2i64(a, b)
+    _vld1q_v2i64(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t {
+unsafe fn vld1q_v4f32<const ALIGN: i32>(a: *const i8) -> float32x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")]
         fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t;
     }
-    _vld1q_v4f32(a, b)
+    _vld1q_v4f32(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4i32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t {
+unsafe fn vld1q_v4i32<const ALIGN: i32>(a: *const i8) -> int32x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")]
         fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t;
     }
-    _vld1q_v4i32(a, b)
+    _vld1q_v4i32(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8i16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-unsafe fn vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t {
+unsafe fn vld1q_v8i16<const ALIGN: i32>(a: *const i8) -> int16x8_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")]
         fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t;
     }
-    _vld1q_v8i16(a, b)
+    _vld1q_v8i16(a, ALIGN)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19585,10 +19279,6 @@ unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
     }
     _vld1_v4f16(a, b)
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -61060,117 +60750,229 @@ pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
     }
     unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
 }
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
+        fn _vshiftlins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
+    }
+    unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
+        fn _vshiftlins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
+    }
+    unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
+        fn _vshiftlins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
+    }
+    unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
+        fn _vshiftlins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
+    }
+    unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
+        fn _vshiftlins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
+    }
+    unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
+        fn _vshiftlins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
+    }
+    unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
+        fn _vshiftlins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
+    }
+    unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) }
+}
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg(target_arch = "arm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[rustc_legacy_const_generics(2)]
+fn vshiftlins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
+        fn _vshiftlins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
+    }
+    unsafe { _vshiftlins_v8i8(a, b, const { int8x8_t([N as i8; 8]) }) }
+}
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
-        fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
+        fn _vshiftrins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
     }
-    unsafe { _vshiftins_v16i8(a, b, c) }
+    unsafe { _vshiftrins_v16i8(a, b, const { int8x16_t([-N as i8; 16]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
-        fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
+        fn _vshiftrins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
     }
-    unsafe { _vshiftins_v1i64(a, b, c) }
+    unsafe { _vshiftrins_v1i64(a, b, const { int64x1_t([-N as i64; 1]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
-        fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
+        fn _vshiftrins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
     }
-    unsafe { _vshiftins_v2i32(a, b, c) }
+    unsafe { _vshiftrins_v2i32(a, b, const { int32x2_t([-N; 2]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
-        fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
+        fn _vshiftrins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
     }
-    unsafe { _vshiftins_v2i64(a, b, c) }
+    unsafe { _vshiftrins_v2i64(a, b, const { int64x2_t([-N as i64; 2]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
-        fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
+        fn _vshiftrins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
     }
-    unsafe { _vshiftins_v4i16(a, b, c) }
+    unsafe { _vshiftrins_v4i16(a, b, const { int16x4_t([-N as i16; 4]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
-        fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
+        fn _vshiftrins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
     }
-    unsafe { _vshiftins_v4i32(a, b, c) }
+    unsafe { _vshiftrins_v4i32(a, b, const { int32x4_t([-N; 4]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
-        fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
+        fn _vshiftrins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
     }
-    unsafe { _vshiftins_v8i16(a, b, c) }
+    unsafe { _vshiftrins_v8i16(a, b, const { int16x8_t([-N as i16; 8]) }) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
+#[rustc_legacy_const_generics(2)]
+fn vshiftrins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
-        fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
+        fn _vshiftrins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
     }
-    unsafe { _vshiftins_v8i8(a, b, c) }
+    unsafe { _vshiftrins_v8i8(a, b, const { int8x8_t([-N as i8; 8]) }) }
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
@@ -62706,7 +62508,7 @@ pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     static_assert_uimm_bits!(N, 3);
-    vshiftins_v8i8(a, b, int8x8_t::splat(N as i8))
+    vshiftlins_v8i8::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
@@ -62718,7 +62520,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     static_assert_uimm_bits!(N, 3);
-    vshiftins_v16i8(a, b, int8x16_t::splat(N as i8))
+    vshiftlins_v16i8::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
@@ -62730,7 +62532,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(N, 4);
-    vshiftins_v4i16(a, b, int16x4_t::splat(N as i16))
+    vshiftlins_v4i16::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
@@ -62742,7 +62544,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(N, 4);
-    vshiftins_v8i16(a, b, int16x8_t::splat(N as i16))
+    vshiftlins_v8i16::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
@@ -62754,7 +62556,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert!(N >= 0 && N <= 31);
-    vshiftins_v2i32(a, b, int32x2_t::splat(N))
+    vshiftlins_v2i32::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
@@ -62766,7 +62568,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert!(N >= 0 && N <= 31);
-    vshiftins_v4i32(a, b, int32x4_t::splat(N))
+    vshiftlins_v4i32::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
@@ -62778,7 +62580,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     static_assert!(N >= 0 && N <= 63);
-    vshiftins_v1i64(a, b, int64x1_t::splat(N as i64))
+    vshiftlins_v1i64::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
@@ -62790,7 +62592,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     static_assert!(N >= 0 && N <= 63);
-    vshiftins_v2i64(a, b, int64x2_t::splat(N as i64))
+    vshiftlins_v2i64::<N>(a, b)
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
@@ -62802,13 +62604,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        transmute(vshiftins_v8i8(
-            transmute(a),
-            transmute(b),
-            int8x8_t::splat(N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v8i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
@@ -62820,13 +62616,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        transmute(vshiftins_v16i8(
-            transmute(a),
-            transmute(b),
-            int8x16_t::splat(N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v16i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
@@ -62838,13 +62628,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        transmute(vshiftins_v4i16(
-            transmute(a),
-            transmute(b),
-            int16x4_t::splat(N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v4i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
@@ -62856,13 +62640,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        transmute(vshiftins_v8i16(
-            transmute(a),
-            transmute(b),
-            int16x8_t::splat(N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v8i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
@@ -62874,13 +62652,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     static_assert!(N >= 0 && N <= 31);
-    unsafe {
-        transmute(vshiftins_v2i32(
-            transmute(a),
-            transmute(b),
-            int32x2_t::splat(N),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v2i32::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
@@ -62892,13 +62664,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     static_assert!(N >= 0 && N <= 31);
-    unsafe {
-        transmute(vshiftins_v4i32(
-            transmute(a),
-            transmute(b),
-            int32x4_t::splat(N),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v4i32::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
@@ -62910,13 +62676,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
     static_assert!(N >= 0 && N <= 63);
-    unsafe {
-        transmute(vshiftins_v1i64(
-            transmute(a),
-            transmute(b),
-            int64x1_t::splat(N as i64),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v1i64::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
@@ -62928,13 +62688,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     static_assert!(N >= 0 && N <= 63);
-    unsafe {
-        transmute(vshiftins_v2i64(
-            transmute(a),
-            transmute(b),
-            int64x2_t::splat(N as i64),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v2i64::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
@@ -62946,13 +62700,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        transmute(vshiftins_v8i8(
-            transmute(a),
-            transmute(b),
-            int8x8_t::splat(N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v8i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
@@ -62964,13 +62712,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        transmute(vshiftins_v16i8(
-            transmute(a),
-            transmute(b),
-            int8x16_t::splat(N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v16i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
@@ -62982,13 +62724,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        transmute(vshiftins_v4i16(
-            transmute(a),
-            transmute(b),
-            int16x4_t::splat(N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v4i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
@@ -63000,13 +62736,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        transmute(vshiftins_v8i16(
-            transmute(a),
-            transmute(b),
-            int16x8_t::splat(N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftlins_v8i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
@@ -63386,7 +63116,7 @@ pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     static_assert!(1 <= N && N <= 8);
-    vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8))
+    vshiftrins_v8i8::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
@@ -63398,7 +63128,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     static_assert!(1 <= N && N <= 8);
-    vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8))
+    vshiftrins_v16i8::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
@@ -63410,7 +63140,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert!(1 <= N && N <= 16);
-    vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16))
+    vshiftrins_v4i16::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
@@ -63422,7 +63152,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert!(1 <= N && N <= 16);
-    vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16))
+    vshiftrins_v8i16::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
@@ -63434,7 +63164,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert!(1 <= N && N <= 32);
-    vshiftins_v2i32(a, b, int32x2_t::splat(-N))
+    vshiftrins_v2i32::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
@@ -63446,7 +63176,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert!(1 <= N && N <= 32);
-    vshiftins_v4i32(a, b, int32x4_t::splat(-N))
+    vshiftrins_v4i32::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
@@ -63458,7 +63188,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     static_assert!(1 <= N && N <= 64);
-    vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64))
+    vshiftrins_v1i64::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
@@ -63470,7 +63200,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     static_assert!(1 <= N && N <= 64);
-    vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64))
+    vshiftrins_v2i64::<N>(a, b)
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
@@ -63482,13 +63212,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     static_assert!(1 <= N && N <= 8);
-    unsafe {
-        transmute(vshiftins_v8i8(
-            transmute(a),
-            transmute(b),
-            int8x8_t::splat(-N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v8i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
@@ -63500,13 +63224,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     static_assert!(1 <= N && N <= 8);
-    unsafe {
-        transmute(vshiftins_v16i8(
-            transmute(a),
-            transmute(b),
-            int8x16_t::splat(-N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v16i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
@@ -63518,13 +63236,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     static_assert!(1 <= N && N <= 16);
-    unsafe {
-        transmute(vshiftins_v4i16(
-            transmute(a),
-            transmute(b),
-            int16x4_t::splat(-N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v4i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
@@ -63536,13 +63248,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     static_assert!(1 <= N && N <= 16);
-    unsafe {
-        transmute(vshiftins_v8i16(
-            transmute(a),
-            transmute(b),
-            int16x8_t::splat(-N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v8i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
@@ -63554,13 +63260,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     static_assert!(1 <= N && N <= 32);
-    unsafe {
-        transmute(vshiftins_v2i32(
-            transmute(a),
-            transmute(b),
-            int32x2_t::splat(-N),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v2i32::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
@@ -63572,13 +63272,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     static_assert!(1 <= N && N <= 32);
-    unsafe {
-        transmute(vshiftins_v4i32(
-            transmute(a),
-            transmute(b),
-            int32x4_t::splat(-N),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v4i32::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
@@ -63590,13 +63284,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
     static_assert!(1 <= N && N <= 64);
-    unsafe {
-        transmute(vshiftins_v1i64(
-            transmute(a),
-            transmute(b),
-            int64x1_t::splat(-N as i64),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v1i64::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
@@ -63608,13 +63296,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     static_assert!(1 <= N && N <= 64);
-    unsafe {
-        transmute(vshiftins_v2i64(
-            transmute(a),
-            transmute(b),
-            int64x2_t::splat(-N as i64),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v2i64::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
@@ -63626,13 +63308,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     static_assert!(1 <= N && N <= 8);
-    unsafe {
-        transmute(vshiftins_v8i8(
-            transmute(a),
-            transmute(b),
-            int8x8_t::splat(-N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v8i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
@@ -63644,13 +63320,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     static_assert!(1 <= N && N <= 8);
-    unsafe {
-        transmute(vshiftins_v16i8(
-            transmute(a),
-            transmute(b),
-            int8x16_t::splat(-N as i8),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v16i8::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
@@ -63662,13 +63332,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     static_assert!(1 <= N && N <= 16);
-    unsafe {
-        transmute(vshiftins_v4i16(
-            transmute(a),
-            transmute(b),
-            int16x4_t::splat(-N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v4i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
@@ -63680,13 +63344,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     static_assert!(1 <= N && N <= 16);
-    unsafe {
-        transmute(vshiftins_v8i16(
-            transmute(a),
-            transmute(b),
-            int16x8_t::splat(-N as i16),
-        ))
-    }
+    unsafe { transmute(vshiftrins_v8i16::<N>(transmute(a), transmute(b))) }
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
@@ -63987,11 +63645,8 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
 pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
-    vst1_v2f32(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<f32>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<f32>() as i32;
+    vst1_v2f32::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
@@ -64004,11 +63659,8 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
 pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
-    vst1q_v4f32(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<f32>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<f32>() as i32;
+    vst1q_v4f32::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
@@ -64021,7 +63673,8 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
 pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
-    vst1_v8i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i8>() as i32;
+    vst1_v8i8::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
@@ -64034,7 +63687,8 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
 pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
-    vst1q_v16i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i8>() as i32;
+    vst1q_v16i8::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
@@ -64047,7 +63701,8 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
-    vst1_v4i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i16>() as i32;
+    vst1_v4i16::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
@@ -64060,7 +63715,8 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
-    vst1q_v8i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i16>() as i32;
+    vst1q_v8i16::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
@@ -64073,7 +63729,8 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
 pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
-    vst1_v2i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i32>() as i32;
+    vst1_v2i32::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
@@ -64086,7 +63743,8 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
 pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
-    vst1q_v4i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i32>() as i32;
+    vst1q_v4i32::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
@@ -64099,7 +63757,8 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
 pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
-    vst1_v1i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i64>() as i32;
+    vst1_v1i64::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
@@ -64112,7 +63771,8 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
 pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
-    vst1q_v2i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
+    const ALIGN: i32 = crate::mem::align_of::<i64>() as i32;
+    vst1q_v2i64::<ALIGN>(ptr as *const i8, a)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
@@ -64125,11 +63785,8 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
 pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
-    vst1_v8i8(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u8>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u8>() as i32;
+    vst1_v8i8::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
@@ -64142,11 +63799,8 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
 pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
-    vst1q_v16i8(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u8>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u8>() as i32;
+    vst1q_v16i8::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
@@ -64159,11 +63813,8 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
-    vst1_v4i16(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u16>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u16>() as i32;
+    vst1_v4i16::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
@@ -64176,11 +63827,8 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
-    vst1q_v8i16(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u16>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u16>() as i32;
+    vst1q_v8i16::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
@@ -64193,11 +63841,8 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
 pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
-    vst1_v2i32(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u32>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u32>() as i32;
+    vst1_v2i32::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
@@ -64210,11 +63855,8 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
 pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
-    vst1q_v4i32(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u32>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u32>() as i32;
+    vst1q_v4i32::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
@@ -64227,11 +63869,8 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
 pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
-    vst1_v1i64(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u64>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u64>() as i32;
+    vst1_v1i64::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
@@ -64244,11 +63883,8 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
 pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
-    vst1q_v2i64(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<u64>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<u64>() as i32;
+    vst1q_v2i64::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
@@ -64261,11 +63897,8 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
 pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
-    vst1_v8i8(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<p8>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p8>() as i32;
+    vst1_v8i8::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
@@ -64278,11 +63911,8 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
 pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
-    vst1q_v16i8(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<p8>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p8>() as i32;
+    vst1q_v16i8::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
@@ -64295,11 +63925,8 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
-    vst1_v4i16(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<p16>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p16>() as i32;
+    vst1_v4i16::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
@@ -64312,11 +63939,8 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
-    vst1q_v8i16(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<p16>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p16>() as i32;
+    vst1q_v8i16::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
@@ -64329,11 +63953,8 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
 pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
-    vst1_v1i64(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<p64>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p64>() as i32;
+    vst1_v1i64::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
@@ -64346,11 +63967,8 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
 pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
-    vst1q_v2i64(
-        ptr as *const i8,
-        transmute(a),
-        crate::mem::align_of::<p64>() as i32,
-    )
+    const ALIGN: i32 = crate::mem::align_of::<p64>() as i32;
+    vst1q_v2i64::<ALIGN>(ptr as *const i8, transmute(a))
 }
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
@@ -66973,175 +66591,145 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
     vst1q_s16_x4(transmute(a), transmute(b))
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v1i64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
-unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1_v1i64<const ALIGN: i32>(addr: *const i8, val: int64x1_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v1i64.p0")]
         fn _vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32);
     }
-    _vst1_v1i64(addr, val, align)
+    _vst1_v1i64(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
-unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1_v2f32<const ALIGN: i32>(addr: *const i8, val: float32x2_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2f32.p0")]
         fn _vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32);
     }
-    _vst1_v2f32(addr, val, align)
+    _vst1_v2f32(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2i32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
-unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1_v2i32<const ALIGN: i32>(addr: *const i8, val: int32x2_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i32.p0")]
         fn _vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32);
     }
-    _vst1_v2i32(addr, val, align)
+    _vst1_v2i32(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4i16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
-unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1_v4i16<const ALIGN: i32>(addr: *const i8, val: int16x4_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i16.p0")]
         fn _vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32);
     }
-    _vst1_v4i16(addr, val, align)
+    _vst1_v4i16(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v8i8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
-unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1_v8i8<const ALIGN: i32>(addr: *const i8, val: int8x8_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i8.p0")]
         fn _vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32);
     }
-    _vst1_v8i8(addr, val, align)
+    _vst1_v8i8(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v16i8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
-unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1q_v16i8<const ALIGN: i32>(addr: *const i8, val: int8x16_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v16i8.p0")]
         fn _vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32);
     }
-    _vst1q_v16i8(addr, val, align)
+    _vst1q_v16i8(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v2i64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
-unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1q_v2i64<const ALIGN: i32>(addr: *const i8, val: int64x2_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i64.p0")]
         fn _vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32);
     }
-    _vst1q_v2i64(addr, val, align)
+    _vst1q_v2i64(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
-unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1q_v4f32<const ALIGN: i32>(addr: *const i8, val: float32x4_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f32.p0")]
         fn _vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32);
     }
-    _vst1q_v4f32(addr, val, align)
+    _vst1q_v4f32(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4i32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
-unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1q_v4i32<const ALIGN: i32>(addr: *const i8, val: int32x4_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i32.p0")]
         fn _vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32);
     }
-    _vst1q_v4i32(addr, val, align)
+    _vst1q_v4i32(addr, val, ALIGN)
 }
-#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8i16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
-unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32) {
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16", ALIGN = 0))]
+#[rustc_legacy_const_generics(2)]
+unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i16.p0")]
         fn _vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32);
     }
-    _vst1q_v8i16(addr, val, align)
+    _vst1q_v8i16(addr, val, ALIGN)
 }
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 43dd3b9031..4816d17bd6 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -11787,39 +11787,39 @@ intrinsics:
 
   - name: "vld1{type[0]}"
     visibility: private
-    doc: "Load multiple single-element structures to one, two, three, or four registers"
-    arguments: ["a: {type[1]}", "b: {type[2]}"]
-    return_type: "{neon_type[3]}"
+    arguments: ["a: {type[1]}"]
+    static_defs: ["const ALIGN: i32"]
+    return_type: "{neon_type[2]}"
     attr:
+      - FnCall: [rustc_legacy_const_generics, ['1']]
       - *target-is-arm
       - *enable-v7
-      # - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vld1.8"', "ALIGN = 0"]]}]]
       - *neon-arm-unstable
     safety:
       unsafe: [neon]
     types:
-      - ["_v8i8", "*const i8", "i32", "int8x8_t"]
-      - ["q_v16i8", "*const i8", "i32", "int8x16_t"]
-      - ["_v4i16", "*const i8", "i32", "int16x4_t"]
-      - ["q_v8i16", "*const i8", "i32", "int16x8_t"]
-      - ["_v2i32", "*const i8", "i32", "int32x2_t"]
-      - ["q_v4i32", "*const i8", "i32", "int32x4_t"]
-      - ["_v1i64", "*const i8", "i32", "int64x1_t"]
-      - ["q_v2i64", "*const i8", "i32", "int64x2_t"]
-      - ["_v2f32", "*const i8", "i32", "float32x2_t"]
-      - ["q_v4f32", "*const i8", "i32", "float32x4_t"]
+      - ["_v8i8",   "*const i8", "int8x8_t"   ]
+      - ["q_v16i8", "*const i8", "int8x16_t"  ]
+      - ["_v4i16",  "*const i8", "int16x4_t"  ]
+      - ["q_v8i16", "*const i8", "int16x8_t"  ]
+      - ["_v2i32",  "*const i8", "int32x2_t"  ]
+      - ["q_v4i32", "*const i8", "int32x4_t"  ]
+      - ["_v1i64",  "*const i8", "int64x1_t"  ]
+      - ["q_v2i64", "*const i8", "int64x2_t"  ]
+      - ["_v2f32",  "*const i8", "float32x2_t"]
+      - ["q_v4f32", "*const i8", "float32x4_t"]
     compose:
       - LLVMLink:
           name: "vld1.{type[0]}"
+          arguments: ["a: {type[1]}", "b: i32"]
           links:
-            - link: "llvm.arm.neon.vld1.{neon_type[3]}"
+            - link: "llvm.arm.neon.vld1.{neon_type[2]}"
               arch: arm
-      - FnCall: ["_vld1{type[0]}", [a, b]]
-
+      - FnCall: ["_vld1{type[0]}", [a, ALIGN]]
 
   - name: "vld1{type[0]}"
     visibility: private
-    doc: "Load multiple single-element structures to one, two, three, or four registers"
     arguments: ["a: {type[1]}", "b: {type[2]}"]
     return_type: "{neon_type[3]}"
     attr:
@@ -11855,19 +11855,23 @@ intrinsics:
       - *neon-arm-unstable
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['{type[2]}']]}]]
     types:
-      - ['*const i8',  int8x8_t,  '"vld1.8"', 'crate::mem::align_of::<i8>() as i32', '_v8i8']
-      - ['*const i8',  int8x16_t, '"vld1.8"', 'crate::mem::align_of::<i8>() as i32', 'q_v16i8']
-      - ['*const i16', int16x4_t, '"vld1.16"', 'crate::mem::align_of::<i16>() as i32', '_v4i16']
-      - ['*const i16', int16x8_t, '"vld1.16"', 'crate::mem::align_of::<i16>() as i32', 'q_v8i16']
-      - ['*const i32', int32x2_t, 'vldr', 'crate::mem::align_of::<i32>() as i32', '_v2i32']
-      - ['*const i32', int32x4_t, '"vld1.32"', 'crate::mem::align_of::<i32>() as i32', 'q_v4i32']
-      - ['*const i64', int64x1_t, 'vldr', 'crate::mem::align_of::<i64>() as i32', '_v1i64']
-      - ['*const i64', int64x2_t, '"vld1.64"', 'crate::mem::align_of::<i64>() as i32', 'q_v2i64']
+      - ['*const i8',  int8x8_t,  '"vld1.8"',  'crate::mem::align_of::<i8>()',  '_v8i8'  ]
+      - ['*const i8',  int8x16_t, '"vld1.8"',  'crate::mem::align_of::<i8>()',  'q_v16i8']
+      - ['*const i16', int16x4_t, '"vld1.16"', 'crate::mem::align_of::<i16>()', '_v4i16' ]
+      - ['*const i16', int16x8_t, '"vld1.16"', 'crate::mem::align_of::<i16>()', 'q_v8i16']
+      - ['*const i32', int32x2_t, 'vldr',      'crate::mem::align_of::<i32>()', '_v2i32' ]
+      - ['*const i32', int32x4_t, '"vld1.32"', 'crate::mem::align_of::<i32>()', 'q_v4i32']
+      - ['*const i64', int64x1_t, 'vldr',      'crate::mem::align_of::<i64>()', '_v1i64' ]
+      - ['*const i64', int64x2_t, '"vld1.64"', 'crate::mem::align_of::<i64>()', 'q_v2i64']
     compose:
+      - Const:
+          - ALIGN
+          - "i32"
+          - "{type[3]} as i32"
       - FnCall:
           - "vld1{type[4]}"
-          - - 'ptr as *const i8'
-            - '{type[3]}'
+          - ['ptr as *const i8']
+          - ['ALIGN']
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers."
@@ -11881,28 +11885,32 @@ intrinsics:
       - *neon-arm-unstable
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['{type[2]}']]}]]
     types:
-      - ['*const u8',  uint8x8_t,   '"vld1.8"', 'neon,v7', 'crate::mem::align_of::<u8>() as i32', '_v8i8']
-      - ['*const u8',  uint8x16_t,  '"vld1.8"', 'neon,v7', 'crate::mem::align_of::<u8>() as i32', 'q_v16i8']
-      - ['*const u16', uint16x4_t,  '"vld1.16"', 'neon,v7', 'crate::mem::align_of::<u16>() as i32', '_v4i16']
-      - ['*const u16', uint16x8_t,  '"vld1.16"', 'neon,v7', 'crate::mem::align_of::<u16>() as i32', 'q_v8i16']
-      - ['*const u32', uint32x2_t,  'vldr', 'neon,v7', 'crate::mem::align_of::<u32>() as i32', '_v2i32']
-      - ['*const u32', uint32x4_t,  '"vld1.32"', 'neon,v7', 'crate::mem::align_of::<u32>() as i32', 'q_v4i32']
-      - ['*const u64', uint64x1_t,  'vldr', 'neon,v7', 'crate::mem::align_of::<u64>() as i32', '_v1i64']
-      - ['*const u64', uint64x2_t,  '"vld1.64"', 'neon,v7', 'crate::mem::align_of::<u64>() as i32', 'q_v2i64']
-      - ['*const p8',  poly8x8_t,   '"vld1.8"', 'neon,v7', 'crate::mem::align_of::<p8>() as i32', '_v8i8']
-      - ['*const p8',  poly8x16_t,  '"vld1.8"', 'neon,v7', 'crate::mem::align_of::<p8>() as i32', 'q_v16i8']
-      - ['*const p16', poly16x4_t,  '"vld1.16"', 'neon,v7', 'crate::mem::align_of::<p16>() as i32', '_v4i16']
-      - ['*const p16', poly16x8_t,  '"vld1.16"', 'neon,v7', 'crate::mem::align_of::<p16>() as i32', 'q_v8i16']
-      - ['*const p64', poly64x2_t,  '"vld1.64"', 'neon,aes', 'crate::mem::align_of::<p64>() as i32', 'q_v2i64']
-      - ['*const f32', float32x2_t, 'vldr', 'neon,v7', 'crate::mem::align_of::<f32>() as i32', '_v2f32']
-      - ['*const f32', float32x4_t, '"vld1.32"', 'neon,v7', 'crate::mem::align_of::<f32>() as i32', 'q_v4f32']
-    compose:
+      - ['*const u8',  uint8x8_t,   '"vld1.8"',  'neon,v7',  'crate::mem::align_of::<u8>()',  '_v8i8'  ]
+      - ['*const u8',  uint8x16_t,  '"vld1.8"',  'neon,v7',  'crate::mem::align_of::<u8>()',  'q_v16i8']
+      - ['*const u16', uint16x4_t,  '"vld1.16"', 'neon,v7',  'crate::mem::align_of::<u16>()', '_v4i16' ]
+      - ['*const u16', uint16x8_t,  '"vld1.16"', 'neon,v7',  'crate::mem::align_of::<u16>()', 'q_v8i16']
+      - ['*const u32', uint32x2_t,  'vldr',      'neon,v7',  'crate::mem::align_of::<u32>()', '_v2i32' ]
+      - ['*const u32', uint32x4_t,  '"vld1.32"', 'neon,v7',  'crate::mem::align_of::<u32>()', 'q_v4i32']
+      - ['*const u64', uint64x1_t,  'vldr',      'neon,v7',  'crate::mem::align_of::<u64>()', '_v1i64' ]
+      - ['*const u64', uint64x2_t,  '"vld1.64"', 'neon,v7',  'crate::mem::align_of::<u64>()', 'q_v2i64']
+      - ['*const p8',  poly8x8_t,   '"vld1.8"',  'neon,v7',  'crate::mem::align_of::<p8>()',  '_v8i8'  ]
+      - ['*const p8',  poly8x16_t,  '"vld1.8"',  'neon,v7',  'crate::mem::align_of::<p8>()',  'q_v16i8']
+      - ['*const p16', poly16x4_t,  '"vld1.16"', 'neon,v7',  'crate::mem::align_of::<p16>()', '_v4i16' ]
+      - ['*const p16', poly16x8_t,  '"vld1.16"', 'neon,v7',  'crate::mem::align_of::<p16>()', 'q_v8i16']
+      - ['*const p64', poly64x2_t,  '"vld1.64"', 'neon,aes', 'crate::mem::align_of::<p64>()', 'q_v2i64']
+      - ['*const f32', float32x2_t, 'vldr',      'neon,v7',  'crate::mem::align_of::<f32>()', '_v2f32' ]
+      - ['*const f32', float32x4_t, '"vld1.32"', 'neon,v7',  'crate::mem::align_of::<f32>()', 'q_v4f32']
+    compose:
+      - Const:
+        - ALIGN
+        - "i32"
+        - "{type[4]} as i32"
       - FnCall:
         - transmute
         - - FnCall:
               - "vld1{type[5]}"
-              - - 'ptr as *const i8'
-                - '{type[4]}'
+              - ['ptr as *const i8']
+              - ['ALIGN']
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers."
@@ -13724,32 +13732,35 @@ intrinsics:
 
   - name: "vst1{type[0]}"
     visibility: private
-    doc: "Store multiple single-element structures from one, two, three, or four registers."
-    arguments: ["addr: {type[1]}", "val: {neon_type[2]}", "align: {type[3]}"]
+    arguments: ["addr: {type[1]}", "val: {neon_type[2]}"]
+    static_defs: ["const ALIGN: i32"]
     safety:
       unsafe: [neon]
     attr:
       - *target-is-arm
       - *neon-v7
       - *neon-arm-unstable
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vst1.{type[4]}"']]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vst1.{type[3]}"', "ALIGN = 0"]]}]]
+      - FnCall: ["rustc_legacy_const_generics", ['2']]
     types:
-      - ['_v8i8', '* const i8', int8x8_t, i32, '8']
-      - ['q_v16i8', '* const i8', int8x16_t, i32, '8']
-      - ['_v4i16', '* const i8', int16x4_t, i32, '16']
-      - ['q_v8i16', '* const i8', int16x8_t, i32, '16']
-      - ['_v2i32', '* const i8', int32x2_t, i32, '32']
-      - ['q_v4i32', '* const i8', int32x4_t, i32, '32']
-      - ['_v1i64', '* const i8', int64x1_t, i32, '64']
-      - ['q_v2i64', '* const i8', int64x2_t, i32, '64']
-      - ['_v2f32', '* const i8', float32x2_t, i32, '32']
-      - ['q_v4f32', '* const i8', float32x4_t, i32, '32']
+      - ['_v8i8',   '* const i8', int8x8_t,    '8' ]
+      - ['q_v16i8', '* const i8', int8x16_t,   '8' ]
+      - ['_v4i16',  '* const i8', int16x4_t,   '16']
+      - ['q_v8i16', '* const i8', int16x8_t,   '16']
+      - ['_v2i32',  '* const i8', int32x2_t,   '32']
+      - ['q_v4i32', '* const i8', int32x4_t,   '32']
+      - ['_v1i64',  '* const i8', int64x1_t,   '64']
+      - ['q_v2i64', '* const i8', int64x2_t,   '64']
+      - ['_v2f32',  '* const i8', float32x2_t, '32']
+      - ['q_v4f32', '* const i8', float32x4_t, '32']
     compose:
       - LLVMLink:
           name: "_vst1{type[0]}"
+          arguments: ["addr: {type[1]}", "val: {neon_type[2]}", "align: i32"]
           links:
             - link: "llvm.arm.neon.vst1.{neon_type[2]}.p0"
               arch: arm
+      - FnCall: ["_vst1{type[0]}",[addr, val, ALIGN]]
 
   - name: "vst1{type[0]}"
     visibility: private
@@ -13785,37 +13796,39 @@ intrinsics:
       - *neon-arm-unstable
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vst1.{type[2]}"']]}]]
     types:
-      - ['*mut i8',  int8x8_t,   '8', 'a', 'crate::mem::align_of::<i8>() as i32', '_v8i8']
-      - ['*mut i8',  int8x16_t,  '8', 'a', 'crate::mem::align_of::<i8>() as i32', 'q_v16i8']
-      - ['*mut i16', int16x4_t, '16', 'a', 'crate::mem::align_of::<i16>() as i32', '_v4i16']
-      - ['*mut i16', int16x8_t, '16', 'a', 'crate::mem::align_of::<i16>() as i32', 'q_v8i16']
-      - ['*mut i32', int32x2_t, '32', 'a', 'crate::mem::align_of::<i32>() as i32', '_v2i32']
-      - ['*mut i32', int32x4_t, '32', 'a', 'crate::mem::align_of::<i32>() as i32', 'q_v4i32']
-      - ['*mut i64', int64x1_t, '64', 'a', 'crate::mem::align_of::<i64>() as i32', '_v1i64']
-      - ['*mut i64', int64x2_t, '64', 'a', 'crate::mem::align_of::<i64>() as i32', 'q_v2i64']
-      - ['*mut u8',  uint8x8_t,   '8', 'transmute(a)', 'crate::mem::align_of::<u8>() as i32', '_v8i8']
-      - ['*mut u8',  uint8x16_t,  '8', 'transmute(a)', 'crate::mem::align_of::<u8>() as i32', 'q_v16i8']
-      - ['*mut u16', uint16x4_t, '16', 'transmute(a)', 'crate::mem::align_of::<u16>() as i32', '_v4i16']
-      - ['*mut u16', uint16x8_t, '16', 'transmute(a)', 'crate::mem::align_of::<u16>() as i32', 'q_v8i16']
-      - ['*mut u32', uint32x2_t, '32', 'transmute(a)', 'crate::mem::align_of::<u32>() as i32', '_v2i32']
-      - ['*mut u32', uint32x4_t, '32', 'transmute(a)', 'crate::mem::align_of::<u32>() as i32', 'q_v4i32']
-      - ['*mut u64', uint64x1_t, '64', 'transmute(a)', 'crate::mem::align_of::<u64>() as i32', '_v1i64']
-      - ['*mut u64', uint64x2_t, '64', 'transmute(a)', 'crate::mem::align_of::<u64>() as i32', 'q_v2i64']
-      - ['*mut p8',  poly8x8_t,    '8', 'transmute(a)', 'crate::mem::align_of::<p8>() as i32', '_v8i8']
-      - ['*mut p8',  poly8x16_t,   '8', 'transmute(a)', 'crate::mem::align_of::<p8>() as i32', 'q_v16i8']
-      - ['*mut p16', poly16x4_t,  '16', 'transmute(a)', 'crate::mem::align_of::<p16>() as i32', '_v4i16']
-      - ['*mut p16', poly16x8_t,  '16', 'transmute(a)', 'crate::mem::align_of::<p16>() as i32', 'q_v8i16']
-      - ['*mut p64', poly64x1_t,  '64', 'transmute(a)', 'crate::mem::align_of::<p64>() as i32', '_v1i64']
-      - ['*mut p64', poly64x2_t,  '64', 'transmute(a)', 'crate::mem::align_of::<p64>() as i32', 'q_v2i64']
-      - ['*mut f32', float32x2_t, '32', 'transmute(a)', 'crate::mem::align_of::<f32>() as i32', '_v2f32']
-      - ['*mut f32', float32x4_t, '32', 'transmute(a)', 'crate::mem::align_of::<f32>() as i32', 'q_v4f32']
-    compose:
+      - ['*mut i8',  int8x8_t,    '8',  'a',            'crate::mem::align_of::<i8>()',  '_v8i8'  ]
+      - ['*mut i8',  int8x16_t,   '8',  'a',            'crate::mem::align_of::<i8>()',  'q_v16i8']
+      - ['*mut i16', int16x4_t,   '16', 'a',            'crate::mem::align_of::<i16>()', '_v4i16' ]
+      - ['*mut i16', int16x8_t,   '16', 'a',            'crate::mem::align_of::<i16>()', 'q_v8i16']
+      - ['*mut i32', int32x2_t,   '32', 'a',            'crate::mem::align_of::<i32>()', '_v2i32' ]
+      - ['*mut i32', int32x4_t,   '32', 'a',            'crate::mem::align_of::<i32>()', 'q_v4i32']
+      - ['*mut i64', int64x1_t,   '64', 'a',            'crate::mem::align_of::<i64>()', '_v1i64' ]
+      - ['*mut i64', int64x2_t,   '64', 'a',            'crate::mem::align_of::<i64>()', 'q_v2i64']
+      - ['*mut u8',  uint8x8_t,   '8',  'transmute(a)', 'crate::mem::align_of::<u8>()',  '_v8i8'  ]
+      - ['*mut u8',  uint8x16_t,  '8',  'transmute(a)', 'crate::mem::align_of::<u8>()',  'q_v16i8']
+      - ['*mut u16', uint16x4_t,  '16', 'transmute(a)', 'crate::mem::align_of::<u16>()', '_v4i16' ]
+      - ['*mut u16', uint16x8_t,  '16', 'transmute(a)', 'crate::mem::align_of::<u16>()', 'q_v8i16']
+      - ['*mut u32', uint32x2_t,  '32', 'transmute(a)', 'crate::mem::align_of::<u32>()', '_v2i32' ]
+      - ['*mut u32', uint32x4_t,  '32', 'transmute(a)', 'crate::mem::align_of::<u32>()', 'q_v4i32']
+      - ['*mut u64', uint64x1_t,  '64', 'transmute(a)', 'crate::mem::align_of::<u64>()', '_v1i64' ]
+      - ['*mut u64', uint64x2_t,  '64', 'transmute(a)', 'crate::mem::align_of::<u64>()', 'q_v2i64']
+      - ['*mut p8',  poly8x8_t,   '8',  'transmute(a)', 'crate::mem::align_of::<p8>()',  '_v8i8'  ]
+      - ['*mut p8',  poly8x16_t,  '8',  'transmute(a)', 'crate::mem::align_of::<p8>()',  'q_v16i8']
+      - ['*mut p16', poly16x4_t,  '16', 'transmute(a)', 'crate::mem::align_of::<p16>()', '_v4i16' ]
+      - ['*mut p16', poly16x8_t,  '16', 'transmute(a)', 'crate::mem::align_of::<p16>()', 'q_v8i16']
+      - ['*mut p64', poly64x1_t,  '64', 'transmute(a)', 'crate::mem::align_of::<p64>()', '_v1i64' ]
+      - ['*mut p64', poly64x2_t,  '64', 'transmute(a)', 'crate::mem::align_of::<p64>()', 'q_v2i64']
+      - ['*mut f32', float32x2_t, '32', 'transmute(a)', 'crate::mem::align_of::<f32>()', '_v2f32' ]
+      - ['*mut f32', float32x4_t, '32', 'transmute(a)', 'crate::mem::align_of::<f32>()', 'q_v4f32']
+    compose:
+      - Const:
+          - ALIGN
+          - "i32"
+          - "{type[4]} as i32"
       - FnCall:
           - "vst1{type[5]}"
-          - - 'ptr as *const i8'
-            - '{type[3]}'
-            - '{type[4]}'
-
+          - ['ptr as *const i8','{type[3]}']
+          - ['ALIGN']
 
   - name: "vst1{neon_type[1].no}"
     doc: "Store multiple single-element structures from one, two, three, or four registers."
@@ -13839,32 +13852,64 @@ intrinsics:
             - '{type[3]}'
             - '{type[4]}'
 
-
-  - name: "vshiftins{type[0]}"
+  - name: "vshiftlins{type[0]}"
     visibility: private
+    arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[1]}"
+    safety: safe
+    attr:
+      - *target-is-arm
+      - *neon-v7
+      - *neon-arm-unstable
+      - FnCall: [rustc_legacy_const_generics, ['2']]
+    static_defs: ['const N: i32']
+    types:
+      - ['_v8i8',  'int8x8_t',  '8',  'int8x8_t([N as i8; 8 ])' ] 
+      - ['_v16i8', 'int8x16_t', '8',  'int8x16_t([N as i8; 16])']
+      - ['_v4i16', 'int16x4_t', '16', 'int16x4_t([N as i16; 4])']
+      - ['_v8i16', 'int16x8_t', '16', 'int16x8_t([N as i16; 8])']
+      - ['_v2i32', 'int32x2_t', '32', 'int32x2_t([N; 2])'       ]
+      - ['_v4i32', 'int32x4_t', '32', 'int32x4_t([N; 4])'       ]
+      - ['_v1i64', 'int64x1_t', '64', 'int64x1_t([N as i64; 1])']
+      - ['_v2i64', 'int64x2_t', '64', 'int64x2_t([N as i64; 2])']
+    compose:
+      - LLVMLink:
+          name: "_vshiftins{type[0]}"
+          arguments: ["a: {type[1]}", "b: {type[1]}", "c: {type[1]}"]
+          links:
+            - link: "llvm.arm.neon.vshiftins.{neon_type[1]}"
+              arch: arm
+      - FnCall: ["_vshiftlins{type[0]}", [a,b, "const {{ {type[3]} }}"], [], true]
+
+  - name: "vshiftrins{type[0]}"
     doc: "Shift Right and Insert (immediate)"
-    arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
+    visibility: private
+    arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[1]}"
     safety: safe
     attr:
       - *target-is-arm
       - *neon-v7
       - *neon-arm-unstable
+      - FnCall: [rustc_legacy_const_generics, ['2']]
+    static_defs: ['const N: i32']
     types:
-      - ['_v8i8',  "int8x8_t", '8']
-      - ['_v16i8', 'int8x16_t', '8']
-      - ['_v4i16', 'int16x4_t', '16']
-      - ['_v8i16', 'int16x8_t', '16']
-      - ['_v2i32', 'int32x2_t', '32']
-      - ['_v4i32', 'int32x4_t', '32']
-      - ['_v1i64', 'int64x1_t', '64']
-      - ['_v2i64', 'int64x2_t', '64']
+      - ['_v8i8',  'int8x8_t',  '8',  'int8x8_t([-N as i8; 8 ])' ]
+      - ['_v16i8', 'int8x16_t', '8',  'int8x16_t([-N as i8; 16])']
+      - ['_v4i16', 'int16x4_t', '16', 'int16x4_t([-N as i16; 4])']
+      - ['_v8i16', 'int16x8_t', '16', 'int16x8_t([-N as i16; 8])']
+      - ['_v2i32', 'int32x2_t', '32', 'int32x2_t([-N; 2])'       ]
+      - ['_v4i32', 'int32x4_t', '32', 'int32x4_t([-N; 4])'       ]
+      - ['_v1i64', 'int64x1_t', '64', 'int64x1_t([-N as i64; 1])']
+      - ['_v2i64', 'int64x2_t', '64', 'int64x2_t([-N as i64; 2])']
     compose:
       - LLVMLink:
           name: "_vshiftins{type[0]}"
+          arguments: ["a: {type[1]}", "b: {type[1]}", "c: {type[1]}"]
           links:
             - link: "llvm.arm.neon.vshiftins.{neon_type[1]}"
               arch: arm
+      - FnCall: ["_vshiftrins{type[0]}", [a,b, "const {{ {type[3]} }}"], [], true]
 
   - name: "vsri{neon_type[0].N}"
     doc: "Shift Right and Insert (immediate)"
@@ -13879,18 +13924,18 @@ intrinsics:
       - FnCall: [rustc_legacy_const_generics, ['2']]
     static_defs: ['const N: i32']
     types:
-      - [uint8x8_t,  "neon,v7",  '8', '1 <= N && N <= 8',   'v8i8', 'int8x8_t::splat',  '-N as i8']
-      - [uint8x16_t, "neon,v7",  '8', '1 <= N && N <= 8',  'v16i8', 'int8x16_t::splat', '-N as i8']
-      - [uint16x4_t, "neon,v7", '16', '1 <= N && N <= 16', 'v4i16', 'int16x4_t::splat', '-N as i16']
-      - [uint16x8_t, "neon,v7", '16', '1 <= N && N <= 16', 'v8i16', 'int16x8_t::splat', '-N as i16']
-      - [uint32x2_t, "neon,v7", '32', '1 <= N && N <= 32', 'v2i32', 'int32x2_t::splat', '-N']
-      - [uint32x4_t, "neon,v7", '32', '1 <= N && N <= 32', 'v4i32', 'int32x4_t::splat', '-N']
-      - [uint64x1_t, "neon,v7", '64', '1 <= N && N <= 64', 'v1i64', 'int64x1_t::splat', '-N as i64']
-      - [uint64x2_t, "neon,v7", '64', '1 <= N && N <= 64', 'v2i64', 'int64x2_t::splat', '-N as i64']
-      - [poly8x8_t,  "neon,v7",  '8', '1 <= N && N <= 8',   'v8i8', 'int8x8_t::splat',  '-N as i8']
-      - [poly8x16_t, "neon,v7",  '8', '1 <= N && N <= 8',  'v16i8', 'int8x16_t::splat', '-N as i8']
-      - [poly16x4_t, "neon,v7", '16', '1 <= N && N <= 16', 'v4i16', 'int16x4_t::splat', '-N as i16']
-      - [poly16x8_t, "neon,v7", '16', '1 <= N && N <= 16', 'v8i16', 'int16x8_t::splat', '-N as i16']
+      - [uint8x8_t,  "neon,v7", '8',  '1 <= N && N <= 8',  'v8i8' ]
+      - [uint8x16_t, "neon,v7", '8',  '1 <= N && N <= 8',  'v16i8']
+      - [uint16x4_t, "neon,v7", '16', '1 <= N && N <= 16', 'v4i16']
+      - [uint16x8_t, "neon,v7", '16', '1 <= N && N <= 16', 'v8i16']
+      - [uint32x2_t, "neon,v7", '32', '1 <= N && N <= 32', 'v2i32']
+      - [uint32x4_t, "neon,v7", '32', '1 <= N && N <= 32', 'v4i32']
+      - [uint64x1_t, "neon,v7", '64', '1 <= N && N <= 64', 'v1i64']
+      - [uint64x2_t, "neon,v7", '64', '1 <= N && N <= 64', 'v2i64']
+      - [poly8x8_t,  "neon,v7",  '8', '1 <= N && N <= 8',  'v8i8' ]
+      - [poly8x16_t, "neon,v7",  '8', '1 <= N && N <= 8',  'v16i8']
+      - [poly16x4_t, "neon,v7", '16', '1 <= N && N <= 16', 'v4i16']
+      - [poly16x8_t, "neon,v7", '16', '1 <= N && N <= 16', 'v8i16']
       ## These live in ./crates/core_arch/src/arm/neon.rs
       #- [poly64x1_t, "neon,v7,aes", '64', '1 <= N && N <= 64', 'v1i64', 'int64x1_t::splat', '-N as i64']
       #- [poly64x2_t, "neon,v7,aes", '64', '1 <= N && N <= 64', 'v2i64', 'int64x2_t::splat', '-N as i64']
@@ -13899,10 +13944,9 @@ intrinsics:
       - FnCall:
           - 'transmute'
           - - FnCall:
-                - "vshiftins_{type[4]}"
+                - "vshiftrins_{type[4]}::<N>"
                 - - FnCall: [transmute, [a]]
                   - FnCall: [transmute, [b]]
-                  - FnCall: ["{type[5]}", ["{type[6]}"]]
 
   - name: "vsri{neon_type[0].N}"
     doc: "Shift Right and Insert (immediate)"
@@ -13917,21 +13961,20 @@ intrinsics:
       - FnCall: [rustc_legacy_const_generics, ['2']]
     safety: safe
     types:
-      - [int8x8_t,  '8',  '1 <= N && N <= 8',  'v8i8',  'int8x8_t::splat',  '-N as i8']
-      - [int8x16_t, '8',  '1 <= N && N <= 8',  'v16i8', 'int8x16_t::splat', '-N as i8']
-      - [int16x4_t, '16', '1 <= N && N <= 16', 'v4i16', 'int16x4_t::splat', '-N as i16']
-      - [int16x8_t, '16', '1 <= N && N <= 16', 'v8i16', 'int16x8_t::splat', '-N as i16']
-      - [int32x2_t, '32', '1 <= N && N <= 32', 'v2i32', 'int32x2_t::splat', '-N']
-      - [int32x4_t, '32', '1 <= N && N <= 32', 'v4i32', 'int32x4_t::splat', '-N']
-      - [int64x1_t, '64', '1 <= N && N <= 64', 'v1i64', 'int64x1_t::splat', '-N as i64']
-      - [int64x2_t, '64', '1 <= N && N <= 64', 'v2i64', 'int64x2_t::splat', '-N as i64']
+      - [int8x8_t,  '8',  '1 <= N && N <= 8',  'v8i8' ]
+      - [int8x16_t, '8',  '1 <= N && N <= 8',  'v16i8']
+      - [int16x4_t, '16', '1 <= N && N <= 16', 'v4i16']
+      - [int16x8_t, '16', '1 <= N && N <= 16', 'v8i16']
+      - [int32x2_t, '32', '1 <= N && N <= 32', 'v2i32']
+      - [int32x4_t, '32', '1 <= N && N <= 32', 'v4i32']
+      - [int64x1_t, '64', '1 <= N && N <= 64', 'v1i64']
+      - [int64x2_t, '64', '1 <= N && N <= 64', 'v2i64']
     compose:
       - FnCall: ["static_assert!", ['{type[2]}']]
       - FnCall:
-          - "vshiftins_{type[3]}"
+          - "vshiftrins_{type[3]}::<N>"
           - - a
             - b
-            - FnCall: ["{type[4]}", ["{type[5]}"]]
 
   - name: "vsli{neon_type[0].N}"
     doc: "Shift Left and Insert (immediate)"
@@ -13946,18 +13989,18 @@ intrinsics:
       - FnCall: [rustc_legacy_const_generics, ['2']]
     static_defs: ['const N: i32']
     types:
-      - [uint8x8_t,  "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',    'v8i8',  'int8x8_t::splat',  'N as i8']
-      - [uint8x16_t, "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',    'v16i8', 'int8x16_t::splat', 'N as i8']
-      - [uint16x4_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v4i16', 'int16x4_t::splat', 'N as i16']
-      - [uint16x8_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v8i16', 'int16x8_t::splat', 'N as i16']
-      - [uint32x2_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v2i32', 'int32x2_t::splat', 'N']
-      - [uint32x4_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v4i32', 'int32x4_t::splat', 'N']
-      - [uint64x1_t, "neon,v7", '64', 'static_assert!', 'N >= 0 && N <= 63', 'v1i64', 'int64x1_t::splat', 'N as i64']
-      - [uint64x2_t, "neon,v7", '64', 'static_assert!', 'N >= 0 && N <= 63', 'v2i64', 'int64x2_t::splat', 'N as i64']
-      - [poly8x8_t,  "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',     'v8i8', 'int8x8_t::splat',  'N as i8']
-      - [poly8x16_t, "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',    'v16i8', 'int8x16_t::splat', 'N as i8']
-      - [poly16x4_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v4i16', 'int16x4_t::splat', 'N as i16']
-      - [poly16x8_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v8i16', 'int16x8_t::splat', 'N as i16']
+      - [uint8x8_t,  "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',     'v8i8']
+      - [uint8x16_t, "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',    'v16i8']
+      - [uint16x4_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v4i16']
+      - [uint16x8_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v8i16']
+      - [uint32x2_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v2i32']
+      - [uint32x4_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v4i32']
+      - [uint64x1_t, "neon,v7", '64', 'static_assert!', 'N >= 0 && N <= 63', 'v1i64']
+      - [uint64x2_t, "neon,v7", '64', 'static_assert!', 'N >= 0 && N <= 63', 'v2i64']
+      - [poly8x8_t,  "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',     'v8i8']
+      - [poly8x16_t, "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',    'v16i8']
+      - [poly16x4_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v4i16']
+      - [poly16x8_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v8i16']
       ## These live in ./crates/core_arch/src/arm/neon.rs
       #- [poly64x1_t, "neon,v7,aes", '"vsli.64"', 'static_assert!', '0 <= N && N <= 63', 'v1i64', 'int64x1_t::splat', 'N as i64']
       #- [poly64x2_t, "neon,v7,aes", '"vsli.64"', 'static_assert!', '0 <= N && N <= 63', 'v2i64', 'int64x2_t::splat', 'N as i64']
@@ -13966,10 +14009,9 @@ intrinsics:
       - FnCall:
           - 'transmute'
           - - FnCall:
-                - "vshiftins_{type[5]}"
+                - "vshiftlins_{type[5]}::<N>"
                 - - FnCall: [transmute, [a]]
                   - FnCall: [transmute, [b]]
-                  - FnCall: ["{type[6]}", ["{type[7]}"]]
   
   - name: "vsli{neon_type[0].N}"
     doc: "Shift Left and Insert (immediate)"
@@ -13984,21 +14026,20 @@ intrinsics:
       - FnCall: [rustc_legacy_const_generics, ['2']]
     static_defs: ['const N: i32']
     types:
-      - [int8x8_t,  '8',  'static_assert_uimm_bits!', 'N, 3',     'v8i8', 'int8x8_t::splat',  'N as i8']
-      - [int8x16_t, '8',  'static_assert_uimm_bits!', 'N, 3',    'v16i8', 'int8x16_t::splat', 'N as i8']
-      - [int16x4_t, '16', 'static_assert_uimm_bits!', 'N, 4',    'v4i16', 'int16x4_t::splat', 'N as i16']
-      - [int16x8_t, '16', 'static_assert_uimm_bits!', 'N, 4',    'v8i16', 'int16x8_t::splat', 'N as i16']
-      - [int32x2_t, '32', 'static_assert!', 'N >= 0 && N <= 31', 'v2i32', 'int32x2_t::splat', 'N']
-      - [int32x4_t, '32', 'static_assert!', 'N >= 0 && N <= 31', 'v4i32', 'int32x4_t::splat', 'N']
-      - [int64x1_t, '64', 'static_assert!', 'N >= 0 && N <= 63', 'v1i64', 'int64x1_t::splat', 'N as i64']
-      - [int64x2_t, '64', 'static_assert!', 'N >= 0 && N <= 63', 'v2i64', 'int64x2_t::splat', 'N as i64']
+      - [int8x8_t,  '8',  'static_assert_uimm_bits!', 'N, 3',              'v8i8' ]
+      - [int8x16_t, '8',  'static_assert_uimm_bits!', 'N, 3',              'v16i8']
+      - [int16x4_t, '16', 'static_assert_uimm_bits!', 'N, 4',              'v4i16']
+      - [int16x8_t, '16', 'static_assert_uimm_bits!', 'N, 4',              'v8i16']
+      - [int32x2_t, '32', 'static_assert!',           'N >= 0 && N <= 31', 'v2i32']
+      - [int32x4_t, '32', 'static_assert!',           'N >= 0 && N <= 31', 'v4i32']
+      - [int64x1_t, '64', 'static_assert!',           'N >= 0 && N <= 63', 'v1i64']
+      - [int64x2_t, '64', 'static_assert!',           'N >= 0 && N <= 63', 'v2i64']
     compose:
       - FnCall: ["{type[2]}", ['{type[3]}']]
       - FnCall:
-          - "vshiftins_{type[4]}"
+          - "vshiftlins_{type[4]}::<N>"
           - - a
             - b
-            - FnCall: ["{type[5]}", ["{type[6]}"]]
 
   - name: "vcombine{neon_type[0].no}"
     doc: Join two smaller vectors into a single larger vector
diff --git a/crates/stdarch-gen-arm/src/expression.rs b/crates/stdarch-gen-arm/src/expression.rs
index d5644ef27d..bf48f0dab7 100644
--- a/crates/stdarch-gen-arm/src/expression.rs
+++ b/crates/stdarch-gen-arm/src/expression.rs
@@ -108,6 +108,8 @@ impl ToTokens for FnCall {
 pub enum Expression {
     /// (Re)Defines a variable
     Let(LetVariant),
+    /// Defines a const
+    Const(WildString, TypeKind, Box<Expression>),
     /// Performs a variable assignment operation
     Assign(String, Box<Expression>),
     /// Performs a macro call
@@ -169,6 +171,7 @@ impl Expression {
                 | LetVariant::WithType(_, _, ex)
                 | LetVariant::MutWithType(_, _, ex),
             ) => ex.pre_build(ctx),
+            Self::Const(_, _, ex) => ex.pre_build(ctx),
             Self::CastAs(ex, _) => ex.pre_build(ctx),
             Self::Multiply(lhs, rhs) | Self::Xor(lhs, rhs) => {
                 lhs.pre_build(ctx)?;
@@ -245,6 +248,15 @@ impl Expression {
                 );
                 ex.build(intrinsic, ctx)
             }
+            Self::Const(var_name, ty, ex) => {
+                var_name.build_acle(ctx.local)?;
+                ctx.local.variables.insert(
+                    var_name.to_string(),
+                    (ty.to_owned(), VariableType::Internal),
+                );
+                ex.build(intrinsic, ctx)
+            }
+
             Self::CastAs(ex, _) => ex.build(intrinsic, ctx),
             Self::Multiply(lhs, rhs) | Self::Xor(lhs, rhs) => {
                 lhs.build(intrinsic, ctx)?;
@@ -303,6 +315,7 @@ impl Expression {
                 | LetVariant::WithType(_, _, exp)
                 | LetVariant::MutWithType(_, _, exp),
             ) => exp.requires_unsafe_wrapper(ctx_fn),
+            Self::Const(_, _, exp) => exp.requires_unsafe_wrapper(ctx_fn),
             Self::Array(exps) => exps.iter().any(|exp| exp.requires_unsafe_wrapper(ctx_fn)),
             Self::Multiply(lhs, rhs) | Self::Xor(lhs, rhs) => {
                 lhs.requires_unsafe_wrapper(ctx_fn) || rhs.requires_unsafe_wrapper(ctx_fn)
@@ -462,6 +475,10 @@ impl ToTokens for Expression {
                 let var_ident = format_ident!("{}", var_name.to_string());
                 tokens.append_all(quote! { let mut #var_ident: #ty = #exp })
             }
+            Self::Const(var_name, ty, exp) => {
+                let var_ident = format_ident!("{}", var_name.to_string());
+                tokens.append_all(quote! { const #var_ident: #ty = #exp })
+            }
             Self::Assign(var_name, exp) => {
                 /* If we are dereferencing a variable to assign a value \
                  * the 'format_ident!' macro does not like the asterix */
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index efaa9e1418..0cdff6ff6c 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1730,7 +1730,8 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok
             "{fn_name} needs to be private, or to have documentation."
         );
         assert!(
-            !safety.has_doc_comments(),
+            !safety.has_doc_comments()
+                || matches!(intrinsic.visibility, FunctionVisibility::Private),
             "{fn_name} needs a documentation section for its safety comments."
         );
     }

From 8f9458e878ddcdfc2b7a4e737b1a08b3cb04b1b2 Mon Sep 17 00:00:00 2001
From: valadaptive <valadaptive@protonmail.com>
Date: Mon, 24 Nov 2025 14:08:15 -0500
Subject: [PATCH 027/326] Correct the docs for WASM relaxed_simd's min/max

---
 crates/core_arch/src/wasm32/relaxed_simd.rs | 24 ++++++++++++++-------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/crates/core_arch/src/wasm32/relaxed_simd.rs b/crates/core_arch/src/wasm32/relaxed_simd.rs
index a9b7e9c04d..8a9d46984d 100644
--- a/crates/core_arch/src/wasm32/relaxed_simd.rs
+++ b/crates/core_arch/src/wasm32/relaxed_simd.rs
@@ -248,8 +248,10 @@ pub fn i64x2_relaxed_laneselect(a: v128, b: v128, m: v128) -> v128 {
 #[stable(feature = "stdarch_wasm_relaxed_simd", since = "1.82.0")]
 pub use i64x2_relaxed_laneselect as u64x2_relaxed_laneselect;
 
-/// A relaxed version of `f32x4_min` which is either `f32x4_min` or
-/// `f32x4_pmin`.
+/// A relaxed version of `f32x4_min` which has implementation-specific behavior
+/// when its operands are NaN or signed zeroes. For more information, see [the
+/// WebAssembly
+/// specification](https://webassembly.github.io/spec/core/exec/numerics.html#op-frelaxed-min).
 #[inline]
 #[cfg_attr(test, assert_instr(f32x4.relaxed_min))]
 #[target_feature(enable = "relaxed-simd")]
@@ -259,8 +261,10 @@ pub fn f32x4_relaxed_min(a: v128, b: v128) -> v128 {
     unsafe { llvm_f32x4_relaxed_min(a.as_f32x4(), b.as_f32x4()).v128() }
 }
 
-/// A relaxed version of `f32x4_max` which is either `f32x4_max` or
-/// `f32x4_pmax`.
+/// A relaxed version of `f32x4_max` which has implementation-specific behavior
+/// when its operands are NaN or signed zeroes. For more information, see [the
+/// WebAssembly
+/// specification](https://webassembly.github.io/spec/core/exec/numerics.html#op-frelaxed-max).
 #[inline]
 #[cfg_attr(test, assert_instr(f32x4.relaxed_max))]
 #[target_feature(enable = "relaxed-simd")]
@@ -270,8 +274,10 @@ pub fn f32x4_relaxed_max(a: v128, b: v128) -> v128 {
     unsafe { llvm_f32x4_relaxed_max(a.as_f32x4(), b.as_f32x4()).v128() }
 }
 
-/// A relaxed version of `f64x2_min` which is either `f64x2_min` or
-/// `f64x2_pmin`.
+/// A relaxed version of `f64x2_min` which has implementation-specific behavior
+/// when its operands are NaN or signed zeroes. For more information, see [the
+/// WebAssembly
+/// specification](https://webassembly.github.io/spec/core/exec/numerics.html#op-frelaxed-min).
 #[inline]
 #[cfg_attr(test, assert_instr(f64x2.relaxed_min))]
 #[target_feature(enable = "relaxed-simd")]
@@ -281,8 +287,10 @@ pub fn f64x2_relaxed_min(a: v128, b: v128) -> v128 {
     unsafe { llvm_f64x2_relaxed_min(a.as_f64x2(), b.as_f64x2()).v128() }
 }
 
-/// A relaxed version of `f64x2_max` which is either `f64x2_max` or
-/// `f64x2_pmax`.
+/// A relaxed version of `f64x2_max` which has implementation-specific behavior
+/// when its operands are NaN or signed zeroes. For more information, see [the
+/// WebAssembly
+/// specification](https://webassembly.github.io/spec/core/exec/numerics.html#op-frelaxed-max).
 #[inline]
 #[cfg_attr(test, assert_instr(f64x2.relaxed_max))]
 #[target_feature(enable = "relaxed-simd")]

From 51f3dabce33248e6d89f8fd45447330b55fb8a3a Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Thu, 6 Nov 2025 10:01:41 +0000
Subject: [PATCH 028/326] Fixes differences found between clang & rust

The intrinsics test was flagging differences in aarch64_be between rust in debug and clang in O2.
It was found that rust was correct in debug, but incorrect in release,
and in both cases were being compared against clang in O2 which was also
incorrect.

The vdot intrinsics were fixed and are now correct in rust for both
release and debug. However the vcmla ones could not be as the issue lies
with LLVM. Both the vdot and vcmla intrinsics were added to the skiplist
as clang is still incorrect for both.
LLVM issue: https://github.com/llvm/llvm-project/issues/166190
---
 ci/intrinsic-test.sh                          |   2 +-
 .../core_arch/src/aarch64/neon/generated.rs   |  24 ++--
 .../src/arm_shared/neon/generated.rs          |  32 +++---
 crates/intrinsic-test/missing_aarch64_be.txt  | 105 ++++++++++++++++++
 .../spec/neon/aarch64.spec.yml                |  30 ++---
 .../spec/neon/arm_shared.spec.yml             |  36 +++---
 6 files changed, 171 insertions(+), 58 deletions(-)
 create mode 100644 crates/intrinsic-test/missing_aarch64_be.txt

diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index be63f0c0c6..a8f96897bc 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -56,7 +56,7 @@ case ${TARGET} in
 
     aarch64_be-unknown-linux-gnu*)
         TEST_CPPFLAGS="-fuse-ld=lld"
-        TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt
+        TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64_be.txt
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER}"
         : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}"
diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 09cf381804..ce864cc7d9 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -9500,10 +9500,10 @@ pub fn vdivh_f16(a: f16, b: f16) -> f16 {
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: int32x4_t = vreinterpretq_s32_s8(c);
     unsafe {
-        let c: int32x4_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, transmute(c))
+        vdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
@@ -9515,11 +9515,11 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: int32x4_t = vreinterpretq_s32_s8(c);
     unsafe {
-        let c: int32x4_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, transmute(c))
+        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
@@ -9531,10 +9531,10 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: uint32x4_t = vreinterpretq_u32_u8(c);
     unsafe {
-        let c: uint32x4_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, transmute(c))
+        vdot_u32(a, b, vreinterpret_u8_u32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
@@ -9546,11 +9546,11 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: uint32x4_t = vreinterpretq_u32_u8(c);
     unsafe {
-        let c: uint32x4_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, transmute(c))
+        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
     }
 }
 #[doc = "Set all vector lanes to the same value"]
@@ -28283,10 +28283,10 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: int32x4_t = vreinterpretq_s32_s8(c);
     unsafe {
-        let c: int32x4_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, transmute(c))
+        vusdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
@@ -28298,11 +28298,11 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: int32x4_t = vreinterpretq_s32_s8(c);
     unsafe {
-        let c: int32x4_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, transmute(c))
+        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Unzip vectors"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index c1bd70175c..7229f33f61 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -9201,10 +9201,10 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 )]
 pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, transmute(c))
+        vdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
@@ -9228,11 +9228,11 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 )]
 pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, transmute(c))
+        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
@@ -9256,10 +9256,10 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 )]
 pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, transmute(c))
+        vdot_u32(a, b, vreinterpret_u8_u32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
@@ -9283,11 +9283,11 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 )]
 pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, transmute(c))
+        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
     }
 }
 #[doc = "Dot product arithmetic (vector)"]
@@ -71710,10 +71710,10 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 )]
 pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, transmute(c), b)
+        vusdot_s32(a, vreinterpret_u8_u32(c), b)
     }
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
@@ -71737,11 +71737,11 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 )]
 pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, transmute(c), b)
+        vusdotq_s32(a, vreinterpretq_u8_u32(c), b)
     }
 }
 #[doc = "Table look-up"]
@@ -73630,10 +73630,10 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, transmute(c))
+        vusdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
@@ -73657,11 +73657,11 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 )]
 pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, transmute(c))
+        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
diff --git a/crates/intrinsic-test/missing_aarch64_be.txt b/crates/intrinsic-test/missing_aarch64_be.txt
new file mode 100644
index 0000000000..28e1d9203e
--- /dev/null
+++ b/crates/intrinsic-test/missing_aarch64_be.txt
@@ -0,0 +1,105 @@
+# Bad LLVM codegen for BE in O2 in clang, and release in rust (https://github.com/llvm/llvm-project/issues/166190)
+vcmla_lane_f16
+vcmla_laneq_f16
+vcmla_rot180_lane_f16
+vcmla_rot180_laneq_f16
+vcmla_rot270_lane_f16
+vcmla_rot270_laneq_f16
+vcmla_rot90_lane_f16
+vcmla_rot90_laneq_f16
+vcmlaq_lane_f16
+vcmlaq_laneq_f16
+vcmlaq_laneq_f32
+vcmlaq_rot180_lane_f16
+vcmlaq_rot180_laneq_f16
+vcmlaq_rot180_laneq_f32
+vcmlaq_rot270_lane_f16
+vcmlaq_rot270_laneq_f16
+vcmlaq_rot270_laneq_f32
+vcmlaq_rot90_lane_f16
+vcmlaq_rot90_laneq_f16
+vcmlaq_rot90_laneq_f32
+# Bad codegen for BE in O2 in clang, correct in rust. Same cause as above issue.
+vdot_lane_s32
+vdot_lane_u32
+vdot_laneq_s32
+vdot_laneq_u32
+vdotq_lane_s32
+vdotq_lane_u32
+vdotq_laneq_s32
+vdotq_laneq_u32
+vsudot_lane_s32
+vsudot_laneq_s32
+vsudotq_lane_s32
+vsudotq_laneq_s32
+vusdot_lane_s32
+vusdot_laneq_s32
+vusdotq_lane_s32
+vusdotq_laneq_s32
+
+# Below are in common to missing_aarch64.txt
+
+# Not implemented in stdarch yet
+vbfdot_f32
+vbfdot_lane_f32
+vbfdot_laneq_f32
+vbfdotq_f32
+vbfdotq_lane_f32
+vbfdotq_laneq_f32
+vbfmlalbq_f32
+vbfmlalbq_lane_f32
+vbfmlalbq_laneq_f32
+vbfmlaltq_f32
+vbfmlaltq_lane_f32
+vbfmlaltq_laneq_f32
+vbfmmlaq_f32
+
+
+# Implemented in stdarch, but missing in Clang.
+vrnd32xq_f64
+vrnd32zq_f64
+vrnd64xq_f64
+vrnd64zq_f64
+vamin_f32
+vaminq_f32
+vaminq_f64
+vamax_f32
+vamaxq_f32
+vamaxq_f64
+# LLVM select error, and missing in Clang.
+vrnd32x_f64
+vrnd32z_f64
+vrnd64x_f64
+vrnd64z_f64
+vluti2_lane_p16
+vluti2_lane_p8
+vluti2_lane_s16
+vluti2_lane_s8
+vluti2_lane_u16
+vluti2_lane_u8
+vluti2q_lane_p16
+vluti2q_lane_p8
+vluti2q_lane_s16
+vluti2q_lane_s8
+vluti2q_lane_u16
+vluti2q_lane_u8
+vluti4q_lane_f16_x2
+vluti4q_lane_p16_x2
+vluti4q_lane_p8
+vluti4q_lane_s16_x2
+vluti4q_lane_s8
+vluti4q_lane_u16_x2
+vluti4q_lane_u8
+vluti4q_laneq_f16_x2
+vluti4q_laneq_p16_x2
+vluti4q_laneq_p8
+vluti4q_laneq_s16_x2
+vluti4q_laneq_s8
+vluti4q_laneq_u16_x2
+vluti4q_laneq_u8
+
+# Broken in Clang
+vcvth_s16_f16
+# FIXME: Broken output due to missing f16 printing support in Rust
+vmulh_lane_f16
+vmulh_laneq_f16
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index fe64f9d786..48c12779a8 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5091,13 +5091,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]']
-      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]','']
+      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}]
+      - Let: [c, int32x4_t, {FnCall: ['vreinterpretq_s32_s8', [c]]}]
       - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]]
+      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
 
   - name: "vsudot{neon_type[0].laneq_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -5123,7 +5123,11 @@ intrinsics:
           - c
           - "{type[4]}"
           - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, {FnCall: [transmute, [c]]}, b]]
+      - FnCall: 
+          - "vusdot{neon_type[0].no}"
+          - - a
+            - FnCall: [transmute, [c]]
+            - b
 
   - name: "vmul{neon_type.no}"
     doc: Multiply
@@ -6580,14 +6584,14 @@ intrinsics:
       - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]']
-      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', '']
+      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -6596,7 +6600,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vdot{neon_type[0].laneq_nox}"
     doc: Dot product arithmetic (indexed)
@@ -6610,14 +6614,14 @@ intrinsics:
       - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
     safety: safe
     types:
-      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]','']
+      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -6626,7 +6630,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 4816d17bd6..bb44aab66b 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6261,19 +6261,19 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]']
-      - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]','']
+      - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
           - int32x2_t
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpret_s32_s8', [c]]
       - Let:
           - c
           - "{type[1]}"
           - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: [transmute, [c]]}]]
+      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
 
   - name: "vsudot{neon_type[0].lane_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -6290,19 +6290,23 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t]
-      - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t]
+      - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t,'']
+      - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t,'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
           - uint32x2_t
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpret_u32_u8', [c]]
       - Let:
           - c
           - "{type[4]}"
           - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, {FnCall: [transmute, [c]]}, b]]
+      - FnCall: 
+          - "vusdot{neon_type[0].no}"
+          - - a
+            - FnCall: ['vreinterpret{type[5]}_u8_u32', [c]]
+            - b
 
   - name: "vmul{neon_type[1].no}"
     doc: Multiply
@@ -7113,14 +7117,14 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]']
-      - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]','']
+      - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7129,7 +7133,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vdot{neon_type[0].lane_nox}"
     doc: Dot product arithmetic (indexed)
@@ -7146,14 +7150,14 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]','']
+      - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7162,7 +7166,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)

From f564a013ef6da9dd541406f6499b5831325cb4da Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Mon, 24 Nov 2025 14:34:03 +0000
Subject: [PATCH 029/326] Provides work-around for vreinterpret inline fail

---
 .../src/arm_shared/neon/generated.rs          | 304 +++++++++++++++++-
 .../spec/neon/arm_shared.spec.yml             |  20 +-
 2 files changed, 300 insertions(+), 24 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 7229f33f61..d45454c696 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -9183,6 +9183,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
@@ -9201,15 +9202,77 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 )]
 pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
+        let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, vreinterpret_s8_s32(c))
+        vdot_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x2_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
+#[inline]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe {
+        let c: int32x2_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vdotq_s32(a, b, transmute(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
 #[inline]
+#[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
@@ -9228,16 +9291,22 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 )]
 pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: int8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
+        let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
@@ -9256,15 +9325,48 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 )]
 pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
+        let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, vreinterpret_u8_u32(c))
+        vdot_u32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x2_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
@@ -9283,11 +9385,45 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 )]
 pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
+        let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
+        vdotq_u32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: uint8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x2_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Dot product arithmetic (vector)"]
@@ -71692,6 +71828,7 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
@@ -71710,15 +71847,77 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 )]
 pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
+        let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, vreinterpret_u8_u32(c), b)
+        vusdot_s32(a, transmute(c), b)
+    }
+}
+#[doc = "Dot product index form with signed and unsigned integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sudot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x2_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vusdot_s32(a, transmute(c), b);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product index form with signed and unsigned integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
+#[inline]
+#[cfg(target_endian = "little")]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sudot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe {
+        let c: uint32x2_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vusdotq_s32(a, transmute(c), b)
     }
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
 #[inline]
+#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
@@ -71737,11 +71936,16 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 )]
 pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: int8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, vreinterpretq_u8_u32(c), b)
+        let ret_val: int32x4_t = vusdotq_s32(a, transmute(c), b);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Table look-up"]
@@ -73612,6 +73816,7 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
@@ -73630,15 +73835,48 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
+        let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, vreinterpret_s8_s32(c))
+        vusdot_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x2_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
@@ -73657,11 +73895,45 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 )]
 pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
+        let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
+        vusdotq_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: uint8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x2_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index bb44aab66b..9ebdc4334c 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6259,6 +6259,7 @@ intrinsics:
       - *neon-unstable-i8mm
       - *neon-cfg-arm-unstable
     static_defs: ["const LANE: i32"]
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     safety: safe
     types:
       - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]','']
@@ -6268,12 +6269,12 @@ intrinsics:
       - Let:
           - c
           - int32x2_t
-          - FnCall: ['vreinterpret_s32_s8', [c]]
+          - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_s32_s8', [c]]
       - Let:
           - c
           - "{type[1]}"
           - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
+      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: [transmute, [c]]}]] #'vreinterpret{type[4]}_s8_s32'
 
   - name: "vsudot{neon_type[0].lane_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -6288,6 +6289,7 @@ intrinsics:
       - *neon-unstable-i8mm
       - *neon-cfg-arm-unstable
     static_defs: ["const LANE: i32"]
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     safety: safe
     types:
       - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t,'']
@@ -6297,7 +6299,7 @@ intrinsics:
       - Let:
           - c
           - uint32x2_t
-          - FnCall: ['vreinterpret_u32_u8', [c]]
+          - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_u32_u8', [c]]
       - Let:
           - c
           - "{type[4]}"
@@ -6305,7 +6307,7 @@ intrinsics:
       - FnCall: 
           - "vusdot{neon_type[0].no}"
           - - a
-            - FnCall: ['vreinterpret{type[5]}_u8_u32', [c]]
+            - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_u8_u32', [c]]
             - b
 
   - name: "vmul{neon_type[1].no}"
@@ -7115,6 +7117,7 @@ intrinsics:
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]]
       - *neon-cfg-arm-unstable
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     safety: safe
     types:
       - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]','']
@@ -7124,7 +7127,7 @@ intrinsics:
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: [transmute, [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7133,7 +7136,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: [transmute, [c]]
 
   - name: "vdot{neon_type[0].lane_nox}"
     doc: Dot product arithmetic (indexed)
@@ -7149,6 +7152,7 @@ intrinsics:
       - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]]
       - *neon-cfg-arm-unstable
     safety: safe
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     types:
       - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]','']
       - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
@@ -7157,7 +7161,7 @@ intrinsics:
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7166,7 +7170,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)

From 1105394c11838b229145a101434437ca5e724752 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 27 Nov 2025 22:36:54 +0100
Subject: [PATCH 030/326] s390x: use `simd_shuffle!` macro

---
 crates/core_arch/src/s390x/vector.rs | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 7208105fb8..1366b5c782 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -896,7 +896,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vrepb, IMM2 = 1))]
     unsafe fn vrepb<const IMM2: u32>(a: vector_signed_char) -> vector_signed_char {
         static_assert_uimm_bits!(IMM2, 4);
-        simd_shuffle(a, a, const { u32x16::from_array([IMM2; 16]) })
+        simd_shuffle!(a, a, [IMM2; 16])
     }
 
     #[inline]
@@ -904,7 +904,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vreph, IMM2 = 1))]
     unsafe fn vreph<const IMM2: u32>(a: vector_signed_short) -> vector_signed_short {
         static_assert_uimm_bits!(IMM2, 3);
-        simd_shuffle(a, a, const { u32x8::from_array([IMM2; 8]) })
+        simd_shuffle!(a, a, [IMM2; 8])
     }
 
     #[inline]
@@ -912,7 +912,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vrepf, IMM2 = 1))]
     unsafe fn vrepf<const IMM2: u32>(a: vector_signed_int) -> vector_signed_int {
         static_assert_uimm_bits!(IMM2, 2);
-        simd_shuffle(a, a, const { u32x4::from_array([IMM2; 4]) })
+        simd_shuffle!(a, a, [IMM2; 4])
     }
 
     #[inline]
@@ -920,7 +920,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vrepg, IMM2 = 1))]
     unsafe fn vrepg<const IMM2: u32>(a: vector_signed_long_long) -> vector_signed_long_long {
         static_assert_uimm_bits!(IMM2, 1);
-        simd_shuffle(a, a, const { u32x2::from_array([IMM2; 2]) })
+        simd_shuffle!(a, a, [IMM2; 2])
     }
 
     macro_rules! impl_vec_splat {
@@ -5307,11 +5307,13 @@ pub unsafe fn vec_search_string_until_zero_cc<T: sealed::VectorSearchString>(
 #[inline]
 #[target_feature(enable = "vector-enhancements-1")]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
-// FIXME: this emits `vflls` where `vldeb` is expected
-// #[cfg_attr(all(test, target_feature = "vector-enhancements-1"), assert_instr(vldeb))]
+// NOTE: `vflls` and `vldeb` are equivalent; our disassmbler prefers vflls.
+#[cfg_attr(
+    all(test, target_feature = "vector-enhancements-1"),
+    assert_instr(vflls)
+)]
 pub unsafe fn vec_doublee(a: vector_float) -> vector_double {
-    let even = simd_shuffle::<_, _, f32x2>(a, a, const { u32x2::from_array([0, 2]) });
-    simd_as(even)
+    simd_as::<f32x2, vector_double>(simd_shuffle!(a, a, [0, 2]))
 }
 
 /// Vector Convert from double to float (even elements)
@@ -5322,11 +5324,7 @@ pub unsafe fn vec_doublee(a: vector_float) -> vector_double {
 // #[cfg_attr(all(test, target_feature = "vector-enhancements-1"), assert_instr(vledb))]
 pub unsafe fn vec_floate(a: vector_double) -> vector_float {
     let truncated: f32x2 = simd_as(a);
-    simd_shuffle(
-        truncated,
-        truncated,
-        const { u32x4::from_array([0, 0, 1, 1]) },
-    )
+    simd_shuffle!(truncated, truncated, [0, 0, 1, 1])
 }
 
 /// Vector Convert from int to float

From c37fef23e31e33f15ad16996e9f5fe0abb4fa985 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 27 Nov 2025 07:04:37 +0530
Subject: [PATCH 031/326] Refactor max/min intrinsics using a helper function

---
 crates/core_arch/src/simd.rs         | 12 ++++
 crates/core_arch/src/x86/avx2.rs     | 72 ++++-----------------
 crates/core_arch/src/x86/avx512bw.rs | 50 +++------------
 crates/core_arch/src/x86/avx512f.rs  | 96 +++++-----------------------
 crates/core_arch/src/x86/sse2.rs     | 24 ++-----
 crates/core_arch/src/x86/sse41.rs    | 48 +++-----------
 6 files changed, 61 insertions(+), 241 deletions(-)

diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index 25834943f0..9fa8e25022 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -2,6 +2,18 @@
 
 #![allow(non_camel_case_types)]
 
+#[inline(always)]
+pub(crate) unsafe fn simd_imax<T: Copy>(a: T, b: T) -> T {
+    let mask: T = crate::intrinsics::simd::simd_gt(a, b);
+    crate::intrinsics::simd::simd_select(mask, a, b)
+}
+
+#[inline(always)]
+pub(crate) unsafe fn simd_imin<T: Copy>(a: T, b: T) -> T {
+    let mask: T = crate::intrinsics::simd::simd_lt(a, b);
+    crate::intrinsics::simd::simd_select(mask, a, b)
+}
+
 macro_rules! simd_ty {
     ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => {
         #[repr(simd)]
diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 8be302cabc..3734915b70 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -1897,11 +1897,7 @@ pub unsafe fn _mm256_maskstore_epi64(mem_addr: *mut i64, mask: __m256i, a: __m25
 #[cfg_attr(test, assert_instr(vpmaxsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_max_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i16x16();
-        let b = b.as_i16x16();
-        transmute(simd_select::<i16x16, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i16x16(), b.as_i16x16()).as_m256i() }
 }
 
 /// Compares packed 32-bit integers in `a` and `b`, and returns the packed
@@ -1913,11 +1909,7 @@ pub fn _mm256_max_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaxsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_max_epi32(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i32x8();
-        let b = b.as_i32x8();
-        transmute(simd_select::<i32x8, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i32x8(), b.as_i32x8()).as_m256i() }
 }
 
 /// Compares packed 8-bit integers in `a` and `b`, and returns the packed
@@ -1929,11 +1921,7 @@ pub fn _mm256_max_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaxsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_max_epi8(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i8x32();
-        let b = b.as_i8x32();
-        transmute(simd_select::<i8x32, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i8x32(), b.as_i8x32()).as_m256i() }
 }
 
 /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns
@@ -1945,11 +1933,7 @@ pub fn _mm256_max_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaxuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_max_epu16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u16x16();
-        let b = b.as_u16x16();
-        transmute(simd_select::<i16x16, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u16x16(), b.as_u16x16()).as_m256i() }
 }
 
 /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns
@@ -1961,11 +1945,7 @@ pub fn _mm256_max_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaxud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_max_epu32(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u32x8();
-        let b = b.as_u32x8();
-        transmute(simd_select::<i32x8, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u32x8(), b.as_u32x8()).as_m256i() }
 }
 
 /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns
@@ -1977,11 +1957,7 @@ pub fn _mm256_max_epu32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmaxub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_max_epu8(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u8x32();
-        let b = b.as_u8x32();
-        transmute(simd_select::<i8x32, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u8x32(), b.as_u8x32()).as_m256i() }
 }
 
 /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
@@ -1993,11 +1969,7 @@ pub fn _mm256_max_epu8(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpminsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_min_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i16x16();
-        let b = b.as_i16x16();
-        transmute(simd_select::<i16x16, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i16x16(), b.as_i16x16()).as_m256i() }
 }
 
 /// Compares packed 32-bit integers in `a` and `b`, and returns the packed
@@ -2009,11 +1981,7 @@ pub fn _mm256_min_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpminsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_min_epi32(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i32x8();
-        let b = b.as_i32x8();
-        transmute(simd_select::<i32x8, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i32x8(), b.as_i32x8()).as_m256i() }
 }
 
 /// Compares packed 8-bit integers in `a` and `b`, and returns the packed
@@ -2025,11 +1993,7 @@ pub fn _mm256_min_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpminsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_min_epi8(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i8x32();
-        let b = b.as_i8x32();
-        transmute(simd_select::<i8x32, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i8x32(), b.as_i8x32()).as_m256i() }
 }
 
 /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns
@@ -2041,11 +2005,7 @@ pub fn _mm256_min_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpminuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_min_epu16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u16x16();
-        let b = b.as_u16x16();
-        transmute(simd_select::<i16x16, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u16x16(), b.as_u16x16()).as_m256i() }
 }
 
 /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns
@@ -2057,11 +2017,7 @@ pub fn _mm256_min_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpminud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_min_epu32(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u32x8();
-        let b = b.as_u32x8();
-        transmute(simd_select::<i32x8, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u32x8(), b.as_u32x8()).as_m256i() }
 }
 
 /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns
@@ -2073,11 +2029,7 @@ pub fn _mm256_min_epu32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpminub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_min_epu8(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u8x32();
-        let b = b.as_u8x32();
-        transmute(simd_select::<i8x32, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u8x32(), b.as_u8x32()).as_m256i() }
 }
 
 /// Creates mask from the most significant bit of each 8-bit element in `a`,
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 0e2dd3ad40..4310c3d0ac 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -1743,11 +1743,7 @@ pub fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
 pub fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u16x32();
-        let b = b.as_u16x32();
-        transmute(simd_select::<i16x32, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u16x32(), b.as_u16x32()).as_m512i() }
 }
 
 /// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -1842,11 +1838,7 @@ pub fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
 pub fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u8x64();
-        let b = b.as_u8x64();
-        transmute(simd_select::<i8x64, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u8x64(), b.as_u8x64()).as_m512i() }
 }
 
 /// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -1941,11 +1933,7 @@ pub fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
 pub fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i16x32();
-        let b = b.as_i16x32();
-        transmute(simd_select::<i16x32, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i16x32(), b.as_i16x32()).as_m512i() }
 }
 
 /// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2040,11 +2028,7 @@ pub fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
 pub fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i8x64();
-        let b = b.as_i8x64();
-        transmute(simd_select::<i8x64, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i8x64(), b.as_i8x64()).as_m512i() }
 }
 
 /// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2139,11 +2123,7 @@ pub fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
 pub fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u16x32();
-        let b = b.as_u16x32();
-        transmute(simd_select::<i16x32, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u16x32(), b.as_u16x32()).as_m512i() }
 }
 
 /// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2238,11 +2218,7 @@ pub fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
 pub fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u8x64();
-        let b = b.as_u8x64();
-        transmute(simd_select::<i8x64, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u8x64(), b.as_u8x64()).as_m512i() }
 }
 
 /// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2337,11 +2313,7 @@ pub fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
 pub fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i16x32();
-        let b = b.as_i16x32();
-        transmute(simd_select::<i16x32, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i16x32(), b.as_i16x32()).as_m512i() }
 }
 
 /// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2436,11 +2408,7 @@ pub fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
 pub fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i8x64();
-        let b = b.as_i8x64();
-        transmute(simd_select::<i8x64, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i8x64(), b.as_i8x64()).as_m512i() }
 }
 
 /// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -21172,7 +21140,7 @@ mod tests {
         let e = _mm_set_epi8(
             0, 0, 0, 0,
             0, 0, 0, 0,
-            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, 
+            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
             u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
         );
         assert_eq_m128i(r, e);
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index f7bf9178db..8c57fc2011 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -2091,11 +2091,7 @@ pub fn _mm_maskz_div_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
 pub fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i32x16();
-        let b = b.as_i32x16();
-        transmute(simd_select::<i32x16, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i32x16(), b.as_i32x16()).as_m512i() }
 }
 
 /// Compare packed signed 32-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2190,11 +2186,7 @@ pub fn _mm_maskz_max_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
 pub fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i64x8();
-        let b = b.as_i64x8();
-        transmute(simd_select::<i64x8, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i64x8(), b.as_i64x8()).as_m512i() }
 }
 
 /// Compare packed signed 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2233,11 +2225,7 @@ pub fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
 pub fn _mm256_max_epi64(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i64x4();
-        let b = b.as_i64x4();
-        transmute(simd_select::<i64x4, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i64x4(), b.as_i64x4()).as_m256i() }
 }
 
 /// Compare packed signed 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2276,11 +2264,7 @@ pub fn _mm256_maskz_max_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
 pub fn _mm_max_epi64(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i64x2();
-        let b = b.as_i64x2();
-        transmute(simd_select::<i64x2, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i64x2(), b.as_i64x2()).as_m128i() }
 }
 
 /// Compare packed signed 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2515,11 +2499,7 @@ pub fn _mm_maskz_max_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
 pub fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u32x16();
-        let b = b.as_u32x16();
-        transmute(simd_select::<i32x16, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u32x16(), b.as_u32x16()).as_m512i() }
 }
 
 /// Compare packed unsigned 32-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2614,11 +2594,7 @@ pub fn _mm_maskz_max_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
 pub fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u64x8();
-        let b = b.as_u64x8();
-        transmute(simd_select::<i64x8, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u64x8(), b.as_u64x8()).as_m512i() }
 }
 
 /// Compare packed unsigned 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2657,11 +2633,7 @@ pub fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
 pub fn _mm256_max_epu64(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u64x4();
-        let b = b.as_u64x4();
-        transmute(simd_select::<i64x4, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u64x4(), b.as_u64x4()).as_m256i() }
 }
 
 /// Compare packed unsigned 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2700,11 +2672,7 @@ pub fn _mm256_maskz_max_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
 pub fn _mm_max_epu64(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u64x2();
-        let b = b.as_u64x2();
-        transmute(simd_select::<i64x2, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u64x2(), b.as_u64x2()).as_m128i() }
 }
 
 /// Compare packed unsigned 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2743,11 +2711,7 @@ pub fn _mm_maskz_max_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
 pub fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i32x16();
-        let b = b.as_i32x16();
-        transmute(simd_select::<i32x16, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i32x16(), b.as_i32x16()).as_m512i() }
 }
 
 /// Compare packed signed 32-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2842,11 +2806,7 @@ pub fn _mm_maskz_min_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
 pub fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_i64x8();
-        let b = b.as_i64x8();
-        transmute(simd_select::<i64x8, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i64x8(), b.as_i64x8()).as_m512i() }
 }
 
 /// Compare packed signed 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2885,11 +2845,7 @@ pub fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
 pub fn _mm256_min_epi64(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_i64x4();
-        let b = b.as_i64x4();
-        transmute(simd_select::<i64x4, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i64x4(), b.as_i64x4()).as_m256i() }
 }
 
 /// Compare packed signed 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -2928,11 +2884,7 @@ pub fn _mm256_maskz_min_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
 pub fn _mm_min_epi64(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i64x2();
-        let b = b.as_i64x2();
-        transmute(simd_select::<i64x2, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i64x2(), b.as_i64x2()).as_m128i() }
 }
 
 /// Compare packed signed 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -3167,11 +3119,7 @@ pub fn _mm_maskz_min_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
 pub fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u32x16();
-        let b = b.as_u32x16();
-        transmute(simd_select::<i32x16, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u32x16(), b.as_u32x16()).as_m512i() }
 }
 
 /// Compare packed unsigned 32-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -3266,11 +3214,7 @@ pub fn _mm_maskz_min_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
 pub fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let a = a.as_u64x8();
-        let b = b.as_u64x8();
-        transmute(simd_select::<i64x8, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u64x8(), b.as_u64x8()).as_m512i() }
 }
 
 /// Compare packed unsigned 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -3309,11 +3253,7 @@ pub fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
 pub fn _mm256_min_epu64(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let a = a.as_u64x4();
-        let b = b.as_u64x4();
-        transmute(simd_select::<i64x4, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u64x4(), b.as_u64x4()).as_m256i() }
 }
 
 /// Compare packed unsigned 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -3352,11 +3292,7 @@ pub fn _mm256_maskz_min_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
 pub fn _mm_min_epu64(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u64x2();
-        let b = b.as_u64x2();
-        transmute(simd_select::<i64x2, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u64x2(), b.as_u64x2()).as_m128i() }
 }
 
 /// Compare packed unsigned 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index 11335856fb..93fe7a7ae3 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -218,11 +218,7 @@ pub fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pmaxsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i16x8();
-        let b = b.as_i16x8();
-        transmute(simd_select::<i16x8, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i16x8(), b.as_i16x8()).as_m128i() }
 }
 
 /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns the
@@ -234,11 +230,7 @@ pub fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pmaxub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u8x16();
-        let b = b.as_u8x16();
-        transmute(simd_select::<i8x16, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u8x16(), b.as_u8x16()).as_m128i() }
 }
 
 /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
@@ -250,11 +242,7 @@ pub fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pminsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i16x8();
-        let b = b.as_i16x8();
-        transmute(simd_select::<i16x8, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i16x8(), b.as_i16x8()).as_m128i() }
 }
 
 /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns the
@@ -266,11 +254,7 @@ pub fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pminub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_epu8(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u8x16();
-        let b = b.as_u8x16();
-        transmute(simd_select::<i8x16, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u8x16(), b.as_u8x16()).as_m128i() }
 }
 
 /// Multiplies the packed 16-bit integers in `a` and `b`.
diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
index f457c74aa9..6c16ee7600 100644
--- a/crates/core_arch/src/x86/sse41.rs
+++ b/crates/core_arch/src/x86/sse41.rs
@@ -312,11 +312,7 @@ pub fn _mm_insert_epi32<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
 #[cfg_attr(test, assert_instr(pmaxsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_epi8(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i8x16();
-        let b = b.as_i8x16();
-        transmute(simd_select::<i8x16, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i8x16(), b.as_i8x16()).as_m128i() }
 }
 
 /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns packed
@@ -328,11 +324,7 @@ pub fn _mm_max_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pmaxuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_epu16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u16x8();
-        let b = b.as_u16x8();
-        transmute(simd_select::<i16x8, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u16x8(), b.as_u16x8()).as_m128i() }
 }
 
 /// Compares packed 32-bit integers in `a` and `b`, and returns packed maximum
@@ -344,11 +336,7 @@ pub fn _mm_max_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pmaxsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_epi32(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i32x4();
-        let b = b.as_i32x4();
-        transmute(simd_select::<i32x4, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_i32x4(), b.as_i32x4()).as_m128i() }
 }
 
 /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns packed
@@ -360,11 +348,7 @@ pub fn _mm_max_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pmaxud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_epu32(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u32x4();
-        let b = b.as_u32x4();
-        transmute(simd_select::<i32x4, _>(simd_gt(a, b), a, b))
-    }
+    unsafe { simd_imax(a.as_u32x4(), b.as_u32x4()).as_m128i() }
 }
 
 /// Compares packed 8-bit integers in `a` and `b` and returns packed minimum
@@ -376,11 +360,7 @@ pub fn _mm_max_epu32(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pminsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_epi8(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i8x16();
-        let b = b.as_i8x16();
-        transmute(simd_select::<i8x16, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i8x16(), b.as_i8x16()).as_m128i() }
 }
 
 /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns packed
@@ -392,11 +372,7 @@ pub fn _mm_min_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pminuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_epu16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u16x8();
-        let b = b.as_u16x8();
-        transmute(simd_select::<i16x8, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u16x8(), b.as_u16x8()).as_m128i() }
 }
 
 /// Compares packed 32-bit integers in `a` and `b`, and returns packed minimum
@@ -408,11 +384,7 @@ pub fn _mm_min_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pminsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_epi32(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_i32x4();
-        let b = b.as_i32x4();
-        transmute(simd_select::<i32x4, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_i32x4(), b.as_i32x4()).as_m128i() }
 }
 
 /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns packed
@@ -424,11 +396,7 @@ pub fn _mm_min_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pminud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let a = a.as_u32x4();
-        let b = b.as_u32x4();
-        transmute(simd_select::<i32x4, _>(simd_lt(a, b), a, b))
-    }
+    unsafe { simd_imin(a.as_u32x4(), b.as_u32x4()).as_m128i() }
 }
 
 /// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers

From 3b0641c67e3e8aa4b8108ddbf9b7721841652f7d Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Fri, 28 Nov 2025 03:31:23 +0530
Subject: [PATCH 032/326] Use generic SIMD intrinsics for AVX512BW cvtepi

---
 crates/core_arch/src/x86/avx512bw.rs | 83 ++++++++++++++--------------
 1 file changed, 42 insertions(+), 41 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 4310c3d0ac..c7f271d22e 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -10735,11 +10735,11 @@ pub fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
-        transmute(vpmovswb(
-            a.as_i16x32(),
-            i8x32::ZERO,
-            0b11111111_11111111_11111111_11111111,
+        simd_cast::<_, i8x32>(simd_imax(
+            simd_imin(a.as_i16x32(), i16x32::splat(i8::MAX as _)),
+            i16x32::splat(i8::MIN as _),
         ))
+        .as_m256i()
     }
 }
 
@@ -10751,7 +10751,9 @@ pub fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
-    unsafe { transmute(vpmovswb(a.as_i16x32(), src.as_i8x32(), k)) }
+    unsafe {
+        simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), src.as_i8x32()).as_m256i()
+    }
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -10762,7 +10764,7 @@ pub fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
-    unsafe { transmute(vpmovswb(a.as_i16x32(), i8x32::ZERO, k)) }
+    unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), i8x32::ZERO).as_m256i() }
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst.
@@ -10773,7 +10775,13 @@ pub fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
-    unsafe { transmute(vpmovswb256(a.as_i16x16(), i8x16::ZERO, 0b11111111_11111111)) }
+    unsafe {
+        simd_cast::<_, i8x16>(simd_imax(
+            simd_imin(a.as_i16x16(), i16x16::splat(i8::MAX as _)),
+            i16x16::splat(i8::MIN as _),
+        ))
+        .as_m128i()
+    }
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -10784,7 +10792,9 @@ pub fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
-    unsafe { transmute(vpmovswb256(a.as_i16x16(), src.as_i8x16(), k)) }
+    unsafe {
+        simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), src.as_i8x16()).as_m128i()
+    }
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -10795,7 +10805,7 @@ pub fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
-    unsafe { transmute(vpmovswb256(a.as_i16x16(), i8x16::ZERO, k)) }
+    unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), i8x16::ZERO).as_m128i() }
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst.
@@ -10840,11 +10850,7 @@ pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
-        transmute(vpmovuswb(
-            a.as_u16x32(),
-            u8x32::ZERO,
-            0b11111111_11111111_11111111_11111111,
-        ))
+        simd_cast::<_, u8x32>(simd_imin(a.as_u16x32(), u16x32::splat(u8::MAX as _))).as_m256i()
     }
 }
 
@@ -10856,7 +10862,9 @@ pub fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
-    unsafe { transmute(vpmovuswb(a.as_u16x32(), src.as_u8x32(), k)) }
+    unsafe {
+        simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), src.as_u8x32()).as_m256i()
+    }
 }
 
 /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -10867,7 +10875,7 @@ pub fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
-    unsafe { transmute(vpmovuswb(a.as_u16x32(), u8x32::ZERO, k)) }
+    unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), u8x32::ZERO).as_m256i() }
 }
 
 /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst.
@@ -10879,11 +10887,7 @@ pub fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
     unsafe {
-        transmute(vpmovuswb256(
-            a.as_u16x16(),
-            u8x16::ZERO,
-            0b11111111_11111111,
-        ))
+        simd_cast::<_, u8x16>(simd_imin(a.as_u16x16(), u16x16::splat(u8::MAX as _))).as_m128i()
     }
 }
 
@@ -10895,7 +10899,9 @@ pub fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
-    unsafe { transmute(vpmovuswb256(a.as_u16x16(), src.as_u8x16(), k)) }
+    unsafe {
+        simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), src.as_u8x16()).as_m128i()
+    }
 }
 
 /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -10906,7 +10912,7 @@ pub fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
-    unsafe { transmute(vpmovuswb256(a.as_u16x16(), u8x16::ZERO, k)) }
+    unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), u8x16::ZERO).as_m128i() }
 }
 
 /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst.
@@ -11592,7 +11598,9 @@ pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a:
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
 pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
-    vpmovwbmem(mem_addr, a.as_i16x32(), k);
+    let result = _mm512_cvtepi16_epi8(a).as_i8x32();
+    let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, result);
 }
 
 /// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
@@ -11603,7 +11611,9 @@ pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32,
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
 pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
-    vpmovwbmem256(mem_addr, a.as_i16x16(), k);
+    let result = _mm256_cvtepi16_epi8(a).as_i8x16();
+    let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, result);
 }
 
 /// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
@@ -11614,7 +11624,13 @@ pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16,
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
 pub unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
-    vpmovwbmem128(mem_addr, a.as_i16x8(), k);
+    let result: i8x8 = simd_shuffle!(
+        _mm_cvtepi16_epi8(a).as_i8x16(),
+        i8x16::ZERO,
+        [0, 1, 2, 3, 4, 5, 6, 7]
+    );
+    let mask = simd_select_bitmask(k, i8x8::splat(!0), i8x8::ZERO);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, result);
 }
 
 /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
@@ -11703,17 +11719,9 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.dbpsadbw.128"]
     fn vdbpsadbw128(a: u8x16, b: u8x16, imm8: i32) -> u16x8;
 
-    #[link_name = "llvm.x86.avx512.mask.pmovs.wb.512"]
-    fn vpmovswb(a: i16x32, src: i8x32, mask: u32) -> i8x32;
-    #[link_name = "llvm.x86.avx512.mask.pmovs.wb.256"]
-    fn vpmovswb256(a: i16x16, src: i8x16, mask: u16) -> i8x16;
     #[link_name = "llvm.x86.avx512.mask.pmovs.wb.128"]
     fn vpmovswb128(a: i16x8, src: i8x16, mask: u8) -> i8x16;
 
-    #[link_name = "llvm.x86.avx512.mask.pmovus.wb.512"]
-    fn vpmovuswb(a: u16x32, src: u8x32, mask: u32) -> u8x32;
-    #[link_name = "llvm.x86.avx512.mask.pmovus.wb.256"]
-    fn vpmovuswb256(a: u16x16, src: u8x16, mask: u16) -> u8x16;
     #[link_name = "llvm.x86.avx512.mask.pmovus.wb.128"]
     fn vpmovuswb128(a: u16x8, src: u8x16, mask: u8) -> u8x16;
 
@@ -11724,13 +11732,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.128"]
     fn vpmovswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
 
-    #[link_name = "llvm.x86.avx512.mask.pmov.wb.mem.512"]
-    fn vpmovwbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
-    #[link_name = "llvm.x86.avx512.mask.pmov.wb.mem.256"]
-    fn vpmovwbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.pmov.wb.mem.128"]
-    fn vpmovwbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
-
     #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.512"]
     fn vpmovuswbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
     #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.256"]

From a904ccefec3aad4ea27b0c5f6ea0644a56936288 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 29 Nov 2025 09:20:03 +0530
Subject: [PATCH 033/326] systematically exclude svml, mmx and mpx rather than
 having an ad-hoc list

---
 crates/intrinsic-test/missing_x86.txt         | 869 +-----------------
 .../src/common/intrinsic_helpers.rs           |   2 +-
 crates/intrinsic-test/src/x86/compile.rs      |  12 +
 crates/intrinsic-test/src/x86/config.rs       |   6 -
 crates/intrinsic-test/src/x86/types.rs        |   6 -
 crates/intrinsic-test/src/x86/xml_parser.rs   |  14 +-
 6 files changed, 47 insertions(+), 862 deletions(-)

diff --git a/crates/intrinsic-test/missing_x86.txt b/crates/intrinsic-test/missing_x86.txt
index 58e37b92a1..11c3eeba90 100644
--- a/crates/intrinsic-test/missing_x86.txt
+++ b/crates/intrinsic-test/missing_x86.txt
@@ -3,17 +3,9 @@
 #__bswap_64
 _bswap64
 
-# Provides pointer to allocated memory, which is difficult to test
-_mm_malloc
-
-# requires target feature 'waitpkg', but would be inlined into function that is compiled without support for 'waitpkg'
-_tpause
-_umwait
-
-# `use of undeclared identifier` error in Clang
+# not present in Clang and Rust
 _bit_scan_forward
 _bit_scan_reverse
-_bswap
 _castf32_u32
 _castf64_u64
 _castu32_f32
@@ -22,569 +14,6 @@ _lrotl
 _lrotr
 _may_i_use_cpu_feature
 _may_i_use_cpu_feature_ext
-_mm256_acos_pd
-_mm256_acos_ph
-_mm256_acos_ps
-_mm256_acosh_pd
-_mm256_acosh_ph
-_mm256_acosh_ps
-_mm256_asin_pd
-_mm256_asin_ph
-_mm256_asin_ps
-_mm256_asinh_pd
-_mm256_asinh_ph
-_mm256_asinh_ps
-_mm256_atan_pd
-_mm256_atan_ps
-_mm256_atan_ph
-_mm256_atan2_pd
-_mm256_atan2_ph
-_mm256_atan2_ps
-_mm256_atanh_pd
-_mm256_atanh_ph
-_mm256_atanh_ps
-_mm256_cbrt_pd
-_mm256_cbrt_ph
-_mm256_cbrt_ps
-_mm256_cdfnorm_pd
-_mm256_cdfnorm_ph
-_mm256_cdfnorm_ps
-_mm256_cdfnorminv_pd
-_mm256_cdfnorminv_ph
-_mm256_cdfnorminv_ps
-_mm256_cexp_ps
-_mm256_cos_pd
-_mm256_cos_ph
-_mm256_cos_ps
-_mm256_cosd_pd
-_mm256_cosd_ph
-_mm256_cosd_ps
-_mm256_cosh_pd
-_mm256_cosh_ph
-_mm256_cosh_ps
-_mm256_csqrt_ps
-_mm256_div_epi16
-_mm256_div_epi32
-_mm256_div_epi64
-_mm256_div_epi8
-_mm256_div_epu16
-_mm256_div_epu32
-_mm256_div_epu64
-_mm256_div_epu8
-_mm256_dpbssd_epi32
-_mm256_dpbssds_epi32
-_mm256_dpbsud_epi32
-_mm256_dpbsuds_epi32
-_mm256_dpbuud_epi32
-_mm256_dpbuuds_epi32
-_mm256_dpwsud_epi32
-_mm256_dpwsuds_epi32
-_mm256_dpwusd_epi32
-_mm256_dpwusds_epi32
-_mm256_dpwuud_epi32
-_mm256_dpwuuds_epi32
-_mm256_erf_pd
-_mm256_erf_ps
-_mm256_erfc_pd
-_mm256_erfc_ph
-_mm256_erfc_ps
-_mm256_erfcinv_pd
-_mm256_erfcinv_ph
-_mm256_erfcinv_ps
-_mm256_erfinv_pd
-_mm256_erfinv_ph
-_mm256_erfinv_ps
-_mm256_exp10_pd
-_mm256_exp10_ph
-_mm256_exp10_ps
-_mm256_exp2_pd
-_mm256_exp2_ph
-_mm256_exp2_ps
-_mm256_exp_pd
-_mm256_exp_ph
-_mm256_exp_ps
-_mm256_expm1_pd
-_mm256_expm1_ph
-_mm256_expm1_ps
-_mm256_hypot_pd
-_mm256_hypot_ph
-_mm256_hypot_ps
-_mm256_idiv_epi32
-_mm256_invcbrt_pd
-_mm256_invcbrt_ph
-_mm256_invcbrt_ps
-_mm256_invsqrt_pd
-_mm256_invsqrt_ph
-_mm256_invsqrt_ps
-_mm256_irem_epi32
-_mm256_log10_pd
-_mm256_log10_ph
-_mm256_log10_ps
-_mm256_log1p_pd
-_mm256_log1p_ph
-_mm256_log1p_ps
-_mm256_log2_pd
-_mm256_log2_ph
-_mm256_log2_ps
-_mm256_log_pd
-_mm256_log_ph
-_mm256_log_ps
-_mm256_logb_pd
-_mm256_logb_ph
-_mm256_logb_ps
-_mm256_clog_ps
-_mm256_madd52hi_avx_epu64
-_mm256_madd52lo_avx_epu64
-_mm256_erf_ph
-_mm256_mask_reduce_add_epi16
-_mm256_mask_reduce_add_epi8
-_mm256_mask_reduce_and_epi16
-_mm256_mask_reduce_and_epi8
-_mm256_mask_reduce_max_epi16
-_mm256_mask_reduce_max_epi8
-_mm256_mask_reduce_max_epu16
-_mm256_mask_reduce_max_epu8
-_mm256_mask_reduce_min_epi16
-_mm256_mask_reduce_min_epi8
-_mm256_mask_reduce_min_epu16
-_mm256_mask_reduce_min_epu8
-_mm256_mask_reduce_mul_epi16
-_mm256_mask_reduce_mul_epi8
-_mm256_mask_reduce_or_epi16
-_mm256_mask_reduce_or_epi8
-_mm512_cosd_ph
-_mm512_cosd_ps
-_mm512_cosh_pd
-_mm512_cosh_ph
-_mm512_cosh_ps
-_mm512_div_epi16
-_mm512_div_epi32
-_mm512_div_epi64
-_mm512_div_epi8
-_mm512_div_epu16
-_mm512_div_epu32
-_mm512_div_epu64
-_mm512_div_epu8
-_mm512_erf_pd
-_mm512_erf_ph
-_mm512_erf_ps
-_mm512_erfc_pd
-_mm512_erfc_ph
-_mm512_erfc_ps
-_mm512_erfcinv_pd
-_mm512_erfcinv_ph
-_mm512_erfcinv_ps
-_mm512_erfinv_pd
-_mm512_erfinv_ph
-_mm512_erfinv_ps
-_mm512_exp10_pd
-_mm512_exp10_ph
-_mm512_exp10_ps
-_mm512_exp2_pd
-_mm512_exp2_ph
-_mm512_exp2_ps
-_mm512_exp_pd
-_mm512_exp_ph
-_mm512_exp_ps
-_mm512_expm1_pd
-_mm512_expm1_ph
-_mm512_expm1_ps
-_mm512_floor_ph
-_mm512_hypot_pd
-_mm512_hypot_ph
-_mm512_hypot_ps
-_mm512_invsqrt_pd
-_mm512_invsqrt_ph
-_mm512_invsqrt_ps
-_mm512_log10_pd
-_mm512_log10_ph
-_mm512_log10_ps
-_mm512_log1p_pd
-_mm512_log1p_ph
-_mm512_log1p_ps
-_mm512_log2_pd
-_mm512_log2_ph
-_mm512_log2_ps
-_mm512_log_pd
-_mm512_log_ph
-_mm512_log_ps
-_mm512_logb_pd
-_mm512_logb_ph
-_mm512_logb_ps
-_mm512_mask_acos_pd
-_mm512_mask_acos_ph
-_mm512_mask_acos_ps
-_mm512_mask_acosh_pd
-_mm512_mask_acosh_ph
-_mm512_mask_acosh_ps
-_mm512_mask_asin_pd
-_mm512_mask_asin_ph
-_mm512_mask_asin_ps
-_mm512_mask_asinh_pd
-_mm512_mask_asinh_ph
-_mm512_mask_asinh_ps
-_mm512_mask_atan2_pd
-_mm512_mask_atan2_ps
-_mm512_mask_atan_pd
-_mm512_mask_atan_ph
-_mm512_mask_atan_ph
-_mm512_mask_atanh_pd
-_mm512_mask_atanh_ph
-_mm512_mask_atanh_ps
-_mm512_mask_cbrt_pd
-_mm512_mask_cbrt_ph
-_mm512_mask_cbrt_ps
-_mm512_mask_cdfnorm_pd
-_mm512_mask_cdfnorm_ph
-_mm512_mask_cdfnorm_ps
-_mm512_mask_cdfnorminv_pd
-_mm512_mask_cdfnorminv_ph
-_mm512_mask_cdfnorminv_ps
-_mm512_mask_ceil_ph
-_mm512_mask_cos_pd
-_mm512_mask_cos_ph
-_mm512_mask_cos_ps
-_mm512_mask_cosd_pd
-_mm512_mask_cosd_ph
-_mm512_mask_cosd_ps
-_mm512_mask_cosh_pd
-_mm512_mask_cosh_ph
-_mm512_mask_cosh_ps
-_mm512_mask_atan_ps
-_mm512_cosd_pd
-_mm512_cos_ps
-_mm512_cos_ph
-_mm512_cos_pd
-_mm512_mask_div_epi32
-_mm512_mask_div_epu32
-_mm512_mask_erf_pd
-_mm512_mask_erf_ph
-_mm512_mask_erf_ps
-_mm512_mask_erfc_pd
-_mm512_mask_erfc_ph
-_mm512_mask_erfc_ps
-_mm512_mask_erfcinv_pd
-_mm512_mask_erfcinv_ph
-_mm512_mask_erfcinv_ps
-_mm512_mask_erfinv_pd
-_mm512_mask_erfinv_ph
-_mm512_mask_erfinv_ps
-_mm512_mask_exp10_pd
-_mm512_mask_exp10_ph
-_mm512_mask_exp10_ps
-_mm512_mask_exp2_pd
-_mm512_mask_exp2_ph
-_mm512_mask_exp2_ps
-_mm512_mask_exp_pd
-_mm512_mask_exp_ph
-_mm512_mask_exp_ps
-_mm512_mask_expm1_pd
-_mm512_mask_expm1_ph
-_mm512_mask_expm1_ps
-_mm512_mask_floor_ph
-_mm512_mask_hypot_pd
-_mm512_mask_hypot_ps
-_mm512_mask_invsqrt_pd
-_mm512_mask_invsqrt_ph
-_mm512_mask_invsqrt_ps
-_mm512_mask_log10_pd
-_mm512_mask_log10_ph
-_mm512_mask_log10_ps
-_mm512_mask_log1p_pd
-_mm512_mask_log1p_ph
-_mm512_mask_log1p_ps
-_mm512_mask_log2_pd
-_mm512_mask_log2_ph
-_mm512_mask_log2_ps
-_mm512_mask_log_pd
-_mm512_mask_log_ph
-_mm512_mask_log_ps
-_mm512_mask_logb_pd
-_mm512_mask_logb_ph
-_mm512_mask_logb_ps
-_mm512_mask_nearbyint_pd
-_mm512_mask_nearbyint_ph
-_mm512_mask_nearbyint_ps
-_mm512_mask_pow_pd
-_mm512_mask_pow_ps
-_mm512_mask_recip_pd
-_mm512_mask_recip_ph
-_mm512_mask_recip_ps
-_mm512_mask_rem_epi32
-_mm512_mask_rem_epu32
-_mm512_mask_rint_pd
-_mm512_mask_rint_ph
-_mm512_mask_rint_ps
-_mm512_mask_sin_pd
-_mm512_mask_sin_ph
-_mm512_mask_sin_ps
-_mm512_mask_sind_pd
-_mm512_mask_sind_ph
-_mm512_mask_sind_ps
-_mm512_mask_sinh_pd
-_mm512_mask_sinh_ph
-_mm512_mask_sinh_ps
-_mm512_mask_svml_round_pd
-_mm512_mask_svml_round_ph
-_mm512_mask_tan_pd
-_mm512_mask_tan_ph
-_mm512_mask_tan_ps
-_mm512_mask_tand_pd
-_mm512_mask_tand_ph
-_mm512_mask_tand_ps
-_mm512_mask_tanh_pd
-_mm512_mask_tanh_ph
-_mm512_mask_tanh_ps
-_mm512_mask_trunc_pd
-_mm512_mask_trunc_ph
-_mm512_mask_trunc_ps
-_mm512_nearbyint_pd
-_mm512_nearbyint_ph
-_mm512_nearbyint_ps
-_mm512_pow_pd
-_mm512_pow_ph
-_mm512_pow_ps
-_mm512_recip_pd
-_mm512_recip_ph
-_mm512_recip_ps
-_mm512_rem_epi16
-_mm512_rem_epi32
-_mm512_rem_epi64
-_mm512_rem_epi8
-_mm512_rem_epu16
-_mm512_rem_epu32
-_mm512_rem_epu64
-_mm512_rem_epu8
-_mm512_rint_pd
-_mm512_rint_ph
-_mm512_rint_ps
-_mm512_sin_pd
-_mm512_sin_ph
-_mm512_sin_ps
-_mm512_sind_pd
-_mm512_sind_ph
-_mm512_sind_ps
-_mm512_sinh_pd
-_mm512_sinh_ph
-_mm512_sinh_ps
-_mm512_svml_round_pd
-_mm512_svml_round_ph
-_mm512_tan_pd
-_mm512_tan_ph
-_mm512_tan_ps
-_mm512_tand_pd
-_mm512_tand_ph
-_mm512_tand_ps
-_mm512_tanh_pd
-_mm512_tanh_ph
-_mm512_tanh_ps
-_mm512_trunc_pd
-_mm512_trunc_ph
-_mm512_trunc_ps
-_mm_acos_pd
-_mm_acos_ph
-_mm_acos_ps
-_mm_acosh_pd
-_mm_acosh_ph
-_mm_acosh_ps
-_mm_asin_pd
-_mm_asin_ph
-_mm_asin_ps
-_mm_asinh_pd
-_mm_asinh_ph
-_mm_asinh_ps
-_mm_atan2_pd
-_mm_atan2_ph
-_mm_atan2_ps
-_mm_atan_pd
-_mm_atan_ph
-_mm_atan_ps
-_mm_atanh_pd
-_mm_atanh_ph
-_mm_atanh_ps
-_mm_cbrt_pd
-_mm_cbrt_ph
-_mm_cbrt_ps
-_mm_cdfnorm_pd
-_mm_cdfnorm_ph
-_mm_cdfnorm_ps
-_mm_cdfnorminv_pd
-_mm_cdfnorminv_ph
-_mm_cdfnorminv_ps
-_mm_cexp_ps
-_mm_clog_ps
-_mm_cos_pd
-_mm_cos_ph
-_mm_cos_ps
-_mm_cosd_pd
-_mm_cosd_ph
-_mm_cosd_ps
-_mm_cosh_pd
-_mm_cosh_ph
-_mm_cosh_ps
-_mm_csqrt_ps
-_mm_cvtsd_si64x
-_mm_cvtsi128_si64x
-_mm_cvtsi64x_sd
-_mm_cvtsi64x_si128
-_mm_cvttsd_si64x
-_mm_div_epi16
-_mm_div_epi32
-_mm_div_epi64
-_mm_div_epi8
-_mm_div_epu16
-_mm_div_epu32
-_mm_div_epu64
-_mm_div_epu8
-_mm_dpbssd_epi32
-_mm_dpbssds_epi32
-_mm_dpbsud_epi32
-_mm_dpbsuds_epi32
-_mm_dpbuud_epi32
-_mm_dpbuuds_epi32
-_mm_dpwsud_epi32
-_mm_dpwsuds_epi32
-_mm_dpwusd_epi32
-_mm_dpwusds_epi32
-_mm_dpwuud_epi32
-_mm_dpwuuds_epi32
-_mm_erf_pd
-_mm_erf_ph
-_mm_erf_ps
-_mm_erfc_pd
-_mm_erfc_ph
-_mm_erfc_ps
-_mm_erfcinv_pd
-_mm_erfcinv_ph
-_mm_erfcinv_ps
-_mm_erfinv_pd
-_mm_erfinv_ph
-_mm_erfinv_ps
-_mm_exp10_pd
-_mm_exp10_ph
-_mm_exp10_ps
-_mm_exp2_pd
-_mm_exp2_ph
-_mm_exp2_ps
-_mm_exp_pd
-_mm_exp_ph
-_mm_exp_ps
-_mm_expm1_pd
-_mm_expm1_ph
-_mm_expm1_ps
-_mm_hypot_pd
-_mm_hypot_ph
-_mm_hypot_ps
-_mm_idiv_epi32
-_mm_invcbrt_pd
-_mm_invcbrt_ph
-_mm_invcbrt_ps
-_mm_invsqrt_pd
-_mm_invsqrt_ph
-_mm_invsqrt_ps
-_mm_irem_epi32
-_mm_log10_pd
-_mm_log10_ph
-_mm_log10_ps
-_mm_log1p_pd
-_mm_log1p_ph
-_mm_log1p_ps
-_mm_log2_pd
-_mm_log2_ph
-_mm_log2_ps
-_mm_log_pd
-_mm_log_ph
-_mm_log_ps
-_mm_logb_pd
-_mm_logb_ph
-_mm_logb_ps
-_mm_madd52hi_avx_epu64
-_mm_madd52lo_avx_epu64
-_mm_mask_reduce_add_epi16
-_mm_mask_reduce_add_epi8
-_mm_mask_reduce_and_epi16
-_mm_mask_reduce_and_epi8
-_mm_mask_reduce_max_epi16
-_mm_mask_reduce_max_epi8
-_mm_mask_reduce_max_epu16
-_mm_mask_reduce_max_epu8
-_mm_mask_reduce_min_epi16
-_mm_mask_reduce_min_epi8
-_mm_mask_reduce_min_epu16
-_mm_mask_reduce_min_epu8
-_mm_mask_reduce_mul_epi16
-_mm_mask_reduce_mul_epi8
-_mm_mask_reduce_or_epi16
-_mm_mask_reduce_or_epi8
-_mm_pow_pd
-_mm_pow_ph
-_mm_pow_ps
-_mm_reduce_add_epi16
-_mm_reduce_add_epi8
-_mm_reduce_and_epi16
-_mm_reduce_and_epi8
-_mm_reduce_max_epi16
-_mm_reduce_max_epi8
-_mm_reduce_max_epu16
-_mm_reduce_max_epu8
-_mm_reduce_min_epi16
-_mm_reduce_min_epi8
-_mm_reduce_min_epu16
-_mm_reduce_min_epu8
-_mm_reduce_mul_epi16
-_mm_reduce_mul_epi8
-_mm_reduce_or_epi16
-_mm_reduce_or_epi8
-_mm_rem_epi16
-_mm_rem_epi32
-_mm_rem_epi64
-_mm_rem_epi8
-_mm_rem_epu16
-_mm_rem_epu32
-_mm_rem_epu64
-_mm_rem_epu8
-_mm_sin_pd
-_mm_sin_ph
-_mm_sin_ps
-_mm_sind_pd
-_mm_sind_ph
-_mm_sind_ps
-_mm_sinh_pd
-_mm_sinh_ph
-_mm_sinh_ps
-_mm_sm3msg1_epi32
-_mm_sm3msg2_epi32
-_mm_sm3rnds2_epi32
-_mm_sm4key4_epi32
-_mm_sm4rnds4_epi32
-_mm_svml_ceil_pd
-_mm_svml_ceil_ph
-_mm_svml_ceil_ps
-_mm_svml_floor_pd
-_mm_svml_floor_ph
-_mm_svml_floor_ps
-_mm_svml_round_pd
-_mm_svml_round_ph
-_mm_svml_round_ps
-_mm_svml_sqrt_pd
-_mm_svml_sqrt_ph
-_mm_svml_sqrt_ps
-_mm_tan_pd
-_mm_tan_ph
-_mm_tan_ps
-_mm_tand_pd
-_mm_tand_ph
-_mm_tand_ps
-_mm_tanh_pd
-_mm_tanh_ph
-_mm_tanh_ps
-_mm_trunc_pd
-_mm_trunc_ph
-_mm_trunc_ps
-_mm_udiv_epi32
-_mm_urem_epi32
-_popcnt32
-_popcnt64
 _rdpmc
 _rotl
 _rotl64
@@ -594,284 +23,30 @@ _rotwl
 _rotwr
 _urdmsr
 
-# Cannot find value in this scope (in Rust testfiles)
+# not present in Clang
+_bswap
+_mm_cvtsd_si64x
+_mm_cvtsi128_si64x
+_mm_cvtsi64x_sd
+_mm_cvtsi64x_si128
+_mm_cvttsd_si64x
+_popcnt32
+_popcnt64
+
+# not present in Rust
+_cvtsh_ss
+_cvtss_sh
+_mm256_set1_pch
 _mm512_set1_pch
-_mm_abs_pi16
-_mm_abs_pi32
-_mm_abs_pi8
-_mm_add_pi16
-_mm_add_pi32
-_mm_add_pi8
-_mm_add_si64
-_mm_adds_pi16
-_mm_adds_pi8
-_mm_adds_pu16
-_mm_adds_pu8
-_mm_alignr_pi8
-_mm_and_si64
-_mm_andnot_si64
-_mm_avg_pu16
-_mm_avg_pu8
-_mm_cmpeq_pi16
-_mm_cmpeq_pi32
-_mm_cmpeq_pi8
-_mm_cmpgt_pi16
-_mm_cmpgt_pi32
-_mm_cmpgt_pi8
-_mm_cvt_pi2ps
-_mm_cvt_ps2pi
-_mm_cvtm64_si64
-_mm_cvtpd_pi32
-_mm_cvtpi16_ps
-_mm_cvtpi32_pd
-_mm_cvtpi32_ps
-_mm_cvtpi32x2_ps
-_mm_cvtpi8_ps
-_mm_cvtps_pi16
-_mm_cvtps_pi32
-_mm_cvtps_pi8
-_mm_cvtpu16_ps
-_mm_cvtpu8_ps
-_mm_cvtsi32_si64
-_mm_cvtsi64_m64
-_mm_cvtsi64_si32
-_mm_cvtt_ps2pi
-_mm_cvttpd_pi32
-_mm512_cbrt_pd
-_mm512_cbrt_ph
-_mm512_cbrt_ps
-_mm512_cdfnorm_pd
-_mm512_cdfnorm_ph
-_mm512_cdfnorm_ps
-_mm512_cdfnorminv_pd
-_mm512_cdfnorminv_ph
-_mm512_cdfnorminv_ps
-_mm512_ceil_pd
-_mm512_ceil_ph
-_mm512_ceil_ps
-_mm512_floor_pd
-_mm512_floor_ps
-_mm512_mask_ceil_pd
-_mm512_mask_ceil_ps
-_mm_max_pi16
-_mm_max_pu8
-_mm_min_pi16
-_mm_min_pu8
-_mm_movemask_pi8
-_mm_movepi64_pi64
-_mm_movpi64_epi64
-_mm_mul_su32
-_mm_mulhi_pi16
-_mm_mulhi_pu16
-_mm_mulhrs_pi16
-_mm_mullo_pi16
-_mm_or_si64
-_mm_packs_pi16
-_mm_packs_pi32
-_mm_packs_pu16
+_mm_malloc
 _mm_popcnt_u32
 _mm_popcnt_u64
-_mm_sad_pu8
-_mm_set1_epi64
 _mm_set1_pch
-_mm_set1_pi16
-_mm_set1_pi32
-_mm_set1_pi8
-_mm_set_epi64
-_mm_set_pi16
-_mm_set_pi32
-_mm_set_pi8
-_mm_setr_epi64
-_mm_setr_pi16
-_mm_setr_pi32
-_mm_setr_pi8
-_mm_shuffle_pi16
-_mm_shuffle_pi8
-_mm_sign_pi16
-_mm_sign_pi32
-_mm_sign_pi8
-_mm_sll_pi16
-_mm_sll_pi32
-_mm_sll_si64
-_mm_slli_pi16
-_mm_slli_pi32
-_mm_slli_si64
-_mm_sra_pi16
-_mm_sra_pi32
-_mm_srai_pi16
-_mm_srai_pi32
-_mm_srl_pi16
-_mm_srl_pi32
-_mm_srl_si64
-_mm_srli_pi16
-_mm_srli_pi32
-_mm_srli_si64
-_mm_sub_pi16
-_mm_sub_pi32
-_mm_sub_pi8
-_mm_sub_si64
-_mm_subs_pi16
-_mm_subs_pi8
-_mm_subs_pu16
-_mm_subs_pu8
-_mm_unpackhi_pi16
-_mm_unpackhi_pi32
-_mm_unpackhi_pi8
-_mm_unpacklo_pi16
-_mm_unpacklo_pi32
-_mm_unpacklo_pi8
-_mm_xor_si64
-_mm256_pow_pd
-_mm256_pow_ph
-_mm256_pow_ps
-_mm256_rem_epi16
-_mm256_rem_epi32
-_mm256_rem_epi64
-_mm256_rem_epi8
-_mm256_rem_epu16
-_mm256_rem_epu32
-_mm256_rem_epu64
-_mm256_rem_epu8
-_mm256_set1_pch
-_mm256_sin_pd
-_mm256_sin_ph
-_mm256_sin_ps
-_mm256_sind_pd
-_mm256_sind_ph
-_mm256_sind_ps
-_mm256_sinh_pd
-_mm256_sinh_ph
-_mm256_sinh_ps
-_mm256_svml_ceil_pd
-_mm256_svml_ceil_ph
-_mm256_svml_ceil_ps
-_mm256_svml_floor_pd
-_mm256_svml_floor_ph
-_mm256_svml_floor_ps
-_mm256_svml_round_pd
-_mm256_svml_round_ph
-_mm256_svml_round_ps
-_mm256_svml_sqrt_pd
-_mm256_svml_sqrt_ph
-_mm256_svml_sqrt_ps
-_mm256_tan_pd
-_mm256_tan_ph
-_mm256_tan_ps
-_mm256_tand_pd
-_mm256_tand_ph
-_mm256_tand_ps
-_mm256_tanh_pd
-_mm256_tanh_ph
-_mm256_tanh_ps
-_mm256_trunc_pd
-_mm256_trunc_ph
-_mm256_trunc_ps
-_mm256_udiv_epi32
-_mm256_urem_epi32
-_mm512_acos_pd
-_mm512_acos_ph
-_mm512_acos_ps
-_mm512_acosh_pd
-_mm512_acosh_ph
-_mm512_acosh_ps
-_mm_cvttps_pi32
-_mm_extract_pi16
-_mm_hadd_pi16
-_mm_hadd_pi32
-_mm_hadds_pi16
-_mm_hsub_pi16
-_mm_hsub_pi32
-_mm_hsubs_pi16
-_mm_insert_pi16
-_mm_madd_pi16
-_mm_maddubs_pi16
-_mm512_asin_pd
-_mm512_asin_ph
-_mm512_asin_ps
-_mm512_asinh_pd
-_mm512_asinh_ph
-_mm512_asinh_ps
-_mm512_atan2_pd
-_mm512_atan2_ph
-_mm512_atan2_ps
-_mm512_atan_pd
-_mm512_atan_ph
-_mm512_atan_ps
-_mm512_atanh_pd
-_mm512_atanh_ph
-_mm512_atanh_ps
-_cvtsh_ss
-_cvtss_sh
-_m_from_int
-_m_from_int64
-_m_packssdw
-_m_packsswb
-_m_packuswb
-_m_paddb
-_m_paddd
-_m_paddsb
-_m_paddsw
-_m_paddusb
-_m_paddusw
-_m_paddw
-_m_pand
-_m_pandn
-_m_pavgb
-_m_pavgw
-_m_pcmpeqb
-_m_pcmpeqd
-_m_pcmpeqw
-_m_pcmpgtb
-_m_pcmpgtd
-_m_pcmpgtw
-_m_pextrw
-_m_pinsrw
-_m_pmaddwd
-_m_pmaxsw
-_m_pmaxub
-_m_pminsw
-_m_pminub
-_m_pmovmskb
-_m_pmulhuw
-_m_pmulhw
-_m_pmullw
-_m_por
-_m_psadbw
-_m_pshufw
-_m_pslld
-_m_pslldi
-_m_psllq
-_m_psllqi
-_m_psllw
-_m_psllwi
-_m_psrad
-_m_psradi
-_m_psraw
-_m_psrawi
-_m_psrld
-_m_psrldi
-_m_psrlq
-_m_psrlqi
-_m_psrlw
-_m_psrlwi
-_m_psubb
-_m_psubd
-_m_psubsb
-_m_psubsw
-_m_psubusb
-_m_psubusw
-_m_psubw
-_m_punpckhbw
-_m_punpckhdq
-_m_punpckhwd
-_m_punpcklbw
-_m_punpckldq
-_m_punpcklwd
-_m_pxor
-_m_to_int
-_m_to_int64
-_mm512_mask_floor_pd
-_mm512_mask_floor_ps
+_tpause
+_umwait
+
+# IMM8 must be an even number in the range `0..=62`
+_mm_sm3rnds2_epi32
 
 # SDE ERROR: Cannot execute XGETBV with ECX != 0
 _xgetbv
@@ -901,4 +76,4 @@ _mm_extract_epi8
 _mm_mask_cvtepi16_epi8
 _mm_mask_cvtpd_epi32
 _mm_mask_cvtpd_ps
-_mm_ucomineq_sh
\ No newline at end of file
+_mm_ucomineq_sh
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index c2d66868ce..bd943c211e 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -42,7 +42,7 @@ impl FromStr for TypeKind {
             "uint" | "unsigned" | "UI8" | "UI16" | "UI32" | "UI64" => Ok(Self::Int(Sign::Unsigned)),
             "void" => Ok(Self::Void),
             "MASK" => Ok(Self::Mask),
-            "M64" | "M128" | "M256" | "M512" => Ok(Self::Vector),
+            "M128" | "M256" | "M512" => Ok(Self::Vector),
             _ => Err(format!("Impossible to parse argument kind {s}")),
         }
     }
diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 60997a1278..65cd291b1b 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -25,14 +25,26 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
             "-mavx512cd",
             "-mavx512fp16",
             "-msha512",
+            "-msm3",
             "-msm4",
             "-mavxvnni",
+            "-mavxvnniint8",
+            "-mavxneconvert",
+            "-mavxifma",
+            "-mavxvnniint16",
+            "-mavx512bf16",
             "-mavx512bitalg",
             "-mavx512ifma",
             "-mavx512vbmi",
             "-mavx512vbmi2",
             "-mavx512vnni",
             "-mavx512vpopcntdq",
+            "-mavx512vp2intersect",
+            "-mbmi",
+            "-mbmi2",
+            "-mgfni",
+            "-mvaes",
+            "-mvpclmulqdq",
             "-ferror-limit=1000",
             "-std=c++23",
         ]);
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 7c349e4482..40607d8491 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -280,12 +280,6 @@ pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
     
     #define _mm512_extract_intrinsic_test_epi64(m, lane) \
         _mm_extract_epi64(_mm512_extracti64x2_epi64((m), (lane) / 2), (lane) % 2)
-    
-    #define _mm64_extract_intrinsic_test_epi8(m, lane) \
-        ((_mm_extract_pi16((m), (lane) / 2) >> (((lane) % 2) * 8)) & 0xFF)
-    
-    #define _mm64_extract_intrinsic_test_epi32(m, lane) \
-        _mm_cvtsi64_si32(_mm_srli_si64(m, (lane) * 32))
         
     // Load f16 (__m128h) and cast to integer (__m128i)
     #define _mm_loadu_ph_to___m128i(mem_addr) _mm_castph_si128(_mm_loadu_ph(mem_addr))
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 87932fcb3e..d6cb938096 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -115,9 +115,6 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             // if "type" starts with __m<num>{h/i/<null>},
             // then use either _mm_set1_epi64,
             // _mm256_set1_epi64 or _mm512_set1_epi64
-            if type_value.contains("__m64") {
-                return String::from("*(__m64*)");
-            }
 
             let type_val_filtered = type_value
                 .chars()
@@ -262,9 +259,6 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             (Some(16), Some(512)) => String::from("(uint16_t)_mm512_extract_intrinsic_test_epi16"),
             (Some(32), Some(512)) => String::from("(uint32_t)_mm512_extract_intrinsic_test_epi32"),
             (Some(64), Some(512)) => String::from("(uint64_t)_mm512_extract_intrinsic_test_epi64"),
-            (Some(8), Some(64)) => String::from("(uint8_t)_mm64_extract_intrinsic_test_epi8"),
-            (Some(16), Some(64)) => String::from("(uint16_t)_mm_extract_pi16"),
-            (Some(32), Some(64)) => String::from("(uint32_t)_mm64_extract_intrinsic_test_epi32"),
             _ => unreachable!(
                 "invalid length for vector argument: {:?}, {:?}",
                 self.bit_len, self.simd_len
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index af85118b8a..681b1a3c52 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -30,8 +30,8 @@ struct XMLIntrinsic {
     pub return_data: Parameter,
     #[serde(rename = "@name")]
     pub name: String,
-    // #[serde(rename = "@tech")]
-    // tech: String,
+    #[serde(rename = "@tech")]
+    tech: String,
     #[serde(rename = "CPUID", default)]
     cpuid: Vec<String>,
     #[serde(rename = "parameter", default)]
@@ -65,6 +65,16 @@ pub fn get_xml_intrinsics(
     let parsed_intrinsics: Vec<Intrinsic<X86IntrinsicType>> = data
         .intrinsics
         .into_iter()
+        .filter(|intrinsic| {
+            intrinsic.tech != "SVML"
+                && intrinsic.tech != "MMX"
+                && !intrinsic.cpuid.contains(&"MPX".to_string())
+                && intrinsic.return_data.type_data != "__m64"
+                && !intrinsic
+                    .parameters
+                    .iter()
+                    .any(|param| param.type_data.contains("__m64"))
+        })
         .filter_map(|intr| {
             // Some(xml_to_intrinsic(intr, target).expect("Couldn't parse XML properly!"))
             xml_to_intrinsic(intr).ok()

From d90008157ba1460d3f1f6ed7425f824a253ee79b Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 29 Nov 2025 10:30:15 +0530
Subject: [PATCH 034/326] Format `f16` values normally, rather than use the bit
 patterns

---
 crates/intrinsic-test/src/arm/config.rs       | 93 +------------------
 .../src/common/intrinsic_helpers.rs           | 13 +--
 crates/intrinsic-test/src/x86/config.rs       | 73 +--------------
 crates/intrinsic-test/src/x86/types.rs        | 44 +++------
 4 files changed, 20 insertions(+), 203 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index a634645969..85cb21c2d6 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -38,11 +38,7 @@ std::ostream& operator<<(std::ostream& os, poly128_t value) {
 #endif
 
 std::ostream& operator<<(std::ostream& os, float16_t value) {
-    uint16_t temp = 0;
-    memcpy(&temp, &value, sizeof(float16_t));
-    std::stringstream ss;
-    ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
-    os << ss.str();
+    os << static_cast<float>(value);
     return os;
 }
 
@@ -52,92 +48,7 @@ std::ostream& operator<<(std::ostream& os, uint8_t value) {
 }
 "#;
 
-// Format f16 values (and vectors containing them) in a way that is consistent with C.
-pub const PLATFORM_RUST_DEFINITIONS: &str = r#"
-/// Used to continue `Debug`ging SIMD types as `MySimd(1, 2, 3, 4)`, as they
-/// were before moving to array-based simd.
-#[inline]
-fn debug_simd_finish<T: core::fmt::Debug, const N: usize>(
-    formatter: &mut core::fmt::Formatter<'_>,
-    type_name: &str,
-    array: &[T; N],
-) -> core::fmt::Result {
-    core::fmt::Formatter::debug_tuple_fields_finish(
-        formatter,
-        type_name,
-        &core::array::from_fn::<&dyn core::fmt::Debug, N, _>(|i| &array[i]),
-    )
-}
-
-#[repr(transparent)]
-struct Hex<T>(T);
-
-impl<T: DebugHexF16> core::fmt::Debug for Hex<T> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        <T as DebugHexF16>::fmt(&self.0, f)
-    }
-}
-
-fn debug_f16<T: DebugHexF16>(x: T) -> impl core::fmt::Debug {
-    Hex(x)
-}
-
-trait DebugHexF16 {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result;
-}
-
-impl DebugHexF16 for f16 {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "{:#06x?}", self.to_bits())
-    }
-}
-
-impl DebugHexF16 for float16x4_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 4]>(*self) };
-        debug_simd_finish(f, "float16x4_t", &array)
-    }
-}
-
-impl DebugHexF16 for float16x8_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 8]>(*self) };
-        debug_simd_finish(f, "float16x8_t", &array)
-    }
-}
-
-impl DebugHexF16 for float16x4x2_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        debug_simd_finish(f, "float16x4x2_t", &[Hex(self.0), Hex(self.1)])
-    }
-}
-impl DebugHexF16 for float16x4x3_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        debug_simd_finish(f, "float16x4x3_t", &[Hex(self.0), Hex(self.1), Hex(self.2)])
-    }
-}
-impl DebugHexF16 for float16x4x4_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        debug_simd_finish(f, "float16x4x4_t", &[Hex(self.0), Hex(self.1), Hex(self.2), Hex(self.3)])
-    }
-}
-
-impl DebugHexF16 for float16x8x2_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        debug_simd_finish(f, "float16x8x2_t", &[Hex(self.0), Hex(self.1)])
-    }
-}
-impl DebugHexF16 for float16x8x3_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        debug_simd_finish(f, "float16x8x3_t", &[Hex(self.0), Hex(self.1), Hex(self.2)])
-    }
-}
-impl DebugHexF16 for float16x8x4_t {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        debug_simd_finish(f, "float16x8x4_t", &[Hex(self.0), Hex(self.1), Hex(self.2), Hex(self.3)])
-    }
-}
- "#;
+pub const PLATFORM_RUST_DEFINITIONS: &str = "";
 
 pub const PLATFORM_RUST_CFGS: &str = r#"
 #![cfg_attr(target_arch = "arm", feature(stdarch_arm_neon_intrinsics))]
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index bd943c211e..a14d7ef05f 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -368,19 +368,8 @@ pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
     /// Generates a std::cout for the intrinsics results that will match the
     /// rust debug output format for the return type. The generated line assumes
     /// there is an int i in scope which is the current pass number.
-    ///
-    /// The `intrinsic-test` crate compares the output of C and Rust intrinsics. Currently, It uses
-    /// a string representation of the output value to compare. In C, f16 values are currently printed
-    /// as hexadecimal integers. Since https://github.com/rust-lang/rust/pull/127013, rust does print
-    /// them as decimal floating point values. To keep the intrinsics tests working, for now, format
-    /// vectors containing f16 values like C prints them.
     fn print_result_rust(&self) -> String {
-        let return_value = match self.kind() {
-            TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)",
-            _ => "format_args!(\"{__return_value:.150?}\")",
-        };
-
-        String::from(return_value)
+        String::from("format_args!(\"{__return_value:.150?}\")")
     }
 
     /// To enable architecture-specific logic
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 40607d8491..bf943b795c 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -142,71 +142,6 @@ fn debug_simd_finish<T: core::fmt::Debug, const N: usize>(
     )
 }
 
-#[repr(transparent)]
-struct Hex<T>(T);
-
-impl<T: DebugHexF16> core::fmt::Debug for Hex<T> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        <T as DebugHexF16>::fmt(&self.0, f)
-    }
-}
-
-fn debug_f16<T: DebugHexF16>(x: T) -> impl core::fmt::Debug {
-    Hex(x)
-}
-
-trait DebugHexF16 {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result;
-}
-
-impl DebugHexF16 for f16 {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "{:#06x?}", self.to_bits())
-    }
-}
-
-impl DebugHexF16 for __m128h {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 8]>(*self) };
-        debug_simd_finish(f, "__m128h", &array)
-    }
-}
-
-impl DebugHexF16 for __m128i {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 8]>(*self) };
-        debug_simd_finish(f, "__m128i", &array)
-    }
-}
-
-impl DebugHexF16 for __m256h {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 16]>(*self) };
-        debug_simd_finish(f, "__m256h", &array)
-    }
-}
-
-impl DebugHexF16 for __m256i {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 16]>(*self) };
-        debug_simd_finish(f, "__m256i", &array)
-    }
-}
-
-impl DebugHexF16 for __m512h {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 32]>(*self) };
-        debug_simd_finish(f, "__m512h", &array)
-    }
-}
-
-impl DebugHexF16 for __m512i {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 32]>(*self) };
-        debug_simd_finish(f, "__m512i", &array)
-    }
-}
-
 trait DebugAs<T> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result;
 }
@@ -232,7 +167,7 @@ macro_rules! impl_debug_as {
     };
 }
 
-impl_debug_as!(__m128i, "__m128i", 128, [u8, i8, u16, i16, u32, i32, u64, i64]);
+impl_debug_as!(__m128i, "__m128i", 128, [u8, i8, u16, i16, u32, i32, u64, i64, f16]);
 impl_debug_as!(__m256i, "__m256i", 256, [u8, i8, u16, i16, u32, i32, u64, i64]);
 impl_debug_as!(__m512i, "__m512i", 512, [u8, i8, u16, i16, u32, i32, u64, i64]);
 impl_debug_as!(__m128h, "__m128h", 128, [f32]);
@@ -336,11 +271,7 @@ pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
 pub const PLATFORM_C_DEFINITIONS: &str = r#"
 
 std::ostream& operator<<(std::ostream& os, _Float16 value) {
-    uint16_t temp = 0;
-    memcpy(&temp, &value, sizeof(_Float16));
-    std::stringstream ss;
-    ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
-    os << ss.str();
+    os << static_cast<float>(value);
     return os;
 }
 
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index d6cb938096..2391ee9c2d 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -172,29 +172,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     /// rust debug output format for the return type. The generated line assumes
     /// there is an int i in scope which is the current pass number.
     fn print_result_c(&self, indentation: Indentation, additional: &str) -> String {
-        let lanes = if self.num_vectors() > 1 {
-            (0..self.num_vectors())
-                .map(|vector| {
-                    format!(
-                        r#""{ty}(" << {lanes} << ")""#,
-                        ty = self.c_single_vector_type(),
-                        lanes = (0..self.num_lanes())
-                            .map(move |idx| -> std::string::String {
-                                format!(
-                                    "{cast}{lane_fn}(__return_value.val[{vector}], {lane})",
-                                    cast = self.generate_final_type_cast(),
-                                    lane_fn = self.get_lane_function(),
-                                    lane = idx,
-                                    vector = vector,
-                                )
-                            })
-                            .collect::<Vec<_>>()
-                            .join(r#" << ", " << "#)
-                    )
-                })
-                .collect::<Vec<_>>()
-                .join(r#" << ", " << "#)
-        } else if self.num_lanes() > 1 {
+        let lanes = if self.num_lanes() > 1 {
             (0..self.num_lanes())
                 .map(|idx| -> std::string::String {
                     let cast_type = self.c_promotion();
@@ -283,12 +261,9 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
 
     fn print_result_rust(&self) -> String {
         let return_value = match self.kind() {
-            TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)".to_string(),
-            TypeKind::Float
-                if self.inner_size() == 32
-                    && ["__m512h"].contains(&self.param.type_data.as_str()) =>
-            {
-                "debug_as::<_, f32>(__return_value)".to_string()
+            // `_mm{256}_cvtps_ph` has return type __m128i but contains f16 values
+            TypeKind::Float if self.param.type_data == "__m128i" => {
+                "format_args!(\"{:.150?}\", debug_as::<_, f16>(__return_value))".to_string()
             }
             TypeKind::Int(_)
                 if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) =>
@@ -463,6 +438,17 @@ impl X86IntrinsicType {
                     }
                 }
 
+                // a few intrinsics have wrong `etype` field in the XML
+                // - _mm512_reduce_add_ph
+                // - _mm512_reduce_mul_ph
+                // - _mm512_reduce_min_ph
+                // - _mm512_reduce_max_ph
+                // - _mm512_conj_pch
+                if param.type_data == "__m512h" && param.etype == "FP32" {
+                    data.bit_len = Some(16);
+                    data.simd_len = Some(32);
+                }
+
                 let mut result = X86IntrinsicType {
                     data,
                     param: param.clone(),

From f1c39caf0a484cecf28d67a7c07fe24230996afd Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 29 Nov 2025 12:02:48 +0530
Subject: [PATCH 035/326] correct behavior of some intrinsics

---
 crates/core_arch/src/x86/avx512bw.rs   | 16 ++++++++--------
 crates/core_arch/src/x86/avx512f.rs    | 14 ++++++--------
 crates/core_arch/src/x86/avx512fp16.rs |  4 ++--
 3 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index c7f271d22e..0073bdeb4a 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -10705,9 +10705,13 @@ pub fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpmovwb))]
 pub fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
-        let convert = _mm_cvtepi16_epi8(a).as_i8x16();
-        let k: __mmask16 = 0b11111111_11111111 & k as __mmask16;
-        transmute(simd_select_bitmask(k, convert, src.as_i8x16()))
+        let a = _mm_cvtepi16_epi8(a).as_i8x16();
+        let src = simd_shuffle!(
+            src.as_i8x16(),
+            i8x16::ZERO,
+            [0, 1, 2, 3, 4, 5, 6, 7, 16, 16, 16, 16, 16, 16, 16, 16]
+        );
+        simd_select_bitmask(k as u16, a, src).as_m128i()
     }
 }
 
@@ -10719,11 +10723,7 @@ pub fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
 pub fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
-    unsafe {
-        let convert = _mm_cvtepi16_epi8(a).as_i8x16();
-        let k: __mmask16 = 0b11111111_11111111 & k as __mmask16;
-        transmute(simd_select_bitmask(k, convert, i8x16::ZERO))
-    }
+    _mm_mask_cvtepi16_epi8(_mm_setzero_si128(), k, a)
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst.
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 8c57fc2011..8d3ddbd964 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -11149,10 +11149,7 @@ pub fn _mm256_maskz_cvtpd_ps(k: __mmask8, a: __m256d) -> __m128 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtpd2ps))]
 pub fn _mm_mask_cvtpd_ps(src: __m128, k: __mmask8, a: __m128d) -> __m128 {
-    unsafe {
-        let convert = _mm_cvtpd_ps(a);
-        transmute(simd_select_bitmask(k, convert.as_f32x4(), src.as_f32x4()))
-    }
+    unsafe { vcvtpd2ps128(a.as_f64x2(), src.as_f32x4(), k).as_m128() }
 }
 
 /// Convert packed double-precision (64-bit) floating-point elements in a to packed single-precision (32-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -11259,10 +11256,7 @@ pub fn _mm256_maskz_cvtpd_epi32(k: __mmask8, a: __m256d) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtpd2dq))]
 pub fn _mm_mask_cvtpd_epi32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i {
-    unsafe {
-        let convert = _mm_cvtpd_epi32(a);
-        transmute(simd_select_bitmask(k, convert.as_i32x4(), src.as_i32x4()))
-    }
+    unsafe { vcvtpd2dq128(a.as_f64x2(), src.as_i32x4(), k).as_m128i() }
 }
 
 /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -42483,9 +42477,13 @@ unsafe extern "C" {
 
     #[link_name = "llvm.x86.avx512.mask.cvtps2pd.512"]
     fn vcvtps2pd(a: f32x8, src: f64x8, mask: u8, sae: i32) -> f64x8;
+    #[link_name = "llvm.x86.avx512.mask.cvtpd2ps"]
+    fn vcvtpd2ps128(a: f64x2, src: f32x4, mask: u8) -> f32x4;
     #[link_name = "llvm.x86.avx512.mask.cvtpd2ps.512"]
     fn vcvtpd2ps(a: f64x8, src: f32x8, mask: u8, rounding: i32) -> f32x8;
 
+    #[link_name = "llvm.x86.avx512.mask.cvtpd2dq.128"]
+    fn vcvtpd2dq128(a: f64x2, src: i32x4, k: u8) -> i32x4;
     #[link_name = "llvm.x86.avx512.mask.cvtpd2dq.512"]
     fn vcvtpd2dq(a: f64x8, src: i32x8, mask: u8, rounding: i32) -> i32x8;
 
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 13cae45d0f..01b1be364f 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -1007,7 +1007,7 @@ pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 {
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
 pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 {
-    _mm_comi_sh::<_CMP_NEQ_OS>(a, b)
+    _mm_comi_sh::<_CMP_NEQ_US>(a, b)
 }
 
 /// Compare the lower half-precision (16-bit) floating-point elements in a and b for equality, and
@@ -1073,7 +1073,7 @@ pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 {
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
 pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 {
-    _mm_comi_sh::<_CMP_NEQ_OQ>(a, b)
+    _mm_comi_sh::<_CMP_NEQ_UQ>(a, b)
 }
 
 /// Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into

From 5536f1c624ee503befa88cf5e1d9fa79d8fc47fc Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 29 Nov 2025 11:53:23 +0530
Subject: [PATCH 036/326] fix intrinsic-test to use `core_arch::arch` rather
 than `std::arch`

---
 crates/intrinsic-test/missing_x86.txt   | 22 +++++-----------------
 crates/intrinsic-test/src/x86/config.rs |  2 +-
 2 files changed, 6 insertions(+), 18 deletions(-)

diff --git a/crates/intrinsic-test/missing_x86.txt b/crates/intrinsic-test/missing_x86.txt
index 11c3eeba90..f88a125bfd 100644
--- a/crates/intrinsic-test/missing_x86.txt
+++ b/crates/intrinsic-test/missing_x86.txt
@@ -51,29 +51,17 @@ _mm_sm3rnds2_epi32
 # SDE ERROR: Cannot execute XGETBV with ECX != 0
 _xgetbv
 
-# Miscellaneous issues that can be fixed first
-_kshiftli_mask16
-_kshiftli_mask32
-_kshiftli_mask64
-_kshiftli_mask8
-_kshiftri_mask16
-_kshiftri_mask32
-_kshiftri_mask64
-_kshiftri_mask8
+# top bits are undefined, unclear how to test these
 _mm256_castsi128_si256
-_mm256_extract_epi16
-_mm256_extract_epi8
 _mm512_castsi128_si512
 _mm512_castsi256_si512
-# _mm512_conj_pch
+
+# Clang bug
+_mm256_extract_epi16
+_mm256_extract_epi8
 _mm512_mask_reduce_max_pd
 _mm512_mask_reduce_max_ps
 _mm512_mask_reduce_min_pd
 _mm512_mask_reduce_min_ps
-_mm_comineq_sh
 _mm_extract_epi16
 _mm_extract_epi8
-_mm_mask_cvtepi16_epi8
-_mm_mask_cvtpd_epi32
-_mm_mask_cvtpd_ps
-_mm_ucomineq_sh
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index bf943b795c..491dbb5147 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -5,7 +5,7 @@ pub const NOTICE: &str = "\
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.
 pub const PLATFORM_RUST_DEFINITIONS: &str = r#"
-use std::arch::x86_64::*;
+use core_arch::arch::x86_64::*;
 
 #[inline]
 unsafe fn _mm_loadu_ph_to___m128i(mem_addr: *const f16) -> __m128i {

From b085e90e19d31b8bff5b1ca045d9b6e5db9b8cfd Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sun, 5 Oct 2025 05:29:09 +0530
Subject: [PATCH 037/326] Make `cpuid` safe and update docs

---
 crates/core_arch/src/x86/cpuid.rs | 40 ++++++++++++++++++-------------
 crates/core_arch/src/x86/xsave.rs |  2 +-
 2 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/crates/core_arch/src/x86/cpuid.rs b/crates/core_arch/src/x86/cpuid.rs
index 0634f10a99..84dcf75492 100644
--- a/crates/core_arch/src/x86/cpuid.rs
+++ b/crates/core_arch/src/x86/cpuid.rs
@@ -28,12 +28,21 @@ pub struct CpuidResult {
 /// Returns the result of the `cpuid` instruction for a given `leaf` (`EAX`)
 /// and `sub_leaf` (`ECX`).
 ///
-/// The highest-supported leaf value is returned by the first tuple argument of
-/// [`__get_cpuid_max(0)`](fn.__get_cpuid_max.html). For leaves containing
-/// sub-leaves, the second tuple argument returns the highest-supported
-/// sub-leaf value.
+/// There are two types of information leaves - basic leaves (with `leaf < 0x8000000`)
+/// and extended leaves (with `leaf >= 0x80000000`). The highest supported basic and
+/// extended leaves can be obtained by calling CPUID with `0` and `0x80000000`,
+/// respectively, and reading the value in the `EAX` register. If the leaf supports
+/// more than one sub-leaf, then the procedure of obtaining the highest supported
+/// sub-leaf, as well as the behavior if a invalid sub-leaf value is passed, depends
+/// on the specific leaf.
 ///
-/// The [CPUID Wikipedia page][wiki_cpuid] contains how to query which
+/// If the `leaf` value is higher than the maximum supported basic or extended leaf
+/// for the processor, this returns the information for the highest supported basic
+/// information leaf (with the passed `sub_leaf` value). If the `leaf` value is less
+/// than or equal to the highest basic or extended leaf value, but the leaf is not
+/// supported on the processor, all zeros are returned.
+///
+/// The [CPUID Wikipedia page][wiki_cpuid] contains information on how to query which
 /// information using the `EAX` and `ECX` registers, and the interpretation of
 /// the results returned in `EAX`, `EBX`, `ECX`, and `EDX`.
 ///
@@ -49,7 +58,7 @@ pub struct CpuidResult {
 #[inline]
 #[cfg_attr(test, assert_instr(cpuid))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
+pub fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
     let eax;
     let ebx;
     let ecx;
@@ -58,7 +67,7 @@ pub unsafe fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
     // LLVM sometimes reserves `ebx` for its internal use, we so we need to use
     // a scratch register for it instead.
     #[cfg(target_arch = "x86")]
-    {
+    unsafe {
         asm!(
             "mov {0}, ebx",
             "cpuid",
@@ -71,7 +80,7 @@ pub unsafe fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
         );
     }
     #[cfg(target_arch = "x86_64")]
-    {
+    unsafe {
         asm!(
             "mov {0:r}, rbx",
             "cpuid",
@@ -86,27 +95,26 @@ pub unsafe fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
     CpuidResult { eax, ebx, ecx, edx }
 }
 
+/// Calls CPUID with the provided `leaf` value, with `sub_leaf` set to 0.
 /// See [`__cpuid_count`](fn.__cpuid_count.html).
 #[inline]
 #[cfg_attr(test, assert_instr(cpuid))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn __cpuid(leaf: u32) -> CpuidResult {
+pub fn __cpuid(leaf: u32) -> CpuidResult {
     __cpuid_count(leaf, 0)
 }
 
-/// Returns the highest-supported `leaf` (`EAX`) and sub-leaf (`ECX`) `cpuid`
-/// values.
+/// Returns the EAX and EBX register after calling CPUID with the provided `leaf`,
+/// with `sub_leaf` set to 0.
 ///
-/// If `cpuid` is supported, and `leaf` is zero, then the first tuple argument
-/// contains the highest `leaf` value that `cpuid` supports. For `leaf`s
-/// containing sub-leafs, the second tuple argument contains the
-/// highest-supported sub-leaf value.
+/// If `leaf` if 0 or `0x80000000`, the first tuple argument contains the maximum
+/// supported basic or extended leaf, respectively.
 ///
 /// See also [`__cpuid`](fn.__cpuid.html) and
 /// [`__cpuid_count`](fn.__cpuid_count.html).
 #[inline]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn __get_cpuid_max(leaf: u32) -> (u32, u32) {
+pub fn __get_cpuid_max(leaf: u32) -> (u32, u32) {
     let CpuidResult { eax, ebx, .. } = __cpuid(leaf);
     (eax, ebx)
 }
diff --git a/crates/core_arch/src/x86/xsave.rs b/crates/core_arch/src/x86/xsave.rs
index 190cef929e..653eb28c42 100644
--- a/crates/core_arch/src/x86/xsave.rs
+++ b/crates/core_arch/src/x86/xsave.rs
@@ -184,7 +184,7 @@ mod tests {
             // `CPUID.(EAX=0DH,ECX=0):ECX` contains the size required to hold all supported xsave
             // components. `EBX` contains the size required to hold all xsave components currently
             // enabled in `XCR0`. We are using `ECX` to ensure enough space in all scenarios
-            let CpuidResult { ecx, .. } = unsafe { __cpuid(0x0d) };
+            let CpuidResult { ecx, .. } = __cpuid(0x0d);
 
             XsaveArea {
                 data: vec![AlignedArray([0; 64]); ecx.div_ceil(64) as usize].into_boxed_slice(),

From c9e9b01734f5f3e2cb12062a4abcdad51675e327 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 2 Dec 2025 00:22:05 +0530
Subject: [PATCH 038/326] use `wrapping_add` for `_kadd` intrinsics

---
 crates/core_arch/src/x86/avx512bw.rs | 4 ++--
 crates/core_arch/src/x86/avx512dq.rs | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 0073bdeb4a..5d17d42532 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -10254,7 +10254,7 @@ pub fn _cvtu32_mask32(a: u32) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
-    a + b
+    a.wrapping_add(b)
 }
 
 /// Add 64-bit masks in a and b, and store the result in k.
@@ -10264,7 +10264,7 @@ pub fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
-    a + b
+    a.wrapping_add(b)
 }
 
 /// Compute the bitwise AND of 32-bit masks a and b, and store the result in k.
diff --git a/crates/core_arch/src/x86/avx512dq.rs b/crates/core_arch/src/x86/avx512dq.rs
index afeb548a55..a691687502 100644
--- a/crates/core_arch/src/x86/avx512dq.rs
+++ b/crates/core_arch/src/x86/avx512dq.rs
@@ -4486,7 +4486,7 @@ pub fn _cvtu32_mask8(a: u32) -> __mmask8 {
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
-    a + b
+    a.wrapping_add(b)
 }
 
 /// Add 8-bit masks a and b, and store the result in dst.
@@ -4496,7 +4496,7 @@ pub fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _kadd_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
-    a + b
+    a.wrapping_add(b)
 }
 
 /// Bitwise AND of 8-bit masks a and b, and store the result in dst.

From 333658f6d484fd47fb1d7d44c7d1910d9bd4dd35 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 4 Nov 2025 19:54:11 +0530
Subject: [PATCH 039/326] feat: configure test-files to run all intrinsics in
 the same process

---
 crates/intrinsic-test/src/common/gen_c.rs    | 16 ++++------------
 crates/intrinsic-test/src/common/gen_rust.rs | 12 +++---------
 2 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index 04741e4f80..30f359a27e 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -147,22 +147,14 @@ pub fn write_main_cpp<'a>(
     }
 
     writeln!(w, "int main(int argc, char **argv) {{")?;
-    writeln!(w, "    std::string intrinsic_name = argv[1];")?;
-
-    writeln!(w, "    if (false) {{")?;
 
     for intrinsic in intrinsics {
-        writeln!(w, "    }} else if (intrinsic_name == \"{intrinsic}\") {{")?;
-        writeln!(w, "        return run_{intrinsic}();")?;
+        writeln!(w, "    std::cout << \"############\" << std::endl;")?;
+        writeln!(w, "    std::cout << \"{intrinsic}\" << std::endl;")?;
+        writeln!(w, "    run_{intrinsic}();\n")?;
     }
 
-    writeln!(w, "    }} else {{")?;
-    writeln!(
-        w,
-        "        std::cerr << \"Unknown command: \" << intrinsic_name << \"\\n\";"
-    )?;
-    writeln!(w, "        return -1;")?;
-    writeln!(w, "    }}")?;
+    writeln!(w, "    return 0;")?;
 
     writeln!(w, "}}")?;
 
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index c8d815e46e..afc6ca4556 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -86,18 +86,12 @@ pub fn write_main_rs<'a>(
 
     writeln!(w, "fn main() {{")?;
 
-    writeln!(w, "    match std::env::args().nth(1).unwrap().as_str() {{")?;
-
     for binary in intrinsics {
-        writeln!(w, "        \"{binary}\" => run_{binary}(),")?;
+        writeln!(w, "    println!(\"############\");")?;
+        writeln!(w, "    println!(\"{binary}\");")?;
+        writeln!(w, "    run_{binary}();\n")?;
     }
 
-    writeln!(
-        w,
-        "        other => panic!(\"unknown intrinsic `{{}}`\", other),"
-    )?;
-
-    writeln!(w, "    }}")?;
     writeln!(w, "}}")?;
 
     Ok(())

From 49ca95e353b8020fc733ce7d8ae650348481cbf9 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 4 Nov 2025 21:54:56 +0530
Subject: [PATCH 040/326] feat: modified the compare function to check one huge
 output stream instead of len(intrinsic) output streams

---
 crates/intrinsic-test/src/common/compare.rs | 145 ++++++++++----------
 1 file changed, 72 insertions(+), 73 deletions(-)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index c0459b743a..96a0bb94aa 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -1,6 +1,7 @@
 use super::cli::FailureReason;
+use itertools::Itertools;
 use rayon::prelude::*;
-use std::process::Command;
+use std::{collections::HashMap, process::Command};
 
 fn runner_command(runner: &str) -> Command {
     let mut it = runner.split_whitespace();
@@ -11,85 +12,83 @@ fn runner_command(runner: &str) -> Command {
 }
 
 pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target: &str) -> bool {
-    let intrinsics = intrinsic_name_list
-        .par_iter()
-        .filter_map(|intrinsic_name| {
-            let c = runner_command(runner)
-                .arg("./intrinsic-test-programs")
-                .arg(intrinsic_name)
-                .current_dir("c_programs")
-                .output();
-
-            let rust = runner_command(runner)
-                .arg(format!("./target/{target}/release/intrinsic-test-programs"))
-                .arg(intrinsic_name)
-                .current_dir("rust_programs")
-                .output();
-
-            let (c, rust) = match (c, rust) {
-                (Ok(c), Ok(rust)) => (c, rust),
-                a => panic!("{a:#?}"),
-            };
-
-            if !c.status.success() {
-                error!(
-                    "Failed to run C program for intrinsic `{intrinsic_name}`\nstdout: {stdout}\nstderr: {stderr}",
-                    stdout = std::str::from_utf8(&c.stdout).unwrap_or(""),
-                    stderr = std::str::from_utf8(&c.stderr).unwrap_or(""),
-                );
-                return Some(FailureReason::RunC(intrinsic_name.clone()));
-            }
-
-            if !rust.status.success() {
-                error!(
-                    "Failed to run Rust program for intrinsic `{intrinsic_name}`\nstdout: {stdout}\nstderr: {stderr}",
-                    stdout = std::str::from_utf8(&rust.stdout).unwrap_or(""),
-                    stderr = std::str::from_utf8(&rust.stderr).unwrap_or(""),
-                );
-                return Some(FailureReason::RunRust(intrinsic_name.clone()));
-            }
+    let c = runner_command(runner)
+        .arg("./intrinsic-test-programs")
+        .current_dir("c_programs")
+        .output();
 
-            info!("Comparing intrinsic: {intrinsic_name}");
+    let rust = runner_command(runner)
+        .arg(format!("./target/{target}/release/intrinsic-test-programs"))
+        .current_dir("rust_programs")
+        .output();
+    
+    let (c, rust) = match (c, rust) {
+        (Ok(c), Ok(rust)) => (c, rust),
+        a => panic!("{a:#?}"),
+    };
+    
+    if !c.status.success() {
+        error!(
+            "Failed to run C program.\nstdout: {stdout}\nstderr: {stderr}",
+            stdout = std::str::from_utf8(&c.stdout).unwrap_or(""),
+            stderr = std::str::from_utf8(&c.stderr).unwrap_or(""),
+        );
+    }
+    
+    if !rust.status.success() {
+        error!(
+            "Failed to run Rust program.\nstdout: {stdout}\nstderr: {stderr}",
+            stdout = std::str::from_utf8(&rust.stdout).unwrap_or(""),
+            stderr = std::str::from_utf8(&rust.stderr).unwrap_or(""),
+        );
+    }
 
-            let c = std::str::from_utf8(&c.stdout)
-                .unwrap()
-                .to_lowercase()
-                .replace("-nan", "nan");
-            let rust = std::str::from_utf8(&rust.stdout)
-                .unwrap()
-                .to_lowercase()
-                .replace("-nan", "nan");
+    let c = std::str::from_utf8(&c.stdout)
+        .unwrap()
+        .to_lowercase()
+        .replace("-nan", "nan");
+    let rust = std::str::from_utf8(&rust.stdout)
+        .unwrap()
+        .to_lowercase()
+        .replace("-nan", "nan");
+    
+    let c_output_map = c.split("############")
+        .filter_map(|output| output.trim().split_once("\n"))
+        .collect::<HashMap<&str, &str>>();
+    let rust_output_map = rust.split("############")
+        .filter_map(|output| output.trim().split_once("\n"))
+        .collect::<HashMap<&str, &str>>();
 
-            if c == rust {
-                None
-            } else {
-                Some(FailureReason::Difference(intrinsic_name.clone(), c, rust))
-            }
-        })
-        .collect::<Vec<_>>();
-
-    intrinsics.iter().for_each(|reason| match reason {
-        FailureReason::Difference(intrinsic, c, rust) => {
+    let intrinsics = c_output_map.keys().chain(rust_output_map.keys()).unique().collect_vec();
+    let intrinsics_diff_count = intrinsics
+        .par_iter()
+        .filter_map(|&&intrinsic| {
             println!("Difference for intrinsic: {intrinsic}");
-            let diff = diff::lines(c, rust);
-            diff.iter().for_each(|diff| match diff {
-                diff::Result::Left(c) => println!("C: {c}"),
-                diff::Result::Right(rust) => println!("Rust: {rust}"),
-                diff::Result::Both(_, _) => (),
-            });
+            let c_output = c_output_map.get(intrinsic).unwrap();
+            let rust_output = rust_output_map.get(intrinsic).unwrap();
+            let diff = diff::lines(c_output, rust_output);
+            let diff_count = diff.into_iter().filter_map(|diff| match diff {
+                diff::Result::Left(c) => {
+                    println!("C: {c}");
+                    Some(c)
+                }
+                diff::Result::Right(rust) => {
+                    println!("Rust: {rust}");
+                    Some(rust)
+                }
+                diff::Result::Both(_, _) => None,
+            }).count();
             println!("****************************************************************");
-        }
-        FailureReason::RunC(intrinsic) => {
-            println!("Failed to run C program for intrinsic {intrinsic}")
-        }
-        FailureReason::RunRust(intrinsic) => {
-            println!("Failed to run rust program for intrinsic {intrinsic}")
-        }
-    });
+            if diff_count > 0 {
+                Some(intrinsic)
+            } else { None }
+        }).count();
+
     println!(
         "{} differences found (tested {} intrinsics)",
-        intrinsics.len(),
+        intrinsics_diff_count,
         intrinsic_name_list.len()
     );
-    intrinsics.is_empty()
+
+    intrinsics_diff_count == 0
 }

From b7ee5cf0b3a6b21cc153318152d12a247903bdee Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 4 Nov 2025 22:02:20 +0530
Subject: [PATCH 041/326] chore: formatting checks

---
 crates/intrinsic-test/src/common/cli.rs     |  6 ---
 crates/intrinsic-test/src/common/compare.rs | 53 +++++++++++++--------
 2 files changed, 32 insertions(+), 27 deletions(-)

diff --git a/crates/intrinsic-test/src/common/cli.rs b/crates/intrinsic-test/src/common/cli.rs
index 461ab542ea..ff34ef3d2d 100644
--- a/crates/intrinsic-test/src/common/cli.rs
+++ b/crates/intrinsic-test/src/common/cli.rs
@@ -7,12 +7,6 @@ pub enum Language {
     C,
 }
 
-pub enum FailureReason {
-    RunC(String),
-    RunRust(String),
-    Difference(String, String, String),
-}
-
 /// Intrinsic test tool
 #[derive(clap::Parser)]
 #[command(
diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 96a0bb94aa..4ab2a33657 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -1,4 +1,3 @@
-use super::cli::FailureReason;
 use itertools::Itertools;
 use rayon::prelude::*;
 use std::{collections::HashMap, process::Command};
@@ -21,12 +20,12 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .arg(format!("./target/{target}/release/intrinsic-test-programs"))
         .current_dir("rust_programs")
         .output();
-    
+
     let (c, rust) = match (c, rust) {
         (Ok(c), Ok(rust)) => (c, rust),
         a => panic!("{a:#?}"),
     };
-    
+
     if !c.status.success() {
         error!(
             "Failed to run C program.\nstdout: {stdout}\nstderr: {stderr}",
@@ -34,7 +33,7 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
             stderr = std::str::from_utf8(&c.stderr).unwrap_or(""),
         );
     }
-    
+
     if !rust.status.success() {
         error!(
             "Failed to run Rust program.\nstdout: {stdout}\nstderr: {stderr}",
@@ -51,15 +50,21 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .unwrap()
         .to_lowercase()
         .replace("-nan", "nan");
-    
-    let c_output_map = c.split("############")
+
+    let c_output_map = c
+        .split("############")
         .filter_map(|output| output.trim().split_once("\n"))
         .collect::<HashMap<&str, &str>>();
-    let rust_output_map = rust.split("############")
+    let rust_output_map = rust
+        .split("############")
         .filter_map(|output| output.trim().split_once("\n"))
         .collect::<HashMap<&str, &str>>();
 
-    let intrinsics = c_output_map.keys().chain(rust_output_map.keys()).unique().collect_vec();
+    let intrinsics = c_output_map
+        .keys()
+        .chain(rust_output_map.keys())
+        .unique()
+        .collect_vec();
     let intrinsics_diff_count = intrinsics
         .par_iter()
         .filter_map(|&&intrinsic| {
@@ -67,22 +72,28 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
             let c_output = c_output_map.get(intrinsic).unwrap();
             let rust_output = rust_output_map.get(intrinsic).unwrap();
             let diff = diff::lines(c_output, rust_output);
-            let diff_count = diff.into_iter().filter_map(|diff| match diff {
-                diff::Result::Left(c) => {
-                    println!("C: {c}");
-                    Some(c)
-                }
-                diff::Result::Right(rust) => {
-                    println!("Rust: {rust}");
-                    Some(rust)
-                }
-                diff::Result::Both(_, _) => None,
-            }).count();
+            let diff_count = diff
+                .into_iter()
+                .filter_map(|diff| match diff {
+                    diff::Result::Left(c) => {
+                        println!("C: {c}");
+                        Some(c)
+                    }
+                    diff::Result::Right(rust) => {
+                        println!("Rust: {rust}");
+                        Some(rust)
+                    }
+                    diff::Result::Both(_, _) => None,
+                })
+                .count();
             println!("****************************************************************");
             if diff_count > 0 {
                 Some(intrinsic)
-            } else { None }
-        }).count();
+            } else {
+                None
+            }
+        })
+        .count();
 
     println!(
         "{} differences found (tested {} intrinsics)",

From 3438ce2dbadbc8e17c957631694b1415b9597ffc Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 4 Nov 2025 22:09:13 +0530
Subject: [PATCH 042/326] feat: increase TEST_SAMPLE_INTRINSICS_PERCENTAGE of
 x86_64 to 30%

---
 ci/intrinsic-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index a8f96897bc..2b40044462 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -75,7 +75,7 @@ case ${TARGET} in
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
-        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=5}"
+        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=30}"
         ;;
     *)
         ;;

From c850c0c38ab9267241d48003d281c6f34b53ec26 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 4 Nov 2025 22:52:33 +0530
Subject: [PATCH 043/326] fix: update the comparison algorithm for cleaner
 comparisons

---
 crates/intrinsic-test/src/common/compare.rs | 28 ++++++++++-----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 4ab2a33657..38fa8dc0ec 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -68,31 +68,31 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
     let intrinsics_diff_count = intrinsics
         .par_iter()
         .filter_map(|&&intrinsic| {
-            println!("Difference for intrinsic: {intrinsic}");
             let c_output = c_output_map.get(intrinsic).unwrap();
             let rust_output = rust_output_map.get(intrinsic).unwrap();
             let diff = diff::lines(c_output, rust_output);
-            let diff_count = diff
+            let diffs = diff
                 .into_iter()
                 .filter_map(|diff| match diff {
-                    diff::Result::Left(c) => {
-                        println!("C: {c}");
-                        Some(c)
-                    }
-                    diff::Result::Right(rust) => {
-                        println!("Rust: {rust}");
-                        Some(rust)
-                    }
+                    diff::Result::Left(_) | diff::Result::Right(_) => Some(diff),
                     diff::Result::Both(_, _) => None,
                 })
-                .count();
-            println!("****************************************************************");
-            if diff_count > 0 {
-                Some(intrinsic)
+                .collect_vec();
+            if diffs.len() > 0 {
+                Some((intrinsic, diffs))
             } else {
                 None
             }
         })
+        .inspect(|(intrinsic, diffs)| {
+            println!("Difference for intrinsic: {intrinsic}");
+            diffs.into_iter().for_each(|diff| match diff {
+                diff::Result::Left(c) => println!("C: {c}"),
+                diff::Result::Right(rust) => println!("Rust: {rust}"),
+                _ => (),
+            });
+            println!("****************************************************************");
+        })
         .count();
 
     println!(

From ae69ae4700018d63335a39ab69995a14afd7a999 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 4 Nov 2025 23:34:33 +0530
Subject: [PATCH 044/326] feat: add equality checks to reduce computation spent
 on equal outputs

---
 crates/intrinsic-test/src/common/compare.rs | 50 ++++++++++++---------
 1 file changed, 29 insertions(+), 21 deletions(-)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 38fa8dc0ec..b89059f9eb 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -11,16 +11,20 @@ fn runner_command(runner: &str) -> Command {
 }
 
 pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target: &str) -> bool {
-    let c = runner_command(runner)
-        .arg("./intrinsic-test-programs")
-        .current_dir("c_programs")
-        .output();
-
-    let rust = runner_command(runner)
-        .arg(format!("./target/{target}/release/intrinsic-test-programs"))
-        .current_dir("rust_programs")
-        .output();
-
+    let (c, rust) = rayon::join(
+        || {
+            runner_command(runner)
+                .arg("./intrinsic-test-programs")
+                .current_dir("c_programs")
+                .output()
+        },
+        || {
+            runner_command(runner)
+                .arg(format!("./target/{target}/release/intrinsic-test-programs"))
+                .current_dir("rust_programs")
+                .output()
+        },
+    );
     let (c, rust) = match (c, rust) {
         (Ok(c), Ok(rust)) => (c, rust),
         a => panic!("{a:#?}"),
@@ -70,18 +74,22 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .filter_map(|&&intrinsic| {
             let c_output = c_output_map.get(intrinsic).unwrap();
             let rust_output = rust_output_map.get(intrinsic).unwrap();
-            let diff = diff::lines(c_output, rust_output);
-            let diffs = diff
-                .into_iter()
-                .filter_map(|diff| match diff {
-                    diff::Result::Left(_) | diff::Result::Right(_) => Some(diff),
-                    diff::Result::Both(_, _) => None,
-                })
-                .collect_vec();
-            if diffs.len() > 0 {
-                Some((intrinsic, diffs))
-            } else {
+            if rust_output.to_string() == c_output.to_string() {
                 None
+            } else {
+                let diff = diff::lines(c_output, rust_output);
+                let diffs = diff
+                    .into_iter()
+                    .filter_map(|diff| match diff {
+                        diff::Result::Left(_) | diff::Result::Right(_) => Some(diff),
+                        diff::Result::Both(_, _) => None,
+                    })
+                    .collect_vec();
+                if diffs.len() > 0 {
+                    Some((intrinsic, diffs))
+                } else {
+                    None
+                }
             }
         })
         .inspect(|(intrinsic, diffs)| {

From c3c3685c3b005d81a35a53691d9545061c59e123 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 5 Nov 2025 11:20:12 +0530
Subject: [PATCH 045/326] feat: extract the delimiter to a const value for
 uniformity

---
 crates/intrinsic-test/src/common/compare.rs  | 9 +++++----
 crates/intrinsic-test/src/common/gen_c.rs    | 6 +++++-
 crates/intrinsic-test/src/common/gen_rust.rs | 8 ++++----
 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index b89059f9eb..7c5d87b51f 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -2,6 +2,7 @@ use itertools::Itertools;
 use rayon::prelude::*;
 use std::{collections::HashMap, process::Command};
 
+pub const INTRINSIC_DELIMITER: &str = "############";
 fn runner_command(runner: &str) -> Command {
     let mut it = runner.split_whitespace();
     let mut cmd = Command::new(it.next().unwrap());
@@ -27,7 +28,7 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
     );
     let (c, rust) = match (c, rust) {
         (Ok(c), Ok(rust)) => (c, rust),
-        a => panic!("{a:#?}"),
+        failure => panic!("Failed to run: {failure:#?}"),
     };
 
     if !c.status.success() {
@@ -56,11 +57,11 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .replace("-nan", "nan");
 
     let c_output_map = c
-        .split("############")
+        .split(INTRINSIC_DELIMITER)
         .filter_map(|output| output.trim().split_once("\n"))
         .collect::<HashMap<&str, &str>>();
     let rust_output_map = rust
-        .split("############")
+        .split(INTRINSIC_DELIMITER)
         .filter_map(|output| output.trim().split_once("\n"))
         .collect::<HashMap<&str, &str>>();
 
@@ -74,7 +75,7 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .filter_map(|&&intrinsic| {
             let c_output = c_output_map.get(intrinsic).unwrap();
             let rust_output = rust_output_map.get(intrinsic).unwrap();
-            if rust_output.to_string() == c_output.to_string() {
+            if rust_output.eq(c_output) {
                 None
             } else {
                 let diff = diff::lines(c_output, rust_output);
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index 30f359a27e..a95b4c36b7 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -1,6 +1,7 @@
 use crate::common::intrinsic::Intrinsic;
 
 use super::argument::Argument;
+use super::compare::INTRINSIC_DELIMITER;
 use super::indentation::Indentation;
 use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
@@ -149,7 +150,10 @@ pub fn write_main_cpp<'a>(
     writeln!(w, "int main(int argc, char **argv) {{")?;
 
     for intrinsic in intrinsics {
-        writeln!(w, "    std::cout << \"############\" << std::endl;")?;
+        writeln!(
+            w,
+            "    std::cout << \"{INTRINSIC_DELIMITER}\" << std::endl;"
+        )?;
         writeln!(w, "    std::cout << \"{intrinsic}\" << std::endl;")?;
         writeln!(w, "    run_{intrinsic}();\n")?;
     }
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index afc6ca4556..fb047e2612 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -1,11 +1,11 @@
 use itertools::Itertools;
 use std::process::Command;
 
-use crate::common::argument::ArgumentList;
-use crate::common::intrinsic::Intrinsic;
-
+use super::compare::INTRINSIC_DELIMITER;
 use super::indentation::Indentation;
 use super::intrinsic_helpers::IntrinsicTypeDefinition;
+use crate::common::argument::ArgumentList;
+use crate::common::intrinsic::Intrinsic;
 
 // The number of times each intrinsic will be called.
 pub(crate) const PASSES: u32 = 20;
@@ -87,7 +87,7 @@ pub fn write_main_rs<'a>(
     writeln!(w, "fn main() {{")?;
 
     for binary in intrinsics {
-        writeln!(w, "    println!(\"############\");")?;
+        writeln!(w, "    println!(\"{INTRINSIC_DELIMITER}\");")?;
         writeln!(w, "    println!(\"{binary}\");")?;
         writeln!(w, "    run_{binary}();\n")?;
     }

From fc224e27d0b54906bdf82b13f7c27fd0f2993809 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 5 Nov 2025 11:57:59 +0530
Subject: [PATCH 046/326] feat: reduce the intrinsics coverage for x86_64
 intrinsics

---
 ci/intrinsic-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index 2b40044462..ff76a0c769 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -75,7 +75,7 @@ case ${TARGET} in
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
-        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=30}"
+        : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=20}"
         ;;
     *)
         ;;

From 1fc119717eaeb441f47de799d1631897d041bd59 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 5 Nov 2025 12:41:58 +0530
Subject: [PATCH 047/326] chore: logging to trace the time taken by binaries to
 complete a run

---
 crates/intrinsic-test/src/common/compare.rs | 3 +++
 crates/intrinsic-test/src/main.rs           | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 7c5d87b51f..c4c2a1e3e4 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -47,6 +47,7 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         );
     }
 
+    info!("Completed running C++ and Rust test binaries");
     let c = std::str::from_utf8(&c.stdout)
         .unwrap()
         .to_lowercase()
@@ -70,6 +71,8 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .chain(rust_output_map.keys())
         .unique()
         .collect_vec();
+
+    info!("Comparing outputs");
     let intrinsics_diff_count = intrinsics
         .par_iter()
         .filter_map(|&&intrinsic| {
diff --git a/crates/intrinsic-test/src/main.rs b/crates/intrinsic-test/src/main.rs
index 3580d80bd1..e5c846877c 100644
--- a/crates/intrinsic-test/src/main.rs
+++ b/crates/intrinsic-test/src/main.rs
@@ -34,7 +34,7 @@ fn run(test_environment: impl SupportedArchitectureTest) {
     if !test_environment.build_rust_file() {
         std::process::exit(3);
     }
-    info!("comparing outputs");
+    info!("Running binaries");
     if !test_environment.compare_outputs() {
         std::process::exit(1);
     }

From 23c78bdcb32087d707f6b2a443fcb63d90d0ce3d Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 11 Nov 2025 03:43:37 +0530
Subject: [PATCH 048/326] Use ordered reduction intrinsics for integer
 reductions

only ordered intrinsics have implementation in rustc-const-eval
---
 crates/core_arch/src/x86/avx512bw.rs | 32 ++++++++++++++--------------
 crates/core_arch/src/x86/avx512f.rs  | 30 ++++++++++++--------------
 2 files changed, 30 insertions(+), 32 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 5d17d42532..c76ec3cb29 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -4778,7 +4778,7 @@ pub fn _mm_mask_cmp_epi8_mask<const IMM8: i32>(k1: __mmask16, a: __m128i, b: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_reduce_add_epi16(a: __m256i) -> i16 {
-    unsafe { simd_reduce_add_unordered(a.as_i16x16()) }
+    unsafe { simd_reduce_add_ordered(a.as_i16x16(), 0) }
 }
 
 /// Reduce the packed 16-bit integers in a by addition using mask k. Returns the sum of all active elements in a.
@@ -4788,7 +4788,7 @@ pub fn _mm256_reduce_add_epi16(a: __m256i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 {
-    unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::ZERO)) }
+    unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::ZERO), 0) }
 }
 
 /// Reduce the packed 16-bit integers in a by addition. Returns the sum of all elements in a.
@@ -4798,7 +4798,7 @@ pub fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_reduce_add_epi16(a: __m128i) -> i16 {
-    unsafe { simd_reduce_add_unordered(a.as_i16x8()) }
+    unsafe { simd_reduce_add_ordered(a.as_i16x8(), 0) }
 }
 
 /// Reduce the packed 16-bit integers in a by addition using mask k. Returns the sum of all active elements in a.
@@ -4808,7 +4808,7 @@ pub fn _mm_reduce_add_epi16(a: __m128i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 {
-    unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::ZERO)) }
+    unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::ZERO), 0) }
 }
 
 /// Reduce the packed 8-bit integers in a by addition. Returns the sum of all elements in a.
@@ -4818,7 +4818,7 @@ pub fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_reduce_add_epi8(a: __m256i) -> i8 {
-    unsafe { simd_reduce_add_unordered(a.as_i8x32()) }
+    unsafe { simd_reduce_add_ordered(a.as_i8x32(), 0) }
 }
 
 /// Reduce the packed 8-bit integers in a by addition using mask k. Returns the sum of all active elements in a.
@@ -4828,7 +4828,7 @@ pub fn _mm256_reduce_add_epi8(a: __m256i) -> i8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 {
-    unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::ZERO)) }
+    unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::ZERO), 0) }
 }
 
 /// Reduce the packed 8-bit integers in a by addition. Returns the sum of all elements in a.
@@ -4838,7 +4838,7 @@ pub fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_reduce_add_epi8(a: __m128i) -> i8 {
-    unsafe { simd_reduce_add_unordered(a.as_i8x16()) }
+    unsafe { simd_reduce_add_ordered(a.as_i8x16(), 0) }
 }
 
 /// Reduce the packed 8-bit integers in a by addition using mask k. Returns the sum of all active elements in a.
@@ -4848,7 +4848,7 @@ pub fn _mm_reduce_add_epi8(a: __m128i) -> i8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_reduce_add_epi8(k: __mmask16, a: __m128i) -> i8 {
-    unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::ZERO)) }
+    unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::ZERO), 0) }
 }
 
 /// Reduce the packed 16-bit integers in a by bitwise AND. Returns the bitwise AND of all elements in a.
@@ -5282,7 +5282,7 @@ pub fn _mm_mask_reduce_min_epu8(k: __mmask16, a: __m128i) -> u8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 {
-    unsafe { simd_reduce_mul_unordered(a.as_i16x16()) }
+    unsafe { simd_reduce_mul_ordered(a.as_i16x16(), 1) }
 }
 
 /// Reduce the packed 16-bit integers in a by multiplication using mask k. Returns the product of all active elements in a.
@@ -5292,7 +5292,7 @@ pub fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 {
-    unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(1))) }
+    unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(1)), 1) }
 }
 
 /// Reduce the packed 16-bit integers in a by multiplication. Returns the product of all elements in a.
@@ -5302,7 +5302,7 @@ pub fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_reduce_mul_epi16(a: __m128i) -> i16 {
-    unsafe { simd_reduce_mul_unordered(a.as_i16x8()) }
+    unsafe { simd_reduce_mul_ordered(a.as_i16x8(), 1) }
 }
 
 /// Reduce the packed 16-bit integers in a by multiplication using mask k. Returns the product of all active elements in a.
@@ -5312,7 +5312,7 @@ pub fn _mm_reduce_mul_epi16(a: __m128i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 {
-    unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(1))) }
+    unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(1)), 1) }
 }
 
 /// Reduce the packed 8-bit integers in a by multiplication. Returns the product of all elements in a.
@@ -5322,7 +5322,7 @@ pub fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 {
-    unsafe { simd_reduce_mul_unordered(a.as_i8x32()) }
+    unsafe { simd_reduce_mul_ordered(a.as_i8x32(), 1) }
 }
 
 /// Reduce the packed 8-bit integers in a by multiplication using mask k. Returns the product of all active elements in a.
@@ -5332,7 +5332,7 @@ pub fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 {
-    unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(1))) }
+    unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(1)), 1) }
 }
 
 /// Reduce the packed 8-bit integers in a by multiplication. Returns the product of all elements in a.
@@ -5342,7 +5342,7 @@ pub fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_reduce_mul_epi8(a: __m128i) -> i8 {
-    unsafe { simd_reduce_mul_unordered(a.as_i8x16()) }
+    unsafe { simd_reduce_mul_ordered(a.as_i8x16(), 1) }
 }
 
 /// Reduce the packed 8-bit integers in a by multiplication using mask k. Returns the product of all active elements in a.
@@ -5352,7 +5352,7 @@ pub fn _mm_reduce_mul_epi8(a: __m128i) -> i8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_reduce_mul_epi8(k: __mmask16, a: __m128i) -> i8 {
-    unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(1))) }
+    unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(1)), 1) }
 }
 
 /// Reduce the packed 16-bit integers in a by bitwise OR. Returns the bitwise OR of all elements in a.
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 8d3ddbd964..d6b30d2d7d 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -33101,7 +33101,7 @@ pub fn _mm_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_reduce_add_epi32(a: __m512i) -> i32 {
-    unsafe { simd_reduce_add_unordered(a.as_i32x16()) }
+    unsafe { simd_reduce_add_ordered(a.as_i32x16(), 0) }
 }
 
 /// Reduce the packed 32-bit integers in a by addition using mask k. Returns the sum of all active elements in a.
@@ -33111,7 +33111,7 @@ pub fn _mm512_reduce_add_epi32(a: __m512i) -> i32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 {
-    unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i32x16(), i32x16::ZERO)) }
+    unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i32x16(), i32x16::ZERO), 0) }
 }
 
 /// Reduce the packed 64-bit integers in a by addition. Returns the sum of all elements in a.
@@ -33121,7 +33121,7 @@ pub fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_reduce_add_epi64(a: __m512i) -> i64 {
-    unsafe { simd_reduce_add_unordered(a.as_i64x8()) }
+    unsafe { simd_reduce_add_ordered(a.as_i64x8(), 0) }
 }
 
 /// Reduce the packed 64-bit integers in a by addition using mask k. Returns the sum of all active elements in a.
@@ -33131,7 +33131,7 @@ pub fn _mm512_reduce_add_epi64(a: __m512i) -> i64 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_mask_reduce_add_epi64(k: __mmask8, a: __m512i) -> i64 {
-    unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i64x8(), i64x8::ZERO)) }
+    unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i64x8(), i64x8::ZERO), 0) }
 }
 
 /// Reduce the packed single-precision (32-bit) floating-point elements in a by addition. Returns the sum of all elements in a.
@@ -33197,7 +33197,7 @@ pub fn _mm512_mask_reduce_add_pd(k: __mmask8, a: __m512d) -> f64 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 {
-    unsafe { simd_reduce_mul_unordered(a.as_i32x16()) }
+    unsafe { simd_reduce_mul_ordered(a.as_i32x16(), 1) }
 }
 
 /// Reduce the packed 32-bit integers in a by multiplication using mask k. Returns the product of all active elements in a.
@@ -33208,11 +33208,10 @@ pub fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe {
-        simd_reduce_mul_unordered(simd_select_bitmask(
-            k,
-            a.as_i32x16(),
-            _mm512_set1_epi32(1).as_i32x16(),
-        ))
+        simd_reduce_mul_ordered(
+            simd_select_bitmask(k, a.as_i32x16(), _mm512_set1_epi32(1).as_i32x16()),
+            1,
+        )
     }
 }
 
@@ -33223,7 +33222,7 @@ pub fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 {
-    unsafe { simd_reduce_mul_unordered(a.as_i64x8()) }
+    unsafe { simd_reduce_mul_ordered(a.as_i64x8(), 1) }
 }
 
 /// Reduce the packed 64-bit integers in a by multiplication using mask k. Returns the product of all active elements in a.
@@ -33234,11 +33233,10 @@ pub fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_mask_reduce_mul_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe {
-        simd_reduce_mul_unordered(simd_select_bitmask(
-            k,
-            a.as_i64x8(),
-            _mm512_set1_epi64(1).as_i64x8(),
-        ))
+        simd_reduce_mul_ordered(
+            simd_select_bitmask(k, a.as_i64x8(), _mm512_set1_epi64(1).as_i64x8()),
+            1,
+        )
     }
 }
 

From 1f94820a0be556a42d0c28abd7a6595474cb5169 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 15 Sep 2025 04:50:49 +0530
Subject: [PATCH 049/326] Make some helpers `const`

---
 crates/core_arch/src/lib.rs            |   5 +-
 crates/core_arch/src/mod.rs            |   5 +
 crates/core_arch/src/simd.rs           |  24 ++-
 crates/core_arch/src/test.rs           |  25 +++
 crates/core_arch/src/x86/avx512fp16.rs |   9 +-
 crates/core_arch/src/x86/mod.rs        |   4 +-
 crates/core_arch/src/x86/test.rs       | 281 ++++++++++++++++---------
 7 files changed, 240 insertions(+), 113 deletions(-)
 create mode 100644 crates/core_arch/src/test.rs

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index a059a9c225..5bedefe42d 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -34,7 +34,10 @@
     aarch64_unstable_target_feature,
     bigint_helper_methods,
     funnel_shifts,
-    avx10_target_feature
+    avx10_target_feature,
+    const_trait_impl,
+    const_cmp,
+    const_eval_select
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]
diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs
index 2105cca1b4..7fc0ed0fca 100644
--- a/crates/core_arch/src/mod.rs
+++ b/crates/core_arch/src/mod.rs
@@ -5,6 +5,11 @@
 #[macro_use]
 mod macros;
 
+#[cfg(test)]
+mod test;
+#[cfg(test)]
+use test::assert_eq_const;
+
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
 mod riscv_shared;
 
diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index 9fa8e25022..b9dbde7597 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -3,13 +3,15 @@
 #![allow(non_camel_case_types)]
 
 #[inline(always)]
-pub(crate) unsafe fn simd_imax<T: Copy>(a: T, b: T) -> T {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn simd_imax<T: Copy>(a: T, b: T) -> T {
     let mask: T = crate::intrinsics::simd::simd_gt(a, b);
     crate::intrinsics::simd::simd_select(mask, a, b)
 }
 
 #[inline(always)]
-pub(crate) unsafe fn simd_imin<T: Copy>(a: T, b: T) -> T {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn simd_imin<T: Copy>(a: T, b: T) -> T {
     let mask: T = crate::intrinsics::simd::simd_lt(a, b);
     crate::intrinsics::simd::simd_select(mask, a, b)
 }
@@ -35,7 +37,8 @@ macro_rules! simd_ty {
             }
             // FIXME: Workaround rust@60637
             #[inline(always)]
-            pub(crate) fn splat(value: $elem_type) -> Self {
+            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+            pub(crate) const fn splat(value: $elem_type) -> Self {
                 #[derive(Copy, Clone)]
                 #[repr(simd)]
                 struct JustOne([$elem_type; 1]);
@@ -50,12 +53,12 @@ macro_rules! simd_ty {
             /// Use for testing only.
             // FIXME: Workaround rust@60637
             #[inline(always)]
-            pub(crate) fn extract(&self, index: usize) -> $elem_type {
+            pub(crate) const fn extract(&self, index: usize) -> $elem_type {
                 self.as_array()[index]
             }
 
             #[inline]
-            pub(crate) fn as_array(&self) -> &[$elem_type; $len] {
+            pub(crate) const fn as_array(&self) -> &[$elem_type; $len] {
                 let simd_ptr: *const Self = self;
                 let array_ptr: *const [$elem_type; $len] = simd_ptr.cast();
                 // SAFETY: We can always read the prefix of a simd type as an array.
@@ -65,7 +68,8 @@ macro_rules! simd_ty {
             }
         }
 
-        impl core::cmp::PartialEq for $id {
+        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+        const impl core::cmp::PartialEq for $id {
             #[inline]
             fn eq(&self, other: &Self) -> bool {
                 self.as_array() == other.as_array()
@@ -101,7 +105,8 @@ macro_rules! simd_m_ty {
 
             // FIXME: Workaround rust@60637
             #[inline(always)]
-            pub(crate) fn splat(value: bool) -> Self {
+            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+            pub(crate) const fn splat(value: bool) -> Self {
                 #[derive(Copy, Clone)]
                 #[repr(simd)]
                 struct JustOne([$elem_type; 1]);
@@ -112,7 +117,7 @@ macro_rules! simd_m_ty {
             }
 
             #[inline]
-            pub(crate) fn as_array(&self) -> &[$elem_type; $len] {
+            pub(crate) const fn as_array(&self) -> &[$elem_type; $len] {
                 let simd_ptr: *const Self = self;
                 let array_ptr: *const [$elem_type; $len] = simd_ptr.cast();
                 // SAFETY: We can always read the prefix of a simd type as an array.
@@ -122,7 +127,8 @@ macro_rules! simd_m_ty {
             }
         }
 
-        impl core::cmp::PartialEq for $id {
+        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+        const impl core::cmp::PartialEq for $id {
             #[inline]
             fn eq(&self, other: &Self) -> bool {
                 self.as_array() == other.as_array()
diff --git a/crates/core_arch/src/test.rs b/crates/core_arch/src/test.rs
new file mode 100644
index 0000000000..976d4ac1b0
--- /dev/null
+++ b/crates/core_arch/src/test.rs
@@ -0,0 +1,25 @@
+use crate::fmt::Debug;
+
+#[track_caller]
+#[allow(unused)]
+pub(crate) fn assert_eq_rt<T: PartialEq + Debug>(a: &T, b: &T) {
+    std::assert_eq!(a, b)
+}
+
+#[allow(unused)]
+macro_rules! assert_eq_const {
+    ($a:expr, $b:expr $(,)?) => {{
+        #[inline(always)]
+        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+        const fn assert_eq_ct<T: [const] PartialEq>(a: &T, b: &T) {
+            assert!(a == b, concat!("`", stringify!($a), "` != `", stringify!($b), "`"));
+        }
+
+        $crate::intrinsics::const_eval_select((&$a, &$b), assert_eq_ct, $crate::core_arch::test::assert_eq_rt);
+    }};
+    ($a:expr, $b:expr, $($t:tt)+) => {
+        ::std::assert_eq!($a, $b, $($t)+)
+    };
+}
+
+pub(crate) use assert_eq_const;
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 01b1be364f..7185531606 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -16714,19 +16714,22 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[target_feature(enable = "avx512fp16")]
-    unsafe fn _mm_set1_pch(re: f16, im: f16) -> __m128h {
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    const fn _mm_set1_pch(re: f16, im: f16) -> __m128h {
         _mm_setr_ph(re, im, re, im, re, im, re, im)
     }
 
     #[target_feature(enable = "avx512fp16")]
-    unsafe fn _mm256_set1_pch(re: f16, im: f16) -> __m256h {
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    const fn _mm256_set1_pch(re: f16, im: f16) -> __m256h {
         _mm256_setr_ph(
             re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im,
         )
     }
 
     #[target_feature(enable = "avx512fp16")]
-    unsafe fn _mm512_set1_pch(re: f16, im: f16) -> __m512h {
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    const fn _mm512_set1_pch(re: f16, im: f16) -> __m512h {
         _mm512_setr_ph(
             re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im, re, im,
             re, im, re, im, re, im, re, im, re, im,
diff --git a/crates/core_arch/src/x86/mod.rs b/crates/core_arch/src/x86/mod.rs
index 79a593e647..7612cffd07 100644
--- a/crates/core_arch/src/x86/mod.rs
+++ b/crates/core_arch/src/x86/mod.rs
@@ -520,14 +520,14 @@ macro_rules! as_transmute {
     ($from:ty => $as_from:ident, $($as_to:ident -> $to:ident),* $(,)?) => {
         impl $from {$(
             #[inline]
-            pub(crate) fn $as_to(self) -> crate::core_arch::simd::$to {
+            pub(crate) const fn $as_to(self) -> crate::core_arch::simd::$to {
                 unsafe { transmute(self) }
             }
         )*}
         $(
             impl crate::core_arch::simd::$to {
                 #[inline]
-                pub(crate) fn $as_from(self) -> $from {
+                pub(crate) const fn $as_from(self) -> $from {
                     unsafe { transmute(self) }
                 }
             }
diff --git a/crates/core_arch/src/x86/test.rs b/crates/core_arch/src/x86/test.rs
index fec25ce2bc..9fa88fc98d 100644
--- a/crates/core_arch/src/x86/test.rs
+++ b/crates/core_arch/src/x86/test.rs
@@ -1,115 +1,228 @@
 //! Utilities used in testing the x86 intrinsics
 
+use crate::core_arch::assert_eq_const as assert_eq;
 use crate::core_arch::x86::*;
 use std::mem::transmute;
 
 #[track_caller]
 #[target_feature(enable = "sse2")]
-pub unsafe fn assert_eq_m128i(a: __m128i, b: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn assert_eq_m128i(a: __m128i, b: __m128i) {
     assert_eq!(transmute::<_, [u64; 2]>(a), transmute::<_, [u64; 2]>(b))
 }
 
 #[track_caller]
-#[target_feature(enable = "sse2")]
-pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) {
-    if _mm_movemask_pd(_mm_cmpeq_pd(a, b)) != 0b11 {
-        panic!("{:?} != {:?}", a, b);
-    }
+#[target_feature(enable = "avx")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn assert_eq_m256i(a: __m256i, b: __m256i) {
+    assert_eq!(transmute::<_, [u64; 4]>(a), transmute::<_, [u64; 4]>(b))
 }
 
-#[target_feature(enable = "sse2")]
-pub unsafe fn get_m128d(a: __m128d, idx: usize) -> f64 {
-    transmute::<_, [f64; 2]>(a)[idx]
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn assert_eq_m512i(a: __m512i, b: __m512i) {
+    assert_eq!(transmute::<_, [i32; 16]>(a), transmute::<_, [i32; 16]>(b))
 }
 
-#[track_caller]
-#[target_feature(enable = "sse")]
-pub unsafe fn assert_eq_m128(a: __m128, b: __m128) {
-    let r = _mm_cmpeq_ps(a, b);
-    if _mm_movemask_ps(r) != 0b1111 {
-        panic!("{:?} != {:?}", a, b);
+macro_rules! make_ct_rt {
+    ($(
+        $( #[$meta:meta] )*
+        $vis:vis unsafe fn $name:ident ($($param:ident : $type:ty),* $(,)?) {
+            ct: $ct:expr;
+            rt: $rt:expr;
+        }
+    )*) => {$(
+        $( #[$meta] )*
+        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+        $vis const unsafe fn $name ($($param : $type),*) {
+            #[inline(always)]
+            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+            const fn ct($($param : $type),*) {
+                $ct
+            }
+            #[inline(always)]
+            fn rt($($param : $type),*) {
+                $rt
+            }
+
+            $crate::intrinsics::const_eval_select(($($param),*), ct, rt)
+        }
+    )*}
+}
+
+make_ct_rt! {
+    // SAFETY: we can use simple float equality because when this should only be used in const
+    // context where Intel peculiarities don't appear
+
+    #[track_caller]
+    #[target_feature(enable = "sse2")]
+    pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f64; 2]>(a), transmute::<_, [f64; 2]>(b))
+        };
+        rt: unsafe {
+            if _mm_movemask_pd(_mm_cmpeq_pd(a, b)) != 0b11 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
     }
-}
 
-#[target_feature(enable = "sse")]
-pub unsafe fn get_m128(a: __m128, idx: usize) -> f32 {
-    transmute::<_, [f32; 4]>(a)[idx]
-}
+    #[track_caller]
+    #[target_feature(enable = "sse")]
+    pub unsafe fn assert_eq_m128(a: __m128, b: __m128) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f32; 4]>(a), transmute::<_, [f32; 4]>(b))
+        };
+        rt: unsafe {
+            let r = _mm_cmpeq_ps(a, b);
+            if _mm_movemask_ps(r) != 0b1111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
+    }
 
-#[track_caller]
-#[target_feature(enable = "avx512fp16,avx512vl")]
-pub unsafe fn assert_eq_m128h(a: __m128h, b: __m128h) {
-    let r = _mm_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
-    if r != 0b1111_1111 {
-        panic!("{:?} != {:?}", a, b);
+    #[track_caller]
+    #[target_feature(enable = "avx512fp16,avx512vl")]
+    pub unsafe fn assert_eq_m128h(a: __m128h, b: __m128h) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f16; 8]>(a), transmute::<_, [f16; 8]>(b))
+        };
+        rt: unsafe {
+            let r = _mm_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
+            if r != 0b1111_1111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
     }
-}
 
-// not actually an intrinsic but useful in various tests as we proted from
-// `i64x2::new` which is backwards from `_mm_set_epi64x`
-#[target_feature(enable = "sse2")]
-pub unsafe fn _mm_setr_epi64x(a: i64, b: i64) -> __m128i {
-    _mm_set_epi64x(b, a)
-}
+    #[track_caller]
+    #[target_feature(enable = "avx")]
+    pub unsafe fn assert_eq_m256d(a: __m256d, b: __m256d) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f64; 4]>(a), transmute::<_, [f64; 4]>(b))
+        };
+        rt: unsafe {
+            let cmp = _mm256_cmp_pd::<_CMP_EQ_OQ>(a, b);
+            if _mm256_movemask_pd(cmp) != 0b1111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
+    }
 
-#[track_caller]
-#[target_feature(enable = "avx")]
-pub unsafe fn assert_eq_m256i(a: __m256i, b: __m256i) {
-    assert_eq!(transmute::<_, [u64; 4]>(a), transmute::<_, [u64; 4]>(b))
-}
+    #[track_caller]
+    #[target_feature(enable = "avx")]
+    pub unsafe fn assert_eq_m256(a: __m256, b: __m256) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f32; 8]>(a), transmute::<_, [f32; 8]>(b))
+        };
+        rt: unsafe {
+            let cmp = _mm256_cmp_ps::<_CMP_EQ_OQ>(a, b);
+            if _mm256_movemask_ps(cmp) != 0b11111111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
+    }
 
-#[track_caller]
-#[target_feature(enable = "avx")]
-pub unsafe fn assert_eq_m256d(a: __m256d, b: __m256d) {
-    let cmp = _mm256_cmp_pd::<_CMP_EQ_OQ>(a, b);
-    if _mm256_movemask_pd(cmp) != 0b1111 {
-        panic!("{:?} != {:?}", a, b);
+    #[track_caller]
+    #[target_feature(enable = "avx512fp16,avx512vl")]
+    pub unsafe fn assert_eq_m256h(a: __m256h, b: __m256h) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f16; 16]>(a), transmute::<_, [f16; 16]>(b))
+        };
+        rt: unsafe {
+            let r = _mm256_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
+            if r != 0b11111111_11111111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
+    }
+
+    #[track_caller]
+    #[target_feature(enable = "avx512f")]
+    pub unsafe fn assert_eq_m512d(a: __m512d, b: __m512d) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f64; 8]>(a), transmute::<_, [f64; 8]>(b))
+        };
+        rt: unsafe {
+            let cmp = _mm512_cmp_pd_mask::<_CMP_EQ_OQ>(a, b);
+            if cmp != 0b11111111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
+    }
+
+    #[track_caller]
+    #[target_feature(enable = "avx512f")]
+    pub unsafe fn assert_eq_m512(a: __m512, b: __m512) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f32; 16]>(a), transmute::<_, [f32; 16]>(b))
+        };
+        rt: unsafe {
+            let cmp = _mm512_cmp_ps_mask::<_CMP_EQ_OQ>(a, b);
+            if cmp != 0b11111111_11111111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
+    }
+
+    #[track_caller]
+    #[target_feature(enable = "avx512fp16")]
+    pub unsafe fn assert_eq_m512h(a: __m512h, b: __m512h) {
+        ct: unsafe {
+            assert_eq!(transmute::<_, [f16; 32]>(a), transmute::<_, [f16; 32]>(b))
+        };
+        rt: unsafe {
+            let r = _mm512_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
+            if r != 0b11111111_11111111_11111111_11111111 {
+                panic!("{:?} != {:?}", a, b);
+            }
+        };
     }
 }
 
-#[target_feature(enable = "avx")]
-pub unsafe fn get_m256d(a: __m256d, idx: usize) -> f64 {
-    transmute::<_, [f64; 4]>(a)[idx]
+#[target_feature(enable = "sse2")]
+pub(crate) const unsafe fn get_m128d(a: __m128d, idx: usize) -> f64 {
+    transmute::<_, [f64; 2]>(a)[idx]
 }
 
-#[track_caller]
-#[target_feature(enable = "avx")]
-pub unsafe fn assert_eq_m256(a: __m256, b: __m256) {
-    let cmp = _mm256_cmp_ps::<_CMP_EQ_OQ>(a, b);
-    if _mm256_movemask_ps(cmp) != 0b11111111 {
-        panic!("{:?} != {:?}", a, b);
-    }
+#[target_feature(enable = "sse")]
+pub(crate) const unsafe fn get_m128(a: __m128, idx: usize) -> f32 {
+    transmute::<_, [f32; 4]>(a)[idx]
 }
 
 #[target_feature(enable = "avx")]
-pub unsafe fn get_m256(a: __m256, idx: usize) -> f32 {
-    transmute::<_, [f32; 8]>(a)[idx]
+pub(crate) const unsafe fn get_m256d(a: __m256d, idx: usize) -> f64 {
+    transmute::<_, [f64; 4]>(a)[idx]
 }
 
-#[track_caller]
-#[target_feature(enable = "avx512fp16,avx512vl")]
-pub unsafe fn assert_eq_m256h(a: __m256h, b: __m256h) {
-    let r = _mm256_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
-    if r != 0b11111111_11111111 {
-        panic!("{:?} != {:?}", a, b);
-    }
+#[target_feature(enable = "avx")]
+pub(crate) const unsafe fn get_m256(a: __m256, idx: usize) -> f32 {
+    transmute::<_, [f32; 8]>(a)[idx]
 }
 
 #[target_feature(enable = "avx512f")]
-pub unsafe fn get_m512(a: __m512, idx: usize) -> f32 {
+pub(crate) const unsafe fn get_m512(a: __m512, idx: usize) -> f32 {
     transmute::<_, [f32; 16]>(a)[idx]
 }
 
 #[target_feature(enable = "avx512f")]
-pub unsafe fn get_m512d(a: __m512d, idx: usize) -> f64 {
+pub(crate) const unsafe fn get_m512d(a: __m512d, idx: usize) -> f64 {
     transmute::<_, [f64; 8]>(a)[idx]
 }
 
 #[target_feature(enable = "avx512f")]
-pub unsafe fn get_m512i(a: __m512i, idx: usize) -> i64 {
+pub(crate) const unsafe fn get_m512i(a: __m512i, idx: usize) -> i64 {
     transmute::<_, [i64; 8]>(a)[idx]
 }
 
+// not actually an intrinsic but useful in various tests as we ported from
+// `i64x2::new` which is backwards from `_mm_set_epi64x`
+#[target_feature(enable = "sse2")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const unsafe fn _mm_setr_epi64x(a: i64, b: i64) -> __m128i {
+    _mm_set_epi64x(b, a)
+}
+
 // These intrinsics doesn't exist on x86 b/c it requires a 64-bit register,
 // which doesn't exist on x86!
 #[cfg(target_arch = "x86")]
@@ -118,14 +231,16 @@ mod x86_polyfill {
     use crate::intrinsics::simd::*;
 
     #[rustc_legacy_const_generics(2)]
-    pub unsafe fn _mm_insert_epi64<const INDEX: i32>(a: __m128i, val: i64) -> __m128i {
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub const unsafe fn _mm_insert_epi64<const INDEX: i32>(a: __m128i, val: i64) -> __m128i {
         static_assert_uimm_bits!(INDEX, 1);
         transmute(simd_insert!(a.as_i64x2(), INDEX as u32, val))
     }
 
     #[target_feature(enable = "avx2")]
     #[rustc_legacy_const_generics(2)]
-    pub unsafe fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, val: i64) -> __m256i {
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub const unsafe fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, val: i64) -> __m256i {
         static_assert_uimm_bits!(INDEX, 2);
         transmute(simd_insert!(a.as_i64x4(), INDEX as u32, val))
     }
@@ -136,33 +251,3 @@ mod x86_polyfill {
     pub use crate::core_arch::x86_64::{_mm_insert_epi64, _mm256_insert_epi64};
 }
 pub use self::x86_polyfill::*;
-
-#[track_caller]
-pub unsafe fn assert_eq_m512i(a: __m512i, b: __m512i) {
-    assert_eq!(transmute::<_, [i32; 16]>(a), transmute::<_, [i32; 16]>(b))
-}
-
-#[track_caller]
-pub unsafe fn assert_eq_m512(a: __m512, b: __m512) {
-    let cmp = _mm512_cmp_ps_mask::<_CMP_EQ_OQ>(a, b);
-    if cmp != 0b11111111_11111111 {
-        panic!("{:?} != {:?}", a, b);
-    }
-}
-
-#[track_caller]
-pub unsafe fn assert_eq_m512d(a: __m512d, b: __m512d) {
-    let cmp = _mm512_cmp_pd_mask::<_CMP_EQ_OQ>(a, b);
-    if cmp != 0b11111111 {
-        panic!("{:?} != {:?}", a, b);
-    }
-}
-
-#[track_caller]
-#[target_feature(enable = "avx512fp16")]
-pub unsafe fn assert_eq_m512h(a: __m512h, b: __m512h) {
-    let r = _mm512_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
-    if r != 0b11111111_11111111_11111111_11111111 {
-        panic!("{:?} != {:?}", a, b);
-    }
-}

From 90ca47b96cc941363b048d7843245cb4ad72f0e6 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 25 Nov 2025 09:45:33 +0530
Subject: [PATCH 050/326] Modify `#[simd_test]` to enable const-testing

---
 crates/simd-test-macro/src/lib.rs | 68 +++++++++++++++++++------------
 1 file changed, 41 insertions(+), 27 deletions(-)

diff --git a/crates/simd-test-macro/src/lib.rs b/crates/simd-test-macro/src/lib.rs
index b18e2d6b63..b8bb874480 100644
--- a/crates/simd-test-macro/src/lib.rs
+++ b/crates/simd-test-macro/src/lib.rs
@@ -7,43 +7,41 @@
 #[macro_use]
 extern crate quote;
 
-use proc_macro2::{Ident, Literal, Span, TokenStream, TokenTree};
+use proc_macro2::{Ident, Span, TokenStream, TokenTree};
 use quote::ToTokens;
 use std::env;
 
-fn string(s: &str) -> TokenTree {
-    Literal::string(s).into()
-}
-
 #[proc_macro_attribute]
 pub fn simd_test(
     attr: proc_macro::TokenStream,
     item: proc_macro::TokenStream,
 ) -> proc_macro::TokenStream {
     let tokens = TokenStream::from(attr).into_iter().collect::<Vec<_>>();
-    if tokens.len() != 3 {
-        panic!("expected #[simd_test(enable = \"feature\")]");
-    }
-    match &tokens[0] {
-        TokenTree::Ident(tt) if *tt == "enable" => {}
-        _ => panic!("expected #[simd_test(enable = \"feature\")]"),
-    }
-    match &tokens[1] {
-        TokenTree::Punct(tt) if tt.as_char() == '=' => {}
-        _ => panic!("expected #[simd_test(enable = \"feature\")]"),
-    }
-    let enable_feature = match &tokens[2] {
-        TokenTree::Literal(tt) => tt.to_string(),
-        _ => panic!("expected #[simd_test(enable = \"feature\")]"),
+    let (target_features, target_feature_attr) = match &tokens[..] {
+        [] => (Vec::new(), TokenStream::new()),
+        [
+            TokenTree::Ident(enable),
+            TokenTree::Punct(equals),
+            TokenTree::Literal(literal),
+        ] if enable == "enable" && equals.as_char() == '=' => {
+            let enable_feature = literal.to_string();
+            let enable_feature = enable_feature.trim_start_matches('"').trim_end_matches('"');
+            let target_features: Vec<_> = enable_feature
+                .replace('+', "")
+                .split(',')
+                .map(String::from)
+                .collect();
+
+            (
+                target_features,
+                quote! {
+                    #[target_feature(enable = #enable_feature)]
+                },
+            )
+        }
+        _ => panic!("expected #[simd_test(enable = \"feature\")] or #[simd_test]"),
     };
-    let enable_feature = enable_feature.trim_start_matches('"').trim_end_matches('"');
-    let target_features: Vec<String> = enable_feature
-        .replace('+', "")
-        .split(',')
-        .map(String::from)
-        .collect();
 
-    let enable_feature = string(enable_feature);
     let mut item = syn::parse_macro_input!(item as syn::ItemFn);
     let item_attrs = std::mem::take(&mut item.attrs);
     let name = &item.sig.ident;
@@ -102,6 +100,19 @@ pub fn simd_test(
         TokenStream::new()
     };
 
+    let (const_test, const_stability) = if item.sig.constness.is_some() {
+        (
+            quote! {
+                const _: () = unsafe { #name() };
+            },
+            quote! {
+                #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+            },
+        )
+    } else {
+        (TokenStream::new(), TokenStream::new())
+    };
+
     let ret: TokenStream = quote_spanned! {
         proc_macro2::Span::call_site() =>
         #[allow(non_snake_case)]
@@ -109,6 +120,8 @@ pub fn simd_test(
         #maybe_ignore
         #(#item_attrs)*
         fn #name() {
+            #const_test
+
             let mut missing_features = ::std::vec::Vec::new();
             #detect_missing_features
             if missing_features.is_empty() {
@@ -118,7 +131,8 @@ pub fn simd_test(
                 ::stdarch_test::assert_skip_test_ok(stringify!(#name), &missing_features);
             }
 
-            #[target_feature(enable = #enable_feature)]
+            #target_feature_attr
+            #const_stability
             #item
         }
     };

From f27005b163a295f4ed1953a2e0c14a0f6a53dd17 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:24:10 +0530
Subject: [PATCH 051/326] Make `abm`, `bmi1`, `bmi2`, `bswap` and `tbm`
 functions const

---
 crates/core_arch/src/x86/abm.rs      | 11 ++++---
 crates/core_arch/src/x86/bmi1.rs     | 34 ++++++++++++--------
 crates/core_arch/src/x86/bmi2.rs     |  6 ++--
 crates/core_arch/src/x86/bswap.rs    | 10 ++++--
 crates/core_arch/src/x86/tbm.rs      | 46 +++++++++++++++++-----------
 crates/core_arch/src/x86_64/abm.rs   | 11 ++++---
 crates/core_arch/src/x86_64/bmi.rs   | 29 +++++++++++-------
 crates/core_arch/src/x86_64/bmi2.rs  |  6 ++--
 crates/core_arch/src/x86_64/bswap.rs | 10 ++++--
 crates/core_arch/src/x86_64/tbm.rs   | 46 +++++++++++++++++-----------
 10 files changed, 131 insertions(+), 78 deletions(-)

diff --git a/crates/core_arch/src/x86/abm.rs b/crates/core_arch/src/x86/abm.rs
index e6d5517600..59f3877b4a 100644
--- a/crates/core_arch/src/x86/abm.rs
+++ b/crates/core_arch/src/x86/abm.rs
@@ -29,7 +29,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "lzcnt")]
 #[cfg_attr(test, assert_instr(lzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _lzcnt_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _lzcnt_u32(x: u32) -> u32 {
     x.leading_zeros()
 }
 
@@ -40,23 +41,25 @@ pub fn _lzcnt_u32(x: u32) -> u32 {
 #[target_feature(enable = "popcnt")]
 #[cfg_attr(test, assert_instr(popcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _popcnt32(x: i32) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _popcnt32(x: i32) -> i32 {
     x.count_ones() as i32
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "lzcnt")]
-    unsafe fn test_lzcnt_u32() {
+    const unsafe fn test_lzcnt_u32() {
         assert_eq!(_lzcnt_u32(0b0101_1010), 25);
     }
 
     #[simd_test(enable = "popcnt")]
-    unsafe fn test_popcnt32() {
+    const unsafe fn test_popcnt32() {
         assert_eq!(_popcnt32(0b0101_1010), 4);
     }
 }
diff --git a/crates/core_arch/src/x86/bmi1.rs b/crates/core_arch/src/x86/bmi1.rs
index eb7242944a..08444aaaed 100644
--- a/crates/core_arch/src/x86/bmi1.rs
+++ b/crates/core_arch/src/x86/bmi1.rs
@@ -46,7 +46,8 @@ pub fn _bextr2_u32(a: u32, control: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(andn))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _andn_u32(a: u32, b: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _andn_u32(a: u32, b: u32) -> u32 {
     !a & b
 }
 
@@ -57,7 +58,8 @@ pub fn _andn_u32(a: u32, b: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(blsi))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsi_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsi_u32(x: u32) -> u32 {
     x & x.wrapping_neg()
 }
 
@@ -68,7 +70,8 @@ pub fn _blsi_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(blsmsk))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsmsk_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsmsk_u32(x: u32) -> u32 {
     x ^ (x.wrapping_sub(1_u32))
 }
 
@@ -81,7 +84,8 @@ pub fn _blsmsk_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(blsr))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsr_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsr_u32(x: u32) -> u32 {
     x & (x.wrapping_sub(1))
 }
 
@@ -94,7 +98,8 @@ pub fn _blsr_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub fn _tzcnt_u16(x: u16) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _tzcnt_u16(x: u16) -> u16 {
     x.trailing_zeros() as u16
 }
 
@@ -107,7 +112,8 @@ pub fn _tzcnt_u16(x: u16) -> u16 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _tzcnt_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _tzcnt_u32(x: u32) -> u32 {
     x.trailing_zeros()
 }
 
@@ -120,7 +126,8 @@ pub fn _tzcnt_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_tzcnt_32(x: u32) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_tzcnt_32(x: u32) -> i32 {
     x.trailing_zeros() as i32
 }
 
@@ -131,6 +138,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
@@ -142,7 +150,7 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_andn_u32() {
+    const unsafe fn test_andn_u32() {
         assert_eq!(_andn_u32(0, 0), 0);
         assert_eq!(_andn_u32(0, 1), 1);
         assert_eq!(_andn_u32(1, 0), 0);
@@ -165,32 +173,32 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_blsi_u32() {
+    const unsafe fn test_blsi_u32() {
         assert_eq!(_blsi_u32(0b1101_0000u32), 0b0001_0000u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_blsmsk_u32() {
+    const unsafe fn test_blsmsk_u32() {
         let r = _blsmsk_u32(0b0011_0000u32);
         assert_eq!(r, 0b0001_1111u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_blsr_u32() {
+    const unsafe fn test_blsr_u32() {
         // TODO: test the behavior when the input is `0`.
         let r = _blsr_u32(0b0011_0000u32);
         assert_eq!(r, 0b0010_0000u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_tzcnt_u16() {
+    const unsafe fn test_tzcnt_u16() {
         assert_eq!(_tzcnt_u16(0b0000_0001u16), 0u16);
         assert_eq!(_tzcnt_u16(0b0000_0000u16), 16u16);
         assert_eq!(_tzcnt_u16(0b1001_0000u16), 4u16);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_tzcnt_u32() {
+    const unsafe fn test_tzcnt_u32() {
         assert_eq!(_tzcnt_u32(0b0000_0001u32), 0u32);
         assert_eq!(_tzcnt_u32(0b0000_0000u32), 32u32);
         assert_eq!(_tzcnt_u32(0b1001_0000u32), 4u32);
diff --git a/crates/core_arch/src/x86/bmi2.rs b/crates/core_arch/src/x86/bmi2.rs
index 83cf650923..b5b7d0f340 100644
--- a/crates/core_arch/src/x86/bmi2.rs
+++ b/crates/core_arch/src/x86/bmi2.rs
@@ -25,7 +25,8 @@ use stdarch_test::assert_instr;
 #[cfg_attr(all(test, target_arch = "x86"), assert_instr(mul))]
 #[target_feature(enable = "bmi2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mulx_u32(a: u32, b: u32, hi: &mut u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mulx_u32(a: u32, b: u32, hi: &mut u32) -> u32 {
     let result: u64 = (a as u64) * (b as u64);
     *hi = (result >> 32) as u32;
     result as u32
@@ -77,6 +78,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
@@ -117,7 +119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_mulx_u32() {
+    const unsafe fn test_mulx_u32() {
         let a: u32 = 4_294_967_200;
         let b: u32 = 2;
         let mut hi = 0;
diff --git a/crates/core_arch/src/x86/bswap.rs b/crates/core_arch/src/x86/bswap.rs
index ea07a7d622..f8e177f7c2 100644
--- a/crates/core_arch/src/x86/bswap.rs
+++ b/crates/core_arch/src/x86/bswap.rs
@@ -10,16 +10,20 @@ use stdarch_test::assert_instr;
 #[inline]
 #[cfg_attr(test, assert_instr(bswap))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _bswap(x: i32) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _bswap(x: i32) -> i32 {
     x.swap_bytes()
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
+    use stdarch_test::simd_test;
+
     use super::*;
 
-    #[test]
-    fn test_bswap() {
+    #[simd_test]
+    const fn test_bswap() {
         assert_eq!(_bswap(0x0EADBE0F), 0x0FBEAD0E);
         assert_eq!(_bswap(0x00000000), 0x00000000);
     }
diff --git a/crates/core_arch/src/x86/tbm.rs b/crates/core_arch/src/x86/tbm.rs
index 5a01752d8a..d7769b916d 100644
--- a/crates/core_arch/src/x86/tbm.rs
+++ b/crates/core_arch/src/x86/tbm.rs
@@ -42,7 +42,8 @@ pub fn _bextri_u32<const CONTROL: u32>(a: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcfill))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcfill_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcfill_u32(x: u32) -> u32 {
     x & (x.wrapping_add(1))
 }
 
@@ -53,7 +54,8 @@ pub fn _blcfill_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blci))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blci_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blci_u32(x: u32) -> u32 {
     x | !x.wrapping_add(1)
 }
 
@@ -64,7 +66,8 @@ pub fn _blci_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcic))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcic_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcic_u32(x: u32) -> u32 {
     !x & x.wrapping_add(1)
 }
 
@@ -76,7 +79,8 @@ pub fn _blcic_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcmsk))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcmsk_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcmsk_u32(x: u32) -> u32 {
     x ^ x.wrapping_add(1)
 }
 
@@ -87,7 +91,8 @@ pub fn _blcmsk_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcs))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcs_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcs_u32(x: u32) -> u32 {
     x | x.wrapping_add(1)
 }
 
@@ -98,7 +103,8 @@ pub fn _blcs_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blsfill))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsfill_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsfill_u32(x: u32) -> u32 {
     x | x.wrapping_sub(1)
 }
 
@@ -109,7 +115,8 @@ pub fn _blsfill_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blsic))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsic_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsic_u32(x: u32) -> u32 {
     !x | x.wrapping_sub(1)
 }
 
@@ -121,7 +128,8 @@ pub fn _blsic_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(t1mskc))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _t1mskc_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _t1mskc_u32(x: u32) -> u32 {
     !x | x.wrapping_add(1)
 }
 
@@ -133,12 +141,14 @@ pub fn _t1mskc_u32(x: u32) -> u32 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(tzmsk))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _tzmsk_u32(x: u32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _tzmsk_u32(x: u32) -> u32 {
     !x & x.wrapping_sub(1)
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
@@ -149,13 +159,13 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcfill_u32() {
+    const unsafe fn test_blcfill_u32() {
         assert_eq!(_blcfill_u32(0b0101_0111u32), 0b0101_0000u32);
         assert_eq!(_blcfill_u32(0b1111_1111u32), 0u32);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blci_u32() {
+    const unsafe fn test_blci_u32() {
         assert_eq!(
             _blci_u32(0b0101_0000u32),
             0b1111_1111_1111_1111_1111_1111_1111_1110u32
@@ -167,25 +177,25 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcic_u32() {
+    const unsafe fn test_blcic_u32() {
         assert_eq!(_blcic_u32(0b0101_0001u32), 0b0000_0010u32);
         assert_eq!(_blcic_u32(0b1111_1111u32), 0b1_0000_0000u32);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcmsk_u32() {
+    const unsafe fn test_blcmsk_u32() {
         assert_eq!(_blcmsk_u32(0b0101_0001u32), 0b0000_0011u32);
         assert_eq!(_blcmsk_u32(0b1111_1111u32), 0b1_1111_1111u32);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcs_u32() {
+    const unsafe fn test_blcs_u32() {
         assert_eq!(_blcs_u32(0b0101_0001u32), 0b0101_0011u32);
         assert_eq!(_blcs_u32(0b1111_1111u32), 0b1_1111_1111u32);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blsfill_u32() {
+    const unsafe fn test_blsfill_u32() {
         assert_eq!(_blsfill_u32(0b0101_0100u32), 0b0101_0111u32);
         assert_eq!(
             _blsfill_u32(0u32),
@@ -194,7 +204,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blsic_u32() {
+    const unsafe fn test_blsic_u32() {
         assert_eq!(
             _blsic_u32(0b0101_0100u32),
             0b1111_1111_1111_1111_1111_1111_1111_1011u32
@@ -206,7 +216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_t1mskc_u32() {
+    const unsafe fn test_t1mskc_u32() {
         assert_eq!(
             _t1mskc_u32(0b0101_0111u32),
             0b1111_1111_1111_1111_1111_1111_1111_1000u32
@@ -218,7 +228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_tzmsk_u32() {
+    const unsafe fn test_tzmsk_u32() {
         assert_eq!(_tzmsk_u32(0b0101_1000u32), 0b0000_0111u32);
         assert_eq!(_tzmsk_u32(0b0101_1001u32), 0b0000_0000u32);
     }
diff --git a/crates/core_arch/src/x86_64/abm.rs b/crates/core_arch/src/x86_64/abm.rs
index bf59cc4632..63e422864d 100644
--- a/crates/core_arch/src/x86_64/abm.rs
+++ b/crates/core_arch/src/x86_64/abm.rs
@@ -29,7 +29,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "lzcnt")]
 #[cfg_attr(test, assert_instr(lzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _lzcnt_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _lzcnt_u64(x: u64) -> u64 {
     x.leading_zeros() as u64
 }
 
@@ -40,23 +41,25 @@ pub fn _lzcnt_u64(x: u64) -> u64 {
 #[target_feature(enable = "popcnt")]
 #[cfg_attr(test, assert_instr(popcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _popcnt64(x: i64) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _popcnt64(x: i64) -> i32 {
     x.count_ones() as i32
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::arch::x86_64::*;
 
     #[simd_test(enable = "lzcnt")]
-    unsafe fn test_lzcnt_u64() {
+    const unsafe fn test_lzcnt_u64() {
         assert_eq!(_lzcnt_u64(0b0101_1010), 57);
     }
 
     #[simd_test(enable = "popcnt")]
-    unsafe fn test_popcnt64() {
+    const unsafe fn test_popcnt64() {
         assert_eq!(_popcnt64(0b0101_1010), 4);
     }
 }
diff --git a/crates/core_arch/src/x86_64/bmi.rs b/crates/core_arch/src/x86_64/bmi.rs
index 5d204d51ae..ee41d41375 100644
--- a/crates/core_arch/src/x86_64/bmi.rs
+++ b/crates/core_arch/src/x86_64/bmi.rs
@@ -48,7 +48,8 @@ pub fn _bextr2_u64(a: u64, control: u64) -> u64 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(andn))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _andn_u64(a: u64, b: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _andn_u64(a: u64, b: u64) -> u64 {
     !a & b
 }
 
@@ -60,7 +61,8 @@ pub fn _andn_u64(a: u64, b: u64) -> u64 {
 #[cfg_attr(test, assert_instr(blsi))]
 #[cfg(not(target_arch = "x86"))] // generates lots of instructions
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsi_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsi_u64(x: u64) -> u64 {
     x & x.wrapping_neg()
 }
 
@@ -72,7 +74,8 @@ pub fn _blsi_u64(x: u64) -> u64 {
 #[cfg_attr(test, assert_instr(blsmsk))]
 #[cfg(not(target_arch = "x86"))] // generates lots of instructions
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsmsk_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsmsk_u64(x: u64) -> u64 {
     x ^ (x.wrapping_sub(1_u64))
 }
 
@@ -86,7 +89,8 @@ pub fn _blsmsk_u64(x: u64) -> u64 {
 #[cfg_attr(test, assert_instr(blsr))]
 #[cfg(not(target_arch = "x86"))] // generates lots of instructions
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsr_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsr_u64(x: u64) -> u64 {
     x & (x.wrapping_sub(1))
 }
 
@@ -99,7 +103,8 @@ pub fn _blsr_u64(x: u64) -> u64 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _tzcnt_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _tzcnt_u64(x: u64) -> u64 {
     x.trailing_zeros() as u64
 }
 
@@ -112,7 +117,8 @@ pub fn _tzcnt_u64(x: u64) -> u64 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_tzcnt_64(x: u64) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_tzcnt_64(x: u64) -> i64 {
     x.trailing_zeros() as i64
 }
 
@@ -123,6 +129,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::{x86::*, x86_64::*};
@@ -134,7 +141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_andn_u64() {
+    const unsafe fn test_andn_u64() {
         assert_eq!(_andn_u64(0, 0), 0);
         assert_eq!(_andn_u64(0, 1), 1);
         assert_eq!(_andn_u64(1, 0), 0);
@@ -157,25 +164,25 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_blsi_u64() {
+    const unsafe fn test_blsi_u64() {
         assert_eq!(_blsi_u64(0b1101_0000u64), 0b0001_0000u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_blsmsk_u64() {
+    const unsafe fn test_blsmsk_u64() {
         let r = _blsmsk_u64(0b0011_0000u64);
         assert_eq!(r, 0b0001_1111u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_blsr_u64() {
+    const unsafe fn test_blsr_u64() {
         // TODO: test the behavior when the input is `0`.
         let r = _blsr_u64(0b0011_0000u64);
         assert_eq!(r, 0b0010_0000u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_tzcnt_u64() {
+    const unsafe fn test_tzcnt_u64() {
         assert_eq!(_tzcnt_u64(0b0000_0001u64), 0u64);
         assert_eq!(_tzcnt_u64(0b0000_0000u64), 64u64);
         assert_eq!(_tzcnt_u64(0b1001_0000u64), 4u64);
diff --git a/crates/core_arch/src/x86_64/bmi2.rs b/crates/core_arch/src/x86_64/bmi2.rs
index ea9daf8857..4eb53ed5ea 100644
--- a/crates/core_arch/src/x86_64/bmi2.rs
+++ b/crates/core_arch/src/x86_64/bmi2.rs
@@ -24,7 +24,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "bmi2")]
 #[cfg(not(target_arch = "x86"))] // calls an intrinsic
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mulx_u64(a: u64, b: u64, hi: &mut u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mulx_u64(a: u64, b: u64, hi: &mut u64) -> u64 {
     let result: u128 = (a as u128) * (b as u128);
     *hi = (result >> 64) as u64;
     result as u64
@@ -79,6 +80,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86_64::*;
@@ -120,7 +122,7 @@ mod tests {
 
     #[simd_test(enable = "bmi2")]
     #[rustfmt::skip]
-    unsafe fn test_mulx_u64() {
+const     unsafe fn test_mulx_u64() {
         let a: u64 = 9_223_372_036_854_775_800;
         let b: u64 = 100;
         let mut hi = 0;
diff --git a/crates/core_arch/src/x86_64/bswap.rs b/crates/core_arch/src/x86_64/bswap.rs
index 4e2d8b96ea..1b1d739a62 100644
--- a/crates/core_arch/src/x86_64/bswap.rs
+++ b/crates/core_arch/src/x86_64/bswap.rs
@@ -11,16 +11,20 @@ use stdarch_test::assert_instr;
 #[inline]
 #[cfg_attr(test, assert_instr(bswap))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _bswap64(x: i64) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _bswap64(x: i64) -> i64 {
     x.swap_bytes()
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
+    use stdarch_test::simd_test;
+
     use super::*;
 
-    #[test]
-    fn test_bswap64() {
+    #[simd_test]
+    const fn test_bswap64() {
         assert_eq!(_bswap64(0x0EADBEEFFADECA0E), 0x0ECADEFAEFBEAD0E);
         assert_eq!(_bswap64(0x0000000000000000), 0x0000000000000000);
     }
diff --git a/crates/core_arch/src/x86_64/tbm.rs b/crates/core_arch/src/x86_64/tbm.rs
index f4bba709f6..e7d4b8d3e4 100644
--- a/crates/core_arch/src/x86_64/tbm.rs
+++ b/crates/core_arch/src/x86_64/tbm.rs
@@ -42,7 +42,8 @@ pub fn _bextri_u64<const CONTROL: u64>(a: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcfill))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcfill_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcfill_u64(x: u64) -> u64 {
     x & x.wrapping_add(1)
 }
 
@@ -53,7 +54,8 @@ pub fn _blcfill_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blci))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blci_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blci_u64(x: u64) -> u64 {
     x | !x.wrapping_add(1)
 }
 
@@ -64,7 +66,8 @@ pub fn _blci_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcic))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcic_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcic_u64(x: u64) -> u64 {
     !x & x.wrapping_add(1)
 }
 
@@ -76,7 +79,8 @@ pub fn _blcic_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcmsk))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcmsk_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcmsk_u64(x: u64) -> u64 {
     x ^ x.wrapping_add(1)
 }
 
@@ -87,7 +91,8 @@ pub fn _blcmsk_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blcs))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blcs_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blcs_u64(x: u64) -> u64 {
     x | x.wrapping_add(1)
 }
 
@@ -98,7 +103,8 @@ pub fn _blcs_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blsfill))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsfill_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsfill_u64(x: u64) -> u64 {
     x | x.wrapping_sub(1)
 }
 
@@ -109,7 +115,8 @@ pub fn _blsfill_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(blsic))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _blsic_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _blsic_u64(x: u64) -> u64 {
     !x | x.wrapping_sub(1)
 }
 
@@ -121,7 +128,8 @@ pub fn _blsic_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(t1mskc))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _t1mskc_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _t1mskc_u64(x: u64) -> u64 {
     !x | x.wrapping_add(1)
 }
 
@@ -133,12 +141,14 @@ pub fn _t1mskc_u64(x: u64) -> u64 {
 #[target_feature(enable = "tbm")]
 #[cfg_attr(test, assert_instr(tzmsk))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _tzmsk_u64(x: u64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _tzmsk_u64(x: u64) -> u64 {
     !x & x.wrapping_sub(1)
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86_64::*;
@@ -149,13 +159,13 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcfill_u64() {
+    const unsafe fn test_blcfill_u64() {
         assert_eq!(_blcfill_u64(0b0101_0111u64), 0b0101_0000u64);
         assert_eq!(_blcfill_u64(0b1111_1111u64), 0u64);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blci_u64() {
+    const unsafe fn test_blci_u64() {
         assert_eq!(
             _blci_u64(0b0101_0000u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1110u64
@@ -167,25 +177,25 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcic_u64() {
+    const unsafe fn test_blcic_u64() {
         assert_eq!(_blcic_u64(0b0101_0001u64), 0b0000_0010u64);
         assert_eq!(_blcic_u64(0b1111_1111u64), 0b1_0000_0000u64);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcmsk_u64() {
+    const unsafe fn test_blcmsk_u64() {
         assert_eq!(_blcmsk_u64(0b0101_0001u64), 0b0000_0011u64);
         assert_eq!(_blcmsk_u64(0b1111_1111u64), 0b1_1111_1111u64);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blcs_u64() {
+    const unsafe fn test_blcs_u64() {
         assert_eq!(_blcs_u64(0b0101_0001u64), 0b0101_0011u64);
         assert_eq!(_blcs_u64(0b1111_1111u64), 0b1_1111_1111u64);
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blsfill_u64() {
+    const unsafe fn test_blsfill_u64() {
         assert_eq!(_blsfill_u64(0b0101_0100u64), 0b0101_0111u64);
         assert_eq!(
             _blsfill_u64(0u64),
@@ -194,7 +204,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_blsic_u64() {
+    const unsafe fn test_blsic_u64() {
         assert_eq!(
             _blsic_u64(0b0101_0100u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1011u64
@@ -206,7 +216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_t1mskc_u64() {
+    const unsafe fn test_t1mskc_u64() {
         assert_eq!(
             _t1mskc_u64(0b0101_0111u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64
@@ -218,7 +228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_tzmsk_u64() {
+    const unsafe fn test_tzmsk_u64() {
         assert_eq!(_tzmsk_u64(0b0101_1000u64), 0b0000_0111u64);
         assert_eq!(_tzmsk_u64(0b0101_1001u64), 0b0000_0000u64);
     }

From 962e4abf7486c7b7a49ee5f5406ce720cba24890 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:11:09 +0530
Subject: [PATCH 052/326] Make `sse` functions const

---
 crates/core_arch/src/x86/sse.rs    | 361 ++++++++++++++---------------
 crates/core_arch/src/x86_64/sse.rs |  44 ++--
 2 files changed, 201 insertions(+), 204 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 7dd96dd1c9..165c61104e 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -18,7 +18,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(addss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_ss(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_ss(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_insert!(a, 0, _mm_cvtss_f32(a) + _mm_cvtss_f32(b)) }
 }
 
@@ -30,7 +31,8 @@ pub fn _mm_add_ss(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(addps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_add(a, b) }
 }
 
@@ -42,7 +44,8 @@ pub fn _mm_add_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(subss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_ss(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_ss(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_insert!(a, 0, _mm_cvtss_f32(a) - _mm_cvtss_f32(b)) }
 }
 
@@ -54,7 +57,8 @@ pub fn _mm_sub_ss(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(subps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_sub(a, b) }
 }
 
@@ -66,7 +70,8 @@ pub fn _mm_sub_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(mulss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mul_ss(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_ss(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_insert!(a, 0, _mm_cvtss_f32(a) * _mm_cvtss_f32(b)) }
 }
 
@@ -78,7 +83,8 @@ pub fn _mm_mul_ss(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(mulps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mul_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_mul(a, b) }
 }
 
@@ -90,7 +96,8 @@ pub fn _mm_mul_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(divss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_div_ss(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_div_ss(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_insert!(a, 0, _mm_cvtss_f32(a) / _mm_cvtss_f32(b)) }
 }
 
@@ -102,7 +109,8 @@ pub fn _mm_div_ss(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(divps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_div_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_div_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_div(a, b) }
 }
 
@@ -241,7 +249,8 @@ pub fn _mm_max_ps(a: __m128, b: __m128) -> __m128 {
     assert_instr(andps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_and_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_and_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let a: __m128i = mem::transmute(a);
         let b: __m128i = mem::transmute(b);
@@ -264,7 +273,8 @@ pub fn _mm_and_ps(a: __m128, b: __m128) -> __m128 {
     assert_instr(andnps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_andnot_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_andnot_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let a: __m128i = mem::transmute(a);
         let b: __m128i = mem::transmute(b);
@@ -284,7 +294,8 @@ pub fn _mm_andnot_ps(a: __m128, b: __m128) -> __m128 {
     assert_instr(orps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_or_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_or_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let a: __m128i = mem::transmute(a);
         let b: __m128i = mem::transmute(b);
@@ -304,7 +315,8 @@ pub fn _mm_or_ps(a: __m128, b: __m128) -> __m128 {
     assert_instr(xorps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_xor_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_xor_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let a: __m128i = mem::transmute(a);
         let b: __m128i = mem::transmute(b);
@@ -866,7 +878,8 @@ pub fn _mm_cvtt_ss2si(a: __m128) -> i32 {
 // No point in using assert_instrs. In Unix x86_64 calling convention this is a
 // no-op, and on msvc it's just a `mov`.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtss_f32(a: __m128) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtss_f32(a: __m128) -> f32 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -881,7 +894,8 @@ pub fn _mm_cvtss_f32(a: __m128) -> f32 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(cvtsi2ss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi32_ss(a: __m128, b: i32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi32_ss(a: __m128, b: i32) -> __m128 {
     unsafe { simd_insert!(a, 0, b as f32) }
 }
 
@@ -904,7 +918,8 @@ pub fn _mm_cvt_si2ss(a: __m128, b: i32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_ss(a: f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_ss(a: f32) -> __m128 {
     __m128([a, 0.0, 0.0, 0.0])
 }
 
@@ -915,7 +930,8 @@ pub fn _mm_set_ss(a: f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(shufps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set1_ps(a: f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_ps(a: f32) -> __m128 {
     __m128([a, a, a, a])
 }
 
@@ -926,7 +942,8 @@ pub fn _mm_set1_ps(a: f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(shufps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_ps1(a: f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_ps1(a: f32) -> __m128 {
     _mm_set1_ps(a)
 }
 
@@ -953,7 +970,8 @@ pub fn _mm_set_ps1(a: f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(unpcklps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
     __m128([d, c, b, a])
 }
 
@@ -979,7 +997,8 @@ pub fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
     assert_instr(movaps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setr_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setr_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
     __m128([a, b, c, d])
 }
 
@@ -990,7 +1009,8 @@ pub fn _mm_setr_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(xorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setzero_ps() -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setzero_ps() -> __m128 {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -1021,7 +1041,8 @@ pub const fn _MM_SHUFFLE(z: u32, y: u32, x: u32, w: u32) -> i32 {
 #[cfg_attr(test, assert_instr(shufps, MASK = 3))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_shuffle_ps<const MASK: i32>(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shuffle_ps<const MASK: i32>(a: __m128, b: __m128) -> __m128 {
     static_assert_uimm_bits!(MASK, 8);
     unsafe {
         simd_shuffle!(
@@ -1045,7 +1066,8 @@ pub fn _mm_shuffle_ps<const MASK: i32>(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(unpckhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpackhi_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpackhi_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
 
@@ -1057,7 +1079,8 @@ pub fn _mm_unpackhi_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(unpcklps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpacklo_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpacklo_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
 
@@ -1069,7 +1092,8 @@ pub fn _mm_unpacklo_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movhlps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movehl_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movehl_ps(a: __m128, b: __m128) -> __m128 {
     // TODO; figure why this is a different instruction on msvc?
     unsafe { simd_shuffle!(a, b, [6, 7, 2, 3]) }
 }
@@ -1082,7 +1106,8 @@ pub fn _mm_movehl_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movlhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movelh_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movelh_ps(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, b, [0, 1, 4, 5]) }
 }
 
@@ -1096,12 +1121,13 @@ pub fn _mm_movelh_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movmskps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movemask_ps(a: __m128) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movemask_ps(a: __m128) -> i32 {
     // Propagate the highest bit to the rest, because simd_bitmask
     // requires all-1 or all-0.
     unsafe {
         let mask: i32x4 = simd_lt(transmute(a), i32x4::ZERO);
-        simd_bitmask::<i32x4, u8>(mask).into()
+        simd_bitmask::<i32x4, u8>(mask) as i32
     }
 }
 
@@ -1115,7 +1141,8 @@ pub fn _mm_movemask_ps(a: __m128) -> i32 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load_ss(p: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_ss(p: *const f32) -> __m128 {
     __m128([*p, 0.0, 0.0, 0.0])
 }
 
@@ -1130,7 +1157,8 @@ pub unsafe fn _mm_load_ss(p: *const f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load1_ps(p: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load1_ps(p: *const f32) -> __m128 {
     let a = *p;
     __m128([a, a, a, a])
 }
@@ -1142,7 +1170,8 @@ pub unsafe fn _mm_load1_ps(p: *const f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load_ps1(p: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_ps1(p: *const f32) -> __m128 {
     _mm_load1_ps(p)
 }
 
@@ -1166,7 +1195,8 @@ pub unsafe fn _mm_load_ps1(p: *const f32) -> __m128 {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_load_ps(p: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_ps(p: *const f32) -> __m128 {
     *(p as *const __m128)
 }
 
@@ -1183,7 +1213,8 @@ pub unsafe fn _mm_load_ps(p: *const f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movups))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadu_ps(p: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_ps(p: *const f32) -> __m128 {
     // Note: Using `*p` would require `f32` alignment, but `movups` has no
     // alignment restrictions.
     let mut dst = _mm_undefined_ps();
@@ -1223,7 +1254,8 @@ pub unsafe fn _mm_loadu_ps(p: *const f32) -> __m128 {
     assert_instr(movaps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
     let a = _mm_load_ps(p);
     simd_shuffle!(a, a, [3, 2, 1, 0])
 }
@@ -1237,7 +1269,8 @@ pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_store_ss(p: *mut f32, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_ss(p: *mut f32, a: __m128) {
     *p = simd_extract!(a, 0);
 }
 
@@ -1267,7 +1300,8 @@ pub unsafe fn _mm_store_ss(p: *mut f32, a: __m128) {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
     let b: __m128 = simd_shuffle!(a, a, [0, 0, 0, 0]);
     *(p as *mut __m128) = b;
 }
@@ -1282,7 +1316,8 @@ pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
     assert_instr(movaps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
     _mm_store1_ps(p, a);
 }
 
@@ -1305,7 +1340,8 @@ pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_store_ps(p: *mut f32, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_ps(p: *mut f32, a: __m128) {
     *(p as *mut __m128) = a;
 }
 
@@ -1320,7 +1356,8 @@ pub unsafe fn _mm_store_ps(p: *mut f32, a: __m128) {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movups))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_storeu_ps(p: *mut f32, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_ps(p: *mut f32, a: __m128) {
     ptr::copy_nonoverlapping(
         ptr::addr_of!(a) as *const u8,
         p as *mut u8,
@@ -1352,7 +1389,8 @@ pub unsafe fn _mm_storeu_ps(p: *mut f32, a: __m128) {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_storer_ps(p: *mut f32, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storer_ps(p: *mut f32, a: __m128) {
     let b: __m128 = simd_shuffle!(a, a, [3, 2, 1, 0]);
     *(p as *mut __m128) = b;
 }
@@ -1370,7 +1408,8 @@ pub unsafe fn _mm_storer_ps(p: *mut f32, a: __m128) {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(movss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_move_ss(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_move_ss(a: __m128, b: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, b, [4, 1, 2, 3]) }
 }
 
@@ -1917,7 +1956,8 @@ pub fn _mm_prefetch<const STRATEGY: i32>(p: *const i8) {
 #[inline]
 #[target_feature(enable = "sse")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_undefined_ps() -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_undefined_ps() -> __m128 {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -1928,7 +1968,8 @@ pub fn _mm_undefined_ps() -> __m128 {
 #[allow(non_snake_case)]
 #[target_feature(enable = "sse")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _MM_TRANSPOSE4_PS(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _MM_TRANSPOSE4_PS(
     row0: &mut __m128,
     row1: &mut __m128,
     row2: &mut __m128,
@@ -2037,6 +2078,7 @@ pub unsafe fn _mm_stream_ps(mem_addr: *mut f32, a: __m128) {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use crate::{hint::black_box, mem::transmute, ptr};
     use std::boxed;
     use stdarch_test::simd_test;
@@ -2046,7 +2088,7 @@ mod tests {
     const NAN: f32 = f32::NAN;
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_add_ps() {
+    const unsafe fn test_mm_add_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_add_ps(a, b);
@@ -2054,7 +2096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_add_ss() {
+    const unsafe fn test_mm_add_ss() {
         let a = _mm_set_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_set_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_add_ss(a, b);
@@ -2062,7 +2104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_sub_ps() {
+    const unsafe fn test_mm_sub_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_sub_ps(a, b);
@@ -2070,7 +2112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_sub_ss() {
+    const unsafe fn test_mm_sub_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_sub_ss(a, b);
@@ -2078,7 +2120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_mul_ps() {
+    const unsafe fn test_mm_mul_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_mul_ps(a, b);
@@ -2086,7 +2128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_mul_ss() {
+    const unsafe fn test_mm_mul_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_mul_ss(a, b);
@@ -2094,7 +2136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_div_ps() {
+    const unsafe fn test_mm_div_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 2.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.2, -5.0);
         let r = _mm_div_ps(a, b);
@@ -2102,7 +2144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_div_ss() {
+    const unsafe fn test_mm_div_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_div_ss(a, b);
@@ -2229,7 +2271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_and_ps() {
+    const unsafe fn test_mm_and_ps() {
         let a = transmute(u32x4::splat(0b0011));
         let b = transmute(u32x4::splat(0b0101));
         let r = _mm_and_ps(*black_box(&a), *black_box(&b));
@@ -2238,7 +2280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_andnot_ps() {
+    const unsafe fn test_mm_andnot_ps() {
         let a = transmute(u32x4::splat(0b0011));
         let b = transmute(u32x4::splat(0b0101));
         let r = _mm_andnot_ps(*black_box(&a), *black_box(&b));
@@ -2247,7 +2289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_or_ps() {
+    const unsafe fn test_mm_or_ps() {
         let a = transmute(u32x4::splat(0b0011));
         let b = transmute(u32x4::splat(0b0101));
         let r = _mm_or_ps(*black_box(&a), *black_box(&b));
@@ -2256,7 +2298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_xor_ps() {
+    const unsafe fn test_mm_xor_ps() {
         let a = transmute(u32x4::splat(0b0011));
         let b = transmute(u32x4::splat(0b0101));
         let r = _mm_xor_ps(*black_box(&a), *black_box(&b));
@@ -2979,36 +3021,40 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtsi32_ss() {
-        let inputs = &[
-            (4555i32, 4555.0f32),
-            (322223333, 322223330.0),
-            (-432, -432.0),
-            (-322223333, -322223330.0),
-        ];
+    const unsafe fn test_mm_cvtsi32_ss() {
+        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-        for &(x, f) in inputs.iter() {
-            let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
-            let r = _mm_cvtsi32_ss(a, x);
-            let e = _mm_setr_ps(f, 6.0, 7.0, 8.0);
-            assert_eq_m128(e, r);
-        }
+        let r = _mm_cvtsi32_ss(a, 4555);
+        let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi32_ss(a, 322223333);
+        let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi32_ss(a, -432);
+        let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi32_ss(a, -322223333);
+        let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtss_f32() {
+    const unsafe fn test_mm_cvtss_f32() {
         let a = _mm_setr_ps(312.0134, 5.0, 6.0, 7.0);
         assert_eq!(_mm_cvtss_f32(a), 312.0134);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_set_ss() {
+    const unsafe fn test_mm_set_ss() {
         let r = _mm_set_ss(black_box(4.25));
         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_set1_ps() {
+    const unsafe fn test_mm_set1_ps() {
         let r1 = _mm_set1_ps(black_box(4.25));
         let r2 = _mm_set_ps1(black_box(4.25));
         assert_eq!(get_m128(r1, 0), 4.25);
@@ -3022,7 +3068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_set_ps() {
+    const unsafe fn test_mm_set_ps() {
         let r = _mm_set_ps(
             black_box(1.0),
             black_box(2.0),
@@ -3036,7 +3082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_setr_ps() {
+    const unsafe fn test_mm_setr_ps() {
         let r = _mm_setr_ps(
             black_box(1.0),
             black_box(2.0),
@@ -3047,21 +3093,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_setzero_ps() {
+    const unsafe fn test_mm_setzero_ps() {
         let r = *black_box(&_mm_setzero_ps());
         assert_eq_m128(r, _mm_set1_ps(0.0));
     }
 
-    #[test]
+    #[simd_test]
     #[allow(non_snake_case)]
-    fn test_MM_SHUFFLE() {
+    const fn test_MM_SHUFFLE() {
         assert_eq!(_MM_SHUFFLE(0, 1, 1, 3), 0b00_01_01_11);
         assert_eq!(_MM_SHUFFLE(3, 1, 1, 0), 0b11_01_01_00);
         assert_eq!(_MM_SHUFFLE(1, 2, 2, 1), 0b01_10_10_01);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_shuffle_ps() {
+    const unsafe fn test_mm_shuffle_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_shuffle_ps::<0b00_01_01_11>(a, b);
@@ -3069,7 +3115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_unpackhi_ps() {
+    const unsafe fn test_mm_unpackhi_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_unpackhi_ps(a, b);
@@ -3077,7 +3123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_unpacklo_ps() {
+    const unsafe fn test_mm_unpacklo_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_unpacklo_ps(a, b);
@@ -3085,7 +3131,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_movehl_ps() {
+    const unsafe fn test_mm_movehl_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_movehl_ps(a, b);
@@ -3093,7 +3139,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_movelh_ps() {
+    const unsafe fn test_mm_movelh_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_movelh_ps(a, b);
@@ -3101,43 +3147,35 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_load_ss() {
+    const unsafe fn test_mm_load_ss() {
         let a = 42.0f32;
         let r = _mm_load_ss(ptr::addr_of!(a));
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_load1_ps() {
+    const unsafe fn test_mm_load1_ps() {
         let a = 42.0f32;
         let r = _mm_load1_ps(ptr::addr_of!(a));
         assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_load_ps() {
-        let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
-
-        let mut p = vals.as_ptr();
-        let mut fixup = 0.0f32;
+    const unsafe fn test_mm_load_ps() {
+        let vals = Memory {
+            data: [1.0f32, 2.0, 3.0, 4.0],
+        };
 
-        // Make sure p is aligned, otherwise we might get a
-        // (signal: 11, SIGSEGV: invalid memory reference)
-
-        let unalignment = (p as usize) & 0xf;
-        if unalignment != 0 {
-            let delta = (16 - unalignment) >> 2;
-            fixup = delta as f32;
-            p = p.add(delta);
-        }
+        // guaranteed to be aligned to 16 bytes
+        let p = vals.data.as_ptr();
 
         let r = _mm_load_ps(p);
-        let e = _mm_add_ps(_mm_setr_ps(1.0, 2.0, 3.0, 4.0), _mm_set1_ps(fixup));
+        let e = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_loadu_ps() {
+    const unsafe fn test_mm_loadu_ps() {
         let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = vals.as_ptr().add(3);
         let r = _mm_loadu_ps(black_box(p));
@@ -3145,29 +3183,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_loadr_ps() {
-        let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
-
-        let mut p = vals.as_ptr();
-        let mut fixup = 0.0f32;
+    const unsafe fn test_mm_loadr_ps() {
+        let vals = Memory {
+            data: [1.0f32, 2.0, 3.0, 4.0],
+        };
 
-        // Make sure p is aligned, otherwise we might get a
-        // (signal: 11, SIGSEGV: invalid memory reference)
-
-        let unalignment = (p as usize) & 0xf;
-        if unalignment != 0 {
-            let delta = (16 - unalignment) >> 2;
-            fixup = delta as f32;
-            p = p.add(delta);
-        }
+        // guaranteed to be aligned to 16 bytes
+        let p = vals.data.as_ptr();
 
         let r = _mm_loadr_ps(p);
-        let e = _mm_add_ps(_mm_setr_ps(4.0, 3.0, 2.0, 1.0), _mm_set1_ps(fixup));
+        let e = _mm_setr_ps(4.0, 3.0, 2.0, 1.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_store_ss() {
+    const unsafe fn test_mm_store_ss() {
         let mut vals = [0.0f32; 8];
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         _mm_store_ss(vals.as_mut_ptr().add(1), a);
@@ -3178,110 +3208,65 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_store1_ps() {
-        let mut vals = [0.0f32; 8];
+    const unsafe fn test_mm_store1_ps() {
+        let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
-        let mut ofs = 0;
-        let mut p = vals.as_mut_ptr();
-
-        if (p as usize) & 0xf != 0 {
-            ofs = (16 - ((p as usize) & 0xf)) >> 2;
-            p = p.add(ofs);
-        }
+        // guaranteed to be aligned to 16 bytes
+        let p = vals.data.as_mut_ptr();
 
         _mm_store1_ps(p, *black_box(&a));
 
-        if ofs > 0 {
-            assert_eq!(vals[ofs - 1], 0.0);
-        }
-        assert_eq!(vals[ofs + 0], 1.0);
-        assert_eq!(vals[ofs + 1], 1.0);
-        assert_eq!(vals[ofs + 2], 1.0);
-        assert_eq!(vals[ofs + 3], 1.0);
-        assert_eq!(vals[ofs + 4], 0.0);
+        assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_store_ps() {
-        let mut vals = [0.0f32; 8];
+    const unsafe fn test_mm_store_ps() {
+        let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
-        let mut ofs = 0;
-        let mut p = vals.as_mut_ptr();
-
-        // Align p to 16-byte boundary
-        if (p as usize) & 0xf != 0 {
-            ofs = (16 - ((p as usize) & 0xf)) >> 2;
-            p = p.add(ofs);
-        }
+        // guaranteed to be aligned to 16 bytes
+        let p = vals.data.as_mut_ptr();
 
         _mm_store_ps(p, *black_box(&a));
 
-        if ofs > 0 {
-            assert_eq!(vals[ofs - 1], 0.0);
-        }
-        assert_eq!(vals[ofs + 0], 1.0);
-        assert_eq!(vals[ofs + 1], 2.0);
-        assert_eq!(vals[ofs + 2], 3.0);
-        assert_eq!(vals[ofs + 3], 4.0);
-        assert_eq!(vals[ofs + 4], 0.0);
+        assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_storer_ps() {
-        let mut vals = [0.0f32; 8];
+    const unsafe fn test_mm_storer_ps() {
+        let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
-        let mut ofs = 0;
-        let mut p = vals.as_mut_ptr();
-
-        // Align p to 16-byte boundary
-        if (p as usize) & 0xf != 0 {
-            ofs = (16 - ((p as usize) & 0xf)) >> 2;
-            p = p.add(ofs);
-        }
+        // guaranteed to be aligned to 16 bytes
+        let p = vals.data.as_mut_ptr();
 
         _mm_storer_ps(p, *black_box(&a));
 
-        if ofs > 0 {
-            assert_eq!(vals[ofs - 1], 0.0);
-        }
-        assert_eq!(vals[ofs + 0], 4.0);
-        assert_eq!(vals[ofs + 1], 3.0);
-        assert_eq!(vals[ofs + 2], 2.0);
-        assert_eq!(vals[ofs + 3], 1.0);
-        assert_eq!(vals[ofs + 4], 0.0);
+        assert_eq!(vals.data, [4.0, 3.0, 2.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_storeu_ps() {
-        let mut vals = [0.0f32; 8];
-        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+    const unsafe fn test_mm_storeu_ps() {
+        #[repr(align(16))]
+        struct Memory8 {
+            data: [f32; 8],
+        }
 
-        let mut ofs = 0;
-        let mut p = vals.as_mut_ptr();
+        // guaranteed to be aligned to 16 bytes
+        let mut vals = Memory8 { data: [0.0f32; 8] };
+        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
-        // Make sure p is **not** aligned to 16-byte boundary
-        if (p as usize) & 0xf == 0 {
-            ofs = 1;
-            p = p.add(1);
-        }
+        // guaranteed to be *not* aligned to 16 bytes
+        let p = vals.data.as_mut_ptr().offset(1);
 
         _mm_storeu_ps(p, *black_box(&a));
 
-        if ofs > 0 {
-            assert_eq!(vals[ofs - 1], 0.0);
-        }
-        assert_eq!(vals[ofs + 0], 1.0);
-        assert_eq!(vals[ofs + 1], 2.0);
-        assert_eq!(vals[ofs + 2], 3.0);
-        assert_eq!(vals[ofs + 3], 4.0);
-        assert_eq!(vals[ofs + 4], 0.0);
+        assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_move_ss() {
+    const unsafe fn test_mm_move_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
@@ -3291,7 +3276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_movemask_ps() {
+    const unsafe fn test_mm_movemask_ps() {
         let r = _mm_movemask_ps(_mm_setr_ps(-1.0, 5.0, -5.0, 0.0));
         assert_eq!(r, 0b0101);
 
@@ -3307,7 +3292,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_MM_TRANSPOSE4_PS() {
+    const unsafe fn test_MM_TRANSPOSE4_PS() {
         let mut a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let mut b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let mut c = _mm_setr_ps(9.0, 10.0, 11.0, 12.0);
diff --git a/crates/core_arch/src/x86_64/sse.rs b/crates/core_arch/src/x86_64/sse.rs
index 6bd7ec83ec..e5c1f79153 100644
--- a/crates/core_arch/src/x86_64/sse.rs
+++ b/crates/core_arch/src/x86_64/sse.rs
@@ -62,13 +62,15 @@ pub fn _mm_cvttss_si64(a: __m128) -> i64 {
 #[target_feature(enable = "sse")]
 #[cfg_attr(test, assert_instr(cvtsi2ss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi64_ss(a: __m128, b: i64) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi64_ss(a: __m128, b: i64) -> __m128 {
     unsafe { simd_insert!(a, 0, b as f32) }
 }
 
 #[cfg(test)]
 mod tests {
     use crate::core_arch::arch::x86_64::*;
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse")]
@@ -123,21 +125,31 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtsi64_ss() {
-        let inputs = &[
-            (4555i64, 4555.0f32),
-            (322223333, 322223330.0),
-            (-432, -432.0),
-            (-322223333, -322223330.0),
-            (9223372036854775807, 9.223372e18),
-            (-9223372036854775808, -9.223372e18),
-        ];
+    const unsafe fn test_mm_cvtsi64_ss() {
+        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-        for &(x, f) in inputs {
-            let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
-            let r = _mm_cvtsi64_ss(a, x);
-            let e = _mm_setr_ps(f, 6.0, 7.0, 8.0);
-            assert_eq_m128(e, r);
-        }
+        let r = _mm_cvtsi64_ss(a, 4555);
+        let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi64_ss(a, 322223333);
+        let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi64_ss(a, -432);
+        let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi64_ss(a, -322223333);
+        let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi64_ss(a, 9223372036854775807);
+        let e = _mm_setr_ps(9.223372e18, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvtsi64_ss(a, -9223372036854775808);
+        let e = _mm_setr_ps(-9.223372e18, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
     }
 }

From 36905a24dfcc5c41df2bc64887af1eb3c6a193af Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:11:14 +0530
Subject: [PATCH 053/326] Make `sse2` functions const

---
 crates/core_arch/src/x86/sse2.rs    | 768 ++++++++++++++++------------
 crates/core_arch/src/x86_64/sse2.rs |  25 +-
 2 files changed, 468 insertions(+), 325 deletions(-)

diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index 93fe7a7ae3..098cd67c02 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -76,7 +76,8 @@ pub fn _mm_mfence() {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_add(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -87,7 +88,8 @@ pub fn _mm_add_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_add(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -98,7 +100,8 @@ pub fn _mm_add_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_add(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -109,7 +112,8 @@ pub fn _mm_add_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_add(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -120,7 +124,8 @@ pub fn _mm_add_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_adds_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_adds_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_add(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -131,7 +136,8 @@ pub fn _mm_adds_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_adds_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_adds_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_add(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -142,7 +148,8 @@ pub fn _mm_adds_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddusb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_adds_epu8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_adds_epu8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_add(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -153,7 +160,8 @@ pub fn _mm_adds_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(paddusw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_adds_epu16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_adds_epu16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_add(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -164,7 +172,8 @@ pub fn _mm_adds_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pavgb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_avg_epu8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_avg_epu8(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let a = simd_cast::<_, u16x16>(a.as_u8x16());
         let b = simd_cast::<_, u16x16>(b.as_u8x16());
@@ -180,7 +189,8 @@ pub fn _mm_avg_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pavgw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let a = simd_cast::<_, u32x8>(a.as_u16x8());
         let b = simd_cast::<_, u32x8>(b.as_u16x8());
@@ -200,7 +210,8 @@ pub fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let r: i32x8 = simd_mul(simd_cast(a.as_i16x8()), simd_cast(b.as_i16x8()));
         let even: i32x4 = simd_shuffle!(r, r, [0, 2, 4, 6]);
@@ -217,7 +228,8 @@ pub fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmaxsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_i16x8(), b.as_i16x8()).as_m128i() }
 }
 
@@ -229,7 +241,8 @@ pub fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmaxub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_u8x16(), b.as_u8x16()).as_m128i() }
 }
 
@@ -241,7 +254,8 @@ pub fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pminsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_i16x8(), b.as_i16x8()).as_m128i() }
 }
 
@@ -253,7 +267,8 @@ pub fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pminub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_min_epu8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epu8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_u8x16(), b.as_u8x16()).as_m128i() }
 }
 
@@ -267,7 +282,8 @@ pub fn _mm_min_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmulhw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mulhi_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mulhi_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let a = simd_cast::<_, i32x8>(a.as_i16x8());
         let b = simd_cast::<_, i32x8>(b.as_i16x8());
@@ -286,7 +302,8 @@ pub fn _mm_mulhi_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmulhuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mulhi_epu16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mulhi_epu16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let a = simd_cast::<_, u32x8>(a.as_u16x8());
         let b = simd_cast::<_, u32x8>(b.as_u16x8());
@@ -305,7 +322,8 @@ pub fn _mm_mulhi_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmullw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mullo_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mullo_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_mul(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -319,11 +337,12 @@ pub fn _mm_mullo_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmuludq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mul_epu32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_epu32(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u64x2();
         let b = b.as_u64x2();
-        let mask = u64x2::splat(u32::MAX.into());
+        let mask = u64x2::splat(u32::MAX as u64);
         transmute(simd_mul(simd_and(a, mask), simd_and(b, mask)))
     }
 }
@@ -351,7 +370,8 @@ pub fn _mm_sad_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_sub(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -362,7 +382,8 @@ pub fn _mm_sub_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_sub(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -373,7 +394,8 @@ pub fn _mm_sub_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_sub(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -384,7 +406,8 @@ pub fn _mm_sub_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_sub(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -396,7 +419,8 @@ pub fn _mm_sub_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_subs_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_subs_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_sub(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -408,7 +432,8 @@ pub fn _mm_subs_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_subs_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_subs_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_sub(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -420,7 +445,8 @@ pub fn _mm_subs_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubusb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_subs_epu8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_subs_epu8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_sub(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -432,7 +458,8 @@ pub fn _mm_subs_epu8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(psubusw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_subs_epu16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_subs_epu16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_saturating_sub(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -444,7 +471,8 @@ pub fn _mm_subs_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pslldq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_slli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_slli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe { _mm_slli_si128_impl::<IMM8>(a) }
 }
@@ -453,7 +481,8 @@ pub fn _mm_slli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
 /// `_mm_slli_si128` intrinsic into a compile-time constant.
 #[inline]
 #[target_feature(enable = "sse2")]
-unsafe fn _mm_slli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+const unsafe fn _mm_slli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i {
     const fn mask(shift: i32, i: u32) -> u32 {
         let shift = shift as u32 & 0xff;
         if shift > 15 { i } else { 16 - shift + i }
@@ -490,7 +519,8 @@ unsafe fn _mm_slli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pslldq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_bslli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_bslli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         _mm_slli_si128_impl::<IMM8>(a)
@@ -505,7 +535,8 @@ pub fn _mm_bslli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psrldq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_bsrli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_bsrli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         _mm_srli_si128_impl::<IMM8>(a)
@@ -520,7 +551,8 @@ pub fn _mm_bsrli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psllw, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_slli_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_slli_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 16 {
@@ -551,7 +583,8 @@ pub fn _mm_sll_epi16(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pslld, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_slli_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_slli_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 32 {
@@ -582,7 +615,8 @@ pub fn _mm_sll_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psllq, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_slli_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_slli_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 64 {
@@ -614,7 +648,8 @@ pub fn _mm_sll_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srai_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srai_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe { transmute(simd_shr(a.as_i16x8(), i16x8::splat(IMM8.min(15) as i16))) }
 }
@@ -640,7 +675,8 @@ pub fn _mm_sra_epi16(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srai_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srai_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe { transmute(simd_shr(a.as_i32x4(), i32x4::splat(IMM8.min(31)))) }
 }
@@ -665,7 +701,8 @@ pub fn _mm_sra_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psrldq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe { _mm_srli_si128_impl::<IMM8>(a) }
 }
@@ -674,7 +711,8 @@ pub fn _mm_srli_si128<const IMM8: i32>(a: __m128i) -> __m128i {
 /// `_mm_srli_si128` intrinsic into a compile-time constant.
 #[inline]
 #[target_feature(enable = "sse2")]
-unsafe fn _mm_srli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+const unsafe fn _mm_srli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i {
     const fn mask(shift: i32, i: u32) -> u32 {
         if (shift as u32) > 15 {
             i + 16
@@ -716,7 +754,8 @@ unsafe fn _mm_srli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psrlw, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srli_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srli_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 16 {
@@ -748,7 +787,8 @@ pub fn _mm_srl_epi16(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psrld, IMM8 = 8))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srli_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srli_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 32 {
@@ -780,7 +820,8 @@ pub fn _mm_srl_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(psrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srli_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srli_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 64 {
@@ -811,7 +852,8 @@ pub fn _mm_srl_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(andps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_and_si128(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_and_si128(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_and(a, b) }
 }
 
@@ -823,7 +865,8 @@ pub fn _mm_and_si128(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(andnps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_andnot_si128(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_andnot_si128(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_and(simd_xor(_mm_set1_epi8(-1), a), b) }
 }
 
@@ -835,7 +878,8 @@ pub fn _mm_andnot_si128(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(orps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_or_si128(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_or_si128(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_or(a, b) }
 }
 
@@ -847,7 +891,8 @@ pub fn _mm_or_si128(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(xorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_xor_si128(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_xor_si128(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_xor(a, b) }
 }
 
@@ -858,7 +903,8 @@ pub fn _mm_xor_si128(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpeqb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpeq_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i8x16, _>(simd_eq(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -869,7 +915,8 @@ pub fn _mm_cmpeq_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpeqw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpeq_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i16x8, _>(simd_eq(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -880,7 +927,8 @@ pub fn _mm_cmpeq_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpeqd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpeq_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i32x4, _>(simd_eq(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -891,7 +939,8 @@ pub fn _mm_cmpeq_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpgtb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpgt_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i8x16, _>(simd_gt(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -902,7 +951,8 @@ pub fn _mm_cmpgt_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpgtw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpgt_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i16x8, _>(simd_gt(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -913,7 +963,8 @@ pub fn _mm_cmpgt_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpgtd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpgt_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i32x4, _>(simd_gt(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -924,7 +975,8 @@ pub fn _mm_cmpgt_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpgtb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmplt_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i8x16, _>(simd_lt(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -935,7 +987,8 @@ pub fn _mm_cmplt_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpgtw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmplt_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i16x8, _>(simd_lt(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -946,7 +999,8 @@ pub fn _mm_cmplt_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pcmpgtd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmplt_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i32x4, _>(simd_lt(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -958,7 +1012,8 @@ pub fn _mm_cmplt_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtdq2pd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi32_pd(a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi32_pd(a: __m128i) -> __m128d {
     unsafe {
         let a = a.as_i32x4();
         simd_cast::<i32x2, __m128d>(simd_shuffle!(a, a, [0, 1]))
@@ -973,7 +1028,8 @@ pub fn _mm_cvtepi32_pd(a: __m128i) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtsi2sd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi32_sd(a: __m128d, b: i32) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi32_sd(a: __m128d, b: i32) -> __m128d {
     unsafe { simd_insert!(a, 0, b as f64) }
 }
 
@@ -985,7 +1041,8 @@ pub fn _mm_cvtsi32_sd(a: __m128d, b: i32) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtdq2ps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi32_ps(a: __m128i) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi32_ps(a: __m128i) -> __m128 {
     unsafe { transmute(simd_cast::<_, f32x4>(a.as_i32x4())) }
 }
 
@@ -1008,7 +1065,8 @@ pub fn _mm_cvtps_epi32(a: __m128) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi32_si128(a: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi32_si128(a: i32) -> __m128i {
     unsafe { transmute(i32x4::new(a, 0, 0, 0)) }
 }
 
@@ -1018,7 +1076,8 @@ pub fn _mm_cvtsi32_si128(a: i32) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi128_si32(a: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi128_si32(a: __m128i) -> i32 {
     unsafe { simd_extract!(a.as_i32x4(), 0) }
 }
 
@@ -1030,7 +1089,8 @@ pub fn _mm_cvtsi128_si32(a: __m128i) -> i32 {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_epi64x(e1: i64, e0: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_epi64x(e1: i64, e0: i64) -> __m128i {
     unsafe { transmute(i64x2::new(e0, e1)) }
 }
 
@@ -1041,7 +1101,8 @@ pub fn _mm_set_epi64x(e1: i64, e0: i64) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
     unsafe { transmute(i32x4::new(e0, e1, e2, e3)) }
 }
 
@@ -1052,7 +1113,8 @@ pub fn _mm_set_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_epi16(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_epi16(
     e7: i16,
     e6: i16,
     e5: i16,
@@ -1072,7 +1134,8 @@ pub fn _mm_set_epi16(
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_epi8(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_epi8(
     e15: i8,
     e14: i8,
     e13: i8,
@@ -1105,7 +1168,8 @@ pub fn _mm_set_epi8(
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set1_epi64x(a: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_epi64x(a: i64) -> __m128i {
     _mm_set_epi64x(a, a)
 }
 
@@ -1116,7 +1180,8 @@ pub fn _mm_set1_epi64x(a: i64) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set1_epi32(a: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_epi32(a: i32) -> __m128i {
     _mm_set_epi32(a, a, a, a)
 }
 
@@ -1127,7 +1192,8 @@ pub fn _mm_set1_epi32(a: i32) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set1_epi16(a: i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_epi16(a: i16) -> __m128i {
     _mm_set_epi16(a, a, a, a, a, a, a, a)
 }
 
@@ -1138,7 +1204,8 @@ pub fn _mm_set1_epi16(a: i16) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set1_epi8(a: i8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_epi8(a: i8) -> __m128i {
     _mm_set_epi8(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
 }
 
@@ -1149,7 +1216,8 @@ pub fn _mm_set1_epi8(a: i8) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setr_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setr_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
     _mm_set_epi32(e0, e1, e2, e3)
 }
 
@@ -1160,7 +1228,8 @@ pub fn _mm_setr_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setr_epi16(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setr_epi16(
     e7: i16,
     e6: i16,
     e5: i16,
@@ -1180,7 +1249,8 @@ pub fn _mm_setr_epi16(
 #[target_feature(enable = "sse2")]
 // no particular instruction to test
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setr_epi8(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setr_epi8(
     e15: i8,
     e14: i8,
     e13: i8,
@@ -1211,7 +1281,8 @@ pub fn _mm_setr_epi8(
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(xorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setzero_si128() -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setzero_si128() -> __m128i {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -1221,7 +1292,8 @@ pub fn _mm_setzero_si128() -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadl_epi64(mem_addr: *const __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadl_epi64(mem_addr: *const __m128i) -> __m128i {
     _mm_set_epi64x(0, ptr::read_unaligned(mem_addr as *const i64))
 }
 
@@ -1237,7 +1309,8 @@ pub unsafe fn _mm_loadl_epi64(mem_addr: *const __m128i) -> __m128i {
     assert_instr(movaps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load_si128(mem_addr: *const __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_si128(mem_addr: *const __m128i) -> __m128i {
     *mem_addr
 }
 
@@ -1250,7 +1323,8 @@ pub unsafe fn _mm_load_si128(mem_addr: *const __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movups))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadu_si128(mem_addr: *const __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_si128(mem_addr: *const __m128i) -> __m128i {
     let mut dst: __m128i = _mm_undefined_si128();
     ptr::copy_nonoverlapping(
         mem_addr as *const u8,
@@ -1299,7 +1373,8 @@ pub unsafe fn _mm_maskmoveu_si128(a: __m128i, mask: __m128i, mem_addr: *mut i8)
     assert_instr(movaps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_store_si128(mem_addr: *mut __m128i, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_si128(mem_addr: *mut __m128i, a: __m128i) {
     *mem_addr = a;
 }
 
@@ -1312,7 +1387,8 @@ pub unsafe fn _mm_store_si128(mem_addr: *mut __m128i, a: __m128i) {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movups))] // FIXME movdqu expected
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_storeu_si128(mem_addr: *mut __m128i, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_si128(mem_addr: *mut __m128i, a: __m128i) {
     mem_addr.write_unaligned(a);
 }
 
@@ -1324,7 +1400,8 @@ pub unsafe fn _mm_storeu_si128(mem_addr: *mut __m128i, a: __m128i) {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_storel_epi64(mem_addr: *mut __m128i, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storel_epi64(mem_addr: *mut __m128i, a: __m128i) {
     ptr::copy_nonoverlapping(ptr::addr_of!(a) as *const u8, mem_addr as *mut u8, 8);
 }
 
@@ -1393,7 +1470,8 @@ pub unsafe fn _mm_stream_si32(mem_addr: *mut i32, a: i32) {
 // FIXME movd on msvc, movd on i686
 #[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(movq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_move_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_move_epi64(a: __m128i) -> __m128i {
     unsafe {
         let r: i64x2 = simd_shuffle!(a.as_i64x2(), i64x2::ZERO, [0, 2]);
         transmute(r)
@@ -1444,7 +1522,8 @@ pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pextrw, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_extract_epi16<const IMM8: i32>(a: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_extract_epi16<const IMM8: i32>(a: __m128i) -> i32 {
     static_assert_uimm_bits!(IMM8, 3);
     unsafe { simd_extract!(a.as_u16x8(), IMM8 as u32, u16) as i32 }
 }
@@ -1457,7 +1536,8 @@ pub fn _mm_extract_epi16<const IMM8: i32>(a: __m128i) -> i32 {
 #[cfg_attr(test, assert_instr(pinsrw, IMM8 = 7))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_insert_epi16<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_insert_epi16<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
     static_assert_uimm_bits!(IMM8, 3);
     unsafe { transmute(simd_insert!(a.as_i16x8(), IMM8 as u32, i as i16)) }
 }
@@ -1469,7 +1549,8 @@ pub fn _mm_insert_epi16<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmovmskb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movemask_epi8(a: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movemask_epi8(a: __m128i) -> i32 {
     unsafe {
         let z = i8x16::ZERO;
         let m: i8x16 = simd_lt(a.as_i8x16(), z);
@@ -1485,7 +1566,8 @@ pub fn _mm_movemask_epi8(a: __m128i) -> i32 {
 #[cfg_attr(test, assert_instr(pshufd, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_shuffle_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shuffle_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i32x4();
@@ -1515,7 +1597,8 @@ pub fn _mm_shuffle_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pshufhw, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_shufflehi_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shufflehi_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i16x8();
@@ -1549,7 +1632,8 @@ pub fn _mm_shufflehi_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pshuflw, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_shufflelo_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shufflelo_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i16x8();
@@ -1578,7 +1662,8 @@ pub fn _mm_shufflelo_epi16<const IMM8: i32>(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(punpckhbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpackhi_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpackhi_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         transmute::<i8x16, _>(simd_shuffle!(
             a.as_i8x16(),
@@ -1595,7 +1680,8 @@ pub fn _mm_unpackhi_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(punpckhwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpackhi_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpackhi_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let x = simd_shuffle!(a.as_i16x8(), b.as_i16x8(), [4, 12, 5, 13, 6, 14, 7, 15]);
         transmute::<i16x8, _>(x)
@@ -1609,7 +1695,8 @@ pub fn _mm_unpackhi_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(unpckhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpackhi_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpackhi_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i32x4, _>(simd_shuffle!(a.as_i32x4(), b.as_i32x4(), [2, 6, 3, 7])) }
 }
 
@@ -1620,7 +1707,8 @@ pub fn _mm_unpackhi_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(unpckhpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpackhi_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpackhi_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i64x2, _>(simd_shuffle!(a.as_i64x2(), b.as_i64x2(), [1, 3])) }
 }
 
@@ -1631,7 +1719,8 @@ pub fn _mm_unpackhi_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(punpcklbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpacklo_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpacklo_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         transmute::<i8x16, _>(simd_shuffle!(
             a.as_i8x16(),
@@ -1648,7 +1737,8 @@ pub fn _mm_unpacklo_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(punpcklwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpacklo_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpacklo_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let x = simd_shuffle!(a.as_i16x8(), b.as_i16x8(), [0, 8, 1, 9, 2, 10, 3, 11]);
         transmute::<i16x8, _>(x)
@@ -1662,7 +1752,8 @@ pub fn _mm_unpacklo_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(unpcklps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpacklo_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpacklo_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i32x4, _>(simd_shuffle!(a.as_i32x4(), b.as_i32x4(), [0, 4, 1, 5])) }
 }
 
@@ -1673,7 +1764,8 @@ pub fn _mm_unpacklo_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movlhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpacklo_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpacklo_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute::<i64x2, _>(simd_shuffle!(a.as_i64x2(), b.as_i64x2(), [0, 2])) }
 }
 
@@ -1685,7 +1777,8 @@ pub fn _mm_unpacklo_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(addsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_sd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_sd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_insert!(a, 0, _mm_cvtsd_f64(a) + _mm_cvtsd_f64(b)) }
 }
 
@@ -1697,7 +1790,8 @@ pub fn _mm_add_sd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(addpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_add_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_add(a, b) }
 }
 
@@ -1709,7 +1803,8 @@ pub fn _mm_add_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(divsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_div_sd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_div_sd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_insert!(a, 0, _mm_cvtsd_f64(a) / _mm_cvtsd_f64(b)) }
 }
 
@@ -1721,7 +1816,8 @@ pub fn _mm_div_sd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(divpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_div_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_div_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_div(a, b) }
 }
 
@@ -1781,7 +1877,8 @@ pub fn _mm_min_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(mulsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mul_sd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_sd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_insert!(a, 0, _mm_cvtsd_f64(a) * _mm_cvtsd_f64(b)) }
 }
 
@@ -1793,7 +1890,8 @@ pub fn _mm_mul_sd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(mulpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mul_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_mul(a, b) }
 }
 
@@ -1828,7 +1926,8 @@ pub fn _mm_sqrt_pd(a: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(subsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_sd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_sd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_insert!(a, 0, _mm_cvtsd_f64(a) - _mm_cvtsd_f64(b)) }
 }
 
@@ -1840,7 +1939,8 @@ pub fn _mm_sub_sd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(subpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sub_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_sub(a, b) }
 }
 
@@ -1852,7 +1952,8 @@ pub fn _mm_sub_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(andps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_and_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_and_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let a: __m128i = transmute(a);
         let b: __m128i = transmute(b);
@@ -1867,7 +1968,8 @@ pub fn _mm_and_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(andnps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_andnot_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_andnot_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let a: __m128i = transmute(a);
         let b: __m128i = transmute(b);
@@ -1882,7 +1984,8 @@ pub fn _mm_andnot_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(orps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_or_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_or_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let a: __m128i = transmute(a);
         let b: __m128i = transmute(b);
@@ -1897,7 +2000,8 @@ pub fn _mm_or_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(xorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_xor_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_xor_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let a: __m128i = transmute(a);
         let b: __m128i = transmute(b);
@@ -2325,7 +2429,8 @@ pub fn _mm_ucomineq_sd(a: __m128d, b: __m128d) -> i32 {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtpd2ps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtpd_ps(a: __m128d) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtpd_ps(a: __m128d) -> __m128 {
     unsafe {
         let r = simd_cast::<_, f32x2>(a.as_f64x2());
         let zero = f32x2::ZERO;
@@ -2342,7 +2447,8 @@ pub fn _mm_cvtpd_ps(a: __m128d) -> __m128 {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtps2pd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtps_pd(a: __m128) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtps_pd(a: __m128) -> __m128d {
     unsafe {
         let a = a.as_f32x4();
         transmute(simd_cast::<f32x2, f64x2>(simd_shuffle!(a, a, [0, 1])))
@@ -2393,7 +2499,8 @@ pub fn _mm_cvtsd_ss(a: __m128, b: __m128d) -> __m128 {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsd_f64(a: __m128d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsd_f64(a: __m128d) -> f64 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -2407,7 +2514,8 @@ pub fn _mm_cvtsd_f64(a: __m128d) -> f64 {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtss2sd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtss_sd(a: __m128d, b: __m128) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtss_sd(a: __m128d, b: __m128) -> __m128d {
     unsafe {
         let elt: f32 = simd_extract!(b, 0);
         simd_insert!(a, 0, elt as f64)
@@ -2457,7 +2565,8 @@ pub fn _mm_cvttps_epi32(a: __m128) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_sd(a: f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_sd(a: f64) -> __m128d {
     _mm_set_pd(0.0, a)
 }
 
@@ -2468,7 +2577,8 @@ pub fn _mm_set_sd(a: f64) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set1_pd(a: f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_pd(a: f64) -> __m128d {
     _mm_set_pd(a, a)
 }
 
@@ -2479,7 +2589,8 @@ pub fn _mm_set1_pd(a: f64) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_pd1(a: f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_pd1(a: f64) -> __m128d {
     _mm_set_pd(a, a)
 }
 
@@ -2490,7 +2601,8 @@ pub fn _mm_set_pd1(a: f64) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_set_pd(a: f64, b: f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_pd(a: f64, b: f64) -> __m128d {
     __m128d([b, a])
 }
 
@@ -2501,7 +2613,8 @@ pub fn _mm_set_pd(a: f64, b: f64) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setr_pd(a: f64, b: f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setr_pd(a: f64, b: f64) -> __m128d {
     _mm_set_pd(b, a)
 }
 
@@ -2513,7 +2626,8 @@ pub fn _mm_setr_pd(a: f64, b: f64) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(xorp))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_setzero_pd() -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setzero_pd() -> __m128d {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2527,12 +2641,13 @@ pub fn _mm_setzero_pd() -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movmskpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movemask_pd(a: __m128d) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movemask_pd(a: __m128d) -> i32 {
     // Propagate the highest bit to the rest, because simd_bitmask
     // requires all-1 or all-0.
     unsafe {
         let mask: i64x2 = simd_lt(transmute(a), i64x2::ZERO);
-        simd_bitmask::<i64x2, u8>(mask).into()
+        simd_bitmask::<i64x2, u8>(mask) as i32
     }
 }
 
@@ -2550,7 +2665,8 @@ pub fn _mm_movemask_pd(a: __m128d) -> i32 {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_load_pd(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_pd(mem_addr: *const f64) -> __m128d {
     *(mem_addr as *const __m128d)
 }
 
@@ -2562,7 +2678,8 @@ pub unsafe fn _mm_load_pd(mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load_sd(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_sd(mem_addr: *const f64) -> __m128d {
     _mm_setr_pd(*mem_addr, 0.)
 }
 
@@ -2575,7 +2692,8 @@ pub unsafe fn _mm_load_sd(mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadh_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadh_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
     _mm_setr_pd(simd_extract!(a, 0), *mem_addr)
 }
 
@@ -2588,7 +2706,8 @@ pub unsafe fn _mm_loadh_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movlps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadl_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadl_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
     _mm_setr_pd(*mem_addr, simd_extract!(a, 1))
 }
 
@@ -2630,7 +2749,8 @@ pub unsafe fn _mm_stream_pd(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movlps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) {
     *mem_addr = simd_extract!(a, 0)
 }
 
@@ -2647,7 +2767,8 @@ pub unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_store_pd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_pd(mem_addr: *mut f64, a: __m128d) {
     *(mem_addr as *mut __m128d) = a;
 }
 
@@ -2660,7 +2781,8 @@ pub unsafe fn _mm_store_pd(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movups))] // FIXME movupd expected
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_storeu_pd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_pd(mem_addr: *mut f64, a: __m128d) {
     mem_addr.cast::<__m128d>().write_unaligned(a);
 }
 
@@ -2672,7 +2794,8 @@ pub unsafe fn _mm_storeu_pd(mem_addr: *mut f64, a: __m128d) {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub unsafe fn _mm_storeu_si16(mem_addr: *mut u8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_si16(mem_addr: *mut u8, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut i16, simd_extract(a.as_i16x8(), 0))
 }
 
@@ -2684,7 +2807,8 @@ pub unsafe fn _mm_storeu_si16(mem_addr: *mut u8, a: __m128i) {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub unsafe fn _mm_storeu_si32(mem_addr: *mut u8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_si32(mem_addr: *mut u8, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut i32, simd_extract(a.as_i32x4(), 0))
 }
 
@@ -2696,7 +2820,8 @@ pub unsafe fn _mm_storeu_si32(mem_addr: *mut u8, a: __m128i) {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub unsafe fn _mm_storeu_si64(mem_addr: *mut u8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_si64(mem_addr: *mut u8, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut i64, simd_extract(a.as_i64x2(), 0))
 }
 
@@ -2709,7 +2834,8 @@ pub unsafe fn _mm_storeu_si64(mem_addr: *mut u8, a: __m128i) {
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_store1_pd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store1_pd(mem_addr: *mut f64, a: __m128d) {
     let b: __m128d = simd_shuffle!(a, a, [0, 0]);
     *(mem_addr as *mut __m128d) = b;
 }
@@ -2723,7 +2849,8 @@ pub unsafe fn _mm_store1_pd(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_store_pd1(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_pd1(mem_addr: *mut f64, a: __m128d) {
     let b: __m128d = simd_shuffle!(a, a, [0, 0]);
     *(mem_addr as *mut __m128d) = b;
 }
@@ -2738,7 +2865,8 @@ pub unsafe fn _mm_store_pd1(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) {
     let b: __m128d = simd_shuffle!(a, a, [1, 0]);
     *(mem_addr as *mut __m128d) = b;
 }
@@ -2751,7 +2879,8 @@ pub unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
     *mem_addr = simd_extract!(a, 1);
 }
 
@@ -2763,7 +2892,8 @@ pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movlps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_storel_pd(mem_addr: *mut f64, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storel_pd(mem_addr: *mut f64, a: __m128d) {
     *mem_addr = simd_extract!(a, 0);
 }
 
@@ -2775,7 +2905,8 @@ pub unsafe fn _mm_storel_pd(mem_addr: *mut f64, a: __m128d) {
 #[target_feature(enable = "sse2")]
 // #[cfg_attr(test, assert_instr(movapd))] // FIXME LLVM uses different codegen
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load1_pd(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load1_pd(mem_addr: *const f64) -> __m128d {
     let d = *mem_addr;
     _mm_setr_pd(d, d)
 }
@@ -2788,7 +2919,8 @@ pub unsafe fn _mm_load1_pd(mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "sse2")]
 // #[cfg_attr(test, assert_instr(movapd))] // FIXME same as _mm_load1_pd
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_load_pd1(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_pd1(mem_addr: *const f64) -> __m128d {
     _mm_load1_pd(mem_addr)
 }
 
@@ -2804,7 +2936,8 @@ pub unsafe fn _mm_load_pd1(mem_addr: *const f64) -> __m128d {
     assert_instr(movaps)
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadr_pd(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadr_pd(mem_addr: *const f64) -> __m128d {
     let a = _mm_load_pd(mem_addr);
     simd_shuffle!(a, a, [1, 0])
 }
@@ -2818,7 +2951,8 @@ pub unsafe fn _mm_loadr_pd(mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movups))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loadu_pd(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_pd(mem_addr: *const f64) -> __m128d {
     let mut dst = _mm_undefined_pd();
     ptr::copy_nonoverlapping(
         mem_addr as *const u8,
@@ -2836,7 +2970,8 @@ pub unsafe fn _mm_loadu_pd(mem_addr: *const f64) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub unsafe fn _mm_loadu_si16(mem_addr: *const u8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_si16(mem_addr: *const u8) -> __m128i {
     transmute(i16x8::new(
         ptr::read_unaligned(mem_addr as *const i16),
         0,
@@ -2857,7 +2992,8 @@ pub unsafe fn _mm_loadu_si16(mem_addr: *const u8) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub unsafe fn _mm_loadu_si32(mem_addr: *const u8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_si32(mem_addr: *const u8) -> __m128i {
     transmute(i32x4::new(
         ptr::read_unaligned(mem_addr as *const i32),
         0,
@@ -2874,7 +3010,8 @@ pub unsafe fn _mm_loadu_si32(mem_addr: *const u8) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86_mm_loadu_si64", since = "1.46.0")]
-pub unsafe fn _mm_loadu_si64(mem_addr: *const u8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_si64(mem_addr: *const u8) -> __m128i {
     transmute(i64x2::new(ptr::read_unaligned(mem_addr as *const i64), 0))
 }
 
@@ -2888,7 +3025,8 @@ pub unsafe fn _mm_loadu_si64(mem_addr: *const u8) -> __m128i {
 #[cfg_attr(test, assert_instr(shufps, MASK = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_shuffle_pd<const MASK: i32>(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shuffle_pd<const MASK: i32>(a: __m128d, b: __m128d) -> __m128d {
     static_assert_uimm_bits!(MASK, 8);
     unsafe { simd_shuffle!(a, b, [MASK as u32 & 0b1, ((MASK as u32 >> 1) & 0b1) + 2]) }
 }
@@ -2902,7 +3040,8 @@ pub fn _mm_shuffle_pd<const MASK: i32>(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_move_sd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_move_sd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { _mm_setr_pd(simd_extract!(b, 0), simd_extract!(a, 1)) }
 }
 
@@ -2913,7 +3052,8 @@ pub fn _mm_move_sd(a: __m128d, b: __m128d) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_castpd_ps(a: __m128d) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castpd_ps(a: __m128d) -> __m128 {
     unsafe { transmute(a) }
 }
 
@@ -2924,7 +3064,8 @@ pub fn _mm_castpd_ps(a: __m128d) -> __m128 {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_castpd_si128(a: __m128d) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castpd_si128(a: __m128d) -> __m128i {
     unsafe { transmute(a) }
 }
 
@@ -2935,7 +3076,8 @@ pub fn _mm_castpd_si128(a: __m128d) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_castps_pd(a: __m128) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castps_pd(a: __m128) -> __m128d {
     unsafe { transmute(a) }
 }
 
@@ -2946,7 +3088,8 @@ pub fn _mm_castps_pd(a: __m128) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_castps_si128(a: __m128) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castps_si128(a: __m128) -> __m128i {
     unsafe { transmute(a) }
 }
 
@@ -2957,7 +3100,8 @@ pub fn _mm_castps_si128(a: __m128) -> __m128i {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_castsi128_pd(a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castsi128_pd(a: __m128i) -> __m128d {
     unsafe { transmute(a) }
 }
 
@@ -2968,7 +3112,8 @@ pub fn _mm_castsi128_pd(a: __m128i) -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_castsi128_ps(a: __m128i) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castsi128_ps(a: __m128i) -> __m128 {
     unsafe { transmute(a) }
 }
 
@@ -2981,7 +3126,8 @@ pub fn _mm_castsi128_ps(a: __m128i) -> __m128 {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_undefined_pd() -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_undefined_pd() -> __m128d {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2994,7 +3140,8 @@ pub fn _mm_undefined_pd() -> __m128d {
 #[inline]
 #[target_feature(enable = "sse2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_undefined_si128() -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_undefined_si128() -> __m128i {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -3009,7 +3156,8 @@ pub fn _mm_undefined_si128() -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(unpckhpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
 
@@ -3024,7 +3172,8 @@ pub fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movlhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
 
@@ -3118,6 +3267,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use crate::{
         core_arch::{simd::*, x86::*},
         hint::black_box,
@@ -3157,7 +3307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_epi8() {
+    const unsafe fn test_mm_add_epi8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let b = _mm_setr_epi8(
@@ -3180,7 +3330,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_epi16() {
+    const unsafe fn test_mm_add_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_add_epi16(a, b);
@@ -3189,7 +3339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_epi32() {
+    const unsafe fn test_mm_add_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(4, 5, 6, 7);
         let r = _mm_add_epi32(a, b);
@@ -3198,7 +3348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_epi64() {
+    const unsafe fn test_mm_add_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(2, 3);
         let r = _mm_add_epi64(a, b);
@@ -3207,7 +3357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epi8() {
+    const unsafe fn test_mm_adds_epi8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let b = _mm_setr_epi8(
@@ -3238,7 +3388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epi16() {
+    const unsafe fn test_mm_adds_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_adds_epi16(a, b);
@@ -3263,7 +3413,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epu8() {
+    const unsafe fn test_mm_adds_epu8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let b = _mm_setr_epi8(
@@ -3286,7 +3436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epu16() {
+    const unsafe fn test_mm_adds_epu16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_adds_epu16(a, b);
@@ -3303,21 +3453,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_avg_epu8() {
+    const unsafe fn test_mm_avg_epu8() {
         let (a, b) = (_mm_set1_epi8(3), _mm_set1_epi8(9));
         let r = _mm_avg_epu8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(6));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_avg_epu16() {
+    const unsafe fn test_mm_avg_epu16() {
         let (a, b) = (_mm_set1_epi16(3), _mm_set1_epi16(9));
         let r = _mm_avg_epu16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(6));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_madd_epi16() {
+    const unsafe fn test_mm_madd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm_madd_epi16(a, b);
@@ -3352,7 +3502,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_max_epi16() {
+    const unsafe fn test_mm_max_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let r = _mm_max_epi16(a, b);
@@ -3360,7 +3510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_max_epu8() {
+    const unsafe fn test_mm_max_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(!0);
         let r = _mm_max_epu8(a, b);
@@ -3368,7 +3518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_min_epi16() {
+    const unsafe fn test_mm_min_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let r = _mm_min_epi16(a, b);
@@ -3376,7 +3526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_min_epu8() {
+    const unsafe fn test_mm_min_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(!0);
         let r = _mm_min_epu8(a, b);
@@ -3384,28 +3534,28 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_mulhi_epi16() {
+    const unsafe fn test_mm_mulhi_epi16() {
         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(-1001));
         let r = _mm_mulhi_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(-16));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_mulhi_epu16() {
+    const unsafe fn test_mm_mulhi_epu16() {
         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(1001));
         let r = _mm_mulhi_epu16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(15));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_mullo_epi16() {
+    const unsafe fn test_mm_mullo_epi16() {
         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(-1001));
         let r = _mm_mullo_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(-17960));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_mul_epu32() {
+    const unsafe fn test_mm_mul_epu32() {
         let a = _mm_setr_epi64x(1_000_000_000, 1 << 34);
         let b = _mm_setr_epi64x(1_000_000_000, 1 << 35);
         let r = _mm_mul_epu32(a, b);
@@ -3429,35 +3579,35 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sub_epi8() {
+    const unsafe fn test_mm_sub_epi8() {
         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(6));
         let r = _mm_sub_epi8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sub_epi16() {
+    const unsafe fn test_mm_sub_epi16() {
         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(6));
         let r = _mm_sub_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sub_epi32() {
+    const unsafe fn test_mm_sub_epi32() {
         let (a, b) = (_mm_set1_epi32(5), _mm_set1_epi32(6));
         let r = _mm_sub_epi32(a, b);
         assert_eq_m128i(r, _mm_set1_epi32(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sub_epi64() {
+    const unsafe fn test_mm_sub_epi64() {
         let (a, b) = (_mm_set1_epi64x(5), _mm_set1_epi64x(6));
         let r = _mm_sub_epi64(a, b);
         assert_eq_m128i(r, _mm_set1_epi64x(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epi8() {
+    const unsafe fn test_mm_subs_epi8() {
         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(2));
         let r = _mm_subs_epi8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(3));
@@ -3480,7 +3630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epi16() {
+    const unsafe fn test_mm_subs_epi16() {
         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(2));
         let r = _mm_subs_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(3));
@@ -3503,7 +3653,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epu8() {
+    const unsafe fn test_mm_subs_epu8() {
         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(2));
         let r = _mm_subs_epu8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(3));
@@ -3518,7 +3668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epu16() {
+    const unsafe fn test_mm_subs_epu16() {
         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(2));
         let r = _mm_subs_epu16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(3));
@@ -3533,7 +3683,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_slli_si128() {
+    const unsafe fn test_mm_slli_si128() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@@ -3559,7 +3709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_slli_epi16() {
+    const unsafe fn test_mm_slli_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_slli_epi16::<4>(a);
         assert_eq_m128i(
@@ -3587,7 +3737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_slli_epi32() {
+    const unsafe fn test_mm_slli_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_slli_epi32::<4>(a);
         assert_eq_m128i(r, _mm_setr_epi32(0xEEEE0, -0xEEEE0, 0xFFFF0, -0xFFFF0));
@@ -3609,7 +3759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_slli_epi64() {
+    const unsafe fn test_mm_slli_epi64() {
         let a = _mm_set_epi64x(0xFFFFFFFF, -0xFFFFFFFF);
         let r = _mm_slli_epi64::<4>(a);
         assert_eq_m128i(r, _mm_set_epi64x(0xFFFFFFFF0, -0xFFFFFFFF0));
@@ -3631,7 +3781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srai_epi16() {
+    const unsafe fn test_mm_srai_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_srai_epi16::<4>(a);
         assert_eq_m128i(
@@ -3659,7 +3809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srai_epi32() {
+    const unsafe fn test_mm_srai_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_srai_epi32::<4>(a);
         assert_eq_m128i(r, _mm_setr_epi32(0xEEE, -0xEEF, 0xFFF, -0x1000));
@@ -3681,7 +3831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srli_si128() {
+    const unsafe fn test_mm_srli_si128() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@@ -3710,7 +3860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srli_epi16() {
+    const unsafe fn test_mm_srli_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_srli_epi16::<4>(a);
         assert_eq_m128i(
@@ -3738,7 +3888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srli_epi32() {
+    const unsafe fn test_mm_srli_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_srli_epi32::<4>(a);
         assert_eq_m128i(r, _mm_setr_epi32(0xEEE, 0xFFFF111, 0xFFF, 0xFFFF000));
@@ -3760,7 +3910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srli_epi64() {
+    const unsafe fn test_mm_srli_epi64() {
         let a = _mm_set_epi64x(0xFFFFFFFF, -0xFFFFFFFF);
         let r = _mm_srli_epi64::<4>(a);
         assert_eq_m128i(r, _mm_set_epi64x(0xFFFFFFF, 0xFFFFFFFF0000000));
@@ -3782,7 +3932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_and_si128() {
+    const unsafe fn test_mm_and_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_and_si128(a, b);
@@ -3790,7 +3940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_andnot_si128() {
+    const unsafe fn test_mm_andnot_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_andnot_si128(a, b);
@@ -3798,7 +3948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_or_si128() {
+    const unsafe fn test_mm_or_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_or_si128(a, b);
@@ -3806,7 +3956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_xor_si128() {
+    const unsafe fn test_mm_xor_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_xor_si128(a, b);
@@ -3814,7 +3964,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpeq_epi8() {
+    const unsafe fn test_mm_cmpeq_epi8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_setr_epi8(15, 14, 2, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_cmpeq_epi8(a, b);
@@ -3828,7 +3978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpeq_epi16() {
+    const unsafe fn test_mm_cmpeq_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(7, 6, 2, 4, 3, 2, 1, 0);
         let r = _mm_cmpeq_epi16(a, b);
@@ -3836,7 +3986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpeq_epi32() {
+    const unsafe fn test_mm_cmpeq_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(3, 2, 2, 0);
         let r = _mm_cmpeq_epi32(a, b);
@@ -3844,7 +3994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpgt_epi8() {
+    const unsafe fn test_mm_cmpgt_epi8() {
         let a = _mm_set_epi8(5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let b = _mm_set1_epi8(0);
         let r = _mm_cmpgt_epi8(a, b);
@@ -3853,7 +4003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpgt_epi16() {
+    const unsafe fn test_mm_cmpgt_epi16() {
         let a = _mm_set_epi16(5, 0, 0, 0, 0, 0, 0, 0);
         let b = _mm_set1_epi16(0);
         let r = _mm_cmpgt_epi16(a, b);
@@ -3862,7 +4012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpgt_epi32() {
+    const unsafe fn test_mm_cmpgt_epi32() {
         let a = _mm_set_epi32(5, 0, 0, 0);
         let b = _mm_set1_epi32(0);
         let r = _mm_cmpgt_epi32(a, b);
@@ -3870,7 +4020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmplt_epi8() {
+    const unsafe fn test_mm_cmplt_epi8() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set_epi8(5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm_cmplt_epi8(a, b);
@@ -3879,7 +4029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmplt_epi16() {
+    const unsafe fn test_mm_cmplt_epi16() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set_epi16(5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm_cmplt_epi16(a, b);
@@ -3888,7 +4038,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmplt_epi32() {
+    const unsafe fn test_mm_cmplt_epi32() {
         let a = _mm_set1_epi32(0);
         let b = _mm_set_epi32(5, 0, 0, 0);
         let r = _mm_cmplt_epi32(a, b);
@@ -3896,21 +4046,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtepi32_pd() {
+    const unsafe fn test_mm_cvtepi32_pd() {
         let a = _mm_set_epi32(35, 25, 15, 5);
         let r = _mm_cvtepi32_pd(a);
         assert_eq_m128d(r, _mm_setr_pd(5.0, 15.0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsi32_sd() {
+    const unsafe fn test_mm_cvtsi32_sd() {
         let a = _mm_set1_pd(3.5);
         let r = _mm_cvtsi32_sd(a, 5);
         assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtepi32_ps() {
+    const unsafe fn test_mm_cvtepi32_ps() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let r = _mm_cvtepi32_ps(a);
         assert_eq_m128(r, _mm_setr_ps(1.0, 2.0, 3.0, 4.0));
@@ -3924,37 +4074,37 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsi32_si128() {
+    const unsafe fn test_mm_cvtsi32_si128() {
         let r = _mm_cvtsi32_si128(5);
         assert_eq_m128i(r, _mm_setr_epi32(5, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsi128_si32() {
+    const unsafe fn test_mm_cvtsi128_si32() {
         let r = _mm_cvtsi128_si32(_mm_setr_epi32(5, 0, 0, 0));
         assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_epi64x() {
+    const unsafe fn test_mm_set_epi64x() {
         let r = _mm_set_epi64x(0, 1);
         assert_eq_m128i(r, _mm_setr_epi64x(1, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_epi32() {
+    const unsafe fn test_mm_set_epi32() {
         let r = _mm_set_epi32(0, 1, 2, 3);
         assert_eq_m128i(r, _mm_setr_epi32(3, 2, 1, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_epi16() {
+    const unsafe fn test_mm_set_epi16() {
         let r = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m128i(r, _mm_setr_epi16(7, 6, 5, 4, 3, 2, 1, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_epi8() {
+    const unsafe fn test_mm_set_epi8() {
         #[rustfmt::skip]
         let r = _mm_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -3968,43 +4118,43 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set1_epi64x() {
+    const unsafe fn test_mm_set1_epi64x() {
         let r = _mm_set1_epi64x(1);
         assert_eq_m128i(r, _mm_set1_epi64x(1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set1_epi32() {
+    const unsafe fn test_mm_set1_epi32() {
         let r = _mm_set1_epi32(1);
         assert_eq_m128i(r, _mm_set1_epi32(1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set1_epi16() {
+    const unsafe fn test_mm_set1_epi16() {
         let r = _mm_set1_epi16(1);
         assert_eq_m128i(r, _mm_set1_epi16(1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set1_epi8() {
+    const unsafe fn test_mm_set1_epi8() {
         let r = _mm_set1_epi8(1);
         assert_eq_m128i(r, _mm_set1_epi8(1));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_setr_epi32() {
+    const unsafe fn test_mm_setr_epi32() {
         let r = _mm_setr_epi32(0, 1, 2, 3);
         assert_eq_m128i(r, _mm_setr_epi32(0, 1, 2, 3));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_setr_epi16() {
+    const unsafe fn test_mm_setr_epi16() {
         let r = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m128i(r, _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_setr_epi8() {
+    const unsafe fn test_mm_setr_epi8() {
         #[rustfmt::skip]
         let r = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -4018,27 +4168,27 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_setzero_si128() {
+    const unsafe fn test_mm_setzero_si128() {
         let r = _mm_setzero_si128();
         assert_eq_m128i(r, _mm_set1_epi64x(0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadl_epi64() {
+    const unsafe fn test_mm_loadl_epi64() {
         let a = _mm_setr_epi64x(6, 5);
         let r = _mm_loadl_epi64(ptr::addr_of!(a));
         assert_eq_m128i(r, _mm_setr_epi64x(6, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_load_si128() {
+    const unsafe fn test_mm_load_si128() {
         let a = _mm_set_epi64x(5, 6);
         let r = _mm_load_si128(ptr::addr_of!(a) as *const _);
         assert_eq_m128i(a, r);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadu_si128() {
+    const unsafe fn test_mm_loadu_si128() {
         let a = _mm_set_epi64x(5, 6);
         let r = _mm_loadu_si128(ptr::addr_of!(a) as *const _);
         assert_eq_m128i(a, r);
@@ -4063,7 +4213,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_store_si128() {
+    const unsafe fn test_mm_store_si128() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi8(0);
         _mm_store_si128(&mut r, a);
@@ -4071,7 +4221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storeu_si128() {
+    const unsafe fn test_mm_storeu_si128() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi8(0);
         _mm_storeu_si128(&mut r, a);
@@ -4079,7 +4229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storel_epi64() {
+    const unsafe fn test_mm_storel_epi64() {
         let a = _mm_setr_epi64x(2, 9);
         let mut r = _mm_set1_epi8(0);
         _mm_storel_epi64(&mut r, a);
@@ -4111,7 +4261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_move_epi64() {
+    const unsafe fn test_mm_move_epi64() {
         let a = _mm_setr_epi64x(5, 6);
         let r = _mm_move_epi64(a);
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
@@ -4154,7 +4304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_extract_epi16() {
+    const unsafe fn test_mm_extract_epi16() {
         let a = _mm_setr_epi16(-1, 1, 2, 3, 4, 5, 6, 7);
         let r1 = _mm_extract_epi16::<0>(a);
         let r2 = _mm_extract_epi16::<3>(a);
@@ -4163,7 +4313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_insert_epi16() {
+    const unsafe fn test_mm_insert_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_insert_epi16::<0>(a, 9);
         let e = _mm_setr_epi16(9, 1, 2, 3, 4, 5, 6, 7);
@@ -4171,7 +4321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_movemask_epi8() {
+    const unsafe fn test_mm_movemask_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0b1000_0000u8 as i8, 0b0, 0b1000_0000u8 as i8, 0b01,
@@ -4184,7 +4334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_shuffle_epi32() {
+    const unsafe fn test_mm_shuffle_epi32() {
         let a = _mm_setr_epi32(5, 10, 15, 20);
         let r = _mm_shuffle_epi32::<0b00_01_01_11>(a);
         let e = _mm_setr_epi32(20, 10, 10, 5);
@@ -4192,7 +4342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_shufflehi_epi16() {
+    const unsafe fn test_mm_shufflehi_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 10, 15, 20);
         let r = _mm_shufflehi_epi16::<0b00_01_01_11>(a);
         let e = _mm_setr_epi16(1, 2, 3, 4, 20, 10, 10, 5);
@@ -4200,7 +4350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_shufflelo_epi16() {
+    const unsafe fn test_mm_shufflelo_epi16() {
         let a = _mm_setr_epi16(5, 10, 15, 20, 1, 2, 3, 4);
         let r = _mm_shufflelo_epi16::<0b00_01_01_11>(a);
         let e = _mm_setr_epi16(20, 10, 10, 5, 1, 2, 3, 4);
@@ -4208,7 +4358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpackhi_epi8() {
+    const unsafe fn test_mm_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4227,7 +4377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpackhi_epi16() {
+    const unsafe fn test_mm_unpackhi_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_unpackhi_epi16(a, b);
@@ -4236,7 +4386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpackhi_epi32() {
+    const unsafe fn test_mm_unpackhi_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(4, 5, 6, 7);
         let r = _mm_unpackhi_epi32(a, b);
@@ -4245,7 +4395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpackhi_epi64() {
+    const unsafe fn test_mm_unpackhi_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(2, 3);
         let r = _mm_unpackhi_epi64(a, b);
@@ -4254,7 +4404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpacklo_epi8() {
+    const unsafe fn test_mm_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4274,7 +4424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpacklo_epi16() {
+    const unsafe fn test_mm_unpacklo_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_unpacklo_epi16(a, b);
@@ -4283,7 +4433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpacklo_epi32() {
+    const unsafe fn test_mm_unpacklo_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(4, 5, 6, 7);
         let r = _mm_unpacklo_epi32(a, b);
@@ -4292,7 +4442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpacklo_epi64() {
+    const unsafe fn test_mm_unpacklo_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(2, 3);
         let r = _mm_unpacklo_epi64(a, b);
@@ -4301,7 +4451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_sd() {
+    const unsafe fn test_mm_add_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_add_sd(a, b);
@@ -4309,7 +4459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_pd() {
+    const unsafe fn test_mm_add_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_add_pd(a, b);
@@ -4317,7 +4467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_div_sd() {
+    const unsafe fn test_mm_div_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_div_sd(a, b);
@@ -4325,7 +4475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_div_pd() {
+    const unsafe fn test_mm_div_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_div_pd(a, b);
@@ -4387,7 +4537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_mul_sd() {
+    const unsafe fn test_mm_mul_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_mul_sd(a, b);
@@ -4395,7 +4545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_mul_pd() {
+    const unsafe fn test_mm_mul_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_mul_pd(a, b);
@@ -4417,7 +4567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sub_sd() {
+    const unsafe fn test_mm_sub_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_sub_sd(a, b);
@@ -4425,7 +4575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sub_pd() {
+    const unsafe fn test_mm_sub_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_sub_pd(a, b);
@@ -4433,7 +4583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_and_pd() {
+    const unsafe fn test_mm_and_pd() {
         let a = transmute(u64x2::splat(5));
         let b = transmute(u64x2::splat(3));
         let r = _mm_and_pd(a, b);
@@ -4442,7 +4592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_andnot_pd() {
+    const unsafe fn test_mm_andnot_pd() {
         let a = transmute(u64x2::splat(5));
         let b = transmute(u64x2::splat(3));
         let r = _mm_andnot_pd(a, b);
@@ -4451,7 +4601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_or_pd() {
+    const unsafe fn test_mm_or_pd() {
         let a = transmute(u64x2::splat(5));
         let b = transmute(u64x2::splat(3));
         let r = _mm_or_pd(a, b);
@@ -4460,7 +4610,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_xor_pd() {
+    const unsafe fn test_mm_xor_pd() {
         let a = transmute(u64x2::splat(5));
         let b = transmute(u64x2::splat(3));
         let r = _mm_xor_pd(a, b);
@@ -4739,7 +4889,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_movemask_pd() {
+    const unsafe fn test_mm_movemask_pd() {
         let r = _mm_movemask_pd(_mm_setr_pd(-1.0, 5.0));
         assert_eq!(r, 0b01);
 
@@ -4753,7 +4903,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_load_pd() {
+    const unsafe fn test_mm_load_pd() {
         let mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
@@ -4765,7 +4915,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_load_sd() {
+    const unsafe fn test_mm_load_sd() {
         let a = 1.;
         let expected = _mm_setr_pd(a, 0.);
         let r = _mm_load_sd(&a);
@@ -4773,7 +4923,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadh_pd() {
+    const unsafe fn test_mm_loadh_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = 3.;
         let expected = _mm_setr_pd(_mm_cvtsd_f64(a), 3.);
@@ -4782,7 +4932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadl_pd() {
+    const unsafe fn test_mm_loadl_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = 3.;
         let expected = _mm_setr_pd(3., get_m128d(a, 1));
@@ -4810,7 +4960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_store_sd() {
+    const unsafe fn test_mm_store_sd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
         _mm_store_sd(&mut dest, a);
@@ -4818,7 +4968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_store_pd() {
+    const unsafe fn test_mm_store_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
@@ -4830,31 +4980,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storeu_pd() {
+    const unsafe fn test_mm_storeu_pd() {
+        // guaranteed to be aligned to 16 bytes
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
 
-        let mut ofs = 0;
-        let mut p = vals.as_mut_ptr();
-
-        // Make sure p is **not** aligned to 16-byte boundary
-        if (p as usize) & 0xf == 0 {
-            ofs = 1;
-            p = p.add(1);
-        }
-
+        // so p is *not* aligned to 16 bytes
+        let p = vals.as_mut_ptr().offset(1);
         _mm_storeu_pd(p, *black_box(&a));
 
-        if ofs > 0 {
-            assert_eq!(vals[ofs - 1], 0.0);
-        }
-        assert_eq!(vals[ofs + 0], 1.0);
-        assert_eq!(vals[ofs + 1], 2.0);
+        assert_eq!(*vals, [0.0, 1.0, 2.0, 0.0]);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storeu_si16() {
+    const unsafe fn test_mm_storeu_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
         _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a);
@@ -4863,7 +5003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storeu_si32() {
+    const unsafe fn test_mm_storeu_si32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = _mm_setr_epi32(5, 6, 7, 8);
         _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a);
@@ -4872,7 +5012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storeu_si64() {
+    const unsafe fn test_mm_storeu_si64() {
         let a = _mm_setr_epi64x(1, 2);
         let mut r = _mm_setr_epi64x(3, 4);
         _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a);
@@ -4881,7 +5021,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_store1_pd() {
+    const unsafe fn test_mm_store1_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
@@ -4893,7 +5033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_store_pd1() {
+    const unsafe fn test_mm_store_pd1() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
@@ -4905,7 +5045,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storer_pd() {
+    const unsafe fn test_mm_storer_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
@@ -4917,7 +5057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storeh_pd() {
+    const unsafe fn test_mm_storeh_pd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
         _mm_storeh_pd(&mut dest, a);
@@ -4925,7 +5065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_storel_pd() {
+    const unsafe fn test_mm_storel_pd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
         _mm_storel_pd(&mut dest, a);
@@ -4933,7 +5073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadr_pd() {
+    const unsafe fn test_mm_loadr_pd() {
         let mut mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
@@ -4945,48 +5085,44 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadu_pd() {
+    const unsafe fn test_mm_loadu_pd() {
+        // guaranteed to be aligned to 16 bytes
         let mut mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
         let vals = &mut mem.data;
-        let mut d = vals.as_ptr();
 
-        // make sure d is not aligned to 16-byte boundary
-        let mut offset = 0;
-        if (d as usize) & 0xf == 0 {
-            offset = 1;
-            d = d.add(offset);
-        }
+        // so this will *not* be aligned to 16 bytes
+        let d = vals.as_ptr().offset(1);
 
         let r = _mm_loadu_pd(d);
-        let e = _mm_add_pd(_mm_setr_pd(1.0, 2.0), _mm_set1_pd(offset as f64));
+        let e = _mm_setr_pd(2.0, 3.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadu_si16() {
+    const unsafe fn test_mm_loadu_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_loadu_si16(ptr::addr_of!(a) as *const _);
         assert_eq_m128i(r, _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadu_si32() {
+    const unsafe fn test_mm_loadu_si32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let r = _mm_loadu_si32(ptr::addr_of!(a) as *const _);
         assert_eq_m128i(r, _mm_setr_epi32(1, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_loadu_si64() {
+    const unsafe fn test_mm_loadu_si64() {
         let a = _mm_setr_epi64x(5, 6);
         let r = _mm_loadu_si64(ptr::addr_of!(a) as *const _);
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtpd_ps() {
+    const unsafe fn test_mm_cvtpd_ps() {
         let r = _mm_cvtpd_ps(_mm_setr_pd(-1.0, 5.0));
         assert_eq_m128(r, _mm_setr_ps(-1.0, 5.0, 0.0, 0.0));
 
@@ -5001,7 +5137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtps_pd() {
+    const unsafe fn test_mm_cvtps_pd() {
         let r = _mm_cvtps_pd(_mm_setr_ps(-1.0, 2.0, -3.0, 5.0));
         assert_eq_m128d(r, _mm_setr_pd(-1.0, 2.0));
 
@@ -5070,13 +5206,13 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsd_f64() {
+    const unsafe fn test_mm_cvtsd_f64() {
         let r = _mm_cvtsd_f64(_mm_setr_pd(-1.1, 2.2));
         assert_eq!(r, -1.1);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtss_sd() {
+    const unsafe fn test_mm_cvtss_sd() {
         let a = _mm_setr_pd(-1.1, 2.2);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
@@ -5124,57 +5260,57 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_sd() {
+    const unsafe fn test_mm_set_sd() {
         let r = _mm_set_sd(-1.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(-1.0_f64, 0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set1_pd() {
+    const unsafe fn test_mm_set1_pd() {
         let r = _mm_set1_pd(-1.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(-1.0_f64, -1.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_pd1() {
+    const unsafe fn test_mm_set_pd1() {
         let r = _mm_set_pd1(-2.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(-2.0_f64, -2.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_set_pd() {
+    const unsafe fn test_mm_set_pd() {
         let r = _mm_set_pd(1.0_f64, 5.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(5.0_f64, 1.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_setr_pd() {
+    const unsafe fn test_mm_setr_pd() {
         let r = _mm_setr_pd(1.0_f64, -5.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(1.0_f64, -5.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_setzero_pd() {
+    const unsafe fn test_mm_setzero_pd() {
         let r = _mm_setzero_pd();
         assert_eq_m128d(r, _mm_setr_pd(0_f64, 0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_load1_pd() {
+    const unsafe fn test_mm_load1_pd() {
         let d = -5.0;
         let r = _mm_load1_pd(&d);
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_load_pd1() {
+    const unsafe fn test_mm_load_pd1() {
         let d = -5.0;
         let r = _mm_load_pd1(&d);
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpackhi_pd() {
+    const unsafe fn test_mm_unpackhi_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(3.0, 4.0);
         let r = _mm_unpackhi_pd(a, b);
@@ -5182,7 +5318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_unpacklo_pd() {
+    const unsafe fn test_mm_unpacklo_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(3.0, 4.0);
         let r = _mm_unpacklo_pd(a, b);
@@ -5190,7 +5326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_shuffle_pd() {
+    const unsafe fn test_mm_shuffle_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(3., 4.);
         let expected = _mm_setr_pd(1., 3.);
@@ -5199,7 +5335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_move_sd() {
+    const unsafe fn test_mm_move_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(3., 4.);
         let expected = _mm_setr_pd(3., 2.);
@@ -5208,7 +5344,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_castpd_ps() {
+    const unsafe fn test_mm_castpd_ps() {
         let a = _mm_set1_pd(0.);
         let expected = _mm_set1_ps(0.);
         let r = _mm_castpd_ps(a);
@@ -5216,7 +5352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_castpd_si128() {
+    const unsafe fn test_mm_castpd_si128() {
         let a = _mm_set1_pd(0.);
         let expected = _mm_set1_epi64x(0);
         let r = _mm_castpd_si128(a);
@@ -5224,7 +5360,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_castps_pd() {
+    const unsafe fn test_mm_castps_pd() {
         let a = _mm_set1_ps(0.);
         let expected = _mm_set1_pd(0.);
         let r = _mm_castps_pd(a);
@@ -5232,7 +5368,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_castps_si128() {
+    const unsafe fn test_mm_castps_si128() {
         let a = _mm_set1_ps(0.);
         let expected = _mm_set1_epi32(0);
         let r = _mm_castps_si128(a);
@@ -5240,7 +5376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_castsi128_pd() {
+    const unsafe fn test_mm_castsi128_pd() {
         let a = _mm_set1_epi64x(0);
         let expected = _mm_set1_pd(0.);
         let r = _mm_castsi128_pd(a);
@@ -5248,7 +5384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_castsi128_ps() {
+    const unsafe fn test_mm_castsi128_ps() {
         let a = _mm_set1_epi32(0);
         let expected = _mm_set1_ps(0.);
         let r = _mm_castsi128_ps(a);
diff --git a/crates/core_arch/src/x86_64/sse2.rs b/crates/core_arch/src/x86_64/sse2.rs
index 0894aa9810..9f350f2368 100644
--- a/crates/core_arch/src/x86_64/sse2.rs
+++ b/crates/core_arch/src/x86_64/sse2.rs
@@ -95,7 +95,8 @@ pub unsafe fn _mm_stream_si64(mem_addr: *mut i64, a: i64) {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi64_si128(a: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi64_si128(a: i64) -> __m128i {
     _mm_set_epi64x(0, a)
 }
 
@@ -107,7 +108,8 @@ pub fn _mm_cvtsi64_si128(a: i64) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
     _mm_cvtsi64_si128(a)
 }
 
@@ -118,7 +120,8 @@ pub fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
     unsafe { simd_extract!(a.as_i64x2(), 0) }
 }
 
@@ -129,7 +132,8 @@ pub fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(movq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi128_si64x(a: __m128i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi128_si64x(a: __m128i) -> i64 {
     _mm_cvtsi128_si64(a)
 }
 
@@ -141,7 +145,8 @@ pub fn _mm_cvtsi128_si64x(a: __m128i) -> i64 {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtsi2sd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi64_sd(a: __m128d, b: i64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi64_sd(a: __m128d, b: i64) -> __m128d {
     unsafe { simd_insert!(a, 0, b as f64) }
 }
 
@@ -153,13 +158,15 @@ pub fn _mm_cvtsi64_sd(a: __m128d, b: i64) -> __m128d {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(cvtsi2sd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtsi64x_sd(a: __m128d, b: i64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi64x_sd(a: __m128d, b: i64) -> __m128d {
     _mm_cvtsi64_sd(a, b)
 }
 
 #[cfg(test)]
 mod tests {
     use crate::core_arch::arch::x86_64::*;
+    use crate::core_arch::assert_eq_const as assert_eq;
     use std::boxed;
     use std::ptr;
     use stdarch_test::simd_test;
@@ -206,19 +213,19 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsi64_si128() {
+    const unsafe fn test_mm_cvtsi64_si128() {
         let r = _mm_cvtsi64_si128(5);
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsi128_si64() {
+    const unsafe fn test_mm_cvtsi128_si64() {
         let r = _mm_cvtsi128_si64(_mm_setr_epi64x(5, 0));
         assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsi64_sd() {
+    const unsafe fn test_mm_cvtsi64_sd() {
         let a = _mm_set1_pd(3.5);
         let r = _mm_cvtsi64_sd(a, 5);
         assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));

From ebc46ca3abe5a29c0303d131cafac4537edb2973 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:21:22 +0530
Subject: [PATCH 054/326] Make `sse3` functions const

---
 crates/core_arch/src/x86/sse3.rs | 51 +++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/crates/core_arch/src/x86/sse3.rs b/crates/core_arch/src/x86/sse3.rs
index 79be7a7e9b..eebca864f4 100644
--- a/crates/core_arch/src/x86/sse3.rs
+++ b/crates/core_arch/src/x86/sse3.rs
@@ -14,7 +14,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(addsubps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_addsub_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_addsub_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let a = a.as_f32x4();
         let b = b.as_f32x4();
@@ -32,7 +33,8 @@ pub fn _mm_addsub_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(addsubpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_addsub_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_addsub_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let a = a.as_f64x2();
         let b = b.as_f64x2();
@@ -50,7 +52,8 @@ pub fn _mm_addsub_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(haddpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hadd_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hadd_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 2]);
         let odd = simd_shuffle!(a, b, [1, 3]);
@@ -66,7 +69,8 @@ pub fn _mm_hadd_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(haddps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hadd_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hadd_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 2, 4, 6]);
         let odd = simd_shuffle!(a, b, [1, 3, 5, 7]);
@@ -82,7 +86,8 @@ pub fn _mm_hadd_ps(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(hsubpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hsub_pd(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hsub_pd(a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 2]);
         let odd = simd_shuffle!(a, b, [1, 3]);
@@ -98,7 +103,8 @@ pub fn _mm_hsub_pd(a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(hsubps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hsub_ps(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hsub_ps(a: __m128, b: __m128) -> __m128 {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 2, 4, 6]);
         let odd = simd_shuffle!(a, b, [1, 3, 5, 7]);
@@ -127,7 +133,8 @@ pub unsafe fn _mm_lddqu_si128(mem_addr: *const __m128i) -> __m128i {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(movddup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movedup_pd(a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movedup_pd(a: __m128d) -> __m128d {
     unsafe { simd_shuffle!(a, a, [0, 0]) }
 }
 
@@ -139,7 +146,8 @@ pub fn _mm_movedup_pd(a: __m128d) -> __m128d {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(movddup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_loaddup_pd(mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loaddup_pd(mem_addr: *const f64) -> __m128d {
     _mm_load1_pd(mem_addr)
 }
 
@@ -151,7 +159,8 @@ pub unsafe fn _mm_loaddup_pd(mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(movshdup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_movehdup_ps(a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movehdup_ps(a: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, a, [1, 1, 3, 3]) }
 }
 
@@ -163,7 +172,8 @@ pub fn _mm_movehdup_ps(a: __m128) -> __m128 {
 #[target_feature(enable = "sse3")]
 #[cfg_attr(test, assert_instr(movsldup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_moveldup_ps(a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_moveldup_ps(a: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, a, [0, 0, 2, 2]) }
 }
 
@@ -175,12 +185,13 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_addsub_ps() {
+    const unsafe fn test_mm_addsub_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_addsub_ps(a, b);
@@ -188,7 +199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_addsub_pd() {
+    const unsafe fn test_mm_addsub_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let b = _mm_setr_pd(-100.0, 20.0);
         let r = _mm_addsub_pd(a, b);
@@ -196,7 +207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_hadd_pd() {
+    const unsafe fn test_mm_hadd_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let b = _mm_setr_pd(-100.0, 20.0);
         let r = _mm_hadd_pd(a, b);
@@ -204,7 +215,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_hadd_ps() {
+    const unsafe fn test_mm_hadd_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_hadd_ps(a, b);
@@ -212,7 +223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_hsub_pd() {
+    const unsafe fn test_mm_hsub_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let b = _mm_setr_pd(-100.0, 20.0);
         let r = _mm_hsub_pd(a, b);
@@ -220,7 +231,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_hsub_ps() {
+    const unsafe fn test_mm_hsub_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_hsub_ps(a, b);
@@ -241,28 +252,28 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_movedup_pd() {
+    const unsafe fn test_mm_movedup_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let r = _mm_movedup_pd(a);
         assert_eq_m128d(r, _mm_setr_pd(-1.0, -1.0));
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_movehdup_ps() {
+    const unsafe fn test_mm_movehdup_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let r = _mm_movehdup_ps(a);
         assert_eq_m128(r, _mm_setr_ps(5.0, 5.0, -10.0, -10.0));
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_moveldup_ps() {
+    const unsafe fn test_mm_moveldup_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let r = _mm_moveldup_ps(a);
         assert_eq_m128(r, _mm_setr_ps(-1.0, -1.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_loaddup_pd() {
+    const unsafe fn test_mm_loaddup_pd() {
         let d = -5.0;
         let r = _mm_loaddup_pd(&d);
         assert_eq_m128d(r, _mm_setr_pd(d, d));

From 4c5f2532f1e5e38125f5745b278dd00065b8d511 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:21:33 +0530
Subject: [PATCH 055/326] Make `ssse3` functions const

---
 crates/core_arch/src/x86/ssse3.rs | 41 +++++++++++++++++++------------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/crates/core_arch/src/x86/ssse3.rs b/crates/core_arch/src/x86/ssse3.rs
index ac067bd4b5..c44da6eb97 100644
--- a/crates/core_arch/src/x86/ssse3.rs
+++ b/crates/core_arch/src/x86/ssse3.rs
@@ -16,7 +16,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(pabsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_abs_epi8(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_abs_epi8(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i8x16();
         let zero = i8x16::ZERO;
@@ -34,7 +35,8 @@ pub fn _mm_abs_epi8(a: __m128i) -> __m128i {
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(pabsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_abs_epi16(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_abs_epi16(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i16x8();
         let zero = i16x8::ZERO;
@@ -52,7 +54,8 @@ pub fn _mm_abs_epi16(a: __m128i) -> __m128i {
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(pabsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_abs_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_abs_epi32(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i32x4();
         let zero = i32x4::ZERO;
@@ -104,7 +107,8 @@ pub fn _mm_shuffle_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(palignr, IMM8 = 15))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_alignr_epi8<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_alignr_epi8<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     // If palignr is shifting the pair of vectors more than the size of two
     // lanes, emit zero.
@@ -163,7 +167,8 @@ pub fn _mm_alignr_epi8<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(phaddw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i {
     let a = a.as_i16x8();
     let b = b.as_i16x8();
     unsafe {
@@ -194,7 +199,8 @@ pub fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(phaddd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hadd_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hadd_epi32(a: __m128i, b: __m128i) -> __m128i {
     let a = a.as_i32x4();
     let b = b.as_i32x4();
     unsafe {
@@ -212,7 +218,8 @@ pub fn _mm_hadd_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(phsubw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i {
     let a = a.as_i16x8();
     let b = b.as_i16x8();
     unsafe {
@@ -244,7 +251,8 @@ pub fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "ssse3")]
 #[cfg_attr(test, assert_instr(phsubd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_hsub_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_hsub_epi32(a: __m128i, b: __m128i) -> __m128i {
     let a = a.as_i32x4();
     let b = b.as_i32x4();
     unsafe {
@@ -353,24 +361,25 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_abs_epi8() {
+    const unsafe fn test_mm_abs_epi8() {
         let r = _mm_abs_epi8(_mm_set1_epi8(-5));
         assert_eq_m128i(r, _mm_set1_epi8(5));
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_abs_epi16() {
+    const unsafe fn test_mm_abs_epi16() {
         let r = _mm_abs_epi16(_mm_set1_epi16(-5));
         assert_eq_m128i(r, _mm_set1_epi16(5));
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_abs_epi32() {
+    const unsafe fn test_mm_abs_epi32() {
         let r = _mm_abs_epi32(_mm_set1_epi32(-5));
         assert_eq_m128i(r, _mm_set1_epi32(5));
     }
@@ -400,7 +409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_alignr_epi8() {
+    const unsafe fn test_mm_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -440,7 +449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_hadd_epi16() {
+    const unsafe fn test_mm_hadd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 24, 12, 6, 19);
         let expected = _mm_setr_epi16(3, 7, 11, 15, 132, 7, 36, 25);
@@ -490,7 +499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_hadd_epi32() {
+    const unsafe fn test_mm_hadd_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let b = _mm_setr_epi32(4, 128, 4, 3);
         let expected = _mm_setr_epi32(3, 7, 132, 7);
@@ -506,7 +515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_hsub_epi16() {
+    const unsafe fn test_mm_hsub_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 24, 12, 6, 19);
         let expected = _mm_setr_epi16(-1, -1, -1, -1, -124, 1, 12, -13);
@@ -556,7 +565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_hsub_epi32() {
+    const unsafe fn test_mm_hsub_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let b = _mm_setr_epi32(4, 128, 4, 3);
         let expected = _mm_setr_epi32(-1, -1, -124, 1);

From 901494df3e473bb5df0222f4b735f492fa2339fd Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:21:41 +0530
Subject: [PATCH 056/326] Make `sse4.1` functions const

---
 crates/core_arch/src/x86/sse41.rs    | 211 ++++++++++++++++-----------
 crates/core_arch/src/x86_64/sse41.rs |  11 +-
 2 files changed, 134 insertions(+), 88 deletions(-)

diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
index 6c16ee7600..a83f8cc747 100644
--- a/crates/core_arch/src/x86/sse41.rs
+++ b/crates/core_arch/src/x86/sse41.rs
@@ -59,7 +59,8 @@ pub const _MM_FROUND_NEARBYINT: i32 = _MM_FROUND_NO_EXC | _MM_FROUND_CUR_DIRECTI
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pblendvb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blendv_epi8(a: __m128i, b: __m128i, mask: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blendv_epi8(a: __m128i, b: __m128i, mask: __m128i) -> __m128i {
     unsafe {
         let mask: i8x16 = simd_lt(mask.as_i8x16(), i8x16::ZERO);
         transmute(simd_select(mask, b.as_i8x16(), a.as_i8x16()))
@@ -78,7 +79,8 @@ pub fn _mm_blendv_epi8(a: __m128i, b: __m128i, mask: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(pblendw, IMM8 = 0xB1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blend_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blend_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         transmute::<i16x8, _>(simd_shuffle!(
@@ -106,7 +108,8 @@ pub fn _mm_blend_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(blendvpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blendv_pd(a: __m128d, b: __m128d, mask: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blendv_pd(a: __m128d, b: __m128d, mask: __m128d) -> __m128d {
     unsafe {
         let mask: i64x2 = simd_lt(transmute::<_, i64x2>(mask), i64x2::ZERO);
         transmute(simd_select(mask, b.as_f64x2(), a.as_f64x2()))
@@ -121,7 +124,8 @@ pub fn _mm_blendv_pd(a: __m128d, b: __m128d, mask: __m128d) -> __m128d {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(blendvps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blendv_ps(a: __m128, b: __m128, mask: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blendv_ps(a: __m128, b: __m128, mask: __m128) -> __m128 {
     unsafe {
         let mask: i32x4 = simd_lt(transmute::<_, i32x4>(mask), i32x4::ZERO);
         transmute(simd_select(mask, b.as_f32x4(), a.as_f32x4()))
@@ -140,7 +144,8 @@ pub fn _mm_blendv_ps(a: __m128, b: __m128, mask: __m128) -> __m128 {
 #[cfg_attr(test, assert_instr(blendps, IMM2 = 0b10))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blend_pd<const IMM2: i32>(a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blend_pd<const IMM2: i32>(a: __m128d, b: __m128d) -> __m128d {
     static_assert_uimm_bits!(IMM2, 2);
     unsafe {
         transmute::<f64x2, _>(simd_shuffle!(
@@ -160,7 +165,8 @@ pub fn _mm_blend_pd<const IMM2: i32>(a: __m128d, b: __m128d) -> __m128d {
 #[cfg_attr(test, assert_instr(blendps, IMM4 = 0b0101))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blend_ps<const IMM4: i32>(a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blend_ps<const IMM4: i32>(a: __m128, b: __m128) -> __m128 {
     static_assert_uimm_bits!(IMM4, 4);
     unsafe {
         transmute::<f32x4, _>(simd_shuffle!(
@@ -207,7 +213,8 @@ pub fn _mm_blend_ps<const IMM4: i32>(a: __m128, b: __m128) -> __m128 {
 #[cfg_attr(test, assert_instr(extractps, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_extract_ps<const IMM8: i32>(a: __m128) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_extract_ps<const IMM8: i32>(a: __m128) -> i32 {
     static_assert_uimm_bits!(IMM8, 2);
     unsafe { simd_extract!(a, IMM8 as u32, f32).to_bits() as i32 }
 }
@@ -223,7 +230,8 @@ pub fn _mm_extract_ps<const IMM8: i32>(a: __m128) -> i32 {
 #[cfg_attr(test, assert_instr(pextrb, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_extract_epi8<const IMM8: i32>(a: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_extract_epi8<const IMM8: i32>(a: __m128i) -> i32 {
     static_assert_uimm_bits!(IMM8, 4);
     unsafe { simd_extract!(a.as_u8x16(), IMM8 as u32, u8) as i32 }
 }
@@ -236,7 +244,8 @@ pub fn _mm_extract_epi8<const IMM8: i32>(a: __m128i) -> i32 {
 #[cfg_attr(test, assert_instr(extractps, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_extract_epi32<const IMM8: i32>(a: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_extract_epi32<const IMM8: i32>(a: __m128i) -> i32 {
     static_assert_uimm_bits!(IMM8, 2);
     unsafe { simd_extract!(a.as_i32x4(), IMM8 as u32, i32) }
 }
@@ -284,7 +293,8 @@ pub fn _mm_insert_ps<const IMM8: i32>(a: __m128, b: __m128) -> __m128 {
 #[cfg_attr(test, assert_instr(pinsrb, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_insert_epi8<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_insert_epi8<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
     static_assert_uimm_bits!(IMM8, 4);
     unsafe { transmute(simd_insert!(a.as_i8x16(), IMM8 as u32, i as i8)) }
 }
@@ -298,7 +308,8 @@ pub fn _mm_insert_epi8<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
 #[cfg_attr(test, assert_instr(pinsrd, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_insert_epi32<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_insert_epi32<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
     static_assert_uimm_bits!(IMM8, 2);
     unsafe { transmute(simd_insert!(a.as_i32x4(), IMM8 as u32, i)) }
 }
@@ -311,7 +322,8 @@ pub fn _mm_insert_epi32<const IMM8: i32>(a: __m128i, i: i32) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmaxsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_max_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_i8x16(), b.as_i8x16()).as_m128i() }
 }
 
@@ -323,7 +335,8 @@ pub fn _mm_max_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmaxuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_max_epu16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epu16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_u16x8(), b.as_u16x8()).as_m128i() }
 }
 
@@ -335,7 +348,8 @@ pub fn _mm_max_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmaxsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_max_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_i32x4(), b.as_i32x4()).as_m128i() }
 }
 
@@ -347,7 +361,8 @@ pub fn _mm_max_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmaxud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_max_epu32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epu32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_u32x4(), b.as_u32x4()).as_m128i() }
 }
 
@@ -359,7 +374,8 @@ pub fn _mm_max_epu32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pminsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_min_epi8(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epi8(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_i8x16(), b.as_i8x16()).as_m128i() }
 }
 
@@ -371,7 +387,8 @@ pub fn _mm_min_epi8(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pminuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_min_epu16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epu16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_u16x8(), b.as_u16x8()).as_m128i() }
 }
 
@@ -383,7 +400,8 @@ pub fn _mm_min_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pminsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_min_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_i32x4(), b.as_i32x4()).as_m128i() }
 }
 
@@ -395,7 +413,8 @@ pub fn _mm_min_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pminud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_u32x4(), b.as_u32x4()).as_m128i() }
 }
 
@@ -418,7 +437,8 @@ pub fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pcmpeqq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpeq_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_eq::<_, i64x2>(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -429,7 +449,8 @@ pub fn _mm_cmpeq_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovsxbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi8_epi16(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi8_epi16(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i8x16();
         let a: i8x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -444,7 +465,8 @@ pub fn _mm_cvtepi8_epi16(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovsxbd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi8_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi8_epi32(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i8x16();
         let a: i8x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -460,7 +482,8 @@ pub fn _mm_cvtepi8_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovsxbq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi8_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi8_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i8x16();
         let a: i8x2 = simd_shuffle!(a, a, [0, 1]);
@@ -475,7 +498,8 @@ pub fn _mm_cvtepi8_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovsxwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi16_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi16_epi32(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i16x8();
         let a: i16x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -490,7 +514,8 @@ pub fn _mm_cvtepi16_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovsxwq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi16_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi16_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i16x8();
         let a: i16x2 = simd_shuffle!(a, a, [0, 1]);
@@ -505,7 +530,8 @@ pub fn _mm_cvtepi16_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovsxdq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepi32_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi32_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i32x4();
         let a: i32x2 = simd_shuffle!(a, a, [0, 1]);
@@ -520,7 +546,8 @@ pub fn _mm_cvtepi32_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovzxbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepu8_epi16(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu8_epi16(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u8x16();
         let a: u8x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -535,7 +562,8 @@ pub fn _mm_cvtepu8_epi16(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovzxbd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepu8_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu8_epi32(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u8x16();
         let a: u8x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -550,7 +578,8 @@ pub fn _mm_cvtepu8_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovzxbq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepu8_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu8_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u8x16();
         let a: u8x2 = simd_shuffle!(a, a, [0, 1]);
@@ -566,7 +595,8 @@ pub fn _mm_cvtepu8_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovzxwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepu16_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu16_epi32(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u16x8();
         let a: u16x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -582,7 +612,8 @@ pub fn _mm_cvtepu16_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovzxwq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepu16_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu16_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u16x8();
         let a: u16x2 = simd_shuffle!(a, a, [0, 1]);
@@ -598,7 +629,8 @@ pub fn _mm_cvtepu16_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmovzxdq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cvtepu32_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu32_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_u32x4();
         let a: u32x2 = simd_shuffle!(a, a, [0, 1]);
@@ -655,7 +687,8 @@ pub fn _mm_dp_ps<const IMM8: i32>(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(roundpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_floor_pd(a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_floor_pd(a: __m128d) -> __m128d {
     unsafe { simd_floor(a) }
 }
 
@@ -668,7 +701,8 @@ pub fn _mm_floor_pd(a: __m128d) -> __m128d {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(roundps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_floor_ps(a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_floor_ps(a: __m128) -> __m128 {
     unsafe { simd_floor(a) }
 }
 
@@ -711,7 +745,8 @@ pub fn _mm_floor_ss(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(roundpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_ceil_pd(a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_ceil_pd(a: __m128d) -> __m128d {
     unsafe { simd_ceil(a) }
 }
 
@@ -724,7 +759,8 @@ pub fn _mm_ceil_pd(a: __m128d) -> __m128d {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(roundps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_ceil_ps(a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_ceil_ps(a: __m128) -> __m128 {
     unsafe { simd_ceil(a) }
 }
 
@@ -887,7 +923,8 @@ pub fn _mm_minpos_epu16(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmuldq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mul_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let a = simd_cast::<_, i64x2>(simd_cast::<_, i32x2>(a.as_i64x2()));
         let b = simd_cast::<_, i64x2>(simd_cast::<_, i32x2>(b.as_i64x2()));
@@ -907,7 +944,8 @@ pub fn _mm_mul_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(pmulld))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_mullo_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mullo_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_mul(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -973,7 +1011,8 @@ pub fn _mm_mpsadbw_epu8<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(ptest))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_testz_si128(a: __m128i, mask: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testz_si128(a: __m128i, mask: __m128i) -> i32 {
     unsafe {
         let r = simd_reduce_or(simd_and(a.as_i64x2(), mask.as_i64x2()));
         (0i64 == r) as i32
@@ -999,7 +1038,8 @@ pub fn _mm_testz_si128(a: __m128i, mask: __m128i) -> i32 {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(ptest))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_testc_si128(a: __m128i, mask: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testc_si128(a: __m128i, mask: __m128i) -> i32 {
     unsafe {
         let r = simd_reduce_or(simd_and(
             simd_xor(a.as_i64x2(), i64x2::splat(!0)),
@@ -1051,7 +1091,8 @@ pub fn _mm_testnzc_si128(a: __m128i, mask: __m128i) -> i32 {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(ptest))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_test_all_zeros(a: __m128i, mask: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_test_all_zeros(a: __m128i, mask: __m128i) -> i32 {
     _mm_testz_si128(a, mask)
 }
 
@@ -1073,7 +1114,8 @@ pub fn _mm_test_all_zeros(a: __m128i, mask: __m128i) -> i32 {
 #[cfg_attr(test, assert_instr(pcmpeqd))]
 #[cfg_attr(test, assert_instr(ptest))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_test_all_ones(a: __m128i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_test_all_ones(a: __m128i) -> i32 {
     _mm_testc_si128(a, _mm_cmpeq_epi32(a, a))
 }
 
@@ -1148,12 +1190,13 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use crate::core_arch::x86::*;
     use std::mem;
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_blendv_epi8() {
+    const unsafe fn test_mm_blendv_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -1176,7 +1219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_blendv_pd() {
+    const unsafe fn test_mm_blendv_pd() {
         let a = _mm_set1_pd(0.0);
         let b = _mm_set1_pd(1.0);
         let mask = transmute(_mm_setr_epi64x(0, -1));
@@ -1186,7 +1229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_blendv_ps() {
+    const unsafe fn test_mm_blendv_ps() {
         let a = _mm_set1_ps(0.0);
         let b = _mm_set1_ps(1.0);
         let mask = transmute(_mm_setr_epi32(0, -1, 0, -1));
@@ -1196,7 +1239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_blend_pd() {
+    const unsafe fn test_mm_blend_pd() {
         let a = _mm_set1_pd(0.0);
         let b = _mm_set1_pd(1.0);
         let r = _mm_blend_pd::<0b10>(a, b);
@@ -1205,7 +1248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_blend_ps() {
+    const unsafe fn test_mm_blend_ps() {
         let a = _mm_set1_ps(0.0);
         let b = _mm_set1_ps(1.0);
         let r = _mm_blend_ps::<0b1010>(a, b);
@@ -1214,7 +1257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_blend_epi16() {
+    const unsafe fn test_mm_blend_epi16() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let r = _mm_blend_epi16::<0b1010_1100>(a, b);
@@ -1223,7 +1266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_extract_ps() {
+    const unsafe fn test_mm_extract_ps() {
         let a = _mm_setr_ps(0.0, 1.0, 2.0, 3.0);
         let r: f32 = f32::from_bits(_mm_extract_ps::<1>(a) as u32);
         assert_eq!(r, 1.0);
@@ -1232,7 +1275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_extract_epi8() {
+    const unsafe fn test_mm_extract_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             -1, 1, 2, 3, 4, 5, 6, 7,
@@ -1245,7 +1288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_extract_epi32() {
+    const unsafe fn test_mm_extract_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let r = _mm_extract_epi32::<1>(a);
         assert_eq!(r, 1);
@@ -1270,7 +1313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_insert_epi8() {
+    const unsafe fn test_mm_insert_epi8() {
         let a = _mm_set1_epi8(0);
         let e = _mm_setr_epi8(0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm_insert_epi8::<1>(a, 32);
@@ -1281,7 +1324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_insert_epi32() {
+    const unsafe fn test_mm_insert_epi32() {
         let a = _mm_set1_epi32(0);
         let e = _mm_setr_epi32(0, 32, 0, 0);
         let r = _mm_insert_epi32::<1>(a, 32);
@@ -1292,7 +1335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_max_epi8() {
+    const unsafe fn test_mm_max_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 4, 5, 8, 9, 12, 13, 16,
@@ -1313,7 +1356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_max_epu16() {
+    const unsafe fn test_mm_max_epu16() {
         let a = _mm_setr_epi16(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm_setr_epi16(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm_max_epu16(a, b);
@@ -1322,7 +1365,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_max_epi32() {
+    const unsafe fn test_mm_max_epi32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_max_epi32(a, b);
@@ -1331,7 +1374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_max_epu32() {
+    const unsafe fn test_mm_max_epu32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_max_epu32(a, b);
@@ -1340,7 +1383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epi8() {
+    const unsafe fn test_mm_min_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 4, 5, 8, 9, 12, 13, 16,
@@ -1379,7 +1422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epu16() {
+    const unsafe fn test_mm_min_epu16() {
         let a = _mm_setr_epi16(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm_setr_epi16(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm_min_epu16(a, b);
@@ -1388,7 +1431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epi32() {
+    const unsafe fn test_mm_min_epi32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_min_epi32(a, b);
@@ -1403,7 +1446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epu32() {
+    const unsafe fn test_mm_min_epu32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_min_epu32(a, b);
@@ -1421,7 +1464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cmpeq_epi64() {
+    const unsafe fn test_mm_cmpeq_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(0, 0);
         let r = _mm_cmpeq_epi64(a, b);
@@ -1430,7 +1473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepi8_epi16() {
+    const unsafe fn test_mm_cvtepi8_epi16() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepi8_epi16(a);
         let e = _mm_set1_epi16(10);
@@ -1442,7 +1485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepi8_epi32() {
+    const unsafe fn test_mm_cvtepi8_epi32() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepi8_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1454,7 +1497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepi8_epi64() {
+    const unsafe fn test_mm_cvtepi8_epi64() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepi8_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1466,7 +1509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepi16_epi32() {
+    const unsafe fn test_mm_cvtepi16_epi32() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepi16_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1478,7 +1521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepi16_epi64() {
+    const unsafe fn test_mm_cvtepi16_epi64() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepi16_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1490,7 +1533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepi32_epi64() {
+    const unsafe fn test_mm_cvtepi32_epi64() {
         let a = _mm_set1_epi32(10);
         let r = _mm_cvtepi32_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1502,7 +1545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepu8_epi16() {
+    const unsafe fn test_mm_cvtepu8_epi16() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepu8_epi16(a);
         let e = _mm_set1_epi16(10);
@@ -1510,7 +1553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepu8_epi32() {
+    const unsafe fn test_mm_cvtepu8_epi32() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepu8_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1518,7 +1561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepu8_epi64() {
+    const unsafe fn test_mm_cvtepu8_epi64() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepu8_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1526,7 +1569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepu16_epi32() {
+    const unsafe fn test_mm_cvtepu16_epi32() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepu16_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1534,7 +1577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepu16_epi64() {
+    const unsafe fn test_mm_cvtepu16_epi64() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepu16_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1542,7 +1585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_cvtepu32_epi64() {
+    const unsafe fn test_mm_cvtepu32_epi64() {
         let a = _mm_set1_epi32(10);
         let r = _mm_cvtepu32_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1566,7 +1609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_floor_pd() {
+    const unsafe fn test_mm_floor_pd() {
         let a = _mm_setr_pd(2.5, 4.5);
         let r = _mm_floor_pd(a);
         let e = _mm_setr_pd(2.0, 4.0);
@@ -1574,7 +1617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_floor_ps() {
+    const unsafe fn test_mm_floor_ps() {
         let a = _mm_setr_ps(2.5, 4.5, 8.5, 16.5);
         let r = _mm_floor_ps(a);
         let e = _mm_setr_ps(2.0, 4.0, 8.0, 16.0);
@@ -1600,7 +1643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_ceil_pd() {
+    const unsafe fn test_mm_ceil_pd() {
         let a = _mm_setr_pd(1.5, 3.5);
         let r = _mm_ceil_pd(a);
         let e = _mm_setr_pd(2.0, 4.0);
@@ -1608,7 +1651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_ceil_ps() {
+    const unsafe fn test_mm_ceil_ps() {
         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
         let r = _mm_ceil_ps(a);
         let e = _mm_setr_ps(2.0, 4.0, 8.0, 16.0);
@@ -1729,7 +1772,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_mul_epi32() {
+    const unsafe fn test_mm_mul_epi32() {
         {
             let a = _mm_setr_epi32(1, 1, 1, 1);
             let b = _mm_setr_epi32(1, 2, 3, 4);
@@ -1750,7 +1793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_mullo_epi32() {
+    const unsafe fn test_mm_mullo_epi32() {
         {
             let a = _mm_setr_epi32(1, 1, 1, 1);
             let b = _mm_setr_epi32(1, 2, 3, 4);
@@ -1808,7 +1851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_testz_si128() {
+    const unsafe fn test_mm_testz_si128() {
         let a = _mm_set1_epi8(1);
         let mask = _mm_set1_epi8(0);
         let r = _mm_testz_si128(a, mask);
@@ -1824,7 +1867,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_testc_si128() {
+    const unsafe fn test_mm_testc_si128() {
         let a = _mm_set1_epi8(-1);
         let mask = _mm_set1_epi8(0);
         let r = _mm_testc_si128(a, mask);
@@ -1860,7 +1903,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_test_all_zeros() {
+    const unsafe fn test_mm_test_all_zeros() {
         let a = _mm_set1_epi8(1);
         let mask = _mm_set1_epi8(0);
         let r = _mm_test_all_zeros(a, mask);
@@ -1876,7 +1919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_test_all_ones() {
+    const unsafe fn test_mm_test_all_ones() {
         let a = _mm_set1_epi8(-1);
         let r = _mm_test_all_ones(a);
         assert_eq!(r, 1);
diff --git a/crates/core_arch/src/x86_64/sse41.rs b/crates/core_arch/src/x86_64/sse41.rs
index 4b7d25f214..3b1c88ad8c 100644
--- a/crates/core_arch/src/x86_64/sse41.rs
+++ b/crates/core_arch/src/x86_64/sse41.rs
@@ -13,7 +13,8 @@ use stdarch_test::assert_instr;
 #[cfg_attr(test, assert_instr(pextrq, IMM1 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_extract_epi64<const IMM1: i32>(a: __m128i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_extract_epi64<const IMM1: i32>(a: __m128i) -> i64 {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe { simd_extract!(a.as_i64x2(), IMM1 as u32) }
 }
@@ -27,7 +28,8 @@ pub fn _mm_extract_epi64<const IMM1: i32>(a: __m128i) -> i64 {
 #[cfg_attr(test, assert_instr(pinsrq, IMM1 = 0))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_insert_epi64<const IMM1: i32>(a: __m128i, i: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_insert_epi64<const IMM1: i32>(a: __m128i, i: i64) -> __m128i {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe { transmute(simd_insert!(a.as_i64x2(), IMM1 as u32, i)) }
 }
@@ -35,10 +37,11 @@ pub fn _mm_insert_epi64<const IMM1: i32>(a: __m128i, i: i64) -> __m128i {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::arch::x86_64::*;
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_extract_epi64() {
+    const unsafe fn test_mm_extract_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let r = _mm_extract_epi64::<1>(a);
         assert_eq!(r, 1);
@@ -47,7 +50,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_insert_epi64() {
+    const unsafe fn test_mm_insert_epi64() {
         let a = _mm_set1_epi64x(0);
         let e = _mm_setr_epi64x(0, 32);
         let r = _mm_insert_epi64::<1>(a, 32);

From f724604c2ef5ed04ae07820126b8430fc47197eb Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:21:58 +0530
Subject: [PATCH 057/326] Make `sse4.2` functions const

---
 crates/core_arch/src/x86/sse42.rs | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/crates/core_arch/src/x86/sse42.rs b/crates/core_arch/src/x86/sse42.rs
index 83c51f2b70..4d3c481fe1 100644
--- a/crates/core_arch/src/x86/sse42.rs
+++ b/crates/core_arch/src/x86/sse42.rs
@@ -563,7 +563,8 @@ pub fn _mm_crc32_u32(crc: u32, v: u32) -> u32 {
 #[target_feature(enable = "sse4.2")]
 #[cfg_attr(test, assert_instr(pcmpgtq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_cmpgt_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_gt::<_, i64x2>(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -609,6 +610,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
@@ -789,7 +791,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpgt_epi64() {
+    const unsafe fn test_mm_cmpgt_epi64() {
         let a = _mm_setr_epi64x(0, 0x2a);
         let b = _mm_set1_epi64x(0x00);
         let i = _mm_cmpgt_epi64(a, b);

From d5743eac5f071b4d7c1332882585be6dadd9fba1 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:11:22 +0530
Subject: [PATCH 058/326] Make `avx` functions const

---
 crates/core_arch/src/x86/avx.rs    | 752 ++++++++++++++++++-----------
 crates/core_arch/src/x86_64/avx.rs |  11 +-
 2 files changed, 466 insertions(+), 297 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index c50c83fcaa..acba0a3db7 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -30,7 +30,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vaddpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_add_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe { simd_add(a, b) }
 }
 
@@ -42,7 +43,8 @@ pub fn _mm256_add_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vaddps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_add_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_ps(a: __m256, b: __m256) -> __m256 {
     unsafe { simd_add(a, b) }
 }
 
@@ -55,7 +57,8 @@ pub fn _mm256_add_ps(a: __m256, b: __m256) -> __m256 {
 // See https://github.com/rust-lang/stdarch/issues/71
 #[cfg_attr(test, assert_instr(vandp))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_and_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_and_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let a: u64x4 = transmute(a);
         let b: u64x4 = transmute(b);
@@ -71,7 +74,8 @@ pub fn _mm256_and_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_and_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_and_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let a: u32x8 = transmute(a);
         let b: u32x8 = transmute(b);
@@ -88,7 +92,8 @@ pub fn _mm256_and_ps(a: __m256, b: __m256) -> __m256 {
 // See <https://github.com/rust-lang/stdarch/issues/71>.
 #[cfg_attr(test, assert_instr(vorp))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_or_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_or_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let a: u64x4 = transmute(a);
         let b: u64x4 = transmute(b);
@@ -104,7 +109,8 @@ pub fn _mm256_or_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_or_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_or_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let a: u32x8 = transmute(a);
         let b: u32x8 = transmute(b);
@@ -121,7 +127,8 @@ pub fn _mm256_or_ps(a: __m256, b: __m256) -> __m256 {
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_shuffle_pd<const MASK: i32>(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_pd<const MASK: i32>(a: __m256d, b: __m256d) -> __m256d {
     static_assert_uimm_bits!(MASK, 8);
     unsafe {
         simd_shuffle!(
@@ -146,7 +153,8 @@ pub fn _mm256_shuffle_pd<const MASK: i32>(a: __m256d, b: __m256d) -> __m256d {
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_shuffle_ps<const MASK: i32>(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_ps<const MASK: i32>(a: __m256, b: __m256) -> __m256 {
     static_assert_uimm_bits!(MASK, 8);
     unsafe {
         simd_shuffle!(
@@ -174,7 +182,8 @@ pub fn _mm256_shuffle_ps<const MASK: i32>(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vandnp))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_andnot_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_andnot_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let a: u64x4 = transmute(a);
         let b: u64x4 = transmute(b);
@@ -191,7 +200,8 @@ pub fn _mm256_andnot_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_andnot_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_andnot_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let a: u32x8 = transmute(a);
         let b: u32x8 = transmute(b);
@@ -255,7 +265,8 @@ pub fn _mm256_min_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmulpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mul_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mul_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe { simd_mul(a, b) }
 }
 
@@ -267,7 +278,8 @@ pub fn _mm256_mul_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmulps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mul_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mul_ps(a: __m256, b: __m256) -> __m256 {
     unsafe { simd_mul(a, b) }
 }
 
@@ -279,7 +291,8 @@ pub fn _mm256_mul_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vaddsubpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_addsub_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_addsub_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let a = a.as_f64x4();
         let b = b.as_f64x4();
@@ -297,7 +310,8 @@ pub fn _mm256_addsub_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vaddsubps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_addsub_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_addsub_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let a = a.as_f32x8();
         let b = b.as_f32x8();
@@ -315,7 +329,8 @@ pub fn _mm256_addsub_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vsubpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sub_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe { simd_sub(a, b) }
 }
 
@@ -327,7 +342,8 @@ pub fn _mm256_sub_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vsubps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sub_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_ps(a: __m256, b: __m256) -> __m256 {
     unsafe { simd_sub(a, b) }
 }
 
@@ -339,7 +355,8 @@ pub fn _mm256_sub_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vdivps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_div_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_div_ps(a: __m256, b: __m256) -> __m256 {
     unsafe { simd_div(a, b) }
 }
 
@@ -351,7 +368,8 @@ pub fn _mm256_div_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vdivpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_div_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_div_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe { simd_div(a, b) }
 }
 
@@ -386,7 +404,8 @@ pub fn _mm256_round_pd<const ROUNDING: i32>(a: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vroundpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_ceil_pd(a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_ceil_pd(a: __m256d) -> __m256d {
     unsafe { simd_ceil(a) }
 }
 
@@ -398,7 +417,8 @@ pub fn _mm256_ceil_pd(a: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vroundpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_floor_pd(a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_floor_pd(a: __m256d) -> __m256d {
     unsafe { simd_floor(a) }
 }
 
@@ -433,7 +453,8 @@ pub fn _mm256_round_ps<const ROUNDING: i32>(a: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vroundps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_ceil_ps(a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_ceil_ps(a: __m256) -> __m256 {
     unsafe { simd_ceil(a) }
 }
 
@@ -445,7 +466,8 @@ pub fn _mm256_ceil_ps(a: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vroundps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_floor_ps(a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_floor_ps(a: __m256) -> __m256 {
     unsafe { simd_floor(a) }
 }
 
@@ -485,7 +507,8 @@ pub fn _mm256_sqrt_pd(a: __m256d) -> __m256d {
 #[cfg_attr(test, assert_instr(vblendps, IMM4 = 9))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blend_pd<const IMM4: i32>(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blend_pd<const IMM4: i32>(a: __m256d, b: __m256d) -> __m256d {
     static_assert_uimm_bits!(IMM4, 4);
     unsafe {
         simd_shuffle!(
@@ -510,7 +533,8 @@ pub fn _mm256_blend_pd<const IMM4: i32>(a: __m256d, b: __m256d) -> __m256d {
 #[cfg_attr(test, assert_instr(vblendps, IMM8 = 9))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blend_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blend_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         simd_shuffle!(
@@ -538,7 +562,8 @@ pub fn _mm256_blend_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vblendvpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blendv_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blendv_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe {
         let mask: i64x4 = simd_lt(transmute::<_, i64x4>(c), i64x4::ZERO);
         transmute(simd_select(mask, b.as_f64x4(), a.as_f64x4()))
@@ -553,7 +578,8 @@ pub fn _mm256_blendv_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vblendvps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blendv_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blendv_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe {
         let mask: i32x8 = simd_lt(transmute::<_, i32x8>(c), i32x8::ZERO);
         transmute(simd_select(mask, b.as_f32x8(), a.as_f32x8()))
@@ -586,7 +612,8 @@ pub fn _mm256_dp_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vhaddpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hadd_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hadd_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 4, 2, 6]);
         let odd = simd_shuffle!(a, b, [1, 5, 3, 7]);
@@ -605,7 +632,8 @@ pub fn _mm256_hadd_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vhaddps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hadd_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hadd_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 2, 8, 10, 4, 6, 12, 14]);
         let odd = simd_shuffle!(a, b, [1, 3, 9, 11, 5, 7, 13, 15]);
@@ -623,7 +651,8 @@ pub fn _mm256_hadd_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vhsubpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hsub_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hsub_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 4, 2, 6]);
         let odd = simd_shuffle!(a, b, [1, 5, 3, 7]);
@@ -642,7 +671,8 @@ pub fn _mm256_hsub_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vhsubps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hsub_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hsub_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let even = simd_shuffle!(a, b, [0, 2, 8, 10, 4, 6, 12, 14]);
         let odd = simd_shuffle!(a, b, [1, 3, 9, 11, 5, 7, 13, 15]);
@@ -658,7 +688,8 @@ pub fn _mm256_hsub_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vxorp))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_xor_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_xor_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let a: u64x4 = transmute(a);
         let b: u64x4 = transmute(b);
@@ -674,7 +705,8 @@ pub fn _mm256_xor_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_xor_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_xor_ps(a: __m256, b: __m256) -> __m256 {
     unsafe {
         let a: u32x8 = transmute(a);
         let b: u32x8 = transmute(b);
@@ -881,7 +913,8 @@ pub fn _mm_cmp_ss<const IMM5: i32>(a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi32_pd(a: __m128i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi32_pd(a: __m128i) -> __m256d {
     unsafe { simd_cast(a.as_i32x4()) }
 }
 
@@ -893,7 +926,8 @@ pub fn _mm256_cvtepi32_pd(a: __m128i) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi32_ps(a: __m256i) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi32_ps(a: __m256i) -> __m256 {
     unsafe { simd_cast(a.as_i32x8()) }
 }
 
@@ -905,7 +939,8 @@ pub fn _mm256_cvtepi32_ps(a: __m256i) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vcvtpd2ps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtpd_ps(a: __m256d) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtpd_ps(a: __m256d) -> __m128 {
     unsafe { simd_cast(a) }
 }
 
@@ -929,7 +964,8 @@ pub fn _mm256_cvtps_epi32(a: __m256) -> __m256i {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vcvtps2pd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtps_pd(a: __m128) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtps_pd(a: __m128) -> __m256d {
     unsafe { simd_cast(a) }
 }
 
@@ -940,7 +976,8 @@ pub fn _mm256_cvtps_pd(a: __m128) -> __m256d {
 #[target_feature(enable = "avx")]
 //#[cfg_attr(test, assert_instr(movsd))] FIXME
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -989,7 +1026,8 @@ pub fn _mm256_cvttps_epi32(a: __m256) -> __m256i {
 #[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extractf128_ps<const IMM1: i32>(a: __m256) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extractf128_ps<const IMM1: i32>(a: __m256) -> __m128 {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         simd_shuffle!(
@@ -1009,7 +1047,8 @@ pub fn _mm256_extractf128_ps<const IMM1: i32>(a: __m256) -> __m128 {
 #[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extractf128_pd<const IMM1: i32>(a: __m256d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extractf128_pd<const IMM1: i32>(a: __m256d) -> __m128d {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe { simd_shuffle!(a, _mm256_undefined_pd(), [[0, 1], [2, 3]][IMM1 as usize]) }
 }
@@ -1022,7 +1061,8 @@ pub fn _mm256_extractf128_pd<const IMM1: i32>(a: __m256d) -> __m128d {
 #[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extractf128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extractf128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         let dst: i64x2 = simd_shuffle!(a.as_i64x4(), i64x4::ZERO, [[0, 1], [2, 3]][IMM1 as usize],);
@@ -1038,7 +1078,8 @@ pub fn _mm256_extractf128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
 // This intrinsic has no corresponding instruction.
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extract_epi32<const INDEX: i32>(a: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extract_epi32<const INDEX: i32>(a: __m256i) -> i32 {
     static_assert_uimm_bits!(INDEX, 3);
     unsafe { simd_extract!(a.as_i32x8(), INDEX as u32) }
 }
@@ -1049,7 +1090,8 @@ pub fn _mm256_extract_epi32<const INDEX: i32>(a: __m256i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtsi256_si32(a: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtsi256_si32(a: __m256i) -> i32 {
     unsafe { simd_extract!(a.as_i32x8(), 0) }
 }
 
@@ -1109,7 +1151,8 @@ pub fn _mm_permutevar_ps(a: __m128, b: __m128i) -> __m128 {
 #[cfg_attr(test, assert_instr(vshufps, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute_ps<const IMM8: i32>(a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute_ps<const IMM8: i32>(a: __m256) -> __m256 {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         simd_shuffle!(
@@ -1138,7 +1181,8 @@ pub fn _mm256_permute_ps<const IMM8: i32>(a: __m256) -> __m256 {
 #[cfg_attr(test, assert_instr(vshufps, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_permute_ps<const IMM8: i32>(a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_permute_ps<const IMM8: i32>(a: __m128) -> __m128 {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         simd_shuffle!(
@@ -1187,7 +1231,8 @@ pub fn _mm_permutevar_pd(a: __m128d, b: __m128i) -> __m128d {
 #[cfg_attr(test, assert_instr(vshufpd, IMM4 = 0x1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute_pd<const IMM4: i32>(a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute_pd<const IMM4: i32>(a: __m256d) -> __m256d {
     static_assert_uimm_bits!(IMM4, 4);
     unsafe {
         simd_shuffle!(
@@ -1212,7 +1257,8 @@ pub fn _mm256_permute_pd<const IMM4: i32>(a: __m256d) -> __m256d {
 #[cfg_attr(test, assert_instr(vshufpd, IMM2 = 0x1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_permute_pd<const IMM2: i32>(a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_permute_pd<const IMM2: i32>(a: __m128d) -> __m128d {
     static_assert_uimm_bits!(IMM2, 2);
     unsafe {
         simd_shuffle!(
@@ -1232,7 +1278,8 @@ pub fn _mm_permute_pd<const IMM2: i32>(a: __m128d) -> __m128d {
 #[cfg_attr(test, assert_instr(vperm2f128, IMM8 = 0x5))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute2f128_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute2f128_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_castsi256_ps(_mm256_permute2f128_si256::<IMM8>(
         _mm256_castps_si256(a),
@@ -1249,7 +1296,8 @@ pub fn _mm256_permute2f128_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
 #[cfg_attr(test, assert_instr(vperm2f128, IMM8 = 0x31))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute2f128_pd<const IMM8: i32>(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute2f128_pd<const IMM8: i32>(a: __m256d, b: __m256d) -> __m256d {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_castsi256_pd(_mm256_permute2f128_si256::<IMM8>(
         _mm256_castpd_si256(a),
@@ -1266,7 +1314,8 @@ pub fn _mm256_permute2f128_pd<const IMM8: i32>(a: __m256d, b: __m256d) -> __m256
 #[cfg_attr(test, assert_instr(vperm2f128, IMM8 = 0x31))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute2f128_si256<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute2f128_si256<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     const fn idx(imm8: i32, pos: u32) -> u32 {
         let part = if pos < 2 {
@@ -1308,7 +1357,8 @@ pub fn _mm256_permute2f128_si256<const IMM8: i32>(a: __m256i, b: __m256i) -> __m
 #[cfg_attr(test, assert_instr(vbroadcastss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::trivially_copy_pass_by_ref)]
-pub fn _mm256_broadcast_ss(f: &f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_ss(f: &f32) -> __m256 {
     _mm256_set1_ps(*f)
 }
 
@@ -1321,7 +1371,8 @@ pub fn _mm256_broadcast_ss(f: &f32) -> __m256 {
 #[cfg_attr(test, assert_instr(vbroadcastss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::trivially_copy_pass_by_ref)]
-pub fn _mm_broadcast_ss(f: &f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcast_ss(f: &f32) -> __m128 {
     _mm_set1_ps(*f)
 }
 
@@ -1334,7 +1385,8 @@ pub fn _mm_broadcast_ss(f: &f32) -> __m128 {
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::trivially_copy_pass_by_ref)]
-pub fn _mm256_broadcast_sd(f: &f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_sd(f: &f64) -> __m256d {
     _mm256_set1_pd(*f)
 }
 
@@ -1346,7 +1398,8 @@ pub fn _mm256_broadcast_sd(f: &f64) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vbroadcastf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcast_ps(a: &__m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_ps(a: &__m128) -> __m256 {
     unsafe { simd_shuffle!(*a, _mm_setzero_ps(), [0, 1, 2, 3, 0, 1, 2, 3]) }
 }
 
@@ -1358,7 +1411,8 @@ pub fn _mm256_broadcast_ps(a: &__m128) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vbroadcastf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcast_pd(a: &__m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_pd(a: &__m128d) -> __m256d {
     unsafe { simd_shuffle!(*a, _mm_setzero_pd(), [0, 1, 0, 1]) }
 }
 
@@ -1372,7 +1426,8 @@ pub fn _mm256_broadcast_pd(a: &__m128d) -> __m256d {
 #[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insertf128_ps<const IMM1: i32>(a: __m256, b: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insertf128_ps<const IMM1: i32>(a: __m256, b: __m128) -> __m256 {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         simd_shuffle!(
@@ -1393,7 +1448,8 @@ pub fn _mm256_insertf128_ps<const IMM1: i32>(a: __m256, b: __m128) -> __m256 {
 #[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insertf128_pd<const IMM1: i32>(a: __m256d, b: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insertf128_pd<const IMM1: i32>(a: __m256d, b: __m128d) -> __m256d {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         simd_shuffle!(
@@ -1413,7 +1469,8 @@ pub fn _mm256_insertf128_pd<const IMM1: i32>(a: __m256d, b: __m128d) -> __m256d
 #[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insertf128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insertf128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m256i {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         let dst: i64x4 = simd_shuffle!(
@@ -1434,7 +1491,8 @@ pub fn _mm256_insertf128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m25
 // This intrinsic has no corresponding instruction.
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insert_epi8<const INDEX: i32>(a: __m256i, i: i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insert_epi8<const INDEX: i32>(a: __m256i, i: i8) -> __m256i {
     static_assert_uimm_bits!(INDEX, 5);
     unsafe { transmute(simd_insert!(a.as_i8x32(), INDEX as u32, i)) }
 }
@@ -1448,7 +1506,8 @@ pub fn _mm256_insert_epi8<const INDEX: i32>(a: __m256i, i: i8) -> __m256i {
 // This intrinsic has no corresponding instruction.
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insert_epi16<const INDEX: i32>(a: __m256i, i: i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insert_epi16<const INDEX: i32>(a: __m256i, i: i16) -> __m256i {
     static_assert_uimm_bits!(INDEX, 4);
     unsafe { transmute(simd_insert!(a.as_i16x16(), INDEX as u32, i)) }
 }
@@ -1462,7 +1521,8 @@ pub fn _mm256_insert_epi16<const INDEX: i32>(a: __m256i, i: i16) -> __m256i {
 // This intrinsic has no corresponding instruction.
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insert_epi32<const INDEX: i32>(a: __m256i, i: i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insert_epi32<const INDEX: i32>(a: __m256i, i: i32) -> __m256i {
     static_assert_uimm_bits!(INDEX, 3);
     unsafe { transmute(simd_insert!(a.as_i32x8(), INDEX as u32, i)) }
 }
@@ -1481,7 +1541,8 @@ pub fn _mm256_insert_epi32<const INDEX: i32>(a: __m256i, i: i32) -> __m256i {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
     *(mem_addr as *const __m256d)
 }
 
@@ -1499,7 +1560,8 @@ pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
     *(mem_addr as *mut __m256d) = a;
 }
 
@@ -1517,7 +1579,8 @@ pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
     *(mem_addr as *const __m256)
 }
 
@@ -1535,7 +1598,8 @@ pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
 )]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[allow(clippy::cast_ptr_alignment)]
-pub unsafe fn _mm256_store_ps(mem_addr: *mut f32, a: __m256) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_store_ps(mem_addr: *mut f32, a: __m256) {
     *(mem_addr as *mut __m256) = a;
 }
 
@@ -1548,7 +1612,8 @@ pub unsafe fn _mm256_store_ps(mem_addr: *mut f32, a: __m256) {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_loadu_pd(mem_addr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_pd(mem_addr: *const f64) -> __m256d {
     let mut dst = _mm256_undefined_pd();
     ptr::copy_nonoverlapping(
         mem_addr as *const u8,
@@ -1567,7 +1632,8 @@ pub unsafe fn _mm256_loadu_pd(mem_addr: *const f64) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_storeu_pd(mem_addr: *mut f64, a: __m256d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_pd(mem_addr: *mut f64, a: __m256d) {
     mem_addr.cast::<__m256d>().write_unaligned(a);
 }
 
@@ -1580,7 +1646,8 @@ pub unsafe fn _mm256_storeu_pd(mem_addr: *mut f64, a: __m256d) {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_loadu_ps(mem_addr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_ps(mem_addr: *const f32) -> __m256 {
     let mut dst = _mm256_undefined_ps();
     ptr::copy_nonoverlapping(
         mem_addr as *const u8,
@@ -1599,7 +1666,8 @@ pub unsafe fn _mm256_loadu_ps(mem_addr: *const f32) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_storeu_ps(mem_addr: *mut f32, a: __m256) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_ps(mem_addr: *mut f32, a: __m256) {
     mem_addr.cast::<__m256>().write_unaligned(a);
 }
 
@@ -1615,7 +1683,8 @@ pub unsafe fn _mm256_storeu_ps(mem_addr: *mut f32, a: __m256) {
     assert_instr(vmovaps)
 )] // FIXME vmovdqa expected
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
     *mem_addr
 }
 
@@ -1631,7 +1700,8 @@ pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
     assert_instr(vmovaps)
 )] // FIXME vmovdqa expected
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_store_si256(mem_addr: *mut __m256i, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_store_si256(mem_addr: *mut __m256i, a: __m256i) {
     *mem_addr = a;
 }
 
@@ -1643,7 +1713,8 @@ pub unsafe fn _mm256_store_si256(mem_addr: *mut __m256i, a: __m256i) {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovups))] // FIXME vmovdqu expected
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_loadu_si256(mem_addr: *const __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_si256(mem_addr: *const __m256i) -> __m256i {
     let mut dst = _mm256_undefined_si256();
     ptr::copy_nonoverlapping(
         mem_addr as *const u8,
@@ -1661,7 +1732,8 @@ pub unsafe fn _mm256_loadu_si256(mem_addr: *const __m256i) -> __m256i {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovups))] // FIXME vmovdqu expected
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_storeu_si256(mem_addr: *mut __m256i, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_si256(mem_addr: *mut __m256i, a: __m256i) {
     mem_addr.write_unaligned(a);
 }
 
@@ -1674,7 +1746,8 @@ pub unsafe fn _mm256_storeu_si256(mem_addr: *mut __m256i, a: __m256i) {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskload_pd(mem_addr: *const f64, mask: __m256i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskload_pd(mem_addr: *const f64, mask: __m256i) -> __m256d {
     let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm256_setzero_pd())
 }
@@ -1687,7 +1760,8 @@ pub unsafe fn _mm256_maskload_pd(mem_addr: *const f64, mask: __m256i) -> __m256d
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskstore_pd(mem_addr: *mut f64, mask: __m256i, a: __m256d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskstore_pd(mem_addr: *mut f64, mask: __m256i, a: __m256d) {
     let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
@@ -1701,7 +1775,8 @@ pub unsafe fn _mm256_maskstore_pd(mem_addr: *mut f64, mask: __m256i, a: __m256d)
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskload_pd(mem_addr: *const f64, mask: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskload_pd(mem_addr: *const f64, mask: __m128i) -> __m128d {
     let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm_setzero_pd())
 }
@@ -1714,7 +1789,8 @@ pub unsafe fn _mm_maskload_pd(mem_addr: *const f64, mask: __m128i) -> __m128d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskstore_pd(mem_addr: *mut f64, mask: __m128i, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskstore_pd(mem_addr: *mut f64, mask: __m128i, a: __m128d) {
     let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
@@ -1728,7 +1804,8 @@ pub unsafe fn _mm_maskstore_pd(mem_addr: *mut f64, mask: __m128i, a: __m128d) {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskload_ps(mem_addr: *const f32, mask: __m256i) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskload_ps(mem_addr: *const f32, mask: __m256i) -> __m256 {
     let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm256_setzero_ps())
 }
@@ -1741,7 +1818,8 @@ pub unsafe fn _mm256_maskload_ps(mem_addr: *const f32, mask: __m256i) -> __m256
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskstore_ps(mem_addr: *mut f32, mask: __m256i, a: __m256) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskstore_ps(mem_addr: *mut f32, mask: __m256i, a: __m256) {
     let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
@@ -1755,7 +1833,8 @@ pub unsafe fn _mm256_maskstore_ps(mem_addr: *mut f32, mask: __m256i, a: __m256)
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskload_ps(mem_addr: *const f32, mask: __m128i) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskload_ps(mem_addr: *const f32, mask: __m128i) -> __m128 {
     let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, _mm_setzero_ps())
 }
@@ -1768,7 +1847,8 @@ pub unsafe fn _mm_maskload_ps(mem_addr: *const f32, mask: __m128i) -> __m128 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmaskmovps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskstore_ps(mem_addr: *mut f32, mask: __m128i, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskstore_ps(mem_addr: *mut f32, mask: __m128i, a: __m128) {
     let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a)
 }
@@ -1781,7 +1861,8 @@ pub unsafe fn _mm_maskstore_ps(mem_addr: *mut f32, mask: __m128i, a: __m128) {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_movehdup_ps(a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movehdup_ps(a: __m256) -> __m256 {
     unsafe { simd_shuffle!(a, a, [1, 1, 3, 3, 5, 5, 7, 7]) }
 }
 
@@ -1793,7 +1874,8 @@ pub fn _mm256_movehdup_ps(a: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_moveldup_ps(a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_moveldup_ps(a: __m256) -> __m256 {
     unsafe { simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6]) }
 }
 
@@ -1805,7 +1887,8 @@ pub fn _mm256_moveldup_ps(a: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovddup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_movedup_pd(a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movedup_pd(a: __m256d) -> __m256d {
     unsafe { simd_shuffle!(a, a, [0, 0, 2, 2]) }
 }
 
@@ -1943,7 +2026,8 @@ pub fn _mm256_rsqrt_ps(a: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpackhi_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpackhi_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
 
@@ -1955,7 +2039,8 @@ pub fn _mm256_unpackhi_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpackhi_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpackhi_ps(a: __m256, b: __m256) -> __m256 {
     unsafe { simd_shuffle!(a, b, [2, 10, 3, 11, 6, 14, 7, 15]) }
 }
 
@@ -1967,7 +2052,8 @@ pub fn _mm256_unpackhi_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpacklo_pd(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpacklo_pd(a: __m256d, b: __m256d) -> __m256d {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
 
@@ -1979,7 +2065,8 @@ pub fn _mm256_unpacklo_pd(a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpacklo_ps(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpacklo_ps(a: __m256, b: __m256) -> __m256 {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 4, 12, 5, 13]) }
 }
 
@@ -1993,7 +2080,8 @@ pub fn _mm256_unpacklo_ps(a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vptest))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_testz_si256(a: __m256i, b: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_testz_si256(a: __m256i, b: __m256i) -> i32 {
     unsafe {
         let r = simd_and(a.as_i64x4(), b.as_i64x4());
         (0i64 == simd_reduce_or(r)) as i32
@@ -2010,7 +2098,8 @@ pub fn _mm256_testz_si256(a: __m256i, b: __m256i) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vptest))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_testc_si256(a: __m256i, b: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_testc_si256(a: __m256i, b: __m256i) -> i32 {
     unsafe {
         let r = simd_and(simd_xor(a.as_i64x4(), i64x4::splat(!0)), b.as_i64x4());
         (0i64 == simd_reduce_or(r)) as i32
@@ -2097,7 +2186,8 @@ pub fn _mm256_testnzc_pd(a: __m256d, b: __m256d) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vtestpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_testz_pd(a: __m128d, b: __m128d) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testz_pd(a: __m128d, b: __m128d) -> i32 {
     unsafe {
         let r: i64x2 = simd_lt(transmute(_mm_and_pd(a, b)), i64x2::ZERO);
         (0i64 == simd_reduce_or(r)) as i32
@@ -2117,7 +2207,8 @@ pub fn _mm_testz_pd(a: __m128d, b: __m128d) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vtestpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_testc_pd(a: __m128d, b: __m128d) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testc_pd(a: __m128d, b: __m128d) -> i32 {
     unsafe {
         let r: i64x2 = simd_lt(transmute(_mm_andnot_pd(a, b)), i64x2::ZERO);
         (0i64 == simd_reduce_or(r)) as i32
@@ -2207,7 +2298,8 @@ pub fn _mm256_testnzc_ps(a: __m256, b: __m256) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vtestps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_testz_ps(a: __m128, b: __m128) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testz_ps(a: __m128, b: __m128) -> i32 {
     unsafe {
         let r: i32x4 = simd_lt(transmute(_mm_and_ps(a, b)), i32x4::ZERO);
         (0i32 == simd_reduce_or(r)) as i32
@@ -2227,7 +2319,8 @@ pub fn _mm_testz_ps(a: __m128, b: __m128) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vtestps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_testc_ps(a: __m128, b: __m128) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testc_ps(a: __m128, b: __m128) -> i32 {
     unsafe {
         let r: i32x4 = simd_lt(transmute(_mm_andnot_ps(a, b)), i32x4::ZERO);
         (0i32 == simd_reduce_or(r)) as i32
@@ -2261,12 +2354,13 @@ pub fn _mm_testnzc_ps(a: __m128, b: __m128) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovmskpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_movemask_pd(a: __m256d) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movemask_pd(a: __m256d) -> i32 {
     // Propagate the highest bit to the rest, because simd_bitmask
     // requires all-1 or all-0.
     unsafe {
         let mask: i64x4 = simd_lt(transmute(a), i64x4::ZERO);
-        simd_bitmask::<i64x4, u8>(mask).into()
+        simd_bitmask::<i64x4, u8>(mask) as i32
     }
 }
 
@@ -2279,12 +2373,13 @@ pub fn _mm256_movemask_pd(a: __m256d) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vmovmskps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_movemask_ps(a: __m256) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movemask_ps(a: __m256) -> i32 {
     // Propagate the highest bit to the rest, because simd_bitmask
     // requires all-1 or all-0.
     unsafe {
         let mask: i32x8 = simd_lt(transmute(a), i32x8::ZERO);
-        simd_bitmask::<i32x8, u8>(mask).into()
+        simd_bitmask::<i32x8, u8>(mask) as i32
     }
 }
 
@@ -2295,7 +2390,8 @@ pub fn _mm256_movemask_ps(a: __m256) -> i32 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vxorp))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setzero_pd() -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setzero_pd() -> __m256d {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2306,7 +2402,8 @@ pub fn _mm256_setzero_pd() -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setzero_ps() -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setzero_ps() -> __m256 {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2317,7 +2414,8 @@ pub fn _mm256_setzero_ps() -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vxor))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setzero_si256() -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setzero_si256() -> __m256i {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2330,7 +2428,8 @@ pub fn _mm256_setzero_si256() -> __m256i {
 // This intrinsic has no corresponding instruction.
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
     _mm256_setr_pd(d, c, b, a)
 }
 
@@ -2342,7 +2441,17 @@ pub fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_ps(a: f32, b: f32, c: f32, d: f32, e: f32, f: f32, g: f32, h: f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_ps(
+    a: f32,
+    b: f32,
+    c: f32,
+    d: f32,
+    e: f32,
+    f: f32,
+    g: f32,
+    h: f32,
+) -> __m256 {
     _mm256_setr_ps(h, g, f, e, d, c, b, a)
 }
 
@@ -2353,7 +2462,8 @@ pub fn _mm256_set_ps(a: f32, b: f32, c: f32, d: f32, e: f32, f: f32, g: f32, h:
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_epi8(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_epi8(
     e00: i8,
     e01: i8,
     e02: i8,
@@ -2403,7 +2513,8 @@ pub fn _mm256_set_epi8(
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_epi16(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_epi16(
     e00: i16,
     e01: i16,
     e02: i16,
@@ -2437,7 +2548,8 @@ pub fn _mm256_set_epi16(
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_epi32(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_epi32(
     e0: i32,
     e1: i32,
     e2: i32,
@@ -2457,7 +2569,8 @@ pub fn _mm256_set_epi32(
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
     _mm256_setr_epi64x(d, c, b, a)
 }
 
@@ -2469,7 +2582,8 @@ pub fn _mm256_set_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
     __m256d([a, b, c, d])
 }
 
@@ -2481,7 +2595,17 @@ pub fn _mm256_setr_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_ps(a: f32, b: f32, c: f32, d: f32, e: f32, f: f32, g: f32, h: f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_ps(
+    a: f32,
+    b: f32,
+    c: f32,
+    d: f32,
+    e: f32,
+    f: f32,
+    g: f32,
+    h: f32,
+) -> __m256 {
     __m256([a, b, c, d, e, f, g, h])
 }
 
@@ -2493,7 +2617,8 @@ pub fn _mm256_setr_ps(a: f32, b: f32, c: f32, d: f32, e: f32, f: f32, g: f32, h:
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_epi8(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_epi8(
     e00: i8,
     e01: i8,
     e02: i8,
@@ -2546,7 +2671,8 @@ pub fn _mm256_setr_epi8(
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_epi16(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_epi16(
     e00: i16,
     e01: i16,
     e02: i16,
@@ -2583,7 +2709,8 @@ pub fn _mm256_setr_epi16(
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_epi32(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_epi32(
     e0: i32,
     e1: i32,
     e2: i32,
@@ -2604,7 +2731,8 @@ pub fn _mm256_setr_epi32(
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
     unsafe { transmute(i64x4::new(a, b, c, d)) }
 }
 
@@ -2616,7 +2744,8 @@ pub fn _mm256_setr_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set1_pd(a: f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_pd(a: f64) -> __m256d {
     _mm256_setr_pd(a, a, a, a)
 }
 
@@ -2628,7 +2757,8 @@ pub fn _mm256_set1_pd(a: f64) -> __m256d {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set1_ps(a: f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_ps(a: f32) -> __m256 {
     _mm256_setr_ps(a, a, a, a, a, a, a, a)
 }
 
@@ -2640,7 +2770,8 @@ pub fn _mm256_set1_ps(a: f32) -> __m256 {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set1_epi8(a: i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_epi8(a: i8) -> __m256i {
     #[rustfmt::skip]
     _mm256_setr_epi8(
         a, a, a, a, a, a, a, a,
@@ -2660,7 +2791,8 @@ pub fn _mm256_set1_epi8(a: i8) -> __m256i {
 #[cfg_attr(test, assert_instr(vinsertf128))]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set1_epi16(a: i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_epi16(a: i16) -> __m256i {
     _mm256_setr_epi16(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
 }
 
@@ -2672,7 +2804,8 @@ pub fn _mm256_set1_epi16(a: i16) -> __m256i {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set1_epi32(a: i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_epi32(a: i32) -> __m256i {
     _mm256_setr_epi32(a, a, a, a, a, a, a, a)
 }
 
@@ -2686,7 +2819,8 @@ pub fn _mm256_set1_epi32(a: i32) -> __m256i {
 #[cfg_attr(all(test, target_arch = "x86"), assert_instr(vbroadcastsd))]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set1_epi64x(a: i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_epi64x(a: i64) -> __m256i {
     _mm256_setr_epi64x(a, a, a, a)
 }
 
@@ -2698,7 +2832,8 @@ pub fn _mm256_set1_epi64x(a: i64) -> __m256i {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castpd_ps(a: __m256d) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castpd_ps(a: __m256d) -> __m256 {
     unsafe { transmute(a) }
 }
 
@@ -2710,7 +2845,8 @@ pub fn _mm256_castpd_ps(a: __m256d) -> __m256 {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castps_pd(a: __m256) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castps_pd(a: __m256) -> __m256d {
     unsafe { transmute(a) }
 }
 
@@ -2722,7 +2858,8 @@ pub fn _mm256_castps_pd(a: __m256) -> __m256d {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castps_si256(a: __m256) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castps_si256(a: __m256) -> __m256i {
     unsafe { transmute(a) }
 }
 
@@ -2734,7 +2871,8 @@ pub fn _mm256_castps_si256(a: __m256) -> __m256i {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castsi256_ps(a: __m256i) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castsi256_ps(a: __m256i) -> __m256 {
     unsafe { transmute(a) }
 }
 
@@ -2746,7 +2884,8 @@ pub fn _mm256_castsi256_ps(a: __m256i) -> __m256 {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castpd_si256(a: __m256d) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castpd_si256(a: __m256d) -> __m256i {
     unsafe { transmute(a) }
 }
 
@@ -2758,7 +2897,8 @@ pub fn _mm256_castpd_si256(a: __m256d) -> __m256i {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castsi256_pd(a: __m256i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castsi256_pd(a: __m256i) -> __m256d {
     unsafe { transmute(a) }
 }
 
@@ -2770,7 +2910,8 @@ pub fn _mm256_castsi256_pd(a: __m256i) -> __m256d {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castps256_ps128(a: __m256) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castps256_ps128(a: __m256) -> __m128 {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
 }
 
@@ -2782,7 +2923,8 @@ pub fn _mm256_castps256_ps128(a: __m256) -> __m128 {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castpd256_pd128(a: __m256d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castpd256_pd128(a: __m256d) -> __m128d {
     unsafe { simd_shuffle!(a, a, [0, 1]) }
 }
 
@@ -2794,7 +2936,8 @@ pub fn _mm256_castpd256_pd128(a: __m256d) -> __m128d {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castsi256_si128(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castsi256_si128(a: __m256i) -> __m128i {
     unsafe {
         let a = a.as_i64x4();
         let dst: i64x2 = simd_shuffle!(a, a, [0, 1]);
@@ -2811,7 +2954,8 @@ pub fn _mm256_castsi256_si128(a: __m256i) -> __m128i {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castps128_ps256(a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castps128_ps256(a: __m128) -> __m256 {
     unsafe { simd_shuffle!(a, _mm_undefined_ps(), [0, 1, 2, 3, 4, 4, 4, 4]) }
 }
 
@@ -2824,7 +2968,8 @@ pub fn _mm256_castps128_ps256(a: __m128) -> __m256 {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castpd128_pd256(a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castpd128_pd256(a: __m128d) -> __m256d {
     unsafe { simd_shuffle!(a, _mm_undefined_pd(), [0, 1, 2, 2]) }
 }
 
@@ -2837,7 +2982,8 @@ pub fn _mm256_castpd128_pd256(a: __m128d) -> __m256d {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_castsi128_si256(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castsi128_si256(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i64x2();
         let undefined = i64x2::ZERO;
@@ -2856,7 +3002,8 @@ pub fn _mm256_castsi128_si256(a: __m128i) -> __m256i {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_zextps128_ps256(a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_zextps128_ps256(a: __m128) -> __m256 {
     unsafe { simd_shuffle!(a, _mm_setzero_ps(), [0, 1, 2, 3, 4, 5, 6, 7]) }
 }
 
@@ -2870,7 +3017,8 @@ pub fn _mm256_zextps128_ps256(a: __m128) -> __m256 {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_zextsi128_si256(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_zextsi128_si256(a: __m128i) -> __m256i {
     unsafe {
         let b = i64x2::ZERO;
         let dst: i64x4 = simd_shuffle!(a.as_i64x2(), b, [0, 1, 2, 3]);
@@ -2889,7 +3037,8 @@ pub fn _mm256_zextsi128_si256(a: __m128i) -> __m256i {
 // This intrinsic is only used for compilation and does not generate any
 // instructions, thus it has zero latency.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_zextpd128_pd256(a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_zextpd128_pd256(a: __m128d) -> __m256d {
     unsafe { simd_shuffle!(a, _mm_setzero_pd(), [0, 1, 2, 3]) }
 }
 
@@ -2903,7 +3052,8 @@ pub fn _mm256_zextpd128_pd256(a: __m128d) -> __m256d {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_undefined_ps() -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_undefined_ps() -> __m256 {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2917,7 +3067,8 @@ pub fn _mm256_undefined_ps() -> __m256 {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_undefined_pd() -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_undefined_pd() -> __m256d {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2931,7 +3082,8 @@ pub fn _mm256_undefined_pd() -> __m256d {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_undefined_si256() -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_undefined_si256() -> __m256i {
     const { unsafe { mem::zeroed() } }
 }
 
@@ -2942,7 +3094,8 @@ pub fn _mm256_undefined_si256() -> __m256i {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_m128(hi: __m128, lo: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_m128(hi: __m128, lo: __m128) -> __m256 {
     unsafe { simd_shuffle!(lo, hi, [0, 1, 2, 3, 4, 5, 6, 7]) }
 }
 
@@ -2953,7 +3106,8 @@ pub fn _mm256_set_m128(hi: __m128, lo: __m128) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_m128d(hi: __m128d, lo: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_m128d(hi: __m128d, lo: __m128d) -> __m256d {
     unsafe {
         let hi: __m128 = transmute(hi);
         let lo: __m128 = transmute(lo);
@@ -2968,7 +3122,8 @@ pub fn _mm256_set_m128d(hi: __m128d, lo: __m128d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_set_m128i(hi: __m128i, lo: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_m128i(hi: __m128i, lo: __m128i) -> __m256i {
     unsafe {
         let hi: __m128 = transmute(hi);
         let lo: __m128 = transmute(lo);
@@ -2983,7 +3138,8 @@ pub fn _mm256_set_m128i(hi: __m128i, lo: __m128i) -> __m256i {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_m128(lo: __m128, hi: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_m128(lo: __m128, hi: __m128) -> __m256 {
     _mm256_set_m128(hi, lo)
 }
 
@@ -2994,7 +3150,8 @@ pub fn _mm256_setr_m128(lo: __m128, hi: __m128) -> __m256 {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_m128d(lo: __m128d, hi: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_m128d(lo: __m128d, hi: __m128d) -> __m256d {
     _mm256_set_m128d(hi, lo)
 }
 
@@ -3005,7 +3162,8 @@ pub fn _mm256_setr_m128d(lo: __m128d, hi: __m128d) -> __m256d {
 #[target_feature(enable = "avx")]
 #[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_setr_m128i(lo: __m128i, hi: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_m128i(lo: __m128i, hi: __m128i) -> __m256i {
     _mm256_set_m128i(hi, lo)
 }
 
@@ -3019,7 +3177,8 @@ pub fn _mm256_setr_m128i(lo: __m128i, hi: __m128i) -> __m256i {
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_loadu2_m128(hiaddr: *const f32, loaddr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu2_m128(hiaddr: *const f32, loaddr: *const f32) -> __m256 {
     let a = _mm256_castps128_ps256(_mm_loadu_ps(loaddr));
     _mm256_insertf128_ps::<1>(a, _mm_loadu_ps(hiaddr))
 }
@@ -3034,7 +3193,8 @@ pub unsafe fn _mm256_loadu2_m128(hiaddr: *const f32, loaddr: *const f32) -> __m2
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_loadu2_m128d(hiaddr: *const f64, loaddr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu2_m128d(hiaddr: *const f64, loaddr: *const f64) -> __m256d {
     let a = _mm256_castpd128_pd256(_mm_loadu_pd(loaddr));
     _mm256_insertf128_pd::<1>(a, _mm_loadu_pd(hiaddr))
 }
@@ -3048,7 +3208,8 @@ pub unsafe fn _mm256_loadu2_m128d(hiaddr: *const f64, loaddr: *const f64) -> __m
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_loadu2_m128i(hiaddr: *const __m128i, loaddr: *const __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu2_m128i(hiaddr: *const __m128i, loaddr: *const __m128i) -> __m256i {
     let a = _mm256_castsi128_si256(_mm_loadu_si128(loaddr));
     _mm256_insertf128_si256::<1>(a, _mm_loadu_si128(hiaddr))
 }
@@ -3063,7 +3224,8 @@ pub unsafe fn _mm256_loadu2_m128i(hiaddr: *const __m128i, loaddr: *const __m128i
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_storeu2_m128(hiaddr: *mut f32, loaddr: *mut f32, a: __m256) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu2_m128(hiaddr: *mut f32, loaddr: *mut f32, a: __m256) {
     let lo = _mm256_castps256_ps128(a);
     _mm_storeu_ps(loaddr, lo);
     let hi = _mm256_extractf128_ps::<1>(a);
@@ -3080,7 +3242,8 @@ pub unsafe fn _mm256_storeu2_m128(hiaddr: *mut f32, loaddr: *mut f32, a: __m256)
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_storeu2_m128d(hiaddr: *mut f64, loaddr: *mut f64, a: __m256d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu2_m128d(hiaddr: *mut f64, loaddr: *mut f64, a: __m256d) {
     let lo = _mm256_castpd256_pd128(a);
     _mm_storeu_pd(loaddr, lo);
     let hi = _mm256_extractf128_pd::<1>(a);
@@ -3096,7 +3259,8 @@ pub unsafe fn _mm256_storeu2_m128d(hiaddr: *mut f64, loaddr: *mut f64, a: __m256
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_storeu2_m128i(hiaddr: *mut __m128i, loaddr: *mut __m128i, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu2_m128i(hiaddr: *mut __m128i, loaddr: *mut __m128i, a: __m256i) {
     let lo = _mm256_castsi256_si128(a);
     _mm_storeu_si128(loaddr, lo);
     let hi = _mm256_extractf128_si256::<1>(a);
@@ -3110,7 +3274,8 @@ pub unsafe fn _mm256_storeu2_m128i(hiaddr: *mut __m128i, loaddr: *mut __m128i, a
 #[target_feature(enable = "avx")]
 //#[cfg_attr(test, assert_instr(movss))] FIXME
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtss_f32(a: __m256) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtss_f32(a: __m256) -> f32 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -3191,6 +3356,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use crate::hint::black_box;
     use crate::ptr;
     use stdarch_test::simd_test;
@@ -3198,7 +3364,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_add_pd() {
+    const unsafe fn test_mm256_add_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_add_pd(a, b);
@@ -3207,7 +3373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_add_ps() {
+    const unsafe fn test_mm256_add_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_add_ps(a, b);
@@ -3216,7 +3382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_and_pd() {
+    const unsafe fn test_mm256_and_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(0.6);
         let r = _mm256_and_pd(a, b);
@@ -3225,7 +3391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_and_ps() {
+    const unsafe fn test_mm256_and_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(0.6);
         let r = _mm256_and_ps(a, b);
@@ -3234,7 +3400,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_or_pd() {
+    const unsafe fn test_mm256_or_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(0.6);
         let r = _mm256_or_pd(a, b);
@@ -3243,7 +3409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_or_ps() {
+    const unsafe fn test_mm256_or_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(0.6);
         let r = _mm256_or_ps(a, b);
@@ -3252,7 +3418,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_shuffle_pd() {
+    const unsafe fn test_mm256_shuffle_pd() {
         let a = _mm256_setr_pd(1., 4., 5., 8.);
         let b = _mm256_setr_pd(2., 3., 6., 7.);
         let r = _mm256_shuffle_pd::<0b11_11_11_11>(a, b);
@@ -3261,7 +3427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_shuffle_ps() {
+    const unsafe fn test_mm256_shuffle_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_shuffle_ps::<0b00_00_11_11>(a, b);
@@ -3270,7 +3436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_andnot_pd() {
+    const unsafe fn test_mm256_andnot_pd() {
         let a = _mm256_set1_pd(0.);
         let b = _mm256_set1_pd(0.6);
         let r = _mm256_andnot_pd(a, b);
@@ -3278,7 +3444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_andnot_ps() {
+    const unsafe fn test_mm256_andnot_ps() {
         let a = _mm256_set1_ps(0.);
         let b = _mm256_set1_ps(0.6);
         let r = _mm256_andnot_ps(a, b);
@@ -3390,7 +3556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_mul_pd() {
+    const unsafe fn test_mm256_mul_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_mul_pd(a, b);
@@ -3399,7 +3565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_mul_ps() {
+    const unsafe fn test_mm256_mul_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_mul_ps(a, b);
@@ -3408,7 +3574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_addsub_pd() {
+    const unsafe fn test_mm256_addsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_addsub_pd(a, b);
@@ -3417,7 +3583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_addsub_ps() {
+    const unsafe fn test_mm256_addsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
         let r = _mm256_addsub_ps(a, b);
@@ -3426,7 +3592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_sub_pd() {
+    const unsafe fn test_mm256_sub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_sub_pd(a, b);
@@ -3435,7 +3601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_sub_ps() {
+    const unsafe fn test_mm256_sub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., -1., -2., -3., -4.);
         let b = _mm256_setr_ps(5., 6., 7., 8., 3., 2., 1., 0.);
         let r = _mm256_sub_ps(a, b);
@@ -3458,7 +3624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_floor_pd() {
+    const unsafe fn test_mm256_floor_pd() {
         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
         let result_down = _mm256_floor_pd(a);
         let expected_down = _mm256_setr_pd(1., 2., 3., -2.);
@@ -3466,7 +3632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_ceil_pd() {
+    const unsafe fn test_mm256_ceil_pd() {
         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
         let result_up = _mm256_ceil_pd(a);
         let expected_up = _mm256_setr_pd(2., 3., 4., -1.);
@@ -3488,7 +3654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_floor_ps() {
+    const unsafe fn test_mm256_floor_ps() {
         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
         let result_down = _mm256_floor_ps(a);
         let expected_down = _mm256_setr_ps(1., 2., 3., -2., 1., 2., 3., -2.);
@@ -3496,7 +3662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_ceil_ps() {
+    const unsafe fn test_mm256_ceil_ps() {
         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
         let result_up = _mm256_ceil_ps(a);
         let expected_up = _mm256_setr_ps(2., 3., 4., -1., 2., 3., 4., -1.);
@@ -3520,7 +3686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_div_ps() {
+    const unsafe fn test_mm256_div_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_div_ps(a, b);
@@ -3529,7 +3695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_div_pd() {
+    const unsafe fn test_mm256_div_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_div_pd(a, b);
@@ -3538,7 +3704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_blend_pd() {
+    const unsafe fn test_mm256_blend_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_blend_pd::<0x0>(a, b);
@@ -3550,7 +3716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_blend_ps() {
+    const unsafe fn test_mm256_blend_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_blend_ps::<0x0>(a, b);
@@ -3562,7 +3728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_blendv_pd() {
+    const unsafe fn test_mm256_blendv_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let c = _mm256_setr_pd(0., 0., !0 as f64, !0 as f64);
@@ -3572,7 +3738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_blendv_ps() {
+    const unsafe fn test_mm256_blendv_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         #[rustfmt::skip]
@@ -3594,7 +3760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_hadd_pd() {
+    const unsafe fn test_mm256_hadd_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_hadd_pd(a, b);
@@ -3609,7 +3775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_hadd_ps() {
+    const unsafe fn test_mm256_hadd_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_hadd_ps(a, b);
@@ -3624,7 +3790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_hsub_pd() {
+    const unsafe fn test_mm256_hsub_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_hsub_pd(a, b);
@@ -3639,7 +3805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_hsub_ps() {
+    const unsafe fn test_mm256_hsub_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_hsub_ps(a, b);
@@ -3654,7 +3820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_xor_pd() {
+    const unsafe fn test_mm256_xor_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_set1_pd(0.);
         let r = _mm256_xor_pd(a, b);
@@ -3662,7 +3828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_xor_ps() {
+    const unsafe fn test_mm256_xor_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_set1_ps(0.);
         let r = _mm256_xor_ps(a, b);
@@ -3728,7 +3894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtepi32_pd() {
+    const unsafe fn test_mm256_cvtepi32_pd() {
         let a = _mm_setr_epi32(4, 9, 16, 25);
         let r = _mm256_cvtepi32_pd(a);
         let e = _mm256_setr_pd(4., 9., 16., 25.);
@@ -3736,7 +3902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtepi32_ps() {
+    const unsafe fn test_mm256_cvtepi32_ps() {
         let a = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
         let r = _mm256_cvtepi32_ps(a);
         let e = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
@@ -3744,7 +3910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtpd_ps() {
+    const unsafe fn test_mm256_cvtpd_ps() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let r = _mm256_cvtpd_ps(a);
         let e = _mm_setr_ps(4., 9., 16., 25.);
@@ -3760,7 +3926,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtps_pd() {
+    const unsafe fn test_mm256_cvtps_pd() {
         let a = _mm_setr_ps(4., 9., 16., 25.);
         let r = _mm256_cvtps_pd(a);
         let e = _mm256_setr_pd(4., 9., 16., 25.);
@@ -3768,7 +3934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtsd_f64() {
+    const unsafe fn test_mm256_cvtsd_f64() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_cvtsd_f64(a);
         assert_eq!(r, 1.);
@@ -3799,7 +3965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_extractf128_ps() {
+    const unsafe fn test_mm256_extractf128_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_extractf128_ps::<0>(a);
         let e = _mm_setr_ps(4., 3., 2., 5.);
@@ -3807,7 +3973,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_extractf128_pd() {
+    const unsafe fn test_mm256_extractf128_pd() {
         let a = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_extractf128_pd::<0>(a);
         let e = _mm_setr_pd(4., 3.);
@@ -3815,7 +3981,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_extractf128_si256() {
+    const unsafe fn test_mm256_extractf128_si256() {
         let a = _mm256_setr_epi64x(4, 3, 2, 5);
         let r = _mm256_extractf128_si256::<0>(a);
         let e = _mm_setr_epi64x(4, 3);
@@ -3823,7 +3989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_extract_epi32() {
+    const unsafe fn test_mm256_extract_epi32() {
         let a = _mm256_setr_epi32(-1, 1, 2, 3, 4, 5, 6, 7);
         let r1 = _mm256_extract_epi32::<0>(a);
         let r2 = _mm256_extract_epi32::<3>(a);
@@ -3832,7 +3998,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtsi256_si32() {
+    const unsafe fn test_mm256_cvtsi256_si32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_cvtsi256_si32(a);
         assert_eq!(r, 1);
@@ -3869,7 +4035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permute_ps() {
+    const unsafe fn test_mm256_permute_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_permute_ps::<0x1b>(a);
         let e = _mm256_setr_ps(5., 2., 3., 4., 50., 64., 9., 8.);
@@ -3877,7 +4043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_permute_ps() {
+    const unsafe fn test_mm_permute_ps() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let r = _mm_permute_ps::<0x1b>(a);
         let e = _mm_setr_ps(5., 2., 3., 4.);
@@ -3903,7 +4069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permute_pd() {
+    const unsafe fn test_mm256_permute_pd() {
         let a = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_permute_pd::<5>(a);
         let e = _mm256_setr_pd(3., 4., 5., 2.);
@@ -3911,7 +4077,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_permute_pd() {
+    const unsafe fn test_mm_permute_pd() {
         let a = _mm_setr_pd(4., 3.);
         let r = _mm_permute_pd::<1>(a);
         let e = _mm_setr_pd(3., 4.);
@@ -3919,7 +4085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permute2f128_ps() {
+    const unsafe fn test_mm256_permute2f128_ps() {
         let a = _mm256_setr_ps(11., 12., 13., 14., 15., 16., 17., 18.);
         let b = _mm256_setr_ps(21., 22., 23., 24., 25., 26., 27., 28.);
         let r = _mm256_permute2f128_ps::<0b0001_0011>(a, b);
@@ -3933,7 +4099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permute2f128_pd() {
+    const unsafe fn test_mm256_permute2f128_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_permute2f128_pd::<0b0011_0001>(a, b);
@@ -3947,7 +4113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permute2f128_si256() {
+    const unsafe fn test_mm256_permute2f128_si256() {
         let a = _mm256_setr_epi32(11, 12, 13, 14, 15, 16, 17, 18);
         let b = _mm256_setr_epi32(21, 22, 23, 24, 25, 26, 27, 28);
         let r = _mm256_permute2f128_si256::<0b0010_0000>(a, b);
@@ -3961,28 +4127,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_broadcast_ss() {
+    const unsafe fn test_mm256_broadcast_ss() {
         let r = _mm256_broadcast_ss(&3.);
         let e = _mm256_set1_ps(3.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_broadcast_ss() {
+    const unsafe fn test_mm_broadcast_ss() {
         let r = _mm_broadcast_ss(&3.);
         let e = _mm_set1_ps(3.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_broadcast_sd() {
+    const unsafe fn test_mm256_broadcast_sd() {
         let r = _mm256_broadcast_sd(&3.);
         let e = _mm256_set1_pd(3.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_broadcast_ps() {
+    const unsafe fn test_mm256_broadcast_ps() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let r = _mm256_broadcast_ps(&a);
         let e = _mm256_setr_ps(4., 3., 2., 5., 4., 3., 2., 5.);
@@ -3990,7 +4156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_broadcast_pd() {
+    const unsafe fn test_mm256_broadcast_pd() {
         let a = _mm_setr_pd(4., 3.);
         let r = _mm256_broadcast_pd(&a);
         let e = _mm256_setr_pd(4., 3., 4., 3.);
@@ -3998,7 +4164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insertf128_ps() {
+    const unsafe fn test_mm256_insertf128_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let b = _mm_setr_ps(4., 9., 16., 25.);
         let r = _mm256_insertf128_ps::<0>(a, b);
@@ -4007,7 +4173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insertf128_pd() {
+    const unsafe fn test_mm256_insertf128_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm256_insertf128_pd::<0>(a, b);
@@ -4016,7 +4182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insertf128_si256() {
+    const unsafe fn test_mm256_insertf128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm_setr_epi64x(5, 6);
         let r = _mm256_insertf128_si256::<0>(a, b);
@@ -4025,7 +4191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insert_epi8() {
+    const unsafe fn test_mm256_insert_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4045,7 +4211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insert_epi16() {
+    const unsafe fn test_mm256_insert_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4061,7 +4227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insert_epi32() {
+    const unsafe fn test_mm256_insert_epi32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_insert_epi32::<7>(a, 0);
         let e = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
@@ -4069,7 +4235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_load_pd() {
+    const unsafe fn test_mm256_load_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let p = ptr::addr_of!(a) as *const f64;
         let r = _mm256_load_pd(p);
@@ -4078,7 +4244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_store_pd() {
+    const unsafe fn test_mm256_store_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut r = _mm256_undefined_pd();
         _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a);
@@ -4086,7 +4252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_load_ps() {
+    const unsafe fn test_mm256_load_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let p = ptr::addr_of!(a) as *const f32;
         let r = _mm256_load_ps(p);
@@ -4095,7 +4261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_store_ps() {
+    const unsafe fn test_mm256_store_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let mut r = _mm256_undefined_ps();
         _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a);
@@ -4103,7 +4269,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_loadu_pd() {
+    const unsafe fn test_mm256_loadu_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let r = _mm256_loadu_pd(black_box(p));
@@ -4112,7 +4278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_storeu_pd() {
+    const unsafe fn test_mm256_storeu_pd() {
         let a = _mm256_set1_pd(9.);
         let mut r = _mm256_undefined_pd();
         _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a);
@@ -4120,7 +4286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_loadu_ps() {
+    const unsafe fn test_mm256_loadu_ps() {
         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
         let p = a.as_ptr();
         let r = _mm256_loadu_ps(black_box(p));
@@ -4129,7 +4295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_storeu_ps() {
+    const unsafe fn test_mm256_storeu_ps() {
         let a = _mm256_set1_ps(9.);
         let mut r = _mm256_undefined_ps();
         _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a);
@@ -4137,7 +4303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_load_si256() {
+    const unsafe fn test_mm256_load_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let p = ptr::addr_of!(a);
         let r = _mm256_load_si256(p);
@@ -4146,7 +4312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_store_si256() {
+    const unsafe fn test_mm256_store_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = _mm256_undefined_si256();
         _mm256_store_si256(ptr::addr_of_mut!(r), a);
@@ -4154,7 +4320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_loadu_si256() {
+    const unsafe fn test_mm256_loadu_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let p = ptr::addr_of!(a);
         let r = _mm256_loadu_si256(black_box(p));
@@ -4163,7 +4329,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_storeu_si256() {
+    const unsafe fn test_mm256_storeu_si256() {
         let a = _mm256_set1_epi8(9);
         let mut r = _mm256_undefined_si256();
         _mm256_storeu_si256(ptr::addr_of_mut!(r), a);
@@ -4171,7 +4337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_maskload_pd() {
+    const unsafe fn test_mm256_maskload_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
@@ -4181,7 +4347,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_maskstore_pd() {
+    const unsafe fn test_mm256_maskstore_pd() {
         let mut r = _mm256_set1_pd(0.);
         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
         let a = _mm256_setr_pd(1., 2., 3., 4.);
@@ -4191,7 +4357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_maskload_pd() {
+    const unsafe fn test_mm_maskload_pd() {
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let mask = _mm_setr_epi64x(0, !0);
@@ -4201,7 +4367,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_maskstore_pd() {
+    const unsafe fn test_mm_maskstore_pd() {
         let mut r = _mm_set1_pd(0.);
         let mask = _mm_setr_epi64x(0, !0);
         let a = _mm_setr_pd(1., 2.);
@@ -4211,7 +4377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_maskload_ps() {
+    const unsafe fn test_mm256_maskload_ps() {
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
@@ -4221,7 +4387,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_maskstore_ps() {
+    const unsafe fn test_mm256_maskstore_ps() {
         let mut r = _mm256_set1_ps(0.);
         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -4231,7 +4397,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_maskload_ps() {
+    const unsafe fn test_mm_maskload_ps() {
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let mask = _mm_setr_epi32(0, !0, 0, !0);
@@ -4241,7 +4407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_maskstore_ps() {
+    const unsafe fn test_mm_maskstore_ps() {
         let mut r = _mm_set1_ps(0.);
         let mask = _mm_setr_epi32(0, !0, 0, !0);
         let a = _mm_setr_ps(1., 2., 3., 4.);
@@ -4251,7 +4417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_movehdup_ps() {
+    const unsafe fn test_mm256_movehdup_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_movehdup_ps(a);
         let e = _mm256_setr_ps(2., 2., 4., 4., 6., 6., 8., 8.);
@@ -4259,7 +4425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_moveldup_ps() {
+    const unsafe fn test_mm256_moveldup_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_moveldup_ps(a);
         let e = _mm256_setr_ps(1., 1., 3., 3., 5., 5., 7., 7.);
@@ -4267,7 +4433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_movedup_pd() {
+    const unsafe fn test_mm256_movedup_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_movedup_pd(a);
         let e = _mm256_setr_pd(1., 1., 3., 3.);
@@ -4370,7 +4536,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_unpackhi_pd() {
+    const unsafe fn test_mm256_unpackhi_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_unpackhi_pd(a, b);
@@ -4379,7 +4545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_unpackhi_ps() {
+    const unsafe fn test_mm256_unpackhi_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_unpackhi_ps(a, b);
@@ -4388,7 +4554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_unpacklo_pd() {
+    const unsafe fn test_mm256_unpacklo_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_unpacklo_pd(a, b);
@@ -4397,7 +4563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_unpacklo_ps() {
+    const unsafe fn test_mm256_unpacklo_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_unpacklo_ps(a, b);
@@ -4406,7 +4572,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testz_si256() {
+    const unsafe fn test_mm256_testz_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm256_setr_epi64x(5, 6, 7, 8);
         let r = _mm256_testz_si256(a, b);
@@ -4417,7 +4583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testc_si256() {
+    const unsafe fn test_mm256_testc_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm256_setr_epi64x(5, 6, 7, 8);
         let r = _mm256_testc_si256(a, b);
@@ -4475,7 +4641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_testz_pd() {
+    const unsafe fn test_mm_testz_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm_testz_pd(a, b);
@@ -4486,7 +4652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_testc_pd() {
+    const unsafe fn test_mm_testc_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm_testc_pd(a, b);
@@ -4541,7 +4707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_testz_ps() {
+    const unsafe fn test_mm_testz_ps() {
         let a = _mm_set1_ps(1.);
         let r = _mm_testz_ps(a, a);
         assert_eq!(r, 1);
@@ -4551,7 +4717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_testc_ps() {
+    const unsafe fn test_mm_testc_ps() {
         let a = _mm_set1_ps(1.);
         let r = _mm_testc_ps(a, a);
         assert_eq!(r, 1);
@@ -4572,51 +4738,51 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_movemask_pd() {
+    const unsafe fn test_mm256_movemask_pd() {
         let a = _mm256_setr_pd(1., -2., 3., -4.);
         let r = _mm256_movemask_pd(a);
         assert_eq!(r, 0xA);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_movemask_ps() {
+    const unsafe fn test_mm256_movemask_ps() {
         let a = _mm256_setr_ps(1., -2., 3., -4., 1., -2., 3., -4.);
         let r = _mm256_movemask_ps(a);
         assert_eq!(r, 0xAA);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setzero_pd() {
+    const unsafe fn test_mm256_setzero_pd() {
         let r = _mm256_setzero_pd();
         assert_eq_m256d(r, _mm256_set1_pd(0.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setzero_ps() {
+    const unsafe fn test_mm256_setzero_ps() {
         let r = _mm256_setzero_ps();
         assert_eq_m256(r, _mm256_set1_ps(0.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setzero_si256() {
+    const unsafe fn test_mm256_setzero_si256() {
         let r = _mm256_setzero_si256();
         assert_eq_m256i(r, _mm256_set1_epi8(0));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_pd() {
+    const unsafe fn test_mm256_set_pd() {
         let r = _mm256_set_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, _mm256_setr_pd(4., 3., 2., 1.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_ps() {
+    const unsafe fn test_mm256_set_ps() {
         let r = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         assert_eq_m256(r, _mm256_setr_ps(8., 7., 6., 5., 4., 3., 2., 1.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_epi8() {
+    const unsafe fn test_mm256_set_epi8() {
         #[rustfmt::skip]
         let r = _mm256_set_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4635,7 +4801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_epi16() {
+    const unsafe fn test_mm256_set_epi16() {
         #[rustfmt::skip]
         let r = _mm256_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4650,31 +4816,31 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_epi32() {
+    const unsafe fn test_mm256_set_epi32() {
         let r = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         assert_eq_m256i(r, _mm256_setr_epi32(8, 7, 6, 5, 4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_epi64x() {
+    const unsafe fn test_mm256_set_epi64x() {
         let r = _mm256_set_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, _mm256_setr_epi64x(4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_pd() {
+    const unsafe fn test_mm256_setr_pd() {
         let r = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, _mm256_setr_pd(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_ps() {
+    const unsafe fn test_mm256_setr_ps() {
         let r = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         assert_eq_m256(r, _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_epi8() {
+    const unsafe fn test_mm256_setr_epi8() {
         #[rustfmt::skip]
         let r = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4694,7 +4860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_epi16() {
+    const unsafe fn test_mm256_setr_epi16() {
         #[rustfmt::skip]
         let r = _mm256_setr_epi16(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4709,55 +4875,55 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_epi32() {
+    const unsafe fn test_mm256_setr_epi32() {
         let r = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         assert_eq_m256i(r, _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_epi64x() {
+    const unsafe fn test_mm256_setr_epi64x() {
         let r = _mm256_setr_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, _mm256_setr_epi64x(1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set1_pd() {
+    const unsafe fn test_mm256_set1_pd() {
         let r = _mm256_set1_pd(1.);
         assert_eq_m256d(r, _mm256_set1_pd(1.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set1_ps() {
+    const unsafe fn test_mm256_set1_ps() {
         let r = _mm256_set1_ps(1.);
         assert_eq_m256(r, _mm256_set1_ps(1.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set1_epi8() {
+    const unsafe fn test_mm256_set1_epi8() {
         let r = _mm256_set1_epi8(1);
         assert_eq_m256i(r, _mm256_set1_epi8(1));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set1_epi16() {
+    const unsafe fn test_mm256_set1_epi16() {
         let r = _mm256_set1_epi16(1);
         assert_eq_m256i(r, _mm256_set1_epi16(1));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set1_epi32() {
+    const unsafe fn test_mm256_set1_epi32() {
         let r = _mm256_set1_epi32(1);
         assert_eq_m256i(r, _mm256_set1_epi32(1));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set1_epi64x() {
+    const unsafe fn test_mm256_set1_epi64x() {
         let r = _mm256_set1_epi64x(1);
         assert_eq_m256i(r, _mm256_set1_epi64x(1));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castpd_ps() {
+    const unsafe fn test_mm256_castpd_ps() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_castpd_ps(a);
         let e = _mm256_setr_ps(0., 1.875, 0., 2., 0., 2.125, 0., 2.25);
@@ -4765,7 +4931,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castps_pd() {
+    const unsafe fn test_mm256_castps_pd() {
         let a = _mm256_setr_ps(0., 1.875, 0., 2., 0., 2.125, 0., 2.25);
         let r = _mm256_castps_pd(a);
         let e = _mm256_setr_pd(1., 2., 3., 4.);
@@ -4773,7 +4939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castps_si256() {
+    const unsafe fn test_mm256_castps_si256() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_castps_si256(a);
         #[rustfmt::skip]
@@ -4787,7 +4953,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castsi256_ps() {
+    const unsafe fn test_mm256_castsi256_ps() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 0, -128, 63, 0, 0, 0, 64,
@@ -4801,63 +4967,63 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castpd_si256() {
+    const unsafe fn test_mm256_castpd_si256() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_castpd_si256(a);
         assert_eq_m256d(transmute(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castsi256_pd() {
+    const unsafe fn test_mm256_castsi256_pd() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_castsi256_pd(a);
         assert_eq_m256d(r, transmute(a));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castps256_ps128() {
+    const unsafe fn test_mm256_castps256_ps128() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_castps256_ps128(a);
         assert_eq_m128(r, _mm_setr_ps(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castpd256_pd128() {
+    const unsafe fn test_mm256_castpd256_pd128() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_castpd256_pd128(a);
         assert_eq_m128d(r, _mm_setr_pd(1., 2.));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castsi256_si128() {
+    const unsafe fn test_mm256_castsi256_si128() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_castsi256_si128(a);
         assert_eq_m128i(r, _mm_setr_epi64x(1, 2));
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castps128_ps256() {
+    const unsafe fn test_mm256_castps128_ps256() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let r = _mm256_castps128_ps256(a);
         assert_eq_m128(_mm256_castps256_ps128(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castpd128_pd256() {
+    const unsafe fn test_mm256_castpd128_pd256() {
         let a = _mm_setr_pd(1., 2.);
         let r = _mm256_castpd128_pd256(a);
         assert_eq_m128d(_mm256_castpd256_pd128(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_castsi128_si256() {
+    const unsafe fn test_mm256_castsi128_si256() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let r = _mm256_castsi128_si256(a);
         assert_eq_m128i(_mm256_castsi256_si128(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_zextps128_ps256() {
+    const unsafe fn test_mm256_zextps128_ps256() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let r = _mm256_zextps128_ps256(a);
         let e = _mm256_setr_ps(1., 2., 3., 4., 0., 0., 0., 0.);
@@ -4865,7 +5031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_zextsi128_si256() {
+    const unsafe fn test_mm256_zextsi128_si256() {
         let a = _mm_setr_epi64x(1, 2);
         let r = _mm256_zextsi128_si256(a);
         let e = _mm256_setr_epi64x(1, 2, 0, 0);
@@ -4873,7 +5039,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_zextpd128_pd256() {
+    const unsafe fn test_mm256_zextpd128_pd256() {
         let a = _mm_setr_pd(1., 2.);
         let r = _mm256_zextpd128_pd256(a);
         let e = _mm256_setr_pd(1., 2., 0., 0.);
@@ -4881,7 +5047,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_m128() {
+    const unsafe fn test_mm256_set_m128() {
         let hi = _mm_setr_ps(5., 6., 7., 8.);
         let lo = _mm_setr_ps(1., 2., 3., 4.);
         let r = _mm256_set_m128(hi, lo);
@@ -4890,7 +5056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_m128d() {
+    const unsafe fn test_mm256_set_m128d() {
         let hi = _mm_setr_pd(3., 4.);
         let lo = _mm_setr_pd(1., 2.);
         let r = _mm256_set_m128d(hi, lo);
@@ -4899,7 +5065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_set_m128i() {
+    const unsafe fn test_mm256_set_m128i() {
         #[rustfmt::skip]
         let hi = _mm_setr_epi8(
             17, 18, 19, 20,
@@ -4926,7 +5092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_m128() {
+    const unsafe fn test_mm256_setr_m128() {
         let lo = _mm_setr_ps(1., 2., 3., 4.);
         let hi = _mm_setr_ps(5., 6., 7., 8.);
         let r = _mm256_setr_m128(lo, hi);
@@ -4935,7 +5101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_m128d() {
+    const unsafe fn test_mm256_setr_m128d() {
         let lo = _mm_setr_pd(1., 2.);
         let hi = _mm_setr_pd(3., 4.);
         let r = _mm256_setr_m128d(lo, hi);
@@ -4944,7 +5110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_setr_m128i() {
+    const unsafe fn test_mm256_setr_m128i() {
         #[rustfmt::skip]
         let lo = _mm_setr_epi8(
             1, 2, 3, 4,
@@ -4969,7 +5135,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_loadu2_m128() {
+    const unsafe fn test_mm256_loadu2_m128() {
         let hi = &[5., 6., 7., 8.];
         let hiaddr = hi.as_ptr();
         let lo = &[1., 2., 3., 4.];
@@ -4980,7 +5146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_loadu2_m128d() {
+    const unsafe fn test_mm256_loadu2_m128d() {
         let hi = &[3., 4.];
         let hiaddr = hi.as_ptr();
         let lo = &[1., 2.];
@@ -4991,7 +5157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_loadu2_m128i() {
+    const unsafe fn test_mm256_loadu2_m128i() {
         #[rustfmt::skip]
         let hi = _mm_setr_epi8(
             17, 18, 19, 20, 21, 22, 23, 24,
@@ -5014,7 +5180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_storeu2_m128() {
+    const unsafe fn test_mm256_storeu2_m128() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let mut hi = _mm_undefined_ps();
         let mut lo = _mm_undefined_ps();
@@ -5028,7 +5194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_storeu2_m128d() {
+    const unsafe fn test_mm256_storeu2_m128d() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut hi = _mm_undefined_pd();
         let mut lo = _mm_undefined_pd();
@@ -5042,7 +5208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_storeu2_m128i() {
+    const unsafe fn test_mm256_storeu2_m128i() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5069,7 +5235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtss_f32() {
+    const unsafe fn test_mm256_cvtss_f32() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_cvtss_f32(a);
         assert_eq!(r, 1.);
diff --git a/crates/core_arch/src/x86_64/avx.rs b/crates/core_arch/src/x86_64/avx.rs
index b494385e4a..bb8d256207 100644
--- a/crates/core_arch/src/x86_64/avx.rs
+++ b/crates/core_arch/src/x86_64/avx.rs
@@ -24,7 +24,8 @@ use crate::{core_arch::x86::*, mem::transmute};
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, i: i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, i: i64) -> __m256i {
     static_assert_uimm_bits!(INDEX, 2);
     unsafe { transmute(simd_insert!(a.as_i64x4(), INDEX as u32, i)) }
 }
@@ -37,19 +38,21 @@ pub fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, i: i64) -> __m256i {
 #[rustc_legacy_const_generics(1)]
 // This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extract_epi64<const INDEX: i32>(a: __m256i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extract_epi64<const INDEX: i32>(a: __m256i) -> i64 {
     static_assert_uimm_bits!(INDEX, 2);
     unsafe { simd_extract!(a.as_i64x4(), INDEX as u32) }
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::arch::x86_64::*;
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_insert_epi64() {
+    const unsafe fn test_mm256_insert_epi64() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_insert_epi64::<3>(a, 0);
         let e = _mm256_setr_epi64x(1, 2, 3, 0);
@@ -57,7 +60,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_extract_epi64() {
+    const unsafe fn test_mm256_extract_epi64() {
         let a = _mm256_setr_epi64x(0, 1, 2, 3);
         let r = _mm256_extract_epi64::<3>(a);
         assert_eq!(r, 3);

From 524c42a942d9afb113fa676101c637c2daa88152 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:13:18 +0530
Subject: [PATCH 059/326] Make `avx2` functions const

---
 crates/core_arch/src/x86/avx2.rs | 661 +++++++++++++++++++------------
 1 file changed, 399 insertions(+), 262 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 3734915b70..b3b2accd73 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -31,7 +31,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpabsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_abs_epi32(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_abs_epi32(a: __m256i) -> __m256i {
     unsafe {
         let a = a.as_i32x8();
         let r = simd_select::<m32x8, _>(simd_lt(a, i32x8::ZERO), simd_neg(a), a);
@@ -46,7 +47,8 @@ pub fn _mm256_abs_epi32(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpabsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_abs_epi16(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_abs_epi16(a: __m256i) -> __m256i {
     unsafe {
         let a = a.as_i16x16();
         let r = simd_select::<m16x16, _>(simd_lt(a, i16x16::ZERO), simd_neg(a), a);
@@ -61,7 +63,8 @@ pub fn _mm256_abs_epi16(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpabsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_abs_epi8(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_abs_epi8(a: __m256i) -> __m256i {
     unsafe {
         let a = a.as_i8x32();
         let r = simd_select::<m8x32, _>(simd_lt(a, i8x32::ZERO), simd_neg(a), a);
@@ -76,7 +79,8 @@ pub fn _mm256_abs_epi8(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_add_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_add(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -87,7 +91,8 @@ pub fn _mm256_add_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_add_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_add(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -98,7 +103,8 @@ pub fn _mm256_add_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_add_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_add(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -109,7 +115,8 @@ pub fn _mm256_add_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_add_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_add(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -120,7 +127,8 @@ pub fn _mm256_add_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_adds_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_adds_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_add(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -131,7 +139,8 @@ pub fn _mm256_adds_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_adds_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_adds_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_add(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -142,7 +151,8 @@ pub fn _mm256_adds_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_adds_epu8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_adds_epu8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_add(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -153,7 +163,8 @@ pub fn _mm256_adds_epu8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_adds_epu16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_adds_epu16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_add(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -166,7 +177,8 @@ pub fn _mm256_adds_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 7))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_alignr_epi8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_alignr_epi8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
 
     // If palignr is shifting the pair of vectors more than the size of two
@@ -247,7 +259,8 @@ pub fn _mm256_alignr_epi8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_and_si256(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_and_si256(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_and(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -259,7 +272,8 @@ pub fn _mm256_and_si256(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_andnot_si256(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_andnot_si256(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let all_ones = _mm256_set1_epi8(-1);
         transmute(simd_and(
@@ -276,7 +290,8 @@ pub fn _mm256_andnot_si256(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpavgw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_avg_epu16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_avg_epu16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let a = simd_cast::<_, u32x16>(a.as_u16x16());
         let b = simd_cast::<_, u32x16>(b.as_u16x16());
@@ -292,7 +307,8 @@ pub fn _mm256_avg_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpavgb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_avg_epu8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_avg_epu8(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let a = simd_cast::<_, u16x32>(a.as_u8x32());
         let b = simd_cast::<_, u16x32>(b.as_u8x32());
@@ -309,7 +325,8 @@ pub fn _mm256_avg_epu8(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vblendps, IMM4 = 9))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_blend_epi32<const IMM4: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_blend_epi32<const IMM4: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM4, 4);
     unsafe {
         let a = a.as_i32x4();
@@ -336,7 +353,8 @@ pub fn _mm_blend_epi32<const IMM4: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vblendps, IMM8 = 9))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blend_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blend_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i32x8();
@@ -367,7 +385,8 @@ pub fn _mm256_blend_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpblendw, IMM8 = 9))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blend_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blend_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i16x16();
@@ -406,7 +425,8 @@ pub fn _mm256_blend_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpblendvb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_blendv_epi8(a: __m256i, b: __m256i, mask: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_blendv_epi8(a: __m256i, b: __m256i, mask: __m256i) -> __m256i {
     unsafe {
         let mask: i8x32 = simd_lt(mask.as_i8x32(), i8x32::ZERO);
         transmute(simd_select(mask, b.as_i8x32(), a.as_i8x32()))
@@ -421,7 +441,8 @@ pub fn _mm256_blendv_epi8(a: __m256i, b: __m256i, mask: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_broadcastb_epi8(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastb_epi8(a: __m128i) -> __m128i {
     unsafe {
         let ret = simd_shuffle!(a.as_i8x16(), i8x16::ZERO, [0_u32; 16]);
         transmute::<i8x16, _>(ret)
@@ -436,7 +457,8 @@ pub fn _mm_broadcastb_epi8(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastb_epi8(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastb_epi8(a: __m128i) -> __m256i {
     unsafe {
         let ret = simd_shuffle!(a.as_i8x16(), i8x16::ZERO, [0_u32; 32]);
         transmute::<i8x32, _>(ret)
@@ -453,7 +475,8 @@ pub fn _mm256_broadcastb_epi8(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_broadcastd_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastd_epi32(a: __m128i) -> __m128i {
     unsafe {
         let ret = simd_shuffle!(a.as_i32x4(), i32x4::ZERO, [0_u32; 4]);
         transmute::<i32x4, _>(ret)
@@ -470,7 +493,8 @@ pub fn _mm_broadcastd_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastd_epi32(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastd_epi32(a: __m128i) -> __m256i {
     unsafe {
         let ret = simd_shuffle!(a.as_i32x4(), i32x4::ZERO, [0_u32; 8]);
         transmute::<i32x8, _>(ret)
@@ -487,7 +511,8 @@ pub fn _mm256_broadcastd_epi32(a: __m128i) -> __m256i {
 // See https://github.com/rust-lang/stdarch/issues/791
 #[cfg_attr(test, assert_instr(vmovddup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_broadcastq_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastq_epi64(a: __m128i) -> __m128i {
     unsafe {
         let ret = simd_shuffle!(a.as_i64x2(), a.as_i64x2(), [0_u32; 2]);
         transmute::<i64x2, _>(ret)
@@ -502,7 +527,8 @@ pub fn _mm_broadcastq_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastq_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastq_epi64(a: __m128i) -> __m256i {
     unsafe {
         let ret = simd_shuffle!(a.as_i64x2(), a.as_i64x2(), [0_u32; 4]);
         transmute::<i64x4, _>(ret)
@@ -517,7 +543,8 @@ pub fn _mm256_broadcastq_epi64(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vmovddup))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_broadcastsd_pd(a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastsd_pd(a: __m128d) -> __m128d {
     unsafe { simd_shuffle!(a, _mm_setzero_pd(), [0_u32; 2]) }
 }
 
@@ -529,7 +556,8 @@ pub fn _mm_broadcastsd_pd(a: __m128d) -> __m128d {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastsd_pd(a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastsd_pd(a: __m128d) -> __m256d {
     unsafe { simd_shuffle!(a, _mm_setzero_pd(), [0_u32; 4]) }
 }
 
@@ -540,7 +568,8 @@ pub fn _mm256_broadcastsd_pd(a: __m128d) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx2")]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub fn _mm_broadcastsi128_si256(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastsi128_si256(a: __m128i) -> __m256i {
     unsafe {
         let ret = simd_shuffle!(a.as_i64x2(), i64x2::ZERO, [0, 1, 0, 1]);
         transmute::<i64x4, _>(ret)
@@ -556,7 +585,8 @@ pub fn _mm_broadcastsi128_si256(a: __m128i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx2")]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastsi128_si256(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastsi128_si256(a: __m128i) -> __m256i {
     unsafe {
         let ret = simd_shuffle!(a.as_i64x2(), i64x2::ZERO, [0, 1, 0, 1]);
         transmute::<i64x4, _>(ret)
@@ -571,7 +601,8 @@ pub fn _mm256_broadcastsi128_si256(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_broadcastss_ps(a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastss_ps(a: __m128) -> __m128 {
     unsafe { simd_shuffle!(a, _mm_setzero_ps(), [0_u32; 4]) }
 }
 
@@ -583,7 +614,8 @@ pub fn _mm_broadcastss_ps(a: __m128) -> __m128 {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastss_ps(a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastss_ps(a: __m128) -> __m256 {
     unsafe { simd_shuffle!(a, _mm_setzero_ps(), [0_u32; 8]) }
 }
 
@@ -595,7 +627,8 @@ pub fn _mm256_broadcastss_ps(a: __m128) -> __m256 {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_broadcastw_epi16(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastw_epi16(a: __m128i) -> __m128i {
     unsafe {
         let ret = simd_shuffle!(a.as_i16x8(), i16x8::ZERO, [0_u32; 8]);
         transmute::<i16x8, _>(ret)
@@ -610,7 +643,8 @@ pub fn _mm_broadcastw_epi16(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_broadcastw_epi16(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastw_epi16(a: __m128i) -> __m256i {
     unsafe {
         let ret = simd_shuffle!(a.as_i16x8(), i16x8::ZERO, [0_u32; 16]);
         transmute::<i16x16, _>(ret)
@@ -624,7 +658,8 @@ pub fn _mm256_broadcastw_epi16(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpeqq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpeq_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i64x4, _>(simd_eq(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -635,7 +670,8 @@ pub fn _mm256_cmpeq_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpeqd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpeq_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i32x8, _>(simd_eq(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -646,7 +682,8 @@ pub fn _mm256_cmpeq_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpeqw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpeq_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i16x16, _>(simd_eq(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -657,7 +694,8 @@ pub fn _mm256_cmpeq_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpeqb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpeq_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i8x32, _>(simd_eq(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -668,7 +706,8 @@ pub fn _mm256_cmpeq_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpgtq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpgt_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i64x4, _>(simd_gt(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -679,7 +718,8 @@ pub fn _mm256_cmpgt_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpgtd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpgt_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i32x8, _>(simd_gt(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -690,7 +730,8 @@ pub fn _mm256_cmpgt_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpgtw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpgt_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i16x16, _>(simd_gt(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -701,7 +742,8 @@ pub fn _mm256_cmpgt_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpcmpgtb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cmpgt_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute::<i8x32, _>(simd_gt(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -712,7 +754,8 @@ pub fn _mm256_cmpgt_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi16_epi32(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi16_epi32(a: __m128i) -> __m256i {
     unsafe { transmute::<i32x8, _>(simd_cast(a.as_i16x8())) }
 }
 
@@ -723,7 +766,8 @@ pub fn _mm256_cvtepi16_epi32(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi16_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi16_epi64(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i16x8();
         let v64: i16x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -738,7 +782,8 @@ pub fn _mm256_cvtepi16_epi64(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi32_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi32_epi64(a: __m128i) -> __m256i {
     unsafe { transmute::<i64x4, _>(simd_cast(a.as_i32x4())) }
 }
 
@@ -749,7 +794,8 @@ pub fn _mm256_cvtepi32_epi64(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi8_epi16(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi8_epi16(a: __m128i) -> __m256i {
     unsafe { transmute::<i16x16, _>(simd_cast(a.as_i8x16())) }
 }
 
@@ -760,7 +806,8 @@ pub fn _mm256_cvtepi8_epi16(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi8_epi32(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi8_epi32(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i8x16();
         let v64: i8x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -775,7 +822,8 @@ pub fn _mm256_cvtepi8_epi32(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepi8_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi8_epi64(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i8x16();
         let v32: i8x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -791,7 +839,8 @@ pub fn _mm256_cvtepi8_epi64(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepu16_epi32(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu16_epi32(a: __m128i) -> __m256i {
     unsafe { transmute::<i32x8, _>(simd_cast(a.as_u16x8())) }
 }
 
@@ -803,7 +852,8 @@ pub fn _mm256_cvtepu16_epi32(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepu16_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu16_epi64(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_u16x8();
         let v64: u16x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -818,7 +868,8 @@ pub fn _mm256_cvtepu16_epi64(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepu32_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu32_epi64(a: __m128i) -> __m256i {
     unsafe { transmute::<i64x4, _>(simd_cast(a.as_u32x4())) }
 }
 
@@ -829,7 +880,8 @@ pub fn _mm256_cvtepu32_epi64(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepu8_epi16(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu8_epi16(a: __m128i) -> __m256i {
     unsafe { transmute::<i16x16, _>(simd_cast(a.as_u8x16())) }
 }
 
@@ -841,7 +893,8 @@ pub fn _mm256_cvtepu8_epi16(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepu8_epi32(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu8_epi32(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_u8x16();
         let v64: u8x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -857,7 +910,8 @@ pub fn _mm256_cvtepu8_epi32(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_cvtepu8_epi64(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu8_epi64(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_u8x16();
         let v32: u8x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -873,7 +927,8 @@ pub fn _mm256_cvtepu8_epi64(a: __m128i) -> __m256i {
 #[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extracti128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extracti128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         let a = a.as_i64x4();
@@ -890,7 +945,8 @@ pub fn _mm256_extracti128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vphaddw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hadd_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hadd_epi16(a: __m256i, b: __m256i) -> __m256i {
     let a = a.as_i16x16();
     let b = b.as_i16x16();
     unsafe {
@@ -915,7 +971,8 @@ pub fn _mm256_hadd_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vphaddd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i {
     let a = a.as_i32x8();
     let b = b.as_i32x8();
     unsafe {
@@ -944,7 +1001,8 @@ pub fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vphsubw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hsub_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hsub_epi16(a: __m256i, b: __m256i) -> __m256i {
     let a = a.as_i16x16();
     let b = b.as_i16x16();
     unsafe {
@@ -969,7 +1027,8 @@ pub fn _mm256_hsub_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vphsubd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i {
     let a = a.as_i32x8();
     let b = b.as_i32x8();
     unsafe {
@@ -1734,7 +1793,8 @@ pub unsafe fn _mm256_mask_i64gather_pd<const SCALE: i32>(
 #[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m256i {
     static_assert_uimm_bits!(IMM1, 1);
     unsafe {
         let a = a.as_i64x4();
@@ -1753,7 +1813,8 @@ pub fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m25
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i32x16 = simd_mul(simd_cast(a.as_i16x16()), simd_cast(b.as_i16x16()));
         let even: i32x8 = simd_shuffle!(r, r, [0, 2, 4, 6, 8, 10, 12, 14]);
@@ -1785,7 +1846,8 @@ pub fn _mm256_maddubs_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskload_epi32(mem_addr: *const i32, mask: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskload_epi32(mem_addr: *const i32, mask: __m128i) -> __m128i {
     let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i32x4::ZERO).as_m128i()
 }
@@ -1799,7 +1861,8 @@ pub unsafe fn _mm_maskload_epi32(mem_addr: *const i32, mask: __m128i) -> __m128i
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskload_epi32(mem_addr: *const i32, mask: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskload_epi32(mem_addr: *const i32, mask: __m256i) -> __m256i {
     let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i32x8::ZERO).as_m256i()
 }
@@ -1813,7 +1876,8 @@ pub unsafe fn _mm256_maskload_epi32(mem_addr: *const i32, mask: __m256i) -> __m2
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskload_epi64(mem_addr: *const i64, mask: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskload_epi64(mem_addr: *const i64, mask: __m128i) -> __m128i {
     let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i64x2::ZERO).as_m128i()
 }
@@ -1827,7 +1891,8 @@ pub unsafe fn _mm_maskload_epi64(mem_addr: *const i64, mask: __m128i) -> __m128i
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskload_epi64(mem_addr: *const i64, mask: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskload_epi64(mem_addr: *const i64, mask: __m256i) -> __m256i {
     let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, i64x4::ZERO).as_m256i()
 }
@@ -1841,7 +1906,8 @@ pub unsafe fn _mm256_maskload_epi64(mem_addr: *const i64, mask: __m256i) -> __m2
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskstore_epi32(mem_addr: *mut i32, mask: __m128i, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskstore_epi32(mem_addr: *mut i32, mask: __m128i, a: __m128i) {
     let mask = simd_shr(mask.as_i32x4(), i32x4::splat(31));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x4())
 }
@@ -1855,7 +1921,8 @@ pub unsafe fn _mm_maskstore_epi32(mem_addr: *mut i32, mask: __m128i, a: __m128i)
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskstore_epi32(mem_addr: *mut i32, mask: __m256i, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskstore_epi32(mem_addr: *mut i32, mask: __m256i, a: __m256i) {
     let mask = simd_shr(mask.as_i32x8(), i32x8::splat(31));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x8())
 }
@@ -1869,7 +1936,8 @@ pub unsafe fn _mm256_maskstore_epi32(mem_addr: *mut i32, mask: __m256i, a: __m25
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_maskstore_epi64(mem_addr: *mut i64, mask: __m128i, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskstore_epi64(mem_addr: *mut i64, mask: __m128i, a: __m128i) {
     let mask = simd_shr(mask.as_i64x2(), i64x2::splat(63));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x2())
 }
@@ -1883,7 +1951,8 @@ pub unsafe fn _mm_maskstore_epi64(mem_addr: *mut i64, mask: __m128i, a: __m128i)
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaskmovq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_maskstore_epi64(mem_addr: *mut i64, mask: __m256i, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskstore_epi64(mem_addr: *mut i64, mask: __m256i, a: __m256i) {
     let mask = simd_shr(mask.as_i64x4(), i64x4::splat(63));
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x4())
 }
@@ -1896,7 +1965,8 @@ pub unsafe fn _mm256_maskstore_epi64(mem_addr: *mut i64, mask: __m256i, a: __m25
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_max_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_i16x16(), b.as_i16x16()).as_m256i() }
 }
 
@@ -1908,7 +1978,8 @@ pub fn _mm256_max_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_max_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_i32x8(), b.as_i32x8()).as_m256i() }
 }
 
@@ -1920,7 +1991,8 @@ pub fn _mm256_max_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_max_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_i8x32(), b.as_i8x32()).as_m256i() }
 }
 
@@ -1932,7 +2004,8 @@ pub fn _mm256_max_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_max_epu16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epu16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_u16x16(), b.as_u16x16()).as_m256i() }
 }
 
@@ -1944,7 +2017,8 @@ pub fn _mm256_max_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_max_epu32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epu32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_u32x8(), b.as_u32x8()).as_m256i() }
 }
 
@@ -1956,7 +2030,8 @@ pub fn _mm256_max_epu32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_max_epu8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epu8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_u8x32(), b.as_u8x32()).as_m256i() }
 }
 
@@ -1968,7 +2043,8 @@ pub fn _mm256_max_epu8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpminsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_min_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_i16x16(), b.as_i16x16()).as_m256i() }
 }
 
@@ -1980,7 +2056,8 @@ pub fn _mm256_min_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpminsd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_min_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_i32x8(), b.as_i32x8()).as_m256i() }
 }
 
@@ -1992,7 +2069,8 @@ pub fn _mm256_min_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpminsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_min_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_i8x32(), b.as_i8x32()).as_m256i() }
 }
 
@@ -2004,7 +2082,8 @@ pub fn _mm256_min_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpminuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_min_epu16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epu16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_u16x16(), b.as_u16x16()).as_m256i() }
 }
 
@@ -2016,7 +2095,8 @@ pub fn _mm256_min_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpminud))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_min_epu32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epu32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_u32x8(), b.as_u32x8()).as_m256i() }
 }
 
@@ -2028,7 +2108,8 @@ pub fn _mm256_min_epu32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpminub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_min_epu8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epu8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_u8x32(), b.as_u8x32()).as_m256i() }
 }
 
@@ -2040,7 +2121,8 @@ pub fn _mm256_min_epu8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmovmskb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_movemask_epi8(a: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movemask_epi8(a: __m256i) -> i32 {
     unsafe {
         let z = i8x32::ZERO;
         let m: i8x32 = simd_lt(a.as_i8x32(), z);
@@ -2077,7 +2159,8 @@ pub fn _mm256_mpsadbw_epu8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mul_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mul_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let a = simd_cast::<_, i64x4>(simd_cast::<_, i32x4>(a.as_i64x4()));
         let b = simd_cast::<_, i64x4>(simd_cast::<_, i32x4>(b.as_i64x4()));
@@ -2095,11 +2178,12 @@ pub fn _mm256_mul_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mul_epu32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mul_epu32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let a = a.as_u64x4();
         let b = b.as_u64x4();
-        let mask = u64x4::splat(u32::MAX.into());
+        let mask = u64x4::splat(u32::MAX as u64);
         transmute(simd_mul(simd_and(a, mask), simd_and(b, mask)))
     }
 }
@@ -2113,7 +2197,8 @@ pub fn _mm256_mul_epu32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mulhi_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mulhi_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let a = simd_cast::<_, i32x16>(a.as_i16x16());
         let b = simd_cast::<_, i32x16>(b.as_i16x16());
@@ -2131,7 +2216,8 @@ pub fn _mm256_mulhi_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mulhi_epu16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mulhi_epu16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let a = simd_cast::<_, u32x16>(a.as_u16x16());
         let b = simd_cast::<_, u32x16>(b.as_u16x16());
@@ -2149,7 +2235,8 @@ pub fn _mm256_mulhi_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmullw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mullo_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mullo_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_mul(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -2162,7 +2249,8 @@ pub fn _mm256_mullo_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmulld))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_mullo_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mullo_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_mul(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -2188,7 +2276,8 @@ pub fn _mm256_mulhrs_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_or(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -2262,7 +2351,8 @@ pub fn _mm256_permutevar8x32_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpermpd, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute4x64_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute4x64_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let zero = i64x4::ZERO;
@@ -2288,7 +2378,8 @@ pub fn _mm256_permute4x64_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vperm2f128, IMM8 = 9))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute2x128_si256<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute2x128_si256<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_permute2f128_si256::<IMM8>(a, b)
 }
@@ -2302,7 +2393,8 @@ pub fn _mm256_permute2x128_si256<const IMM8: i32>(a: __m256i, b: __m256i) -> __m
 #[cfg_attr(test, assert_instr(vpermpd, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_permute4x64_pd<const IMM8: i32>(a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permute4x64_pd<const IMM8: i32>(a: __m256d) -> __m256d {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         simd_shuffle!(
@@ -2417,7 +2509,8 @@ pub fn _mm256_shuffle_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vshufps, MASK = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_shuffle_epi32<const MASK: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_epi32<const MASK: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(MASK, 8);
     unsafe {
         let r: i32x8 = simd_shuffle!(
@@ -2448,7 +2541,8 @@ pub fn _mm256_shuffle_epi32<const MASK: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_shufflehi_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shufflehi_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i16x16();
@@ -2488,7 +2582,8 @@ pub fn _mm256_shufflehi_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 9))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_shufflelo_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shufflelo_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         let a = a.as_i16x16();
@@ -2602,7 +2697,8 @@ pub fn _mm256_sll_epi64(a: __m256i, count: __m128i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_slli_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_slli_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 16 {
@@ -2622,7 +2718,8 @@ pub fn _mm256_slli_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_slli_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_slli_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -2642,7 +2739,8 @@ pub fn _mm256_slli_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_slli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_slli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -2661,7 +2759,8 @@ pub fn _mm256_slli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpslldq, IMM8 = 3))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_slli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_slli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_bslli_epi128::<IMM8>(a)
 }
@@ -2674,7 +2773,8 @@ pub fn _mm256_slli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpslldq, IMM8 = 3))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_bslli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_bslli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     const fn mask(shift: i32, i: u32) -> u32 {
         let shift = shift as u32 & 0xff;
@@ -2737,7 +2837,8 @@ pub fn _mm256_bslli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u32x4();
         let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
@@ -2755,7 +2856,8 @@ pub fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u32x8();
         let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
@@ -2773,7 +2875,8 @@ pub fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u64x2();
         let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
@@ -2791,7 +2894,8 @@ pub fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sllv_epi64(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sllv_epi64(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u64x4();
         let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
@@ -2833,7 +2937,8 @@ pub fn _mm256_sra_epi32(a: __m256i, count: __m128i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srai_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srai_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe { transmute(simd_shr(a.as_i16x16(), i16x16::splat(IMM8.min(15) as i16))) }
 }
@@ -2847,7 +2952,8 @@ pub fn _mm256_srai_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srai_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srai_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe { transmute(simd_shr(a.as_i32x8(), i32x8::splat(IMM8.min(31)))) }
 }
@@ -2860,7 +2966,8 @@ pub fn _mm256_srai_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsravd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u32x4();
         let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
@@ -2877,7 +2984,8 @@ pub fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsravd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u32x8();
         let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
@@ -2894,7 +3002,8 @@ pub fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrldq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_bsrli_epi128::<IMM8>(a)
 }
@@ -2907,7 +3016,8 @@ pub fn _mm256_srli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrldq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     const fn mask(shift: i32, i: u32) -> u32 {
         let shift = shift as u32 & 0xff;
@@ -3006,7 +3116,8 @@ pub fn _mm256_srl_epi64(a: __m256i, count: __m128i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srli_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srli_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 16 {
@@ -3026,7 +3137,8 @@ pub fn _mm256_srli_epi16<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srli_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srli_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 32 {
@@ -3046,7 +3158,8 @@ pub fn _mm256_srli_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 7))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     unsafe {
         if IMM8 >= 64 {
@@ -3065,7 +3178,8 @@ pub fn _mm256_srli_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u32x4();
         let no_overflow: u32x4 = simd_lt(count, u32x4::splat(u32::BITS));
@@ -3082,7 +3196,8 @@ pub fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u32x8();
         let no_overflow: u32x8 = simd_lt(count, u32x8::splat(u32::BITS));
@@ -3099,7 +3214,8 @@ pub fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u64x2();
         let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
@@ -3116,7 +3232,8 @@ pub fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u64x4();
         let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
@@ -3152,7 +3269,8 @@ pub unsafe fn _mm256_stream_load_si256(mem_addr: *const __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sub_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_sub(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -3163,7 +3281,8 @@ pub fn _mm256_sub_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sub_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_sub(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -3174,7 +3293,8 @@ pub fn _mm256_sub_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubq))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sub_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_sub(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -3185,7 +3305,8 @@ pub fn _mm256_sub_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_sub_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_sub(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -3197,7 +3318,8 @@ pub fn _mm256_sub_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_subs_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_subs_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_sub(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -3209,7 +3331,8 @@ pub fn _mm256_subs_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_subs_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_subs_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_sub(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -3221,7 +3344,8 @@ pub fn _mm256_subs_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_subs_epu16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_subs_epu16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_sub(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -3233,7 +3357,8 @@ pub fn _mm256_subs_epu16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_subs_epu8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_subs_epu8(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_saturating_sub(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -3280,7 +3405,8 @@ pub fn _mm256_subs_epu8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpackhi_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpackhi_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         #[rustfmt::skip]
         let r: i8x32 = simd_shuffle!(a.as_i8x32(), b.as_i8x32(), [
@@ -3335,7 +3461,8 @@ pub fn _mm256_unpackhi_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpacklo_epi8(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpacklo_epi8(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         #[rustfmt::skip]
         let r: i8x32 = simd_shuffle!(a.as_i8x32(), b.as_i8x32(), [
@@ -3386,7 +3513,8 @@ pub fn _mm256_unpacklo_epi8(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpackhi_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpackhi_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i16x16 = simd_shuffle!(
             a.as_i16x16(),
@@ -3436,7 +3564,8 @@ pub fn _mm256_unpackhi_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpacklo_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpacklo_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i16x16 = simd_shuffle!(
             a.as_i16x16(),
@@ -3479,7 +3608,8 @@ pub fn _mm256_unpacklo_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpackhi_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpackhi_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i32x8 = simd_shuffle!(a.as_i32x8(), b.as_i32x8(), [2, 10, 3, 11, 6, 14, 7, 15]);
         transmute(r)
@@ -3518,7 +3648,8 @@ pub fn _mm256_unpackhi_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpacklo_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpacklo_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i32x8 = simd_shuffle!(a.as_i32x8(), b.as_i32x8(), [0, 8, 1, 9, 4, 12, 5, 13]);
         transmute(r)
@@ -3557,7 +3688,8 @@ pub fn _mm256_unpacklo_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpackhi_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpackhi_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i64x4 = simd_shuffle!(a.as_i64x4(), b.as_i64x4(), [1, 5, 3, 7]);
         transmute(r)
@@ -3596,7 +3728,8 @@ pub fn _mm256_unpackhi_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_unpacklo_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_unpacklo_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let r: i64x4 = simd_shuffle!(a.as_i64x4(), b.as_i64x4(), [0, 4, 2, 6]);
         transmute(r)
@@ -3611,7 +3744,8 @@ pub fn _mm256_unpacklo_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_xor_si256(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_xor_si256(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_xor(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -3626,7 +3760,8 @@ pub fn _mm256_xor_si256(a: __m256i, b: __m256i) -> __m256i {
 // This intrinsic has no corresponding instruction.
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extract_epi8<const INDEX: i32>(a: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extract_epi8<const INDEX: i32>(a: __m256i) -> i32 {
     static_assert_uimm_bits!(INDEX, 5);
     unsafe { simd_extract!(a.as_u8x32(), INDEX as u32, u8) as i32 }
 }
@@ -3642,7 +3777,8 @@ pub fn _mm256_extract_epi8<const INDEX: i32>(a: __m256i) -> i32 {
 // This intrinsic has no corresponding instruction.
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
     static_assert_uimm_bits!(INDEX, 4);
     unsafe { simd_extract!(a.as_u16x16(), INDEX as u32, u16) as i32 }
 }
@@ -3771,13 +3907,14 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_abs_epi32() {
+    const unsafe fn test_mm256_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -3793,7 +3930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_abs_epi16() {
+    const unsafe fn test_mm256_abs_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0,  1, -1, 2, -2, 3, -3, 4,
@@ -3809,7 +3946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_abs_epi8() {
+    const unsafe fn test_mm256_abs_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, -1, 2, -2, 3, -3, 4,
@@ -3829,7 +3966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_add_epi64() {
+    const unsafe fn test_mm256_add_epi64() {
         let a = _mm256_setr_epi64x(-10, 0, 100, 1_000_000_000);
         let b = _mm256_setr_epi64x(-1, 0, 1, 2);
         let r = _mm256_add_epi64(a, b);
@@ -3838,7 +3975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_add_epi32() {
+    const unsafe fn test_mm256_add_epi32() {
         let a = _mm256_setr_epi32(-1, 0, 1, 2, 3, 4, 5, 6);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_add_epi32(a, b);
@@ -3847,7 +3984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_add_epi16() {
+    const unsafe fn test_mm256_add_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -3868,7 +4005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_add_epi8() {
+    const unsafe fn test_mm256_add_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -3895,7 +4032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epi8() {
+    const unsafe fn test_mm256_adds_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -3938,7 +4075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epi16() {
+    const unsafe fn test_mm256_adds_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -3976,7 +4113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epu8() {
+    const unsafe fn test_mm256_adds_epu8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4011,7 +4148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epu16() {
+    const unsafe fn test_mm256_adds_epu16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4041,7 +4178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_and_si256() {
+    const unsafe fn test_mm256_and_si256() {
         let a = _mm256_set1_epi8(5);
         let b = _mm256_set1_epi8(3);
         let got = _mm256_and_si256(a, b);
@@ -4049,7 +4186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_andnot_si256() {
+    const unsafe fn test_mm256_andnot_si256() {
         let a = _mm256_set1_epi8(5);
         let b = _mm256_set1_epi8(3);
         let got = _mm256_andnot_si256(a, b);
@@ -4057,21 +4194,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_avg_epu8() {
+    const unsafe fn test_mm256_avg_epu8() {
         let (a, b) = (_mm256_set1_epi8(3), _mm256_set1_epi8(9));
         let r = _mm256_avg_epu8(a, b);
         assert_eq_m256i(r, _mm256_set1_epi8(6));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_avg_epu16() {
+    const unsafe fn test_mm256_avg_epu16() {
         let (a, b) = (_mm256_set1_epi16(3), _mm256_set1_epi16(9));
         let r = _mm256_avg_epu16(a, b);
         assert_eq_m256i(r, _mm256_set1_epi16(6));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_blend_epi32() {
+    const unsafe fn test_mm_blend_epi32() {
         let (a, b) = (_mm_set1_epi32(3), _mm_set1_epi32(9));
         let e = _mm_setr_epi32(9, 3, 3, 3);
         let r = _mm_blend_epi32::<0x01>(a, b);
@@ -4082,7 +4219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_blend_epi32() {
+    const unsafe fn test_mm256_blend_epi32() {
         let (a, b) = (_mm256_set1_epi32(3), _mm256_set1_epi32(9));
         let e = _mm256_setr_epi32(9, 3, 3, 3, 3, 3, 3, 3);
         let r = _mm256_blend_epi32::<0x01>(a, b);
@@ -4098,7 +4235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_blend_epi16() {
+    const unsafe fn test_mm256_blend_epi16() {
         let (a, b) = (_mm256_set1_epi16(3), _mm256_set1_epi16(9));
         let e = _mm256_setr_epi16(9, 3, 3, 3, 3, 3, 3, 3, 9, 3, 3, 3, 3, 3, 3, 3);
         let r = _mm256_blend_epi16::<0x01>(a, b);
@@ -4109,7 +4246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_blendv_epi8() {
+    const unsafe fn test_mm256_blendv_epi8() {
         let (a, b) = (_mm256_set1_epi8(4), _mm256_set1_epi8(2));
         let mask = _mm256_insert_epi8::<2>(_mm256_set1_epi8(0), -1);
         let e = _mm256_insert_epi8::<2>(_mm256_set1_epi8(4), 2);
@@ -4118,63 +4255,63 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastb_epi8() {
+    const unsafe fn test_mm_broadcastb_epi8() {
         let a = _mm_insert_epi8::<0>(_mm_set1_epi8(0x00), 0x2a);
         let res = _mm_broadcastb_epi8(a);
         assert_eq_m128i(res, _mm_set1_epi8(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastb_epi8() {
+    const unsafe fn test_mm256_broadcastb_epi8() {
         let a = _mm_insert_epi8::<0>(_mm_set1_epi8(0x00), 0x2a);
         let res = _mm256_broadcastb_epi8(a);
         assert_eq_m256i(res, _mm256_set1_epi8(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastd_epi32() {
+    const unsafe fn test_mm_broadcastd_epi32() {
         let a = _mm_setr_epi32(0x2a, 0x8000000, 0, 0);
         let res = _mm_broadcastd_epi32(a);
         assert_eq_m128i(res, _mm_set1_epi32(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastd_epi32() {
+    const unsafe fn test_mm256_broadcastd_epi32() {
         let a = _mm_setr_epi32(0x2a, 0x8000000, 0, 0);
         let res = _mm256_broadcastd_epi32(a);
         assert_eq_m256i(res, _mm256_set1_epi32(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastq_epi64() {
+    const unsafe fn test_mm_broadcastq_epi64() {
         let a = _mm_setr_epi64x(0x1ffffffff, 0);
         let res = _mm_broadcastq_epi64(a);
         assert_eq_m128i(res, _mm_set1_epi64x(0x1ffffffff));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastq_epi64() {
+    const unsafe fn test_mm256_broadcastq_epi64() {
         let a = _mm_setr_epi64x(0x1ffffffff, 0);
         let res = _mm256_broadcastq_epi64(a);
         assert_eq_m256i(res, _mm256_set1_epi64x(0x1ffffffff));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastsd_pd() {
+    const unsafe fn test_mm_broadcastsd_pd() {
         let a = _mm_setr_pd(6.88, 3.44);
         let res = _mm_broadcastsd_pd(a);
         assert_eq_m128d(res, _mm_set1_pd(6.88));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastsd_pd() {
+    const unsafe fn test_mm256_broadcastsd_pd() {
         let a = _mm_setr_pd(6.88, 3.44);
         let res = _mm256_broadcastsd_pd(a);
         assert_eq_m256d(res, _mm256_set1_pd(6.88f64));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastsi128_si256() {
+    const unsafe fn test_mm_broadcastsi128_si256() {
         let a = _mm_setr_epi64x(0x0987654321012334, 0x5678909876543210);
         let res = _mm_broadcastsi128_si256(a);
         let retval = _mm256_setr_epi64x(
@@ -4187,7 +4324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastsi128_si256() {
+    const unsafe fn test_mm256_broadcastsi128_si256() {
         let a = _mm_setr_epi64x(0x0987654321012334, 0x5678909876543210);
         let res = _mm256_broadcastsi128_si256(a);
         let retval = _mm256_setr_epi64x(
@@ -4200,35 +4337,35 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastss_ps() {
+    const unsafe fn test_mm_broadcastss_ps() {
         let a = _mm_setr_ps(6.88, 3.44, 0.0, 0.0);
         let res = _mm_broadcastss_ps(a);
         assert_eq_m128(res, _mm_set1_ps(6.88));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastss_ps() {
+    const unsafe fn test_mm256_broadcastss_ps() {
         let a = _mm_setr_ps(6.88, 3.44, 0.0, 0.0);
         let res = _mm256_broadcastss_ps(a);
         assert_eq_m256(res, _mm256_set1_ps(6.88));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_broadcastw_epi16() {
+    const unsafe fn test_mm_broadcastw_epi16() {
         let a = _mm_insert_epi16::<0>(_mm_set1_epi16(0x2a), 0x22b);
         let res = _mm_broadcastw_epi16(a);
         assert_eq_m128i(res, _mm_set1_epi16(0x22b));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_broadcastw_epi16() {
+    const unsafe fn test_mm256_broadcastw_epi16() {
         let a = _mm_insert_epi16::<0>(_mm_set1_epi16(0x2a), 0x22b);
         let res = _mm256_broadcastw_epi16(a);
         assert_eq_m256i(res, _mm256_set1_epi16(0x22b));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpeq_epi8() {
+    const unsafe fn test_mm256_cmpeq_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4248,7 +4385,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpeq_epi16() {
+    const unsafe fn test_mm256_cmpeq_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4264,7 +4401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpeq_epi32() {
+    const unsafe fn test_mm256_cmpeq_epi32() {
         let a = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_setr_epi32(7, 6, 2, 4, 3, 2, 1, 0);
         let r = _mm256_cmpeq_epi32(a, b);
@@ -4274,7 +4411,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpeq_epi64() {
+    const unsafe fn test_mm256_cmpeq_epi64() {
         let a = _mm256_setr_epi64x(0, 1, 2, 3);
         let b = _mm256_setr_epi64x(3, 2, 2, 0);
         let r = _mm256_cmpeq_epi64(a, b);
@@ -4282,7 +4419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpgt_epi8() {
+    const unsafe fn test_mm256_cmpgt_epi8() {
         let a = _mm256_insert_epi8::<0>(_mm256_set1_epi8(0), 5);
         let b = _mm256_set1_epi8(0);
         let r = _mm256_cmpgt_epi8(a, b);
@@ -4290,7 +4427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpgt_epi16() {
+    const unsafe fn test_mm256_cmpgt_epi16() {
         let a = _mm256_insert_epi16::<0>(_mm256_set1_epi16(0), 5);
         let b = _mm256_set1_epi16(0);
         let r = _mm256_cmpgt_epi16(a, b);
@@ -4298,7 +4435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpgt_epi32() {
+    const unsafe fn test_mm256_cmpgt_epi32() {
         let a = _mm256_insert_epi32::<0>(_mm256_set1_epi32(0), 5);
         let b = _mm256_set1_epi32(0);
         let r = _mm256_cmpgt_epi32(a, b);
@@ -4306,7 +4443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cmpgt_epi64() {
+    const unsafe fn test_mm256_cmpgt_epi64() {
         let a = _mm256_insert_epi64::<0>(_mm256_set1_epi64x(0), 5);
         let b = _mm256_set1_epi64x(0);
         let r = _mm256_cmpgt_epi64(a, b);
@@ -4314,7 +4451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepi8_epi16() {
+    const unsafe fn test_mm256_cvtepi8_epi16() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 0, -1, 1, -2, 2, -3, 3,
@@ -4329,7 +4466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepi8_epi32() {
+    const unsafe fn test_mm256_cvtepi8_epi32() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 0, -1, 1, -2, 2, -3, 3,
@@ -4340,7 +4477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepi8_epi64() {
+    const unsafe fn test_mm256_cvtepi8_epi64() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 0, -1, 1, -2, 2, -3, 3,
@@ -4351,49 +4488,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepi16_epi32() {
+    const unsafe fn test_mm256_cvtepi16_epi32() {
         let a = _mm_setr_epi16(0, 0, -1, 1, -2, 2, -3, 3);
         let r = _mm256_setr_epi32(0, 0, -1, 1, -2, 2, -3, 3);
         assert_eq_m256i(r, _mm256_cvtepi16_epi32(a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepi16_epi64() {
+    const unsafe fn test_mm256_cvtepi16_epi64() {
         let a = _mm_setr_epi16(0, 0, -1, 1, -2, 2, -3, 3);
         let r = _mm256_setr_epi64x(0, 0, -1, 1);
         assert_eq_m256i(r, _mm256_cvtepi16_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepi32_epi64() {
+    const unsafe fn test_mm256_cvtepi32_epi64() {
         let a = _mm_setr_epi32(0, 0, -1, 1);
         let r = _mm256_setr_epi64x(0, 0, -1, 1);
         assert_eq_m256i(r, _mm256_cvtepi32_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepu16_epi32() {
+    const unsafe fn test_mm256_cvtepu16_epi32() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m256i(r, _mm256_cvtepu16_epi32(a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepu16_epi64() {
+    const unsafe fn test_mm256_cvtepu16_epi64() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_setr_epi64x(0, 1, 2, 3);
         assert_eq_m256i(r, _mm256_cvtepu16_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepu32_epi64() {
+    const unsafe fn test_mm256_cvtepu32_epi64() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let r = _mm256_setr_epi64x(0, 1, 2, 3);
         assert_eq_m256i(r, _mm256_cvtepu32_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepu8_epi16() {
+    const unsafe fn test_mm256_cvtepu8_epi16() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4408,7 +4545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepu8_epi32() {
+    const unsafe fn test_mm256_cvtepu8_epi32() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4419,7 +4556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtepu8_epi64() {
+    const unsafe fn test_mm256_cvtepu8_epi64() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4430,7 +4567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_extracti128_si256() {
+    const unsafe fn test_mm256_extracti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_extracti128_si256::<1>(a);
         let e = _mm_setr_epi64x(3, 4);
@@ -4438,7 +4575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_hadd_epi16() {
+    const unsafe fn test_mm256_hadd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_hadd_epi16(a, b);
@@ -4447,7 +4584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_hadd_epi32() {
+    const unsafe fn test_mm256_hadd_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_hadd_epi32(a, b);
@@ -4471,7 +4608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_hsub_epi16() {
+    const unsafe fn test_mm256_hsub_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_hsub_epi16(a, b);
@@ -4480,7 +4617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_hsub_epi32() {
+    const unsafe fn test_mm256_hsub_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_hsub_epi32(a, b);
@@ -4500,7 +4637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_madd_epi16() {
+    const unsafe fn test_mm256_madd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_madd_epi16(a, b);
@@ -4509,7 +4646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_inserti128_si256() {
+    const unsafe fn test_mm256_inserti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm_setr_epi64x(7, 8);
         let r = _mm256_inserti128_si256::<1>(a, b);
@@ -4527,7 +4664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_maskload_epi32() {
+    const unsafe fn test_mm_maskload_epi32() {
         let nums = [1, 2, 3, 4];
         let a = &nums as *const i32;
         let mask = _mm_setr_epi32(-1, 0, 0, -1);
@@ -4537,7 +4674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_maskload_epi32() {
+    const unsafe fn test_mm256_maskload_epi32() {
         let nums = [1, 2, 3, 4, 5, 6, 7, 8];
         let a = &nums as *const i32;
         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
@@ -4547,7 +4684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_maskload_epi64() {
+    const unsafe fn test_mm_maskload_epi64() {
         let nums = [1_i64, 2_i64];
         let a = &nums as *const i64;
         let mask = _mm_setr_epi64x(0, -1);
@@ -4557,7 +4694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_maskload_epi64() {
+    const unsafe fn test_mm256_maskload_epi64() {
         let nums = [1_i64, 2_i64, 3_i64, 4_i64];
         let a = &nums as *const i64;
         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
@@ -4567,7 +4704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_maskstore_epi32() {
+    const unsafe fn test_mm_maskstore_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut arr = [-1, -1, -1, -1];
         let mask = _mm_setr_epi32(-1, 0, 0, -1);
@@ -4577,7 +4714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_maskstore_epi32() {
+    const unsafe fn test_mm256_maskstore_epi32() {
         let a = _mm256_setr_epi32(1, 0x6d726f, 3, 42, 0x777161, 6, 7, 8);
         let mut arr = [-1, -1, -1, 0x776173, -1, 0x68657265, -1, -1];
         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
@@ -4587,7 +4724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_maskstore_epi64() {
+    const unsafe fn test_mm_maskstore_epi64() {
         let a = _mm_setr_epi64x(1_i64, 2_i64);
         let mut arr = [-1_i64, -1_i64];
         let mask = _mm_setr_epi64x(0, -1);
@@ -4597,7 +4734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_maskstore_epi64() {
+    const unsafe fn test_mm256_maskstore_epi64() {
         let a = _mm256_setr_epi64x(1_i64, 2_i64, 3_i64, 4_i64);
         let mut arr = [-1_i64, -1_i64, -1_i64, -1_i64];
         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
@@ -4607,7 +4744,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_max_epi16() {
+    const unsafe fn test_mm256_max_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_max_epi16(a, b);
@@ -4615,7 +4752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_max_epi32() {
+    const unsafe fn test_mm256_max_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_max_epi32(a, b);
@@ -4623,7 +4760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_max_epi8() {
+    const unsafe fn test_mm256_max_epi8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_max_epi8(a, b);
@@ -4631,7 +4768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_max_epu16() {
+    const unsafe fn test_mm256_max_epu16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_max_epu16(a, b);
@@ -4639,7 +4776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_max_epu32() {
+    const unsafe fn test_mm256_max_epu32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_max_epu32(a, b);
@@ -4647,7 +4784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_max_epu8() {
+    const unsafe fn test_mm256_max_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_max_epu8(a, b);
@@ -4655,7 +4792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_min_epi16() {
+    const unsafe fn test_mm256_min_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_min_epi16(a, b);
@@ -4663,7 +4800,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_min_epi32() {
+    const unsafe fn test_mm256_min_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_min_epi32(a, b);
@@ -4671,7 +4808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_min_epi8() {
+    const unsafe fn test_mm256_min_epi8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_min_epi8(a, b);
@@ -4679,7 +4816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_min_epu16() {
+    const unsafe fn test_mm256_min_epu16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_min_epu16(a, b);
@@ -4687,7 +4824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_min_epu32() {
+    const unsafe fn test_mm256_min_epu32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_min_epu32(a, b);
@@ -4695,7 +4832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_min_epu8() {
+    const unsafe fn test_mm256_min_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_min_epu8(a, b);
@@ -4703,7 +4840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_movemask_epi8() {
+    const unsafe fn test_mm256_movemask_epi8() {
         let a = _mm256_set1_epi8(-1);
         let r = _mm256_movemask_epi8(a);
         let e = -1;
@@ -4720,7 +4857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mul_epi32() {
+    const unsafe fn test_mm256_mul_epi32() {
         let a = _mm256_setr_epi32(0, 0, 0, 0, 2, 2, 2, 2);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mul_epi32(a, b);
@@ -4729,7 +4866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mul_epu32() {
+    const unsafe fn test_mm256_mul_epu32() {
         let a = _mm256_setr_epi32(0, 0, 0, 0, 2, 2, 2, 2);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mul_epu32(a, b);
@@ -4738,7 +4875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mulhi_epi16() {
+    const unsafe fn test_mm256_mulhi_epi16() {
         let a = _mm256_set1_epi16(6535);
         let b = _mm256_set1_epi16(6535);
         let r = _mm256_mulhi_epi16(a, b);
@@ -4747,7 +4884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mulhi_epu16() {
+    const unsafe fn test_mm256_mulhi_epu16() {
         let a = _mm256_set1_epi16(6535);
         let b = _mm256_set1_epi16(6535);
         let r = _mm256_mulhi_epu16(a, b);
@@ -4756,7 +4893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mullo_epi16() {
+    const unsafe fn test_mm256_mullo_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_mullo_epi16(a, b);
@@ -4765,7 +4902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mullo_epi32() {
+    const unsafe fn test_mm256_mullo_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_mullo_epi32(a, b);
@@ -4783,7 +4920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_or_si256() {
+    const unsafe fn test_mm256_or_si256() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(0);
         let r = _mm256_or_si256(a, b);
@@ -4852,7 +4989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_shufflehi_epi16() {
+    const unsafe fn test_mm256_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 11, 22, 33, 44,
@@ -4868,7 +5005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_shufflelo_epi16() {
+    const unsafe fn test_mm256_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             11, 22, 33, 44, 0, 1, 2, 3,
@@ -4935,7 +5072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_slli_epi16() {
+    const unsafe fn test_mm256_slli_epi16() {
         assert_eq_m256i(
             _mm256_slli_epi16::<4>(_mm256_set1_epi16(0xFF)),
             _mm256_set1_epi16(0xFF0),
@@ -4943,7 +5080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_slli_epi32() {
+    const unsafe fn test_mm256_slli_epi32() {
         assert_eq_m256i(
             _mm256_slli_epi32::<4>(_mm256_set1_epi32(0xFFFF)),
             _mm256_set1_epi32(0xFFFF0),
@@ -4951,7 +5088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_slli_epi64() {
+    const unsafe fn test_mm256_slli_epi64() {
         assert_eq_m256i(
             _mm256_slli_epi64::<4>(_mm256_set1_epi64x(0xFFFFFFFF)),
             _mm256_set1_epi64x(0xFFFFFFFF0),
@@ -4959,14 +5096,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_slli_si256() {
+    const unsafe fn test_mm256_slli_si256() {
         let a = _mm256_set1_epi64x(0xFFFFFFFF);
         let r = _mm256_slli_si256::<3>(a);
         assert_eq_m256i(r, _mm256_set1_epi64x(0xFFFFFFFF000000));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_sllv_epi32() {
+    const unsafe fn test_mm_sllv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(1);
         let r = _mm_sllv_epi32(a, b);
@@ -4975,7 +5112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sllv_epi32() {
+    const unsafe fn test_mm256_sllv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_sllv_epi32(a, b);
@@ -4984,7 +5121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_sllv_epi64() {
+    const unsafe fn test_mm_sllv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(1);
         let r = _mm_sllv_epi64(a, b);
@@ -4993,7 +5130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sllv_epi64() {
+    const unsafe fn test_mm256_sllv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_sllv_epi64(a, b);
@@ -5018,7 +5155,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srai_epi16() {
+    const unsafe fn test_mm256_srai_epi16() {
         assert_eq_m256i(
             _mm256_srai_epi16::<1>(_mm256_set1_epi16(-1)),
             _mm256_set1_epi16(-1),
@@ -5026,7 +5163,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srai_epi32() {
+    const unsafe fn test_mm256_srai_epi32() {
         assert_eq_m256i(
             _mm256_srai_epi32::<1>(_mm256_set1_epi32(-1)),
             _mm256_set1_epi32(-1),
@@ -5034,7 +5171,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_srav_epi32() {
+    const unsafe fn test_mm_srav_epi32() {
         let a = _mm_set1_epi32(4);
         let count = _mm_set1_epi32(1);
         let r = _mm_srav_epi32(a, count);
@@ -5043,7 +5180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srav_epi32() {
+    const unsafe fn test_mm256_srav_epi32() {
         let a = _mm256_set1_epi32(4);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_srav_epi32(a, count);
@@ -5052,7 +5189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srli_si256() {
+    const unsafe fn test_mm256_srli_si256() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5096,7 +5233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srli_epi16() {
+    const unsafe fn test_mm256_srli_epi16() {
         assert_eq_m256i(
             _mm256_srli_epi16::<4>(_mm256_set1_epi16(0xFF)),
             _mm256_set1_epi16(0xF),
@@ -5104,7 +5241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srli_epi32() {
+    const unsafe fn test_mm256_srli_epi32() {
         assert_eq_m256i(
             _mm256_srli_epi32::<4>(_mm256_set1_epi32(0xFFFF)),
             _mm256_set1_epi32(0xFFF),
@@ -5112,7 +5249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srli_epi64() {
+    const unsafe fn test_mm256_srli_epi64() {
         assert_eq_m256i(
             _mm256_srli_epi64::<4>(_mm256_set1_epi64x(0xFFFFFFFF)),
             _mm256_set1_epi64x(0xFFFFFFF),
@@ -5120,7 +5257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_srlv_epi32() {
+    const unsafe fn test_mm_srlv_epi32() {
         let a = _mm_set1_epi32(2);
         let count = _mm_set1_epi32(1);
         let r = _mm_srlv_epi32(a, count);
@@ -5129,7 +5266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srlv_epi32() {
+    const unsafe fn test_mm256_srlv_epi32() {
         let a = _mm256_set1_epi32(2);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_srlv_epi32(a, count);
@@ -5138,7 +5275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_srlv_epi64() {
+    const unsafe fn test_mm_srlv_epi64() {
         let a = _mm_set1_epi64x(2);
         let count = _mm_set1_epi64x(1);
         let r = _mm_srlv_epi64(a, count);
@@ -5147,7 +5284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srlv_epi64() {
+    const unsafe fn test_mm256_srlv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_srlv_epi64(a, count);
@@ -5163,7 +5300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sub_epi16() {
+    const unsafe fn test_mm256_sub_epi16() {
         let a = _mm256_set1_epi16(4);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_sub_epi16(a, b);
@@ -5171,7 +5308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sub_epi32() {
+    const unsafe fn test_mm256_sub_epi32() {
         let a = _mm256_set1_epi32(4);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_sub_epi32(a, b);
@@ -5179,7 +5316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sub_epi64() {
+    const unsafe fn test_mm256_sub_epi64() {
         let a = _mm256_set1_epi64x(4);
         let b = _mm256_set1_epi64x(2);
         let r = _mm256_sub_epi64(a, b);
@@ -5187,7 +5324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sub_epi8() {
+    const unsafe fn test_mm256_sub_epi8() {
         let a = _mm256_set1_epi8(4);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_sub_epi8(a, b);
@@ -5195,7 +5332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_subs_epi16() {
+    const unsafe fn test_mm256_subs_epi16() {
         let a = _mm256_set1_epi16(4);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_subs_epi16(a, b);
@@ -5203,7 +5340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_subs_epi8() {
+    const unsafe fn test_mm256_subs_epi8() {
         let a = _mm256_set1_epi8(4);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_subs_epi8(a, b);
@@ -5211,7 +5348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_subs_epu16() {
+    const unsafe fn test_mm256_subs_epu16() {
         let a = _mm256_set1_epi16(4);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_subs_epu16(a, b);
@@ -5219,7 +5356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_subs_epu8() {
+    const unsafe fn test_mm256_subs_epu8() {
         let a = _mm256_set1_epi8(4);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_subs_epu8(a, b);
@@ -5227,7 +5364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_xor_si256() {
+    const unsafe fn test_mm256_xor_si256() {
         let a = _mm256_set1_epi8(5);
         let b = _mm256_set1_epi8(3);
         let r = _mm256_xor_si256(a, b);
@@ -5235,7 +5372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_alignr_epi8() {
+    const unsafe fn test_mm256_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5327,7 +5464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_permute4x64_epi64() {
+    const unsafe fn test_mm256_permute4x64_epi64() {
         let a = _mm256_setr_epi64x(100, 200, 300, 400);
         let expected = _mm256_setr_epi64x(400, 100, 200, 100);
         let r = _mm256_permute4x64_epi64::<0b00010011>(a);
@@ -5335,7 +5472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_permute2x128_si256() {
+    const unsafe fn test_mm256_permute2x128_si256() {
         let a = _mm256_setr_epi64x(100, 200, 500, 600);
         let b = _mm256_setr_epi64x(300, 400, 700, 800);
         let r = _mm256_permute2x128_si256::<0b00_01_00_11>(a, b);
@@ -5344,7 +5481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_permute4x64_pd() {
+    const unsafe fn test_mm256_permute4x64_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_permute4x64_pd::<0b00_01_00_11>(a);
         let e = _mm256_setr_pd(4., 1., 2., 1.);
@@ -5702,7 +5839,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_extract_epi8() {
+    const unsafe fn test_mm256_extract_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             -1, 1, 2, 3, 4, 5, 6, 7,
@@ -5717,7 +5854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_extract_epi16() {
+    const unsafe fn test_mm256_extract_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             -1, 1, 2, 3, 4, 5, 6, 7,

From 039aba00eacd23a20ad01092519fa5e8d7261930 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Wed, 1 Oct 2025 11:31:19 +0530
Subject: [PATCH 060/326] Make `fma` functions const

---
 crates/core_arch/src/x86/fma.rs | 161 +++++++++++++++++++-------------
 1 file changed, 97 insertions(+), 64 deletions(-)

diff --git a/crates/core_arch/src/x86/fma.rs b/crates/core_arch/src/x86/fma.rs
index d3988422b9..abf79f4904 100644
--- a/crates/core_arch/src/x86/fma.rs
+++ b/crates/core_arch/src/x86/fma.rs
@@ -33,7 +33,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -45,7 +46,8 @@ pub fn _mm_fmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -57,7 +59,8 @@ pub fn _mm256_fmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -69,7 +72,8 @@ pub fn _mm_fmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -83,7 +87,8 @@ pub fn _mm256_fmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         simd_insert!(
             a,
@@ -103,7 +108,8 @@ pub fn _mm_fmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         simd_insert!(
             a,
@@ -122,7 +128,8 @@ pub fn _mm_fmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -139,7 +146,8 @@ pub fn _mm_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -156,7 +164,8 @@ pub fn _mm256_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmaddsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmaddsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -173,7 +182,8 @@ pub fn _mm_fmaddsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmaddsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmaddsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -189,7 +199,8 @@ pub fn _mm256_fmaddsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -201,7 +212,8 @@ pub fn _mm_fmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -213,7 +225,8 @@ pub fn _mm256_fmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsub213ps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -225,7 +238,8 @@ pub fn _mm_fmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsub213ps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -239,7 +253,8 @@ pub fn _mm256_fmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         simd_insert!(
             a,
@@ -259,7 +274,8 @@ pub fn _mm_fmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         simd_insert!(
             a,
@@ -278,7 +294,8 @@ pub fn _mm_fmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -295,7 +312,8 @@ pub fn _mm_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -312,7 +330,8 @@ pub fn _mm256_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fmsubadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsubadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -329,7 +348,8 @@ pub fn _mm_fmsubadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fmsubadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmsubadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -345,7 +365,8 @@ pub fn _mm256_fmsubadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -357,7 +378,8 @@ pub fn _mm_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -369,7 +391,8 @@ pub fn _mm256_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -381,7 +404,8 @@ pub fn _mm_fnmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fnmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fnmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -395,7 +419,8 @@ pub fn _mm256_fnmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         simd_insert!(
             a,
@@ -415,7 +440,8 @@ pub fn _mm_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         simd_insert!(
             a,
@@ -434,7 +460,8 @@ pub fn _mm_fnmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -447,7 +474,8 @@ pub fn _mm_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -460,7 +488,8 @@ pub fn _mm256_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -473,7 +502,8 @@ pub fn _mm_fnmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_fnmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fnmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -488,7 +518,8 @@ pub fn _mm256_fnmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         simd_insert!(
             a,
@@ -509,7 +540,8 @@ pub fn _mm_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
 #[target_feature(enable = "fma")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_fnmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         simd_insert!(
             a,
@@ -521,13 +553,14 @@ pub fn _mm_fnmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmadd_pd() {
+    const unsafe fn test_mm_fmadd_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -536,7 +569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmadd_pd() {
+    const unsafe fn test_mm256_fmadd_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -545,7 +578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmadd_ps() {
+    const unsafe fn test_mm_fmadd_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -554,7 +587,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmadd_ps() {
+    const unsafe fn test_mm256_fmadd_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -563,7 +596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmadd_sd() {
+    const unsafe fn test_mm_fmadd_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -572,7 +605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmadd_ss() {
+    const unsafe fn test_mm_fmadd_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -581,7 +614,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmaddsub_pd() {
+    const unsafe fn test_mm_fmaddsub_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -590,7 +623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmaddsub_pd() {
+    const unsafe fn test_mm256_fmaddsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -599,7 +632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmaddsub_ps() {
+    const unsafe fn test_mm_fmaddsub_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -608,7 +641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmaddsub_ps() {
+    const unsafe fn test_mm256_fmaddsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -617,7 +650,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmsub_pd() {
+    const unsafe fn test_mm_fmsub_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -626,7 +659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmsub_pd() {
+    const unsafe fn test_mm256_fmsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -635,7 +668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmsub_ps() {
+    const unsafe fn test_mm_fmsub_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -644,7 +677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmsub_ps() {
+    const unsafe fn test_mm256_fmsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -653,7 +686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmsub_sd() {
+    const unsafe fn test_mm_fmsub_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -662,7 +695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmsub_ss() {
+    const unsafe fn test_mm_fmsub_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -671,7 +704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmsubadd_pd() {
+    const unsafe fn test_mm_fmsubadd_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -680,7 +713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmsubadd_pd() {
+    const unsafe fn test_mm256_fmsubadd_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -689,7 +722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fmsubadd_ps() {
+    const unsafe fn test_mm_fmsubadd_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -698,7 +731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fmsubadd_ps() {
+    const unsafe fn test_mm256_fmsubadd_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -707,7 +740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmadd_pd() {
+    const unsafe fn test_mm_fnmadd_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -716,7 +749,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fnmadd_pd() {
+    const unsafe fn test_mm256_fnmadd_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -725,7 +758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmadd_ps() {
+    const unsafe fn test_mm_fnmadd_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -734,7 +767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fnmadd_ps() {
+    const unsafe fn test_mm256_fnmadd_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -743,7 +776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmadd_sd() {
+    const unsafe fn test_mm_fnmadd_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -752,7 +785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmadd_ss() {
+    const unsafe fn test_mm_fnmadd_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -761,7 +794,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmsub_pd() {
+    const unsafe fn test_mm_fnmsub_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -770,7 +803,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fnmsub_pd() {
+    const unsafe fn test_mm256_fnmsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -779,7 +812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmsub_ps() {
+    const unsafe fn test_mm_fnmsub_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -788,7 +821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm256_fnmsub_ps() {
+    const unsafe fn test_mm256_fnmsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -797,7 +830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmsub_sd() {
+    const unsafe fn test_mm_fnmsub_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -806,7 +839,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    unsafe fn test_mm_fnmsub_ss() {
+    const unsafe fn test_mm_fnmsub_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);

From 622823a03592f87ad1cbc528afd819bd9530cec3 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:11:28 +0530
Subject: [PATCH 061/326] Make `avx512f` functions const

---
 crates/core_arch/src/x86/avx512f.rs    | 6306 +++++++++++++++---------
 crates/core_arch/src/x86_64/avx512f.rs | 1305 ++---
 2 files changed, 4751 insertions(+), 2860 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index d6b30d2d7d..f300bf48ef 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -17,7 +17,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm512_abs_epi32(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_epi32(a: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i32x16();
         let r = simd_select::<i32x16, _>(simd_lt(a, i32x16::ZERO), simd_neg(a), a);
@@ -34,7 +35,8 @@ pub fn _mm512_abs_epi32(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm512_mask_abs_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_abs_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, abs, src.as_i32x16()))
@@ -50,7 +52,8 @@ pub fn _mm512_mask_abs_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm512_maskz_abs_epi32(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_abs_epi32(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, abs, i32x16::ZERO))
@@ -64,7 +67,8 @@ pub fn _mm512_maskz_abs_epi32(k: __mmask16, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm256_mask_abs_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_abs_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, abs, src.as_i32x8()))
@@ -78,7 +82,8 @@ pub fn _mm256_mask_abs_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm256_maskz_abs_epi32(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_abs_epi32(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, abs, i32x8::ZERO))
@@ -92,7 +97,8 @@ pub fn _mm256_maskz_abs_epi32(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm_mask_abs_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_abs_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, abs, src.as_i32x4()))
@@ -106,7 +112,8 @@ pub fn _mm_mask_abs_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsd))]
-pub fn _mm_maskz_abs_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_abs_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, abs, i32x4::ZERO))
@@ -120,7 +127,8 @@ pub fn _mm_maskz_abs_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm512_abs_epi64(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_epi64(a: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i64x8();
         let r = simd_select::<i64x8, _>(simd_lt(a, i64x8::ZERO), simd_neg(a), a);
@@ -135,7 +143,8 @@ pub fn _mm512_abs_epi64(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm512_mask_abs_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_abs_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, abs, src.as_i64x8()))
@@ -149,7 +158,8 @@ pub fn _mm512_mask_abs_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm512_maskz_abs_epi64(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_abs_epi64(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, abs, i64x8::ZERO))
@@ -163,7 +173,8 @@ pub fn _mm512_maskz_abs_epi64(k: __mmask8, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm256_abs_epi64(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_abs_epi64(a: __m256i) -> __m256i {
     unsafe {
         let a = a.as_i64x4();
         let r = simd_select::<i64x4, _>(simd_lt(a, i64x4::ZERO), simd_neg(a), a);
@@ -178,7 +189,8 @@ pub fn _mm256_abs_epi64(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm256_mask_abs_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_abs_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, abs, src.as_i64x4()))
@@ -192,7 +204,8 @@ pub fn _mm256_mask_abs_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm256_maskz_abs_epi64(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_abs_epi64(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, abs, i64x4::ZERO))
@@ -206,7 +219,8 @@ pub fn _mm256_maskz_abs_epi64(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm_abs_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_abs_epi64(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i64x2();
         let r = simd_select::<i64x2, _>(simd_lt(a, i64x2::ZERO), simd_neg(a), a);
@@ -221,7 +235,8 @@ pub fn _mm_abs_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm_mask_abs_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_abs_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, abs, src.as_i64x2()))
@@ -235,7 +250,8 @@ pub fn _mm_mask_abs_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsq))]
-pub fn _mm_maskz_abs_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_abs_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, abs, i64x2::ZERO))
@@ -249,7 +265,8 @@ pub fn _mm_maskz_abs_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm512_abs_ps(v2: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_ps(v2: __m512) -> __m512 {
     unsafe { simd_fabs(v2) }
 }
 
@@ -260,7 +277,8 @@ pub fn _mm512_abs_ps(v2: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm512_mask_abs_ps(src: __m512, k: __mmask16, v2: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_abs_ps(src: __m512, k: __mmask16, v2: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, simd_fabs(v2), src) }
 }
 
@@ -271,7 +289,8 @@ pub fn _mm512_mask_abs_ps(src: __m512, k: __mmask16, v2: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm512_abs_pd(v2: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_pd(v2: __m512d) -> __m512d {
     unsafe { simd_fabs(v2) }
 }
 
@@ -282,7 +301,8 @@ pub fn _mm512_abs_pd(v2: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm512_mask_abs_pd(src: __m512d, k: __mmask8, v2: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_abs_pd(src: __m512d, k: __mmask8, v2: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, simd_fabs(v2), src) }
 }
 
@@ -293,7 +313,8 @@ pub fn _mm512_mask_abs_pd(src: __m512d, k: __mmask8, v2: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
-pub fn _mm512_mask_mov_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mov_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i32x16();
         transmute(simd_select_bitmask(k, mov, src.as_i32x16()))
@@ -307,7 +328,8 @@ pub fn _mm512_mask_mov_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
-pub fn _mm512_maskz_mov_epi32(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mov_epi32(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i32x16();
         transmute(simd_select_bitmask(k, mov, i32x16::ZERO))
@@ -321,7 +343,8 @@ pub fn _mm512_maskz_mov_epi32(k: __mmask16, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
-pub fn _mm256_mask_mov_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mov_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i32x8();
         transmute(simd_select_bitmask(k, mov, src.as_i32x8()))
@@ -335,7 +358,8 @@ pub fn _mm256_mask_mov_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
-pub fn _mm256_maskz_mov_epi32(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mov_epi32(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i32x8();
         transmute(simd_select_bitmask(k, mov, i32x8::ZERO))
@@ -349,7 +373,8 @@ pub fn _mm256_maskz_mov_epi32(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
-pub fn _mm_mask_mov_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mov_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i32x4();
         transmute(simd_select_bitmask(k, mov, src.as_i32x4()))
@@ -363,7 +388,8 @@ pub fn _mm_mask_mov_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
-pub fn _mm_maskz_mov_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mov_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i32x4();
         transmute(simd_select_bitmask(k, mov, i32x4::ZERO))
@@ -377,7 +403,8 @@ pub fn _mm_maskz_mov_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
-pub fn _mm512_mask_mov_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mov_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i64x8();
         transmute(simd_select_bitmask(k, mov, src.as_i64x8()))
@@ -391,7 +418,8 @@ pub fn _mm512_mask_mov_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
-pub fn _mm512_maskz_mov_epi64(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mov_epi64(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i64x8();
         transmute(simd_select_bitmask(k, mov, i64x8::ZERO))
@@ -405,7 +433,8 @@ pub fn _mm512_maskz_mov_epi64(k: __mmask8, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
-pub fn _mm256_mask_mov_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mov_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i64x4();
         transmute(simd_select_bitmask(k, mov, src.as_i64x4()))
@@ -419,7 +448,8 @@ pub fn _mm256_mask_mov_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
-pub fn _mm256_maskz_mov_epi64(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mov_epi64(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i64x4();
         transmute(simd_select_bitmask(k, mov, i64x4::ZERO))
@@ -433,7 +463,8 @@ pub fn _mm256_maskz_mov_epi64(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
-pub fn _mm_mask_mov_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mov_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i64x2();
         transmute(simd_select_bitmask(k, mov, src.as_i64x2()))
@@ -447,7 +478,8 @@ pub fn _mm_mask_mov_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
-pub fn _mm_maskz_mov_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mov_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i64x2();
         transmute(simd_select_bitmask(k, mov, i64x2::ZERO))
@@ -461,7 +493,8 @@ pub fn _mm_maskz_mov_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))]
-pub fn _mm512_mask_mov_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mov_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         let mov = a.as_f32x16();
         transmute(simd_select_bitmask(k, mov, src.as_f32x16()))
@@ -475,7 +508,8 @@ pub fn _mm512_mask_mov_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))]
-pub fn _mm512_maskz_mov_ps(k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mov_ps(k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         let mov = a.as_f32x16();
         transmute(simd_select_bitmask(k, mov, f32x16::ZERO))
@@ -489,7 +523,8 @@ pub fn _mm512_maskz_mov_ps(k: __mmask16, a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))]
-pub fn _mm256_mask_mov_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mov_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let mov = a.as_f32x8();
         transmute(simd_select_bitmask(k, mov, src.as_f32x8()))
@@ -503,7 +538,8 @@ pub fn _mm256_mask_mov_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))]
-pub fn _mm256_maskz_mov_ps(k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mov_ps(k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let mov = a.as_f32x8();
         transmute(simd_select_bitmask(k, mov, f32x8::ZERO))
@@ -517,7 +553,8 @@ pub fn _mm256_maskz_mov_ps(k: __mmask8, a: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))]
-pub fn _mm_mask_mov_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mov_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let mov = a.as_f32x4();
         transmute(simd_select_bitmask(k, mov, src.as_f32x4()))
@@ -531,7 +568,8 @@ pub fn _mm_mask_mov_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))]
-pub fn _mm_maskz_mov_ps(k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mov_ps(k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let mov = a.as_f32x4();
         transmute(simd_select_bitmask(k, mov, f32x4::ZERO))
@@ -545,7 +583,8 @@ pub fn _mm_maskz_mov_ps(k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))]
-pub fn _mm512_mask_mov_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mov_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
     unsafe {
         let mov = a.as_f64x8();
         transmute(simd_select_bitmask(k, mov, src.as_f64x8()))
@@ -559,7 +598,8 @@ pub fn _mm512_mask_mov_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))]
-pub fn _mm512_maskz_mov_pd(k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mov_pd(k: __mmask8, a: __m512d) -> __m512d {
     unsafe {
         let mov = a.as_f64x8();
         transmute(simd_select_bitmask(k, mov, f64x8::ZERO))
@@ -573,7 +613,8 @@ pub fn _mm512_maskz_mov_pd(k: __mmask8, a: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))]
-pub fn _mm256_mask_mov_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mov_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
     unsafe {
         let mov = a.as_f64x4();
         transmute(simd_select_bitmask(k, mov, src.as_f64x4()))
@@ -587,7 +628,8 @@ pub fn _mm256_mask_mov_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))]
-pub fn _mm256_maskz_mov_pd(k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mov_pd(k: __mmask8, a: __m256d) -> __m256d {
     unsafe {
         let mov = a.as_f64x4();
         transmute(simd_select_bitmask(k, mov, f64x4::ZERO))
@@ -601,7 +643,8 @@ pub fn _mm256_maskz_mov_pd(k: __mmask8, a: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))]
-pub fn _mm_mask_mov_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mov_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
     unsafe {
         let mov = a.as_f64x2();
         transmute(simd_select_bitmask(k, mov, src.as_f64x2()))
@@ -615,7 +658,8 @@ pub fn _mm_mask_mov_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))]
-pub fn _mm_maskz_mov_pd(k: __mmask8, a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mov_pd(k: __mmask8, a: __m128d) -> __m128d {
     unsafe {
         let mov = a.as_f64x2();
         transmute(simd_select_bitmask(k, mov, f64x2::ZERO))
@@ -629,7 +673,8 @@ pub fn _mm_maskz_mov_pd(k: __mmask8, a: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm512_add_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_add(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -640,7 +685,8 @@ pub fn _mm512_add_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm512_mask_add_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, add, src.as_i32x16()))
@@ -654,7 +700,8 @@ pub fn _mm512_mask_add_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm512_maskz_add_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, add, i32x16::ZERO))
@@ -668,7 +715,8 @@ pub fn _mm512_maskz_add_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm256_mask_add_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, add, src.as_i32x8()))
@@ -682,7 +730,8 @@ pub fn _mm256_mask_add_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm256_maskz_add_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, add, i32x8::ZERO))
@@ -696,7 +745,8 @@ pub fn _mm256_maskz_add_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm_mask_add_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, add, src.as_i32x4()))
@@ -710,7 +760,8 @@ pub fn _mm_mask_add_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddd))]
-pub fn _mm_maskz_add_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, add, i32x4::ZERO))
@@ -724,7 +775,8 @@ pub fn _mm_maskz_add_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm512_add_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_add(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -735,7 +787,8 @@ pub fn _mm512_add_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm512_mask_add_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, add, src.as_i64x8()))
@@ -749,7 +802,8 @@ pub fn _mm512_mask_add_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm512_maskz_add_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, add, i64x8::ZERO))
@@ -763,7 +817,8 @@ pub fn _mm512_maskz_add_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm256_mask_add_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, add, src.as_i64x4()))
@@ -777,7 +832,8 @@ pub fn _mm256_mask_add_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm256_maskz_add_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, add, i64x4::ZERO))
@@ -791,7 +847,8 @@ pub fn _mm256_maskz_add_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm_mask_add_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, add, src.as_i64x2()))
@@ -805,7 +862,8 @@ pub fn _mm_mask_add_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddq))]
-pub fn _mm_maskz_add_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, add, i64x2::ZERO))
@@ -819,7 +877,8 @@ pub fn _mm_maskz_add_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm512_add_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_ps(a: __m512, b: __m512) -> __m512 {
     unsafe { transmute(simd_add(a.as_f32x16(), b.as_f32x16())) }
 }
 
@@ -830,7 +889,8 @@ pub fn _mm512_add_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm512_mask_add_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let add = _mm512_add_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, add, src.as_f32x16()))
@@ -844,7 +904,8 @@ pub fn _mm512_mask_add_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm512_maskz_add_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let add = _mm512_add_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, add, f32x16::ZERO))
@@ -858,7 +919,8 @@ pub fn _mm512_maskz_add_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm256_mask_add_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let add = _mm256_add_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, add, src.as_f32x8()))
@@ -872,7 +934,8 @@ pub fn _mm256_mask_add_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm256_maskz_add_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let add = _mm256_add_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, add, f32x8::ZERO))
@@ -886,7 +949,8 @@ pub fn _mm256_maskz_add_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm_mask_add_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let add = _mm_add_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, add, src.as_f32x4()))
@@ -900,7 +964,8 @@ pub fn _mm_mask_add_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddps))]
-pub fn _mm_maskz_add_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let add = _mm_add_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, add, f32x4::ZERO))
@@ -914,7 +979,8 @@ pub fn _mm_maskz_add_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm512_add_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_add(a.as_f64x8(), b.as_f64x8())) }
 }
 
@@ -925,7 +991,8 @@ pub fn _mm512_add_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm512_mask_add_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let add = _mm512_add_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, add, src.as_f64x8()))
@@ -939,7 +1006,8 @@ pub fn _mm512_mask_add_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm512_maskz_add_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let add = _mm512_add_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, add, f64x8::ZERO))
@@ -953,7 +1021,8 @@ pub fn _mm512_maskz_add_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm256_mask_add_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let add = _mm256_add_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, add, src.as_f64x4()))
@@ -967,7 +1036,8 @@ pub fn _mm256_mask_add_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm256_maskz_add_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let add = _mm256_add_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, add, f64x4::ZERO))
@@ -981,7 +1051,8 @@ pub fn _mm256_maskz_add_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm_mask_add_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let add = _mm_add_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, add, src.as_f64x2()))
@@ -995,7 +1066,8 @@ pub fn _mm_mask_add_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddpd))]
-pub fn _mm_maskz_add_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let add = _mm_add_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, add, f64x2::ZERO))
@@ -1009,7 +1081,8 @@ pub fn _mm_maskz_add_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm512_sub_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_sub(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -1020,7 +1093,8 @@ pub fn _mm512_sub_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm512_mask_sub_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, sub, src.as_i32x16()))
@@ -1034,7 +1108,8 @@ pub fn _mm512_mask_sub_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm512_maskz_sub_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, sub, i32x16::ZERO))
@@ -1048,7 +1123,8 @@ pub fn _mm512_maskz_sub_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm256_mask_sub_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, sub, src.as_i32x8()))
@@ -1062,7 +1138,8 @@ pub fn _mm256_mask_sub_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm256_maskz_sub_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, sub, i32x8::ZERO))
@@ -1076,7 +1153,8 @@ pub fn _mm256_maskz_sub_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm_mask_sub_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, sub, src.as_i32x4()))
@@ -1090,7 +1168,8 @@ pub fn _mm_mask_sub_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubd))]
-pub fn _mm_maskz_sub_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, sub, i32x4::ZERO))
@@ -1104,7 +1183,8 @@ pub fn _mm_maskz_sub_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm512_sub_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_sub(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -1115,7 +1195,8 @@ pub fn _mm512_sub_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm512_mask_sub_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, sub, src.as_i64x8()))
@@ -1129,7 +1210,8 @@ pub fn _mm512_mask_sub_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm512_maskz_sub_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, sub, i64x8::ZERO))
@@ -1143,7 +1225,8 @@ pub fn _mm512_maskz_sub_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm256_mask_sub_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, sub, src.as_i64x4()))
@@ -1157,7 +1240,8 @@ pub fn _mm256_mask_sub_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm256_maskz_sub_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, sub, i64x4::ZERO))
@@ -1171,7 +1255,8 @@ pub fn _mm256_maskz_sub_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm_mask_sub_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, sub, src.as_i64x2()))
@@ -1185,7 +1270,8 @@ pub fn _mm_mask_sub_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubq))]
-pub fn _mm_maskz_sub_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, sub, i64x2::ZERO))
@@ -1199,7 +1285,8 @@ pub fn _mm_maskz_sub_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm512_sub_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_ps(a: __m512, b: __m512) -> __m512 {
     unsafe { transmute(simd_sub(a.as_f32x16(), b.as_f32x16())) }
 }
 
@@ -1210,7 +1297,8 @@ pub fn _mm512_sub_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm512_mask_sub_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let sub = _mm512_sub_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, sub, src.as_f32x16()))
@@ -1224,7 +1312,8 @@ pub fn _mm512_mask_sub_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm512_maskz_sub_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let sub = _mm512_sub_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, sub, f32x16::ZERO))
@@ -1238,7 +1327,8 @@ pub fn _mm512_maskz_sub_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm256_mask_sub_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let sub = _mm256_sub_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, sub, src.as_f32x8()))
@@ -1252,7 +1342,8 @@ pub fn _mm256_mask_sub_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm256_maskz_sub_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let sub = _mm256_sub_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, sub, f32x8::ZERO))
@@ -1266,7 +1357,8 @@ pub fn _mm256_maskz_sub_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm_mask_sub_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let sub = _mm_sub_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, sub, src.as_f32x4()))
@@ -1280,7 +1372,8 @@ pub fn _mm_mask_sub_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubps))]
-pub fn _mm_maskz_sub_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let sub = _mm_sub_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, sub, f32x4::ZERO))
@@ -1294,7 +1387,8 @@ pub fn _mm_maskz_sub_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm512_sub_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_sub(a.as_f64x8(), b.as_f64x8())) }
 }
 
@@ -1305,7 +1399,8 @@ pub fn _mm512_sub_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm512_mask_sub_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let sub = _mm512_sub_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, sub, src.as_f64x8()))
@@ -1319,7 +1414,8 @@ pub fn _mm512_mask_sub_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm512_maskz_sub_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let sub = _mm512_sub_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, sub, f64x8::ZERO))
@@ -1333,7 +1429,8 @@ pub fn _mm512_maskz_sub_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm256_mask_sub_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let sub = _mm256_sub_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, sub, src.as_f64x4()))
@@ -1347,7 +1444,8 @@ pub fn _mm256_mask_sub_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm256_maskz_sub_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let sub = _mm256_sub_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, sub, f64x4::ZERO))
@@ -1361,7 +1459,8 @@ pub fn _mm256_maskz_sub_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm_mask_sub_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let sub = _mm_sub_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, sub, src.as_f64x2()))
@@ -1375,7 +1474,8 @@ pub fn _mm_mask_sub_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubpd))]
-pub fn _mm_maskz_sub_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let sub = _mm_sub_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, sub, f64x2::ZERO))
@@ -1389,7 +1489,8 @@ pub fn _mm_maskz_sub_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm512_mul_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mul_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = simd_cast::<_, i64x8>(simd_cast::<_, i32x8>(a.as_i64x8()));
         let b = simd_cast::<_, i64x8>(simd_cast::<_, i32x8>(b.as_i64x8()));
@@ -1404,7 +1505,8 @@ pub fn _mm512_mul_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm512_mask_mul_epi32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mul_epi32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mul_epi32(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, mul, src.as_i64x8()))
@@ -1418,7 +1520,8 @@ pub fn _mm512_mask_mul_epi32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm512_maskz_mul_epi32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mul_epi32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mul_epi32(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, mul, i64x8::ZERO))
@@ -1432,7 +1535,8 @@ pub fn _mm512_maskz_mul_epi32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm256_mask_mul_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mul_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mul_epi32(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, mul, src.as_i64x4()))
@@ -1446,7 +1550,8 @@ pub fn _mm256_mask_mul_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm256_maskz_mul_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mul_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mul_epi32(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, mul, i64x4::ZERO))
@@ -1460,7 +1565,8 @@ pub fn _mm256_maskz_mul_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm_mask_mul_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mul_epi32(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, mul, src.as_i64x2()))
@@ -1474,7 +1580,8 @@ pub fn _mm_mask_mul_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuldq))]
-pub fn _mm_maskz_mul_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mul_epi32(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, mul, i64x2::ZERO))
@@ -1488,7 +1595,8 @@ pub fn _mm_maskz_mul_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm512_mullo_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mullo_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_mul(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -1499,7 +1607,13 @@ pub fn _mm512_mullo_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm512_mask_mullo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mullo_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let mul = _mm512_mullo_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, mul, src.as_i32x16()))
@@ -1513,7 +1627,8 @@ pub fn _mm512_mask_mullo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm512_maskz_mullo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mullo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mullo_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, mul, i32x16::ZERO))
@@ -1527,7 +1642,8 @@ pub fn _mm512_maskz_mullo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm256_mask_mullo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mullo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mullo_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, mul, src.as_i32x8()))
@@ -1541,7 +1657,8 @@ pub fn _mm256_mask_mullo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm256_maskz_mullo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mullo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mullo_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, mul, i32x8::ZERO))
@@ -1555,7 +1672,8 @@ pub fn _mm256_maskz_mullo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm_mask_mullo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mullo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mullo_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, mul, src.as_i32x4()))
@@ -1569,7 +1687,8 @@ pub fn _mm_mask_mullo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulld))]
-pub fn _mm_maskz_mullo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mullo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mullo_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, mul, i32x4::ZERO))
@@ -1584,7 +1703,8 @@ pub fn _mm_maskz_mullo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mullox_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mullox_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_mul(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -1596,7 +1716,13 @@ pub fn _mm512_mullox_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_mullox_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mullox_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let mul = _mm512_mullox_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, mul, src.as_i64x8()))
@@ -1610,11 +1736,12 @@ pub fn _mm512_mask_mullox_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm512_mul_epu32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mul_epu32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_u64x8();
         let b = b.as_u64x8();
-        let mask = u64x8::splat(u32::MAX.into());
+        let mask = u64x8::splat(u32::MAX as u64);
         transmute(simd_mul(simd_and(a, mask), simd_and(b, mask)))
     }
 }
@@ -1626,7 +1753,8 @@ pub fn _mm512_mul_epu32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm512_mask_mul_epu32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mul_epu32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mul_epu32(a, b).as_u64x8();
         transmute(simd_select_bitmask(k, mul, src.as_u64x8()))
@@ -1640,7 +1768,8 @@ pub fn _mm512_mask_mul_epu32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm512_maskz_mul_epu32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mul_epu32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mul_epu32(a, b).as_u64x8();
         transmute(simd_select_bitmask(k, mul, u64x8::ZERO))
@@ -1654,7 +1783,8 @@ pub fn _mm512_maskz_mul_epu32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm256_mask_mul_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mul_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mul_epu32(a, b).as_u64x4();
         transmute(simd_select_bitmask(k, mul, src.as_u64x4()))
@@ -1668,7 +1798,8 @@ pub fn _mm256_mask_mul_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm256_maskz_mul_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mul_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mul_epu32(a, b).as_u64x4();
         transmute(simd_select_bitmask(k, mul, u64x4::ZERO))
@@ -1682,7 +1813,8 @@ pub fn _mm256_maskz_mul_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm_mask_mul_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mul_epu32(a, b).as_u64x2();
         transmute(simd_select_bitmask(k, mul, src.as_u64x2()))
@@ -1696,7 +1828,8 @@ pub fn _mm_mask_mul_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmuludq))]
-pub fn _mm_maskz_mul_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mul_epu32(a, b).as_u64x2();
         transmute(simd_select_bitmask(k, mul, u64x2::ZERO))
@@ -1710,7 +1843,8 @@ pub fn _mm_maskz_mul_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm512_mul_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mul_ps(a: __m512, b: __m512) -> __m512 {
     unsafe { transmute(simd_mul(a.as_f32x16(), b.as_f32x16())) }
 }
 
@@ -1721,7 +1855,8 @@ pub fn _mm512_mul_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm512_mask_mul_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mul_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let mul = _mm512_mul_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, mul, src.as_f32x16()))
@@ -1735,7 +1870,8 @@ pub fn _mm512_mask_mul_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm512_maskz_mul_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mul_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let mul = _mm512_mul_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, mul, f32x16::ZERO))
@@ -1749,7 +1885,8 @@ pub fn _mm512_maskz_mul_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm256_mask_mul_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mul_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let mul = _mm256_mul_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, mul, src.as_f32x8()))
@@ -1763,7 +1900,8 @@ pub fn _mm256_mask_mul_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm256_maskz_mul_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mul_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let mul = _mm256_mul_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, mul, f32x8::ZERO))
@@ -1777,7 +1915,8 @@ pub fn _mm256_maskz_mul_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm_mask_mul_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mul = _mm_mul_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, mul, src.as_f32x4()))
@@ -1791,7 +1930,8 @@ pub fn _mm_mask_mul_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulps))]
-pub fn _mm_maskz_mul_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mul = _mm_mul_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, mul, f32x4::ZERO))
@@ -1805,7 +1945,8 @@ pub fn _mm_maskz_mul_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm512_mul_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mul_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_mul(a.as_f64x8(), b.as_f64x8())) }
 }
 
@@ -1816,7 +1957,8 @@ pub fn _mm512_mul_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm512_mask_mul_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mul_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let mul = _mm512_mul_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, mul, src.as_f64x8()))
@@ -1830,7 +1972,8 @@ pub fn _mm512_mask_mul_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm512_maskz_mul_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mul_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let mul = _mm512_mul_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, mul, f64x8::ZERO))
@@ -1844,7 +1987,8 @@ pub fn _mm512_maskz_mul_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm256_mask_mul_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mul_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let mul = _mm256_mul_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, mul, src.as_f64x4()))
@@ -1858,7 +2002,8 @@ pub fn _mm256_mask_mul_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm256_maskz_mul_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mul_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let mul = _mm256_mul_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, mul, f64x4::ZERO))
@@ -1872,7 +2017,8 @@ pub fn _mm256_maskz_mul_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm_mask_mul_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mul = _mm_mul_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, mul, src.as_f64x2()))
@@ -1886,7 +2032,8 @@ pub fn _mm_mask_mul_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulpd))]
-pub fn _mm_maskz_mul_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mul = _mm_mul_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, mul, f64x2::ZERO))
@@ -1900,7 +2047,8 @@ pub fn _mm_maskz_mul_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm512_div_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_div_ps(a: __m512, b: __m512) -> __m512 {
     unsafe { transmute(simd_div(a.as_f32x16(), b.as_f32x16())) }
 }
 
@@ -1911,7 +2059,8 @@ pub fn _mm512_div_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm512_mask_div_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_div_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let div = _mm512_div_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, div, src.as_f32x16()))
@@ -1925,7 +2074,8 @@ pub fn _mm512_mask_div_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm512_maskz_div_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_div_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let div = _mm512_div_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, div, f32x16::ZERO))
@@ -1939,7 +2089,8 @@ pub fn _mm512_maskz_div_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm256_mask_div_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_div_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let div = _mm256_div_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, div, src.as_f32x8()))
@@ -1953,7 +2104,8 @@ pub fn _mm256_mask_div_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm256_maskz_div_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_div_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let div = _mm256_div_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, div, f32x8::ZERO))
@@ -1967,7 +2119,8 @@ pub fn _mm256_maskz_div_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm_mask_div_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_div_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let div = _mm_div_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, div, src.as_f32x4()))
@@ -1981,7 +2134,8 @@ pub fn _mm_mask_div_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivps))]
-pub fn _mm_maskz_div_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_div_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let div = _mm_div_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, div, f32x4::ZERO))
@@ -1995,7 +2149,8 @@ pub fn _mm_maskz_div_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm512_div_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_div_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_div(a.as_f64x8(), b.as_f64x8())) }
 }
 
@@ -2006,7 +2161,8 @@ pub fn _mm512_div_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm512_mask_div_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_div_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let div = _mm512_div_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, div, src.as_f64x8()))
@@ -2020,7 +2176,8 @@ pub fn _mm512_mask_div_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm512_maskz_div_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_div_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let div = _mm512_div_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, div, f64x8::ZERO))
@@ -2034,7 +2191,8 @@ pub fn _mm512_maskz_div_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm256_mask_div_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_div_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let div = _mm256_div_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, div, src.as_f64x4()))
@@ -2048,7 +2206,8 @@ pub fn _mm256_mask_div_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm256_maskz_div_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_div_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let div = _mm256_div_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, div, f64x4::ZERO))
@@ -2062,7 +2221,8 @@ pub fn _mm256_maskz_div_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm_mask_div_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_div_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let div = _mm_div_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, div, src.as_f64x2()))
@@ -2076,7 +2236,8 @@ pub fn _mm_mask_div_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivpd))]
-pub fn _mm_maskz_div_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_div_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let div = _mm_div_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, div, f64x2::ZERO))
@@ -2090,7 +2251,8 @@ pub fn _mm_maskz_div_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_i32x16(), b.as_i32x16()).as_m512i() }
 }
 
@@ -2101,7 +2263,8 @@ pub fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm512_mask_max_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, max, src.as_i32x16()))
@@ -2115,7 +2278,8 @@ pub fn _mm512_mask_max_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm512_maskz_max_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, max, i32x16::ZERO))
@@ -2129,7 +2293,8 @@ pub fn _mm512_maskz_max_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm256_mask_max_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, max, src.as_i32x8()))
@@ -2143,7 +2308,8 @@ pub fn _mm256_mask_max_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm256_maskz_max_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, max, i32x8::ZERO))
@@ -2157,7 +2323,8 @@ pub fn _mm256_maskz_max_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm_mask_max_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, max, src.as_i32x4()))
@@ -2171,7 +2338,8 @@ pub fn _mm_mask_max_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsd))]
-pub fn _mm_maskz_max_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, max, i32x4::ZERO))
@@ -2185,7 +2353,8 @@ pub fn _mm_maskz_max_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_i64x8(), b.as_i64x8()).as_m512i() }
 }
 
@@ -2196,7 +2365,8 @@ pub fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm512_mask_max_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, max, src.as_i64x8()))
@@ -2210,7 +2380,8 @@ pub fn _mm512_mask_max_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, max, i64x8::ZERO))
@@ -2224,7 +2395,8 @@ pub fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm256_max_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_i64x4(), b.as_i64x4()).as_m256i() }
 }
 
@@ -2235,7 +2407,8 @@ pub fn _mm256_max_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm256_mask_max_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, max, src.as_i64x4()))
@@ -2249,7 +2422,8 @@ pub fn _mm256_mask_max_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm256_maskz_max_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, max, i64x4::ZERO))
@@ -2263,7 +2437,8 @@ pub fn _mm256_maskz_max_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm_max_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_i64x2(), b.as_i64x2()).as_m128i() }
 }
 
@@ -2274,7 +2449,8 @@ pub fn _mm_max_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm_mask_max_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, max, src.as_i64x2()))
@@ -2288,7 +2464,8 @@ pub fn _mm_mask_max_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsq))]
-pub fn _mm_maskz_max_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, max, i64x2::ZERO))
@@ -2498,7 +2675,8 @@ pub fn _mm_maskz_max_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_u32x16(), b.as_u32x16()).as_m512i() }
 }
 
@@ -2509,7 +2687,8 @@ pub fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm512_mask_max_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu32(a, b).as_u32x16();
         transmute(simd_select_bitmask(k, max, src.as_u32x16()))
@@ -2523,7 +2702,8 @@ pub fn _mm512_mask_max_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm512_maskz_max_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu32(a, b).as_u32x16();
         transmute(simd_select_bitmask(k, max, u32x16::ZERO))
@@ -2537,7 +2717,8 @@ pub fn _mm512_maskz_max_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm256_mask_max_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu32(a, b).as_u32x8();
         transmute(simd_select_bitmask(k, max, src.as_u32x8()))
@@ -2551,7 +2732,8 @@ pub fn _mm256_mask_max_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm256_maskz_max_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu32(a, b).as_u32x8();
         transmute(simd_select_bitmask(k, max, u32x8::ZERO))
@@ -2565,7 +2747,8 @@ pub fn _mm256_maskz_max_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm_mask_max_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu32(a, b).as_u32x4();
         transmute(simd_select_bitmask(k, max, src.as_u32x4()))
@@ -2579,7 +2762,8 @@ pub fn _mm_mask_max_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxud))]
-pub fn _mm_maskz_max_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu32(a, b).as_u32x4();
         transmute(simd_select_bitmask(k, max, u32x4::ZERO))
@@ -2593,7 +2777,8 @@ pub fn _mm_maskz_max_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_u64x8(), b.as_u64x8()).as_m512i() }
 }
 
@@ -2604,7 +2789,8 @@ pub fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm512_mask_max_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu64(a, b).as_u64x8();
         transmute(simd_select_bitmask(k, max, src.as_u64x8()))
@@ -2618,7 +2804,8 @@ pub fn _mm512_mask_max_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu64(a, b).as_u64x8();
         transmute(simd_select_bitmask(k, max, u64x8::ZERO))
@@ -2632,7 +2819,8 @@ pub fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm256_max_epu64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_max_epu64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imax(a.as_u64x4(), b.as_u64x4()).as_m256i() }
 }
 
@@ -2643,7 +2831,8 @@ pub fn _mm256_max_epu64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm256_mask_max_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu64(a, b).as_u64x4();
         transmute(simd_select_bitmask(k, max, src.as_u64x4()))
@@ -2657,7 +2846,8 @@ pub fn _mm256_mask_max_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm256_maskz_max_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu64(a, b).as_u64x4();
         transmute(simd_select_bitmask(k, max, u64x4::ZERO))
@@ -2671,7 +2861,8 @@ pub fn _mm256_maskz_max_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm_max_epu64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_max_epu64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imax(a.as_u64x2(), b.as_u64x2()).as_m128i() }
 }
 
@@ -2682,7 +2873,8 @@ pub fn _mm_max_epu64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm_mask_max_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu64(a, b).as_u64x2();
         transmute(simd_select_bitmask(k, max, src.as_u64x2()))
@@ -2696,7 +2888,8 @@ pub fn _mm_mask_max_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuq))]
-pub fn _mm_maskz_max_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu64(a, b).as_u64x2();
         transmute(simd_select_bitmask(k, max, u64x2::ZERO))
@@ -2710,7 +2903,8 @@ pub fn _mm_maskz_max_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_i32x16(), b.as_i32x16()).as_m512i() }
 }
 
@@ -2721,7 +2915,8 @@ pub fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm512_mask_min_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, min, src.as_i32x16()))
@@ -2735,7 +2930,8 @@ pub fn _mm512_mask_min_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm512_maskz_min_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, min, i32x16::ZERO))
@@ -2749,7 +2945,8 @@ pub fn _mm512_maskz_min_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm256_mask_min_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, min, src.as_i32x8()))
@@ -2763,7 +2960,8 @@ pub fn _mm256_mask_min_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm256_maskz_min_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, min, i32x8::ZERO))
@@ -2777,7 +2975,8 @@ pub fn _mm256_maskz_min_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm_mask_min_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, min, src.as_i32x4()))
@@ -2791,7 +2990,8 @@ pub fn _mm_mask_min_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsd))]
-pub fn _mm_maskz_min_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, min, i32x4::ZERO))
@@ -2805,7 +3005,8 @@ pub fn _mm_maskz_min_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_i64x8(), b.as_i64x8()).as_m512i() }
 }
 
@@ -2816,7 +3017,8 @@ pub fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm512_mask_min_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, min, src.as_i64x8()))
@@ -2830,7 +3032,8 @@ pub fn _mm512_mask_min_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, min, i64x8::ZERO))
@@ -2844,7 +3047,8 @@ pub fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm256_min_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_i64x4(), b.as_i64x4()).as_m256i() }
 }
 
@@ -2855,7 +3059,8 @@ pub fn _mm256_min_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm256_mask_min_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, min, src.as_i64x4()))
@@ -2869,7 +3074,8 @@ pub fn _mm256_mask_min_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm256_maskz_min_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, min, i64x4::ZERO))
@@ -2883,7 +3089,8 @@ pub fn _mm256_maskz_min_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm_min_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_i64x2(), b.as_i64x2()).as_m128i() }
 }
 
@@ -2894,7 +3101,8 @@ pub fn _mm_min_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm_mask_min_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, min, src.as_i64x2()))
@@ -2908,7 +3116,8 @@ pub fn _mm_mask_min_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsq))]
-pub fn _mm_maskz_min_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, min, i64x2::ZERO))
@@ -3118,7 +3327,8 @@ pub fn _mm_maskz_min_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_u32x16(), b.as_u32x16()).as_m512i() }
 }
 
@@ -3129,7 +3339,8 @@ pub fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm512_mask_min_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu32(a, b).as_u32x16();
         transmute(simd_select_bitmask(k, min, src.as_u32x16()))
@@ -3143,7 +3354,8 @@ pub fn _mm512_mask_min_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm512_maskz_min_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu32(a, b).as_u32x16();
         transmute(simd_select_bitmask(k, min, u32x16::ZERO))
@@ -3157,7 +3369,8 @@ pub fn _mm512_maskz_min_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm256_mask_min_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu32(a, b).as_u32x8();
         transmute(simd_select_bitmask(k, min, src.as_u32x8()))
@@ -3171,7 +3384,8 @@ pub fn _mm256_mask_min_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm256_maskz_min_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu32(a, b).as_u32x8();
         transmute(simd_select_bitmask(k, min, u32x8::ZERO))
@@ -3185,7 +3399,8 @@ pub fn _mm256_maskz_min_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm_mask_min_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu32(a, b).as_u32x4();
         transmute(simd_select_bitmask(k, min, src.as_u32x4()))
@@ -3199,7 +3414,8 @@ pub fn _mm_mask_min_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminud))]
-pub fn _mm_maskz_min_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu32(a, b).as_u32x4();
         transmute(simd_select_bitmask(k, min, u32x4::ZERO))
@@ -3213,7 +3429,8 @@ pub fn _mm_maskz_min_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_u64x8(), b.as_u64x8()).as_m512i() }
 }
 
@@ -3224,7 +3441,8 @@ pub fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm512_mask_min_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu64(a, b).as_u64x8();
         transmute(simd_select_bitmask(k, min, src.as_u64x8()))
@@ -3238,7 +3456,8 @@ pub fn _mm512_mask_min_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu64(a, b).as_u64x8();
         transmute(simd_select_bitmask(k, min, u64x8::ZERO))
@@ -3252,7 +3471,8 @@ pub fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm256_min_epu64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_min_epu64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { simd_imin(a.as_u64x4(), b.as_u64x4()).as_m256i() }
 }
 
@@ -3263,7 +3483,8 @@ pub fn _mm256_min_epu64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm256_mask_min_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu64(a, b).as_u64x4();
         transmute(simd_select_bitmask(k, min, src.as_u64x4()))
@@ -3277,7 +3498,8 @@ pub fn _mm256_mask_min_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm256_maskz_min_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu64(a, b).as_u64x4();
         transmute(simd_select_bitmask(k, min, u64x4::ZERO))
@@ -3291,7 +3513,8 @@ pub fn _mm256_maskz_min_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm_min_epu64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_min_epu64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_u64x2(), b.as_u64x2()).as_m128i() }
 }
 
@@ -3302,7 +3525,8 @@ pub fn _mm_min_epu64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm_mask_min_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu64(a, b).as_u64x2();
         transmute(simd_select_bitmask(k, min, src.as_u64x2()))
@@ -3316,7 +3540,8 @@ pub fn _mm_mask_min_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuq))]
-pub fn _mm_maskz_min_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu64(a, b).as_u64x2();
         transmute(simd_select_bitmask(k, min, u64x2::ZERO))
@@ -3484,7 +3709,8 @@ pub fn _mm_maskz_sqrt_pd(k: __mmask8, a: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm512_fmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -3495,7 +3721,8 @@ pub fn _mm512_fmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm512_mask_fmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ps(a, b, c), a) }
 }
 
@@ -3506,7 +3733,8 @@ pub fn _mm512_mask_fmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm512_maskz_fmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ps(a, b, c), _mm512_setzero_ps()) }
 }
 
@@ -3517,7 +3745,8 @@ pub fn _mm512_maskz_fmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm512_mask3_fmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ps(a, b, c), c) }
 }
 
@@ -3528,7 +3757,8 @@ pub fn _mm512_mask3_fmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm256_mask_fmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ps(a, b, c), a) }
 }
 
@@ -3539,7 +3769,8 @@ pub fn _mm256_mask_fmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm256_maskz_fmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ps(a, b, c), _mm256_setzero_ps()) }
 }
 
@@ -3550,7 +3781,8 @@ pub fn _mm256_maskz_fmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm256_mask3_fmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ps(a, b, c), c) }
 }
 
@@ -3561,7 +3793,8 @@ pub fn _mm256_mask3_fmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm_mask_fmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ps(a, b, c), a) }
 }
 
@@ -3572,7 +3805,8 @@ pub fn _mm_mask_fmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm_maskz_fmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ps(a, b, c), _mm_setzero_ps()) }
 }
 
@@ -3583,7 +3817,8 @@ pub fn _mm_maskz_fmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
-pub fn _mm_mask3_fmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ps(a, b, c), c) }
 }
 
@@ -3594,7 +3829,8 @@ pub fn _mm_mask3_fmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm512_fmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -3605,7 +3841,8 @@ pub fn _mm512_fmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm512_mask_fmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_pd(a, b, c), a) }
 }
 
@@ -3616,7 +3853,8 @@ pub fn _mm512_mask_fmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm512_maskz_fmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_pd(a, b, c), _mm512_setzero_pd()) }
 }
 
@@ -3627,7 +3865,8 @@ pub fn _mm512_maskz_fmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm512_mask3_fmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_pd(a, b, c), c) }
 }
 
@@ -3638,7 +3877,8 @@ pub fn _mm512_mask3_fmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm256_mask_fmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_pd(a, b, c), a) }
 }
 
@@ -3649,7 +3889,8 @@ pub fn _mm256_mask_fmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm256_maskz_fmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_pd(a, b, c), _mm256_setzero_pd()) }
 }
 
@@ -3660,7 +3901,8 @@ pub fn _mm256_maskz_fmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm256_mask3_fmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_pd(a, b, c), c) }
 }
 
@@ -3671,7 +3913,8 @@ pub fn _mm256_mask3_fmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm_mask_fmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmadd_pd(a, b, c), a) }
 }
 
@@ -3682,7 +3925,8 @@ pub fn _mm_mask_fmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm_maskz_fmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmadd_pd(a, b, c), _mm_setzero_pd()) }
 }
 
@@ -3693,7 +3937,8 @@ pub fn _mm_maskz_fmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
-pub fn _mm_mask3_fmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmadd_pd(a, b, c), c) }
 }
 
@@ -3704,7 +3949,8 @@ pub fn _mm_mask3_fmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm512_fmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -3715,7 +3961,8 @@ pub fn _mm512_fmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm512_mask_fmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ps(a, b, c), a) }
 }
 
@@ -3726,7 +3973,8 @@ pub fn _mm512_mask_fmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm512_maskz_fmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ps(a, b, c), _mm512_setzero_ps()) }
 }
 
@@ -3737,7 +3985,8 @@ pub fn _mm512_maskz_fmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm512_mask3_fmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ps(a, b, c), c) }
 }
 
@@ -3748,7 +3997,8 @@ pub fn _mm512_mask3_fmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm256_mask_fmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ps(a, b, c), a) }
 }
 
@@ -3759,7 +4009,8 @@ pub fn _mm256_mask_fmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm256_maskz_fmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ps(a, b, c), _mm256_setzero_ps()) }
 }
 
@@ -3770,7 +4021,8 @@ pub fn _mm256_maskz_fmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm256_mask3_fmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ps(a, b, c), c) }
 }
 
@@ -3781,7 +4033,8 @@ pub fn _mm256_mask3_fmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm_mask_fmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ps(a, b, c), a) }
 }
 
@@ -3792,7 +4045,8 @@ pub fn _mm_mask_fmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm_maskz_fmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ps(a, b, c), _mm_setzero_ps()) }
 }
 
@@ -3803,7 +4057,8 @@ pub fn _mm_maskz_fmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
-pub fn _mm_mask3_fmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ps(a, b, c), c) }
 }
 
@@ -3814,7 +4069,8 @@ pub fn _mm_mask3_fmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm512_fmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -3825,7 +4081,8 @@ pub fn _mm512_fmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm512_mask_fmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_pd(a, b, c), a) }
 }
 
@@ -3836,7 +4093,8 @@ pub fn _mm512_mask_fmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm512_maskz_fmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_pd(a, b, c), _mm512_setzero_pd()) }
 }
 
@@ -3847,7 +4105,8 @@ pub fn _mm512_maskz_fmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm512_mask3_fmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_pd(a, b, c), c) }
 }
 
@@ -3858,7 +4117,8 @@ pub fn _mm512_mask3_fmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm256_mask_fmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_pd(a, b, c), a) }
 }
 
@@ -3869,7 +4129,8 @@ pub fn _mm256_mask_fmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm256_maskz_fmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_pd(a, b, c), _mm256_setzero_pd()) }
 }
 
@@ -3880,7 +4141,8 @@ pub fn _mm256_maskz_fmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm256_mask3_fmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_pd(a, b, c), c) }
 }
 
@@ -3891,7 +4153,8 @@ pub fn _mm256_mask3_fmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm_mask_fmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmsub_pd(a, b, c), a) }
 }
 
@@ -3902,7 +4165,8 @@ pub fn _mm_mask_fmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm_maskz_fmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmsub_pd(a, b, c), _mm_setzero_pd()) }
 }
 
@@ -3913,7 +4177,8 @@ pub fn _mm_maskz_fmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
-pub fn _mm_mask3_fmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmsub_pd(a, b, c), c) }
 }
 
@@ -3924,7 +4189,8 @@ pub fn _mm_mask3_fmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm512_fmaddsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmaddsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -3943,7 +4209,8 @@ pub fn _mm512_fmaddsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm512_mask_fmaddsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmaddsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ps(a, b, c), a) }
 }
 
@@ -3954,7 +4221,8 @@ pub fn _mm512_mask_fmaddsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm512_maskz_fmaddsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmaddsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ps(a, b, c), _mm512_setzero_ps()) }
 }
 
@@ -3965,7 +4233,8 @@ pub fn _mm512_maskz_fmaddsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm512_mask3_fmaddsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmaddsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ps(a, b, c), c) }
 }
 
@@ -3976,7 +4245,8 @@ pub fn _mm512_mask3_fmaddsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm256_mask_fmaddsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmaddsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ps(a, b, c), a) }
 }
 
@@ -3987,7 +4257,8 @@ pub fn _mm256_mask_fmaddsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm256_maskz_fmaddsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmaddsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ps(a, b, c), _mm256_setzero_ps()) }
 }
 
@@ -3998,7 +4269,8 @@ pub fn _mm256_maskz_fmaddsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm256_mask3_fmaddsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmaddsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ps(a, b, c), c) }
 }
 
@@ -4009,7 +4281,8 @@ pub fn _mm256_mask3_fmaddsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm_mask_fmaddsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmaddsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ps(a, b, c), a) }
 }
 
@@ -4020,7 +4293,8 @@ pub fn _mm_mask_fmaddsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm_maskz_fmaddsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmaddsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ps(a, b, c), _mm_setzero_ps()) }
 }
 
@@ -4031,7 +4305,8 @@ pub fn _mm_maskz_fmaddsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
-pub fn _mm_mask3_fmaddsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmaddsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ps(a, b, c), c) }
 }
 
@@ -4042,7 +4317,8 @@ pub fn _mm_mask3_fmaddsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm512_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -4057,7 +4333,8 @@ pub fn _mm512_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm512_mask_fmaddsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmaddsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_pd(a, b, c), a) }
 }
 
@@ -4068,7 +4345,8 @@ pub fn _mm512_mask_fmaddsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm512_maskz_fmaddsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmaddsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_pd(a, b, c), _mm512_setzero_pd()) }
 }
 
@@ -4079,7 +4357,8 @@ pub fn _mm512_maskz_fmaddsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm512_mask3_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_pd(a, b, c), c) }
 }
 
@@ -4090,7 +4369,8 @@ pub fn _mm512_mask3_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm256_mask_fmaddsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmaddsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_pd(a, b, c), a) }
 }
 
@@ -4101,7 +4381,8 @@ pub fn _mm256_mask_fmaddsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm256_maskz_fmaddsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmaddsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_pd(a, b, c), _mm256_setzero_pd()) }
 }
 
@@ -4112,7 +4393,8 @@ pub fn _mm256_maskz_fmaddsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm256_mask3_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_pd(a, b, c), c) }
 }
 
@@ -4123,7 +4405,8 @@ pub fn _mm256_mask3_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm_mask_fmaddsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmaddsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_pd(a, b, c), a) }
 }
 
@@ -4134,7 +4417,8 @@ pub fn _mm_mask_fmaddsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm_maskz_fmaddsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmaddsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_pd(a, b, c), _mm_setzero_pd()) }
 }
 
@@ -4145,7 +4429,8 @@ pub fn _mm_maskz_fmaddsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
-pub fn _mm_mask3_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_pd(a, b, c), c) }
 }
 
@@ -4156,7 +4441,8 @@ pub fn _mm_mask3_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm512_fmsubadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmsubadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -4175,7 +4461,8 @@ pub fn _mm512_fmsubadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm512_mask_fmsubadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmsubadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ps(a, b, c), a) }
 }
 
@@ -4186,7 +4473,8 @@ pub fn _mm512_mask_fmsubadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm512_maskz_fmsubadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmsubadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ps(a, b, c), _mm512_setzero_ps()) }
 }
 
@@ -4197,7 +4485,8 @@ pub fn _mm512_maskz_fmsubadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm512_mask3_fmsubadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmsubadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ps(a, b, c), c) }
 }
 
@@ -4208,7 +4497,8 @@ pub fn _mm512_mask3_fmsubadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm256_mask_fmsubadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmsubadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ps(a, b, c), a) }
 }
 
@@ -4219,7 +4509,8 @@ pub fn _mm256_mask_fmsubadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm256_maskz_fmsubadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmsubadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ps(a, b, c), _mm256_setzero_ps()) }
 }
 
@@ -4230,7 +4521,8 @@ pub fn _mm256_maskz_fmsubadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm256_mask3_fmsubadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmsubadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ps(a, b, c), c) }
 }
 
@@ -4241,7 +4533,8 @@ pub fn _mm256_mask3_fmsubadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm_mask_fmsubadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsubadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ps(a, b, c), a) }
 }
 
@@ -4252,7 +4545,8 @@ pub fn _mm_mask_fmsubadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm_maskz_fmsubadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsubadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ps(a, b, c), _mm_setzero_ps()) }
 }
 
@@ -4263,7 +4557,8 @@ pub fn _mm_maskz_fmsubadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
-pub fn _mm_mask3_fmsubadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsubadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ps(a, b, c), c) }
 }
 
@@ -4274,7 +4569,8 @@ pub fn _mm_mask3_fmsubadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm512_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -4289,7 +4585,8 @@ pub fn _mm512_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm512_mask_fmsubadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmsubadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_pd(a, b, c), a) }
 }
 
@@ -4300,7 +4597,8 @@ pub fn _mm512_mask_fmsubadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm512_maskz_fmsubadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmsubadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_pd(a, b, c), _mm512_setzero_pd()) }
 }
 
@@ -4311,7 +4609,8 @@ pub fn _mm512_maskz_fmsubadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm512_mask3_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_pd(a, b, c), c) }
 }
 
@@ -4322,7 +4621,8 @@ pub fn _mm512_mask3_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm256_mask_fmsubadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmsubadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_pd(a, b, c), a) }
 }
 
@@ -4333,7 +4633,8 @@ pub fn _mm256_mask_fmsubadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm256_maskz_fmsubadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmsubadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_pd(a, b, c), _mm256_setzero_pd()) }
 }
 
@@ -4344,7 +4645,8 @@ pub fn _mm256_maskz_fmsubadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm256_mask3_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_pd(a, b, c), c) }
 }
 
@@ -4355,7 +4657,8 @@ pub fn _mm256_mask3_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm_mask_fmsubadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsubadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_pd(a, b, c), a) }
 }
 
@@ -4366,7 +4669,8 @@ pub fn _mm_mask_fmsubadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm_maskz_fmsubadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsubadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_pd(a, b, c), _mm_setzero_pd()) }
 }
 
@@ -4377,7 +4681,8 @@ pub fn _mm_maskz_fmsubadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
-pub fn _mm_mask3_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_pd(a, b, c), c) }
 }
 
@@ -4388,7 +4693,8 @@ pub fn _mm_mask3_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm512_fnmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fnmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -4399,7 +4705,8 @@ pub fn _mm512_fnmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm512_mask_fnmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fnmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ps(a, b, c), a) }
 }
 
@@ -4410,7 +4717,8 @@ pub fn _mm512_mask_fnmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm512_maskz_fnmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fnmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ps(a, b, c), _mm512_setzero_ps()) }
 }
 
@@ -4421,7 +4729,8 @@ pub fn _mm512_maskz_fnmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm512_mask3_fnmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fnmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ps(a, b, c), c) }
 }
 
@@ -4432,7 +4741,8 @@ pub fn _mm512_mask3_fnmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm256_mask_fnmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fnmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ps(a, b, c), a) }
 }
 
@@ -4443,7 +4753,8 @@ pub fn _mm256_mask_fnmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm256_maskz_fnmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fnmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ps(a, b, c), _mm256_setzero_ps()) }
 }
 
@@ -4454,7 +4765,8 @@ pub fn _mm256_maskz_fnmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm256_mask3_fnmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fnmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ps(a, b, c), c) }
 }
 
@@ -4465,7 +4777,8 @@ pub fn _mm256_mask3_fnmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm_mask_fnmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ps(a, b, c), a) }
 }
 
@@ -4476,7 +4789,8 @@ pub fn _mm_mask_fnmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm_maskz_fnmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ps(a, b, c), _mm_setzero_ps()) }
 }
 
@@ -4487,7 +4801,8 @@ pub fn _mm_maskz_fnmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
-pub fn _mm_mask3_fnmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ps(a, b, c), c) }
 }
 
@@ -4498,7 +4813,8 @@ pub fn _mm_mask3_fnmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm512_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -4509,7 +4825,8 @@ pub fn _mm512_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm512_mask_fnmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fnmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_pd(a, b, c), a) }
 }
 
@@ -4520,7 +4837,8 @@ pub fn _mm512_mask_fnmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm512_maskz_fnmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fnmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_pd(a, b, c), _mm512_setzero_pd()) }
 }
 
@@ -4531,7 +4849,8 @@ pub fn _mm512_maskz_fnmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm512_mask3_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_pd(a, b, c), c) }
 }
 
@@ -4542,7 +4861,8 @@ pub fn _mm512_mask3_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm256_mask_fnmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fnmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_pd(a, b, c), a) }
 }
 
@@ -4553,7 +4873,8 @@ pub fn _mm256_mask_fnmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm256_maskz_fnmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fnmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_pd(a, b, c), _mm256_setzero_pd()) }
 }
 
@@ -4564,7 +4885,8 @@ pub fn _mm256_maskz_fnmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm256_mask3_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_pd(a, b, c), c) }
 }
 
@@ -4575,7 +4897,8 @@ pub fn _mm256_mask3_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm_mask_fnmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_pd(a, b, c), a) }
 }
 
@@ -4586,7 +4909,8 @@ pub fn _mm_mask_fnmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm_maskz_fnmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_pd(a, b, c), _mm_setzero_pd()) }
 }
 
@@ -4597,7 +4921,8 @@ pub fn _mm_maskz_fnmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
-pub fn _mm_mask3_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_pd(a, b, c), c) }
 }
 
@@ -4608,7 +4933,8 @@ pub fn _mm_mask3_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm512_fnmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fnmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -4619,7 +4945,8 @@ pub fn _mm512_fnmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm512_mask_fnmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fnmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ps(a, b, c), a) }
 }
 
@@ -4630,7 +4957,8 @@ pub fn _mm512_mask_fnmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm512_maskz_fnmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fnmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ps(a, b, c), _mm512_setzero_ps()) }
 }
 
@@ -4641,7 +4969,8 @@ pub fn _mm512_maskz_fnmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm512_mask3_fnmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fnmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ps(a, b, c), c) }
 }
 
@@ -4652,7 +4981,8 @@ pub fn _mm512_mask3_fnmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm256_mask_fnmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fnmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ps(a, b, c), a) }
 }
 
@@ -4663,7 +4993,8 @@ pub fn _mm256_mask_fnmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm256_maskz_fnmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fnmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ps(a, b, c), _mm256_setzero_ps()) }
 }
 
@@ -4674,7 +5005,8 @@ pub fn _mm256_maskz_fnmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm256_mask3_fnmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fnmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ps(a, b, c), c) }
 }
 
@@ -4685,7 +5017,8 @@ pub fn _mm256_mask3_fnmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm_mask_fnmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ps(a, b, c), a) }
 }
 
@@ -4696,7 +5029,8 @@ pub fn _mm_mask_fnmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm_maskz_fnmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ps(a, b, c), _mm_setzero_ps()) }
 }
 
@@ -4707,7 +5041,8 @@ pub fn _mm_maskz_fnmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
-pub fn _mm_mask3_fnmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ps(a, b, c), c) }
 }
 
@@ -4718,7 +5053,8 @@ pub fn _mm_mask3_fnmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm512_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -4729,7 +5065,8 @@ pub fn _mm512_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm512_mask_fnmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fnmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_pd(a, b, c), a) }
 }
 
@@ -4740,7 +5077,8 @@ pub fn _mm512_mask_fnmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) ->
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm512_maskz_fnmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fnmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_pd(a, b, c), _mm512_setzero_pd()) }
 }
 
@@ -4751,7 +5089,8 @@ pub fn _mm512_maskz_fnmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm512_mask3_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_pd(a, b, c), c) }
 }
 
@@ -4762,7 +5101,8 @@ pub fn _mm512_mask3_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm256_mask_fnmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fnmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_pd(a, b, c), a) }
 }
 
@@ -4773,7 +5113,8 @@ pub fn _mm256_mask_fnmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm256_maskz_fnmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fnmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_pd(a, b, c), _mm256_setzero_pd()) }
 }
 
@@ -4784,7 +5125,8 @@ pub fn _mm256_maskz_fnmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm256_mask3_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_pd(a, b, c), c) }
 }
 
@@ -4795,7 +5137,8 @@ pub fn _mm256_mask3_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm_mask_fnmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_pd(a, b, c), a) }
 }
 
@@ -4806,7 +5149,8 @@ pub fn _mm_mask_fnmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm_maskz_fnmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_pd(a, b, c), _mm_setzero_pd()) }
 }
 
@@ -4817,7 +5161,8 @@ pub fn _mm_maskz_fnmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
-pub fn _mm_mask3_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_pd(a, b, c), c) }
 }
 
@@ -11446,7 +11791,8 @@ pub fn _mm512_mask_cvtpd_pslo(src: __m512, k: __mmask8, v2: __m512d) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm512_cvtepi8_epi32(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi8_epi32(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_i8x16();
         transmute::<i32x16, _>(simd_cast(a))
@@ -11460,7 +11806,8 @@ pub fn _mm512_cvtepi8_epi32(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm512_mask_cvtepi8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi8_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, src.as_i32x16()))
@@ -11474,7 +11821,8 @@ pub fn _mm512_mask_cvtepi8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm512_maskz_cvtepi8_epi32(k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi8_epi32(k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi8_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, i32x16::ZERO))
@@ -11488,7 +11836,8 @@ pub fn _mm512_maskz_cvtepi8_epi32(k: __mmask16, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm256_mask_cvtepi8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi8_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, src.as_i32x8()))
@@ -11502,7 +11851,8 @@ pub fn _mm256_mask_cvtepi8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm256_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi8_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, i32x8::ZERO))
@@ -11516,7 +11866,8 @@ pub fn _mm256_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm_mask_cvtepi8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi8_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, src.as_i32x4()))
@@ -11530,7 +11881,8 @@ pub fn _mm_mask_cvtepi8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbd))]
-pub fn _mm_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi8_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, i32x4::ZERO))
@@ -11544,7 +11896,8 @@ pub fn _mm_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm512_cvtepi8_epi64(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi8_epi64(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_i8x16();
         let v64: i8x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -11559,7 +11912,8 @@ pub fn _mm512_cvtepi8_epi64(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm512_mask_cvtepi8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi8_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, src.as_i64x8()))
@@ -11573,7 +11927,8 @@ pub fn _mm512_mask_cvtepi8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m51
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm512_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi8_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, i64x8::ZERO))
@@ -11587,7 +11942,8 @@ pub fn _mm512_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm256_mask_cvtepi8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi8_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, src.as_i64x4()))
@@ -11601,7 +11957,8 @@ pub fn _mm256_mask_cvtepi8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm256_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi8_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, i64x4::ZERO))
@@ -11615,7 +11972,8 @@ pub fn _mm256_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm_mask_cvtepi8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi8_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, src.as_i64x2()))
@@ -11629,7 +11987,8 @@ pub fn _mm_mask_cvtepi8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbq))]
-pub fn _mm_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi8_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, i64x2::ZERO))
@@ -11643,7 +12002,8 @@ pub fn _mm_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm512_cvtepu8_epi32(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu8_epi32(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_u8x16();
         transmute::<i32x16, _>(simd_cast(a))
@@ -11657,7 +12017,8 @@ pub fn _mm512_cvtepu8_epi32(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm512_mask_cvtepu8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu8_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, src.as_i32x16()))
@@ -11671,7 +12032,8 @@ pub fn _mm512_mask_cvtepu8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm512_maskz_cvtepu8_epi32(k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu8_epi32(k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu8_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, i32x16::ZERO))
@@ -11685,7 +12047,8 @@ pub fn _mm512_maskz_cvtepu8_epi32(k: __mmask16, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm256_mask_cvtepu8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu8_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, src.as_i32x8()))
@@ -11699,7 +12062,8 @@ pub fn _mm256_mask_cvtepu8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm256_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu8_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, i32x8::ZERO))
@@ -11713,7 +12077,8 @@ pub fn _mm256_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm_mask_cvtepu8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu8_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, src.as_i32x4()))
@@ -11727,7 +12092,8 @@ pub fn _mm_mask_cvtepu8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbd))]
-pub fn _mm_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu8_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, i32x4::ZERO))
@@ -11741,7 +12107,8 @@ pub fn _mm_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm512_cvtepu8_epi64(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu8_epi64(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_u8x16();
         let v64: u8x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -11756,7 +12123,8 @@ pub fn _mm512_cvtepu8_epi64(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm512_mask_cvtepu8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu8_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, src.as_i64x8()))
@@ -11770,7 +12138,8 @@ pub fn _mm512_mask_cvtepu8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m51
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm512_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu8_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, i64x8::ZERO))
@@ -11784,7 +12153,8 @@ pub fn _mm512_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm256_mask_cvtepu8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu8_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, src.as_i64x4()))
@@ -11798,7 +12168,8 @@ pub fn _mm256_mask_cvtepu8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm256_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu8_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, i64x4::ZERO))
@@ -11812,7 +12183,8 @@ pub fn _mm256_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm_mask_cvtepu8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu8_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, src.as_i64x2()))
@@ -11826,7 +12198,8 @@ pub fn _mm_mask_cvtepu8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbq))]
-pub fn _mm_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu8_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, i64x2::ZERO))
@@ -11840,7 +12213,8 @@ pub fn _mm_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm512_cvtepi16_epi32(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi16_epi32(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_i16x16();
         transmute::<i32x16, _>(simd_cast(a))
@@ -11854,7 +12228,8 @@ pub fn _mm512_cvtepi16_epi32(a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm512_mask_cvtepi16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi16_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, src.as_i32x16()))
@@ -11868,7 +12243,8 @@ pub fn _mm512_mask_cvtepi16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm512_maskz_cvtepi16_epi32(k: __mmask16, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi16_epi32(k: __mmask16, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi16_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, i32x16::ZERO))
@@ -11882,7 +12258,8 @@ pub fn _mm512_maskz_cvtepi16_epi32(k: __mmask16, a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm256_mask_cvtepi16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi16_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, src.as_i32x8()))
@@ -11896,7 +12273,8 @@ pub fn _mm256_mask_cvtepi16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm256_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi16_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, i32x8::ZERO))
@@ -11910,7 +12288,8 @@ pub fn _mm256_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm_mask_cvtepi16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi16_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, src.as_i32x4()))
@@ -11924,7 +12303,8 @@ pub fn _mm_mask_cvtepi16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwd))]
-pub fn _mm_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi16_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, i32x4::ZERO))
@@ -11938,7 +12318,8 @@ pub fn _mm_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm512_cvtepi16_epi64(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi16_epi64(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_i16x8();
         transmute::<i64x8, _>(simd_cast(a))
@@ -11952,7 +12333,8 @@ pub fn _mm512_cvtepi16_epi64(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm512_mask_cvtepi16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi16_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, src.as_i64x8()))
@@ -11966,7 +12348,8 @@ pub fn _mm512_mask_cvtepi16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm512_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi16_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, i64x8::ZERO))
@@ -11980,7 +12363,8 @@ pub fn _mm512_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm256_mask_cvtepi16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi16_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, src.as_i64x4()))
@@ -11994,7 +12378,8 @@ pub fn _mm256_mask_cvtepi16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm256_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi16_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, i64x4::ZERO))
@@ -12008,7 +12393,8 @@ pub fn _mm256_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm_mask_cvtepi16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi16_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, src.as_i64x2()))
@@ -12022,7 +12408,8 @@ pub fn _mm_mask_cvtepi16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxwq))]
-pub fn _mm_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi16_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, i64x2::ZERO))
@@ -12036,7 +12423,8 @@ pub fn _mm_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm512_cvtepu16_epi32(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu16_epi32(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_u16x16();
         transmute::<i32x16, _>(simd_cast(a))
@@ -12050,7 +12438,8 @@ pub fn _mm512_cvtepu16_epi32(a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm512_mask_cvtepu16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu16_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, src.as_i32x16()))
@@ -12064,7 +12453,8 @@ pub fn _mm512_mask_cvtepu16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm512_maskz_cvtepu16_epi32(k: __mmask16, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu16_epi32(k: __mmask16, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu16_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, convert, i32x16::ZERO))
@@ -12078,7 +12468,8 @@ pub fn _mm512_maskz_cvtepu16_epi32(k: __mmask16, a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm256_mask_cvtepu16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu16_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, src.as_i32x8()))
@@ -12092,7 +12483,8 @@ pub fn _mm256_mask_cvtepu16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm256_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu16_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, i32x8::ZERO))
@@ -12106,7 +12498,8 @@ pub fn _mm256_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm_mask_cvtepu16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu16_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, src.as_i32x4()))
@@ -12120,7 +12513,8 @@ pub fn _mm_mask_cvtepu16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwd))]
-pub fn _mm_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu16_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, i32x4::ZERO))
@@ -12134,7 +12528,8 @@ pub fn _mm_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm512_cvtepu16_epi64(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu16_epi64(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_u16x8();
         transmute::<i64x8, _>(simd_cast(a))
@@ -12148,7 +12543,8 @@ pub fn _mm512_cvtepu16_epi64(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm512_mask_cvtepu16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu16_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, src.as_i64x8()))
@@ -12162,7 +12558,8 @@ pub fn _mm512_mask_cvtepu16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm512_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu16_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, i64x8::ZERO))
@@ -12176,7 +12573,8 @@ pub fn _mm512_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm256_mask_cvtepu16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu16_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, src.as_i64x4()))
@@ -12190,7 +12588,8 @@ pub fn _mm256_mask_cvtepu16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm256_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu16_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, i64x4::ZERO))
@@ -12204,7 +12603,8 @@ pub fn _mm256_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm_mask_cvtepu16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu16_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, src.as_i64x2()))
@@ -12218,7 +12618,8 @@ pub fn _mm_mask_cvtepu16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxwq))]
-pub fn _mm_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu16_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, i64x2::ZERO))
@@ -12232,7 +12633,8 @@ pub fn _mm_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm512_cvtepi32_epi64(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi32_epi64(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_i32x8();
         transmute::<i64x8, _>(simd_cast(a))
@@ -12246,7 +12648,8 @@ pub fn _mm512_cvtepi32_epi64(a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm512_mask_cvtepi32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi32_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, src.as_i64x8()))
@@ -12260,7 +12663,8 @@ pub fn _mm512_mask_cvtepi32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm512_maskz_cvtepi32_epi64(k: __mmask8, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi32_epi64(k: __mmask8, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi32_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, i64x8::ZERO))
@@ -12274,7 +12678,8 @@ pub fn _mm512_maskz_cvtepi32_epi64(k: __mmask8, a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm256_mask_cvtepi32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi32_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, src.as_i64x4()))
@@ -12288,7 +12693,8 @@ pub fn _mm256_mask_cvtepi32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm256_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi32_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, i64x4::ZERO))
@@ -12302,7 +12708,8 @@ pub fn _mm256_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm_mask_cvtepi32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi32_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, src.as_i64x2()))
@@ -12316,7 +12723,8 @@ pub fn _mm_mask_cvtepi32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxdq))]
-pub fn _mm_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi32_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, i64x2::ZERO))
@@ -12330,7 +12738,8 @@ pub fn _mm_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm512_cvtepu32_epi64(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu32_epi64(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_u32x8();
         transmute::<i64x8, _>(simd_cast(a))
@@ -12344,7 +12753,8 @@ pub fn _mm512_cvtepu32_epi64(a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm512_mask_cvtepu32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu32_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, src.as_i64x8()))
@@ -12358,7 +12768,8 @@ pub fn _mm512_mask_cvtepu32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm512_maskz_cvtepu32_epi64(k: __mmask8, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu32_epi64(k: __mmask8, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu32_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, convert, i64x8::ZERO))
@@ -12372,7 +12783,8 @@ pub fn _mm512_maskz_cvtepu32_epi64(k: __mmask8, a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm256_mask_cvtepu32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu32_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, src.as_i64x4()))
@@ -12386,7 +12798,8 @@ pub fn _mm256_mask_cvtepu32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm256_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu32_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, convert, i64x4::ZERO))
@@ -12400,7 +12813,8 @@ pub fn _mm256_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm_mask_cvtepu32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu32_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, src.as_i64x2()))
@@ -12414,7 +12828,8 @@ pub fn _mm_mask_cvtepu32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxdq))]
-pub fn _mm_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu32_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, convert, i64x2::ZERO))
@@ -12428,7 +12843,8 @@ pub fn _mm_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm512_cvtepi32_ps(a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi32_ps(a: __m512i) -> __m512 {
     unsafe {
         let a = a.as_i32x16();
         transmute::<f32x16, _>(simd_cast(a))
@@ -12442,7 +12858,8 @@ pub fn _mm512_cvtepi32_ps(a: __m512i) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm512_mask_cvtepi32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 {
     unsafe {
         let convert = _mm512_cvtepi32_ps(a).as_f32x16();
         transmute(simd_select_bitmask(k, convert, src.as_f32x16()))
@@ -12456,7 +12873,8 @@ pub fn _mm512_mask_cvtepi32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm512_maskz_cvtepi32_ps(k: __mmask16, a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi32_ps(k: __mmask16, a: __m512i) -> __m512 {
     unsafe {
         let convert = _mm512_cvtepi32_ps(a).as_f32x16();
         transmute(simd_select_bitmask(k, convert, f32x16::ZERO))
@@ -12470,7 +12888,8 @@ pub fn _mm512_maskz_cvtepi32_ps(k: __mmask16, a: __m512i) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm256_mask_cvtepi32_ps(src: __m256, k: __mmask8, a: __m256i) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi32_ps(src: __m256, k: __mmask8, a: __m256i) -> __m256 {
     unsafe {
         let convert = _mm256_cvtepi32_ps(a).as_f32x8();
         transmute(simd_select_bitmask(k, convert, src.as_f32x8()))
@@ -12484,7 +12903,8 @@ pub fn _mm256_mask_cvtepi32_ps(src: __m256, k: __mmask8, a: __m256i) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm256_maskz_cvtepi32_ps(k: __mmask8, a: __m256i) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi32_ps(k: __mmask8, a: __m256i) -> __m256 {
     unsafe {
         let convert = _mm256_cvtepi32_ps(a).as_f32x8();
         transmute(simd_select_bitmask(k, convert, f32x8::ZERO))
@@ -12498,7 +12918,8 @@ pub fn _mm256_maskz_cvtepi32_ps(k: __mmask8, a: __m256i) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm_mask_cvtepi32_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi32_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 {
     unsafe {
         let convert = _mm_cvtepi32_ps(a).as_f32x4();
         transmute(simd_select_bitmask(k, convert, src.as_f32x4()))
@@ -12512,7 +12933,8 @@ pub fn _mm_mask_cvtepi32_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2ps))]
-pub fn _mm_maskz_cvtepi32_ps(k: __mmask8, a: __m128i) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi32_ps(k: __mmask8, a: __m128i) -> __m128 {
     unsafe {
         let convert = _mm_cvtepi32_ps(a).as_f32x4();
         transmute(simd_select_bitmask(k, convert, f32x4::ZERO))
@@ -12526,7 +12948,8 @@ pub fn _mm_maskz_cvtepi32_ps(k: __mmask8, a: __m128i) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm512_cvtepi32_pd(a: __m256i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi32_pd(a: __m256i) -> __m512d {
     unsafe {
         let a = a.as_i32x8();
         transmute::<f64x8, _>(simd_cast(a))
@@ -12540,7 +12963,8 @@ pub fn _mm512_cvtepi32_pd(a: __m256i) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm512_mask_cvtepi32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d {
     unsafe {
         let convert = _mm512_cvtepi32_pd(a).as_f64x8();
         transmute(simd_select_bitmask(k, convert, src.as_f64x8()))
@@ -12554,7 +12978,8 @@ pub fn _mm512_mask_cvtepi32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm512_maskz_cvtepi32_pd(k: __mmask8, a: __m256i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi32_pd(k: __mmask8, a: __m256i) -> __m512d {
     unsafe {
         let convert = _mm512_cvtepi32_pd(a).as_f64x8();
         transmute(simd_select_bitmask(k, convert, f64x8::ZERO))
@@ -12568,7 +12993,8 @@ pub fn _mm512_maskz_cvtepi32_pd(k: __mmask8, a: __m256i) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm256_mask_cvtepi32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d {
     unsafe {
         let convert = _mm256_cvtepi32_pd(a).as_f64x4();
         transmute(simd_select_bitmask(k, convert, src.as_f64x4()))
@@ -12582,7 +13008,8 @@ pub fn _mm256_mask_cvtepi32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm256_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m256d {
     unsafe {
         let convert = _mm256_cvtepi32_pd(a).as_f64x4();
         transmute(simd_select_bitmask(k, convert, f64x4::ZERO))
@@ -12596,7 +13023,8 @@ pub fn _mm256_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm_mask_cvtepi32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d {
     unsafe {
         let convert = _mm_cvtepi32_pd(a).as_f64x2();
         transmute(simd_select_bitmask(k, convert, src.as_f64x2()))
@@ -12610,7 +13038,8 @@ pub fn _mm_mask_cvtepi32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m128d {
     unsafe {
         let convert = _mm_cvtepi32_pd(a).as_f64x2();
         transmute(simd_select_bitmask(k, convert, f64x2::ZERO))
@@ -12624,7 +13053,8 @@ pub fn _mm_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2ps))]
-pub fn _mm512_cvtepu32_ps(a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu32_ps(a: __m512i) -> __m512 {
     unsafe {
         let a = a.as_u32x16();
         transmute::<f32x16, _>(simd_cast(a))
@@ -12638,7 +13068,8 @@ pub fn _mm512_cvtepu32_ps(a: __m512i) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2ps))]
-pub fn _mm512_mask_cvtepu32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 {
     unsafe {
         let convert = _mm512_cvtepu32_ps(a).as_f32x16();
         transmute(simd_select_bitmask(k, convert, src.as_f32x16()))
@@ -12652,7 +13083,8 @@ pub fn _mm512_mask_cvtepu32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2ps))]
-pub fn _mm512_maskz_cvtepu32_ps(k: __mmask16, a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu32_ps(k: __mmask16, a: __m512i) -> __m512 {
     unsafe {
         let convert = _mm512_cvtepu32_ps(a).as_f32x16();
         transmute(simd_select_bitmask(k, convert, f32x16::ZERO))
@@ -12666,7 +13098,8 @@ pub fn _mm512_maskz_cvtepu32_ps(k: __mmask16, a: __m512i) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm512_cvtepu32_pd(a: __m256i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu32_pd(a: __m256i) -> __m512d {
     unsafe {
         let a = a.as_u32x8();
         transmute::<f64x8, _>(simd_cast(a))
@@ -12680,7 +13113,8 @@ pub fn _mm512_cvtepu32_pd(a: __m256i) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm512_mask_cvtepu32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d {
     unsafe {
         let convert = _mm512_cvtepu32_pd(a).as_f64x8();
         transmute(simd_select_bitmask(k, convert, src.as_f64x8()))
@@ -12694,7 +13128,8 @@ pub fn _mm512_mask_cvtepu32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm512_maskz_cvtepu32_pd(k: __mmask8, a: __m256i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu32_pd(k: __mmask8, a: __m256i) -> __m512d {
     unsafe {
         let convert = _mm512_cvtepu32_pd(a).as_f64x8();
         transmute(simd_select_bitmask(k, convert, f64x8::ZERO))
@@ -12708,7 +13143,8 @@ pub fn _mm512_maskz_cvtepu32_pd(k: __mmask8, a: __m256i) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm256_cvtepu32_pd(a: __m128i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepu32_pd(a: __m128i) -> __m256d {
     unsafe {
         let a = a.as_u32x4();
         transmute::<f64x4, _>(simd_cast(a))
@@ -12722,7 +13158,8 @@ pub fn _mm256_cvtepu32_pd(a: __m128i) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm256_mask_cvtepu32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d {
     unsafe {
         let convert = _mm256_cvtepu32_pd(a).as_f64x4();
         transmute(simd_select_bitmask(k, convert, src.as_f64x4()))
@@ -12736,7 +13173,8 @@ pub fn _mm256_mask_cvtepu32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm256_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m256d {
     unsafe {
         let convert = _mm256_cvtepu32_pd(a).as_f64x4();
         transmute(simd_select_bitmask(k, convert, f64x4::ZERO))
@@ -12750,7 +13188,8 @@ pub fn _mm256_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm_cvtepu32_pd(a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepu32_pd(a: __m128i) -> __m128d {
     unsafe {
         let a = a.as_u32x4();
         let u64: u32x2 = simd_shuffle!(a, a, [0, 1]);
@@ -12765,7 +13204,8 @@ pub fn _mm_cvtepu32_pd(a: __m128i) -> __m128d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm_mask_cvtepu32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d {
     unsafe {
         let convert = _mm_cvtepu32_pd(a).as_f64x2();
         transmute(simd_select_bitmask(k, convert, src.as_f64x2()))
@@ -12779,7 +13219,8 @@ pub fn _mm_mask_cvtepu32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m128d {
     unsafe {
         let convert = _mm_cvtepu32_pd(a).as_f64x2();
         transmute(simd_select_bitmask(k, convert, f64x2::ZERO))
@@ -12793,7 +13234,8 @@ pub fn _mm_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm512_cvtepi32lo_pd(v2: __m512i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi32lo_pd(v2: __m512i) -> __m512d {
     unsafe {
         let v2 = v2.as_i32x16();
         let v256: i32x8 = simd_shuffle!(v2, v2, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -12808,7 +13250,8 @@ pub fn _mm512_cvtepi32lo_pd(v2: __m512i) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtdq2pd))]
-pub fn _mm512_mask_cvtepi32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m512d {
     unsafe {
         let convert = _mm512_cvtepi32lo_pd(v2).as_f64x8();
         transmute(simd_select_bitmask(k, convert, src.as_f64x8()))
@@ -12822,7 +13265,8 @@ pub fn _mm512_mask_cvtepi32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm512_cvtepu32lo_pd(v2: __m512i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu32lo_pd(v2: __m512i) -> __m512d {
     unsafe {
         let v2 = v2.as_u32x16();
         let v256: u32x8 = simd_shuffle!(v2, v2, [0, 1, 2, 3, 4, 5, 6, 7]);
@@ -12837,7 +13281,8 @@ pub fn _mm512_cvtepu32lo_pd(v2: __m512i) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtudq2pd))]
-pub fn _mm512_mask_cvtepu32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m512d {
     unsafe {
         let convert = _mm512_cvtepu32lo_pd(v2).as_f64x8();
         transmute(simd_select_bitmask(k, convert, src.as_f64x8()))
@@ -12851,7 +13296,8 @@ pub fn _mm512_mask_cvtepu32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdw))]
-pub fn _mm512_cvtepi32_epi16(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi32_epi16(a: __m512i) -> __m256i {
     unsafe {
         let a = a.as_i32x16();
         transmute::<i16x16, _>(simd_cast(a))
@@ -12865,7 +13311,8 @@ pub fn _mm512_cvtepi32_epi16(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdw))]
-pub fn _mm512_mask_cvtepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m256i {
     unsafe {
         let convert = _mm512_cvtepi32_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, convert, src.as_i16x16()))
@@ -12879,7 +13326,8 @@ pub fn _mm512_mask_cvtepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdw))]
-pub fn _mm512_maskz_cvtepi32_epi16(k: __mmask16, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi32_epi16(k: __mmask16, a: __m512i) -> __m256i {
     unsafe {
         let convert = _mm512_cvtepi32_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, convert, i16x16::ZERO))
@@ -12893,7 +13341,8 @@ pub fn _mm512_maskz_cvtepi32_epi16(k: __mmask16, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdw))]
-pub fn _mm256_cvtepi32_epi16(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi32_epi16(a: __m256i) -> __m128i {
     unsafe {
         let a = a.as_i32x8();
         transmute::<i16x8, _>(simd_cast(a))
@@ -12907,7 +13356,8 @@ pub fn _mm256_cvtepi32_epi16(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdw))]
-pub fn _mm256_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i {
     unsafe {
         let convert = _mm256_cvtepi32_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, src.as_i16x8()))
@@ -12921,7 +13371,8 @@ pub fn _mm256_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m1
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdw))]
-pub fn _mm256_maskz_cvtepi32_epi16(k: __mmask8, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi32_epi16(k: __mmask8, a: __m256i) -> __m128i {
     unsafe {
         let convert = _mm256_cvtepi32_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, i16x8::ZERO))
@@ -12968,7 +13419,8 @@ pub fn _mm_maskz_cvtepi32_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdb))]
-pub fn _mm512_cvtepi32_epi8(a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi32_epi8(a: __m512i) -> __m128i {
     unsafe {
         let a = a.as_i32x16();
         transmute::<i8x16, _>(simd_cast(a))
@@ -12982,7 +13434,8 @@ pub fn _mm512_cvtepi32_epi8(a: __m512i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdb))]
-pub fn _mm512_mask_cvtepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m128i {
     unsafe {
         let convert = _mm512_cvtepi32_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, convert, src.as_i8x16()))
@@ -12996,7 +13449,8 @@ pub fn _mm512_mask_cvtepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovdb))]
-pub fn _mm512_maskz_cvtepi32_epi8(k: __mmask16, a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi32_epi8(k: __mmask16, a: __m512i) -> __m128i {
     unsafe {
         let convert = _mm512_cvtepi32_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, convert, i8x16::ZERO))
@@ -13076,7 +13530,8 @@ pub fn _mm_maskz_cvtepi32_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqd))]
-pub fn _mm512_cvtepi64_epi32(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi64_epi32(a: __m512i) -> __m256i {
     unsafe {
         let a = a.as_i64x8();
         transmute::<i32x8, _>(simd_cast(a))
@@ -13090,7 +13545,8 @@ pub fn _mm512_cvtepi64_epi32(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqd))]
-pub fn _mm512_mask_cvtepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m256i {
     unsafe {
         let convert = _mm512_cvtepi64_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, src.as_i32x8()))
@@ -13104,7 +13560,8 @@ pub fn _mm512_mask_cvtepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m2
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqd))]
-pub fn _mm512_maskz_cvtepi64_epi32(k: __mmask8, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi64_epi32(k: __mmask8, a: __m512i) -> __m256i {
     unsafe {
         let convert = _mm512_cvtepi64_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, convert, i32x8::ZERO))
@@ -13118,7 +13575,8 @@ pub fn _mm512_maskz_cvtepi64_epi32(k: __mmask8, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqd))]
-pub fn _mm256_cvtepi64_epi32(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi64_epi32(a: __m256i) -> __m128i {
     unsafe {
         let a = a.as_i64x4();
         transmute::<i32x4, _>(simd_cast(a))
@@ -13132,7 +13590,8 @@ pub fn _mm256_cvtepi64_epi32(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqd))]
-pub fn _mm256_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m128i {
     unsafe {
         let convert = _mm256_cvtepi64_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, src.as_i32x4()))
@@ -13146,7 +13605,8 @@ pub fn _mm256_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m1
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqd))]
-pub fn _mm256_maskz_cvtepi64_epi32(k: __mmask8, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi64_epi32(k: __mmask8, a: __m256i) -> __m128i {
     unsafe {
         let convert = _mm256_cvtepi64_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, convert, i32x4::ZERO))
@@ -13193,7 +13653,8 @@ pub fn _mm_maskz_cvtepi64_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqw))]
-pub fn _mm512_cvtepi64_epi16(a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi64_epi16(a: __m512i) -> __m128i {
     unsafe {
         let a = a.as_i64x8();
         transmute::<i16x8, _>(simd_cast(a))
@@ -13207,7 +13668,8 @@ pub fn _mm512_cvtepi64_epi16(a: __m512i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqw))]
-pub fn _mm512_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m128i {
     unsafe {
         let convert = _mm512_cvtepi64_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, src.as_i16x8()))
@@ -13221,7 +13683,8 @@ pub fn _mm512_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovqw))]
-pub fn _mm512_maskz_cvtepi64_epi16(k: __mmask8, a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi64_epi16(k: __mmask8, a: __m512i) -> __m128i {
     unsafe {
         let convert = _mm512_cvtepi64_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, i16x8::ZERO))
@@ -16178,7 +16641,8 @@ pub fn _mm_maskz_cvttpd_epu32(k: __mmask8, a: __m128d) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxorps))]
-pub fn _mm512_setzero_pd() -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setzero_pd() -> __m512d {
     // All-0 is a properly initialized __m512d
     unsafe { const { mem::zeroed() } }
 }
@@ -16190,7 +16654,8 @@ pub fn _mm512_setzero_pd() -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxorps))]
-pub fn _mm512_setzero_ps() -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setzero_ps() -> __m512 {
     // All-0 is a properly initialized __m512
     unsafe { const { mem::zeroed() } }
 }
@@ -16202,7 +16667,8 @@ pub fn _mm512_setzero_ps() -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxorps))]
-pub fn _mm512_setzero() -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setzero() -> __m512 {
     // All-0 is a properly initialized __m512
     unsafe { const { mem::zeroed() } }
 }
@@ -16214,7 +16680,8 @@ pub fn _mm512_setzero() -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxorps))]
-pub fn _mm512_setzero_si512() -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setzero_si512() -> __m512i {
     // All-0 is a properly initialized __m512i
     unsafe { const { mem::zeroed() } }
 }
@@ -16226,7 +16693,8 @@ pub fn _mm512_setzero_si512() -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxorps))]
-pub fn _mm512_setzero_epi32() -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setzero_epi32() -> __m512i {
     // All-0 is a properly initialized __m512i
     unsafe { const { mem::zeroed() } }
 }
@@ -16238,7 +16706,8 @@ pub fn _mm512_setzero_epi32() -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr_epi32(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr_epi32(
     e15: i32,
     e14: i32,
     e13: i32,
@@ -16270,7 +16739,8 @@ pub fn _mm512_setr_epi32(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set_epi8(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_epi8(
     e63: i8,
     e62: i8,
     e61: i8,
@@ -16353,7 +16823,8 @@ pub fn _mm512_set_epi8(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set_epi16(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_epi16(
     e31: i16,
     e30: i16,
     e29: i16,
@@ -16402,7 +16873,8 @@ pub fn _mm512_set_epi16(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i {
     _mm512_set_epi32(d, c, b, a, d, c, b, a, d, c, b, a, d, c, b, a)
 }
 
@@ -16412,7 +16884,8 @@ pub fn _mm512_set4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 {
     _mm512_set_ps(d, c, b, a, d, c, b, a, d, c, b, a, d, c, b, a)
 }
 
@@ -16422,7 +16895,8 @@ pub fn _mm512_set4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d {
     _mm512_set_pd(d, c, b, a, d, c, b, a)
 }
 
@@ -16432,7 +16906,8 @@ pub fn _mm512_set4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i {
     _mm512_set_epi32(a, b, c, d, a, b, c, d, a, b, c, d, a, b, c, d)
 }
 
@@ -16442,7 +16917,8 @@ pub fn _mm512_setr4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 {
     _mm512_set_ps(a, b, c, d, a, b, c, d, a, b, c, d, a, b, c, d)
 }
 
@@ -16452,7 +16928,8 @@ pub fn _mm512_setr4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d {
     _mm512_set_pd(a, b, c, d, a, b, c, d)
 }
 
@@ -16462,7 +16939,8 @@ pub fn _mm512_setr4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set_epi64(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_epi64(
     e0: i64,
     e1: i64,
     e2: i64,
@@ -16481,7 +16959,8 @@ pub fn _mm512_set_epi64(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr_epi64(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr_epi64(
     e0: i64,
     e1: i64,
     e2: i64,
@@ -19006,7 +19485,8 @@ pub fn _mm_maskz_expand_pd(k: __mmask8, a: __m128d) -> __m128d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_rol_epi32<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_rol_epi32<const IMM8: i32>(a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_rolv_epi32(a, _mm512_set1_epi32(IMM8))
 }
@@ -19019,7 +19499,12 @@ pub fn _mm512_rol_epi32<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_rol_epi32<const IMM8: i32>(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_rol_epi32<const IMM8: i32>(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_rolv_epi32(src, k, a, _mm512_set1_epi32(IMM8))
 }
@@ -19032,7 +19517,8 @@ pub fn _mm512_mask_rol_epi32<const IMM8: i32>(src: __m512i, k: __mmask16, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_rol_epi32<const IMM8: i32>(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_rol_epi32<const IMM8: i32>(k: __mmask16, a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_maskz_rolv_epi32(k, a, _mm512_set1_epi32(IMM8))
 }
@@ -19045,7 +19531,8 @@ pub fn _mm512_maskz_rol_epi32<const IMM8: i32>(k: __mmask16, a: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_rol_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_rol_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_rolv_epi32(a, _mm256_set1_epi32(IMM8))
 }
@@ -19058,7 +19545,12 @@ pub fn _mm256_rol_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_rol_epi32<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_rol_epi32<const IMM8: i32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_rolv_epi32(src, k, a, _mm256_set1_epi32(IMM8))
 }
@@ -19071,7 +19563,8 @@ pub fn _mm256_mask_rol_epi32<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_rol_epi32<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_rol_epi32<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_maskz_rolv_epi32(k, a, _mm256_set1_epi32(IMM8))
 }
@@ -19084,7 +19577,8 @@ pub fn _mm256_maskz_rol_epi32<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm_rol_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_rol_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_rolv_epi32(a, _mm_set1_epi32(IMM8))
 }
@@ -19097,7 +19591,8 @@ pub fn _mm_rol_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_rol_epi32<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_rol_epi32<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_rolv_epi32(src, k, a, _mm_set1_epi32(IMM8))
 }
@@ -19110,7 +19605,8 @@ pub fn _mm_mask_rol_epi32<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_rol_epi32<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_rol_epi32<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_maskz_rolv_epi32(k, a, _mm_set1_epi32(IMM8))
 }
@@ -19123,7 +19619,8 @@ pub fn _mm_maskz_rol_epi32<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_ror_epi32<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_ror_epi32<const IMM8: i32>(a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_rorv_epi32(a, _mm512_set1_epi32(IMM8))
 }
@@ -19136,7 +19633,12 @@ pub fn _mm512_ror_epi32<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_ror_epi32<const IMM8: i32>(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_ror_epi32<const IMM8: i32>(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_rorv_epi32(src, k, a, _mm512_set1_epi32(IMM8))
 }
@@ -19149,7 +19651,8 @@ pub fn _mm512_mask_ror_epi32<const IMM8: i32>(src: __m512i, k: __mmask16, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_ror_epi32<const IMM8: i32>(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_ror_epi32<const IMM8: i32>(k: __mmask16, a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_maskz_rorv_epi32(k, a, _mm512_set1_epi32(IMM8))
 }
@@ -19162,7 +19665,8 @@ pub fn _mm512_maskz_ror_epi32<const IMM8: i32>(k: __mmask16, a: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_ror_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_ror_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_rorv_epi32(a, _mm256_set1_epi32(IMM8))
 }
@@ -19175,7 +19679,12 @@ pub fn _mm256_ror_epi32<const IMM8: i32>(a: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_ror_epi32<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_ror_epi32<const IMM8: i32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_rorv_epi32(src, k, a, _mm256_set1_epi32(IMM8))
 }
@@ -19188,7 +19697,8 @@ pub fn _mm256_mask_ror_epi32<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_ror_epi32<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_ror_epi32<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_maskz_rorv_epi32(k, a, _mm256_set1_epi32(IMM8))
 }
@@ -19201,7 +19711,8 @@ pub fn _mm256_maskz_ror_epi32<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm_ror_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_ror_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_rorv_epi32(a, _mm_set1_epi32(IMM8))
 }
@@ -19214,7 +19725,8 @@ pub fn _mm_ror_epi32<const IMM8: i32>(a: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_ror_epi32<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_ror_epi32<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_rorv_epi32(src, k, a, _mm_set1_epi32(IMM8))
 }
@@ -19227,7 +19739,8 @@ pub fn _mm_mask_ror_epi32<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_ror_epi32<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_ror_epi32<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_maskz_rorv_epi32(k, a, _mm_set1_epi32(IMM8))
 }
@@ -19240,7 +19753,8 @@ pub fn _mm_maskz_ror_epi32<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_rol_epi64<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_rol_epi64<const IMM8: i32>(a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_rolv_epi64(a, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -19253,7 +19767,12 @@ pub fn _mm512_rol_epi64<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_rol_epi64<const IMM8: i32>(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_rol_epi64<const IMM8: i32>(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_rolv_epi64(src, k, a, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -19266,7 +19785,8 @@ pub fn _mm512_mask_rol_epi64<const IMM8: i32>(src: __m512i, k: __mmask8, a: __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_maskz_rolv_epi64(k, a, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -19279,7 +19799,8 @@ pub fn _mm512_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m51
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_rol_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_rol_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_rolv_epi64(a, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -19292,7 +19813,12 @@ pub fn _mm256_rol_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_rol_epi64<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_rol_epi64<const IMM8: i32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_rolv_epi64(src, k, a, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -19305,7 +19831,8 @@ pub fn _mm256_mask_rol_epi64<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_maskz_rolv_epi64(k, a, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -19318,7 +19845,8 @@ pub fn _mm256_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm_rol_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_rol_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_rolv_epi64(a, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -19331,7 +19859,8 @@ pub fn _mm_rol_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_rol_epi64<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_rol_epi64<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_rolv_epi64(src, k, a, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -19344,7 +19873,8 @@ pub fn _mm_mask_rol_epi64<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_maskz_rolv_epi64(k, a, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -19357,7 +19887,8 @@ pub fn _mm_maskz_rol_epi64<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_ror_epi64<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_ror_epi64<const IMM8: i32>(a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_rorv_epi64(a, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -19370,7 +19901,12 @@ pub fn _mm512_ror_epi64<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_ror_epi64<const IMM8: i32>(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_ror_epi64<const IMM8: i32>(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_rorv_epi64(src, k, a, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -19383,7 +19919,8 @@ pub fn _mm512_mask_ror_epi64<const IMM8: i32>(src: __m512i, k: __mmask8, a: __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_maskz_rorv_epi64(k, a, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -19396,7 +19933,8 @@ pub fn _mm512_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m51
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_ror_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_ror_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_rorv_epi64(a, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -19409,7 +19947,12 @@ pub fn _mm256_ror_epi64<const IMM8: i32>(a: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_ror_epi64<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_ror_epi64<const IMM8: i32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_rorv_epi64(src, k, a, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -19422,7 +19965,8 @@ pub fn _mm256_mask_ror_epi64<const IMM8: i32>(src: __m256i, k: __mmask8, a: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_maskz_rorv_epi64(k, a, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -19435,7 +19979,8 @@ pub fn _mm256_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm_ror_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_ror_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_rorv_epi64(a, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -19448,7 +19993,8 @@ pub fn _mm_ror_epi64<const IMM8: i32>(a: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_ror_epi64<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_ror_epi64<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_rorv_epi64(src, k, a, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -19461,7 +20007,8 @@ pub fn _mm_mask_ror_epi64<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_maskz_rorv_epi64(k, a, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -19474,7 +20021,8 @@ pub fn _mm_maskz_ror_epi64<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_slli_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_slli_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19493,7 +20041,12 @@ pub fn _mm512_slli_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_slli_epi32<const IMM8: u32>(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_slli_epi32<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 32 {
@@ -19513,7 +20066,8 @@ pub fn _mm512_mask_slli_epi32<const IMM8: u32>(src: __m512i, k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_slli_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_slli_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19533,7 +20087,12 @@ pub fn _mm512_maskz_slli_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_slli_epi32<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_slli_epi32<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 32 {
@@ -19553,7 +20112,8 @@ pub fn _mm256_mask_slli_epi32<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_slli_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_slli_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19573,7 +20133,12 @@ pub fn _mm256_maskz_slli_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_slli_epi32<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_slli_epi32<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 32 {
@@ -19593,7 +20158,8 @@ pub fn _mm_mask_slli_epi32<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_slli_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_slli_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19613,7 +20179,8 @@ pub fn _mm_maskz_slli_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_srli_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srli_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19632,7 +20199,12 @@ pub fn _mm512_srli_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_srli_epi32<const IMM8: u32>(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srli_epi32<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 32 {
@@ -19652,7 +20224,8 @@ pub fn _mm512_mask_srli_epi32<const IMM8: u32>(src: __m512i, k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_srli_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srli_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19672,7 +20245,12 @@ pub fn _mm512_maskz_srli_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_srli_epi32<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srli_epi32<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 32 {
@@ -19692,7 +20270,8 @@ pub fn _mm256_mask_srli_epi32<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_srli_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srli_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19712,7 +20291,12 @@ pub fn _mm256_maskz_srli_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_srli_epi32<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srli_epi32<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 32 {
@@ -19732,7 +20316,8 @@ pub fn _mm_mask_srli_epi32<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_srli_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srli_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 32 {
@@ -19752,7 +20337,8 @@ pub fn _mm_maskz_srli_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_slli_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_slli_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19771,7 +20357,12 @@ pub fn _mm512_slli_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_slli_epi64<const IMM8: u32>(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_slli_epi64<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 64 {
@@ -19791,7 +20382,8 @@ pub fn _mm512_mask_slli_epi64<const IMM8: u32>(src: __m512i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19811,7 +20403,12 @@ pub fn _mm512_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_slli_epi64<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_slli_epi64<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 64 {
@@ -19831,7 +20428,8 @@ pub fn _mm256_mask_slli_epi64<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19851,7 +20449,12 @@ pub fn _mm256_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_slli_epi64<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_slli_epi64<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 64 {
@@ -19871,7 +20474,8 @@ pub fn _mm_mask_slli_epi64<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19891,7 +20495,8 @@ pub fn _mm_maskz_slli_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_srli_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srli_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19910,7 +20515,12 @@ pub fn _mm512_srli_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_srli_epi64<const IMM8: u32>(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srli_epi64<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 64 {
@@ -19930,7 +20540,8 @@ pub fn _mm512_mask_srli_epi64<const IMM8: u32>(src: __m512i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19950,7 +20561,12 @@ pub fn _mm512_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_srli_epi64<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srli_epi64<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 64 {
@@ -19970,7 +20586,8 @@ pub fn _mm256_mask_srli_epi64<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -19990,7 +20607,12 @@ pub fn _mm256_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_srli_epi64<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srli_epi64<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = if IMM8 >= 64 {
@@ -20010,7 +20632,8 @@ pub fn _mm_mask_srli_epi64<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srli_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 64 {
@@ -20622,7 +21245,8 @@ pub fn _mm_maskz_sra_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_srai_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srai_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         transmute(simd_shr(a.as_i32x16(), i32x16::splat(IMM8.min(31) as i32)))
@@ -20637,7 +21261,12 @@ pub fn _mm512_srai_epi32<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_srai_epi32<const IMM8: u32>(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srai_epi32<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = simd_shr(a.as_i32x16(), i32x16::splat(IMM8.min(31) as i32));
@@ -20653,7 +21282,8 @@ pub fn _mm512_mask_srai_epi32<const IMM8: u32>(src: __m512i, k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_srai_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srai_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = simd_shr(a.as_i32x16(), i32x16::splat(IMM8.min(31) as i32));
@@ -20669,7 +21299,12 @@ pub fn _mm512_maskz_srai_epi32<const IMM8: u32>(k: __mmask16, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_srai_epi32<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srai_epi32<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         let r = simd_shr(a.as_i32x8(), i32x8::splat(IMM8.min(31) as i32));
         transmute(simd_select_bitmask(k, r, src.as_i32x8()))
@@ -20684,7 +21319,8 @@ pub fn _mm256_mask_srai_epi32<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_srai_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srai_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let r = simd_shr(a.as_i32x8(), i32x8::splat(IMM8.min(31) as i32));
         transmute(simd_select_bitmask(k, r, i32x8::ZERO))
@@ -20699,7 +21335,12 @@ pub fn _mm256_maskz_srai_epi32<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_srai_epi32<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srai_epi32<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         let r = simd_shr(a.as_i32x4(), i32x4::splat(IMM8.min(31) as i32));
         transmute(simd_select_bitmask(k, r, src.as_i32x4()))
@@ -20714,7 +21355,8 @@ pub fn _mm_mask_srai_epi32<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_srai_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srai_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let r = simd_shr(a.as_i32x4(), i32x4::splat(IMM8.min(31) as i32));
         transmute(simd_select_bitmask(k, r, i32x4::ZERO))
@@ -20729,7 +21371,8 @@ pub fn _mm_maskz_srai_epi32<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_srai_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srai_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         transmute(simd_shr(a.as_i64x8(), i64x8::splat(IMM8.min(63) as i64)))
@@ -20744,7 +21387,12 @@ pub fn _mm512_srai_epi64<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_srai_epi64<const IMM8: u32>(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srai_epi64<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i64x8(), i64x8::splat(IMM8.min(63) as i64));
@@ -20760,7 +21408,8 @@ pub fn _mm512_mask_srai_epi64<const IMM8: u32>(src: __m512i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i64x8(), i64x8::splat(IMM8.min(63) as i64));
@@ -20776,7 +21425,8 @@ pub fn _mm512_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m512i) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_srai_epi64<const IMM8: u32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srai_epi64<const IMM8: u32>(a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         transmute(simd_shr(a.as_i64x4(), i64x4::splat(IMM8.min(63) as i64)))
@@ -20791,7 +21441,12 @@ pub fn _mm256_srai_epi64<const IMM8: u32>(a: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_srai_epi64<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srai_epi64<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i64x4(), i64x4::splat(IMM8.min(63) as i64));
@@ -20807,7 +21462,8 @@ pub fn _mm256_mask_srai_epi64<const IMM8: u32>(src: __m256i, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i64x4(), i64x4::splat(IMM8.min(63) as i64));
@@ -20823,7 +21479,8 @@ pub fn _mm256_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m256i) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm_srai_epi64<const IMM8: u32>(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srai_epi64<const IMM8: u32>(a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         transmute(simd_shr(a.as_i64x2(), i64x2::splat(IMM8.min(63) as i64)))
@@ -20838,7 +21495,12 @@ pub fn _mm_srai_epi64<const IMM8: u32>(a: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_srai_epi64<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srai_epi64<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i64x2(), i64x2::splat(IMM8.min(63) as i64));
@@ -20854,7 +21516,8 @@ pub fn _mm_mask_srai_epi64<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i64x2(), i64x2::splat(IMM8.min(63) as i64));
@@ -20869,7 +21532,8 @@ pub fn _mm_maskz_srai_epi64<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u32x16();
         let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
@@ -20885,7 +21549,13 @@ pub fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm512_mask_srav_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srav_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_srav_epi32(a, count).as_i32x16();
         transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
@@ -20899,7 +21569,8 @@ pub fn _mm512_mask_srav_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_srav_epi32(a, count).as_i32x16();
         transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -20913,7 +21584,13 @@ pub fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m5
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm256_mask_srav_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srav_epi32(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_srav_epi32(a, count).as_i32x8();
         transmute(simd_select_bitmask(k, shf, src.as_i32x8()))
@@ -20927,7 +21604,8 @@ pub fn _mm256_mask_srav_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_srav_epi32(a, count).as_i32x8();
         transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -20941,7 +21619,8 @@ pub fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srav_epi32(a, count).as_i32x4();
         transmute(simd_select_bitmask(k, shf, src.as_i32x4()))
@@ -20955,7 +21634,8 @@ pub fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravd))]
-pub fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srav_epi32(a, count).as_i32x4();
         transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -20969,7 +21649,8 @@ pub fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u64x8();
         let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
@@ -20985,7 +21666,13 @@ pub fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm512_mask_srav_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srav_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_srav_epi64(a, count).as_i64x8();
         transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
@@ -20999,7 +21686,8 @@ pub fn _mm512_mask_srav_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_srav_epi64(a, count).as_i64x8();
         transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -21013,7 +21701,8 @@ pub fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u64x4();
         let no_overflow: u64x4 = simd_lt(count, u64x4::splat(u64::BITS as u64));
@@ -21029,7 +21718,13 @@ pub fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm256_mask_srav_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srav_epi64(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_srav_epi64(a, count).as_i64x4();
         transmute(simd_select_bitmask(k, shf, src.as_i64x4()))
@@ -21043,7 +21738,8 @@ pub fn _mm256_mask_srav_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_srav_epi64(a, count).as_i64x4();
         transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -21057,7 +21753,8 @@ pub fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u64x2();
         let no_overflow: u64x2 = simd_lt(count, u64x2::splat(u64::BITS as u64));
@@ -21073,7 +21770,8 @@ pub fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srav_epi64(a, count).as_i64x2();
         transmute(simd_select_bitmask(k, shf, src.as_i64x2()))
@@ -21087,7 +21785,8 @@ pub fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravq))]
-pub fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srav_epi64(a, count).as_i64x2();
         transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -21101,7 +21800,8 @@ pub fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm512_rolv_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_rolv_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_u32x16(),
@@ -21118,7 +21818,8 @@ pub fn _mm512_rolv_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm512_mask_rolv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_rolv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let rol = _mm512_rolv_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, rol, src.as_i32x16()))
@@ -21132,7 +21833,8 @@ pub fn _mm512_mask_rolv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm512_maskz_rolv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_rolv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let rol = _mm512_rolv_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, rol, i32x16::ZERO))
@@ -21146,7 +21848,8 @@ pub fn _mm512_maskz_rolv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm256_rolv_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_rolv_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_u32x8(),
@@ -21163,7 +21866,8 @@ pub fn _mm256_rolv_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm256_mask_rolv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_rolv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let rol = _mm256_rolv_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, rol, src.as_i32x8()))
@@ -21177,7 +21881,8 @@ pub fn _mm256_mask_rolv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm256_maskz_rolv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_rolv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let rol = _mm256_rolv_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, rol, i32x8::ZERO))
@@ -21191,7 +21896,8 @@ pub fn _mm256_maskz_rolv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm_rolv_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_rolv_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_u32x4(),
@@ -21208,7 +21914,8 @@ pub fn _mm_rolv_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm_mask_rolv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_rolv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let rol = _mm_rolv_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, rol, src.as_i32x4()))
@@ -21222,7 +21929,8 @@ pub fn _mm_mask_rolv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvd))]
-pub fn _mm_maskz_rolv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_rolv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let rol = _mm_rolv_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, rol, i32x4::ZERO))
@@ -21236,7 +21944,8 @@ pub fn _mm_maskz_rolv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm512_rorv_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_rorv_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shr(
             a.as_u32x16(),
@@ -21253,7 +21962,8 @@ pub fn _mm512_rorv_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm512_mask_rorv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_rorv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let ror = _mm512_rorv_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, ror, src.as_i32x16()))
@@ -21267,7 +21977,8 @@ pub fn _mm512_mask_rorv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm512_maskz_rorv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_rorv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let ror = _mm512_rorv_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, ror, i32x16::ZERO))
@@ -21281,7 +21992,8 @@ pub fn _mm512_maskz_rorv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm256_rorv_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_rorv_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shr(
             a.as_u32x8(),
@@ -21298,7 +22010,8 @@ pub fn _mm256_rorv_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm256_mask_rorv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_rorv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let ror = _mm256_rorv_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, ror, src.as_i32x8()))
@@ -21312,7 +22025,8 @@ pub fn _mm256_mask_rorv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm256_maskz_rorv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_rorv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let ror = _mm256_rorv_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, ror, i32x8::ZERO))
@@ -21326,7 +22040,8 @@ pub fn _mm256_maskz_rorv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm_rorv_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_rorv_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shr(
             a.as_u32x4(),
@@ -21343,7 +22058,8 @@ pub fn _mm_rorv_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm_mask_rorv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_rorv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let ror = _mm_rorv_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, ror, src.as_i32x4()))
@@ -21357,7 +22073,8 @@ pub fn _mm_mask_rorv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvd))]
-pub fn _mm_maskz_rorv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_rorv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let ror = _mm_rorv_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, ror, i32x4::ZERO))
@@ -21371,7 +22088,8 @@ pub fn _mm_maskz_rorv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm512_rolv_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_rolv_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_u64x8(),
@@ -21388,7 +22106,8 @@ pub fn _mm512_rolv_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm512_mask_rolv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_rolv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let rol = _mm512_rolv_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, rol, src.as_i64x8()))
@@ -21402,7 +22121,8 @@ pub fn _mm512_mask_rolv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm512_maskz_rolv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_rolv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let rol = _mm512_rolv_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, rol, i64x8::ZERO))
@@ -21416,7 +22136,8 @@ pub fn _mm512_maskz_rolv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm256_rolv_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_rolv_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_u64x4(),
@@ -21433,7 +22154,8 @@ pub fn _mm256_rolv_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm256_mask_rolv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_rolv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let rol = _mm256_rolv_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, rol, src.as_i64x4()))
@@ -21447,7 +22169,8 @@ pub fn _mm256_mask_rolv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm256_maskz_rolv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_rolv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let rol = _mm256_rolv_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, rol, i64x4::ZERO))
@@ -21461,7 +22184,8 @@ pub fn _mm256_maskz_rolv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm_rolv_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_rolv_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_u64x2(),
@@ -21478,7 +22202,8 @@ pub fn _mm_rolv_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm_mask_rolv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_rolv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let rol = _mm_rolv_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, rol, src.as_i64x2()))
@@ -21492,7 +22217,8 @@ pub fn _mm_mask_rolv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprolvq))]
-pub fn _mm_maskz_rolv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_rolv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let rol = _mm_rolv_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, rol, i64x2::ZERO))
@@ -21506,7 +22232,8 @@ pub fn _mm_maskz_rolv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm512_rorv_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_rorv_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shr(
             a.as_u64x8(),
@@ -21523,7 +22250,8 @@ pub fn _mm512_rorv_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm512_mask_rorv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_rorv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let ror = _mm512_rorv_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, ror, src.as_i64x8()))
@@ -21537,7 +22265,8 @@ pub fn _mm512_mask_rorv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm512_maskz_rorv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_rorv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let ror = _mm512_rorv_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, ror, i64x8::ZERO))
@@ -21551,7 +22280,8 @@ pub fn _mm512_maskz_rorv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm256_rorv_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_rorv_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shr(
             a.as_u64x4(),
@@ -21568,7 +22298,8 @@ pub fn _mm256_rorv_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm256_mask_rorv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_rorv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let ror = _mm256_rorv_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, ror, src.as_i64x4()))
@@ -21582,7 +22313,8 @@ pub fn _mm256_mask_rorv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm256_maskz_rorv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_rorv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let ror = _mm256_rorv_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, ror, i64x4::ZERO))
@@ -21596,7 +22328,8 @@ pub fn _mm256_maskz_rorv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm_rorv_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_rorv_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shr(
             a.as_u64x2(),
@@ -21613,7 +22346,8 @@ pub fn _mm_rorv_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm_mask_rorv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_rorv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let ror = _mm_rorv_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, ror, src.as_i64x2()))
@@ -21627,7 +22361,8 @@ pub fn _mm_mask_rorv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vprorvq))]
-pub fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let ror = _mm_rorv_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, ror, i64x2::ZERO))
@@ -21641,7 +22376,8 @@ pub fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u32x16();
         let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
@@ -21657,7 +22393,13 @@ pub fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm512_mask_sllv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sllv_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_sllv_epi32(a, count).as_i32x16();
         transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
@@ -21671,7 +22413,8 @@ pub fn _mm512_mask_sllv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_sllv_epi32(a, count).as_i32x16();
         transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -21685,7 +22428,13 @@ pub fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m5
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm256_mask_sllv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sllv_epi32(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_sllv_epi32(a, count).as_i32x8();
         transmute(simd_select_bitmask(k, shf, src.as_i32x8()))
@@ -21699,7 +22448,8 @@ pub fn _mm256_mask_sllv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_sllv_epi32(a, count).as_i32x8();
         transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -21713,7 +22463,8 @@ pub fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_sllv_epi32(a, count).as_i32x4();
         transmute(simd_select_bitmask(k, shf, src.as_i32x4()))
@@ -21727,7 +22478,8 @@ pub fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvd))]
-pub fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_sllv_epi32(a, count).as_i32x4();
         transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -21741,7 +22493,8 @@ pub fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u32x16();
         let no_overflow: u32x16 = simd_lt(count, u32x16::splat(u32::BITS));
@@ -21757,7 +22510,13 @@ pub fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm512_mask_srlv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srlv_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_srlv_epi32(a, count).as_i32x16();
         transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
@@ -21771,7 +22530,8 @@ pub fn _mm512_mask_srlv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_srlv_epi32(a, count).as_i32x16();
         transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -21785,7 +22545,13 @@ pub fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m5
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm256_mask_srlv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srlv_epi32(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_srlv_epi32(a, count).as_i32x8();
         transmute(simd_select_bitmask(k, shf, src.as_i32x8()))
@@ -21799,7 +22565,8 @@ pub fn _mm256_mask_srlv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_srlv_epi32(a, count).as_i32x8();
         transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -21813,7 +22580,8 @@ pub fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srlv_epi32(a, count).as_i32x4();
         transmute(simd_select_bitmask(k, shf, src.as_i32x4()))
@@ -21827,7 +22595,8 @@ pub fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvd))]
-pub fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srlv_epi32(a, count).as_i32x4();
         transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -21841,7 +22610,8 @@ pub fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u64x8();
         let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
@@ -21857,7 +22627,13 @@ pub fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm512_mask_sllv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sllv_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_sllv_epi64(a, count).as_i64x8();
         transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
@@ -21871,7 +22647,8 @@ pub fn _mm512_mask_sllv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_sllv_epi64(a, count).as_i64x8();
         transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -21885,7 +22662,13 @@ pub fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm256_mask_sllv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sllv_epi64(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_sllv_epi64(a, count).as_i64x4();
         transmute(simd_select_bitmask(k, shf, src.as_i64x4()))
@@ -21899,7 +22682,8 @@ pub fn _mm256_mask_sllv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_sllv_epi64(a, count).as_i64x4();
         transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -21913,7 +22697,8 @@ pub fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_sllv_epi64(a, count).as_i64x2();
         transmute(simd_select_bitmask(k, shf, src.as_i64x2()))
@@ -21927,7 +22712,8 @@ pub fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvq))]
-pub fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_sllv_epi64(a, count).as_i64x2();
         transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -21941,7 +22727,8 @@ pub fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u64x8();
         let no_overflow: u64x8 = simd_lt(count, u64x8::splat(u64::BITS as u64));
@@ -21957,7 +22744,13 @@ pub fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm512_mask_srlv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srlv_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_srlv_epi64(a, count).as_i64x8();
         transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
@@ -21971,7 +22764,8 @@ pub fn _mm512_mask_srlv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_srlv_epi64(a, count).as_i64x8();
         transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -21985,7 +22779,13 @@ pub fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm256_mask_srlv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srlv_epi64(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_srlv_epi64(a, count).as_i64x4();
         transmute(simd_select_bitmask(k, shf, src.as_i64x4()))
@@ -21999,7 +22799,8 @@ pub fn _mm256_mask_srlv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_srlv_epi64(a, count).as_i64x4();
         transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -22013,7 +22814,8 @@ pub fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srlv_epi64(a, count).as_i64x2();
         transmute(simd_select_bitmask(k, shf, src.as_i64x2()))
@@ -22027,7 +22829,8 @@ pub fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvq))]
-pub fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srlv_epi64(a, count).as_i64x2();
         transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -22042,7 +22845,8 @@ pub fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_permute_ps<const MASK: i32>(a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_permute_ps<const MASK: i32>(a: __m512) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -22078,7 +22882,12 @@ pub fn _mm512_permute_ps<const MASK: i32>(a: __m512) -> __m512 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_permute_ps<const MASK: i32>(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_permute_ps<const MASK: i32>(
+    src: __m512,
+    k: __mmask16,
+    a: __m512,
+) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_permute_ps::<MASK>(a);
@@ -22094,7 +22903,8 @@ pub fn _mm512_mask_permute_ps<const MASK: i32>(src: __m512, k: __mmask16, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_permute_ps<const MASK: i32>(k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_permute_ps<const MASK: i32>(k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_permute_ps::<MASK>(a);
@@ -22110,7 +22920,12 @@ pub fn _mm512_maskz_permute_ps<const MASK: i32>(k: __mmask16, a: __m512) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_permute_ps<const MASK: i32>(src: __m256, k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_permute_ps<const MASK: i32>(
+    src: __m256,
+    k: __mmask8,
+    a: __m256,
+) -> __m256 {
     unsafe {
         let r = _mm256_permute_ps::<MASK>(a);
         transmute(simd_select_bitmask(k, r.as_f32x8(), src.as_f32x8()))
@@ -22125,7 +22940,8 @@ pub fn _mm256_mask_permute_ps<const MASK: i32>(src: __m256, k: __mmask8, a: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_permute_ps<const MASK: i32>(k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_permute_ps<const MASK: i32>(k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let r = _mm256_permute_ps::<MASK>(a);
         transmute(simd_select_bitmask(k, r.as_f32x8(), f32x8::ZERO))
@@ -22140,7 +22956,8 @@ pub fn _mm256_maskz_permute_ps<const MASK: i32>(k: __mmask8, a: __m256) -> __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_permute_ps<const MASK: i32>(src: __m128, k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_permute_ps<const MASK: i32>(src: __m128, k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let r = _mm_permute_ps::<MASK>(a);
         transmute(simd_select_bitmask(k, r.as_f32x4(), src.as_f32x4()))
@@ -22155,7 +22972,8 @@ pub fn _mm_mask_permute_ps<const MASK: i32>(src: __m128, k: __mmask8, a: __m128)
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_permute_ps<const MASK: i32>(k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_permute_ps<const MASK: i32>(k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let r = _mm_permute_ps::<MASK>(a);
         transmute(simd_select_bitmask(k, r.as_f32x4(), f32x4::ZERO))
@@ -22170,7 +22988,8 @@ pub fn _mm_maskz_permute_ps<const MASK: i32>(k: __mmask8, a: __m128) -> __m128 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01_10_01))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_permute_pd<const MASK: i32>(a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_permute_pd<const MASK: i32>(a: __m512d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -22198,7 +23017,12 @@ pub fn _mm512_permute_pd<const MASK: i32>(a: __m512d) -> __m512d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01_10_01))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_permute_pd<const MASK: i32>(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_permute_pd<const MASK: i32>(
+    src: __m512d,
+    k: __mmask8,
+    a: __m512d,
+) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_permute_pd::<MASK>(a);
@@ -22214,7 +23038,8 @@ pub fn _mm512_mask_permute_pd<const MASK: i32>(src: __m512d, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01_10_01))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_permute_pd<const MASK: i32>(k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_permute_pd<const MASK: i32>(k: __mmask8, a: __m512d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_permute_pd::<MASK>(a);
@@ -22230,7 +23055,12 @@ pub fn _mm512_maskz_permute_pd<const MASK: i32>(k: __mmask8, a: __m512d) -> __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_permute_pd<const MASK: i32>(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_permute_pd<const MASK: i32>(
+    src: __m256d,
+    k: __mmask8,
+    a: __m256d,
+) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 4);
         let r = _mm256_permute_pd::<MASK>(a);
@@ -22246,7 +23076,8 @@ pub fn _mm256_mask_permute_pd<const MASK: i32>(src: __m256d, k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_permute_pd<const MASK: i32>(k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_permute_pd<const MASK: i32>(k: __mmask8, a: __m256d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 4);
         let r = _mm256_permute_pd::<MASK>(a);
@@ -22262,7 +23093,12 @@ pub fn _mm256_maskz_permute_pd<const MASK: i32>(k: __mmask8, a: __m256d) -> __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, IMM2 = 0b01))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_permute_pd<const IMM2: i32>(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_permute_pd<const IMM2: i32>(
+    src: __m128d,
+    k: __mmask8,
+    a: __m128d,
+) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(IMM2, 2);
         let r = _mm_permute_pd::<IMM2>(a);
@@ -22278,7 +23114,8 @@ pub fn _mm_mask_permute_pd<const IMM2: i32>(src: __m128d, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, IMM2 = 0b01))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_permute_pd<const IMM2: i32>(k: __mmask8, a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_permute_pd<const IMM2: i32>(k: __mmask8, a: __m128d) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(IMM2, 2);
         let r = _mm_permute_pd::<IMM2>(a);
@@ -22294,7 +23131,8 @@ pub fn _mm_maskz_permute_pd<const IMM2: i32>(k: __mmask8, a: __m128d) -> __m128d
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_permutex_epi64<const MASK: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_permutex_epi64<const MASK: i32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -22322,7 +23160,8 @@ pub fn _mm512_permutex_epi64<const MASK: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_permutex_epi64<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_permutex_epi64<const MASK: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -22342,7 +23181,8 @@ pub fn _mm512_mask_permutex_epi64<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_permutex_epi64<const MASK: i32>(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_permutex_epi64<const MASK: i32>(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_permutex_epi64::<MASK>(a);
@@ -22358,7 +23198,8 @@ pub fn _mm512_maskz_permutex_epi64<const MASK: i32>(k: __mmask8, a: __m512i) ->
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_permutex_epi64<const MASK: i32>(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permutex_epi64<const MASK: i32>(a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -22382,7 +23223,8 @@ pub fn _mm256_permutex_epi64<const MASK: i32>(a: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_permutex_epi64<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_permutex_epi64<const MASK: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -22402,7 +23244,8 @@ pub fn _mm256_mask_permutex_epi64<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_permutex_epi64<const MASK: i32>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_permutex_epi64<const MASK: i32>(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_permutex_epi64::<MASK>(a);
@@ -22418,7 +23261,8 @@ pub fn _mm256_maskz_permutex_epi64<const MASK: i32>(k: __mmask8, a: __m256i) ->
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_permutex_pd<const MASK: i32>(a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_permutex_pd<const MASK: i32>(a: __m512d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -22446,7 +23290,12 @@ pub fn _mm512_permutex_pd<const MASK: i32>(a: __m512d) -> __m512d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_permutex_pd<const MASK: i32>(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_permutex_pd<const MASK: i32>(
+    src: __m512d,
+    k: __mmask8,
+    a: __m512d,
+) -> __m512d {
     unsafe {
         let r = _mm512_permutex_pd::<MASK>(a);
         transmute(simd_select_bitmask(k, r.as_f64x8(), src.as_f64x8()))
@@ -22461,7 +23310,8 @@ pub fn _mm512_mask_permutex_pd<const MASK: i32>(src: __m512d, k: __mmask8, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_permutex_pd<const MASK: i32>(k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_permutex_pd<const MASK: i32>(k: __mmask8, a: __m512d) -> __m512d {
     unsafe {
         let r = _mm512_permutex_pd::<MASK>(a);
         transmute(simd_select_bitmask(k, r.as_f64x8(), f64x8::ZERO))
@@ -22476,7 +23326,8 @@ pub fn _mm512_maskz_permutex_pd<const MASK: i32>(k: __mmask8, a: __m512d) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_permutex_pd<const MASK: i32>(a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_permutex_pd<const MASK: i32>(a: __m256d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -22500,7 +23351,12 @@ pub fn _mm256_permutex_pd<const MASK: i32>(a: __m256d) -> __m256d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_permutex_pd<const MASK: i32>(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_permutex_pd<const MASK: i32>(
+    src: __m256d,
+    k: __mmask8,
+    a: __m256d,
+) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_permutex_pd::<MASK>(a);
@@ -22516,7 +23372,8 @@ pub fn _mm256_mask_permutex_pd<const MASK: i32>(src: __m256d, k: __mmask8, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_permutex_pd<const MASK: i32>(k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_permutex_pd<const MASK: i32>(k: __mmask8, a: __m256d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_permutex_pd::<MASK>(a);
@@ -23786,7 +24643,8 @@ pub fn _mm_mask2_permutex2var_pd(a: __m128d, idx: __m128i, k: __mmask8, b: __m12
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 9))] //should be vpshufd
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_shuffle_epi32<const MASK: _MM_PERM_ENUM>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_epi32<const MASK: _MM_PERM_ENUM>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r: i32x16 = simd_shuffle!(
@@ -23823,7 +24681,8 @@ pub fn _mm512_shuffle_epi32<const MASK: _MM_PERM_ENUM>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -23843,7 +24702,11 @@ pub fn _mm512_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
+    k: __mmask16,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_shuffle_epi32::<MASK>(a);
@@ -23859,7 +24722,8 @@ pub fn _mm512_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -23879,7 +24743,11 @@ pub fn _mm256_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
+    k: __mmask8,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_epi32::<MASK>(a);
@@ -23895,7 +24763,8 @@ pub fn _mm256_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(k: __mmask8, a: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -23915,7 +24784,11 @@ pub fn _mm_mask_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm_shuffle_epi32::<MASK>(a);
@@ -23931,7 +24804,8 @@ pub fn _mm_maskz_shuffle_epi32<const MASK: _MM_PERM_ENUM>(k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shuffle_ps<const MASK: i32>(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_ps<const MASK: i32>(a: __m512, b: __m512) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -23967,7 +24841,8 @@ pub fn _mm512_shuffle_ps<const MASK: i32>(a: __m512, b: __m512) -> __m512 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shuffle_ps<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_ps<const MASK: i32>(
     src: __m512,
     k: __mmask16,
     a: __m512,
@@ -23988,7 +24863,12 @@ pub fn _mm512_mask_shuffle_ps<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shuffle_ps<const MASK: i32>(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_ps<const MASK: i32>(
+    k: __mmask16,
+    a: __m512,
+    b: __m512,
+) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_shuffle_ps::<MASK>(a, b);
@@ -24004,7 +24884,8 @@ pub fn _mm512_maskz_shuffle_ps<const MASK: i32>(k: __mmask16, a: __m512, b: __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shuffle_ps<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_ps<const MASK: i32>(
     src: __m256,
     k: __mmask8,
     a: __m256,
@@ -24025,7 +24906,8 @@ pub fn _mm256_mask_shuffle_ps<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shuffle_ps<const MASK: i32>(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_ps<const MASK: i32>(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_ps::<MASK>(a, b);
@@ -24041,7 +24923,8 @@ pub fn _mm256_maskz_shuffle_ps<const MASK: i32>(k: __mmask8, a: __m256, b: __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shuffle_ps<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shuffle_ps<const MASK: i32>(
     src: __m128,
     k: __mmask8,
     a: __m128,
@@ -24062,7 +24945,8 @@ pub fn _mm_mask_shuffle_ps<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufps, MASK = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shuffle_ps<const MASK: i32>(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shuffle_ps<const MASK: i32>(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm_shuffle_ps::<MASK>(a, b);
@@ -24078,7 +24962,8 @@ pub fn _mm_maskz_shuffle_ps<const MASK: i32>(k: __mmask8, a: __m128, b: __m128)
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shuffle_pd<const MASK: i32>(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_pd<const MASK: i32>(a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         simd_shuffle!(
@@ -24106,7 +24991,8 @@ pub fn _mm512_shuffle_pd<const MASK: i32>(a: __m512d, b: __m512d) -> __m512d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shuffle_pd<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_pd<const MASK: i32>(
     src: __m512d,
     k: __mmask8,
     a: __m512d,
@@ -24127,7 +25013,12 @@ pub fn _mm512_mask_shuffle_pd<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_pd<const MASK: i32>(
+    k: __mmask8,
+    a: __m512d,
+    b: __m512d,
+) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_shuffle_pd::<MASK>(a, b);
@@ -24143,7 +25034,8 @@ pub fn _mm512_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m512d, b: __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shuffle_pd<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_pd<const MASK: i32>(
     src: __m256d,
     k: __mmask8,
     a: __m256d,
@@ -24164,7 +25056,12 @@ pub fn _mm256_mask_shuffle_pd<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_pd<const MASK: i32>(
+    k: __mmask8,
+    a: __m256d,
+    b: __m256d,
+) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_pd::<MASK>(a, b);
@@ -24180,7 +25077,8 @@ pub fn _mm256_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m256d, b: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shuffle_pd<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shuffle_pd<const MASK: i32>(
     src: __m128d,
     k: __mmask8,
     a: __m128d,
@@ -24201,7 +25099,8 @@ pub fn _mm_mask_shuffle_pd<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufpd, MASK = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm_shuffle_pd::<MASK>(a, b);
@@ -24217,7 +25116,8 @@ pub fn _mm_maskz_shuffle_pd<const MASK: i32>(k: __mmask8, a: __m128d, b: __m128d
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_01_01_01))] //should be vshufi32x4
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shuffle_i32x4<const MASK: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_i32x4<const MASK: i32>(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_i32x16();
@@ -24256,7 +25156,8 @@ pub fn _mm512_shuffle_i32x4<const MASK: i32>(a: __m512i, b: __m512i) -> __m512i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b10_11_01_01))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shuffle_i32x4<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_i32x4<const MASK: i32>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -24277,7 +25178,8 @@ pub fn _mm512_mask_shuffle_i32x4<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b10_11_01_01))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shuffle_i32x4<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_i32x4<const MASK: i32>(
     k: __mmask16,
     a: __m512i,
     b: __m512i,
@@ -24297,7 +25199,8 @@ pub fn _mm512_maskz_shuffle_i32x4<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b11))] //should be vshufi32x4
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shuffle_i32x4<const MASK: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_i32x4<const MASK: i32>(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_i32x8();
@@ -24328,7 +25231,8 @@ pub fn _mm256_shuffle_i32x4<const MASK: i32>(a: __m256i, b: __m256i) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b11))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shuffle_i32x4<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_i32x4<const MASK: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -24349,7 +25253,12 @@ pub fn _mm256_mask_shuffle_i32x4<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shuffle_i32x4<const MASK: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_i32x4<const MASK: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_i32x4::<MASK>(a, b);
@@ -24365,7 +25274,8 @@ pub fn _mm256_maskz_shuffle_i32x4<const MASK: i32>(k: __mmask8, a: __m256i, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_11_11_11))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shuffle_i64x2<const MASK: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_i64x2<const MASK: i32>(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_i64x8();
@@ -24396,7 +25306,8 @@ pub fn _mm512_shuffle_i64x2<const MASK: i32>(a: __m512i, b: __m512i) -> __m512i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_11_11_11))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shuffle_i64x2<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_i64x2<const MASK: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -24417,7 +25328,12 @@ pub fn _mm512_mask_shuffle_i64x2<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_11_11_11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shuffle_i64x2<const MASK: i32>(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_i64x2<const MASK: i32>(
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_shuffle_i64x2::<MASK>(a, b);
@@ -24433,7 +25349,8 @@ pub fn _mm512_maskz_shuffle_i64x2<const MASK: i32>(k: __mmask8, a: __m512i, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b01))] //should be vshufi64x2
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shuffle_i64x2<const MASK: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_i64x2<const MASK: i32>(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_i64x4();
@@ -24460,7 +25377,8 @@ pub fn _mm256_shuffle_i64x2<const MASK: i32>(a: __m256i, b: __m256i) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b11))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shuffle_i64x2<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_i64x2<const MASK: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -24481,7 +25399,12 @@ pub fn _mm256_mask_shuffle_i64x2<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shuffle_i64x2<const MASK: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_i64x2<const MASK: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_i64x2::<MASK>(a, b);
@@ -24497,7 +25420,8 @@ pub fn _mm256_maskz_shuffle_i64x2<const MASK: i32>(k: __mmask8, a: __m256i, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b1011))] //should be vshuff32x4, but generate vshuff64x2
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shuffle_f32x4<const MASK: i32>(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_f32x4<const MASK: i32>(a: __m512, b: __m512) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_f32x16();
@@ -24536,7 +25460,8 @@ pub fn _mm512_shuffle_f32x4<const MASK: i32>(a: __m512, b: __m512) -> __m512 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b1011))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shuffle_f32x4<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_f32x4<const MASK: i32>(
     src: __m512,
     k: __mmask16,
     a: __m512,
@@ -24557,7 +25482,12 @@ pub fn _mm512_mask_shuffle_f32x4<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b1011))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shuffle_f32x4<const MASK: i32>(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_f32x4<const MASK: i32>(
+    k: __mmask16,
+    a: __m512,
+    b: __m512,
+) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_shuffle_f32x4::<MASK>(a, b);
@@ -24573,7 +25503,8 @@ pub fn _mm512_maskz_shuffle_f32x4<const MASK: i32>(k: __mmask16, a: __m512, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b01))] //should be vshuff32x4
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shuffle_f32x4<const MASK: i32>(a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_f32x4<const MASK: i32>(a: __m256, b: __m256) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_f32x8();
@@ -24604,7 +25535,8 @@ pub fn _mm256_shuffle_f32x4<const MASK: i32>(a: __m256, b: __m256) -> __m256 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b11))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shuffle_f32x4<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_f32x4<const MASK: i32>(
     src: __m256,
     k: __mmask8,
     a: __m256,
@@ -24625,7 +25557,12 @@ pub fn _mm256_mask_shuffle_f32x4<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shuffle_f32x4<const MASK: i32>(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_f32x4<const MASK: i32>(
+    k: __mmask8,
+    a: __m256,
+    b: __m256,
+) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_f32x4::<MASK>(a, b);
@@ -24641,7 +25578,8 @@ pub fn _mm256_maskz_shuffle_f32x4<const MASK: i32>(k: __mmask8, a: __m256, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b10_11_11_11))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shuffle_f64x2<const MASK: i32>(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shuffle_f64x2<const MASK: i32>(a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_f64x8();
@@ -24672,7 +25610,8 @@ pub fn _mm512_shuffle_f64x2<const MASK: i32>(a: __m512d, b: __m512d) -> __m512d
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b10_11_11_11))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shuffle_f64x2<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shuffle_f64x2<const MASK: i32>(
     src: __m512d,
     k: __mmask8,
     a: __m512d,
@@ -24693,7 +25632,12 @@ pub fn _mm512_mask_shuffle_f64x2<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b10_11_11_11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shuffle_f64x2<const MASK: i32>(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shuffle_f64x2<const MASK: i32>(
+    k: __mmask8,
+    a: __m512d,
+    b: __m512d,
+) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm512_shuffle_f64x2::<MASK>(a, b);
@@ -24709,7 +25653,8 @@ pub fn _mm512_maskz_shuffle_f64x2<const MASK: i32>(k: __mmask8, a: __m512d, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vperm, MASK = 0b01))] //should be vshuff64x2
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shuffle_f64x2<const MASK: i32>(a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shuffle_f64x2<const MASK: i32>(a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let a = a.as_f64x4();
@@ -24736,7 +25681,8 @@ pub fn _mm256_shuffle_f64x2<const MASK: i32>(a: __m256d, b: __m256d) -> __m256d
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b11))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shuffle_f64x2<const MASK: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shuffle_f64x2<const MASK: i32>(
     src: __m256d,
     k: __mmask8,
     a: __m256d,
@@ -24757,7 +25703,12 @@ pub fn _mm256_mask_shuffle_f64x2<const MASK: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b11))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shuffle_f64x2<const MASK: i32>(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shuffle_f64x2<const MASK: i32>(
+    k: __mmask8,
+    a: __m256d,
+    b: __m256d,
+) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(MASK, 8);
         let r = _mm256_shuffle_f64x2::<MASK>(a, b);
@@ -24773,7 +25724,8 @@ pub fn _mm256_maskz_shuffle_f64x2<const MASK: i32>(k: __mmask8, a: __m256d, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_extractf32x4_ps<const IMM8: i32>(a: __m512) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extractf32x4_ps<const IMM8: i32>(a: __m512) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         match IMM8 & 0x3 {
@@ -24793,7 +25745,12 @@ pub fn _mm512_extractf32x4_ps<const IMM8: i32>(a: __m512) -> __m128 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a: __m512) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extractf32x4_ps<const IMM8: i32>(
+    src: __m128,
+    k: __mmask8,
+    a: __m512,
+) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let r = _mm512_extractf32x4_ps::<IMM8>(a);
@@ -24809,7 +25766,8 @@ pub fn _mm512_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a:
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m512) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m512) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let r = _mm512_extractf32x4_ps::<IMM8>(a);
@@ -24828,7 +25786,8 @@ pub fn _mm512_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m512) ->
     assert_instr(vextract, IMM8 = 1) //should be vextractf32x4
 )]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_extractf32x4_ps<const IMM8: i32>(a: __m256) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extractf32x4_ps<const IMM8: i32>(a: __m256) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         match IMM8 & 0x1 {
@@ -24846,7 +25805,12 @@ pub fn _mm256_extractf32x4_ps<const IMM8: i32>(a: __m256) -> __m128 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a: __m256) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_extractf32x4_ps<const IMM8: i32>(
+    src: __m128,
+    k: __mmask8,
+    a: __m256,
+) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm256_extractf32x4_ps::<IMM8>(a);
@@ -24862,7 +25826,8 @@ pub fn _mm256_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a:
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m256) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m256) -> __m128 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm256_extractf32x4_ps::<IMM8>(a);
@@ -24881,7 +25846,8 @@ pub fn _mm256_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m256) ->
     assert_instr(vextractf64x4, IMM1 = 1) //should be vextracti64x4
 )]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_extracti64x4_epi64<const IMM1: i32>(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extracti64x4_epi64<const IMM1: i32>(a: __m512i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM1, 1);
         match IMM1 {
@@ -24899,7 +25865,8 @@ pub fn _mm512_extracti64x4_epi64<const IMM1: i32>(a: __m512i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextracti64x4, IMM1 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_extracti64x4_epi64<const IMM1: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extracti64x4_epi64<const IMM1: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m512i,
@@ -24919,7 +25886,8 @@ pub fn _mm512_mask_extracti64x4_epi64<const IMM1: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextracti64x4, IMM1 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_extracti64x4_epi64<const IMM1: i32>(k: __mmask8, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extracti64x4_epi64<const IMM1: i32>(k: __mmask8, a: __m512i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM1, 1);
         let r = _mm512_extracti64x4_epi64::<IMM1>(a);
@@ -24935,7 +25903,8 @@ pub fn _mm512_maskz_extracti64x4_epi64<const IMM1: i32>(k: __mmask8, a: __m512i)
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_extractf64x4_pd<const IMM8: i32>(a: __m512d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extractf64x4_pd<const IMM8: i32>(a: __m512d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         match IMM8 & 0x1 {
@@ -24953,7 +25922,8 @@ pub fn _mm512_extractf64x4_pd<const IMM8: i32>(a: __m512d) -> __m256d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_extractf64x4_pd<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extractf64x4_pd<const IMM8: i32>(
     src: __m256d,
     k: __mmask8,
     a: __m512d,
@@ -24973,7 +25943,8 @@ pub fn _mm512_mask_extractf64x4_pd<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_extractf64x4_pd<const IMM8: i32>(k: __mmask8, a: __m512d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extractf64x4_pd<const IMM8: i32>(k: __mmask8, a: __m512d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm512_extractf64x4_pd::<IMM8>(a);
@@ -24992,7 +25963,8 @@ pub fn _mm512_maskz_extractf64x4_pd<const IMM8: i32>(k: __mmask8, a: __m512d) ->
     assert_instr(vextractf32x4, IMM2 = 3) //should be vextracti32x4
 )]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_extracti32x4_epi32<const IMM2: i32>(a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extracti32x4_epi32<const IMM2: i32>(a: __m512i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM2, 2);
         let a = a.as_i32x16();
@@ -25015,7 +25987,8 @@ pub fn _mm512_extracti32x4_epi32<const IMM2: i32>(a: __m512i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextracti32x4, IMM2 = 3))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_extracti32x4_epi32<const IMM2: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extracti32x4_epi32<const IMM2: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m512i,
@@ -25035,7 +26008,8 @@ pub fn _mm512_mask_extracti32x4_epi32<const IMM2: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextracti32x4, IMM2 = 3))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_extracti32x4_epi32<const IMM2: i32>(k: __mmask8, a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extracti32x4_epi32<const IMM2: i32>(k: __mmask8, a: __m512i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM2, 2);
         let r = _mm512_extracti32x4_epi32::<IMM2>(a);
@@ -25054,7 +26028,8 @@ pub fn _mm512_maskz_extracti32x4_epi32<const IMM2: i32>(k: __mmask8, a: __m512i)
     assert_instr(vextract, IMM1 = 1) //should be vextracti32x4
 )]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm256_extracti32x4_epi32<const IMM1: i32>(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extracti32x4_epi32<const IMM1: i32>(a: __m256i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM1, 1);
         let a = a.as_i32x8();
@@ -25075,7 +26050,8 @@ pub fn _mm256_extracti32x4_epi32<const IMM1: i32>(a: __m256i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextracti32x4, IMM1 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_extracti32x4_epi32<const IMM1: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_extracti32x4_epi32<const IMM1: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m256i,
@@ -25095,7 +26071,8 @@ pub fn _mm256_mask_extracti32x4_epi32<const IMM1: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vextracti32x4, IMM1 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_extracti32x4_epi32<const IMM1: i32>(k: __mmask8, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_extracti32x4_epi32<const IMM1: i32>(k: __mmask8, a: __m256i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM1, 1);
         let r = _mm256_extracti32x4_epi32::<IMM1>(a);
@@ -25110,7 +26087,8 @@ pub fn _mm256_maskz_extracti32x4_epi32<const IMM1: i32>(k: __mmask8, a: __m256i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm512_moveldup_ps(a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_moveldup_ps(a: __m512) -> __m512 {
     unsafe {
         let r: f32x16 = simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14]);
         transmute(r)
@@ -25124,7 +26102,8 @@ pub fn _mm512_moveldup_ps(a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm512_mask_moveldup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_moveldup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         let mov: f32x16 =
             simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14]);
@@ -25139,7 +26118,8 @@ pub fn _mm512_mask_moveldup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm512_maskz_moveldup_ps(k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_moveldup_ps(k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         let mov: f32x16 =
             simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14]);
@@ -25154,7 +26134,8 @@ pub fn _mm512_maskz_moveldup_ps(k: __mmask16, a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm256_mask_moveldup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_moveldup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let mov = _mm256_moveldup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x8(), src.as_f32x8()))
@@ -25168,7 +26149,8 @@ pub fn _mm256_mask_moveldup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm256_maskz_moveldup_ps(k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_moveldup_ps(k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let mov = _mm256_moveldup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x8(), f32x8::ZERO))
@@ -25182,7 +26164,8 @@ pub fn _mm256_maskz_moveldup_ps(k: __mmask8, a: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm_mask_moveldup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_moveldup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let mov = _mm_moveldup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x4(), src.as_f32x4()))
@@ -25196,7 +26179,8 @@ pub fn _mm_mask_moveldup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsldup))]
-pub fn _mm_maskz_moveldup_ps(k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_moveldup_ps(k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let mov = _mm_moveldup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x4(), f32x4::ZERO))
@@ -25210,7 +26194,8 @@ pub fn _mm_maskz_moveldup_ps(k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm512_movehdup_ps(a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movehdup_ps(a: __m512) -> __m512 {
     unsafe {
         let r: f32x16 = simd_shuffle!(a, a, [1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15]);
         transmute(r)
@@ -25224,7 +26209,8 @@ pub fn _mm512_movehdup_ps(a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm512_mask_movehdup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_movehdup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         let mov: f32x16 =
             simd_shuffle!(a, a, [1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15]);
@@ -25239,7 +26225,8 @@ pub fn _mm512_mask_movehdup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm512_maskz_movehdup_ps(k: __mmask16, a: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_movehdup_ps(k: __mmask16, a: __m512) -> __m512 {
     unsafe {
         let mov: f32x16 =
             simd_shuffle!(a, a, [1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15]);
@@ -25254,7 +26241,8 @@ pub fn _mm512_maskz_movehdup_ps(k: __mmask16, a: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm256_mask_movehdup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_movehdup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let mov = _mm256_movehdup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x8(), src.as_f32x8()))
@@ -25268,7 +26256,8 @@ pub fn _mm256_mask_movehdup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm256_maskz_movehdup_ps(k: __mmask8, a: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_movehdup_ps(k: __mmask8, a: __m256) -> __m256 {
     unsafe {
         let mov = _mm256_movehdup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x8(), f32x8::ZERO))
@@ -25282,7 +26271,8 @@ pub fn _mm256_maskz_movehdup_ps(k: __mmask8, a: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm_mask_movehdup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_movehdup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let mov = _mm_movehdup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x4(), src.as_f32x4()))
@@ -25296,7 +26286,8 @@ pub fn _mm_mask_movehdup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovshdup))]
-pub fn _mm_maskz_movehdup_ps(k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_movehdup_ps(k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let mov = _mm_movehdup_ps(a);
         transmute(simd_select_bitmask(k, mov.as_f32x4(), f32x4::ZERO))
@@ -25310,7 +26301,8 @@ pub fn _mm_maskz_movehdup_ps(k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm512_movedup_pd(a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movedup_pd(a: __m512d) -> __m512d {
     unsafe {
         let r: f64x8 = simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6]);
         transmute(r)
@@ -25324,7 +26316,8 @@ pub fn _mm512_movedup_pd(a: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm512_mask_movedup_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_movedup_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
     unsafe {
         let mov: f64x8 = simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6]);
         transmute(simd_select_bitmask(k, mov, src.as_f64x8()))
@@ -25338,7 +26331,8 @@ pub fn _mm512_mask_movedup_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm512_maskz_movedup_pd(k: __mmask8, a: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_movedup_pd(k: __mmask8, a: __m512d) -> __m512d {
     unsafe {
         let mov: f64x8 = simd_shuffle!(a, a, [0, 0, 2, 2, 4, 4, 6, 6]);
         transmute(simd_select_bitmask(k, mov, f64x8::ZERO))
@@ -25352,7 +26346,8 @@ pub fn _mm512_maskz_movedup_pd(k: __mmask8, a: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm256_mask_movedup_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_movedup_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d {
     unsafe {
         let mov = _mm256_movedup_pd(a);
         transmute(simd_select_bitmask(k, mov.as_f64x4(), src.as_f64x4()))
@@ -25366,7 +26361,8 @@ pub fn _mm256_mask_movedup_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm256_maskz_movedup_pd(k: __mmask8, a: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_movedup_pd(k: __mmask8, a: __m256d) -> __m256d {
     unsafe {
         let mov = _mm256_movedup_pd(a);
         transmute(simd_select_bitmask(k, mov.as_f64x4(), f64x4::ZERO))
@@ -25380,7 +26376,8 @@ pub fn _mm256_maskz_movedup_pd(k: __mmask8, a: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm_mask_movedup_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_movedup_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
     unsafe {
         let mov = _mm_movedup_pd(a);
         transmute(simd_select_bitmask(k, mov.as_f64x2(), src.as_f64x2()))
@@ -25394,7 +26391,8 @@ pub fn _mm_mask_movedup_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovddup))]
-pub fn _mm_maskz_movedup_pd(k: __mmask8, a: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_movedup_pd(k: __mmask8, a: __m128d) -> __m128d {
     unsafe {
         let mov = _mm_movedup_pd(a);
         transmute(simd_select_bitmask(k, mov.as_f64x2(), f64x2::ZERO))
@@ -25409,7 +26407,8 @@ pub fn _mm_maskz_movedup_pd(k: __mmask8, a: __m128d) -> __m128d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))] //should be vinserti32x4
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_inserti32x4<const IMM8: i32>(a: __m512i, b: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_inserti32x4<const IMM8: i32>(a: __m512i, b: __m128i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let a = a.as_i32x16();
@@ -25452,7 +26451,8 @@ pub fn _mm512_inserti32x4<const IMM8: i32>(a: __m512i, b: __m128i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 2))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_inserti32x4<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_inserti32x4<const IMM8: i32>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -25473,7 +26473,12 @@ pub fn _mm512_mask_inserti32x4<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 2))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_inserti32x4<const IMM8: i32>(k: __mmask16, a: __m512i, b: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_inserti32x4<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512i,
+    b: __m128i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let r = _mm512_inserti32x4::<IMM8>(a, b);
@@ -25492,7 +26497,8 @@ pub fn _mm512_maskz_inserti32x4<const IMM8: i32>(k: __mmask16, a: __m512i, b: __
     assert_instr(vinsert, IMM8 = 1) //should be vinserti32x4
 )]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_inserti32x4<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_inserti32x4<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let a = a.as_i32x8();
@@ -25513,7 +26519,8 @@ pub fn _mm256_inserti32x4<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_inserti32x4<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_inserti32x4<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -25534,7 +26541,12 @@ pub fn _mm256_mask_inserti32x4<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_inserti32x4<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_inserti32x4<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m128i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm256_inserti32x4::<IMM8>(a, b);
@@ -25550,7 +26562,8 @@ pub fn _mm256_maskz_inserti32x4<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))] //should be vinserti64x4
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_inserti64x4<const IMM8: i32>(a: __m512i, b: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_inserti64x4<const IMM8: i32>(a: __m512i, b: __m256i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm512_castsi256_si512(b);
@@ -25569,7 +26582,8 @@ pub fn _mm512_inserti64x4<const IMM8: i32>(a: __m512i, b: __m256i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinserti64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_inserti64x4<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_inserti64x4<const IMM8: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -25590,7 +26604,12 @@ pub fn _mm512_mask_inserti64x4<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinserti64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_inserti64x4<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_inserti64x4<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512i,
+    b: __m256i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm512_inserti64x4::<IMM8>(a, b);
@@ -25606,7 +26625,8 @@ pub fn _mm512_maskz_inserti64x4<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_insertf32x4<const IMM8: i32>(a: __m512, b: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_insertf32x4<const IMM8: i32>(a: __m512, b: __m128) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let b = _mm512_castps128_ps512(b);
@@ -25647,7 +26667,8 @@ pub fn _mm512_insertf32x4<const IMM8: i32>(a: __m512, b: __m128) -> __m512 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_insertf32x4<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_insertf32x4<const IMM8: i32>(
     src: __m512,
     k: __mmask16,
     a: __m512,
@@ -25668,7 +26689,12 @@ pub fn _mm512_mask_insertf32x4<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_insertf32x4<const IMM8: i32>(k: __mmask16, a: __m512, b: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_insertf32x4<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512,
+    b: __m128,
+) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let r = _mm512_insertf32x4::<IMM8>(a, b);
@@ -25687,7 +26713,8 @@ pub fn _mm512_maskz_insertf32x4<const IMM8: i32>(k: __mmask16, a: __m512, b: __m
     assert_instr(vinsert, IMM8 = 1) //should be vinsertf32x4
 )]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_insertf32x4<const IMM8: i32>(a: __m256, b: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insertf32x4<const IMM8: i32>(a: __m256, b: __m128) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm256_castps128_ps256(b);
@@ -25706,7 +26733,8 @@ pub fn _mm256_insertf32x4<const IMM8: i32>(a: __m256, b: __m128) -> __m256 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_insertf32x4<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_insertf32x4<const IMM8: i32>(
     src: __m256,
     k: __mmask8,
     a: __m256,
@@ -25727,7 +26755,12 @@ pub fn _mm256_mask_insertf32x4<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_insertf32x4<const IMM8: i32>(k: __mmask8, a: __m256, b: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_insertf32x4<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256,
+    b: __m128,
+) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm256_insertf32x4::<IMM8>(a, b);
@@ -25743,7 +26776,8 @@ pub fn _mm256_maskz_insertf32x4<const IMM8: i32>(k: __mmask8, a: __m256, b: __m1
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_insertf64x4<const IMM8: i32>(a: __m512d, b: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_insertf64x4<const IMM8: i32>(a: __m512d, b: __m256d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm512_castpd256_pd512(b);
@@ -25762,7 +26796,8 @@ pub fn _mm512_insertf64x4<const IMM8: i32>(a: __m512d, b: __m256d) -> __m512d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_insertf64x4<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_insertf64x4<const IMM8: i32>(
     src: __m512d,
     k: __mmask8,
     a: __m512d,
@@ -25783,7 +26818,12 @@ pub fn _mm512_mask_insertf64x4<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_insertf64x4<const IMM8: i32>(k: __mmask8, a: __m512d, b: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_insertf64x4<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512d,
+    b: __m256d,
+) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let r = _mm512_insertf64x4::<IMM8>(a, b);
@@ -25798,7 +26838,8 @@ pub fn _mm512_maskz_insertf64x4<const IMM8: i32>(k: __mmask8, a: __m512d, b: __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))] //should be vpunpckhdq
-pub fn _mm512_unpackhi_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpackhi_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i32x16();
         let b = b.as_i32x16();
@@ -25821,7 +26862,13 @@ pub fn _mm512_unpackhi_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhdq))]
-pub fn _mm512_mask_unpackhi_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpackhi_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i32x16()))
@@ -25835,7 +26882,8 @@ pub fn _mm512_mask_unpackhi_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhdq))]
-pub fn _mm512_maskz_unpackhi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpackhi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, unpackhi, i32x16::ZERO))
@@ -25849,7 +26897,13 @@ pub fn _mm512_maskz_unpackhi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m5
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhdq))]
-pub fn _mm256_mask_unpackhi_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpackhi_epi32(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i32x8()))
@@ -25863,7 +26917,8 @@ pub fn _mm256_mask_unpackhi_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhdq))]
-pub fn _mm256_maskz_unpackhi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpackhi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, unpackhi, i32x8::ZERO))
@@ -25877,7 +26932,8 @@ pub fn _mm256_maskz_unpackhi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhdq))]
-pub fn _mm_mask_unpackhi_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpackhi_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i32x4()))
@@ -25891,7 +26947,8 @@ pub fn _mm_mask_unpackhi_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhdq))]
-pub fn _mm_maskz_unpackhi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpackhi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, unpackhi, i32x4::ZERO))
@@ -25905,7 +26962,8 @@ pub fn _mm_maskz_unpackhi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))] //should be vpunpckhqdq
-pub fn _mm512_unpackhi_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpackhi_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_shuffle!(a, b, [1, 9, 1 + 2, 9 + 2, 1 + 4, 9 + 4, 1 + 6, 9 + 6]) }
 }
 
@@ -25916,7 +26974,13 @@ pub fn _mm512_unpackhi_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhqdq))]
-pub fn _mm512_mask_unpackhi_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpackhi_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i64x8()))
@@ -25930,7 +26994,8 @@ pub fn _mm512_mask_unpackhi_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhqdq))]
-pub fn _mm512_maskz_unpackhi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpackhi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, unpackhi, i64x8::ZERO))
@@ -25944,7 +27009,13 @@ pub fn _mm512_maskz_unpackhi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m51
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhqdq))]
-pub fn _mm256_mask_unpackhi_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpackhi_epi64(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i64x4()))
@@ -25958,7 +27029,8 @@ pub fn _mm256_mask_unpackhi_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhqdq))]
-pub fn _mm256_maskz_unpackhi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpackhi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, unpackhi, i64x4::ZERO))
@@ -25972,7 +27044,8 @@ pub fn _mm256_maskz_unpackhi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhqdq))]
-pub fn _mm_mask_unpackhi_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpackhi_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i64x2()))
@@ -25986,7 +27059,8 @@ pub fn _mm_mask_unpackhi_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhqdq))]
-pub fn _mm_maskz_unpackhi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpackhi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, unpackhi, i64x2::ZERO))
@@ -26000,7 +27074,8 @@ pub fn _mm_maskz_unpackhi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm512_unpackhi_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpackhi_ps(a: __m512, b: __m512) -> __m512 {
     unsafe {
         #[rustfmt::skip]
         simd_shuffle!(
@@ -26020,7 +27095,8 @@ pub fn _mm512_unpackhi_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm512_mask_unpackhi_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpackhi_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let unpackhi = _mm512_unpackhi_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, unpackhi, src.as_f32x16()))
@@ -26034,7 +27110,8 @@ pub fn _mm512_mask_unpackhi_ps(src: __m512, k: __mmask16, a: __m512, b: __m512)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm512_maskz_unpackhi_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpackhi_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let unpackhi = _mm512_unpackhi_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, unpackhi, f32x16::ZERO))
@@ -26048,7 +27125,8 @@ pub fn _mm512_maskz_unpackhi_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm256_mask_unpackhi_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpackhi_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let unpackhi = _mm256_unpackhi_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, unpackhi, src.as_f32x8()))
@@ -26062,7 +27140,8 @@ pub fn _mm256_mask_unpackhi_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm256_maskz_unpackhi_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpackhi_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let unpackhi = _mm256_unpackhi_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, unpackhi, f32x8::ZERO))
@@ -26076,7 +27155,8 @@ pub fn _mm256_maskz_unpackhi_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm_mask_unpackhi_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpackhi_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let unpackhi = _mm_unpackhi_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, unpackhi, src.as_f32x4()))
@@ -26090,7 +27170,8 @@ pub fn _mm_mask_unpackhi_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhps))]
-pub fn _mm_maskz_unpackhi_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpackhi_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let unpackhi = _mm_unpackhi_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, unpackhi, f32x4::ZERO))
@@ -26104,7 +27185,8 @@ pub fn _mm_maskz_unpackhi_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm512_unpackhi_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpackhi_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { simd_shuffle!(a, b, [1, 9, 1 + 2, 9 + 2, 1 + 4, 9 + 4, 1 + 6, 9 + 6]) }
 }
 
@@ -26115,7 +27197,8 @@ pub fn _mm512_unpackhi_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm512_mask_unpackhi_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpackhi_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let unpackhi = _mm512_unpackhi_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, unpackhi, src.as_f64x8()))
@@ -26129,7 +27212,8 @@ pub fn _mm512_mask_unpackhi_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm512_maskz_unpackhi_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpackhi_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let unpackhi = _mm512_unpackhi_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, unpackhi, f64x8::ZERO))
@@ -26143,7 +27227,8 @@ pub fn _mm512_maskz_unpackhi_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm256_mask_unpackhi_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpackhi_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let unpackhi = _mm256_unpackhi_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, unpackhi, src.as_f64x4()))
@@ -26157,7 +27242,8 @@ pub fn _mm256_mask_unpackhi_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm256_maskz_unpackhi_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpackhi_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let unpackhi = _mm256_unpackhi_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, unpackhi, f64x4::ZERO))
@@ -26171,7 +27257,8 @@ pub fn _mm256_maskz_unpackhi_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm_mask_unpackhi_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpackhi_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let unpackhi = _mm_unpackhi_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, unpackhi, src.as_f64x2()))
@@ -26185,7 +27272,8 @@ pub fn _mm_mask_unpackhi_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpckhpd))]
-pub fn _mm_maskz_unpackhi_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpackhi_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let unpackhi = _mm_unpackhi_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, unpackhi, f64x2::ZERO))
@@ -26199,7 +27287,8 @@ pub fn _mm_maskz_unpackhi_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))] //should be vpunpckldq
-pub fn _mm512_unpacklo_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpacklo_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i32x16();
         let b = b.as_i32x16();
@@ -26222,7 +27311,13 @@ pub fn _mm512_unpacklo_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckldq))]
-pub fn _mm512_mask_unpacklo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpacklo_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i32x16()))
@@ -26236,7 +27331,8 @@ pub fn _mm512_mask_unpacklo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckldq))]
-pub fn _mm512_maskz_unpacklo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpacklo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, unpacklo, i32x16::ZERO))
@@ -26250,7 +27346,13 @@ pub fn _mm512_maskz_unpacklo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m5
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckldq))]
-pub fn _mm256_mask_unpacklo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpacklo_epi32(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i32x8()))
@@ -26264,7 +27366,8 @@ pub fn _mm256_mask_unpacklo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckldq))]
-pub fn _mm256_maskz_unpacklo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpacklo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, unpacklo, i32x8::ZERO))
@@ -26278,7 +27381,8 @@ pub fn _mm256_maskz_unpacklo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckldq))]
-pub fn _mm_mask_unpacklo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpacklo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i32x4()))
@@ -26292,7 +27396,8 @@ pub fn _mm_mask_unpacklo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckldq))]
-pub fn _mm_maskz_unpacklo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpacklo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, unpacklo, i32x4::ZERO))
@@ -26306,7 +27411,8 @@ pub fn _mm_maskz_unpacklo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))] //should be vpunpcklqdq
-pub fn _mm512_unpacklo_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpacklo_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_shuffle!(a, b, [0, 8, 0 + 2, 8 + 2, 0 + 4, 8 + 4, 0 + 6, 8 + 6]) }
 }
 
@@ -26317,7 +27423,13 @@ pub fn _mm512_unpacklo_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklqdq))]
-pub fn _mm512_mask_unpacklo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpacklo_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i64x8()))
@@ -26331,7 +27443,8 @@ pub fn _mm512_mask_unpacklo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklqdq))]
-pub fn _mm512_maskz_unpacklo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpacklo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, unpacklo, i64x8::ZERO))
@@ -26345,7 +27458,13 @@ pub fn _mm512_maskz_unpacklo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m51
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklqdq))]
-pub fn _mm256_mask_unpacklo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpacklo_epi64(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i64x4()))
@@ -26359,7 +27478,8 @@ pub fn _mm256_mask_unpacklo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklqdq))]
-pub fn _mm256_maskz_unpacklo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpacklo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, unpacklo, i64x4::ZERO))
@@ -26373,7 +27493,8 @@ pub fn _mm256_maskz_unpacklo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklqdq))]
-pub fn _mm_mask_unpacklo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpacklo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i64x2()))
@@ -26387,7 +27508,8 @@ pub fn _mm_mask_unpacklo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklqdq))]
-pub fn _mm_maskz_unpacklo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpacklo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, unpacklo, i64x2::ZERO))
@@ -26401,7 +27523,8 @@ pub fn _mm_maskz_unpacklo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm512_unpacklo_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpacklo_ps(a: __m512, b: __m512) -> __m512 {
     unsafe {
         #[rustfmt::skip]
         simd_shuffle!(a, b,
@@ -26420,7 +27543,8 @@ pub fn _mm512_unpacklo_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm512_mask_unpacklo_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpacklo_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let unpacklo = _mm512_unpacklo_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, unpacklo, src.as_f32x16()))
@@ -26434,7 +27558,8 @@ pub fn _mm512_mask_unpacklo_ps(src: __m512, k: __mmask16, a: __m512, b: __m512)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm512_maskz_unpacklo_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpacklo_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let unpacklo = _mm512_unpacklo_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, unpacklo, f32x16::ZERO))
@@ -26448,7 +27573,8 @@ pub fn _mm512_maskz_unpacklo_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm256_mask_unpacklo_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpacklo_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let unpacklo = _mm256_unpacklo_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, unpacklo, src.as_f32x8()))
@@ -26462,7 +27588,8 @@ pub fn _mm256_mask_unpacklo_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm256_maskz_unpacklo_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpacklo_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let unpacklo = _mm256_unpacklo_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, unpacklo, f32x8::ZERO))
@@ -26476,7 +27603,8 @@ pub fn _mm256_maskz_unpacklo_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm_mask_unpacklo_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpacklo_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let unpacklo = _mm_unpacklo_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, unpacklo, src.as_f32x4()))
@@ -26490,7 +27618,8 @@ pub fn _mm_mask_unpacklo_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklps))]
-pub fn _mm_maskz_unpacklo_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpacklo_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let unpacklo = _mm_unpacklo_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, unpacklo, f32x4::ZERO))
@@ -26504,7 +27633,8 @@ pub fn _mm_maskz_unpacklo_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm512_unpacklo_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpacklo_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { simd_shuffle!(a, b, [0, 8, 0 + 2, 8 + 2, 0 + 4, 8 + 4, 0 + 6, 8 + 6]) }
 }
 
@@ -26515,7 +27645,8 @@ pub fn _mm512_unpacklo_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm512_mask_unpacklo_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpacklo_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let unpacklo = _mm512_unpacklo_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, unpacklo, src.as_f64x8()))
@@ -26529,7 +27660,8 @@ pub fn _mm512_mask_unpacklo_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm512_maskz_unpacklo_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpacklo_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let unpacklo = _mm512_unpacklo_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, unpacklo, f64x8::ZERO))
@@ -26543,7 +27675,8 @@ pub fn _mm512_maskz_unpacklo_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm256_mask_unpacklo_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpacklo_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let unpacklo = _mm256_unpacklo_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, unpacklo, src.as_f64x4()))
@@ -26557,7 +27690,8 @@ pub fn _mm256_mask_unpacklo_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm256_maskz_unpacklo_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpacklo_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let unpacklo = _mm256_unpacklo_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, unpacklo, f64x4::ZERO))
@@ -26571,7 +27705,8 @@ pub fn _mm256_maskz_unpacklo_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm_mask_unpacklo_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpacklo_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let unpacklo = _mm_unpacklo_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, unpacklo, src.as_f64x2()))
@@ -26585,7 +27720,8 @@ pub fn _mm_mask_unpacklo_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vunpcklpd))]
-pub fn _mm_maskz_unpacklo_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpacklo_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let unpacklo = _mm_unpacklo_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, unpacklo, f64x2::ZERO))
@@ -26598,7 +27734,8 @@ pub fn _mm_maskz_unpacklo_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castps128_ps512(a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps128_ps512(a: __m128) -> __m512 {
     unsafe {
         simd_shuffle!(
             a,
@@ -26614,7 +27751,8 @@ pub fn _mm512_castps128_ps512(a: __m128) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castps256_ps512(a: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps256_ps512(a: __m256) -> __m512 {
     unsafe {
         simd_shuffle!(
             a,
@@ -26630,7 +27768,8 @@ pub fn _mm512_castps256_ps512(a: __m256) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_zextps128_ps512(a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextps128_ps512(a: __m128) -> __m512 {
     unsafe {
         simd_shuffle!(
             a,
@@ -26646,7 +27785,8 @@ pub fn _mm512_zextps128_ps512(a: __m128) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_zextps256_ps512(a: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextps256_ps512(a: __m256) -> __m512 {
     unsafe {
         simd_shuffle!(
             a,
@@ -26662,7 +27802,8 @@ pub fn _mm512_zextps256_ps512(a: __m256) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castps512_ps128(a: __m512) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps512_ps128(a: __m512) -> __m128 {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
 }
 
@@ -26672,7 +27813,8 @@ pub fn _mm512_castps512_ps128(a: __m512) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castps512_ps256(a: __m512) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps512_ps256(a: __m512) -> __m256 {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
 }
 
@@ -26682,7 +27824,8 @@ pub fn _mm512_castps512_ps256(a: __m512) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castps_pd(a: __m512) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps_pd(a: __m512) -> __m512d {
     unsafe { transmute(a) }
 }
 
@@ -26692,7 +27835,8 @@ pub fn _mm512_castps_pd(a: __m512) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castps_si512(a: __m512) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps_si512(a: __m512) -> __m512i {
     unsafe { transmute(a) }
 }
 
@@ -26702,7 +27846,8 @@ pub fn _mm512_castps_si512(a: __m512) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castpd128_pd512(a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd128_pd512(a: __m128d) -> __m512d {
     unsafe { simd_shuffle!(a, _mm_undefined_pd(), [0, 1, 2, 2, 2, 2, 2, 2]) }
 }
 
@@ -26712,7 +27857,8 @@ pub fn _mm512_castpd128_pd512(a: __m128d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castpd256_pd512(a: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd256_pd512(a: __m256d) -> __m512d {
     unsafe { simd_shuffle!(a, _mm256_undefined_pd(), [0, 1, 2, 3, 4, 4, 4, 4]) }
 }
 
@@ -26722,7 +27868,8 @@ pub fn _mm512_castpd256_pd512(a: __m256d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_zextpd128_pd512(a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextpd128_pd512(a: __m128d) -> __m512d {
     unsafe { simd_shuffle!(a, _mm_set1_pd(0.), [0, 1, 2, 2, 2, 2, 2, 2]) }
 }
 
@@ -26732,7 +27879,8 @@ pub fn _mm512_zextpd128_pd512(a: __m128d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_zextpd256_pd512(a: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextpd256_pd512(a: __m256d) -> __m512d {
     unsafe { simd_shuffle!(a, _mm256_set1_pd(0.), [0, 1, 2, 3, 4, 4, 4, 4]) }
 }
 
@@ -26742,7 +27890,8 @@ pub fn _mm512_zextpd256_pd512(a: __m256d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castpd512_pd128(a: __m512d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd512_pd128(a: __m512d) -> __m128d {
     unsafe { simd_shuffle!(a, a, [0, 1]) }
 }
 
@@ -26752,7 +27901,8 @@ pub fn _mm512_castpd512_pd128(a: __m512d) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castpd512_pd256(a: __m512d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd512_pd256(a: __m512d) -> __m256d {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
 }
 
@@ -26762,7 +27912,8 @@ pub fn _mm512_castpd512_pd256(a: __m512d) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castpd_ps(a: __m512d) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd_ps(a: __m512d) -> __m512 {
     unsafe { transmute(a) }
 }
 
@@ -26772,7 +27923,8 @@ pub fn _mm512_castpd_ps(a: __m512d) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castpd_si512(a: __m512d) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd_si512(a: __m512d) -> __m512i {
     unsafe { transmute(a) }
 }
 
@@ -26782,7 +27934,8 @@ pub fn _mm512_castpd_si512(a: __m512d) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castsi128_si512(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi128_si512(a: __m128i) -> __m512i {
     unsafe { simd_shuffle!(a, _mm_undefined_si128(), [0, 1, 2, 2, 2, 2, 2, 2]) }
 }
 
@@ -26792,7 +27945,8 @@ pub fn _mm512_castsi128_si512(a: __m128i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castsi256_si512(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi256_si512(a: __m256i) -> __m512i {
     unsafe { simd_shuffle!(a, _mm256_undefined_si256(), [0, 1, 2, 3, 4, 4, 4, 4]) }
 }
 
@@ -26802,7 +27956,8 @@ pub fn _mm512_castsi256_si512(a: __m256i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_zextsi128_si512(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextsi128_si512(a: __m128i) -> __m512i {
     unsafe { simd_shuffle!(a, _mm_setzero_si128(), [0, 1, 2, 2, 2, 2, 2, 2]) }
 }
 
@@ -26812,7 +27967,8 @@ pub fn _mm512_zextsi128_si512(a: __m128i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_zextsi256_si512(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextsi256_si512(a: __m256i) -> __m512i {
     unsafe { simd_shuffle!(a, _mm256_setzero_si256(), [0, 1, 2, 3, 4, 4, 4, 4]) }
 }
 
@@ -26822,7 +27978,8 @@ pub fn _mm512_zextsi256_si512(a: __m256i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castsi512_si128(a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi512_si128(a: __m512i) -> __m128i {
     unsafe { simd_shuffle!(a, a, [0, 1]) }
 }
 
@@ -26832,7 +27989,8 @@ pub fn _mm512_castsi512_si128(a: __m512i) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castsi512_si256(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi512_si256(a: __m512i) -> __m256i {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
 }
 
@@ -26842,7 +28000,8 @@ pub fn _mm512_castsi512_si256(a: __m512i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castsi512_ps(a: __m512i) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi512_ps(a: __m512i) -> __m512 {
     unsafe { transmute(a) }
 }
 
@@ -26852,7 +28011,8 @@ pub fn _mm512_castsi512_ps(a: __m512i) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_castsi512_pd(a: __m512i) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi512_pd(a: __m512i) -> __m512d {
     unsafe { transmute(a) }
 }
 
@@ -26863,7 +28023,8 @@ pub fn _mm512_castsi512_pd(a: __m512i) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovd))]
-pub fn _mm512_cvtsi512_si32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtsi512_si32(a: __m512i) -> i32 {
     unsafe { simd_extract!(a.as_i32x16(), 0) }
 }
 
@@ -26873,7 +28034,8 @@ pub fn _mm512_cvtsi512_si32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_cvtss_f32(a: __m512) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtss_f32(a: __m512) -> f32 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -26883,7 +28045,8 @@ pub fn _mm512_cvtss_f32(a: __m512) -> f32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_cvtsd_f64(a: __m512d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtsd_f64(a: __m512d) -> f64 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -26894,7 +28057,8 @@ pub fn _mm512_cvtsd_f64(a: __m512d) -> f64 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcast))] //should be vpbroadcastd
-pub fn _mm512_broadcastd_epi32(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastd_epi32(a: __m128i) -> __m512i {
     unsafe {
         let a = _mm512_castsi128_si512(a).as_i32x16();
         let ret: i32x16 = simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]);
@@ -26909,7 +28073,8 @@ pub fn _mm512_broadcastd_epi32(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
-pub fn _mm512_mask_broadcastd_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcastd_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastd_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, broadcast, src.as_i32x16()))
@@ -26923,7 +28088,8 @@ pub fn _mm512_mask_broadcastd_epi32(src: __m512i, k: __mmask16, a: __m128i) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
-pub fn _mm512_maskz_broadcastd_epi32(k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcastd_epi32(k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastd_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, broadcast, i32x16::ZERO))
@@ -26937,7 +28103,8 @@ pub fn _mm512_maskz_broadcastd_epi32(k: __mmask16, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
-pub fn _mm256_mask_broadcastd_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcastd_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastd_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_i32x8()))
@@ -26951,7 +28118,8 @@ pub fn _mm256_mask_broadcastd_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
-pub fn _mm256_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastd_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, broadcast, i32x8::ZERO))
@@ -26965,7 +28133,8 @@ pub fn _mm256_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
-pub fn _mm_mask_broadcastd_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_broadcastd_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastd_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, broadcast, src.as_i32x4()))
@@ -26979,7 +28148,8 @@ pub fn _mm_mask_broadcastd_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
-pub fn _mm_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastd_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, broadcast, i32x4::ZERO))
@@ -26993,7 +28163,8 @@ pub fn _mm_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcast))] //should be vpbroadcastq
-pub fn _mm512_broadcastq_epi64(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastq_epi64(a: __m128i) -> __m512i {
     unsafe { simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0]) }
 }
 
@@ -27004,7 +28175,8 @@ pub fn _mm512_broadcastq_epi64(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
-pub fn _mm512_mask_broadcastq_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcastq_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastq_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_i64x8()))
@@ -27018,7 +28190,8 @@ pub fn _mm512_mask_broadcastq_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
-pub fn _mm512_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastq_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, broadcast, i64x8::ZERO))
@@ -27032,7 +28205,8 @@ pub fn _mm512_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
-pub fn _mm256_mask_broadcastq_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcastq_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastq_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, broadcast, src.as_i64x4()))
@@ -27046,7 +28220,8 @@ pub fn _mm256_mask_broadcastq_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
-pub fn _mm256_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastq_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, broadcast, i64x4::ZERO))
@@ -27060,7 +28235,8 @@ pub fn _mm256_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
-pub fn _mm_mask_broadcastq_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_broadcastq_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastq_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, broadcast, src.as_i64x2()))
@@ -27074,7 +28250,8 @@ pub fn _mm_mask_broadcastq_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
-pub fn _mm_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastq_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, broadcast, i64x2::ZERO))
@@ -27088,7 +28265,8 @@ pub fn _mm_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm512_broadcastss_ps(a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastss_ps(a: __m128) -> __m512 {
     unsafe { simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]) }
 }
 
@@ -27099,7 +28277,8 @@ pub fn _mm512_broadcastss_ps(a: __m128) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm512_mask_broadcastss_ps(src: __m512, k: __mmask16, a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcastss_ps(src: __m512, k: __mmask16, a: __m128) -> __m512 {
     unsafe {
         let broadcast = _mm512_broadcastss_ps(a).as_f32x16();
         transmute(simd_select_bitmask(k, broadcast, src.as_f32x16()))
@@ -27113,7 +28292,8 @@ pub fn _mm512_mask_broadcastss_ps(src: __m512, k: __mmask16, a: __m128) -> __m51
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm512_maskz_broadcastss_ps(k: __mmask16, a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcastss_ps(k: __mmask16, a: __m128) -> __m512 {
     unsafe {
         let broadcast = _mm512_broadcastss_ps(a).as_f32x16();
         transmute(simd_select_bitmask(k, broadcast, f32x16::ZERO))
@@ -27127,7 +28307,8 @@ pub fn _mm512_maskz_broadcastss_ps(k: __mmask16, a: __m128) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm256_mask_broadcastss_ps(src: __m256, k: __mmask8, a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcastss_ps(src: __m256, k: __mmask8, a: __m128) -> __m256 {
     unsafe {
         let broadcast = _mm256_broadcastss_ps(a).as_f32x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_f32x8()))
@@ -27141,7 +28322,8 @@ pub fn _mm256_mask_broadcastss_ps(src: __m256, k: __mmask8, a: __m128) -> __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm256_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m256 {
     unsafe {
         let broadcast = _mm256_broadcastss_ps(a).as_f32x8();
         transmute(simd_select_bitmask(k, broadcast, f32x8::ZERO))
@@ -27155,7 +28337,8 @@ pub fn _mm256_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm_mask_broadcastss_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_broadcastss_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let broadcast = _mm_broadcastss_ps(a).as_f32x4();
         transmute(simd_select_bitmask(k, broadcast, src.as_f32x4()))
@@ -27169,7 +28352,8 @@ pub fn _mm_mask_broadcastss_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastss))]
-pub fn _mm_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m128 {
     unsafe {
         let broadcast = _mm_broadcastss_ps(a).as_f32x4();
         transmute(simd_select_bitmask(k, broadcast, f32x4::ZERO))
@@ -27183,7 +28367,8 @@ pub fn _mm_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
-pub fn _mm512_broadcastsd_pd(a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastsd_pd(a: __m128d) -> __m512d {
     unsafe { simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0]) }
 }
 
@@ -27194,7 +28379,8 @@ pub fn _mm512_broadcastsd_pd(a: __m128d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
-pub fn _mm512_mask_broadcastsd_pd(src: __m512d, k: __mmask8, a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcastsd_pd(src: __m512d, k: __mmask8, a: __m128d) -> __m512d {
     unsafe {
         let broadcast = _mm512_broadcastsd_pd(a).as_f64x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_f64x8()))
@@ -27208,7 +28394,8 @@ pub fn _mm512_mask_broadcastsd_pd(src: __m512d, k: __mmask8, a: __m128d) -> __m5
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
-pub fn _mm512_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m512d {
     unsafe {
         let broadcast = _mm512_broadcastsd_pd(a).as_f64x8();
         transmute(simd_select_bitmask(k, broadcast, f64x8::ZERO))
@@ -27222,7 +28409,8 @@ pub fn _mm512_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
-pub fn _mm256_mask_broadcastsd_pd(src: __m256d, k: __mmask8, a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcastsd_pd(src: __m256d, k: __mmask8, a: __m128d) -> __m256d {
     unsafe {
         let broadcast = _mm256_broadcastsd_pd(a).as_f64x4();
         transmute(simd_select_bitmask(k, broadcast, src.as_f64x4()))
@@ -27236,7 +28424,8 @@ pub fn _mm256_mask_broadcastsd_pd(src: __m256d, k: __mmask8, a: __m128d) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vbroadcastsd))]
-pub fn _mm256_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m256d {
     unsafe {
         let broadcast = _mm256_broadcastsd_pd(a).as_f64x4();
         transmute(simd_select_bitmask(k, broadcast, f64x4::ZERO))
@@ -27249,7 +28438,8 @@ pub fn _mm256_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_i32x4(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_i32x4(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_i32x4();
         let ret: i32x16 = simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3]);
@@ -27263,7 +28453,8 @@ pub fn _mm512_broadcast_i32x4(a: __m128i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_i32x4(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_i32x4(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcast_i32x4(a).as_i32x16();
         transmute(simd_select_bitmask(k, broadcast, src.as_i32x16()))
@@ -27276,7 +28467,8 @@ pub fn _mm512_mask_broadcast_i32x4(src: __m512i, k: __mmask16, a: __m128i) -> __
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_i32x4(k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_i32x4(k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcast_i32x4(a).as_i32x16();
         transmute(simd_select_bitmask(k, broadcast, i32x16::ZERO))
@@ -27289,7 +28481,8 @@ pub fn _mm512_maskz_broadcast_i32x4(k: __mmask16, a: __m128i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcasti32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_broadcast_i32x4(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_i32x4(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i32x4();
         let ret: i32x8 = simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]);
@@ -27303,7 +28496,8 @@ pub fn _mm256_broadcast_i32x4(a: __m128i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcasti32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_broadcast_i32x4(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcast_i32x4(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcast_i32x4(a).as_i32x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_i32x8()))
@@ -27316,7 +28510,8 @@ pub fn _mm256_mask_broadcast_i32x4(src: __m256i, k: __mmask8, a: __m128i) -> __m
 #[inline]
 #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcasti32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_broadcast_i32x4(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcast_i32x4(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcast_i32x4(a).as_i32x8();
         transmute(simd_select_bitmask(k, broadcast, i32x8::ZERO))
@@ -27329,7 +28524,8 @@ pub fn _mm256_maskz_broadcast_i32x4(k: __mmask8, a: __m128i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_i64x4(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_i64x4(a: __m256i) -> __m512i {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]) }
 }
 
@@ -27339,7 +28535,8 @@ pub fn _mm512_broadcast_i64x4(a: __m256i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_i64x4(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_i64x4(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcast_i64x4(a).as_i64x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_i64x8()))
@@ -27352,7 +28549,8 @@ pub fn _mm512_mask_broadcast_i64x4(src: __m512i, k: __mmask8, a: __m256i) -> __m
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_i64x4(k: __mmask8, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_i64x4(k: __mmask8, a: __m256i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcast_i64x4(a).as_i64x8();
         transmute(simd_select_bitmask(k, broadcast, i64x8::ZERO))
@@ -27365,7 +28563,8 @@ pub fn _mm512_maskz_broadcast_i64x4(k: __mmask8, a: __m256i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_f32x4(a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_f32x4(a: __m128) -> __m512 {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3]) }
 }
 
@@ -27375,7 +28574,8 @@ pub fn _mm512_broadcast_f32x4(a: __m128) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshu
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_f32x4(src: __m512, k: __mmask16, a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_f32x4(src: __m512, k: __mmask16, a: __m128) -> __m512 {
     unsafe {
         let broadcast = _mm512_broadcast_f32x4(a).as_f32x16();
         transmute(simd_select_bitmask(k, broadcast, src.as_f32x16()))
@@ -27388,7 +28588,8 @@ pub fn _mm512_mask_broadcast_f32x4(src: __m512, k: __mmask16, a: __m128) -> __m5
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshu
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_f32x4(k: __mmask16, a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_f32x4(k: __mmask16, a: __m128) -> __m512 {
     unsafe {
         let broadcast = _mm512_broadcast_f32x4(a).as_f32x16();
         transmute(simd_select_bitmask(k, broadcast, f32x16::ZERO))
@@ -27401,7 +28602,8 @@ pub fn _mm512_maskz_broadcast_f32x4(k: __mmask16, a: __m128) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcastf32x4, linux: vshuf
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_broadcast_f32x4(a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_f32x4(a: __m128) -> __m256 {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]) }
 }
 
@@ -27411,7 +28613,8 @@ pub fn _mm256_broadcast_f32x4(a: __m128) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcastf32x4, linux: vshu
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_broadcast_f32x4(src: __m256, k: __mmask8, a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcast_f32x4(src: __m256, k: __mmask8, a: __m128) -> __m256 {
     unsafe {
         let broadcast = _mm256_broadcast_f32x4(a).as_f32x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_f32x8()))
@@ -27424,7 +28627,8 @@ pub fn _mm256_mask_broadcast_f32x4(src: __m256, k: __mmask8, a: __m128) -> __m25
 #[inline]
 #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcastf32x4, linux: vshu
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_broadcast_f32x4(k: __mmask8, a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcast_f32x4(k: __mmask8, a: __m128) -> __m256 {
     unsafe {
         let broadcast = _mm256_broadcast_f32x4(a).as_f32x8();
         transmute(simd_select_bitmask(k, broadcast, f32x8::ZERO))
@@ -27437,7 +28641,8 @@ pub fn _mm256_maskz_broadcast_f32x4(k: __mmask8, a: __m128) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vperm
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_f64x4(a: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_f64x4(a: __m256d) -> __m512d {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]) }
 }
 
@@ -27447,7 +28652,8 @@ pub fn _mm512_broadcast_f64x4(a: __m256d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vper
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_f64x4(src: __m512d, k: __mmask8, a: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_f64x4(src: __m512d, k: __mmask8, a: __m256d) -> __m512d {
     unsafe {
         let broadcast = _mm512_broadcast_f64x4(a).as_f64x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_f64x8()))
@@ -27460,7 +28666,8 @@ pub fn _mm512_mask_broadcast_f64x4(src: __m512d, k: __mmask8, a: __m256d) -> __m
 #[inline]
 #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vper
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_f64x4(k: __mmask8, a: __m256d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_f64x4(k: __mmask8, a: __m256d) -> __m512d {
     unsafe {
         let broadcast = _mm512_broadcast_f64x4(a).as_f64x8();
         transmute(simd_select_bitmask(k, broadcast, f64x8::ZERO))
@@ -27474,7 +28681,8 @@ pub fn _mm512_maskz_broadcast_f64x4(k: __mmask8, a: __m256d) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd
-pub fn _mm512_mask_blend_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i32x16(), a.as_i32x16())) }
 }
 
@@ -27485,7 +28693,8 @@ pub fn _mm512_mask_blend_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd
-pub fn _mm256_mask_blend_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i32x8(), a.as_i32x8())) }
 }
 
@@ -27496,7 +28705,8 @@ pub fn _mm256_mask_blend_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd
-pub fn _mm_mask_blend_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i32x4(), a.as_i32x4())) }
 }
 
@@ -27507,7 +28717,8 @@ pub fn _mm_mask_blend_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq
-pub fn _mm512_mask_blend_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i64x8(), a.as_i64x8())) }
 }
 
@@ -27518,7 +28729,8 @@ pub fn _mm512_mask_blend_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq
-pub fn _mm256_mask_blend_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i64x4(), a.as_i64x4())) }
 }
 
@@ -27529,7 +28741,8 @@ pub fn _mm256_mask_blend_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq
-pub fn _mm_mask_blend_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i64x2(), a.as_i64x2())) }
 }
 
@@ -27540,7 +28753,8 @@ pub fn _mm_mask_blend_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps
-pub fn _mm512_mask_blend_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe { transmute(simd_select_bitmask(k, b.as_f32x16(), a.as_f32x16())) }
 }
 
@@ -27551,7 +28765,8 @@ pub fn _mm512_mask_blend_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps
-pub fn _mm256_mask_blend_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe { transmute(simd_select_bitmask(k, b.as_f32x8(), a.as_f32x8())) }
 }
 
@@ -27562,7 +28777,8 @@ pub fn _mm256_mask_blend_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps
-pub fn _mm_mask_blend_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe { transmute(simd_select_bitmask(k, b.as_f32x4(), a.as_f32x4())) }
 }
 
@@ -27573,7 +28789,8 @@ pub fn _mm_mask_blend_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd
-pub fn _mm512_mask_blend_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_select_bitmask(k, b.as_f64x8(), a.as_f64x8())) }
 }
 
@@ -27584,7 +28801,8 @@ pub fn _mm512_mask_blend_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd
-pub fn _mm256_mask_blend_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe { transmute(simd_select_bitmask(k, b.as_f64x4(), a.as_f64x4())) }
 }
 
@@ -27595,7 +28813,8 @@ pub fn _mm256_mask_blend_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd
-pub fn _mm_mask_blend_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe { transmute(simd_select_bitmask(k, b.as_f64x2(), a.as_f64x2())) }
 }
 
@@ -27609,7 +28828,8 @@ pub fn _mm_mask_blend_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_alignr_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_alignr_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let a = a.as_i32x16();
@@ -27690,7 +28910,8 @@ pub fn _mm512_alignr_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_alignr_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_alignr_epi32<const IMM8: i32>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -27711,7 +28932,12 @@ pub fn _mm512_mask_alignr_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_alignr_epi32<const IMM8: i32>(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_alignr_epi32<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm512_alignr_epi32::<IMM8>(a, b);
@@ -27729,7 +28955,8 @@ pub fn _mm512_maskz_alignr_epi32<const IMM8: i32>(k: __mmask16, a: __m512i, b: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_alignr_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_alignr_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let a = a.as_i32x8();
@@ -27758,7 +28985,8 @@ pub fn _mm256_alignr_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_alignr_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_alignr_epi32<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -27779,7 +29007,12 @@ pub fn _mm256_mask_alignr_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_alignr_epi32<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_alignr_epi32<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm256_alignr_epi32::<IMM8>(a, b);
@@ -27797,7 +29030,8 @@ pub fn _mm256_maskz_alignr_epi32<const IMM8: i32>(k: __mmask8, a: __m256i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] //should be valignd
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_alignr_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_alignr_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let a = a.as_i32x4();
@@ -27822,7 +29056,8 @@ pub fn _mm_alignr_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_alignr_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_alignr_epi32<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -27843,7 +29078,12 @@ pub fn _mm_mask_alignr_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_alignr_epi32<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_alignr_epi32<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm_alignr_epi32::<IMM8>(a, b);
@@ -27861,7 +29101,8 @@ pub fn _mm_maskz_alignr_epi32<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m12
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_alignr_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_alignr_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let imm8: i32 = IMM8 % 8;
@@ -27888,7 +29129,8 @@ pub fn _mm512_alignr_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_alignr_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_alignr_epi64<const IMM8: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -27909,7 +29151,12 @@ pub fn _mm512_mask_alignr_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_alignr_epi64<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_alignr_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm512_alignr_epi64::<IMM8>(a, b);
@@ -27927,7 +29174,8 @@ pub fn _mm512_maskz_alignr_epi64<const IMM8: i32>(k: __mmask8, a: __m512i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_alignr_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_alignr_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let imm8: i32 = IMM8 % 4;
@@ -27950,7 +29198,8 @@ pub fn _mm256_alignr_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_alignr_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_alignr_epi64<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -27971,7 +29220,12 @@ pub fn _mm256_mask_alignr_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_alignr_epi64<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_alignr_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm256_alignr_epi64::<IMM8>(a, b);
@@ -27989,7 +29243,8 @@ pub fn _mm256_maskz_alignr_epi64<const IMM8: i32>(k: __mmask8, a: __m256i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] //should be valignq
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_alignr_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_alignr_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let imm8: i32 = IMM8 % 2;
@@ -28010,7 +29265,8 @@ pub fn _mm_alignr_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_alignr_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_alignr_epi64<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -28031,7 +29287,12 @@ pub fn _mm_mask_alignr_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_alignr_epi64<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_alignr_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm_alignr_epi64::<IMM8>(a, b);
@@ -28046,7 +29307,8 @@ pub fn _mm_maskz_alignr_epi64<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))] //should be vpandd, but generate vpandq
-pub fn _mm512_and_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_and_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_and(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -28057,7 +29319,8 @@ pub fn _mm512_and_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm512_mask_and_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_and_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let and = _mm512_and_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, and, src.as_i32x16()))
@@ -28071,7 +29334,8 @@ pub fn _mm512_mask_and_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm512_maskz_and_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_and_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let and = _mm512_and_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, and, i32x16::ZERO))
@@ -28085,7 +29349,8 @@ pub fn _mm512_maskz_and_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm256_mask_and_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_and_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let and = simd_and(a.as_i32x8(), b.as_i32x8());
         transmute(simd_select_bitmask(k, and, src.as_i32x8()))
@@ -28099,7 +29364,8 @@ pub fn _mm256_mask_and_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm256_maskz_and_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_and_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let and = simd_and(a.as_i32x8(), b.as_i32x8());
         transmute(simd_select_bitmask(k, and, i32x8::ZERO))
@@ -28113,7 +29379,8 @@ pub fn _mm256_maskz_and_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm_mask_and_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_and_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let and = simd_and(a.as_i32x4(), b.as_i32x4());
         transmute(simd_select_bitmask(k, and, src.as_i32x4()))
@@ -28127,7 +29394,8 @@ pub fn _mm_mask_and_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandd))]
-pub fn _mm_maskz_and_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_and_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let and = simd_and(a.as_i32x4(), b.as_i32x4());
         transmute(simd_select_bitmask(k, and, i32x4::ZERO))
@@ -28141,7 +29409,8 @@ pub fn _mm_maskz_and_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm512_and_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_and_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_and(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -28152,7 +29421,8 @@ pub fn _mm512_and_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm512_mask_and_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_and_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let and = _mm512_and_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, and, src.as_i64x8()))
@@ -28166,7 +29436,8 @@ pub fn _mm512_mask_and_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm512_maskz_and_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_and_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let and = _mm512_and_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, and, i64x8::ZERO))
@@ -28180,7 +29451,8 @@ pub fn _mm512_maskz_and_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm256_mask_and_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_and_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let and = simd_and(a.as_i64x4(), b.as_i64x4());
         transmute(simd_select_bitmask(k, and, src.as_i64x4()))
@@ -28194,7 +29466,8 @@ pub fn _mm256_mask_and_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm256_maskz_and_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_and_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let and = simd_and(a.as_i64x4(), b.as_i64x4());
         transmute(simd_select_bitmask(k, and, i64x4::ZERO))
@@ -28208,7 +29481,8 @@ pub fn _mm256_maskz_and_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm_mask_and_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_and_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let and = simd_and(a.as_i64x2(), b.as_i64x2());
         transmute(simd_select_bitmask(k, and, src.as_i64x2()))
@@ -28222,7 +29496,8 @@ pub fn _mm_mask_and_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm_maskz_and_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_and_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let and = simd_and(a.as_i64x2(), b.as_i64x2());
         transmute(simd_select_bitmask(k, and, i64x2::ZERO))
@@ -28236,7 +29511,8 @@ pub fn _mm_maskz_and_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandq))]
-pub fn _mm512_and_si512(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_and_si512(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_and(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -28247,7 +29523,8 @@ pub fn _mm512_and_si512(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm512_or_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_or_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_or(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -28258,7 +29535,8 @@ pub fn _mm512_or_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpord))]
-pub fn _mm512_mask_or_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_or_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let or = _mm512_or_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, or, src.as_i32x16()))
@@ -28272,7 +29550,8 @@ pub fn _mm512_mask_or_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpord))]
-pub fn _mm512_maskz_or_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_or_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let or = _mm512_or_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, or, i32x16::ZERO))
@@ -28286,7 +29565,8 @@ pub fn _mm512_maskz_or_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vor))] //should be vpord
-pub fn _mm256_or_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_or_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_or(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -28297,7 +29577,8 @@ pub fn _mm256_or_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpord))]
-pub fn _mm256_mask_or_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_or_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let or = _mm256_or_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, or, src.as_i32x8()))
@@ -28311,7 +29592,8 @@ pub fn _mm256_mask_or_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpord))]
-pub fn _mm256_maskz_or_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_or_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let or = _mm256_or_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, or, i32x8::ZERO))
@@ -28325,7 +29607,8 @@ pub fn _mm256_maskz_or_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vor))] //should be vpord
-pub fn _mm_or_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_or_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_or(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -28336,7 +29619,8 @@ pub fn _mm_or_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpord))]
-pub fn _mm_mask_or_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_or_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let or = _mm_or_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, or, src.as_i32x4()))
@@ -28350,7 +29634,8 @@ pub fn _mm_mask_or_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpord))]
-pub fn _mm_maskz_or_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_or_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let or = _mm_or_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, or, i32x4::ZERO))
@@ -28364,7 +29649,8 @@ pub fn _mm_maskz_or_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm512_or_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_or_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_or(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -28375,7 +29661,8 @@ pub fn _mm512_or_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm512_mask_or_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_or_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let or = _mm512_or_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, or, src.as_i64x8()))
@@ -28389,7 +29676,8 @@ pub fn _mm512_mask_or_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm512_maskz_or_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_or_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let or = _mm512_or_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, or, i64x8::ZERO))
@@ -28403,7 +29691,8 @@ pub fn _mm512_maskz_or_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vor))] //should be vporq
-pub fn _mm256_or_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_or_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_or(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -28414,7 +29703,8 @@ pub fn _mm256_or_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm256_mask_or_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_or_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let or = _mm256_or_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, or, src.as_i64x4()))
@@ -28428,7 +29718,8 @@ pub fn _mm256_mask_or_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm256_maskz_or_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_or_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let or = _mm256_or_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, or, i64x4::ZERO))
@@ -28442,7 +29733,8 @@ pub fn _mm256_maskz_or_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vor))] //should be vporq
-pub fn _mm_or_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_or_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_or(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -28453,7 +29745,8 @@ pub fn _mm_or_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm_mask_or_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_or_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let or = _mm_or_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, or, src.as_i64x2()))
@@ -28467,7 +29760,8 @@ pub fn _mm_mask_or_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm_maskz_or_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_or_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let or = _mm_or_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, or, i64x2::ZERO))
@@ -28481,7 +29775,8 @@ pub fn _mm_maskz_or_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vporq))]
-pub fn _mm512_or_si512(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_or_si512(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_or(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -28492,7 +29787,8 @@ pub fn _mm512_or_si512(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))] //should be vpxord
-pub fn _mm512_xor_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_xor_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_xor(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -28503,7 +29799,8 @@ pub fn _mm512_xor_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxord))]
-pub fn _mm512_mask_xor_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_xor_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let xor = _mm512_xor_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, xor, src.as_i32x16()))
@@ -28517,7 +29814,8 @@ pub fn _mm512_mask_xor_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxord))]
-pub fn _mm512_maskz_xor_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_xor_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let xor = _mm512_xor_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, xor, i32x16::ZERO))
@@ -28531,7 +29829,8 @@ pub fn _mm512_maskz_xor_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxor))] //should be vpxord
-pub fn _mm256_xor_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_xor_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_xor(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -28542,7 +29841,8 @@ pub fn _mm256_xor_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxord))]
-pub fn _mm256_mask_xor_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_xor_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let xor = _mm256_xor_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, xor, src.as_i32x8()))
@@ -28556,7 +29856,8 @@ pub fn _mm256_mask_xor_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxord))]
-pub fn _mm256_maskz_xor_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_xor_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let xor = _mm256_xor_epi32(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, xor, i32x8::ZERO))
@@ -28570,7 +29871,8 @@ pub fn _mm256_maskz_xor_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxor))] //should be vpxord
-pub fn _mm_xor_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_xor_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_xor(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -28581,7 +29883,8 @@ pub fn _mm_xor_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxord))]
-pub fn _mm_mask_xor_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_xor_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let xor = _mm_xor_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, xor, src.as_i32x4()))
@@ -28595,7 +29898,8 @@ pub fn _mm_mask_xor_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxord))]
-pub fn _mm_maskz_xor_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_xor_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let xor = _mm_xor_epi32(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, xor, i32x4::ZERO))
@@ -28609,7 +29913,8 @@ pub fn _mm_maskz_xor_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm512_xor_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_xor_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_xor(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -28620,7 +29925,8 @@ pub fn _mm512_xor_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm512_mask_xor_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_xor_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let xor = _mm512_xor_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, xor, src.as_i64x8()))
@@ -28634,7 +29940,8 @@ pub fn _mm512_mask_xor_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm512_maskz_xor_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_xor_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let xor = _mm512_xor_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, xor, i64x8::ZERO))
@@ -28648,7 +29955,8 @@ pub fn _mm512_maskz_xor_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxor))] //should be vpxorq
-pub fn _mm256_xor_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_xor_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_xor(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -28659,7 +29967,8 @@ pub fn _mm256_xor_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm256_mask_xor_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_xor_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let xor = _mm256_xor_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, xor, src.as_i64x4()))
@@ -28673,7 +29982,8 @@ pub fn _mm256_mask_xor_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm256_maskz_xor_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_xor_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let xor = _mm256_xor_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, xor, i64x4::ZERO))
@@ -28687,7 +29997,8 @@ pub fn _mm256_maskz_xor_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vxor))] //should be vpxorq
-pub fn _mm_xor_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_xor_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_xor(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -28698,7 +30009,8 @@ pub fn _mm_xor_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm_mask_xor_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_xor_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let xor = _mm_xor_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, xor, src.as_i64x2()))
@@ -28712,7 +30024,8 @@ pub fn _mm_mask_xor_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm_maskz_xor_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_xor_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let xor = _mm_xor_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, xor, i64x2::ZERO))
@@ -28726,7 +30039,8 @@ pub fn _mm_maskz_xor_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpxorq))]
-pub fn _mm512_xor_si512(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_xor_si512(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_xor(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -28737,7 +30051,8 @@ pub fn _mm512_xor_si512(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))] //should be vpandnd
-pub fn _mm512_andnot_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_andnot_epi32(a: __m512i, b: __m512i) -> __m512i {
     _mm512_and_epi32(_mm512_xor_epi32(a, _mm512_set1_epi32(u32::MAX as i32)), b)
 }
 
@@ -28748,7 +30063,13 @@ pub fn _mm512_andnot_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnd))]
-pub fn _mm512_mask_andnot_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_andnot_epi32(
+    src: __m512i,
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let andnot = _mm512_andnot_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, andnot, src.as_i32x16()))
@@ -28762,7 +30083,8 @@ pub fn _mm512_mask_andnot_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m51
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnd))]
-pub fn _mm512_maskz_andnot_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_andnot_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let andnot = _mm512_andnot_epi32(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, andnot, i32x16::ZERO))
@@ -28776,7 +30098,13 @@ pub fn _mm512_maskz_andnot_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnd))]
-pub fn _mm256_mask_andnot_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_andnot_epi32(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let not = _mm256_xor_epi32(a, _mm256_set1_epi32(u32::MAX as i32));
         let andnot = simd_and(not.as_i32x8(), b.as_i32x8());
@@ -28791,7 +30119,8 @@ pub fn _mm256_mask_andnot_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnd))]
-pub fn _mm256_maskz_andnot_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_andnot_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let not = _mm256_xor_epi32(a, _mm256_set1_epi32(u32::MAX as i32));
         let andnot = simd_and(not.as_i32x8(), b.as_i32x8());
@@ -28806,7 +30135,8 @@ pub fn _mm256_maskz_andnot_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnd))]
-pub fn _mm_mask_andnot_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_andnot_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let not = _mm_xor_epi32(a, _mm_set1_epi32(u32::MAX as i32));
         let andnot = simd_and(not.as_i32x4(), b.as_i32x4());
@@ -28821,7 +30151,8 @@ pub fn _mm_mask_andnot_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnd))]
-pub fn _mm_maskz_andnot_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_andnot_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let not = _mm_xor_epi32(a, _mm_set1_epi32(u32::MAX as i32));
         let andnot = simd_and(not.as_i32x4(), b.as_i32x4());
@@ -28836,7 +30167,8 @@ pub fn _mm_maskz_andnot_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))] //should be vpandnd
-pub fn _mm512_andnot_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_andnot_epi64(a: __m512i, b: __m512i) -> __m512i {
     _mm512_and_epi64(_mm512_xor_epi64(a, _mm512_set1_epi64(u64::MAX as i64)), b)
 }
 
@@ -28847,7 +30179,13 @@ pub fn _mm512_andnot_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm512_mask_andnot_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_andnot_epi64(
+    src: __m512i,
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let andnot = _mm512_andnot_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, andnot, src.as_i64x8()))
@@ -28861,7 +30199,8 @@ pub fn _mm512_mask_andnot_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm512_maskz_andnot_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_andnot_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let andnot = _mm512_andnot_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, andnot, i64x8::ZERO))
@@ -28875,7 +30214,13 @@ pub fn _mm512_maskz_andnot_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm256_mask_andnot_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_andnot_epi64(
+    src: __m256i,
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let not = _mm256_xor_epi64(a, _mm256_set1_epi64x(u64::MAX as i64));
         let andnot = simd_and(not.as_i64x4(), b.as_i64x4());
@@ -28890,7 +30235,8 @@ pub fn _mm256_mask_andnot_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm256_maskz_andnot_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_andnot_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let not = _mm256_xor_epi64(a, _mm256_set1_epi64x(u64::MAX as i64));
         let andnot = simd_and(not.as_i64x4(), b.as_i64x4());
@@ -28905,7 +30251,8 @@ pub fn _mm256_maskz_andnot_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm_mask_andnot_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_andnot_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let not = _mm_xor_epi64(a, _mm_set1_epi64x(u64::MAX as i64));
         let andnot = simd_and(not.as_i64x2(), b.as_i64x2());
@@ -28920,7 +30267,8 @@ pub fn _mm_mask_andnot_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm_maskz_andnot_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_andnot_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let not = _mm_xor_epi64(a, _mm_set1_epi64x(u64::MAX as i64));
         let andnot = simd_and(not.as_i64x2(), b.as_i64x2());
@@ -28935,7 +30283,8 @@ pub fn _mm_maskz_andnot_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpandnq))]
-pub fn _mm512_andnot_si512(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_andnot_si512(a: __m512i, b: __m512i) -> __m512i {
     _mm512_and_epi64(_mm512_xor_epi64(a, _mm512_set1_epi64(u64::MAX as i64)), b)
 }
 
@@ -28945,7 +30294,8 @@ pub fn _mm512_andnot_si512(a: __m512i, b: __m512i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtmask16_u32(a: __mmask16) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtmask16_u32(a: __mmask16) -> u32 {
     a as u32
 }
 
@@ -28955,7 +30305,8 @@ pub fn _cvtmask16_u32(a: __mmask16) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtu32_mask16(a: u32) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtu32_mask16(a: u32) -> __mmask16 {
     a as __mmask16
 }
 
@@ -28966,7 +30317,8 @@ pub fn _cvtu32_mask16(a: u32) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(and))] // generate normal and code instead of kandw
-pub fn _kand_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kand_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
     a & b
 }
 
@@ -28977,7 +30329,8 @@ pub fn _kand_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(and))] // generate normal and code instead of kandw
-pub fn _mm512_kand(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kand(a: __mmask16, b: __mmask16) -> __mmask16 {
     a & b
 }
 
@@ -28988,7 +30341,8 @@ pub fn _mm512_kand(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(or))] // generate normal or code instead of korw
-pub fn _kor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
     a | b
 }
 
@@ -28999,7 +30353,8 @@ pub fn _kor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(or))] // generate normal or code instead of korw
-pub fn _mm512_kor(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kor(a: __mmask16, b: __mmask16) -> __mmask16 {
     a | b
 }
 
@@ -29010,7 +30365,8 @@ pub fn _mm512_kor(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(xor))] // generate normal xor code instead of kxorw
-pub fn _kxor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
     a ^ b
 }
 
@@ -29021,7 +30377,8 @@ pub fn _kxor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(xor))] // generate normal xor code instead of kxorw
-pub fn _mm512_kxor(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kxor(a: __mmask16, b: __mmask16) -> __mmask16 {
     a ^ b
 }
 
@@ -29031,7 +30388,8 @@ pub fn _mm512_kxor(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _knot_mask16(a: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _knot_mask16(a: __mmask16) -> __mmask16 {
     a ^ 0b11111111_11111111
 }
 
@@ -29041,7 +30399,8 @@ pub fn _knot_mask16(a: __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_knot(a: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_knot(a: __mmask16) -> __mmask16 {
     a ^ 0b11111111_11111111
 }
 
@@ -29052,7 +30411,8 @@ pub fn _mm512_knot(a: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(not))] // generate normal and, not code instead of kandnw
-pub fn _kandn_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kandn_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
     _mm512_kand(_mm512_knot(a), b)
 }
 
@@ -29063,7 +30423,8 @@ pub fn _kandn_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(not))] // generate normal and code instead of kandw
-pub fn _mm512_kandn(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kandn(a: __mmask16, b: __mmask16) -> __mmask16 {
     _mm512_kand(_mm512_knot(a), b)
 }
 
@@ -29074,7 +30435,8 @@ pub fn _mm512_kandn(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(xor))] // generate normal xor, not code instead of kxnorw
-pub fn _kxnor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxnor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
     _mm512_knot(_mm512_kxor(a, b))
 }
 
@@ -29085,7 +30447,8 @@ pub fn _kxnor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(xor))] // generate normal and code instead of kandw
-pub fn _mm512_kxnor(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kxnor(a: __mmask16, b: __mmask16) -> __mmask16 {
     _mm512_knot(_mm512_kxor(a, b))
 }
 
@@ -29096,7 +30459,8 @@ pub fn _mm512_kxnor(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _kortest_mask16_u8(a: __mmask16, b: __mmask16, all_ones: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _kortest_mask16_u8(a: __mmask16, b: __mmask16, all_ones: *mut u8) -> u8 {
     let tmp = _kor_mask16(a, b);
     *all_ones = (tmp == 0xffff) as u8;
     (tmp == 0) as u8
@@ -29109,7 +30473,8 @@ pub unsafe fn _kortest_mask16_u8(a: __mmask16, b: __mmask16, all_ones: *mut u8)
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
     (_kor_mask16(a, b) == 0xffff) as u8
 }
 
@@ -29120,7 +30485,8 @@ pub fn _kortestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
     (_kor_mask16(a, b) == 0) as u8
 }
 
@@ -29131,7 +30497,8 @@ pub fn _kortestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
 #[target_feature(enable = "avx512f")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftli_mask16<const COUNT: u32>(a: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftli_mask16<const COUNT: u32>(a: __mmask16) -> __mmask16 {
     a.unbounded_shl(COUNT)
 }
 
@@ -29142,7 +30509,8 @@ pub fn _kshiftli_mask16<const COUNT: u32>(a: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftri_mask16<const COUNT: u32>(a: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftri_mask16<const COUNT: u32>(a: __mmask16) -> __mmask16 {
     a.unbounded_shr(COUNT)
 }
 
@@ -29152,7 +30520,8 @@ pub fn _kshiftri_mask16<const COUNT: u32>(a: __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _load_mask16(mem_addr: *const __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _load_mask16(mem_addr: *const __mmask16) -> __mmask16 {
     *mem_addr
 }
 
@@ -29162,7 +30531,8 @@ pub unsafe fn _load_mask16(mem_addr: *const __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _store_mask16(mem_addr: *mut __mmask16, a: __mmask16) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _store_mask16(mem_addr: *mut __mmask16, a: __mmask16) {
     *mem_addr = a;
 }
 
@@ -29173,7 +30543,8 @@ pub unsafe fn _store_mask16(mem_addr: *mut __mmask16, a: __mmask16) {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kmovw
-pub fn _mm512_kmov(a: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kmov(a: __mmask16) -> __mmask16 {
     a
 }
 
@@ -29183,7 +30554,8 @@ pub fn _mm512_kmov(a: __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512f")] // generate normal and code instead of kmovw
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_int2mask(mask: i32) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_int2mask(mask: i32) -> __mmask16 {
     mask as u16
 }
 
@@ -29194,7 +30566,8 @@ pub fn _mm512_int2mask(mask: i32) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kmovw
-pub fn _mm512_mask2int(k1: __mmask16) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask2int(k1: __mmask16) -> i32 {
     k1 as i32
 }
 
@@ -29205,7 +30578,8 @@ pub fn _mm512_mask2int(k1: __mmask16) -> i32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kunpckbw
-pub fn _mm512_kunpackb(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kunpackb(a: __mmask16, b: __mmask16) -> __mmask16 {
     ((a & 0xff) << 8) | (b & 0xff)
 }
 
@@ -29216,7 +30590,8 @@ pub fn _mm512_kunpackb(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(cmp))] // generate normal and code instead of kortestw
-pub fn _mm512_kortestc(a: __mmask16, b: __mmask16) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kortestc(a: __mmask16, b: __mmask16) -> i32 {
     let r = (a | b) == 0b11111111_11111111;
     r as i32
 }
@@ -29228,7 +30603,8 @@ pub fn _mm512_kortestc(a: __mmask16, b: __mmask16) -> i32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(xor))] // generate normal and code instead of kortestw
-pub fn _mm512_kortestz(a: __mmask16, b: __mmask16) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kortestz(a: __mmask16, b: __mmask16) -> i32 {
     let r = (a | b) == 0;
     r as i32
 }
@@ -29240,7 +30616,8 @@ pub fn _mm512_kortestz(a: __mmask16, b: __mmask16) -> i32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmd))]
-pub fn _mm512_test_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_test_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     let and = _mm512_and_epi32(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpneq_epi32_mask(and, zero)
@@ -29253,7 +30630,8 @@ pub fn _mm512_test_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmd))]
-pub fn _mm512_mask_test_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_test_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     let and = _mm512_and_epi32(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpneq_epi32_mask(k, and, zero)
@@ -29266,7 +30644,8 @@ pub fn _mm512_mask_test_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mm
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmd))]
-pub fn _mm256_test_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_test_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpneq_epi32_mask(and, zero)
@@ -29279,7 +30658,8 @@ pub fn _mm256_test_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmd))]
-pub fn _mm256_mask_test_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_test_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpneq_epi32_mask(k, and, zero)
@@ -29292,7 +30672,8 @@ pub fn _mm256_mask_test_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mma
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmd))]
-pub fn _mm_test_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_test_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpneq_epi32_mask(and, zero)
@@ -29305,7 +30686,8 @@ pub fn _mm_test_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmd))]
-pub fn _mm_mask_test_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_test_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpneq_epi32_mask(k, and, zero)
@@ -29318,7 +30700,8 @@ pub fn _mm_mask_test_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmq))]
-pub fn _mm512_test_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_test_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     let and = _mm512_and_epi64(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpneq_epi64_mask(and, zero)
@@ -29331,7 +30714,8 @@ pub fn _mm512_test_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmq))]
-pub fn _mm512_mask_test_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_test_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     let and = _mm512_and_epi64(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpneq_epi64_mask(k, and, zero)
@@ -29344,7 +30728,8 @@ pub fn _mm512_mask_test_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mma
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmq))]
-pub fn _mm256_test_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_test_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpneq_epi64_mask(and, zero)
@@ -29357,7 +30742,8 @@ pub fn _mm256_test_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmq))]
-pub fn _mm256_mask_test_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_test_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpneq_epi64_mask(k, and, zero)
@@ -29370,7 +30756,8 @@ pub fn _mm256_mask_test_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mma
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmq))]
-pub fn _mm_test_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_test_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpneq_epi64_mask(and, zero)
@@ -29383,7 +30770,8 @@ pub fn _mm_test_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmq))]
-pub fn _mm_mask_test_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_test_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpneq_epi64_mask(k, and, zero)
@@ -29396,7 +30784,8 @@ pub fn _mm_mask_test_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmd))]
-pub fn _mm512_testn_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_testn_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     let and = _mm512_and_epi32(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpeq_epi32_mask(and, zero)
@@ -29409,7 +30798,8 @@ pub fn _mm512_testn_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmd))]
-pub fn _mm512_mask_testn_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_testn_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     let and = _mm512_and_epi32(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpeq_epi32_mask(k, and, zero)
@@ -29422,7 +30812,8 @@ pub fn _mm512_mask_testn_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmd))]
-pub fn _mm256_testn_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_testn_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpeq_epi32_mask(and, zero)
@@ -29435,7 +30826,8 @@ pub fn _mm256_testn_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmd))]
-pub fn _mm256_mask_testn_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_testn_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpeq_epi32_mask(k, and, zero)
@@ -29448,7 +30840,8 @@ pub fn _mm256_mask_testn_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mm
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmd))]
-pub fn _mm_testn_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testn_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpeq_epi32_mask(and, zero)
@@ -29461,7 +30854,8 @@ pub fn _mm_testn_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmd))]
-pub fn _mm_mask_testn_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_testn_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpeq_epi32_mask(k, and, zero)
@@ -29474,7 +30868,8 @@ pub fn _mm_mask_testn_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmq))]
-pub fn _mm512_testn_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_testn_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     let and = _mm512_and_epi64(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpeq_epi64_mask(and, zero)
@@ -29487,7 +30882,8 @@ pub fn _mm512_testn_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmq))]
-pub fn _mm512_mask_testn_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_testn_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     let and = _mm512_and_epi64(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpeq_epi64_mask(k, and, zero)
@@ -29500,7 +30896,8 @@ pub fn _mm512_mask_testn_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mm
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmq))]
-pub fn _mm256_testn_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_testn_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpeq_epi64_mask(and, zero)
@@ -29513,7 +30910,8 @@ pub fn _mm256_testn_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmq))]
-pub fn _mm256_mask_testn_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_testn_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpeq_epi64_mask(k, and, zero)
@@ -29526,7 +30924,8 @@ pub fn _mm256_mask_testn_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mm
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmq))]
-pub fn _mm_testn_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testn_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpeq_epi64_mask(and, zero)
@@ -29539,7 +30938,8 @@ pub fn _mm_testn_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmq))]
-pub fn _mm_mask_testn_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_testn_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpeq_epi64_mask(k, and, zero)
@@ -29651,7 +31051,8 @@ pub unsafe fn _mm512_stream_load_si512(mem_addr: *const __m512i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set_ps(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_ps(
     e0: f32,
     e1: f32,
     e2: f32,
@@ -29681,7 +31082,8 @@ pub fn _mm512_set_ps(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr_ps(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr_ps(
     e0: f32,
     e1: f32,
     e2: f32,
@@ -29713,7 +31115,8 @@ pub fn _mm512_setr_ps(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set1_pd(a: f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_pd(a: f64) -> __m512d {
     unsafe { transmute(f64x8::splat(a)) }
 }
 
@@ -29723,7 +31126,8 @@ pub fn _mm512_set1_pd(a: f64) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set1_ps(a: f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_ps(a: f32) -> __m512 {
     unsafe { transmute(f32x16::splat(a)) }
 }
 
@@ -29733,7 +31137,8 @@ pub fn _mm512_set1_ps(a: f32) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set_epi32(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_epi32(
     e15: i32,
     e14: i32,
     e13: i32,
@@ -29762,7 +31167,8 @@ pub fn _mm512_set_epi32(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set1_epi8(a: i8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_epi8(a: i8) -> __m512i {
     unsafe { transmute(i8x64::splat(a)) }
 }
 
@@ -29772,7 +31178,8 @@ pub fn _mm512_set1_epi8(a: i8) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set1_epi16(a: i16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_epi16(a: i16) -> __m512i {
     unsafe { transmute(i16x32::splat(a)) }
 }
 
@@ -29782,7 +31189,8 @@ pub fn _mm512_set1_epi16(a: i16) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set1_epi32(a: i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_epi32(a: i32) -> __m512i {
     unsafe { transmute(i32x16::splat(a)) }
 }
 
@@ -29793,7 +31201,8 @@ pub fn _mm512_set1_epi32(a: i32) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastd))]
-pub fn _mm512_mask_set1_epi32(src: __m512i, k: __mmask16, a: i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_set1_epi32(src: __m512i, k: __mmask16, a: i32) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, r, src.as_i32x16()))
@@ -29807,7 +31216,8 @@ pub fn _mm512_mask_set1_epi32(src: __m512i, k: __mmask16, a: i32) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastd))]
-pub fn _mm512_maskz_set1_epi32(k: __mmask16, a: i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_set1_epi32(k: __mmask16, a: i32) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, r, i32x16::ZERO))
@@ -29821,7 +31231,8 @@ pub fn _mm512_maskz_set1_epi32(k: __mmask16, a: i32) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastd))]
-pub fn _mm256_mask_set1_epi32(src: __m256i, k: __mmask8, a: i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_set1_epi32(src: __m256i, k: __mmask8, a: i32) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, r, src.as_i32x8()))
@@ -29835,7 +31246,8 @@ pub fn _mm256_mask_set1_epi32(src: __m256i, k: __mmask8, a: i32) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastd))]
-pub fn _mm256_maskz_set1_epi32(k: __mmask8, a: i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_set1_epi32(k: __mmask8, a: i32) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, r, i32x8::ZERO))
@@ -29849,7 +31261,8 @@ pub fn _mm256_maskz_set1_epi32(k: __mmask8, a: i32) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastd))]
-pub fn _mm_mask_set1_epi32(src: __m128i, k: __mmask8, a: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_set1_epi32(src: __m128i, k: __mmask8, a: i32) -> __m128i {
     unsafe {
         let r = _mm_set1_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, r, src.as_i32x4()))
@@ -29863,7 +31276,8 @@ pub fn _mm_mask_set1_epi32(src: __m128i, k: __mmask8, a: i32) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastd))]
-pub fn _mm_maskz_set1_epi32(k: __mmask8, a: i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_set1_epi32(k: __mmask8, a: i32) -> __m128i {
     unsafe {
         let r = _mm_set1_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, r, i32x4::ZERO))
@@ -29876,7 +31290,8 @@ pub fn _mm_maskz_set1_epi32(k: __mmask8, a: i32) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set1_epi64(a: i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_epi64(a: i64) -> __m512i {
     unsafe { transmute(i64x8::splat(a)) }
 }
 
@@ -29887,7 +31302,8 @@ pub fn _mm512_set1_epi64(a: i64) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastq))]
-pub fn _mm512_mask_set1_epi64(src: __m512i, k: __mmask8, a: i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_set1_epi64(src: __m512i, k: __mmask8, a: i64) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, r, src.as_i64x8()))
@@ -29901,7 +31317,8 @@ pub fn _mm512_mask_set1_epi64(src: __m512i, k: __mmask8, a: i64) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastq))]
-pub fn _mm512_maskz_set1_epi64(k: __mmask8, a: i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_set1_epi64(k: __mmask8, a: i64) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, r, i64x8::ZERO))
@@ -29915,7 +31332,8 @@ pub fn _mm512_maskz_set1_epi64(k: __mmask8, a: i64) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastq))]
-pub fn _mm256_mask_set1_epi64(src: __m256i, k: __mmask8, a: i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_set1_epi64(src: __m256i, k: __mmask8, a: i64) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi64x(a).as_i64x4();
         transmute(simd_select_bitmask(k, r, src.as_i64x4()))
@@ -29929,7 +31347,8 @@ pub fn _mm256_mask_set1_epi64(src: __m256i, k: __mmask8, a: i64) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastq))]
-pub fn _mm256_maskz_set1_epi64(k: __mmask8, a: i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_set1_epi64(k: __mmask8, a: i64) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi64x(a).as_i64x4();
         transmute(simd_select_bitmask(k, r, i64x4::ZERO))
@@ -29943,7 +31362,8 @@ pub fn _mm256_maskz_set1_epi64(k: __mmask8, a: i64) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastq))]
-pub fn _mm_mask_set1_epi64(src: __m128i, k: __mmask8, a: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_set1_epi64(src: __m128i, k: __mmask8, a: i64) -> __m128i {
     unsafe {
         let r = _mm_set1_epi64x(a).as_i64x2();
         transmute(simd_select_bitmask(k, r, src.as_i64x2()))
@@ -29957,7 +31377,8 @@ pub fn _mm_mask_set1_epi64(src: __m128i, k: __mmask8, a: i64) -> __m128i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastq))]
-pub fn _mm_maskz_set1_epi64(k: __mmask8, a: i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_set1_epi64(k: __mmask8, a: i64) -> __m128i {
     unsafe {
         let r = _mm_set1_epi64x(a).as_i64x2();
         transmute(simd_select_bitmask(k, r, i64x2::ZERO))
@@ -29970,7 +31391,8 @@ pub fn _mm_maskz_set1_epi64(k: __mmask8, a: i64) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
     _mm512_set_epi64(d, c, b, a, d, c, b, a)
 }
 
@@ -29980,7 +31402,8 @@ pub fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
     _mm512_set_epi64(a, b, c, d, a, b, c, d)
 }
 
@@ -30809,7 +32232,8 @@ pub fn _mm_mask_cmp_round_sd_mask<const IMM5: i32, const SAE: i32>(
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_cmplt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<u32x16, _>(simd_lt(a.as_u32x16(), b.as_u32x16())) }
 }
 
@@ -30820,7 +32244,8 @@ pub fn _mm512_cmplt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_mask_cmplt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -30831,7 +32256,8 @@ pub fn _mm512_mask_cmplt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_cmplt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x8, _>(simd_lt(a.as_u32x8(), b.as_u32x8())) }
 }
 
@@ -30842,7 +32268,8 @@ pub fn _mm256_cmplt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_mask_cmplt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -30853,7 +32280,8 @@ pub fn _mm256_mask_cmplt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_cmplt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x4, _>(simd_lt(a.as_u32x4(), b.as_u32x4())) }
 }
 
@@ -30864,7 +32292,8 @@ pub fn _mm_cmplt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_mask_cmplt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu32_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -30875,7 +32304,8 @@ pub fn _mm_mask_cmplt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_cmpgt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<u32x16, _>(simd_gt(a.as_u32x16(), b.as_u32x16())) }
 }
 
@@ -30886,7 +32316,8 @@ pub fn _mm512_cmpgt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_mask_cmpgt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -30897,7 +32328,8 @@ pub fn _mm512_mask_cmpgt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_cmpgt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x8, _>(simd_gt(a.as_u32x8(), b.as_u32x8())) }
 }
 
@@ -30908,7 +32340,8 @@ pub fn _mm256_cmpgt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -30919,7 +32352,8 @@ pub fn _mm256_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_cmpgt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x4, _>(simd_gt(a.as_u32x4(), b.as_u32x4())) }
 }
 
@@ -30930,7 +32364,8 @@ pub fn _mm_cmpgt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu32_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -30941,7 +32376,8 @@ pub fn _mm_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_cmple_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<u32x16, _>(simd_le(a.as_u32x16(), b.as_u32x16())) }
 }
 
@@ -30952,7 +32388,8 @@ pub fn _mm512_cmple_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_mask_cmple_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -30963,7 +32400,8 @@ pub fn _mm512_mask_cmple_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_cmple_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x8, _>(simd_le(a.as_u32x8(), b.as_u32x8())) }
 }
 
@@ -30974,7 +32412,8 @@ pub fn _mm256_cmple_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_mask_cmple_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -30985,7 +32424,8 @@ pub fn _mm256_mask_cmple_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_cmple_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x4, _>(simd_le(a.as_u32x4(), b.as_u32x4())) }
 }
 
@@ -30996,7 +32436,8 @@ pub fn _mm_cmple_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_mask_cmple_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu32_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -31007,7 +32448,8 @@ pub fn _mm_mask_cmple_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_cmpge_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<u32x16, _>(simd_ge(a.as_u32x16(), b.as_u32x16())) }
 }
 
@@ -31018,7 +32460,8 @@ pub fn _mm512_cmpge_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_mask_cmpge_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -31029,7 +32472,8 @@ pub fn _mm512_mask_cmpge_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_cmpge_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x8, _>(simd_ge(a.as_u32x8(), b.as_u32x8())) }
 }
 
@@ -31040,7 +32484,8 @@ pub fn _mm256_cmpge_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_mask_cmpge_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -31051,7 +32496,8 @@ pub fn _mm256_mask_cmpge_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_cmpge_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x4, _>(simd_ge(a.as_u32x4(), b.as_u32x4())) }
 }
 
@@ -31062,7 +32508,8 @@ pub fn _mm_cmpge_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_mask_cmpge_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu32_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -31073,7 +32520,8 @@ pub fn _mm_mask_cmpge_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_cmpeq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<u32x16, _>(simd_eq(a.as_u32x16(), b.as_u32x16())) }
 }
 
@@ -31084,7 +32532,8 @@ pub fn _mm512_cmpeq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_mask_cmpeq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -31095,7 +32544,8 @@ pub fn _mm512_mask_cmpeq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_cmpeq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x8, _>(simd_eq(a.as_u32x8(), b.as_u32x8())) }
 }
 
@@ -31106,7 +32556,8 @@ pub fn _mm256_cmpeq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -31117,7 +32568,8 @@ pub fn _mm256_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_cmpeq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x4, _>(simd_eq(a.as_u32x4(), b.as_u32x4())) }
 }
 
@@ -31128,7 +32580,8 @@ pub fn _mm_cmpeq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu32_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -31139,7 +32592,8 @@ pub fn _mm_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_cmpneq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<u32x16, _>(simd_ne(a.as_u32x16(), b.as_u32x16())) }
 }
 
@@ -31150,7 +32604,8 @@ pub fn _mm512_cmpneq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm512_mask_cmpneq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -31161,7 +32616,8 @@ pub fn _mm512_mask_cmpneq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_cmpneq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x8, _>(simd_ne(a.as_u32x8(), b.as_u32x8())) }
 }
 
@@ -31172,7 +32628,8 @@ pub fn _mm256_cmpneq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm256_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -31183,7 +32640,8 @@ pub fn _mm256_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_cmpneq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u32x4, _>(simd_ne(a.as_u32x4(), b.as_u32x4())) }
 }
 
@@ -31194,7 +32652,8 @@ pub fn _mm_cmpneq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud
-pub fn _mm_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu32_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -31206,7 +32665,11 @@ pub fn _mm_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m512i,
+    b: __m512i,
+) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_u32x16();
@@ -31233,7 +32696,8 @@ pub fn _mm512_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask16,
     a: __m512i,
     b: __m512i,
@@ -31265,7 +32729,11 @@ pub fn _mm512_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m256i,
+    b: __m256i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_u32x8();
@@ -31292,7 +32760,8 @@ pub fn _mm256_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m256i,
     b: __m256i,
@@ -31324,7 +32793,8 @@ pub fn _mm256_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_u32x4();
@@ -31351,7 +32821,8 @@ pub fn _mm_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m128i,
     b: __m128i,
@@ -31382,7 +32853,8 @@ pub fn _mm_mask_cmp_epu32_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_cmplt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<i32x16, _>(simd_lt(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -31393,7 +32865,8 @@ pub fn _mm512_cmplt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_mask_cmplt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -31404,7 +32877,8 @@ pub fn _mm512_mask_cmplt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_cmplt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x8, _>(simd_lt(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -31415,7 +32889,8 @@ pub fn _mm256_cmplt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_mask_cmplt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -31426,7 +32901,8 @@ pub fn _mm256_mask_cmplt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_cmplt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x4, _>(simd_lt(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -31437,7 +32913,8 @@ pub fn _mm_cmplt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_mask_cmplt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi32_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -31448,7 +32925,8 @@ pub fn _mm_mask_cmplt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_cmpgt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<i32x16, _>(simd_gt(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -31459,7 +32937,8 @@ pub fn _mm512_cmpgt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_mask_cmpgt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -31470,7 +32949,8 @@ pub fn _mm512_mask_cmpgt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_cmpgt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x8, _>(simd_gt(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -31481,7 +32961,8 @@ pub fn _mm256_cmpgt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -31492,7 +32973,8 @@ pub fn _mm256_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_cmpgt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x4, _>(simd_gt(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -31503,7 +32985,8 @@ pub fn _mm_cmpgt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi32_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -31514,7 +32997,8 @@ pub fn _mm_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_cmple_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<i32x16, _>(simd_le(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -31525,7 +33009,8 @@ pub fn _mm512_cmple_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_mask_cmple_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -31536,7 +33021,8 @@ pub fn _mm512_mask_cmple_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_cmple_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x8, _>(simd_le(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -31547,7 +33033,8 @@ pub fn _mm256_cmple_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_mask_cmple_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -31558,7 +33045,8 @@ pub fn _mm256_mask_cmple_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_cmple_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x4, _>(simd_le(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -31569,7 +33057,8 @@ pub fn _mm_cmple_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_mask_cmple_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi32_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -31580,7 +33069,8 @@ pub fn _mm_mask_cmple_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_cmpge_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<i32x16, _>(simd_ge(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -31591,7 +33081,8 @@ pub fn _mm512_cmpge_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_mask_cmpge_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -31602,7 +33093,8 @@ pub fn _mm512_mask_cmpge_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_cmpge_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x8, _>(simd_ge(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -31613,7 +33105,8 @@ pub fn _mm256_cmpge_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_mask_cmpge_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -31624,7 +33117,8 @@ pub fn _mm256_mask_cmpge_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_cmpge_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x4, _>(simd_ge(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -31635,7 +33129,8 @@ pub fn _mm_cmpge_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_mask_cmpge_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi32_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -31646,7 +33141,8 @@ pub fn _mm_mask_cmpge_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_cmpeq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<i32x16, _>(simd_eq(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -31657,7 +33153,8 @@ pub fn _mm512_cmpeq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_mask_cmpeq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -31668,7 +33165,8 @@ pub fn _mm512_mask_cmpeq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_cmpeq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x8, _>(simd_eq(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -31679,7 +33177,8 @@ pub fn _mm256_cmpeq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -31690,7 +33189,8 @@ pub fn _mm256_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_cmpeq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x4, _>(simd_eq(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -31701,7 +33201,8 @@ pub fn _mm_cmpeq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi32_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -31712,7 +33213,8 @@ pub fn _mm_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_cmpneq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
     unsafe { simd_bitmask::<i32x16, _>(simd_ne(a.as_i32x16(), b.as_i32x16())) }
 }
 
@@ -31723,7 +33225,8 @@ pub fn _mm512_cmpneq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm512_mask_cmpneq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
     _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -31734,7 +33237,8 @@ pub fn _mm512_mask_cmpneq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> _
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_cmpneq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x8, _>(simd_ne(a.as_i32x8(), b.as_i32x8())) }
 }
 
@@ -31745,7 +33249,8 @@ pub fn _mm256_cmpneq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm256_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -31756,7 +33261,8 @@ pub fn _mm256_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_cmpneq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i32x4, _>(simd_ne(a.as_i32x4(), b.as_i32x4())) }
 }
 
@@ -31767,7 +33273,8 @@ pub fn _mm_cmpneq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd
-pub fn _mm_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi32_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -31779,7 +33286,11 @@ pub fn _mm_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m512i,
+    b: __m512i,
+) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_i32x16();
@@ -31806,7 +33317,8 @@ pub fn _mm512_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask16,
     a: __m512i,
     b: __m512i,
@@ -31838,7 +33350,11 @@ pub fn _mm512_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m256i,
+    b: __m256i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_i32x8();
@@ -31865,7 +33381,8 @@ pub fn _mm256_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m256i,
     b: __m256i,
@@ -31897,7 +33414,8 @@ pub fn _mm256_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_i32x4();
@@ -31924,7 +33442,8 @@ pub fn _mm_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m128i,
     b: __m128i,
@@ -31955,7 +33474,8 @@ pub fn _mm_mask_cmp_epi32_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_lt(a.as_u64x8(), b.as_u64x8())) }
 }
 
@@ -31966,7 +33486,8 @@ pub fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_mask_cmplt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -31977,7 +33498,8 @@ pub fn _mm512_mask_cmplt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_cmplt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_lt(a.as_u64x4(), b.as_u64x4())) }
 }
 
@@ -31988,7 +33510,8 @@ pub fn _mm256_cmplt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_mask_cmplt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -31999,7 +33522,8 @@ pub fn _mm256_mask_cmplt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_cmplt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_lt(a.as_u64x2(), b.as_u64x2())) }
 }
 
@@ -32010,7 +33534,8 @@ pub fn _mm_cmplt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_mask_cmplt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -32021,7 +33546,8 @@ pub fn _mm_mask_cmplt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_cmpgt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_gt(a.as_u64x8(), b.as_u64x8())) }
 }
 
@@ -32032,7 +33558,8 @@ pub fn _mm512_cmpgt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -32043,7 +33570,8 @@ pub fn _mm512_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_cmpgt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_gt(a.as_u64x4(), b.as_u64x4())) }
 }
 
@@ -32054,7 +33582,8 @@ pub fn _mm256_cmpgt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -32065,7 +33594,8 @@ pub fn _mm256_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_cmpgt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_gt(a.as_u64x2(), b.as_u64x2())) }
 }
 
@@ -32076,7 +33606,8 @@ pub fn _mm_cmpgt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu64_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -32087,7 +33618,8 @@ pub fn _mm_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_cmple_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_le(a.as_u64x8(), b.as_u64x8())) }
 }
 
@@ -32098,7 +33630,8 @@ pub fn _mm512_cmple_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_mask_cmple_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -32109,7 +33642,8 @@ pub fn _mm512_mask_cmple_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_cmple_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_le(a.as_u64x4(), b.as_u64x4())) }
 }
 
@@ -32120,7 +33654,8 @@ pub fn _mm256_cmple_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_mask_cmple_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -32131,7 +33666,8 @@ pub fn _mm256_mask_cmple_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_cmple_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_le(a.as_u64x2(), b.as_u64x2())) }
 }
 
@@ -32142,7 +33678,8 @@ pub fn _mm_cmple_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_mask_cmple_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -32153,7 +33690,8 @@ pub fn _mm_mask_cmple_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_cmpge_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_ge(a.as_u64x8(), b.as_u64x8())) }
 }
 
@@ -32164,7 +33702,8 @@ pub fn _mm512_cmpge_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_mask_cmpge_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -32175,7 +33714,8 @@ pub fn _mm512_mask_cmpge_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_cmpge_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_ge(a.as_u64x4(), b.as_u64x4())) }
 }
 
@@ -32186,7 +33726,8 @@ pub fn _mm256_cmpge_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_mask_cmpge_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -32197,7 +33738,8 @@ pub fn _mm256_mask_cmpge_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_cmpge_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_ge(a.as_u64x2(), b.as_u64x2())) }
 }
 
@@ -32208,7 +33750,8 @@ pub fn _mm_cmpge_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_mask_cmpge_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu64_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -32219,7 +33762,8 @@ pub fn _mm_mask_cmpge_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_cmpeq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_eq(a.as_u64x8(), b.as_u64x8())) }
 }
 
@@ -32230,7 +33774,8 @@ pub fn _mm512_cmpeq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -32241,7 +33786,8 @@ pub fn _mm512_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_cmpeq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_eq(a.as_u64x4(), b.as_u64x4())) }
 }
 
@@ -32252,7 +33798,8 @@ pub fn _mm256_cmpeq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -32263,7 +33810,8 @@ pub fn _mm256_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_cmpeq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_eq(a.as_u64x2(), b.as_u64x2())) }
 }
 
@@ -32274,7 +33822,8 @@ pub fn _mm_cmpeq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu64_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -32285,7 +33834,8 @@ pub fn _mm_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_cmpneq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_ne(a.as_u64x8(), b.as_u64x8())) }
 }
 
@@ -32296,7 +33846,8 @@ pub fn _mm512_cmpneq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm512_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -32307,7 +33858,8 @@ pub fn _mm512_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_cmpneq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_ne(a.as_u64x4(), b.as_u64x4())) }
 }
 
@@ -32318,7 +33870,8 @@ pub fn _mm256_cmpneq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm256_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -32329,7 +33882,8 @@ pub fn _mm256_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_cmpneq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_ne(a.as_u64x2(), b.as_u64x2())) }
 }
 
@@ -32340,7 +33894,8 @@ pub fn _mm_cmpneq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq
-pub fn _mm_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu64_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -32352,7 +33907,11 @@ pub fn _mm_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m512i,
+    b: __m512i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_u64x8();
@@ -32379,7 +33938,8 @@ pub fn _mm512_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m512i,
     b: __m512i,
@@ -32411,7 +33971,11 @@ pub fn _mm512_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m256i,
+    b: __m256i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_u64x4();
@@ -32438,7 +34002,8 @@ pub fn _mm256_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m256i,
     b: __m256i,
@@ -32470,7 +34035,8 @@ pub fn _mm256_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_u64x2();
@@ -32497,7 +34063,8 @@ pub fn _mm_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m128i,
     b: __m128i,
@@ -32528,7 +34095,8 @@ pub fn _mm_mask_cmp_epu64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_cmplt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_lt(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -32539,7 +34107,8 @@ pub fn _mm512_cmplt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_mask_cmplt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -32550,7 +34119,8 @@ pub fn _mm512_mask_cmplt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_cmplt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_lt(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -32561,7 +34131,8 @@ pub fn _mm256_cmplt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_mask_cmplt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -32572,7 +34143,8 @@ pub fn _mm256_mask_cmplt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_cmplt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_lt(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -32583,7 +34155,8 @@ pub fn _mm_cmplt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_mask_cmplt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -32594,7 +34167,8 @@ pub fn _mm_mask_cmplt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_cmpgt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_gt(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -32605,7 +34179,8 @@ pub fn _mm512_cmpgt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -32616,7 +34191,8 @@ pub fn _mm512_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_cmpgt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_gt(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -32627,7 +34203,8 @@ pub fn _mm256_cmpgt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -32638,7 +34215,8 @@ pub fn _mm256_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_cmpgt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_gt(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -32649,7 +34227,8 @@ pub fn _mm_cmpgt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi64_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -32660,7 +34239,8 @@ pub fn _mm_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_cmple_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_le(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -32671,7 +34251,8 @@ pub fn _mm512_cmple_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_mask_cmple_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -32682,7 +34263,8 @@ pub fn _mm512_mask_cmple_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_cmple_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_le(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -32693,7 +34275,8 @@ pub fn _mm256_cmple_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_mask_cmple_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -32704,7 +34287,8 @@ pub fn _mm256_mask_cmple_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_cmple_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_le(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -32715,7 +34299,8 @@ pub fn _mm_cmple_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_mask_cmple_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -32726,7 +34311,8 @@ pub fn _mm_mask_cmple_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_cmpge_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_ge(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -32737,7 +34323,8 @@ pub fn _mm512_cmpge_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_mask_cmpge_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -32748,7 +34335,8 @@ pub fn _mm512_mask_cmpge_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_cmpge_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_ge(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -32759,7 +34347,8 @@ pub fn _mm256_cmpge_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_mask_cmpge_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -32770,7 +34359,8 @@ pub fn _mm256_mask_cmpge_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_cmpge_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_ge(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -32781,7 +34371,8 @@ pub fn _mm_cmpge_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_mask_cmpge_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi64_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -32792,7 +34383,8 @@ pub fn _mm_mask_cmpge_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_cmpeq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_eq(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -32803,7 +34395,8 @@ pub fn _mm512_cmpeq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -32814,7 +34407,8 @@ pub fn _mm512_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_cmpeq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_eq(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -32825,7 +34419,8 @@ pub fn _mm256_cmpeq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -32836,7 +34431,8 @@ pub fn _mm256_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_cmpeq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_eq(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -32847,7 +34443,8 @@ pub fn _mm_cmpeq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi64_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -32858,7 +34455,8 @@ pub fn _mm_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_cmpneq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
     unsafe { simd_bitmask::<__m512i, _>(simd_ne(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -32869,7 +34467,8 @@ pub fn _mm512_cmpneq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm512_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
     _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -32880,7 +34479,8 @@ pub fn _mm512_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_cmpneq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
     unsafe { simd_bitmask::<__m256i, _>(simd_ne(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -32891,7 +34491,8 @@ pub fn _mm256_cmpneq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm256_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 {
     _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -32902,7 +34503,8 @@ pub fn _mm256_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_cmpneq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<__m128i, _>(simd_ne(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -32913,7 +34515,8 @@ pub fn _mm_cmpneq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq
-pub fn _mm_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi64_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -32925,7 +34528,11 @@ pub fn _mm_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m512i,
+    b: __m512i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_i64x8();
@@ -32952,7 +34559,8 @@ pub fn _mm512_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m512i, b: __m512i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm512_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m512i,
     b: __m512i,
@@ -32984,7 +34592,11 @@ pub fn _mm512_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
+    a: __m256i,
+    b: __m256i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_i64x4();
@@ -33011,7 +34623,8 @@ pub fn _mm256_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m256i, b: __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm256_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m256i,
     b: __m256i,
@@ -33043,7 +34656,8 @@ pub fn _mm256_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM3, 3);
         let a = a.as_i64x2();
@@ -33070,7 +34684,8 @@ pub fn _mm_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(a: __m128i, b: __m128i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))]
-pub fn _mm_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
     k1: __mmask8,
     a: __m128i,
     b: __m128i,
@@ -33100,7 +34715,8 @@ pub fn _mm_mask_cmp_epi64_mask<const IMM3: _MM_CMPINT_ENUM>(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_add_epi32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_add_epi32(a: __m512i) -> i32 {
     unsafe { simd_reduce_add_ordered(a.as_i32x16(), 0) }
 }
 
@@ -33110,7 +34726,8 @@ pub fn _mm512_reduce_add_epi32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i32x16(), i32x16::ZERO), 0) }
 }
 
@@ -33120,7 +34737,8 @@ pub fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_add_epi64(a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_add_epi64(a: __m512i) -> i64 {
     unsafe { simd_reduce_add_ordered(a.as_i64x8(), 0) }
 }
 
@@ -33130,7 +34748,8 @@ pub fn _mm512_reduce_add_epi64(a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_add_epi64(k: __mmask8, a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_add_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i64x8(), i64x8::ZERO), 0) }
 }
 
@@ -33140,7 +34759,8 @@ pub fn _mm512_mask_reduce_add_epi64(k: __mmask8, a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_add_ps(a: __m512) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_add_ps(a: __m512) -> f32 {
     unsafe {
         // we have to use `simd_shuffle` here because `_mm512_extractf32x8_ps` is in AVX512DQ
         let a = _mm256_add_ps(
@@ -33159,7 +34779,8 @@ pub fn _mm512_reduce_add_ps(a: __m512) -> f32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_add_ps(k: __mmask16, a: __m512) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_add_ps(k: __mmask16, a: __m512) -> f32 {
     unsafe { _mm512_reduce_add_ps(simd_select_bitmask(k, a, _mm512_setzero_ps())) }
 }
 
@@ -33169,7 +34790,8 @@ pub fn _mm512_mask_reduce_add_ps(k: __mmask16, a: __m512) -> f32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_add_pd(a: __m512d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_add_pd(a: __m512d) -> f64 {
     unsafe {
         let a = _mm256_add_pd(
             _mm512_extractf64x4_pd::<0>(a),
@@ -33186,7 +34808,8 @@ pub fn _mm512_reduce_add_pd(a: __m512d) -> f64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_add_pd(k: __mmask8, a: __m512d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_add_pd(k: __mmask8, a: __m512d) -> f64 {
     unsafe { _mm512_reduce_add_pd(simd_select_bitmask(k, a, _mm512_setzero_pd())) }
 }
 
@@ -33196,7 +34819,8 @@ pub fn _mm512_mask_reduce_add_pd(k: __mmask8, a: __m512d) -> f64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 {
     unsafe { simd_reduce_mul_ordered(a.as_i32x16(), 1) }
 }
 
@@ -33206,7 +34830,8 @@ pub fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe {
         simd_reduce_mul_ordered(
             simd_select_bitmask(k, a.as_i32x16(), _mm512_set1_epi32(1).as_i32x16()),
@@ -33221,7 +34846,8 @@ pub fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 {
     unsafe { simd_reduce_mul_ordered(a.as_i64x8(), 1) }
 }
 
@@ -33231,7 +34857,8 @@ pub fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_mul_epi64(k: __mmask8, a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_mul_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe {
         simd_reduce_mul_ordered(
             simd_select_bitmask(k, a.as_i64x8(), _mm512_set1_epi64(1).as_i64x8()),
@@ -33246,7 +34873,8 @@ pub fn _mm512_mask_reduce_mul_epi64(k: __mmask8, a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_mul_ps(a: __m512) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_mul_ps(a: __m512) -> f32 {
     unsafe {
         // we have to use `simd_shuffle` here because `_mm512_extractf32x8_ps` is in AVX512DQ
         let a = _mm256_mul_ps(
@@ -33265,7 +34893,8 @@ pub fn _mm512_reduce_mul_ps(a: __m512) -> f32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_mul_ps(k: __mmask16, a: __m512) -> f32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_mul_ps(k: __mmask16, a: __m512) -> f32 {
     unsafe { _mm512_reduce_mul_ps(simd_select_bitmask(k, a, _mm512_set1_ps(1.))) }
 }
 
@@ -33275,7 +34904,8 @@ pub fn _mm512_mask_reduce_mul_ps(k: __mmask16, a: __m512) -> f32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_mul_pd(a: __m512d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_mul_pd(a: __m512d) -> f64 {
     unsafe {
         let a = _mm256_mul_pd(
             _mm512_extractf64x4_pd::<0>(a),
@@ -33292,7 +34922,8 @@ pub fn _mm512_reduce_mul_pd(a: __m512d) -> f64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_mul_pd(k: __mmask8, a: __m512d) -> f64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_mul_pd(k: __mmask8, a: __m512d) -> f64 {
     unsafe { _mm512_reduce_mul_pd(simd_select_bitmask(k, a, _mm512_set1_pd(1.))) }
 }
 
@@ -33302,7 +34933,8 @@ pub fn _mm512_mask_reduce_mul_pd(k: __mmask8, a: __m512d) -> f64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_max_epi32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_max_epi32(a: __m512i) -> i32 {
     unsafe { simd_reduce_max(a.as_i32x16()) }
 }
 
@@ -33312,7 +34944,8 @@ pub fn _mm512_reduce_max_epi32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_max_epi32(k: __mmask16, a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_max_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe {
         simd_reduce_max(simd_select_bitmask(
             k,
@@ -33328,7 +34961,8 @@ pub fn _mm512_mask_reduce_max_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_max_epi64(a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_max_epi64(a: __m512i) -> i64 {
     unsafe { simd_reduce_max(a.as_i64x8()) }
 }
 
@@ -33338,7 +34972,8 @@ pub fn _mm512_reduce_max_epi64(a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_max_epi64(k: __mmask8, a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_max_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i64x8(), i64x8::splat(i64::MIN))) }
 }
 
@@ -33348,7 +34983,8 @@ pub fn _mm512_mask_reduce_max_epi64(k: __mmask8, a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_max_epu32(a: __m512i) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_max_epu32(a: __m512i) -> u32 {
     unsafe { simd_reduce_max(a.as_u32x16()) }
 }
 
@@ -33358,7 +34994,8 @@ pub fn _mm512_reduce_max_epu32(a: __m512i) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_max_epu32(k: __mmask16, a: __m512i) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_max_epu32(k: __mmask16, a: __m512i) -> u32 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u32x16(), u32x16::ZERO)) }
 }
 
@@ -33368,7 +35005,8 @@ pub fn _mm512_mask_reduce_max_epu32(k: __mmask16, a: __m512i) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_max_epu64(a: __m512i) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_max_epu64(a: __m512i) -> u64 {
     unsafe { simd_reduce_max(a.as_u64x8()) }
 }
 
@@ -33378,7 +35016,8 @@ pub fn _mm512_reduce_max_epu64(a: __m512i) -> u64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_max_epu64(k: __mmask8, a: __m512i) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_max_epu64(k: __mmask8, a: __m512i) -> u64 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u64x8(), u64x8::ZERO)) }
 }
 
@@ -33443,7 +35082,8 @@ pub fn _mm512_mask_reduce_max_pd(k: __mmask8, a: __m512d) -> f64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_min_epi32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_min_epi32(a: __m512i) -> i32 {
     unsafe { simd_reduce_min(a.as_i32x16()) }
 }
 
@@ -33453,7 +35093,8 @@ pub fn _mm512_reduce_min_epi32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_min_epi32(k: __mmask16, a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_min_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe {
         simd_reduce_min(simd_select_bitmask(
             k,
@@ -33469,7 +35110,8 @@ pub fn _mm512_mask_reduce_min_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_min_epi64(a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_min_epi64(a: __m512i) -> i64 {
     unsafe { simd_reduce_min(a.as_i64x8()) }
 }
 
@@ -33479,7 +35121,8 @@ pub fn _mm512_reduce_min_epi64(a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_min_epi64(k: __mmask8, a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_min_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i64x8(), i64x8::splat(i64::MAX))) }
 }
 
@@ -33489,7 +35132,8 @@ pub fn _mm512_mask_reduce_min_epi64(k: __mmask8, a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_min_epu32(a: __m512i) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_min_epu32(a: __m512i) -> u32 {
     unsafe { simd_reduce_min(a.as_u32x16()) }
 }
 
@@ -33499,7 +35143,8 @@ pub fn _mm512_reduce_min_epu32(a: __m512i) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_min_epu32(k: __mmask16, a: __m512i) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_min_epu32(k: __mmask16, a: __m512i) -> u32 {
     unsafe {
         simd_reduce_min(simd_select_bitmask(
             k,
@@ -33515,7 +35160,8 @@ pub fn _mm512_mask_reduce_min_epu32(k: __mmask16, a: __m512i) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_min_epu64(a: __m512i) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_min_epu64(a: __m512i) -> u64 {
     unsafe { simd_reduce_min(a.as_u64x8()) }
 }
 
@@ -33525,7 +35171,8 @@ pub fn _mm512_reduce_min_epu64(a: __m512i) -> u64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_min_epu64(k: __mmask8, a: __m512i) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_min_epu64(k: __mmask8, a: __m512i) -> u64 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u64x8(), u64x8::splat(u64::MAX))) }
 }
 
@@ -33590,7 +35237,8 @@ pub fn _mm512_mask_reduce_min_pd(k: __mmask8, a: __m512d) -> f64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_and_epi32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_and_epi32(a: __m512i) -> i32 {
     unsafe { simd_reduce_and(a.as_i32x16()) }
 }
 
@@ -33600,7 +35248,8 @@ pub fn _mm512_reduce_and_epi32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_and_epi32(k: __mmask16, a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_and_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe { simd_reduce_and(simd_select_bitmask(k, a.as_i32x16(), i32x16::splat(-1))) }
 }
 
@@ -33610,7 +35259,8 @@ pub fn _mm512_mask_reduce_and_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_and_epi64(a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_and_epi64(a: __m512i) -> i64 {
     unsafe { simd_reduce_and(a.as_i64x8()) }
 }
 
@@ -33620,7 +35270,8 @@ pub fn _mm512_reduce_and_epi64(a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_and_epi64(k: __mmask8, a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_and_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe { simd_reduce_and(simd_select_bitmask(k, a.as_i64x8(), i64x8::splat(-1))) }
 }
 
@@ -33630,7 +35281,8 @@ pub fn _mm512_mask_reduce_and_epi64(k: __mmask8, a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_or_epi32(a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_or_epi32(a: __m512i) -> i32 {
     unsafe { simd_reduce_or(a.as_i32x16()) }
 }
 
@@ -33640,7 +35292,8 @@ pub fn _mm512_reduce_or_epi32(a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_or_epi32(k: __mmask16, a: __m512i) -> i32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_or_epi32(k: __mmask16, a: __m512i) -> i32 {
     unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i32x16(), i32x16::ZERO)) }
 }
 
@@ -33650,7 +35303,8 @@ pub fn _mm512_mask_reduce_or_epi32(k: __mmask16, a: __m512i) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_reduce_or_epi64(a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_or_epi64(a: __m512i) -> i64 {
     unsafe { simd_reduce_or(a.as_i64x8()) }
 }
 
@@ -33660,7 +35314,8 @@ pub fn _mm512_reduce_or_epi64(a: __m512i) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_reduce_or_epi64(k: __mmask8, a: __m512i) -> i64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_reduce_or_epi64(k: __mmask8, a: __m512i) -> i64 {
     unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i64x8(), i64x8::ZERO)) }
 }
 
@@ -33674,7 +35329,8 @@ pub fn _mm512_mask_reduce_or_epi64(k: __mmask8, a: __m512i) -> i64 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 // This intrinsic has no corresponding instruction.
-pub fn _mm512_undefined_pd() -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_undefined_pd() -> __m512d {
     unsafe { const { mem::zeroed() } }
 }
 
@@ -33688,7 +35344,8 @@ pub fn _mm512_undefined_pd() -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 // This intrinsic has no corresponding instruction.
-pub fn _mm512_undefined_ps() -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_undefined_ps() -> __m512 {
     unsafe { const { mem::zeroed() } }
 }
 
@@ -33702,7 +35359,8 @@ pub fn _mm512_undefined_ps() -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 // This intrinsic has no corresponding instruction.
-pub fn _mm512_undefined_epi32() -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_undefined_epi32() -> __m512i {
     unsafe { const { mem::zeroed() } }
 }
 
@@ -33716,7 +35374,8 @@ pub fn _mm512_undefined_epi32() -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 // This intrinsic has no corresponding instruction.
-pub fn _mm512_undefined() -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_undefined() -> __m512 {
     unsafe { const { mem::zeroed() } }
 }
 
@@ -33727,7 +35386,8 @@ pub fn _mm512_undefined() -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm512_loadu_epi32(mem_addr: *const i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_epi32(mem_addr: *const i32) -> __m512i {
     ptr::read_unaligned(mem_addr as *const __m512i)
 }
 
@@ -33738,7 +35398,8 @@ pub unsafe fn _mm512_loadu_epi32(mem_addr: *const i32) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm256_loadu_epi32(mem_addr: *const i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_epi32(mem_addr: *const i32) -> __m256i {
     ptr::read_unaligned(mem_addr as *const __m256i)
 }
 
@@ -33749,7 +35410,8 @@ pub unsafe fn _mm256_loadu_epi32(mem_addr: *const i32) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm_loadu_epi32(mem_addr: *const i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_epi32(mem_addr: *const i32) -> __m128i {
     ptr::read_unaligned(mem_addr as *const __m128i)
 }
 
@@ -34255,7 +35917,8 @@ pub unsafe fn _mm_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8,
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm512_storeu_epi32(mem_addr: *mut i32, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_epi32(mem_addr: *mut i32, a: __m512i) {
     ptr::write_unaligned(mem_addr as *mut __m512i, a);
 }
 
@@ -34266,7 +35929,8 @@ pub unsafe fn _mm512_storeu_epi32(mem_addr: *mut i32, a: __m512i) {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm256_storeu_epi32(mem_addr: *mut i32, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_epi32(mem_addr: *mut i32, a: __m256i) {
     ptr::write_unaligned(mem_addr as *mut __m256i, a);
 }
 
@@ -34277,7 +35941,8 @@ pub unsafe fn _mm256_storeu_epi32(mem_addr: *mut i32, a: __m256i) {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm_storeu_epi32(mem_addr: *mut i32, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_epi32(mem_addr: *mut i32, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut __m128i, a);
 }
 
@@ -34288,7 +35953,8 @@ pub unsafe fn _mm_storeu_epi32(mem_addr: *mut i32, a: __m128i) {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64
-pub unsafe fn _mm512_loadu_epi64(mem_addr: *const i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_epi64(mem_addr: *const i64) -> __m512i {
     ptr::read_unaligned(mem_addr as *const __m512i)
 }
 
@@ -34299,7 +35965,8 @@ pub unsafe fn _mm512_loadu_epi64(mem_addr: *const i64) -> __m512i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64
-pub unsafe fn _mm256_loadu_epi64(mem_addr: *const i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_epi64(mem_addr: *const i64) -> __m256i {
     ptr::read_unaligned(mem_addr as *const __m256i)
 }
 
@@ -34310,7 +35977,8 @@ pub unsafe fn _mm256_loadu_epi64(mem_addr: *const i64) -> __m256i {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64
-pub unsafe fn _mm_loadu_epi64(mem_addr: *const i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_epi64(mem_addr: *const i64) -> __m128i {
     ptr::read_unaligned(mem_addr as *const __m128i)
 }
 
@@ -34321,7 +35989,8 @@ pub unsafe fn _mm_loadu_epi64(mem_addr: *const i64) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64
-pub unsafe fn _mm512_storeu_epi64(mem_addr: *mut i64, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_epi64(mem_addr: *mut i64, a: __m512i) {
     ptr::write_unaligned(mem_addr as *mut __m512i, a);
 }
 
@@ -34332,7 +36001,8 @@ pub unsafe fn _mm512_storeu_epi64(mem_addr: *mut i64, a: __m512i) {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64
-pub unsafe fn _mm256_storeu_epi64(mem_addr: *mut i64, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_epi64(mem_addr: *mut i64, a: __m256i) {
     ptr::write_unaligned(mem_addr as *mut __m256i, a);
 }
 
@@ -34343,7 +36013,8 @@ pub unsafe fn _mm256_storeu_epi64(mem_addr: *mut i64, a: __m256i) {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64
-pub unsafe fn _mm_storeu_epi64(mem_addr: *mut i64, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_epi64(mem_addr: *mut i64, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut __m128i, a);
 }
 
@@ -34354,7 +36025,8 @@ pub unsafe fn _mm_storeu_epi64(mem_addr: *mut i64, a: __m128i) {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm512_loadu_si512(mem_addr: *const __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_si512(mem_addr: *const __m512i) -> __m512i {
     ptr::read_unaligned(mem_addr)
 }
 
@@ -34365,7 +36037,8 @@ pub unsafe fn _mm512_loadu_si512(mem_addr: *const __m512i) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32
-pub unsafe fn _mm512_storeu_si512(mem_addr: *mut __m512i, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_si512(mem_addr: *mut __m512i, a: __m512i) {
     ptr::write_unaligned(mem_addr, a);
 }
 
@@ -34378,7 +36051,8 @@ pub unsafe fn _mm512_storeu_si512(mem_addr: *mut __m512i, a: __m512i) {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))]
-pub unsafe fn _mm512_loadu_pd(mem_addr: *const f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_pd(mem_addr: *const f64) -> __m512d {
     ptr::read_unaligned(mem_addr as *const __m512d)
 }
 
@@ -34391,7 +36065,8 @@ pub unsafe fn _mm512_loadu_pd(mem_addr: *const f64) -> __m512d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))]
-pub unsafe fn _mm512_storeu_pd(mem_addr: *mut f64, a: __m512d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_pd(mem_addr: *mut f64, a: __m512d) {
     ptr::write_unaligned(mem_addr as *mut __m512d, a);
 }
 
@@ -34404,7 +36079,8 @@ pub unsafe fn _mm512_storeu_pd(mem_addr: *mut f64, a: __m512d) {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))]
-pub unsafe fn _mm512_loadu_ps(mem_addr: *const f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_ps(mem_addr: *const f32) -> __m512 {
     ptr::read_unaligned(mem_addr as *const __m512)
 }
 
@@ -34417,7 +36093,8 @@ pub unsafe fn _mm512_loadu_ps(mem_addr: *const f32) -> __m512 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))]
-pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) {
     ptr::write_unaligned(mem_addr as *mut __m512, a);
 }
 
@@ -34431,7 +36108,8 @@ pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
     ptr::read(mem_addr)
 }
 
@@ -34445,7 +36123,8 @@ pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
     ptr::write(mem_addr, a);
 }
 
@@ -34459,7 +36138,8 @@ pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
     ptr::read(mem_addr as *const __m512i)
 }
 
@@ -34473,7 +36153,8 @@ pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
     ptr::read(mem_addr as *const __m256i)
 }
 
@@ -34487,7 +36168,8 @@ pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
     ptr::read(mem_addr as *const __m128i)
 }
 
@@ -34501,7 +36183,8 @@ pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
     ptr::write(mem_addr as *mut __m512i, a);
 }
 
@@ -34515,7 +36198,8 @@ pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
     ptr::write(mem_addr as *mut __m256i, a);
 }
 
@@ -34529,7 +36213,8 @@ pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa32
-pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
     ptr::write(mem_addr as *mut __m128i, a);
 }
 
@@ -34543,7 +36228,8 @@ pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa64
-pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
     ptr::read(mem_addr as *const __m512i)
 }
 
@@ -34557,7 +36243,8 @@ pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa64
-pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
     ptr::read(mem_addr as *const __m256i)
 }
 
@@ -34571,7 +36258,8 @@ pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa64
-pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
     ptr::read(mem_addr as *const __m128i)
 }
 
@@ -34585,7 +36273,8 @@ pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa64
-pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
     ptr::write(mem_addr as *mut __m512i, a);
 }
 
@@ -34599,7 +36288,8 @@ pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa64
-pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
     ptr::write(mem_addr as *mut __m256i, a);
 }
 
@@ -34613,7 +36303,8 @@ pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovdqa64
-pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
     ptr::write(mem_addr as *mut __m128i, a);
 }
 
@@ -34627,7 +36318,8 @@ pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )]
-pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
     ptr::read(mem_addr as *const __m512)
 }
 
@@ -34641,7 +36333,8 @@ pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )]
-pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
     ptr::write(mem_addr as *mut __m512, a);
 }
 
@@ -34655,7 +36348,8 @@ pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovapd
-pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
     ptr::read(mem_addr as *const __m512d)
 }
 
@@ -34669,7 +36363,8 @@ pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
     all(test, not(all(target_arch = "x86", target_env = "msvc"))),
     assert_instr(vmovaps)
 )] //should be vmovapd
-pub unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) {
     ptr::write(mem_addr as *mut __m512d, a);
 }
 
@@ -34682,7 +36377,12 @@ pub unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) {
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_loadu_epi32(src: __m512i, k: __mmask16, mem_addr: *const i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_loadu_epi32(
+    src: __m512i,
+    k: __mmask16,
+    mem_addr: *const i32,
+) -> __m512i {
     let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i32x16()).as_m512i()
 }
@@ -34696,7 +36396,8 @@ pub unsafe fn _mm512_mask_loadu_epi32(src: __m512i, k: __mmask16, mem_addr: *con
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_loadu_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_loadu_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i {
     _mm512_mask_loadu_epi32(_mm512_setzero_si512(), k, mem_addr)
 }
 
@@ -34709,7 +36410,12 @@ pub unsafe fn _mm512_maskz_loadu_epi32(k: __mmask16, mem_addr: *const i32) -> __
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_loadu_epi64(src: __m512i, k: __mmask8, mem_addr: *const i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_loadu_epi64(
+    src: __m512i,
+    k: __mmask8,
+    mem_addr: *const i64,
+) -> __m512i {
     let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i64x8()).as_m512i()
 }
@@ -34723,7 +36429,8 @@ pub unsafe fn _mm512_mask_loadu_epi64(src: __m512i, k: __mmask8, mem_addr: *cons
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i {
     _mm512_mask_loadu_epi64(_mm512_setzero_si512(), k, mem_addr)
 }
 
@@ -34736,7 +36443,12 @@ pub unsafe fn _mm512_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_loadu_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_loadu_ps(
+    src: __m512,
+    k: __mmask16,
+    mem_addr: *const f32,
+) -> __m512 {
     let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f32x16()).as_m512()
 }
@@ -34750,7 +36462,8 @@ pub unsafe fn _mm512_mask_loadu_ps(src: __m512, k: __mmask16, mem_addr: *const f
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_loadu_ps(k: __mmask16, mem_addr: *const f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_loadu_ps(k: __mmask16, mem_addr: *const f32) -> __m512 {
     _mm512_mask_loadu_ps(_mm512_setzero_ps(), k, mem_addr)
 }
 
@@ -34763,7 +36476,12 @@ pub unsafe fn _mm512_maskz_loadu_ps(k: __mmask16, mem_addr: *const f32) -> __m51
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_loadu_pd(src: __m512d, k: __mmask8, mem_addr: *const f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_loadu_pd(
+    src: __m512d,
+    k: __mmask8,
+    mem_addr: *const f64,
+) -> __m512d {
     let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f64x8()).as_m512d()
 }
@@ -34777,7 +36495,8 @@ pub unsafe fn _mm512_mask_loadu_pd(src: __m512d, k: __mmask8, mem_addr: *const f
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512d {
     _mm512_mask_loadu_pd(_mm512_setzero_pd(), k, mem_addr)
 }
 
@@ -34790,7 +36509,12 @@ pub unsafe fn _mm512_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_loadu_epi32(src: __m256i, k: __mmask8, mem_addr: *const i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_loadu_epi32(
+    src: __m256i,
+    k: __mmask8,
+    mem_addr: *const i32,
+) -> __m256i {
     let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i32x8()).as_m256i()
 }
@@ -34804,7 +36528,8 @@ pub unsafe fn _mm256_mask_loadu_epi32(src: __m256i, k: __mmask8, mem_addr: *cons
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i {
     _mm256_mask_loadu_epi32(_mm256_setzero_si256(), k, mem_addr)
 }
 
@@ -34817,7 +36542,12 @@ pub unsafe fn _mm256_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_loadu_epi64(src: __m256i, k: __mmask8, mem_addr: *const i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_loadu_epi64(
+    src: __m256i,
+    k: __mmask8,
+    mem_addr: *const i64,
+) -> __m256i {
     let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i64x4()).as_m256i()
 }
@@ -34831,7 +36561,8 @@ pub unsafe fn _mm256_mask_loadu_epi64(src: __m256i, k: __mmask8, mem_addr: *cons
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i {
     _mm256_mask_loadu_epi64(_mm256_setzero_si256(), k, mem_addr)
 }
 
@@ -34844,7 +36575,8 @@ pub unsafe fn _mm256_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_loadu_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_loadu_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 {
     let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f32x8()).as_m256()
 }
@@ -34858,7 +36590,8 @@ pub unsafe fn _mm256_mask_loadu_ps(src: __m256, k: __mmask8, mem_addr: *const f3
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256 {
     _mm256_mask_loadu_ps(_mm256_setzero_ps(), k, mem_addr)
 }
 
@@ -34871,7 +36604,12 @@ pub unsafe fn _mm256_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_loadu_pd(src: __m256d, k: __mmask8, mem_addr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_loadu_pd(
+    src: __m256d,
+    k: __mmask8,
+    mem_addr: *const f64,
+) -> __m256d {
     let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f64x4()).as_m256d()
 }
@@ -34885,7 +36623,8 @@ pub unsafe fn _mm256_mask_loadu_pd(src: __m256d, k: __mmask8, mem_addr: *const f
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256d {
     _mm256_mask_loadu_pd(_mm256_setzero_pd(), k, mem_addr)
 }
 
@@ -34898,7 +36637,12 @@ pub unsafe fn _mm256_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_loadu_epi32(src: __m128i, k: __mmask8, mem_addr: *const i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_loadu_epi32(
+    src: __m128i,
+    k: __mmask8,
+    mem_addr: *const i32,
+) -> __m128i {
     let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i32x4()).as_m128i()
 }
@@ -34912,7 +36656,8 @@ pub unsafe fn _mm_mask_loadu_epi32(src: __m128i, k: __mmask8, mem_addr: *const i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i {
     _mm_mask_loadu_epi32(_mm_setzero_si128(), k, mem_addr)
 }
 
@@ -34925,7 +36670,12 @@ pub unsafe fn _mm_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_loadu_epi64(src: __m128i, k: __mmask8, mem_addr: *const i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_loadu_epi64(
+    src: __m128i,
+    k: __mmask8,
+    mem_addr: *const i64,
+) -> __m128i {
     let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i64x2()).as_m128i()
 }
@@ -34939,7 +36689,8 @@ pub unsafe fn _mm_mask_loadu_epi64(src: __m128i, k: __mmask8, mem_addr: *const i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i {
     _mm_mask_loadu_epi64(_mm_setzero_si128(), k, mem_addr)
 }
 
@@ -34952,7 +36703,8 @@ pub unsafe fn _mm_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_loadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_loadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
     let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f32x4()).as_m128()
 }
@@ -34966,7 +36718,8 @@ pub unsafe fn _mm_mask_loadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
     _mm_mask_loadu_ps(_mm_setzero_ps(), k, mem_addr)
 }
 
@@ -34979,7 +36732,8 @@ pub unsafe fn _mm_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_loadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_loadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
     let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_f64x2()).as_m128d()
 }
@@ -34993,7 +36747,8 @@ pub unsafe fn _mm_mask_loadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
     _mm_mask_loadu_pd(_mm_setzero_pd(), k, mem_addr)
 }
 
@@ -35006,7 +36761,12 @@ pub unsafe fn _mm_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_load_epi32(src: __m512i, k: __mmask16, mem_addr: *const i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_load_epi32(
+    src: __m512i,
+    k: __mmask16,
+    mem_addr: *const i32,
+) -> __m512i {
     let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i32x16()).as_m512i()
 }
@@ -35020,7 +36780,8 @@ pub unsafe fn _mm512_mask_load_epi32(src: __m512i, k: __mmask16, mem_addr: *cons
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_load_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_load_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i {
     _mm512_mask_load_epi32(_mm512_setzero_si512(), k, mem_addr)
 }
 
@@ -35033,7 +36794,12 @@ pub unsafe fn _mm512_maskz_load_epi32(k: __mmask16, mem_addr: *const i32) -> __m
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_load_epi64(src: __m512i, k: __mmask8, mem_addr: *const i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_load_epi64(
+    src: __m512i,
+    k: __mmask8,
+    mem_addr: *const i64,
+) -> __m512i {
     let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i64x8()).as_m512i()
 }
@@ -35047,7 +36813,8 @@ pub unsafe fn _mm512_mask_load_epi64(src: __m512i, k: __mmask8, mem_addr: *const
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i {
     _mm512_mask_load_epi64(_mm512_setzero_si512(), k, mem_addr)
 }
 
@@ -35060,7 +36827,8 @@ pub unsafe fn _mm512_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m5
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_load_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_load_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 {
     let mask = simd_select_bitmask(k, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f32x16()).as_m512()
 }
@@ -35074,7 +36842,8 @@ pub unsafe fn _mm512_mask_load_ps(src: __m512, k: __mmask16, mem_addr: *const f3
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_load_ps(k: __mmask16, mem_addr: *const f32) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_load_ps(k: __mmask16, mem_addr: *const f32) -> __m512 {
     _mm512_mask_load_ps(_mm512_setzero_ps(), k, mem_addr)
 }
 
@@ -35087,7 +36856,12 @@ pub unsafe fn _mm512_maskz_load_ps(k: __mmask16, mem_addr: *const f32) -> __m512
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_load_pd(src: __m512d, k: __mmask8, mem_addr: *const f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_load_pd(
+    src: __m512d,
+    k: __mmask8,
+    mem_addr: *const f64,
+) -> __m512d {
     let mask = simd_select_bitmask(k, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f64x8()).as_m512d()
 }
@@ -35101,7 +36875,8 @@ pub unsafe fn _mm512_mask_load_pd(src: __m512d, k: __mmask8, mem_addr: *const f6
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m512d {
     _mm512_mask_load_pd(_mm512_setzero_pd(), k, mem_addr)
 }
 
@@ -35114,7 +36889,12 @@ pub unsafe fn _mm512_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m512d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_load_epi32(src: __m256i, k: __mmask8, mem_addr: *const i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_load_epi32(
+    src: __m256i,
+    k: __mmask8,
+    mem_addr: *const i32,
+) -> __m256i {
     let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i32x8()).as_m256i()
 }
@@ -35128,7 +36908,8 @@ pub unsafe fn _mm256_mask_load_epi32(src: __m256i, k: __mmask8, mem_addr: *const
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i {
     _mm256_mask_load_epi32(_mm256_setzero_si256(), k, mem_addr)
 }
 
@@ -35141,7 +36922,12 @@ pub unsafe fn _mm256_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_load_epi64(src: __m256i, k: __mmask8, mem_addr: *const i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_load_epi64(
+    src: __m256i,
+    k: __mmask8,
+    mem_addr: *const i64,
+) -> __m256i {
     let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i64x4()).as_m256i()
 }
@@ -35155,7 +36941,8 @@ pub unsafe fn _mm256_mask_load_epi64(src: __m256i, k: __mmask8, mem_addr: *const
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i {
     _mm256_mask_load_epi64(_mm256_setzero_si256(), k, mem_addr)
 }
 
@@ -35168,7 +36955,8 @@ pub unsafe fn _mm256_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m2
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_load_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_load_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 {
     let mask = simd_select_bitmask(k, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f32x8()).as_m256()
 }
@@ -35182,7 +36970,8 @@ pub unsafe fn _mm256_mask_load_ps(src: __m256, k: __mmask8, mem_addr: *const f32
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m256 {
     _mm256_mask_load_ps(_mm256_setzero_ps(), k, mem_addr)
 }
 
@@ -35195,7 +36984,12 @@ pub unsafe fn _mm256_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_load_pd(src: __m256d, k: __mmask8, mem_addr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_load_pd(
+    src: __m256d,
+    k: __mmask8,
+    mem_addr: *const f64,
+) -> __m256d {
     let mask = simd_select_bitmask(k, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f64x4()).as_m256d()
 }
@@ -35209,7 +37003,8 @@ pub unsafe fn _mm256_mask_load_pd(src: __m256d, k: __mmask8, mem_addr: *const f6
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m256d {
     _mm256_mask_load_pd(_mm256_setzero_pd(), k, mem_addr)
 }
 
@@ -35222,7 +37017,12 @@ pub unsafe fn _mm256_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m256d
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_load_epi32(src: __m128i, k: __mmask8, mem_addr: *const i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_load_epi32(
+    src: __m128i,
+    k: __mmask8,
+    mem_addr: *const i32,
+) -> __m128i {
     let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i32x4()).as_m128i()
 }
@@ -35236,7 +37036,8 @@ pub unsafe fn _mm_mask_load_epi32(src: __m128i, k: __mmask8, mem_addr: *const i3
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i {
     _mm_mask_load_epi32(_mm_setzero_si128(), k, mem_addr)
 }
 
@@ -35249,7 +37050,12 @@ pub unsafe fn _mm_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_load_epi64(src: __m128i, k: __mmask8, mem_addr: *const i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_load_epi64(
+    src: __m128i,
+    k: __mmask8,
+    mem_addr: *const i64,
+) -> __m128i {
     let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_i64x2()).as_m128i()
 }
@@ -35263,7 +37069,8 @@ pub unsafe fn _mm_mask_load_epi64(src: __m128i, k: __mmask8, mem_addr: *const i6
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i {
     _mm_mask_load_epi64(_mm_setzero_si128(), k, mem_addr)
 }
 
@@ -35276,7 +37083,8 @@ pub unsafe fn _mm_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_load_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_load_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
     let mask = simd_select_bitmask(k, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f32x4()).as_m128()
 }
@@ -35290,7 +37098,8 @@ pub unsafe fn _mm_mask_load_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
     _mm_mask_load_ps(_mm_setzero_ps(), k, mem_addr)
 }
 
@@ -35303,7 +37112,8 @@ pub unsafe fn _mm_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m128 {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_load_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_load_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
     let mask = simd_select_bitmask(k, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_load!(SimdAlign::Vector, mask, mem_addr, src.as_f64x2()).as_m128d()
 }
@@ -35317,7 +37127,8 @@ pub unsafe fn _mm_mask_load_pd(src: __m128d, k: __mmask8, mem_addr: *const f64)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
     _mm_mask_load_pd(_mm_setzero_pd(), k, mem_addr)
 }
 
@@ -35417,7 +37228,8 @@ pub unsafe fn _mm_maskz_load_sd(k: __mmask8, mem_addr: *const f64) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) {
     let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x16());
 }
@@ -35430,7 +37242,8 @@ pub unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: _
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) {
     let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x8());
 }
@@ -35443,7 +37256,8 @@ pub unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) {
     let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f32x16());
 }
@@ -35456,7 +37270,8 @@ pub unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m5
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) {
     let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f64x8());
 }
@@ -35469,7 +37284,8 @@ pub unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m51
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) {
     let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x8());
 }
@@ -35482,7 +37298,8 @@ pub unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) {
     let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x4());
 }
@@ -35495,7 +37312,8 @@ pub unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) {
     let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f32x8());
 }
@@ -35508,7 +37326,8 @@ pub unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) {
     let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f64x4());
 }
@@ -35521,7 +37340,8 @@ pub unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m25
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) {
     let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i32x4());
 }
@@ -35534,7 +37354,8 @@ pub unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) {
     let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i64x2());
 }
@@ -35547,7 +37368,8 @@ pub unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m12
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovups))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
     let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f32x4());
 }
@@ -35560,7 +37382,8 @@ pub unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128)
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovupd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) {
     let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_f64x2());
 }
@@ -35573,7 +37396,8 @@ pub unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d)
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) {
     let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i32x16());
 }
@@ -35586,7 +37410,8 @@ pub unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) {
     let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i64x8());
 }
@@ -35599,7 +37424,8 @@ pub unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) {
     let mask = simd_select_bitmask(mask, i32x16::splat(!0), i32x16::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f32x16());
 }
@@ -35612,7 +37438,8 @@ pub unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m51
 #[target_feature(enable = "avx512f")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) {
     let mask = simd_select_bitmask(mask, i64x8::splat(!0), i64x8::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f64x8());
 }
@@ -35625,7 +37452,8 @@ pub unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) {
     let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i32x8());
 }
@@ -35638,7 +37466,8 @@ pub unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) {
     let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i64x4());
 }
@@ -35651,7 +37480,8 @@ pub unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) {
     let mask = simd_select_bitmask(mask, i32x8::splat(!0), i32x8::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f32x8());
 }
@@ -35664,7 +37494,8 @@ pub unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) {
     let mask = simd_select_bitmask(mask, i64x4::splat(!0), i64x4::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f64x4());
 }
@@ -35677,7 +37508,8 @@ pub unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa32))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) {
     let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i32x4());
 }
@@ -35690,7 +37522,8 @@ pub unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqa64))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) {
     let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_i64x2());
 }
@@ -35703,7 +37536,8 @@ pub unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovaps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
     let mask = simd_select_bitmask(mask, i32x4::splat(!0), i32x4::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f32x4());
 }
@@ -35716,7 +37550,8 @@ pub unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) {
 #[target_feature(enable = "avx512f,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovapd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) {
     let mask = simd_select_bitmask(mask, i64x2::splat(!0), i64x2::ZERO);
     simd_masked_store!(SimdAlign::Vector, mask, mem_addr, a.as_f64x2());
 }
@@ -36063,7 +37898,8 @@ pub unsafe fn _mm_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> __m
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_setr_pd(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr_pd(
     e0: f64,
     e1: f64,
     e2: f64,
@@ -36085,7 +37921,8 @@ pub fn _mm512_setr_pd(
 #[inline]
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_set_pd(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_pd(
     e0: f64,
     e1: f64,
     e2: f64,
@@ -36105,7 +37942,8 @@ pub fn _mm512_set_pd(
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovss))]
-pub fn _mm_mask_move_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_move_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let extractsrc: f32 = simd_extract!(src, 0);
         let mut mov: f32 = extractsrc;
@@ -36123,7 +37961,8 @@ pub fn _mm_mask_move_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovss))]
-pub fn _mm_maskz_move_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_move_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mut mov: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36140,7 +37979,8 @@ pub fn _mm_maskz_move_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsd))]
-pub fn _mm_mask_move_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_move_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let extractsrc: f64 = simd_extract!(src, 0);
         let mut mov: f64 = extractsrc;
@@ -36158,7 +37998,8 @@ pub fn _mm_mask_move_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovsd))]
-pub fn _mm_maskz_move_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_move_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mut mov: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36175,7 +38016,8 @@ pub fn _mm_maskz_move_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddss))]
-pub fn _mm_mask_add_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let extractsrc: f32 = simd_extract!(src, 0);
         let mut add: f32 = extractsrc;
@@ -36195,7 +38037,8 @@ pub fn _mm_mask_add_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddss))]
-pub fn _mm_maskz_add_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mut add: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36214,7 +38057,8 @@ pub fn _mm_maskz_add_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddsd))]
-pub fn _mm_mask_add_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let extractsrc: f64 = simd_extract!(src, 0);
         let mut add: f64 = extractsrc;
@@ -36234,7 +38078,8 @@ pub fn _mm_mask_add_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vaddsd))]
-pub fn _mm_maskz_add_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mut add: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36253,7 +38098,8 @@ pub fn _mm_maskz_add_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubss))]
-pub fn _mm_mask_sub_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let extractsrc: f32 = simd_extract!(src, 0);
         let mut add: f32 = extractsrc;
@@ -36273,7 +38119,8 @@ pub fn _mm_mask_sub_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubss))]
-pub fn _mm_maskz_sub_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mut add: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36292,7 +38139,8 @@ pub fn _mm_maskz_sub_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubsd))]
-pub fn _mm_mask_sub_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let extractsrc: f64 = simd_extract!(src, 0);
         let mut add: f64 = extractsrc;
@@ -36312,7 +38160,8 @@ pub fn _mm_mask_sub_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vsubsd))]
-pub fn _mm_maskz_sub_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mut add: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36331,7 +38180,8 @@ pub fn _mm_maskz_sub_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulss))]
-pub fn _mm_mask_mul_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let extractsrc: f32 = simd_extract!(src, 0);
         let mut add: f32 = extractsrc;
@@ -36351,7 +38201,8 @@ pub fn _mm_mask_mul_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulss))]
-pub fn _mm_maskz_mul_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mut add: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36370,7 +38221,8 @@ pub fn _mm_maskz_mul_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulsd))]
-pub fn _mm_mask_mul_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let extractsrc: f64 = simd_extract!(src, 0);
         let mut add: f64 = extractsrc;
@@ -36390,7 +38242,8 @@ pub fn _mm_mask_mul_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmulsd))]
-pub fn _mm_maskz_mul_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mut add: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36409,7 +38262,8 @@ pub fn _mm_maskz_mul_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivss))]
-pub fn _mm_mask_div_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_div_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let extractsrc: f32 = simd_extract!(src, 0);
         let mut add: f32 = extractsrc;
@@ -36429,7 +38283,8 @@ pub fn _mm_mask_div_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivss))]
-pub fn _mm_maskz_div_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_div_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let mut add: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -36448,7 +38303,8 @@ pub fn _mm_maskz_div_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivsd))]
-pub fn _mm_mask_div_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_div_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let extractsrc: f64 = simd_extract!(src, 0);
         let mut add: f64 = extractsrc;
@@ -36468,7 +38324,8 @@ pub fn _mm_mask_div_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vdivsd))]
-pub fn _mm_maskz_div_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_div_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let mut add: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37452,7 +39309,8 @@ pub fn _mm_maskz_scalef_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-pub fn _mm_mask_fmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fmadd: f32 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37471,7 +39329,8 @@ pub fn _mm_mask_fmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-pub fn _mm_maskz_fmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fmadd: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37491,7 +39350,8 @@ pub fn _mm_maskz_fmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-pub fn _mm_mask3_fmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe {
         let mut fmadd: f32 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37510,7 +39370,8 @@ pub fn _mm_mask3_fmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-pub fn _mm_mask_fmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fmadd: f64 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37529,7 +39390,8 @@ pub fn _mm_mask_fmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-pub fn _mm_maskz_fmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fmadd: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37549,7 +39411,8 @@ pub fn _mm_maskz_fmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-pub fn _mm_mask3_fmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe {
         let mut fmadd: f64 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37568,7 +39431,8 @@ pub fn _mm_mask3_fmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-pub fn _mm_mask_fmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fmsub: f32 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37588,7 +39452,8 @@ pub fn _mm_mask_fmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-pub fn _mm_maskz_fmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fmsub: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37609,7 +39474,8 @@ pub fn _mm_maskz_fmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-pub fn _mm_mask3_fmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe {
         let mut fmsub: f32 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37629,7 +39495,8 @@ pub fn _mm_mask3_fmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-pub fn _mm_mask_fmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fmsub: f64 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37649,7 +39516,8 @@ pub fn _mm_mask_fmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-pub fn _mm_maskz_fmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fmsub: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37670,7 +39538,8 @@ pub fn _mm_maskz_fmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-pub fn _mm_mask3_fmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe {
         let mut fmsub: f64 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37690,7 +39559,8 @@ pub fn _mm_mask3_fmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-pub fn _mm_mask_fnmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fnmadd: f32 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37710,7 +39580,8 @@ pub fn _mm_mask_fnmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-pub fn _mm_maskz_fnmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fnmadd: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37731,7 +39602,8 @@ pub fn _mm_maskz_fnmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-pub fn _mm_mask3_fnmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe {
         let mut fnmadd: f32 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37751,7 +39623,8 @@ pub fn _mm_mask3_fnmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-pub fn _mm_mask_fnmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fnmadd: f64 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37771,7 +39644,8 @@ pub fn _mm_mask_fnmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-pub fn _mm_maskz_fnmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fnmadd: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37792,7 +39666,8 @@ pub fn _mm_maskz_fnmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-pub fn _mm_mask3_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe {
         let mut fnmadd: f64 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37812,7 +39687,8 @@ pub fn _mm_mask3_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-pub fn _mm_mask_fnmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fnmsub: f32 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37833,7 +39709,8 @@ pub fn _mm_mask_fnmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-pub fn _mm_maskz_fnmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 {
     unsafe {
         let mut fnmsub: f32 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37855,7 +39732,8 @@ pub fn _mm_maskz_fnmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-pub fn _mm_mask3_fnmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 {
     unsafe {
         let mut fnmsub: f32 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -37876,7 +39754,8 @@ pub fn _mm_mask3_fnmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-pub fn _mm_mask_fnmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fnmsub: f64 = simd_extract!(a, 0);
         if (k & 0b00000001) != 0 {
@@ -37897,7 +39776,8 @@ pub fn _mm_mask_fnmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-pub fn _mm_maskz_fnmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d {
     unsafe {
         let mut fnmsub: f64 = 0.;
         if (k & 0b00000001) != 0 {
@@ -37919,7 +39799,8 @@ pub fn _mm_maskz_fnmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-pub fn _mm_mask3_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d {
     unsafe {
         let mut fnmsub: f64 = simd_extract!(c, 0);
         if (k & 0b00000001) != 0 {
@@ -41499,7 +43380,8 @@ pub fn _mm_cvt_roundu32_ss<const ROUNDING: i32>(a: __m128, b: u32) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtsi2ss))]
-pub fn _mm_cvti32_ss(a: __m128, b: i32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvti32_ss(a: __m128, b: i32) -> __m128 {
     unsafe {
         let b = b as f32;
         simd_insert!(a, 0, b)
@@ -41513,7 +43395,8 @@ pub fn _mm_cvti32_ss(a: __m128, b: i32) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtsi2sd))]
-pub fn _mm_cvti32_sd(a: __m128d, b: i32) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvti32_sd(a: __m128d, b: i32) -> __m128d {
     unsafe {
         let b = b as f64;
         simd_insert!(a, 0, b)
@@ -41673,7 +43556,8 @@ pub fn _mm_cvttsd_u32(a: __m128d) -> u32 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtusi2ss))]
-pub fn _mm_cvtu32_ss(a: __m128, b: u32) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtu32_ss(a: __m128, b: u32) -> __m128 {
     unsafe {
         let b = b as f32;
         simd_insert!(a, 0, b)
@@ -41687,7 +43571,8 @@ pub fn _mm_cvtu32_ss(a: __m128, b: u32) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtusi2sd))]
-pub fn _mm_cvtu32_sd(a: __m128d, b: u32) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtu32_sd(a: __m128d, b: u32) -> __m128d {
     unsafe {
         let b = b as f64;
         simd_insert!(a, 0, b)
@@ -43139,6 +45024,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
@@ -43147,7 +45033,7 @@ mod tests {
     use crate::mem::{self};
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_abs_epi32() {
+    const unsafe fn test_mm512_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43167,7 +45053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_abs_epi32() {
+    const unsafe fn test_mm512_mask_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43189,7 +45075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_abs_epi32() {
+    const unsafe fn test_mm512_maskz_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43211,7 +45097,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_abs_epi32() {
+    const unsafe fn test_mm256_mask_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43229,7 +45115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_abs_epi32() {
+    const unsafe fn test_mm256_maskz_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43247,7 +45133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_abs_epi32() {
+    const unsafe fn test_mm_mask_abs_epi32() {
         let a = _mm_setr_epi32(i32::MIN, 100, -100, -32);
         let r = _mm_mask_abs_epi32(a, 0, a);
         assert_eq_m128i(r, a);
@@ -43257,7 +45143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_abs_epi32() {
+    const unsafe fn test_mm_maskz_abs_epi32() {
         let a = _mm_setr_epi32(i32::MIN, 100, -100, -32);
         let r = _mm_maskz_abs_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -43267,7 +45153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_abs_ps() {
+    const unsafe fn test_mm512_abs_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43287,7 +45173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_abs_ps() {
+    const unsafe fn test_mm512_mask_abs_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43309,7 +45195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mov_epi32() {
+    const unsafe fn test_mm512_mask_mov_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(2);
         let r = _mm512_mask_mov_epi32(src, 0, a);
@@ -43319,7 +45205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mov_epi32() {
+    const unsafe fn test_mm512_maskz_mov_epi32() {
         let a = _mm512_set1_epi32(2);
         let r = _mm512_maskz_mov_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -43328,7 +45214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mov_epi32() {
+    const unsafe fn test_mm256_mask_mov_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(2);
         let r = _mm256_mask_mov_epi32(src, 0, a);
@@ -43338,7 +45224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mov_epi32() {
+    const unsafe fn test_mm256_maskz_mov_epi32() {
         let a = _mm256_set1_epi32(2);
         let r = _mm256_maskz_mov_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -43347,7 +45233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mov_epi32() {
+    const unsafe fn test_mm_mask_mov_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(2);
         let r = _mm_mask_mov_epi32(src, 0, a);
@@ -43357,7 +45243,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mov_epi32() {
+    const unsafe fn test_mm_maskz_mov_epi32() {
         let a = _mm_set1_epi32(2);
         let r = _mm_maskz_mov_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -43366,7 +45252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mov_ps() {
+    const unsafe fn test_mm512_mask_mov_ps() {
         let src = _mm512_set1_ps(1.);
         let a = _mm512_set1_ps(2.);
         let r = _mm512_mask_mov_ps(src, 0, a);
@@ -43376,7 +45262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mov_ps() {
+    const unsafe fn test_mm512_maskz_mov_ps() {
         let a = _mm512_set1_ps(2.);
         let r = _mm512_maskz_mov_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -43385,7 +45271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mov_ps() {
+    const unsafe fn test_mm256_mask_mov_ps() {
         let src = _mm256_set1_ps(1.);
         let a = _mm256_set1_ps(2.);
         let r = _mm256_mask_mov_ps(src, 0, a);
@@ -43395,7 +45281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mov_ps() {
+    const unsafe fn test_mm256_maskz_mov_ps() {
         let a = _mm256_set1_ps(2.);
         let r = _mm256_maskz_mov_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -43404,7 +45290,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mov_ps() {
+    const unsafe fn test_mm_mask_mov_ps() {
         let src = _mm_set1_ps(1.);
         let a = _mm_set1_ps(2.);
         let r = _mm_mask_mov_ps(src, 0, a);
@@ -43414,7 +45300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mov_ps() {
+    const unsafe fn test_mm_maskz_mov_ps() {
         let a = _mm_set1_ps(2.);
         let r = _mm_maskz_mov_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -43423,7 +45309,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_add_epi32() {
+    const unsafe fn test_mm512_add_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43444,7 +45330,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_add_epi32() {
+    const unsafe fn test_mm512_mask_add_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43467,7 +45353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_add_epi32() {
+    const unsafe fn test_mm512_maskz_add_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43490,7 +45376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_add_epi32() {
+    const unsafe fn test_mm256_mask_add_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_add_epi32(a, 0, a, b);
@@ -43501,7 +45387,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_add_epi32() {
+    const unsafe fn test_mm256_maskz_add_epi32() {
         let a = _mm256_setr_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_add_epi32(0, a, b);
@@ -43512,7 +45398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_add_epi32() {
+    const unsafe fn test_mm_mask_add_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_add_epi32(a, 0, a, b);
@@ -43523,7 +45409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_add_epi32() {
+    const unsafe fn test_mm_maskz_add_epi32() {
         let a = _mm_setr_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_add_epi32(0, a, b);
@@ -43534,7 +45420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_add_ps() {
+    const unsafe fn test_mm512_add_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43555,7 +45441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_add_ps() {
+    const unsafe fn test_mm512_mask_add_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43578,7 +45464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_add_ps() {
+    const unsafe fn test_mm512_maskz_add_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43601,7 +45487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_add_ps() {
+    const unsafe fn test_mm256_mask_add_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_mask_add_ps(a, 0, a, b);
@@ -43612,7 +45498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_add_ps() {
+    const unsafe fn test_mm256_maskz_add_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_maskz_add_ps(0, a, b);
@@ -43623,7 +45509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_add_ps() {
+    const unsafe fn test_mm_mask_add_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_mask_add_ps(a, 0, a, b);
@@ -43634,7 +45520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_add_ps() {
+    const unsafe fn test_mm_maskz_add_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_maskz_add_ps(0, a, b);
@@ -43645,7 +45531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sub_epi32() {
+    const unsafe fn test_mm512_sub_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43666,7 +45552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sub_epi32() {
+    const unsafe fn test_mm512_mask_sub_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43689,7 +45575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sub_epi32() {
+    const unsafe fn test_mm512_maskz_sub_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43712,7 +45598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sub_epi32() {
+    const unsafe fn test_mm256_mask_sub_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_sub_epi32(a, 0, a, b);
@@ -43723,7 +45609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_epi32() {
+    const unsafe fn test_mm256_maskz_sub_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_sub_epi32(0, a, b);
@@ -43734,7 +45620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sub_epi32() {
+    const unsafe fn test_mm_mask_sub_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_sub_epi32(a, 0, a, b);
@@ -43745,7 +45631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sub_epi32() {
+    const unsafe fn test_mm_maskz_sub_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_sub_epi32(0, a, b);
@@ -43756,7 +45642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sub_ps() {
+    const unsafe fn test_mm512_sub_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43777,7 +45663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sub_ps() {
+    const unsafe fn test_mm512_mask_sub_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43800,7 +45686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sub_ps() {
+    const unsafe fn test_mm512_maskz_sub_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43823,7 +45709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sub_ps() {
+    const unsafe fn test_mm256_mask_sub_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_mask_sub_ps(a, 0, a, b);
@@ -43834,7 +45720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_ps() {
+    const unsafe fn test_mm256_maskz_sub_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_maskz_sub_ps(0, a, b);
@@ -43845,7 +45731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sub_ps() {
+    const unsafe fn test_mm_mask_sub_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_mask_sub_ps(a, 0, a, b);
@@ -43856,7 +45742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sub_ps() {
+    const unsafe fn test_mm_maskz_sub_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_maskz_sub_ps(0, a, b);
@@ -43867,7 +45753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mullo_epi32() {
+    const unsafe fn test_mm512_mullo_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43884,7 +45770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mullo_epi32() {
+    const unsafe fn test_mm512_mask_mullo_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43907,7 +45793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mullo_epi32() {
+    const unsafe fn test_mm512_maskz_mullo_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -43924,7 +45810,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mullo_epi32() {
+    const unsafe fn test_mm256_mask_mullo_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_mask_mullo_epi32(a, 0, a, b);
@@ -43935,7 +45821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mullo_epi32() {
+    const unsafe fn test_mm256_maskz_mullo_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_maskz_mullo_epi32(0, a, b);
@@ -43946,7 +45832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mullo_epi32() {
+    const unsafe fn test_mm_mask_mullo_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(2);
         let r = _mm_mask_mullo_epi32(a, 0, a, b);
@@ -43957,7 +45843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mullo_epi32() {
+    const unsafe fn test_mm_maskz_mullo_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(2);
         let r = _mm_maskz_mullo_epi32(0, a, b);
@@ -43968,7 +45854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mul_ps() {
+    const unsafe fn test_mm512_mul_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -43990,7 +45876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mul_ps() {
+    const unsafe fn test_mm512_mask_mul_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -44013,7 +45899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mul_ps() {
+    const unsafe fn test_mm512_maskz_mul_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -44036,7 +45922,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mul_ps() {
+    const unsafe fn test_mm256_mask_mul_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(2.);
         let r = _mm256_mask_mul_ps(a, 0, a, b);
@@ -44051,7 +45937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mul_ps() {
+    const unsafe fn test_mm256_maskz_mul_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(2.);
         let r = _mm256_maskz_mul_ps(0, a, b);
@@ -44066,7 +45952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mul_ps() {
+    const unsafe fn test_mm_mask_mul_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(2.);
         let r = _mm_mask_mul_ps(a, 0, a, b);
@@ -44077,7 +45963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mul_ps() {
+    const unsafe fn test_mm_maskz_mul_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(2.);
         let r = _mm_maskz_mul_ps(0, a, b);
@@ -44088,7 +45974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_div_ps() {
+    const unsafe fn test_mm512_div_ps() {
         let a = _mm512_setr_ps(
             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
         );
@@ -44107,7 +45993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_div_ps() {
+    const unsafe fn test_mm512_mask_div_ps() {
         let a = _mm512_setr_ps(
             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
         );
@@ -44128,7 +46014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_div_ps() {
+    const unsafe fn test_mm512_maskz_div_ps() {
         let a = _mm512_setr_ps(
             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
         );
@@ -44149,7 +46035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_div_ps() {
+    const unsafe fn test_mm256_mask_div_ps() {
         let a = _mm256_set_ps(0., 1., -1., -2., 100., 100., -100., -32.);
         let b = _mm256_set_ps(2., 2., 2., 2., 2., 0., 2., 2.);
         let r = _mm256_mask_div_ps(a, 0, a, b);
@@ -44160,7 +46046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_div_ps() {
+    const unsafe fn test_mm256_maskz_div_ps() {
         let a = _mm256_set_ps(0., 1., -1., -2., 100., 100., -100., -32.);
         let b = _mm256_set_ps(2., 2., 2., 2., 2., 0., 2., 2.);
         let r = _mm256_maskz_div_ps(0, a, b);
@@ -44171,7 +46057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_div_ps() {
+    const unsafe fn test_mm_mask_div_ps() {
         let a = _mm_set_ps(100., 100., -100., -32.);
         let b = _mm_set_ps(2., 0., 2., 2.);
         let r = _mm_mask_div_ps(a, 0, a, b);
@@ -44182,7 +46068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_div_ps() {
+    const unsafe fn test_mm_maskz_div_ps() {
         let a = _mm_set_ps(100., 100., -100., -32.);
         let b = _mm_set_ps(2., 0., 2., 2.);
         let r = _mm_maskz_div_ps(0, a, b);
@@ -44193,7 +46079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_epi32() {
+    const unsafe fn test_mm512_max_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epi32(a, b);
@@ -44202,7 +46088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_epi32() {
+    const unsafe fn test_mm512_mask_max_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epi32(a, 0, a, b);
@@ -44213,7 +46099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_epi32() {
+    const unsafe fn test_mm512_maskz_max_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epi32(0, a, b);
@@ -44224,7 +46110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_max_epi32() {
+    const unsafe fn test_mm256_mask_max_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epi32(a, 0, a, b);
@@ -44235,7 +46121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epi32() {
+    const unsafe fn test_mm256_maskz_max_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epi32(0, a, b);
@@ -44246,7 +46132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_max_epi32() {
+    const unsafe fn test_mm_mask_max_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_max_epi32(a, 0, a, b);
@@ -44257,7 +46143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_max_epi32() {
+    const unsafe fn test_mm_maskz_max_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_max_epi32(0, a, b);
@@ -44361,7 +46247,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_epu32() {
+    const unsafe fn test_mm512_max_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epu32(a, b);
@@ -44370,7 +46256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_epu32() {
+    const unsafe fn test_mm512_mask_max_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epu32(a, 0, a, b);
@@ -44381,7 +46267,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_epu32() {
+    const unsafe fn test_mm512_maskz_max_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epu32(0, a, b);
@@ -44392,7 +46278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_max_epu32() {
+    const unsafe fn test_mm256_mask_max_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epu32(a, 0, a, b);
@@ -44403,7 +46289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epu32() {
+    const unsafe fn test_mm256_maskz_max_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epu32(0, a, b);
@@ -44414,7 +46300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_max_epu32() {
+    const unsafe fn test_mm_mask_max_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_max_epu32(a, 0, a, b);
@@ -44425,7 +46311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_max_epu32() {
+    const unsafe fn test_mm_maskz_max_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_max_epu32(0, a, b);
@@ -44436,7 +46322,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_epi32() {
+    const unsafe fn test_mm512_min_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epi32(a, b);
@@ -44445,7 +46331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_epi32() {
+    const unsafe fn test_mm512_mask_min_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epi32(a, 0, a, b);
@@ -44456,7 +46342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_epi32() {
+    const unsafe fn test_mm512_maskz_min_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epi32(0, a, b);
@@ -44467,7 +46353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_min_epi32() {
+    const unsafe fn test_mm256_mask_min_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epi32(a, 0, a, b);
@@ -44478,7 +46364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epi32() {
+    const unsafe fn test_mm256_maskz_min_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epi32(0, a, b);
@@ -44489,7 +46375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_min_epi32() {
+    const unsafe fn test_mm_mask_min_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_min_epi32(a, 0, a, b);
@@ -44500,7 +46386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_min_epi32() {
+    const unsafe fn test_mm_maskz_min_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_min_epi32(0, a, b);
@@ -44604,7 +46490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_epu32() {
+    const unsafe fn test_mm512_min_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epu32(a, b);
@@ -44613,7 +46499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_epu32() {
+    const unsafe fn test_mm512_mask_min_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epu32(a, 0, a, b);
@@ -44624,7 +46510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_epu32() {
+    const unsafe fn test_mm512_maskz_min_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epu32(0, a, b);
@@ -44635,7 +46521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_min_epu32() {
+    const unsafe fn test_mm256_mask_min_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epu32(a, 0, a, b);
@@ -44646,7 +46532,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epu32() {
+    const unsafe fn test_mm256_maskz_min_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epu32(0, a, b);
@@ -44657,7 +46543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_min_epu32() {
+    const unsafe fn test_mm_mask_min_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_min_epu32(a, 0, a, b);
@@ -44668,7 +46554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_min_epu32() {
+    const unsafe fn test_mm_maskz_min_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_min_epu32(0, a, b);
@@ -44759,7 +46645,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmadd_ps() {
+    const unsafe fn test_mm512_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44773,7 +46659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmadd_ps() {
+    const unsafe fn test_mm512_mask_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44789,7 +46675,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmadd_ps() {
+    const unsafe fn test_mm512_maskz_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44805,7 +46691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmadd_ps() {
+    const unsafe fn test_mm512_mask3_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44821,7 +46707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmadd_ps() {
+    const unsafe fn test_mm256_mask_fmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -44833,7 +46719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmadd_ps() {
+    const unsafe fn test_mm256_maskz_fmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -44845,7 +46731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmadd_ps() {
+    const unsafe fn test_mm256_mask3_fmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -44857,7 +46743,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_ps() {
+    const unsafe fn test_mm_mask_fmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -44869,7 +46755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_ps() {
+    const unsafe fn test_mm_maskz_fmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -44881,7 +46767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_ps() {
+    const unsafe fn test_mm_mask3_fmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -44893,7 +46779,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsub_ps() {
+    const unsafe fn test_mm512_fmsub_ps() {
         let a = _mm512_setr_ps(
             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
         );
@@ -44911,7 +46797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsub_ps() {
+    const unsafe fn test_mm512_mask_fmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44927,7 +46813,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsub_ps() {
+    const unsafe fn test_mm512_maskz_fmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44943,7 +46829,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsub_ps() {
+    const unsafe fn test_mm512_mask3_fmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -44961,7 +46847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmsub_ps() {
+    const unsafe fn test_mm256_mask_fmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -44973,7 +46859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmsub_ps() {
+    const unsafe fn test_mm256_maskz_fmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -44985,7 +46871,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmsub_ps() {
+    const unsafe fn test_mm256_mask3_fmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -44997,7 +46883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmsub_ps() {
+    const unsafe fn test_mm_mask_fmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45009,7 +46895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmsub_ps() {
+    const unsafe fn test_mm_maskz_fmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45021,7 +46907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmsub_ps() {
+    const unsafe fn test_mm_mask3_fmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45033,7 +46919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmaddsub_ps() {
+    const unsafe fn test_mm512_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45047,7 +46933,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmaddsub_ps() {
+    const unsafe fn test_mm512_mask_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45063,7 +46949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmaddsub_ps() {
+    const unsafe fn test_mm512_maskz_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45079,7 +46965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmaddsub_ps() {
+    const unsafe fn test_mm512_mask3_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45097,7 +46983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmaddsub_ps() {
+    const unsafe fn test_mm256_mask_fmaddsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45109,7 +46995,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmaddsub_ps() {
+    const unsafe fn test_mm256_maskz_fmaddsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45121,7 +47007,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmaddsub_ps() {
+    const unsafe fn test_mm256_mask3_fmaddsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45133,7 +47019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmaddsub_ps() {
+    const unsafe fn test_mm_mask_fmaddsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45145,7 +47031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmaddsub_ps() {
+    const unsafe fn test_mm_maskz_fmaddsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45157,7 +47043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmaddsub_ps() {
+    const unsafe fn test_mm_mask3_fmaddsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45169,7 +47055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsubadd_ps() {
+    const unsafe fn test_mm512_fmsubadd_ps() {
         let a = _mm512_setr_ps(
             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
         );
@@ -45187,7 +47073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsubadd_ps() {
+    const unsafe fn test_mm512_mask_fmsubadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45203,7 +47089,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsubadd_ps() {
+    const unsafe fn test_mm512_maskz_fmsubadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45219,7 +47105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsubadd_ps() {
+    const unsafe fn test_mm512_mask3_fmsubadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45237,7 +47123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmsubadd_ps() {
+    const unsafe fn test_mm256_mask_fmsubadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45249,7 +47135,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmsubadd_ps() {
+    const unsafe fn test_mm256_maskz_fmsubadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45261,7 +47147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmsubadd_ps() {
+    const unsafe fn test_mm256_mask3_fmsubadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45273,7 +47159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmsubadd_ps() {
+    const unsafe fn test_mm_mask_fmsubadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45285,7 +47171,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmsubadd_ps() {
+    const unsafe fn test_mm_maskz_fmsubadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45297,7 +47183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmsubadd_ps() {
+    const unsafe fn test_mm_mask3_fmsubadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45309,7 +47195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmadd_ps() {
+    const unsafe fn test_mm512_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45323,7 +47209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmadd_ps() {
+    const unsafe fn test_mm512_mask_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45339,7 +47225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmadd_ps() {
+    const unsafe fn test_mm512_maskz_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45355,7 +47241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmadd_ps() {
+    const unsafe fn test_mm512_mask3_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45373,7 +47259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fnmadd_ps() {
+    const unsafe fn test_mm256_mask_fnmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45385,7 +47271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fnmadd_ps() {
+    const unsafe fn test_mm256_maskz_fnmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45397,7 +47283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fnmadd_ps() {
+    const unsafe fn test_mm256_mask3_fnmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45409,7 +47295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fnmadd_ps() {
+    const unsafe fn test_mm_mask_fnmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45421,7 +47307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fnmadd_ps() {
+    const unsafe fn test_mm_maskz_fnmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45433,7 +47319,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fnmadd_ps() {
+    const unsafe fn test_mm_mask3_fnmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45445,7 +47331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmsub_ps() {
+    const unsafe fn test_mm512_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45459,7 +47345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmsub_ps() {
+    const unsafe fn test_mm512_mask_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45475,7 +47361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmsub_ps() {
+    const unsafe fn test_mm512_maskz_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45491,7 +47377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmsub_ps() {
+    const unsafe fn test_mm512_mask3_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -45509,7 +47395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fnmsub_ps() {
+    const unsafe fn test_mm256_mask_fnmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45521,7 +47407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fnmsub_ps() {
+    const unsafe fn test_mm256_maskz_fnmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45533,7 +47419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fnmsub_ps() {
+    const unsafe fn test_mm256_mask3_fnmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -45545,7 +47431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fnmsub_ps() {
+    const unsafe fn test_mm_mask_fnmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45557,7 +47443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fnmsub_ps() {
+    const unsafe fn test_mm_maskz_fnmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -45569,7 +47455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fnmsub_ps() {
+    const unsafe fn test_mm_mask3_fnmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47731,7 +49617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi8_epi32() {
+    const unsafe fn test_mm512_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi8_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -47739,7 +49625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi8_epi32() {
+    const unsafe fn test_mm512_mask_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepi8_epi32(src, 0, a);
@@ -47750,7 +49636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi8_epi32() {
+    const unsafe fn test_mm512_maskz_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi8_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -47760,7 +49646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi8_epi32() {
+    const unsafe fn test_mm256_mask_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepi8_epi32(src, 0, a);
@@ -47771,7 +49657,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi8_epi32() {
+    const unsafe fn test_mm256_maskz_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi8_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -47781,7 +49667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi8_epi32() {
+    const unsafe fn test_mm_mask_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepi8_epi32(src, 0, a);
@@ -47792,7 +49678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi8_epi32() {
+    const unsafe fn test_mm_maskz_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepi8_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -47802,7 +49688,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu8_epi32() {
+    const unsafe fn test_mm512_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu8_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -47810,7 +49696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu8_epi32() {
+    const unsafe fn test_mm512_mask_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepu8_epi32(src, 0, a);
@@ -47821,7 +49707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu8_epi32() {
+    const unsafe fn test_mm512_maskz_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu8_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -47831,7 +49717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu8_epi32() {
+    const unsafe fn test_mm256_mask_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepu8_epi32(src, 0, a);
@@ -47842,7 +49728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu8_epi32() {
+    const unsafe fn test_mm256_maskz_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu8_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -47852,7 +49738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu8_epi32() {
+    const unsafe fn test_mm_mask_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepu8_epi32(src, 0, a);
@@ -47863,7 +49749,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu8_epi32() {
+    const unsafe fn test_mm_maskz_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu8_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -47873,7 +49759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi16_epi32() {
+    const unsafe fn test_mm512_cvtepi16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi16_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -47881,7 +49767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi16_epi32() {
+    const unsafe fn test_mm512_mask_cvtepi16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepi16_epi32(src, 0, a);
@@ -47892,7 +49778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi16_epi32() {
+    const unsafe fn test_mm512_maskz_cvtepi16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi16_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -47902,7 +49788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi16_epi32() {
+    const unsafe fn test_mm256_mask_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepi16_epi32(src, 0, a);
@@ -47913,7 +49799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi16_epi32() {
+    const unsafe fn test_mm256_maskz_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_cvtepi16_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -47923,7 +49809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi16_epi32() {
+    const unsafe fn test_mm_mask_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepi16_epi32(src, 0, a);
@@ -47934,7 +49820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi16_epi32() {
+    const unsafe fn test_mm_maskz_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_cvtepi16_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -47944,7 +49830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu16_epi32() {
+    const unsafe fn test_mm512_cvtepu16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu16_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -47952,7 +49838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu16_epi32() {
+    const unsafe fn test_mm512_mask_cvtepu16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepu16_epi32(src, 0, a);
@@ -47963,7 +49849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu16_epi32() {
+    const unsafe fn test_mm512_maskz_cvtepu16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu16_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -47973,7 +49859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu16_epi32() {
+    const unsafe fn test_mm256_mask_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepu16_epi32(src, 0, a);
@@ -47984,7 +49870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu16_epi32() {
+    const unsafe fn test_mm256_maskz_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu16_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -47994,7 +49880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu16_epi32() {
+    const unsafe fn test_mm_mask_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepu16_epi32(src, 0, a);
@@ -48005,7 +49891,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu16_epi32() {
+    const unsafe fn test_mm_maskz_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu16_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -48015,7 +49901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi32_ps() {
+    const unsafe fn test_mm512_cvtepi32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_ps(a);
         let e = _mm512_set_ps(
@@ -48025,7 +49911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_ps() {
+    const unsafe fn test_mm512_mask_cvtepi32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_ps(-1.);
         let r = _mm512_mask_cvtepi32_ps(src, 0, a);
@@ -48038,7 +49924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi32_ps() {
+    const unsafe fn test_mm512_maskz_cvtepi32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -48050,7 +49936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_ps() {
+    const unsafe fn test_mm256_mask_cvtepi32_ps() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm256_set1_ps(-1.);
         let r = _mm256_mask_cvtepi32_ps(src, 0, a);
@@ -48061,7 +49947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi32_ps() {
+    const unsafe fn test_mm256_maskz_cvtepi32_ps() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_cvtepi32_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -48071,7 +49957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_ps() {
+    const unsafe fn test_mm_mask_cvtepi32_ps() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let src = _mm_set1_ps(-1.);
         let r = _mm_mask_cvtepi32_ps(src, 0, a);
@@ -48082,7 +49968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi32_ps() {
+    const unsafe fn test_mm_maskz_cvtepi32_ps() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_cvtepi32_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -48092,7 +49978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu32_ps() {
+    const unsafe fn test_mm512_cvtepu32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32_ps(a);
         let e = _mm512_set_ps(
@@ -48102,7 +49988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu32_ps() {
+    const unsafe fn test_mm512_mask_cvtepu32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_ps(-1.);
         let r = _mm512_mask_cvtepu32_ps(src, 0, a);
@@ -48115,7 +50001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu32_ps() {
+    const unsafe fn test_mm512_maskz_cvtepu32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu32_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -48127,7 +50013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi32_epi16() {
+    const unsafe fn test_mm512_cvtepi32_epi16() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_epi16(a);
         let e = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -48135,7 +50021,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_epi16() {
+    const unsafe fn test_mm512_mask_cvtepi32_epi16() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi16(-1);
         let r = _mm512_mask_cvtepi32_epi16(src, 0, a);
@@ -48146,7 +50032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi32_epi16() {
+    const unsafe fn test_mm512_maskz_cvtepi32_epi16() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -48156,7 +50042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtepi32_epi16() {
+    const unsafe fn test_mm256_cvtepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_cvtepi32_epi16(a);
         let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
@@ -48164,7 +50050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_epi16() {
+    const unsafe fn test_mm256_mask_cvtepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm_set1_epi16(-1);
         let r = _mm256_mask_cvtepi32_epi16(src, 0, a);
@@ -48175,7 +50061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi32_epi16() {
+    const unsafe fn test_mm256_maskz_cvtepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_cvtepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -48214,7 +50100,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi32_epi8() {
+    const unsafe fn test_mm512_cvtepi32_epi8() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_epi8(a);
         let e = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -48222,7 +50108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_epi8() {
+    const unsafe fn test_mm512_mask_cvtepi32_epi8() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi8(-1);
         let r = _mm512_mask_cvtepi32_epi8(src, 0, a);
@@ -48233,7 +50119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi32_epi8() {
+    const unsafe fn test_mm512_maskz_cvtepi32_epi8() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49982,7 +51868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmplt_epu32_mask() {
+    const unsafe fn test_mm512_cmplt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -49992,7 +51878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmplt_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50003,7 +51889,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmplt_epu32_mask() {
+    const unsafe fn test_mm256_cmplt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 101, 100, 99);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmplt_epu32_mask(a, b);
@@ -50011,7 +51897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 101, 100, 99);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -50020,7 +51906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmplt_epu32_mask() {
+    const unsafe fn test_mm_cmplt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmplt_epu32_mask(a, b);
@@ -50028,7 +51914,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epu32_mask() {
+    const unsafe fn test_mm_mask_cmplt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -50037,7 +51923,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpgt_epu32_mask() {
+    const unsafe fn test_mm512_cmpgt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50047,7 +51933,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpgt_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50058,7 +51944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epu32_mask() {
+    const unsafe fn test_mm256_cmpgt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 99, 100, 101);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmpgt_epu32_mask(a, b);
@@ -50066,7 +51952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 99, 100, 101);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -50075,7 +51961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpgt_epu32_mask() {
+    const unsafe fn test_mm_cmpgt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmpgt_epu32_mask(a, b);
@@ -50083,7 +51969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epu32_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -50092,7 +51978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmple_epu32_mask() {
+    const unsafe fn test_mm512_cmple_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50104,7 +51990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmple_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmple_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50117,7 +52003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmple_epu32_mask() {
+    const unsafe fn test_mm256_cmple_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 200, 100, 101);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmple_epu32_mask(a, b);
@@ -50125,7 +52011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmple_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 200, 100, 101);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -50134,7 +52020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmple_epu32_mask() {
+    const unsafe fn test_mm_cmple_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmple_epu32_mask(a, b);
@@ -50142,7 +52028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epu32_mask() {
+    const unsafe fn test_mm_mask_cmple_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -50151,7 +52037,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpge_epu32_mask() {
+    const unsafe fn test_mm512_cmpge_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50163,7 +52049,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpge_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50173,7 +52059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpge_epu32_mask() {
+    const unsafe fn test_mm256_cmpge_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 300, 100, 200);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmpge_epu32_mask(a, b);
@@ -50181,7 +52067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 300, 100, 200);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -50190,7 +52076,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpge_epu32_mask() {
+    const unsafe fn test_mm_cmpge_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmpge_epu32_mask(a, b);
@@ -50198,7 +52084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epu32_mask() {
+    const unsafe fn test_mm_mask_cmpge_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -50207,7 +52093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpeq_epu32_mask() {
+    const unsafe fn test_mm512_cmpeq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50219,7 +52105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpeq_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50232,7 +52118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epu32_mask() {
+    const unsafe fn test_mm256_cmpeq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let m = _mm256_cmpeq_epu32_mask(b, a);
@@ -50240,7 +52126,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let mask = 0b01111010;
@@ -50249,7 +52135,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpeq_epu32_mask() {
+    const unsafe fn test_mm_cmpeq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let m = _mm_cmpeq_epu32_mask(b, a);
@@ -50257,7 +52143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epu32_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -50266,7 +52152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpneq_epu32_mask() {
+    const unsafe fn test_mm512_cmpneq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50278,7 +52164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpneq_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
@@ -50291,7 +52177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epu32_mask() {
+    const unsafe fn test_mm256_cmpneq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, -100, 100);
         let r = _mm256_cmpneq_epu32_mask(b, a);
@@ -50299,7 +52185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, -100, 100);
         let mask = 0b11111111;
@@ -50308,7 +52194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpneq_epu32_mask() {
+    const unsafe fn test_mm_cmpneq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let r = _mm_cmpneq_epu32_mask(b, a);
@@ -50316,7 +52202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epu32_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -50325,7 +52211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_epu32_mask() {
+    const unsafe fn test_mm512_cmp_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50335,7 +52221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_epu32_mask() {
+    const unsafe fn test_mm512_mask_cmp_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50346,7 +52232,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmp_epu32_mask() {
+    const unsafe fn test_mm256_cmp_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let m = _mm256_cmp_epu32_mask::<_MM_CMPINT_LT>(a, b);
@@ -50354,7 +52240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epu32_mask() {
+    const unsafe fn test_mm256_mask_cmp_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50363,7 +52249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmp_epu32_mask() {
+    const unsafe fn test_mm_cmp_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, i32::MAX);
         let b = _mm_set1_epi32(1);
         let m = _mm_cmp_epu32_mask::<_MM_CMPINT_LT>(a, b);
@@ -50371,7 +52257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epu32_mask() {
+    const unsafe fn test_mm_mask_cmp_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, i32::MAX);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -50380,7 +52266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmplt_epi32_mask() {
+    const unsafe fn test_mm512_cmplt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50390,7 +52276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmplt_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50401,7 +52287,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmplt_epi32_mask() {
+    const unsafe fn test_mm256_cmplt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 101, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmplt_epi32_mask(a, b);
@@ -50409,7 +52295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 101, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50418,7 +52304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmplt_epi32_mask() {
+    const unsafe fn test_mm_cmplt_epi32_mask() {
         let a = _mm_set_epi32(i32::MAX, i32::MIN, 100, -100);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmplt_epi32_mask(a, b);
@@ -50426,7 +52312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epi32_mask() {
+    const unsafe fn test_mm_mask_cmplt_epi32_mask() {
         let a = _mm_set_epi32(i32::MAX, i32::MIN, 100, -100);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50435,7 +52321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpgt_epi32_mask() {
+    const unsafe fn test_mm512_cmpgt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50445,7 +52331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpgt_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50456,7 +52342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epi32_mask() {
+    const unsafe fn test_mm256_cmpgt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmpgt_epi32_mask(a, b);
@@ -50464,7 +52350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50473,7 +52359,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpgt_epi32_mask() {
+    const unsafe fn test_mm_cmpgt_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmpgt_epi32_mask(a, b);
@@ -50481,7 +52367,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epi32_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50490,7 +52376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmple_epi32_mask() {
+    const unsafe fn test_mm512_cmple_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50502,7 +52388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmple_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmple_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50512,7 +52398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmple_epi32_mask() {
+    const unsafe fn test_mm256_cmple_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 200, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmple_epi32_mask(a, b);
@@ -50520,7 +52406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmple_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 200, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50529,7 +52415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmple_epi32_mask() {
+    const unsafe fn test_mm_cmple_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 200);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmple_epi32_mask(a, b);
@@ -50537,7 +52423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epi32_mask() {
+    const unsafe fn test_mm_mask_cmple_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 200);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50546,7 +52432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpge_epi32_mask() {
+    const unsafe fn test_mm512_cmpge_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50558,7 +52444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpge_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -50571,7 +52457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpge_epi32_mask() {
+    const unsafe fn test_mm256_cmpge_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmpge_epi32_mask(a, b);
@@ -50579,7 +52465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50588,7 +52474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpge_epi32_mask() {
+    const unsafe fn test_mm_cmpge_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmpge_epi32_mask(a, b);
@@ -50596,7 +52482,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epi32_mask() {
+    const unsafe fn test_mm_mask_cmpge_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -50605,7 +52491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpeq_epi32_mask() {
+    const unsafe fn test_mm512_cmpeq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50617,7 +52503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpeq_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50630,7 +52516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epi32_mask() {
+    const unsafe fn test_mm256_cmpeq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let m = _mm256_cmpeq_epi32_mask(b, a);
@@ -50638,7 +52524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let mask = 0b01111010;
@@ -50647,7 +52533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpeq_epi32_mask() {
+    const unsafe fn test_mm_cmpeq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let m = _mm_cmpeq_epi32_mask(b, a);
@@ -50655,7 +52541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epi32_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -50664,7 +52550,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpneq_epi32_mask() {
+    const unsafe fn test_mm512_cmpneq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50676,7 +52562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpneq_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100);
@@ -50689,7 +52575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epi32_mask() {
+    const unsafe fn test_mm256_cmpneq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let m = _mm256_cmpneq_epi32_mask(b, a);
@@ -50697,7 +52583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let mask = 0b11111111;
@@ -50706,7 +52592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpneq_epi32_mask() {
+    const unsafe fn test_mm_cmpneq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let r = _mm_cmpneq_epi32_mask(b, a);
@@ -50714,7 +52600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epi32_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -50723,7 +52609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_epi32_mask() {
+    const unsafe fn test_mm512_cmp_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50733,7 +52619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_epi32_mask() {
+    const unsafe fn test_mm512_mask_cmp_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -50744,7 +52630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmp_epi32_mask() {
+    const unsafe fn test_mm256_cmp_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let m = _mm256_cmp_epi32_mask::<_MM_CMPINT_LT>(a, b);
@@ -50752,7 +52638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epi32_mask() {
+    const unsafe fn test_mm256_mask_cmp_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b01100110;
@@ -50761,7 +52647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmp_epi32_mask() {
+    const unsafe fn test_mm_cmp_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(1);
         let m = _mm_cmp_epi32_mask::<_MM_CMPINT_LT>(a, b);
@@ -50769,7 +52655,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epi32_mask() {
+    const unsafe fn test_mm_mask_cmp_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -50778,7 +52664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set_epi8() {
+    const unsafe fn test_mm512_set_epi8() {
         let r = _mm512_set1_epi8(2);
         assert_eq_m512i(
             r,
@@ -50791,7 +52677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set_epi16() {
+    const unsafe fn test_mm512_set_epi16() {
         let r = _mm512_set1_epi16(2);
         assert_eq_m512i(
             r,
@@ -50803,7 +52689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set_epi32() {
+    const unsafe fn test_mm512_set_epi32() {
         let r = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         assert_eq_m512i(
             r,
@@ -50812,7 +52698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr_epi32() {
+    const unsafe fn test_mm512_setr_epi32() {
         let r = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         assert_eq_m512i(
             r,
@@ -50821,7 +52707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set1_epi8() {
+    const unsafe fn test_mm512_set1_epi8() {
         let r = _mm512_set_epi8(
             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
@@ -50831,7 +52717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set1_epi16() {
+    const unsafe fn test_mm512_set1_epi16() {
         let r = _mm512_set_epi16(
             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -50840,23 +52726,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set1_epi32() {
+    const unsafe fn test_mm512_set1_epi32() {
         let r = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         assert_eq_m512i(r, _mm512_set1_epi32(2));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setzero_si512() {
+    const unsafe fn test_mm512_setzero_si512() {
         assert_eq_m512i(_mm512_set1_epi32(0), _mm512_setzero_si512());
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setzero_epi32() {
+    const unsafe fn test_mm512_setzero_epi32() {
         assert_eq_m512i(_mm512_set1_epi32(0), _mm512_setzero_epi32());
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set_ps() {
+    const unsafe fn test_mm512_set_ps() {
         let r = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -50869,7 +52755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr_ps() {
+    const unsafe fn test_mm512_setr_ps() {
         let r = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -50882,7 +52768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set1_ps() {
+    const unsafe fn test_mm512_set1_ps() {
         #[rustfmt::skip]
         let expected = _mm512_set_ps(2., 2., 2., 2., 2., 2., 2., 2.,
                                      2., 2., 2., 2., 2., 2., 2., 2.);
@@ -50890,13 +52776,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set4_epi32() {
+    const unsafe fn test_mm512_set4_epi32() {
         let r = _mm512_set_epi32(4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_set4_epi32(4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set4_ps() {
+    const unsafe fn test_mm512_set4_ps() {
         let r = _mm512_set_ps(
             4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1.,
         );
@@ -50904,13 +52790,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr4_epi32() {
+    const unsafe fn test_mm512_setr4_epi32() {
         let r = _mm512_set_epi32(4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_setr4_epi32(1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr4_ps() {
+    const unsafe fn test_mm512_setr4_ps() {
         let r = _mm512_set_ps(
             4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1.,
         );
@@ -50918,17 +52804,17 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setzero_ps() {
+    const unsafe fn test_mm512_setzero_ps() {
         assert_eq_m512(_mm512_setzero_ps(), _mm512_set1_ps(0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setzero() {
+    const unsafe fn test_mm512_setzero() {
         assert_eq_m512(_mm512_setzero(), _mm512_set1_ps(0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_loadu_pd() {
+    const unsafe fn test_mm512_loadu_pd() {
         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
         let p = a.as_ptr();
         let r = _mm512_loadu_pd(black_box(p));
@@ -50937,7 +52823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_storeu_pd() {
+    const unsafe fn test_mm512_storeu_pd() {
         let a = _mm512_set1_pd(9.);
         let mut r = _mm512_undefined_pd();
         _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a);
@@ -50945,7 +52831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_loadu_ps() {
+    const unsafe fn test_mm512_loadu_ps() {
         let a = &[
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         ];
@@ -50958,7 +52844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_storeu_ps() {
+    const unsafe fn test_mm512_storeu_ps() {
         let a = _mm512_set1_ps(9.);
         let mut r = _mm512_undefined_ps();
         _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a);
@@ -50966,7 +52852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_loadu_epi32() {
+    const unsafe fn test_mm512_mask_loadu_epi32() {
         let src = _mm512_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
@@ -50977,7 +52863,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_loadu_epi32() {
+    const unsafe fn test_mm512_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
@@ -50987,7 +52873,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_load_epi32() {
+    const unsafe fn test_mm512_mask_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -51004,7 +52890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_load_epi32() {
+    const unsafe fn test_mm512_maskz_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -51020,7 +52906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_storeu_epi32() {
+    const unsafe fn test_mm512_mask_storeu_epi32() {
         let mut r = [42_i32; 16];
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let m = 0b11101000_11001010;
@@ -51030,7 +52916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_store_epi32() {
+    const unsafe fn test_mm512_mask_store_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16],
@@ -51044,7 +52930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_loadu_epi64() {
+    const unsafe fn test_mm512_mask_loadu_epi64() {
         let src = _mm512_set1_epi64(42);
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
@@ -51055,7 +52941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_loadu_epi64() {
+    const unsafe fn test_mm512_maskz_loadu_epi64() {
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
@@ -51065,7 +52951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_load_epi64() {
+    const unsafe fn test_mm512_mask_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -51082,7 +52968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_load_epi64() {
+    const unsafe fn test_mm512_maskz_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -51098,7 +52984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_storeu_epi64() {
+    const unsafe fn test_mm512_mask_storeu_epi64() {
         let mut r = [42_i64; 8];
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
@@ -51108,7 +52994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_store_epi64() {
+    const unsafe fn test_mm512_mask_store_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8],
@@ -51123,7 +53009,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_loadu_ps() {
+    const unsafe fn test_mm512_mask_loadu_ps() {
         let src = _mm512_set1_ps(42.0);
         let a = &[
             1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0,
@@ -51140,7 +53026,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_loadu_ps() {
+    const unsafe fn test_mm512_maskz_loadu_ps() {
         let a = &[
             1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0,
             16.0,
@@ -51155,7 +53041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_load_ps() {
+    const unsafe fn test_mm512_mask_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -51178,7 +53064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_load_ps() {
+    const unsafe fn test_mm512_maskz_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -51199,7 +53085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_storeu_ps() {
+    const unsafe fn test_mm512_mask_storeu_ps() {
         let mut r = [42_f32; 16];
         let a = _mm512_setr_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
@@ -51214,7 +53100,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_store_ps() {
+    const unsafe fn test_mm512_mask_store_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16],
@@ -51233,7 +53119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_loadu_pd() {
+    const unsafe fn test_mm512_mask_loadu_pd() {
         let src = _mm512_set1_pd(42.0);
         let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
@@ -51244,7 +53130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_loadu_pd() {
+    const unsafe fn test_mm512_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
@@ -51254,7 +53140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_load_pd() {
+    const unsafe fn test_mm512_mask_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -51271,7 +53157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_load_pd() {
+    const unsafe fn test_mm512_maskz_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -51287,7 +53173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_storeu_pd() {
+    const unsafe fn test_mm512_mask_storeu_pd() {
         let mut r = [42_f64; 8];
         let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
@@ -51297,7 +53183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_store_pd() {
+    const unsafe fn test_mm512_mask_store_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8],
@@ -51311,7 +53197,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_loadu_epi32() {
+    const unsafe fn test_mm256_mask_loadu_epi32() {
         let src = _mm256_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
@@ -51322,7 +53208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_loadu_epi32() {
+    const unsafe fn test_mm256_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
@@ -51332,7 +53218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_load_epi32() {
+    const unsafe fn test_mm256_mask_load_epi32() {
         #[repr(align(32))]
         struct Align {
             data: [i32; 8], // 32 bytes
@@ -51349,7 +53235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_load_epi32() {
+    const unsafe fn test_mm256_maskz_load_epi32() {
         #[repr(align(32))]
         struct Align {
             data: [i32; 8], // 32 bytes
@@ -51365,7 +53251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_storeu_epi32() {
+    const unsafe fn test_mm256_mask_storeu_epi32() {
         let mut r = [42_i32; 8];
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
@@ -51375,7 +53261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_store_epi32() {
+    const unsafe fn test_mm256_mask_store_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 8],
@@ -51389,7 +53275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_loadu_epi64() {
+    const unsafe fn test_mm256_mask_loadu_epi64() {
         let src = _mm256_set1_epi64x(42);
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
@@ -51400,7 +53286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_loadu_epi64() {
+    const unsafe fn test_mm256_maskz_loadu_epi64() {
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
@@ -51410,7 +53296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_load_epi64() {
+    const unsafe fn test_mm256_mask_load_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4], // 32 bytes
@@ -51427,7 +53313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_load_epi64() {
+    const unsafe fn test_mm256_maskz_load_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4], // 32 bytes
@@ -51443,7 +53329,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_storeu_epi64() {
+    const unsafe fn test_mm256_mask_storeu_epi64() {
         let mut r = [42_i64; 4];
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let m = 0b1010;
@@ -51453,7 +53339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_store_epi64() {
+    const unsafe fn test_mm256_mask_store_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4],
@@ -51467,7 +53353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_loadu_ps() {
+    const unsafe fn test_mm256_mask_loadu_ps() {
         let src = _mm256_set1_ps(42.0);
         let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
@@ -51478,7 +53364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_loadu_ps() {
+    const unsafe fn test_mm256_maskz_loadu_ps() {
         let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
@@ -51488,7 +53374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_load_ps() {
+    const unsafe fn test_mm256_mask_load_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8], // 32 bytes
@@ -51505,7 +53391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_load_ps() {
+    const unsafe fn test_mm256_maskz_load_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8], // 32 bytes
@@ -51521,7 +53407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_storeu_ps() {
+    const unsafe fn test_mm256_mask_storeu_ps() {
         let mut r = [42_f32; 8];
         let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
@@ -51531,7 +53417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_store_ps() {
+    const unsafe fn test_mm256_mask_store_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8],
@@ -51545,7 +53431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_loadu_pd() {
+    const unsafe fn test_mm256_mask_loadu_pd() {
         let src = _mm256_set1_pd(42.0);
         let a = &[1.0_f64, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
@@ -51556,7 +53442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_loadu_pd() {
+    const unsafe fn test_mm256_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
@@ -51566,7 +53452,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_load_pd() {
+    const unsafe fn test_mm256_mask_load_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4], // 32 bytes
@@ -51583,7 +53469,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_load_pd() {
+    const unsafe fn test_mm256_maskz_load_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4], // 32 bytes
@@ -51599,7 +53485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_storeu_pd() {
+    const unsafe fn test_mm256_mask_storeu_pd() {
         let mut r = [42_f64; 4];
         let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
@@ -51609,7 +53495,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_store_pd() {
+    const unsafe fn test_mm256_mask_store_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4],
@@ -51623,7 +53509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_loadu_epi32() {
+    const unsafe fn test_mm_mask_loadu_epi32() {
         let src = _mm_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
@@ -51634,7 +53520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_loadu_epi32() {
+    const unsafe fn test_mm_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
@@ -51644,7 +53530,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_load_epi32() {
+    const unsafe fn test_mm_mask_load_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 32 bytes
@@ -51661,7 +53547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_load_epi32() {
+    const unsafe fn test_mm_maskz_load_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 16 bytes
@@ -51677,7 +53563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_storeu_epi32() {
+    const unsafe fn test_mm_mask_storeu_epi32() {
         let mut r = [42_i32; 4];
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let m = 0b1010;
@@ -51687,7 +53573,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_store_epi32() {
+    const unsafe fn test_mm_mask_store_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 16 bytes
@@ -51701,7 +53587,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_loadu_epi64() {
+    const unsafe fn test_mm_mask_loadu_epi64() {
         let src = _mm_set1_epi64x(42);
         let a = &[1_i64, 2];
         let p = a.as_ptr();
@@ -51712,7 +53598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_loadu_epi64() {
+    const unsafe fn test_mm_maskz_loadu_epi64() {
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b10;
@@ -51722,7 +53608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_load_epi64() {
+    const unsafe fn test_mm_mask_load_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -51737,7 +53623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_load_epi64() {
+    const unsafe fn test_mm_maskz_load_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -51751,7 +53637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_storeu_epi64() {
+    const unsafe fn test_mm_mask_storeu_epi64() {
         let mut r = [42_i64; 2];
         let a = _mm_setr_epi64x(1, 2);
         let m = 0b10;
@@ -51761,7 +53647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_store_epi64() {
+    const unsafe fn test_mm_mask_store_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -51775,7 +53661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_loadu_ps() {
+    const unsafe fn test_mm_mask_loadu_ps() {
         let src = _mm_set1_ps(42.0);
         let a = &[1.0_f32, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
@@ -51786,7 +53672,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_loadu_ps() {
+    const unsafe fn test_mm_maskz_loadu_ps() {
         let a = &[1.0_f32, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
@@ -51796,7 +53682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_load_ps() {
+    const unsafe fn test_mm_mask_load_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -51813,7 +53699,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_load_ps() {
+    const unsafe fn test_mm_maskz_load_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -51829,7 +53715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_storeu_ps() {
+    const unsafe fn test_mm_mask_storeu_ps() {
         let mut r = [42_f32; 4];
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
@@ -51839,7 +53725,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_store_ps() {
+    const unsafe fn test_mm_mask_store_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -51853,7 +53739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_loadu_pd() {
+    const unsafe fn test_mm_mask_loadu_pd() {
         let src = _mm_set1_pd(42.0);
         let a = &[1.0_f64, 2.0];
         let p = a.as_ptr();
@@ -51864,7 +53750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_loadu_pd() {
+    const unsafe fn test_mm_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0];
         let p = a.as_ptr();
         let m = 0b10;
@@ -51874,7 +53760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_load_pd() {
+    const unsafe fn test_mm_mask_load_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -51891,7 +53777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_load_pd() {
+    const unsafe fn test_mm_maskz_load_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -51961,7 +53847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_storeu_pd() {
+    const unsafe fn test_mm_mask_storeu_pd() {
         let mut r = [42_f64; 2];
         let a = _mm_setr_pd(1.0, 2.0);
         let m = 0b10;
@@ -51971,7 +53857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_store_pd() {
+    const unsafe fn test_mm_mask_store_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -52013,19 +53899,19 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr_pd() {
+    const unsafe fn test_mm512_setr_pd() {
         let r = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         assert_eq_m512d(r, _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set_pd() {
+    const unsafe fn test_mm512_set_pd() {
         let r = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         assert_eq_m512d(r, _mm512_set_pd(7., 6., 5., 4., 3., 2., 1., 0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rol_epi32() {
+    const unsafe fn test_mm512_rol_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_rol_epi32::<1>(a);
         let e = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
@@ -52033,7 +53919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rol_epi32() {
+    const unsafe fn test_mm512_mask_rol_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_mask_rol_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -52043,7 +53929,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rol_epi32() {
+    const unsafe fn test_mm512_maskz_rol_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let r = _mm512_maskz_rol_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -52053,7 +53939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rol_epi32() {
+    const unsafe fn test_mm256_rol_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_rol_epi32::<1>(a);
         let e = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
@@ -52061,7 +53947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rol_epi32() {
+    const unsafe fn test_mm256_mask_rol_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_mask_rol_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -52071,7 +53957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rol_epi32() {
+    const unsafe fn test_mm256_maskz_rol_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_maskz_rol_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -52081,7 +53967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rol_epi32() {
+    const unsafe fn test_mm_rol_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_rol_epi32::<1>(a);
         let e = _mm_set_epi32(1 << 0, 2, 2, 2);
@@ -52089,7 +53975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rol_epi32() {
+    const unsafe fn test_mm_mask_rol_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_mask_rol_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -52099,7 +53985,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rol_epi32() {
+    const unsafe fn test_mm_maskz_rol_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_maskz_rol_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -52109,7 +53995,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_ror_epi32() {
+    const unsafe fn test_mm512_ror_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_ror_epi32::<1>(a);
         let e = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
@@ -52117,7 +54003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_ror_epi32() {
+    const unsafe fn test_mm512_mask_ror_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_mask_ror_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -52127,7 +54013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_ror_epi32() {
+    const unsafe fn test_mm512_maskz_ror_epi32() {
         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
         let r = _mm512_maskz_ror_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -52137,7 +54023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_ror_epi32() {
+    const unsafe fn test_mm256_ror_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm256_ror_epi32::<1>(a);
         let e = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
@@ -52145,7 +54031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_ror_epi32() {
+    const unsafe fn test_mm256_mask_ror_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm256_mask_ror_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -52155,7 +54041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_ror_epi32() {
+    const unsafe fn test_mm256_maskz_ror_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm256_maskz_ror_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -52165,7 +54051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_ror_epi32() {
+    const unsafe fn test_mm_ror_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let r = _mm_ror_epi32::<1>(a);
         let e = _mm_set_epi32(1 << 31, 1, 1, 1);
@@ -52173,7 +54059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_ror_epi32() {
+    const unsafe fn test_mm_mask_ror_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let r = _mm_mask_ror_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -52183,7 +54069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_ror_epi32() {
+    const unsafe fn test_mm_maskz_ror_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let r = _mm_maskz_ror_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -52193,7 +54079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_slli_epi32() {
+    const unsafe fn test_mm512_slli_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_slli_epi32::<1>(a);
         let e = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
@@ -52201,7 +54087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_slli_epi32() {
+    const unsafe fn test_mm512_mask_slli_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_mask_slli_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -52211,7 +54097,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_slli_epi32() {
+    const unsafe fn test_mm512_maskz_slli_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let r = _mm512_maskz_slli_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -52221,7 +54107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_slli_epi32() {
+    const unsafe fn test_mm256_mask_slli_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_mask_slli_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -52231,7 +54117,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_slli_epi32() {
+    const unsafe fn test_mm256_maskz_slli_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_maskz_slli_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -52241,7 +54127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_slli_epi32() {
+    const unsafe fn test_mm_mask_slli_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_mask_slli_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -52251,7 +54137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_slli_epi32() {
+    const unsafe fn test_mm_maskz_slli_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_maskz_slli_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -52261,7 +54147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srli_epi32() {
+    const unsafe fn test_mm512_srli_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_srli_epi32::<1>(a);
         let e = _mm512_set_epi32(0 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
@@ -52269,7 +54155,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srli_epi32() {
+    const unsafe fn test_mm512_mask_srli_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_mask_srli_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -52279,7 +54165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srli_epi32() {
+    const unsafe fn test_mm512_maskz_srli_epi32() {
         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
         let r = _mm512_maskz_srli_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -52289,7 +54175,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srli_epi32() {
+    const unsafe fn test_mm256_mask_srli_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_mask_srli_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -52299,7 +54185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srli_epi32() {
+    const unsafe fn test_mm256_maskz_srli_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_maskz_srli_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -52309,7 +54195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srli_epi32() {
+    const unsafe fn test_mm_mask_srli_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_mask_srli_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -52319,7 +54205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srli_epi32() {
+    const unsafe fn test_mm_maskz_srli_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_maskz_srli_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -52329,7 +54215,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rolv_epi32() {
+    const unsafe fn test_mm512_rolv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_rolv_epi32(a, b);
@@ -52338,7 +54224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rolv_epi32() {
+    const unsafe fn test_mm512_mask_rolv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_mask_rolv_epi32(a, 0, a, b);
@@ -52349,7 +54235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rolv_epi32() {
+    const unsafe fn test_mm512_maskz_rolv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_rolv_epi32(0, a, b);
@@ -52360,7 +54246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rolv_epi32() {
+    const unsafe fn test_mm256_rolv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_rolv_epi32(a, b);
@@ -52369,7 +54255,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rolv_epi32() {
+    const unsafe fn test_mm256_mask_rolv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_rolv_epi32(a, 0, a, b);
@@ -52380,7 +54266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rolv_epi32() {
+    const unsafe fn test_mm256_maskz_rolv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_rolv_epi32(0, a, b);
@@ -52391,7 +54277,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rolv_epi32() {
+    const unsafe fn test_mm_rolv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let b = _mm_set1_epi32(1);
         let r = _mm_rolv_epi32(a, b);
@@ -52400,7 +54286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rolv_epi32() {
+    const unsafe fn test_mm_mask_rolv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_rolv_epi32(a, 0, a, b);
@@ -52411,7 +54297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rolv_epi32() {
+    const unsafe fn test_mm_maskz_rolv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_rolv_epi32(0, a, b);
@@ -52422,7 +54308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rorv_epi32() {
+    const unsafe fn test_mm512_rorv_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_rorv_epi32(a, b);
@@ -52431,7 +54317,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rorv_epi32() {
+    const unsafe fn test_mm512_mask_rorv_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_mask_rorv_epi32(a, 0, a, b);
@@ -52442,7 +54328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rorv_epi32() {
+    const unsafe fn test_mm512_maskz_rorv_epi32() {
         let a = _mm512_set_epi32(3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_rorv_epi32(0, a, b);
@@ -52453,7 +54339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rorv_epi32() {
+    const unsafe fn test_mm256_rorv_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_rorv_epi32(a, b);
@@ -52462,7 +54348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rorv_epi32() {
+    const unsafe fn test_mm256_mask_rorv_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_rorv_epi32(a, 0, a, b);
@@ -52473,7 +54359,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rorv_epi32() {
+    const unsafe fn test_mm256_maskz_rorv_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_rorv_epi32(0, a, b);
@@ -52484,7 +54370,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rorv_epi32() {
+    const unsafe fn test_mm_rorv_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let b = _mm_set1_epi32(1);
         let r = _mm_rorv_epi32(a, b);
@@ -52493,7 +54379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rorv_epi32() {
+    const unsafe fn test_mm_mask_rorv_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_rorv_epi32(a, 0, a, b);
@@ -52504,7 +54390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rorv_epi32() {
+    const unsafe fn test_mm_maskz_rorv_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_rorv_epi32(0, a, b);
@@ -52515,7 +54401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sllv_epi32() {
+    const unsafe fn test_mm512_sllv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_sllv_epi32(a, count);
@@ -52524,7 +54410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sllv_epi32() {
+    const unsafe fn test_mm512_mask_sllv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_mask_sllv_epi32(a, 0, a, count);
@@ -52535,7 +54421,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sllv_epi32() {
+    const unsafe fn test_mm512_maskz_sllv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_maskz_sllv_epi32(0, a, count);
@@ -52546,7 +54432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sllv_epi32() {
+    const unsafe fn test_mm256_mask_sllv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_mask_sllv_epi32(a, 0, a, count);
@@ -52557,7 +54443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sllv_epi32() {
+    const unsafe fn test_mm256_maskz_sllv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_maskz_sllv_epi32(0, a, count);
@@ -52568,7 +54454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sllv_epi32() {
+    const unsafe fn test_mm_mask_sllv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let count = _mm_set1_epi32(1);
         let r = _mm_mask_sllv_epi32(a, 0, a, count);
@@ -52579,7 +54465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sllv_epi32() {
+    const unsafe fn test_mm_maskz_sllv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let count = _mm_set1_epi32(1);
         let r = _mm_maskz_sllv_epi32(0, a, count);
@@ -52590,7 +54476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srlv_epi32() {
+    const unsafe fn test_mm512_srlv_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_srlv_epi32(a, count);
@@ -52599,7 +54485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srlv_epi32() {
+    const unsafe fn test_mm512_mask_srlv_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_mask_srlv_epi32(a, 0, a, count);
@@ -52610,7 +54496,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srlv_epi32() {
+    const unsafe fn test_mm512_maskz_srlv_epi32() {
         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
         let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_maskz_srlv_epi32(0, a, count);
@@ -52621,7 +54507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srlv_epi32() {
+    const unsafe fn test_mm256_mask_srlv_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_mask_srlv_epi32(a, 0, a, count);
@@ -52632,7 +54518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srlv_epi32() {
+    const unsafe fn test_mm256_maskz_srlv_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_maskz_srlv_epi32(0, a, count);
@@ -52643,7 +54529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srlv_epi32() {
+    const unsafe fn test_mm_mask_srlv_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_mask_srlv_epi32(a, 0, a, count);
@@ -52654,7 +54540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srlv_epi32() {
+    const unsafe fn test_mm_maskz_srlv_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_maskz_srlv_epi32(0, a, count);
@@ -52938,7 +54824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srav_epi32() {
+    const unsafe fn test_mm512_srav_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm512_srav_epi32(a, count);
@@ -52947,7 +54833,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srav_epi32() {
+    const unsafe fn test_mm512_mask_srav_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16);
         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
         let r = _mm512_mask_srav_epi32(a, 0, a, count);
@@ -52958,7 +54844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srav_epi32() {
+    const unsafe fn test_mm512_maskz_srav_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -15, -14);
         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2);
         let r = _mm512_maskz_srav_epi32(0, a, count);
@@ -52969,7 +54855,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srav_epi32() {
+    const unsafe fn test_mm256_mask_srav_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_mask_srav_epi32(a, 0, a, count);
@@ -52980,7 +54866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srav_epi32() {
+    const unsafe fn test_mm256_maskz_srav_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_maskz_srav_epi32(0, a, count);
@@ -52991,7 +54877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srav_epi32() {
+    const unsafe fn test_mm_mask_srav_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_mask_srav_epi32(a, 0, a, count);
@@ -53002,7 +54888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srav_epi32() {
+    const unsafe fn test_mm_maskz_srav_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_maskz_srav_epi32(0, a, count);
@@ -53013,7 +54899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srai_epi32() {
+    const unsafe fn test_mm512_srai_epi32() {
         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, -15);
         let r = _mm512_srai_epi32::<2>(a);
         let e = _mm512_set_epi32(2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, -4);
@@ -53021,7 +54907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srai_epi32() {
+    const unsafe fn test_mm512_mask_srai_epi32() {
         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, -15);
         let r = _mm512_mask_srai_epi32::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -53031,7 +54917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srai_epi32() {
+    const unsafe fn test_mm512_maskz_srai_epi32() {
         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, -15);
         let r = _mm512_maskz_srai_epi32::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -53041,7 +54927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srai_epi32() {
+    const unsafe fn test_mm256_mask_srai_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_mask_srai_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -53051,7 +54937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srai_epi32() {
+    const unsafe fn test_mm256_maskz_srai_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_maskz_srai_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -53061,7 +54947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srai_epi32() {
+    const unsafe fn test_mm_mask_srai_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_mask_srai_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -53071,7 +54957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srai_epi32() {
+    const unsafe fn test_mm_maskz_srai_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_maskz_srai_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -53081,7 +54967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permute_ps() {
+    const unsafe fn test_mm512_permute_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -53093,7 +54979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permute_ps() {
+    const unsafe fn test_mm512_mask_permute_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -53107,7 +54993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permute_ps() {
+    const unsafe fn test_mm512_maskz_permute_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -53121,7 +55007,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permute_ps() {
+    const unsafe fn test_mm256_mask_permute_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_mask_permute_ps::<0b11_11_11_11>(a, 0, a);
         assert_eq_m256(r, a);
@@ -53131,7 +55017,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permute_ps() {
+    const unsafe fn test_mm256_maskz_permute_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_maskz_permute_ps::<0b11_11_11_11>(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -53141,7 +55027,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permute_ps() {
+    const unsafe fn test_mm_mask_permute_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_mask_permute_ps::<0b11_11_11_11>(a, 0, a);
         assert_eq_m128(r, a);
@@ -53151,7 +55037,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permute_ps() {
+    const unsafe fn test_mm_maskz_permute_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_maskz_permute_ps::<0b11_11_11_11>(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -53750,7 +55636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_epi32() {
+    const unsafe fn test_mm512_shuffle_epi32() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm512_shuffle_epi32::<_MM_PERM_AADD>(a);
         let e = _mm512_setr_epi32(8, 8, 1, 1, 16, 16, 9, 9, 8, 8, 1, 1, 16, 16, 9, 9);
@@ -53758,7 +55644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_epi32() {
+    const unsafe fn test_mm512_mask_shuffle_epi32() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm512_mask_shuffle_epi32::<_MM_PERM_AADD>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -53768,7 +55654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_epi32() {
+    const unsafe fn test_mm512_maskz_shuffle_epi32() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm512_maskz_shuffle_epi32::<_MM_PERM_AADD>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -53778,7 +55664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_epi32() {
+    const unsafe fn test_mm256_mask_shuffle_epi32() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm256_mask_shuffle_epi32::<_MM_PERM_AADD>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -53788,7 +55674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_epi32() {
+    const unsafe fn test_mm256_maskz_shuffle_epi32() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm256_maskz_shuffle_epi32::<_MM_PERM_AADD>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -53798,7 +55684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_shuffle_epi32() {
+    const unsafe fn test_mm_mask_shuffle_epi32() {
         let a = _mm_set_epi32(1, 4, 5, 8);
         let r = _mm_mask_shuffle_epi32::<_MM_PERM_AADD>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -53808,7 +55694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_shuffle_epi32() {
+    const unsafe fn test_mm_maskz_shuffle_epi32() {
         let a = _mm_set_epi32(1, 4, 5, 8);
         let r = _mm_maskz_shuffle_epi32::<_MM_PERM_AADD>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -53818,7 +55704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_ps() {
+    const unsafe fn test_mm512_shuffle_ps() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -53833,7 +55719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_ps() {
+    const unsafe fn test_mm512_mask_shuffle_ps() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -53850,7 +55736,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_ps() {
+    const unsafe fn test_mm512_maskz_shuffle_ps() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -53867,7 +55753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_ps() {
+    const unsafe fn test_mm256_mask_shuffle_ps() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_mask_shuffle_ps::<0b11_11_11_11>(a, 0, a, b);
@@ -53878,7 +55764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_ps() {
+    const unsafe fn test_mm256_maskz_shuffle_ps() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_maskz_shuffle_ps::<0b11_11_11_11>(0, a, b);
@@ -53889,7 +55775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_shuffle_ps() {
+    const unsafe fn test_mm_mask_shuffle_ps() {
         let a = _mm_set_ps(1., 4., 5., 8.);
         let b = _mm_set_ps(2., 3., 6., 7.);
         let r = _mm_mask_shuffle_ps::<0b11_11_11_11>(a, 0, a, b);
@@ -53900,7 +55786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_shuffle_ps() {
+    const unsafe fn test_mm_maskz_shuffle_ps() {
         let a = _mm_set_ps(1., 4., 5., 8.);
         let b = _mm_set_ps(2., 3., 6., 7.);
         let r = _mm_maskz_shuffle_ps::<0b11_11_11_11>(0, a, b);
@@ -53911,7 +55797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_i32x4() {
+    const unsafe fn test_mm512_shuffle_i32x4() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_shuffle_i32x4::<0b00_00_00_00>(a, b);
@@ -53920,7 +55806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_i32x4() {
+    const unsafe fn test_mm512_mask_shuffle_i32x4() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_mask_shuffle_i32x4::<0b00_00_00_00>(a, 0, a, b);
@@ -53931,7 +55817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_i32x4() {
+    const unsafe fn test_mm512_maskz_shuffle_i32x4() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_maskz_shuffle_i32x4::<0b00_00_00_00>(0, a, b);
@@ -53942,7 +55828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_shuffle_i32x4() {
+    const unsafe fn test_mm256_shuffle_i32x4() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm256_set_epi32(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm256_shuffle_i32x4::<0b00>(a, b);
@@ -53951,7 +55837,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_i32x4() {
+    const unsafe fn test_mm256_mask_shuffle_i32x4() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm256_set_epi32(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm256_mask_shuffle_i32x4::<0b00>(a, 0, a, b);
@@ -53962,7 +55848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_i32x4() {
+    const unsafe fn test_mm256_maskz_shuffle_i32x4() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm256_set_epi32(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm256_maskz_shuffle_i32x4::<0b00>(0, a, b);
@@ -53973,7 +55859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_f32x4() {
+    const unsafe fn test_mm512_shuffle_f32x4() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -53988,7 +55874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_f32x4() {
+    const unsafe fn test_mm512_mask_shuffle_f32x4() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -54005,7 +55891,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_f32x4() {
+    const unsafe fn test_mm512_maskz_shuffle_f32x4() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -54022,7 +55908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_shuffle_f32x4() {
+    const unsafe fn test_mm256_shuffle_f32x4() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_shuffle_f32x4::<0b00>(a, b);
@@ -54031,7 +55917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_f32x4() {
+    const unsafe fn test_mm256_mask_shuffle_f32x4() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_mask_shuffle_f32x4::<0b00>(a, 0, a, b);
@@ -54042,7 +55928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_f32x4() {
+    const unsafe fn test_mm256_maskz_shuffle_f32x4() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_maskz_shuffle_f32x4::<0b00>(0, a, b);
@@ -54053,7 +55939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_extractf32x4_ps() {
+    const unsafe fn test_mm512_extractf32x4_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54063,7 +55949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_extractf32x4_ps() {
+    const unsafe fn test_mm512_mask_extractf32x4_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54076,7 +55962,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_extractf32x4_ps() {
+    const unsafe fn test_mm512_maskz_extractf32x4_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54088,7 +55974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_extractf32x4_ps() {
+    const unsafe fn test_mm256_extractf32x4_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_extractf32x4_ps::<1>(a);
         let e = _mm_set_ps(1., 2., 3., 4.);
@@ -54096,7 +55982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_extractf32x4_ps() {
+    const unsafe fn test_mm256_mask_extractf32x4_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let src = _mm_set1_ps(100.);
         let r = _mm256_mask_extractf32x4_ps::<1>(src, 0, a);
@@ -54107,7 +55993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_extractf32x4_ps() {
+    const unsafe fn test_mm256_maskz_extractf32x4_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_maskz_extractf32x4_ps::<1>(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -54117,7 +56003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_extracti32x4_epi32() {
+    const unsafe fn test_mm512_extracti32x4_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_extracti32x4_epi32::<1>(a);
         let e = _mm_setr_epi32(5, 6, 7, 8);
@@ -54125,7 +56011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_extracti32x4_epi32() {
+    const unsafe fn test_mm512_mask_extracti32x4_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm_set1_epi32(100);
         let r = _mm512_mask_extracti32x4_epi32::<1>(src, 0, a);
@@ -54136,7 +56022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm512_maskz_extracti32x4_epi32() {
+    const unsafe fn test_mm512_maskz_extracti32x4_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_extracti32x4_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54146,7 +56032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_extracti32x4_epi32() {
+    const unsafe fn test_mm256_extracti32x4_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_extracti32x4_epi32::<1>(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -54154,7 +56040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_extracti32x4_epi32() {
+    const unsafe fn test_mm256_mask_extracti32x4_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set1_epi32(100);
         let r = _mm256_mask_extracti32x4_epi32::<1>(src, 0, a);
@@ -54165,7 +56051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_extracti32x4_epi32() {
+    const unsafe fn test_mm256_maskz_extracti32x4_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_extracti32x4_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54175,7 +56061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_moveldup_ps() {
+    const unsafe fn test_mm512_moveldup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54187,7 +56073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_moveldup_ps() {
+    const unsafe fn test_mm512_mask_moveldup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54201,7 +56087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_moveldup_ps() {
+    const unsafe fn test_mm512_maskz_moveldup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54215,7 +56101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_moveldup_ps() {
+    const unsafe fn test_mm256_mask_moveldup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_mask_moveldup_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -54225,7 +56111,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_moveldup_ps() {
+    const unsafe fn test_mm256_maskz_moveldup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_maskz_moveldup_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -54235,7 +56121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_moveldup_ps() {
+    const unsafe fn test_mm_mask_moveldup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_mask_moveldup_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -54245,7 +56131,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_moveldup_ps() {
+    const unsafe fn test_mm_maskz_moveldup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_moveldup_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -54255,7 +56141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_movehdup_ps() {
+    const unsafe fn test_mm512_movehdup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54267,7 +56153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_movehdup_ps() {
+    const unsafe fn test_mm512_mask_movehdup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54281,7 +56167,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_movehdup_ps() {
+    const unsafe fn test_mm512_maskz_movehdup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54295,7 +56181,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_movehdup_ps() {
+    const unsafe fn test_mm256_mask_movehdup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_mask_movehdup_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -54305,7 +56191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_movehdup_ps() {
+    const unsafe fn test_mm256_maskz_movehdup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_maskz_movehdup_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -54315,7 +56201,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_movehdup_ps() {
+    const unsafe fn test_mm_mask_movehdup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_mask_movehdup_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -54325,7 +56211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_movehdup_ps() {
+    const unsafe fn test_mm_maskz_movehdup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_movehdup_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -54335,7 +56221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_inserti32x4() {
+    const unsafe fn test_mm512_inserti32x4() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_setr_epi32(17, 18, 19, 20);
         let r = _mm512_inserti32x4::<0>(a, b);
@@ -54344,7 +56230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_inserti32x4() {
+    const unsafe fn test_mm512_mask_inserti32x4() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_setr_epi32(17, 18, 19, 20);
         let r = _mm512_mask_inserti32x4::<0>(a, 0, a, b);
@@ -54355,7 +56241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_inserti32x4() {
+    const unsafe fn test_mm512_maskz_inserti32x4() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_setr_epi32(17, 18, 19, 20);
         let r = _mm512_maskz_inserti32x4::<0>(0, a, b);
@@ -54366,7 +56252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_inserti32x4() {
+    const unsafe fn test_mm256_inserti32x4() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_inserti32x4::<1>(a, b);
@@ -54375,7 +56261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_inserti32x4() {
+    const unsafe fn test_mm256_mask_inserti32x4() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_mask_inserti32x4::<0>(a, 0, a, b);
@@ -54386,7 +56272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_inserti32x4() {
+    const unsafe fn test_mm256_maskz_inserti32x4() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_maskz_inserti32x4::<0>(0, a, b);
@@ -54397,7 +56283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_insertf32x4() {
+    const unsafe fn test_mm512_insertf32x4() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54410,7 +56296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_insertf32x4() {
+    const unsafe fn test_mm512_mask_insertf32x4() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54425,7 +56311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_insertf32x4() {
+    const unsafe fn test_mm512_maskz_insertf32x4() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54440,7 +56326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_insertf32x4() {
+    const unsafe fn test_mm256_insertf32x4() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_insertf32x4::<1>(a, b);
@@ -54449,7 +56335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_insertf32x4() {
+    const unsafe fn test_mm256_mask_insertf32x4() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_mask_insertf32x4::<0>(a, 0, a, b);
@@ -54460,7 +56346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_insertf32x4() {
+    const unsafe fn test_mm256_maskz_insertf32x4() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_maskz_insertf32x4::<0>(0, a, b);
@@ -54471,21 +56357,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castps128_ps512() {
+    const unsafe fn test_mm512_castps128_ps512() {
         let a = _mm_setr_ps(17., 18., 19., 20.);
         let r = _mm512_castps128_ps512(a);
         assert_eq_m128(_mm512_castps512_ps128(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castps256_ps512() {
+    const unsafe fn test_mm512_castps256_ps512() {
         let a = _mm256_setr_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_castps256_ps512(a);
         assert_eq_m256(_mm512_castps512_ps256(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_zextps128_ps512() {
+    const unsafe fn test_mm512_zextps128_ps512() {
         let a = _mm_setr_ps(17., 18., 19., 20.);
         let r = _mm512_zextps128_ps512(a);
         let e = _mm512_setr_ps(
@@ -54495,7 +56381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_zextps256_ps512() {
+    const unsafe fn test_mm512_zextps256_ps512() {
         let a = _mm256_setr_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_zextps256_ps512(a);
         let e = _mm512_setr_ps(
@@ -54505,7 +56391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castps512_ps128() {
+    const unsafe fn test_mm512_castps512_ps128() {
         let a = _mm512_setr_ps(
             17., 18., 19., 20., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1.,
         );
@@ -54515,7 +56401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castps512_ps256() {
+    const unsafe fn test_mm512_castps512_ps256() {
         let a = _mm512_setr_ps(
             17., 18., 19., 20., 21., 22., 23., 24., -1., -1., -1., -1., -1., -1., -1., -1.,
         );
@@ -54525,7 +56411,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castps_pd() {
+    const unsafe fn test_mm512_castps_pd() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_castps_pd(a);
         let e = _mm512_set1_pd(0.007812501848093234);
@@ -54533,7 +56419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castps_si512() {
+    const unsafe fn test_mm512_castps_si512() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_castps_si512(a);
         let e = _mm512_set1_epi32(1065353216);
@@ -54541,7 +56427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcastd_epi32() {
+    const unsafe fn test_mm512_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_broadcastd_epi32(a);
         let e = _mm512_set1_epi32(20);
@@ -54549,7 +56435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcastd_epi32() {
+    const unsafe fn test_mm512_mask_broadcastd_epi32() {
         let src = _mm512_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_mask_broadcastd_epi32(src, 0, a);
@@ -54560,7 +56446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcastd_epi32() {
+    const unsafe fn test_mm512_maskz_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_maskz_broadcastd_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -54570,7 +56456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_broadcastd_epi32() {
+    const unsafe fn test_mm256_mask_broadcastd_epi32() {
         let src = _mm256_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_mask_broadcastd_epi32(src, 0, a);
@@ -54581,7 +56467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcastd_epi32() {
+    const unsafe fn test_mm256_maskz_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_maskz_broadcastd_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -54591,7 +56477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_broadcastd_epi32() {
+    const unsafe fn test_mm_mask_broadcastd_epi32() {
         let src = _mm_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_mask_broadcastd_epi32(src, 0, a);
@@ -54602,7 +56488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_broadcastd_epi32() {
+    const unsafe fn test_mm_maskz_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_maskz_broadcastd_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54612,7 +56498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcastss_ps() {
+    const unsafe fn test_mm512_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_broadcastss_ps(a);
         let e = _mm512_set1_ps(20.);
@@ -54620,7 +56506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcastss_ps() {
+    const unsafe fn test_mm512_mask_broadcastss_ps() {
         let src = _mm512_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_mask_broadcastss_ps(src, 0, a);
@@ -54631,7 +56517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcastss_ps() {
+    const unsafe fn test_mm512_maskz_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_maskz_broadcastss_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -54643,7 +56529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_broadcastss_ps() {
+    const unsafe fn test_mm256_mask_broadcastss_ps() {
         let src = _mm256_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_mask_broadcastss_ps(src, 0, a);
@@ -54654,7 +56540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcastss_ps() {
+    const unsafe fn test_mm256_maskz_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_maskz_broadcastss_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -54664,7 +56550,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_broadcastss_ps() {
+    const unsafe fn test_mm_mask_broadcastss_ps() {
         let src = _mm_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_mask_broadcastss_ps(src, 0, a);
@@ -54675,7 +56561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_broadcastss_ps() {
+    const unsafe fn test_mm_maskz_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_maskz_broadcastss_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -54685,7 +56571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcast_i32x4() {
+    const unsafe fn test_mm512_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_broadcast_i32x4(a);
         let e = _mm512_set_epi32(
@@ -54695,7 +56581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcast_i32x4() {
+    const unsafe fn test_mm512_mask_broadcast_i32x4() {
         let src = _mm512_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_mask_broadcast_i32x4(src, 0, a);
@@ -54708,7 +56594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcast_i32x4() {
+    const unsafe fn test_mm512_maskz_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_maskz_broadcast_i32x4(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -54718,7 +56604,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_broadcast_i32x4() {
+    const unsafe fn test_mm256_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_broadcast_i32x4(a);
         let e = _mm256_set_epi32(17, 18, 19, 20, 17, 18, 19, 20);
@@ -54726,7 +56612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_broadcast_i32x4() {
+    const unsafe fn test_mm256_mask_broadcast_i32x4() {
         let src = _mm256_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_mask_broadcast_i32x4(src, 0, a);
@@ -54737,7 +56623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcast_i32x4() {
+    const unsafe fn test_mm256_maskz_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_maskz_broadcast_i32x4(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -54747,7 +56633,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcast_f32x4() {
+    const unsafe fn test_mm512_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_broadcast_f32x4(a);
         let e = _mm512_set_ps(
@@ -54757,7 +56643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcast_f32x4() {
+    const unsafe fn test_mm512_mask_broadcast_f32x4() {
         let src = _mm512_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_mask_broadcast_f32x4(src, 0, a);
@@ -54770,7 +56656,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcast_f32x4() {
+    const unsafe fn test_mm512_maskz_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_maskz_broadcast_f32x4(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -54782,7 +56668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_broadcast_f32x4() {
+    const unsafe fn test_mm256_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_broadcast_f32x4(a);
         let e = _mm256_set_ps(17., 18., 19., 20., 17., 18., 19., 20.);
@@ -54790,7 +56676,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_broadcast_f32x4() {
+    const unsafe fn test_mm256_mask_broadcast_f32x4() {
         let src = _mm256_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_mask_broadcast_f32x4(src, 0, a);
@@ -54801,7 +56687,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcast_f32x4() {
+    const unsafe fn test_mm256_maskz_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_maskz_broadcast_f32x4(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -54811,7 +56697,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_blend_epi32() {
+    const unsafe fn test_mm512_mask_blend_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(2);
         let r = _mm512_mask_blend_epi32(0b11111111_00000000, a, b);
@@ -54820,7 +56706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_blend_epi32() {
+    const unsafe fn test_mm256_mask_blend_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_mask_blend_epi32(0b11111111, a, b);
@@ -54829,7 +56715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_blend_epi32() {
+    const unsafe fn test_mm_mask_blend_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(2);
         let r = _mm_mask_blend_epi32(0b00001111, a, b);
@@ -54838,7 +56724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_blend_ps() {
+    const unsafe fn test_mm512_mask_blend_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(2.);
         let r = _mm512_mask_blend_ps(0b11111111_00000000, a, b);
@@ -54849,7 +56735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_blend_ps() {
+    const unsafe fn test_mm256_mask_blend_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(2.);
         let r = _mm256_mask_blend_ps(0b11111111, a, b);
@@ -54858,7 +56744,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_blend_ps() {
+    const unsafe fn test_mm_mask_blend_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let r = _mm_mask_blend_ps(0b00001111, a, b);
@@ -54867,7 +56753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpackhi_epi32() {
+    const unsafe fn test_mm512_unpackhi_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -54878,7 +56764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpackhi_epi32() {
+    const unsafe fn test_mm512_mask_unpackhi_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -54891,7 +56777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpackhi_epi32() {
+    const unsafe fn test_mm512_maskz_unpackhi_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -54904,7 +56790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpackhi_epi32() {
+    const unsafe fn test_mm256_mask_unpackhi_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_mask_unpackhi_epi32(a, 0, a, b);
@@ -54915,7 +56801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpackhi_epi32() {
+    const unsafe fn test_mm256_maskz_unpackhi_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_maskz_unpackhi_epi32(0, a, b);
@@ -54926,7 +56812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpackhi_epi32() {
+    const unsafe fn test_mm_mask_unpackhi_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_mask_unpackhi_epi32(a, 0, a, b);
@@ -54937,7 +56823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpackhi_epi32() {
+    const unsafe fn test_mm_maskz_unpackhi_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_maskz_unpackhi_epi32(0, a, b);
@@ -54948,7 +56834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpackhi_ps() {
+    const unsafe fn test_mm512_unpackhi_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54963,7 +56849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpackhi_ps() {
+    const unsafe fn test_mm512_mask_unpackhi_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54980,7 +56866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpackhi_ps() {
+    const unsafe fn test_mm512_maskz_unpackhi_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -54997,7 +56883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpackhi_ps() {
+    const unsafe fn test_mm256_mask_unpackhi_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_mask_unpackhi_ps(a, 0, a, b);
@@ -55008,7 +56894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpackhi_ps() {
+    const unsafe fn test_mm256_maskz_unpackhi_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_maskz_unpackhi_ps(0, a, b);
@@ -55019,7 +56905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpackhi_ps() {
+    const unsafe fn test_mm_mask_unpackhi_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_mask_unpackhi_ps(a, 0, a, b);
@@ -55030,7 +56916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpackhi_ps() {
+    const unsafe fn test_mm_maskz_unpackhi_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_maskz_unpackhi_ps(0, a, b);
@@ -55041,7 +56927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpacklo_epi32() {
+    const unsafe fn test_mm512_unpacklo_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -55052,7 +56938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpacklo_epi32() {
+    const unsafe fn test_mm512_mask_unpacklo_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -55065,7 +56951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpacklo_epi32() {
+    const unsafe fn test_mm512_maskz_unpacklo_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -55078,7 +56964,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpacklo_epi32() {
+    const unsafe fn test_mm256_mask_unpacklo_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_mask_unpacklo_epi32(a, 0, a, b);
@@ -55089,7 +56975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpacklo_epi32() {
+    const unsafe fn test_mm256_maskz_unpacklo_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_maskz_unpacklo_epi32(0, a, b);
@@ -55100,7 +56986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpacklo_epi32() {
+    const unsafe fn test_mm_mask_unpacklo_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_mask_unpacklo_epi32(a, 0, a, b);
@@ -55111,7 +56997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpacklo_epi32() {
+    const unsafe fn test_mm_maskz_unpacklo_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_maskz_unpacklo_epi32(0, a, b);
@@ -55122,7 +57008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpacklo_ps() {
+    const unsafe fn test_mm512_unpacklo_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -55137,7 +57023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpacklo_ps() {
+    const unsafe fn test_mm512_mask_unpacklo_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -55154,7 +57040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpacklo_ps() {
+    const unsafe fn test_mm512_maskz_unpacklo_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -55171,7 +57057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpacklo_ps() {
+    const unsafe fn test_mm256_mask_unpacklo_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_mask_unpacklo_ps(a, 0, a, b);
@@ -55182,7 +57068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpacklo_ps() {
+    const unsafe fn test_mm256_maskz_unpacklo_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_maskz_unpacklo_ps(0, a, b);
@@ -55193,7 +57079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpacklo_ps() {
+    const unsafe fn test_mm_mask_unpacklo_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_mask_unpacklo_ps(a, 0, a, b);
@@ -55204,7 +57090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpacklo_ps() {
+    const unsafe fn test_mm_maskz_unpacklo_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_maskz_unpacklo_ps(0, a, b);
@@ -55215,7 +57101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_alignr_epi32() {
+    const unsafe fn test_mm512_alignr_epi32() {
         let a = _mm512_set_epi32(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi32(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17,
@@ -55232,7 +57118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_alignr_epi32() {
+    const unsafe fn test_mm512_mask_alignr_epi32() {
         let a = _mm512_set_epi32(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi32(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17,
@@ -55247,7 +57133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_alignr_epi32() {
+    const unsafe fn test_mm512_maskz_alignr_epi32() {
         let a = _mm512_set_epi32(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi32(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17,
@@ -55260,7 +57146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_alignr_epi32() {
+    const unsafe fn test_mm256_alignr_epi32() {
         let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm256_alignr_epi32::<0>(a, b);
@@ -55271,7 +57157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_alignr_epi32() {
+    const unsafe fn test_mm256_mask_alignr_epi32() {
         let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm256_mask_alignr_epi32::<1>(a, 0, a, b);
@@ -55282,7 +57168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_alignr_epi32() {
+    const unsafe fn test_mm256_maskz_alignr_epi32() {
         let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm256_maskz_alignr_epi32::<1>(0, a, b);
@@ -55293,7 +57179,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_alignr_epi32() {
+    const unsafe fn test_mm_alignr_epi32() {
         let a = _mm_set_epi32(4, 3, 2, 1);
         let b = _mm_set_epi32(8, 7, 6, 5);
         let r = _mm_alignr_epi32::<0>(a, b);
@@ -55304,7 +57190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_alignr_epi32() {
+    const unsafe fn test_mm_mask_alignr_epi32() {
         let a = _mm_set_epi32(4, 3, 2, 1);
         let b = _mm_set_epi32(8, 7, 6, 5);
         let r = _mm_mask_alignr_epi32::<1>(a, 0, a, b);
@@ -55315,7 +57201,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_alignr_epi32() {
+    const unsafe fn test_mm_maskz_alignr_epi32() {
         let a = _mm_set_epi32(4, 3, 2, 1);
         let b = _mm_set_epi32(8, 7, 6, 5);
         let r = _mm_maskz_alignr_epi32::<1>(0, a, b);
@@ -55326,7 +57212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_and_epi32() {
+    const unsafe fn test_mm512_and_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55347,7 +57233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_and_epi32() {
+    const unsafe fn test_mm512_mask_and_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55376,7 +57262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_and_epi32() {
+    const unsafe fn test_mm512_maskz_and_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55399,7 +57285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_and_epi32() {
+    const unsafe fn test_mm256_mask_and_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_and_epi32(a, 0, a, b);
@@ -55410,7 +57296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_and_epi32() {
+    const unsafe fn test_mm256_maskz_and_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_maskz_and_epi32(0, a, b);
@@ -55421,7 +57307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_and_epi32() {
+    const unsafe fn test_mm_mask_and_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_and_epi32(a, 0, a, b);
@@ -55432,7 +57318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_and_epi32() {
+    const unsafe fn test_mm_maskz_and_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_maskz_and_epi32(0, a, b);
@@ -55443,7 +57329,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_and_si512() {
+    const unsafe fn test_mm512_and_si512() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55464,7 +57350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_or_epi32() {
+    const unsafe fn test_mm512_or_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55491,7 +57377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_or_epi32() {
+    const unsafe fn test_mm512_mask_or_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55520,7 +57406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_or_epi32() {
+    const unsafe fn test_mm512_maskz_or_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55549,7 +57435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_or_epi32() {
+    const unsafe fn test_mm256_or_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_or_epi32(a, b);
@@ -55558,7 +57444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_or_epi32() {
+    const unsafe fn test_mm256_mask_or_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_or_epi32(a, 0, a, b);
@@ -55569,7 +57455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_or_epi32() {
+    const unsafe fn test_mm256_maskz_or_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_maskz_or_epi32(0, a, b);
@@ -55580,7 +57466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_or_epi32() {
+    const unsafe fn test_mm_or_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_or_epi32(a, b);
@@ -55589,7 +57475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_or_epi32() {
+    const unsafe fn test_mm_mask_or_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_or_epi32(a, 0, a, b);
@@ -55600,7 +57486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_or_epi32() {
+    const unsafe fn test_mm_maskz_or_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_maskz_or_epi32(0, a, b);
@@ -55611,7 +57497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_or_si512() {
+    const unsafe fn test_mm512_or_si512() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55638,7 +57524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_xor_epi32() {
+    const unsafe fn test_mm512_xor_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55665,7 +57551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_xor_epi32() {
+    const unsafe fn test_mm512_mask_xor_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55694,7 +57580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_xor_epi32() {
+    const unsafe fn test_mm512_maskz_xor_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55717,7 +57603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_xor_epi32() {
+    const unsafe fn test_mm256_xor_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_xor_epi32(a, b);
@@ -55726,7 +57612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_xor_epi32() {
+    const unsafe fn test_mm256_mask_xor_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_xor_epi32(a, 0, a, b);
@@ -55737,7 +57623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_xor_epi32() {
+    const unsafe fn test_mm256_maskz_xor_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_maskz_xor_epi32(0, a, b);
@@ -55748,7 +57634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_xor_epi32() {
+    const unsafe fn test_mm_xor_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_xor_epi32(a, b);
@@ -55757,7 +57643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_xor_epi32() {
+    const unsafe fn test_mm_mask_xor_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_xor_epi32(a, 0, a, b);
@@ -55768,7 +57654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_xor_epi32() {
+    const unsafe fn test_mm_maskz_xor_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_maskz_xor_epi32(0, a, b);
@@ -55779,7 +57665,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_xor_si512() {
+    const unsafe fn test_mm512_xor_si512() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -55806,7 +57692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_andnot_epi32() {
+    const unsafe fn test_mm512_andnot_epi32() {
         let a = _mm512_set1_epi32(0);
         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm512_andnot_epi32(a, b);
@@ -55815,7 +57701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_andnot_epi32() {
+    const unsafe fn test_mm512_mask_andnot_epi32() {
         let a = _mm512_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm512_mask_andnot_epi32(a, 0, a, b);
@@ -55826,7 +57712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_andnot_epi32() {
+    const unsafe fn test_mm512_maskz_andnot_epi32() {
         let a = _mm512_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm512_maskz_andnot_epi32(0, a, b);
@@ -55843,7 +57729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_andnot_epi32() {
+    const unsafe fn test_mm256_mask_andnot_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm256_mask_andnot_epi32(a, 0, a, b);
@@ -55854,7 +57740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_andnot_epi32() {
+    const unsafe fn test_mm256_maskz_andnot_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm256_maskz_andnot_epi32(0, a, b);
@@ -55865,7 +57751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_andnot_epi32() {
+    const unsafe fn test_mm_mask_andnot_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm_mask_andnot_epi32(a, 0, a, b);
@@ -55876,7 +57762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_andnot_epi32() {
+    const unsafe fn test_mm_maskz_andnot_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm_maskz_andnot_epi32(0, a, b);
@@ -55887,7 +57773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_cvtmask16_u32() {
+    const unsafe fn test_cvtmask16_u32() {
         let a: __mmask16 = 0b11001100_00110011;
         let r = _cvtmask16_u32(a);
         let e: u32 = 0b11001100_00110011;
@@ -55895,7 +57781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_cvtu32_mask16() {
+    const unsafe fn test_cvtu32_mask16() {
         let a: u32 = 0b11001100_00110011;
         let r = _cvtu32_mask16(a);
         let e: __mmask16 = 0b11001100_00110011;
@@ -55903,7 +57789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kand() {
+    const unsafe fn test_mm512_kand() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b11001100_00110011;
         let r = _mm512_kand(a, b);
@@ -55912,7 +57798,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kand_mask16() {
+    const unsafe fn test_kand_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b11001100_00110011;
         let r = _kand_mask16(a, b);
@@ -55921,7 +57807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kor() {
+    const unsafe fn test_mm512_kor() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kor(a, b);
@@ -55930,7 +57816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kor_mask16() {
+    const unsafe fn test_kor_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kor_mask16(a, b);
@@ -55939,7 +57825,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kxor() {
+    const unsafe fn test_mm512_kxor() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kxor(a, b);
@@ -55948,7 +57834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kxor_mask16() {
+    const unsafe fn test_kxor_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kxor_mask16(a, b);
@@ -55957,7 +57843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_knot() {
+    const unsafe fn test_mm512_knot() {
         let a: u16 = 0b11001100_00110011;
         let r = _mm512_knot(a);
         let e: u16 = 0b00110011_11001100;
@@ -55965,7 +57851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_knot_mask16() {
+    const unsafe fn test_knot_mask16() {
         let a: u16 = 0b11001100_00110011;
         let r = _knot_mask16(a);
         let e: u16 = 0b00110011_11001100;
@@ -55973,7 +57859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kandn() {
+    const unsafe fn test_mm512_kandn() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kandn(a, b);
@@ -55982,7 +57868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kandn_mask16() {
+    const unsafe fn test_kandn_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kandn_mask16(a, b);
@@ -55991,7 +57877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kxnor() {
+    const unsafe fn test_mm512_kxnor() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kxnor(a, b);
@@ -56000,7 +57886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kxnor_mask16() {
+    const unsafe fn test_kxnor_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kxnor_mask16(a, b);
@@ -56009,7 +57895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kortest_mask16_u8() {
+    const unsafe fn test_kortest_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let mut all_ones: u8 = 0;
@@ -56019,7 +57905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kortestc_mask16_u8() {
+    const unsafe fn test_kortestc_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let r = _kortestc_mask16_u8(a, b);
@@ -56027,7 +57913,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kortestz_mask16_u8() {
+    const unsafe fn test_kortestz_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let r = _kortestz_mask16_u8(a, b);
@@ -56035,7 +57921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kshiftli_mask16() {
+    const unsafe fn test_kshiftli_mask16() {
         let a: __mmask16 = 0b1001011011000011;
         let r = _kshiftli_mask16::<3>(a);
         let e: __mmask16 = 0b1011011000011000;
@@ -56055,7 +57941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_kshiftri_mask16() {
+    const unsafe fn test_kshiftri_mask16() {
         let a: __mmask16 = 0b1010100100111100;
         let r = _kshiftri_mask16::<3>(a);
         let e: __mmask16 = 0b0001010100100111;
@@ -56075,7 +57961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_load_mask16() {
+    const unsafe fn test_load_mask16() {
         let a: __mmask16 = 0b1001011011000011;
         let r = _load_mask16(&a);
         let e: __mmask16 = 0b1001011011000011;
@@ -56083,7 +57969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_store_mask16() {
+    const unsafe fn test_store_mask16() {
         let a: __mmask16 = 0b0110100100111100;
         let mut r = 0;
         _store_mask16(&mut r, a);
@@ -56092,7 +57978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kmov() {
+    const unsafe fn test_mm512_kmov() {
         let a: u16 = 0b11001100_00110011;
         let r = _mm512_kmov(a);
         let e: u16 = 0b11001100_00110011;
@@ -56100,7 +57986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_int2mask() {
+    const unsafe fn test_mm512_int2mask() {
         let a: i32 = 0b11001100_00110011;
         let r = _mm512_int2mask(a);
         let e: u16 = 0b11001100_00110011;
@@ -56108,7 +57994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask2int() {
+    const unsafe fn test_mm512_mask2int() {
         let k1: __mmask16 = 0b11001100_00110011;
         let r = _mm512_mask2int(k1);
         let e: i32 = 0b11001100_00110011;
@@ -56116,7 +58002,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kunpackb() {
+    const unsafe fn test_mm512_kunpackb() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kunpackb(a, b);
@@ -56125,7 +58011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kortestc() {
+    const unsafe fn test_mm512_kortestc() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kortestc(a, b);
@@ -56136,7 +58022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_kortestz() {
+    const unsafe fn test_mm512_kortestz() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kortestz(a, b);
@@ -56146,7 +58032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_test_epi32_mask() {
+    const unsafe fn test_mm512_test_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm512_test_epi32_mask(a, b);
@@ -56155,7 +58041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_test_epi32_mask() {
+    const unsafe fn test_mm512_mask_test_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi32_mask(0, a, b);
@@ -56166,7 +58052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_test_epi32_mask() {
+    const unsafe fn test_mm256_test_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm256_test_epi32_mask(a, b);
@@ -56175,7 +58061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_test_epi32_mask() {
+    const unsafe fn test_mm256_mask_test_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi32_mask(0, a, b);
@@ -56186,7 +58072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_test_epi32_mask() {
+    const unsafe fn test_mm_test_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm_test_epi32_mask(a, b);
@@ -56195,7 +58081,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_test_epi32_mask() {
+    const unsafe fn test_mm_mask_test_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi32_mask(0, a, b);
@@ -56206,7 +58092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_testn_epi32_mask() {
+    const unsafe fn test_mm512_testn_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi32_mask(a, b);
@@ -56215,7 +58101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_testn_epi32_mask() {
+    const unsafe fn test_mm512_mask_testn_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 1);
         let r = _mm512_mask_test_epi32_mask(0, a, b);
@@ -56226,7 +58112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_testn_epi32_mask() {
+    const unsafe fn test_mm256_testn_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_testn_epi32_mask(a, b);
@@ -56235,7 +58121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_testn_epi32_mask() {
+    const unsafe fn test_mm256_mask_testn_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_test_epi32_mask(0, a, b);
@@ -56246,7 +58132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_testn_epi32_mask() {
+    const unsafe fn test_mm_testn_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_testn_epi32_mask(a, b);
@@ -56255,7 +58141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_testn_epi32_mask() {
+    const unsafe fn test_mm_mask_testn_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_test_epi32_mask(0, a, b);
@@ -56324,84 +58210,84 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_add_epi32() {
+    const unsafe fn test_mm512_reduce_add_epi32() {
         let a = _mm512_set1_epi32(1);
         let e: i32 = _mm512_reduce_add_epi32(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_add_epi32() {
+    const unsafe fn test_mm512_mask_reduce_add_epi32() {
         let a = _mm512_set1_epi32(1);
         let e: i32 = _mm512_mask_reduce_add_epi32(0b11111111_00000000, a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_add_ps() {
+    const unsafe fn test_mm512_reduce_add_ps() {
         let a = _mm512_set1_ps(1.);
         let e: f32 = _mm512_reduce_add_ps(a);
         assert_eq!(16., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_add_ps() {
+    const unsafe fn test_mm512_mask_reduce_add_ps() {
         let a = _mm512_set1_ps(1.);
         let e: f32 = _mm512_mask_reduce_add_ps(0b11111111_00000000, a);
         assert_eq!(8., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_mul_epi32() {
+    const unsafe fn test_mm512_reduce_mul_epi32() {
         let a = _mm512_set1_epi32(2);
         let e: i32 = _mm512_reduce_mul_epi32(a);
         assert_eq!(65536, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_mul_epi32() {
+    const unsafe fn test_mm512_mask_reduce_mul_epi32() {
         let a = _mm512_set1_epi32(2);
         let e: i32 = _mm512_mask_reduce_mul_epi32(0b11111111_00000000, a);
         assert_eq!(256, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_mul_ps() {
+    const unsafe fn test_mm512_reduce_mul_ps() {
         let a = _mm512_set1_ps(2.);
         let e: f32 = _mm512_reduce_mul_ps(a);
         assert_eq!(65536., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_mul_ps() {
+    const unsafe fn test_mm512_mask_reduce_mul_ps() {
         let a = _mm512_set1_ps(2.);
         let e: f32 = _mm512_mask_reduce_mul_ps(0b11111111_00000000, a);
         assert_eq!(256., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_max_epi32() {
+    const unsafe fn test_mm512_reduce_max_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_reduce_max_epi32(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_max_epi32() {
+    const unsafe fn test_mm512_mask_reduce_max_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_mask_reduce_max_epi32(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_max_epu32() {
+    const unsafe fn test_mm512_reduce_max_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_reduce_max_epu32(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_max_epu32() {
+    const unsafe fn test_mm512_mask_reduce_max_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_mask_reduce_max_epu32(0b11111111_00000000, a);
         assert_eq!(7, e);
@@ -56426,28 +58312,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_min_epi32() {
+    const unsafe fn test_mm512_reduce_min_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_reduce_min_epi32(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_min_epi32() {
+    const unsafe fn test_mm512_mask_reduce_min_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_mask_reduce_min_epi32(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_min_epu32() {
+    const unsafe fn test_mm512_reduce_min_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_reduce_min_epu32(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_min_epu32() {
+    const unsafe fn test_mm512_mask_reduce_min_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_mask_reduce_min_epu32(0b11111111_00000000, a);
         assert_eq!(0, e);
@@ -56472,28 +58358,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_and_epi32() {
+    const unsafe fn test_mm512_reduce_and_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_reduce_and_epi32(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_and_epi32() {
+    const unsafe fn test_mm512_mask_reduce_and_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_mask_reduce_and_epi32(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_or_epi32() {
+    const unsafe fn test_mm512_reduce_or_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_reduce_or_epi32(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_or_epi32() {
+    const unsafe fn test_mm512_mask_reduce_or_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_mask_reduce_and_epi32(0b11111111_00000000, a);
         assert_eq!(1, e);
@@ -56904,7 +58790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_loadu_epi32() {
+    const unsafe fn test_mm512_loadu_epi32() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50];
         let p = a.as_ptr();
         let r = _mm512_loadu_epi32(black_box(p));
@@ -56913,7 +58799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_loadu_epi32() {
+    const unsafe fn test_mm256_loadu_epi32() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50];
         let p = a.as_ptr();
         let r = _mm256_loadu_epi32(black_box(p));
@@ -56922,7 +58808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_loadu_epi32() {
+    const unsafe fn test_mm_loadu_epi32() {
         let a = &[4, 3, 2, 5];
         let p = a.as_ptr();
         let r = _mm_loadu_epi32(black_box(p));
@@ -57126,7 +59012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_storeu_epi32() {
+    const unsafe fn test_mm512_storeu_epi32() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
         _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a);
@@ -57134,7 +59020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_storeu_epi32() {
+    const unsafe fn test_mm256_storeu_epi32() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
         _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a);
@@ -57142,7 +59028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_storeu_epi32() {
+    const unsafe fn test_mm_storeu_epi32() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_undefined_si128();
         _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a);
@@ -57150,7 +59036,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_loadu_si512() {
+    const unsafe fn test_mm512_loadu_si512() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50];
         let p = a.as_ptr().cast();
         let r = _mm512_loadu_si512(black_box(p));
@@ -57159,7 +59045,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_storeu_si512() {
+    const unsafe fn test_mm512_storeu_si512() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
         _mm512_storeu_si512(&mut r as *mut _, a);
@@ -57167,7 +59053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_load_si512() {
+    const unsafe fn test_mm512_load_si512() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -57182,7 +59068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_store_si512() {
+    const unsafe fn test_mm512_store_si512() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
         _mm512_store_si512(&mut r as *mut _, a);
@@ -57190,7 +59076,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_load_epi32() {
+    const unsafe fn test_mm512_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -57205,7 +59091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_load_epi32() {
+    const unsafe fn test_mm256_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 8],
@@ -57220,7 +59106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_load_epi32() {
+    const unsafe fn test_mm_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 4],
@@ -57233,7 +59119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_store_epi32() {
+    const unsafe fn test_mm512_store_epi32() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
         _mm512_store_epi32(&mut r as *mut _ as *mut i32, a);
@@ -57241,7 +59127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_store_epi32() {
+    const unsafe fn test_mm256_store_epi32() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
         _mm256_store_epi32(&mut r as *mut _ as *mut i32, a);
@@ -57249,7 +59135,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_store_epi32() {
+    const unsafe fn test_mm_store_epi32() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_undefined_si128();
         _mm_store_epi32(&mut r as *mut _ as *mut i32, a);
@@ -57257,7 +59143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_load_ps() {
+    const unsafe fn test_mm512_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -57276,7 +59162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_store_ps() {
+    const unsafe fn test_mm512_store_ps() {
         let a = _mm512_set1_ps(9.);
         let mut r = _mm512_undefined_ps();
         _mm512_store_ps(&mut r as *mut _ as *mut f32, a);
@@ -57284,7 +59170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_set1_epi32() {
+    const unsafe fn test_mm512_mask_set1_epi32() {
         let src = _mm512_set1_epi32(2);
         let a: i32 = 11;
         let r = _mm512_mask_set1_epi32(src, 0, a);
@@ -57295,7 +59181,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_set1_epi32() {
+    const unsafe fn test_mm512_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm512_maskz_set1_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -57305,7 +59191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_set1_epi32() {
+    const unsafe fn test_mm256_mask_set1_epi32() {
         let src = _mm256_set1_epi32(2);
         let a: i32 = 11;
         let r = _mm256_mask_set1_epi32(src, 0, a);
@@ -57316,7 +59202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_set1_epi32() {
+    const unsafe fn test_mm256_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm256_maskz_set1_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -57326,7 +59212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_set1_epi32() {
+    const unsafe fn test_mm_mask_set1_epi32() {
         let src = _mm_set1_epi32(2);
         let a: i32 = 11;
         let r = _mm_mask_set1_epi32(src, 0, a);
@@ -57337,7 +59223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_set1_epi32() {
+    const unsafe fn test_mm_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm_maskz_set1_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -57347,7 +59233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_move_ss() {
+    const unsafe fn test_mm_mask_move_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -57360,7 +59246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_move_ss() {
+    const unsafe fn test_mm_maskz_move_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_move_ss(0, a, b);
@@ -57372,7 +59258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_move_sd() {
+    const unsafe fn test_mm_mask_move_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -57385,7 +59271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_move_sd() {
+    const unsafe fn test_mm_maskz_move_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_move_sd(0, a, b);
@@ -57397,7 +59283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_add_ss() {
+    const unsafe fn test_mm_mask_add_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -57410,7 +59296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_add_ss() {
+    const unsafe fn test_mm_maskz_add_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_add_ss(0, a, b);
@@ -57422,7 +59308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_add_sd() {
+    const unsafe fn test_mm_mask_add_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -57435,7 +59321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_add_sd() {
+    const unsafe fn test_mm_maskz_add_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_add_sd(0, a, b);
@@ -57447,7 +59333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sub_ss() {
+    const unsafe fn test_mm_mask_sub_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -57460,7 +59346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sub_ss() {
+    const unsafe fn test_mm_maskz_sub_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_sub_ss(0, a, b);
@@ -57472,7 +59358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sub_sd() {
+    const unsafe fn test_mm_mask_sub_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -57485,7 +59371,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sub_sd() {
+    const unsafe fn test_mm_maskz_sub_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_sub_sd(0, a, b);
@@ -57497,7 +59383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_mul_ss() {
+    const unsafe fn test_mm_mask_mul_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -57510,7 +59396,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_mul_ss() {
+    const unsafe fn test_mm_maskz_mul_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_mul_ss(0, a, b);
@@ -57522,7 +59408,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_mul_sd() {
+    const unsafe fn test_mm_mask_mul_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -57535,7 +59421,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_mul_sd() {
+    const unsafe fn test_mm_maskz_mul_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_mul_sd(0, a, b);
@@ -57547,7 +59433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_div_ss() {
+    const unsafe fn test_mm_mask_div_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -57560,7 +59446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_div_ss() {
+    const unsafe fn test_mm_maskz_div_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_div_ss(0, a, b);
@@ -57572,7 +59458,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_div_sd() {
+    const unsafe fn test_mm_mask_div_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -57585,7 +59471,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_div_sd() {
+    const unsafe fn test_mm_maskz_div_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_div_sd(0, a, b);
@@ -58143,7 +60029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmadd_ss() {
+    const unsafe fn test_mm_mask_fmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58155,7 +60041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmadd_ss() {
+    const unsafe fn test_mm_maskz_fmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58168,7 +60054,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmadd_ss() {
+    const unsafe fn test_mm_mask3_fmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58180,7 +60066,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmadd_sd() {
+    const unsafe fn test_mm_mask_fmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58192,7 +60078,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmadd_sd() {
+    const unsafe fn test_mm_maskz_fmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58205,7 +60091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmadd_sd() {
+    const unsafe fn test_mm_mask3_fmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58217,7 +60103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmsub_ss() {
+    const unsafe fn test_mm_mask_fmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58229,7 +60115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmsub_ss() {
+    const unsafe fn test_mm_maskz_fmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58242,7 +60128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmsub_ss() {
+    const unsafe fn test_mm_mask3_fmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58254,7 +60140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmsub_sd() {
+    const unsafe fn test_mm_mask_fmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58266,7 +60152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmsub_sd() {
+    const unsafe fn test_mm_maskz_fmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58279,7 +60165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmsub_sd() {
+    const unsafe fn test_mm_mask3_fmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58291,7 +60177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmadd_ss() {
+    const unsafe fn test_mm_mask_fnmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58303,7 +60189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmadd_ss() {
+    const unsafe fn test_mm_maskz_fnmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58316,7 +60202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmadd_ss() {
+    const unsafe fn test_mm_mask3_fnmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58328,7 +60214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmadd_sd() {
+    const unsafe fn test_mm_mask_fnmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58340,7 +60226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmadd_sd() {
+    const unsafe fn test_mm_maskz_fnmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58353,7 +60239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmadd_sd() {
+    const unsafe fn test_mm_mask3_fnmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58365,7 +60251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmsub_ss() {
+    const unsafe fn test_mm_mask_fnmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58377,7 +60263,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmsub_ss() {
+    const unsafe fn test_mm_maskz_fnmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58390,7 +60276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmsub_ss() {
+    const unsafe fn test_mm_mask3_fnmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -58402,7 +60288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmsub_sd() {
+    const unsafe fn test_mm_mask_fnmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58414,7 +60300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmsub_sd() {
+    const unsafe fn test_mm_maskz_fnmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -58427,7 +60313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmsub_sd() {
+    const unsafe fn test_mm_mask3_fnmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60082,7 +61968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvti32_ss() {
+    const unsafe fn test_mm_cvti32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i32 = 9;
         let r = _mm_cvti32_ss(a, b);
@@ -60091,7 +61977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvti32_sd() {
+    const unsafe fn test_mm_cvti32_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: i32 = 9;
         let r = _mm_cvti32_sd(a, b);
@@ -60180,7 +62066,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtu32_ss() {
+    const unsafe fn test_mm_cvtu32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: u32 = 9;
         let r = _mm_cvtu32_ss(a, b);
@@ -60189,7 +62075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtu32_sd() {
+    const unsafe fn test_mm_cvtu32_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: u32 = 9;
         let r = _mm_cvtu32_sd(a, b);
@@ -60216,7 +62102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsi512_si32() {
+    const unsafe fn test_mm512_cvtsi512_si32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvtsi512_si32(a);
         let e: i32 = 1;
@@ -60224,7 +62110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtss_f32() {
+    const unsafe fn test_mm512_cvtss_f32() {
         let a = _mm512_setr_ps(
             312.0134, 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         );
@@ -60232,13 +62118,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsd_f64() {
+    const unsafe fn test_mm512_cvtsd_f64() {
         let r = _mm512_cvtsd_f64(_mm512_setr_pd(-1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8));
         assert_eq!(r, -1.1);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_pd() {
+    const unsafe fn test_mm512_shuffle_pd() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
         let r = _mm512_shuffle_pd::<0b11_11_11_11>(a, b);
@@ -60247,7 +62133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_pd() {
+    const unsafe fn test_mm512_mask_shuffle_pd() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
         let r = _mm512_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
@@ -60258,7 +62144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_pd() {
+    const unsafe fn test_mm512_maskz_shuffle_pd() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
         let r = _mm512_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
diff --git a/crates/core_arch/src/x86_64/avx512f.rs b/crates/core_arch/src/x86_64/avx512f.rs
index a2656c8535..c85a5580c8 100644
--- a/crates/core_arch/src/x86_64/avx512f.rs
+++ b/crates/core_arch/src/x86_64/avx512f.rs
@@ -57,7 +57,8 @@ pub fn _mm_cvtsd_u64(a: __m128d) -> u64 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtsi2ss))]
-pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
     unsafe {
         let b = b as f32;
         simd_insert!(a, 0, b)
@@ -71,7 +72,8 @@ pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtsi2sd))]
-pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
     unsafe {
         let b = b as f64;
         simd_insert!(a, 0, b)
@@ -85,7 +87,8 @@ pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtusi2ss))]
-pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
     unsafe {
         let b = b as f32;
         simd_insert!(a, 0, b)
@@ -99,7 +102,8 @@ pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
 #[target_feature(enable = "avx512f")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvtusi2sd))]
-pub fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
     unsafe {
         let b = b as f64;
         simd_insert!(a, 0, b)
@@ -554,6 +558,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
@@ -562,7 +567,7 @@ mod tests {
     use crate::hint::black_box;
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_abs_epi64() {
+    const unsafe fn test_mm512_abs_epi64() {
         let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let r = _mm512_abs_epi64(a);
         let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
@@ -570,7 +575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_abs_epi64() {
+    const unsafe fn test_mm512_mask_abs_epi64() {
         let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let r = _mm512_mask_abs_epi64(a, 0, a);
         assert_eq_m512i(r, a);
@@ -580,7 +585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_abs_epi64() {
+    const unsafe fn test_mm512_maskz_abs_epi64() {
         let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let r = _mm512_maskz_abs_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -590,7 +595,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_abs_epi64() {
+    const unsafe fn test_mm256_abs_epi64() {
         let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
         let r = _mm256_abs_epi64(a);
         let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
@@ -598,7 +603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_abs_epi64() {
+    const unsafe fn test_mm256_mask_abs_epi64() {
         let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
         let r = _mm256_mask_abs_epi64(a, 0, a);
         assert_eq_m256i(r, a);
@@ -608,7 +613,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_abs_epi64() {
+    const unsafe fn test_mm256_maskz_abs_epi64() {
         let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
         let r = _mm256_maskz_abs_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -618,7 +623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_abs_epi64() {
+    const unsafe fn test_mm_abs_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let r = _mm_abs_epi64(a);
         let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
@@ -630,7 +635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_abs_epi64() {
+    const unsafe fn test_mm_mask_abs_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let r = _mm_mask_abs_epi64(a, 0, a);
         assert_eq_m128i(r, a);
@@ -644,7 +649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_abs_epi64() {
+    const unsafe fn test_mm_maskz_abs_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let r = _mm_maskz_abs_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -658,7 +663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_abs_pd() {
+    const unsafe fn test_mm512_abs_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let r = _mm512_abs_pd(a);
         let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
@@ -666,7 +671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_abs_pd() {
+    const unsafe fn test_mm512_mask_abs_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let r = _mm512_mask_abs_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -676,7 +681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mov_epi64() {
+    const unsafe fn test_mm512_mask_mov_epi64() {
         let src = _mm512_set1_epi64(1);
         let a = _mm512_set1_epi64(2);
         let r = _mm512_mask_mov_epi64(src, 0, a);
@@ -686,7 +691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mov_epi64() {
+    const unsafe fn test_mm512_maskz_mov_epi64() {
         let a = _mm512_set1_epi64(2);
         let r = _mm512_maskz_mov_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -695,7 +700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mov_epi64() {
+    const unsafe fn test_mm256_mask_mov_epi64() {
         let src = _mm256_set1_epi64x(1);
         let a = _mm256_set1_epi64x(2);
         let r = _mm256_mask_mov_epi64(src, 0, a);
@@ -705,7 +710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mov_epi64() {
+    const unsafe fn test_mm256_maskz_mov_epi64() {
         let a = _mm256_set1_epi64x(2);
         let r = _mm256_maskz_mov_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -714,7 +719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mov_epi64() {
+    const unsafe fn test_mm_mask_mov_epi64() {
         let src = _mm_set1_epi64x(1);
         let a = _mm_set1_epi64x(2);
         let r = _mm_mask_mov_epi64(src, 0, a);
@@ -724,7 +729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mov_epi64() {
+    const unsafe fn test_mm_maskz_mov_epi64() {
         let a = _mm_set1_epi64x(2);
         let r = _mm_maskz_mov_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -733,7 +738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mov_pd() {
+    const unsafe fn test_mm512_mask_mov_pd() {
         let src = _mm512_set1_pd(1.);
         let a = _mm512_set1_pd(2.);
         let r = _mm512_mask_mov_pd(src, 0, a);
@@ -743,7 +748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mov_pd() {
+    const unsafe fn test_mm512_maskz_mov_pd() {
         let a = _mm512_set1_pd(2.);
         let r = _mm512_maskz_mov_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -752,7 +757,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mov_pd() {
+    const unsafe fn test_mm256_mask_mov_pd() {
         let src = _mm256_set1_pd(1.);
         let a = _mm256_set1_pd(2.);
         let r = _mm256_mask_mov_pd(src, 0, a);
@@ -762,7 +767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mov_pd() {
+    const unsafe fn test_mm256_maskz_mov_pd() {
         let a = _mm256_set1_pd(2.);
         let r = _mm256_maskz_mov_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -771,7 +776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mov_pd() {
+    const unsafe fn test_mm_mask_mov_pd() {
         let src = _mm_set1_pd(1.);
         let a = _mm_set1_pd(2.);
         let r = _mm_mask_mov_pd(src, 0, a);
@@ -781,7 +786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mov_pd() {
+    const unsafe fn test_mm_maskz_mov_pd() {
         let a = _mm_set1_pd(2.);
         let r = _mm_maskz_mov_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -790,7 +795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_add_epi64() {
+    const unsafe fn test_mm512_add_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_add_epi64(a, b);
@@ -799,7 +804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_add_epi64() {
+    const unsafe fn test_mm512_mask_add_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_mask_add_epi64(a, 0, a, b);
@@ -810,7 +815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_add_epi64() {
+    const unsafe fn test_mm512_maskz_add_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_maskz_add_epi64(0, a, b);
@@ -821,7 +826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_add_epi64() {
+    const unsafe fn test_mm256_mask_add_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_mask_add_epi64(a, 0, a, b);
@@ -832,7 +837,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_add_epi64() {
+    const unsafe fn test_mm256_maskz_add_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_add_epi64(0, a, b);
@@ -843,7 +848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_add_epi64() {
+    const unsafe fn test_mm_mask_add_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_mask_add_epi64(a, 0, a, b);
@@ -854,7 +859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_add_epi64() {
+    const unsafe fn test_mm_maskz_add_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_maskz_add_epi64(0, a, b);
@@ -865,7 +870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_add_pd() {
+    const unsafe fn test_mm512_add_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_add_pd(a, b);
@@ -874,7 +879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_add_pd() {
+    const unsafe fn test_mm512_mask_add_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_mask_add_pd(a, 0, a, b);
@@ -885,7 +890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_add_pd() {
+    const unsafe fn test_mm512_maskz_add_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_maskz_add_pd(0, a, b);
@@ -896,7 +901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_add_pd() {
+    const unsafe fn test_mm256_mask_add_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_mask_add_pd(a, 0, a, b);
@@ -907,7 +912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_add_pd() {
+    const unsafe fn test_mm256_maskz_add_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_maskz_add_pd(0, a, b);
@@ -918,7 +923,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_add_pd() {
+    const unsafe fn test_mm_mask_add_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_mask_add_pd(a, 0, a, b);
@@ -929,7 +934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_add_pd() {
+    const unsafe fn test_mm_maskz_add_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_maskz_add_pd(0, a, b);
@@ -940,7 +945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sub_epi64() {
+    const unsafe fn test_mm512_sub_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_sub_epi64(a, b);
@@ -949,7 +954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sub_epi64() {
+    const unsafe fn test_mm512_mask_sub_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_mask_sub_epi64(a, 0, a, b);
@@ -960,7 +965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sub_epi64() {
+    const unsafe fn test_mm512_maskz_sub_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_maskz_sub_epi64(0, a, b);
@@ -971,7 +976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sub_epi64() {
+    const unsafe fn test_mm256_mask_sub_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_mask_sub_epi64(a, 0, a, b);
@@ -982,7 +987,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_epi64() {
+    const unsafe fn test_mm256_maskz_sub_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_sub_epi64(0, a, b);
@@ -993,7 +998,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sub_epi64() {
+    const unsafe fn test_mm_mask_sub_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_mask_sub_epi64(a, 0, a, b);
@@ -1004,7 +1009,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sub_epi64() {
+    const unsafe fn test_mm_maskz_sub_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_maskz_sub_epi64(0, a, b);
@@ -1015,7 +1020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sub_pd() {
+    const unsafe fn test_mm512_sub_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_sub_pd(a, b);
@@ -1024,7 +1029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sub_pd() {
+    const unsafe fn test_mm512_mask_sub_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_mask_sub_pd(a, 0, a, b);
@@ -1035,7 +1040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sub_pd() {
+    const unsafe fn test_mm512_maskz_sub_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_maskz_sub_pd(0, a, b);
@@ -1046,7 +1051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sub_pd() {
+    const unsafe fn test_mm256_mask_sub_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_mask_sub_pd(a, 0, a, b);
@@ -1057,7 +1062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_pd() {
+    const unsafe fn test_mm256_maskz_sub_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_maskz_sub_pd(0, a, b);
@@ -1068,7 +1073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sub_pd() {
+    const unsafe fn test_mm_mask_sub_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_mask_sub_pd(a, 0, a, b);
@@ -1079,7 +1084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sub_pd() {
+    const unsafe fn test_mm_maskz_sub_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_maskz_sub_pd(0, a, b);
@@ -1090,7 +1095,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mul_epi32() {
+    const unsafe fn test_mm512_mul_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mul_epi32(a, b);
@@ -1099,7 +1104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mul_epi32() {
+    const unsafe fn test_mm512_mask_mul_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_mul_epi32(a, 0, a, b);
@@ -1114,7 +1119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mul_epi32() {
+    const unsafe fn test_mm512_maskz_mul_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_mul_epi32(0, a, b);
@@ -1125,7 +1130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mul_epi32() {
+    const unsafe fn test_mm256_mask_mul_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mask_mul_epi32(a, 0, a, b);
@@ -1136,7 +1141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mul_epi32() {
+    const unsafe fn test_mm256_maskz_mul_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_mul_epi32(0, a, b);
@@ -1147,7 +1152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mul_epi32() {
+    const unsafe fn test_mm_mask_mul_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_mask_mul_epi32(a, 0, a, b);
@@ -1158,7 +1163,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mul_epi32() {
+    const unsafe fn test_mm_maskz_mul_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_mul_epi32(0, a, b);
@@ -1169,7 +1174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mul_epu32() {
+    const unsafe fn test_mm512_mul_epu32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mul_epu32(a, b);
@@ -1178,7 +1183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mul_epu32() {
+    const unsafe fn test_mm512_mask_mul_epu32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_mul_epu32(a, 0, a, b);
@@ -1193,7 +1198,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mul_epu32() {
+    const unsafe fn test_mm512_maskz_mul_epu32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_mul_epu32(0, a, b);
@@ -1204,7 +1209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mul_epu32() {
+    const unsafe fn test_mm256_mask_mul_epu32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mask_mul_epu32(a, 0, a, b);
@@ -1215,7 +1220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mul_epu32() {
+    const unsafe fn test_mm256_maskz_mul_epu32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_mul_epu32(0, a, b);
@@ -1226,7 +1231,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mul_epu32() {
+    const unsafe fn test_mm_mask_mul_epu32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_mask_mul_epu32(a, 0, a, b);
@@ -1237,7 +1242,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mul_epu32() {
+    const unsafe fn test_mm_maskz_mul_epu32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_mul_epu32(0, a, b);
@@ -1248,7 +1253,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mullox_epi64() {
+    const unsafe fn test_mm512_mullox_epi64() {
         let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
         let b = _mm512_set1_epi64(2);
         let r = _mm512_mullox_epi64(a, b);
@@ -1257,7 +1262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mullox_epi64() {
+    const unsafe fn test_mm512_mask_mullox_epi64() {
         let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
         let b = _mm512_set1_epi64(2);
         let r = _mm512_mask_mullox_epi64(a, 0, a, b);
@@ -1268,7 +1273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mul_pd() {
+    const unsafe fn test_mm512_mul_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_mul_pd(a, b);
@@ -1281,7 +1286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mul_pd() {
+    const unsafe fn test_mm512_mask_mul_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_mask_mul_pd(a, 0, a, b);
@@ -1296,7 +1301,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mul_pd() {
+    const unsafe fn test_mm512_maskz_mul_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_maskz_mul_pd(0, a, b);
@@ -1307,7 +1312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_mul_pd() {
+    const unsafe fn test_mm256_mask_mul_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(2.);
         let r = _mm256_mask_mul_pd(a, 0, a, b);
@@ -1318,7 +1323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_mul_pd() {
+    const unsafe fn test_mm256_maskz_mul_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(2.);
         let r = _mm256_maskz_mul_pd(0, a, b);
@@ -1329,7 +1334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_mul_pd() {
+    const unsafe fn test_mm_mask_mul_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(2.);
         let r = _mm_mask_mul_pd(a, 0, a, b);
@@ -1340,7 +1345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_mul_pd() {
+    const unsafe fn test_mm_maskz_mul_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(2.);
         let r = _mm_maskz_mul_pd(0, a, b);
@@ -1351,7 +1356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_div_pd() {
+    const unsafe fn test_mm512_div_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
         let r = _mm512_div_pd(a, b);
@@ -1364,7 +1369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_div_pd() {
+    const unsafe fn test_mm512_mask_div_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
         let r = _mm512_mask_div_pd(a, 0, a, b);
@@ -1379,7 +1384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_div_pd() {
+    const unsafe fn test_mm512_maskz_div_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
         let r = _mm512_maskz_div_pd(0, a, b);
@@ -1390,7 +1395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_div_pd() {
+    const unsafe fn test_mm256_mask_div_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set_pd(2., 2., 0., 0.);
         let r = _mm256_mask_div_pd(a, 0, a, b);
@@ -1401,7 +1406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_div_pd() {
+    const unsafe fn test_mm256_maskz_div_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set_pd(2., 2., 0., 0.);
         let r = _mm256_maskz_div_pd(0, a, b);
@@ -1412,7 +1417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_div_pd() {
+    const unsafe fn test_mm_mask_div_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set_pd(0., 0.);
         let r = _mm_mask_div_pd(a, 0, a, b);
@@ -1423,7 +1428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_div_pd() {
+    const unsafe fn test_mm_maskz_div_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set_pd(0., 0.);
         let r = _mm_maskz_div_pd(0, a, b);
@@ -1434,7 +1439,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_epi64() {
+    const unsafe fn test_mm512_max_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epi64(a, b);
@@ -1443,7 +1448,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_epi64() {
+    const unsafe fn test_mm512_mask_max_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epi64(a, 0, a, b);
@@ -1454,7 +1459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_epi64() {
+    const unsafe fn test_mm512_maskz_max_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epi64(0, a, b);
@@ -1465,7 +1470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_max_epi64() {
+    const unsafe fn test_mm256_max_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_max_epi64(a, b);
@@ -1474,7 +1479,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_max_epi64() {
+    const unsafe fn test_mm256_mask_max_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_max_epi64(a, 0, a, b);
@@ -1485,7 +1490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epi64() {
+    const unsafe fn test_mm256_maskz_max_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_max_epi64(0, a, b);
@@ -1496,7 +1501,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_max_epi64() {
+    const unsafe fn test_mm_max_epi64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_max_epi64(a, b);
@@ -1505,7 +1510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_max_epi64() {
+    const unsafe fn test_mm_mask_max_epi64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_mask_max_epi64(a, 0, a, b);
@@ -1516,7 +1521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_max_epi64() {
+    const unsafe fn test_mm_maskz_max_epi64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_maskz_max_epi64(0, a, b);
@@ -1602,7 +1607,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_epu64() {
+    const unsafe fn test_mm512_max_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epu64(a, b);
@@ -1611,7 +1616,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_epu64() {
+    const unsafe fn test_mm512_mask_max_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epu64(a, 0, a, b);
@@ -1622,7 +1627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_epu64() {
+    const unsafe fn test_mm512_maskz_max_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epu64(0, a, b);
@@ -1633,7 +1638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_max_epu64() {
+    const unsafe fn test_mm256_max_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_max_epu64(a, b);
@@ -1642,7 +1647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_max_epu64() {
+    const unsafe fn test_mm256_mask_max_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_max_epu64(a, 0, a, b);
@@ -1653,7 +1658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epu64() {
+    const unsafe fn test_mm256_maskz_max_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_max_epu64(0, a, b);
@@ -1664,7 +1669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_max_epu64() {
+    const unsafe fn test_mm_max_epu64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_max_epu64(a, b);
@@ -1673,7 +1678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_max_epu64() {
+    const unsafe fn test_mm_mask_max_epu64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_mask_max_epu64(a, 0, a, b);
@@ -1684,7 +1689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_max_epu64() {
+    const unsafe fn test_mm_maskz_max_epu64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_maskz_max_epu64(0, a, b);
@@ -1695,7 +1700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_epi64() {
+    const unsafe fn test_mm512_min_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epi64(a, b);
@@ -1704,7 +1709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_epi64() {
+    const unsafe fn test_mm512_mask_min_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epi64(a, 0, a, b);
@@ -1715,7 +1720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_epi64() {
+    const unsafe fn test_mm512_maskz_min_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epi64(0, a, b);
@@ -1726,7 +1731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_min_epi64() {
+    const unsafe fn test_mm256_min_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_min_epi64(a, b);
@@ -1735,7 +1740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_min_epi64() {
+    const unsafe fn test_mm256_mask_min_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_min_epi64(a, 0, a, b);
@@ -1746,7 +1751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epi64() {
+    const unsafe fn test_mm256_maskz_min_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_min_epi64(0, a, b);
@@ -1757,7 +1762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_min_epi64() {
+    const unsafe fn test_mm_min_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_min_epi64(a, b);
@@ -1771,7 +1776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_min_epi64() {
+    const unsafe fn test_mm_mask_min_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_mask_min_epi64(a, 0, a, b);
@@ -1782,7 +1787,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_min_epi64() {
+    const unsafe fn test_mm_maskz_min_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_maskz_min_epi64(0, a, b);
@@ -1868,7 +1873,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_epu64() {
+    const unsafe fn test_mm512_min_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epu64(a, b);
@@ -1877,7 +1882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_epu64() {
+    const unsafe fn test_mm512_mask_min_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epu64(a, 0, a, b);
@@ -1888,7 +1893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_epu64() {
+    const unsafe fn test_mm512_maskz_min_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epu64(0, a, b);
@@ -1899,7 +1904,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_min_epu64() {
+    const unsafe fn test_mm256_min_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_min_epu64(a, b);
@@ -1908,7 +1913,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_min_epu64() {
+    const unsafe fn test_mm256_mask_min_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_min_epu64(a, 0, a, b);
@@ -1919,7 +1924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epu64() {
+    const unsafe fn test_mm256_maskz_min_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_min_epu64(0, a, b);
@@ -1930,7 +1935,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_min_epu64() {
+    const unsafe fn test_mm_min_epu64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(1, 0);
         let r = _mm_min_epu64(a, b);
@@ -1939,7 +1944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_min_epu64() {
+    const unsafe fn test_mm_mask_min_epu64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(1, 0);
         let r = _mm_mask_min_epu64(a, 0, a, b);
@@ -1950,7 +1955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_min_epu64() {
+    const unsafe fn test_mm_maskz_min_epu64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(1, 0);
         let r = _mm_maskz_min_epu64(0, a, b);
@@ -2029,7 +2034,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmadd_pd() {
+    const unsafe fn test_mm512_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
@@ -2039,7 +2044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmadd_pd() {
+    const unsafe fn test_mm512_mask_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
@@ -2051,7 +2056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmadd_pd() {
+    const unsafe fn test_mm512_maskz_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
@@ -2063,7 +2068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmadd_pd() {
+    const unsafe fn test_mm512_mask3_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2075,7 +2080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmadd_pd() {
+    const unsafe fn test_mm256_mask_fmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2087,7 +2092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmadd_pd() {
+    const unsafe fn test_mm256_maskz_fmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2099,7 +2104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmadd_pd() {
+    const unsafe fn test_mm256_mask3_fmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2111,7 +2116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_pd() {
+    const unsafe fn test_mm_mask_fmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2123,7 +2128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_pd() {
+    const unsafe fn test_mm_maskz_fmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2135,7 +2140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_pd() {
+    const unsafe fn test_mm_mask3_fmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2147,7 +2152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsub_pd() {
+    const unsafe fn test_mm512_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2157,7 +2162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsub_pd() {
+    const unsafe fn test_mm512_mask_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2169,7 +2174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsub_pd() {
+    const unsafe fn test_mm512_maskz_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2181,7 +2186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsub_pd() {
+    const unsafe fn test_mm512_mask3_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2193,7 +2198,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmsub_pd() {
+    const unsafe fn test_mm256_mask_fmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2205,7 +2210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmsub_pd() {
+    const unsafe fn test_mm256_maskz_fmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2217,7 +2222,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmsub_pd() {
+    const unsafe fn test_mm256_mask3_fmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2229,7 +2234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmsub_pd() {
+    const unsafe fn test_mm_mask_fmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2241,7 +2246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmsub_pd() {
+    const unsafe fn test_mm_maskz_fmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2253,7 +2258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmsub_pd() {
+    const unsafe fn test_mm_mask3_fmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2265,7 +2270,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmaddsub_pd() {
+    const unsafe fn test_mm512_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2275,7 +2280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmaddsub_pd() {
+    const unsafe fn test_mm512_mask_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2287,7 +2292,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmaddsub_pd() {
+    const unsafe fn test_mm512_maskz_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2299,7 +2304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmaddsub_pd() {
+    const unsafe fn test_mm512_mask3_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2311,7 +2316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmaddsub_pd() {
+    const unsafe fn test_mm256_mask_fmaddsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2323,7 +2328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmaddsub_pd() {
+    const unsafe fn test_mm256_maskz_fmaddsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2335,7 +2340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmaddsub_pd() {
+    const unsafe fn test_mm256_mask3_fmaddsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2347,7 +2352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmaddsub_pd() {
+    const unsafe fn test_mm_mask_fmaddsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2359,7 +2364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmaddsub_pd() {
+    const unsafe fn test_mm_maskz_fmaddsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2371,7 +2376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmaddsub_pd() {
+    const unsafe fn test_mm_mask3_fmaddsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2383,7 +2388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsubadd_pd() {
+    const unsafe fn test_mm512_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2393,7 +2398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsubadd_pd() {
+    const unsafe fn test_mm512_mask_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2405,7 +2410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsubadd_pd() {
+    const unsafe fn test_mm512_maskz_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2417,7 +2422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsubadd_pd() {
+    const unsafe fn test_mm512_mask3_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2429,7 +2434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fmsubadd_pd() {
+    const unsafe fn test_mm256_mask_fmsubadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2441,7 +2446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fmsubadd_pd() {
+    const unsafe fn test_mm256_maskz_fmsubadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2453,7 +2458,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fmsubadd_pd() {
+    const unsafe fn test_mm256_mask3_fmsubadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2465,7 +2470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fmsubadd_pd() {
+    const unsafe fn test_mm_mask_fmsubadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2477,7 +2482,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fmsubadd_pd() {
+    const unsafe fn test_mm_maskz_fmsubadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2489,7 +2494,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fmsubadd_pd() {
+    const unsafe fn test_mm_mask3_fmsubadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2501,7 +2506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmadd_pd() {
+    const unsafe fn test_mm512_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2511,7 +2516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmadd_pd() {
+    const unsafe fn test_mm512_mask_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2523,7 +2528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmadd_pd() {
+    const unsafe fn test_mm512_maskz_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2535,7 +2540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmadd_pd() {
+    const unsafe fn test_mm512_mask3_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2547,7 +2552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fnmadd_pd() {
+    const unsafe fn test_mm256_mask_fnmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2559,7 +2564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fnmadd_pd() {
+    const unsafe fn test_mm256_maskz_fnmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2571,7 +2576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fnmadd_pd() {
+    const unsafe fn test_mm256_mask3_fnmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2583,7 +2588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fnmadd_pd() {
+    const unsafe fn test_mm_mask_fnmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2595,7 +2600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fnmadd_pd() {
+    const unsafe fn test_mm_maskz_fnmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2607,7 +2612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fnmadd_pd() {
+    const unsafe fn test_mm_mask3_fnmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2619,7 +2624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmsub_pd() {
+    const unsafe fn test_mm512_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2629,7 +2634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmsub_pd() {
+    const unsafe fn test_mm512_mask_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2641,7 +2646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmsub_pd() {
+    const unsafe fn test_mm512_maskz_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2653,7 +2658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmsub_pd() {
+    const unsafe fn test_mm512_mask3_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2665,7 +2670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fnmsub_pd() {
+    const unsafe fn test_mm256_mask_fnmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2677,7 +2682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fnmsub_pd() {
+    const unsafe fn test_mm256_maskz_fnmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2689,7 +2694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask3_fnmsub_pd() {
+    const unsafe fn test_mm256_mask3_fnmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2701,7 +2706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fnmsub_pd() {
+    const unsafe fn test_mm_mask_fnmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2713,7 +2718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fnmsub_pd() {
+    const unsafe fn test_mm_maskz_fnmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2725,7 +2730,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask3_fnmsub_pd() {
+    const unsafe fn test_mm_mask3_fnmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -3764,7 +3769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi8_epi64() {
+    const unsafe fn test_mm512_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi8_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3772,7 +3777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi8_epi64() {
+    const unsafe fn test_mm512_mask_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
@@ -3783,7 +3788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi8_epi64() {
+    const unsafe fn test_mm512_maskz_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi8_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -3793,7 +3798,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi8_epi64() {
+    const unsafe fn test_mm256_mask_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
@@ -3804,7 +3809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi8_epi64() {
+    const unsafe fn test_mm256_maskz_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi8_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3814,7 +3819,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi8_epi64() {
+    const unsafe fn test_mm_mask_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepi8_epi64(src, 0, a);
@@ -3825,7 +3830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi8_epi64() {
+    const unsafe fn test_mm_maskz_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepi8_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3835,7 +3840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu8_epi64() {
+    const unsafe fn test_mm512_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu8_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3843,7 +3848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu8_epi64() {
+    const unsafe fn test_mm512_mask_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
@@ -3854,7 +3859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu8_epi64() {
+    const unsafe fn test_mm512_maskz_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu8_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -3864,7 +3869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu8_epi64() {
+    const unsafe fn test_mm256_mask_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
@@ -3875,7 +3880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu8_epi64() {
+    const unsafe fn test_mm256_maskz_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu8_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3885,7 +3890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu8_epi64() {
+    const unsafe fn test_mm_mask_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepu8_epi64(src, 0, a);
@@ -3896,7 +3901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu8_epi64() {
+    const unsafe fn test_mm_maskz_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu8_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3906,7 +3911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi16_epi64() {
+    const unsafe fn test_mm512_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi16_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3914,7 +3919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi16_epi64() {
+    const unsafe fn test_mm512_mask_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
@@ -3925,7 +3930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi16_epi64() {
+    const unsafe fn test_mm512_maskz_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi16_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -3935,7 +3940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi16_epi64() {
+    const unsafe fn test_mm256_mask_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
@@ -3946,7 +3951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi16_epi64() {
+    const unsafe fn test_mm256_maskz_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi16_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3956,7 +3961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi16_epi64() {
+    const unsafe fn test_mm_mask_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepi16_epi64(src, 0, a);
@@ -3967,7 +3972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi16_epi64() {
+    const unsafe fn test_mm_maskz_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepi16_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3977,7 +3982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu16_epi64() {
+    const unsafe fn test_mm512_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu16_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3985,7 +3990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu16_epi64() {
+    const unsafe fn test_mm512_mask_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
@@ -3996,7 +4001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu16_epi64() {
+    const unsafe fn test_mm512_maskz_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu16_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -4006,7 +4011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu16_epi64() {
+    const unsafe fn test_mm256_mask_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
@@ -4017,7 +4022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu16_epi64() {
+    const unsafe fn test_mm256_maskz_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu16_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4027,7 +4032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu16_epi64() {
+    const unsafe fn test_mm_mask_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepu16_epi64(src, 0, a);
@@ -4038,7 +4043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu16_epi64() {
+    const unsafe fn test_mm_maskz_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu16_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4048,7 +4053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi32_epi64() {
+    const unsafe fn test_mm512_cvtepi32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4056,7 +4061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_epi64() {
+    const unsafe fn test_mm512_mask_cvtepi32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
@@ -4067,7 +4072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi32_epi64() {
+    const unsafe fn test_mm512_maskz_cvtepi32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -4077,7 +4082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_epi64() {
+    const unsafe fn test_mm256_mask_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
@@ -4088,7 +4093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi32_epi64() {
+    const unsafe fn test_mm256_maskz_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let r = _mm256_maskz_cvtepi32_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4098,7 +4103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_epi64() {
+    const unsafe fn test_mm_mask_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let src = _mm_set1_epi64x(0);
         let r = _mm_mask_cvtepi32_epi64(src, 0, a);
@@ -4109,7 +4114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi32_epi64() {
+    const unsafe fn test_mm_maskz_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let r = _mm_maskz_cvtepi32_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4119,7 +4124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu32_epi64() {
+    const unsafe fn test_mm512_cvtepu32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4127,7 +4132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu32_epi64() {
+    const unsafe fn test_mm512_mask_cvtepu32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
@@ -4138,7 +4143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu32_epi64() {
+    const unsafe fn test_mm512_maskz_cvtepu32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu32_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -4148,7 +4153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu32_epi64() {
+    const unsafe fn test_mm256_mask_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
@@ -4159,7 +4164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu32_epi64() {
+    const unsafe fn test_mm256_maskz_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu32_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4169,7 +4174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu32_epi64() {
+    const unsafe fn test_mm_mask_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepu32_epi64(src, 0, a);
@@ -4180,7 +4185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu32_epi64() {
+    const unsafe fn test_mm_maskz_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_maskz_cvtepu32_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4190,7 +4195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi32_pd() {
+    const unsafe fn test_mm512_cvtepi32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4198,7 +4203,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_pd() {
+    const unsafe fn test_mm512_mask_cvtepi32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepi32_pd(src, 0, a);
@@ -4209,7 +4214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi32_pd() {
+    const unsafe fn test_mm512_maskz_cvtepi32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -4219,7 +4224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_pd() {
+    const unsafe fn test_mm256_mask_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm256_set1_pd(-1.);
         let r = _mm256_mask_cvtepi32_pd(src, 0, a);
@@ -4230,7 +4235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi32_pd() {
+    const unsafe fn test_mm256_maskz_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi32_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -4240,7 +4245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_pd() {
+    const unsafe fn test_mm_mask_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm_set1_pd(-1.);
         let r = _mm_mask_cvtepi32_pd(src, 0, a);
@@ -4251,7 +4256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi32_pd() {
+    const unsafe fn test_mm_maskz_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_maskz_cvtepi32_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -4261,7 +4266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu32_pd() {
+    const unsafe fn test_mm512_cvtepu32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4269,7 +4274,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu32_pd() {
+    const unsafe fn test_mm512_mask_cvtepu32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepu32_pd(src, 0, a);
@@ -4280,7 +4285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepu32_pd() {
+    const unsafe fn test_mm512_maskz_cvtepu32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu32_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -4290,7 +4295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtepu32_pd() {
+    const unsafe fn test_mm256_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_cvtepu32_pd(a);
         let e = _mm256_set_pd(12., 13., 14., 15.);
@@ -4298,7 +4303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu32_pd() {
+    const unsafe fn test_mm256_mask_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm256_set1_pd(-1.);
         let r = _mm256_mask_cvtepu32_pd(src, 0, a);
@@ -4309,7 +4314,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu32_pd() {
+    const unsafe fn test_mm256_maskz_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu32_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -4319,7 +4324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtepu32_pd() {
+    const unsafe fn test_mm_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_cvtepu32_pd(a);
         let e = _mm_set_pd(14., 15.);
@@ -4327,7 +4332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu32_pd() {
+    const unsafe fn test_mm_mask_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm_set1_pd(-1.);
         let r = _mm_mask_cvtepu32_pd(src, 0, a);
@@ -4338,7 +4343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu32_pd() {
+    const unsafe fn test_mm_maskz_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_maskz_cvtepu32_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -4348,7 +4353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi32lo_pd() {
+    const unsafe fn test_mm512_cvtepi32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32lo_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4356,7 +4361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32lo_pd() {
+    const unsafe fn test_mm512_mask_cvtepi32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
@@ -4367,7 +4372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepu32lo_pd() {
+    const unsafe fn test_mm512_cvtepu32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32lo_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4375,7 +4380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepu32lo_pd() {
+    const unsafe fn test_mm512_mask_cvtepu32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
@@ -4386,7 +4391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi64_epi32() {
+    const unsafe fn test_mm512_cvtepi64_epi32() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi64_epi32(a);
         let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4394,7 +4399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_epi32() {
+    const unsafe fn test_mm512_mask_cvtepi64_epi32() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
@@ -4405,7 +4410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi64_epi32() {
+    const unsafe fn test_mm512_maskz_cvtepi64_epi32() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi64_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4415,7 +4420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtepi64_epi32() {
+    const unsafe fn test_mm256_cvtepi64_epi32() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepi64_epi32(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -4423,7 +4428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_epi32() {
+    const unsafe fn test_mm256_mask_cvtepi64_epi32() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
@@ -4434,7 +4439,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi64_epi32() {
+    const unsafe fn test_mm256_maskz_cvtepi64_epi32() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4473,7 +4478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi64_epi16() {
+    const unsafe fn test_mm512_cvtepi64_epi16() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi64_epi16(a);
         let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4481,7 +4486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_epi16() {
+    const unsafe fn test_mm512_mask_cvtepi64_epi16() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi16(-1);
         let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
@@ -4492,7 +4497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi64_epi16() {
+    const unsafe fn test_mm512_maskz_cvtepi64_epi16() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -6449,42 +6454,42 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setzero_pd() {
+    const unsafe fn test_mm512_setzero_pd() {
         assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set1_epi64() {
+    const unsafe fn test_mm512_set1_epi64() {
         let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
         assert_eq_m512i(r, _mm512_set1_epi64(2));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set1_pd() {
+    const unsafe fn test_mm512_set1_pd() {
         let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
         assert_eq_m512d(expected, _mm512_set1_pd(2.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set4_epi64() {
+    const unsafe fn test_mm512_set4_epi64() {
         let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set4_pd() {
+    const unsafe fn test_mm512_set4_pd() {
         let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
         assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr4_epi64() {
+    const unsafe fn test_mm512_setr4_epi64() {
         let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr4_pd() {
+    const unsafe fn test_mm512_setr4_pd() {
         let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
         assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
     }
@@ -6709,7 +6714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmplt_epu64_mask() {
+    const unsafe fn test_mm512_cmplt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmplt_epu64_mask(a, b);
@@ -6717,7 +6722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmplt_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -6726,7 +6731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmplt_epu64_mask() {
+    const unsafe fn test_mm256_cmplt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 100);
         let b = _mm256_set1_epi64x(2);
         let r = _mm256_cmplt_epu64_mask(a, b);
@@ -6734,7 +6739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 100);
         let b = _mm256_set1_epi64x(2);
         let mask = 0b11111111;
@@ -6743,7 +6748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmplt_epu64_mask() {
+    const unsafe fn test_mm_cmplt_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(2);
         let r = _mm_cmplt_epu64_mask(a, b);
@@ -6751,7 +6756,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epu64_mask() {
+    const unsafe fn test_mm_mask_cmplt_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(2);
         let mask = 0b11111111;
@@ -6760,7 +6765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpgt_epu64_mask() {
+    const unsafe fn test_mm512_cmpgt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmpgt_epu64_mask(b, a);
@@ -6768,7 +6773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -6777,7 +6782,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epu64_mask() {
+    const unsafe fn test_mm256_cmpgt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_cmpgt_epu64_mask(a, b);
@@ -6785,7 +6790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6794,7 +6799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpgt_epu64_mask() {
+    const unsafe fn test_mm_cmpgt_epu64_mask() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmpgt_epu64_mask(a, b);
@@ -6802,7 +6807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epu64_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epu64_mask() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6811,7 +6816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmple_epu64_mask() {
+    const unsafe fn test_mm512_cmple_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -6821,7 +6826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmple_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmple_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -6829,7 +6834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmple_epu64_mask() {
+    const unsafe fn test_mm256_cmple_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 1);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_cmple_epu64_mask(a, b);
@@ -6837,7 +6842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmple_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 1);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6846,7 +6851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmple_epu64_mask() {
+    const unsafe fn test_mm_cmple_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmple_epu64_mask(a, b);
@@ -6854,7 +6859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epu64_mask() {
+    const unsafe fn test_mm_mask_cmple_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6863,7 +6868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpge_epu64_mask() {
+    const unsafe fn test_mm512_cmpge_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -6873,7 +6878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpge_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b11111111;
@@ -6882,7 +6887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpge_epu64_mask() {
+    const unsafe fn test_mm256_cmpge_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_cmpge_epu64_mask(a, b);
@@ -6890,7 +6895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6899,7 +6904,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpge_epu64_mask() {
+    const unsafe fn test_mm_cmpge_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmpge_epu64_mask(a, b);
@@ -6907,7 +6912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epu64_mask() {
+    const unsafe fn test_mm_mask_cmpge_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6916,7 +6921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpeq_epu64_mask() {
+    const unsafe fn test_mm512_cmpeq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpeq_epu64_mask(b, a);
@@ -6924,7 +6929,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -6933,7 +6938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epu64_mask() {
+    const unsafe fn test_mm256_cmpeq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let m = _mm256_cmpeq_epu64_mask(b, a);
@@ -6941,7 +6946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -6950,7 +6955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpeq_epu64_mask() {
+    const unsafe fn test_mm_cmpeq_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let m = _mm_cmpeq_epu64_mask(b, a);
@@ -6958,7 +6963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epu64_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let mask = 0b11111111;
@@ -6967,7 +6972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpneq_epu64_mask() {
+    const unsafe fn test_mm512_cmpneq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpneq_epu64_mask(b, a);
@@ -6975,7 +6980,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -6984,7 +6989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epu64_mask() {
+    const unsafe fn test_mm256_cmpneq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let r = _mm256_cmpneq_epu64_mask(b, a);
@@ -6992,7 +6997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -7001,7 +7006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpneq_epu64_mask() {
+    const unsafe fn test_mm_cmpneq_epu64_mask() {
         let a = _mm_set_epi64x(-1, u64::MAX as i64);
         let b = _mm_set_epi64x(13, 42);
         let r = _mm_cmpneq_epu64_mask(b, a);
@@ -7009,7 +7014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epu64_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epu64_mask() {
         let a = _mm_set_epi64x(-1, u64::MAX as i64);
         let b = _mm_set_epi64x(13, 42);
         let mask = 0b11111111;
@@ -7018,7 +7023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_epu64_mask() {
+    const unsafe fn test_mm512_cmp_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7026,7 +7031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_epu64_mask() {
+    const unsafe fn test_mm512_mask_cmp_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -7035,7 +7040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmp_epu64_mask() {
+    const unsafe fn test_mm256_cmp_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 100);
         let b = _mm256_set1_epi64x(1);
         let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7043,7 +7048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epu64_mask() {
+    const unsafe fn test_mm256_mask_cmp_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 100);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7052,7 +7057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmp_epu64_mask() {
+    const unsafe fn test_mm_cmp_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7060,7 +7065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epu64_mask() {
+    const unsafe fn test_mm_mask_cmp_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7069,7 +7074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmplt_epi64_mask() {
+    const unsafe fn test_mm512_cmplt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmplt_epi64_mask(a, b);
@@ -7077,7 +7082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmplt_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01100110;
@@ -7086,7 +7091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmplt_epi64_mask() {
+    const unsafe fn test_mm256_cmplt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, -13);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmplt_epi64_mask(a, b);
@@ -7094,7 +7099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, -13);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7103,7 +7108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmplt_epi64_mask() {
+    const unsafe fn test_mm_cmplt_epi64_mask() {
         let a = _mm_set_epi64x(-1, -13);
         let b = _mm_set1_epi64x(-1);
         let r = _mm_cmplt_epi64_mask(a, b);
@@ -7111,7 +7116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epi64_mask() {
+    const unsafe fn test_mm_mask_cmplt_epi64_mask() {
         let a = _mm_set_epi64x(-1, -13);
         let b = _mm_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7120,7 +7125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpgt_epi64_mask() {
+    const unsafe fn test_mm512_cmpgt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmpgt_epi64_mask(b, a);
@@ -7128,7 +7133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01100110;
@@ -7137,7 +7142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epi64_mask() {
+    const unsafe fn test_mm256_cmpgt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmpgt_epi64_mask(a, b);
@@ -7145,7 +7150,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7154,7 +7159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpgt_epi64_mask() {
+    const unsafe fn test_mm_cmpgt_epi64_mask() {
         let a = _mm_set_epi64x(0, -1);
         let b = _mm_set1_epi64x(-1);
         let r = _mm_cmpgt_epi64_mask(a, b);
@@ -7162,7 +7167,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epi64_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epi64_mask() {
         let a = _mm_set_epi64x(0, -1);
         let b = _mm_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7171,7 +7176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmple_epi64_mask() {
+    const unsafe fn test_mm512_cmple_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -7181,7 +7186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmple_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmple_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -7189,7 +7194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmple_epi64_mask() {
+    const unsafe fn test_mm256_cmple_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmple_epi64_mask(a, b);
@@ -7197,7 +7202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmple_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7206,7 +7211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmple_epi64_mask() {
+    const unsafe fn test_mm_cmple_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmple_epi64_mask(a, b);
@@ -7214,7 +7219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epi64_mask() {
+    const unsafe fn test_mm_mask_cmple_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7223,7 +7228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpge_epi64_mask() {
+    const unsafe fn test_mm512_cmpge_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -7233,7 +7238,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpge_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b11111111;
@@ -7242,7 +7247,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpge_epi64_mask() {
+    const unsafe fn test_mm256_cmpge_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmpge_epi64_mask(a, b);
@@ -7250,7 +7255,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7259,7 +7264,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpge_epi64_mask() {
+    const unsafe fn test_mm_cmpge_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(-1);
         let r = _mm_cmpge_epi64_mask(a, b);
@@ -7267,7 +7272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epi64_mask() {
+    const unsafe fn test_mm_mask_cmpge_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7276,7 +7281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpeq_epi64_mask() {
+    const unsafe fn test_mm512_cmpeq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpeq_epi64_mask(b, a);
@@ -7284,7 +7289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -7293,7 +7298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epi64_mask() {
+    const unsafe fn test_mm256_cmpeq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let m = _mm256_cmpeq_epi64_mask(b, a);
@@ -7301,7 +7306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -7310,7 +7315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpeq_epi64_mask() {
+    const unsafe fn test_mm_cmpeq_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let m = _mm_cmpeq_epi64_mask(b, a);
@@ -7318,7 +7323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epi64_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let mask = 0b11111111;
@@ -7327,19 +7332,19 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_set_epi64() {
+    const unsafe fn test_mm512_set_epi64() {
         let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_setr_epi64() {
+    const unsafe fn test_mm512_setr_epi64() {
         let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpneq_epi64_mask() {
+    const unsafe fn test_mm512_cmpneq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpneq_epi64_mask(b, a);
@@ -7347,7 +7352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -7356,7 +7361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epi64_mask() {
+    const unsafe fn test_mm256_cmpneq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let r = _mm256_cmpneq_epi64_mask(b, a);
@@ -7364,7 +7369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -7373,7 +7378,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmpneq_epi64_mask() {
+    const unsafe fn test_mm_cmpneq_epi64_mask() {
         let a = _mm_set_epi64x(-1, 13);
         let b = _mm_set_epi64x(13, 42);
         let r = _mm_cmpneq_epi64_mask(b, a);
@@ -7381,7 +7386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epi64_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epi64_mask() {
         let a = _mm_set_epi64x(-1, 13);
         let b = _mm_set_epi64x(13, 42);
         let mask = 0b11111111;
@@ -7390,7 +7395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_epi64_mask() {
+    const unsafe fn test_mm512_cmp_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7398,7 +7403,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_epi64_mask() {
+    const unsafe fn test_mm512_mask_cmp_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01100110;
@@ -7407,7 +7412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmp_epi64_mask() {
+    const unsafe fn test_mm256_cmp_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(1);
         let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7415,7 +7420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epi64_mask() {
+    const unsafe fn test_mm256_mask_cmp_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7424,7 +7429,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmp_epi64_mask() {
+    const unsafe fn test_mm_cmp_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7432,7 +7437,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epi64_mask() {
+    const unsafe fn test_mm_mask_cmp_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -8313,7 +8318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rol_epi64() {
+    const unsafe fn test_mm512_rol_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8329,7 +8334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rol_epi64() {
+    const unsafe fn test_mm512_mask_rol_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8347,7 +8352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rol_epi64() {
+    const unsafe fn test_mm512_maskz_rol_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8361,7 +8366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rol_epi64() {
+    const unsafe fn test_mm256_rol_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_rol_epi64::<1>(a);
         let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
@@ -8369,7 +8374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rol_epi64() {
+    const unsafe fn test_mm256_mask_rol_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8379,7 +8384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rol_epi64() {
+    const unsafe fn test_mm256_maskz_rol_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_maskz_rol_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8389,7 +8394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rol_epi64() {
+    const unsafe fn test_mm_rol_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_rol_epi64::<1>(a);
         let e = _mm_set_epi64x(1 << 0, 1 << 33);
@@ -8397,7 +8402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rol_epi64() {
+    const unsafe fn test_mm_mask_rol_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_mask_rol_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8407,7 +8412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rol_epi64() {
+    const unsafe fn test_mm_maskz_rol_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_maskz_rol_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8417,7 +8422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_ror_epi64() {
+    const unsafe fn test_mm512_ror_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0,  1 << 32, 1 << 32, 1 << 32,
@@ -8433,7 +8438,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_ror_epi64() {
+    const unsafe fn test_mm512_mask_ror_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0,  1 << 32, 1 << 32, 1 << 32,
@@ -8451,7 +8456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_ror_epi64() {
+    const unsafe fn test_mm512_maskz_ror_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8465,7 +8470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_ror_epi64() {
+    const unsafe fn test_mm256_ror_epi64() {
         let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_ror_epi64::<1>(a);
         let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
@@ -8473,7 +8478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_ror_epi64() {
+    const unsafe fn test_mm256_mask_ror_epi64() {
         let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8483,7 +8488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_ror_epi64() {
+    const unsafe fn test_mm256_maskz_ror_epi64() {
         let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_maskz_ror_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8493,7 +8498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_ror_epi64() {
+    const unsafe fn test_mm_ror_epi64() {
         let a = _mm_set_epi64x(1 << 0, 1 << 32);
         let r = _mm_ror_epi64::<1>(a);
         let e = _mm_set_epi64x(1 << 63, 1 << 31);
@@ -8501,7 +8506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_ror_epi64() {
+    const unsafe fn test_mm_mask_ror_epi64() {
         let a = _mm_set_epi64x(1 << 0, 1 << 32);
         let r = _mm_mask_ror_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8511,7 +8516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_ror_epi64() {
+    const unsafe fn test_mm_maskz_ror_epi64() {
         let a = _mm_set_epi64x(1 << 0, 1 << 32);
         let r = _mm_maskz_ror_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8521,7 +8526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_slli_epi64() {
+    const unsafe fn test_mm512_slli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8537,7 +8542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_slli_epi64() {
+    const unsafe fn test_mm512_mask_slli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8555,7 +8560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_slli_epi64() {
+    const unsafe fn test_mm512_maskz_slli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8569,7 +8574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_slli_epi64() {
+    const unsafe fn test_mm256_mask_slli_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8579,7 +8584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_slli_epi64() {
+    const unsafe fn test_mm256_maskz_slli_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_maskz_slli_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8589,7 +8594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_slli_epi64() {
+    const unsafe fn test_mm_mask_slli_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_mask_slli_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8599,7 +8604,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_slli_epi64() {
+    const unsafe fn test_mm_maskz_slli_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_maskz_slli_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8609,7 +8614,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srli_epi64() {
+    const unsafe fn test_mm512_srli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0, 1 << 32, 1 << 32, 1 << 32,
@@ -8625,7 +8630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srli_epi64() {
+    const unsafe fn test_mm512_mask_srli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0, 1 << 32, 1 << 32, 1 << 32,
@@ -8643,7 +8648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srli_epi64() {
+    const unsafe fn test_mm512_maskz_srli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8657,7 +8662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srli_epi64() {
+    const unsafe fn test_mm256_mask_srli_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8667,7 +8672,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srli_epi64() {
+    const unsafe fn test_mm256_maskz_srli_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_maskz_srli_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8677,7 +8682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srli_epi64() {
+    const unsafe fn test_mm_mask_srli_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_mask_srli_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8687,7 +8692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srli_epi64() {
+    const unsafe fn test_mm_maskz_srli_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_maskz_srli_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8697,7 +8702,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rolv_epi64() {
+    const unsafe fn test_mm512_rolv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -8714,7 +8719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rolv_epi64() {
+    const unsafe fn test_mm512_mask_rolv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -8733,7 +8738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rolv_epi64() {
+    const unsafe fn test_mm512_maskz_rolv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8748,7 +8753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rolv_epi64() {
+    const unsafe fn test_mm256_rolv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_rolv_epi64(a, b);
@@ -8757,7 +8762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rolv_epi64() {
+    const unsafe fn test_mm256_mask_rolv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_rolv_epi64(a, 0, a, b);
@@ -8768,7 +8773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rolv_epi64() {
+    const unsafe fn test_mm256_maskz_rolv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_rolv_epi64(0, a, b);
@@ -8779,7 +8784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rolv_epi64() {
+    const unsafe fn test_mm_rolv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 63);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_rolv_epi64(a, b);
@@ -8788,7 +8793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rolv_epi64() {
+    const unsafe fn test_mm_mask_rolv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 63);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_mask_rolv_epi64(a, 0, a, b);
@@ -8799,7 +8804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rolv_epi64() {
+    const unsafe fn test_mm_maskz_rolv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 63);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_rolv_epi64(0, a, b);
@@ -8810,7 +8815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rorv_epi64() {
+    const unsafe fn test_mm512_rorv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -8827,7 +8832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rorv_epi64() {
+    const unsafe fn test_mm512_mask_rorv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -8846,7 +8851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rorv_epi64() {
+    const unsafe fn test_mm512_maskz_rorv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8861,7 +8866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rorv_epi64() {
+    const unsafe fn test_mm256_rorv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_rorv_epi64(a, b);
@@ -8870,7 +8875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rorv_epi64() {
+    const unsafe fn test_mm256_mask_rorv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_rorv_epi64(a, 0, a, b);
@@ -8881,7 +8886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rorv_epi64() {
+    const unsafe fn test_mm256_maskz_rorv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_rorv_epi64(0, a, b);
@@ -8892,7 +8897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rorv_epi64() {
+    const unsafe fn test_mm_rorv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 0);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_rorv_epi64(a, b);
@@ -8901,7 +8906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rorv_epi64() {
+    const unsafe fn test_mm_mask_rorv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 0);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_mask_rorv_epi64(a, 0, a, b);
@@ -8912,7 +8917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rorv_epi64() {
+    const unsafe fn test_mm_maskz_rorv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 0);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_rorv_epi64(0, a, b);
@@ -8923,7 +8928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sllv_epi64() {
+    const unsafe fn test_mm512_sllv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -8940,7 +8945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sllv_epi64() {
+    const unsafe fn test_mm512_mask_sllv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 63, 1 << 32,
@@ -8959,7 +8964,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sllv_epi64() {
+    const unsafe fn test_mm512_maskz_sllv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8974,7 +8979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sllv_epi64() {
+    const unsafe fn test_mm256_mask_sllv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
         let count = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_sllv_epi64(a, 0, a, count);
@@ -8985,7 +8990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sllv_epi64() {
+    const unsafe fn test_mm256_maskz_sllv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
         let count = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_sllv_epi64(0, a, count);
@@ -8996,7 +9001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sllv_epi64() {
+    const unsafe fn test_mm_mask_sllv_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let count = _mm_set_epi64x(2, 3);
         let r = _mm_mask_sllv_epi64(a, 0, a, count);
@@ -9007,7 +9012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sllv_epi64() {
+    const unsafe fn test_mm_maskz_sllv_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let count = _mm_set_epi64x(2, 3);
         let r = _mm_maskz_sllv_epi64(0, a, count);
@@ -9018,7 +9023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srlv_epi64() {
+    const unsafe fn test_mm512_srlv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -9035,7 +9040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srlv_epi64() {
+    const unsafe fn test_mm512_mask_srlv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -9054,7 +9059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srlv_epi64() {
+    const unsafe fn test_mm512_maskz_srlv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -9069,7 +9074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srlv_epi64() {
+    const unsafe fn test_mm256_mask_srlv_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_mask_srlv_epi64(a, 0, a, count);
@@ -9080,7 +9085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srlv_epi64() {
+    const unsafe fn test_mm256_maskz_srlv_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_srlv_epi64(0, a, count);
@@ -9091,7 +9096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srlv_epi64() {
+    const unsafe fn test_mm_mask_srlv_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_mask_srlv_epi64(a, 0, a, count);
@@ -9102,7 +9107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srlv_epi64() {
+    const unsafe fn test_mm_maskz_srlv_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_maskz_srlv_epi64(0, a, count);
@@ -9399,7 +9404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srav_epi64() {
+    const unsafe fn test_mm512_srav_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
         let r = _mm512_srav_epi64(a, count);
@@ -9408,7 +9413,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srav_epi64() {
+    const unsafe fn test_mm512_mask_srav_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
         let r = _mm512_mask_srav_epi64(a, 0, a, count);
@@ -9419,7 +9424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srav_epi64() {
+    const unsafe fn test_mm512_maskz_srav_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
         let r = _mm512_maskz_srav_epi64(0, a, count);
@@ -9430,7 +9435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_srav_epi64() {
+    const unsafe fn test_mm256_srav_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_srav_epi64(a, count);
@@ -9439,7 +9444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srav_epi64() {
+    const unsafe fn test_mm256_mask_srav_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_mask_srav_epi64(a, 0, a, count);
@@ -9450,7 +9455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srav_epi64() {
+    const unsafe fn test_mm256_maskz_srav_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_srav_epi64(0, a, count);
@@ -9461,7 +9466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_srav_epi64() {
+    const unsafe fn test_mm_srav_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_srav_epi64(a, count);
@@ -9470,7 +9475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srav_epi64() {
+    const unsafe fn test_mm_mask_srav_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_mask_srav_epi64(a, 0, a, count);
@@ -9481,7 +9486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srav_epi64() {
+    const unsafe fn test_mm_maskz_srav_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_maskz_srav_epi64(0, a, count);
@@ -9492,7 +9497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srai_epi64() {
+    const unsafe fn test_mm512_srai_epi64() {
         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
         let r = _mm512_srai_epi64::<2>(a);
         let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
@@ -9500,7 +9505,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srai_epi64() {
+    const unsafe fn test_mm512_mask_srai_epi64() {
         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
         let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -9510,7 +9515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srai_epi64() {
+    const unsafe fn test_mm512_maskz_srai_epi64() {
         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
         let r = _mm512_maskz_srai_epi64::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -9520,7 +9525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_srai_epi64() {
+    const unsafe fn test_mm256_srai_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_srai_epi64::<1>(a);
         let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
@@ -9528,7 +9533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srai_epi64() {
+    const unsafe fn test_mm256_mask_srai_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -9538,7 +9543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srai_epi64() {
+    const unsafe fn test_mm256_maskz_srai_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_maskz_srai_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -9548,7 +9553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_srai_epi64() {
+    const unsafe fn test_mm_srai_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_srai_epi64::<1>(a);
         let e = _mm_set_epi64x(1 << 4, 0);
@@ -9556,7 +9561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srai_epi64() {
+    const unsafe fn test_mm_mask_srai_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_mask_srai_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -9566,7 +9571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srai_epi64() {
+    const unsafe fn test_mm_maskz_srai_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_maskz_srai_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -9576,7 +9581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permute_pd() {
+    const unsafe fn test_mm512_permute_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_permute_pd::<0b11_11_11_11>(a);
         let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
@@ -9584,7 +9589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permute_pd() {
+    const unsafe fn test_mm512_mask_permute_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
         assert_eq_m512d(r, a);
@@ -9594,7 +9599,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permute_pd() {
+    const unsafe fn test_mm512_maskz_permute_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -9604,7 +9609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permute_pd() {
+    const unsafe fn test_mm256_mask_permute_pd() {
         let a = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
         assert_eq_m256d(r, a);
@@ -9614,7 +9619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permute_pd() {
+    const unsafe fn test_mm256_maskz_permute_pd() {
         let a = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -9624,7 +9629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permute_pd() {
+    const unsafe fn test_mm_mask_permute_pd() {
         let a = _mm_set_pd(1., 0.);
         let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
         assert_eq_m128d(r, a);
@@ -9634,7 +9639,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permute_pd() {
+    const unsafe fn test_mm_maskz_permute_pd() {
         let a = _mm_set_pd(1., 0.);
         let r = _mm_maskz_permute_pd::<0b11>(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -9644,7 +9649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutex_epi64() {
+    const unsafe fn test_mm512_permutex_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
         let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
@@ -9652,7 +9657,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutex_epi64() {
+    const unsafe fn test_mm512_mask_permutex_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -9662,7 +9667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutex_epi64() {
+    const unsafe fn test_mm512_maskz_permutex_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -9672,7 +9677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutex_epi64() {
+    const unsafe fn test_mm256_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
         let e = _mm256_set_epi64x(3, 3, 3, 3);
@@ -9680,7 +9685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutex_epi64() {
+    const unsafe fn test_mm256_mask_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -9690,7 +9695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex_epi64() {
+    const unsafe fn test_mm256_maskz_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -9700,7 +9705,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutex_pd() {
+    const unsafe fn test_mm512_permutex_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
         let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
@@ -9708,7 +9713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutex_pd() {
+    const unsafe fn test_mm512_mask_permutex_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
         assert_eq_m512d(r, a);
@@ -9718,7 +9723,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutex_pd() {
+    const unsafe fn test_mm512_maskz_permutex_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -9728,7 +9733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutex_pd() {
+    const unsafe fn test_mm256_permutex_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
         let e = _mm256_set_pd(0., 0., 0., 0.);
@@ -9736,7 +9741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutex_pd() {
+    const unsafe fn test_mm256_mask_permutex_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
         assert_eq_m256d(r, a);
@@ -9746,7 +9751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex_pd() {
+    const unsafe fn test_mm256_maskz_permutex_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -10231,7 +10236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_pd() {
+    const unsafe fn test_mm256_mask_shuffle_pd() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
@@ -10242,7 +10247,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_pd() {
+    const unsafe fn test_mm256_maskz_shuffle_pd() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
@@ -10253,7 +10258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_shuffle_pd() {
+    const unsafe fn test_mm_mask_shuffle_pd() {
         let a = _mm_set_pd(1., 4.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
@@ -10264,7 +10269,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_shuffle_pd() {
+    const unsafe fn test_mm_maskz_shuffle_pd() {
         let a = _mm_set_pd(1., 4.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
@@ -10275,7 +10280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_i64x2() {
+    const unsafe fn test_mm512_shuffle_i64x2() {
         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
@@ -10284,7 +10289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_i64x2() {
+    const unsafe fn test_mm512_mask_shuffle_i64x2() {
         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
@@ -10295,7 +10300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_i64x2() {
+    const unsafe fn test_mm512_maskz_shuffle_i64x2() {
         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
@@ -10306,7 +10311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_shuffle_i64x2() {
+    const unsafe fn test_mm256_shuffle_i64x2() {
         let a = _mm256_set_epi64x(1, 4, 5, 8);
         let b = _mm256_set_epi64x(2, 3, 6, 7);
         let r = _mm256_shuffle_i64x2::<0b00>(a, b);
@@ -10315,7 +10320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_i64x2() {
+    const unsafe fn test_mm256_mask_shuffle_i64x2() {
         let a = _mm256_set_epi64x(1, 4, 5, 8);
         let b = _mm256_set_epi64x(2, 3, 6, 7);
         let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
@@ -10326,7 +10331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_i64x2() {
+    const unsafe fn test_mm256_maskz_shuffle_i64x2() {
         let a = _mm256_set_epi64x(1, 4, 5, 8);
         let b = _mm256_set_epi64x(2, 3, 6, 7);
         let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
@@ -10337,7 +10342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_shuffle_f64x2() {
+    const unsafe fn test_mm512_shuffle_f64x2() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
@@ -10346,7 +10351,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_shuffle_f64x2() {
+    const unsafe fn test_mm512_mask_shuffle_f64x2() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
@@ -10357,7 +10362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_shuffle_f64x2() {
+    const unsafe fn test_mm512_maskz_shuffle_f64x2() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
@@ -10368,7 +10373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_shuffle_f64x2() {
+    const unsafe fn test_mm256_shuffle_f64x2() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_shuffle_f64x2::<0b00>(a, b);
@@ -10377,7 +10382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_f64x2() {
+    const unsafe fn test_mm256_mask_shuffle_f64x2() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
@@ -10388,7 +10393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_f64x2() {
+    const unsafe fn test_mm256_maskz_shuffle_f64x2() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
@@ -10399,7 +10404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_movedup_pd() {
+    const unsafe fn test_mm512_movedup_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_movedup_pd(a);
         let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
@@ -10407,7 +10412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_movedup_pd() {
+    const unsafe fn test_mm512_mask_movedup_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_mask_movedup_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -10417,7 +10422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_movedup_pd() {
+    const unsafe fn test_mm512_maskz_movedup_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_movedup_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -10427,7 +10432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_movedup_pd() {
+    const unsafe fn test_mm256_mask_movedup_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_mask_movedup_pd(a, 0, a);
         assert_eq_m256d(r, a);
@@ -10437,7 +10442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_movedup_pd() {
+    const unsafe fn test_mm256_maskz_movedup_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_movedup_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -10447,7 +10452,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_movedup_pd() {
+    const unsafe fn test_mm_mask_movedup_pd() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_mask_movedup_pd(a, 0, a);
         assert_eq_m128d(r, a);
@@ -10457,7 +10462,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_movedup_pd() {
+    const unsafe fn test_mm_maskz_movedup_pd() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_maskz_movedup_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -10467,7 +10472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_inserti64x4() {
+    const unsafe fn test_mm512_inserti64x4() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_inserti64x4::<1>(a, b);
@@ -10476,7 +10481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_inserti64x4() {
+    const unsafe fn test_mm512_mask_inserti64x4() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
@@ -10487,7 +10492,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_inserti64x4() {
+    const unsafe fn test_mm512_maskz_inserti64x4() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
@@ -10498,7 +10503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_insertf64x4() {
+    const unsafe fn test_mm512_insertf64x4() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_insertf64x4::<1>(a, b);
@@ -10507,7 +10512,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_insertf64x4() {
+    const unsafe fn test_mm512_mask_insertf64x4() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
@@ -10518,7 +10523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_insertf64x4() {
+    const unsafe fn test_mm512_maskz_insertf64x4() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
@@ -10529,21 +10534,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castpd128_pd512() {
+    const unsafe fn test_mm512_castpd128_pd512() {
         let a = _mm_setr_pd(17., 18.);
         let r = _mm512_castpd128_pd512(a);
         assert_eq_m128d(_mm512_castpd512_pd128(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castpd256_pd512() {
+    const unsafe fn test_mm512_castpd256_pd512() {
         let a = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_castpd256_pd512(a);
         assert_eq_m256d(_mm512_castpd512_pd256(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_zextpd128_pd512() {
+    const unsafe fn test_mm512_zextpd128_pd512() {
         let a = _mm_setr_pd(17., 18.);
         let r = _mm512_zextpd128_pd512(a);
         let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
@@ -10551,7 +10556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_zextpd256_pd512() {
+    const unsafe fn test_mm512_zextpd256_pd512() {
         let a = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_zextpd256_pd512(a);
         let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
@@ -10559,7 +10564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castpd512_pd128() {
+    const unsafe fn test_mm512_castpd512_pd128() {
         let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
         let r = _mm512_castpd512_pd128(a);
         let e = _mm_setr_pd(17., 18.);
@@ -10567,7 +10572,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castpd512_pd256() {
+    const unsafe fn test_mm512_castpd512_pd256() {
         let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
         let r = _mm512_castpd512_pd256(a);
         let e = _mm256_setr_pd(17., 18., 19., 20.);
@@ -10575,7 +10580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castpd_ps() {
+    const unsafe fn test_mm512_castpd_ps() {
         let a = _mm512_set1_pd(1.);
         let r = _mm512_castpd_ps(a);
         let e = _mm512_set_ps(
@@ -10586,7 +10591,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castpd_si512() {
+    const unsafe fn test_mm512_castpd_si512() {
         let a = _mm512_set1_pd(1.);
         let r = _mm512_castpd_si512(a);
         let e = _mm512_set_epi32(
@@ -10597,21 +10602,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castsi128_si512() {
+    const unsafe fn test_mm512_castsi128_si512() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_castsi128_si512(a);
         assert_eq_m128i(_mm512_castsi512_si128(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castsi256_si512() {
+    const unsafe fn test_mm512_castsi256_si512() {
         let a = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_castsi256_si512(a);
         assert_eq_m256i(_mm512_castsi512_si256(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_zextsi128_si512() {
+    const unsafe fn test_mm512_zextsi128_si512() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_zextsi128_si512(a);
         let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
@@ -10619,7 +10624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_zextsi256_si512() {
+    const unsafe fn test_mm512_zextsi256_si512() {
         let a = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_zextsi256_si512(a);
         let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
@@ -10627,7 +10632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castsi512_si128() {
+    const unsafe fn test_mm512_castsi512_si128() {
         let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
         let r = _mm512_castsi512_si128(a);
         let e = _mm_setr_epi64x(17, 18);
@@ -10635,7 +10640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castsi512_si256() {
+    const unsafe fn test_mm512_castsi512_si256() {
         let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
         let r = _mm512_castsi512_si256(a);
         let e = _mm256_setr_epi64x(17, 18, 19, 20);
@@ -10643,7 +10648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castsi512_ps() {
+    const unsafe fn test_mm512_castsi512_ps() {
         let a = _mm512_set1_epi64(1 << 62);
         let r = _mm512_castsi512_ps(a);
         let e = _mm512_set_ps(
@@ -10653,7 +10658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_castsi512_pd() {
+    const unsafe fn test_mm512_castsi512_pd() {
         let a = _mm512_set1_epi64(1 << 62);
         let r = _mm512_castsi512_pd(a);
         let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
@@ -10661,7 +10666,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcastq_epi64() {
+    const unsafe fn test_mm512_broadcastq_epi64() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_broadcastq_epi64(a);
         let e = _mm512_set1_epi64(17);
@@ -10669,7 +10674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcastq_epi64() {
+    const unsafe fn test_mm512_mask_broadcastq_epi64() {
         let src = _mm512_set1_epi64(18);
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_mask_broadcastq_epi64(src, 0, a);
@@ -10680,7 +10685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcastq_epi64() {
+    const unsafe fn test_mm512_maskz_broadcastq_epi64() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_maskz_broadcastq_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -10690,7 +10695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_broadcastq_epi64() {
+    const unsafe fn test_mm256_mask_broadcastq_epi64() {
         let src = _mm256_set1_epi64x(18);
         let a = _mm_set_epi64x(17, 18);
         let r = _mm256_mask_broadcastq_epi64(src, 0, a);
@@ -10701,7 +10706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcastq_epi64() {
+    const unsafe fn test_mm256_maskz_broadcastq_epi64() {
         let a = _mm_set_epi64x(17, 18);
         let r = _mm256_maskz_broadcastq_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -10711,7 +10716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_broadcastq_epi64() {
+    const unsafe fn test_mm_mask_broadcastq_epi64() {
         let src = _mm_set1_epi64x(18);
         let a = _mm_set_epi64x(17, 18);
         let r = _mm_mask_broadcastq_epi64(src, 0, a);
@@ -10722,7 +10727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_broadcastq_epi64() {
+    const unsafe fn test_mm_maskz_broadcastq_epi64() {
         let a = _mm_set_epi64x(17, 18);
         let r = _mm_maskz_broadcastq_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -10732,7 +10737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcastsd_pd() {
+    const unsafe fn test_mm512_broadcastsd_pd() {
         let a = _mm_set_pd(17., 18.);
         let r = _mm512_broadcastsd_pd(a);
         let e = _mm512_set1_pd(18.);
@@ -10740,7 +10745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcastsd_pd() {
+    const unsafe fn test_mm512_mask_broadcastsd_pd() {
         let src = _mm512_set1_pd(18.);
         let a = _mm_set_pd(17., 18.);
         let r = _mm512_mask_broadcastsd_pd(src, 0, a);
@@ -10751,7 +10756,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcastsd_pd() {
+    const unsafe fn test_mm512_maskz_broadcastsd_pd() {
         let a = _mm_set_pd(17., 18.);
         let r = _mm512_maskz_broadcastsd_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -10761,7 +10766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_broadcastsd_pd() {
+    const unsafe fn test_mm256_mask_broadcastsd_pd() {
         let src = _mm256_set1_pd(18.);
         let a = _mm_set_pd(17., 18.);
         let r = _mm256_mask_broadcastsd_pd(src, 0, a);
@@ -10772,7 +10777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcastsd_pd() {
+    const unsafe fn test_mm256_maskz_broadcastsd_pd() {
         let a = _mm_set_pd(17., 18.);
         let r = _mm256_maskz_broadcastsd_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -10782,7 +10787,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcast_i64x4() {
+    const unsafe fn test_mm512_broadcast_i64x4() {
         let a = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm512_broadcast_i64x4(a);
         let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
@@ -10790,7 +10795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcast_i64x4() {
+    const unsafe fn test_mm512_mask_broadcast_i64x4() {
         let src = _mm512_set1_epi64(18);
         let a = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm512_mask_broadcast_i64x4(src, 0, a);
@@ -10801,7 +10806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcast_i64x4() {
+    const unsafe fn test_mm512_maskz_broadcast_i64x4() {
         let a = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm512_maskz_broadcast_i64x4(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -10811,7 +10816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_broadcast_f64x4() {
+    const unsafe fn test_mm512_broadcast_f64x4() {
         let a = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm512_broadcast_f64x4(a);
         let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
@@ -10819,7 +10824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_broadcast_f64x4() {
+    const unsafe fn test_mm512_mask_broadcast_f64x4() {
         let src = _mm512_set1_pd(18.);
         let a = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm512_mask_broadcast_f64x4(src, 0, a);
@@ -10830,7 +10835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_broadcast_f64x4() {
+    const unsafe fn test_mm512_maskz_broadcast_f64x4() {
         let a = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm512_maskz_broadcast_f64x4(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -10840,7 +10845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_blend_epi64() {
+    const unsafe fn test_mm512_mask_blend_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(2);
         let r = _mm512_mask_blend_epi64(0b11110000, a, b);
@@ -10849,7 +10854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_blend_epi64() {
+    const unsafe fn test_mm256_mask_blend_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(2);
         let r = _mm256_mask_blend_epi64(0b00001111, a, b);
@@ -10858,7 +10863,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_blend_epi64() {
+    const unsafe fn test_mm_mask_blend_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(2);
         let r = _mm_mask_blend_epi64(0b00000011, a, b);
@@ -10867,7 +10872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_blend_pd() {
+    const unsafe fn test_mm512_mask_blend_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_mask_blend_pd(0b11110000, a, b);
@@ -10876,7 +10881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_blend_pd() {
+    const unsafe fn test_mm256_mask_blend_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(2.);
         let r = _mm256_mask_blend_pd(0b00001111, a, b);
@@ -10885,7 +10890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_blend_pd() {
+    const unsafe fn test_mm_mask_blend_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let r = _mm_mask_blend_pd(0b00000011, a, b);
@@ -10894,7 +10899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpackhi_epi64() {
+    const unsafe fn test_mm512_unpackhi_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_unpackhi_epi64(a, b);
@@ -10903,7 +10908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpackhi_epi64() {
+    const unsafe fn test_mm512_mask_unpackhi_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
@@ -10914,7 +10919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpackhi_epi64() {
+    const unsafe fn test_mm512_maskz_unpackhi_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_unpackhi_epi64(0, a, b);
@@ -10925,7 +10930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpackhi_epi64() {
+    const unsafe fn test_mm256_mask_unpackhi_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
@@ -10936,7 +10941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpackhi_epi64() {
+    const unsafe fn test_mm256_maskz_unpackhi_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_maskz_unpackhi_epi64(0, a, b);
@@ -10947,7 +10952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpackhi_epi64() {
+    const unsafe fn test_mm_mask_unpackhi_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
@@ -10958,7 +10963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpackhi_epi64() {
+    const unsafe fn test_mm_maskz_unpackhi_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_maskz_unpackhi_epi64(0, a, b);
@@ -10969,7 +10974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpackhi_pd() {
+    const unsafe fn test_mm512_unpackhi_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_unpackhi_pd(a, b);
@@ -10978,7 +10983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpackhi_pd() {
+    const unsafe fn test_mm512_mask_unpackhi_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
@@ -10989,7 +10994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpackhi_pd() {
+    const unsafe fn test_mm512_maskz_unpackhi_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_maskz_unpackhi_pd(0, a, b);
@@ -11000,7 +11005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpackhi_pd() {
+    const unsafe fn test_mm256_mask_unpackhi_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
@@ -11011,7 +11016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpackhi_pd() {
+    const unsafe fn test_mm256_maskz_unpackhi_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_maskz_unpackhi_pd(0, a, b);
@@ -11022,7 +11027,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpackhi_pd() {
+    const unsafe fn test_mm_mask_unpackhi_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_mask_unpackhi_pd(a, 0, a, b);
@@ -11033,7 +11038,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpackhi_pd() {
+    const unsafe fn test_mm_maskz_unpackhi_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_maskz_unpackhi_pd(0, a, b);
@@ -11044,7 +11049,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpacklo_epi64() {
+    const unsafe fn test_mm512_unpacklo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_unpacklo_epi64(a, b);
@@ -11053,7 +11058,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpacklo_epi64() {
+    const unsafe fn test_mm512_mask_unpacklo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
@@ -11064,7 +11069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpacklo_epi64() {
+    const unsafe fn test_mm512_maskz_unpacklo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_unpacklo_epi64(0, a, b);
@@ -11075,7 +11080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpacklo_epi64() {
+    const unsafe fn test_mm256_mask_unpacklo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
@@ -11086,7 +11091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpacklo_epi64() {
+    const unsafe fn test_mm256_maskz_unpacklo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_maskz_unpacklo_epi64(0, a, b);
@@ -11097,7 +11102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpacklo_epi64() {
+    const unsafe fn test_mm_mask_unpacklo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
@@ -11108,7 +11113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpacklo_epi64() {
+    const unsafe fn test_mm_maskz_unpacklo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_maskz_unpacklo_epi64(0, a, b);
@@ -11119,7 +11124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_unpacklo_pd() {
+    const unsafe fn test_mm512_unpacklo_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_unpacklo_pd(a, b);
@@ -11128,7 +11133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_unpacklo_pd() {
+    const unsafe fn test_mm512_mask_unpacklo_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
@@ -11139,7 +11144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_unpacklo_pd() {
+    const unsafe fn test_mm512_maskz_unpacklo_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_maskz_unpacklo_pd(0, a, b);
@@ -11150,7 +11155,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_unpacklo_pd() {
+    const unsafe fn test_mm256_mask_unpacklo_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
@@ -11161,7 +11166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_unpacklo_pd() {
+    const unsafe fn test_mm256_maskz_unpacklo_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_maskz_unpacklo_pd(0, a, b);
@@ -11172,7 +11177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_unpacklo_pd() {
+    const unsafe fn test_mm_mask_unpacklo_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_mask_unpacklo_pd(a, 0, a, b);
@@ -11183,7 +11188,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_unpacklo_pd() {
+    const unsafe fn test_mm_maskz_unpacklo_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_maskz_unpacklo_pd(0, a, b);
@@ -11194,7 +11199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_alignr_epi64() {
+    const unsafe fn test_mm512_alignr_epi64() {
         let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm512_alignr_epi64::<0>(a, b);
@@ -11207,7 +11212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_alignr_epi64() {
+    const unsafe fn test_mm512_mask_alignr_epi64() {
         let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
@@ -11218,7 +11223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_alignr_epi64() {
+    const unsafe fn test_mm512_maskz_alignr_epi64() {
         let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
@@ -11229,7 +11234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_alignr_epi64() {
+    const unsafe fn test_mm256_alignr_epi64() {
         let a = _mm256_set_epi64x(4, 3, 2, 1);
         let b = _mm256_set_epi64x(8, 7, 6, 5);
         let r = _mm256_alignr_epi64::<0>(a, b);
@@ -11244,7 +11249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_alignr_epi64() {
+    const unsafe fn test_mm256_mask_alignr_epi64() {
         let a = _mm256_set_epi64x(4, 3, 2, 1);
         let b = _mm256_set_epi64x(8, 7, 6, 5);
         let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
@@ -11255,7 +11260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_alignr_epi64() {
+    const unsafe fn test_mm256_maskz_alignr_epi64() {
         let a = _mm256_set_epi64x(4, 3, 2, 1);
         let b = _mm256_set_epi64x(8, 7, 6, 5);
         let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
@@ -11266,7 +11271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_alignr_epi64() {
+    const unsafe fn test_mm_alignr_epi64() {
         let a = _mm_set_epi64x(2, 1);
         let b = _mm_set_epi64x(4, 3);
         let r = _mm_alignr_epi64::<0>(a, b);
@@ -11275,7 +11280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_alignr_epi64() {
+    const unsafe fn test_mm_mask_alignr_epi64() {
         let a = _mm_set_epi64x(2, 1);
         let b = _mm_set_epi64x(4, 3);
         let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
@@ -11286,7 +11291,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_alignr_epi64() {
+    const unsafe fn test_mm_maskz_alignr_epi64() {
         let a = _mm_set_epi64x(2, 1);
         let b = _mm_set_epi64x(4, 3);
         let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
@@ -11297,7 +11302,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_and_epi64() {
+    const unsafe fn test_mm512_and_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_and_epi64(a, b);
@@ -11306,7 +11311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_and_epi64() {
+    const unsafe fn test_mm512_mask_and_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_mask_and_epi64(a, 0, a, b);
@@ -11317,7 +11322,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_and_epi64() {
+    const unsafe fn test_mm512_maskz_and_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_maskz_and_epi64(0, a, b);
@@ -11328,7 +11333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_and_epi64() {
+    const unsafe fn test_mm256_mask_and_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 0);
         let r = _mm256_mask_and_epi64(a, 0, a, b);
@@ -11339,7 +11344,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_and_epi64() {
+    const unsafe fn test_mm256_maskz_and_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 0);
         let r = _mm256_maskz_and_epi64(0, a, b);
@@ -11350,7 +11355,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_and_epi64() {
+    const unsafe fn test_mm_mask_and_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 0);
         let r = _mm_mask_and_epi64(a, 0, a, b);
@@ -11361,7 +11366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_and_epi64() {
+    const unsafe fn test_mm_maskz_and_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 0);
         let r = _mm_maskz_and_epi64(0, a, b);
@@ -11372,7 +11377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_and_si512() {
+    const unsafe fn test_mm512_and_si512() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_and_epi64(a, b);
@@ -11381,7 +11386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_or_epi64() {
+    const unsafe fn test_mm512_or_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_or_epi64(a, b);
@@ -11394,7 +11399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_or_epi64() {
+    const unsafe fn test_mm512_mask_or_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_mask_or_epi64(a, 0, a, b);
@@ -11409,7 +11414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_or_epi64() {
+    const unsafe fn test_mm512_maskz_or_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_maskz_or_epi64(0, a, b);
@@ -11420,7 +11425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_or_epi64() {
+    const unsafe fn test_mm256_or_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_or_epi64(a, b);
@@ -11429,7 +11434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_or_epi64() {
+    const unsafe fn test_mm256_mask_or_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_mask_or_epi64(a, 0, a, b);
@@ -11440,7 +11445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_or_epi64() {
+    const unsafe fn test_mm256_maskz_or_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_maskz_or_epi64(0, a, b);
@@ -11451,7 +11456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_or_epi64() {
+    const unsafe fn test_mm_or_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_or_epi64(a, b);
@@ -11460,7 +11465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_or_epi64() {
+    const unsafe fn test_mm_mask_or_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_mask_or_epi64(a, 0, a, b);
@@ -11471,7 +11476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_or_epi64() {
+    const unsafe fn test_mm_maskz_or_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_maskz_or_epi64(0, a, b);
@@ -11482,7 +11487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_or_si512() {
+    const unsafe fn test_mm512_or_si512() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_or_epi64(a, b);
@@ -11495,7 +11500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_xor_epi64() {
+    const unsafe fn test_mm512_xor_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_xor_epi64(a, b);
@@ -11504,7 +11509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_xor_epi64() {
+    const unsafe fn test_mm512_mask_xor_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_mask_xor_epi64(a, 0, a, b);
@@ -11515,7 +11520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_xor_epi64() {
+    const unsafe fn test_mm512_maskz_xor_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_maskz_xor_epi64(0, a, b);
@@ -11526,7 +11531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_xor_epi64() {
+    const unsafe fn test_mm256_xor_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_xor_epi64(a, b);
@@ -11535,7 +11540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_xor_epi64() {
+    const unsafe fn test_mm256_mask_xor_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_mask_xor_epi64(a, 0, a, b);
@@ -11546,7 +11551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_xor_epi64() {
+    const unsafe fn test_mm256_maskz_xor_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_maskz_xor_epi64(0, a, b);
@@ -11557,7 +11562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_xor_epi64() {
+    const unsafe fn test_mm_xor_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_xor_epi64(a, b);
@@ -11566,7 +11571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_xor_epi64() {
+    const unsafe fn test_mm_mask_xor_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_mask_xor_epi64(a, 0, a, b);
@@ -11577,7 +11582,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_xor_epi64() {
+    const unsafe fn test_mm_maskz_xor_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_maskz_xor_epi64(0, a, b);
@@ -11588,7 +11593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_xor_si512() {
+    const unsafe fn test_mm512_xor_si512() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_xor_epi64(a, b);
@@ -11597,7 +11602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_andnot_epi64() {
+    const unsafe fn test_mm512_andnot_epi64() {
         let a = _mm512_set1_epi64(0);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_andnot_epi64(a, b);
@@ -11606,7 +11611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_andnot_epi64() {
+    const unsafe fn test_mm512_mask_andnot_epi64() {
         let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_mask_andnot_epi64(a, 0, a, b);
@@ -11617,7 +11622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_andnot_epi64() {
+    const unsafe fn test_mm512_maskz_andnot_epi64() {
         let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_maskz_andnot_epi64(0, a, b);
@@ -11632,7 +11637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_andnot_epi64() {
+    const unsafe fn test_mm256_mask_andnot_epi64() {
         let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm256_mask_andnot_epi64(a, 0, a, b);
@@ -11643,7 +11648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_andnot_epi64() {
+    const unsafe fn test_mm256_maskz_andnot_epi64() {
         let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm256_maskz_andnot_epi64(0, a, b);
@@ -11654,7 +11659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_andnot_epi64() {
+    const unsafe fn test_mm_mask_andnot_epi64() {
         let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm_mask_andnot_epi64(a, 0, a, b);
@@ -11665,7 +11670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_andnot_epi64() {
+    const unsafe fn test_mm_maskz_andnot_epi64() {
         let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm_maskz_andnot_epi64(0, a, b);
@@ -11676,7 +11681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_andnot_si512() {
+    const unsafe fn test_mm512_andnot_si512() {
         let a = _mm512_set1_epi64(0);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_andnot_si512(a, b);
@@ -11685,84 +11690,84 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_add_epi64() {
+    const unsafe fn test_mm512_reduce_add_epi64() {
         let a = _mm512_set1_epi64(1);
         let e: i64 = _mm512_reduce_add_epi64(a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_add_epi64() {
+    const unsafe fn test_mm512_mask_reduce_add_epi64() {
         let a = _mm512_set1_epi64(1);
         let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
         assert_eq!(4, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_add_pd() {
+    const unsafe fn test_mm512_reduce_add_pd() {
         let a = _mm512_set1_pd(1.);
         let e: f64 = _mm512_reduce_add_pd(a);
         assert_eq!(8., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_add_pd() {
+    const unsafe fn test_mm512_mask_reduce_add_pd() {
         let a = _mm512_set1_pd(1.);
         let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
         assert_eq!(4., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_mul_epi64() {
+    const unsafe fn test_mm512_reduce_mul_epi64() {
         let a = _mm512_set1_epi64(2);
         let e: i64 = _mm512_reduce_mul_epi64(a);
         assert_eq!(256, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_mul_epi64() {
+    const unsafe fn test_mm512_mask_reduce_mul_epi64() {
         let a = _mm512_set1_epi64(2);
         let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_mul_pd() {
+    const unsafe fn test_mm512_reduce_mul_pd() {
         let a = _mm512_set1_pd(2.);
         let e: f64 = _mm512_reduce_mul_pd(a);
         assert_eq!(256., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_mul_pd() {
+    const unsafe fn test_mm512_mask_reduce_mul_pd() {
         let a = _mm512_set1_pd(2.);
         let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
         assert_eq!(16., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_max_epi64() {
+    const unsafe fn test_mm512_reduce_max_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_reduce_max_epi64(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_max_epi64() {
+    const unsafe fn test_mm512_mask_reduce_max_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_max_epu64() {
+    const unsafe fn test_mm512_reduce_max_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_reduce_max_epu64(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_max_epu64() {
+    const unsafe fn test_mm512_mask_reduce_max_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
         assert_eq!(3, e);
@@ -11783,28 +11788,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_min_epi64() {
+    const unsafe fn test_mm512_reduce_min_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_reduce_min_epi64(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_min_epi64() {
+    const unsafe fn test_mm512_mask_reduce_min_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_min_epu64() {
+    const unsafe fn test_mm512_reduce_min_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_reduce_min_epu64(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_min_epu64() {
+    const unsafe fn test_mm512_mask_reduce_min_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
         assert_eq!(0, e);
@@ -11825,35 +11830,35 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_and_epi64() {
+    const unsafe fn test_mm512_reduce_and_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_reduce_and_epi64(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_and_epi64() {
+    const unsafe fn test_mm512_mask_reduce_and_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_or_epi64() {
+    const unsafe fn test_mm512_reduce_or_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_reduce_or_epi64(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_or_epi64() {
+    const unsafe fn test_mm512_mask_reduce_or_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_extractf64x4_pd() {
+    const unsafe fn test_mm512_extractf64x4_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_extractf64x4_pd::<1>(a);
         let e = _mm256_setr_pd(5., 6., 7., 8.);
@@ -11861,7 +11866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_extractf64x4_pd() {
+    const unsafe fn test_mm512_mask_extractf64x4_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let src = _mm256_set1_pd(100.);
         let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
@@ -11872,7 +11877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_extractf64x4_pd() {
+    const unsafe fn test_mm512_maskz_extractf64x4_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -11882,7 +11887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_extracti64x4_epi64() {
+    const unsafe fn test_mm512_extracti64x4_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_extracti64x4_epi64::<0x1>(a);
         let e = _mm256_setr_epi64x(5, 6, 7, 8);
@@ -11890,7 +11895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_extracti64x4_epi64() {
+    const unsafe fn test_mm512_mask_extracti64x4_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm256_set1_epi64x(100);
         let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
@@ -11901,7 +11906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_extracti64x4_epi64() {
+    const unsafe fn test_mm512_maskz_extracti64x4_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -12163,7 +12168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_loadu_epi64() {
+    const unsafe fn test_mm512_loadu_epi64() {
         let a = &[4, 3, 2, 5, -8, -9, -64, -50];
         let p = a.as_ptr();
         let r = _mm512_loadu_epi64(black_box(p));
@@ -12172,7 +12177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_loadu_epi64() {
+    const unsafe fn test_mm256_loadu_epi64() {
         let a = &[4, 3, 2, 5];
         let p = a.as_ptr();
         let r = _mm256_loadu_epi64(black_box(p));
@@ -12181,7 +12186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_loadu_epi64() {
+    const unsafe fn test_mm_loadu_epi64() {
         let a = &[4, 3];
         let p = a.as_ptr();
         let r = _mm_loadu_epi64(black_box(p));
@@ -12472,7 +12477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_storeu_epi64() {
+    const unsafe fn test_mm512_storeu_epi64() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm512_set1_epi64(0);
         _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
@@ -12480,7 +12485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_storeu_epi64() {
+    const unsafe fn test_mm256_storeu_epi64() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm256_set1_epi64x(0);
         _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
@@ -12488,7 +12493,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_storeu_epi64() {
+    const unsafe fn test_mm_storeu_epi64() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi64x(0);
         _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
@@ -12496,7 +12501,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_load_epi64() {
+    const unsafe fn test_mm512_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -12511,7 +12516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_load_epi64() {
+    const unsafe fn test_mm256_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 4],
@@ -12524,7 +12529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_load_epi64() {
+    const unsafe fn test_mm_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 2],
@@ -12537,7 +12542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_store_epi64() {
+    const unsafe fn test_mm512_store_epi64() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm512_set1_epi64(0);
         _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
@@ -12545,7 +12550,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_store_epi64() {
+    const unsafe fn test_mm256_store_epi64() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm256_set1_epi64x(0);
         _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
@@ -12553,7 +12558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_store_epi64() {
+    const unsafe fn test_mm_store_epi64() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi64x(0);
         _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
@@ -12561,7 +12566,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_load_pd() {
+    const unsafe fn test_mm512_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -12576,7 +12581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_store_pd() {
+    const unsafe fn test_mm512_store_pd() {
         let a = _mm512_set1_pd(9.);
         let mut r = _mm512_undefined_pd();
         _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
@@ -12584,7 +12589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_test_epi64_mask() {
+    const unsafe fn test_mm512_test_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
         let r = _mm512_test_epi64_mask(a, b);
@@ -12593,7 +12598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_test_epi64_mask() {
+    const unsafe fn test_mm512_mask_test_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi64_mask(0, a, b);
@@ -12604,7 +12609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_test_epi64_mask() {
+    const unsafe fn test_mm256_test_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm256_test_epi64_mask(a, b);
@@ -12613,7 +12618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_test_epi64_mask() {
+    const unsafe fn test_mm256_mask_test_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi64_mask(0, a, b);
@@ -12624,7 +12629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_test_epi64_mask() {
+    const unsafe fn test_mm_test_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm_test_epi64_mask(a, b);
@@ -12633,7 +12638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_test_epi64_mask() {
+    const unsafe fn test_mm_mask_test_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi64_mask(0, a, b);
@@ -12644,7 +12649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_testn_epi64_mask() {
+    const unsafe fn test_mm512_testn_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi64_mask(a, b);
@@ -12653,7 +12658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_testn_epi64_mask() {
+    const unsafe fn test_mm512_mask_testn_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 1);
         let r = _mm512_mask_testn_epi64_mask(0, a, b);
@@ -12664,7 +12669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_testn_epi64_mask() {
+    const unsafe fn test_mm256_testn_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 1);
         let r = _mm256_testn_epi64_mask(a, b);
@@ -12673,7 +12678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_testn_epi64_mask() {
+    const unsafe fn test_mm256_mask_testn_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 1);
         let r = _mm256_mask_testn_epi64_mask(0, a, b);
@@ -12684,7 +12689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_testn_epi64_mask() {
+    const unsafe fn test_mm_testn_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 1);
         let r = _mm_testn_epi64_mask(a, b);
@@ -12693,7 +12698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_testn_epi64_mask() {
+    const unsafe fn test_mm_mask_testn_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 1);
         let r = _mm_mask_testn_epi64_mask(0, a, b);
@@ -12704,7 +12709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_set1_epi64() {
+    const unsafe fn test_mm512_mask_set1_epi64() {
         let src = _mm512_set1_epi64(2);
         let a: i64 = 11;
         let r = _mm512_mask_set1_epi64(src, 0, a);
@@ -12715,7 +12720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_set1_epi64() {
+    const unsafe fn test_mm512_maskz_set1_epi64() {
         let a: i64 = 11;
         let r = _mm512_maskz_set1_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -12725,7 +12730,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_set1_epi64() {
+    const unsafe fn test_mm256_mask_set1_epi64() {
         let src = _mm256_set1_epi64x(2);
         let a: i64 = 11;
         let r = _mm256_mask_set1_epi64(src, 0, a);
@@ -12736,7 +12741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_set1_epi64() {
+    const unsafe fn test_mm256_maskz_set1_epi64() {
         let a: i64 = 11;
         let r = _mm256_maskz_set1_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -12746,7 +12751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_set1_epi64() {
+    const unsafe fn test_mm_mask_set1_epi64() {
         let src = _mm_set1_epi64x(2);
         let a: i64 = 11;
         let r = _mm_mask_set1_epi64(src, 0, a);
@@ -12757,7 +12762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_set1_epi64() {
+    const unsafe fn test_mm_maskz_set1_epi64() {
         let a: i64 = 11;
         let r = _mm_maskz_set1_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -12801,7 +12806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvti64_ss() {
+    const unsafe fn test_mm_cvti64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvti64_ss(a, b);
@@ -12810,7 +12815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvti64_sd() {
+    const unsafe fn test_mm_cvti64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvti64_sd(a, b);
@@ -12963,7 +12968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtu64_ss() {
+    const unsafe fn test_mm_cvtu64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: u64 = 9;
         let r = _mm_cvtu64_ss(a, b);
@@ -12972,7 +12977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtu64_sd() {
+    const unsafe fn test_mm_cvtu64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: u64 = 9;
         let r = _mm_cvtu64_sd(a, b);

From e944c467dad916077896d146a9d59f656633b87d Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:23:10 +0530
Subject: [PATCH 062/326] Make `avx512bw` functions const

---
 crates/core_arch/src/x86/avx512bw.rs    | 3738 ++++++++++++++---------
 crates/core_arch/src/x86_64/avx512bw.rs |   11 +-
 2 files changed, 2332 insertions(+), 1417 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index c76ec3cb29..b6e941908a 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -14,7 +14,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm512_abs_epi16(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_epi16(a: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i16x32();
         let cmp: i16x32 = simd_gt(a, i16x32::ZERO);
@@ -29,7 +30,8 @@ pub fn _mm512_abs_epi16(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, abs, src.as_i16x32()))
@@ -43,7 +45,8 @@ pub fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm512_maskz_abs_epi16(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_abs_epi16(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, abs, i16x32::ZERO))
@@ -57,7 +60,8 @@ pub fn _mm512_maskz_abs_epi16(k: __mmask32, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm256_mask_abs_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_abs_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, abs, src.as_i16x16()))
@@ -71,7 +75,8 @@ pub fn _mm256_mask_abs_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm256_maskz_abs_epi16(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_abs_epi16(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, abs, i16x16::ZERO))
@@ -85,7 +90,8 @@ pub fn _mm256_maskz_abs_epi16(k: __mmask16, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm_mask_abs_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_abs_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, abs, src.as_i16x8()))
@@ -99,7 +105,8 @@ pub fn _mm_mask_abs_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsw))]
-pub fn _mm_maskz_abs_epi16(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_abs_epi16(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, abs, i16x8::ZERO))
@@ -113,7 +120,8 @@ pub fn _mm_maskz_abs_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm512_abs_epi8(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_epi8(a: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i8x64();
         let cmp: i8x64 = simd_gt(a, i8x64::ZERO);
@@ -128,7 +136,8 @@ pub fn _mm512_abs_epi8(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm512_mask_abs_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_abs_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi8(a).as_i8x64();
         transmute(simd_select_bitmask(k, abs, src.as_i8x64()))
@@ -142,7 +151,8 @@ pub fn _mm512_mask_abs_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm512_maskz_abs_epi8(k: __mmask64, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_abs_epi8(k: __mmask64, a: __m512i) -> __m512i {
     unsafe {
         let abs = _mm512_abs_epi8(a).as_i8x64();
         transmute(simd_select_bitmask(k, abs, i8x64::ZERO))
@@ -156,7 +166,8 @@ pub fn _mm512_maskz_abs_epi8(k: __mmask64, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm256_mask_abs_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_abs_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, abs, src.as_i8x32()))
@@ -170,7 +181,8 @@ pub fn _mm256_mask_abs_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm256_maskz_abs_epi8(k: __mmask32, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_abs_epi8(k: __mmask32, a: __m256i) -> __m256i {
     unsafe {
         let abs = _mm256_abs_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, abs, i8x32::ZERO))
@@ -184,7 +196,8 @@ pub fn _mm256_maskz_abs_epi8(k: __mmask32, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm_mask_abs_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_abs_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, abs, src.as_i8x16()))
@@ -198,7 +211,8 @@ pub fn _mm_mask_abs_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpabsb))]
-pub fn _mm_maskz_abs_epi8(k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_abs_epi8(k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         let abs = _mm_abs_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, abs, i8x16::ZERO))
@@ -212,7 +226,8 @@ pub fn _mm_maskz_abs_epi8(k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm512_add_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_add(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -223,7 +238,8 @@ pub fn _mm512_add_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm512_mask_add_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, add, src.as_i16x32()))
@@ -237,7 +253,8 @@ pub fn _mm512_mask_add_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm512_maskz_add_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, add, i16x32::ZERO))
@@ -251,7 +268,8 @@ pub fn _mm512_maskz_add_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm256_mask_add_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, add, src.as_i16x16()))
@@ -265,7 +283,8 @@ pub fn _mm256_mask_add_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm256_maskz_add_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, add, i16x16::ZERO))
@@ -279,7 +298,8 @@ pub fn _mm256_maskz_add_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm_mask_add_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, add, src.as_i16x8()))
@@ -293,7 +313,8 @@ pub fn _mm_mask_add_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddw))]
-pub fn _mm_maskz_add_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, add, i16x8::ZERO))
@@ -307,7 +328,8 @@ pub fn _mm_maskz_add_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm512_add_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_add(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -318,7 +340,8 @@ pub fn _mm512_add_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm512_mask_add_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, add, src.as_i8x64()))
@@ -332,7 +355,8 @@ pub fn _mm512_mask_add_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm512_maskz_add_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_add_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, add, i8x64::ZERO))
@@ -346,7 +370,8 @@ pub fn _mm512_maskz_add_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm256_mask_add_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, add, src.as_i8x32()))
@@ -360,7 +385,8 @@ pub fn _mm256_mask_add_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm256_maskz_add_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_add_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, add, i8x32::ZERO))
@@ -374,7 +400,8 @@ pub fn _mm256_maskz_add_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm_mask_add_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, add, src.as_i8x16()))
@@ -388,7 +415,8 @@ pub fn _mm_mask_add_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddb))]
-pub fn _mm_maskz_add_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_add_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, add, i8x16::ZERO))
@@ -402,7 +430,8 @@ pub fn _mm_maskz_add_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm512_adds_epu16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_adds_epu16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_add(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -413,7 +442,8 @@ pub fn _mm512_adds_epu16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm512_mask_adds_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_adds_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, add, src.as_u16x32()))
@@ -427,7 +457,8 @@ pub fn _mm512_mask_adds_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm512_maskz_adds_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_adds_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, add, u16x32::ZERO))
@@ -441,7 +472,8 @@ pub fn _mm512_maskz_adds_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm256_mask_adds_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_adds_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, add, src.as_u16x16()))
@@ -455,7 +487,8 @@ pub fn _mm256_mask_adds_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm256_maskz_adds_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_adds_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, add, u16x16::ZERO))
@@ -469,7 +502,8 @@ pub fn _mm256_maskz_adds_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm_mask_adds_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_adds_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, add, src.as_u16x8()))
@@ -483,7 +517,8 @@ pub fn _mm_mask_adds_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusw))]
-pub fn _mm_maskz_adds_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_adds_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, add, u16x8::ZERO))
@@ -497,7 +532,8 @@ pub fn _mm_maskz_adds_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm512_adds_epu8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_adds_epu8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_add(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -508,7 +544,8 @@ pub fn _mm512_adds_epu8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm512_mask_adds_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_adds_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, add, src.as_u8x64()))
@@ -522,7 +559,8 @@ pub fn _mm512_mask_adds_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm512_maskz_adds_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_adds_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, add, u8x64::ZERO))
@@ -536,7 +574,8 @@ pub fn _mm512_maskz_adds_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm256_mask_adds_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_adds_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, add, src.as_u8x32()))
@@ -550,7 +589,8 @@ pub fn _mm256_mask_adds_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm256_maskz_adds_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_adds_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, add, u8x32::ZERO))
@@ -564,7 +604,8 @@ pub fn _mm256_maskz_adds_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm_mask_adds_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_adds_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, add, src.as_u8x16()))
@@ -578,7 +619,8 @@ pub fn _mm_mask_adds_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddusb))]
-pub fn _mm_maskz_adds_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_adds_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, add, u8x16::ZERO))
@@ -592,7 +634,8 @@ pub fn _mm_maskz_adds_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm512_adds_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_adds_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_add(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -603,7 +646,8 @@ pub fn _mm512_adds_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm512_mask_adds_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_adds_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, add, src.as_i16x32()))
@@ -617,7 +661,8 @@ pub fn _mm512_mask_adds_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm512_maskz_adds_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_adds_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, add, i16x32::ZERO))
@@ -631,7 +676,8 @@ pub fn _mm512_maskz_adds_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm256_mask_adds_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_adds_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, add, src.as_i16x16()))
@@ -645,7 +691,8 @@ pub fn _mm256_mask_adds_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm256_maskz_adds_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_adds_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, add, i16x16::ZERO))
@@ -659,7 +706,8 @@ pub fn _mm256_maskz_adds_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm_mask_adds_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_adds_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, add, src.as_i16x8()))
@@ -673,7 +721,8 @@ pub fn _mm_mask_adds_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsw))]
-pub fn _mm_maskz_adds_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_adds_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, add, i16x8::ZERO))
@@ -687,7 +736,8 @@ pub fn _mm_maskz_adds_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm512_adds_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_adds_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_add(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -698,7 +748,8 @@ pub fn _mm512_adds_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm512_mask_adds_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_adds_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, add, src.as_i8x64()))
@@ -712,7 +763,8 @@ pub fn _mm512_mask_adds_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm512_maskz_adds_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_adds_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let add = _mm512_adds_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, add, i8x64::ZERO))
@@ -726,7 +778,8 @@ pub fn _mm512_maskz_adds_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm256_mask_adds_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_adds_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, add, src.as_i8x32()))
@@ -740,7 +793,8 @@ pub fn _mm256_mask_adds_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm256_maskz_adds_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_adds_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let add = _mm256_adds_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, add, i8x32::ZERO))
@@ -754,7 +808,8 @@ pub fn _mm256_maskz_adds_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm_mask_adds_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_adds_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, add, src.as_i8x16()))
@@ -768,7 +823,8 @@ pub fn _mm_mask_adds_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpaddsb))]
-pub fn _mm_maskz_adds_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_adds_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let add = _mm_adds_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, add, i8x16::ZERO))
@@ -782,7 +838,8 @@ pub fn _mm_maskz_adds_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm512_sub_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_sub(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -793,7 +850,8 @@ pub fn _mm512_sub_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm512_mask_sub_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, sub, src.as_i16x32()))
@@ -807,7 +865,8 @@ pub fn _mm512_mask_sub_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm512_maskz_sub_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, sub, i16x32::ZERO))
@@ -821,7 +880,8 @@ pub fn _mm512_maskz_sub_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm256_mask_sub_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, sub, src.as_i16x16()))
@@ -835,7 +895,8 @@ pub fn _mm256_mask_sub_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm256_maskz_sub_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, sub, i16x16::ZERO))
@@ -849,7 +910,8 @@ pub fn _mm256_maskz_sub_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm_mask_sub_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, sub, src.as_i16x8()))
@@ -863,7 +925,8 @@ pub fn _mm_mask_sub_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubw))]
-pub fn _mm_maskz_sub_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, sub, i16x8::ZERO))
@@ -877,7 +940,8 @@ pub fn _mm_maskz_sub_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm512_sub_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_sub(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -888,7 +952,8 @@ pub fn _mm512_sub_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm512_mask_sub_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, sub, src.as_i8x64()))
@@ -902,7 +967,8 @@ pub fn _mm512_mask_sub_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm512_maskz_sub_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_sub_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, sub, i8x64::ZERO))
@@ -916,7 +982,8 @@ pub fn _mm512_maskz_sub_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm256_mask_sub_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, sub, src.as_i8x32()))
@@ -930,7 +997,8 @@ pub fn _mm256_mask_sub_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm256_maskz_sub_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_sub_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, sub, i8x32::ZERO))
@@ -944,7 +1012,8 @@ pub fn _mm256_maskz_sub_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm_mask_sub_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, sub, src.as_i8x16()))
@@ -958,7 +1027,8 @@ pub fn _mm_mask_sub_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubb))]
-pub fn _mm_maskz_sub_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_sub_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, sub, i8x16::ZERO))
@@ -972,7 +1042,8 @@ pub fn _mm_maskz_sub_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm512_subs_epu16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_subs_epu16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_sub(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -983,7 +1054,8 @@ pub fn _mm512_subs_epu16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm512_mask_subs_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_subs_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, sub, src.as_u16x32()))
@@ -997,7 +1069,8 @@ pub fn _mm512_mask_subs_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm512_maskz_subs_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_subs_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, sub, u16x32::ZERO))
@@ -1011,7 +1084,8 @@ pub fn _mm512_maskz_subs_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm256_mask_subs_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_subs_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, sub, src.as_u16x16()))
@@ -1025,7 +1099,8 @@ pub fn _mm256_mask_subs_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm256_maskz_subs_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_subs_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, sub, u16x16::ZERO))
@@ -1039,7 +1114,8 @@ pub fn _mm256_maskz_subs_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm_mask_subs_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_subs_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, sub, src.as_u16x8()))
@@ -1053,7 +1129,8 @@ pub fn _mm_mask_subs_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusw))]
-pub fn _mm_maskz_subs_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_subs_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, sub, u16x8::ZERO))
@@ -1067,7 +1144,8 @@ pub fn _mm_maskz_subs_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm512_subs_epu8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_subs_epu8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_sub(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -1078,7 +1156,8 @@ pub fn _mm512_subs_epu8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm512_mask_subs_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_subs_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, sub, src.as_u8x64()))
@@ -1092,7 +1171,8 @@ pub fn _mm512_mask_subs_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm512_maskz_subs_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_subs_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, sub, u8x64::ZERO))
@@ -1106,7 +1186,8 @@ pub fn _mm512_maskz_subs_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm256_mask_subs_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_subs_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, sub, src.as_u8x32()))
@@ -1120,7 +1201,8 @@ pub fn _mm256_mask_subs_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm256_maskz_subs_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_subs_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, sub, u8x32::ZERO))
@@ -1134,7 +1216,8 @@ pub fn _mm256_maskz_subs_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm_mask_subs_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_subs_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, sub, src.as_u8x16()))
@@ -1148,7 +1231,8 @@ pub fn _mm_mask_subs_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubusb))]
-pub fn _mm_maskz_subs_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_subs_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, sub, u8x16::ZERO))
@@ -1162,7 +1246,8 @@ pub fn _mm_maskz_subs_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm512_subs_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_subs_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_sub(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -1173,7 +1258,8 @@ pub fn _mm512_subs_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm512_mask_subs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_subs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, sub, src.as_i16x32()))
@@ -1187,7 +1273,8 @@ pub fn _mm512_mask_subs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm512_maskz_subs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_subs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, sub, i16x32::ZERO))
@@ -1201,7 +1288,8 @@ pub fn _mm512_maskz_subs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm256_mask_subs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_subs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, sub, src.as_i16x16()))
@@ -1215,7 +1303,8 @@ pub fn _mm256_mask_subs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm256_maskz_subs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_subs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, sub, i16x16::ZERO))
@@ -1229,7 +1318,8 @@ pub fn _mm256_maskz_subs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm_mask_subs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_subs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, sub, src.as_i16x8()))
@@ -1243,7 +1333,8 @@ pub fn _mm_mask_subs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsw))]
-pub fn _mm_maskz_subs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_subs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, sub, i16x8::ZERO))
@@ -1257,7 +1348,8 @@ pub fn _mm_maskz_subs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm512_subs_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_subs_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_saturating_sub(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -1268,7 +1360,8 @@ pub fn _mm512_subs_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm512_mask_subs_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_subs_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, sub, src.as_i8x64()))
@@ -1282,7 +1375,8 @@ pub fn _mm512_mask_subs_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm512_maskz_subs_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_subs_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let sub = _mm512_subs_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, sub, i8x64::ZERO))
@@ -1296,7 +1390,8 @@ pub fn _mm512_maskz_subs_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm256_mask_subs_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_subs_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, sub, src.as_i8x32()))
@@ -1310,7 +1405,8 @@ pub fn _mm256_mask_subs_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm256_maskz_subs_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_subs_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let sub = _mm256_subs_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, sub, i8x32::ZERO))
@@ -1324,7 +1420,8 @@ pub fn _mm256_maskz_subs_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm_mask_subs_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_subs_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, sub, src.as_i8x16()))
@@ -1338,7 +1435,8 @@ pub fn _mm_mask_subs_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsubsb))]
-pub fn _mm_maskz_subs_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_subs_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let sub = _mm_subs_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, sub, i8x16::ZERO))
@@ -1352,7 +1450,8 @@ pub fn _mm_maskz_subs_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm512_mulhi_epu16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mulhi_epu16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = simd_cast::<_, u32x32>(a.as_u16x32());
         let b = simd_cast::<_, u32x32>(b.as_u16x32());
@@ -1368,7 +1467,13 @@ pub fn _mm512_mulhi_epu16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm512_mask_mulhi_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mulhi_epu16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let mul = _mm512_mulhi_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, mul, src.as_u16x32()))
@@ -1382,7 +1487,8 @@ pub fn _mm512_mask_mulhi_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm512_maskz_mulhi_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mulhi_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mulhi_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, mul, u16x32::ZERO))
@@ -1396,7 +1502,13 @@ pub fn _mm512_maskz_mulhi_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm256_mask_mulhi_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mulhi_epu16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let mul = _mm256_mulhi_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, mul, src.as_u16x16()))
@@ -1410,7 +1522,8 @@ pub fn _mm256_mask_mulhi_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm256_maskz_mulhi_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mulhi_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mulhi_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, mul, u16x16::ZERO))
@@ -1424,7 +1537,8 @@ pub fn _mm256_maskz_mulhi_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm_mask_mulhi_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mulhi_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mulhi_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, mul, src.as_u16x8()))
@@ -1438,7 +1552,8 @@ pub fn _mm_mask_mulhi_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhuw))]
-pub fn _mm_maskz_mulhi_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mulhi_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mulhi_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, mul, u16x8::ZERO))
@@ -1452,7 +1567,8 @@ pub fn _mm_maskz_mulhi_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm512_mulhi_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mulhi_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = simd_cast::<_, i32x32>(a.as_i16x32());
         let b = simd_cast::<_, i32x32>(b.as_i16x32());
@@ -1468,7 +1584,13 @@ pub fn _mm512_mulhi_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm512_mask_mulhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mulhi_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let mul = _mm512_mulhi_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, mul, src.as_i16x32()))
@@ -1482,7 +1604,8 @@ pub fn _mm512_mask_mulhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm512_maskz_mulhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mulhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mulhi_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, mul, i16x32::ZERO))
@@ -1496,7 +1619,13 @@ pub fn _mm512_maskz_mulhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm256_mask_mulhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mulhi_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let mul = _mm256_mulhi_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, mul, src.as_i16x16()))
@@ -1510,7 +1639,8 @@ pub fn _mm256_mask_mulhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm256_maskz_mulhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mulhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mulhi_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, mul, i16x16::ZERO))
@@ -1524,7 +1654,8 @@ pub fn _mm256_maskz_mulhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm_mask_mulhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mulhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mulhi_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, mul, src.as_i16x8()))
@@ -1538,7 +1669,8 @@ pub fn _mm_mask_mulhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmulhw))]
-pub fn _mm_maskz_mulhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mulhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mulhi_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, mul, i16x8::ZERO))
@@ -1647,7 +1779,8 @@ pub fn _mm_maskz_mulhrs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm512_mullo_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mullo_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_mul(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -1658,7 +1791,13 @@ pub fn _mm512_mullo_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm512_mask_mullo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mullo_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let mul = _mm512_mullo_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, mul, src.as_i16x32()))
@@ -1672,7 +1811,8 @@ pub fn _mm512_mask_mullo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm512_maskz_mullo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mullo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let mul = _mm512_mullo_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, mul, i16x32::ZERO))
@@ -1686,7 +1826,13 @@ pub fn _mm512_maskz_mullo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm256_mask_mullo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mullo_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let mul = _mm256_mullo_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, mul, src.as_i16x16()))
@@ -1700,7 +1846,8 @@ pub fn _mm256_mask_mullo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm256_maskz_mullo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mullo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let mul = _mm256_mullo_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, mul, i16x16::ZERO))
@@ -1714,7 +1861,8 @@ pub fn _mm256_maskz_mullo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm_mask_mullo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mullo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mullo_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, mul, src.as_i16x8()))
@@ -1728,7 +1876,8 @@ pub fn _mm_mask_mullo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmullw))]
-pub fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let mul = _mm_mullo_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, mul, i16x8::ZERO))
@@ -1742,7 +1891,8 @@ pub fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_u16x32(), b.as_u16x32()).as_m512i() }
 }
 
@@ -1753,7 +1903,8 @@ pub fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm512_mask_max_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, max, src.as_u16x32()))
@@ -1767,7 +1918,8 @@ pub fn _mm512_mask_max_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm512_maskz_max_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, max, u16x32::ZERO))
@@ -1781,7 +1933,8 @@ pub fn _mm512_maskz_max_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm256_mask_max_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, max, src.as_u16x16()))
@@ -1795,7 +1948,8 @@ pub fn _mm256_mask_max_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm256_maskz_max_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, max, u16x16::ZERO))
@@ -1809,7 +1963,8 @@ pub fn _mm256_maskz_max_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm_mask_max_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, max, src.as_u16x8()))
@@ -1823,7 +1978,8 @@ pub fn _mm_mask_max_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxuw))]
-pub fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, max, u16x8::ZERO))
@@ -1837,7 +1993,8 @@ pub fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_u8x64(), b.as_u8x64()).as_m512i() }
 }
 
@@ -1848,7 +2005,8 @@ pub fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm512_mask_max_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, max, src.as_u8x64()))
@@ -1862,7 +2020,8 @@ pub fn _mm512_mask_max_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm512_maskz_max_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, max, u8x64::ZERO))
@@ -1876,7 +2035,8 @@ pub fn _mm512_maskz_max_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm256_mask_max_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, max, src.as_u8x32()))
@@ -1890,7 +2050,8 @@ pub fn _mm256_mask_max_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm256_maskz_max_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, max, u8x32::ZERO))
@@ -1904,7 +2065,8 @@ pub fn _mm256_maskz_max_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm_mask_max_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, max, src.as_u8x16()))
@@ -1918,7 +2080,8 @@ pub fn _mm_mask_max_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxub))]
-pub fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, max, u8x16::ZERO))
@@ -1932,7 +2095,8 @@ pub fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_i16x32(), b.as_i16x32()).as_m512i() }
 }
 
@@ -1943,7 +2107,8 @@ pub fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm512_mask_max_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, max, src.as_i16x32()))
@@ -1957,7 +2122,8 @@ pub fn _mm512_mask_max_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm512_maskz_max_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, max, i16x32::ZERO))
@@ -1971,7 +2137,8 @@ pub fn _mm512_maskz_max_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm256_mask_max_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, max, src.as_i16x16()))
@@ -1985,7 +2152,8 @@ pub fn _mm256_mask_max_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm256_maskz_max_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, max, i16x16::ZERO))
@@ -1999,7 +2167,8 @@ pub fn _mm256_maskz_max_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm_mask_max_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, max, src.as_i16x8()))
@@ -2013,7 +2182,8 @@ pub fn _mm_mask_max_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsw))]
-pub fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, max, i16x8::ZERO))
@@ -2027,7 +2197,8 @@ pub fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imax(a.as_i8x64(), b.as_i8x64()).as_m512i() }
 }
 
@@ -2038,7 +2209,8 @@ pub fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm512_mask_max_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_max_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, max, src.as_i8x64()))
@@ -2052,7 +2224,8 @@ pub fn _mm512_mask_max_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm512_maskz_max_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_max_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let max = _mm512_max_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, max, i8x64::ZERO))
@@ -2066,7 +2239,8 @@ pub fn _mm512_maskz_max_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm256_mask_max_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_max_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, max, src.as_i8x32()))
@@ -2080,7 +2254,8 @@ pub fn _mm256_mask_max_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm256_maskz_max_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_max_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let max = _mm256_max_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, max, i8x32::ZERO))
@@ -2094,7 +2269,8 @@ pub fn _mm256_maskz_max_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm_mask_max_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_max_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, max, src.as_i8x16()))
@@ -2108,7 +2284,8 @@ pub fn _mm_mask_max_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaxsb))]
-pub fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let max = _mm_max_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, max, i8x16::ZERO))
@@ -2122,7 +2299,8 @@ pub fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_u16x32(), b.as_u16x32()).as_m512i() }
 }
 
@@ -2133,7 +2311,8 @@ pub fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm512_mask_min_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, min, src.as_u16x32()))
@@ -2147,7 +2326,8 @@ pub fn _mm512_mask_min_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm512_maskz_min_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, min, u16x32::ZERO))
@@ -2161,7 +2341,8 @@ pub fn _mm512_maskz_min_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm256_mask_min_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, min, src.as_u16x16()))
@@ -2175,7 +2356,8 @@ pub fn _mm256_mask_min_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm256_maskz_min_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, min, u16x16::ZERO))
@@ -2189,7 +2371,8 @@ pub fn _mm256_maskz_min_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm_mask_min_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, min, src.as_u16x8()))
@@ -2203,7 +2386,8 @@ pub fn _mm_mask_min_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminuw))]
-pub fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, min, u16x8::ZERO))
@@ -2217,7 +2401,8 @@ pub fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_u8x64(), b.as_u8x64()).as_m512i() }
 }
 
@@ -2228,7 +2413,8 @@ pub fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm512_mask_min_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, min, src.as_u8x64()))
@@ -2242,7 +2428,8 @@ pub fn _mm512_mask_min_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm512_maskz_min_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, min, u8x64::ZERO))
@@ -2256,7 +2443,8 @@ pub fn _mm512_maskz_min_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm256_mask_min_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, min, src.as_u8x32()))
@@ -2270,7 +2458,8 @@ pub fn _mm256_mask_min_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm256_maskz_min_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, min, u8x32::ZERO))
@@ -2284,7 +2473,8 @@ pub fn _mm256_maskz_min_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm_mask_min_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, min, src.as_u8x16()))
@@ -2298,7 +2488,8 @@ pub fn _mm_mask_min_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminub))]
-pub fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, min, u8x16::ZERO))
@@ -2312,7 +2503,8 @@ pub fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_i16x32(), b.as_i16x32()).as_m512i() }
 }
 
@@ -2323,7 +2515,8 @@ pub fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm512_mask_min_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, min, src.as_i16x32()))
@@ -2337,7 +2530,8 @@ pub fn _mm512_mask_min_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm512_maskz_min_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, min, i16x32::ZERO))
@@ -2351,7 +2545,8 @@ pub fn _mm512_maskz_min_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm256_mask_min_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, min, src.as_i16x16()))
@@ -2365,7 +2560,8 @@ pub fn _mm256_mask_min_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm256_maskz_min_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, min, i16x16::ZERO))
@@ -2379,7 +2575,8 @@ pub fn _mm256_maskz_min_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm_mask_min_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, min, src.as_i16x8()))
@@ -2393,7 +2590,8 @@ pub fn _mm_mask_min_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsw))]
-pub fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, min, i16x8::ZERO))
@@ -2407,7 +2605,8 @@ pub fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe { simd_imin(a.as_i8x64(), b.as_i8x64()).as_m512i() }
 }
 
@@ -2418,7 +2617,8 @@ pub fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm512_mask_min_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_min_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, min, src.as_i8x64()))
@@ -2432,7 +2632,8 @@ pub fn _mm512_mask_min_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm512_maskz_min_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_min_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let min = _mm512_min_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, min, i8x64::ZERO))
@@ -2446,7 +2647,8 @@ pub fn _mm512_maskz_min_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm256_mask_min_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_min_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, min, src.as_i8x32()))
@@ -2460,7 +2662,8 @@ pub fn _mm256_mask_min_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm256_maskz_min_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_min_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let min = _mm256_min_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, min, i8x32::ZERO))
@@ -2474,7 +2677,8 @@ pub fn _mm256_maskz_min_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm_mask_min_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_min_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, min, src.as_i8x16()))
@@ -2488,7 +2692,8 @@ pub fn _mm_mask_min_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpminsb))]
-pub fn _mm_maskz_min_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_min_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let min = _mm_min_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, min, i8x16::ZERO))
@@ -2502,7 +2707,8 @@ pub fn _mm_maskz_min_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmplt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<u16x32, _>(simd_lt(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -2513,7 +2719,8 @@ pub fn _mm512_cmplt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmplt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2524,7 +2731,8 @@ pub fn _mm512_mask_cmplt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmplt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<u16x16, _>(simd_lt(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -2535,7 +2743,8 @@ pub fn _mm256_cmplt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmplt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2546,7 +2755,8 @@ pub fn _mm256_mask_cmplt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmplt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u16x8, _>(simd_lt(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -2557,7 +2767,8 @@ pub fn _mm_cmplt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmplt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2568,7 +2779,8 @@ pub fn _mm_mask_cmplt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmplt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<u8x64, _>(simd_lt(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -2579,7 +2791,8 @@ pub fn _mm512_cmplt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmplt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2590,7 +2803,8 @@ pub fn _mm512_mask_cmplt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmplt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<u8x32, _>(simd_lt(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -2601,7 +2815,8 @@ pub fn _mm256_cmplt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmplt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2612,7 +2827,8 @@ pub fn _mm256_mask_cmplt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmplt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<u8x16, _>(simd_lt(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -2623,7 +2839,8 @@ pub fn _mm_cmplt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmplt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2634,7 +2851,8 @@ pub fn _mm_mask_cmplt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmplt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<i16x32, _>(simd_lt(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -2645,7 +2863,8 @@ pub fn _mm512_cmplt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmplt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2656,7 +2875,8 @@ pub fn _mm512_mask_cmplt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmplt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<i16x16, _>(simd_lt(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -2667,7 +2887,8 @@ pub fn _mm256_cmplt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmplt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2678,7 +2899,8 @@ pub fn _mm256_mask_cmplt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmplt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i16x8, _>(simd_lt(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -2689,7 +2911,8 @@ pub fn _mm_cmplt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmplt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2700,7 +2923,8 @@ pub fn _mm_mask_cmplt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmplt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmplt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<i8x64, _>(simd_lt(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -2711,7 +2935,8 @@ pub fn _mm512_cmplt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmplt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmplt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2722,7 +2947,8 @@ pub fn _mm512_mask_cmplt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmplt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmplt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<i8x32, _>(simd_lt(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -2733,7 +2959,8 @@ pub fn _mm256_cmplt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmplt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmplt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2744,7 +2971,8 @@ pub fn _mm256_mask_cmplt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmplt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmplt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<i8x16, _>(simd_lt(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -2755,7 +2983,8 @@ pub fn _mm_cmplt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmplt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmplt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(k1, a, b)
 }
 
@@ -2766,7 +2995,8 @@ pub fn _mm_mask_cmplt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpgt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<u16x32, _>(simd_gt(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -2777,7 +3007,8 @@ pub fn _mm512_cmpgt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpgt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2788,7 +3019,8 @@ pub fn _mm512_mask_cmpgt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpgt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<u16x16, _>(simd_gt(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -2799,7 +3031,8 @@ pub fn _mm256_cmpgt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpgt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2810,7 +3043,8 @@ pub fn _mm256_mask_cmpgt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpgt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u16x8, _>(simd_gt(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -2821,7 +3055,8 @@ pub fn _mm_cmpgt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpgt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu16_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2832,7 +3067,8 @@ pub fn _mm_mask_cmpgt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpgt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<u8x64, _>(simd_gt(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -2843,7 +3079,8 @@ pub fn _mm512_cmpgt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpgt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2854,7 +3091,8 @@ pub fn _mm512_mask_cmpgt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpgt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<u8x32, _>(simd_gt(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -2865,7 +3103,8 @@ pub fn _mm256_cmpgt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpgt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2876,7 +3115,8 @@ pub fn _mm256_mask_cmpgt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpgt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<u8x16, _>(simd_gt(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -2887,7 +3127,8 @@ pub fn _mm_cmpgt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpgt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epu8_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2898,7 +3139,8 @@ pub fn _mm_mask_cmpgt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpgt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<i16x32, _>(simd_gt(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -2909,7 +3151,8 @@ pub fn _mm512_cmpgt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpgt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2920,7 +3163,8 @@ pub fn _mm512_mask_cmpgt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpgt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<i16x16, _>(simd_gt(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -2931,7 +3175,8 @@ pub fn _mm256_cmpgt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpgt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2942,7 +3187,8 @@ pub fn _mm256_mask_cmpgt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpgt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i16x8, _>(simd_gt(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -2953,7 +3199,8 @@ pub fn _mm_cmpgt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpgt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi16_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2964,7 +3211,8 @@ pub fn _mm_mask_cmpgt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpgt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpgt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<i8x64, _>(simd_gt(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -2975,7 +3223,8 @@ pub fn _mm512_cmpgt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpgt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpgt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -2986,7 +3235,8 @@ pub fn _mm512_mask_cmpgt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpgt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpgt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<i8x32, _>(simd_gt(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -2997,7 +3247,8 @@ pub fn _mm256_cmpgt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpgt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpgt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -3008,7 +3259,8 @@ pub fn _mm256_mask_cmpgt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpgt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpgt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<i8x16, _>(simd_gt(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -3019,7 +3271,8 @@ pub fn _mm_cmpgt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpgt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpgt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epi8_mask::<_MM_CMPINT_NLE>(k1, a, b)
 }
 
@@ -3030,7 +3283,8 @@ pub fn _mm_mask_cmpgt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmple_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<u16x32, _>(simd_le(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -3041,7 +3295,8 @@ pub fn _mm512_cmple_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmple_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3052,7 +3307,8 @@ pub fn _mm512_mask_cmple_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmple_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<u16x16, _>(simd_le(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -3063,7 +3319,8 @@ pub fn _mm256_cmple_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmple_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3074,7 +3331,8 @@ pub fn _mm256_mask_cmple_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmple_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u16x8, _>(simd_le(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -3085,7 +3343,8 @@ pub fn _mm_cmple_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmple_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu16_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3096,7 +3355,8 @@ pub fn _mm_mask_cmple_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmple_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<u8x64, _>(simd_le(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -3107,7 +3367,8 @@ pub fn _mm512_cmple_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmple_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3118,7 +3379,8 @@ pub fn _mm512_mask_cmple_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmple_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<u8x32, _>(simd_le(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -3129,7 +3391,8 @@ pub fn _mm256_cmple_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmple_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3140,7 +3403,8 @@ pub fn _mm256_mask_cmple_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmple_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<u8x16, _>(simd_le(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -3151,7 +3415,8 @@ pub fn _mm_cmple_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmple_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epu8_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3162,7 +3427,8 @@ pub fn _mm_mask_cmple_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmple_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<i16x32, _>(simd_le(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -3173,7 +3439,8 @@ pub fn _mm512_cmple_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmple_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3184,7 +3451,8 @@ pub fn _mm512_mask_cmple_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmple_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<i16x16, _>(simd_le(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -3195,7 +3463,8 @@ pub fn _mm256_cmple_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmple_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3206,7 +3475,8 @@ pub fn _mm256_mask_cmple_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmple_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i16x8, _>(simd_le(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -3217,7 +3487,8 @@ pub fn _mm_cmple_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmple_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi16_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3228,7 +3499,8 @@ pub fn _mm_mask_cmple_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmple_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmple_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<i8x64, _>(simd_le(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -3239,7 +3511,8 @@ pub fn _mm512_cmple_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmple_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmple_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3250,7 +3523,8 @@ pub fn _mm512_mask_cmple_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmple_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmple_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<i8x32, _>(simd_le(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -3261,7 +3535,8 @@ pub fn _mm256_cmple_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmple_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmple_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3272,7 +3547,8 @@ pub fn _mm256_mask_cmple_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmple_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmple_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<i8x16, _>(simd_le(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -3283,7 +3559,8 @@ pub fn _mm_cmple_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmple_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmple_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epi8_mask::<_MM_CMPINT_LE>(k1, a, b)
 }
 
@@ -3294,7 +3571,8 @@ pub fn _mm_mask_cmple_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpge_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<u16x32, _>(simd_ge(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -3305,7 +3583,8 @@ pub fn _mm512_cmpge_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpge_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3316,7 +3595,8 @@ pub fn _mm512_mask_cmpge_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpge_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<u16x16, _>(simd_ge(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -3327,7 +3607,8 @@ pub fn _mm256_cmpge_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpge_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3338,7 +3619,8 @@ pub fn _mm256_mask_cmpge_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpge_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u16x8, _>(simd_ge(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -3349,7 +3631,8 @@ pub fn _mm_cmpge_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpge_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu16_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3360,7 +3643,8 @@ pub fn _mm_mask_cmpge_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpge_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<u8x64, _>(simd_ge(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -3371,7 +3655,8 @@ pub fn _mm512_cmpge_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpge_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3382,7 +3667,8 @@ pub fn _mm512_mask_cmpge_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpge_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<u8x32, _>(simd_ge(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -3393,7 +3679,8 @@ pub fn _mm256_cmpge_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpge_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3404,7 +3691,8 @@ pub fn _mm256_mask_cmpge_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpge_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<u8x16, _>(simd_ge(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -3415,7 +3703,8 @@ pub fn _mm_cmpge_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpge_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epu8_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3426,7 +3715,8 @@ pub fn _mm_mask_cmpge_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpge_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<i16x32, _>(simd_ge(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -3437,7 +3727,8 @@ pub fn _mm512_cmpge_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpge_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3448,7 +3739,8 @@ pub fn _mm512_mask_cmpge_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpge_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<i16x16, _>(simd_ge(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -3459,7 +3751,8 @@ pub fn _mm256_cmpge_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpge_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3470,7 +3763,8 @@ pub fn _mm256_mask_cmpge_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpge_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i16x8, _>(simd_ge(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -3481,7 +3775,8 @@ pub fn _mm_cmpge_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpge_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi16_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3492,7 +3787,8 @@ pub fn _mm_mask_cmpge_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpge_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpge_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<i8x64, _>(simd_ge(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -3503,7 +3799,8 @@ pub fn _mm512_cmpge_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpge_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpge_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3514,7 +3811,8 @@ pub fn _mm512_mask_cmpge_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpge_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpge_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<i8x32, _>(simd_ge(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -3525,7 +3823,8 @@ pub fn _mm256_cmpge_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpge_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpge_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3536,7 +3835,8 @@ pub fn _mm256_mask_cmpge_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpge_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpge_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<i8x16, _>(simd_ge(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -3547,7 +3847,8 @@ pub fn _mm_cmpge_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpge_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpge_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epi8_mask::<_MM_CMPINT_NLT>(k1, a, b)
 }
 
@@ -3558,7 +3859,8 @@ pub fn _mm_mask_cmpge_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpeq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<u16x32, _>(simd_eq(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -3569,7 +3871,8 @@ pub fn _mm512_cmpeq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpeq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3580,7 +3883,8 @@ pub fn _mm512_mask_cmpeq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpeq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<u16x16, _>(simd_eq(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -3591,7 +3895,8 @@ pub fn _mm256_cmpeq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpeq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3602,7 +3907,8 @@ pub fn _mm256_mask_cmpeq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpeq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u16x8, _>(simd_eq(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -3613,7 +3919,8 @@ pub fn _mm_cmpeq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpeq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu16_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3624,7 +3931,8 @@ pub fn _mm_mask_cmpeq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpeq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<u8x64, _>(simd_eq(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -3635,7 +3943,8 @@ pub fn _mm512_cmpeq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpeq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3646,7 +3955,8 @@ pub fn _mm512_mask_cmpeq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpeq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<u8x32, _>(simd_eq(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -3657,7 +3967,8 @@ pub fn _mm256_cmpeq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpeq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3668,7 +3979,8 @@ pub fn _mm256_mask_cmpeq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpeq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<u8x16, _>(simd_eq(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -3679,7 +3991,8 @@ pub fn _mm_cmpeq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpeq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epu8_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3690,7 +4003,8 @@ pub fn _mm_mask_cmpeq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpeq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<i16x32, _>(simd_eq(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -3701,7 +4015,8 @@ pub fn _mm512_cmpeq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpeq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3712,7 +4027,8 @@ pub fn _mm512_mask_cmpeq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpeq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<i16x16, _>(simd_eq(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -3723,7 +4039,8 @@ pub fn _mm256_cmpeq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpeq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3734,7 +4051,8 @@ pub fn _mm256_mask_cmpeq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpeq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i16x8, _>(simd_eq(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -3745,7 +4063,8 @@ pub fn _mm_cmpeq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpeq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi16_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3756,7 +4075,8 @@ pub fn _mm_mask_cmpeq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpeq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpeq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<i8x64, _>(simd_eq(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -3767,7 +4087,8 @@ pub fn _mm512_cmpeq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpeq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpeq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3778,7 +4099,8 @@ pub fn _mm512_mask_cmpeq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpeq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpeq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<i8x32, _>(simd_eq(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -3789,7 +4111,8 @@ pub fn _mm256_cmpeq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpeq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpeq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3800,7 +4123,8 @@ pub fn _mm256_mask_cmpeq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpeq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpeq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<i8x16, _>(simd_eq(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -3811,7 +4135,8 @@ pub fn _mm_cmpeq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpeq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpeq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epi8_mask::<_MM_CMPINT_EQ>(k1, a, b)
 }
 
@@ -3822,7 +4147,8 @@ pub fn _mm_mask_cmpeq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpneq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<u16x32, _>(simd_ne(a.as_u16x32(), b.as_u16x32())) }
 }
 
@@ -3833,7 +4159,8 @@ pub fn _mm512_cmpneq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpneq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3844,7 +4171,8 @@ pub fn _mm512_mask_cmpneq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> _
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpneq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<u16x16, _>(simd_ne(a.as_u16x16(), b.as_u16x16())) }
 }
 
@@ -3855,7 +4183,8 @@ pub fn _mm256_cmpneq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpneq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3866,7 +4195,8 @@ pub fn _mm256_mask_cmpneq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> _
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpneq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<u16x8, _>(simd_ne(a.as_u16x8(), b.as_u16x8())) }
 }
 
@@ -3877,7 +4207,8 @@ pub fn _mm_cmpneq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpneq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epu16_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3888,7 +4219,8 @@ pub fn _mm_mask_cmpneq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpneq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<u8x64, _>(simd_ne(a.as_u8x64(), b.as_u8x64())) }
 }
 
@@ -3899,7 +4231,8 @@ pub fn _mm512_cmpneq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpneq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3910,7 +4243,8 @@ pub fn _mm512_mask_cmpneq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpneq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<u8x32, _>(simd_ne(a.as_u8x32(), b.as_u8x32())) }
 }
 
@@ -3921,7 +4255,8 @@ pub fn _mm256_cmpneq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpneq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3932,7 +4267,8 @@ pub fn _mm256_mask_cmpneq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpneq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<u8x16, _>(simd_ne(a.as_u8x16(), b.as_u8x16())) }
 }
 
@@ -3943,7 +4279,8 @@ pub fn _mm_cmpneq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpneq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epu8_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3954,7 +4291,8 @@ pub fn _mm_mask_cmpneq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mma
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpneq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe { simd_bitmask::<i16x32, _>(simd_ne(a.as_i16x32(), b.as_i16x32())) }
 }
 
@@ -3965,7 +4303,8 @@ pub fn _mm512_cmpneq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpneq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3976,7 +4315,8 @@ pub fn _mm512_mask_cmpneq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> _
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpneq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe { simd_bitmask::<i16x16, _>(simd_ne(a.as_i16x16(), b.as_i16x16())) }
 }
 
@@ -3987,7 +4327,8 @@ pub fn _mm256_cmpneq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpneq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -3998,7 +4339,8 @@ pub fn _mm256_mask_cmpneq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> _
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpneq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe { simd_bitmask::<i16x8, _>(simd_ne(a.as_i16x8(), b.as_i16x8())) }
 }
 
@@ -4009,7 +4351,8 @@ pub fn _mm_cmpneq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpneq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     _mm_mask_cmp_epi16_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -4020,7 +4363,8 @@ pub fn _mm_mask_cmpneq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_cmpneq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmpneq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe { simd_bitmask::<i8x64, _>(simd_ne(a.as_i8x64(), b.as_i8x64())) }
 }
 
@@ -4031,7 +4375,8 @@ pub fn _mm512_cmpneq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm512_mask_cmpneq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmpneq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -4042,7 +4387,8 @@ pub fn _mm512_mask_cmpneq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_cmpneq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmpneq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe { simd_bitmask::<i8x32, _>(simd_ne(a.as_i8x32(), b.as_i8x32())) }
 }
 
@@ -4053,7 +4399,8 @@ pub fn _mm256_cmpneq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm256_mask_cmpneq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmpneq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -4064,7 +4411,8 @@ pub fn _mm256_mask_cmpneq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_cmpneq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmpneq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe { simd_bitmask::<i8x16, _>(simd_ne(a.as_i8x16(), b.as_i8x16())) }
 }
 
@@ -4075,7 +4423,8 @@ pub fn _mm_cmpneq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpcmp))]
-pub fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     _mm_mask_cmp_epi8_mask::<_MM_CMPINT_NE>(k1, a, b)
 }
 
@@ -4087,7 +4436,8 @@ pub fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mma
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_cmp_epu16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epu16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u16x32();
@@ -4114,7 +4464,8 @@ pub fn _mm512_cmp_epu16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_mask_cmp_epu16_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epu16_mask<const IMM8: i32>(
     k1: __mmask32,
     a: __m512i,
     b: __m512i,
@@ -4146,7 +4497,8 @@ pub fn _mm512_mask_cmp_epu16_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_cmp_epu16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epu16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u16x16();
@@ -4173,7 +4525,8 @@ pub fn _mm256_cmp_epu16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_mask_cmp_epu16_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epu16_mask<const IMM8: i32>(
     k1: __mmask16,
     a: __m256i,
     b: __m256i,
@@ -4205,7 +4558,8 @@ pub fn _mm256_mask_cmp_epu16_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_cmp_epu16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epu16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u16x8();
@@ -4232,7 +4586,12 @@ pub fn _mm_cmp_epu16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_mask_cmp_epu16_mask<const IMM8: i32>(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epu16_mask<const IMM8: i32>(
+    k1: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u16x8();
@@ -4260,7 +4619,8 @@ pub fn _mm_mask_cmp_epu16_mask<const IMM8: i32>(k1: __mmask8, a: __m128i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_cmp_epu8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epu8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u8x64();
@@ -4287,7 +4647,8 @@ pub fn _mm512_cmp_epu8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask6
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_mask_cmp_epu8_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epu8_mask<const IMM8: i32>(
     k1: __mmask64,
     a: __m512i,
     b: __m512i,
@@ -4319,7 +4680,8 @@ pub fn _mm512_mask_cmp_epu8_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_cmp_epu8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epu8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u8x32();
@@ -4346,7 +4708,8 @@ pub fn _mm256_cmp_epu8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask3
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_mask_cmp_epu8_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epu8_mask<const IMM8: i32>(
     k1: __mmask32,
     a: __m256i,
     b: __m256i,
@@ -4378,7 +4741,8 @@ pub fn _mm256_mask_cmp_epu8_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_cmp_epu8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epu8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u8x16();
@@ -4405,7 +4769,12 @@ pub fn _mm_cmp_epu8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_mask_cmp_epu8_mask<const IMM8: i32>(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epu8_mask<const IMM8: i32>(
+    k1: __mmask16,
+    a: __m128i,
+    b: __m128i,
+) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_u8x16();
@@ -4433,7 +4802,8 @@ pub fn _mm_mask_cmp_epu8_mask<const IMM8: i32>(k1: __mmask16, a: __m128i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_cmp_epi16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epi16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i16x32();
@@ -4460,7 +4830,8 @@ pub fn _mm512_cmp_epi16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_mask_cmp_epi16_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epi16_mask<const IMM8: i32>(
     k1: __mmask32,
     a: __m512i,
     b: __m512i,
@@ -4492,7 +4863,8 @@ pub fn _mm512_mask_cmp_epi16_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_cmp_epi16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epi16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i16x16();
@@ -4519,7 +4891,8 @@ pub fn _mm256_cmp_epi16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_mask_cmp_epi16_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epi16_mask<const IMM8: i32>(
     k1: __mmask16,
     a: __m256i,
     b: __m256i,
@@ -4551,7 +4924,8 @@ pub fn _mm256_mask_cmp_epi16_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_cmp_epi16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epi16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i16x8();
@@ -4578,7 +4952,12 @@ pub fn _mm_cmp_epi16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_mask_cmp_epi16_mask<const IMM8: i32>(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epi16_mask<const IMM8: i32>(
+    k1: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i16x8();
@@ -4606,7 +4985,8 @@ pub fn _mm_mask_cmp_epi16_mask<const IMM8: i32>(k1: __mmask8, a: __m128i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_cmp_epi8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cmp_epi8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask64 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i8x64();
@@ -4633,7 +5013,8 @@ pub fn _mm512_cmp_epi8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask6
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm512_mask_cmp_epi8_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cmp_epi8_mask<const IMM8: i32>(
     k1: __mmask64,
     a: __m512i,
     b: __m512i,
@@ -4665,7 +5046,8 @@ pub fn _mm512_mask_cmp_epi8_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_cmp_epi8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cmp_epi8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i8x32();
@@ -4692,7 +5074,8 @@ pub fn _mm256_cmp_epi8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask3
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm256_mask_cmp_epi8_mask<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cmp_epi8_mask<const IMM8: i32>(
     k1: __mmask32,
     a: __m256i,
     b: __m256i,
@@ -4724,7 +5107,8 @@ pub fn _mm256_mask_cmp_epi8_mask<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_cmp_epi8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cmp_epi8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i8x16();
@@ -4751,7 +5135,12 @@ pub fn _mm_cmp_epi8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
-pub fn _mm_mask_cmp_epi8_mask<const IMM8: i32>(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cmp_epi8_mask<const IMM8: i32>(
+    k1: __mmask16,
+    a: __m128i,
+    b: __m128i,
+) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 3);
         let a = a.as_i8x16();
@@ -4777,7 +5166,8 @@ pub fn _mm_mask_cmp_epi8_mask<const IMM8: i32>(k1: __mmask16, a: __m128i, b: __m
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_add_epi16(a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_add_epi16(a: __m256i) -> i16 {
     unsafe { simd_reduce_add_ordered(a.as_i16x16(), 0) }
 }
 
@@ -4787,7 +5177,8 @@ pub fn _mm256_reduce_add_epi16(a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 {
     unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::ZERO), 0) }
 }
 
@@ -4797,7 +5188,8 @@ pub fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_add_epi16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_add_epi16(a: __m128i) -> i16 {
     unsafe { simd_reduce_add_ordered(a.as_i16x8(), 0) }
 }
 
@@ -4807,7 +5199,8 @@ pub fn _mm_reduce_add_epi16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 {
     unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::ZERO), 0) }
 }
 
@@ -4817,7 +5210,8 @@ pub fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_add_epi8(a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_add_epi8(a: __m256i) -> i8 {
     unsafe { simd_reduce_add_ordered(a.as_i8x32(), 0) }
 }
 
@@ -4827,7 +5221,8 @@ pub fn _mm256_reduce_add_epi8(a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 {
     unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::ZERO), 0) }
 }
 
@@ -4837,7 +5232,8 @@ pub fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_add_epi8(a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_add_epi8(a: __m128i) -> i8 {
     unsafe { simd_reduce_add_ordered(a.as_i8x16(), 0) }
 }
 
@@ -4847,7 +5243,8 @@ pub fn _mm_reduce_add_epi8(a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_add_epi8(k: __mmask16, a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_add_epi8(k: __mmask16, a: __m128i) -> i8 {
     unsafe { simd_reduce_add_ordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::ZERO), 0) }
 }
 
@@ -4857,7 +5254,8 @@ pub fn _mm_mask_reduce_add_epi8(k: __mmask16, a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_and_epi16(a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_and_epi16(a: __m256i) -> i16 {
     unsafe { simd_reduce_and(a.as_i16x16()) }
 }
 
@@ -4867,7 +5265,8 @@ pub fn _mm256_reduce_and_epi16(a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_and_epi16(k: __mmask16, a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_and_epi16(k: __mmask16, a: __m256i) -> i16 {
     unsafe {
         simd_reduce_and(simd_select_bitmask(
             k,
@@ -4883,7 +5282,8 @@ pub fn _mm256_mask_reduce_and_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_and_epi16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_and_epi16(a: __m128i) -> i16 {
     unsafe { simd_reduce_and(a.as_i16x8()) }
 }
 
@@ -4893,7 +5293,8 @@ pub fn _mm_reduce_and_epi16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_and_epi16(k: __mmask8, a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_and_epi16(k: __mmask8, a: __m128i) -> i16 {
     unsafe {
         simd_reduce_and(simd_select_bitmask(
             k,
@@ -4909,7 +5310,8 @@ pub fn _mm_mask_reduce_and_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_and_epi8(a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_and_epi8(a: __m256i) -> i8 {
     unsafe { simd_reduce_and(a.as_i8x32()) }
 }
 
@@ -4919,7 +5321,8 @@ pub fn _mm256_reduce_and_epi8(a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_and_epi8(k: __mmask32, a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_and_epi8(k: __mmask32, a: __m256i) -> i8 {
     unsafe {
         simd_reduce_and(simd_select_bitmask(
             k,
@@ -4935,7 +5338,8 @@ pub fn _mm256_mask_reduce_and_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_and_epi8(a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_and_epi8(a: __m128i) -> i8 {
     unsafe { simd_reduce_and(a.as_i8x16()) }
 }
 
@@ -4945,7 +5349,8 @@ pub fn _mm_reduce_and_epi8(a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_and_epi8(k: __mmask16, a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_and_epi8(k: __mmask16, a: __m128i) -> i8 {
     unsafe {
         simd_reduce_and(simd_select_bitmask(
             k,
@@ -4961,7 +5366,8 @@ pub fn _mm_mask_reduce_and_epi8(k: __mmask16, a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_max_epi16(a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_max_epi16(a: __m256i) -> i16 {
     unsafe { simd_reduce_max(a.as_i16x16()) }
 }
 
@@ -4971,7 +5377,8 @@ pub fn _mm256_reduce_max_epi16(a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_max_epi16(k: __mmask16, a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_max_epi16(k: __mmask16, a: __m256i) -> i16 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(-32768))) }
 }
 
@@ -4981,7 +5388,8 @@ pub fn _mm256_mask_reduce_max_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_max_epi16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_max_epi16(a: __m128i) -> i16 {
     unsafe { simd_reduce_max(a.as_i16x8()) }
 }
 
@@ -4991,7 +5399,8 @@ pub fn _mm_reduce_max_epi16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_max_epi16(k: __mmask8, a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_max_epi16(k: __mmask8, a: __m128i) -> i16 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(-32768))) }
 }
 
@@ -5001,7 +5410,8 @@ pub fn _mm_mask_reduce_max_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_max_epi8(a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_max_epi8(a: __m256i) -> i8 {
     unsafe { simd_reduce_max(a.as_i8x32()) }
 }
 
@@ -5011,7 +5421,8 @@ pub fn _mm256_reduce_max_epi8(a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_max_epi8(k: __mmask32, a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_max_epi8(k: __mmask32, a: __m256i) -> i8 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(-128))) }
 }
 
@@ -5021,7 +5432,8 @@ pub fn _mm256_mask_reduce_max_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_max_epi8(a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_max_epi8(a: __m128i) -> i8 {
     unsafe { simd_reduce_max(a.as_i8x16()) }
 }
 
@@ -5031,7 +5443,8 @@ pub fn _mm_reduce_max_epi8(a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_max_epi8(k: __mmask16, a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_max_epi8(k: __mmask16, a: __m128i) -> i8 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(-128))) }
 }
 
@@ -5041,7 +5454,8 @@ pub fn _mm_mask_reduce_max_epi8(k: __mmask16, a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_max_epu16(a: __m256i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_max_epu16(a: __m256i) -> u16 {
     unsafe { simd_reduce_max(a.as_u16x16()) }
 }
 
@@ -5051,7 +5465,8 @@ pub fn _mm256_reduce_max_epu16(a: __m256i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_max_epu16(k: __mmask16, a: __m256i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_max_epu16(k: __mmask16, a: __m256i) -> u16 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u16x16(), u16x16::ZERO)) }
 }
 
@@ -5061,7 +5476,8 @@ pub fn _mm256_mask_reduce_max_epu16(k: __mmask16, a: __m256i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_max_epu16(a: __m128i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_max_epu16(a: __m128i) -> u16 {
     unsafe { simd_reduce_max(a.as_u16x8()) }
 }
 
@@ -5071,7 +5487,8 @@ pub fn _mm_reduce_max_epu16(a: __m128i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_max_epu16(k: __mmask8, a: __m128i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_max_epu16(k: __mmask8, a: __m128i) -> u16 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u16x8(), u16x8::ZERO)) }
 }
 
@@ -5081,7 +5498,8 @@ pub fn _mm_mask_reduce_max_epu16(k: __mmask8, a: __m128i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_max_epu8(a: __m256i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_max_epu8(a: __m256i) -> u8 {
     unsafe { simd_reduce_max(a.as_u8x32()) }
 }
 
@@ -5091,7 +5509,8 @@ pub fn _mm256_reduce_max_epu8(a: __m256i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_max_epu8(k: __mmask32, a: __m256i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_max_epu8(k: __mmask32, a: __m256i) -> u8 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u8x32(), u8x32::ZERO)) }
 }
 
@@ -5101,7 +5520,8 @@ pub fn _mm256_mask_reduce_max_epu8(k: __mmask32, a: __m256i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_max_epu8(a: __m128i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_max_epu8(a: __m128i) -> u8 {
     unsafe { simd_reduce_max(a.as_u8x16()) }
 }
 
@@ -5111,7 +5531,8 @@ pub fn _mm_reduce_max_epu8(a: __m128i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_max_epu8(k: __mmask16, a: __m128i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_max_epu8(k: __mmask16, a: __m128i) -> u8 {
     unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u8x16(), u8x16::ZERO)) }
 }
 
@@ -5121,7 +5542,8 @@ pub fn _mm_mask_reduce_max_epu8(k: __mmask16, a: __m128i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_min_epi16(a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_min_epi16(a: __m256i) -> i16 {
     unsafe { simd_reduce_min(a.as_i16x16()) }
 }
 
@@ -5131,7 +5553,8 @@ pub fn _mm256_reduce_min_epi16(a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_min_epi16(k: __mmask16, a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_min_epi16(k: __mmask16, a: __m256i) -> i16 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(0x7fff))) }
 }
 
@@ -5141,7 +5564,8 @@ pub fn _mm256_mask_reduce_min_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_min_epi16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_min_epi16(a: __m128i) -> i16 {
     unsafe { simd_reduce_min(a.as_i16x8()) }
 }
 
@@ -5151,7 +5575,8 @@ pub fn _mm_reduce_min_epi16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_min_epi16(k: __mmask8, a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_min_epi16(k: __mmask8, a: __m128i) -> i16 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(0x7fff))) }
 }
 
@@ -5161,7 +5586,8 @@ pub fn _mm_mask_reduce_min_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_min_epi8(a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_min_epi8(a: __m256i) -> i8 {
     unsafe { simd_reduce_min(a.as_i8x32()) }
 }
 
@@ -5171,7 +5597,8 @@ pub fn _mm256_reduce_min_epi8(a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_min_epi8(k: __mmask32, a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_min_epi8(k: __mmask32, a: __m256i) -> i8 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(0x7f))) }
 }
 
@@ -5181,7 +5608,8 @@ pub fn _mm256_mask_reduce_min_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_min_epi8(a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_min_epi8(a: __m128i) -> i8 {
     unsafe { simd_reduce_min(a.as_i8x16()) }
 }
 
@@ -5191,7 +5619,8 @@ pub fn _mm_reduce_min_epi8(a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_min_epi8(k: __mmask16, a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_min_epi8(k: __mmask16, a: __m128i) -> i8 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(0x7f))) }
 }
 
@@ -5201,7 +5630,8 @@ pub fn _mm_mask_reduce_min_epi8(k: __mmask16, a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_min_epu16(a: __m256i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_min_epu16(a: __m256i) -> u16 {
     unsafe { simd_reduce_min(a.as_u16x16()) }
 }
 
@@ -5211,7 +5641,8 @@ pub fn _mm256_reduce_min_epu16(a: __m256i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_min_epu16(k: __mmask16, a: __m256i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_min_epu16(k: __mmask16, a: __m256i) -> u16 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u16x16(), u16x16::splat(0xffff))) }
 }
 
@@ -5221,7 +5652,8 @@ pub fn _mm256_mask_reduce_min_epu16(k: __mmask16, a: __m256i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_min_epu16(a: __m128i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_min_epu16(a: __m128i) -> u16 {
     unsafe { simd_reduce_min(a.as_u16x8()) }
 }
 
@@ -5231,7 +5663,8 @@ pub fn _mm_reduce_min_epu16(a: __m128i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_min_epu16(k: __mmask8, a: __m128i) -> u16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_min_epu16(k: __mmask8, a: __m128i) -> u16 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u16x8(), u16x8::splat(0xffff))) }
 }
 
@@ -5241,7 +5674,8 @@ pub fn _mm_mask_reduce_min_epu16(k: __mmask8, a: __m128i) -> u16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_min_epu8(a: __m256i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_min_epu8(a: __m256i) -> u8 {
     unsafe { simd_reduce_min(a.as_u8x32()) }
 }
 
@@ -5251,7 +5685,8 @@ pub fn _mm256_reduce_min_epu8(a: __m256i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_min_epu8(k: __mmask32, a: __m256i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_min_epu8(k: __mmask32, a: __m256i) -> u8 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u8x32(), u8x32::splat(0xff))) }
 }
 
@@ -5261,7 +5696,8 @@ pub fn _mm256_mask_reduce_min_epu8(k: __mmask32, a: __m256i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_min_epu8(a: __m128i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_min_epu8(a: __m128i) -> u8 {
     unsafe { simd_reduce_min(a.as_u8x16()) }
 }
 
@@ -5271,7 +5707,8 @@ pub fn _mm_reduce_min_epu8(a: __m128i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_min_epu8(k: __mmask16, a: __m128i) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_min_epu8(k: __mmask16, a: __m128i) -> u8 {
     unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u8x16(), u8x16::splat(0xff))) }
 }
 
@@ -5281,7 +5718,8 @@ pub fn _mm_mask_reduce_min_epu8(k: __mmask16, a: __m128i) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 {
     unsafe { simd_reduce_mul_ordered(a.as_i16x16(), 1) }
 }
 
@@ -5291,7 +5729,8 @@ pub fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 {
     unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(1)), 1) }
 }
 
@@ -5301,7 +5740,8 @@ pub fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_mul_epi16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_mul_epi16(a: __m128i) -> i16 {
     unsafe { simd_reduce_mul_ordered(a.as_i16x8(), 1) }
 }
 
@@ -5311,7 +5751,8 @@ pub fn _mm_reduce_mul_epi16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 {
     unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(1)), 1) }
 }
 
@@ -5321,7 +5762,8 @@ pub fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 {
     unsafe { simd_reduce_mul_ordered(a.as_i8x32(), 1) }
 }
 
@@ -5331,7 +5773,8 @@ pub fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 {
     unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(1)), 1) }
 }
 
@@ -5341,7 +5784,8 @@ pub fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_mul_epi8(a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_mul_epi8(a: __m128i) -> i8 {
     unsafe { simd_reduce_mul_ordered(a.as_i8x16(), 1) }
 }
 
@@ -5351,7 +5795,8 @@ pub fn _mm_reduce_mul_epi8(a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_mul_epi8(k: __mmask16, a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_mul_epi8(k: __mmask16, a: __m128i) -> i8 {
     unsafe { simd_reduce_mul_ordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(1)), 1) }
 }
 
@@ -5361,7 +5806,8 @@ pub fn _mm_mask_reduce_mul_epi8(k: __mmask16, a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_or_epi16(a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_or_epi16(a: __m256i) -> i16 {
     unsafe { simd_reduce_or(a.as_i16x16()) }
 }
 
@@ -5371,7 +5817,8 @@ pub fn _mm256_reduce_or_epi16(a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_or_epi16(k: __mmask16, a: __m256i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_or_epi16(k: __mmask16, a: __m256i) -> i16 {
     unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i16x16(), i16x16::ZERO)) }
 }
 
@@ -5381,7 +5828,8 @@ pub fn _mm256_mask_reduce_or_epi16(k: __mmask16, a: __m256i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_or_epi16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_or_epi16(a: __m128i) -> i16 {
     unsafe { simd_reduce_or(a.as_i16x8()) }
 }
 
@@ -5391,7 +5839,8 @@ pub fn _mm_reduce_or_epi16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_or_epi16(k: __mmask8, a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_or_epi16(k: __mmask8, a: __m128i) -> i16 {
     unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i16x8(), i16x8::ZERO)) }
 }
 
@@ -5401,7 +5850,8 @@ pub fn _mm_mask_reduce_or_epi16(k: __mmask8, a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_reduce_or_epi8(a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_or_epi8(a: __m256i) -> i8 {
     unsafe { simd_reduce_or(a.as_i8x32()) }
 }
 
@@ -5411,7 +5861,8 @@ pub fn _mm256_reduce_or_epi8(a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_reduce_or_epi8(k: __mmask32, a: __m256i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_reduce_or_epi8(k: __mmask32, a: __m256i) -> i8 {
     unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i8x32(), i8x32::ZERO)) }
 }
 
@@ -5421,7 +5872,8 @@ pub fn _mm256_mask_reduce_or_epi8(k: __mmask32, a: __m256i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_reduce_or_epi8(a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_or_epi8(a: __m128i) -> i8 {
     unsafe { simd_reduce_or(a.as_i8x16()) }
 }
 
@@ -5431,7 +5883,8 @@ pub fn _mm_reduce_or_epi8(a: __m128i) -> i8 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_reduce_or_epi8(k: __mmask16, a: __m128i) -> i8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_reduce_or_epi8(k: __mmask16, a: __m128i) -> i8 {
     unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i8x16(), i8x16::ZERO)) }
 }
 
@@ -5442,7 +5895,8 @@ pub fn _mm_mask_reduce_or_epi8(k: __mmask16, a: __m128i) -> i8 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
-pub unsafe fn _mm512_loadu_epi16(mem_addr: *const i16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_epi16(mem_addr: *const i16) -> __m512i {
     ptr::read_unaligned(mem_addr as *const __m512i)
 }
 
@@ -5453,7 +5907,8 @@ pub unsafe fn _mm512_loadu_epi16(mem_addr: *const i16) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
-pub unsafe fn _mm256_loadu_epi16(mem_addr: *const i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_epi16(mem_addr: *const i16) -> __m256i {
     ptr::read_unaligned(mem_addr as *const __m256i)
 }
 
@@ -5464,7 +5919,8 @@ pub unsafe fn _mm256_loadu_epi16(mem_addr: *const i16) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
-pub unsafe fn _mm_loadu_epi16(mem_addr: *const i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_epi16(mem_addr: *const i16) -> __m128i {
     ptr::read_unaligned(mem_addr as *const __m128i)
 }
 
@@ -5475,7 +5931,8 @@ pub unsafe fn _mm_loadu_epi16(mem_addr: *const i16) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
-pub unsafe fn _mm512_loadu_epi8(mem_addr: *const i8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_epi8(mem_addr: *const i8) -> __m512i {
     ptr::read_unaligned(mem_addr as *const __m512i)
 }
 
@@ -5486,7 +5943,8 @@ pub unsafe fn _mm512_loadu_epi8(mem_addr: *const i8) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
-pub unsafe fn _mm256_loadu_epi8(mem_addr: *const i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_epi8(mem_addr: *const i8) -> __m256i {
     ptr::read_unaligned(mem_addr as *const __m256i)
 }
 
@@ -5497,7 +5955,8 @@ pub unsafe fn _mm256_loadu_epi8(mem_addr: *const i8) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
-pub unsafe fn _mm_loadu_epi8(mem_addr: *const i8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_epi8(mem_addr: *const i8) -> __m128i {
     ptr::read_unaligned(mem_addr as *const __m128i)
 }
 
@@ -5508,7 +5967,8 @@ pub unsafe fn _mm_loadu_epi8(mem_addr: *const i8) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
-pub unsafe fn _mm512_storeu_epi16(mem_addr: *mut i16, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_epi16(mem_addr: *mut i16, a: __m512i) {
     ptr::write_unaligned(mem_addr as *mut __m512i, a);
 }
 
@@ -5519,7 +5979,8 @@ pub unsafe fn _mm512_storeu_epi16(mem_addr: *mut i16, a: __m512i) {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
-pub unsafe fn _mm256_storeu_epi16(mem_addr: *mut i16, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_epi16(mem_addr: *mut i16, a: __m256i) {
     ptr::write_unaligned(mem_addr as *mut __m256i, a);
 }
 
@@ -5530,7 +5991,8 @@ pub unsafe fn _mm256_storeu_epi16(mem_addr: *mut i16, a: __m256i) {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
-pub unsafe fn _mm_storeu_epi16(mem_addr: *mut i16, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_epi16(mem_addr: *mut i16, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut __m128i, a);
 }
 
@@ -5541,7 +6003,8 @@ pub unsafe fn _mm_storeu_epi16(mem_addr: *mut i16, a: __m128i) {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
-pub unsafe fn _mm512_storeu_epi8(mem_addr: *mut i8, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_epi8(mem_addr: *mut i8, a: __m512i) {
     ptr::write_unaligned(mem_addr as *mut __m512i, a);
 }
 
@@ -5552,7 +6015,8 @@ pub unsafe fn _mm512_storeu_epi8(mem_addr: *mut i8, a: __m512i) {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
-pub unsafe fn _mm256_storeu_epi8(mem_addr: *mut i8, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_epi8(mem_addr: *mut i8, a: __m256i) {
     ptr::write_unaligned(mem_addr as *mut __m256i, a);
 }
 
@@ -5563,7 +6027,8 @@ pub unsafe fn _mm256_storeu_epi8(mem_addr: *mut i8, a: __m256i) {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
-pub unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) {
     ptr::write_unaligned(mem_addr as *mut __m128i, a);
 }
 
@@ -5576,7 +6041,12 @@ pub unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) {
 #[target_feature(enable = "avx512bw")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_loadu_epi16(src: __m512i, k: __mmask32, mem_addr: *const i16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_loadu_epi16(
+    src: __m512i,
+    k: __mmask32,
+    mem_addr: *const i16,
+) -> __m512i {
     let mask = simd_select_bitmask(k, i16x32::splat(!0), i16x32::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i16x32()).as_m512i()
 }
@@ -5590,7 +6060,8 @@ pub unsafe fn _mm512_mask_loadu_epi16(src: __m512i, k: __mmask32, mem_addr: *con
 #[target_feature(enable = "avx512bw")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __m512i {
     _mm512_mask_loadu_epi16(_mm512_setzero_si512(), k, mem_addr)
 }
 
@@ -5603,7 +6074,12 @@ pub unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __
 #[target_feature(enable = "avx512bw")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_loadu_epi8(src: __m512i, k: __mmask64, mem_addr: *const i8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_loadu_epi8(
+    src: __m512i,
+    k: __mmask64,
+    mem_addr: *const i8,
+) -> __m512i {
     let mask = simd_select_bitmask(k, i8x64::splat(!0), i8x64::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i8x64()).as_m512i()
 }
@@ -5617,7 +6093,8 @@ pub unsafe fn _mm512_mask_loadu_epi8(src: __m512i, k: __mmask64, mem_addr: *cons
 #[target_feature(enable = "avx512bw")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m512i {
     _mm512_mask_loadu_epi8(_mm512_setzero_si512(), k, mem_addr)
 }
 
@@ -5630,7 +6107,12 @@ pub unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m5
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_loadu_epi16(src: __m256i, k: __mmask16, mem_addr: *const i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_loadu_epi16(
+    src: __m256i,
+    k: __mmask16,
+    mem_addr: *const i16,
+) -> __m256i {
     let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i16x16()).as_m256i()
 }
@@ -5644,7 +6126,8 @@ pub unsafe fn _mm256_mask_loadu_epi16(src: __m256i, k: __mmask16, mem_addr: *con
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __m256i {
     _mm256_mask_loadu_epi16(_mm256_setzero_si256(), k, mem_addr)
 }
 
@@ -5657,7 +6140,12 @@ pub unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_loadu_epi8(src: __m256i, k: __mmask32, mem_addr: *const i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_loadu_epi8(
+    src: __m256i,
+    k: __mmask32,
+    mem_addr: *const i8,
+) -> __m256i {
     let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i8x32()).as_m256i()
 }
@@ -5671,7 +6159,8 @@ pub unsafe fn _mm256_mask_loadu_epi8(src: __m256i, k: __mmask32, mem_addr: *cons
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m256i {
     _mm256_mask_loadu_epi8(_mm256_setzero_si256(), k, mem_addr)
 }
 
@@ -5684,7 +6173,12 @@ pub unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_loadu_epi16(src: __m128i, k: __mmask8, mem_addr: *const i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_loadu_epi16(
+    src: __m128i,
+    k: __mmask8,
+    mem_addr: *const i16,
+) -> __m128i {
     let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i16x8()).as_m128i()
 }
@@ -5698,7 +6192,8 @@ pub unsafe fn _mm_mask_loadu_epi16(src: __m128i, k: __mmask8, mem_addr: *const i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128i {
     _mm_mask_loadu_epi16(_mm_setzero_si128(), k, mem_addr)
 }
 
@@ -5711,7 +6206,12 @@ pub unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_loadu_epi8(src: __m128i, k: __mmask16, mem_addr: *const i8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_loadu_epi8(
+    src: __m128i,
+    k: __mmask16,
+    mem_addr: *const i8,
+) -> __m128i {
     let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO);
     simd_masked_load!(SimdAlign::Unaligned, mask, mem_addr, src.as_i8x16()).as_m128i()
 }
@@ -5725,7 +6225,8 @@ pub unsafe fn _mm_mask_loadu_epi8(src: __m128i, k: __mmask16, mem_addr: *const i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i {
     _mm_mask_loadu_epi8(_mm_setzero_si128(), k, mem_addr)
 }
 
@@ -5737,7 +6238,8 @@ pub unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: __m512i) {
     let mask = simd_select_bitmask(mask, i16x32::splat(!0), i16x32::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i16x32());
 }
@@ -5750,7 +6252,8 @@ pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: _
 #[target_feature(enable = "avx512bw")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m512i) {
     let mask = simd_select_bitmask(mask, i8x64::splat(!0), i8x64::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i8x64());
 }
@@ -5763,7 +6266,8 @@ pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: __m256i) {
     let mask = simd_select_bitmask(mask, i16x16::splat(!0), i16x16::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i16x16());
 }
@@ -5776,7 +6280,8 @@ pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: _
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m256i) {
     let mask = simd_select_bitmask(mask, i8x32::splat(!0), i8x32::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i8x32());
 }
@@ -5789,7 +6294,8 @@ pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m128i) {
     let mask = simd_select_bitmask(mask, i16x8::splat(!0), i16x8::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i16x8());
 }
@@ -5802,7 +6308,8 @@ pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m12
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128i) {
     let mask = simd_select_bitmask(mask, i8x16::splat(!0), i8x16::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, a.as_i8x16());
 }
@@ -5814,7 +6321,8 @@ pub unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let r: i32x32 = simd_mul(simd_cast(a.as_i16x32()), simd_cast(b.as_i16x32()));
         let even: i32x16 = simd_shuffle!(
@@ -5838,7 +6346,8 @@ pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, src.as_i32x16()))
@@ -5852,7 +6361,8 @@ pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, i32x16::ZERO))
@@ -5866,7 +6376,8 @@ pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, src.as_i32x8()))
@@ -5880,7 +6391,8 @@ pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, i32x8::ZERO))
@@ -5894,7 +6406,8 @@ pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, src.as_i32x4()))
@@ -5908,7 +6421,8 @@ pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, i32x4::ZERO))
@@ -6397,7 +6911,8 @@ pub fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm512_avg_epu16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_avg_epu16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = simd_cast::<_, u32x32>(a.as_u16x32());
         let b = simd_cast::<_, u32x32>(b.as_u16x32());
@@ -6413,7 +6928,8 @@ pub fn _mm512_avg_epu16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm512_mask_avg_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_avg_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let avg = _mm512_avg_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, avg, src.as_u16x32()))
@@ -6427,7 +6943,8 @@ pub fn _mm512_mask_avg_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm512_maskz_avg_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_avg_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let avg = _mm512_avg_epu16(a, b).as_u16x32();
         transmute(simd_select_bitmask(k, avg, u16x32::ZERO))
@@ -6441,7 +6958,8 @@ pub fn _mm512_maskz_avg_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm256_mask_avg_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_avg_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let avg = _mm256_avg_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, avg, src.as_u16x16()))
@@ -6455,7 +6973,8 @@ pub fn _mm256_mask_avg_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm256_maskz_avg_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_avg_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let avg = _mm256_avg_epu16(a, b).as_u16x16();
         transmute(simd_select_bitmask(k, avg, u16x16::ZERO))
@@ -6469,7 +6988,8 @@ pub fn _mm256_maskz_avg_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm_mask_avg_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_avg_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let avg = _mm_avg_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, avg, src.as_u16x8()))
@@ -6483,7 +7003,8 @@ pub fn _mm_mask_avg_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgw))]
-pub fn _mm_maskz_avg_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_avg_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let avg = _mm_avg_epu16(a, b).as_u16x8();
         transmute(simd_select_bitmask(k, avg, u16x8::ZERO))
@@ -6497,7 +7018,8 @@ pub fn _mm_maskz_avg_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm512_avg_epu8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_avg_epu8(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = simd_cast::<_, u16x64>(a.as_u8x64());
         let b = simd_cast::<_, u16x64>(b.as_u8x64());
@@ -6513,7 +7035,8 @@ pub fn _mm512_avg_epu8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm512_mask_avg_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_avg_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let avg = _mm512_avg_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, avg, src.as_u8x64()))
@@ -6527,7 +7050,8 @@ pub fn _mm512_mask_avg_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm512_maskz_avg_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_avg_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let avg = _mm512_avg_epu8(a, b).as_u8x64();
         transmute(simd_select_bitmask(k, avg, u8x64::ZERO))
@@ -6541,7 +7065,8 @@ pub fn _mm512_maskz_avg_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm256_mask_avg_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_avg_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let avg = _mm256_avg_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, avg, src.as_u8x32()))
@@ -6555,7 +7080,8 @@ pub fn _mm256_mask_avg_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm256_maskz_avg_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_avg_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let avg = _mm256_avg_epu8(a, b).as_u8x32();
         transmute(simd_select_bitmask(k, avg, u8x32::ZERO))
@@ -6569,7 +7095,8 @@ pub fn _mm256_maskz_avg_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm_mask_avg_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_avg_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let avg = _mm_avg_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, avg, src.as_u8x16()))
@@ -6583,7 +7110,8 @@ pub fn _mm_mask_avg_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpavgb))]
-pub fn _mm_maskz_avg_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_avg_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let avg = _mm_avg_epu8(a, b).as_u8x16();
         transmute(simd_select_bitmask(k, avg, u8x16::ZERO))
@@ -6693,7 +7221,8 @@ pub fn _mm_maskz_sll_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_slli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_slli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 16 {
@@ -6712,7 +7241,12 @@ pub fn _mm512_slli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_slli_epi16<const IMM8: u32>(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_slli_epi16<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 16 {
@@ -6732,7 +7266,8 @@ pub fn _mm512_mask_slli_epi16<const IMM8: u32>(src: __m512i, k: __mmask32, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_slli_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_slli_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 16 {
@@ -6752,7 +7287,12 @@ pub fn _mm512_maskz_slli_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_slli_epi16<const IMM8: u32>(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_slli_epi16<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 16 {
@@ -6772,7 +7312,8 @@ pub fn _mm256_mask_slli_epi16<const IMM8: u32>(src: __m256i, k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_slli_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_slli_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 16 {
@@ -6792,7 +7333,12 @@ pub fn _mm256_maskz_slli_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_slli_epi16<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_slli_epi16<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 16 {
@@ -6812,7 +7358,8 @@ pub fn _mm_mask_slli_epi16<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_slli_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_slli_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 16 {
@@ -6831,7 +7378,8 @@ pub fn _mm_maskz_slli_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u16x32();
         let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
@@ -6847,7 +7395,13 @@ pub fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm512_mask_sllv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sllv_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_sllv_epi16(a, count).as_i16x32();
         transmute(simd_select_bitmask(k, shf, src.as_i16x32()))
@@ -6861,7 +7415,8 @@ pub fn _mm512_mask_sllv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_sllv_epi16(a, count).as_i16x32();
         transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -6875,7 +7430,8 @@ pub fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u16x16();
         let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
@@ -6891,7 +7447,13 @@ pub fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm256_mask_sllv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sllv_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_sllv_epi16(a, count).as_i16x16();
         transmute(simd_select_bitmask(k, shf, src.as_i16x16()))
@@ -6905,7 +7467,8 @@ pub fn _mm256_mask_sllv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_sllv_epi16(a, count).as_i16x16();
         transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -6919,7 +7482,8 @@ pub fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u16x8();
         let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
@@ -6935,7 +7499,8 @@ pub fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_sllv_epi16(a, count).as_i16x8();
         transmute(simd_select_bitmask(k, shf, src.as_i16x8()))
@@ -6949,7 +7514,8 @@ pub fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsllvw))]
-pub fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_sllv_epi16(a, count).as_i16x8();
         transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -7059,7 +7625,8 @@ pub fn _mm_maskz_srl_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_srli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         if IMM8 >= 16 {
@@ -7078,7 +7645,12 @@ pub fn _mm512_srli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_srli_epi16<const IMM8: u32>(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srli_epi16<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = if IMM8 >= 16 {
@@ -7098,7 +7670,8 @@ pub fn _mm512_mask_srli_epi16<const IMM8: u32>(src: __m512i, k: __mmask32, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_srli_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srli_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         //imm8 should be u32, it seems the document to verify is incorrect
@@ -7119,7 +7692,12 @@ pub fn _mm512_maskz_srli_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_srli_epi16<const IMM8: i32>(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srli_epi16<const IMM8: i32>(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_srli_epi16::<IMM8>(a);
@@ -7135,7 +7713,8 @@ pub fn _mm256_mask_srli_epi16<const IMM8: i32>(src: __m256i, k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_srli_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srli_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_srli_epi16::<IMM8>(a);
@@ -7151,7 +7730,12 @@ pub fn _mm256_maskz_srli_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_srli_epi16<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srli_epi16<const IMM8: i32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_srli_epi16::<IMM8>(a);
@@ -7167,7 +7751,8 @@ pub fn _mm_mask_srli_epi16<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_srli_epi16::<IMM8>(a);
@@ -7182,7 +7767,8 @@ pub fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u16x32();
         let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
@@ -7198,7 +7784,13 @@ pub fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm512_mask_srlv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srlv_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_srlv_epi16(a, count).as_i16x32();
         transmute(simd_select_bitmask(k, shf, src.as_i16x32()))
@@ -7212,7 +7804,8 @@ pub fn _mm512_mask_srlv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_srlv_epi16(a, count).as_i16x32();
         transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -7226,7 +7819,8 @@ pub fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u16x16();
         let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
@@ -7242,7 +7836,13 @@ pub fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm256_mask_srlv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srlv_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_srlv_epi16(a, count).as_i16x16();
         transmute(simd_select_bitmask(k, shf, src.as_i16x16()))
@@ -7256,7 +7856,8 @@ pub fn _mm256_mask_srlv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_srlv_epi16(a, count).as_i16x16();
         transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -7270,7 +7871,8 @@ pub fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u16x8();
         let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
@@ -7286,7 +7888,8 @@ pub fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srlv_epi16(a, count).as_i16x8();
         transmute(simd_select_bitmask(k, shf, src.as_i16x8()))
@@ -7300,7 +7903,8 @@ pub fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrlvw))]
-pub fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srlv_epi16(a, count).as_i16x8();
         transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -7410,7 +8014,8 @@ pub fn _mm_maskz_sra_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_srai_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srai_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         transmute(simd_shr(a.as_i16x32(), i16x32::splat(IMM8.min(15) as i16)))
@@ -7425,7 +8030,12 @@ pub fn _mm512_srai_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_srai_epi16<const IMM8: u32>(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srai_epi16<const IMM8: u32>(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i16x32(), i16x32::splat(IMM8.min(15) as i16));
@@ -7441,7 +8051,8 @@ pub fn _mm512_mask_srai_epi16<const IMM8: u32>(src: __m512i, k: __mmask32, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_srai_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srai_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = simd_shr(a.as_i16x32(), i16x32::splat(IMM8.min(15) as i16));
@@ -7457,7 +8068,12 @@ pub fn _mm512_maskz_srai_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_srai_epi16<const IMM8: u32>(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srai_epi16<const IMM8: u32>(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = simd_shr(a.as_i16x16(), i16x16::splat(IMM8.min(15) as i16));
@@ -7473,7 +8089,8 @@ pub fn _mm256_mask_srai_epi16<const IMM8: u32>(src: __m256i, k: __mmask16, a: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_srai_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srai_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = simd_shr(a.as_i16x16(), i16x16::splat(IMM8.min(15) as i16));
@@ -7489,7 +8106,12 @@ pub fn _mm256_maskz_srai_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_srai_epi16<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srai_epi16<const IMM8: u32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = simd_shr(a.as_i16x8(), i16x8::splat(IMM8.min(15) as i16));
@@ -7505,7 +8127,8 @@ pub fn _mm_mask_srai_epi16<const IMM8: u32>(src: __m128i, k: __mmask8, a: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_srai_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srai_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = simd_shr(a.as_i16x8(), i16x8::splat(IMM8.min(15) as i16));
@@ -7520,7 +8143,8 @@ pub fn _mm_maskz_srai_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let count = count.as_u16x32();
         let no_overflow: u16x32 = simd_lt(count, u16x32::splat(u16::BITS as u16));
@@ -7536,7 +8160,13 @@ pub fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm512_mask_srav_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_srav_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    count: __m512i,
+) -> __m512i {
     unsafe {
         let shf = _mm512_srav_epi16(a, count).as_i16x32();
         transmute(simd_select_bitmask(k, shf, src.as_i16x32()))
@@ -7550,7 +8180,8 @@ pub fn _mm512_mask_srav_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_srav_epi16(a, count).as_i16x32();
         transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -7564,7 +8195,8 @@ pub fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let count = count.as_u16x16();
         let no_overflow: u16x16 = simd_lt(count, u16x16::splat(u16::BITS as u16));
@@ -7580,7 +8212,13 @@ pub fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm256_mask_srav_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_srav_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    count: __m256i,
+) -> __m256i {
     unsafe {
         let shf = _mm256_srav_epi16(a, count).as_i16x16();
         transmute(simd_select_bitmask(k, shf, src.as_i16x16()))
@@ -7594,7 +8232,8 @@ pub fn _mm256_mask_srav_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_srav_epi16(a, count).as_i16x16();
         transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -7608,7 +8247,8 @@ pub fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let count = count.as_u16x8();
         let no_overflow: u16x8 = simd_lt(count, u16x8::splat(u16::BITS as u16));
@@ -7624,7 +8264,8 @@ pub fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srav_epi16(a, count).as_i16x8();
         transmute(simd_select_bitmask(k, shf, src.as_i16x8()))
@@ -7638,7 +8279,8 @@ pub fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsravw))]
-pub fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_srav_epi16(a, count).as_i16x8();
         transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -7968,7 +8610,8 @@ pub fn _mm_maskz_permutexvar_epi16(k: __mmask8, idx: __m128i, a: __m128i) -> __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw
-pub fn _mm512_mask_blend_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i16x32(), a.as_i16x32())) }
 }
 
@@ -7979,7 +8622,8 @@ pub fn _mm512_mask_blend_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw
-pub fn _mm256_mask_blend_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i16x16(), a.as_i16x16())) }
 }
 
@@ -7990,7 +8634,8 @@ pub fn _mm256_mask_blend_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw
-pub fn _mm_mask_blend_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i16x8(), a.as_i16x8())) }
 }
 
@@ -8001,7 +8646,8 @@ pub fn _mm_mask_blend_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb
-pub fn _mm512_mask_blend_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i8x64(), a.as_i8x64())) }
 }
 
@@ -8012,7 +8658,8 @@ pub fn _mm512_mask_blend_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb
-pub fn _mm256_mask_blend_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i8x32(), a.as_i8x32())) }
 }
 
@@ -8023,7 +8670,8 @@ pub fn _mm256_mask_blend_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb
-pub fn _mm_mask_blend_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_select_bitmask(k, b.as_i8x16(), a.as_i8x16())) }
 }
 
@@ -8034,7 +8682,8 @@ pub fn _mm_mask_blend_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm512_broadcastw_epi16(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastw_epi16(a: __m128i) -> __m512i {
     unsafe {
         let a = _mm512_castsi128_si512(a).as_i16x32();
         let ret: i16x32 = simd_shuffle!(
@@ -8056,7 +8705,8 @@ pub fn _mm512_broadcastw_epi16(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm512_mask_broadcastw_epi16(src: __m512i, k: __mmask32, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcastw_epi16(src: __m512i, k: __mmask32, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastw_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, broadcast, src.as_i16x32()))
@@ -8070,7 +8720,8 @@ pub fn _mm512_mask_broadcastw_epi16(src: __m512i, k: __mmask32, a: __m128i) -> _
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm512_maskz_broadcastw_epi16(k: __mmask32, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcastw_epi16(k: __mmask32, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastw_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, broadcast, i16x32::ZERO))
@@ -8084,7 +8735,8 @@ pub fn _mm512_maskz_broadcastw_epi16(k: __mmask32, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm256_mask_broadcastw_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcastw_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastw_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, broadcast, src.as_i16x16()))
@@ -8098,7 +8750,8 @@ pub fn _mm256_mask_broadcastw_epi16(src: __m256i, k: __mmask16, a: __m128i) -> _
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm256_maskz_broadcastw_epi16(k: __mmask16, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcastw_epi16(k: __mmask16, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastw_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, broadcast, i16x16::ZERO))
@@ -8112,7 +8765,8 @@ pub fn _mm256_maskz_broadcastw_epi16(k: __mmask16, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm_mask_broadcastw_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_broadcastw_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastw_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, broadcast, src.as_i16x8()))
@@ -8126,7 +8780,8 @@ pub fn _mm_mask_broadcastw_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m12
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm_maskz_broadcastw_epi16(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_broadcastw_epi16(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastw_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, broadcast, i16x8::ZERO))
@@ -8140,7 +8795,8 @@ pub fn _mm_maskz_broadcastw_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm512_broadcastb_epi8(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastb_epi8(a: __m128i) -> __m512i {
     unsafe {
         let a = _mm512_castsi128_si512(a).as_i8x64();
         let ret: i8x64 = simd_shuffle!(
@@ -8163,7 +8819,8 @@ pub fn _mm512_broadcastb_epi8(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm512_mask_broadcastb_epi8(src: __m512i, k: __mmask64, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcastb_epi8(src: __m512i, k: __mmask64, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastb_epi8(a).as_i8x64();
         transmute(simd_select_bitmask(k, broadcast, src.as_i8x64()))
@@ -8177,7 +8834,8 @@ pub fn _mm512_mask_broadcastb_epi8(src: __m512i, k: __mmask64, a: __m128i) -> __
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm512_maskz_broadcastb_epi8(k: __mmask64, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcastb_epi8(k: __mmask64, a: __m128i) -> __m512i {
     unsafe {
         let broadcast = _mm512_broadcastb_epi8(a).as_i8x64();
         transmute(simd_select_bitmask(k, broadcast, i8x64::ZERO))
@@ -8191,7 +8849,8 @@ pub fn _mm512_maskz_broadcastb_epi8(k: __mmask64, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm256_mask_broadcastb_epi8(src: __m256i, k: __mmask32, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcastb_epi8(src: __m256i, k: __mmask32, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastb_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, broadcast, src.as_i8x32()))
@@ -8205,7 +8864,8 @@ pub fn _mm256_mask_broadcastb_epi8(src: __m256i, k: __mmask32, a: __m128i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm256_maskz_broadcastb_epi8(k: __mmask32, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcastb_epi8(k: __mmask32, a: __m128i) -> __m256i {
     unsafe {
         let broadcast = _mm256_broadcastb_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, broadcast, i8x32::ZERO))
@@ -8219,7 +8879,8 @@ pub fn _mm256_maskz_broadcastb_epi8(k: __mmask32, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm_mask_broadcastb_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_broadcastb_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastb_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, broadcast, src.as_i8x16()))
@@ -8233,7 +8894,8 @@ pub fn _mm_mask_broadcastb_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m12
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastb))]
-pub fn _mm_maskz_broadcastb_epi8(k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_broadcastb_epi8(k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         let broadcast = _mm_broadcastb_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, broadcast, i8x16::ZERO))
@@ -8247,7 +8909,8 @@ pub fn _mm_maskz_broadcastb_epi8(k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm512_unpackhi_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpackhi_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i16x32();
         let b = b.as_i16x32();
@@ -8277,7 +8940,13 @@ pub fn _mm512_unpackhi_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm512_mask_unpackhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpackhi_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i16x32()))
@@ -8291,7 +8960,8 @@ pub fn _mm512_mask_unpackhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm512_maskz_unpackhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpackhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, unpackhi, i16x32::ZERO))
@@ -8305,7 +8975,13 @@ pub fn _mm512_maskz_unpackhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m5
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm256_mask_unpackhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpackhi_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i16x16()))
@@ -8319,7 +8995,8 @@ pub fn _mm256_mask_unpackhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm256_maskz_unpackhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpackhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, unpackhi, i16x16::ZERO))
@@ -8333,7 +9010,8 @@ pub fn _mm256_maskz_unpackhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm_mask_unpackhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpackhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i16x8()))
@@ -8347,7 +9025,8 @@ pub fn _mm_mask_unpackhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhwd))]
-pub fn _mm_maskz_unpackhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpackhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, unpackhi, i16x8::ZERO))
@@ -8361,7 +9040,8 @@ pub fn _mm_maskz_unpackhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm512_unpackhi_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpackhi_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i8x64();
         let b = b.as_i8x64();
@@ -8399,7 +9079,13 @@ pub fn _mm512_unpackhi_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm512_mask_unpackhi_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpackhi_epi8(
+    src: __m512i,
+    k: __mmask64,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i8x64()))
@@ -8413,7 +9099,8 @@ pub fn _mm512_mask_unpackhi_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m5
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm512_maskz_unpackhi_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpackhi_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpackhi = _mm512_unpackhi_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, unpackhi, i8x64::ZERO))
@@ -8427,7 +9114,13 @@ pub fn _mm512_maskz_unpackhi_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m51
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm256_mask_unpackhi_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpackhi_epi8(
+    src: __m256i,
+    k: __mmask32,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i8x32()))
@@ -8441,7 +9134,8 @@ pub fn _mm256_mask_unpackhi_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm256_maskz_unpackhi_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpackhi_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpackhi = _mm256_unpackhi_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, unpackhi, i8x32::ZERO))
@@ -8455,7 +9149,8 @@ pub fn _mm256_maskz_unpackhi_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m25
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm_mask_unpackhi_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpackhi_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, unpackhi, src.as_i8x16()))
@@ -8469,7 +9164,8 @@ pub fn _mm_mask_unpackhi_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpckhbw))]
-pub fn _mm_maskz_unpackhi_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpackhi_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpackhi = _mm_unpackhi_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, unpackhi, i8x16::ZERO))
@@ -8483,7 +9179,8 @@ pub fn _mm_maskz_unpackhi_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm512_unpacklo_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpacklo_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i16x32();
         let b = b.as_i16x32();
@@ -8513,7 +9210,13 @@ pub fn _mm512_unpacklo_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm512_mask_unpacklo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpacklo_epi16(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i16x32()))
@@ -8527,7 +9230,8 @@ pub fn _mm512_mask_unpacklo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm512_maskz_unpacklo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpacklo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi16(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, unpacklo, i16x32::ZERO))
@@ -8541,7 +9245,13 @@ pub fn _mm512_maskz_unpacklo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m5
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm256_mask_unpacklo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpacklo_epi16(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i16x16()))
@@ -8555,7 +9265,8 @@ pub fn _mm256_mask_unpacklo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm256_maskz_unpacklo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpacklo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi16(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, unpacklo, i16x16::ZERO))
@@ -8569,7 +9280,8 @@ pub fn _mm256_maskz_unpacklo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm_mask_unpacklo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpacklo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i16x8()))
@@ -8583,7 +9295,8 @@ pub fn _mm_mask_unpacklo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklwd))]
-pub fn _mm_maskz_unpacklo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpacklo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi16(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, unpacklo, i16x8::ZERO))
@@ -8597,7 +9310,8 @@ pub fn _mm_maskz_unpacklo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm512_unpacklo_epi8(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_unpacklo_epi8(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let a = a.as_i8x64();
         let b = b.as_i8x64();
@@ -8635,7 +9349,13 @@ pub fn _mm512_unpacklo_epi8(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm512_mask_unpacklo_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_unpacklo_epi8(
+    src: __m512i,
+    k: __mmask64,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i8x64()))
@@ -8649,7 +9369,8 @@ pub fn _mm512_mask_unpacklo_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m5
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm512_maskz_unpacklo_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_unpacklo_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let unpacklo = _mm512_unpacklo_epi8(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, unpacklo, i8x64::ZERO))
@@ -8663,7 +9384,13 @@ pub fn _mm512_maskz_unpacklo_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m51
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm256_mask_unpacklo_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_unpacklo_epi8(
+    src: __m256i,
+    k: __mmask32,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i8x32()))
@@ -8677,7 +9404,8 @@ pub fn _mm256_mask_unpacklo_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm256_maskz_unpacklo_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_unpacklo_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let unpacklo = _mm256_unpacklo_epi8(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, unpacklo, i8x32::ZERO))
@@ -8691,7 +9419,8 @@ pub fn _mm256_maskz_unpacklo_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m25
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm_mask_unpacklo_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_unpacklo_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, unpacklo, src.as_i8x16()))
@@ -8705,7 +9434,8 @@ pub fn _mm_mask_unpacklo_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpunpcklbw))]
-pub fn _mm_maskz_unpacklo_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_unpacklo_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let unpacklo = _mm_unpacklo_epi8(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, unpacklo, i8x16::ZERO))
@@ -8719,7 +9449,8 @@ pub fn _mm_maskz_unpacklo_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
-pub fn _mm512_mask_mov_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mov_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i16x32();
         transmute(simd_select_bitmask(k, mov, src.as_i16x32()))
@@ -8733,7 +9464,8 @@ pub fn _mm512_mask_mov_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
-pub fn _mm512_maskz_mov_epi16(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mov_epi16(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i16x32();
         transmute(simd_select_bitmask(k, mov, i16x32::ZERO))
@@ -8747,7 +9479,8 @@ pub fn _mm512_maskz_mov_epi16(k: __mmask32, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
-pub fn _mm256_mask_mov_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mov_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i16x16();
         transmute(simd_select_bitmask(k, mov, src.as_i16x16()))
@@ -8761,7 +9494,8 @@ pub fn _mm256_mask_mov_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
-pub fn _mm256_maskz_mov_epi16(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mov_epi16(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i16x16();
         transmute(simd_select_bitmask(k, mov, i16x16::ZERO))
@@ -8775,7 +9509,8 @@ pub fn _mm256_maskz_mov_epi16(k: __mmask16, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
-pub fn _mm_mask_mov_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mov_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i16x8();
         transmute(simd_select_bitmask(k, mov, src.as_i16x8()))
@@ -8789,7 +9524,8 @@ pub fn _mm_mask_mov_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu16))]
-pub fn _mm_maskz_mov_epi16(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mov_epi16(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i16x8();
         transmute(simd_select_bitmask(k, mov, i16x8::ZERO))
@@ -8803,7 +9539,8 @@ pub fn _mm_maskz_mov_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
-pub fn _mm512_mask_mov_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mov_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i8x64();
         transmute(simd_select_bitmask(k, mov, src.as_i8x64()))
@@ -8817,7 +9554,8 @@ pub fn _mm512_mask_mov_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
-pub fn _mm512_maskz_mov_epi8(k: __mmask64, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mov_epi8(k: __mmask64, a: __m512i) -> __m512i {
     unsafe {
         let mov = a.as_i8x64();
         transmute(simd_select_bitmask(k, mov, i8x64::ZERO))
@@ -8831,7 +9569,8 @@ pub fn _mm512_maskz_mov_epi8(k: __mmask64, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
-pub fn _mm256_mask_mov_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mov_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i8x32();
         transmute(simd_select_bitmask(k, mov, src.as_i8x32()))
@@ -8845,7 +9584,8 @@ pub fn _mm256_mask_mov_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
-pub fn _mm256_maskz_mov_epi8(k: __mmask32, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mov_epi8(k: __mmask32, a: __m256i) -> __m256i {
     unsafe {
         let mov = a.as_i8x32();
         transmute(simd_select_bitmask(k, mov, i8x32::ZERO))
@@ -8859,7 +9599,8 @@ pub fn _mm256_maskz_mov_epi8(k: __mmask32, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
-pub fn _mm_mask_mov_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mov_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i8x16();
         transmute(simd_select_bitmask(k, mov, src.as_i8x16()))
@@ -8873,7 +9614,8 @@ pub fn _mm_mask_mov_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vmovdqu8))]
-pub fn _mm_maskz_mov_epi8(k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mov_epi8(k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         let mov = a.as_i8x16();
         transmute(simd_select_bitmask(k, mov, i8x16::ZERO))
@@ -8887,7 +9629,8 @@ pub fn _mm_maskz_mov_epi8(k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm512_mask_set1_epi16(src: __m512i, k: __mmask32, a: i16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_set1_epi16(src: __m512i, k: __mmask32, a: i16) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, r, src.as_i16x32()))
@@ -8901,7 +9644,8 @@ pub fn _mm512_mask_set1_epi16(src: __m512i, k: __mmask32, a: i16) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm512_maskz_set1_epi16(k: __mmask32, a: i16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_set1_epi16(k: __mmask32, a: i16) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, r, i16x32::ZERO))
@@ -8915,7 +9659,8 @@ pub fn _mm512_maskz_set1_epi16(k: __mmask32, a: i16) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm256_mask_set1_epi16(src: __m256i, k: __mmask16, a: i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_set1_epi16(src: __m256i, k: __mmask16, a: i16) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, r, src.as_i16x16()))
@@ -8929,7 +9674,8 @@ pub fn _mm256_mask_set1_epi16(src: __m256i, k: __mmask16, a: i16) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm256_maskz_set1_epi16(k: __mmask16, a: i16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_set1_epi16(k: __mmask16, a: i16) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, r, i16x16::ZERO))
@@ -8943,7 +9689,8 @@ pub fn _mm256_maskz_set1_epi16(k: __mmask16, a: i16) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm_mask_set1_epi16(src: __m128i, k: __mmask8, a: i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_set1_epi16(src: __m128i, k: __mmask8, a: i16) -> __m128i {
     unsafe {
         let r = _mm_set1_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, r, src.as_i16x8()))
@@ -8957,7 +9704,8 @@ pub fn _mm_mask_set1_epi16(src: __m128i, k: __mmask8, a: i16) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcastw))]
-pub fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i {
     unsafe {
         let r = _mm_set1_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, r, i16x8::ZERO))
@@ -8971,7 +9719,8 @@ pub fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))]
-pub fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi8(a).as_i8x64();
         transmute(simd_select_bitmask(k, r, src.as_i8x64()))
@@ -8985,7 +9734,8 @@ pub fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))]
-pub fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i {
     unsafe {
         let r = _mm512_set1_epi8(a).as_i8x64();
         transmute(simd_select_bitmask(k, r, i8x64::ZERO))
@@ -8999,7 +9749,8 @@ pub fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))]
-pub fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, r, src.as_i8x32()))
@@ -9013,7 +9764,8 @@ pub fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))]
-pub fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i {
     unsafe {
         let r = _mm256_set1_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, r, i8x32::ZERO))
@@ -9027,7 +9779,8 @@ pub fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))]
-pub fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i {
     unsafe {
         let r = _mm_set1_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, r, src.as_i8x16()))
@@ -9041,7 +9794,8 @@ pub fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))]
-pub fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i {
     unsafe {
         let r = _mm_set1_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, r, i8x16::ZERO))
@@ -9056,7 +9810,8 @@ pub fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_shufflelo_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shufflelo_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let a = a.as_i16x32();
@@ -9110,7 +9865,8 @@ pub fn _mm512_shufflelo_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_shufflelo_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shufflelo_epi16<const IMM8: i32>(
     src: __m512i,
     k: __mmask32,
     a: __m512i,
@@ -9130,7 +9886,8 @@ pub fn _mm512_mask_shufflelo_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm512_shufflelo_epi16::<IMM8>(a);
@@ -9146,7 +9903,8 @@ pub fn _mm512_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_shufflelo_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shufflelo_epi16<const IMM8: i32>(
     src: __m256i,
     k: __mmask16,
     a: __m256i,
@@ -9166,7 +9924,8 @@ pub fn _mm256_mask_shufflelo_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shuffle = _mm256_shufflelo_epi16::<IMM8>(a);
@@ -9182,7 +9941,12 @@ pub fn _mm256_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_shufflelo_epi16<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shufflelo_epi16<const IMM8: i32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shuffle = _mm_shufflelo_epi16::<IMM8>(a);
@@ -9198,7 +9962,8 @@ pub fn _mm_mask_shufflelo_epi16<const IMM8: i32>(src: __m128i, k: __mmask8, a: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shuffle = _mm_shufflelo_epi16::<IMM8>(a);
@@ -9214,7 +9979,8 @@ pub fn _mm_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_shufflehi_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shufflehi_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let a = a.as_i16x32();
@@ -9268,7 +10034,8 @@ pub fn _mm512_shufflehi_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_mask_shufflehi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shufflehi_epi16<const IMM8: i32>(
     src: __m512i,
     k: __mmask32,
     a: __m512i,
@@ -9288,7 +10055,8 @@ pub fn _mm512_mask_shufflehi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm512_shufflehi_epi16::<IMM8>(a);
@@ -9304,7 +10072,8 @@ pub fn _mm512_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_mask_shufflehi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shufflehi_epi16<const IMM8: i32>(
     src: __m256i,
     k: __mmask16,
     a: __m256i,
@@ -9324,7 +10093,8 @@ pub fn _mm256_mask_shufflehi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shuffle = _mm256_shufflehi_epi16::<IMM8>(a);
@@ -9340,7 +10110,12 @@ pub fn _mm256_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_mask_shufflehi_epi16<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shufflehi_epi16<const IMM8: i32>(
+    src: __m128i,
+    k: __mmask8,
+    a: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shuffle = _mm_shufflehi_epi16::<IMM8>(a);
@@ -9356,7 +10131,8 @@ pub fn _mm_mask_shufflehi_epi16<const IMM8: i32>(src: __m128i, k: __mmask8, a: _
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shuffle = _mm_shufflehi_epi16::<IMM8>(a);
@@ -9466,7 +10242,8 @@ pub fn _mm_maskz_shuffle_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmw))]
-pub fn _mm512_test_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_test_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpneq_epi16_mask(and, zero)
@@ -9479,7 +10256,8 @@ pub fn _mm512_test_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmw))]
-pub fn _mm512_mask_test_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_test_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpneq_epi16_mask(k, and, zero)
@@ -9492,7 +10270,8 @@ pub fn _mm512_mask_test_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mm
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmw))]
-pub fn _mm256_test_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_test_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpneq_epi16_mask(and, zero)
@@ -9505,7 +10284,8 @@ pub fn _mm256_test_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmw))]
-pub fn _mm256_mask_test_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_test_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpneq_epi16_mask(k, and, zero)
@@ -9518,7 +10298,8 @@ pub fn _mm256_mask_test_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mm
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmw))]
-pub fn _mm_test_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_test_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpneq_epi16_mask(and, zero)
@@ -9531,7 +10312,8 @@ pub fn _mm_test_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmw))]
-pub fn _mm_mask_test_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_test_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpneq_epi16_mask(k, and, zero)
@@ -9544,7 +10326,8 @@ pub fn _mm_mask_test_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmb))]
-pub fn _mm512_test_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_test_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpneq_epi8_mask(and, zero)
@@ -9557,7 +10340,8 @@ pub fn _mm512_test_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmb))]
-pub fn _mm512_mask_test_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_test_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpneq_epi8_mask(k, and, zero)
@@ -9570,7 +10354,8 @@ pub fn _mm512_mask_test_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mma
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmb))]
-pub fn _mm256_test_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_test_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpneq_epi8_mask(and, zero)
@@ -9583,7 +10368,8 @@ pub fn _mm256_test_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmb))]
-pub fn _mm256_mask_test_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_test_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpneq_epi8_mask(k, and, zero)
@@ -9596,7 +10382,8 @@ pub fn _mm256_mask_test_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mma
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmb))]
-pub fn _mm_test_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_test_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpneq_epi8_mask(and, zero)
@@ -9609,7 +10396,8 @@ pub fn _mm_test_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestmb))]
-pub fn _mm_mask_test_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_test_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpneq_epi8_mask(k, and, zero)
@@ -9622,7 +10410,8 @@ pub fn _mm_mask_test_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask1
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmw))]
-pub fn _mm512_testn_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_testn_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpeq_epi16_mask(and, zero)
@@ -9635,7 +10424,8 @@ pub fn _mm512_testn_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmw))]
-pub fn _mm512_mask_testn_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_testn_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpeq_epi16_mask(k, and, zero)
@@ -9648,7 +10438,8 @@ pub fn _mm512_mask_testn_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmw))]
-pub fn _mm256_testn_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_testn_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpeq_epi16_mask(and, zero)
@@ -9661,7 +10452,8 @@ pub fn _mm256_testn_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmw))]
-pub fn _mm256_mask_testn_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_testn_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpeq_epi16_mask(k, and, zero)
@@ -9674,7 +10466,8 @@ pub fn _mm256_mask_testn_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmw))]
-pub fn _mm_testn_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testn_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpeq_epi16_mask(and, zero)
@@ -9687,7 +10480,8 @@ pub fn _mm_testn_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmw))]
-pub fn _mm_mask_testn_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_testn_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpeq_epi16_mask(k, and, zero)
@@ -9700,7 +10494,8 @@ pub fn _mm_mask_testn_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmb))]
-pub fn _mm512_testn_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_testn_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_cmpeq_epi8_mask(and, zero)
@@ -9713,7 +10508,8 @@ pub fn _mm512_testn_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmb))]
-pub fn _mm512_mask_testn_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_testn_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
     let and = _mm512_and_si512(a, b);
     let zero = _mm512_setzero_si512();
     _mm512_mask_cmpeq_epi8_mask(k, and, zero)
@@ -9726,7 +10522,8 @@ pub fn _mm512_mask_testn_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mm
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmb))]
-pub fn _mm256_testn_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_testn_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_cmpeq_epi8_mask(and, zero)
@@ -9739,7 +10536,8 @@ pub fn _mm256_testn_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmb))]
-pub fn _mm256_mask_testn_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_testn_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
     let and = _mm256_and_si256(a, b);
     let zero = _mm256_setzero_si256();
     _mm256_mask_cmpeq_epi8_mask(k, and, zero)
@@ -9752,7 +10550,8 @@ pub fn _mm256_mask_testn_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mm
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmb))]
-pub fn _mm_testn_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_testn_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_cmpeq_epi8_mask(and, zero)
@@ -9765,7 +10564,8 @@ pub fn _mm_testn_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vptestnmb))]
-pub fn _mm_mask_testn_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_testn_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
     let and = _mm_and_si128(a, b);
     let zero = _mm_setzero_si128();
     _mm_mask_cmpeq_epi8_mask(k, and, zero)
@@ -9778,7 +10578,8 @@ pub fn _mm_mask_testn_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] //should be kmovq
-pub unsafe fn _store_mask64(mem_addr: *mut __mmask64, a: __mmask64) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _store_mask64(mem_addr: *mut __mmask64, a: __mmask64) {
     ptr::write(mem_addr as *mut __mmask64, a);
 }
 
@@ -9789,7 +10590,8 @@ pub unsafe fn _store_mask64(mem_addr: *mut __mmask64, a: __mmask64) {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] //should be kmovd
-pub unsafe fn _store_mask32(mem_addr: *mut __mmask32, a: __mmask32) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _store_mask32(mem_addr: *mut __mmask32, a: __mmask32) {
     ptr::write(mem_addr as *mut __mmask32, a);
 }
 
@@ -9800,7 +10602,8 @@ pub unsafe fn _store_mask32(mem_addr: *mut __mmask32, a: __mmask32) {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] //should be kmovq
-pub unsafe fn _load_mask64(mem_addr: *const __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _load_mask64(mem_addr: *const __mmask64) -> __mmask64 {
     ptr::read(mem_addr as *const __mmask64)
 }
 
@@ -9811,7 +10614,8 @@ pub unsafe fn _load_mask64(mem_addr: *const __mmask64) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] //should be kmovd
-pub unsafe fn _load_mask32(mem_addr: *const __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _load_mask32(mem_addr: *const __mmask32) -> __mmask32 {
     ptr::read(mem_addr as *const __mmask32)
 }
 
@@ -10010,7 +10814,8 @@ pub fn _mm_maskz_dbsad_epu8<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovw2m))]
-pub fn _mm512_movepi16_mask(a: __m512i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movepi16_mask(a: __m512i) -> __mmask32 {
     let filter = _mm512_set1_epi16(1 << 15);
     let a = _mm512_and_si512(a, filter);
     _mm512_cmpeq_epi16_mask(a, filter)
@@ -10023,7 +10828,8 @@ pub fn _mm512_movepi16_mask(a: __m512i) -> __mmask32 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovw2m))]
-pub fn _mm256_movepi16_mask(a: __m256i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movepi16_mask(a: __m256i) -> __mmask16 {
     let filter = _mm256_set1_epi16(1 << 15);
     let a = _mm256_and_si256(a, filter);
     _mm256_cmpeq_epi16_mask(a, filter)
@@ -10036,7 +10842,8 @@ pub fn _mm256_movepi16_mask(a: __m256i) -> __mmask16 {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovw2m))]
-pub fn _mm_movepi16_mask(a: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movepi16_mask(a: __m128i) -> __mmask8 {
     let filter = _mm_set1_epi16(1 << 15);
     let a = _mm_and_si128(a, filter);
     _mm_cmpeq_epi16_mask(a, filter)
@@ -10049,7 +10856,8 @@ pub fn _mm_movepi16_mask(a: __m128i) -> __mmask8 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovb2m))]
-pub fn _mm512_movepi8_mask(a: __m512i) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movepi8_mask(a: __m512i) -> __mmask64 {
     let filter = _mm512_set1_epi8(1 << 7);
     let a = _mm512_and_si512(a, filter);
     _mm512_cmpeq_epi8_mask(a, filter)
@@ -10061,9 +10869,11 @@ pub fn _mm512_movepi8_mask(a: __m512i) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-#[cfg_attr(test, assert_instr(vpmovmskb))] // should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than
+#[cfg_attr(test, assert_instr(vpmovmskb))]
+// should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than
 // using vpmovb2m plus converting the mask register to a standard register.
-pub fn _mm256_movepi8_mask(a: __m256i) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movepi8_mask(a: __m256i) -> __mmask32 {
     let filter = _mm256_set1_epi8(1 << 7);
     let a = _mm256_and_si256(a, filter);
     _mm256_cmpeq_epi8_mask(a, filter)
@@ -10075,9 +10885,11 @@ pub fn _mm256_movepi8_mask(a: __m256i) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-#[cfg_attr(test, assert_instr(vpmovmskb))] // should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than
+#[cfg_attr(test, assert_instr(vpmovmskb))]
+// should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than
 // using vpmovb2m plus converting the mask register to a standard register.
-pub fn _mm_movepi8_mask(a: __m128i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movepi8_mask(a: __m128i) -> __mmask16 {
     let filter = _mm_set1_epi8(1 << 7);
     let a = _mm_and_si128(a, filter);
     _mm_cmpeq_epi8_mask(a, filter)
@@ -10090,7 +10902,8 @@ pub fn _mm_movepi8_mask(a: __m128i) -> __mmask16 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovm2w))]
-pub fn _mm512_movm_epi16(k: __mmask32) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movm_epi16(k: __mmask32) -> __m512i {
     unsafe {
         let one = _mm512_set1_epi16(
             1 << 15
@@ -10122,7 +10935,8 @@ pub fn _mm512_movm_epi16(k: __mmask32) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovm2w))]
-pub fn _mm256_movm_epi16(k: __mmask16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movm_epi16(k: __mmask16) -> __m256i {
     unsafe {
         let one = _mm256_set1_epi16(
             1 << 15
@@ -10154,7 +10968,8 @@ pub fn _mm256_movm_epi16(k: __mmask16) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovm2w))]
-pub fn _mm_movm_epi16(k: __mmask8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movm_epi16(k: __mmask8) -> __m128i {
     unsafe {
         let one = _mm_set1_epi16(
             1 << 15
@@ -10186,7 +11001,8 @@ pub fn _mm_movm_epi16(k: __mmask8) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovm2b))]
-pub fn _mm512_movm_epi8(k: __mmask64) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movm_epi8(k: __mmask64) -> __m512i {
     unsafe {
         let one =
             _mm512_set1_epi8(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0)
@@ -10202,7 +11018,8 @@ pub fn _mm512_movm_epi8(k: __mmask64) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovm2b))]
-pub fn _mm256_movm_epi8(k: __mmask32) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movm_epi8(k: __mmask32) -> __m256i {
     unsafe {
         let one =
             _mm256_set1_epi8(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0)
@@ -10218,7 +11035,8 @@ pub fn _mm256_movm_epi8(k: __mmask32) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovm2b))]
-pub fn _mm_movm_epi8(k: __mmask16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movm_epi8(k: __mmask16) -> __m128i {
     unsafe {
         let one =
             _mm_set1_epi8(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0)
@@ -10233,7 +11051,8 @@ pub fn _mm_movm_epi8(k: __mmask16) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtmask32_u32(a: __mmask32) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtmask32_u32(a: __mmask32) -> u32 {
     a
 }
 
@@ -10243,7 +11062,8 @@ pub fn _cvtmask32_u32(a: __mmask32) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtu32_mask32(a: u32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtu32_mask32(a: u32) -> __mmask32 {
     a
 }
 
@@ -10253,7 +11073,8 @@ pub fn _cvtu32_mask32(a: u32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
     a.wrapping_add(b)
 }
 
@@ -10263,7 +11084,8 @@ pub fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
     a.wrapping_add(b)
 }
 
@@ -10273,7 +11095,8 @@ pub fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kand_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kand_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
     a & b
 }
 
@@ -10283,7 +11106,8 @@ pub fn _kand_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kand_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kand_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
     a & b
 }
 
@@ -10293,7 +11117,8 @@ pub fn _kand_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _knot_mask32(a: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _knot_mask32(a: __mmask32) -> __mmask32 {
     !a
 }
 
@@ -10303,7 +11128,8 @@ pub fn _knot_mask32(a: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _knot_mask64(a: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _knot_mask64(a: __mmask64) -> __mmask64 {
     !a
 }
 
@@ -10313,7 +11139,8 @@ pub fn _knot_mask64(a: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kandn_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kandn_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
     _knot_mask32(a) & b
 }
 
@@ -10323,7 +11150,8 @@ pub fn _kandn_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kandn_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kandn_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
     _knot_mask64(a) & b
 }
 
@@ -10333,7 +11161,8 @@ pub fn _kandn_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
     a | b
 }
 
@@ -10343,7 +11172,8 @@ pub fn _kor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
     a | b
 }
 
@@ -10353,7 +11183,8 @@ pub fn _kor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kxor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
     a ^ b
 }
 
@@ -10363,7 +11194,8 @@ pub fn _kxor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kxor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
     a ^ b
 }
 
@@ -10373,7 +11205,8 @@ pub fn _kxor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kxnor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxnor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
     _knot_mask32(a ^ b)
 }
 
@@ -10383,7 +11216,8 @@ pub fn _kxnor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kxnor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxnor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
     _knot_mask64(a ^ b)
 }
 
@@ -10394,7 +11228,8 @@ pub fn _kxnor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _kortest_mask32_u8(a: __mmask32, b: __mmask32, all_ones: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _kortest_mask32_u8(a: __mmask32, b: __mmask32, all_ones: *mut u8) -> u8 {
     let tmp = _kor_mask32(a, b);
     *all_ones = (tmp == 0xffffffff) as u8;
     (tmp == 0) as u8
@@ -10407,7 +11242,8 @@ pub unsafe fn _kortest_mask32_u8(a: __mmask32, b: __mmask32, all_ones: *mut u8)
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _kortest_mask64_u8(a: __mmask64, b: __mmask64, all_ones: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _kortest_mask64_u8(a: __mmask64, b: __mmask64, all_ones: *mut u8) -> u8 {
     let tmp = _kor_mask64(a, b);
     *all_ones = (tmp == 0xffffffff_ffffffff) as u8;
     (tmp == 0) as u8
@@ -10420,7 +11256,8 @@ pub unsafe fn _kortest_mask64_u8(a: __mmask64, b: __mmask64, all_ones: *mut u8)
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
     (_kor_mask32(a, b) == 0xffffffff) as u8
 }
 
@@ -10431,7 +11268,8 @@ pub fn _kortestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
     (_kor_mask64(a, b) == 0xffffffff_ffffffff) as u8
 }
 
@@ -10442,7 +11280,8 @@ pub fn _kortestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
     (_kor_mask32(a, b) == 0) as u8
 }
 
@@ -10453,7 +11292,8 @@ pub fn _kortestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
     (_kor_mask64(a, b) == 0) as u8
 }
 
@@ -10464,7 +11304,8 @@ pub fn _kortestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
 #[target_feature(enable = "avx512bw")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftli_mask32<const COUNT: u32>(a: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftli_mask32<const COUNT: u32>(a: __mmask32) -> __mmask32 {
     a.unbounded_shl(COUNT)
 }
 
@@ -10475,7 +11316,8 @@ pub fn _kshiftli_mask32<const COUNT: u32>(a: __mmask32) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftli_mask64<const COUNT: u32>(a: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftli_mask64<const COUNT: u32>(a: __mmask64) -> __mmask64 {
     a.unbounded_shl(COUNT)
 }
 
@@ -10486,7 +11328,8 @@ pub fn _kshiftli_mask64<const COUNT: u32>(a: __mmask64) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftri_mask32<const COUNT: u32>(a: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftri_mask32<const COUNT: u32>(a: __mmask32) -> __mmask32 {
     a.unbounded_shr(COUNT)
 }
 
@@ -10497,7 +11340,8 @@ pub fn _kshiftri_mask32<const COUNT: u32>(a: __mmask32) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftri_mask64<const COUNT: u32>(a: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftri_mask64<const COUNT: u32>(a: __mmask64) -> __mmask64 {
     a.unbounded_shr(COUNT)
 }
 
@@ -10509,7 +11353,8 @@ pub fn _kshiftri_mask64<const COUNT: u32>(a: __mmask64) -> __mmask64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _ktest_mask32_u8(a: __mmask32, b: __mmask32, and_not: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _ktest_mask32_u8(a: __mmask32, b: __mmask32, and_not: *mut u8) -> u8 {
     *and_not = (_kandn_mask32(a, b) == 0) as u8;
     (_kand_mask32(a, b) == 0) as u8
 }
@@ -10522,7 +11367,8 @@ pub unsafe fn _ktest_mask32_u8(a: __mmask32, b: __mmask32, and_not: *mut u8) ->
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _ktest_mask64_u8(a: __mmask64, b: __mmask64, and_not: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _ktest_mask64_u8(a: __mmask64, b: __mmask64, and_not: *mut u8) -> u8 {
     *and_not = (_kandn_mask64(a, b) == 0) as u8;
     (_kand_mask64(a, b) == 0) as u8
 }
@@ -10534,7 +11380,8 @@ pub unsafe fn _ktest_mask64_u8(a: __mmask64, b: __mmask64, and_not: *mut u8) ->
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
     (_kandn_mask32(a, b) == 0) as u8
 }
 
@@ -10545,7 +11392,8 @@ pub fn _ktestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
     (_kandn_mask64(a, b) == 0) as u8
 }
 
@@ -10556,7 +11404,8 @@ pub fn _ktestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
     (_kand_mask32(a, b) == 0) as u8
 }
 
@@ -10567,7 +11416,8 @@ pub fn _ktestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
     (_kand_mask64(a, b) == 0) as u8
 }
 
@@ -10578,7 +11428,8 @@ pub fn _ktestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kunpckwd
-pub fn _mm512_kunpackw(a: __mmask32, b: __mmask32) -> __mmask32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kunpackw(a: __mmask32, b: __mmask32) -> __mmask32 {
     ((a & 0xffff) << 16) | (b & 0xffff)
 }
 
@@ -10589,7 +11440,8 @@ pub fn _mm512_kunpackw(a: __mmask32, b: __mmask32) -> __mmask32 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kunpckdq
-pub fn _mm512_kunpackd(a: __mmask64, b: __mmask64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_kunpackd(a: __mmask64, b: __mmask64) -> __mmask64 {
     ((a & 0xffffffff) << 32) | (b & 0xffffffff)
 }
 
@@ -10600,7 +11452,8 @@ pub fn _mm512_kunpackd(a: __mmask64, b: __mmask64) -> __mmask64 {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm512_cvtepi16_epi8(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
         let a = a.as_i16x32();
         transmute::<i8x32, _>(simd_cast(a))
@@ -10614,7 +11467,8 @@ pub fn _mm512_cvtepi16_epi8(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm512_mask_cvtepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
     unsafe {
         let convert = _mm512_cvtepi16_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, convert, src.as_i8x32()))
@@ -10628,7 +11482,8 @@ pub fn _mm512_mask_cvtepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m2
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm512_maskz_cvtepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
     unsafe {
         let convert = _mm512_cvtepi16_epi8(a).as_i8x32();
         transmute(simd_select_bitmask(k, convert, i8x32::ZERO))
@@ -10642,7 +11497,8 @@ pub fn _mm512_maskz_cvtepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm256_cvtepi16_epi8(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtepi16_epi8(a: __m256i) -> __m128i {
     unsafe {
         let a = a.as_i16x16();
         transmute::<i8x16, _>(simd_cast(a))
@@ -10656,7 +11512,8 @@ pub fn _mm256_cvtepi16_epi8(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm256_mask_cvtepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
     unsafe {
         let convert = _mm256_cvtepi16_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, convert, src.as_i8x16()))
@@ -10670,7 +11527,8 @@ pub fn _mm256_mask_cvtepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m1
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm256_maskz_cvtepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
     unsafe {
         let convert = _mm256_cvtepi16_epi8(a).as_i8x16();
         transmute(simd_select_bitmask(k, convert, i8x16::ZERO))
@@ -10684,7 +11542,8 @@ pub fn _mm256_maskz_cvtepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i16x8();
         let v256: i16x16 = simd_shuffle!(
@@ -10703,7 +11562,8 @@ pub fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let a = _mm_cvtepi16_epi8(a).as_i8x16();
         let src = simd_shuffle!(
@@ -10722,7 +11582,8 @@ pub fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
     _mm_mask_cvtepi16_epi8(_mm_setzero_si128(), k, a)
 }
 
@@ -10733,7 +11594,8 @@ pub fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-pub fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
         simd_cast::<_, i8x32>(simd_imax(
             simd_imin(a.as_i16x32(), i16x32::splat(i8::MAX as _)),
@@ -10750,7 +11612,8 @@ pub fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-pub fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
     unsafe {
         simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), src.as_i8x32()).as_m256i()
     }
@@ -10763,7 +11626,8 @@ pub fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-pub fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
     unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), i8x32::ZERO).as_m256i() }
 }
 
@@ -10774,7 +11638,8 @@ pub fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-pub fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
     unsafe {
         simd_cast::<_, i8x16>(simd_imax(
             simd_imin(a.as_i16x16(), i16x16::splat(i8::MAX as _)),
@@ -10791,7 +11656,8 @@ pub fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-pub fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
     unsafe {
         simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), src.as_i8x16()).as_m128i()
     }
@@ -10804,7 +11670,8 @@ pub fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-pub fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
     unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), i8x16::ZERO).as_m128i() }
 }
 
@@ -10848,7 +11715,8 @@ pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-pub fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
         simd_cast::<_, u8x32>(simd_imin(a.as_u16x32(), u16x32::splat(u8::MAX as _))).as_m256i()
     }
@@ -10861,7 +11729,8 @@ pub fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-pub fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
     unsafe {
         simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), src.as_u8x32()).as_m256i()
     }
@@ -10874,7 +11743,8 @@ pub fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-pub fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
     unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), u8x32::ZERO).as_m256i() }
 }
 
@@ -10885,7 +11755,8 @@ pub fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-pub fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
     unsafe {
         simd_cast::<_, u8x16>(simd_imin(a.as_u16x16(), u16x16::splat(u8::MAX as _))).as_m128i()
     }
@@ -10898,7 +11769,8 @@ pub fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-pub fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
     unsafe {
         simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), src.as_u8x16()).as_m128i()
     }
@@ -10911,7 +11783,8 @@ pub fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-pub fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
     unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), u8x16::ZERO).as_m128i() }
 }
 
@@ -10955,7 +11828,8 @@ pub fn _mm_maskz_cvtusepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm512_cvtepi8_epi16(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepi8_epi16(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_i8x32();
         transmute::<i16x32, _>(simd_cast(a))
@@ -10969,7 +11843,8 @@ pub fn _mm512_cvtepi8_epi16(a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm512_mask_cvtepi8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepi8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi8_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, convert, src.as_i16x32()))
@@ -10983,7 +11858,8 @@ pub fn _mm512_mask_cvtepi8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m5
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm512_maskz_cvtepi8_epi16(k: __mmask32, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepi8_epi16(k: __mmask32, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepi8_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, convert, i16x32::ZERO))
@@ -10997,7 +11873,8 @@ pub fn _mm512_maskz_cvtepi8_epi16(k: __mmask32, a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm256_mask_cvtepi8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepi8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi8_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, convert, src.as_i16x16()))
@@ -11011,7 +11888,8 @@ pub fn _mm256_mask_cvtepi8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm256_maskz_cvtepi8_epi16(k: __mmask16, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepi8_epi16(k: __mmask16, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepi8_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, convert, i16x16::ZERO))
@@ -11025,7 +11903,8 @@ pub fn _mm256_maskz_cvtepi8_epi16(k: __mmask16, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm_mask_cvtepi8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepi8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi8_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, src.as_i16x8()))
@@ -11039,7 +11918,8 @@ pub fn _mm_mask_cvtepi8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovsxbw))]
-pub fn _mm_maskz_cvtepi8_epi16(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepi8_epi16(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepi8_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, i16x8::ZERO))
@@ -11053,7 +11933,8 @@ pub fn _mm_maskz_cvtepi8_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm512_cvtepu8_epi16(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtepu8_epi16(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_u8x32();
         transmute::<i16x32, _>(simd_cast(a))
@@ -11067,7 +11948,8 @@ pub fn _mm512_cvtepu8_epi16(a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm512_mask_cvtepu8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_cvtepu8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu8_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, convert, src.as_i16x32()))
@@ -11081,7 +11963,8 @@ pub fn _mm512_mask_cvtepu8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m5
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm512_maskz_cvtepu8_epi16(k: __mmask32, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_cvtepu8_epi16(k: __mmask32, a: __m256i) -> __m512i {
     unsafe {
         let convert = _mm512_cvtepu8_epi16(a).as_i16x32();
         transmute(simd_select_bitmask(k, convert, i16x32::ZERO))
@@ -11095,7 +11978,8 @@ pub fn _mm512_maskz_cvtepu8_epi16(k: __mmask32, a: __m256i) -> __m512i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm256_mask_cvtepu8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_cvtepu8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu8_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, convert, src.as_i16x16()))
@@ -11109,7 +11993,8 @@ pub fn _mm256_mask_cvtepu8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m2
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm256_maskz_cvtepu8_epi16(k: __mmask16, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_cvtepu8_epi16(k: __mmask16, a: __m128i) -> __m256i {
     unsafe {
         let convert = _mm256_cvtepu8_epi16(a).as_i16x16();
         transmute(simd_select_bitmask(k, convert, i16x16::ZERO))
@@ -11123,7 +12008,8 @@ pub fn _mm256_maskz_cvtepu8_epi16(k: __mmask16, a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm_mask_cvtepu8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_cvtepu8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu8_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, src.as_i16x8()))
@@ -11137,7 +12023,8 @@ pub fn _mm_mask_cvtepu8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovzxbw))]
-pub fn _mm_maskz_cvtepu8_epi16(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_cvtepu8_epi16(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let convert = _mm_cvtepu8_epi16(a).as_i16x8();
         transmute(simd_select_bitmask(k, convert, i16x8::ZERO))
@@ -11152,7 +12039,8 @@ pub fn _mm_maskz_cvtepu8_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpslldq, IMM8 = 3))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_bslli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_bslli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         const fn mask(shift: i32, i: u32) -> u32 {
@@ -11247,7 +12135,8 @@ pub fn _mm512_bslli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpsrldq, IMM8 = 3))]
 #[rustc_legacy_const_generics(1)]
-pub fn _mm512_bsrli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_bsrli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         const fn mask(shift: i32, i: u32) -> u32 {
@@ -11344,7 +12233,8 @@ pub fn _mm512_bsrli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     const fn mask(shift: u32, i: u32) -> u32 {
         let shift = shift % 16;
         let mod_i = i % 16;
@@ -11454,7 +12344,8 @@ pub fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_alignr_epi8<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_alignr_epi8<const IMM8: i32>(
     src: __m512i,
     k: __mmask64,
     a: __m512i,
@@ -11475,7 +12366,12 @@ pub fn _mm512_mask_alignr_epi8<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_alignr_epi8<const IMM8: i32>(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_alignr_epi8<const IMM8: i32>(
+    k: __mmask64,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm512_alignr_epi8::<IMM8>(a, b);
@@ -11491,7 +12387,8 @@ pub fn _mm512_maskz_alignr_epi8<const IMM8: i32>(k: __mmask64, a: __m512i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(4)]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
-pub fn _mm256_mask_alignr_epi8<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_alignr_epi8<const IMM8: i32>(
     src: __m256i,
     k: __mmask32,
     a: __m256i,
@@ -11512,7 +12409,12 @@ pub fn _mm256_mask_alignr_epi8<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
-pub fn _mm256_maskz_alignr_epi8<const IMM8: i32>(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_alignr_epi8<const IMM8: i32>(
+    k: __mmask32,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm256_alignr_epi8::<IMM8>(a, b);
@@ -11528,7 +12430,8 @@ pub fn _mm256_maskz_alignr_epi8<const IMM8: i32>(k: __mmask32, a: __m256i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(4)]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
-pub fn _mm_mask_alignr_epi8<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_alignr_epi8<const IMM8: i32>(
     src: __m128i,
     k: __mmask16,
     a: __m128i,
@@ -11549,7 +12452,12 @@ pub fn _mm_mask_alignr_epi8<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[rustc_legacy_const_generics(3)]
 #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
-pub fn _mm_maskz_alignr_epi8<const IMM8: i32>(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_alignr_epi8<const IMM8: i32>(
+    k: __mmask16,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let r = _mm_alignr_epi8::<IMM8>(a, b);
@@ -11597,7 +12505,8 @@ pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a:
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
     let result = _mm512_cvtepi16_epi8(a).as_i8x32();
     let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, result);
@@ -11610,7 +12519,8 @@ pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32,
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
     let result = _mm256_cvtepi16_epi8(a).as_i8x16();
     let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO);
     simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, result);
@@ -11623,7 +12533,8 @@ pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16,
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-pub unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub const unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
     let result: i8x8 = simd_shuffle!(
         _mm_cvtepi16_epi8(a).as_i8x16(),
         i8x16::ZERO,
@@ -11742,6 +12653,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
@@ -11750,7 +12662,7 @@ mod tests {
     use crate::mem::{self};
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_abs_epi16() {
+    const unsafe fn test_mm512_abs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let r = _mm512_abs_epi16(a);
         let e = _mm512_set1_epi16(1);
@@ -11758,7 +12670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_abs_epi16() {
+    const unsafe fn test_mm512_mask_abs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let r = _mm512_mask_abs_epi16(a, 0, a);
         assert_eq_m512i(r, a);
@@ -11770,7 +12682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_abs_epi16() {
+    const unsafe fn test_mm512_maskz_abs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let r = _mm512_maskz_abs_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -11782,7 +12694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_abs_epi16() {
+    const unsafe fn test_mm256_mask_abs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let r = _mm256_mask_abs_epi16(a, 0, a);
         assert_eq_m256i(r, a);
@@ -11792,7 +12704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_abs_epi16() {
+    const unsafe fn test_mm256_maskz_abs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let r = _mm256_maskz_abs_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -11802,7 +12714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_abs_epi16() {
+    const unsafe fn test_mm_mask_abs_epi16() {
         let a = _mm_set1_epi16(-1);
         let r = _mm_mask_abs_epi16(a, 0, a);
         assert_eq_m128i(r, a);
@@ -11812,7 +12724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_abs_epi16() {
+    const unsafe fn test_mm_maskz_abs_epi16() {
         let a = _mm_set1_epi16(-1);
         let r = _mm_maskz_abs_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -11822,7 +12734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_abs_epi8() {
+    const unsafe fn test_mm512_abs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let r = _mm512_abs_epi8(a);
         let e = _mm512_set1_epi8(1);
@@ -11830,7 +12742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_abs_epi8() {
+    const unsafe fn test_mm512_mask_abs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let r = _mm512_mask_abs_epi8(a, 0, a);
         assert_eq_m512i(r, a);
@@ -11848,7 +12760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_abs_epi8() {
+    const unsafe fn test_mm512_maskz_abs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let r = _mm512_maskz_abs_epi8(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -11865,7 +12777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_abs_epi8() {
+    const unsafe fn test_mm256_mask_abs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let r = _mm256_mask_abs_epi8(a, 0, a);
         assert_eq_m256i(r, a);
@@ -11877,7 +12789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_abs_epi8() {
+    const unsafe fn test_mm256_maskz_abs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let r = _mm256_maskz_abs_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -11889,7 +12801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_abs_epi8() {
+    const unsafe fn test_mm_mask_abs_epi8() {
         let a = _mm_set1_epi8(-1);
         let r = _mm_mask_abs_epi8(a, 0, a);
         assert_eq_m128i(r, a);
@@ -11899,7 +12811,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_abs_epi8() {
+    const unsafe fn test_mm_maskz_abs_epi8() {
         let a = _mm_set1_epi8(-1);
         let r = _mm_maskz_abs_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -11910,7 +12822,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_add_epi16() {
+    const unsafe fn test_mm512_add_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_add_epi16(a, b);
@@ -11919,7 +12831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_add_epi16() {
+    const unsafe fn test_mm512_mask_add_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_mask_add_epi16(a, 0, a, b);
@@ -11932,7 +12844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_add_epi16() {
+    const unsafe fn test_mm512_maskz_add_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_maskz_add_epi16(0, a, b);
@@ -11945,7 +12857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_add_epi16() {
+    const unsafe fn test_mm256_mask_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_mask_add_epi16(a, 0, a, b);
@@ -11956,7 +12868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_add_epi16() {
+    const unsafe fn test_mm256_maskz_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_maskz_add_epi16(0, a, b);
@@ -11967,7 +12879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_add_epi16() {
+    const unsafe fn test_mm_mask_add_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_mask_add_epi16(a, 0, a, b);
@@ -11978,7 +12890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_add_epi16() {
+    const unsafe fn test_mm_maskz_add_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_maskz_add_epi16(0, a, b);
@@ -11989,7 +12901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_add_epi8() {
+    const unsafe fn test_mm512_add_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_add_epi8(a, b);
@@ -11998,7 +12910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_add_epi8() {
+    const unsafe fn test_mm512_mask_add_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_mask_add_epi8(a, 0, a, b);
@@ -12018,7 +12930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_add_epi8() {
+    const unsafe fn test_mm512_maskz_add_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_maskz_add_epi8(0, a, b);
@@ -12037,7 +12949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_add_epi8() {
+    const unsafe fn test_mm256_mask_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_mask_add_epi8(a, 0, a, b);
@@ -12050,7 +12962,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_add_epi8() {
+    const unsafe fn test_mm256_maskz_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_maskz_add_epi8(0, a, b);
@@ -12063,7 +12975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_add_epi8() {
+    const unsafe fn test_mm_mask_add_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_mask_add_epi8(a, 0, a, b);
@@ -12074,7 +12986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_add_epi8() {
+    const unsafe fn test_mm_maskz_add_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_maskz_add_epi8(0, a, b);
@@ -12085,7 +12997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_adds_epu16() {
+    const unsafe fn test_mm512_adds_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_adds_epu16(a, b);
@@ -12094,7 +13006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_adds_epu16() {
+    const unsafe fn test_mm512_mask_adds_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_mask_adds_epu16(a, 0, a, b);
@@ -12107,7 +13019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_adds_epu16() {
+    const unsafe fn test_mm512_maskz_adds_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_maskz_adds_epu16(0, a, b);
@@ -12120,7 +13032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_adds_epu16() {
+    const unsafe fn test_mm256_mask_adds_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_mask_adds_epu16(a, 0, a, b);
@@ -12132,7 +13044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_adds_epu16() {
+    const unsafe fn test_mm256_maskz_adds_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_maskz_adds_epu16(0, a, b);
@@ -12144,7 +13056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_adds_epu16() {
+    const unsafe fn test_mm_mask_adds_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_mask_adds_epu16(a, 0, a, b);
@@ -12156,7 +13068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_adds_epu16() {
+    const unsafe fn test_mm_maskz_adds_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_maskz_adds_epu16(0, a, b);
@@ -12168,7 +13080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_adds_epu8() {
+    const unsafe fn test_mm512_adds_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_adds_epu8(a, b);
@@ -12177,7 +13089,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_adds_epu8() {
+    const unsafe fn test_mm512_mask_adds_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_mask_adds_epu8(a, 0, a, b);
@@ -12197,7 +13109,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_adds_epu8() {
+    const unsafe fn test_mm512_maskz_adds_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_maskz_adds_epu8(0, a, b);
@@ -12216,7 +13128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_adds_epu8() {
+    const unsafe fn test_mm256_mask_adds_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_mask_adds_epu8(a, 0, a, b);
@@ -12229,7 +13141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_adds_epu8() {
+    const unsafe fn test_mm256_maskz_adds_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_maskz_adds_epu8(0, a, b);
@@ -12242,7 +13154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_adds_epu8() {
+    const unsafe fn test_mm_mask_adds_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_mask_adds_epu8(a, 0, a, b);
@@ -12254,7 +13166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_adds_epu8() {
+    const unsafe fn test_mm_maskz_adds_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_maskz_adds_epu8(0, a, b);
@@ -12266,7 +13178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_adds_epi16() {
+    const unsafe fn test_mm512_adds_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_adds_epi16(a, b);
@@ -12275,7 +13187,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_adds_epi16() {
+    const unsafe fn test_mm512_mask_adds_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_mask_adds_epi16(a, 0, a, b);
@@ -12288,7 +13200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_adds_epi16() {
+    const unsafe fn test_mm512_maskz_adds_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_maskz_adds_epi16(0, a, b);
@@ -12301,7 +13213,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_adds_epi16() {
+    const unsafe fn test_mm256_mask_adds_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_mask_adds_epi16(a, 0, a, b);
@@ -12313,7 +13225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_adds_epi16() {
+    const unsafe fn test_mm256_maskz_adds_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_maskz_adds_epi16(0, a, b);
@@ -12325,7 +13237,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_adds_epi16() {
+    const unsafe fn test_mm_mask_adds_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_mask_adds_epi16(a, 0, a, b);
@@ -12336,7 +13248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_adds_epi16() {
+    const unsafe fn test_mm_maskz_adds_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_maskz_adds_epi16(0, a, b);
@@ -12347,7 +13259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_adds_epi8() {
+    const unsafe fn test_mm512_adds_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_adds_epi8(a, b);
@@ -12356,7 +13268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_adds_epi8() {
+    const unsafe fn test_mm512_mask_adds_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_mask_adds_epi8(a, 0, a, b);
@@ -12376,7 +13288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_adds_epi8() {
+    const unsafe fn test_mm512_maskz_adds_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_maskz_adds_epi8(0, a, b);
@@ -12395,7 +13307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_adds_epi8() {
+    const unsafe fn test_mm256_mask_adds_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_mask_adds_epi8(a, 0, a, b);
@@ -12408,7 +13320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_adds_epi8() {
+    const unsafe fn test_mm256_maskz_adds_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_maskz_adds_epi8(0, a, b);
@@ -12421,7 +13333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_adds_epi8() {
+    const unsafe fn test_mm_mask_adds_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_mask_adds_epi8(a, 0, a, b);
@@ -12433,7 +13345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_adds_epi8() {
+    const unsafe fn test_mm_maskz_adds_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_maskz_adds_epi8(0, a, b);
@@ -12445,7 +13357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_sub_epi16() {
+    const unsafe fn test_mm512_sub_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_sub_epi16(a, b);
@@ -12454,7 +13366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_sub_epi16() {
+    const unsafe fn test_mm512_mask_sub_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_mask_sub_epi16(a, 0, a, b);
@@ -12467,7 +13379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_sub_epi16() {
+    const unsafe fn test_mm512_maskz_sub_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_maskz_sub_epi16(0, a, b);
@@ -12480,7 +13392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_sub_epi16() {
+    const unsafe fn test_mm256_mask_sub_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_mask_sub_epi16(a, 0, a, b);
@@ -12491,7 +13403,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_epi16() {
+    const unsafe fn test_mm256_maskz_sub_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_maskz_sub_epi16(0, a, b);
@@ -12502,7 +13414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_sub_epi16() {
+    const unsafe fn test_mm_mask_sub_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_mask_sub_epi16(a, 0, a, b);
@@ -12513,7 +13425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_sub_epi16() {
+    const unsafe fn test_mm_maskz_sub_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_maskz_sub_epi16(0, a, b);
@@ -12524,7 +13436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_sub_epi8() {
+    const unsafe fn test_mm512_sub_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_sub_epi8(a, b);
@@ -12533,7 +13445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_sub_epi8() {
+    const unsafe fn test_mm512_mask_sub_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_mask_sub_epi8(a, 0, a, b);
@@ -12553,7 +13465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_sub_epi8() {
+    const unsafe fn test_mm512_maskz_sub_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_maskz_sub_epi8(0, a, b);
@@ -12572,7 +13484,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_sub_epi8() {
+    const unsafe fn test_mm256_mask_sub_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_mask_sub_epi8(a, 0, a, b);
@@ -12585,7 +13497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_epi8() {
+    const unsafe fn test_mm256_maskz_sub_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_maskz_sub_epi8(0, a, b);
@@ -12598,7 +13510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_sub_epi8() {
+    const unsafe fn test_mm_mask_sub_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_mask_sub_epi8(a, 0, a, b);
@@ -12609,7 +13521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_sub_epi8() {
+    const unsafe fn test_mm_maskz_sub_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_maskz_sub_epi8(0, a, b);
@@ -12620,7 +13532,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_subs_epu16() {
+    const unsafe fn test_mm512_subs_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_subs_epu16(a, b);
@@ -12629,7 +13541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_subs_epu16() {
+    const unsafe fn test_mm512_mask_subs_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_mask_subs_epu16(a, 0, a, b);
@@ -12642,7 +13554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_subs_epu16() {
+    const unsafe fn test_mm512_maskz_subs_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_maskz_subs_epu16(0, a, b);
@@ -12655,7 +13567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_subs_epu16() {
+    const unsafe fn test_mm256_mask_subs_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_mask_subs_epu16(a, 0, a, b);
@@ -12666,7 +13578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_subs_epu16() {
+    const unsafe fn test_mm256_maskz_subs_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_maskz_subs_epu16(0, a, b);
@@ -12677,7 +13589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_subs_epu16() {
+    const unsafe fn test_mm_mask_subs_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_mask_subs_epu16(a, 0, a, b);
@@ -12688,7 +13600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_subs_epu16() {
+    const unsafe fn test_mm_maskz_subs_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_maskz_subs_epu16(0, a, b);
@@ -12699,7 +13611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_subs_epu8() {
+    const unsafe fn test_mm512_subs_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_subs_epu8(a, b);
@@ -12708,7 +13620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_subs_epu8() {
+    const unsafe fn test_mm512_mask_subs_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_mask_subs_epu8(a, 0, a, b);
@@ -12728,7 +13640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_subs_epu8() {
+    const unsafe fn test_mm512_maskz_subs_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_maskz_subs_epu8(0, a, b);
@@ -12747,7 +13659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_subs_epu8() {
+    const unsafe fn test_mm256_mask_subs_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_mask_subs_epu8(a, 0, a, b);
@@ -12760,7 +13672,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_subs_epu8() {
+    const unsafe fn test_mm256_maskz_subs_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_maskz_subs_epu8(0, a, b);
@@ -12773,7 +13685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_subs_epu8() {
+    const unsafe fn test_mm_mask_subs_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_mask_subs_epu8(a, 0, a, b);
@@ -12784,7 +13696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_subs_epu8() {
+    const unsafe fn test_mm_maskz_subs_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_maskz_subs_epu8(0, a, b);
@@ -12795,7 +13707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_subs_epi16() {
+    const unsafe fn test_mm512_subs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_subs_epi16(a, b);
@@ -12804,7 +13716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_subs_epi16() {
+    const unsafe fn test_mm512_mask_subs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_mask_subs_epi16(a, 0, a, b);
@@ -12817,7 +13729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_subs_epi16() {
+    const unsafe fn test_mm512_maskz_subs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_maskz_subs_epi16(0, a, b);
@@ -12830,7 +13742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_subs_epi16() {
+    const unsafe fn test_mm256_mask_subs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_mask_subs_epi16(a, 0, a, b);
@@ -12842,7 +13754,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_subs_epi16() {
+    const unsafe fn test_mm256_maskz_subs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_maskz_subs_epi16(0, a, b);
@@ -12854,7 +13766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_subs_epi16() {
+    const unsafe fn test_mm_mask_subs_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_mask_subs_epi16(a, 0, a, b);
@@ -12865,7 +13777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_subs_epi16() {
+    const unsafe fn test_mm_maskz_subs_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_maskz_subs_epi16(0, a, b);
@@ -12876,7 +13788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_subs_epi8() {
+    const unsafe fn test_mm512_subs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_subs_epi8(a, b);
@@ -12885,7 +13797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_subs_epi8() {
+    const unsafe fn test_mm512_mask_subs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_mask_subs_epi8(a, 0, a, b);
@@ -12905,7 +13817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_subs_epi8() {
+    const unsafe fn test_mm512_maskz_subs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_maskz_subs_epi8(0, a, b);
@@ -12924,7 +13836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_subs_epi8() {
+    const unsafe fn test_mm256_mask_subs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_mask_subs_epi8(a, 0, a, b);
@@ -12937,7 +13849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_subs_epi8() {
+    const unsafe fn test_mm256_maskz_subs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_maskz_subs_epi8(0, a, b);
@@ -12950,7 +13862,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_subs_epi8() {
+    const unsafe fn test_mm_mask_subs_epi8() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_mask_subs_epi8(a, 0, a, b);
@@ -12962,7 +13874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_subs_epi8() {
+    const unsafe fn test_mm_maskz_subs_epi8() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_maskz_subs_epi8(0, a, b);
@@ -12974,7 +13886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mulhi_epu16() {
+    const unsafe fn test_mm512_mulhi_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mulhi_epu16(a, b);
@@ -12983,7 +13895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_mulhi_epu16() {
+    const unsafe fn test_mm512_mask_mulhi_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mulhi_epu16(a, 0, a, b);
@@ -12996,7 +13908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_mulhi_epu16() {
+    const unsafe fn test_mm512_maskz_mulhi_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mulhi_epu16(0, a, b);
@@ -13009,7 +13921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_mulhi_epu16() {
+    const unsafe fn test_mm256_mask_mulhi_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mulhi_epu16(a, 0, a, b);
@@ -13020,7 +13932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_mulhi_epu16() {
+    const unsafe fn test_mm256_maskz_mulhi_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mulhi_epu16(0, a, b);
@@ -13031,7 +13943,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_mulhi_epu16() {
+    const unsafe fn test_mm_mask_mulhi_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mulhi_epu16(a, 0, a, b);
@@ -13042,7 +13954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_mulhi_epu16() {
+    const unsafe fn test_mm_maskz_mulhi_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mulhi_epu16(0, a, b);
@@ -13053,7 +13965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mulhi_epi16() {
+    const unsafe fn test_mm512_mulhi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mulhi_epi16(a, b);
@@ -13062,7 +13974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_mulhi_epi16() {
+    const unsafe fn test_mm512_mask_mulhi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mulhi_epi16(a, 0, a, b);
@@ -13075,7 +13987,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_mulhi_epi16() {
+    const unsafe fn test_mm512_maskz_mulhi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mulhi_epi16(0, a, b);
@@ -13088,7 +14000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_mulhi_epi16() {
+    const unsafe fn test_mm256_mask_mulhi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mulhi_epi16(a, 0, a, b);
@@ -13099,7 +14011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_mulhi_epi16() {
+    const unsafe fn test_mm256_maskz_mulhi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mulhi_epi16(0, a, b);
@@ -13110,7 +14022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_mulhi_epi16() {
+    const unsafe fn test_mm_mask_mulhi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mulhi_epi16(a, 0, a, b);
@@ -13121,7 +14033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_mulhi_epi16() {
+    const unsafe fn test_mm_maskz_mulhi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mulhi_epi16(0, a, b);
@@ -13211,7 +14123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mullo_epi16() {
+    const unsafe fn test_mm512_mullo_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mullo_epi16(a, b);
@@ -13220,7 +14132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_mullo_epi16() {
+    const unsafe fn test_mm512_mask_mullo_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mullo_epi16(a, 0, a, b);
@@ -13233,7 +14145,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_mullo_epi16() {
+    const unsafe fn test_mm512_maskz_mullo_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mullo_epi16(0, a, b);
@@ -13246,7 +14158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_mullo_epi16() {
+    const unsafe fn test_mm256_mask_mullo_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mullo_epi16(a, 0, a, b);
@@ -13257,7 +14169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_mullo_epi16() {
+    const unsafe fn test_mm256_maskz_mullo_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mullo_epi16(0, a, b);
@@ -13268,7 +14180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_mullo_epi16() {
+    const unsafe fn test_mm_mask_mullo_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mullo_epi16(a, 0, a, b);
@@ -13279,7 +14191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_mullo_epi16() {
+    const unsafe fn test_mm_maskz_mullo_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mullo_epi16(0, a, b);
@@ -13290,7 +14202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_max_epu16() {
+    const unsafe fn test_mm512_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13305,7 +14217,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_max_epu16() {
+    const unsafe fn test_mm512_mask_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13322,7 +14234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_max_epu16() {
+    const unsafe fn test_mm512_maskz_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13339,7 +14251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_max_epu16() {
+    const unsafe fn test_mm256_mask_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epu16(a, 0, a, b);
@@ -13350,7 +14262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epu16() {
+    const unsafe fn test_mm256_maskz_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epu16(0, a, b);
@@ -13361,7 +14273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_max_epu16() {
+    const unsafe fn test_mm_mask_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epu16(a, 0, a, b);
@@ -13372,7 +14284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_max_epu16() {
+    const unsafe fn test_mm_maskz_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epu16(0, a, b);
@@ -13383,7 +14295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_max_epu8() {
+    const unsafe fn test_mm512_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13404,7 +14316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_max_epu8() {
+    const unsafe fn test_mm512_mask_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13432,7 +14344,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_max_epu8() {
+    const unsafe fn test_mm512_maskz_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13459,7 +14371,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_max_epu8() {
+    const unsafe fn test_mm256_mask_max_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13476,7 +14388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epu8() {
+    const unsafe fn test_mm256_maskz_max_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13493,7 +14405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_max_epu8() {
+    const unsafe fn test_mm_mask_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epu8(a, 0, a, b);
@@ -13504,7 +14416,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_max_epu8() {
+    const unsafe fn test_mm_maskz_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epu8(0, a, b);
@@ -13515,7 +14427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_max_epi16() {
+    const unsafe fn test_mm512_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13530,7 +14442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_max_epi16() {
+    const unsafe fn test_mm512_mask_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13547,7 +14459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_max_epi16() {
+    const unsafe fn test_mm512_maskz_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13564,7 +14476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_max_epi16() {
+    const unsafe fn test_mm256_mask_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epi16(a, 0, a, b);
@@ -13575,7 +14487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epi16() {
+    const unsafe fn test_mm256_maskz_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epi16(0, a, b);
@@ -13586,7 +14498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_max_epi16() {
+    const unsafe fn test_mm_mask_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epi16(a, 0, a, b);
@@ -13597,7 +14509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_max_epi16() {
+    const unsafe fn test_mm_maskz_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epi16(0, a, b);
@@ -13608,7 +14520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_max_epi8() {
+    const unsafe fn test_mm512_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13629,7 +14541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_max_epi8() {
+    const unsafe fn test_mm512_mask_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13657,7 +14569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_max_epi8() {
+    const unsafe fn test_mm512_maskz_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13684,7 +14596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_max_epi8() {
+    const unsafe fn test_mm256_mask_max_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13701,7 +14613,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_max_epi8() {
+    const unsafe fn test_mm256_maskz_max_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13718,7 +14630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_max_epi8() {
+    const unsafe fn test_mm_mask_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epi8(a, 0, a, b);
@@ -13729,7 +14641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_max_epi8() {
+    const unsafe fn test_mm_maskz_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epi8(0, a, b);
@@ -13740,7 +14652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_min_epu16() {
+    const unsafe fn test_mm512_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13755,7 +14667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_min_epu16() {
+    const unsafe fn test_mm512_mask_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13772,7 +14684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_min_epu16() {
+    const unsafe fn test_mm512_maskz_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13789,7 +14701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_min_epu16() {
+    const unsafe fn test_mm256_mask_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epu16(a, 0, a, b);
@@ -13800,7 +14712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epu16() {
+    const unsafe fn test_mm256_maskz_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epu16(0, a, b);
@@ -13811,7 +14723,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_min_epu16() {
+    const unsafe fn test_mm_mask_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epu16(a, 0, a, b);
@@ -13822,7 +14734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_min_epu16() {
+    const unsafe fn test_mm_maskz_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epu16(0, a, b);
@@ -13833,7 +14745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_min_epu8() {
+    const unsafe fn test_mm512_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13854,7 +14766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_min_epu8() {
+    const unsafe fn test_mm512_mask_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13882,7 +14794,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_min_epu8() {
+    const unsafe fn test_mm512_maskz_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -13909,7 +14821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_min_epu8() {
+    const unsafe fn test_mm256_mask_min_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13926,7 +14838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epu8() {
+    const unsafe fn test_mm256_maskz_min_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13943,7 +14855,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_min_epu8() {
+    const unsafe fn test_mm_mask_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epu8(a, 0, a, b);
@@ -13954,7 +14866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_min_epu8() {
+    const unsafe fn test_mm_maskz_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epu8(0, a, b);
@@ -13965,7 +14877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_min_epi16() {
+    const unsafe fn test_mm512_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13980,7 +14892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_min_epi16() {
+    const unsafe fn test_mm512_mask_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -13997,7 +14909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_min_epi16() {
+    const unsafe fn test_mm512_maskz_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14014,7 +14926,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_min_epi16() {
+    const unsafe fn test_mm256_mask_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epi16(a, 0, a, b);
@@ -14025,7 +14937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epi16() {
+    const unsafe fn test_mm256_maskz_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epi16(0, a, b);
@@ -14036,7 +14948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_min_epi16() {
+    const unsafe fn test_mm_mask_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epi16(a, 0, a, b);
@@ -14047,7 +14959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_min_epi16() {
+    const unsafe fn test_mm_maskz_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epi16(0, a, b);
@@ -14058,7 +14970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_min_epi8() {
+    const unsafe fn test_mm512_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14079,7 +14991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_min_epi8() {
+    const unsafe fn test_mm512_mask_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14107,7 +15019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_min_epi8() {
+    const unsafe fn test_mm512_maskz_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14134,7 +15046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_min_epi8() {
+    const unsafe fn test_mm256_mask_min_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14151,7 +15063,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_min_epi8() {
+    const unsafe fn test_mm256_maskz_min_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14168,7 +15080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_min_epi8() {
+    const unsafe fn test_mm_mask_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epi8(a, 0, a, b);
@@ -14179,7 +15091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_min_epi8() {
+    const unsafe fn test_mm_maskz_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epi8(0, a, b);
@@ -14190,7 +15102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmplt_epu16_mask() {
+    const unsafe fn test_mm512_cmplt_epu16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmplt_epu16_mask(a, b);
@@ -14198,7 +15110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmplt_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epu16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14207,7 +15119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmplt_epu16_mask() {
+    const unsafe fn test_mm256_cmplt_epu16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmplt_epu16_mask(a, b);
@@ -14215,7 +15127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epu16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -14224,7 +15136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmplt_epu16_mask() {
+    const unsafe fn test_mm_cmplt_epu16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmplt_epu16_mask(a, b);
@@ -14232,7 +15144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epu16_mask() {
+    const unsafe fn test_mm_mask_cmplt_epu16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -14241,7 +15153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmplt_epu8_mask() {
+    const unsafe fn test_mm512_cmplt_epu8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmplt_epu8_mask(a, b);
@@ -14252,7 +15164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmplt_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epu8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14264,7 +15176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmplt_epu8_mask() {
+    const unsafe fn test_mm256_cmplt_epu8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmplt_epu8_mask(a, b);
@@ -14272,7 +15184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epu8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14281,7 +15193,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmplt_epu8_mask() {
+    const unsafe fn test_mm_cmplt_epu8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmplt_epu8_mask(a, b);
@@ -14289,7 +15201,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epu8_mask() {
+    const unsafe fn test_mm_mask_cmplt_epu8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -14298,7 +15210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmplt_epi16_mask() {
+    const unsafe fn test_mm512_cmplt_epi16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmplt_epi16_mask(a, b);
@@ -14306,7 +15218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmplt_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epi16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14315,7 +15227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmplt_epi16_mask() {
+    const unsafe fn test_mm256_cmplt_epi16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmplt_epi16_mask(a, b);
@@ -14323,7 +15235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epi16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -14332,7 +15244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmplt_epi16_mask() {
+    const unsafe fn test_mm_cmplt_epi16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmplt_epi16_mask(a, b);
@@ -14340,7 +15252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epi16_mask() {
+    const unsafe fn test_mm_mask_cmplt_epi16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -14349,7 +15261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmplt_epi8_mask() {
+    const unsafe fn test_mm512_cmplt_epi8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmplt_epi8_mask(a, b);
@@ -14360,7 +15272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmplt_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmplt_epi8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14372,7 +15284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmplt_epi8_mask() {
+    const unsafe fn test_mm256_cmplt_epi8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmplt_epi8_mask(a, b);
@@ -14380,7 +15292,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmplt_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmplt_epi8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14389,7 +15301,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmplt_epi8_mask() {
+    const unsafe fn test_mm_cmplt_epi8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmplt_epi8_mask(a, b);
@@ -14397,7 +15309,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmplt_epi8_mask() {
+    const unsafe fn test_mm_mask_cmplt_epi8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -14406,7 +15318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpgt_epu16_mask() {
+    const unsafe fn test_mm512_cmpgt_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpgt_epu16_mask(a, b);
@@ -14414,7 +15326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpgt_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14423,7 +15335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epu16_mask() {
+    const unsafe fn test_mm256_cmpgt_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpgt_epu16_mask(a, b);
@@ -14431,7 +15343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -14440,7 +15352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpgt_epu16_mask() {
+    const unsafe fn test_mm_cmpgt_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpgt_epu16_mask(a, b);
@@ -14448,7 +15360,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epu16_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -14457,7 +15369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpgt_epu8_mask() {
+    const unsafe fn test_mm512_cmpgt_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpgt_epu8_mask(a, b);
@@ -14468,7 +15380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpgt_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14480,7 +15392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epu8_mask() {
+    const unsafe fn test_mm256_cmpgt_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpgt_epu8_mask(a, b);
@@ -14488,7 +15400,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14497,7 +15409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpgt_epu8_mask() {
+    const unsafe fn test_mm_cmpgt_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpgt_epu8_mask(a, b);
@@ -14505,7 +15417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epu8_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -14514,7 +15426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpgt_epi16_mask() {
+    const unsafe fn test_mm512_cmpgt_epi16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpgt_epi16_mask(a, b);
@@ -14522,7 +15434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpgt_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epi16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14531,7 +15443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epi16_mask() {
+    const unsafe fn test_mm256_cmpgt_epi16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpgt_epi16_mask(a, b);
@@ -14539,7 +15451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epi16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b001010101_01010101;
@@ -14548,7 +15460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpgt_epi16_mask() {
+    const unsafe fn test_mm_cmpgt_epi16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpgt_epi16_mask(a, b);
@@ -14556,7 +15468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epi16_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epi16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -14565,7 +15477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpgt_epi8_mask() {
+    const unsafe fn test_mm512_cmpgt_epi8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpgt_epi8_mask(a, b);
@@ -14576,7 +15488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpgt_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmpgt_epi8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14588,7 +15500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpgt_epi8_mask() {
+    const unsafe fn test_mm256_cmpgt_epi8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpgt_epi8_mask(a, b);
@@ -14596,7 +15508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpgt_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmpgt_epi8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14605,7 +15517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpgt_epi8_mask() {
+    const unsafe fn test_mm_cmpgt_epi8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpgt_epi8_mask(a, b);
@@ -14613,7 +15525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpgt_epi8_mask() {
+    const unsafe fn test_mm_mask_cmpgt_epi8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -14622,7 +15534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmple_epu16_mask() {
+    const unsafe fn test_mm512_cmple_epu16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmple_epu16_mask(a, b);
@@ -14630,7 +15542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmple_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmple_epu16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14639,7 +15551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmple_epu16_mask() {
+    const unsafe fn test_mm256_cmple_epu16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmple_epu16_mask(a, b);
@@ -14647,7 +15559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmple_epu16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -14656,7 +15568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmple_epu16_mask() {
+    const unsafe fn test_mm_cmple_epu16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmple_epu16_mask(a, b);
@@ -14664,7 +15576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epu16_mask() {
+    const unsafe fn test_mm_mask_cmple_epu16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -14673,7 +15585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmple_epu8_mask() {
+    const unsafe fn test_mm512_cmple_epu8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmple_epu8_mask(a, b);
@@ -14684,7 +15596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmple_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmple_epu8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14696,7 +15608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmple_epu8_mask() {
+    const unsafe fn test_mm256_cmple_epu8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmple_epu8_mask(a, b);
@@ -14704,7 +15616,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmple_epu8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14713,7 +15625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmple_epu8_mask() {
+    const unsafe fn test_mm_cmple_epu8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmple_epu8_mask(a, b);
@@ -14721,7 +15633,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epu8_mask() {
+    const unsafe fn test_mm_mask_cmple_epu8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -14730,7 +15642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmple_epi16_mask() {
+    const unsafe fn test_mm512_cmple_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmple_epi16_mask(a, b);
@@ -14738,7 +15650,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmple_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmple_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14747,7 +15659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmple_epi16_mask() {
+    const unsafe fn test_mm256_cmple_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmple_epi16_mask(a, b);
@@ -14755,7 +15667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmple_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -14764,7 +15676,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmple_epi16_mask() {
+    const unsafe fn test_mm_cmple_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmple_epi16_mask(a, b);
@@ -14772,7 +15684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epi16_mask() {
+    const unsafe fn test_mm_mask_cmple_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -14781,7 +15693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmple_epi8_mask() {
+    const unsafe fn test_mm512_cmple_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmple_epi8_mask(a, b);
@@ -14792,7 +15704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmple_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmple_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14804,7 +15716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmple_epi8_mask() {
+    const unsafe fn test_mm256_cmple_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmple_epi8_mask(a, b);
@@ -14812,7 +15724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmple_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmple_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14821,7 +15733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmple_epi8_mask() {
+    const unsafe fn test_mm_cmple_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmple_epi8_mask(a, b);
@@ -14829,7 +15741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmple_epi8_mask() {
+    const unsafe fn test_mm_mask_cmple_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -14838,7 +15750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpge_epu16_mask() {
+    const unsafe fn test_mm512_cmpge_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpge_epu16_mask(a, b);
@@ -14846,7 +15758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpge_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14855,7 +15767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpge_epu16_mask() {
+    const unsafe fn test_mm256_cmpge_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpge_epu16_mask(a, b);
@@ -14863,7 +15775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -14872,7 +15784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpge_epu16_mask() {
+    const unsafe fn test_mm_cmpge_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpge_epu16_mask(a, b);
@@ -14880,7 +15792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epu16_mask() {
+    const unsafe fn test_mm_mask_cmpge_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -14889,7 +15801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpge_epu8_mask() {
+    const unsafe fn test_mm512_cmpge_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpge_epu8_mask(a, b);
@@ -14900,7 +15812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpge_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -14912,7 +15824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpge_epu8_mask() {
+    const unsafe fn test_mm256_cmpge_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpge_epu8_mask(a, b);
@@ -14920,7 +15832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14929,7 +15841,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpge_epu8_mask() {
+    const unsafe fn test_mm_cmpge_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpge_epu8_mask(a, b);
@@ -14937,7 +15849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epu8_mask() {
+    const unsafe fn test_mm_mask_cmpge_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -14946,7 +15858,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpge_epi16_mask() {
+    const unsafe fn test_mm512_cmpge_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpge_epi16_mask(a, b);
@@ -14954,7 +15866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpge_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -14963,7 +15875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpge_epi16_mask() {
+    const unsafe fn test_mm256_cmpge_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpge_epi16_mask(a, b);
@@ -14971,7 +15883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -14980,7 +15892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpge_epi16_mask() {
+    const unsafe fn test_mm_cmpge_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpge_epi16_mask(a, b);
@@ -14988,7 +15900,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epi16_mask() {
+    const unsafe fn test_mm_mask_cmpge_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -14997,7 +15909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpge_epi8_mask() {
+    const unsafe fn test_mm512_cmpge_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpge_epi8_mask(a, b);
@@ -15008,7 +15920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpge_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmpge_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15020,7 +15932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpge_epi8_mask() {
+    const unsafe fn test_mm256_cmpge_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpge_epi8_mask(a, b);
@@ -15028,7 +15940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpge_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmpge_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15037,7 +15949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpge_epi8_mask() {
+    const unsafe fn test_mm_cmpge_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpge_epi8_mask(a, b);
@@ -15045,7 +15957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpge_epi8_mask() {
+    const unsafe fn test_mm_mask_cmpge_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15054,7 +15966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpeq_epu16_mask() {
+    const unsafe fn test_mm512_cmpeq_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpeq_epu16_mask(a, b);
@@ -15062,7 +15974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpeq_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15071,7 +15983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epu16_mask() {
+    const unsafe fn test_mm256_cmpeq_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpeq_epu16_mask(a, b);
@@ -15079,7 +15991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -15088,7 +16000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpeq_epu16_mask() {
+    const unsafe fn test_mm_cmpeq_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpeq_epu16_mask(a, b);
@@ -15096,7 +16008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epu16_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -15105,7 +16017,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpeq_epu8_mask() {
+    const unsafe fn test_mm512_cmpeq_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpeq_epu8_mask(a, b);
@@ -15116,7 +16028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpeq_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15128,7 +16040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epu8_mask() {
+    const unsafe fn test_mm256_cmpeq_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpeq_epu8_mask(a, b);
@@ -15136,7 +16048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15145,7 +16057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpeq_epu8_mask() {
+    const unsafe fn test_mm_cmpeq_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpeq_epu8_mask(a, b);
@@ -15153,7 +16065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epu8_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -15162,7 +16074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpeq_epi16_mask() {
+    const unsafe fn test_mm512_cmpeq_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpeq_epi16_mask(a, b);
@@ -15170,7 +16082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpeq_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15179,7 +16091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epi16_mask() {
+    const unsafe fn test_mm256_cmpeq_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpeq_epi16_mask(a, b);
@@ -15187,7 +16099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15196,7 +16108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpeq_epi16_mask() {
+    const unsafe fn test_mm_cmpeq_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpeq_epi16_mask(a, b);
@@ -15204,7 +16116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epi16_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15213,7 +16125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpeq_epi8_mask() {
+    const unsafe fn test_mm512_cmpeq_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpeq_epi8_mask(a, b);
@@ -15224,7 +16136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpeq_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmpeq_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15236,7 +16148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpeq_epi8_mask() {
+    const unsafe fn test_mm256_cmpeq_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpeq_epi8_mask(a, b);
@@ -15244,7 +16156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpeq_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmpeq_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15253,7 +16165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpeq_epi8_mask() {
+    const unsafe fn test_mm_cmpeq_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpeq_epi8_mask(a, b);
@@ -15261,7 +16173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpeq_epi8_mask() {
+    const unsafe fn test_mm_mask_cmpeq_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15270,7 +16182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpneq_epu16_mask() {
+    const unsafe fn test_mm512_cmpneq_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpneq_epu16_mask(a, b);
@@ -15278,7 +16190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpneq_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15287,7 +16199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epu16_mask() {
+    const unsafe fn test_mm256_cmpneq_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpneq_epu16_mask(a, b);
@@ -15295,7 +16207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -15304,7 +16216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpneq_epu16_mask() {
+    const unsafe fn test_mm_cmpneq_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpneq_epu16_mask(a, b);
@@ -15312,7 +16224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epu16_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -15321,7 +16233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpneq_epu8_mask() {
+    const unsafe fn test_mm512_cmpneq_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpneq_epu8_mask(a, b);
@@ -15332,7 +16244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpneq_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15344,7 +16256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epu8_mask() {
+    const unsafe fn test_mm256_cmpneq_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpneq_epu8_mask(a, b);
@@ -15352,7 +16264,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15361,7 +16273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpneq_epu8_mask() {
+    const unsafe fn test_mm_cmpneq_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpneq_epu8_mask(a, b);
@@ -15369,7 +16281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epu8_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -15378,7 +16290,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpneq_epi16_mask() {
+    const unsafe fn test_mm512_cmpneq_epi16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpneq_epi16_mask(a, b);
@@ -15386,7 +16298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpneq_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epi16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15395,7 +16307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epi16_mask() {
+    const unsafe fn test_mm256_cmpneq_epi16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpneq_epi16_mask(a, b);
@@ -15403,7 +16315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epi16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15412,7 +16324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpneq_epi16_mask() {
+    const unsafe fn test_mm_cmpneq_epi16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpneq_epi16_mask(a, b);
@@ -15420,7 +16332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epi16_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epi16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15429,7 +16341,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmpneq_epi8_mask() {
+    const unsafe fn test_mm512_cmpneq_epi8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpneq_epi8_mask(a, b);
@@ -15440,7 +16352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmpneq_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmpneq_epi8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15452,7 +16364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmpneq_epi8_mask() {
+    const unsafe fn test_mm256_cmpneq_epi8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpneq_epi8_mask(a, b);
@@ -15460,7 +16372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmpneq_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmpneq_epi8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15469,7 +16381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmpneq_epi8_mask() {
+    const unsafe fn test_mm_cmpneq_epi8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpneq_epi8_mask(a, b);
@@ -15477,7 +16389,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmpneq_epi8_mask() {
+    const unsafe fn test_mm_mask_cmpneq_epi8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15486,7 +16398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmp_epu16_mask() {
+    const unsafe fn test_mm512_cmp_epu16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
@@ -15494,7 +16406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmp_epu16_mask() {
+    const unsafe fn test_mm512_mask_cmp_epu16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15503,7 +16415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmp_epu16_mask() {
+    const unsafe fn test_mm256_cmp_epu16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
@@ -15511,7 +16423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epu16_mask() {
+    const unsafe fn test_mm256_mask_cmp_epu16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -15520,7 +16432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmp_epu16_mask() {
+    const unsafe fn test_mm_cmp_epu16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
@@ -15528,7 +16440,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epu16_mask() {
+    const unsafe fn test_mm_mask_cmp_epu16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -15537,7 +16449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmp_epu8_mask() {
+    const unsafe fn test_mm512_cmp_epu8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
@@ -15548,7 +16460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmp_epu8_mask() {
+    const unsafe fn test_mm512_mask_cmp_epu8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15560,7 +16472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmp_epu8_mask() {
+    const unsafe fn test_mm256_cmp_epu8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
@@ -15568,7 +16480,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epu8_mask() {
+    const unsafe fn test_mm256_mask_cmp_epu8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15577,7 +16489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmp_epu8_mask() {
+    const unsafe fn test_mm_cmp_epu8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
@@ -15585,7 +16497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epu8_mask() {
+    const unsafe fn test_mm_mask_cmp_epu8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -15594,7 +16506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmp_epi16_mask() {
+    const unsafe fn test_mm512_cmp_epi16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
@@ -15602,7 +16514,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmp_epi16_mask() {
+    const unsafe fn test_mm512_mask_cmp_epi16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15611,7 +16523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmp_epi16_mask() {
+    const unsafe fn test_mm256_cmp_epi16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
@@ -15619,7 +16531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epi16_mask() {
+    const unsafe fn test_mm256_mask_cmp_epi16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -15628,7 +16540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmp_epi16_mask() {
+    const unsafe fn test_mm_cmp_epi16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
@@ -15636,7 +16548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epi16_mask() {
+    const unsafe fn test_mm_mask_cmp_epi16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -15645,7 +16557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cmp_epi8_mask() {
+    const unsafe fn test_mm512_cmp_epi8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
@@ -15656,7 +16568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cmp_epi8_mask() {
+    const unsafe fn test_mm512_mask_cmp_epi8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15668,7 +16580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cmp_epi8_mask() {
+    const unsafe fn test_mm256_cmp_epi8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
@@ -15676,7 +16588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_epi8_mask() {
+    const unsafe fn test_mm256_mask_cmp_epi8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15685,7 +16597,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cmp_epi8_mask() {
+    const unsafe fn test_mm_cmp_epi8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
@@ -15693,7 +16605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cmp_epi8_mask() {
+    const unsafe fn test_mm_mask_cmp_epi8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -15702,91 +16614,91 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_add_epi16() {
+    const unsafe fn test_mm256_reduce_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let e = _mm256_reduce_add_epi16(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_add_epi16() {
+    const unsafe fn test_mm256_mask_reduce_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let e = _mm256_mask_reduce_add_epi16(0b11111111_00000000, a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_add_epi16() {
+    const unsafe fn test_mm_reduce_add_epi16() {
         let a = _mm_set1_epi16(1);
         let e = _mm_reduce_add_epi16(a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_add_epi16() {
+    const unsafe fn test_mm_mask_reduce_add_epi16() {
         let a = _mm_set1_epi16(1);
         let e = _mm_mask_reduce_add_epi16(0b11110000, a);
         assert_eq!(4, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_add_epi8() {
+    const unsafe fn test_mm256_reduce_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let e = _mm256_reduce_add_epi8(a);
         assert_eq!(32, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_add_epi8() {
+    const unsafe fn test_mm256_mask_reduce_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let e = _mm256_mask_reduce_add_epi8(0b11111111_00000000_11111111_00000000, a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_add_epi8() {
+    const unsafe fn test_mm_reduce_add_epi8() {
         let a = _mm_set1_epi8(1);
         let e = _mm_reduce_add_epi8(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_add_epi8() {
+    const unsafe fn test_mm_mask_reduce_add_epi8() {
         let a = _mm_set1_epi8(1);
         let e = _mm_mask_reduce_add_epi8(0b11111111_00000000, a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_and_epi16() {
+    const unsafe fn test_mm256_reduce_and_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_reduce_and_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_and_epi16() {
+    const unsafe fn test_mm256_mask_reduce_and_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_mask_reduce_and_epi16(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_and_epi16() {
+    const unsafe fn test_mm_reduce_and_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_reduce_and_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_and_epi16() {
+    const unsafe fn test_mm_mask_reduce_and_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_mask_reduce_and_epi16(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_and_epi8() {
+    const unsafe fn test_mm256_reduce_and_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -15796,7 +16708,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_and_epi8() {
+    const unsafe fn test_mm256_mask_reduce_and_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -15806,49 +16718,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_and_epi8() {
+    const unsafe fn test_mm_reduce_and_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_reduce_and_epi8(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_and_epi8() {
+    const unsafe fn test_mm_mask_reduce_and_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_mask_reduce_and_epi8(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_mul_epi16() {
+    const unsafe fn test_mm256_reduce_mul_epi16() {
         let a = _mm256_set_epi16(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
         let e = _mm256_reduce_mul_epi16(a);
         assert_eq!(256, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_mul_epi16() {
+    const unsafe fn test_mm256_mask_reduce_mul_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_mask_reduce_mul_epi16(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_mul_epi16() {
+    const unsafe fn test_mm_reduce_mul_epi16() {
         let a = _mm_set_epi16(2, 2, 2, 2, 1, 1, 1, 1);
         let e = _mm_reduce_mul_epi16(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_mul_epi16() {
+    const unsafe fn test_mm_mask_reduce_mul_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_mask_reduce_mul_epi16(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_mul_epi8() {
+    const unsafe fn test_mm256_reduce_mul_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
             2, 2, 2,
@@ -15858,7 +16770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_mul_epi8() {
+    const unsafe fn test_mm256_mask_reduce_mul_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
             2, 2, 2,
@@ -15868,49 +16780,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_mul_epi8() {
+    const unsafe fn test_mm_reduce_mul_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2);
         let e = _mm_reduce_mul_epi8(a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_mul_epi8() {
+    const unsafe fn test_mm_mask_reduce_mul_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2);
         let e = _mm_mask_reduce_mul_epi8(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_max_epi16() {
+    const unsafe fn test_mm256_reduce_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_reduce_max_epi16(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_max_epi16() {
+    const unsafe fn test_mm256_mask_reduce_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_mask_reduce_max_epi16(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_max_epi16() {
+    const unsafe fn test_mm_reduce_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_reduce_max_epi16(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_max_epi16() {
+    const unsafe fn test_mm_mask_reduce_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_mask_reduce_max_epi16(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_max_epi8() {
+    const unsafe fn test_mm256_reduce_max_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -15920,7 +16832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_max_epi8() {
+    const unsafe fn test_mm256_mask_reduce_max_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -15930,49 +16842,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_max_epi8() {
+    const unsafe fn test_mm_reduce_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_reduce_max_epi8(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_max_epi8() {
+    const unsafe fn test_mm_mask_reduce_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_mask_reduce_max_epi8(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_max_epu16() {
+    const unsafe fn test_mm256_reduce_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_reduce_max_epu16(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_max_epu16() {
+    const unsafe fn test_mm256_mask_reduce_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_mask_reduce_max_epu16(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_max_epu16() {
+    const unsafe fn test_mm_reduce_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_reduce_max_epu16(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_max_epu16() {
+    const unsafe fn test_mm_mask_reduce_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_mask_reduce_max_epu16(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_max_epu8() {
+    const unsafe fn test_mm256_reduce_max_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -15982,7 +16894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_max_epu8() {
+    const unsafe fn test_mm256_mask_reduce_max_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -15992,49 +16904,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_max_epu8() {
+    const unsafe fn test_mm_reduce_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_reduce_max_epu8(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_max_epu8() {
+    const unsafe fn test_mm_mask_reduce_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_mask_reduce_max_epu8(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_min_epi16() {
+    const unsafe fn test_mm256_reduce_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_reduce_min_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_min_epi16() {
+    const unsafe fn test_mm256_mask_reduce_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_mask_reduce_min_epi16(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_min_epi16() {
+    const unsafe fn test_mm_reduce_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_reduce_min_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_min_epi16() {
+    const unsafe fn test_mm_mask_reduce_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_mask_reduce_min_epi16(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_min_epi8() {
+    const unsafe fn test_mm256_reduce_min_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16044,7 +16956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_min_epi8() {
+    const unsafe fn test_mm256_mask_reduce_min_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16054,49 +16966,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_min_epi8() {
+    const unsafe fn test_mm_reduce_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_reduce_min_epi8(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_min_epi8() {
+    const unsafe fn test_mm_mask_reduce_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_mask_reduce_min_epi8(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_min_epu16() {
+    const unsafe fn test_mm256_reduce_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_reduce_min_epu16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_min_epu16() {
+    const unsafe fn test_mm256_mask_reduce_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_mask_reduce_min_epu16(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_min_epu16() {
+    const unsafe fn test_mm_reduce_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_reduce_min_epu16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_min_epu16() {
+    const unsafe fn test_mm_mask_reduce_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_mask_reduce_min_epu16(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_min_epu8() {
+    const unsafe fn test_mm256_reduce_min_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16106,7 +17018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_min_epu8() {
+    const unsafe fn test_mm256_mask_reduce_min_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16116,49 +17028,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_min_epu8() {
+    const unsafe fn test_mm_reduce_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_reduce_min_epu8(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_min_epu8() {
+    const unsafe fn test_mm_mask_reduce_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_mask_reduce_min_epu8(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_or_epi16() {
+    const unsafe fn test_mm256_reduce_or_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_reduce_or_epi16(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_or_epi16() {
+    const unsafe fn test_mm256_mask_reduce_or_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_mask_reduce_or_epi16(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_or_epi16() {
+    const unsafe fn test_mm_reduce_or_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_reduce_or_epi16(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_or_epi16() {
+    const unsafe fn test_mm_mask_reduce_or_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_mask_reduce_or_epi16(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_reduce_or_epi8() {
+    const unsafe fn test_mm256_reduce_or_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -16168,7 +17080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_or_epi8() {
+    const unsafe fn test_mm256_mask_reduce_or_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -16178,21 +17090,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_reduce_or_epi8() {
+    const unsafe fn test_mm_reduce_or_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_reduce_or_epi8(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_reduce_or_epi8() {
+    const unsafe fn test_mm_mask_reduce_or_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_mask_reduce_or_epi8(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_loadu_epi16() {
+    const unsafe fn test_mm512_loadu_epi16() {
         #[rustfmt::skip]
         let a: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
         let r = _mm512_loadu_epi16(&a[0]);
@@ -16202,7 +17114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_loadu_epi16() {
+    const unsafe fn test_mm256_loadu_epi16() {
         let a: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let r = _mm256_loadu_epi16(&a[0]);
         let e = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
@@ -16210,7 +17122,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_loadu_epi16() {
+    const unsafe fn test_mm_loadu_epi16() {
         let a: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let r = _mm_loadu_epi16(&a[0]);
         let e = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1);
@@ -16218,7 +17130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_loadu_epi8() {
+    const unsafe fn test_mm512_loadu_epi8() {
         #[rustfmt::skip]
         let a: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
                            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
@@ -16230,7 +17142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_loadu_epi8() {
+    const unsafe fn test_mm256_loadu_epi8() {
         #[rustfmt::skip]
         let a: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
         let r = _mm256_loadu_epi8(&a[0]);
@@ -16240,7 +17152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_loadu_epi8() {
+    const unsafe fn test_mm_loadu_epi8() {
         let a: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let r = _mm_loadu_epi8(&a[0]);
         let e = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
@@ -16248,7 +17160,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_storeu_epi16() {
+    const unsafe fn test_mm512_storeu_epi16() {
         let a = _mm512_set1_epi16(9);
         let mut r = _mm512_undefined_epi32();
         _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a);
@@ -16256,7 +17168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_storeu_epi16() {
+    const unsafe fn test_mm256_storeu_epi16() {
         let a = _mm256_set1_epi16(9);
         let mut r = _mm256_set1_epi32(0);
         _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a);
@@ -16264,7 +17176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_storeu_epi16() {
+    const unsafe fn test_mm_storeu_epi16() {
         let a = _mm_set1_epi16(9);
         let mut r = _mm_set1_epi32(0);
         _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a);
@@ -16272,7 +17184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_storeu_epi8() {
+    const unsafe fn test_mm512_storeu_epi8() {
         let a = _mm512_set1_epi8(9);
         let mut r = _mm512_undefined_epi32();
         _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a);
@@ -16280,7 +17192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_storeu_epi8() {
+    const unsafe fn test_mm256_storeu_epi8() {
         let a = _mm256_set1_epi8(9);
         let mut r = _mm256_set1_epi32(0);
         _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a);
@@ -16288,7 +17200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_storeu_epi8() {
+    const unsafe fn test_mm_storeu_epi8() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi32(0);
         _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a);
@@ -16296,7 +17208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_loadu_epi16() {
+    const unsafe fn test_mm512_mask_loadu_epi16() {
         let src = _mm512_set1_epi16(42);
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16314,7 +17226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_loadu_epi16() {
+    const unsafe fn test_mm512_maskz_loadu_epi16() {
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -16331,7 +17243,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_storeu_epi16() {
+    const unsafe fn test_mm512_mask_storeu_epi16() {
         let mut r = [42_i16; 32];
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16349,7 +17261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_loadu_epi8() {
+    const unsafe fn test_mm512_mask_loadu_epi8() {
         let src = _mm512_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16369,7 +17281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_loadu_epi8() {
+    const unsafe fn test_mm512_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
@@ -16388,7 +17300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_storeu_epi8() {
+    const unsafe fn test_mm512_mask_storeu_epi8() {
         let mut r = [42_i8; 64];
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16408,7 +17320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_loadu_epi16() {
+    const unsafe fn test_mm256_mask_loadu_epi16() {
         let src = _mm256_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
@@ -16422,7 +17334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_loadu_epi16() {
+    const unsafe fn test_mm256_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
@@ -16433,7 +17345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_storeu_epi16() {
+    const unsafe fn test_mm256_mask_storeu_epi16() {
         let mut r = [42_i16; 16];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let a = _mm256_loadu_epi16(a.as_ptr());
@@ -16447,7 +17359,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_loadu_epi8() {
+    const unsafe fn test_mm256_mask_loadu_epi8() {
         let src = _mm256_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16465,7 +17377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_loadu_epi8() {
+    const unsafe fn test_mm256_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -16482,7 +17394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_storeu_epi8() {
+    const unsafe fn test_mm256_mask_storeu_epi8() {
         let mut r = [42_i8; 32];
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -16500,7 +17412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_loadu_epi16() {
+    const unsafe fn test_mm_mask_loadu_epi16() {
         let src = _mm_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
@@ -16512,7 +17424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_loadu_epi16() {
+    const unsafe fn test_mm_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
@@ -16523,7 +17435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_storeu_epi16() {
+    const unsafe fn test_mm_mask_storeu_epi16() {
         let mut r = [42_i16; 8];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let a = _mm_loadu_epi16(a.as_ptr());
@@ -16535,7 +17447,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_loadu_epi8() {
+    const unsafe fn test_mm_mask_loadu_epi8() {
         let src = _mm_set1_epi8(42);
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
@@ -16549,7 +17461,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_loadu_epi8() {
+    const unsafe fn test_mm_maskz_loadu_epi8() {
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
@@ -16560,7 +17472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_storeu_epi8() {
+    const unsafe fn test_mm_mask_storeu_epi8() {
         let mut r = [42_i8; 16];
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let a = _mm_loadu_epi8(a.as_ptr());
@@ -16574,7 +17486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_madd_epi16() {
+    const unsafe fn test_mm512_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_madd_epi16(a, b);
@@ -16583,7 +17495,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_madd_epi16() {
+    const unsafe fn test_mm512_mask_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_madd_epi16(a, 0, a, b);
@@ -16611,7 +17523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_madd_epi16() {
+    const unsafe fn test_mm512_maskz_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_madd_epi16(0, a, b);
@@ -16622,7 +17534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_madd_epi16() {
+    const unsafe fn test_mm256_mask_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_madd_epi16(a, 0, a, b);
@@ -16642,7 +17554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_madd_epi16() {
+    const unsafe fn test_mm256_maskz_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_madd_epi16(0, a, b);
@@ -16653,7 +17565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_madd_epi16() {
+    const unsafe fn test_mm_mask_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_madd_epi16(a, 0, a, b);
@@ -16664,7 +17576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_madd_epi16() {
+    const unsafe fn test_mm_maskz_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_madd_epi16(0, a, b);
@@ -17123,7 +18035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_avg_epu16() {
+    const unsafe fn test_mm512_avg_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_avg_epu16(a, b);
@@ -17132,7 +18044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_avg_epu16() {
+    const unsafe fn test_mm512_mask_avg_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_avg_epu16(a, 0, a, b);
@@ -17145,7 +18057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_avg_epu16() {
+    const unsafe fn test_mm512_maskz_avg_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_avg_epu16(0, a, b);
@@ -17158,7 +18070,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_avg_epu16() {
+    const unsafe fn test_mm256_mask_avg_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_avg_epu16(a, 0, a, b);
@@ -17169,7 +18081,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_avg_epu16() {
+    const unsafe fn test_mm256_maskz_avg_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_avg_epu16(0, a, b);
@@ -17180,7 +18092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_avg_epu16() {
+    const unsafe fn test_mm_mask_avg_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_avg_epu16(a, 0, a, b);
@@ -17191,7 +18103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_avg_epu16() {
+    const unsafe fn test_mm_maskz_avg_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_avg_epu16(0, a, b);
@@ -17202,7 +18114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_avg_epu8() {
+    const unsafe fn test_mm512_avg_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_avg_epu8(a, b);
@@ -17211,7 +18123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_avg_epu8() {
+    const unsafe fn test_mm512_mask_avg_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_mask_avg_epu8(a, 0, a, b);
@@ -17231,7 +18143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_avg_epu8() {
+    const unsafe fn test_mm512_maskz_avg_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_maskz_avg_epu8(0, a, b);
@@ -17250,7 +18162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_avg_epu8() {
+    const unsafe fn test_mm256_mask_avg_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_mask_avg_epu8(a, 0, a, b);
@@ -17263,7 +18175,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_avg_epu8() {
+    const unsafe fn test_mm256_maskz_avg_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_maskz_avg_epu8(0, a, b);
@@ -17276,7 +18188,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_avg_epu8() {
+    const unsafe fn test_mm_mask_avg_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_mask_avg_epu8(a, 0, a, b);
@@ -17287,7 +18199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_avg_epu8() {
+    const unsafe fn test_mm_maskz_avg_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_maskz_avg_epu8(0, a, b);
@@ -17373,7 +18285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_slli_epi16() {
+    const unsafe fn test_mm512_slli_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_slli_epi16::<1>(a);
         let e = _mm512_set1_epi16(0);
@@ -17381,7 +18293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_slli_epi16() {
+    const unsafe fn test_mm512_mask_slli_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_mask_slli_epi16::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -17391,7 +18303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_slli_epi16() {
+    const unsafe fn test_mm512_maskz_slli_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_maskz_slli_epi16::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -17401,7 +18313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_slli_epi16() {
+    const unsafe fn test_mm256_mask_slli_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let r = _mm256_mask_slli_epi16::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -17411,7 +18323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_slli_epi16() {
+    const unsafe fn test_mm256_maskz_slli_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let r = _mm256_maskz_slli_epi16::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -17421,7 +18333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_slli_epi16() {
+    const unsafe fn test_mm_mask_slli_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let r = _mm_mask_slli_epi16::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -17431,7 +18343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_slli_epi16() {
+    const unsafe fn test_mm_maskz_slli_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let r = _mm_maskz_slli_epi16::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -17441,7 +18353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_sllv_epi16() {
+    const unsafe fn test_mm512_sllv_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_sllv_epi16(a, count);
@@ -17450,7 +18362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_sllv_epi16() {
+    const unsafe fn test_mm512_mask_sllv_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_mask_sllv_epi16(a, 0, a, count);
@@ -17461,7 +18373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_sllv_epi16() {
+    const unsafe fn test_mm512_maskz_sllv_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_maskz_sllv_epi16(0, a, count);
@@ -17472,7 +18384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_sllv_epi16() {
+    const unsafe fn test_mm256_sllv_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_sllv_epi16(a, count);
@@ -17481,7 +18393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_sllv_epi16() {
+    const unsafe fn test_mm256_mask_sllv_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_mask_sllv_epi16(a, 0, a, count);
@@ -17492,7 +18404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_sllv_epi16() {
+    const unsafe fn test_mm256_maskz_sllv_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_maskz_sllv_epi16(0, a, count);
@@ -17503,7 +18415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_sllv_epi16() {
+    const unsafe fn test_mm_sllv_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_sllv_epi16(a, count);
@@ -17512,7 +18424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_sllv_epi16() {
+    const unsafe fn test_mm_mask_sllv_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_sllv_epi16(a, 0, a, count);
@@ -17523,7 +18435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_sllv_epi16() {
+    const unsafe fn test_mm_maskz_sllv_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_sllv_epi16(0, a, count);
@@ -17609,7 +18521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_srli_epi16() {
+    const unsafe fn test_mm512_srli_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let r = _mm512_srli_epi16::<2>(a);
         let e = _mm512_set1_epi16(0);
@@ -17617,7 +18529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_srli_epi16() {
+    const unsafe fn test_mm512_mask_srli_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let r = _mm512_mask_srli_epi16::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -17627,7 +18539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_srli_epi16() {
+    const unsafe fn test_mm512_maskz_srli_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let r = _mm512_maskz_srli_epi16::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -17637,7 +18549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_srli_epi16() {
+    const unsafe fn test_mm256_mask_srli_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let r = _mm256_mask_srli_epi16::<2>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -17647,7 +18559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_srli_epi16() {
+    const unsafe fn test_mm256_maskz_srli_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let r = _mm256_maskz_srli_epi16::<2>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -17657,7 +18569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_srli_epi16() {
+    const unsafe fn test_mm_mask_srli_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let r = _mm_mask_srli_epi16::<2>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -17667,7 +18579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_srli_epi16() {
+    const unsafe fn test_mm_maskz_srli_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let r = _mm_maskz_srli_epi16::<2>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -17677,7 +18589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_srlv_epi16() {
+    const unsafe fn test_mm512_srlv_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_srlv_epi16(a, count);
@@ -17686,7 +18598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_srlv_epi16() {
+    const unsafe fn test_mm512_mask_srlv_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_mask_srlv_epi16(a, 0, a, count);
@@ -17697,7 +18609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_srlv_epi16() {
+    const unsafe fn test_mm512_maskz_srlv_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_maskz_srlv_epi16(0, a, count);
@@ -17708,7 +18620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_srlv_epi16() {
+    const unsafe fn test_mm256_srlv_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_srlv_epi16(a, count);
@@ -17717,7 +18629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_srlv_epi16() {
+    const unsafe fn test_mm256_mask_srlv_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_mask_srlv_epi16(a, 0, a, count);
@@ -17728,7 +18640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_srlv_epi16() {
+    const unsafe fn test_mm256_maskz_srlv_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_maskz_srlv_epi16(0, a, count);
@@ -17739,7 +18651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_srlv_epi16() {
+    const unsafe fn test_mm_srlv_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_srlv_epi16(a, count);
@@ -17748,7 +18660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_srlv_epi16() {
+    const unsafe fn test_mm_mask_srlv_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_srlv_epi16(a, 0, a, count);
@@ -17759,7 +18671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_srlv_epi16() {
+    const unsafe fn test_mm_maskz_srlv_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_srlv_epi16(0, a, count);
@@ -17845,7 +18757,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_srai_epi16() {
+    const unsafe fn test_mm512_srai_epi16() {
         let a = _mm512_set1_epi16(8);
         let r = _mm512_srai_epi16::<2>(a);
         let e = _mm512_set1_epi16(2);
@@ -17853,7 +18765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_srai_epi16() {
+    const unsafe fn test_mm512_mask_srai_epi16() {
         let a = _mm512_set1_epi16(8);
         let r = _mm512_mask_srai_epi16::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -17863,7 +18775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_srai_epi16() {
+    const unsafe fn test_mm512_maskz_srai_epi16() {
         let a = _mm512_set1_epi16(8);
         let r = _mm512_maskz_srai_epi16::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -17873,7 +18785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_srai_epi16() {
+    const unsafe fn test_mm256_mask_srai_epi16() {
         let a = _mm256_set1_epi16(8);
         let r = _mm256_mask_srai_epi16::<2>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -17883,7 +18795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_srai_epi16() {
+    const unsafe fn test_mm256_maskz_srai_epi16() {
         let a = _mm256_set1_epi16(8);
         let r = _mm256_maskz_srai_epi16::<2>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -17893,7 +18805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_srai_epi16() {
+    const unsafe fn test_mm_mask_srai_epi16() {
         let a = _mm_set1_epi16(8);
         let r = _mm_mask_srai_epi16::<2>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -17903,7 +18815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_srai_epi16() {
+    const unsafe fn test_mm_maskz_srai_epi16() {
         let a = _mm_set1_epi16(8);
         let r = _mm_maskz_srai_epi16::<2>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -17913,7 +18825,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_srav_epi16() {
+    const unsafe fn test_mm512_srav_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_srav_epi16(a, count);
@@ -17922,7 +18834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_srav_epi16() {
+    const unsafe fn test_mm512_mask_srav_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_mask_srav_epi16(a, 0, a, count);
@@ -17933,7 +18845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_srav_epi16() {
+    const unsafe fn test_mm512_maskz_srav_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_maskz_srav_epi16(0, a, count);
@@ -17944,7 +18856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_srav_epi16() {
+    const unsafe fn test_mm256_srav_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_srav_epi16(a, count);
@@ -17953,7 +18865,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_srav_epi16() {
+    const unsafe fn test_mm256_mask_srav_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_mask_srav_epi16(a, 0, a, count);
@@ -17964,7 +18876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_srav_epi16() {
+    const unsafe fn test_mm256_maskz_srav_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_maskz_srav_epi16(0, a, count);
@@ -17975,7 +18887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_srav_epi16() {
+    const unsafe fn test_mm_srav_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(2);
         let r = _mm_srav_epi16(a, count);
@@ -17984,7 +18896,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_srav_epi16() {
+    const unsafe fn test_mm_mask_srav_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_srav_epi16(a, 0, a, count);
@@ -17995,7 +18907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_srav_epi16() {
+    const unsafe fn test_mm_maskz_srav_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_srav_epi16(0, a, count);
@@ -18288,7 +19200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_blend_epi16() {
+    const unsafe fn test_mm512_mask_blend_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_mask_blend_epi16(0b11111111_00000000_11111111_00000000, a, b);
@@ -18299,7 +19211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_blend_epi16() {
+    const unsafe fn test_mm256_mask_blend_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_mask_blend_epi16(0b11111111_00000000, a, b);
@@ -18308,7 +19220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_blend_epi16() {
+    const unsafe fn test_mm_mask_blend_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_mask_blend_epi16(0b11110000, a, b);
@@ -18317,7 +19229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_blend_epi8() {
+    const unsafe fn test_mm512_mask_blend_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_mask_blend_epi8(
@@ -18334,7 +19246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_blend_epi8() {
+    const unsafe fn test_mm256_mask_blend_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_mask_blend_epi8(0b11111111_00000000_11111111_00000000, a, b);
@@ -18345,7 +19257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_blend_epi8() {
+    const unsafe fn test_mm_mask_blend_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_mask_blend_epi8(0b11111111_00000000, a, b);
@@ -18354,7 +19266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_broadcastw_epi16() {
+    const unsafe fn test_mm512_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_broadcastw_epi16(a);
         let e = _mm512_set1_epi16(24);
@@ -18362,7 +19274,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_broadcastw_epi16() {
+    const unsafe fn test_mm512_mask_broadcastw_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_broadcastw_epi16(src, 0, a);
@@ -18373,7 +19285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_broadcastw_epi16() {
+    const unsafe fn test_mm512_maskz_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_broadcastw_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -18383,7 +19295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_broadcastw_epi16() {
+    const unsafe fn test_mm256_mask_broadcastw_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_mask_broadcastw_epi16(src, 0, a);
@@ -18394,7 +19306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcastw_epi16() {
+    const unsafe fn test_mm256_maskz_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_maskz_broadcastw_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -18404,7 +19316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_broadcastw_epi16() {
+    const unsafe fn test_mm_mask_broadcastw_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm_mask_broadcastw_epi16(src, 0, a);
@@ -18415,7 +19327,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_broadcastw_epi16() {
+    const unsafe fn test_mm_maskz_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm_maskz_broadcastw_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -18425,7 +19337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_broadcastb_epi8() {
+    const unsafe fn test_mm512_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -18435,7 +19347,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_broadcastb_epi8() {
+    const unsafe fn test_mm512_mask_broadcastb_epi8() {
         let src = _mm512_set1_epi8(1);
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18452,7 +19364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_broadcastb_epi8() {
+    const unsafe fn test_mm512_maskz_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -18467,7 +19379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_broadcastb_epi8() {
+    const unsafe fn test_mm256_mask_broadcastb_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18480,7 +19392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcastb_epi8() {
+    const unsafe fn test_mm256_maskz_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -18492,7 +19404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_broadcastb_epi8() {
+    const unsafe fn test_mm_mask_broadcastb_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18505,7 +19417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_broadcastb_epi8() {
+    const unsafe fn test_mm_maskz_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -18517,7 +19429,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_unpackhi_epi16() {
+    const unsafe fn test_mm512_unpackhi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18532,7 +19444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_unpackhi_epi16() {
+    const unsafe fn test_mm512_mask_unpackhi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18549,7 +19461,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_unpackhi_epi16() {
+    const unsafe fn test_mm512_maskz_unpackhi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18566,7 +19478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_unpackhi_epi16() {
+    const unsafe fn test_mm256_mask_unpackhi_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -18579,7 +19491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_unpackhi_epi16() {
+    const unsafe fn test_mm256_maskz_unpackhi_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -18592,7 +19504,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_unpackhi_epi16() {
+    const unsafe fn test_mm_mask_unpackhi_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_mask_unpackhi_epi16(a, 0, a, b);
@@ -18603,7 +19515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_unpackhi_epi16() {
+    const unsafe fn test_mm_maskz_unpackhi_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_maskz_unpackhi_epi16(0, a, b);
@@ -18614,7 +19526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_unpackhi_epi8() {
+    const unsafe fn test_mm512_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18635,7 +19547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_unpackhi_epi8() {
+    const unsafe fn test_mm512_mask_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18663,7 +19575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_unpackhi_epi8() {
+    const unsafe fn test_mm512_maskz_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18690,7 +19602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_unpackhi_epi8() {
+    const unsafe fn test_mm256_mask_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18707,7 +19619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_unpackhi_epi8() {
+    const unsafe fn test_mm256_maskz_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18724,7 +19636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_unpackhi_epi8() {
+    const unsafe fn test_mm_mask_unpackhi_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -18737,7 +19649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_unpackhi_epi8() {
+    const unsafe fn test_mm_maskz_unpackhi_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -18750,7 +19662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_unpacklo_epi16() {
+    const unsafe fn test_mm512_unpacklo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18765,7 +19677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_unpacklo_epi16() {
+    const unsafe fn test_mm512_mask_unpacklo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18782,7 +19694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_unpacklo_epi16() {
+    const unsafe fn test_mm512_maskz_unpacklo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18799,7 +19711,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_unpacklo_epi16() {
+    const unsafe fn test_mm256_mask_unpacklo_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -18812,7 +19724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_unpacklo_epi16() {
+    const unsafe fn test_mm256_maskz_unpacklo_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -18825,7 +19737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_unpacklo_epi16() {
+    const unsafe fn test_mm_mask_unpacklo_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_mask_unpacklo_epi16(a, 0, a, b);
@@ -18836,7 +19748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_unpacklo_epi16() {
+    const unsafe fn test_mm_maskz_unpacklo_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_maskz_unpacklo_epi16(0, a, b);
@@ -18847,7 +19759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_unpacklo_epi8() {
+    const unsafe fn test_mm512_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18868,7 +19780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_unpacklo_epi8() {
+    const unsafe fn test_mm512_mask_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18896,7 +19808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_unpacklo_epi8() {
+    const unsafe fn test_mm512_maskz_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -18923,7 +19835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_unpacklo_epi8() {
+    const unsafe fn test_mm256_mask_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18940,7 +19852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_unpacklo_epi8() {
+    const unsafe fn test_mm256_maskz_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -18957,7 +19869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_unpacklo_epi8() {
+    const unsafe fn test_mm_mask_unpacklo_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -18972,7 +19884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_unpacklo_epi8() {
+    const unsafe fn test_mm_maskz_unpacklo_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -18987,7 +19899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_mov_epi16() {
+    const unsafe fn test_mm512_mask_mov_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm512_set1_epi16(2);
         let r = _mm512_mask_mov_epi16(src, 0, a);
@@ -18997,7 +19909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_mov_epi16() {
+    const unsafe fn test_mm512_maskz_mov_epi16() {
         let a = _mm512_set1_epi16(2);
         let r = _mm512_maskz_mov_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19006,7 +19918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_mov_epi16() {
+    const unsafe fn test_mm256_mask_mov_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm256_set1_epi16(2);
         let r = _mm256_mask_mov_epi16(src, 0, a);
@@ -19016,7 +19928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_mov_epi16() {
+    const unsafe fn test_mm256_maskz_mov_epi16() {
         let a = _mm256_set1_epi16(2);
         let r = _mm256_maskz_mov_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19025,7 +19937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_mov_epi16() {
+    const unsafe fn test_mm_mask_mov_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi16(2);
         let r = _mm_mask_mov_epi16(src, 0, a);
@@ -19035,7 +19947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_mov_epi16() {
+    const unsafe fn test_mm_maskz_mov_epi16() {
         let a = _mm_set1_epi16(2);
         let r = _mm_maskz_mov_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19044,7 +19956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_mov_epi8() {
+    const unsafe fn test_mm512_mask_mov_epi8() {
         let src = _mm512_set1_epi8(1);
         let a = _mm512_set1_epi8(2);
         let r = _mm512_mask_mov_epi8(src, 0, a);
@@ -19058,7 +19970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_mov_epi8() {
+    const unsafe fn test_mm512_maskz_mov_epi8() {
         let a = _mm512_set1_epi8(2);
         let r = _mm512_maskz_mov_epi8(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19070,7 +19982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_mov_epi8() {
+    const unsafe fn test_mm256_mask_mov_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm256_set1_epi8(2);
         let r = _mm256_mask_mov_epi8(src, 0, a);
@@ -19080,7 +19992,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_mov_epi8() {
+    const unsafe fn test_mm256_maskz_mov_epi8() {
         let a = _mm256_set1_epi8(2);
         let r = _mm256_maskz_mov_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19089,7 +20001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_mov_epi8() {
+    const unsafe fn test_mm_mask_mov_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm_set1_epi8(2);
         let r = _mm_mask_mov_epi8(src, 0, a);
@@ -19099,7 +20011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_mov_epi8() {
+    const unsafe fn test_mm_maskz_mov_epi8() {
         let a = _mm_set1_epi8(2);
         let r = _mm_maskz_mov_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19108,7 +20020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_set1_epi16() {
+    const unsafe fn test_mm512_mask_set1_epi16() {
         let src = _mm512_set1_epi16(2);
         let a: i16 = 11;
         let r = _mm512_mask_set1_epi16(src, 0, a);
@@ -19119,7 +20031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_set1_epi16() {
+    const unsafe fn test_mm512_maskz_set1_epi16() {
         let a: i16 = 11;
         let r = _mm512_maskz_set1_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19129,7 +20041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_set1_epi16() {
+    const unsafe fn test_mm256_mask_set1_epi16() {
         let src = _mm256_set1_epi16(2);
         let a: i16 = 11;
         let r = _mm256_mask_set1_epi16(src, 0, a);
@@ -19140,7 +20052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_set1_epi16() {
+    const unsafe fn test_mm256_maskz_set1_epi16() {
         let a: i16 = 11;
         let r = _mm256_maskz_set1_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19150,7 +20062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_set1_epi16() {
+    const unsafe fn test_mm_mask_set1_epi16() {
         let src = _mm_set1_epi16(2);
         let a: i16 = 11;
         let r = _mm_mask_set1_epi16(src, 0, a);
@@ -19161,7 +20073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_set1_epi16() {
+    const unsafe fn test_mm_maskz_set1_epi16() {
         let a: i16 = 11;
         let r = _mm_maskz_set1_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19171,7 +20083,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_set1_epi8() {
+    const unsafe fn test_mm512_mask_set1_epi8() {
         let src = _mm512_set1_epi8(2);
         let a: i8 = 11;
         let r = _mm512_mask_set1_epi8(src, 0, a);
@@ -19186,7 +20098,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_set1_epi8() {
+    const unsafe fn test_mm512_maskz_set1_epi8() {
         let a: i8 = 11;
         let r = _mm512_maskz_set1_epi8(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19199,7 +20111,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_set1_epi8() {
+    const unsafe fn test_mm256_mask_set1_epi8() {
         let src = _mm256_set1_epi8(2);
         let a: i8 = 11;
         let r = _mm256_mask_set1_epi8(src, 0, a);
@@ -19210,7 +20122,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_set1_epi8() {
+    const unsafe fn test_mm256_maskz_set1_epi8() {
         let a: i8 = 11;
         let r = _mm256_maskz_set1_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19220,7 +20132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_set1_epi8() {
+    const unsafe fn test_mm_mask_set1_epi8() {
         let src = _mm_set1_epi8(2);
         let a: i8 = 11;
         let r = _mm_mask_set1_epi8(src, 0, a);
@@ -19231,7 +20143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_set1_epi8() {
+    const unsafe fn test_mm_maskz_set1_epi8() {
         let a: i8 = 11;
         let r = _mm_maskz_set1_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19241,7 +20153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_shufflelo_epi16() {
+    const unsafe fn test_mm512_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -19257,7 +20169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_shufflelo_epi16() {
+    const unsafe fn test_mm512_mask_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -19279,7 +20191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_shufflelo_epi16() {
+    const unsafe fn test_mm512_maskz_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -19298,7 +20210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_shufflelo_epi16() {
+    const unsafe fn test_mm256_mask_shufflelo_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -19308,7 +20220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_shufflelo_epi16() {
+    const unsafe fn test_mm256_maskz_shufflelo_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19318,7 +20230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_shufflelo_epi16() {
+    const unsafe fn test_mm_mask_shufflelo_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -19328,7 +20240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_shufflelo_epi16() {
+    const unsafe fn test_mm_maskz_shufflelo_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19338,7 +20250,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_shufflehi_epi16() {
+    const unsafe fn test_mm512_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -19354,7 +20266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_shufflehi_epi16() {
+    const unsafe fn test_mm512_mask_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -19376,7 +20288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_shufflehi_epi16() {
+    const unsafe fn test_mm512_maskz_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -19395,7 +20307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_shufflehi_epi16() {
+    const unsafe fn test_mm256_mask_shufflehi_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -19405,7 +20317,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_shufflehi_epi16() {
+    const unsafe fn test_mm256_maskz_shufflehi_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19415,7 +20327,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_shufflehi_epi16() {
+    const unsafe fn test_mm_mask_shufflehi_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -19425,7 +20337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_shufflehi_epi16() {
+    const unsafe fn test_mm_maskz_shufflehi_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19556,7 +20468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_test_epi16_mask() {
+    const unsafe fn test_mm512_test_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_test_epi16_mask(a, b);
@@ -19565,7 +20477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_test_epi16_mask() {
+    const unsafe fn test_mm512_mask_test_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi16_mask(0, a, b);
@@ -19576,7 +20488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_test_epi16_mask() {
+    const unsafe fn test_mm256_test_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_test_epi16_mask(a, b);
@@ -19585,7 +20497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_test_epi16_mask() {
+    const unsafe fn test_mm256_mask_test_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi16_mask(0, a, b);
@@ -19596,7 +20508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_test_epi16_mask() {
+    const unsafe fn test_mm_test_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_test_epi16_mask(a, b);
@@ -19605,7 +20517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_test_epi16_mask() {
+    const unsafe fn test_mm_mask_test_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi16_mask(0, a, b);
@@ -19616,7 +20528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_test_epi8_mask() {
+    const unsafe fn test_mm512_test_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_test_epi8_mask(a, b);
@@ -19626,7 +20538,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_test_epi8_mask() {
+    const unsafe fn test_mm512_mask_test_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi8_mask(0, a, b);
@@ -19642,7 +20554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_test_epi8_mask() {
+    const unsafe fn test_mm256_test_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_test_epi8_mask(a, b);
@@ -19651,7 +20563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_test_epi8_mask() {
+    const unsafe fn test_mm256_mask_test_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi8_mask(0, a, b);
@@ -19662,7 +20574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_test_epi8_mask() {
+    const unsafe fn test_mm_test_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_test_epi8_mask(a, b);
@@ -19671,7 +20583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_test_epi8_mask() {
+    const unsafe fn test_mm_mask_test_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi8_mask(0, a, b);
@@ -19682,7 +20594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_testn_epi16_mask() {
+    const unsafe fn test_mm512_testn_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi16_mask(a, b);
@@ -19691,7 +20603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_testn_epi16_mask() {
+    const unsafe fn test_mm512_mask_testn_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_mask_testn_epi16_mask(0, a, b);
@@ -19702,7 +20614,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_testn_epi16_mask() {
+    const unsafe fn test_mm256_testn_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_testn_epi16_mask(a, b);
@@ -19711,7 +20623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_testn_epi16_mask() {
+    const unsafe fn test_mm256_mask_testn_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_mask_testn_epi16_mask(0, a, b);
@@ -19722,7 +20634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_testn_epi16_mask() {
+    const unsafe fn test_mm_testn_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_testn_epi16_mask(a, b);
@@ -19731,7 +20643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_testn_epi16_mask() {
+    const unsafe fn test_mm_mask_testn_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_mask_testn_epi16_mask(0, a, b);
@@ -19742,7 +20654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_testn_epi8_mask() {
+    const unsafe fn test_mm512_testn_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi8_mask(a, b);
@@ -19752,7 +20664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_testn_epi8_mask() {
+    const unsafe fn test_mm512_mask_testn_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_mask_testn_epi8_mask(0, a, b);
@@ -19768,7 +20680,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_testn_epi8_mask() {
+    const unsafe fn test_mm256_testn_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_testn_epi8_mask(a, b);
@@ -19777,7 +20689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_testn_epi8_mask() {
+    const unsafe fn test_mm256_mask_testn_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_mask_testn_epi8_mask(0, a, b);
@@ -19788,7 +20700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_testn_epi8_mask() {
+    const unsafe fn test_mm_testn_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_testn_epi8_mask(a, b);
@@ -19797,7 +20709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_testn_epi8_mask() {
+    const unsafe fn test_mm_mask_testn_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_mask_testn_epi8_mask(0, a, b);
@@ -19808,7 +20720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_store_mask64() {
+    const unsafe fn test_store_mask64() {
         let a: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
         let mut r = 0;
@@ -19817,7 +20729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_store_mask32() {
+    const unsafe fn test_store_mask32() {
         let a: __mmask32 = 0b11111111_00000000_11111111_00000000;
         let mut r = 0;
         _store_mask32(&mut r, a);
@@ -19825,7 +20737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_load_mask64() {
+    const unsafe fn test_load_mask64() {
         let p: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
         let r = _load_mask64(&p);
@@ -19835,7 +20747,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_load_mask32() {
+    const unsafe fn test_load_mask32() {
         let p: __mmask32 = 0b11111111_00000000_11111111_00000000;
         let r = _load_mask32(&p);
         let e: __mmask32 = 0b11111111_00000000_11111111_00000000;
@@ -19948,7 +20860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_movepi16_mask() {
+    const unsafe fn test_mm512_movepi16_mask() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_movepi16_mask(a);
         let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
@@ -19956,7 +20868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_movepi16_mask() {
+    const unsafe fn test_mm256_movepi16_mask() {
         let a = _mm256_set1_epi16(1 << 15);
         let r = _mm256_movepi16_mask(a);
         let e: __mmask16 = 0b11111111_11111111;
@@ -19964,7 +20876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_movepi16_mask() {
+    const unsafe fn test_mm_movepi16_mask() {
         let a = _mm_set1_epi16(1 << 15);
         let r = _mm_movepi16_mask(a);
         let e: __mmask8 = 0b11111111;
@@ -19972,7 +20884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_movepi8_mask() {
+    const unsafe fn test_mm512_movepi8_mask() {
         let a = _mm512_set1_epi8(1 << 7);
         let r = _mm512_movepi8_mask(a);
         let e: __mmask64 =
@@ -19981,7 +20893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_movepi8_mask() {
+    const unsafe fn test_mm256_movepi8_mask() {
         let a = _mm256_set1_epi8(1 << 7);
         let r = _mm256_movepi8_mask(a);
         let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
@@ -19989,7 +20901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_movepi8_mask() {
+    const unsafe fn test_mm_movepi8_mask() {
         let a = _mm_set1_epi8(1 << 7);
         let r = _mm_movepi8_mask(a);
         let e: __mmask16 = 0b11111111_11111111;
@@ -19997,7 +20909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_movm_epi16() {
+    const unsafe fn test_mm512_movm_epi16() {
         let a: __mmask32 = 0b11111111_11111111_11111111_11111111;
         let r = _mm512_movm_epi16(a);
         let e = _mm512_set1_epi16(
@@ -20022,7 +20934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_movm_epi16() {
+    const unsafe fn test_mm256_movm_epi16() {
         let a: __mmask16 = 0b11111111_11111111;
         let r = _mm256_movm_epi16(a);
         let e = _mm256_set1_epi16(
@@ -20047,7 +20959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_movm_epi16() {
+    const unsafe fn test_mm_movm_epi16() {
         let a: __mmask8 = 0b11111111;
         let r = _mm_movm_epi16(a);
         let e = _mm_set1_epi16(
@@ -20072,7 +20984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_movm_epi8() {
+    const unsafe fn test_mm512_movm_epi8() {
         let a: __mmask64 =
             0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
         let r = _mm512_movm_epi8(a);
@@ -20082,7 +20994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_movm_epi8() {
+    const unsafe fn test_mm256_movm_epi8() {
         let a: __mmask32 = 0b11111111_11111111_11111111_11111111;
         let r = _mm256_movm_epi8(a);
         let e =
@@ -20091,7 +21003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_movm_epi8() {
+    const unsafe fn test_mm_movm_epi8() {
         let a: __mmask16 = 0b11111111_11111111;
         let r = _mm_movm_epi8(a);
         let e =
@@ -20100,7 +21012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_cvtmask32_u32() {
+    const unsafe fn test_cvtmask32_u32() {
         let a: __mmask32 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtmask32_u32(a);
         let e: u32 = 0b11001100_00110011_01100110_10011001;
@@ -20108,7 +21020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_cvtu32_mask32() {
+    const unsafe fn test_cvtu32_mask32() {
         let a: u32 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtu32_mask32(a);
         let e: __mmask32 = 0b11001100_00110011_01100110_10011001;
@@ -20116,7 +21028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kadd_mask32() {
+    const unsafe fn test_kadd_mask32() {
         let a: __mmask32 = 11;
         let b: __mmask32 = 22;
         let r = _kadd_mask32(a, b);
@@ -20125,7 +21037,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kadd_mask64() {
+    const unsafe fn test_kadd_mask64() {
         let a: __mmask64 = 11;
         let b: __mmask64 = 22;
         let r = _kadd_mask64(a, b);
@@ -20134,7 +21046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kand_mask32() {
+    const unsafe fn test_kand_mask32() {
         let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kand_mask32(a, b);
@@ -20143,7 +21055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kand_mask64() {
+    const unsafe fn test_kand_mask64() {
         let a: __mmask64 =
             0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
         let b: __mmask64 =
@@ -20155,7 +21067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_knot_mask32() {
+    const unsafe fn test_knot_mask32() {
         let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _knot_mask32(a);
         let e: __mmask32 = 0b00110011_11001100_00110011_11001100;
@@ -20163,7 +21075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_knot_mask64() {
+    const unsafe fn test_knot_mask64() {
         let a: __mmask64 =
             0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
         let r = _knot_mask64(a);
@@ -20173,7 +21085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kandn_mask32() {
+    const unsafe fn test_kandn_mask32() {
         let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kandn_mask32(a, b);
@@ -20182,7 +21094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kandn_mask64() {
+    const unsafe fn test_kandn_mask64() {
         let a: __mmask64 =
             0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
         let b: __mmask64 =
@@ -20194,7 +21106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kor_mask32() {
+    const unsafe fn test_kor_mask32() {
         let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kor_mask32(a, b);
@@ -20203,7 +21115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kor_mask64() {
+    const unsafe fn test_kor_mask64() {
         let a: __mmask64 =
             0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
         let b: __mmask64 =
@@ -20215,7 +21127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kxor_mask32() {
+    const unsafe fn test_kxor_mask32() {
         let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kxor_mask32(a, b);
@@ -20224,7 +21136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kxor_mask64() {
+    const unsafe fn test_kxor_mask64() {
         let a: __mmask64 =
             0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
         let b: __mmask64 =
@@ -20236,7 +21148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kxnor_mask32() {
+    const unsafe fn test_kxnor_mask32() {
         let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kxnor_mask32(a, b);
@@ -20245,7 +21157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kxnor_mask64() {
+    const unsafe fn test_kxnor_mask64() {
         let a: __mmask64 =
             0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
         let b: __mmask64 =
@@ -20257,7 +21169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kortest_mask32_u8() {
+    const unsafe fn test_kortest_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let mut all_ones: u8 = 0;
@@ -20267,7 +21179,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kortest_mask64_u8() {
+    const unsafe fn test_kortest_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let mut all_ones: u8 = 0;
@@ -20277,7 +21189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kortestc_mask32_u8() {
+    const unsafe fn test_kortestc_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let r = _kortestc_mask32_u8(a, b);
@@ -20285,7 +21197,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kortestc_mask64_u8() {
+    const unsafe fn test_kortestc_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let r = _kortestc_mask64_u8(a, b);
@@ -20293,7 +21205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kortestz_mask32_u8() {
+    const unsafe fn test_kortestz_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let r = _kortestz_mask32_u8(a, b);
@@ -20301,7 +21213,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kortestz_mask64_u8() {
+    const unsafe fn test_kortestz_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let r = _kortestz_mask64_u8(a, b);
@@ -20309,7 +21221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kshiftli_mask32() {
+    const unsafe fn test_kshiftli_mask32() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let r = _kshiftli_mask32::<3>(a);
         let e: __mmask32 = 0b0100101101001011_0100101101001000;
@@ -20329,7 +21241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kshiftli_mask64() {
+    const unsafe fn test_kshiftli_mask64() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let r = _kshiftli_mask64::<3>(a);
         let e: __mmask64 = 0b0110100101101001011_0100101101001000;
@@ -20349,7 +21261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kshiftri_mask32() {
+    const unsafe fn test_kshiftri_mask32() {
         let a: __mmask32 = 0b1010100101101001_0110100101101001;
         let r = _kshiftri_mask32::<3>(a);
         let e: __mmask32 = 0b0001010100101101_0010110100101101;
@@ -20369,7 +21281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_kshiftri_mask64() {
+    const unsafe fn test_kshiftri_mask64() {
         let a: __mmask64 = 0b1010100101101001011_0100101101001000;
         let r = _kshiftri_mask64::<3>(a);
         let e: __mmask64 = 0b1010100101101001_0110100101101001;
@@ -20393,7 +21305,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_ktest_mask32_u8() {
+    const unsafe fn test_ktest_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let mut and_not: u8 = 0;
@@ -20403,7 +21315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_ktestc_mask32_u8() {
+    const unsafe fn test_ktestc_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let r = _ktestc_mask32_u8(a, b);
@@ -20411,7 +21323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_ktestz_mask32_u8() {
+    const unsafe fn test_ktestz_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let r = _ktestz_mask32_u8(a, b);
@@ -20419,7 +21331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_ktest_mask64_u8() {
+    const unsafe fn test_ktest_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let mut and_not: u8 = 0;
@@ -20429,7 +21341,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_ktestc_mask64_u8() {
+    const unsafe fn test_ktestc_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let r = _ktestc_mask64_u8(a, b);
@@ -20437,7 +21349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_ktestz_mask64_u8() {
+    const unsafe fn test_ktestz_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let r = _ktestz_mask64_u8(a, b);
@@ -20445,7 +21357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_kunpackw() {
+    const unsafe fn test_mm512_kunpackw() {
         let a: u32 = 0x00110011;
         let b: u32 = 0x00001011;
         let r = _mm512_kunpackw(a, b);
@@ -20454,7 +21366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_kunpackd() {
+    const unsafe fn test_mm512_kunpackd() {
         let a: u64 = 0x11001100_00110011;
         let b: u64 = 0x00101110_00001011;
         let r = _mm512_kunpackd(a, b);
@@ -20463,7 +21375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cvtepi16_epi8() {
+    const unsafe fn test_mm512_cvtepi16_epi8() {
         let a = _mm512_set1_epi16(2);
         let r = _mm512_cvtepi16_epi8(a);
         let e = _mm256_set1_epi8(2);
@@ -20471,7 +21383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtepi16_epi8() {
+    const unsafe fn test_mm512_mask_cvtepi16_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm512_set1_epi16(2);
         let r = _mm512_mask_cvtepi16_epi8(src, 0, a);
@@ -20482,7 +21394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_cvtepi16_epi8() {
+    const unsafe fn test_mm512_maskz_cvtepi16_epi8() {
         let a = _mm512_set1_epi16(2);
         let r = _mm512_maskz_cvtepi16_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20492,7 +21404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cvtepi16_epi8() {
+    const unsafe fn test_mm256_cvtepi16_epi8() {
         let a = _mm256_set1_epi16(2);
         let r = _mm256_cvtepi16_epi8(a);
         let e = _mm_set1_epi8(2);
@@ -20500,7 +21412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi16_epi8() {
+    const unsafe fn test_mm256_mask_cvtepi16_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm256_set1_epi16(2);
         let r = _mm256_mask_cvtepi16_epi8(src, 0, a);
@@ -20511,7 +21423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi16_epi8() {
+    const unsafe fn test_mm256_maskz_cvtepi16_epi8() {
         let a = _mm256_set1_epi16(2);
         let r = _mm256_maskz_cvtepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20521,7 +21433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cvtepi16_epi8() {
+    const unsafe fn test_mm_cvtepi16_epi8() {
         let a = _mm_set1_epi16(2);
         let r = _mm_cvtepi16_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
@@ -20529,7 +21441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi16_epi8() {
+    const unsafe fn test_mm_mask_cvtepi16_epi8() {
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
         let a = _mm_set1_epi16(2);
         let r = _mm_mask_cvtepi16_epi8(src, 0, a);
@@ -20540,7 +21452,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi16_epi8() {
+    const unsafe fn test_mm_maskz_cvtepi16_epi8() {
         let a = _mm_set1_epi16(2);
         let r = _mm_maskz_cvtepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20727,7 +21639,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cvtepi8_epi16() {
+    const unsafe fn test_mm512_cvtepi8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_cvtepi8_epi16(a);
         let e = _mm512_set1_epi16(2);
@@ -20735,7 +21647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtepi8_epi16() {
+    const unsafe fn test_mm512_mask_cvtepi8_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm256_set1_epi8(2);
         let r = _mm512_mask_cvtepi8_epi16(src, 0, a);
@@ -20746,7 +21658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_cvtepi8_epi16() {
+    const unsafe fn test_mm512_maskz_cvtepi8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_maskz_cvtepi8_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -20756,7 +21668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi8_epi16() {
+    const unsafe fn test_mm256_mask_cvtepi8_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm256_mask_cvtepi8_epi16(src, 0, a);
@@ -20767,7 +21679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi8_epi16() {
+    const unsafe fn test_mm256_maskz_cvtepi8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm256_maskz_cvtepi8_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20777,7 +21689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi8_epi16() {
+    const unsafe fn test_mm_mask_cvtepi8_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm_mask_cvtepi8_epi16(src, 0, a);
@@ -20788,7 +21700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi8_epi16() {
+    const unsafe fn test_mm_maskz_cvtepi8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm_maskz_cvtepi8_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20798,7 +21710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cvtepu8_epi16() {
+    const unsafe fn test_mm512_cvtepu8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_cvtepu8_epi16(a);
         let e = _mm512_set1_epi16(2);
@@ -20806,7 +21718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtepu8_epi16() {
+    const unsafe fn test_mm512_mask_cvtepu8_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm256_set1_epi8(2);
         let r = _mm512_mask_cvtepu8_epi16(src, 0, a);
@@ -20817,7 +21729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_cvtepu8_epi16() {
+    const unsafe fn test_mm512_maskz_cvtepu8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_maskz_cvtepu8_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -20827,7 +21739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu8_epi16() {
+    const unsafe fn test_mm256_mask_cvtepu8_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm256_mask_cvtepu8_epi16(src, 0, a);
@@ -20838,7 +21750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu8_epi16() {
+    const unsafe fn test_mm256_maskz_cvtepu8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm256_maskz_cvtepu8_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20848,7 +21760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu8_epi16() {
+    const unsafe fn test_mm_mask_cvtepu8_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm_mask_cvtepu8_epi16(src, 0, a);
@@ -20859,7 +21771,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu8_epi16() {
+    const unsafe fn test_mm_maskz_cvtepu8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm_maskz_cvtepu8_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20869,7 +21781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_bslli_epi128() {
+    const unsafe fn test_mm512_bslli_epi128() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -20889,7 +21801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_bsrli_epi128() {
+    const unsafe fn test_mm512_bsrli_epi128() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@@ -20909,7 +21821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_alignr_epi8() {
+    const unsafe fn test_mm512_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -20930,7 +21842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_alignr_epi8() {
+    const unsafe fn test_mm512_mask_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -20958,7 +21870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_alignr_epi8() {
+    const unsafe fn test_mm512_maskz_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -20985,7 +21897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_alignr_epi8() {
+    const unsafe fn test_mm256_mask_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21004,7 +21916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_alignr_epi8() {
+    const unsafe fn test_mm256_maskz_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21023,7 +21935,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_alignr_epi8() {
+    const unsafe fn test_mm_mask_alignr_epi8() {
         let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
         let b = _mm_set1_epi8(1);
         let r = _mm_mask_alignr_epi8::<14>(a, 0, a, b);
@@ -21034,7 +21946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_alignr_epi8() {
+    const unsafe fn test_mm_maskz_alignr_epi8() {
         let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
         let b = _mm_set1_epi8(1);
         let r = _mm_maskz_alignr_epi8::<14>(0, a, b);
diff --git a/crates/core_arch/src/x86_64/avx512bw.rs b/crates/core_arch/src/x86_64/avx512bw.rs
index 466c36ef31..a8e5183e0c 100644
--- a/crates/core_arch/src/x86_64/avx512bw.rs
+++ b/crates/core_arch/src/x86_64/avx512bw.rs
@@ -6,7 +6,8 @@ use crate::core_arch::x86::*;
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtmask64_u64(a: __mmask64) -> u64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtmask64_u64(a: __mmask64) -> u64 {
     a
 }
 
@@ -16,19 +17,21 @@ pub fn _cvtmask64_u64(a: __mmask64) -> u64 {
 #[inline]
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtu64_mask64(a: u64) -> __mmask64 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtu64_mask64(a: u64) -> __mmask64 {
     a
 }
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
     use crate::core_arch::{x86::*, x86_64::*};
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_cvtmask64_u64() {
+    const unsafe fn test_cvtmask64_u64() {
         let a: __mmask64 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtmask64_u64(a);
         let e: u64 = 0b11001100_00110011_01100110_10011001;
@@ -36,7 +39,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_cvtu64_mask64() {
+    const unsafe fn test_cvtu64_mask64() {
         let a: u64 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtu64_mask64(a);
         let e: __mmask64 = 0b11001100_00110011_01100110_10011001;

From 550f9f46d0a9e2ffd6882cd40ce7996a6552653f Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:23:20 +0530
Subject: [PATCH 063/326] Make `avx512cd` functions const

---
 crates/core_arch/src/x86/avx512cd.rs | 121 ++++++++++++++++-----------
 1 file changed, 73 insertions(+), 48 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512cd.rs b/crates/core_arch/src/x86/avx512cd.rs
index 78735fcc90..b163698b56 100644
--- a/crates/core_arch/src/x86/avx512cd.rs
+++ b/crates/core_arch/src/x86/avx512cd.rs
@@ -11,7 +11,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
-pub fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i {
     _mm512_set1_epi32(k as i32)
 }
 
@@ -22,7 +23,8 @@ pub fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
-pub fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i {
     _mm256_set1_epi32(k as i32)
 }
 
@@ -33,7 +35,8 @@ pub fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
-pub fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i {
     _mm_set1_epi32(k as i32)
 }
 
@@ -44,7 +47,8 @@ pub fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i {
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
-pub fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i {
     _mm512_set1_epi64(k as i64)
 }
 
@@ -55,7 +59,8 @@ pub fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
-pub fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i {
     _mm256_set1_epi64x(k as i64)
 }
 
@@ -66,7 +71,8 @@ pub fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
-pub fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i {
     _mm_set1_epi64x(k as i64)
 }
 
@@ -311,7 +317,8 @@ pub fn _mm_maskz_conflict_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i {
     unsafe { transmute(simd_ctlz(a.as_i32x16())) }
 }
 
@@ -322,7 +329,8 @@ pub fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         let zerocount = _mm512_lzcnt_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, zerocount, src.as_i32x16()))
@@ -336,7 +344,8 @@ pub fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         let zerocount = _mm512_lzcnt_epi32(a).as_i32x16();
         transmute(simd_select_bitmask(k, zerocount, i32x16::ZERO))
@@ -350,7 +359,8 @@ pub fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i {
     unsafe { transmute(simd_ctlz(a.as_i32x8())) }
 }
 
@@ -361,7 +371,8 @@ pub fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let zerocount = _mm256_lzcnt_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, zerocount, src.as_i32x8()))
@@ -375,7 +386,8 @@ pub fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let zerocount = _mm256_lzcnt_epi32(a).as_i32x8();
         transmute(simd_select_bitmask(k, zerocount, i32x8::ZERO))
@@ -389,7 +401,8 @@ pub fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm_lzcnt_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_lzcnt_epi32(a: __m128i) -> __m128i {
     unsafe { transmute(simd_ctlz(a.as_i32x4())) }
 }
 
@@ -400,7 +413,8 @@ pub fn _mm_lzcnt_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let zerocount = _mm_lzcnt_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, zerocount, src.as_i32x4()))
@@ -414,7 +428,8 @@ pub fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntd))]
-pub fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let zerocount = _mm_lzcnt_epi32(a).as_i32x4();
         transmute(simd_select_bitmask(k, zerocount, i32x4::ZERO))
@@ -428,7 +443,8 @@ pub fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i {
     unsafe { transmute(simd_ctlz(a.as_i64x8())) }
 }
 
@@ -439,7 +455,8 @@ pub fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         let zerocount = _mm512_lzcnt_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, zerocount, src.as_i64x8()))
@@ -453,7 +470,8 @@ pub fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i
 #[target_feature(enable = "avx512cd")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         let zerocount = _mm512_lzcnt_epi64(a).as_i64x8();
         transmute(simd_select_bitmask(k, zerocount, i64x8::ZERO))
@@ -467,7 +485,8 @@ pub fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i {
     unsafe { transmute(simd_ctlz(a.as_i64x4())) }
 }
 
@@ -478,7 +497,8 @@ pub fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let zerocount = _mm256_lzcnt_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, zerocount, src.as_i64x4()))
@@ -492,7 +512,8 @@ pub fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         let zerocount = _mm256_lzcnt_epi64(a).as_i64x4();
         transmute(simd_select_bitmask(k, zerocount, i64x4::ZERO))
@@ -506,7 +527,8 @@ pub fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm_lzcnt_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_lzcnt_epi64(a: __m128i) -> __m128i {
     unsafe { transmute(simd_ctlz(a.as_i64x2())) }
 }
 
@@ -517,7 +539,8 @@ pub fn _mm_lzcnt_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let zerocount = _mm_lzcnt_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, zerocount, src.as_i64x2()))
@@ -531,7 +554,8 @@ pub fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512cd,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vplzcntq))]
-pub fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let zerocount = _mm_lzcnt_epi64(a).as_i64x2();
         transmute(simd_select_bitmask(k, zerocount, i64x2::ZERO))
@@ -557,12 +581,13 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use crate::core_arch::x86::*;
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_broadcastmw_epi32() {
+    const unsafe fn test_mm512_broadcastmw_epi32() {
         let a: __mmask16 = 2;
         let r = _mm512_broadcastmw_epi32(a);
         let e = _mm512_set1_epi32(2);
@@ -570,7 +595,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_broadcastmw_epi32() {
+    const unsafe fn test_mm256_broadcastmw_epi32() {
         let a: __mmask16 = 2;
         let r = _mm256_broadcastmw_epi32(a);
         let e = _mm256_set1_epi32(2);
@@ -578,7 +603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_broadcastmw_epi32() {
+    const unsafe fn test_mm_broadcastmw_epi32() {
         let a: __mmask16 = 2;
         let r = _mm_broadcastmw_epi32(a);
         let e = _mm_set1_epi32(2);
@@ -586,7 +611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_broadcastmb_epi64() {
+    const unsafe fn test_mm512_broadcastmb_epi64() {
         let a: __mmask8 = 2;
         let r = _mm512_broadcastmb_epi64(a);
         let e = _mm512_set1_epi64(2);
@@ -594,7 +619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_broadcastmb_epi64() {
+    const unsafe fn test_mm256_broadcastmb_epi64() {
         let a: __mmask8 = 2;
         let r = _mm256_broadcastmb_epi64(a);
         let e = _mm256_set1_epi64x(2);
@@ -602,7 +627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_broadcastmb_epi64() {
+    const unsafe fn test_mm_broadcastmb_epi64() {
         let a: __mmask8 = 2;
         let r = _mm_broadcastmb_epi64(a);
         let e = _mm_set1_epi64x(2);
@@ -1063,7 +1088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_lzcnt_epi32() {
+    const unsafe fn test_mm512_lzcnt_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_lzcnt_epi32(a);
         let e = _mm512_set1_epi32(31);
@@ -1071,7 +1096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_mask_lzcnt_epi32() {
+    const unsafe fn test_mm512_mask_lzcnt_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_mask_lzcnt_epi32(a, 0, a);
         assert_eq_m512i(r, a);
@@ -1081,7 +1106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_maskz_lzcnt_epi32() {
+    const unsafe fn test_mm512_maskz_lzcnt_epi32() {
         let a = _mm512_set1_epi32(2);
         let r = _mm512_maskz_lzcnt_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -1091,7 +1116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_lzcnt_epi32() {
+    const unsafe fn test_mm256_lzcnt_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_lzcnt_epi32(a);
         let e = _mm256_set1_epi32(31);
@@ -1099,7 +1124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_mask_lzcnt_epi32() {
+    const unsafe fn test_mm256_mask_lzcnt_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_mask_lzcnt_epi32(a, 0, a);
         assert_eq_m256i(r, a);
@@ -1109,7 +1134,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_maskz_lzcnt_epi32() {
+    const unsafe fn test_mm256_maskz_lzcnt_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_maskz_lzcnt_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -1119,7 +1144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_lzcnt_epi32() {
+    const unsafe fn test_mm_lzcnt_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_lzcnt_epi32(a);
         let e = _mm_set1_epi32(31);
@@ -1127,7 +1152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_mask_lzcnt_epi32() {
+    const unsafe fn test_mm_mask_lzcnt_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_mask_lzcnt_epi32(a, 0, a);
         assert_eq_m128i(r, a);
@@ -1137,7 +1162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_maskz_lzcnt_epi32() {
+    const unsafe fn test_mm_maskz_lzcnt_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_maskz_lzcnt_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -1147,7 +1172,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_lzcnt_epi64() {
+    const unsafe fn test_mm512_lzcnt_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_lzcnt_epi64(a);
         let e = _mm512_set1_epi64(63);
@@ -1155,7 +1180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_mask_lzcnt_epi64() {
+    const unsafe fn test_mm512_mask_lzcnt_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_mask_lzcnt_epi64(a, 0, a);
         assert_eq_m512i(r, a);
@@ -1165,7 +1190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_maskz_lzcnt_epi64() {
+    const unsafe fn test_mm512_maskz_lzcnt_epi64() {
         let a = _mm512_set1_epi64(2);
         let r = _mm512_maskz_lzcnt_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -1175,7 +1200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_lzcnt_epi64() {
+    const unsafe fn test_mm256_lzcnt_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_lzcnt_epi64(a);
         let e = _mm256_set1_epi64x(63);
@@ -1183,7 +1208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_mask_lzcnt_epi64() {
+    const unsafe fn test_mm256_mask_lzcnt_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_mask_lzcnt_epi64(a, 0, a);
         assert_eq_m256i(r, a);
@@ -1193,7 +1218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_maskz_lzcnt_epi64() {
+    const unsafe fn test_mm256_maskz_lzcnt_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_lzcnt_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -1203,7 +1228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_lzcnt_epi64() {
+    const unsafe fn test_mm_lzcnt_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_lzcnt_epi64(a);
         let e = _mm_set1_epi64x(63);
@@ -1211,7 +1236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_mask_lzcnt_epi64() {
+    const unsafe fn test_mm_mask_lzcnt_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_mask_lzcnt_epi64(a, 0, a);
         assert_eq_m128i(r, a);
@@ -1221,7 +1246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_maskz_lzcnt_epi64() {
+    const unsafe fn test_mm_maskz_lzcnt_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_maskz_lzcnt_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());

From a33d9275c6cbef001f6d950b9f6308a7c82235a7 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:24:24 +0530
Subject: [PATCH 064/326] Make `avx512dq` functions const

---
 crates/core_arch/src/x86/avx512dq.rs | 874 ++++++++++++++++-----------
 1 file changed, 536 insertions(+), 338 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512dq.rs b/crates/core_arch/src/x86/avx512dq.rs
index a691687502..4ab5880c55 100644
--- a/crates/core_arch/src/x86/avx512dq.rs
+++ b/crates/core_arch/src/x86/avx512dq.rs
@@ -15,7 +15,8 @@ use crate::{
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_and_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_and_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let and = _mm_and_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, and, src.as_f64x2()))
@@ -30,7 +31,8 @@ pub fn _mm_mask_and_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_and_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_and_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let and = _mm_and_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, and, f64x2::ZERO))
@@ -46,7 +48,8 @@ pub fn _mm_maskz_and_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_and_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_and_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let and = _mm256_and_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, and, src.as_f64x4()))
@@ -61,7 +64,8 @@ pub fn _mm256_mask_and_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) ->
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_and_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_and_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let and = _mm256_and_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, and, f64x4::ZERO))
@@ -76,7 +80,8 @@ pub fn _mm256_maskz_and_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandp))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_and_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_and_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_and(transmute::<_, u64x8>(a), transmute::<_, u64x8>(b))) }
 }
 
@@ -89,7 +94,8 @@ pub fn _mm512_and_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_and_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_and_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let and = _mm512_and_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, and, src.as_f64x8()))
@@ -104,7 +110,8 @@ pub fn _mm512_mask_and_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) ->
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_and_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_and_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let and = _mm512_and_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, and, f64x8::ZERO))
@@ -120,7 +127,8 @@ pub fn _mm512_maskz_and_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_and_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_and_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let and = _mm_and_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, and, src.as_f32x4()))
@@ -135,7 +143,8 @@ pub fn _mm_mask_and_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_and_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_and_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let and = _mm_and_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, and, f32x4::ZERO))
@@ -151,7 +160,8 @@ pub fn _mm_maskz_and_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_and_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_and_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let and = _mm256_and_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, and, src.as_f32x8()))
@@ -166,7 +176,8 @@ pub fn _mm256_mask_and_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_and_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_and_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let and = _mm256_and_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, and, f32x8::ZERO))
@@ -181,7 +192,8 @@ pub fn _mm256_maskz_and_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_and_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_and_ps(a: __m512, b: __m512) -> __m512 {
     unsafe {
         transmute(simd_and(
             transmute::<_, u32x16>(a),
@@ -199,7 +211,8 @@ pub fn _mm512_and_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_and_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_and_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let and = _mm512_and_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, and, src.as_f32x16()))
@@ -214,7 +227,8 @@ pub fn _mm512_mask_and_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_and_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_and_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let and = _mm512_and_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, and, f32x16::ZERO))
@@ -232,7 +246,8 @@ pub fn _mm512_maskz_and_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_andnot_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_andnot_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let andnot = _mm_andnot_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, andnot, src.as_f64x2()))
@@ -248,7 +263,8 @@ pub fn _mm_mask_andnot_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) ->
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_andnot_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_andnot_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let andnot = _mm_andnot_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, andnot, f64x2::ZERO))
@@ -264,7 +280,8 @@ pub fn _mm_maskz_andnot_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_andnot_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_andnot_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let andnot = _mm256_andnot_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, andnot, src.as_f64x4()))
@@ -280,7 +297,8 @@ pub fn _mm256_mask_andnot_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d)
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_andnot_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_andnot_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let andnot = _mm256_andnot_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, andnot, f64x4::ZERO))
@@ -295,7 +313,8 @@ pub fn _mm256_maskz_andnot_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandnp))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_andnot_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_andnot_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { _mm512_and_pd(_mm512_xor_pd(a, transmute(_mm512_set1_epi64(-1))), b) }
 }
 
@@ -308,7 +327,8 @@ pub fn _mm512_andnot_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandnpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_andnot_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_andnot_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let andnot = _mm512_andnot_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, andnot, src.as_f64x8()))
@@ -324,7 +344,8 @@ pub fn _mm512_mask_andnot_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d)
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandnpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_andnot_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_andnot_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let andnot = _mm512_andnot_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, andnot, f64x8::ZERO))
@@ -340,7 +361,8 @@ pub fn _mm512_maskz_andnot_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_andnot_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_andnot_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let andnot = _mm_andnot_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, andnot, src.as_f32x4()))
@@ -356,7 +378,8 @@ pub fn _mm_mask_andnot_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_andnot_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_andnot_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let andnot = _mm_andnot_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, andnot, f32x4::ZERO))
@@ -372,7 +395,8 @@ pub fn _mm_maskz_andnot_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_andnot_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_andnot_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let andnot = _mm256_andnot_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, andnot, src.as_f32x8()))
@@ -388,7 +412,8 @@ pub fn _mm256_mask_andnot_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) ->
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_andnot_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_andnot_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let andnot = _mm256_andnot_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, andnot, f32x8::ZERO))
@@ -403,7 +428,8 @@ pub fn _mm256_maskz_andnot_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_andnot_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_andnot_ps(a: __m512, b: __m512) -> __m512 {
     unsafe { _mm512_and_ps(_mm512_xor_ps(a, transmute(_mm512_set1_epi32(-1))), b) }
 }
 
@@ -416,7 +442,8 @@ pub fn _mm512_andnot_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_andnot_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_andnot_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let andnot = _mm512_andnot_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, andnot, src.as_f32x16()))
@@ -432,7 +459,8 @@ pub fn _mm512_mask_andnot_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) ->
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vandnps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_andnot_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_andnot_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let andnot = _mm512_andnot_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, andnot, f32x16::ZERO))
@@ -450,7 +478,8 @@ pub fn _mm512_maskz_andnot_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_or_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_or_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let or = _mm_or_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, or, src.as_f64x2()))
@@ -465,7 +494,8 @@ pub fn _mm_mask_or_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m1
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_or_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_or_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let or = _mm_or_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, or, f64x2::ZERO))
@@ -481,7 +511,8 @@ pub fn _mm_maskz_or_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_or_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_or_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let or = _mm256_or_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, or, src.as_f64x4()))
@@ -496,7 +527,8 @@ pub fn _mm256_mask_or_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> _
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_or_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_or_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let or = _mm256_or_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, or, f64x4::ZERO))
@@ -511,7 +543,8 @@ pub fn _mm256_maskz_or_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vorp))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_or_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_or_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_or(transmute::<_, u64x8>(a), transmute::<_, u64x8>(b))) }
 }
 
@@ -524,7 +557,8 @@ pub fn _mm512_or_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_or_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_or_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let or = _mm512_or_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, or, src.as_f64x8()))
@@ -539,7 +573,8 @@ pub fn _mm512_mask_or_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> _
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_or_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_or_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let or = _mm512_or_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, or, f64x8::ZERO))
@@ -555,7 +590,8 @@ pub fn _mm512_maskz_or_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_or_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_or_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let or = _mm_or_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, or, src.as_f32x4()))
@@ -570,7 +606,8 @@ pub fn _mm_mask_or_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_or_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_or_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let or = _mm_or_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, or, f32x4::ZERO))
@@ -586,7 +623,8 @@ pub fn _mm_maskz_or_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_or_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_or_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let or = _mm256_or_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, or, src.as_f32x8()))
@@ -601,7 +639,8 @@ pub fn _mm256_mask_or_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m2
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_or_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_or_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let or = _mm256_or_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, or, f32x8::ZERO))
@@ -616,7 +655,8 @@ pub fn _mm256_maskz_or_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_or_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_or_ps(a: __m512, b: __m512) -> __m512 {
     unsafe {
         transmute(simd_or(
             transmute::<_, u32x16>(a),
@@ -634,7 +674,8 @@ pub fn _mm512_or_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_or_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_or_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let or = _mm512_or_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, or, src.as_f32x16()))
@@ -649,7 +690,8 @@ pub fn _mm512_mask_or_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_or_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_or_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let or = _mm512_or_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, or, f32x16::ZERO))
@@ -667,7 +709,8 @@ pub fn _mm512_maskz_or_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_xor_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_xor_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let xor = _mm_xor_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, xor, src.as_f64x2()))
@@ -682,7 +725,8 @@ pub fn _mm_mask_xor_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_xor_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_xor_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
     unsafe {
         let xor = _mm_xor_pd(a, b).as_f64x2();
         transmute(simd_select_bitmask(k, xor, f64x2::ZERO))
@@ -698,7 +742,8 @@ pub fn _mm_maskz_xor_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_xor_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_xor_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let xor = _mm256_xor_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, xor, src.as_f64x4()))
@@ -713,7 +758,8 @@ pub fn _mm256_mask_xor_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) ->
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_xor_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_xor_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
     unsafe {
         let xor = _mm256_xor_pd(a, b).as_f64x4();
         transmute(simd_select_bitmask(k, xor, f64x4::ZERO))
@@ -728,7 +774,8 @@ pub fn _mm256_maskz_xor_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vxorp))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_xor_pd(a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_xor_pd(a: __m512d, b: __m512d) -> __m512d {
     unsafe { transmute(simd_xor(transmute::<_, u64x8>(a), transmute::<_, u64x8>(b))) }
 }
 
@@ -741,7 +788,8 @@ pub fn _mm512_xor_pd(a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vxorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_xor_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_xor_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let xor = _mm512_xor_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, xor, src.as_f64x8()))
@@ -756,7 +804,8 @@ pub fn _mm512_mask_xor_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) ->
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vxorpd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_xor_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_xor_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
     unsafe {
         let xor = _mm512_xor_pd(a, b).as_f64x8();
         transmute(simd_select_bitmask(k, xor, f64x8::ZERO))
@@ -772,7 +821,8 @@ pub fn _mm512_maskz_xor_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_xor_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_xor_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let xor = _mm_xor_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, xor, src.as_f32x4()))
@@ -787,7 +837,8 @@ pub fn _mm_mask_xor_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_xor_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_xor_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
     unsafe {
         let xor = _mm_xor_ps(a, b).as_f32x4();
         transmute(simd_select_bitmask(k, xor, f32x4::ZERO))
@@ -803,7 +854,8 @@ pub fn _mm_maskz_xor_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_xor_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_xor_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let xor = _mm256_xor_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, xor, src.as_f32x8()))
@@ -818,7 +870,8 @@ pub fn _mm256_mask_xor_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_xor_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_xor_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
     unsafe {
         let xor = _mm256_xor_ps(a, b).as_f32x8();
         transmute(simd_select_bitmask(k, xor, f32x8::ZERO))
@@ -833,7 +886,8 @@ pub fn _mm256_maskz_xor_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_xor_ps(a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_xor_ps(a: __m512, b: __m512) -> __m512 {
     unsafe {
         transmute(simd_xor(
             transmute::<_, u32x16>(a),
@@ -851,7 +905,8 @@ pub fn _mm512_xor_ps(a: __m512, b: __m512) -> __m512 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_xor_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_xor_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let xor = _mm512_xor_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, xor, src.as_f32x16()))
@@ -866,7 +921,8 @@ pub fn _mm512_mask_xor_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vxorps))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_xor_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_xor_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
     unsafe {
         let xor = _mm512_xor_ps(a, b).as_f32x16();
         transmute(simd_select_bitmask(k, xor, f32x16::ZERO))
@@ -882,7 +938,8 @@ pub fn _mm512_maskz_xor_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_broadcast_f32x2(a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_f32x2(a: __m128) -> __m256 {
     unsafe {
         let b: f32x8 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1]);
         transmute(b)
@@ -897,7 +954,8 @@ pub fn _mm256_broadcast_f32x2(a: __m128) -> __m256 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vbroadcastf32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_broadcast_f32x2(src: __m256, k: __mmask8, a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcast_f32x2(src: __m256, k: __mmask8, a: __m128) -> __m256 {
     unsafe {
         let b = _mm256_broadcast_f32x2(a).as_f32x8();
         transmute(simd_select_bitmask(k, b, src.as_f32x8()))
@@ -912,7 +970,8 @@ pub fn _mm256_mask_broadcast_f32x2(src: __m256, k: __mmask8, a: __m128) -> __m25
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vbroadcastf32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_broadcast_f32x2(k: __mmask8, a: __m128) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcast_f32x2(k: __mmask8, a: __m128) -> __m256 {
     unsafe {
         let b = _mm256_broadcast_f32x2(a).as_f32x8();
         transmute(simd_select_bitmask(k, b, f32x8::ZERO))
@@ -926,7 +985,8 @@ pub fn _mm256_maskz_broadcast_f32x2(k: __mmask8, a: __m128) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_f32x2(a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_f32x2(a: __m128) -> __m512 {
     unsafe {
         let b: f32x16 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]);
         transmute(b)
@@ -941,7 +1001,8 @@ pub fn _mm512_broadcast_f32x2(a: __m128) -> __m512 {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vbroadcastf32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_f32x2(src: __m512, k: __mmask16, a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_f32x2(src: __m512, k: __mmask16, a: __m128) -> __m512 {
     unsafe {
         let b = _mm512_broadcast_f32x2(a).as_f32x16();
         transmute(simd_select_bitmask(k, b, src.as_f32x16()))
@@ -956,7 +1017,8 @@ pub fn _mm512_mask_broadcast_f32x2(src: __m512, k: __mmask16, a: __m128) -> __m5
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vbroadcastf32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_f32x2(k: __mmask16, a: __m128) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_f32x2(k: __mmask16, a: __m128) -> __m512 {
     unsafe {
         let b = _mm512_broadcast_f32x2(a).as_f32x16();
         transmute(simd_select_bitmask(k, b, f32x16::ZERO))
@@ -970,7 +1032,8 @@ pub fn _mm512_maskz_broadcast_f32x2(k: __mmask16, a: __m128) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_f32x8(a: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_f32x8(a: __m256) -> __m512 {
     unsafe {
         let b: f32x16 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7]);
         transmute(b)
@@ -984,7 +1047,8 @@ pub fn _mm512_broadcast_f32x8(a: __m256) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_f32x8(src: __m512, k: __mmask16, a: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_f32x8(src: __m512, k: __mmask16, a: __m256) -> __m512 {
     unsafe {
         let b = _mm512_broadcast_f32x8(a).as_f32x16();
         transmute(simd_select_bitmask(k, b, src.as_f32x16()))
@@ -998,7 +1062,8 @@ pub fn _mm512_mask_broadcast_f32x8(src: __m512, k: __mmask16, a: __m256) -> __m5
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_f32x8(k: __mmask16, a: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_f32x8(k: __mmask16, a: __m256) -> __m512 {
     unsafe {
         let b = _mm512_broadcast_f32x8(a).as_f32x16();
         transmute(simd_select_bitmask(k, b, f32x16::ZERO))
@@ -1012,7 +1077,8 @@ pub fn _mm512_maskz_broadcast_f32x8(k: __mmask16, a: __m256) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_broadcast_f64x2(a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_f64x2(a: __m128d) -> __m256d {
     unsafe {
         let b: f64x4 = simd_shuffle!(a, a, [0, 1, 0, 1]);
         transmute(b)
@@ -1026,7 +1092,8 @@ pub fn _mm256_broadcast_f64x2(a: __m128d) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_broadcast_f64x2(src: __m256d, k: __mmask8, a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcast_f64x2(src: __m256d, k: __mmask8, a: __m128d) -> __m256d {
     unsafe {
         let b = _mm256_broadcast_f64x2(a).as_f64x4();
         transmute(simd_select_bitmask(k, b, src.as_f64x4()))
@@ -1040,7 +1107,8 @@ pub fn _mm256_mask_broadcast_f64x2(src: __m256d, k: __mmask8, a: __m128d) -> __m
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m256d {
     unsafe {
         let b = _mm256_broadcast_f64x2(a).as_f64x4();
         transmute(simd_select_bitmask(k, b, f64x4::ZERO))
@@ -1054,7 +1122,8 @@ pub fn _mm256_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_f64x2(a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_f64x2(a: __m128d) -> __m512d {
     unsafe {
         let b: f64x8 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1]);
         transmute(b)
@@ -1068,7 +1137,8 @@ pub fn _mm512_broadcast_f64x2(a: __m128d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_f64x2(src: __m512d, k: __mmask8, a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_f64x2(src: __m512d, k: __mmask8, a: __m128d) -> __m512d {
     unsafe {
         let b = _mm512_broadcast_f64x2(a).as_f64x8();
         transmute(simd_select_bitmask(k, b, src.as_f64x8()))
@@ -1082,7 +1152,8 @@ pub fn _mm512_mask_broadcast_f64x2(src: __m512d, k: __mmask8, a: __m128d) -> __m
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m512d {
     unsafe {
         let b = _mm512_broadcast_f64x2(a).as_f64x8();
         transmute(simd_select_bitmask(k, b, f64x8::ZERO))
@@ -1095,7 +1166,8 @@ pub fn _mm512_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_broadcast_i32x2(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_broadcast_i32x2(a: __m128i) -> __m128i {
     unsafe {
         let a = a.as_i32x4();
         let b: i32x4 = simd_shuffle!(a, a, [0, 1, 0, 1]);
@@ -1111,7 +1183,8 @@ pub fn _mm_broadcast_i32x2(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vbroadcasti32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_broadcast_i32x2(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_broadcast_i32x2(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let b = _mm_broadcast_i32x2(a).as_i32x4();
         transmute(simd_select_bitmask(k, b, src.as_i32x4()))
@@ -1126,7 +1199,8 @@ pub fn _mm_mask_broadcast_i32x2(src: __m128i, k: __mmask8, a: __m128i) -> __m128
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vbroadcasti32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         let b = _mm_broadcast_i32x2(a).as_i32x4();
         transmute(simd_select_bitmask(k, b, i32x4::ZERO))
@@ -1139,7 +1213,8 @@ pub fn _mm_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_broadcast_i32x2(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_i32x2(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i32x4();
         let b: i32x8 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1]);
@@ -1155,7 +1230,8 @@ pub fn _mm256_broadcast_i32x2(a: __m128i) -> __m256i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vbroadcasti32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_broadcast_i32x2(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcast_i32x2(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let b = _mm256_broadcast_i32x2(a).as_i32x8();
         transmute(simd_select_bitmask(k, b, src.as_i32x8()))
@@ -1170,7 +1246,8 @@ pub fn _mm256_mask_broadcast_i32x2(src: __m256i, k: __mmask8, a: __m128i) -> __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vbroadcasti32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let b = _mm256_broadcast_i32x2(a).as_i32x8();
         transmute(simd_select_bitmask(k, b, i32x8::ZERO))
@@ -1183,7 +1260,8 @@ pub fn _mm256_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_i32x2(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_i32x2(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_i32x4();
         let b: i32x16 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]);
@@ -1199,7 +1277,8 @@ pub fn _mm512_broadcast_i32x2(a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vbroadcasti32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_i32x2(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_i32x2(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let b = _mm512_broadcast_i32x2(a).as_i32x16();
         transmute(simd_select_bitmask(k, b, src.as_i32x16()))
@@ -1214,7 +1293,8 @@ pub fn _mm512_mask_broadcast_i32x2(src: __m512i, k: __mmask16, a: __m128i) -> __
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vbroadcasti32x2))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_i32x2(k: __mmask16, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_i32x2(k: __mmask16, a: __m128i) -> __m512i {
     unsafe {
         let b = _mm512_broadcast_i32x2(a).as_i32x16();
         transmute(simd_select_bitmask(k, b, i32x16::ZERO))
@@ -1227,7 +1307,8 @@ pub fn _mm512_maskz_broadcast_i32x2(k: __mmask16, a: __m128i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_i32x8(a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_i32x8(a: __m256i) -> __m512i {
     unsafe {
         let a = a.as_i32x8();
         let b: i32x16 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7]);
@@ -1242,7 +1323,8 @@ pub fn _mm512_broadcast_i32x8(a: __m256i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_i32x8(src: __m512i, k: __mmask16, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_i32x8(src: __m512i, k: __mmask16, a: __m256i) -> __m512i {
     unsafe {
         let b = _mm512_broadcast_i32x8(a).as_i32x16();
         transmute(simd_select_bitmask(k, b, src.as_i32x16()))
@@ -1256,7 +1338,8 @@ pub fn _mm512_mask_broadcast_i32x8(src: __m512i, k: __mmask16, a: __m256i) -> __
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_i32x8(k: __mmask16, a: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_i32x8(k: __mmask16, a: __m256i) -> __m512i {
     unsafe {
         let b = _mm512_broadcast_i32x8(a).as_i32x16();
         transmute(simd_select_bitmask(k, b, i32x16::ZERO))
@@ -1269,7 +1352,8 @@ pub fn _mm512_maskz_broadcast_i32x8(k: __mmask16, a: __m256i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_broadcast_i64x2(a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_broadcast_i64x2(a: __m128i) -> __m256i {
     unsafe {
         let a = a.as_i64x2();
         let b: i64x4 = simd_shuffle!(a, a, [0, 1, 0, 1]);
@@ -1284,7 +1368,8 @@ pub fn _mm256_broadcast_i64x2(a: __m128i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_broadcast_i64x2(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_broadcast_i64x2(src: __m256i, k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let b = _mm256_broadcast_i64x2(a).as_i64x4();
         transmute(simd_select_bitmask(k, b, src.as_i64x4()))
@@ -1298,7 +1383,8 @@ pub fn _mm256_mask_broadcast_i64x2(src: __m256i, k: __mmask8, a: __m128i) -> __m
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m256i {
     unsafe {
         let b = _mm256_broadcast_i64x2(a).as_i64x4();
         transmute(simd_select_bitmask(k, b, i64x4::ZERO))
@@ -1311,7 +1397,8 @@ pub fn _mm256_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_broadcast_i64x2(a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_broadcast_i64x2(a: __m128i) -> __m512i {
     unsafe {
         let a = a.as_i64x2();
         let b: i64x8 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1]);
@@ -1326,7 +1413,8 @@ pub fn _mm512_broadcast_i64x2(a: __m128i) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_broadcast_i64x2(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_broadcast_i64x2(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let b = _mm512_broadcast_i64x2(a).as_i64x8();
         transmute(simd_select_bitmask(k, b, src.as_i64x8()))
@@ -1340,7 +1428,8 @@ pub fn _mm512_mask_broadcast_i64x2(src: __m512i, k: __mmask8, a: __m128i) -> __m
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m512i {
     unsafe {
         let b = _mm512_broadcast_i64x2(a).as_i64x8();
         transmute(simd_select_bitmask(k, b, i64x8::ZERO))
@@ -1357,7 +1446,8 @@ pub fn _mm512_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m512i {
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_extractf32x8_ps<const IMM8: i32>(a: __m512) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extractf32x8_ps<const IMM8: i32>(a: __m512) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         match IMM8 & 1 {
@@ -1377,7 +1467,12 @@ pub fn _mm512_extractf32x8_ps<const IMM8: i32>(a: __m512) -> __m256 {
 #[cfg_attr(test, assert_instr(vextractf32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_extractf32x8_ps<const IMM8: i32>(src: __m256, k: __mmask8, a: __m512) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extractf32x8_ps<const IMM8: i32>(
+    src: __m256,
+    k: __mmask8,
+    a: __m512,
+) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm512_extractf32x8_ps::<IMM8>(a);
@@ -1395,7 +1490,8 @@ pub fn _mm512_mask_extractf32x8_ps<const IMM8: i32>(src: __m256, k: __mmask8, a:
 #[cfg_attr(test, assert_instr(vextractf32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_extractf32x8_ps<const IMM8: i32>(k: __mmask8, a: __m512) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extractf32x8_ps<const IMM8: i32>(k: __mmask8, a: __m512) -> __m256 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm512_extractf32x8_ps::<IMM8>(a);
@@ -1411,7 +1507,8 @@ pub fn _mm512_maskz_extractf32x8_ps<const IMM8: i32>(k: __mmask8, a: __m512) ->
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_extractf64x2_pd<const IMM8: i32>(a: __m256d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extractf64x2_pd<const IMM8: i32>(a: __m256d) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         match IMM8 & 1 {
@@ -1431,7 +1528,8 @@ pub fn _mm256_extractf64x2_pd<const IMM8: i32>(a: __m256d) -> __m128d {
 #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_extractf64x2_pd<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_extractf64x2_pd<const IMM8: i32>(
     src: __m128d,
     k: __mmask8,
     a: __m256d,
@@ -1453,7 +1551,8 @@ pub fn _mm256_mask_extractf64x2_pd<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_extractf64x2_pd<const IMM8: i32>(k: __mmask8, a: __m256d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_extractf64x2_pd<const IMM8: i32>(k: __mmask8, a: __m256d) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm256_extractf64x2_pd::<IMM8>(a);
@@ -1469,7 +1568,8 @@ pub fn _mm256_maskz_extractf64x2_pd<const IMM8: i32>(k: __mmask8, a: __m256d) ->
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_extractf64x2_pd<const IMM8: i32>(a: __m512d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extractf64x2_pd<const IMM8: i32>(a: __m512d) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         match IMM8 & 3 {
@@ -1491,7 +1591,8 @@ pub fn _mm512_extractf64x2_pd<const IMM8: i32>(a: __m512d) -> __m128d {
 #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_extractf64x2_pd<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extractf64x2_pd<const IMM8: i32>(
     src: __m128d,
     k: __mmask8,
     a: __m512d,
@@ -1513,7 +1614,8 @@ pub fn _mm512_mask_extractf64x2_pd<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_extractf64x2_pd<const IMM8: i32>(k: __mmask8, a: __m512d) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extractf64x2_pd<const IMM8: i32>(k: __mmask8, a: __m512d) -> __m128d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let b = _mm512_extractf64x2_pd::<IMM8>(a).as_f64x2();
@@ -1529,7 +1631,8 @@ pub fn _mm512_maskz_extractf64x2_pd<const IMM8: i32>(k: __mmask8, a: __m512d) ->
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_extracti32x8_epi32<const IMM8: i32>(a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extracti32x8_epi32<const IMM8: i32>(a: __m512i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let a = a.as_i32x16();
@@ -1550,7 +1653,8 @@ pub fn _mm512_extracti32x8_epi32<const IMM8: i32>(a: __m512i) -> __m256i {
 #[cfg_attr(test, assert_instr(vextracti32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_extracti32x8_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extracti32x8_epi32<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m512i,
@@ -1571,7 +1675,8 @@ pub fn _mm512_mask_extracti32x8_epi32<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vextracti32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_extracti32x8_epi32<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extracti32x8_epi32<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm512_extracti32x8_epi32::<IMM8>(a).as_i32x8();
@@ -1587,7 +1692,8 @@ pub fn _mm512_maskz_extracti32x8_epi32<const IMM8: i32>(k: __mmask8, a: __m512i)
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_extracti64x2_epi64<const IMM8: i32>(a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_extracti64x2_epi64<const IMM8: i32>(a: __m256i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let a = a.as_i64x4();
@@ -1607,7 +1713,8 @@ pub fn _mm256_extracti64x2_epi64<const IMM8: i32>(a: __m256i) -> __m128i {
 #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_extracti64x2_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_extracti64x2_epi64<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m256i,
@@ -1628,7 +1735,8 @@ pub fn _mm256_mask_extracti64x2_epi64<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_extracti64x2_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_extracti64x2_epi64<const IMM8: i32>(k: __mmask8, a: __m256i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm256_extracti64x2_epi64::<IMM8>(a).as_i64x2();
@@ -1644,7 +1752,8 @@ pub fn _mm256_maskz_extracti64x2_epi64<const IMM8: i32>(k: __mmask8, a: __m256i)
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_extracti64x2_epi64<const IMM8: i32>(a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_extracti64x2_epi64<const IMM8: i32>(a: __m512i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let a = a.as_i64x8();
@@ -1666,7 +1775,8 @@ pub fn _mm512_extracti64x2_epi64<const IMM8: i32>(a: __m512i) -> __m128i {
 #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_extracti64x2_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_extracti64x2_epi64<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m512i,
@@ -1687,7 +1797,8 @@ pub fn _mm512_mask_extracti64x2_epi64<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_extracti64x2_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_extracti64x2_epi64<const IMM8: i32>(k: __mmask8, a: __m512i) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let b = _mm512_extracti64x2_epi64::<IMM8>(a).as_i64x2();
@@ -1705,7 +1816,8 @@ pub fn _mm512_maskz_extracti64x2_epi64<const IMM8: i32>(k: __mmask8, a: __m512i)
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_insertf32x8<const IMM8: i32>(a: __m512, b: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_insertf32x8<const IMM8: i32>(a: __m512, b: __m256) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm512_castps256_ps512(b);
@@ -1738,7 +1850,8 @@ pub fn _mm512_insertf32x8<const IMM8: i32>(a: __m512, b: __m256) -> __m512 {
 #[cfg_attr(test, assert_instr(vinsertf32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_insertf32x8<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_insertf32x8<const IMM8: i32>(
     src: __m512,
     k: __mmask16,
     a: __m512,
@@ -1761,7 +1874,12 @@ pub fn _mm512_mask_insertf32x8<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vinsertf32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_insertf32x8<const IMM8: i32>(k: __mmask16, a: __m512, b: __m256) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_insertf32x8<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512,
+    b: __m256,
+) -> __m512 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let c = _mm512_insertf32x8::<IMM8>(a, b).as_f32x16();
@@ -1777,7 +1895,8 @@ pub fn _mm512_maskz_insertf32x8<const IMM8: i32>(k: __mmask16, a: __m512, b: __m
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_insertf64x2<const IMM8: i32>(a: __m256d, b: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_insertf64x2<const IMM8: i32>(a: __m256d, b: __m128d) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let b = _mm256_castpd128_pd256(b);
@@ -1798,7 +1917,8 @@ pub fn _mm256_insertf64x2<const IMM8: i32>(a: __m256d, b: __m128d) -> __m256d {
 #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_insertf64x2<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_insertf64x2<const IMM8: i32>(
     src: __m256d,
     k: __mmask8,
     a: __m256d,
@@ -1821,7 +1941,12 @@ pub fn _mm256_mask_insertf64x2<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_insertf64x2<const IMM8: i32>(k: __mmask8, a: __m256d, b: __m128d) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_insertf64x2<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256d,
+    b: __m128d,
+) -> __m256d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let c = _mm256_insertf64x2::<IMM8>(a, b).as_f64x4();
@@ -1837,7 +1962,8 @@ pub fn _mm256_maskz_insertf64x2<const IMM8: i32>(k: __mmask8, a: __m256d, b: __m
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_insertf64x2<const IMM8: i32>(a: __m512d, b: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_insertf64x2<const IMM8: i32>(a: __m512d, b: __m128d) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let b = _mm512_castpd128_pd512(b);
@@ -1860,7 +1986,8 @@ pub fn _mm512_insertf64x2<const IMM8: i32>(a: __m512d, b: __m128d) -> __m512d {
 #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(4)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_insertf64x2<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_insertf64x2<const IMM8: i32>(
     src: __m512d,
     k: __mmask8,
     a: __m512d,
@@ -1883,7 +2010,12 @@ pub fn _mm512_mask_insertf64x2<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_insertf64x2<const IMM8: i32>(k: __mmask8, a: __m512d, b: __m128d) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_insertf64x2<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512d,
+    b: __m128d,
+) -> __m512d {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let c = _mm512_insertf64x2::<IMM8>(a, b).as_f64x8();
@@ -1899,7 +2031,8 @@ pub fn _mm512_maskz_insertf64x2<const IMM8: i32>(k: __mmask8, a: __m512d, b: __m
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_inserti32x8<const IMM8: i32>(a: __m512i, b: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_inserti32x8<const IMM8: i32>(a: __m512i, b: __m256i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let a = a.as_i32x16();
@@ -1934,7 +2067,8 @@ pub fn _mm512_inserti32x8<const IMM8: i32>(a: __m512i, b: __m256i) -> __m512i {
 #[cfg_attr(test, assert_instr(vinserti32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_inserti32x8<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_inserti32x8<const IMM8: i32>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -1957,7 +2091,12 @@ pub fn _mm512_mask_inserti32x8<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vinserti32x8, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_inserti32x8<const IMM8: i32>(k: __mmask16, a: __m512i, b: __m256i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_inserti32x8<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512i,
+    b: __m256i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let c = _mm512_inserti32x8::<IMM8>(a, b).as_i32x16();
@@ -1973,7 +2112,8 @@ pub fn _mm512_maskz_inserti32x8<const IMM8: i32>(k: __mmask16, a: __m512i, b: __
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_inserti64x2<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_inserti64x2<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let a = a.as_i64x4();
@@ -1995,7 +2135,8 @@ pub fn _mm256_inserti64x2<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
 #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(4)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_inserti64x2<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_inserti64x2<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -2018,7 +2159,12 @@ pub fn _mm256_mask_inserti64x2<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_inserti64x2<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m128i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_inserti64x2<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m128i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 1);
         let c = _mm256_inserti64x2::<IMM8>(a, b).as_i64x4();
@@ -2034,7 +2180,8 @@ pub fn _mm256_maskz_inserti64x2<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_inserti64x2<const IMM8: i32>(a: __m512i, b: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_inserti64x2<const IMM8: i32>(a: __m512i, b: __m128i) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let a = a.as_i64x8();
@@ -2058,7 +2205,8 @@ pub fn _mm512_inserti64x2<const IMM8: i32>(a: __m512i, b: __m128i) -> __m512i {
 #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(4)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_inserti64x2<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_inserti64x2<const IMM8: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -2081,7 +2229,12 @@ pub fn _mm512_mask_inserti64x2<const IMM8: i32>(
 #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 3))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_inserti64x2<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m128i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_inserti64x2<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512i,
+    b: __m128i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 2);
         let c = _mm512_inserti64x2::<IMM8>(a, b).as_i64x8();
@@ -4333,7 +4486,8 @@ pub fn _mm512_maskz_cvttps_epu64(k: __mmask8, a: __m256) -> __m512i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mullo_epi64(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mullo_epi64(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(simd_mul(a.as_i64x2(), b.as_i64x2())) }
 }
 
@@ -4346,7 +4500,8 @@ pub fn _mm_mullo_epi64(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_mask_mullo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mullo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let b = _mm_mullo_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, b, src.as_i64x2()))
@@ -4362,7 +4517,8 @@ pub fn _mm_mask_mullo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_maskz_mullo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mullo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let b = _mm_mullo_epi64(a, b).as_i64x2();
         transmute(simd_select_bitmask(k, b, i64x2::ZERO))
@@ -4377,7 +4533,8 @@ pub fn _mm_maskz_mullo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mullo_epi64(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mullo_epi64(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_mul(a.as_i64x4(), b.as_i64x4())) }
 }
 
@@ -4390,7 +4547,8 @@ pub fn _mm256_mullo_epi64(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_mask_mullo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mullo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let b = _mm256_mullo_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, b, src.as_i64x4()))
@@ -4406,7 +4564,8 @@ pub fn _mm256_mask_mullo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_maskz_mullo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mullo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let b = _mm256_mullo_epi64(a, b).as_i64x4();
         transmute(simd_select_bitmask(k, b, i64x4::ZERO))
@@ -4421,7 +4580,8 @@ pub fn _mm256_maskz_mullo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mullo_epi64(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mullo_epi64(a: __m512i, b: __m512i) -> __m512i {
     unsafe { transmute(simd_mul(a.as_i64x8(), b.as_i64x8())) }
 }
 
@@ -4434,7 +4594,8 @@ pub fn _mm512_mullo_epi64(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_mask_mullo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mullo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let b = _mm512_mullo_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, b, src.as_i64x8()))
@@ -4450,7 +4611,8 @@ pub fn _mm512_mask_mullo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vpmullq))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_maskz_mullo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mullo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let b = _mm512_mullo_epi64(a, b).as_i64x8();
         transmute(simd_select_bitmask(k, b, i64x8::ZERO))
@@ -4465,7 +4627,8 @@ pub fn _mm512_maskz_mullo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtmask8_u32(a: __mmask8) -> u32 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtmask8_u32(a: __mmask8) -> u32 {
     a as u32
 }
 
@@ -4475,7 +4638,8 @@ pub fn _cvtmask8_u32(a: __mmask8) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _cvtu32_mask8(a: u32) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _cvtu32_mask8(a: u32) -> __mmask8 {
     a as __mmask8
 }
 
@@ -4485,7 +4649,8 @@ pub fn _cvtu32_mask8(a: u32) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
     a.wrapping_add(b)
 }
 
@@ -4495,7 +4660,8 @@ pub fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kadd_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kadd_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
     a.wrapping_add(b)
 }
 
@@ -4505,7 +4671,8 @@ pub fn _kadd_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kand_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kand_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
     a & b
 }
 
@@ -4515,7 +4682,8 @@ pub fn _kand_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kandn_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kandn_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
     _knot_mask8(a) & b
 }
 
@@ -4525,7 +4693,8 @@ pub fn _kandn_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _knot_mask8(a: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _knot_mask8(a: __mmask8) -> __mmask8 {
     a ^ 0b11111111
 }
 
@@ -4535,7 +4704,8 @@ pub fn _knot_mask8(a: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
     a | b
 }
 
@@ -4545,7 +4715,8 @@ pub fn _kor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kxnor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxnor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
     _knot_mask8(_kxor_mask8(a, b))
 }
 
@@ -4555,7 +4726,8 @@ pub fn _kxnor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kxor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kxor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
     a ^ b
 }
 
@@ -4566,7 +4738,8 @@ pub fn _kxor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _kortest_mask8_u8(a: __mmask8, b: __mmask8, all_ones: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _kortest_mask8_u8(a: __mmask8, b: __mmask8, all_ones: *mut u8) -> u8 {
     let tmp = _kor_mask8(a, b);
     *all_ones = (tmp == 0xff) as u8;
     (tmp == 0) as u8
@@ -4579,7 +4752,8 @@ pub unsafe fn _kortest_mask8_u8(a: __mmask8, b: __mmask8, all_ones: *mut u8) ->
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
     (_kor_mask8(a, b) == 0xff) as u8
 }
 
@@ -4590,7 +4764,8 @@ pub fn _kortestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kortestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kortestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
     (_kor_mask8(a, b) == 0) as u8
 }
 
@@ -4601,7 +4776,8 @@ pub fn _kortestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftli_mask8<const COUNT: u32>(a: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftli_mask8<const COUNT: u32>(a: __mmask8) -> __mmask8 {
     a.unbounded_shl(COUNT)
 }
 
@@ -4612,7 +4788,8 @@ pub fn _kshiftli_mask8<const COUNT: u32>(a: __mmask8) -> __mmask8 {
 #[target_feature(enable = "avx512dq")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _kshiftri_mask8<const COUNT: u32>(a: __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _kshiftri_mask8<const COUNT: u32>(a: __mmask8) -> __mmask8 {
     a.unbounded_shr(COUNT)
 }
 
@@ -4624,7 +4801,8 @@ pub fn _kshiftri_mask8<const COUNT: u32>(a: __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _ktest_mask16_u8(a: __mmask16, b: __mmask16, and_not: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _ktest_mask16_u8(a: __mmask16, b: __mmask16, and_not: *mut u8) -> u8 {
     *and_not = (_kandn_mask16(a, b) == 0) as u8;
     (_kand_mask16(a, b) == 0) as u8
 }
@@ -4637,7 +4815,8 @@ pub unsafe fn _ktest_mask16_u8(a: __mmask16, b: __mmask16, and_not: *mut u8) ->
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _ktest_mask8_u8(a: __mmask8, b: __mmask8, and_not: *mut u8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _ktest_mask8_u8(a: __mmask8, b: __mmask8, and_not: *mut u8) -> u8 {
     *and_not = (_kandn_mask8(a, b) == 0) as u8;
     (_kand_mask8(a, b) == 0) as u8
 }
@@ -4649,7 +4828,8 @@ pub unsafe fn _ktest_mask8_u8(a: __mmask8, b: __mmask8, and_not: *mut u8) -> u8
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
     (_kandn_mask16(a, b) == 0) as u8
 }
 
@@ -4660,7 +4840,8 @@ pub fn _ktestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
     (_kandn_mask8(a, b) == 0) as u8
 }
 
@@ -4671,7 +4852,8 @@ pub fn _ktestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
     (_kand_mask16(a, b) == 0) as u8
 }
 
@@ -4682,7 +4864,8 @@ pub fn _ktestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _ktestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _ktestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
     (_kand_mask8(a, b) == 0) as u8
 }
 
@@ -4692,7 +4875,8 @@ pub fn _ktestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _load_mask8(mem_addr: *const __mmask8) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _load_mask8(mem_addr: *const __mmask8) -> __mmask8 {
     *mem_addr
 }
 
@@ -4702,7 +4886,8 @@ pub unsafe fn _load_mask8(mem_addr: *const __mmask8) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub unsafe fn _store_mask8(mem_addr: *mut __mmask8, a: __mmask8) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _store_mask8(mem_addr: *mut __mmask8, a: __mmask8) {
     *mem_addr = a;
 }
 
@@ -4713,7 +4898,8 @@ pub unsafe fn _store_mask8(mem_addr: *mut __mmask8, a: __mmask8) {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_movepi32_mask(a: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movepi32_mask(a: __m128i) -> __mmask8 {
     let zero = _mm_setzero_si128();
     _mm_cmplt_epi32_mask(a, zero)
 }
@@ -4725,7 +4911,8 @@ pub fn _mm_movepi32_mask(a: __m128i) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_movepi32_mask(a: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movepi32_mask(a: __m256i) -> __mmask8 {
     let zero = _mm256_setzero_si256();
     _mm256_cmplt_epi32_mask(a, zero)
 }
@@ -4737,7 +4924,8 @@ pub fn _mm256_movepi32_mask(a: __m256i) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_movepi32_mask(a: __m512i) -> __mmask16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movepi32_mask(a: __m512i) -> __mmask16 {
     let zero = _mm512_setzero_si512();
     _mm512_cmplt_epi32_mask(a, zero)
 }
@@ -4749,7 +4937,8 @@ pub fn _mm512_movepi32_mask(a: __m512i) -> __mmask16 {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_movepi64_mask(a: __m128i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movepi64_mask(a: __m128i) -> __mmask8 {
     let zero = _mm_setzero_si128();
     _mm_cmplt_epi64_mask(a, zero)
 }
@@ -4761,7 +4950,8 @@ pub fn _mm_movepi64_mask(a: __m128i) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_movepi64_mask(a: __m256i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movepi64_mask(a: __m256i) -> __mmask8 {
     let zero = _mm256_setzero_si256();
     _mm256_cmplt_epi64_mask(a, zero)
 }
@@ -4773,7 +4963,8 @@ pub fn _mm256_movepi64_mask(a: __m256i) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512dq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_movepi64_mask(a: __m512i) -> __mmask8 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movepi64_mask(a: __m512i) -> __mmask8 {
     let zero = _mm512_setzero_si512();
     _mm512_cmplt_epi64_mask(a, zero)
 }
@@ -4786,7 +4977,8 @@ pub fn _mm512_movepi64_mask(a: __m512i) -> __mmask8 {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmovm2d))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_movm_epi32(k: __mmask8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movm_epi32(k: __mmask8) -> __m128i {
     let ones = _mm_set1_epi32(-1);
     _mm_maskz_mov_epi32(k, ones)
 }
@@ -4799,7 +4991,8 @@ pub fn _mm_movm_epi32(k: __mmask8) -> __m128i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmovm2d))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_movm_epi32(k: __mmask8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movm_epi32(k: __mmask8) -> __m256i {
     let ones = _mm256_set1_epi32(-1);
     _mm256_maskz_mov_epi32(k, ones)
 }
@@ -4812,7 +5005,8 @@ pub fn _mm256_movm_epi32(k: __mmask8) -> __m256i {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vpmovm2d))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_movm_epi32(k: __mmask16) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movm_epi32(k: __mmask16) -> __m512i {
     let ones = _mm512_set1_epi32(-1);
     _mm512_maskz_mov_epi32(k, ones)
 }
@@ -4825,7 +5019,8 @@ pub fn _mm512_movm_epi32(k: __mmask16) -> __m512i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmovm2q))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm_movm_epi64(k: __mmask8) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_movm_epi64(k: __mmask8) -> __m128i {
     let ones = _mm_set1_epi64x(-1);
     _mm_maskz_mov_epi64(k, ones)
 }
@@ -4838,7 +5033,8 @@ pub fn _mm_movm_epi64(k: __mmask8) -> __m128i {
 #[target_feature(enable = "avx512dq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpmovm2q))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm256_movm_epi64(k: __mmask8) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_movm_epi64(k: __mmask8) -> __m256i {
     let ones = _mm256_set1_epi64x(-1);
     _mm256_maskz_mov_epi64(k, ones)
 }
@@ -4851,7 +5047,8 @@ pub fn _mm256_movm_epi64(k: __mmask8) -> __m256i {
 #[target_feature(enable = "avx512dq")]
 #[cfg_attr(test, assert_instr(vpmovm2q))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
-pub fn _mm512_movm_epi64(k: __mmask8) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_movm_epi64(k: __mmask8) -> __m512i {
     let ones = _mm512_set1_epi64(-1);
     _mm512_maskz_mov_epi64(k, ones)
 }
@@ -7203,6 +7400,7 @@ unsafe extern "C" {
 #[cfg(test)]
 mod tests {
     use super::*;
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
@@ -7226,7 +7424,7 @@ mod tests {
     const XOR_32: f32 = unsafe { transmute(0x66666666_u32) };
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_and_pd() {
+    const unsafe fn test_mm_mask_and_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7236,7 +7434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_and_pd() {
+    const unsafe fn test_mm_maskz_and_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_and_pd(0b01, a, b);
@@ -7245,7 +7443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_and_pd() {
+    const unsafe fn test_mm256_mask_and_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7255,7 +7453,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_and_pd() {
+    const unsafe fn test_mm256_maskz_and_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_and_pd(0b0101, a, b);
@@ -7264,7 +7462,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_and_pd() {
+    const unsafe fn test_mm512_and_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_and_pd(a, b);
@@ -7273,7 +7471,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_and_pd() {
+    const unsafe fn test_mm512_mask_and_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7283,7 +7481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_and_pd() {
+    const unsafe fn test_mm512_maskz_and_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_and_pd(0b01010101, a, b);
@@ -7292,7 +7490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_and_ps() {
+    const unsafe fn test_mm_mask_and_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7302,7 +7500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_and_ps() {
+    const unsafe fn test_mm_maskz_and_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_and_ps(0b0101, a, b);
@@ -7311,7 +7509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_and_ps() {
+    const unsafe fn test_mm256_mask_and_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7321,7 +7519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_and_ps() {
+    const unsafe fn test_mm256_maskz_and_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_and_ps(0b01010101, a, b);
@@ -7330,7 +7528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_and_ps() {
+    const unsafe fn test_mm512_and_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_and_ps(a, b);
@@ -7339,7 +7537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_and_ps() {
+    const unsafe fn test_mm512_mask_and_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7354,7 +7552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_and_ps() {
+    const unsafe fn test_mm512_maskz_and_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_and_ps(0b0101010101010101, a, b);
@@ -7366,7 +7564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_andnot_pd() {
+    const unsafe fn test_mm_mask_andnot_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7376,7 +7574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_andnot_pd() {
+    const unsafe fn test_mm_maskz_andnot_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_andnot_pd(0b01, a, b);
@@ -7385,7 +7583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_andnot_pd() {
+    const unsafe fn test_mm256_mask_andnot_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7395,7 +7593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_andnot_pd() {
+    const unsafe fn test_mm256_maskz_andnot_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_andnot_pd(0b0101, a, b);
@@ -7404,7 +7602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_andnot_pd() {
+    const unsafe fn test_mm512_andnot_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_andnot_pd(a, b);
@@ -7413,7 +7611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_andnot_pd() {
+    const unsafe fn test_mm512_mask_andnot_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7423,7 +7621,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_andnot_pd() {
+    const unsafe fn test_mm512_maskz_andnot_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_andnot_pd(0b01010101, a, b);
@@ -7432,7 +7630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_andnot_ps() {
+    const unsafe fn test_mm_mask_andnot_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7442,7 +7640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_andnot_ps() {
+    const unsafe fn test_mm_maskz_andnot_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_andnot_ps(0b0101, a, b);
@@ -7451,7 +7649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_andnot_ps() {
+    const unsafe fn test_mm256_mask_andnot_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7461,7 +7659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_andnot_ps() {
+    const unsafe fn test_mm256_maskz_andnot_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_andnot_ps(0b01010101, a, b);
@@ -7470,7 +7668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_andnot_ps() {
+    const unsafe fn test_mm512_andnot_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_andnot_ps(a, b);
@@ -7479,7 +7677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_andnot_ps() {
+    const unsafe fn test_mm512_mask_andnot_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7494,7 +7692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_andnot_ps() {
+    const unsafe fn test_mm512_maskz_andnot_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_andnot_ps(0b0101010101010101, a, b);
@@ -7506,7 +7704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_or_pd() {
+    const unsafe fn test_mm_mask_or_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7516,7 +7714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_or_pd() {
+    const unsafe fn test_mm_maskz_or_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_or_pd(0b01, a, b);
@@ -7525,7 +7723,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_or_pd() {
+    const unsafe fn test_mm256_mask_or_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7535,7 +7733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_or_pd() {
+    const unsafe fn test_mm256_maskz_or_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_or_pd(0b0101, a, b);
@@ -7544,7 +7742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_or_pd() {
+    const unsafe fn test_mm512_or_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_or_pd(a, b);
@@ -7553,7 +7751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_or_pd() {
+    const unsafe fn test_mm512_mask_or_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7563,7 +7761,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_or_pd() {
+    const unsafe fn test_mm512_maskz_or_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_or_pd(0b01010101, a, b);
@@ -7572,7 +7770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_or_ps() {
+    const unsafe fn test_mm_mask_or_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7582,7 +7780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_or_ps() {
+    const unsafe fn test_mm_maskz_or_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_or_ps(0b0101, a, b);
@@ -7591,7 +7789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_or_ps() {
+    const unsafe fn test_mm256_mask_or_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7601,7 +7799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_or_ps() {
+    const unsafe fn test_mm256_maskz_or_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_or_ps(0b01010101, a, b);
@@ -7610,7 +7808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_or_ps() {
+    const unsafe fn test_mm512_or_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_or_ps(a, b);
@@ -7619,7 +7817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_or_ps() {
+    const unsafe fn test_mm512_mask_or_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7634,7 +7832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_or_ps() {
+    const unsafe fn test_mm512_maskz_or_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_or_ps(0b0101010101010101, a, b);
@@ -7645,7 +7843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_xor_pd() {
+    const unsafe fn test_mm_mask_xor_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7655,7 +7853,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_xor_pd() {
+    const unsafe fn test_mm_maskz_xor_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_xor_pd(0b01, a, b);
@@ -7664,7 +7862,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_xor_pd() {
+    const unsafe fn test_mm256_mask_xor_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7674,7 +7872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_xor_pd() {
+    const unsafe fn test_mm256_maskz_xor_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_xor_pd(0b0101, a, b);
@@ -7683,7 +7881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_xor_pd() {
+    const unsafe fn test_mm512_xor_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_xor_pd(a, b);
@@ -7692,7 +7890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_xor_pd() {
+    const unsafe fn test_mm512_mask_xor_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7702,7 +7900,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_xor_pd() {
+    const unsafe fn test_mm512_maskz_xor_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_xor_pd(0b01010101, a, b);
@@ -7711,7 +7909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_xor_ps() {
+    const unsafe fn test_mm_mask_xor_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7721,7 +7919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_xor_ps() {
+    const unsafe fn test_mm_maskz_xor_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_xor_ps(0b0101, a, b);
@@ -7730,7 +7928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_xor_ps() {
+    const unsafe fn test_mm256_mask_xor_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7740,7 +7938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_xor_ps() {
+    const unsafe fn test_mm256_maskz_xor_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_xor_ps(0b01010101, a, b);
@@ -7749,7 +7947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_xor_ps() {
+    const unsafe fn test_mm512_xor_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_xor_ps(a, b);
@@ -7758,7 +7956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_xor_ps() {
+    const unsafe fn test_mm512_mask_xor_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7773,7 +7971,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_xor_ps() {
+    const unsafe fn test_mm512_maskz_xor_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_xor_ps(0b0101010101010101, a, b);
@@ -7785,7 +7983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_broadcast_f32x2() {
+    const unsafe fn test_mm256_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_broadcast_f32x2(a);
         let e = _mm256_set_ps(3., 4., 3., 4., 3., 4., 3., 4.);
@@ -7793,7 +7991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_broadcast_f32x2() {
+    const unsafe fn test_mm256_mask_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm256_set_ps(5., 6., 7., 8., 9., 10., 11., 12.);
         let r = _mm256_mask_broadcast_f32x2(b, 0b01101001, a);
@@ -7802,7 +8000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcast_f32x2() {
+    const unsafe fn test_mm256_maskz_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_maskz_broadcast_f32x2(0b01101001, a);
         let e = _mm256_set_ps(0., 4., 3., 0., 3., 0., 0., 4.);
@@ -7810,7 +8008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_broadcast_f32x2() {
+    const unsafe fn test_mm512_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm512_broadcast_f32x2(a);
         let e = _mm512_set_ps(
@@ -7820,7 +8018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_broadcast_f32x2() {
+    const unsafe fn test_mm512_mask_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm512_set_ps(
             5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20.,
@@ -7833,7 +8031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_broadcast_f32x2() {
+    const unsafe fn test_mm512_maskz_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm512_maskz_broadcast_f32x2(0b0110100100111100, a);
         let e = _mm512_set_ps(
@@ -7843,7 +8041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_broadcast_f32x8() {
+    const unsafe fn test_mm512_broadcast_f32x8() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_broadcast_f32x8(a);
         let e = _mm512_set_ps(
@@ -7853,7 +8051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_broadcast_f32x8() {
+    const unsafe fn test_mm512_mask_broadcast_f32x8() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_ps(
             9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24.,
@@ -7866,7 +8064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_broadcast_f32x8() {
+    const unsafe fn test_mm512_maskz_broadcast_f32x8() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_broadcast_f32x8(0b0110100100111100, a);
         let e = _mm512_set_ps(
@@ -7876,7 +8074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_broadcast_f64x2() {
+    const unsafe fn test_mm256_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm256_broadcast_f64x2(a);
         let e = _mm256_set_pd(1., 2., 1., 2.);
@@ -7884,7 +8082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_broadcast_f64x2() {
+    const unsafe fn test_mm256_mask_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm256_set_pd(3., 4., 5., 6.);
         let r = _mm256_mask_broadcast_f64x2(b, 0b0110, a);
@@ -7893,7 +8091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcast_f64x2() {
+    const unsafe fn test_mm256_maskz_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm256_maskz_broadcast_f64x2(0b0110, a);
         let e = _mm256_set_pd(0., 2., 1., 0.);
@@ -7901,7 +8099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_broadcast_f64x2() {
+    const unsafe fn test_mm512_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm512_broadcast_f64x2(a);
         let e = _mm512_set_pd(1., 2., 1., 2., 1., 2., 1., 2.);
@@ -7909,7 +8107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_broadcast_f64x2() {
+    const unsafe fn test_mm512_mask_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm512_set_pd(3., 4., 5., 6., 7., 8., 9., 10.);
         let r = _mm512_mask_broadcast_f64x2(b, 0b01101001, a);
@@ -7918,7 +8116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_broadcast_f64x2() {
+    const unsafe fn test_mm512_maskz_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm512_maskz_broadcast_f64x2(0b01101001, a);
         let e = _mm512_set_pd(0., 2., 1., 0., 1., 0., 0., 2.);
@@ -7926,7 +8124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_broadcast_i32x2() {
+    const unsafe fn test_mm_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_broadcast_i32x2(a);
         let e = _mm_set_epi32(3, 4, 3, 4);
@@ -7934,7 +8132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_broadcast_i32x2() {
+    const unsafe fn test_mm_mask_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(5, 6, 7, 8);
         let r = _mm_mask_broadcast_i32x2(b, 0b0110, a);
@@ -7943,7 +8141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_broadcast_i32x2() {
+    const unsafe fn test_mm_maskz_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_broadcast_i32x2(0b0110, a);
         let e = _mm_set_epi32(0, 4, 3, 0);
@@ -7951,7 +8149,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_broadcast_i32x2() {
+    const unsafe fn test_mm256_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm256_broadcast_i32x2(a);
         let e = _mm256_set_epi32(3, 4, 3, 4, 3, 4, 3, 4);
@@ -7959,7 +8157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_broadcast_i32x2() {
+    const unsafe fn test_mm256_mask_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm256_set_epi32(5, 6, 7, 8, 9, 10, 11, 12);
         let r = _mm256_mask_broadcast_i32x2(b, 0b01101001, a);
@@ -7968,7 +8166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcast_i32x2() {
+    const unsafe fn test_mm256_maskz_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm256_maskz_broadcast_i32x2(0b01101001, a);
         let e = _mm256_set_epi32(0, 4, 3, 0, 3, 0, 0, 4);
@@ -7976,7 +8174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_broadcast_i32x2() {
+    const unsafe fn test_mm512_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm512_broadcast_i32x2(a);
         let e = _mm512_set_epi32(3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4);
@@ -7984,7 +8182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_broadcast_i32x2() {
+    const unsafe fn test_mm512_mask_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm512_set_epi32(5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20);
         let r = _mm512_mask_broadcast_i32x2(b, 0b0110100100111100, a);
@@ -7993,7 +8191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_broadcast_i32x2() {
+    const unsafe fn test_mm512_maskz_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm512_maskz_broadcast_i32x2(0b0110100100111100, a);
         let e = _mm512_set_epi32(0, 4, 3, 0, 3, 0, 0, 4, 0, 0, 3, 4, 3, 4, 0, 0);
@@ -8001,7 +8199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_broadcast_i32x8() {
+    const unsafe fn test_mm512_broadcast_i32x8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_broadcast_i32x8(a);
         let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
@@ -8009,7 +8207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_broadcast_i32x8() {
+    const unsafe fn test_mm512_mask_broadcast_i32x8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi32(
             9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
@@ -8020,7 +8218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_broadcast_i32x8() {
+    const unsafe fn test_mm512_maskz_broadcast_i32x8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_broadcast_i32x8(0b0110100100111100, a);
         let e = _mm512_set_epi32(0, 2, 3, 0, 5, 0, 0, 8, 0, 0, 3, 4, 5, 6, 0, 0);
@@ -8028,7 +8226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_broadcast_i64x2() {
+    const unsafe fn test_mm256_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm256_broadcast_i64x2(a);
         let e = _mm256_set_epi64x(1, 2, 1, 2);
@@ -8036,7 +8234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_broadcast_i64x2() {
+    const unsafe fn test_mm256_mask_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm256_set_epi64x(3, 4, 5, 6);
         let r = _mm256_mask_broadcast_i64x2(b, 0b0110, a);
@@ -8045,7 +8243,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_broadcast_i64x2() {
+    const unsafe fn test_mm256_maskz_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm256_maskz_broadcast_i64x2(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 1, 0);
@@ -8053,7 +8251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_broadcast_i64x2() {
+    const unsafe fn test_mm512_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm512_broadcast_i64x2(a);
         let e = _mm512_set_epi64(1, 2, 1, 2, 1, 2, 1, 2);
@@ -8061,7 +8259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_broadcast_i64x2() {
+    const unsafe fn test_mm512_mask_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm512_set_epi64(3, 4, 5, 6, 7, 8, 9, 10);
         let r = _mm512_mask_broadcast_i64x2(b, 0b01101001, a);
@@ -8070,7 +8268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_broadcast_i64x2() {
+    const unsafe fn test_mm512_maskz_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm512_maskz_broadcast_i64x2(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 1, 0, 1, 0, 0, 2);
@@ -8078,7 +8276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_extractf32x8_ps() {
+    const unsafe fn test_mm512_extractf32x8_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8088,7 +8286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_extractf32x8_ps() {
+    const unsafe fn test_mm512_mask_extractf32x8_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8099,7 +8297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_extractf32x8_ps() {
+    const unsafe fn test_mm512_maskz_extractf32x8_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8109,7 +8307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_extractf64x2_pd() {
+    const unsafe fn test_mm256_extractf64x2_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_extractf64x2_pd::<1>(a);
         let e = _mm_set_pd(1., 2.);
@@ -8117,7 +8315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_extractf64x2_pd() {
+    const unsafe fn test_mm256_mask_extractf64x2_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let r = _mm256_mask_extractf64x2_pd::<1>(b, 0b01, a);
@@ -8126,7 +8324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_extractf64x2_pd() {
+    const unsafe fn test_mm256_maskz_extractf64x2_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_extractf64x2_pd::<1>(0b01, a);
         let e = _mm_set_pd(0., 2.);
@@ -8134,7 +8332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_extractf64x2_pd() {
+    const unsafe fn test_mm512_extractf64x2_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_extractf64x2_pd::<2>(a);
         let e = _mm_set_pd(3., 4.);
@@ -8142,7 +8340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_extractf64x2_pd() {
+    const unsafe fn test_mm512_mask_extractf64x2_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let r = _mm512_mask_extractf64x2_pd::<2>(b, 0b01, a);
@@ -8151,7 +8349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_extractf64x2_pd() {
+    const unsafe fn test_mm512_maskz_extractf64x2_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_extractf64x2_pd::<2>(0b01, a);
         let e = _mm_set_pd(0., 4.);
@@ -8159,7 +8357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_extracti32x8_epi32() {
+    const unsafe fn test_mm512_extracti32x8_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_extracti32x8_epi32::<1>(a);
         let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
@@ -8167,7 +8365,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_extracti32x8_epi32() {
+    const unsafe fn test_mm512_mask_extracti32x8_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_extracti32x8_epi32::<1>(b, 0b01101001, a);
@@ -8176,7 +8374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_extracti32x8_epi32() {
+    const unsafe fn test_mm512_maskz_extracti32x8_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_extracti32x8_epi32::<1>(0b01101001, a);
         let e = _mm256_set_epi32(0, 2, 3, 0, 5, 0, 0, 8);
@@ -8184,7 +8382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_extracti64x2_epi64() {
+    const unsafe fn test_mm256_extracti64x2_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_extracti64x2_epi64::<1>(a);
         let e = _mm_set_epi64x(1, 2);
@@ -8192,7 +8390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_extracti64x2_epi64() {
+    const unsafe fn test_mm256_mask_extracti64x2_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm256_mask_extracti64x2_epi64::<1>(b, 0b01, a);
@@ -8201,7 +8399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_extracti64x2_epi64() {
+    const unsafe fn test_mm256_maskz_extracti64x2_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_extracti64x2_epi64::<1>(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -8209,7 +8407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_extracti64x2_epi64() {
+    const unsafe fn test_mm512_extracti64x2_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_extracti64x2_epi64::<2>(a);
         let e = _mm_set_epi64x(3, 4);
@@ -8217,7 +8415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_extracti64x2_epi64() {
+    const unsafe fn test_mm512_mask_extracti64x2_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let r = _mm512_mask_extracti64x2_epi64::<2>(b, 0b01, a);
@@ -8226,7 +8424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_extracti64x2_epi64() {
+    const unsafe fn test_mm512_maskz_extracti64x2_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_extracti64x2_epi64::<2>(0b01, a);
         let e = _mm_set_epi64x(0, 4);
@@ -8234,7 +8432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_insertf32x8() {
+    const unsafe fn test_mm512_insertf32x8() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8247,7 +8445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_insertf32x8() {
+    const unsafe fn test_mm512_mask_insertf32x8() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8263,7 +8461,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_insertf32x8() {
+    const unsafe fn test_mm512_maskz_insertf32x8() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8276,7 +8474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_insertf64x2() {
+    const unsafe fn test_mm256_insertf64x2() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let r = _mm256_insertf64x2::<1>(a, b);
@@ -8285,7 +8483,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_insertf64x2() {
+    const unsafe fn test_mm256_mask_insertf64x2() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let src = _mm256_set_pd(7., 8., 9., 10.);
@@ -8295,7 +8493,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_insertf64x2() {
+    const unsafe fn test_mm256_maskz_insertf64x2() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let r = _mm256_maskz_insertf64x2::<1>(0b0110, a, b);
@@ -8304,7 +8502,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_insertf64x2() {
+    const unsafe fn test_mm512_insertf64x2() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let r = _mm512_insertf64x2::<2>(a, b);
@@ -8313,7 +8511,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_insertf64x2() {
+    const unsafe fn test_mm512_mask_insertf64x2() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let src = _mm512_set_pd(11., 12., 13., 14., 15., 16., 17., 18.);
@@ -8323,7 +8521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_insertf64x2() {
+    const unsafe fn test_mm512_maskz_insertf64x2() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let r = _mm512_maskz_insertf64x2::<2>(0b01101001, a, b);
@@ -8332,7 +8530,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_inserti32x8() {
+    const unsafe fn test_mm512_inserti32x8() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_inserti32x8::<1>(a, b);
@@ -8343,7 +8541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_inserti32x8() {
+    const unsafe fn test_mm512_mask_inserti32x8() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let src = _mm512_set_epi32(
@@ -8357,7 +8555,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_inserti32x8() {
+    const unsafe fn test_mm512_maskz_inserti32x8() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_inserti32x8::<1>(0b0110100100111100, a, b);
@@ -8366,7 +8564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_inserti64x2() {
+    const unsafe fn test_mm256_inserti64x2() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm256_inserti64x2::<1>(a, b);
@@ -8375,7 +8573,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_inserti64x2() {
+    const unsafe fn test_mm256_mask_inserti64x2() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let src = _mm256_set_epi64x(7, 8, 9, 10);
@@ -8385,7 +8583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_inserti64x2() {
+    const unsafe fn test_mm256_maskz_inserti64x2() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm256_maskz_inserti64x2::<1>(0b0110, a, b);
@@ -8394,7 +8592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_inserti64x2() {
+    const unsafe fn test_mm512_inserti64x2() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let r = _mm512_inserti64x2::<2>(a, b);
@@ -8403,7 +8601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_inserti64x2() {
+    const unsafe fn test_mm512_mask_inserti64x2() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let src = _mm512_set_epi64(11, 12, 13, 14, 15, 16, 17, 18);
@@ -8413,7 +8611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_inserti64x2() {
+    const unsafe fn test_mm512_maskz_inserti64x2() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let r = _mm512_maskz_inserti64x2::<2>(0b01101001, a, b);
@@ -9654,7 +9852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mullo_epi64() {
+    const unsafe fn test_mm_mullo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_mullo_epi64(a, b);
@@ -9663,7 +9861,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_mullo_epi64() {
+    const unsafe fn test_mm_mask_mullo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(3, 4);
         let c = _mm_set_epi64x(5, 6);
@@ -9673,7 +9871,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_mullo_epi64() {
+    const unsafe fn test_mm_maskz_mullo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_maskz_mullo_epi64(0b01, a, b);
@@ -9682,7 +9880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mullo_epi64() {
+    const unsafe fn test_mm256_mullo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mullo_epi64(a, b);
@@ -9691,7 +9889,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_mullo_epi64() {
+    const unsafe fn test_mm256_mask_mullo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let c = _mm256_set_epi64x(9, 10, 11, 12);
@@ -9701,7 +9899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_mullo_epi64() {
+    const unsafe fn test_mm256_maskz_mullo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_maskz_mullo_epi64(0b0110, a, b);
@@ -9710,7 +9908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mullo_epi64() {
+    const unsafe fn test_mm512_mullo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mullo_epi64(a, b);
@@ -9719,7 +9917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_mullo_epi64() {
+    const unsafe fn test_mm512_mask_mullo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let c = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
@@ -9729,7 +9927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_mullo_epi64() {
+    const unsafe fn test_mm512_maskz_mullo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_mullo_epi64(0b01101001, a, b);
@@ -9738,7 +9936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_cvtmask8_u32() {
+    const unsafe fn test_cvtmask8_u32() {
         let a: __mmask8 = 0b01101001;
         let r = _cvtmask8_u32(a);
         let e: u32 = 0b01101001;
@@ -9746,7 +9944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_cvtu32_mask8() {
+    const unsafe fn test_cvtu32_mask8() {
         let a: u32 = 0b01101001;
         let r = _cvtu32_mask8(a);
         let e: __mmask8 = 0b01101001;
@@ -9754,7 +9952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kadd_mask16() {
+    const unsafe fn test_kadd_mask16() {
         let a: __mmask16 = 27549;
         let b: __mmask16 = 23434;
         let r = _kadd_mask16(a, b);
@@ -9763,7 +9961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kadd_mask8() {
+    const unsafe fn test_kadd_mask8() {
         let a: __mmask8 = 98;
         let b: __mmask8 = 117;
         let r = _kadd_mask8(a, b);
@@ -9772,7 +9970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kand_mask8() {
+    const unsafe fn test_kand_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kand_mask8(a, b);
@@ -9781,7 +9979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kandn_mask8() {
+    const unsafe fn test_kandn_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kandn_mask8(a, b);
@@ -9790,7 +9988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_knot_mask8() {
+    const unsafe fn test_knot_mask8() {
         let a: __mmask8 = 0b01101001;
         let r = _knot_mask8(a);
         let e: __mmask8 = 0b10010110;
@@ -9798,7 +9996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kor_mask8() {
+    const unsafe fn test_kor_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kor_mask8(a, b);
@@ -9807,7 +10005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kxnor_mask8() {
+    const unsafe fn test_kxnor_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kxnor_mask8(a, b);
@@ -9816,7 +10014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kxor_mask8() {
+    const unsafe fn test_kxor_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kxor_mask8(a, b);
@@ -9825,7 +10023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kortest_mask8_u8() {
+    const unsafe fn test_kortest_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let mut all_ones: u8 = 0;
@@ -9835,7 +10033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kortestc_mask8_u8() {
+    const unsafe fn test_kortestc_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let r = _kortestc_mask8_u8(a, b);
@@ -9843,7 +10041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kortestz_mask8_u8() {
+    const unsafe fn test_kortestz_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let r = _kortestz_mask8_u8(a, b);
@@ -9851,7 +10049,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kshiftli_mask8() {
+    const unsafe fn test_kshiftli_mask8() {
         let a: __mmask8 = 0b01101001;
         let r = _kshiftli_mask8::<3>(a);
         let e: __mmask8 = 0b01001000;
@@ -9871,7 +10069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_kshiftri_mask8() {
+    const unsafe fn test_kshiftri_mask8() {
         let a: __mmask8 = 0b10101001;
         let r = _kshiftri_mask8::<3>(a);
         let e: __mmask8 = 0b00010101;
@@ -9891,7 +10089,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_ktest_mask8_u8() {
+    const unsafe fn test_ktest_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let mut and_not: u8 = 0;
@@ -9901,7 +10099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_ktestc_mask8_u8() {
+    const unsafe fn test_ktestc_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let r = _ktestc_mask8_u8(a, b);
@@ -9909,7 +10107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_ktestz_mask8_u8() {
+    const unsafe fn test_ktestz_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let r = _ktestz_mask8_u8(a, b);
@@ -9917,7 +10115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_ktest_mask16_u8() {
+    const unsafe fn test_ktest_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let mut and_not: u8 = 0;
@@ -9927,7 +10125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_ktestc_mask16_u8() {
+    const unsafe fn test_ktestc_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let r = _ktestc_mask16_u8(a, b);
@@ -9935,7 +10133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_ktestz_mask16_u8() {
+    const unsafe fn test_ktestz_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let r = _ktestz_mask16_u8(a, b);
@@ -9943,7 +10141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_load_mask8() {
+    const unsafe fn test_load_mask8() {
         let a: __mmask8 = 0b01101001;
         let r = _load_mask8(&a);
         let e: __mmask8 = 0b01101001;
@@ -9951,7 +10149,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_store_mask8() {
+    const unsafe fn test_store_mask8() {
         let a: __mmask8 = 0b01101001;
         let mut r = 0;
         _store_mask8(&mut r, a);
@@ -9960,7 +10158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_movepi32_mask() {
+    const unsafe fn test_mm_movepi32_mask() {
         let a = _mm_set_epi32(0, -2, -3, 4);
         let r = _mm_movepi32_mask(a);
         let e = 0b0110;
@@ -9968,7 +10166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_movepi32_mask() {
+    const unsafe fn test_mm256_movepi32_mask() {
         let a = _mm256_set_epi32(0, -2, -3, 4, -5, 6, 7, -8);
         let r = _mm256_movepi32_mask(a);
         let e = 0b01101001;
@@ -9976,7 +10174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_movepi32_mask() {
+    const unsafe fn test_mm512_movepi32_mask() {
         let a = _mm512_set_epi32(
             0, -2, -3, 4, -5, 6, 7, -8, 9, 10, -11, -12, -13, -14, 15, 16,
         );
@@ -9986,7 +10184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_movepi64_mask() {
+    const unsafe fn test_mm_movepi64_mask() {
         let a = _mm_set_epi64x(0, -2);
         let r = _mm_movepi64_mask(a);
         let e = 0b01;
@@ -9994,7 +10192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_movepi64_mask() {
+    const unsafe fn test_mm256_movepi64_mask() {
         let a = _mm256_set_epi64x(0, -2, -3, 4);
         let r = _mm256_movepi64_mask(a);
         let e = 0b0110;
@@ -10002,7 +10200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_movepi64_mask() {
+    const unsafe fn test_mm512_movepi64_mask() {
         let a = _mm512_set_epi64(0, -2, -3, 4, -5, 6, 7, -8);
         let r = _mm512_movepi64_mask(a);
         let e = 0b01101001;
@@ -10010,7 +10208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_movm_epi32() {
+    const unsafe fn test_mm_movm_epi32() {
         let a = 0b0110;
         let r = _mm_movm_epi32(a);
         let e = _mm_set_epi32(0, -1, -1, 0);
@@ -10018,7 +10216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_movm_epi32() {
+    const unsafe fn test_mm256_movm_epi32() {
         let a = 0b01101001;
         let r = _mm256_movm_epi32(a);
         let e = _mm256_set_epi32(0, -1, -1, 0, -1, 0, 0, -1);
@@ -10026,7 +10224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_movm_epi32() {
+    const unsafe fn test_mm512_movm_epi32() {
         let a = 0b0110100100111100;
         let r = _mm512_movm_epi32(a);
         let e = _mm512_set_epi32(0, -1, -1, 0, -1, 0, 0, -1, 0, 0, -1, -1, -1, -1, 0, 0);
@@ -10034,7 +10232,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_movm_epi64() {
+    const unsafe fn test_mm_movm_epi64() {
         let a = 0b01;
         let r = _mm_movm_epi64(a);
         let e = _mm_set_epi64x(0, -1);
@@ -10042,7 +10240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_movm_epi64() {
+    const unsafe fn test_mm256_movm_epi64() {
         let a = 0b0110;
         let r = _mm256_movm_epi64(a);
         let e = _mm256_set_epi64x(0, -1, -1, 0);
@@ -10050,7 +10248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_movm_epi64() {
+    const unsafe fn test_mm512_movm_epi64() {
         let a = 0b01101001;
         let r = _mm512_movm_epi64(a);
         let e = _mm512_set_epi64(0, -1, -1, 0, -1, 0, 0, -1);

From 2792ab51b88121467c975da51da5e10bfa4a83a6 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:26:40 +0530
Subject: [PATCH 065/326] Make `avx512vbmi2` functions const

---
 crates/core_arch/src/x86/avx512vbmi2.rs | 613 +++++++++++++++---------
 1 file changed, 397 insertions(+), 216 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512vbmi2.rs b/crates/core_arch/src/x86/avx512vbmi2.rs
index e25fd4528d..da268f969c 100644
--- a/crates/core_arch/src/x86/avx512vbmi2.rs
+++ b/crates/core_arch/src/x86/avx512vbmi2.rs
@@ -499,7 +499,8 @@ pub fn _mm_maskz_expand_epi8(k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm512_shldv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shldv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i64x8(),
@@ -516,7 +517,8 @@ pub fn _mm512_shldv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm512_mask_shldv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shldv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shldv_epi64(a, b, c).as_i64x8();
         transmute(simd_select_bitmask(k, shf, a.as_i64x8()))
@@ -530,7 +532,8 @@ pub fn _mm512_mask_shldv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm512_maskz_shldv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shldv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shldv_epi64(a, b, c).as_i64x8();
         transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -544,7 +547,8 @@ pub fn _mm512_maskz_shldv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm256_shldv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shldv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i64x4(),
@@ -561,7 +565,8 @@ pub fn _mm256_shldv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm256_mask_shldv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shldv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shldv_epi64(a, b, c).as_i64x4();
         transmute(simd_select_bitmask(k, shf, a.as_i64x4()))
@@ -575,7 +580,8 @@ pub fn _mm256_mask_shldv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm256_maskz_shldv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shldv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shldv_epi64(a, b, c).as_i64x4();
         transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -589,7 +595,8 @@ pub fn _mm256_maskz_shldv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm_shldv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shldv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i64x2(),
@@ -606,7 +613,8 @@ pub fn _mm_shldv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm_mask_shldv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shldv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shldv_epi64(a, b, c).as_i64x2();
         transmute(simd_select_bitmask(k, shf, a.as_i64x2()))
@@ -620,7 +628,8 @@ pub fn _mm_mask_shldv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvq))]
-pub fn _mm_maskz_shldv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shldv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shldv_epi64(a, b, c).as_i64x2();
         transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -634,7 +643,8 @@ pub fn _mm_maskz_shldv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm512_shldv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shldv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i32x16(),
@@ -651,7 +661,8 @@ pub fn _mm512_shldv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm512_mask_shldv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shldv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shldv_epi32(a, b, c).as_i32x16();
         transmute(simd_select_bitmask(k, shf, a.as_i32x16()))
@@ -665,7 +676,8 @@ pub fn _mm512_mask_shldv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm512_maskz_shldv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shldv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shldv_epi32(a, b, c).as_i32x16();
         transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -679,7 +691,8 @@ pub fn _mm512_maskz_shldv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm256_shldv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shldv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i32x8(),
@@ -696,7 +709,8 @@ pub fn _mm256_shldv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm256_mask_shldv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shldv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shldv_epi32(a, b, c).as_i32x8();
         transmute(simd_select_bitmask(k, shf, a.as_i32x8()))
@@ -710,7 +724,8 @@ pub fn _mm256_mask_shldv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm256_maskz_shldv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shldv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shldv_epi32(a, b, c).as_i32x8();
         transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -724,7 +739,8 @@ pub fn _mm256_maskz_shldv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm_shldv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shldv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i32x4(),
@@ -741,7 +757,8 @@ pub fn _mm_shldv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm_mask_shldv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shldv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shldv_epi32(a, b, c).as_i32x4();
         transmute(simd_select_bitmask(k, shf, a.as_i32x4()))
@@ -755,7 +772,8 @@ pub fn _mm_mask_shldv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvd))]
-pub fn _mm_maskz_shldv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shldv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shldv_epi32(a, b, c).as_i32x4();
         transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -769,7 +787,8 @@ pub fn _mm_maskz_shldv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm512_shldv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shldv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i16x32(),
@@ -786,7 +805,8 @@ pub fn _mm512_shldv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm512_mask_shldv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shldv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shldv_epi16(a, b, c).as_i16x32();
         transmute(simd_select_bitmask(k, shf, a.as_i16x32()))
@@ -800,7 +820,8 @@ pub fn _mm512_mask_shldv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm512_maskz_shldv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shldv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shldv_epi16(a, b, c).as_i16x32();
         transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -814,7 +835,8 @@ pub fn _mm512_maskz_shldv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm256_shldv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shldv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i16x16(),
@@ -831,7 +853,8 @@ pub fn _mm256_shldv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm256_mask_shldv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shldv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shldv_epi16(a, b, c).as_i16x16();
         transmute(simd_select_bitmask(k, shf, a.as_i16x16()))
@@ -845,7 +868,8 @@ pub fn _mm256_mask_shldv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm256_maskz_shldv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shldv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shldv_epi16(a, b, c).as_i16x16();
         transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -859,7 +883,8 @@ pub fn _mm256_maskz_shldv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm_shldv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shldv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shl(
             a.as_i16x8(),
@@ -876,7 +901,8 @@ pub fn _mm_shldv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm_mask_shldv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shldv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shldv_epi16(a, b, c).as_i16x8();
         transmute(simd_select_bitmask(k, shf, a.as_i16x8()))
@@ -890,7 +916,8 @@ pub fn _mm_mask_shldv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldvw))]
-pub fn _mm_maskz_shldv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shldv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shldv_epi16(a, b, c).as_i16x8();
         transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -904,7 +931,8 @@ pub fn _mm_maskz_shldv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm512_shrdv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shrdv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i64x8(),
@@ -921,7 +949,8 @@ pub fn _mm512_shrdv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm512_mask_shrdv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shrdv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shrdv_epi64(a, b, c).as_i64x8();
         transmute(simd_select_bitmask(k, shf, a.as_i64x8()))
@@ -935,7 +964,8 @@ pub fn _mm512_mask_shrdv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm512_maskz_shrdv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shrdv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shrdv_epi64(a, b, c).as_i64x8();
         transmute(simd_select_bitmask(k, shf, i64x8::ZERO))
@@ -949,7 +979,8 @@ pub fn _mm512_maskz_shrdv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm256_shrdv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shrdv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i64x4(),
@@ -966,7 +997,8 @@ pub fn _mm256_shrdv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm256_mask_shrdv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shrdv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shrdv_epi64(a, b, c).as_i64x4();
         transmute(simd_select_bitmask(k, shf, a.as_i64x4()))
@@ -980,7 +1012,8 @@ pub fn _mm256_mask_shrdv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm256_maskz_shrdv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shrdv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shrdv_epi64(a, b, c).as_i64x4();
         transmute(simd_select_bitmask(k, shf, i64x4::ZERO))
@@ -994,7 +1027,8 @@ pub fn _mm256_maskz_shrdv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm_shrdv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shrdv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i64x2(),
@@ -1011,7 +1045,8 @@ pub fn _mm_shrdv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm_mask_shrdv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shrdv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shrdv_epi64(a, b, c).as_i64x2();
         transmute(simd_select_bitmask(k, shf, a.as_i64x2()))
@@ -1025,7 +1060,8 @@ pub fn _mm_mask_shrdv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvq))]
-pub fn _mm_maskz_shrdv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shrdv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shrdv_epi64(a, b, c).as_i64x2();
         transmute(simd_select_bitmask(k, shf, i64x2::ZERO))
@@ -1039,7 +1075,8 @@ pub fn _mm_maskz_shrdv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm512_shrdv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shrdv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i32x16(),
@@ -1056,7 +1093,8 @@ pub fn _mm512_shrdv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm512_mask_shrdv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shrdv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shrdv_epi32(a, b, c).as_i32x16();
         transmute(simd_select_bitmask(k, shf, a.as_i32x16()))
@@ -1070,7 +1108,8 @@ pub fn _mm512_mask_shrdv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm512_maskz_shrdv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shrdv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shrdv_epi32(a, b, c).as_i32x16();
         transmute(simd_select_bitmask(k, shf, i32x16::ZERO))
@@ -1084,7 +1123,8 @@ pub fn _mm512_maskz_shrdv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm256_shrdv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shrdv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i32x8(),
@@ -1101,7 +1141,8 @@ pub fn _mm256_shrdv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm256_mask_shrdv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shrdv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shrdv_epi32(a, b, c).as_i32x8();
         transmute(simd_select_bitmask(k, shf, a.as_i32x8()))
@@ -1115,7 +1156,8 @@ pub fn _mm256_mask_shrdv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm256_maskz_shrdv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shrdv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shrdv_epi32(a, b, c).as_i32x8();
         transmute(simd_select_bitmask(k, shf, i32x8::ZERO))
@@ -1129,7 +1171,8 @@ pub fn _mm256_maskz_shrdv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm_shrdv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shrdv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i32x4(),
@@ -1146,7 +1189,8 @@ pub fn _mm_shrdv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm_mask_shrdv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shrdv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shrdv_epi32(a, b, c).as_i32x4();
         transmute(simd_select_bitmask(k, shf, a.as_i32x4()))
@@ -1160,7 +1204,8 @@ pub fn _mm_mask_shrdv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvd))]
-pub fn _mm_maskz_shrdv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shrdv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shrdv_epi32(a, b, c).as_i32x4();
         transmute(simd_select_bitmask(k, shf, i32x4::ZERO))
@@ -1174,7 +1219,8 @@ pub fn _mm_maskz_shrdv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm512_shrdv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shrdv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i16x32(),
@@ -1191,7 +1237,8 @@ pub fn _mm512_shrdv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm512_mask_shrdv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shrdv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shrdv_epi16(a, b, c).as_i16x32();
         transmute(simd_select_bitmask(k, shf, a.as_i16x32()))
@@ -1205,7 +1252,8 @@ pub fn _mm512_mask_shrdv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i)
 #[target_feature(enable = "avx512vbmi2")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm512_maskz_shrdv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shrdv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i) -> __m512i {
     unsafe {
         let shf = _mm512_shrdv_epi16(a, b, c).as_i16x32();
         transmute(simd_select_bitmask(k, shf, i16x32::ZERO))
@@ -1219,7 +1267,8 @@ pub fn _mm512_maskz_shrdv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm256_shrdv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shrdv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i16x16(),
@@ -1236,7 +1285,8 @@ pub fn _mm256_shrdv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm256_mask_shrdv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shrdv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shrdv_epi16(a, b, c).as_i16x16();
         transmute(simd_select_bitmask(k, shf, a.as_i16x16()))
@@ -1250,7 +1300,8 @@ pub fn _mm256_mask_shrdv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i)
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm256_maskz_shrdv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shrdv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i) -> __m256i {
     unsafe {
         let shf = _mm256_shrdv_epi16(a, b, c).as_i16x16();
         transmute(simd_select_bitmask(k, shf, i16x16::ZERO))
@@ -1264,7 +1315,8 @@ pub fn _mm256_maskz_shrdv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm_shrdv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shrdv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         transmute(simd_funnel_shr(
             b.as_i16x8(),
@@ -1281,7 +1333,8 @@ pub fn _mm_shrdv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm_mask_shrdv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shrdv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shrdv_epi16(a, b, c).as_i16x8();
         transmute(simd_select_bitmask(k, shf, a.as_i16x8()))
@@ -1295,7 +1348,8 @@ pub fn _mm_mask_shrdv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) ->
 #[target_feature(enable = "avx512vbmi2,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshrdvw))]
-pub fn _mm_maskz_shrdv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shrdv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
     unsafe {
         let shf = _mm_shrdv_epi16(a, b, c).as_i16x8();
         transmute(simd_select_bitmask(k, shf, i16x8::ZERO))
@@ -1310,7 +1364,8 @@ pub fn _mm_maskz_shrdv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) ->
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shldi_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shldi_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_shldv_epi64(a, b, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -1323,7 +1378,8 @@ pub fn _mm512_shldi_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shldi_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shldi_epi64<const IMM8: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -1344,7 +1400,12 @@ pub fn _mm512_mask_shldi_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shldi_epi64<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shldi_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm512_shldi_epi64::<IMM8>(a, b).as_i64x8();
@@ -1360,7 +1421,8 @@ pub fn _mm512_maskz_shldi_epi64<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shldi_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shldi_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_shldv_epi64(a, b, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -1373,7 +1435,8 @@ pub fn _mm256_shldi_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shldi_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shldi_epi64<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -1394,7 +1457,12 @@ pub fn _mm256_mask_shldi_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shldi_epi64<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shldi_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_shldi_epi64::<IMM8>(a, b).as_i64x4();
@@ -1410,7 +1478,8 @@ pub fn _mm256_maskz_shldi_epi64<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_shldi_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shldi_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_shldv_epi64(a, b, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -1423,7 +1492,8 @@ pub fn _mm_shldi_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shldi_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shldi_epi64<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -1444,7 +1514,12 @@ pub fn _mm_mask_shldi_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shldi_epi64<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shldi_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_shldi_epi64::<IMM8>(a, b).as_i64x2();
@@ -1460,7 +1535,8 @@ pub fn _mm_maskz_shldi_epi64<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shldi_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shldi_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_shldv_epi32(a, b, _mm512_set1_epi32(IMM8))
 }
@@ -1473,7 +1549,8 @@ pub fn _mm512_shldi_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shldi_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shldi_epi32<const IMM8: i32>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -1494,7 +1571,12 @@ pub fn _mm512_mask_shldi_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shldi_epi32<const IMM8: i32>(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shldi_epi32<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm512_shldi_epi32::<IMM8>(a, b).as_i32x16();
@@ -1510,7 +1592,8 @@ pub fn _mm512_maskz_shldi_epi32<const IMM8: i32>(k: __mmask16, a: __m512i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shldi_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shldi_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_shldv_epi32(a, b, _mm256_set1_epi32(IMM8))
 }
@@ -1523,7 +1606,8 @@ pub fn _mm256_shldi_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shldi_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shldi_epi32<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -1544,7 +1628,12 @@ pub fn _mm256_mask_shldi_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shldi_epi32<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shldi_epi32<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_shldi_epi32::<IMM8>(a, b).as_i32x8();
@@ -1560,7 +1649,8 @@ pub fn _mm256_maskz_shldi_epi32<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_shldi_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shldi_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_shldv_epi32(a, b, _mm_set1_epi32(IMM8))
 }
@@ -1573,7 +1663,8 @@ pub fn _mm_shldi_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shldi_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shldi_epi32<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -1594,7 +1685,12 @@ pub fn _mm_mask_shldi_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shldi_epi32<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shldi_epi32<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_shldi_epi32::<IMM8>(a, b).as_i32x4();
@@ -1610,7 +1706,8 @@ pub fn _mm_maskz_shldi_epi32<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shldi_epi16<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shldi_epi16<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_shldv_epi16(a, b, _mm512_set1_epi16(IMM8 as i16))
 }
@@ -1623,7 +1720,8 @@ pub fn _mm512_shldi_epi16<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shldi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shldi_epi16<const IMM8: i32>(
     src: __m512i,
     k: __mmask32,
     a: __m512i,
@@ -1644,7 +1742,12 @@ pub fn _mm512_mask_shldi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shldi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shldi_epi16<const IMM8: i32>(
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm512_shldi_epi16::<IMM8>(a, b).as_i16x32();
@@ -1660,7 +1763,8 @@ pub fn _mm512_maskz_shldi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shldi_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shldi_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_shldv_epi16(a, b, _mm256_set1_epi16(IMM8 as i16))
 }
@@ -1673,7 +1777,8 @@ pub fn _mm256_shldi_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shldi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shldi_epi16<const IMM8: i32>(
     src: __m256i,
     k: __mmask16,
     a: __m256i,
@@ -1694,7 +1799,12 @@ pub fn _mm256_mask_shldi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shldi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shldi_epi16<const IMM8: i32>(
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_shldi_epi16::<IMM8>(a, b).as_i16x16();
@@ -1710,7 +1820,8 @@ pub fn _mm256_maskz_shldi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_shldi_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shldi_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_shldv_epi16(a, b, _mm_set1_epi16(IMM8 as i16))
 }
@@ -1723,7 +1834,8 @@ pub fn _mm_shldi_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shldi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shldi_epi16<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -1744,7 +1856,12 @@ pub fn _mm_mask_shldi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))]
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shldi_epi16<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shldi_epi16<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_shldi_epi16::<IMM8>(a, b).as_i16x8();
@@ -1760,7 +1877,8 @@ pub fn _mm_maskz_shldi_epi16<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shrdi_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shrdi_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_shrdv_epi64(a, b, _mm512_set1_epi64(IMM8 as i64))
 }
@@ -1773,7 +1891,8 @@ pub fn _mm512_shrdi_epi64<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shrdi_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shrdi_epi64<const IMM8: i32>(
     src: __m512i,
     k: __mmask8,
     a: __m512i,
@@ -1794,7 +1913,12 @@ pub fn _mm512_mask_shrdi_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 255))] //should be vpshrdq
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shrdi_epi64<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shrdi_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm512_shrdi_epi64::<IMM8>(a, b).as_i64x8();
@@ -1810,7 +1934,8 @@ pub fn _mm512_maskz_shrdi_epi64<const IMM8: i32>(k: __mmask8, a: __m512i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shrdi_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shrdi_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_shrdv_epi64(a, b, _mm256_set1_epi64x(IMM8 as i64))
 }
@@ -1823,7 +1948,8 @@ pub fn _mm256_shrdi_epi64<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shrdi_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shrdi_epi64<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -1844,7 +1970,12 @@ pub fn _mm256_mask_shrdi_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shrdi_epi64<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shrdi_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_shrdi_epi64::<IMM8>(a, b).as_i64x4();
@@ -1860,7 +1991,8 @@ pub fn _mm256_maskz_shrdi_epi64<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_shrdi_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shrdi_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_shrdv_epi64(a, b, _mm_set1_epi64x(IMM8 as i64))
 }
@@ -1873,7 +2005,8 @@ pub fn _mm_shrdi_epi64<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shrdi_epi64<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shrdi_epi64<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -1894,7 +2027,12 @@ pub fn _mm_mask_shrdi_epi64<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shrdi_epi64<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shrdi_epi64<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_shrdi_epi64::<IMM8>(a, b).as_i64x2();
@@ -1910,7 +2048,8 @@ pub fn _mm_maskz_shrdi_epi64<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shrdi_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shrdi_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_shrdv_epi32(a, b, _mm512_set1_epi32(IMM8))
 }
@@ -1923,7 +2062,8 @@ pub fn _mm512_shrdi_epi32<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shrdi_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shrdi_epi32<const IMM8: i32>(
     src: __m512i,
     k: __mmask16,
     a: __m512i,
@@ -1944,7 +2084,12 @@ pub fn _mm512_mask_shrdi_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shrdi_epi32<const IMM8: i32>(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shrdi_epi32<const IMM8: i32>(
+    k: __mmask16,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm512_shrdi_epi32::<IMM8>(a, b).as_i32x16();
@@ -1960,7 +2105,8 @@ pub fn _mm512_maskz_shrdi_epi32<const IMM8: i32>(k: __mmask16, a: __m512i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shrdi_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shrdi_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_shrdv_epi32(a, b, _mm256_set1_epi32(IMM8))
 }
@@ -1973,7 +2119,8 @@ pub fn _mm256_shrdi_epi32<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shrdi_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shrdi_epi32<const IMM8: i32>(
     src: __m256i,
     k: __mmask8,
     a: __m256i,
@@ -1994,7 +2141,12 @@ pub fn _mm256_mask_shrdi_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shrdi_epi32<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shrdi_epi32<const IMM8: i32>(
+    k: __mmask8,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_shrdi_epi32::<IMM8>(a, b).as_i32x8();
@@ -2010,7 +2162,8 @@ pub fn _mm256_maskz_shrdi_epi32<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_shrdi_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shrdi_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_shrdv_epi32(a, b, _mm_set1_epi32(IMM8))
 }
@@ -2023,7 +2176,8 @@ pub fn _mm_shrdi_epi32<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shrdi_epi32<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shrdi_epi32<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -2044,7 +2198,12 @@ pub fn _mm_mask_shrdi_epi32<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shrdi_epi32<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shrdi_epi32<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_shrdi_epi32::<IMM8>(a, b).as_i32x4();
@@ -2060,7 +2219,8 @@ pub fn _mm_maskz_shrdi_epi32<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(2)]
-pub fn _mm512_shrdi_epi16<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_shrdi_epi16<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_shrdv_epi16(a, b, _mm512_set1_epi16(IMM8 as i16))
 }
@@ -2073,7 +2233,8 @@ pub fn _mm512_shrdi_epi16<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(4)]
-pub fn _mm512_mask_shrdi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_shrdi_epi16<const IMM8: i32>(
     src: __m512i,
     k: __mmask32,
     a: __m512i,
@@ -2094,7 +2255,12 @@ pub fn _mm512_mask_shrdi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(3)]
-pub fn _mm512_maskz_shrdi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_shrdi_epi16<const IMM8: i32>(
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm512_shrdi_epi16::<IMM8>(a, b).as_i16x32();
@@ -2110,7 +2276,8 @@ pub fn _mm512_maskz_shrdi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(2)]
-pub fn _mm256_shrdi_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_shrdi_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_shrdv_epi16(a, b, _mm256_set1_epi16(IMM8 as i16))
 }
@@ -2123,7 +2290,8 @@ pub fn _mm256_shrdi_epi16<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(4)]
-pub fn _mm256_mask_shrdi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_shrdi_epi16<const IMM8: i32>(
     src: __m256i,
     k: __mmask16,
     a: __m256i,
@@ -2144,7 +2312,12 @@ pub fn _mm256_mask_shrdi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(3)]
-pub fn _mm256_maskz_shrdi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_shrdi_epi16<const IMM8: i32>(
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm256_shrdi_epi16::<IMM8>(a, b).as_i16x16();
@@ -2160,7 +2333,8 @@ pub fn _mm256_maskz_shrdi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i, b: __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(2)]
-pub fn _mm_shrdi_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_shrdi_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_shrdv_epi16(a, b, _mm_set1_epi16(IMM8 as i16))
 }
@@ -2173,7 +2347,8 @@ pub fn _mm_shrdi_epi16<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(4)]
-pub fn _mm_mask_shrdi_epi16<const IMM8: i32>(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_shrdi_epi16<const IMM8: i32>(
     src: __m128i,
     k: __mmask8,
     a: __m128i,
@@ -2194,7 +2369,12 @@ pub fn _mm_mask_shrdi_epi16<const IMM8: i32>(
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw
 #[rustc_legacy_const_generics(3)]
-pub fn _mm_maskz_shrdi_epi16<const IMM8: i32>(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_shrdi_epi16<const IMM8: i32>(
+    k: __mmask8,
+    a: __m128i,
+    b: __m128i,
+) -> __m128i {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
         let shf = _mm_shrdi_epi16::<IMM8>(a, b).as_i16x8();
@@ -2262,6 +2442,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
 
     use stdarch_test::simd_test;
 
@@ -2581,7 +2762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shldv_epi64() {
+    const unsafe fn test_mm512_shldv_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let c = _mm512_set1_epi64(2);
@@ -2591,7 +2772,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shldv_epi64() {
+    const unsafe fn test_mm512_mask_shldv_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let c = _mm512_set1_epi64(2);
@@ -2603,7 +2784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shldv_epi64() {
+    const unsafe fn test_mm512_maskz_shldv_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let c = _mm512_set1_epi64(2);
@@ -2615,7 +2796,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shldv_epi64() {
+    const unsafe fn test_mm256_shldv_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let c = _mm256_set1_epi64x(2);
@@ -2625,7 +2806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shldv_epi64() {
+    const unsafe fn test_mm256_mask_shldv_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let c = _mm256_set1_epi64x(2);
@@ -2637,7 +2818,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shldv_epi64() {
+    const unsafe fn test_mm256_maskz_shldv_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let c = _mm256_set1_epi64x(2);
@@ -2649,7 +2830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shldv_epi64() {
+    const unsafe fn test_mm_shldv_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let c = _mm_set1_epi64x(2);
@@ -2659,7 +2840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shldv_epi64() {
+    const unsafe fn test_mm_mask_shldv_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let c = _mm_set1_epi64x(2);
@@ -2671,7 +2852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shldv_epi64() {
+    const unsafe fn test_mm_maskz_shldv_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let c = _mm_set1_epi64x(2);
@@ -2683,7 +2864,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shldv_epi32() {
+    const unsafe fn test_mm512_shldv_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let c = _mm512_set1_epi32(2);
@@ -2693,7 +2874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shldv_epi32() {
+    const unsafe fn test_mm512_mask_shldv_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let c = _mm512_set1_epi32(2);
@@ -2705,7 +2886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shldv_epi32() {
+    const unsafe fn test_mm512_maskz_shldv_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let c = _mm512_set1_epi32(2);
@@ -2717,7 +2898,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shldv_epi32() {
+    const unsafe fn test_mm256_shldv_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let c = _mm256_set1_epi32(2);
@@ -2727,7 +2908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shldv_epi32() {
+    const unsafe fn test_mm256_mask_shldv_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let c = _mm256_set1_epi32(2);
@@ -2739,7 +2920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shldv_epi32() {
+    const unsafe fn test_mm256_maskz_shldv_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let c = _mm256_set1_epi32(2);
@@ -2751,7 +2932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shldv_epi32() {
+    const unsafe fn test_mm_shldv_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let c = _mm_set1_epi32(2);
@@ -2761,7 +2942,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shldv_epi32() {
+    const unsafe fn test_mm_mask_shldv_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let c = _mm_set1_epi32(2);
@@ -2773,7 +2954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shldv_epi32() {
+    const unsafe fn test_mm_maskz_shldv_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let c = _mm_set1_epi32(2);
@@ -2785,7 +2966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shldv_epi16() {
+    const unsafe fn test_mm512_shldv_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let c = _mm512_set1_epi16(2);
@@ -2795,7 +2976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shldv_epi16() {
+    const unsafe fn test_mm512_mask_shldv_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let c = _mm512_set1_epi16(2);
@@ -2807,7 +2988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shldv_epi16() {
+    const unsafe fn test_mm512_maskz_shldv_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let c = _mm512_set1_epi16(2);
@@ -2819,7 +3000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shldv_epi16() {
+    const unsafe fn test_mm256_shldv_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let c = _mm256_set1_epi16(2);
@@ -2829,7 +3010,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shldv_epi16() {
+    const unsafe fn test_mm256_mask_shldv_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let c = _mm256_set1_epi16(2);
@@ -2841,7 +3022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shldv_epi16() {
+    const unsafe fn test_mm256_maskz_shldv_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let c = _mm256_set1_epi16(2);
@@ -2853,7 +3034,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shldv_epi16() {
+    const unsafe fn test_mm_shldv_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let c = _mm_set1_epi16(2);
@@ -2863,7 +3044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shldv_epi16() {
+    const unsafe fn test_mm_mask_shldv_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let c = _mm_set1_epi16(2);
@@ -2875,7 +3056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shldv_epi16() {
+    const unsafe fn test_mm_maskz_shldv_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let c = _mm_set1_epi16(2);
@@ -2887,7 +3068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shrdv_epi64() {
+    const unsafe fn test_mm512_shrdv_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let c = _mm512_set1_epi64(1);
@@ -2897,7 +3078,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shrdv_epi64() {
+    const unsafe fn test_mm512_mask_shrdv_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let c = _mm512_set1_epi64(1);
@@ -2909,7 +3090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shrdv_epi64() {
+    const unsafe fn test_mm512_maskz_shrdv_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let c = _mm512_set1_epi64(1);
@@ -2921,7 +3102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shrdv_epi64() {
+    const unsafe fn test_mm256_shrdv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let c = _mm256_set1_epi64x(1);
@@ -2931,7 +3112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shrdv_epi64() {
+    const unsafe fn test_mm256_mask_shrdv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let c = _mm256_set1_epi64x(1);
@@ -2943,7 +3124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shrdv_epi64() {
+    const unsafe fn test_mm256_maskz_shrdv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let c = _mm256_set1_epi64x(1);
@@ -2955,7 +3136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shrdv_epi64() {
+    const unsafe fn test_mm_shrdv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let c = _mm_set1_epi64x(1);
@@ -2965,7 +3146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shrdv_epi64() {
+    const unsafe fn test_mm_mask_shrdv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let c = _mm_set1_epi64x(1);
@@ -2977,7 +3158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shrdv_epi64() {
+    const unsafe fn test_mm_maskz_shrdv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let c = _mm_set1_epi64x(1);
@@ -2989,7 +3170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shrdv_epi32() {
+    const unsafe fn test_mm512_shrdv_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let c = _mm512_set1_epi32(1);
@@ -2999,7 +3180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shrdv_epi32() {
+    const unsafe fn test_mm512_mask_shrdv_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let c = _mm512_set1_epi32(1);
@@ -3011,7 +3192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shrdv_epi32() {
+    const unsafe fn test_mm512_maskz_shrdv_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let c = _mm512_set1_epi32(1);
@@ -3023,7 +3204,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shrdv_epi32() {
+    const unsafe fn test_mm256_shrdv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let c = _mm256_set1_epi32(1);
@@ -3033,7 +3214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shrdv_epi32() {
+    const unsafe fn test_mm256_mask_shrdv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let c = _mm256_set1_epi32(1);
@@ -3045,7 +3226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shrdv_epi32() {
+    const unsafe fn test_mm256_maskz_shrdv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let c = _mm256_set1_epi32(1);
@@ -3057,7 +3238,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shrdv_epi32() {
+    const unsafe fn test_mm_shrdv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let c = _mm_set1_epi32(1);
@@ -3067,7 +3248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shrdv_epi32() {
+    const unsafe fn test_mm_mask_shrdv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let c = _mm_set1_epi32(1);
@@ -3079,7 +3260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shrdv_epi32() {
+    const unsafe fn test_mm_maskz_shrdv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let c = _mm_set1_epi32(1);
@@ -3091,7 +3272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shrdv_epi16() {
+    const unsafe fn test_mm512_shrdv_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let c = _mm512_set1_epi16(1);
@@ -3101,7 +3282,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shrdv_epi16() {
+    const unsafe fn test_mm512_mask_shrdv_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let c = _mm512_set1_epi16(1);
@@ -3113,7 +3294,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shrdv_epi16() {
+    const unsafe fn test_mm512_maskz_shrdv_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let c = _mm512_set1_epi16(1);
@@ -3125,7 +3306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shrdv_epi16() {
+    const unsafe fn test_mm256_shrdv_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let c = _mm256_set1_epi16(1);
@@ -3135,7 +3316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shrdv_epi16() {
+    const unsafe fn test_mm256_mask_shrdv_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let c = _mm256_set1_epi16(1);
@@ -3147,7 +3328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shrdv_epi16() {
+    const unsafe fn test_mm256_maskz_shrdv_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let c = _mm256_set1_epi16(1);
@@ -3159,7 +3340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shrdv_epi16() {
+    const unsafe fn test_mm_shrdv_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let c = _mm_set1_epi16(1);
@@ -3169,7 +3350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shrdv_epi16() {
+    const unsafe fn test_mm_mask_shrdv_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let c = _mm_set1_epi16(1);
@@ -3181,7 +3362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shrdv_epi16() {
+    const unsafe fn test_mm_maskz_shrdv_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let c = _mm_set1_epi16(1);
@@ -3193,7 +3374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shldi_epi64() {
+    const unsafe fn test_mm512_shldi_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let r = _mm512_shldi_epi64::<2>(a, b);
@@ -3202,7 +3383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shldi_epi64() {
+    const unsafe fn test_mm512_mask_shldi_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let r = _mm512_mask_shldi_epi64::<2>(a, 0, a, b);
@@ -3213,7 +3394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shldi_epi64() {
+    const unsafe fn test_mm512_maskz_shldi_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let r = _mm512_maskz_shldi_epi64::<2>(0, a, b);
@@ -3224,7 +3405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shldi_epi64() {
+    const unsafe fn test_mm256_shldi_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let r = _mm256_shldi_epi64::<2>(a, b);
@@ -3233,7 +3414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shldi_epi64() {
+    const unsafe fn test_mm256_mask_shldi_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let r = _mm256_mask_shldi_epi64::<2>(a, 0, a, b);
@@ -3244,7 +3425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shldi_epi64() {
+    const unsafe fn test_mm256_maskz_shldi_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let r = _mm256_maskz_shldi_epi64::<2>(0, a, b);
@@ -3255,7 +3436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shldi_epi64() {
+    const unsafe fn test_mm_shldi_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let r = _mm_shldi_epi64::<2>(a, b);
@@ -3264,7 +3445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shldi_epi64() {
+    const unsafe fn test_mm_mask_shldi_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let r = _mm_mask_shldi_epi64::<2>(a, 0, a, b);
@@ -3275,7 +3456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shldi_epi64() {
+    const unsafe fn test_mm_maskz_shldi_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let r = _mm_maskz_shldi_epi64::<2>(0, a, b);
@@ -3286,7 +3467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shldi_epi32() {
+    const unsafe fn test_mm512_shldi_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let r = _mm512_shldi_epi32::<2>(a, b);
@@ -3295,7 +3476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shldi_epi32() {
+    const unsafe fn test_mm512_mask_shldi_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let r = _mm512_mask_shldi_epi32::<2>(a, 0, a, b);
@@ -3306,7 +3487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shldi_epi32() {
+    const unsafe fn test_mm512_maskz_shldi_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let r = _mm512_maskz_shldi_epi32::<2>(0, a, b);
@@ -3317,7 +3498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shldi_epi32() {
+    const unsafe fn test_mm256_shldi_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let r = _mm256_shldi_epi32::<2>(a, b);
@@ -3326,7 +3507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shldi_epi32() {
+    const unsafe fn test_mm256_mask_shldi_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let r = _mm256_mask_shldi_epi32::<2>(a, 0, a, b);
@@ -3337,7 +3518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shldi_epi32() {
+    const unsafe fn test_mm256_maskz_shldi_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let r = _mm256_maskz_shldi_epi32::<2>(0, a, b);
@@ -3348,7 +3529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shldi_epi32() {
+    const unsafe fn test_mm_shldi_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let r = _mm_shldi_epi32::<2>(a, b);
@@ -3357,7 +3538,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shldi_epi32() {
+    const unsafe fn test_mm_mask_shldi_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let r = _mm_mask_shldi_epi32::<2>(a, 0, a, b);
@@ -3368,7 +3549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shldi_epi32() {
+    const unsafe fn test_mm_maskz_shldi_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let r = _mm_maskz_shldi_epi32::<2>(0, a, b);
@@ -3379,7 +3560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shldi_epi16() {
+    const unsafe fn test_mm512_shldi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let r = _mm512_shldi_epi16::<2>(a, b);
@@ -3388,7 +3569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shldi_epi16() {
+    const unsafe fn test_mm512_mask_shldi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let r = _mm512_mask_shldi_epi16::<2>(a, 0, a, b);
@@ -3399,7 +3580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shldi_epi16() {
+    const unsafe fn test_mm512_maskz_shldi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let r = _mm512_maskz_shldi_epi16::<2>(0, a, b);
@@ -3410,7 +3591,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shldi_epi16() {
+    const unsafe fn test_mm256_shldi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let r = _mm256_shldi_epi16::<2>(a, b);
@@ -3419,7 +3600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shldi_epi16() {
+    const unsafe fn test_mm256_mask_shldi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let r = _mm256_mask_shldi_epi16::<2>(a, 0, a, b);
@@ -3430,7 +3611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shldi_epi16() {
+    const unsafe fn test_mm256_maskz_shldi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let r = _mm256_maskz_shldi_epi16::<2>(0, a, b);
@@ -3441,7 +3622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shldi_epi16() {
+    const unsafe fn test_mm_shldi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let r = _mm_shldi_epi16::<2>(a, b);
@@ -3450,7 +3631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shldi_epi16() {
+    const unsafe fn test_mm_mask_shldi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let r = _mm_mask_shldi_epi16::<2>(a, 0, a, b);
@@ -3461,7 +3642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shldi_epi16() {
+    const unsafe fn test_mm_maskz_shldi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let r = _mm_maskz_shldi_epi16::<2>(0, a, b);
@@ -3472,7 +3653,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shrdi_epi64() {
+    const unsafe fn test_mm512_shrdi_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let r = _mm512_shrdi_epi64::<1>(a, b);
@@ -3481,7 +3662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shrdi_epi64() {
+    const unsafe fn test_mm512_mask_shrdi_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let r = _mm512_mask_shrdi_epi64::<1>(a, 0, a, b);
@@ -3492,7 +3673,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shrdi_epi64() {
+    const unsafe fn test_mm512_maskz_shrdi_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let r = _mm512_maskz_shrdi_epi64::<1>(0, a, b);
@@ -3503,7 +3684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shrdi_epi64() {
+    const unsafe fn test_mm256_shrdi_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let r = _mm256_shrdi_epi64::<1>(a, b);
@@ -3512,7 +3693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shrdi_epi64() {
+    const unsafe fn test_mm256_mask_shrdi_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let r = _mm256_mask_shrdi_epi64::<1>(a, 0, a, b);
@@ -3523,7 +3704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shrdi_epi64() {
+    const unsafe fn test_mm256_maskz_shrdi_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let r = _mm256_maskz_shrdi_epi64::<1>(0, a, b);
@@ -3534,7 +3715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shrdi_epi64() {
+    const unsafe fn test_mm_shrdi_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let r = _mm_shrdi_epi64::<1>(a, b);
@@ -3543,7 +3724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shrdi_epi64() {
+    const unsafe fn test_mm_mask_shrdi_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let r = _mm_mask_shrdi_epi64::<1>(a, 0, a, b);
@@ -3554,7 +3735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shrdi_epi64() {
+    const unsafe fn test_mm_maskz_shrdi_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let r = _mm_maskz_shrdi_epi64::<1>(0, a, b);
@@ -3565,7 +3746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shrdi_epi32() {
+    const unsafe fn test_mm512_shrdi_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let r = _mm512_shrdi_epi32::<1>(a, b);
@@ -3574,7 +3755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shrdi_epi32() {
+    const unsafe fn test_mm512_mask_shrdi_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let r = _mm512_mask_shrdi_epi32::<1>(a, 0, a, b);
@@ -3585,7 +3766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shrdi_epi32() {
+    const unsafe fn test_mm512_maskz_shrdi_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let r = _mm512_maskz_shrdi_epi32::<1>(0, a, b);
@@ -3596,7 +3777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shrdi_epi32() {
+    const unsafe fn test_mm256_shrdi_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let r = _mm256_shrdi_epi32::<1>(a, b);
@@ -3605,7 +3786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shrdi_epi32() {
+    const unsafe fn test_mm256_mask_shrdi_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let r = _mm256_mask_shrdi_epi32::<1>(a, 0, a, b);
@@ -3616,7 +3797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shrdi_epi32() {
+    const unsafe fn test_mm256_maskz_shrdi_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let r = _mm256_maskz_shrdi_epi32::<1>(0, a, b);
@@ -3627,7 +3808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shrdi_epi32() {
+    const unsafe fn test_mm_shrdi_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let r = _mm_shrdi_epi32::<1>(a, b);
@@ -3636,7 +3817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shrdi_epi32() {
+    const unsafe fn test_mm_mask_shrdi_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let r = _mm_mask_shrdi_epi32::<1>(a, 0, a, b);
@@ -3647,7 +3828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shrdi_epi32() {
+    const unsafe fn test_mm_maskz_shrdi_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let r = _mm_maskz_shrdi_epi32::<1>(0, a, b);
@@ -3658,7 +3839,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_shrdi_epi16() {
+    const unsafe fn test_mm512_shrdi_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let r = _mm512_shrdi_epi16::<1>(a, b);
@@ -3667,7 +3848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_shrdi_epi16() {
+    const unsafe fn test_mm512_mask_shrdi_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let r = _mm512_mask_shrdi_epi16::<1>(a, 0, a, b);
@@ -3678,7 +3859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_shrdi_epi16() {
+    const unsafe fn test_mm512_maskz_shrdi_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let r = _mm512_maskz_shrdi_epi16::<1>(0, a, b);
@@ -3689,7 +3870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_shrdi_epi16() {
+    const unsafe fn test_mm256_shrdi_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let r = _mm256_shrdi_epi16::<1>(a, b);
@@ -3698,7 +3879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_shrdi_epi16() {
+    const unsafe fn test_mm256_mask_shrdi_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let r = _mm256_mask_shrdi_epi16::<1>(a, 0, a, b);
@@ -3709,7 +3890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_shrdi_epi16() {
+    const unsafe fn test_mm256_maskz_shrdi_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let r = _mm256_maskz_shrdi_epi16::<1>(0, a, b);
@@ -3720,7 +3901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_shrdi_epi16() {
+    const unsafe fn test_mm_shrdi_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let r = _mm_shrdi_epi16::<1>(a, b);
@@ -3729,7 +3910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_shrdi_epi16() {
+    const unsafe fn test_mm_mask_shrdi_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let r = _mm_mask_shrdi_epi16::<1>(a, 0, a, b);
@@ -3740,7 +3921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_shrdi_epi16() {
+    const unsafe fn test_mm_maskz_shrdi_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let r = _mm_maskz_shrdi_epi16::<1>(0, a, b);

From b6db22d3e584a2ea9e4200e783a416623f4195dd Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 18:28:32 +0530
Subject: [PATCH 066/326] Make `avx512bitalg` functions const

---
 crates/core_arch/src/x86/avx512bitalg.rs | 91 ++++++++++++++----------
 1 file changed, 55 insertions(+), 36 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bitalg.rs b/crates/core_arch/src/x86/avx512bitalg.rs
index 1cbf0faea0..832a584322 100644
--- a/crates/core_arch/src/x86/avx512bitalg.rs
+++ b/crates/core_arch/src/x86/avx512bitalg.rs
@@ -43,7 +43,8 @@ unsafe extern "C" {
 #[target_feature(enable = "avx512bitalg")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm512_popcnt_epi16(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_popcnt_epi16(a: __m512i) -> __m512i {
     unsafe { transmute(simd_ctpop(a.as_i16x32())) }
 }
 
@@ -57,7 +58,8 @@ pub fn _mm512_popcnt_epi16(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bitalg")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm512_maskz_popcnt_epi16(k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_popcnt_epi16(k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -77,7 +79,8 @@ pub fn _mm512_maskz_popcnt_epi16(k: __mmask32, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bitalg")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm512_mask_popcnt_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_popcnt_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -94,7 +97,8 @@ pub fn _mm512_mask_popcnt_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m51
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm256_popcnt_epi16(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_popcnt_epi16(a: __m256i) -> __m256i {
     unsafe { transmute(simd_ctpop(a.as_i16x16())) }
 }
 
@@ -108,7 +112,8 @@ pub fn _mm256_popcnt_epi16(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm256_maskz_popcnt_epi16(k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_popcnt_epi16(k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -128,7 +133,8 @@ pub fn _mm256_maskz_popcnt_epi16(k: __mmask16, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm256_mask_popcnt_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_popcnt_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -145,7 +151,8 @@ pub fn _mm256_mask_popcnt_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m25
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm_popcnt_epi16(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_popcnt_epi16(a: __m128i) -> __m128i {
     unsafe { transmute(simd_ctpop(a.as_i16x8())) }
 }
 
@@ -159,7 +166,8 @@ pub fn _mm_popcnt_epi16(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm_maskz_popcnt_epi16(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_popcnt_epi16(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -179,7 +187,8 @@ pub fn _mm_maskz_popcnt_epi16(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntw))]
-pub fn _mm_mask_popcnt_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_popcnt_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -196,7 +205,8 @@ pub fn _mm_mask_popcnt_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bitalg")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm512_popcnt_epi8(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_popcnt_epi8(a: __m512i) -> __m512i {
     unsafe { transmute(simd_ctpop(a.as_i8x64())) }
 }
 
@@ -210,7 +220,8 @@ pub fn _mm512_popcnt_epi8(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bitalg")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm512_maskz_popcnt_epi8(k: __mmask64, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_popcnt_epi8(k: __mmask64, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -230,7 +241,8 @@ pub fn _mm512_maskz_popcnt_epi8(k: __mmask64, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bitalg")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm512_mask_popcnt_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_popcnt_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -247,7 +259,8 @@ pub fn _mm512_mask_popcnt_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm256_popcnt_epi8(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_popcnt_epi8(a: __m256i) -> __m256i {
     unsafe { transmute(simd_ctpop(a.as_i8x32())) }
 }
 
@@ -261,7 +274,8 @@ pub fn _mm256_popcnt_epi8(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm256_maskz_popcnt_epi8(k: __mmask32, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_popcnt_epi8(k: __mmask32, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -281,7 +295,8 @@ pub fn _mm256_maskz_popcnt_epi8(k: __mmask32, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm256_mask_popcnt_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_popcnt_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -298,7 +313,8 @@ pub fn _mm256_mask_popcnt_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm_popcnt_epi8(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_popcnt_epi8(a: __m128i) -> __m128i {
     unsafe { transmute(simd_ctpop(a.as_i8x16())) }
 }
 
@@ -312,7 +328,8 @@ pub fn _mm_popcnt_epi8(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm_maskz_popcnt_epi8(k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_popcnt_epi8(k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -332,7 +349,8 @@ pub fn _mm_maskz_popcnt_epi8(k: __mmask16, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bitalg,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntb))]
-pub fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -436,12 +454,13 @@ mod tests {
     // __mXXXi happens to be defined in terms of signed integers.
     #![allow(overflowing_literals)]
 
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_popcnt_epi16() {
+    const unsafe fn test_mm512_popcnt_epi16() {
         let test_data = _mm512_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF, 0xFF_FF, -1, -100, 255, 256, 2, 4, 8, 16, 32, 64, 128, 256, 512,
@@ -456,7 +475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_maskz_popcnt_epi16() {
+    const unsafe fn test_mm512_maskz_popcnt_epi16() {
         let test_data = _mm512_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF, 0xFF_FF, -1, -100, 255, 256, 2, 4, 8, 16, 32, 64, 128, 256, 512,
@@ -472,7 +491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_mask_popcnt_epi16() {
+    const unsafe fn test_mm512_mask_popcnt_epi16() {
         let test_data = _mm512_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF, 0xFF_FF, -1, -100, 255, 256, 2, 4, 8, 16, 32, 64, 128, 256, 512,
@@ -488,7 +507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_popcnt_epi16() {
+    const unsafe fn test_mm256_popcnt_epi16() {
         let test_data = _mm256_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF,
@@ -500,7 +519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_popcnt_epi16() {
+    const unsafe fn test_mm256_maskz_popcnt_epi16() {
         let test_data = _mm256_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF,
@@ -512,7 +531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_popcnt_epi16() {
+    const unsafe fn test_mm256_mask_popcnt_epi16() {
         let test_data = _mm256_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF,
@@ -526,7 +545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_popcnt_epi16() {
+    const unsafe fn test_mm_popcnt_epi16() {
         let test_data = _mm_set_epi16(0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F);
         let actual_result = _mm_popcnt_epi16(test_data);
         let reference_result = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
@@ -534,7 +553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_popcnt_epi16() {
+    const unsafe fn test_mm_maskz_popcnt_epi16() {
         let test_data = _mm_set_epi16(0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F);
         let mask = 0xF0;
         let actual_result = _mm_maskz_popcnt_epi16(mask, test_data);
@@ -543,7 +562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_mask_popcnt_epi16() {
+    const unsafe fn test_mm_mask_popcnt_epi16() {
         let test_data = _mm_set_epi16(0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F);
         let mask = 0xF0;
         let actual_result = _mm_mask_popcnt_epi16(test_data, mask, test_data);
@@ -552,7 +571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_popcnt_epi8() {
+    const unsafe fn test_mm512_popcnt_epi8() {
         let test_data = _mm512_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172, 183, 154, 84, 56, 227, 189,
@@ -569,7 +588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_maskz_popcnt_epi8() {
+    const unsafe fn test_mm512_maskz_popcnt_epi8() {
         let test_data = _mm512_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172, 183, 154, 84, 56, 227, 189,
@@ -587,7 +606,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_mask_popcnt_epi8() {
+    const unsafe fn test_mm512_mask_popcnt_epi8() {
         let test_data = _mm512_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172, 183, 154, 84, 56, 227, 189,
@@ -605,7 +624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_popcnt_epi8() {
+    const unsafe fn test_mm256_popcnt_epi8() {
         let test_data = _mm256_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172,
@@ -619,7 +638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_popcnt_epi8() {
+    const unsafe fn test_mm256_maskz_popcnt_epi8() {
         let test_data = _mm256_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 251, 73, 121, 143,
             145, 85, 91, 137, 90, 225, 21, 249, 211, 155, 228, 70,
@@ -634,7 +653,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_popcnt_epi8() {
+    const unsafe fn test_mm256_mask_popcnt_epi8() {
         let test_data = _mm256_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 251, 73, 121, 143,
             145, 85, 91, 137, 90, 225, 21, 249, 211, 155, 228, 70,
@@ -649,7 +668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_popcnt_epi8() {
+    const unsafe fn test_mm_popcnt_epi8() {
         let test_data = _mm_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64,
         );
@@ -659,7 +678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_popcnt_epi8() {
+    const unsafe fn test_mm_maskz_popcnt_epi8() {
         let test_data = _mm_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 90, 225, 21, 249, 211, 155, 228, 70,
         );
@@ -670,7 +689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_mask_popcnt_epi8() {
+    const unsafe fn test_mm_mask_popcnt_epi8() {
         let test_data = _mm_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 90, 225, 21, 249, 211, 155, 228, 70,
         );

From 7d7124af78f2e5033f56b995f54ce1109ae328d5 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:06:52 +0530
Subject: [PATCH 067/326] Make `avx512vpopcntdq` functions const

---
 crates/core_arch/src/x86/avx512vpopcntdq.rs | 91 +++++++++++++--------
 1 file changed, 55 insertions(+), 36 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512vpopcntdq.rs b/crates/core_arch/src/x86/avx512vpopcntdq.rs
index e47a14b24d..42bff33a28 100644
--- a/crates/core_arch/src/x86/avx512vpopcntdq.rs
+++ b/crates/core_arch/src/x86/avx512vpopcntdq.rs
@@ -26,7 +26,8 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "avx512vpopcntdq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm512_popcnt_epi32(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_popcnt_epi32(a: __m512i) -> __m512i {
     unsafe { transmute(simd_ctpop(a.as_i32x16())) }
 }
 
@@ -40,7 +41,8 @@ pub fn _mm512_popcnt_epi32(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vpopcntdq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm512_maskz_popcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_popcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -60,7 +62,8 @@ pub fn _mm512_maskz_popcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vpopcntdq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm512_mask_popcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_popcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -77,7 +80,8 @@ pub fn _mm512_mask_popcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m51
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm256_popcnt_epi32(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_popcnt_epi32(a: __m256i) -> __m256i {
     unsafe { transmute(simd_ctpop(a.as_i32x8())) }
 }
 
@@ -91,7 +95,8 @@ pub fn _mm256_popcnt_epi32(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm256_maskz_popcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_popcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -111,7 +116,8 @@ pub fn _mm256_maskz_popcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm256_mask_popcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_popcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -128,7 +134,8 @@ pub fn _mm256_mask_popcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm_popcnt_epi32(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_popcnt_epi32(a: __m128i) -> __m128i {
     unsafe { transmute(simd_ctpop(a.as_i32x4())) }
 }
 
@@ -142,7 +149,8 @@ pub fn _mm_popcnt_epi32(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm_maskz_popcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_popcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -162,7 +170,8 @@ pub fn _mm_maskz_popcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntd))]
-pub fn _mm_mask_popcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_popcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -179,7 +188,8 @@ pub fn _mm_mask_popcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vpopcntdq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm512_popcnt_epi64(a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_popcnt_epi64(a: __m512i) -> __m512i {
     unsafe { transmute(simd_ctpop(a.as_i64x8())) }
 }
 
@@ -193,7 +203,8 @@ pub fn _mm512_popcnt_epi64(a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vpopcntdq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm512_maskz_popcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_popcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -213,7 +224,8 @@ pub fn _mm512_maskz_popcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
 #[target_feature(enable = "avx512vpopcntdq")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm512_mask_popcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_popcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -230,7 +242,8 @@ pub fn _mm512_mask_popcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm256_popcnt_epi64(a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_popcnt_epi64(a: __m256i) -> __m256i {
     unsafe { transmute(simd_ctpop(a.as_i64x4())) }
 }
 
@@ -244,7 +257,8 @@ pub fn _mm256_popcnt_epi64(a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm256_maskz_popcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_popcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -264,7 +278,8 @@ pub fn _mm256_maskz_popcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm256_mask_popcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_popcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -281,7 +296,8 @@ pub fn _mm256_mask_popcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm_popcnt_epi64(a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_popcnt_epi64(a: __m128i) -> __m128i {
     unsafe { transmute(simd_ctpop(a.as_i64x2())) }
 }
 
@@ -295,7 +311,8 @@ pub fn _mm_popcnt_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm_maskz_popcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_popcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -315,7 +332,8 @@ pub fn _mm_maskz_popcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512vpopcntdq,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpopcntq))]
-pub fn _mm_mask_popcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_popcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
     unsafe {
         transmute(simd_select_bitmask(
             k,
@@ -327,12 +345,13 @@ pub fn _mm_mask_popcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    unsafe fn test_mm512_popcnt_epi32() {
+    const unsafe fn test_mm512_popcnt_epi32() {
         let test_data = _mm512_set_epi32(
             0,
             1,
@@ -358,7 +377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    unsafe fn test_mm512_mask_popcnt_epi32() {
+    const unsafe fn test_mm512_mask_popcnt_epi32() {
         let test_data = _mm512_set_epi32(
             0,
             1,
@@ -401,7 +420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    unsafe fn test_mm512_maskz_popcnt_epi32() {
+    const unsafe fn test_mm512_maskz_popcnt_epi32() {
         let test_data = _mm512_set_epi32(
             0,
             1,
@@ -427,7 +446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    unsafe fn test_mm256_popcnt_epi32() {
+    const unsafe fn test_mm256_popcnt_epi32() {
         let test_data = _mm256_set_epi32(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF, -100);
         let actual_result = _mm256_popcnt_epi32(test_data);
         let reference_result = _mm256_set_epi32(0, 1, 32, 1, 3, 15, 31, 28);
@@ -435,7 +454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_popcnt_epi32() {
+    const unsafe fn test_mm256_mask_popcnt_epi32() {
         let test_data = _mm256_set_epi32(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm256_mask_popcnt_epi32(test_data, mask, test_data);
@@ -444,7 +463,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_popcnt_epi32() {
+    const unsafe fn test_mm256_maskz_popcnt_epi32() {
         let test_data = _mm256_set_epi32(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm256_maskz_popcnt_epi32(mask, test_data);
@@ -453,7 +472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    unsafe fn test_mm_popcnt_epi32() {
+    const unsafe fn test_mm_popcnt_epi32() {
         let test_data = _mm_set_epi32(0, 1, -1, -100);
         let actual_result = _mm_popcnt_epi32(test_data);
         let reference_result = _mm_set_epi32(0, 1, 32, 28);
@@ -461,7 +480,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    unsafe fn test_mm_mask_popcnt_epi32() {
+    const unsafe fn test_mm_mask_popcnt_epi32() {
         let test_data = _mm_set_epi32(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm_mask_popcnt_epi32(test_data, mask, test_data);
@@ -470,7 +489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_popcnt_epi32() {
+    const unsafe fn test_mm_maskz_popcnt_epi32() {
         let test_data = _mm_set_epi32(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm_maskz_popcnt_epi32(mask, test_data);
@@ -479,7 +498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    unsafe fn test_mm512_popcnt_epi64() {
+    const unsafe fn test_mm512_popcnt_epi64() {
         let test_data = _mm512_set_epi64(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF_FF_FF_FF_FF, -100);
         let actual_result = _mm512_popcnt_epi64(test_data);
         let reference_result = _mm512_set_epi64(0, 1, 64, 1, 3, 15, 63, 60);
@@ -487,7 +506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    unsafe fn test_mm512_mask_popcnt_epi64() {
+    const unsafe fn test_mm512_mask_popcnt_epi64() {
         let test_data = _mm512_set_epi64(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF_FF_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm512_mask_popcnt_epi64(test_data, mask, test_data);
@@ -497,7 +516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    unsafe fn test_mm512_maskz_popcnt_epi64() {
+    const unsafe fn test_mm512_maskz_popcnt_epi64() {
         let test_data = _mm512_set_epi64(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF_FF_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm512_maskz_popcnt_epi64(mask, test_data);
@@ -506,7 +525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    unsafe fn test_mm256_popcnt_epi64() {
+    const unsafe fn test_mm256_popcnt_epi64() {
         let test_data = _mm256_set_epi64x(0, 1, -1, -100);
         let actual_result = _mm256_popcnt_epi64(test_data);
         let reference_result = _mm256_set_epi64x(0, 1, 64, 60);
@@ -514,7 +533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    unsafe fn test_mm256_mask_popcnt_epi64() {
+    const unsafe fn test_mm256_mask_popcnt_epi64() {
         let test_data = _mm256_set_epi64x(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm256_mask_popcnt_epi64(test_data, mask, test_data);
@@ -523,7 +542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    unsafe fn test_mm256_maskz_popcnt_epi64() {
+    const unsafe fn test_mm256_maskz_popcnt_epi64() {
         let test_data = _mm256_set_epi64x(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm256_maskz_popcnt_epi64(mask, test_data);
@@ -532,7 +551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    unsafe fn test_mm_popcnt_epi64() {
+    const unsafe fn test_mm_popcnt_epi64() {
         let test_data = _mm_set_epi64x(0, 1);
         let actual_result = _mm_popcnt_epi64(test_data);
         let reference_result = _mm_set_epi64x(0, 1);
@@ -544,7 +563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    unsafe fn test_mm_mask_popcnt_epi64() {
+    const unsafe fn test_mm_mask_popcnt_epi64() {
         let test_data = _mm_set_epi64x(0, -100);
         let mask = 0x2;
         let actual_result = _mm_mask_popcnt_epi64(test_data, mask, test_data);
@@ -558,7 +577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    unsafe fn test_mm_maskz_popcnt_epi64() {
+    const unsafe fn test_mm_maskz_popcnt_epi64() {
         let test_data = _mm_set_epi64x(0, 1);
         let mask = 0x2;
         let actual_result = _mm_maskz_popcnt_epi64(mask, test_data);

From 539894baa782ed8d3f500d4f7e36cea87763e2da Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 23 Sep 2025 19:11:35 +0530
Subject: [PATCH 068/326] Make `avx512fp16` functions const

---
 crates/core_arch/src/x86/avx512fp16.rs | 1105 ++++++++++++++----------
 crates/core_arch/src/x86/f16c.rs       |   11 +-
 2 files changed, 671 insertions(+), 445 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 7185531606..de058c3073 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -9,7 +9,8 @@ use crate::ptr;
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_set_ph(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_ph(
     e7: f16,
     e6: f16,
     e5: f16,
@@ -28,7 +29,8 @@ pub fn _mm_set_ph(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_set_ph(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set_ph(
     e15: f16,
     e14: f16,
     e13: f16,
@@ -57,7 +59,8 @@ pub fn _mm256_set_ph(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_set_ph(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set_ph(
     e31: f16,
     e30: f16,
     e29: f16,
@@ -104,7 +107,8 @@ pub fn _mm512_set_ph(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_set_sh(a: f16) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set_sh(a: f16) -> __m128h {
     __m128h([a, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0])
 }
 
@@ -114,7 +118,8 @@ pub fn _mm_set_sh(a: f16) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_set1_ph(a: f16) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_set1_ph(a: f16) -> __m128h {
     unsafe { transmute(f16x8::splat(a)) }
 }
 
@@ -124,7 +129,8 @@ pub fn _mm_set1_ph(a: f16) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_set1_ph(a: f16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_set1_ph(a: f16) -> __m256h {
     unsafe { transmute(f16x16::splat(a)) }
 }
 
@@ -134,7 +140,8 @@ pub fn _mm256_set1_ph(a: f16) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_set1_ph(a: f16) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_set1_ph(a: f16) -> __m512h {
     unsafe { transmute(f16x32::splat(a)) }
 }
 
@@ -144,7 +151,8 @@ pub fn _mm512_set1_ph(a: f16) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_setr_ph(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setr_ph(
     e0: f16,
     e1: f16,
     e2: f16,
@@ -163,7 +171,8 @@ pub fn _mm_setr_ph(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_setr_ph(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setr_ph(
     e0: f16,
     e1: f16,
     e2: f16,
@@ -192,7 +201,8 @@ pub fn _mm256_setr_ph(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_setr_ph(
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setr_ph(
     e0: f16,
     e1: f16,
     e2: f16,
@@ -238,7 +248,8 @@ pub fn _mm512_setr_ph(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_setzero_ph() -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_setzero_ph() -> __m128h {
     unsafe { transmute(f16x8::ZERO) }
 }
 
@@ -248,7 +259,8 @@ pub fn _mm_setzero_ph() -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_setzero_ph() -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_setzero_ph() -> __m256h {
     f16x16::ZERO.as_m256h()
 }
 
@@ -258,7 +270,8 @@ pub fn _mm256_setzero_ph() -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_setzero_ph() -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_setzero_ph() -> __m512h {
     f16x32::ZERO.as_m512h()
 }
 
@@ -271,7 +284,8 @@ pub fn _mm512_setzero_ph() -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_undefined_ph() -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_undefined_ph() -> __m128h {
     f16x8::ZERO.as_m128h()
 }
 
@@ -284,7 +298,8 @@ pub fn _mm_undefined_ph() -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_undefined_ph() -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_undefined_ph() -> __m256h {
     f16x16::ZERO.as_m256h()
 }
 
@@ -297,7 +312,8 @@ pub fn _mm256_undefined_ph() -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_undefined_ph() -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_undefined_ph() -> __m512h {
     f16x32::ZERO.as_m512h()
 }
 
@@ -308,7 +324,8 @@ pub fn _mm512_undefined_ph() -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_castpd_ph(a: __m128d) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castpd_ph(a: __m128d) -> __m128h {
     unsafe { transmute(a) }
 }
 
@@ -319,7 +336,8 @@ pub fn _mm_castpd_ph(a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castpd_ph(a: __m256d) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h {
     unsafe { transmute(a) }
 }
 
@@ -330,7 +348,8 @@ pub fn _mm256_castpd_ph(a: __m256d) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castpd_ph(a: __m512d) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h {
     unsafe { transmute(a) }
 }
 
@@ -341,7 +360,8 @@ pub fn _mm512_castpd_ph(a: __m512d) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_castph_pd(a: __m128h) -> __m128d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castph_pd(a: __m128h) -> __m128d {
     unsafe { transmute(a) }
 }
 
@@ -352,7 +372,8 @@ pub fn _mm_castph_pd(a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castph_pd(a: __m256h) -> __m256d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castph_pd(a: __m256h) -> __m256d {
     unsafe { transmute(a) }
 }
 
@@ -363,7 +384,8 @@ pub fn _mm256_castph_pd(a: __m256h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph_pd(a: __m512h) -> __m512d {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph_pd(a: __m512h) -> __m512d {
     unsafe { transmute(a) }
 }
 
@@ -374,7 +396,8 @@ pub fn _mm512_castph_pd(a: __m512h) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_castps_ph(a: __m128) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castps_ph(a: __m128) -> __m128h {
     unsafe { transmute(a) }
 }
 
@@ -385,7 +408,8 @@ pub fn _mm_castps_ph(a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castps_ph(a: __m256) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castps_ph(a: __m256) -> __m256h {
     unsafe { transmute(a) }
 }
 
@@ -396,7 +420,8 @@ pub fn _mm256_castps_ph(a: __m256) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castps_ph(a: __m512) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castps_ph(a: __m512) -> __m512h {
     unsafe { transmute(a) }
 }
 
@@ -407,7 +432,8 @@ pub fn _mm512_castps_ph(a: __m512) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_castph_ps(a: __m128h) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castph_ps(a: __m128h) -> __m128 {
     unsafe { transmute(a) }
 }
 
@@ -418,7 +444,8 @@ pub fn _mm_castph_ps(a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castph_ps(a: __m256h) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castph_ps(a: __m256h) -> __m256 {
     unsafe { transmute(a) }
 }
 
@@ -429,7 +456,8 @@ pub fn _mm256_castph_ps(a: __m256h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph_ps(a: __m512h) -> __m512 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph_ps(a: __m512h) -> __m512 {
     unsafe { transmute(a) }
 }
 
@@ -440,7 +468,8 @@ pub fn _mm512_castph_ps(a: __m512h) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_castsi128_ph(a: __m128i) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h {
     unsafe { transmute(a) }
 }
 
@@ -451,7 +480,8 @@ pub fn _mm_castsi128_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
     unsafe { transmute(a) }
 }
 
@@ -462,7 +492,8 @@ pub fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
     unsafe { transmute(a) }
 }
 
@@ -473,7 +504,8 @@ pub fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_castph_si128(a: __m128h) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_castph_si128(a: __m128h) -> __m128i {
     unsafe { transmute(a) }
 }
 
@@ -484,7 +516,8 @@ pub fn _mm_castph_si128(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castph_si256(a: __m256h) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castph_si256(a: __m256h) -> __m256i {
     unsafe { transmute(a) }
 }
 
@@ -495,7 +528,8 @@ pub fn _mm256_castph_si256(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph_si512(a: __m512h) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph_si512(a: __m512h) -> __m512i {
     unsafe { transmute(a) }
 }
 
@@ -506,7 +540,8 @@ pub fn _mm512_castph_si512(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
 }
 
@@ -517,7 +552,8 @@ pub fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
 }
 
@@ -528,7 +564,8 @@ pub fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
 }
 
@@ -540,7 +577,8 @@ pub fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
     unsafe {
         simd_shuffle!(
             a,
@@ -558,7 +596,8 @@ pub fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
     unsafe {
         simd_shuffle!(
             a,
@@ -579,7 +618,8 @@ pub fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
     unsafe {
         simd_shuffle!(
             a,
@@ -600,7 +640,8 @@ pub fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
     unsafe {
         simd_shuffle!(
             a,
@@ -618,7 +659,8 @@ pub fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
     unsafe {
         simd_shuffle!(
             a,
@@ -639,7 +681,8 @@ pub fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_zextph128_ph512(a: __m128h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h {
     unsafe {
         simd_shuffle!(
             a,
@@ -1083,7 +1126,8 @@ pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm_load_ph(mem_addr: *const f16) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_ph(mem_addr: *const f16) -> __m128h {
     *mem_addr.cast()
 }
 
@@ -1094,7 +1138,8 @@ pub unsafe fn _mm_load_ph(mem_addr: *const f16) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm256_load_ph(mem_addr: *const f16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_load_ph(mem_addr: *const f16) -> __m256h {
     *mem_addr.cast()
 }
 
@@ -1105,7 +1150,8 @@ pub unsafe fn _mm256_load_ph(mem_addr: *const f16) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm512_load_ph(mem_addr: *const f16) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_load_ph(mem_addr: *const f16) -> __m512h {
     *mem_addr.cast()
 }
 
@@ -1116,7 +1162,8 @@ pub unsafe fn _mm512_load_ph(mem_addr: *const f16) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm_load_sh(mem_addr: *const f16) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_load_sh(mem_addr: *const f16) -> __m128h {
     _mm_set_sh(*mem_addr)
 }
 
@@ -1165,7 +1212,8 @@ pub unsafe fn _mm_maskz_load_sh(k: __mmask8, mem_addr: *const f16) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm_loadu_ph(mem_addr: *const f16) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_loadu_ph(mem_addr: *const f16) -> __m128h {
     ptr::read_unaligned(mem_addr.cast())
 }
 
@@ -1176,7 +1224,8 @@ pub unsafe fn _mm_loadu_ph(mem_addr: *const f16) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm256_loadu_ph(mem_addr: *const f16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_loadu_ph(mem_addr: *const f16) -> __m256h {
     ptr::read_unaligned(mem_addr.cast())
 }
 
@@ -1187,7 +1236,8 @@ pub unsafe fn _mm256_loadu_ph(mem_addr: *const f16) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h {
     ptr::read_unaligned(mem_addr.cast())
 }
 
@@ -1199,7 +1249,8 @@ pub unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mut mov: f16 = simd_extract!(src, 0);
         if (k & 1) != 0 {
@@ -1217,7 +1268,8 @@ pub fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mut mov: f16 = 0.;
         if (k & 1) != 0 {
@@ -1234,7 +1286,8 @@ pub fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mov: f16 = simd_extract!(b, 0);
         simd_insert!(a, 0, mov)
@@ -1248,7 +1301,8 @@ pub fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm_store_ph(mem_addr: *mut f16, a: __m128h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_ph(mem_addr: *mut f16, a: __m128h) {
     *mem_addr.cast() = a;
 }
 
@@ -1259,7 +1313,8 @@ pub unsafe fn _mm_store_ph(mem_addr: *mut f16, a: __m128h) {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm256_store_ph(mem_addr: *mut f16, a: __m256h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_store_ph(mem_addr: *mut f16, a: __m256h) {
     *mem_addr.cast() = a;
 }
 
@@ -1270,7 +1325,8 @@ pub unsafe fn _mm256_store_ph(mem_addr: *mut f16, a: __m256h) {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm512_store_ph(mem_addr: *mut f16, a: __m512h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_store_ph(mem_addr: *mut f16, a: __m512h) {
     *mem_addr.cast() = a;
 }
 
@@ -1280,7 +1336,8 @@ pub unsafe fn _mm512_store_ph(mem_addr: *mut f16, a: __m512h) {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm_store_sh(mem_addr: *mut f16, a: __m128h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_store_sh(mem_addr: *mut f16, a: __m128h) {
     *mem_addr = simd_extract!(a, 0);
 }
 
@@ -1307,7 +1364,8 @@ pub unsafe fn _mm_mask_store_sh(mem_addr: *mut f16, k: __mmask8, a: __m128h) {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm_storeu_ph(mem_addr: *mut f16, a: __m128h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm_storeu_ph(mem_addr: *mut f16, a: __m128h) {
     ptr::write_unaligned(mem_addr.cast(), a);
 }
 
@@ -1318,7 +1376,8 @@ pub unsafe fn _mm_storeu_ph(mem_addr: *mut f16, a: __m128h) {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm256_storeu_ph(mem_addr: *mut f16, a: __m256h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm256_storeu_ph(mem_addr: *mut f16, a: __m256h) {
     ptr::write_unaligned(mem_addr.cast(), a);
 }
 
@@ -1329,7 +1388,8 @@ pub unsafe fn _mm256_storeu_ph(mem_addr: *mut f16, a: __m256h) {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) {
     ptr::write_unaligned(mem_addr.cast(), a);
 }
 
@@ -1340,7 +1400,8 @@ pub unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_add(a, b) }
 }
 
@@ -1352,7 +1413,8 @@ pub fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_add_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -1367,7 +1429,8 @@ pub fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_add_ph(a, b);
         simd_select_bitmask(k, r, _mm_setzero_ph())
@@ -1381,7 +1444,8 @@ pub fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_add(a, b) }
 }
 
@@ -1393,7 +1457,8 @@ pub fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_add_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -1408,7 +1473,8 @@ pub fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_add_ph(a, b);
         simd_select_bitmask(k, r, _mm256_setzero_ph())
@@ -1422,7 +1488,8 @@ pub fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_add(a, b) }
 }
 
@@ -1434,7 +1501,8 @@ pub fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_add_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -1449,7 +1517,8 @@ pub fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_add_ph(a, b);
         simd_select_bitmask(k, r, _mm512_setzero_ph())
@@ -1614,7 +1683,8 @@ pub fn _mm_maskz_add_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) }
 }
 
@@ -1627,7 +1697,8 @@ pub fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let extractsrc: f16 = simd_extract!(src, 0);
         let mut add: f16 = extractsrc;
@@ -1649,7 +1720,8 @@ pub fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mut add: f16 = 0.;
         if (k & 0b00000001) != 0 {
@@ -1668,7 +1740,8 @@ pub fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_sub(a, b) }
 }
 
@@ -1680,7 +1753,8 @@ pub fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_sub_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -1695,7 +1769,8 @@ pub fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_sub_ph(a, b);
         simd_select_bitmask(k, r, _mm_setzero_ph())
@@ -1709,7 +1784,8 @@ pub fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_sub(a, b) }
 }
 
@@ -1721,7 +1797,8 @@ pub fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_sub_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -1736,7 +1813,8 @@ pub fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_sub_ph(a, b);
         simd_select_bitmask(k, r, _mm256_setzero_ph())
@@ -1750,7 +1828,8 @@ pub fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_sub(a, b) }
 }
 
@@ -1762,7 +1841,8 @@ pub fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_sub_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -1777,7 +1857,8 @@ pub fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_sub_ph(a, b);
         simd_select_bitmask(k, r, _mm512_setzero_ph())
@@ -1943,7 +2024,8 @@ pub fn _mm_maskz_sub_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) }
 }
 
@@ -1956,7 +2038,8 @@ pub fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let extractsrc: f16 = simd_extract!(src, 0);
         let mut add: f16 = extractsrc;
@@ -1978,7 +2061,8 @@ pub fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mut add: f16 = 0.;
         if (k & 0b00000001) != 0 {
@@ -1997,7 +2081,8 @@ pub fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_mul(a, b) }
 }
 
@@ -2009,7 +2094,8 @@ pub fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_mul_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -2024,7 +2110,8 @@ pub fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_mul_ph(a, b);
         simd_select_bitmask(k, r, _mm_setzero_ph())
@@ -2038,7 +2125,8 @@ pub fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_mul(a, b) }
 }
 
@@ -2050,7 +2138,8 @@ pub fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_mul_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -2065,7 +2154,8 @@ pub fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_mul_ph(a, b);
         simd_select_bitmask(k, r, _mm256_setzero_ph())
@@ -2079,7 +2169,8 @@ pub fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_mul(a, b) }
 }
 
@@ -2091,7 +2182,8 @@ pub fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_mul_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -2106,7 +2198,8 @@ pub fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_mul_ph(a, b);
         simd_select_bitmask(k, r, _mm512_setzero_ph())
@@ -2272,7 +2365,8 @@ pub fn _mm_maskz_mul_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) }
 }
 
@@ -2285,7 +2379,8 @@ pub fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let extractsrc: f16 = simd_extract!(src, 0);
         let mut add: f16 = extractsrc;
@@ -2307,7 +2402,8 @@ pub fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mut add: f16 = 0.;
         if (k & 0b00000001) != 0 {
@@ -2326,7 +2422,8 @@ pub fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_div(a, b) }
 }
 
@@ -2338,7 +2435,8 @@ pub fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_div_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -2353,7 +2451,8 @@ pub fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let r = _mm_div_ph(a, b);
         simd_select_bitmask(k, r, _mm_setzero_ph())
@@ -2367,7 +2466,8 @@ pub fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_div(a, b) }
 }
 
@@ -2379,7 +2479,8 @@ pub fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_div_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -2394,7 +2495,8 @@ pub fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
         let r = _mm256_div_ph(a, b);
         simd_select_bitmask(k, r, _mm256_setzero_ph())
@@ -2408,7 +2510,8 @@ pub fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_div(a, b) }
 }
 
@@ -2420,7 +2523,8 @@ pub fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_div_ph(a, b);
         simd_select_bitmask(k, r, src)
@@ -2435,7 +2539,8 @@ pub fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         let r = _mm512_div_ph(a, b);
         simd_select_bitmask(k, r, _mm512_setzero_ph())
@@ -2601,7 +2706,8 @@ pub fn _mm_maskz_div_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) }
 }
 
@@ -2614,7 +2720,8 @@ pub fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let extractsrc: f16 = simd_extract!(src, 0);
         let mut add: f16 = extractsrc;
@@ -2636,7 +2743,8 @@ pub fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
         let mut add: f16 = 0.;
         if (k & 0b00000001) != 0 {
@@ -3967,7 +4075,8 @@ pub fn _mm_maskz_fcmul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_abs_ph(v2: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_abs_ph(v2: __m128h) -> __m128h {
     unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) }
 }
 
@@ -3978,7 +4087,8 @@ pub fn _mm_abs_ph(v2: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_abs_ph(v2: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h {
     unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) }
 }
 
@@ -3989,7 +4099,8 @@ pub fn _mm256_abs_ph(v2: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_abs_ph(v2: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h {
     unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) }
 }
 
@@ -4002,7 +4113,8 @@ pub fn _mm512_abs_ph(v2: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_conj_pch(a: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_conj_pch(a: __m128h) -> __m128h {
     unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) }
 }
 
@@ -4015,7 +4127,8 @@ pub fn _mm_conj_pch(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
         let r: __m128 = transmute(_mm_conj_pch(a));
         transmute(simd_select_bitmask(k, r, transmute(src)))
@@ -4031,7 +4144,8 @@ pub fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_conj_pch(_mm_setzero_ph(), k, a)
 }
 
@@ -4043,7 +4157,8 @@ pub fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_conj_pch(a: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_conj_pch(a: __m256h) -> __m256h {
     unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) }
 }
 
@@ -4056,7 +4171,8 @@ pub fn _mm256_conj_pch(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h {
     unsafe {
         let r: __m256 = transmute(_mm256_conj_pch(a));
         transmute(simd_select_bitmask(k, r, transmute(src)))
@@ -4072,7 +4188,8 @@ pub fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
     _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a)
 }
 
@@ -4084,7 +4201,8 @@ pub fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_conj_pch(a: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_conj_pch(a: __m512h) -> __m512h {
     unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) }
 }
 
@@ -4097,7 +4215,8 @@ pub fn _mm512_conj_pch(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h {
     unsafe {
         let r: __m512 = transmute(_mm512_conj_pch(a));
         transmute(simd_select_bitmask(k, r, transmute(src)))
@@ -4113,7 +4232,8 @@ pub fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
     _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a)
 }
 
@@ -5198,7 +5318,8 @@ pub fn _mm_maskz_fcmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -5211,7 +5332,8 @@ pub fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) }
 }
 
@@ -5224,7 +5346,8 @@ pub fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) }
 }
 
@@ -5237,7 +5360,8 @@ pub fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) }
 }
 
@@ -5249,7 +5373,8 @@ pub fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -5262,7 +5387,8 @@ pub fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) }
 }
 
@@ -5275,7 +5401,8 @@ pub fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) }
 }
 
@@ -5288,7 +5415,8 @@ pub fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) }
 }
 
@@ -5300,7 +5428,8 @@ pub fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(a, b, c) }
 }
 
@@ -5313,7 +5442,8 @@ pub fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) }
 }
 
@@ -5326,7 +5456,8 @@ pub fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) }
 }
 
@@ -5339,7 +5470,8 @@ pub fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) }
 }
 
@@ -5470,7 +5602,8 @@ pub fn _mm512_maskz_fmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let extracta: f16 = simd_extract!(a, 0);
         let extractb: f16 = simd_extract!(b, 0);
@@ -5490,7 +5623,8 @@ pub fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fmadd: f16 = simd_extract!(a, 0);
         if k & 1 != 0 {
@@ -5512,7 +5646,8 @@ pub fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         let mut fmadd: f16 = simd_extract!(c, 0);
         if k & 1 != 0 {
@@ -5534,7 +5669,8 @@ pub fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fmadd: f16 = 0.0;
         if k & 1 != 0 {
@@ -5697,7 +5833,8 @@ pub fn _mm_maskz_fmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -5710,7 +5847,8 @@ pub fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) }
 }
 
@@ -5723,7 +5861,8 @@ pub fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) }
 }
 
@@ -5736,7 +5875,8 @@ pub fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) }
 }
 
@@ -5748,7 +5888,8 @@ pub fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -5761,7 +5902,8 @@ pub fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) }
 }
 
@@ -5774,7 +5916,8 @@ pub fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) }
 }
 
@@ -5787,7 +5930,8 @@ pub fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) }
 }
 
@@ -5799,7 +5943,8 @@ pub fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
 }
 
@@ -5812,7 +5957,8 @@ pub fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) }
 }
 
@@ -5825,7 +5971,8 @@ pub fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) }
 }
 
@@ -5838,7 +5985,8 @@ pub fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) }
 }
 
@@ -5969,7 +6117,8 @@ pub fn _mm512_maskz_fmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let extracta: f16 = simd_extract!(a, 0);
         let extractb: f16 = simd_extract!(b, 0);
@@ -5989,7 +6138,8 @@ pub fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fmsub: f16 = simd_extract!(a, 0);
         if k & 1 != 0 {
@@ -6011,7 +6161,8 @@ pub fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         let mut fmsub: f16 = simd_extract!(c, 0);
         if k & 1 != 0 {
@@ -6033,7 +6184,8 @@ pub fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fmsub: f16 = 0.0;
         if k & 1 != 0 {
@@ -6187,7 +6339,8 @@ pub fn _mm_maskz_fmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -6200,7 +6353,8 @@ pub fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) }
 }
 
@@ -6213,7 +6367,8 @@ pub fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) }
 }
 
@@ -6226,7 +6381,8 @@ pub fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) }
 }
 
@@ -6238,7 +6394,8 @@ pub fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -6251,7 +6408,8 @@ pub fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) }
 }
 
@@ -6264,7 +6422,8 @@ pub fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) }
 }
 
@@ -6277,7 +6436,8 @@ pub fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16)
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) }
 }
 
@@ -6289,7 +6449,8 @@ pub fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(simd_neg(a), b, c) }
 }
 
@@ -6302,7 +6463,8 @@ pub fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) }
 }
 
@@ -6315,7 +6477,8 @@ pub fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) }
 }
 
@@ -6328,7 +6491,8 @@ pub fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) }
 }
 
@@ -6459,7 +6623,8 @@ pub fn _mm512_maskz_fnmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let extracta: f16 = simd_extract!(a, 0);
         let extractb: f16 = simd_extract!(b, 0);
@@ -6479,7 +6644,8 @@ pub fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fnmadd: f16 = simd_extract!(a, 0);
         if k & 1 != 0 {
@@ -6501,7 +6667,8 @@ pub fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         let mut fnmadd: f16 = simd_extract!(c, 0);
         if k & 1 != 0 {
@@ -6523,7 +6690,8 @@ pub fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fnmadd: f16 = 0.0;
         if k & 1 != 0 {
@@ -6685,7 +6853,8 @@ pub fn _mm_maskz_fnmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -6698,7 +6867,8 @@ pub fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) }
 }
 
@@ -6711,7 +6881,8 @@ pub fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) }
 }
 
@@ -6724,7 +6895,8 @@ pub fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) }
 }
 
@@ -6736,7 +6908,8 @@ pub fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -6749,7 +6922,8 @@ pub fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) }
 }
 
@@ -6762,7 +6936,8 @@ pub fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) }
 }
 
@@ -6775,7 +6950,8 @@ pub fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16)
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) }
 }
 
@@ -6787,7 +6963,8 @@ pub fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
 }
 
@@ -6800,7 +6977,8 @@ pub fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) }
 }
 
@@ -6813,7 +6991,8 @@ pub fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) }
 }
 
@@ -6826,7 +7005,8 @@ pub fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) }
 }
 
@@ -6957,7 +7137,8 @@ pub fn _mm512_maskz_fnmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let extracta: f16 = simd_extract!(a, 0);
         let extractb: f16 = simd_extract!(b, 0);
@@ -6977,7 +7158,8 @@ pub fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fnmsub: f16 = simd_extract!(a, 0);
         if k & 1 != 0 {
@@ -6999,7 +7181,8 @@ pub fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         let mut fnmsub: f16 = simd_extract!(c, 0);
         if k & 1 != 0 {
@@ -7021,7 +7204,8 @@ pub fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let mut fnmsub: f16 = 0.0;
         if k & 1 != 0 {
@@ -7183,7 +7367,8 @@ pub fn _mm_maskz_fnmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -7200,7 +7385,8 @@ pub fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) }
 }
 
@@ -7213,7 +7399,8 @@ pub fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) }
 }
 
@@ -7226,7 +7413,8 @@ pub fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) }
 }
 
@@ -7238,7 +7426,8 @@ pub fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -7259,7 +7448,8 @@ pub fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) }
 }
 
@@ -7272,7 +7462,8 @@ pub fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h)
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) }
 }
 
@@ -7285,7 +7476,8 @@ pub fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) }
 }
 
@@ -7297,7 +7489,8 @@ pub fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         let add = simd_fma(a, b, c);
         let sub = simd_fma(a, b, simd_neg(c));
@@ -7321,7 +7514,8 @@ pub fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) }
 }
 
@@ -7334,7 +7528,8 @@ pub fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) }
 }
 
@@ -7347,7 +7542,8 @@ pub fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) }
 }
 
@@ -7481,7 +7677,8 @@ pub fn _mm512_maskz_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
 }
 
@@ -7494,7 +7691,8 @@ pub fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) }
 }
 
@@ -7507,7 +7705,8 @@ pub fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) }
 }
 
@@ -7520,7 +7719,8 @@ pub fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) }
 }
 
@@ -7532,7 +7732,8 @@ pub fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) ->
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
 }
 
@@ -7545,7 +7746,8 @@ pub fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) }
 }
 
@@ -7558,7 +7760,8 @@ pub fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h)
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) }
 }
 
@@ -7571,7 +7774,8 @@ pub fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) }
 }
 
@@ -7583,7 +7787,8 @@ pub fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
 }
 
@@ -7596,7 +7801,8 @@ pub fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) }
 }
 
@@ -7609,7 +7815,8 @@ pub fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) }
 }
 
@@ -7622,7 +7829,8 @@ pub fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) }
 }
 
@@ -11117,7 +11325,8 @@ pub fn _mm_maskz_reduce_round_sh<const IMM8: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_reduce_add_ph(a: __m128h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_add_ph(a: __m128h) -> f16 {
     unsafe {
         let b = simd_shuffle!(a, a, [4, 5, 6, 7, 0, 1, 2, 3]);
         let a = _mm_add_ph(a, b);
@@ -11134,7 +11343,8 @@ pub fn _mm_reduce_add_ph(a: __m128h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_reduce_add_ph(a: __m256h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_add_ph(a: __m256h) -> f16 {
     unsafe {
         let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
         let q = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -11149,7 +11359,8 @@ pub fn _mm256_reduce_add_ph(a: __m256h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_reduce_add_ph(a: __m512h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_add_ph(a: __m512h) -> f16 {
     unsafe {
         let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         let q = simd_shuffle!(
@@ -11170,7 +11381,8 @@ pub fn _mm512_reduce_add_ph(a: __m512h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_reduce_mul_ph(a: __m128h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_reduce_mul_ph(a: __m128h) -> f16 {
     unsafe {
         let b = simd_shuffle!(a, a, [4, 5, 6, 7, 0, 1, 2, 3]);
         let a = _mm_mul_ph(a, b);
@@ -11187,7 +11399,8 @@ pub fn _mm_reduce_mul_ph(a: __m128h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_reduce_mul_ph(a: __m256h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_reduce_mul_ph(a: __m256h) -> f16 {
     unsafe {
         let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
         let q = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -11202,7 +11415,8 @@ pub fn _mm256_reduce_mul_ph(a: __m256h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_reduce_mul_ph(a: __m512h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_reduce_mul_ph(a: __m512h) -> f16 {
     unsafe {
         let p = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         let q = simd_shuffle!(
@@ -11566,7 +11780,8 @@ pub fn _mm_mask_fpclass_sh_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, b, a) }
 }
 
@@ -11577,7 +11792,8 @@ pub fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, b, a) }
 }
 
@@ -11588,7 +11804,8 @@ pub fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, b, a) }
 }
 
@@ -16304,7 +16521,8 @@ pub fn _mm_maskz_cvt_roundsh_sd<const SAE: i32>(k: __mmask8, a: __m128d, b: __m1
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_cvtsh_h(a: __m128h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsh_h(a: __m128h) -> f16 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -16314,7 +16532,8 @@ pub fn _mm_cvtsh_h(a: __m128h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm256_cvtsh_h(a: __m256h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtsh_h(a: __m256h) -> f16 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -16324,7 +16543,8 @@ pub fn _mm256_cvtsh_h(a: __m256h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm512_cvtsh_h(a: __m512h) -> f16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 {
     unsafe { simd_extract!(a, 0) }
 }
 
@@ -16334,7 +16554,8 @@ pub fn _mm512_cvtsh_h(a: __m512h) -> f16 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
     unsafe { simd_extract!(a.as_i16x8(), 0) }
 }
 
@@ -16344,7 +16565,8 @@ pub fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
-pub fn _mm_cvtsi16_si128(a: i16) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i {
     unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) }
 }
 
@@ -16708,6 +16930,7 @@ unsafe extern "C" {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use crate::core_arch::x86::*;
     use crate::mem::transmute;
     use crate::ptr::{addr_of, addr_of_mut};
@@ -16737,14 +16960,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_set_ph() {
+    const unsafe fn test_mm_set_ph() {
         let r = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let e = _mm_setr_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_set_ph() {
+    const unsafe fn test_mm256_set_ph() {
         let r = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -16755,7 +16978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_set_ph() {
+    const unsafe fn test_mm512_set_ph() {
         let r = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -16770,21 +16993,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_set_sh() {
+    const unsafe fn test_mm_set_sh() {
         let r = _mm_set_sh(1.0);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_set1_ph() {
+    const unsafe fn test_mm_set1_ph() {
         let r = _mm_set1_ph(1.0);
         let e = _mm_set_ph(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_set1_ph() {
+    const unsafe fn test_mm256_set1_ph() {
         let r = _mm256_set1_ph(1.0);
         let e = _mm256_set_ph(
             1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
@@ -16793,7 +17016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_set1_ph() {
+    const unsafe fn test_mm512_set1_ph() {
         let r = _mm512_set1_ph(1.0);
         let e = _mm512_set_ph(
             1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
@@ -16803,14 +17026,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_setr_ph() {
+    const unsafe fn test_mm_setr_ph() {
         let r = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let e = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_setr_ph() {
+    const unsafe fn test_mm256_setr_ph() {
         let r = _mm256_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -16821,7 +17044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_setr_ph() {
+    const unsafe fn test_mm512_setr_ph() {
         let r = _mm512_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -16836,28 +17059,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_setzero_ph() {
+    const unsafe fn test_mm_setzero_ph() {
         let r = _mm_setzero_ph();
         let e = _mm_set1_ph(0.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_setzero_ph() {
+    const unsafe fn test_mm256_setzero_ph() {
         let r = _mm256_setzero_ph();
         let e = _mm256_set1_ph(0.0);
         assert_eq_m256h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_setzero_ph() {
+    const unsafe fn test_mm512_setzero_ph() {
         let r = _mm512_setzero_ph();
         let e = _mm512_set1_ph(0.0);
         assert_eq_m512h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_castsi128_ph() {
+    const unsafe fn test_mm_castsi128_ph() {
         let a = _mm_set1_epi16(0x3c00);
         let r = _mm_castsi128_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -16865,7 +17088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_castsi256_ph() {
+    const unsafe fn test_mm256_castsi256_ph() {
         let a = _mm256_set1_epi16(0x3c00);
         let r = _mm256_castsi256_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -16873,7 +17096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_castsi512_ph() {
+    const unsafe fn test_mm512_castsi512_ph() {
         let a = _mm512_set1_epi16(0x3c00);
         let r = _mm512_castsi512_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -16881,7 +17104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_castph_si128() {
+    const unsafe fn test_mm_castph_si128() {
         let a = _mm_set1_ph(1.0);
         let r = _mm_castph_si128(a);
         let e = _mm_set1_epi16(0x3c00);
@@ -16889,7 +17112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm256_castph_si256() {
+    const unsafe fn test_mm256_castph_si256() {
         let a = _mm256_set1_ph(1.0);
         let r = _mm256_castph_si256(a);
         let e = _mm256_set1_epi16(0x3c00);
@@ -16897,7 +17120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_castph_si512() {
+    const unsafe fn test_mm512_castph_si512() {
         let a = _mm512_set1_ph(1.0);
         let r = _mm512_castph_si512(a);
         let e = _mm512_set1_epi16(0x3c00);
@@ -16905,7 +17128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_castps_ph() {
+    const unsafe fn test_mm_castps_ph() {
         let a = _mm_castsi128_ps(_mm_set1_epi16(0x3c00));
         let r = _mm_castps_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -16913,7 +17136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_castps_ph() {
+    const unsafe fn test_mm256_castps_ph() {
         let a = _mm256_castsi256_ps(_mm256_set1_epi16(0x3c00));
         let r = _mm256_castps_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -16921,7 +17144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_castps_ph() {
+    const unsafe fn test_mm512_castps_ph() {
         let a = _mm512_castsi512_ps(_mm512_set1_epi16(0x3c00));
         let r = _mm512_castps_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -16929,7 +17152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_castph_ps() {
+    const unsafe fn test_mm_castph_ps() {
         let a = _mm_castsi128_ph(_mm_set1_epi32(0x3f800000));
         let r = _mm_castph_ps(a);
         let e = _mm_set1_ps(1.0);
@@ -16937,7 +17160,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm256_castph_ps() {
+    const unsafe fn test_mm256_castph_ps() {
         let a = _mm256_castsi256_ph(_mm256_set1_epi32(0x3f800000));
         let r = _mm256_castph_ps(a);
         let e = _mm256_set1_ps(1.0);
@@ -16945,7 +17168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_castph_ps() {
+    const unsafe fn test_mm512_castph_ps() {
         let a = _mm512_castsi512_ph(_mm512_set1_epi32(0x3f800000));
         let r = _mm512_castph_ps(a);
         let e = _mm512_set1_ps(1.0);
@@ -16953,7 +17176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_castpd_ph() {
+    const unsafe fn test_mm_castpd_ph() {
         let a = _mm_castsi128_pd(_mm_set1_epi16(0x3c00));
         let r = _mm_castpd_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -16961,7 +17184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_castpd_ph() {
+    const unsafe fn test_mm256_castpd_ph() {
         let a = _mm256_castsi256_pd(_mm256_set1_epi16(0x3c00));
         let r = _mm256_castpd_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -16969,7 +17192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_castpd_ph() {
+    const unsafe fn test_mm512_castpd_ph() {
         let a = _mm512_castsi512_pd(_mm512_set1_epi16(0x3c00));
         let r = _mm512_castpd_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -16977,7 +17200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_castph_pd() {
+    const unsafe fn test_mm_castph_pd() {
         let a = _mm_castsi128_ph(_mm_set1_epi64x(0x3ff0000000000000));
         let r = _mm_castph_pd(a);
         let e = _mm_set1_pd(1.0);
@@ -16985,7 +17208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm256_castph_pd() {
+    const unsafe fn test_mm256_castph_pd() {
         let a = _mm256_castsi256_ph(_mm256_set1_epi64x(0x3ff0000000000000));
         let r = _mm256_castph_pd(a);
         let e = _mm256_set1_pd(1.0);
@@ -16993,7 +17216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_castph_pd() {
+    const unsafe fn test_mm512_castph_pd() {
         let a = _mm512_castsi512_ph(_mm512_set1_epi64(0x3ff0000000000000));
         let r = _mm512_castph_pd(a);
         let e = _mm512_set1_pd(1.0);
@@ -17001,7 +17224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_castph256_ph128() {
+    const unsafe fn test_mm256_castph256_ph128() {
         let a = _mm256_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -17011,7 +17234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_castph512_ph128() {
+    const unsafe fn test_mm512_castph512_ph128() {
         let a = _mm512_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19.,
             20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
@@ -17022,7 +17245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_castph512_ph256() {
+    const unsafe fn test_mm512_castph512_ph256() {
         let a = _mm512_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19.,
             20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
@@ -17035,21 +17258,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_castph128_ph256() {
+    const unsafe fn test_mm256_castph128_ph256() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_castph128_ph256(a);
         assert_eq_m128h(_mm256_castph256_ph128(r), a);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_castph128_ph512() {
+    const unsafe fn test_mm512_castph128_ph512() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_castph128_ph512(a);
         assert_eq_m128h(_mm512_castph512_ph128(r), a);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_castph256_ph512() {
+    const unsafe fn test_mm512_castph256_ph512() {
         let a = _mm256_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -17058,7 +17281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_zextph128_ph256() {
+    const unsafe fn test_mm256_zextph128_ph256() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_zextph128_ph256(a);
         let e = _mm256_setr_ph(
@@ -17068,7 +17291,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_zextph128_ph512() {
+    const unsafe fn test_mm512_zextph128_ph512() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_zextph128_ph512(a);
         let e = _mm512_setr_ph(
@@ -17079,7 +17302,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_zextph256_ph512() {
+    const unsafe fn test_mm512_zextph256_ph512() {
         let a = _mm256_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -17346,14 +17569,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_load_ph() {
+    const unsafe fn test_mm_load_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_load_ph(addr_of!(a).cast());
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_load_ph() {
+    const unsafe fn test_mm256_load_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17362,7 +17585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_load_ph() {
+    const unsafe fn test_mm512_load_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17373,7 +17596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_load_sh() {
+    const unsafe fn test_mm_load_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_load_sh(addr_of!(a).cast());
         assert_eq_m128h(a, b);
@@ -17399,7 +17622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_loadu_ph() {
+    const unsafe fn test_mm_loadu_ph() {
         let array = [1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let r = _mm_loadu_ph(array.as_ptr());
         let e = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -17407,7 +17630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_loadu_ph() {
+    const unsafe fn test_mm256_loadu_ph() {
         let array = [
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ];
@@ -17419,7 +17642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_loadu_ph() {
+    const unsafe fn test_mm512_loadu_ph() {
         let array = [
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17435,7 +17658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_move_sh() {
+    const unsafe fn test_mm_move_sh() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_sh(9.0);
         let r = _mm_move_sh(a, b);
@@ -17444,7 +17667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_move_sh() {
+    const unsafe fn test_mm_mask_move_sh() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_sh(9.0);
         let src = _mm_set_sh(10.0);
@@ -17454,7 +17677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_move_sh() {
+    const unsafe fn test_mm_maskz_move_sh() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_sh(9.0);
         let r = _mm_maskz_move_sh(0, a, b);
@@ -17463,7 +17686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_store_ph() {
+    const unsafe fn test_mm_store_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let mut b = _mm_setzero_ph();
         _mm_store_ph(addr_of_mut!(b).cast(), a);
@@ -17471,7 +17694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_store_ph() {
+    const unsafe fn test_mm256_store_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17481,7 +17704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_store_ph() {
+    const unsafe fn test_mm512_store_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17493,7 +17716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_store_sh() {
+    const unsafe fn test_mm_store_sh() {
         let a = _mm_set_sh(1.0);
         let mut b = _mm_setzero_ph();
         _mm_store_sh(addr_of_mut!(b).cast(), a);
@@ -17511,7 +17734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_storeu_ph() {
+    const unsafe fn test_mm_storeu_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let mut array = [0.0; 8];
         _mm_storeu_ph(array.as_mut_ptr(), a);
@@ -17519,7 +17742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_storeu_ph() {
+    const unsafe fn test_mm256_storeu_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17529,7 +17752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_storeu_ph() {
+    const unsafe fn test_mm512_storeu_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17541,7 +17764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_add_ph() {
+    const unsafe fn test_mm_add_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_add_ph(a, b);
@@ -17550,7 +17773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_add_ph() {
+    const unsafe fn test_mm_mask_add_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
@@ -17560,7 +17783,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_add_ph() {
+    const unsafe fn test_mm_maskz_add_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_maskz_add_ph(0b01010101, a, b);
@@ -17569,7 +17792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_add_ph() {
+    const unsafe fn test_mm256_add_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17582,7 +17805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_add_ph() {
+    const unsafe fn test_mm256_mask_add_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17600,7 +17823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_add_ph() {
+    const unsafe fn test_mm256_maskz_add_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17615,7 +17838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_add_ph() {
+    const unsafe fn test_mm512_add_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17632,7 +17855,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_add_ph() {
+    const unsafe fn test_mm512_mask_add_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17656,7 +17879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_add_ph() {
+    const unsafe fn test_mm512_maskz_add_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17786,7 +18009,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_add_sh() {
+    const unsafe fn test_mm_add_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_add_sh(a, b);
@@ -17795,7 +18018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_add_sh() {
+    const unsafe fn test_mm_mask_add_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -17808,7 +18031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_add_sh() {
+    const unsafe fn test_mm_maskz_add_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_add_sh(0, a, b);
@@ -17820,7 +18043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_sub_ph() {
+    const unsafe fn test_mm_sub_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_sub_ph(a, b);
@@ -17829,7 +18052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_sub_ph() {
+    const unsafe fn test_mm_mask_sub_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
@@ -17839,7 +18062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_sub_ph() {
+    const unsafe fn test_mm_maskz_sub_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_maskz_sub_ph(0b01010101, a, b);
@@ -17848,7 +18071,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_sub_ph() {
+    const unsafe fn test_mm256_sub_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17864,7 +18087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_sub_ph() {
+    const unsafe fn test_mm256_mask_sub_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17882,7 +18105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_sub_ph() {
+    const unsafe fn test_mm256_maskz_sub_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17897,7 +18120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_sub_ph() {
+    const unsafe fn test_mm512_sub_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17918,7 +18141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_sub_ph() {
+    const unsafe fn test_mm512_mask_sub_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17942,7 +18165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_sub_ph() {
+    const unsafe fn test_mm512_maskz_sub_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18076,7 +18299,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_sub_sh() {
+    const unsafe fn test_mm_sub_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_sub_sh(a, b);
@@ -18085,7 +18308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_sub_sh() {
+    const unsafe fn test_mm_mask_sub_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18098,7 +18321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_sub_sh() {
+    const unsafe fn test_mm_maskz_sub_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_sub_sh(0, a, b);
@@ -18110,7 +18333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mul_ph() {
+    const unsafe fn test_mm_mul_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_mul_ph(a, b);
@@ -18119,7 +18342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_mul_ph() {
+    const unsafe fn test_mm_mask_mul_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
@@ -18129,7 +18352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_mul_ph() {
+    const unsafe fn test_mm_maskz_mul_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_maskz_mul_ph(0b01010101, a, b);
@@ -18138,7 +18361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mul_ph() {
+    const unsafe fn test_mm256_mul_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18154,7 +18377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_mul_ph() {
+    const unsafe fn test_mm256_mask_mul_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18172,7 +18395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_mul_ph() {
+    const unsafe fn test_mm256_maskz_mul_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18187,7 +18410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mul_ph() {
+    const unsafe fn test_mm512_mul_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18208,7 +18431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_mul_ph() {
+    const unsafe fn test_mm512_mask_mul_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18232,7 +18455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_mul_ph() {
+    const unsafe fn test_mm512_maskz_mul_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18366,7 +18589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mul_sh() {
+    const unsafe fn test_mm_mul_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_mul_sh(a, b);
@@ -18375,7 +18598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_mul_sh() {
+    const unsafe fn test_mm_mask_mul_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18388,7 +18611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_mul_sh() {
+    const unsafe fn test_mm_maskz_mul_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_mul_sh(0, a, b);
@@ -18400,7 +18623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_div_ph() {
+    const unsafe fn test_mm_div_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let r = _mm_div_ph(a, b);
@@ -18409,7 +18632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_div_ph() {
+    const unsafe fn test_mm_mask_div_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let src = _mm_set_ph(4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0);
@@ -18419,7 +18642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_div_ph() {
+    const unsafe fn test_mm_maskz_div_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let r = _mm_maskz_div_ph(0b01010101, a, b);
@@ -18428,7 +18651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_div_ph() {
+    const unsafe fn test_mm256_div_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let r = _mm256_div_ph(a, b);
@@ -18437,7 +18660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_div_ph() {
+    const unsafe fn test_mm256_mask_div_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let src = _mm256_set_ph(
@@ -18452,7 +18675,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_div_ph() {
+    const unsafe fn test_mm256_maskz_div_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let r = _mm256_maskz_div_ph(0b0101010101010101, a, b);
@@ -18463,7 +18686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_div_ph() {
+    const unsafe fn test_mm512_div_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let r = _mm512_div_ph(a, b);
@@ -18472,7 +18695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_div_ph() {
+    const unsafe fn test_mm512_mask_div_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let src = _mm512_set_ph(
@@ -18489,7 +18712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_div_ph() {
+    const unsafe fn test_mm512_maskz_div_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let r = _mm512_maskz_div_ph(0b01010101010101010101010101010101, a, b);
@@ -18588,7 +18811,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_div_sh() {
+    const unsafe fn test_mm_div_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_div_sh(a, b);
@@ -18597,7 +18820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_div_sh() {
+    const unsafe fn test_mm_mask_div_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18610,7 +18833,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_div_sh() {
+    const unsafe fn test_mm_maskz_div_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_div_sh(0, a, b);
@@ -19454,7 +19677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_abs_ph() {
+    const unsafe fn test_mm_abs_ph() {
         let a = _mm_set_ph(-1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0);
         let r = _mm_abs_ph(a);
         let e = _mm_set_ph(1.0, 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0);
@@ -19462,7 +19685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_abs_ph() {
+    const unsafe fn test_mm256_abs_ph() {
         let a = _mm256_set_ph(
             -1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0,
             -14.0,
@@ -19475,7 +19698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_abs_ph() {
+    const unsafe fn test_mm512_abs_ph() {
         let a = _mm512_set_ph(
             -1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0,
             -14.0, 15.0, -16.0, 17.0, -18.0, 19.0, -20.0, 21.0, -22.0, 23.0, -24.0, 25.0, -26.0,
@@ -19491,7 +19714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_conj_pch() {
+    const unsafe fn test_mm_conj_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let r = _mm_conj_pch(a);
         let e = _mm_set1_pch(0.0, -1.0);
@@ -19499,7 +19722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_conj_pch() {
+    const unsafe fn test_mm_mask_conj_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
         let r = _mm_mask_conj_pch(src, 0b0101, a);
@@ -19508,7 +19731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_conj_pch() {
+    const unsafe fn test_mm_maskz_conj_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let r = _mm_maskz_conj_pch(0b0101, a);
         let e = _mm_setr_ph(0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0);
@@ -19516,7 +19739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_conj_pch() {
+    const unsafe fn test_mm256_conj_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_conj_pch(a);
         let e = _mm256_set1_pch(0.0, -1.0);
@@ -19524,7 +19747,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_conj_pch() {
+    const unsafe fn test_mm256_mask_conj_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let src = _mm256_setr_ph(
             2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
@@ -19537,7 +19760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_conj_pch() {
+    const unsafe fn test_mm256_maskz_conj_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_maskz_conj_pch(0b01010101, a);
         let e = _mm256_setr_ph(
@@ -19547,7 +19770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_conj_pch() {
+    const unsafe fn test_mm512_conj_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_conj_pch(a);
         let e = _mm512_set1_pch(0.0, -1.0);
@@ -19555,7 +19778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_conj_pch() {
+    const unsafe fn test_mm512_mask_conj_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let src = _mm512_setr_ph(
             2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
@@ -19572,7 +19795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_conj_pch() {
+    const unsafe fn test_mm512_maskz_conj_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_maskz_conj_pch(0b0101010101010101, a);
         let e = _mm512_setr_ph(
@@ -20203,7 +20426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmadd_ph() {
+    const unsafe fn test_mm_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20213,7 +20436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_ph() {
+    const unsafe fn test_mm_mask_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20223,7 +20446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_ph() {
+    const unsafe fn test_mm_mask3_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20233,7 +20456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_ph() {
+    const unsafe fn test_mm_maskz_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20243,7 +20466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fmadd_ph() {
+    const unsafe fn test_mm256_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20253,7 +20476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fmadd_ph() {
+    const unsafe fn test_mm256_mask_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20265,7 +20488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fmadd_ph() {
+    const unsafe fn test_mm256_mask3_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20277,7 +20500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fmadd_ph() {
+    const unsafe fn test_mm256_maskz_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20289,7 +20512,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmadd_ph() {
+    const unsafe fn test_mm512_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20299,7 +20522,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmadd_ph() {
+    const unsafe fn test_mm512_mask_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20312,7 +20535,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmadd_ph() {
+    const unsafe fn test_mm512_mask3_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20325,7 +20548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmadd_ph() {
+    const unsafe fn test_mm512_maskz_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20402,7 +20625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmadd_sh() {
+    const unsafe fn test_mm_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20412,7 +20635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_sh() {
+    const unsafe fn test_mm_mask_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20425,7 +20648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_sh() {
+    const unsafe fn test_mm_mask3_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20438,7 +20661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_sh() {
+    const unsafe fn test_mm_maskz_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20512,7 +20735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmsub_ph() {
+    const unsafe fn test_mm_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20522,7 +20745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmsub_ph() {
+    const unsafe fn test_mm_mask_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20532,7 +20755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmsub_ph() {
+    const unsafe fn test_mm_mask3_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20542,7 +20765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmsub_ph() {
+    const unsafe fn test_mm_maskz_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20552,7 +20775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fmsub_ph() {
+    const unsafe fn test_mm256_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20562,7 +20785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fmsub_ph() {
+    const unsafe fn test_mm256_mask_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20574,7 +20797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fmsub_ph() {
+    const unsafe fn test_mm256_mask3_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20586,7 +20809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fmsub_ph() {
+    const unsafe fn test_mm256_maskz_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20598,7 +20821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmsub_ph() {
+    const unsafe fn test_mm512_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20608,7 +20831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmsub_ph() {
+    const unsafe fn test_mm512_mask_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20621,7 +20844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmsub_ph() {
+    const unsafe fn test_mm512_mask3_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20634,7 +20857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmsub_ph() {
+    const unsafe fn test_mm512_maskz_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20711,7 +20934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmsub_sh() {
+    const unsafe fn test_mm_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20721,7 +20944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmsub_sh() {
+    const unsafe fn test_mm_mask_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20734,7 +20957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmsub_sh() {
+    const unsafe fn test_mm_mask3_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20747,7 +20970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmsub_sh() {
+    const unsafe fn test_mm_maskz_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20821,7 +21044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fnmadd_ph() {
+    const unsafe fn test_mm_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20831,7 +21054,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fnmadd_ph() {
+    const unsafe fn test_mm_mask_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20841,7 +21064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fnmadd_ph() {
+    const unsafe fn test_mm_mask3_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20851,7 +21074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fnmadd_ph() {
+    const unsafe fn test_mm_maskz_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20861,7 +21084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fnmadd_ph() {
+    const unsafe fn test_mm256_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20871,7 +21094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fnmadd_ph() {
+    const unsafe fn test_mm256_mask_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20883,7 +21106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fnmadd_ph() {
+    const unsafe fn test_mm256_mask3_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20895,7 +21118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fnmadd_ph() {
+    const unsafe fn test_mm256_maskz_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20907,7 +21130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fnmadd_ph() {
+    const unsafe fn test_mm512_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20917,7 +21140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fnmadd_ph() {
+    const unsafe fn test_mm512_mask_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20930,7 +21153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fnmadd_ph() {
+    const unsafe fn test_mm512_mask3_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20943,7 +21166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fnmadd_ph() {
+    const unsafe fn test_mm512_maskz_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21021,7 +21244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fnmadd_sh() {
+    const unsafe fn test_mm_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21031,7 +21254,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fnmadd_sh() {
+    const unsafe fn test_mm_mask_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21044,7 +21267,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fnmadd_sh() {
+    const unsafe fn test_mm_mask3_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21057,7 +21280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fnmadd_sh() {
+    const unsafe fn test_mm_maskz_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21131,7 +21354,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fnmsub_ph() {
+    const unsafe fn test_mm_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21141,7 +21364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fnmsub_ph() {
+    const unsafe fn test_mm_mask_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21151,7 +21374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fnmsub_ph() {
+    const unsafe fn test_mm_mask3_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21161,7 +21384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fnmsub_ph() {
+    const unsafe fn test_mm_maskz_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21171,7 +21394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fnmsub_ph() {
+    const unsafe fn test_mm256_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21181,7 +21404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fnmsub_ph() {
+    const unsafe fn test_mm256_mask_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21193,7 +21416,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fnmsub_ph() {
+    const unsafe fn test_mm256_mask3_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21205,7 +21428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fnmsub_ph() {
+    const unsafe fn test_mm256_maskz_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21217,7 +21440,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fnmsub_ph() {
+    const unsafe fn test_mm512_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21227,7 +21450,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fnmsub_ph() {
+    const unsafe fn test_mm512_mask_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21240,7 +21463,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fnmsub_ph() {
+    const unsafe fn test_mm512_mask3_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21253,7 +21476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fnmsub_ph() {
+    const unsafe fn test_mm512_maskz_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21331,7 +21554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fnmsub_sh() {
+    const unsafe fn test_mm_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21341,7 +21564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fnmsub_sh() {
+    const unsafe fn test_mm_mask_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21354,7 +21577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fnmsub_sh() {
+    const unsafe fn test_mm_mask3_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21367,7 +21590,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fnmsub_sh() {
+    const unsafe fn test_mm_maskz_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21441,7 +21664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmaddsub_ph() {
+    const unsafe fn test_mm_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21451,7 +21674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmaddsub_ph() {
+    const unsafe fn test_mm_mask_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21461,7 +21684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmaddsub_ph() {
+    const unsafe fn test_mm_mask3_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21471,7 +21694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmaddsub_ph() {
+    const unsafe fn test_mm_maskz_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21481,7 +21704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fmaddsub_ph() {
+    const unsafe fn test_mm256_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21493,7 +21716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fmaddsub_ph() {
+    const unsafe fn test_mm256_mask_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21505,7 +21728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fmaddsub_ph() {
+    const unsafe fn test_mm256_mask3_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21517,7 +21740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fmaddsub_ph() {
+    const unsafe fn test_mm256_maskz_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21529,7 +21752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmaddsub_ph() {
+    const unsafe fn test_mm512_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21542,7 +21765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmaddsub_ph() {
+    const unsafe fn test_mm512_mask_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21555,7 +21778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmaddsub_ph() {
+    const unsafe fn test_mm512_mask3_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21568,7 +21791,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmaddsub_ph() {
+    const unsafe fn test_mm512_maskz_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21649,7 +21872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmsubadd_ph() {
+    const unsafe fn test_mm_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21659,7 +21882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmsubadd_ph() {
+    const unsafe fn test_mm_mask_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21669,7 +21892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmsubadd_ph() {
+    const unsafe fn test_mm_mask3_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21679,7 +21902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmsubadd_ph() {
+    const unsafe fn test_mm_maskz_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21689,7 +21912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fmsubadd_ph() {
+    const unsafe fn test_mm256_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21701,7 +21924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fmsubadd_ph() {
+    const unsafe fn test_mm256_mask_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21713,7 +21936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fmsubadd_ph() {
+    const unsafe fn test_mm256_mask3_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21725,7 +21948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fmsubadd_ph() {
+    const unsafe fn test_mm256_maskz_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21737,7 +21960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmsubadd_ph() {
+    const unsafe fn test_mm512_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21750,7 +21973,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmsubadd_ph() {
+    const unsafe fn test_mm512_mask_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21763,7 +21986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmsubadd_ph() {
+    const unsafe fn test_mm512_mask3_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21776,7 +21999,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmsubadd_ph() {
+    const unsafe fn test_mm512_maskz_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -23741,42 +23964,42 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_add_ph() {
+    const unsafe fn test_mm_reduce_add_ph() {
         let a = _mm_set1_ph(2.0);
         let r = _mm_reduce_add_ph(a);
         assert_eq!(r, 16.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_reduce_add_ph() {
+    const unsafe fn test_mm256_reduce_add_ph() {
         let a = _mm256_set1_ph(2.0);
         let r = _mm256_reduce_add_ph(a);
         assert_eq!(r, 32.0);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_reduce_add_ph() {
+    const unsafe fn test_mm512_reduce_add_ph() {
         let a = _mm512_set1_ph(2.0);
         let r = _mm512_reduce_add_ph(a);
         assert_eq!(r, 64.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_mul_ph() {
+    const unsafe fn test_mm_reduce_mul_ph() {
         let a = _mm_set1_ph(2.0);
         let r = _mm_reduce_mul_ph(a);
         assert_eq!(r, 256.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_reduce_mul_ph() {
+    const unsafe fn test_mm256_reduce_mul_ph() {
         let a = _mm256_set1_ph(2.0);
         let r = _mm256_reduce_mul_ph(a);
         assert_eq!(r, 65536.0);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_reduce_mul_ph() {
+    const unsafe fn test_mm512_reduce_mul_ph() {
         let a = _mm512_set1_ph(2.0);
         let r = _mm512_reduce_mul_ph(a);
         assert_eq!(r, 16777216.0);
@@ -24013,7 +24236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_blend_ph() {
+    const unsafe fn test_mm_mask_blend_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(-1.0, -2.0, -3.0, -4.0, -5.0, -6.0, -7.0, -8.0);
         let r = _mm_mask_blend_ph(0b01010101, a, b);
@@ -24022,7 +24245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_blend_ph() {
+    const unsafe fn test_mm256_mask_blend_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -24039,7 +24262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_blend_ph() {
+    const unsafe fn test_mm512_mask_blend_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -27310,14 +27533,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_h() {
+    const unsafe fn test_mm_cvtsh_h() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtsh_h(a);
         assert_eq!(r, 1.0);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm256_cvtsh_h() {
+    const unsafe fn test_mm256_cvtsh_h() {
         let a = _mm256_setr_ph(
             1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -27326,7 +27549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtsh_h() {
+    const unsafe fn test_mm512_cvtsh_h() {
         let a = _mm512_setr_ph(
             1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -27337,14 +27560,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsi128_si16() {
+    const unsafe fn test_mm_cvtsi128_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_cvtsi128_si16(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsi16_si128() {
+    const unsafe fn test_mm_cvtsi16_si128() {
         let a = 1;
         let r = _mm_cvtsi16_si128(a);
         let e = _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0);
diff --git a/crates/core_arch/src/x86/f16c.rs b/crates/core_arch/src/x86/f16c.rs
index 519cc38294..09971939ba 100644
--- a/crates/core_arch/src/x86/f16c.rs
+++ b/crates/core_arch/src/x86/f16c.rs
@@ -25,7 +25,8 @@ unsafe extern "unadjusted" {
 #[target_feature(enable = "f16c")]
 #[cfg_attr(test, assert_instr("vcvtph2ps"))]
 #[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")]
-pub fn _mm_cvtph_ps(a: __m128i) -> __m128 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_cvtph_ps(a: __m128i) -> __m128 {
     unsafe {
         let a: f16x8 = transmute(a);
         let a: f16x4 = simd_shuffle!(a, a, [0, 1, 2, 3]);
@@ -41,7 +42,8 @@ pub fn _mm_cvtph_ps(a: __m128i) -> __m128 {
 #[target_feature(enable = "f16c")]
 #[cfg_attr(test, assert_instr("vcvtph2ps"))]
 #[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")]
-pub fn _mm256_cvtph_ps(a: __m128i) -> __m256 {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_cvtph_ps(a: __m128i) -> __m256 {
     unsafe {
         let a: f16x8 = transmute(a);
         simd_cast(a)
@@ -103,6 +105,7 @@ pub fn _mm256_cvtps_ph<const IMM_ROUNDING: i32>(a: __m256) -> __m128i {
 
 #[cfg(test)]
 mod tests {
+    use crate::core_arch::assert_eq_const as assert_eq;
     use crate::{core_arch::x86::*, mem::transmute};
     use stdarch_test::simd_test;
 
@@ -116,7 +119,7 @@ mod tests {
     const F16_EIGHT: i16 = 0x4800;
 
     #[simd_test(enable = "f16c")]
-    unsafe fn test_mm_cvtph_ps() {
+    const unsafe fn test_mm_cvtph_ps() {
         let a = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
         let r = _mm_cvtph_ps(a);
         let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
@@ -124,7 +127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "f16c")]
-    unsafe fn test_mm256_cvtph_ps() {
+    const unsafe fn test_mm256_cvtph_ps() {
         let a = _mm_set_epi16(
             F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT,
         );

From 9cfc7d379e0a4016b9a995de11f85df6448e9328 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Fri, 24 Oct 2025 10:15:30 +0100
Subject: [PATCH 069/326] Modifies CI to pass profile to test tool

---
 .github/workflows/main.yml                   |  4 +--
 ci/intrinsic-test-docker.sh                  |  1 +
 ci/intrinsic-test.sh                         | 21 ++++++++------
 ci/run-docker.sh                             |  1 +
 ci/run.sh                                    | 30 ++++++++++----------
 crates/intrinsic-test/src/common/cli.rs      |  7 +++++
 crates/intrinsic-test/src/common/compare.rs  | 16 +++++++++--
 crates/intrinsic-test/src/common/gen_rust.rs |  9 ++++--
 crates/intrinsic-test/src/common/mod.rs      |  4 ++-
 9 files changed, 62 insertions(+), 31 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 28c15cf473..92083443e4 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -220,7 +220,7 @@ jobs:
       if: matrix.build_std != ''
 
     # Configure some env vars based on matrix configuration
-    - run: echo "PROFILE=--profile=${{matrix.profile}}" >> $GITHUB_ENV
+    - run: echo "PROFILE=${{matrix.profile}}" >> $GITHUB_ENV
       shell: bash
     - run: echo "NORUN=1" >> $GITHUB_ENV
       shell: bash
@@ -280,7 +280,7 @@ jobs:
       if: ${{ matrix.build_std }}
 
     # Configure some env vars based on matrix configuration
-    - run: echo "PROFILE=--profile=${{ matrix.profile }}" >> $GITHUB_ENV
+    - run: echo "PROFILE=${{ matrix.profile }}" >> $GITHUB_ENV
     - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }}
       if: ${{ !startsWith(matrix.target, 'thumb') }}
       env:
diff --git a/ci/intrinsic-test-docker.sh b/ci/intrinsic-test-docker.sh
index f62d7e484f..beeff42c76 100755
--- a/ci/intrinsic-test-docker.sh
+++ b/ci/intrinsic-test-docker.sh
@@ -30,6 +30,7 @@ run() {
       --env CARGO_HOME=/cargo \
       --env CARGO_TARGET_DIR=/checkout/target \
       --env TARGET="${1}" \
+      --env PROFILE \
       --env "${HOST_LINKER}"="cc" \
       --env STDARCH_DISABLE_ASSERT_INSTR \
       --env NOSTD \
diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index ff76a0c769..89104e2672 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -6,7 +6,7 @@ set -ex
 
 export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir"
 export HOST_RUSTFLAGS="${RUSTFLAGS}"
-export PROFILE="${PROFILE:="--profile=release"}"
+export PROFILE="${PROFILE:="release"}"
 
 case ${TARGET} in
     # On 32-bit use a static relocation model which avoids some extra
@@ -85,27 +85,29 @@ esac
 # Arm specific
 case "${TARGET}" in
     aarch64-unknown-linux-gnu*|armv7-unknown-linux-gnueabihf*)
-        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=info \
-            cargo run "${INTRINSIC_TEST}" "${PROFILE}" \
+        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \
+            cargo run "${INTRINSIC_TEST}" --release  \
             --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \
             --runner "${TEST_RUNNER}" \
             --cppcompiler "${TEST_CXX_COMPILER}" \
             --skip "${TEST_SKIP_INTRINSICS}" \
             --target "${TARGET}" \
+            --profile "${PROFILE}" \
             --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}"
         ;;
 
     aarch64_be-unknown-linux-gnu*)
-        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=info \
-            cargo run "${INTRINSIC_TEST}" "${PROFILE}"  \
+        CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \
+            cargo run "${INTRINSIC_TEST}" --release  \
             --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \
             --runner "${TEST_RUNNER}" \
             --cppcompiler "${TEST_CXX_COMPILER}" \
             --skip "${TEST_SKIP_INTRINSICS}" \
             --target "${TARGET}" \
-            --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" \
+            --profile "${PROFILE}" \
             --linker "${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER}" \
-            --cxx-toolchain-dir "${AARCH64_BE_TOOLCHAIN}"
+            --cxx-toolchain-dir "${AARCH64_BE_TOOLCHAIN}" \
+            --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}"
         ;;
 
     x86_64-unknown-linux-gnu*)
@@ -114,13 +116,14 @@ case "${TARGET}" in
         # Hence the use of `env -u`.
         env -u CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER \
             CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" \
-            RUST_LOG=info RUST_BACKTRACE=1 \
-            cargo run "${INTRINSIC_TEST}" "${PROFILE}"  \
+            RUST_LOG=warn RUST_BACKTRACE=1 \
+            cargo run "${INTRINSIC_TEST}" --release \
             --bin intrinsic-test -- intrinsics_data/x86-intel.xml \
             --runner "${TEST_RUNNER}" \
             --skip "${TEST_SKIP_INTRINSICS}" \
             --cppcompiler "${TEST_CXX_COMPILER}" \
             --target "${TARGET}" \
+            --profile "${PROFILE}" \
             --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}"
         ;;
      *)
diff --git a/ci/run-docker.sh b/ci/run-docker.sh
index d7aa50a8c9..28dfd5a24a 100755
--- a/ci/run-docker.sh
+++ b/ci/run-docker.sh
@@ -37,6 +37,7 @@ run() {
       --env NORUN \
       --env RUSTFLAGS \
       --env CARGO_UNSTABLE_BUILD_STD \
+      --env PROFILE \
       --volume "${HOME}/.cargo":/cargo \
       --volume "$(rustc --print sysroot)":/rust:ro \
       --volume "$(pwd)":/checkout:ro \
diff --git a/ci/run.sh b/ci/run.sh
index 2bb77bae25..a8925c470a 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -12,7 +12,7 @@ set -ex
 
 export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir"
 export HOST_RUSTFLAGS="${RUSTFLAGS}"
-export PROFILE="${PROFILE:="--profile=release"}"
+export PROFILE="${PROFILE:="release"}"
 
 case ${TARGET} in
     # On Windows the linker performs identical COMDAT folding (ICF) by default
@@ -63,7 +63,7 @@ cargo_test() {
     if [ "$NORUN" = "1" ]; then
         export subcmd="build"
     fi
-    cmd="$cmd ${subcmd} --target=$TARGET $1"
+    cmd="$cmd ${subcmd} --target=$TARGET --profile=$PROFILE $1"
     cmd="$cmd -- $2"
 
     case ${TARGET} in
@@ -80,10 +80,10 @@ cargo_test() {
 CORE_ARCH="--manifest-path=crates/core_arch/Cargo.toml"
 STDARCH_EXAMPLES="--manifest-path=examples/Cargo.toml"
 
-cargo_test "${CORE_ARCH} ${PROFILE}"
+cargo_test "${CORE_ARCH}"
 
 if [ "$NOSTD" != "1" ]; then
-    cargo_test "${STDARCH_EXAMPLES} ${PROFILE}"
+    cargo_test "${STDARCH_EXAMPLES}"
 fi
 
 
@@ -93,41 +93,41 @@ case ${TARGET} in
         export STDARCH_DISABLE_ASSERT_INSTR=1
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
-        cargo_test "${PROFILE}"
+        cargo_test 
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx512f"
-        cargo_test "${PROFILE}"
+        cargo_test 
         ;;
     x86_64* | i686*)
         export STDARCH_DISABLE_ASSERT_INSTR=1
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
-        cargo_test "${PROFILE}"
+        cargo_test 
         ;;
     # FIXME: don't build anymore
     #mips-*gnu* | mipsel-*gnu*)
     #    export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+msa,+fp64,+mips32r5"
-    #    cargo_test "${PROFILE}"
+    #    cargo_test 
 	  #    ;;
     mips64*)
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+msa"
-        cargo_test "${PROFILE}"
+        cargo_test 
 	      ;;
     s390x*)
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+vector-enhancements-1"
-        cargo_test "${PROFILE}"
+        cargo_test 
 	      ;;
     powerpc64*)
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+altivec"
-        cargo_test "${PROFILE}"
+        cargo_test 
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+vsx"
-        cargo_test "${PROFILE}"
+        cargo_test 
         ;;
     powerpc*)
         # qemu has a bug in PPC32 which leads to a crash when compiled with `vsx`
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+altivec"
-        cargo_test "${PROFILE}"
+        cargo_test 
         ;;
     *)
         ;;
@@ -138,7 +138,7 @@ if [ "$NORUN" != "1" ] && [ "$NOSTD" != 1 ]; then
     # Test examples
     (
         cd examples
-        cargo test --target "$TARGET" "${PROFILE}"
-        echo test | cargo run --target "$TARGET" "${PROFILE}" hex
+        cargo test --target "${TARGET}" --profile "${PROFILE}"
+        echo test | cargo run --target "${TARGET}" --profile "${PROFILE}" hex
     )
 fi
diff --git a/crates/intrinsic-test/src/common/cli.rs b/crates/intrinsic-test/src/common/cli.rs
index ff34ef3d2d..bed8259de8 100644
--- a/crates/intrinsic-test/src/common/cli.rs
+++ b/crates/intrinsic-test/src/common/cli.rs
@@ -41,6 +41,10 @@ pub struct Cli {
     #[arg(long, default_value_t = String::from("armv7-unknown-linux-gnueabihf"))]
     pub target: String,
 
+    /// Pass a profile (release, dev)
+    #[arg(long, default_value_t = String::from("release"))]
+    pub profile: String,
+
     /// Set the linker
     #[arg(long)]
     pub linker: Option<String>,
@@ -59,6 +63,7 @@ pub struct ProcessedCli {
     pub cpp_compiler: Option<String>,
     pub runner: String,
     pub target: String,
+    pub profile: String,
     pub linker: Option<String>,
     pub cxx_toolchain_dir: Option<String>,
     pub skip: Vec<String>,
@@ -70,6 +75,7 @@ impl ProcessedCli {
         let filename = cli_options.input;
         let runner = cli_options.runner.unwrap_or_default();
         let target = cli_options.target;
+        let profile = cli_options.profile;
         let linker = cli_options.linker;
         let cxx_toolchain_dir = cli_options.cxx_toolchain_dir;
         let sample_percentage = cli_options.sample_percentage;
@@ -103,6 +109,7 @@ impl ProcessedCli {
             cpp_compiler,
             runner,
             target,
+            profile,
             linker,
             cxx_toolchain_dir,
             skip,
diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index c4c2a1e3e4..5214349171 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -11,7 +11,17 @@ fn runner_command(runner: &str) -> Command {
     cmd
 }
 
-pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target: &str) -> bool {
+pub fn compare_outputs(
+    intrinsic_name_list: &Vec<String>,
+    runner: &str,
+    target: &str,
+    profile: &str,
+) -> bool {
+    let profile_dir = match profile {
+        "dev" => "debug",
+        _ => "release",
+    };
+
     let (c, rust) = rayon::join(
         || {
             runner_command(runner)
@@ -21,7 +31,9 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         },
         || {
             runner_command(runner)
-                .arg(format!("./target/{target}/release/intrinsic-test-programs"))
+                .arg(format!(
+                    "./target/{target}/{profile_dir}/intrinsic-test-programs"
+                ))
                 .current_dir("rust_programs")
                 .output()
         },
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index fb047e2612..82b97701bb 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -140,7 +140,12 @@ pub fn write_lib_rs<T: IntrinsicTypeDefinition>(
     Ok(())
 }
 
-pub fn compile_rust_programs(toolchain: Option<&str>, target: &str, linker: Option<&str>) -> bool {
+pub fn compile_rust_programs(
+    toolchain: Option<&str>,
+    target: &str,
+    profile: &str,
+    linker: Option<&str>,
+) -> bool {
     /* If there has been a linker explicitly set from the command line then
      * we want to set it via setting it in the RUSTFLAGS*/
 
@@ -161,7 +166,7 @@ pub fn compile_rust_programs(toolchain: Option<&str>, target: &str, linker: Opti
     if toolchain.is_some_and(|val| !val.is_empty()) {
         cargo_command.arg(toolchain.unwrap());
     }
-    cargo_command.args(["build", "--target", target, "--release"]);
+    cargo_command.args(["build", "--target", target, "--profile", profile]);
 
     let mut rust_flags = "-Cdebuginfo=0".to_string();
     if let Some(linker) = linker {
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index 8b6bd943a7..a1062b3a87 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -146,6 +146,7 @@ pub trait SupportedArchitectureTest {
         .unwrap();
 
         let target = &self.cli_options().target;
+        let profile = &self.cli_options().profile;
         let toolchain = self.cli_options().toolchain.as_deref();
         let linker = self.cli_options().linker.as_deref();
 
@@ -178,7 +179,7 @@ pub trait SupportedArchitectureTest {
             .collect::<Result<(), std::io::Error>>()
             .unwrap();
 
-        compile_rust_programs(toolchain, target, linker)
+        compile_rust_programs(toolchain, target, profile, linker)
     }
 
     fn compare_outputs(&self) -> bool {
@@ -193,6 +194,7 @@ pub trait SupportedArchitectureTest {
                 &intrinsics_name_list,
                 &self.cli_options().runner,
                 &self.cli_options().target,
+                &self.cli_options().profile,
             )
         } else {
             true

From a32c9cdbd4647adcbc97d83df48430863c8a0427 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Tue, 28 Oct 2025 12:19:12 +0000
Subject: [PATCH 070/326] Fixes hardcoded path for WASM runner

---
 ci/docker/wasm32-wasip1/Dockerfile | 2 --
 ci/run.sh                          | 6 ++++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/ci/docker/wasm32-wasip1/Dockerfile b/ci/docker/wasm32-wasip1/Dockerfile
index 0527c0df17..cb4a9b2948 100644
--- a/ci/docker/wasm32-wasip1/Dockerfile
+++ b/ci/docker/wasm32-wasip1/Dockerfile
@@ -11,5 +11,3 @@ ENV VERSION=v38.0.3
 
 RUN curl -L https://github.com/bytecodealliance/wasmtime/releases/download/${VERSION}/wasmtime-${VERSION}-x86_64-linux.tar.xz | tar xJf -
 ENV PATH=$PATH:/wasmtime-${VERSION}-x86_64-linux
-
-ENV CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime -Wexceptions --dir /checkout/target/wasm32-wasip1/release/deps::."
diff --git a/ci/run.sh b/ci/run.sh
index a8925c470a..f40a305117 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -71,6 +71,12 @@ cargo_test() {
         # harness isn't trying to capture output, otherwise we won't get any useful
         # output.
         wasm32*)
+            if [ "$PROFILE" = "release" ]; then
+              dir="release"
+            else
+              dir="debug"
+            fi
+            export CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime -Wexceptions --dir /checkout/target/wasm32-wasip1/$dir/deps::."
             cmd="$cmd --nocapture"
             ;;
     esac

From b1726c2d0e879e4e61f606be5a662eb98a99cac0 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Thu, 4 Dec 2025 12:18:28 +0000
Subject: [PATCH 071/326] Removes excess x86_64 test runs

---
 ci/run.sh | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/ci/run.sh b/ci/run.sh
index f40a305117..58d9a60e34 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -95,15 +95,6 @@ fi
 
 # Test targets compiled with extra features.
 case ${TARGET} in
-    x86_64-unknown-linux-gnu)
-        export STDARCH_DISABLE_ASSERT_INSTR=1
-
-        export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
-        cargo_test 
-
-        export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx512f"
-        cargo_test 
-        ;;
     x86_64* | i686*)
         export STDARCH_DISABLE_ASSERT_INSTR=1
 

From 9df16e3c2bde4b0d641467c7218b9ce202931d78 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 28 Aug 2025 04:34:53 +0530
Subject: [PATCH 072/326] (Partially) Stabilize AVX512-FP16, except for
 functions that explicitly use `f16` in the signature

---
 crates/core_arch/src/x86/avx512fp16.rs    | 1762 ++++++++++-----------
 crates/core_arch/src/x86/avxneconvert.rs  |    8 +-
 crates/core_arch/src/x86/mod.rs           |    4 +-
 crates/core_arch/src/x86_64/avx512fp16.rs |   24 +-
 crates/core_arch/src/x86_64/mod.rs        |    2 +-
 5 files changed, 900 insertions(+), 900 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index de058c3073..df53a1b294 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -247,7 +247,7 @@ pub const fn _mm512_setr_ph(
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_setzero_ph() -> __m128h {
     unsafe { transmute(f16x8::ZERO) }
@@ -258,7 +258,7 @@ pub const fn _mm_setzero_ph() -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_setzero_ph() -> __m256h {
     f16x16::ZERO.as_m256h()
@@ -269,7 +269,7 @@ pub const fn _mm256_setzero_ph() -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_setzero_ph() -> __m512h {
     f16x32::ZERO.as_m512h()
@@ -283,7 +283,7 @@ pub const fn _mm512_setzero_ph() -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_undefined_ph() -> __m128h {
     f16x8::ZERO.as_m128h()
@@ -297,7 +297,7 @@ pub const fn _mm_undefined_ph() -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_undefined_ph() -> __m256h {
     f16x16::ZERO.as_m256h()
@@ -311,7 +311,7 @@ pub const fn _mm256_undefined_ph() -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_undefined_ph() -> __m512h {
     f16x32::ZERO.as_m512h()
@@ -323,7 +323,7 @@ pub const fn _mm512_undefined_ph() -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castpd_ph(a: __m128d) -> __m128h {
     unsafe { transmute(a) }
@@ -335,7 +335,7 @@ pub const fn _mm_castpd_ph(a: __m128d) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h {
     unsafe { transmute(a) }
@@ -347,7 +347,7 @@ pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h {
     unsafe { transmute(a) }
@@ -359,7 +359,7 @@ pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_pd)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castph_pd(a: __m128h) -> __m128d {
     unsafe { transmute(a) }
@@ -371,7 +371,7 @@ pub const fn _mm_castph_pd(a: __m128h) -> __m128d {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_pd)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph_pd(a: __m256h) -> __m256d {
     unsafe { transmute(a) }
@@ -383,7 +383,7 @@ pub const fn _mm256_castph_pd(a: __m256h) -> __m256d {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_pd)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph_pd(a: __m512h) -> __m512d {
     unsafe { transmute(a) }
@@ -395,7 +395,7 @@ pub const fn _mm512_castph_pd(a: __m512h) -> __m512d {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castps_ph(a: __m128) -> __m128h {
     unsafe { transmute(a) }
@@ -407,7 +407,7 @@ pub const fn _mm_castps_ph(a: __m128) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castps_ph(a: __m256) -> __m256h {
     unsafe { transmute(a) }
@@ -419,7 +419,7 @@ pub const fn _mm256_castps_ph(a: __m256) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castps_ph(a: __m512) -> __m512h {
     unsafe { transmute(a) }
@@ -431,7 +431,7 @@ pub const fn _mm512_castps_ph(a: __m512) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_ps)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castph_ps(a: __m128h) -> __m128 {
     unsafe { transmute(a) }
@@ -443,7 +443,7 @@ pub const fn _mm_castph_ps(a: __m128h) -> __m128 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_ps)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph_ps(a: __m256h) -> __m256 {
     unsafe { transmute(a) }
@@ -455,7 +455,7 @@ pub const fn _mm256_castph_ps(a: __m256h) -> __m256 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_ps)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph_ps(a: __m512h) -> __m512 {
     unsafe { transmute(a) }
@@ -467,7 +467,7 @@ pub const fn _mm512_castph_ps(a: __m512h) -> __m512 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h {
     unsafe { transmute(a) }
@@ -479,7 +479,7 @@ pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
     unsafe { transmute(a) }
@@ -491,7 +491,7 @@ pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
     unsafe { transmute(a) }
@@ -503,7 +503,7 @@ pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_si128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castph_si128(a: __m128h) -> __m128i {
     unsafe { transmute(a) }
@@ -515,7 +515,7 @@ pub const fn _mm_castph_si128(a: __m128h) -> __m128i {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_si256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph_si256(a: __m256h) -> __m256i {
     unsafe { transmute(a) }
@@ -527,7 +527,7 @@ pub const fn _mm256_castph_si256(a: __m256h) -> __m256i {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_si512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph_si512(a: __m512h) -> __m512i {
     unsafe { transmute(a) }
@@ -539,7 +539,7 @@ pub const fn _mm512_castph_si512(a: __m512h) -> __m512i {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph256_ph128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -551,7 +551,7 @@ pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -563,7 +563,7 @@ pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
@@ -576,7 +576,7 @@ pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph128_ph256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
     unsafe {
@@ -595,7 +595,7 @@ pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph128_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
     unsafe {
@@ -617,7 +617,7 @@ pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph256_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
     unsafe {
@@ -639,7 +639,7 @@ pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
     unsafe {
@@ -658,7 +658,7 @@ pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph256_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
     unsafe {
@@ -680,7 +680,7 @@ pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph128_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h {
     unsafe {
@@ -730,7 +730,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -746,7 +746,7 @@ pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -761,7 +761,7 @@ pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -777,7 +777,7 @@ pub fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
     k1: __mmask16,
     a: __m256h,
@@ -796,7 +796,7 @@ pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -812,7 +812,7 @@ pub fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
     k1: __mmask32,
     a: __m512h,
@@ -833,7 +833,7 @@ pub fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
     a: __m512h,
     b: __m512h,
@@ -868,7 +868,7 @@ pub fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
     k1: __mmask32,
     a: __m512h,
@@ -903,7 +903,7 @@ pub fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __mmask8 {
     static_assert_uimm_bits!(IMM5, 5);
     static_assert_sae!(SAE);
@@ -918,7 +918,7 @@ pub fn _mm_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(
     k1: __mmask8,
     a: __m128h,
@@ -938,7 +938,7 @@ pub fn _mm_mask_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cmp_sh_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
     static_assert_uimm_bits!(IMM5, 5);
     _mm_cmp_round_sh_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(a, b)
@@ -951,7 +951,7 @@ pub fn _mm_cmp_sh_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cmp_sh_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
     static_assert_uimm_bits!(IMM5, 5);
     _mm_mask_cmp_round_sh_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(k1, a, b)
@@ -965,7 +965,7 @@ pub fn _mm_mask_cmp_sh_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comi_round_sh<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h) -> i32 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -981,7 +981,7 @@ pub fn _mm_comi_round_sh<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comi_sh<const IMM5: i32>(a: __m128h, b: __m128h) -> i32 {
     static_assert_uimm_bits!(IMM5, 5);
     _mm_comi_round_sh::<IMM5, _MM_FROUND_CUR_DIRECTION>(a, b)
@@ -993,7 +993,7 @@ pub fn _mm_comi_sh<const IMM5: i32>(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_EQ_OS>(a, b)
 }
@@ -1004,7 +1004,7 @@ pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GE_OS>(a, b)
 }
@@ -1015,7 +1015,7 @@ pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GT_OS>(a, b)
 }
@@ -1026,7 +1026,7 @@ pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LE_OS>(a, b)
 }
@@ -1037,7 +1037,7 @@ pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LT_OS>(a, b)
 }
@@ -1048,7 +1048,7 @@ pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_NEQ_US>(a, b)
 }
@@ -1059,7 +1059,7 @@ pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_EQ_OQ>(a, b)
 }
@@ -1070,7 +1070,7 @@ pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GE_OQ>(a, b)
 }
@@ -1081,7 +1081,7 @@ pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GT_OQ>(a, b)
 }
@@ -1092,7 +1092,7 @@ pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LE_OQ>(a, b)
 }
@@ -1103,7 +1103,7 @@ pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LT_OQ>(a, b)
 }
@@ -1114,7 +1114,7 @@ pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_NEQ_UQ>(a, b)
 }
@@ -1248,7 +1248,7 @@ pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1267,7 +1267,7 @@ pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1285,7 +1285,7 @@ pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1399,7 +1399,7 @@ pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_add(a, b) }
@@ -1412,7 +1412,7 @@ pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1428,7 +1428,7 @@ pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1443,7 +1443,7 @@ pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_add(a, b) }
@@ -1456,7 +1456,7 @@ pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1472,7 +1472,7 @@ pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1487,7 +1487,7 @@ pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_add(a, b) }
@@ -1500,7 +1500,7 @@ pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1516,7 +1516,7 @@ pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1539,7 +1539,7 @@ pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_add_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -1562,7 +1562,7 @@ pub fn _mm512_add_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_add_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -1590,7 +1590,7 @@ pub fn _mm512_mask_add_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_add_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -1618,7 +1618,7 @@ pub fn _mm512_maskz_add_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_add_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_add_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -1640,7 +1640,7 @@ pub fn _mm_add_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_add_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -1669,7 +1669,7 @@ pub fn _mm_mask_add_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_add_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_add_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -1682,7 +1682,7 @@ pub fn _mm_maskz_add_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) }
@@ -1696,7 +1696,7 @@ pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1719,7 +1719,7 @@ pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1739,7 +1739,7 @@ pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_sub(a, b) }
@@ -1752,7 +1752,7 @@ pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1768,7 +1768,7 @@ pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1783,7 +1783,7 @@ pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_sub(a, b) }
@@ -1796,7 +1796,7 @@ pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1812,7 +1812,7 @@ pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1827,7 +1827,7 @@ pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_sub(a, b) }
@@ -1840,7 +1840,7 @@ pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1856,7 +1856,7 @@ pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1879,7 +1879,7 @@ pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_sub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -1902,7 +1902,7 @@ pub fn _mm512_sub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_sub_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -1931,7 +1931,7 @@ pub fn _mm512_mask_sub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_sub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -1959,7 +1959,7 @@ pub fn _mm512_maskz_sub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_sub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_sub_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -1981,7 +1981,7 @@ pub fn _mm_sub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_sub_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -2010,7 +2010,7 @@ pub fn _mm_mask_sub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_sub_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_sub_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -2023,7 +2023,7 @@ pub fn _mm_maskz_sub_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) }
@@ -2037,7 +2037,7 @@ pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2060,7 +2060,7 @@ pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2080,7 +2080,7 @@ pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_mul(a, b) }
@@ -2093,7 +2093,7 @@ pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2109,7 +2109,7 @@ pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2124,7 +2124,7 @@ pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_mul(a, b) }
@@ -2137,7 +2137,7 @@ pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2153,7 +2153,7 @@ pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2168,7 +2168,7 @@ pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_mul(a, b) }
@@ -2181,7 +2181,7 @@ pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2197,7 +2197,7 @@ pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2220,7 +2220,7 @@ pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mul_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -2243,7 +2243,7 @@ pub fn _mm512_mul_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_mul_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -2272,7 +2272,7 @@ pub fn _mm512_mask_mul_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_mul_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -2300,7 +2300,7 @@ pub fn _mm512_maskz_mul_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mul_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_mul_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -2322,7 +2322,7 @@ pub fn _mm_mul_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_mul_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -2351,7 +2351,7 @@ pub fn _mm_mask_mul_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_mul_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_mul_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -2364,7 +2364,7 @@ pub fn _mm_maskz_mul_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) }
@@ -2378,7 +2378,7 @@ pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2401,7 +2401,7 @@ pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2421,7 +2421,7 @@ pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_div(a, b) }
@@ -2434,7 +2434,7 @@ pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2450,7 +2450,7 @@ pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2465,7 +2465,7 @@ pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_div(a, b) }
@@ -2478,7 +2478,7 @@ pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2494,7 +2494,7 @@ pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2509,7 +2509,7 @@ pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_div(a, b) }
@@ -2522,7 +2522,7 @@ pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2538,7 +2538,7 @@ pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2561,7 +2561,7 @@ pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_div_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -2584,7 +2584,7 @@ pub fn _mm512_div_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_div_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -2613,7 +2613,7 @@ pub fn _mm512_mask_div_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_div_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -2641,7 +2641,7 @@ pub fn _mm512_maskz_div_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_div_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_div_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -2663,7 +2663,7 @@ pub fn _mm_div_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_div_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -2692,7 +2692,7 @@ pub fn _mm_mask_div_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_div_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_div_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -2705,7 +2705,7 @@ pub fn _mm_maskz_div_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) }
@@ -2719,7 +2719,7 @@ pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2742,7 +2742,7 @@ pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2764,7 +2764,7 @@ pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_pch(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -2777,7 +2777,7 @@ pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { transmute(vfmulcph_128(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -2790,7 +2790,7 @@ pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_pch(_mm_setzero_ph(), k, a, b)
 }
@@ -2803,7 +2803,7 @@ pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_mul_pch(_mm256_undefined_ph(), 0xff, a, b)
 }
@@ -2816,7 +2816,7 @@ pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     unsafe { transmute(vfmulcph_256(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -2829,7 +2829,7 @@ pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_mul_pch(_mm256_setzero_ph(), k, a, b)
 }
@@ -2842,7 +2842,7 @@ pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_pch(_mm512_undefined_ph(), 0xffff, a, b)
 }
@@ -2855,7 +2855,7 @@ pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -2868,7 +2868,7 @@ pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_pch(_mm512_setzero_ph(), k, a, b)
 }
@@ -2890,7 +2890,7 @@ pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_mul_round_pch::<ROUNDING>(_mm512_undefined_ph(), 0xffff, a, b)
@@ -2913,7 +2913,7 @@ pub fn _mm512_mul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_mul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -2949,7 +2949,7 @@ pub fn _mm512_mask_mul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_mul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -2968,7 +2968,7 @@ pub fn _mm512_maskz_mul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -2982,7 +2982,7 @@ pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -2996,7 +2996,7 @@ pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -3019,7 +3019,7 @@ pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_mul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -3043,7 +3043,7 @@ pub fn _mm_mul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_mul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -3080,7 +3080,7 @@ pub fn _mm_mask_mul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_mul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -3098,7 +3098,7 @@ pub fn _mm_maskz_mul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mul_pch(a, b)
 }
@@ -3111,7 +3111,7 @@ pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_pch(src, k, a, b)
 }
@@ -3124,7 +3124,7 @@ pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_mul_pch(k, a, b)
 }
@@ -3137,7 +3137,7 @@ pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mul_pch(a, b)
 }
@@ -3150,7 +3150,7 @@ pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_mul_pch(src, k, a, b)
 }
@@ -3163,7 +3163,7 @@ pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_maskz_mul_pch(k, a, b)
 }
@@ -3175,7 +3175,7 @@ pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mul_pch(a, b)
 }
@@ -3188,7 +3188,7 @@ pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_pch(src, k, a, b)
 }
@@ -3201,7 +3201,7 @@ pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_maskz_mul_pch(k, a, b)
 }
@@ -3221,7 +3221,7 @@ pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mul_round_pch::<ROUNDING>(a, b)
@@ -3243,7 +3243,7 @@ pub fn _mm512_fmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -3270,7 +3270,7 @@ pub fn _mm512_mask_fmul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -3288,7 +3288,7 @@ pub fn _mm512_maskz_fmul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mul_sch(a, b)
 }
@@ -3301,7 +3301,7 @@ pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_sch(src, k, a, b)
 }
@@ -3314,7 +3314,7 @@ pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_mul_sch(k, a, b)
 }
@@ -3335,7 +3335,7 @@ pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mul_round_sch::<ROUNDING>(a, b)
@@ -3358,7 +3358,7 @@ pub fn _mm_fmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -3386,7 +3386,7 @@ pub fn _mm_mask_fmul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -3405,7 +3405,7 @@ pub fn _mm_maskz_fmul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_pch(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -3419,7 +3419,7 @@ pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { transmute(vfcmulcph_128(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -3433,7 +3433,7 @@ pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_pch(_mm_setzero_ph(), k, a, b)
 }
@@ -3447,7 +3447,7 @@ pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_cmul_pch(_mm256_undefined_ph(), 0xff, a, b)
 }
@@ -3461,7 +3461,7 @@ pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     unsafe { transmute(vfcmulcph_256(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -3475,7 +3475,7 @@ pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_cmul_pch(_mm256_setzero_ph(), k, a, b)
 }
@@ -3489,7 +3489,7 @@ pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_pch(_mm512_undefined_ph(), 0xffff, a, b)
 }
@@ -3503,7 +3503,7 @@ pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -3517,7 +3517,7 @@ pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_pch(_mm512_setzero_ph(), k, a, b)
 }
@@ -3540,7 +3540,7 @@ pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cmul_round_pch::<ROUNDING>(_mm512_undefined_ph(), 0xffff, a, b)
@@ -3564,7 +3564,7 @@ pub fn _mm512_cmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cmul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -3601,7 +3601,7 @@ pub fn _mm512_mask_cmul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cmul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -3619,7 +3619,7 @@ pub fn _mm512_maskz_cmul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -3633,7 +3633,7 @@ pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -3647,7 +3647,7 @@ pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -3669,7 +3669,7 @@ pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_cmul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -3693,7 +3693,7 @@ pub fn _mm_cmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cmul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -3730,7 +3730,7 @@ pub fn _mm_mask_cmul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cmul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -3749,7 +3749,7 @@ pub fn _mm_maskz_cmul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_cmul_pch(a, b)
 }
@@ -3763,7 +3763,7 @@ pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_pch(src, k, a, b)
 }
@@ -3777,7 +3777,7 @@ pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_cmul_pch(k, a, b)
 }
@@ -3791,7 +3791,7 @@ pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_cmul_pch(a, b)
 }
@@ -3805,7 +3805,7 @@ pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_cmul_pch(src, k, a, b)
 }
@@ -3819,7 +3819,7 @@ pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_maskz_cmul_pch(k, a, b)
 }
@@ -3833,7 +3833,7 @@ pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_cmul_pch(a, b)
 }
@@ -3847,7 +3847,7 @@ pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_pch(src, k, a, b)
 }
@@ -3861,7 +3861,7 @@ pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_maskz_cmul_pch(k, a, b)
 }
@@ -3883,7 +3883,7 @@ pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fcmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_cmul_round_pch::<ROUNDING>(a, b)
@@ -3907,7 +3907,7 @@ pub fn _mm512_fcmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fcmul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -3936,7 +3936,7 @@ pub fn _mm512_mask_fcmul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fcmul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -3955,7 +3955,7 @@ pub fn _mm512_maskz_fcmul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_cmul_sch(a, b)
 }
@@ -3969,7 +3969,7 @@ pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_sch(src, k, a, b)
 }
@@ -3983,7 +3983,7 @@ pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_cmul_sch(k, a, b)
 }
@@ -4005,7 +4005,7 @@ pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fcmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_cmul_round_sch::<ROUNDING>(a, b)
@@ -4029,7 +4029,7 @@ pub fn _mm_fcmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fcmul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -4058,7 +4058,7 @@ pub fn _mm_mask_fcmul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fcmul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -4074,7 +4074,7 @@ pub fn _mm_maskz_fcmul_round_sch<const ROUNDING: i32>(
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_abs_ph(v2: __m128h) -> __m128h {
     unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) }
@@ -4086,7 +4086,7 @@ pub const fn _mm_abs_ph(v2: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h {
     unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) }
@@ -4098,7 +4098,7 @@ pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h {
     unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) }
@@ -4112,7 +4112,7 @@ pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_conj_pch(a: __m128h) -> __m128h {
     unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) }
@@ -4126,7 +4126,7 @@ pub const fn _mm_conj_pch(a: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
@@ -4143,7 +4143,7 @@ pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_conj_pch(_mm_setzero_ph(), k, a)
@@ -4156,7 +4156,7 @@ pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_conj_pch(a: __m256h) -> __m256h {
     unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) }
@@ -4170,7 +4170,7 @@ pub const fn _mm256_conj_pch(a: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h {
     unsafe {
@@ -4187,7 +4187,7 @@ pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m2
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
     _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a)
@@ -4200,7 +4200,7 @@ pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_conj_pch(a: __m512h) -> __m512h {
     unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) }
@@ -4214,7 +4214,7 @@ pub const fn _mm512_conj_pch(a: __m512h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h {
     unsafe {
@@ -4231,7 +4231,7 @@ pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
     _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a)
@@ -4245,7 +4245,7 @@ pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask3_fmadd_pch(a, b, c, 0xff)
 }
@@ -4259,7 +4259,7 @@ pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let r: __m128 = transmute(_mm_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4276,7 +4276,7 @@ pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         transmute(vfmaddcph_mask3_128(
@@ -4297,7 +4297,7 @@ pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         transmute(vfmaddcph_maskz_128(
@@ -4317,7 +4317,7 @@ pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_mask3_fmadd_pch(a, b, c, 0xff)
 }
@@ -4331,7 +4331,7 @@ pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         let r: __m256 = transmute(_mm256_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4348,7 +4348,7 @@ pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h {
     unsafe {
         transmute(vfmaddcph_mask3_256(
@@ -4369,7 +4369,7 @@ pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         transmute(vfmaddcph_maskz_256(
@@ -4389,7 +4389,7 @@ pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -4403,7 +4403,7 @@ pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h {
     _mm512_mask_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -4417,7 +4417,7 @@ pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h {
     _mm512_mask3_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -4431,7 +4431,7 @@ pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_maskz_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -4453,7 +4453,7 @@ pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask3_fmadd_round_pch::<ROUNDING>(a, b, c, 0xffff)
@@ -4477,7 +4477,7 @@ pub fn _mm512_fmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask16,
@@ -4509,7 +4509,7 @@ pub fn _mm512_mask_fmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -4546,7 +4546,7 @@ pub fn _mm512_mask3_fmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmadd_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -4574,7 +4574,7 @@ pub fn _mm512_maskz_fmadd_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -4589,7 +4589,7 @@ pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -4604,7 +4604,7 @@ pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     _mm_mask3_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -4619,7 +4619,7 @@ pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_maskz_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -4641,7 +4641,7 @@ pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -4674,7 +4674,7 @@ pub fn _mm_fmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -4708,7 +4708,7 @@ pub fn _mm_mask_fmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -4742,7 +4742,7 @@ pub fn _mm_mask3_fmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmadd_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -4770,7 +4770,7 @@ pub fn _mm_maskz_fmadd_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask3_fcmadd_pch(a, b, c, 0xff)
 }
@@ -4785,7 +4785,7 @@ pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let r: __m128 = transmute(_mm_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4803,7 +4803,7 @@ pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         transmute(vfcmaddcph_mask3_128(
@@ -4825,7 +4825,7 @@ pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         transmute(vfcmaddcph_maskz_128(
@@ -4846,7 +4846,7 @@ pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_mask3_fcmadd_pch(a, b, c, 0xff)
 }
@@ -4861,7 +4861,7 @@ pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         let r: __m256 = transmute(_mm256_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4879,7 +4879,7 @@ pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h {
     unsafe {
         transmute(vfcmaddcph_mask3_256(
@@ -4901,7 +4901,7 @@ pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         transmute(vfcmaddcph_maskz_256(
@@ -4922,7 +4922,7 @@ pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -4937,7 +4937,7 @@ pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h {
     _mm512_mask_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -4952,7 +4952,7 @@ pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h {
     _mm512_mask3_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -4967,7 +4967,7 @@ pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_maskz_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -4990,7 +4990,7 @@ pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fcmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask3_fcmadd_round_pch::<ROUNDING>(a, b, c, 0xffff)
@@ -5015,7 +5015,7 @@ pub fn _mm512_fcmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fcmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask16,
@@ -5048,7 +5048,7 @@ pub fn _mm512_mask_fcmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fcmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -5086,7 +5086,7 @@ pub fn _mm512_mask3_fcmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fcmadd_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -5115,7 +5115,7 @@ pub fn _mm512_maskz_fcmadd_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -5131,7 +5131,7 @@ pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -5147,7 +5147,7 @@ pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     _mm_mask3_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -5163,7 +5163,7 @@ pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_maskz_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -5187,7 +5187,7 @@ pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fcmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -5221,7 +5221,7 @@ pub fn _mm_fcmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m1
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fcmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -5256,7 +5256,7 @@ pub fn _mm_mask_fcmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fcmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -5291,7 +5291,7 @@ pub fn _mm_mask3_fcmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fcmadd_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -5317,7 +5317,7 @@ pub fn _mm_maskz_fcmadd_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(a, b, c) }
@@ -5331,7 +5331,7 @@ pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) }
@@ -5345,7 +5345,7 @@ pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) }
@@ -5359,7 +5359,7 @@ pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) }
@@ -5372,7 +5372,7 @@ pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(a, b, c) }
@@ -5386,7 +5386,7 @@ pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) }
@@ -5400,7 +5400,7 @@ pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) }
@@ -5414,7 +5414,7 @@ pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) }
@@ -5427,7 +5427,7 @@ pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(a, b, c) }
@@ -5441,7 +5441,7 @@ pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) }
@@ -5455,7 +5455,7 @@ pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) }
@@ -5469,7 +5469,7 @@ pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) }
@@ -5491,7 +5491,7 @@ pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -5516,7 +5516,7 @@ pub fn _mm512_fmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -5546,7 +5546,7 @@ pub fn _mm512_mask_fmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -5576,7 +5576,7 @@ pub fn _mm512_mask3_fmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmadd_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -5601,7 +5601,7 @@ pub fn _mm512_maskz_fmadd_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -5622,7 +5622,7 @@ pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -5645,7 +5645,7 @@ pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -5668,7 +5668,7 @@ pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -5700,7 +5700,7 @@ pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -5730,7 +5730,7 @@ pub fn _mm_fmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -5767,7 +5767,7 @@ pub fn _mm_mask_fmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -5804,7 +5804,7 @@ pub fn _mm_mask3_fmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmadd_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -5832,7 +5832,7 @@ pub fn _mm_maskz_fmadd_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
@@ -5846,7 +5846,7 @@ pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) }
@@ -5860,7 +5860,7 @@ pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) }
@@ -5874,7 +5874,7 @@ pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) }
@@ -5887,7 +5887,7 @@ pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
@@ -5901,7 +5901,7 @@ pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) }
@@ -5915,7 +5915,7 @@ pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) }
@@ -5929,7 +5929,7 @@ pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) }
@@ -5942,7 +5942,7 @@ pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
@@ -5956,7 +5956,7 @@ pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) }
@@ -5970,7 +5970,7 @@ pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) }
@@ -5984,7 +5984,7 @@ pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) }
@@ -6006,7 +6006,7 @@ pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6031,7 +6031,7 @@ pub fn _mm512_fmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -6061,7 +6061,7 @@ pub fn _mm512_mask_fmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -6091,7 +6091,7 @@ pub fn _mm512_mask3_fmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmsub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -6116,7 +6116,7 @@ pub fn _mm512_maskz_fmsub_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6137,7 +6137,7 @@ pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6160,7 +6160,7 @@ pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -6183,7 +6183,7 @@ pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6215,7 +6215,7 @@ pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6245,7 +6245,7 @@ pub fn _mm_fmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -6282,7 +6282,7 @@ pub fn _mm_mask_fmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -6311,7 +6311,7 @@ pub fn _mm_mask3_fmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fmsub_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -6338,7 +6338,7 @@ pub fn _mm_maskz_fmsub_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(simd_neg(a), b, c) }
@@ -6352,7 +6352,7 @@ pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) }
@@ -6366,7 +6366,7 @@ pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) }
@@ -6380,7 +6380,7 @@ pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) }
@@ -6393,7 +6393,7 @@ pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(simd_neg(a), b, c) }
@@ -6407,7 +6407,7 @@ pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) }
@@ -6421,7 +6421,7 @@ pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) }
@@ -6435,7 +6435,7 @@ pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) }
@@ -6448,7 +6448,7 @@ pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(simd_neg(a), b, c) }
@@ -6462,7 +6462,7 @@ pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) }
@@ -6476,7 +6476,7 @@ pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) }
@@ -6490,7 +6490,7 @@ pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) }
@@ -6512,7 +6512,7 @@ pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fnmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6537,7 +6537,7 @@ pub fn _mm512_fnmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fnmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -6567,7 +6567,7 @@ pub fn _mm512_mask_fnmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fnmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -6597,7 +6597,7 @@ pub fn _mm512_mask3_fnmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fnmadd_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -6622,7 +6622,7 @@ pub fn _mm512_maskz_fnmadd_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6643,7 +6643,7 @@ pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6666,7 +6666,7 @@ pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -6689,7 +6689,7 @@ pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6721,7 +6721,7 @@ pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fnmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6751,7 +6751,7 @@ pub fn _mm_fnmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fnmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -6788,7 +6788,7 @@ pub fn _mm_mask_fnmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fnmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -6825,7 +6825,7 @@ pub fn _mm_mask3_fnmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fnmadd_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -6852,7 +6852,7 @@ pub fn _mm_maskz_fnmadd_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
@@ -6866,7 +6866,7 @@ pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) }
@@ -6880,7 +6880,7 @@ pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) }
@@ -6894,7 +6894,7 @@ pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) }
@@ -6907,7 +6907,7 @@ pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
@@ -6921,7 +6921,7 @@ pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) }
@@ -6935,7 +6935,7 @@ pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) }
@@ -6949,7 +6949,7 @@ pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) }
@@ -6962,7 +6962,7 @@ pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
@@ -6976,7 +6976,7 @@ pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) }
@@ -6990,7 +6990,7 @@ pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) }
@@ -7004,7 +7004,7 @@ pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) }
@@ -7026,7 +7026,7 @@ pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fnmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -7051,7 +7051,7 @@ pub fn _mm512_fnmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fnmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -7081,7 +7081,7 @@ pub fn _mm512_mask_fnmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fnmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7111,7 +7111,7 @@ pub fn _mm512_mask3_fnmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fnmsub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -7136,7 +7136,7 @@ pub fn _mm512_maskz_fnmsub_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7157,7 +7157,7 @@ pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7180,7 +7180,7 @@ pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -7203,7 +7203,7 @@ pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7235,7 +7235,7 @@ pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fnmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -7265,7 +7265,7 @@ pub fn _mm_fnmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fnmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -7302,7 +7302,7 @@ pub fn _mm_mask_fnmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask3_fnmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -7339,7 +7339,7 @@ pub fn _mm_mask3_fnmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_fnmsub_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -7366,7 +7366,7 @@ pub fn _mm_maskz_fnmsub_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7384,7 +7384,7 @@ pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) }
@@ -7398,7 +7398,7 @@ pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) }
@@ -7412,7 +7412,7 @@ pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) }
@@ -7425,7 +7425,7 @@ pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
@@ -7447,7 +7447,7 @@ pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) }
@@ -7461,7 +7461,7 @@ pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) }
@@ -7475,7 +7475,7 @@ pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) }
@@ -7488,7 +7488,7 @@ pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
@@ -7513,7 +7513,7 @@ pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) }
@@ -7527,7 +7527,7 @@ pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) }
@@ -7541,7 +7541,7 @@ pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) }
@@ -7563,7 +7563,7 @@ pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmaddsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7592,7 +7592,7 @@ pub fn _mm512_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmaddsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -7622,7 +7622,7 @@ pub fn _mm512_mask_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fmaddsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7652,7 +7652,7 @@ pub fn _mm512_mask3_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmaddsub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -7676,7 +7676,7 @@ pub fn _mm512_maskz_fmaddsub_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
@@ -7690,7 +7690,7 @@ pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) }
@@ -7704,7 +7704,7 @@ pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) }
@@ -7718,7 +7718,7 @@ pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) }
@@ -7731,7 +7731,7 @@ pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
@@ -7745,7 +7745,7 @@ pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) }
@@ -7759,7 +7759,7 @@ pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) }
@@ -7773,7 +7773,7 @@ pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) }
@@ -7786,7 +7786,7 @@ pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
@@ -7800,7 +7800,7 @@ pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) }
@@ -7814,7 +7814,7 @@ pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) }
@@ -7828,7 +7828,7 @@ pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) }
@@ -7850,7 +7850,7 @@ pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fmsubadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7879,7 +7879,7 @@ pub fn _mm512_fmsubadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fmsubadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -7909,7 +7909,7 @@ pub fn _mm512_mask_fmsubadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask3_fmsubadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7939,7 +7939,7 @@ pub fn _mm512_mask3_fmsubadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_fmsubadd_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -7963,7 +7963,7 @@ pub fn _mm512_maskz_fmsubadd_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_rcp_ph(a: __m128h) -> __m128h {
     _mm_mask_rcp_ph(_mm_undefined_ph(), 0xff, a)
 }
@@ -7976,7 +7976,7 @@ pub fn _mm_rcp_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { vrcpph_128(a, src, k) }
 }
@@ -7989,7 +7989,7 @@ pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_rcp_ph(_mm_setzero_ph(), k, a)
 }
@@ -8001,7 +8001,7 @@ pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_rcp_ph(a: __m256h) -> __m256h {
     _mm256_mask_rcp_ph(_mm256_undefined_ph(), 0xffff, a)
 }
@@ -8014,7 +8014,7 @@ pub fn _mm256_rcp_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { vrcpph_256(a, src, k) }
 }
@@ -8027,7 +8027,7 @@ pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h {
     _mm256_mask_rcp_ph(_mm256_setzero_ph(), k, a)
 }
@@ -8039,7 +8039,7 @@ pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_rcp_ph(a: __m512h) -> __m512h {
     _mm512_mask_rcp_ph(_mm512_undefined_ph(), 0xffffffff, a)
 }
@@ -8052,7 +8052,7 @@ pub fn _mm512_rcp_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     unsafe { vrcpph_512(a, src, k) }
 }
@@ -8065,7 +8065,7 @@ pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_rcp_ph(_mm512_setzero_ph(), k, a)
 }
@@ -8079,7 +8079,7 @@ pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -8093,7 +8093,7 @@ pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { vrcpsh(a, b, src, k) }
 }
@@ -8107,7 +8107,7 @@ pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8120,7 +8120,7 @@ pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h {
     _mm_mask_rsqrt_ph(_mm_undefined_ph(), 0xff, a)
 }
@@ -8134,7 +8134,7 @@ pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { vrsqrtph_128(a, src, k) }
 }
@@ -8148,7 +8148,7 @@ pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_rsqrt_ph(_mm_setzero_ph(), k, a)
 }
@@ -8161,7 +8161,7 @@ pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h {
     _mm256_mask_rsqrt_ph(_mm256_undefined_ph(), 0xffff, a)
 }
@@ -8175,7 +8175,7 @@ pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { vrsqrtph_256(a, src, k) }
 }
@@ -8189,7 +8189,7 @@ pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
     _mm256_mask_rsqrt_ph(_mm256_setzero_ph(), k, a)
 }
@@ -8202,7 +8202,7 @@ pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h {
     _mm512_mask_rsqrt_ph(_mm512_undefined_ph(), 0xffffffff, a)
 }
@@ -8216,7 +8216,7 @@ pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     unsafe { vrsqrtph_512(a, src, k) }
 }
@@ -8230,7 +8230,7 @@ pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_rsqrt_ph(_mm512_setzero_ph(), k, a)
 }
@@ -8244,7 +8244,7 @@ pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -8258,7 +8258,7 @@ pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { vrsqrtsh(a, b, src, k) }
 }
@@ -8272,7 +8272,7 @@ pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8284,7 +8284,7 @@ pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_sqrt_ph(a: __m128h) -> __m128h {
     unsafe { simd_fsqrt(a) }
 }
@@ -8296,7 +8296,7 @@ pub fn _mm_sqrt_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), src) }
 }
@@ -8308,7 +8308,7 @@ pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), _mm_setzero_ph()) }
 }
@@ -8320,7 +8320,7 @@ pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h {
     unsafe { simd_fsqrt(a) }
 }
@@ -8332,7 +8332,7 @@ pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), src) }
 }
@@ -8344,7 +8344,7 @@ pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), _mm256_setzero_ph()) }
 }
@@ -8356,7 +8356,7 @@ pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h {
     unsafe { simd_fsqrt(a) }
 }
@@ -8368,7 +8368,7 @@ pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), src) }
 }
@@ -8380,7 +8380,7 @@ pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), _mm512_setzero_ph()) }
 }
@@ -8400,7 +8400,7 @@ pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_sqrt_round_ph<const ROUNDING: i32>(a: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -8423,7 +8423,7 @@ pub fn _mm512_sqrt_round_ph<const ROUNDING: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_sqrt_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -8450,7 +8450,7 @@ pub fn _mm512_mask_sqrt_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_sqrt_round_ph<const ROUNDING: i32>(k: __mmask32, a: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -8466,7 +8466,7 @@ pub fn _mm512_maskz_sqrt_round_ph<const ROUNDING: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -8479,7 +8479,7 @@ pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_sqrt_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -8492,7 +8492,7 @@ pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8513,7 +8513,7 @@ pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_sqrt_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_sqrt_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -8535,7 +8535,7 @@ pub fn _mm_sqrt_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_sqrt_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -8564,7 +8564,7 @@ pub fn _mm_mask_sqrt_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_sqrt_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -8582,7 +8582,7 @@ pub fn _mm_maskz_sqrt_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { vmaxph_128(a, b) }
 }
@@ -8596,7 +8596,7 @@ pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), src) }
 }
@@ -8610,7 +8610,7 @@ pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), _mm_setzero_ph()) }
 }
@@ -8623,7 +8623,7 @@ pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { vmaxph_256(a, b) }
 }
@@ -8637,7 +8637,7 @@ pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), src) }
 }
@@ -8651,7 +8651,7 @@ pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), _mm256_setzero_ph()) }
 }
@@ -8664,7 +8664,7 @@ pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h {
     _mm512_max_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b)
 }
@@ -8678,7 +8678,7 @@ pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), src) }
 }
@@ -8692,7 +8692,7 @@ pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), _mm512_setzero_ph()) }
 }
@@ -8707,7 +8707,7 @@ pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_max_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -8725,7 +8725,7 @@ pub fn _mm512_max_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_max_round_ph<const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -8748,7 +8748,7 @@ pub fn _mm512_mask_max_round_ph<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_max_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -8765,7 +8765,7 @@ pub fn _mm512_maskz_max_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_max_sh(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -8779,7 +8779,7 @@ pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_max_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -8793,7 +8793,7 @@ pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_max_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8808,7 +8808,7 @@ pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_max_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_max_round_sh::<SAE>(_mm_undefined_ph(), 0xff, a, b)
@@ -8825,7 +8825,7 @@ pub fn _mm_max_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_max_round_sh<const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -8849,7 +8849,7 @@ pub fn _mm_mask_max_round_sh<const SAE: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_max_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_max_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -8863,7 +8863,7 @@ pub fn _mm_maskz_max_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { vminph_128(a, b) }
 }
@@ -8877,7 +8877,7 @@ pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), src) }
 }
@@ -8891,7 +8891,7 @@ pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), _mm_setzero_ph()) }
 }
@@ -8904,7 +8904,7 @@ pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { vminph_256(a, b) }
 }
@@ -8918,7 +8918,7 @@ pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), src) }
 }
@@ -8932,7 +8932,7 @@ pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), _mm256_setzero_ph()) }
 }
@@ -8945,7 +8945,7 @@ pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h {
     _mm512_min_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b)
 }
@@ -8959,7 +8959,7 @@ pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), src) }
 }
@@ -8973,7 +8973,7 @@ pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), _mm512_setzero_ph()) }
 }
@@ -8987,7 +8987,7 @@ pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_min_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -9005,7 +9005,7 @@ pub fn _mm512_min_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_min_round_ph<const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -9028,7 +9028,7 @@ pub fn _mm512_mask_min_round_ph<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_min_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -9045,7 +9045,7 @@ pub fn _mm512_maskz_min_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_min_sh(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -9059,7 +9059,7 @@ pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_min_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -9073,7 +9073,7 @@ pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_min_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -9088,7 +9088,7 @@ pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_min_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_min_round_sh::<SAE>(_mm_undefined_ph(), 0xff, a, b)
@@ -9105,7 +9105,7 @@ pub fn _mm_min_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_min_round_sh<const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -9129,7 +9129,7 @@ pub fn _mm_mask_min_round_sh<const SAE: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_min_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_min_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -9143,7 +9143,7 @@ pub fn _mm_maskz_min_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_getexp_ph(a: __m128h) -> __m128h {
     _mm_mask_getexp_ph(_mm_undefined_ph(), 0xff, a)
 }
@@ -9157,7 +9157,7 @@ pub fn _mm_getexp_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { vgetexpph_128(a, src, k) }
 }
@@ -9171,7 +9171,7 @@ pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_getexp_ph(_mm_setzero_ph(), k, a)
 }
@@ -9184,7 +9184,7 @@ pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_getexp_ph(a: __m256h) -> __m256h {
     _mm256_mask_getexp_ph(_mm256_undefined_ph(), 0xffff, a)
 }
@@ -9198,7 +9198,7 @@ pub fn _mm256_getexp_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { vgetexpph_256(a, src, k) }
 }
@@ -9212,7 +9212,7 @@ pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h {
     _mm256_mask_getexp_ph(_mm256_setzero_ph(), k, a)
 }
@@ -9225,7 +9225,7 @@ pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_getexp_ph(a: __m512h) -> __m512h {
     _mm512_mask_getexp_ph(_mm512_undefined_ph(), 0xffffffff, a)
 }
@@ -9239,7 +9239,7 @@ pub fn _mm512_getexp_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_getexp_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a)
 }
@@ -9253,7 +9253,7 @@ pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_getexp_ph(_mm512_setzero_ph(), k, a)
 }
@@ -9268,7 +9268,7 @@ pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_getexp_round_ph<const SAE: i32>(a: __m512h) -> __m512h {
     static_assert_sae!(SAE);
     _mm512_mask_getexp_round_ph::<SAE>(_mm512_undefined_ph(), 0xffffffff, a)
@@ -9284,7 +9284,7 @@ pub fn _mm512_getexp_round_ph<const SAE: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_getexp_round_ph<const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -9306,7 +9306,7 @@ pub fn _mm512_mask_getexp_round_ph<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_getexp_round_ph<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512h {
     static_assert_sae!(SAE);
     _mm512_mask_getexp_round_ph::<SAE>(_mm512_setzero_ph(), k, a)
@@ -9321,7 +9321,7 @@ pub fn _mm512_maskz_getexp_round_ph<const SAE: i32>(k: __mmask32, a: __m512h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -9336,7 +9336,7 @@ pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_getexp_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -9351,7 +9351,7 @@ pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -9367,7 +9367,7 @@ pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_getexp_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_getexp_round_sh::<SAE>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -9384,7 +9384,7 @@ pub fn _mm_getexp_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_getexp_round_sh<const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -9408,7 +9408,7 @@ pub fn _mm_mask_getexp_round_sh<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_getexp_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_getexp_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -9436,7 +9436,7 @@ pub fn _mm_maskz_getexp_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(1, 2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m128h,
 ) -> __m128h {
@@ -9468,7 +9468,7 @@ pub fn _mm_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTIS
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9507,7 +9507,7 @@ pub fn _mm_mask_getmant_ph<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9542,7 +9542,7 @@ pub fn _mm_maskz_getmant_ph<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(1, 2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m256h,
 ) -> __m256h {
@@ -9574,7 +9574,7 @@ pub fn _mm256_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MAN
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9613,7 +9613,7 @@ pub fn _mm256_mask_getmant_ph<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9648,7 +9648,7 @@ pub fn _mm256_maskz_getmant_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(1, 2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m512h,
 ) -> __m512h {
@@ -9680,7 +9680,7 @@ pub fn _mm512_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MAN
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9717,7 +9717,7 @@ pub fn _mm512_mask_getmant_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9755,7 +9755,7 @@ pub fn _mm512_maskz_getmant_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(1, 2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_getmant_round_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9795,7 +9795,7 @@ pub fn _mm512_getmant_round_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4, 5)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_getmant_round_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9839,7 +9839,7 @@ pub fn _mm512_mask_getmant_round_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_getmant_round_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9877,7 +9877,7 @@ pub fn _mm512_maskz_getmant_round_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_getmant_sh<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m128h,
     b: __m128h,
@@ -9911,7 +9911,7 @@ pub fn _mm_getmant_sh<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTIS
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(4, 5)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_getmant_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9950,7 +9950,7 @@ pub fn _mm_mask_getmant_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_getmant_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9990,7 +9990,7 @@ pub fn _mm_maskz_getmant_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_getmant_round_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -10031,7 +10031,7 @@ pub fn _mm_getmant_round_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(4, 5, 6)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_getmant_round_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -10076,7 +10076,7 @@ pub fn _mm_mask_getmant_round_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4, 5)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_getmant_round_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -10108,7 +10108,7 @@ pub fn _mm_maskz_getmant_round_sh<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_roundscale_ph<const IMM8: i32>(a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_ph::<IMM8>(_mm_undefined_ph(), 0xff, a)
@@ -10131,7 +10131,7 @@ pub fn _mm_roundscale_ph<const IMM8: i32>(a: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_roundscale_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -10156,7 +10156,7 @@ pub fn _mm_mask_roundscale_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_roundscale_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_ph::<IMM8>(_mm_setzero_ph(), k, a)
@@ -10178,7 +10178,7 @@ pub fn _mm_maskz_roundscale_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m1
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_roundscale_ph<const IMM8: i32>(a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_roundscale_ph::<IMM8>(_mm256_undefined_ph(), 0xffff, a)
@@ -10201,7 +10201,7 @@ pub fn _mm256_roundscale_ph<const IMM8: i32>(a: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_roundscale_ph<const IMM8: i32>(
     src: __m256h,
     k: __mmask16,
@@ -10230,7 +10230,7 @@ pub fn _mm256_mask_roundscale_ph<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_roundscale_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_roundscale_ph::<IMM8>(_mm256_setzero_ph(), k, a)
@@ -10252,7 +10252,7 @@ pub fn _mm256_maskz_roundscale_ph<const IMM8: i32>(k: __mmask16, a: __m256h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_roundscale_ph<const IMM8: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_roundscale_ph::<IMM8>(_mm512_undefined_ph(), 0xffffffff, a)
@@ -10275,7 +10275,7 @@ pub fn _mm512_roundscale_ph<const IMM8: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_roundscale_ph<const IMM8: i32>(
     src: __m512h,
     k: __mmask32,
@@ -10302,7 +10302,7 @@ pub fn _mm512_mask_roundscale_ph<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_roundscale_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_roundscale_ph::<IMM8>(_mm512_setzero_ph(), k, a)
@@ -10325,7 +10325,7 @@ pub fn _mm512_maskz_roundscale_ph<const IMM8: i32>(k: __mmask32, a: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(1, 2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_roundscale_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -10350,7 +10350,7 @@ pub fn _mm512_roundscale_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -10380,7 +10380,7 @@ pub fn _mm512_mask_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
     k: __mmask32,
     a: __m512h,
@@ -10407,7 +10407,7 @@ pub fn _mm512_maskz_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_roundscale_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_sh::<IMM8>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -10430,7 +10430,7 @@ pub fn _mm_roundscale_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_roundscale_sh<const IMM8: i32>(
     src: __m128h,
     k: __mmask8,
@@ -10458,7 +10458,7 @@ pub fn _mm_mask_roundscale_sh<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_roundscale_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_sh::<IMM8>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -10483,7 +10483,7 @@ pub fn _mm_maskz_roundscale_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m1
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_roundscale_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -10509,7 +10509,7 @@ pub fn _mm_roundscale_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(4, 5)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -10542,7 +10542,7 @@ pub fn _mm_mask_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
     k: __mmask8,
     a: __m128h,
@@ -10560,7 +10560,7 @@ pub fn _mm_maskz_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_ph(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -10572,7 +10572,7 @@ pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { vscalefph_128(a, b, src, k) }
 }
@@ -10584,7 +10584,7 @@ pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_ph(_mm_setzero_ph(), k, a, b)
 }
@@ -10596,7 +10596,7 @@ pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_scalef_ph(_mm256_undefined_ph(), 0xffff, a, b)
 }
@@ -10608,7 +10608,7 @@ pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { vscalefph_256(a, b, src, k) }
 }
@@ -10620,7 +10620,7 @@ pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_scalef_ph(_mm256_setzero_ph(), k, a, b)
 }
@@ -10632,7 +10632,7 @@ pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_scalef_ph(_mm512_undefined_ph(), 0xffffffff, a, b)
 }
@@ -10644,7 +10644,7 @@ pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_scalef_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -10656,7 +10656,7 @@ pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_scalef_ph(_mm512_setzero_ph(), k, a, b)
 }
@@ -10677,7 +10677,7 @@ pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_scalef_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_scalef_round_ph::<ROUNDING>(_mm512_undefined_ph(), 0xffffffff, a, b)
@@ -10699,7 +10699,7 @@ pub fn _mm512_scalef_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_scalef_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -10728,7 +10728,7 @@ pub fn _mm512_mask_scalef_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_scalef_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -10746,7 +10746,7 @@ pub fn _mm512_maskz_scalef_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -10759,7 +10759,7 @@ pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -10772,7 +10772,7 @@ pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -10794,7 +10794,7 @@ pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_scalef_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_scalef_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -10817,7 +10817,7 @@ pub fn _mm_scalef_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_scalef_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -10847,7 +10847,7 @@ pub fn _mm_mask_scalef_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_scalef_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -10873,7 +10873,7 @@ pub fn _mm_maskz_scalef_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_reduce_ph<const IMM8: i32>(a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_ph::<IMM8>(_mm_undefined_ph(), 0xff, a)
@@ -10896,7 +10896,7 @@ pub fn _mm_reduce_ph<const IMM8: i32>(a: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_reduce_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -10921,7 +10921,7 @@ pub fn _mm_mask_reduce_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_reduce_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_ph::<IMM8>(_mm_setzero_ph(), k, a)
@@ -10943,7 +10943,7 @@ pub fn _mm_maskz_reduce_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_reduce_ph<const IMM8: i32>(a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_reduce_ph::<IMM8>(_mm256_undefined_ph(), 0xffff, a)
@@ -10966,7 +10966,7 @@ pub fn _mm256_reduce_ph<const IMM8: i32>(a: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_reduce_ph<const IMM8: i32>(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -10991,7 +10991,7 @@ pub fn _mm256_mask_reduce_ph<const IMM8: i32>(src: __m256h, k: __mmask16, a: __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_reduce_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_reduce_ph::<IMM8>(_mm256_setzero_ph(), k, a)
@@ -11013,7 +11013,7 @@ pub fn _mm256_maskz_reduce_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m2
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_reduce_ph<const IMM8: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_reduce_ph::<IMM8>(_mm512_undefined_ph(), 0xffffffff, a)
@@ -11036,7 +11036,7 @@ pub fn _mm512_reduce_ph<const IMM8: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_reduce_ph<const IMM8: i32>(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_reduce_round_ph::<IMM8, _MM_FROUND_CUR_DIRECTION>(src, k, a)
@@ -11059,7 +11059,7 @@ pub fn _mm512_mask_reduce_ph<const IMM8: i32>(src: __m512h, k: __mmask32, a: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_reduce_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_reduce_ph::<IMM8>(_mm512_setzero_ph(), k, a)
@@ -11083,7 +11083,7 @@ pub fn _mm512_maskz_reduce_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(1, 2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_reduce_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -11109,7 +11109,7 @@ pub fn _mm512_reduce_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_reduce_round_ph<const IMM8: i32, const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -11141,7 +11141,7 @@ pub fn _mm512_mask_reduce_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_reduce_round_ph<const IMM8: i32, const SAE: i32>(
     k: __mmask32,
     a: __m512h,
@@ -11168,7 +11168,7 @@ pub fn _mm512_maskz_reduce_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_reduce_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_sh::<IMM8>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -11192,7 +11192,7 @@ pub fn _mm_reduce_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_reduce_sh<const IMM8: i32>(
     src: __m128h,
     k: __mmask8,
@@ -11221,7 +11221,7 @@ pub fn _mm_mask_reduce_sh<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_reduce_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_sh::<IMM8>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -11246,7 +11246,7 @@ pub fn _mm_maskz_reduce_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_reduce_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -11273,7 +11273,7 @@ pub fn _mm_reduce_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(4, 5)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_reduce_round_sh<const IMM8: i32, const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -11307,7 +11307,7 @@ pub fn _mm_mask_reduce_round_sh<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_reduce_round_sh<const IMM8: i32, const SAE: i32>(
     k: __mmask8,
     a: __m128h,
@@ -11582,7 +11582,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11609,7 +11609,7 @@ pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11635,7 +11635,7 @@ pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11662,7 +11662,7 @@ pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11688,7 +11688,7 @@ pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11715,7 +11715,7 @@ pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask32, a: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11741,7 +11741,7 @@ pub fn _mm512_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask32, a: __m512h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_fpclass_sh_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
     _mm_mask_fpclass_sh_mask::<IMM8>(0xff, a)
 }
@@ -11765,7 +11765,7 @@ pub fn _mm_fpclass_sh_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_fpclass_sh_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11779,7 +11779,7 @@ pub fn _mm_mask_fpclass_sh_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_blend_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, b, a) }
@@ -11791,7 +11791,7 @@ pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_blend_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, b, a) }
@@ -11803,7 +11803,7 @@ pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m25
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, b, a) }
@@ -11815,7 +11815,7 @@ pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m51
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutex2var_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h {
     _mm_castsi128_ph(_mm_permutex2var_epi16(
         _mm_castph_si128(a),
@@ -11830,7 +11830,7 @@ pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex2var_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h {
     _mm256_castsi256_ph(_mm256_permutex2var_epi16(
         _mm256_castph_si256(a),
@@ -11845,7 +11845,7 @@ pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h {
     _mm512_castsi512_ph(_mm512_permutex2var_epi16(
         _mm512_castph_si512(a),
@@ -11860,7 +11860,7 @@ pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutexvar_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h {
     _mm_castsi128_ph(_mm_permutexvar_epi16(idx, _mm_castph_si128(a)))
 }
@@ -11871,7 +11871,7 @@ pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutexvar_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h {
     _mm256_castsi256_ph(_mm256_permutexvar_epi16(idx, _mm256_castph_si256(a)))
 }
@@ -11882,7 +11882,7 @@ pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h {
     _mm512_castsi512_ph(_mm512_permutexvar_epi16(idx, _mm512_castph_si512(a)))
 }
@@ -11894,7 +11894,7 @@ pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h {
     unsafe { vcvtw2ph_128(a.as_i16x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -11907,7 +11907,7 @@ pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_cvtepi16_ph(a), src) }
 }
@@ -11919,7 +11919,7 @@ pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepi16_ph(_mm_setzero_ph(), k, a)
 }
@@ -11931,7 +11931,7 @@ pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h {
     unsafe { vcvtw2ph_256(a.as_i16x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -11944,7 +11944,7 @@ pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepi16_ph(a), src) }
 }
@@ -11956,7 +11956,7 @@ pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h {
     _mm256_mask_cvtepi16_ph(_mm256_setzero_ph(), k, a)
 }
@@ -11968,7 +11968,7 @@ pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h {
     unsafe { vcvtw2ph_512(a.as_i16x32(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -11981,7 +11981,7 @@ pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepi16_ph(a), src) }
 }
@@ -11993,7 +11993,7 @@ pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h {
     _mm512_mask_cvtepi16_ph(_mm512_setzero_ph(), k, a)
 }
@@ -12014,7 +12014,7 @@ pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundepi16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12039,7 +12039,7 @@ pub fn _mm512_cvt_roundepi16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundepi16_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -12067,7 +12067,7 @@ pub fn _mm512_mask_cvt_roundepi16_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundepi16_ph<const ROUNDING: i32>(k: __mmask32, a: __m512i) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepi16_ph::<ROUNDING>(_mm512_setzero_ph(), k, a)
@@ -12080,7 +12080,7 @@ pub fn _mm512_maskz_cvt_roundepi16_ph<const ROUNDING: i32>(k: __mmask32, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h {
     unsafe { vcvtuw2ph_128(a.as_u16x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12093,7 +12093,7 @@ pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_cvtepu16_ph(a), src) }
 }
@@ -12105,7 +12105,7 @@ pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepu16_ph(_mm_setzero_ph(), k, a)
 }
@@ -12117,7 +12117,7 @@ pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h {
     unsafe { vcvtuw2ph_256(a.as_u16x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12130,7 +12130,7 @@ pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepu16_ph(a), src) }
 }
@@ -12142,7 +12142,7 @@ pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h {
     _mm256_mask_cvtepu16_ph(_mm256_setzero_ph(), k, a)
 }
@@ -12154,7 +12154,7 @@ pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h {
     unsafe { vcvtuw2ph_512(a.as_u16x32(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12167,7 +12167,7 @@ pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepu16_ph(a), src) }
 }
@@ -12179,7 +12179,7 @@ pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h {
     _mm512_mask_cvtepu16_ph(_mm512_setzero_ph(), k, a)
 }
@@ -12200,7 +12200,7 @@ pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundepu16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12225,7 +12225,7 @@ pub fn _mm512_cvt_roundepu16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundepu16_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -12253,7 +12253,7 @@ pub fn _mm512_mask_cvt_roundepu16_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundepu16_ph<const ROUNDING: i32>(k: __mmask32, a: __m512i) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepu16_ph::<ROUNDING>(_mm512_setzero_ph(), k, a)
@@ -12266,7 +12266,7 @@ pub fn _mm512_maskz_cvt_roundepu16_ph<const ROUNDING: i32>(k: __mmask32, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepi32_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12279,7 +12279,7 @@ pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtdq2ph_128(a.as_i32x4(), src, k) }
 }
@@ -12292,7 +12292,7 @@ pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepi32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12304,7 +12304,7 @@ pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h {
     unsafe { vcvtdq2ph_256(a.as_i32x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12317,7 +12317,7 @@ pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepi32_ph(a), src) }
 }
@@ -12329,7 +12329,7 @@ pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepi32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12341,7 +12341,7 @@ pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h {
     unsafe { vcvtdq2ph_512(a.as_i32x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12354,7 +12354,7 @@ pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepi32_ph(a), src) }
 }
@@ -12366,7 +12366,7 @@ pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h {
     _mm512_mask_cvtepi32_ph(f16x16::ZERO.as_m256h(), k, a)
 }
@@ -12387,7 +12387,7 @@ pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundepi32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12412,7 +12412,7 @@ pub fn _mm512_cvt_roundepi32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundepi32_ph<const ROUNDING: i32>(
     src: __m256h,
     k: __mmask16,
@@ -12440,7 +12440,7 @@ pub fn _mm512_mask_cvt_roundepi32_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundepi32_ph<const ROUNDING: i32>(k: __mmask16, a: __m512i) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepi32_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
@@ -12454,7 +12454,7 @@ pub fn _mm512_maskz_cvt_roundepi32_ph<const ROUNDING: i32>(k: __mmask16, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h {
     unsafe { vcvtsi2sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12476,7 +12476,7 @@ pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundi32_sh<const ROUNDING: i32>(a: __m128h, b: i32) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12491,7 +12491,7 @@ pub fn _mm_cvt_roundi32_sh<const ROUNDING: i32>(a: __m128h, b: i32) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepu32_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12504,7 +12504,7 @@ pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtudq2ph_128(a.as_u32x4(), src, k) }
 }
@@ -12517,7 +12517,7 @@ pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepu32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12529,7 +12529,7 @@ pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h {
     unsafe { vcvtudq2ph_256(a.as_u32x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12542,7 +12542,7 @@ pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepu32_ph(a), src) }
 }
@@ -12554,7 +12554,7 @@ pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepu32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12566,7 +12566,7 @@ pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h {
     unsafe { vcvtudq2ph_512(a.as_u32x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12579,7 +12579,7 @@ pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepu32_ph(a), src) }
 }
@@ -12591,7 +12591,7 @@ pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h {
     _mm512_mask_cvtepu32_ph(f16x16::ZERO.as_m256h(), k, a)
 }
@@ -12612,7 +12612,7 @@ pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundepu32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12637,7 +12637,7 @@ pub fn _mm512_cvt_roundepu32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundepu32_ph<const ROUNDING: i32>(
     src: __m256h,
     k: __mmask16,
@@ -12665,7 +12665,7 @@ pub fn _mm512_mask_cvt_roundepu32_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundepu32_ph<const ROUNDING: i32>(k: __mmask16, a: __m512i) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepu32_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
@@ -12679,7 +12679,7 @@ pub fn _mm512_maskz_cvt_roundepu32_ph<const ROUNDING: i32>(k: __mmask16, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h {
     unsafe { vcvtusi2sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12701,7 +12701,7 @@ pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundu32_sh<const ROUNDING: i32>(a: __m128h, b: u32) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12716,7 +12716,7 @@ pub fn _mm_cvt_roundu32_sh<const ROUNDING: i32>(a: __m128h, b: u32) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12729,7 +12729,7 @@ pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtqq2ph_128(a.as_i64x2(), src, k) }
 }
@@ -12742,7 +12742,7 @@ pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepi64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12754,7 +12754,7 @@ pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h {
     _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12767,7 +12767,7 @@ pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { vcvtqq2ph_256(a.as_i64x4(), src, k) }
 }
@@ -12780,7 +12780,7 @@ pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12792,7 +12792,7 @@ pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h {
     unsafe { vcvtqq2ph_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12805,7 +12805,7 @@ pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepi64_ph(a), src) }
 }
@@ -12817,7 +12817,7 @@ pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h {
     _mm512_mask_cvtepi64_ph(f16x8::ZERO.as_m128h(), k, a)
 }
@@ -12838,7 +12838,7 @@ pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundepi64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12863,7 +12863,7 @@ pub fn _mm512_cvt_roundepi64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundepi64_ph<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -12891,7 +12891,7 @@ pub fn _mm512_mask_cvt_roundepi64_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundepi64_ph<const ROUNDING: i32>(k: __mmask8, a: __m512i) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepi64_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
@@ -12904,7 +12904,7 @@ pub fn _mm512_maskz_cvt_roundepi64_ph<const ROUNDING: i32>(k: __mmask8, a: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12917,7 +12917,7 @@ pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtuqq2ph_128(a.as_u64x2(), src, k) }
 }
@@ -12930,7 +12930,7 @@ pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepu64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12942,7 +12942,7 @@ pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h {
     _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12955,7 +12955,7 @@ pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { vcvtuqq2ph_256(a.as_u64x4(), src, k) }
 }
@@ -12968,7 +12968,7 @@ pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12980,7 +12980,7 @@ pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h {
     unsafe { vcvtuqq2ph_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12993,7 +12993,7 @@ pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepu64_ph(a), src) }
 }
@@ -13005,7 +13005,7 @@ pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h {
     _mm512_mask_cvtepu64_ph(f16x8::ZERO.as_m128h(), k, a)
 }
@@ -13026,7 +13026,7 @@ pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundepu64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -13051,7 +13051,7 @@ pub fn _mm512_cvt_roundepu64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundepu64_ph<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13079,7 +13079,7 @@ pub fn _mm512_mask_cvt_roundepu64_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundepu64_ph<const ROUNDING: i32>(k: __mmask8, a: __m512i) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepu64_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
@@ -13092,7 +13092,7 @@ pub fn _mm512_maskz_cvt_roundepu64_ph<const ROUNDING: i32>(k: __mmask8, a: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtxps_ph(a: __m128) -> __m128h {
     _mm_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13105,7 +13105,7 @@ pub fn _mm_cvtxps_ph(a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h {
     unsafe { vcvtps2phx_128(a, src, k) }
 }
@@ -13118,7 +13118,7 @@ pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h {
     _mm_mask_cvtxps_ph(_mm_setzero_ph(), k, a)
 }
@@ -13130,7 +13130,7 @@ pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h {
     _mm256_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13143,7 +13143,7 @@ pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h {
     unsafe { vcvtps2phx_256(a, src, k) }
 }
@@ -13156,7 +13156,7 @@ pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h {
     _mm256_mask_cvtxps_ph(_mm_setzero_ph(), k, a)
 }
@@ -13168,7 +13168,7 @@ pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h {
     _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), 0xffff, a)
 }
@@ -13181,7 +13181,7 @@ pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h {
     unsafe { vcvtps2phx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13194,7 +13194,7 @@ pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h {
     _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), k, a)
 }
@@ -13215,7 +13215,7 @@ pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtx_roundps_ph<const ROUNDING: i32>(a: __m512) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvtx_roundps_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), 0xffff, a)
@@ -13238,7 +13238,7 @@ pub fn _mm512_cvtx_roundps_ph<const ROUNDING: i32>(a: __m512) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtx_roundps_ph<const ROUNDING: i32>(
     src: __m256h,
     k: __mmask16,
@@ -13267,7 +13267,7 @@ pub fn _mm512_mask_cvtx_roundps_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtx_roundps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvtx_roundps_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
@@ -13281,7 +13281,7 @@ pub fn _mm512_maskz_cvtx_roundps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h {
     _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -13295,7 +13295,7 @@ pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __m128h {
     unsafe { vcvtss2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13309,7 +13309,7 @@ pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h {
     _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -13331,7 +13331,7 @@ pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundss_sh<const ROUNDING: i32>(a: __m128h, b: __m128) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_cvt_roundss_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -13355,7 +13355,7 @@ pub fn _mm_cvt_roundss_sh<const ROUNDING: i32>(a: __m128h, b: __m128) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvt_roundss_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13386,7 +13386,7 @@ pub fn _mm_mask_cvt_roundss_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvt_roundss_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -13403,7 +13403,7 @@ pub fn _mm_maskz_cvt_roundss_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h {
     _mm_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13416,7 +13416,7 @@ pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h {
     unsafe { vcvtpd2ph_128(a, src, k) }
 }
@@ -13429,7 +13429,7 @@ pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h {
     _mm_mask_cvtpd_ph(_mm_setzero_ph(), k, a)
 }
@@ -13441,7 +13441,7 @@ pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h {
     _mm256_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13454,7 +13454,7 @@ pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h {
     unsafe { vcvtpd2ph_256(a, src, k) }
 }
@@ -13467,7 +13467,7 @@ pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h {
     _mm256_mask_cvtpd_ph(_mm_setzero_ph(), k, a)
 }
@@ -13479,7 +13479,7 @@ pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h {
     _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), 0xff, a)
 }
@@ -13492,7 +13492,7 @@ pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h {
     unsafe { vcvtpd2ph_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13505,7 +13505,7 @@ pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h {
     _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), k, a)
 }
@@ -13526,7 +13526,7 @@ pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundpd_ph<const ROUNDING: i32>(a: __m512d) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundpd_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a)
@@ -13549,7 +13549,7 @@ pub fn _mm512_cvt_roundpd_ph<const ROUNDING: i32>(a: __m512d) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundpd_ph<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13578,7 +13578,7 @@ pub fn _mm512_mask_cvt_roundpd_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundpd_ph<const ROUNDING: i32>(k: __mmask8, a: __m512d) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundpd_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
@@ -13592,7 +13592,7 @@ pub fn _mm512_maskz_cvt_roundpd_ph<const ROUNDING: i32>(k: __mmask8, a: __m512d)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h {
     _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -13606,7 +13606,7 @@ pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
     unsafe { vcvtsd2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13620,7 +13620,7 @@ pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
     _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -13642,7 +13642,7 @@ pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsd_sh<const ROUNDING: i32>(a: __m128h, b: __m128d) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_cvt_roundsd_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -13666,7 +13666,7 @@ pub fn _mm_cvt_roundsd_sh<const ROUNDING: i32>(a: __m128h, b: __m128d) -> __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvt_roundsd_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13697,7 +13697,7 @@ pub fn _mm_mask_cvt_roundsd_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvt_roundsd_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -13714,7 +13714,7 @@ pub fn _mm_maskz_cvt_roundsd_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi16(_mm_undefined_si128(), 0xff, a)
 }
@@ -13727,7 +13727,7 @@ pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2w_128(a, src.as_i16x8(), k)) }
 }
@@ -13739,7 +13739,7 @@ pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi16(_mm_setzero_si128(), k, a)
 }
@@ -13751,7 +13751,7 @@ pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epi16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -13764,7 +13764,7 @@ pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvtph2w_256(a, src.as_i16x16(), k)) }
 }
@@ -13776,7 +13776,7 @@ pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epi16(_mm256_setzero_si256(), k, a)
 }
@@ -13788,7 +13788,7 @@ pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epi16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -13801,7 +13801,7 @@ pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvtph2w_512(
@@ -13820,7 +13820,7 @@ pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epi16(_mm512_setzero_si512(), k, a)
 }
@@ -13841,7 +13841,7 @@ pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_epi16<const ROUNDING: i32>(a: __m512h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi16::<ROUNDING>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -13864,7 +13864,7 @@ pub fn _mm512_cvt_roundph_epi16<const ROUNDING: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_epi16<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask32,
@@ -13892,7 +13892,7 @@ pub fn _mm512_mask_cvt_roundph_epi16<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_epi16<const ROUNDING: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi16::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -13905,7 +13905,7 @@ pub fn _mm512_maskz_cvt_roundph_epi16<const ROUNDING: i32>(k: __mmask32, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu16(_mm_undefined_si128(), 0xff, a)
 }
@@ -13918,7 +13918,7 @@ pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2uw_128(a, src.as_u16x8(), k)) }
 }
@@ -13930,7 +13930,7 @@ pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu16(_mm_setzero_si128(), k, a)
 }
@@ -13942,7 +13942,7 @@ pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epu16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -13955,7 +13955,7 @@ pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvtph2uw_256(a, src.as_u16x16(), k)) }
 }
@@ -13967,7 +13967,7 @@ pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epu16(_mm256_setzero_si256(), k, a)
 }
@@ -13979,7 +13979,7 @@ pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epu16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -13992,7 +13992,7 @@ pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvtph2uw_512(
@@ -14011,7 +14011,7 @@ pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epu16(_mm512_setzero_si512(), k, a)
 }
@@ -14026,7 +14026,7 @@ pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_epu16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -14043,7 +14043,7 @@ pub fn _mm512_cvt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_epu16<const SAE: i32>(
     src: __m512i,
     k: __mmask32,
@@ -14065,7 +14065,7 @@ pub fn _mm512_mask_cvt_roundph_epu16<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_epu16::<SAE>(_mm512_setzero_si512(), k, a)
@@ -14078,7 +14078,7 @@ pub fn _mm512_maskz_cvt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi16(_mm_undefined_si128(), 0xff, a)
 }
@@ -14091,7 +14091,7 @@ pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2w_128(a, src.as_i16x8(), k)) }
 }
@@ -14104,7 +14104,7 @@ pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi16(_mm_setzero_si128(), k, a)
 }
@@ -14116,7 +14116,7 @@ pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epi16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -14129,7 +14129,7 @@ pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvttph2w_256(a, src.as_i16x16(), k)) }
 }
@@ -14142,7 +14142,7 @@ pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epi16(_mm256_setzero_si256(), k, a)
 }
@@ -14154,7 +14154,7 @@ pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epi16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -14167,7 +14167,7 @@ pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvttph2w_512(
@@ -14187,7 +14187,7 @@ pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epi16(_mm512_setzero_si512(), k, a)
 }
@@ -14202,7 +14202,7 @@ pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtt_roundph_epi16<const SAE: i32>(a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -14219,7 +14219,7 @@ pub fn _mm512_cvtt_roundph_epi16<const SAE: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtt_roundph_epi16<const SAE: i32>(
     src: __m512i,
     k: __mmask32,
@@ -14242,7 +14242,7 @@ pub fn _mm512_mask_cvtt_roundph_epi16<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtt_roundph_epi16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi16::<SAE>(_mm512_setzero_si512(), k, a)
@@ -14255,7 +14255,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi16<const SAE: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu16(_mm_undefined_si128(), 0xff, a)
 }
@@ -14268,7 +14268,7 @@ pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2uw_128(a, src.as_u16x8(), k)) }
 }
@@ -14281,7 +14281,7 @@ pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu16(_mm_setzero_si128(), k, a)
 }
@@ -14293,7 +14293,7 @@ pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epu16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -14306,7 +14306,7 @@ pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvttph2uw_256(a, src.as_u16x16(), k)) }
 }
@@ -14319,7 +14319,7 @@ pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epu16(_mm256_setzero_si256(), k, a)
 }
@@ -14331,7 +14331,7 @@ pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epu16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -14344,7 +14344,7 @@ pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvttph2uw_512(
@@ -14364,7 +14364,7 @@ pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epu16(_mm512_setzero_si512(), k, a)
 }
@@ -14379,7 +14379,7 @@ pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -14396,7 +14396,7 @@ pub fn _mm512_cvtt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtt_roundph_epu16<const SAE: i32>(
     src: __m512i,
     k: __mmask32,
@@ -14419,7 +14419,7 @@ pub fn _mm512_mask_cvtt_roundph_epu16<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu16::<SAE>(_mm512_setzero_si512(), k, a)
@@ -14432,7 +14432,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi32(_mm_undefined_si128(), 0xff, a)
 }
@@ -14444,7 +14444,7 @@ pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2dq_128(a, src.as_i32x4(), k)) }
 }
@@ -14456,7 +14456,7 @@ pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi32(_mm_setzero_si128(), k, a)
 }
@@ -14468,7 +14468,7 @@ pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -14480,7 +14480,7 @@ pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2dq_256(a, src.as_i32x8(), k)) }
 }
@@ -14492,7 +14492,7 @@ pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi32(_mm256_setzero_si256(), k, a)
 }
@@ -14504,7 +14504,7 @@ pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epi32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -14516,7 +14516,7 @@ pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvtph2dq_512(
@@ -14535,7 +14535,7 @@ pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epi32(_mm512_setzero_si512(), k, a)
 }
@@ -14556,7 +14556,7 @@ pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_epi32<const ROUNDING: i32>(a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi32::<ROUNDING>(_mm512_undefined_epi32(), 0xffff, a)
@@ -14578,7 +14578,7 @@ pub fn _mm512_cvt_roundph_epi32<const ROUNDING: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_epi32<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask16,
@@ -14606,7 +14606,7 @@ pub fn _mm512_mask_cvt_roundph_epi32<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_epi32<const ROUNDING: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi32::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -14619,7 +14619,7 @@ pub fn _mm512_maskz_cvt_roundph_epi32<const ROUNDING: i32>(k: __mmask16, a: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsh_i32(a: __m128h) -> i32 {
     unsafe { vcvtsh2si32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -14640,7 +14640,7 @@ pub fn _mm_cvtsh_i32(a: __m128h) -> i32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsh_i32<const ROUNDING: i32>(a: __m128h) -> i32 {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -14655,7 +14655,7 @@ pub fn _mm_cvt_roundsh_i32<const ROUNDING: i32>(a: __m128h) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu32(_mm_undefined_si128(), 0xff, a)
 }
@@ -14667,7 +14667,7 @@ pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2udq_128(a, src.as_u32x4(), k)) }
 }
@@ -14679,7 +14679,7 @@ pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu32(_mm_setzero_si128(), k, a)
 }
@@ -14691,7 +14691,7 @@ pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -14703,7 +14703,7 @@ pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2udq_256(a, src.as_u32x8(), k)) }
 }
@@ -14715,7 +14715,7 @@ pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu32(_mm256_setzero_si256(), k, a)
 }
@@ -14727,7 +14727,7 @@ pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epu32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -14739,7 +14739,7 @@ pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvtph2udq_512(
@@ -14758,7 +14758,7 @@ pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epu32(_mm512_setzero_si512(), k, a)
 }
@@ -14779,7 +14779,7 @@ pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_epu32<const ROUNDING: i32>(a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu32::<ROUNDING>(_mm512_undefined_epi32(), 0xffff, a)
@@ -14801,7 +14801,7 @@ pub fn _mm512_cvt_roundph_epu32<const ROUNDING: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_epu32<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask16,
@@ -14829,7 +14829,7 @@ pub fn _mm512_mask_cvt_roundph_epu32<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_epu32<const ROUNDING: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu32::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -14842,7 +14842,7 @@ pub fn _mm512_maskz_cvt_roundph_epu32<const ROUNDING: i32>(k: __mmask16, a: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsh_u32(a: __m128h) -> u32 {
     unsafe { vcvtsh2usi32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -14857,7 +14857,7 @@ pub fn _mm_cvtsh_u32(a: __m128h) -> u32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
     unsafe {
         static_assert_rounding!(SAE);
@@ -14872,7 +14872,7 @@ pub fn _mm_cvt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi32(_mm_undefined_si128(), 0xff, a)
 }
@@ -14884,7 +14884,7 @@ pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2dq_128(a, src.as_i32x4(), k)) }
 }
@@ -14896,7 +14896,7 @@ pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi32(_mm_setzero_si128(), k, a)
 }
@@ -14908,7 +14908,7 @@ pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -14920,7 +14920,7 @@ pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2dq_256(a, src.as_i32x8(), k)) }
 }
@@ -14932,7 +14932,7 @@ pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi32(_mm256_setzero_si256(), k, a)
 }
@@ -14944,7 +14944,7 @@ pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epi32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -14956,7 +14956,7 @@ pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvttph2dq_512(
@@ -14975,7 +14975,7 @@ pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epi32(_mm512_setzero_si512(), k, a)
 }
@@ -14990,7 +14990,7 @@ pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtt_roundph_epi32<const SAE: i32>(a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi32::<SAE>(_mm512_undefined_epi32(), 0xffff, a)
@@ -15006,7 +15006,7 @@ pub fn _mm512_cvtt_roundph_epi32<const SAE: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtt_roundph_epi32<const SAE: i32>(
     src: __m512i,
     k: __mmask16,
@@ -15028,7 +15028,7 @@ pub fn _mm512_mask_cvtt_roundph_epi32<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtt_roundph_epi32<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi32::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15041,7 +15041,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi32<const SAE: i32>(k: __mmask16, a: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttsh_i32(a: __m128h) -> i32 {
     unsafe { vcvttsh2si32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -15056,7 +15056,7 @@ pub fn _mm_cvttsh_i32(a: __m128h) -> i32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtt_roundsh_i32<const SAE: i32>(a: __m128h) -> i32 {
     unsafe {
         static_assert_sae!(SAE);
@@ -15071,7 +15071,7 @@ pub fn _mm_cvtt_roundsh_i32<const SAE: i32>(a: __m128h) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu32(_mm_undefined_si128(), 0xff, a)
 }
@@ -15083,7 +15083,7 @@ pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2udq_128(a, src.as_u32x4(), k)) }
 }
@@ -15095,7 +15095,7 @@ pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu32(_mm_setzero_si128(), k, a)
 }
@@ -15107,7 +15107,7 @@ pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15119,7 +15119,7 @@ pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2udq_256(a, src.as_u32x8(), k)) }
 }
@@ -15131,7 +15131,7 @@ pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu32(_mm256_setzero_si256(), k, a)
 }
@@ -15143,7 +15143,7 @@ pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epu32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -15155,7 +15155,7 @@ pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvttph2udq_512(
@@ -15174,7 +15174,7 @@ pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epu32(_mm512_setzero_si512(), k, a)
 }
@@ -15189,7 +15189,7 @@ pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtt_roundph_epu32<const SAE: i32>(a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu32::<SAE>(_mm512_undefined_epi32(), 0xffff, a)
@@ -15205,7 +15205,7 @@ pub fn _mm512_cvtt_roundph_epu32<const SAE: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtt_roundph_epu32<const SAE: i32>(
     src: __m512i,
     k: __mmask16,
@@ -15227,7 +15227,7 @@ pub fn _mm512_mask_cvtt_roundph_epu32<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtt_roundph_epu32<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu32::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15240,7 +15240,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu32<const SAE: i32>(k: __mmask16, a: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttsh_u32(a: __m128h) -> u32 {
     unsafe { vcvttsh2usi32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -15255,7 +15255,7 @@ pub fn _mm_cvttsh_u32(a: __m128h) -> u32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
     unsafe {
         static_assert_sae!(SAE);
@@ -15270,7 +15270,7 @@ pub fn _mm_cvtt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15282,7 +15282,7 @@ pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2qq_128(a, src.as_i64x2(), k)) }
 }
@@ -15294,7 +15294,7 @@ pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi64(_mm_setzero_si128(), k, a)
 }
@@ -15306,7 +15306,7 @@ pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15318,7 +15318,7 @@ pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2qq_256(a, src.as_i64x4(), k)) }
 }
@@ -15330,7 +15330,7 @@ pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi64(_mm256_setzero_si256(), k, a)
 }
@@ -15342,7 +15342,7 @@ pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epi64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15354,7 +15354,7 @@ pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvtph2qq_512(
@@ -15373,7 +15373,7 @@ pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epi64(_mm512_setzero_si512(), k, a)
 }
@@ -15394,7 +15394,7 @@ pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_epi64<const ROUNDING: i32>(a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi64::<ROUNDING>(_mm512_undefined_epi32(), 0xff, a)
@@ -15416,7 +15416,7 @@ pub fn _mm512_cvt_roundph_epi64<const ROUNDING: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_epi64<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15444,7 +15444,7 @@ pub fn _mm512_mask_cvt_roundph_epi64<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_epi64<const ROUNDING: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi64::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -15457,7 +15457,7 @@ pub fn _mm512_maskz_cvt_roundph_epi64<const ROUNDING: i32>(k: __mmask8, a: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15469,7 +15469,7 @@ pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2uqq_128(a, src.as_u64x2(), k)) }
 }
@@ -15481,7 +15481,7 @@ pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu64(_mm_setzero_si128(), k, a)
 }
@@ -15493,7 +15493,7 @@ pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15505,7 +15505,7 @@ pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2uqq_256(a, src.as_u64x4(), k)) }
 }
@@ -15517,7 +15517,7 @@ pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu64(_mm256_setzero_si256(), k, a)
 }
@@ -15529,7 +15529,7 @@ pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epu64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15541,7 +15541,7 @@ pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvtph2uqq_512(
@@ -15560,7 +15560,7 @@ pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epu64(_mm512_setzero_si512(), k, a)
 }
@@ -15581,7 +15581,7 @@ pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_epu64<const ROUNDING: i32>(a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu64::<ROUNDING>(_mm512_undefined_epi32(), 0xff, a)
@@ -15603,7 +15603,7 @@ pub fn _mm512_cvt_roundph_epu64<const ROUNDING: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_epu64<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15631,7 +15631,7 @@ pub fn _mm512_mask_cvt_roundph_epu64<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_epu64<const ROUNDING: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu64::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -15644,7 +15644,7 @@ pub fn _mm512_maskz_cvt_roundph_epu64<const ROUNDING: i32>(k: __mmask8, a: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15656,7 +15656,7 @@ pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2qq_128(a, src.as_i64x2(), k)) }
 }
@@ -15668,7 +15668,7 @@ pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi64(_mm_setzero_si128(), k, a)
 }
@@ -15680,7 +15680,7 @@ pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15692,7 +15692,7 @@ pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2qq_256(a, src.as_i64x4(), k)) }
 }
@@ -15704,7 +15704,7 @@ pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi64(_mm256_setzero_si256(), k, a)
 }
@@ -15716,7 +15716,7 @@ pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epi64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15728,7 +15728,7 @@ pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvttph2qq_512(
@@ -15747,7 +15747,7 @@ pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epi64(_mm512_setzero_si512(), k, a)
 }
@@ -15762,7 +15762,7 @@ pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtt_roundph_epi64<const SAE: i32>(a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi64::<SAE>(_mm512_undefined_epi32(), 0xff, a)
@@ -15778,7 +15778,7 @@ pub fn _mm512_cvtt_roundph_epi64<const SAE: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtt_roundph_epi64<const SAE: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15800,7 +15800,7 @@ pub fn _mm512_mask_cvtt_roundph_epi64<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtt_roundph_epi64<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi64::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15813,7 +15813,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi64<const SAE: i32>(k: __mmask8, a: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15825,7 +15825,7 @@ pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2uqq_128(a, src.as_u64x2(), k)) }
 }
@@ -15837,7 +15837,7 @@ pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu64(_mm_setzero_si128(), k, a)
 }
@@ -15849,7 +15849,7 @@ pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15861,7 +15861,7 @@ pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2uqq_256(a, src.as_u64x4(), k)) }
 }
@@ -15873,7 +15873,7 @@ pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu64(_mm256_setzero_si256(), k, a)
 }
@@ -15885,7 +15885,7 @@ pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epu64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15897,7 +15897,7 @@ pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvttph2uqq_512(
@@ -15916,7 +15916,7 @@ pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epu64(_mm512_setzero_si512(), k, a)
 }
@@ -15931,7 +15931,7 @@ pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtt_roundph_epu64<const SAE: i32>(a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu64::<SAE>(_mm512_undefined_epi32(), 0xff, a)
@@ -15947,7 +15947,7 @@ pub fn _mm512_cvtt_roundph_epu64<const SAE: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtt_roundph_epu64<const SAE: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15969,7 +15969,7 @@ pub fn _mm512_mask_cvtt_roundph_epu64<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtt_roundph_epu64<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu64::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15982,7 +15982,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu64<const SAE: i32>(k: __mmask8, a: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 {
     _mm_mask_cvtxph_ps(_mm_setzero_ps(), 0xff, a)
 }
@@ -15995,7 +15995,7 @@ pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 {
     unsafe { vcvtph2psx_128(a, src, k) }
 }
@@ -16008,7 +16008,7 @@ pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 {
     _mm_mask_cvtxph_ps(_mm_setzero_ps(), k, a)
 }
@@ -16020,7 +16020,7 @@ pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 {
     _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), 0xff, a)
 }
@@ -16033,7 +16033,7 @@ pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 {
     unsafe { vcvtph2psx_256(a, src, k) }
 }
@@ -16046,7 +16046,7 @@ pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 {
     _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), k, a)
 }
@@ -16058,7 +16058,7 @@ pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 {
     _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), 0xffff, a)
 }
@@ -16071,7 +16071,7 @@ pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 {
     unsafe { vcvtph2psx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16084,7 +16084,7 @@ pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 {
     _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), k, a)
 }
@@ -16099,7 +16099,7 @@ pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtx_roundph_ps<const SAE: i32>(a: __m256h) -> __m512 {
     static_assert_sae!(SAE);
     _mm512_mask_cvtx_roundph_ps::<SAE>(_mm512_setzero_ps(), 0xffff, a)
@@ -16116,7 +16116,7 @@ pub fn _mm512_cvtx_roundph_ps<const SAE: i32>(a: __m256h) -> __m512 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtx_roundph_ps<const SAE: i32>(
     src: __m512,
     k: __mmask16,
@@ -16139,7 +16139,7 @@ pub fn _mm512_mask_cvtx_roundph_ps<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtx_roundph_ps<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512 {
     static_assert_sae!(SAE);
     _mm512_mask_cvtx_roundph_ps::<SAE>(_mm512_setzero_ps(), k, a)
@@ -16153,7 +16153,7 @@ pub fn _mm512_maskz_cvtx_roundph_ps<const SAE: i32>(k: __mmask16, a: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 {
     _mm_mask_cvtsh_ss(a, 0xff, a, b)
 }
@@ -16167,7 +16167,7 @@ pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m128 {
     unsafe { vcvtsh2ss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16181,7 +16181,7 @@ pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
     _mm_mask_cvtsh_ss(_mm_set_ss(0.0), k, a, b)
 }
@@ -16197,7 +16197,7 @@ pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsh_ss<const SAE: i32>(a: __m128, b: __m128h) -> __m128 {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_ss::<SAE>(_mm_undefined_ps(), 0xff, a, b)
@@ -16215,7 +16215,7 @@ pub fn _mm_cvt_roundsh_ss<const SAE: i32>(a: __m128, b: __m128h) -> __m128 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvt_roundsh_ss<const SAE: i32>(
     src: __m128,
     k: __mmask8,
@@ -16240,7 +16240,7 @@ pub fn _mm_mask_cvt_roundsh_ss<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvt_roundsh_ss<const SAE: i32>(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_ss::<SAE>(_mm_set_ss(0.0), k, a, b)
@@ -16253,7 +16253,7 @@ pub fn _mm_maskz_cvt_roundsh_ss<const SAE: i32>(k: __mmask8, a: __m128, b: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtph_pd(a: __m128h) -> __m128d {
     _mm_mask_cvtph_pd(_mm_setzero_pd(), 0xff, a)
 }
@@ -16266,7 +16266,7 @@ pub fn _mm_cvtph_pd(a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d {
     unsafe { vcvtph2pd_128(a, src, k) }
 }
@@ -16279,7 +16279,7 @@ pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d {
     _mm_mask_cvtph_pd(_mm_setzero_pd(), k, a)
 }
@@ -16291,7 +16291,7 @@ pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d {
     _mm256_mask_cvtph_pd(_mm256_setzero_pd(), 0xff, a)
 }
@@ -16304,7 +16304,7 @@ pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d {
     unsafe { vcvtph2pd_256(a, src, k) }
 }
@@ -16317,7 +16317,7 @@ pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d {
     _mm256_mask_cvtph_pd(_mm256_setzero_pd(), k, a)
 }
@@ -16329,7 +16329,7 @@ pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d {
     _mm512_mask_cvtph_pd(_mm512_setzero_pd(), 0xff, a)
 }
@@ -16342,7 +16342,7 @@ pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d {
     unsafe { vcvtph2pd_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16355,7 +16355,7 @@ pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d {
     _mm512_mask_cvtph_pd(_mm512_setzero_pd(), k, a)
 }
@@ -16370,7 +16370,7 @@ pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_cvt_roundph_pd<const SAE: i32>(a: __m128h) -> __m512d {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_pd::<SAE>(_mm512_setzero_pd(), 0xff, a)
@@ -16387,7 +16387,7 @@ pub fn _mm512_cvt_roundph_pd<const SAE: i32>(a: __m128h) -> __m512d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_mask_cvt_roundph_pd<const SAE: i32>(
     src: __m512d,
     k: __mmask8,
@@ -16410,7 +16410,7 @@ pub fn _mm512_mask_cvt_roundph_pd<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm512_maskz_cvt_roundph_pd<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512d {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_pd::<SAE>(_mm512_setzero_pd(), k, a)
@@ -16424,7 +16424,7 @@ pub fn _mm512_maskz_cvt_roundph_pd<const SAE: i32>(k: __mmask8, a: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d {
     _mm_mask_cvtsh_sd(a, 0xff, a, b)
 }
@@ -16438,7 +16438,7 @@ pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
     unsafe { vcvtsh2sd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16451,7 +16451,7 @@ pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
     _mm_mask_cvtsh_sd(_mm_set_sd(0.0), k, a, b)
 }
@@ -16467,7 +16467,7 @@ pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsh_sd<const SAE: i32>(a: __m128d, b: __m128h) -> __m128d {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_sd::<SAE>(a, 0xff, a, b)
@@ -16485,7 +16485,7 @@ pub fn _mm_cvt_roundsh_sd<const SAE: i32>(a: __m128d, b: __m128h) -> __m128d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_mask_cvt_roundsh_sd<const SAE: i32>(
     src: __m128d,
     k: __mmask8,
@@ -16509,7 +16509,7 @@ pub fn _mm_mask_cvt_roundsh_sd<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_maskz_cvt_roundsh_sd<const SAE: i32>(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_sd::<SAE>(_mm_set_sd(0.0), k, a, b)
@@ -16553,7 +16553,7 @@ pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si16)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
     unsafe { simd_extract!(a.as_i16x8(), 0) }
@@ -16564,7 +16564,7 @@ pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi16_si128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i {
     unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) }
diff --git a/crates/core_arch/src/x86/avxneconvert.rs b/crates/core_arch/src/x86/avxneconvert.rs
index b92ec823ec..a53d6d97e8 100644
--- a/crates/core_arch/src/x86/avxneconvert.rs
+++ b/crates/core_arch/src/x86/avxneconvert.rs
@@ -87,7 +87,7 @@ pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneeph2ps))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 {
     transmute(cvtneeph2ps_128(a))
 }
@@ -99,7 +99,7 @@ pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneeph2ps))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 {
     transmute(cvtneeph2ps_256(a))
 }
@@ -135,7 +135,7 @@ pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneoph2ps))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 {
     transmute(cvtneoph2ps_128(a))
 }
@@ -147,7 +147,7 @@ pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneoph2ps))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 {
     transmute(cvtneoph2ps_256(a))
 }
diff --git a/crates/core_arch/src/x86/mod.rs b/crates/core_arch/src/x86/mod.rs
index 7612cffd07..c40fbd3ca3 100644
--- a/crates/core_arch/src/x86/mod.rs
+++ b/crates/core_arch/src/x86/mod.rs
@@ -401,7 +401,7 @@ types! {
 }
 
 types! {
-    #![unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+    #![stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 
     /// 128-bit wide set of 8 `f16` types, x86-specific
     ///
@@ -768,7 +768,7 @@ mod avxneconvert;
 pub use self::avxneconvert::*;
 
 mod avx512fp16;
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub use self::avx512fp16::*;
 
 mod kl;
diff --git a/crates/core_arch/src/x86_64/avx512fp16.rs b/crates/core_arch/src/x86_64/avx512fp16.rs
index 955c6ccc75..d0123f22d7 100644
--- a/crates/core_arch/src/x86_64/avx512fp16.rs
+++ b/crates/core_arch/src/x86_64/avx512fp16.rs
@@ -10,7 +10,7 @@ use stdarch_test::assert_instr;
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h {
     unsafe { vcvtsi642sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -32,7 +32,7 @@ pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundi64_sh<const ROUNDING: i32>(a: __m128h, b: i64) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -48,7 +48,7 @@ pub fn _mm_cvt_roundi64_sh<const ROUNDING: i32>(a: __m128h, b: i64) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h {
     unsafe { vcvtusi642sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -70,7 +70,7 @@ pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundu64_sh<const ROUNDING: i32>(a: __m128h, b: u64) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -85,7 +85,7 @@ pub fn _mm_cvt_roundu64_sh<const ROUNDING: i32>(a: __m128h, b: u64) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsh_i64(a: __m128h) -> i64 {
     unsafe { vcvtsh2si64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -106,7 +106,7 @@ pub fn _mm_cvtsh_i64(a: __m128h) -> i64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsh_i64<const ROUNDING: i32>(a: __m128h) -> i64 {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -121,7 +121,7 @@ pub fn _mm_cvt_roundsh_i64<const ROUNDING: i32>(a: __m128h) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtsh_u64(a: __m128h) -> u64 {
     unsafe { vcvtsh2usi64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -142,7 +142,7 @@ pub fn _mm_cvtsh_u64(a: __m128h) -> u64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvt_roundsh_u64<const ROUNDING: i32>(a: __m128h) -> u64 {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -157,7 +157,7 @@ pub fn _mm_cvt_roundsh_u64<const ROUNDING: i32>(a: __m128h) -> u64 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttsh_i64(a: __m128h) -> i64 {
     unsafe { vcvttsh2si64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -172,7 +172,7 @@ pub fn _mm_cvttsh_i64(a: __m128h) -> i64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtt_roundsh_i64<const SAE: i32>(a: __m128h) -> i64 {
     unsafe {
         static_assert_sae!(SAE);
@@ -187,7 +187,7 @@ pub fn _mm_cvtt_roundsh_i64<const SAE: i32>(a: __m128h) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi))]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvttsh_u64(a: __m128h) -> u64 {
     unsafe { vcvttsh2usi64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -202,7 +202,7 @@ pub fn _mm_cvttsh_u64(a: __m128h) -> u64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub fn _mm_cvtt_roundsh_u64<const SAE: i32>(a: __m128h) -> u64 {
     unsafe {
         static_assert_sae!(SAE);
diff --git a/crates/core_arch/src/x86_64/mod.rs b/crates/core_arch/src/x86_64/mod.rs
index 7d681882be..c6dc7a85e7 100644
--- a/crates/core_arch/src/x86_64/mod.rs
+++ b/crates/core_arch/src/x86_64/mod.rs
@@ -75,7 +75,7 @@ mod bt;
 pub use self::bt::*;
 
 mod avx512fp16;
-#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
 pub use self::avx512fp16::*;
 
 mod amx;

From 2f540336c2ced869e6b08c2e5d8bf329a848cd26 Mon Sep 17 00:00:00 2001
From: Urgau <urgau@numericable.fr>
Date: Mon, 8 Dec 2025 18:58:56 +0100
Subject: [PATCH 073/326] Remove `[no-mentions]` handler in our triagebot
 config

https://github.blog/changelog/2025-11-07-removing-notifications-for-mentions-in-commit-messages/
---
 triagebot.toml | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/triagebot.toml b/triagebot.toml
index 2c281c8f7d..621f39b2cb 100644
--- a/triagebot.toml
+++ b/triagebot.toml
@@ -56,7 +56,3 @@ Thanks!
 # Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html
 [issue-links]
 check-commits = false
-
-# Prevents mentions in commits to avoid users being spammed
-# Documentation at: https://forge.rust-lang.org/triagebot/no-mentions.html
-[no-mentions]

From 7ac0dbada92c7106531da5173d860dedb7336e1e Mon Sep 17 00:00:00 2001
From: Manuel Drehwald <git@manuel.drehwald.info>
Date: Tue, 9 Dec 2025 10:52:13 +0100
Subject: [PATCH 074/326] thread, grid, and block dim/idx can only return
 non-negative values

---
 crates/core_arch/src/nvptx/mod.rs | 48 +++++++++++++++----------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/crates/core_arch/src/nvptx/mod.rs b/crates/core_arch/src/nvptx/mod.rs
index 8d16dfb53d..5471ef8198 100644
--- a/crates/core_arch/src/nvptx/mod.rs
+++ b/crates/core_arch/src/nvptx/mod.rs
@@ -23,29 +23,29 @@ unsafe extern "C" {
     #[link_name = "llvm.nvvm.barrier0"]
     fn syncthreads() -> ();
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.x"]
-    fn block_dim_x() -> i32;
+    fn block_dim_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.y"]
-    fn block_dim_y() -> i32;
+    fn block_dim_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.z"]
-    fn block_dim_z() -> i32;
+    fn block_dim_z() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.x"]
-    fn block_idx_x() -> i32;
+    fn block_idx_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.y"]
-    fn block_idx_y() -> i32;
+    fn block_idx_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.z"]
-    fn block_idx_z() -> i32;
+    fn block_idx_z() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.x"]
-    fn grid_dim_x() -> i32;
+    fn grid_dim_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.y"]
-    fn grid_dim_y() -> i32;
+    fn grid_dim_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.z"]
-    fn grid_dim_z() -> i32;
+    fn grid_dim_z() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.x"]
-    fn thread_idx_x() -> i32;
+    fn thread_idx_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.y"]
-    fn thread_idx_y() -> i32;
+    fn thread_idx_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.z"]
-    fn thread_idx_z() -> i32;
+    fn thread_idx_z() -> u32;
 }
 
 /// Synchronizes all threads in the block.
@@ -58,84 +58,84 @@ pub unsafe fn _syncthreads() -> () {
 /// x-th thread-block dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_dim_x() -> i32 {
+pub unsafe fn _block_dim_x() -> u32 {
     block_dim_x()
 }
 
 /// y-th thread-block dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_dim_y() -> i32 {
+pub unsafe fn _block_dim_y() -> u32 {
     block_dim_y()
 }
 
 /// z-th thread-block dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_dim_z() -> i32 {
+pub unsafe fn _block_dim_z() -> u32 {
     block_dim_z()
 }
 
 /// x-th thread-block index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_idx_x() -> i32 {
+pub unsafe fn _block_idx_x() -> u32 {
     block_idx_x()
 }
 
 /// y-th thread-block index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_idx_y() -> i32 {
+pub unsafe fn _block_idx_y() -> u32 {
     block_idx_y()
 }
 
 /// z-th thread-block index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_idx_z() -> i32 {
+pub unsafe fn _block_idx_z() -> u32 {
     block_idx_z()
 }
 
 /// x-th block-grid dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _grid_dim_x() -> i32 {
+pub unsafe fn _grid_dim_x() -> u32 {
     grid_dim_x()
 }
 
 /// y-th block-grid dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _grid_dim_y() -> i32 {
+pub unsafe fn _grid_dim_y() -> u32 {
     grid_dim_y()
 }
 
 /// z-th block-grid dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _grid_dim_z() -> i32 {
+pub unsafe fn _grid_dim_z() -> u32 {
     grid_dim_z()
 }
 
 /// x-th thread index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _thread_idx_x() -> i32 {
+pub unsafe fn _thread_idx_x() -> u32 {
     thread_idx_x()
 }
 
 /// y-th thread index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _thread_idx_y() -> i32 {
+pub unsafe fn _thread_idx_y() -> u32 {
     thread_idx_y()
 }
 
 /// z-th thread index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _thread_idx_z() -> i32 {
+pub unsafe fn _thread_idx_z() -> u32 {
     thread_idx_z()
 }
 

From 8abeb42b8d7629872f28ba5cbfa9f5317ccbc706 Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Sun, 14 Dec 2025 16:01:13 +0800
Subject: [PATCH 075/326] use simd_reduce_add_ordered on aarch64

---
 .../core_arch/src/aarch64/neon/generated.rs   | 32 +++++++++----------
 .../spec/neon/aarch64.spec.yml                | 16 +++++-----
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index ce864cc7d9..b1d36343a0 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -613,7 +613,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddv_s32(a: int32x2_t) -> i32 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"]
@@ -622,7 +622,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_s8(a: int8x8_t) -> i8 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"]
@@ -631,7 +631,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_s8(a: int8x16_t) -> i8 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"]
@@ -640,7 +640,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_s16(a: int16x4_t) -> i16 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"]
@@ -649,7 +649,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_s16(a: int16x8_t) -> i16 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"]
@@ -658,7 +658,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_s32(a: int32x4_t) -> i32 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"]
@@ -667,7 +667,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddv_u32(a: uint32x2_t) -> u32 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"]
@@ -676,7 +676,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_u8(a: uint8x8_t) -> u8 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"]
@@ -685,7 +685,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"]
@@ -694,7 +694,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_u16(a: uint16x4_t) -> u16 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"]
@@ -703,7 +703,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"]
@@ -712,7 +712,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"]
@@ -721,7 +721,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddvq_s64(a: int64x2_t) -> i64 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"]
@@ -730,7 +730,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
@@ -15774,7 +15774,7 @@ pub fn vpadds_f32(a: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddd_s64(a: int64x2_t) -> i64 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"]
@@ -15783,7 +15783,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
-    unsafe { simd_reduce_add_unordered(a) }
+    unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 48c12779a8..41ba11fb06 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -13261,7 +13261,7 @@ intrinsics:
     types:
       - [int64x2_t, i64]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vpaddd_u64"
     doc: "Add pairwise"
@@ -13274,7 +13274,7 @@ intrinsics:
     types:
       - [uint64x2_t, u64]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
@@ -13291,7 +13291,7 @@ intrinsics:
       - [int16x8_t, i16]
       - [int32x4_t, i32]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
@@ -13304,7 +13304,7 @@ intrinsics:
     types:
       - [int32x2_t, i32]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
@@ -13317,7 +13317,7 @@ intrinsics:
     types:
       - [int64x2_t, i64]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
@@ -13334,7 +13334,7 @@ intrinsics:
       - [uint16x8_t, u16]
       - [uint32x4_t, u32]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
@@ -13347,7 +13347,7 @@ intrinsics:
     types:
       - [uint32x2_t, u32, i32]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
@@ -13360,7 +13360,7 @@ intrinsics:
     types:
       - [uint64x2_t, u64, i64]
     compose:
-      - FnCall: [simd_reduce_add_unordered, [a]]
+      - FnCall: [simd_reduce_add_ordered, [a, 0]]
 
   - name: "vaddlv{neon_type[0].no}"
     doc: "Signed Add Long across Vector"

From 2f7d8e3d0d87f884bef097c0db7100699ee491fd Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Wed, 17 Dec 2025 01:41:29 +0530
Subject: [PATCH 076/326] panic if cpuid is called with SGX

---
 crates/core_arch/src/x86/cpuid.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/crates/core_arch/src/x86/cpuid.rs b/crates/core_arch/src/x86/cpuid.rs
index 84dcf75492..b35699bd7a 100644
--- a/crates/core_arch/src/x86/cpuid.rs
+++ b/crates/core_arch/src/x86/cpuid.rs
@@ -59,6 +59,10 @@ pub struct CpuidResult {
 #[cfg_attr(test, assert_instr(cpuid))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
+    if cfg!(target_env = "sgx") {
+        panic!("`__cpuid` cannot be used in SGX");
+    }
+
     let eax;
     let ebx;
     let ecx;

From 7426ad5b968bae9f4078dba1f3f63ffabea3e4b0 Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Mon, 15 Dec 2025 17:06:56 +0000
Subject: [PATCH 077/326] Remove fp16 target feature from some aarch64
 intrinsics

This seems to affect codegen on a lot of Arm intrinsics so I've avoided
making the change there.
---
 .../core_arch/src/aarch64/neon/generated.rs   |  20 +-
 .../src/arm_shared/neon/generated.rs          | 233 ++++++++++++------
 .../spec/neon/aarch64.spec.yml                |   3 -
 .../spec/neon/arm_shared.spec.yml             |  82 +++---
 4 files changed, 207 insertions(+), 131 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index ce864cc7d9..f1291c8fbd 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -7217,8 +7217,8 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 #[doc = "Floating-point convert to lower precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
-#[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
@@ -7227,8 +7227,8 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 #[doc = "Floating-point convert to higher precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
-#[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
@@ -21492,7 +21492,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21503,7 +21503,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21515,7 +21515,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21526,7 +21526,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21541,7 +21541,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21552,7 +21552,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21566,7 +21566,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21577,7 +21577,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,fp16")]
+#[target_feature(enable = "neon")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index d45454c696..cfd9c20186 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -7569,8 +7569,9 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -7785,13 +7786,14 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcreate_f16(a: u64) -> float16x4_t {
@@ -7801,13 +7803,14 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcreate_f16(a: u64) -> float16x4_t {
@@ -8305,13 +8308,14 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 # [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(fcvtn)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
@@ -8380,13 +8384,14 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(fcvtl)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
@@ -9545,6 +9550,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
 #[cfg_attr(
@@ -9552,7 +9558,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
     assert_instr(dup, N = 2)
 )]
 #[rustc_legacy_const_generics(1)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
@@ -9562,6 +9568,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
 #[cfg_attr(
@@ -9569,7 +9576,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
     assert_instr(dup, N = 2)
 )]
 #[rustc_legacy_const_generics(1)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
@@ -10108,6 +10115,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
 #[cfg_attr(
@@ -10115,7 +10123,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
     assert_instr(dup, N = 4)
 )]
 #[rustc_legacy_const_generics(1)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
@@ -10125,6 +10133,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
 #[cfg_attr(
@@ -10132,7 +10141,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
     assert_instr(dup, N = 4)
 )]
 #[rustc_legacy_const_generics(1)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
@@ -10671,13 +10680,14 @@ pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(dup)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_n_f16(a: f16) -> float16x4_t {
@@ -10686,13 +10696,14 @@ pub fn vdup_n_f16(a: f16) -> float16x4_t {
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(dup)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_n_f16(a: f16) -> float16x8_t {
@@ -12829,8 +12840,9 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -12840,8 +12852,9 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -13082,14 +13095,15 @@ pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop, LANE = 0)
 )]
 #[rustc_legacy_const_generics(1)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
@@ -13099,14 +13113,15 @@ pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop, LANE = 0)
 )]
 #[rustc_legacy_const_generics(1)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
@@ -14457,13 +14472,14 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1r)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
@@ -14475,13 +14491,14 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1r)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
@@ -15123,13 +15140,14 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
@@ -15148,13 +15166,14 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
@@ -15173,13 +15192,14 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
@@ -15198,13 +15218,14 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
@@ -15223,13 +15244,14 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
@@ -15248,13 +15270,14 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld1)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
@@ -15654,6 +15677,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
 #[cfg_attr(
@@ -15661,7 +15685,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
     assert_instr(ld1, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t) -> float16x4_t {
@@ -15673,6 +15697,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
 #[cfg_attr(
@@ -15680,7 +15705,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
     assert_instr(ld1, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t) -> float16x8_t {
@@ -19458,9 +19483,10 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -19476,9 +19502,10 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -19494,12 +19521,13 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld2r)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
@@ -19517,12 +19545,13 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld2r)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
@@ -20435,10 +20464,11 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
@@ -20453,10 +20483,11 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
@@ -20471,12 +20502,13 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld2)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
@@ -20494,12 +20526,13 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld2)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
@@ -20801,7 +20834,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
@@ -20827,7 +20860,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
@@ -20849,13 +20882,14 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld2, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
@@ -20875,13 +20909,14 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld2, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
@@ -22031,10 +22066,11 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
@@ -22049,10 +22085,11 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
@@ -22067,12 +22104,13 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld3r)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
@@ -22090,12 +22128,13 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld3r)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
@@ -23030,10 +23069,11 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
@@ -23048,10 +23088,11 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
@@ -23066,12 +23107,13 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld3)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
@@ -23089,12 +23131,13 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld3)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
@@ -23396,7 +23439,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
@@ -23423,7 +23466,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
@@ -23446,13 +23489,14 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld3, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
@@ -23477,13 +23521,14 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(ld3, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
@@ -31524,13 +31569,14 @@ pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(dup)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmov_n_f16(a: f16) -> float16x4_t {
@@ -31539,13 +31585,14 @@ pub fn vmov_n_f16(a: f16) -> float16x4_t {
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(dup)
 )]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmovq_n_f16(a: f16) -> float16x8_t {
@@ -63675,9 +63722,10 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -63699,9 +63747,10 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -64313,6 +64362,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -64320,7 +64370,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
     assert_instr(nop, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
@@ -64332,6 +64382,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -64339,7 +64390,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
     assert_instr(nop, LANE = 0)
 )]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
@@ -66933,8 +66984,9 @@ pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(st2))]
@@ -66953,8 +67005,9 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(st2))]
@@ -66973,9 +67026,10 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst2))]
@@ -66991,9 +67045,10 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst2))]
@@ -67289,10 +67344,11 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
@@ -67311,10 +67367,11 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
@@ -67333,11 +67390,12 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
@@ -67353,11 +67411,12 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
@@ -68157,9 +68216,10 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst3))]
@@ -68175,9 +68235,10 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst3))]
@@ -68193,8 +68254,9 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(st3))]
@@ -68213,8 +68275,9 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(st3))]
@@ -68513,11 +68576,12 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
@@ -68540,11 +68604,12 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
@@ -68567,10 +68632,11 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
@@ -68589,10 +68655,11 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
@@ -69437,9 +69504,10 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst4))]
@@ -69462,9 +69530,10 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(vst4))]
@@ -69487,8 +69556,9 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(st4))]
@@ -69507,8 +69577,9 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(st4))]
@@ -69856,11 +69927,12 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
@@ -69884,11 +69956,12 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
@@ -69912,10 +69985,11 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
@@ -69941,10 +70015,11 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline]
+#[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
-#[target_feature(enable = "neon,fp16")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 48c12779a8..f3faf14838 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -1506,7 +1506,6 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
-      - *neon-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe
@@ -1524,7 +1523,6 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
-      - *neon-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe
@@ -8793,7 +8791,6 @@ intrinsics:
     arguments: ["a: {type[0]}"]
     return_type: "{type[1]}"
     attr:
-      - *neon-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [nop]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 9ebdc4334c..9727f0a4bb 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -71,6 +71,10 @@ neon-i8mm: &neon-i8mm
 neon-fp16: &neon-fp16
   FnCall: [target_feature, ['enable = "neon,fp16"']]
 
+# #[cfg_attr[target_arch = "arm", target_feature(enable = "neon,fp16")]
+arm-fp16: &arm-fp16
+  FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [target_feature, ['enable = "fp16"']]}]]
+
 enable-fcma: &enable-fcma
   FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, { FnCall: [target_feature, ['enable = "fcma"']] }]]
 
@@ -1502,7 +1506,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vdup.16"', 'N = 4']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [dup, 'N = 4']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const N: i32']
@@ -1522,7 +1526,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vdup.16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [dup]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe
@@ -1541,7 +1545,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vdup.16"', 'N = 2']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [dup, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const N: i32']
@@ -2754,7 +2758,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -2785,7 +2789,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1, 'LANE = 0']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -2806,7 +2810,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vld1"]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1r]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3399,7 +3403,7 @@ intrinsics:
       - *neon-v7
       - *target-is-arm
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld2]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3428,7 +3432,7 @@ intrinsics:
     attr:
       - *target-not-arm
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3455,7 +3459,7 @@ intrinsics:
     attr:
       - *neon-v7
       - *target-is-arm
-      - *neon-fp16
+      - *arm-fp16
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld2]]}]]
       - *neon-unstable-f16
       - *target-not-arm64ec
@@ -3486,7 +3490,7 @@ intrinsics:
     attr:
       - *target-not-arm
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2r]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3516,7 +3520,7 @@ intrinsics:
       - *target-is-arm
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['vld2', 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs:
@@ -3559,7 +3563,7 @@ intrinsics:
       - *target-not-arm
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs:
@@ -3600,7 +3604,7 @@ intrinsics:
       - *neon-v7
       - *target-is-arm
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld3]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3629,7 +3633,7 @@ intrinsics:
     attr:
       - *target-not-arm
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3657,7 +3661,7 @@ intrinsics:
       - *neon-v7
       - *target-is-arm
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld3]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3687,7 +3691,7 @@ intrinsics:
     attr:
       - *target-not-arm
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3r]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety:
@@ -3717,7 +3721,7 @@ intrinsics:
       - *target-is-arm
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['vld3', 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs:
@@ -3762,7 +3766,7 @@ intrinsics:
       - *target-not-arm
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs:
@@ -4744,7 +4748,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     types:
@@ -4982,7 +4986,7 @@ intrinsics:
     attr:
       - *target-is-arm
       - *neon-v7
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [vst1]
@@ -5126,7 +5130,7 @@ intrinsics:
     arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"]
     attr:
       - *target-not-arm
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [st2]
@@ -5217,7 +5221,7 @@ intrinsics:
       - *target-not-arm
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -5309,7 +5313,7 @@ intrinsics:
     attr:
       - *target-is-arm
       - *neon-v7
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [vst2]
@@ -5376,7 +5380,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst2, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -5587,7 +5591,7 @@ intrinsics:
     attr:
       - *target-is-arm
       - *neon-v7
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [vst3]
@@ -5656,7 +5660,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst3, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -5717,7 +5721,7 @@ intrinsics:
     arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"]
     attr:
       - *target-not-arm
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [st3]
@@ -5782,7 +5786,7 @@ intrinsics:
       - *target-not-arm
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -5996,7 +6000,7 @@ intrinsics:
     attr:
       - *target-is-arm
       - *neon-v7
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [vst4]
@@ -6066,7 +6070,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst4, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -6129,7 +6133,7 @@ intrinsics:
     arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"]
     attr:
       - *target-not-arm
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [st4]
@@ -6196,7 +6200,7 @@ intrinsics:
       - *target-not-arm
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -9139,7 +9143,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe
@@ -10730,7 +10734,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt.f16.f32]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtn]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe
@@ -10747,7 +10751,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtl]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe
@@ -14055,7 +14059,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - *neon-v7
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [nop]
@@ -14071,7 +14075,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-v7
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     assert_instr: [nop]
@@ -14088,10 +14092,10 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - *neon-v7
-      - *neon-fp16
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["1"]]
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
@@ -14111,7 +14115,7 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vdup.16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [dup]]}]]
-      - *neon-fp16
+      - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
     safety: safe

From 48260eb454b21b7d4d571ddfd3ffa6137d91d4dc Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Tue, 16 Dec 2025 11:24:11 +0000
Subject: [PATCH 078/326] Fix some Arm instruction assertion tests

---
 crates/core_arch/src/aarch64/neon/generated.rs       | 10 +++++-----
 crates/core_arch/src/arm_shared/neon/generated.rs    |  2 +-
 crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml    |  8 ++++----
 crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index f1291c8fbd..0c703916c1 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -9487,7 +9487,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(fdiv))]
 pub fn vdivh_f16(a: f16, b: f16) -> f16 {
     a / b
 }
@@ -14829,7 +14829,7 @@ pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(fmul))]
 pub fn vmulh_f16(a: f16, b: f16) -> f16 {
     a * b
 }
@@ -26719,7 +26719,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(sub))]
 pub fn vsubd_s64(a: i64, b: i64) -> i64 {
     a.wrapping_sub(b)
 }
@@ -26728,7 +26728,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(sub))]
 pub fn vsubd_u64(a: u64, b: u64) -> u64 {
     a.wrapping_sub(b)
 }
@@ -26738,7 +26738,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(fsub))]
 pub fn vsubh_f16(a: f16, b: f16) -> f16 {
     a - b
 }
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index cfd9c20186..314965cc20 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -8310,7 +8310,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-# [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(fcvtn)
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index f3faf14838..42f716874b 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5669,7 +5669,7 @@ intrinsics:
       - *neon-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
-    assert_instr: [nop]
+    assert_instr: [fdiv]
     safety: safe
     types:
       - [f16, 'h']
@@ -5694,7 +5694,7 @@ intrinsics:
     arguments: ["a: {type[1]}", "b: {type[1]}"]
     return_type: "{type[1]}"
     attr: [*neon-stable]
-    assert_instr: [nop]
+    assert_instr: [sub]
     safety: safe
     types:
       - ['d_s64', 'i64']
@@ -5710,7 +5710,7 @@ intrinsics:
       - *neon-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
-    assert_instr: [nop]
+    assert_instr: [fsub]
     safety: safe
     types:
       - ['h_f16', 'f16']
@@ -11271,7 +11271,7 @@ intrinsics:
       - *neon-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
-    assert_instr: [nop]
+    assert_instr: [fmul]
     safety: safe
     types:
       - [f16, 'h']
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 9727f0a4bb..e8b31d73f9 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -10732,7 +10732,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - *neon-v7
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt.f16.f32]]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtn]]}]]
       - *arm-fp16
       - *neon-unstable-f16

From d2d11ac33cab3c7baade17ba2a1fc5b872c7b89c Mon Sep 17 00:00:00 2001
From: Niko Kajula <niko.kajula@student.oulu.fi>
Date: Wed, 17 Dec 2025 22:41:21 +0200
Subject: [PATCH 079/326] Fix broken AMD Developer's Manual links

---
 crates/core_arch/src/x86/abm.rs    | 2 +-
 crates/core_arch/src/x86/avx.rs    | 2 +-
 crates/core_arch/src/x86/avx2.rs   | 2 +-
 crates/core_arch/src/x86/cpuid.rs  | 2 +-
 crates/core_arch/src/x86/fma.rs    | 2 +-
 crates/core_arch/src/x86/tbm.rs    | 2 +-
 crates/core_arch/src/x86_64/abm.rs | 2 +-
 crates/core_arch/src/x86_64/avx.rs | 2 +-
 crates/core_arch/src/x86_64/tbm.rs | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/crates/core_arch/src/x86/abm.rs b/crates/core_arch/src/x86/abm.rs
index 59f3877b4a..7f46e1a8d0 100644
--- a/crates/core_arch/src/x86/abm.rs
+++ b/crates/core_arch/src/x86/abm.rs
@@ -13,7 +13,7 @@
 //! available.
 //!
 //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 
diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index acba0a3db7..bda0b8ac50 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -10,7 +10,7 @@
 //! [Wikipedia][wiki] provides a quick overview of the instructions available.
 //!
 //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 
 use crate::{
diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index b3b2accd73..e7fd19fa2e 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -14,7 +14,7 @@
 //! overview of the instructions available.
 //!
 //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki_avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
 
diff --git a/crates/core_arch/src/x86/cpuid.rs b/crates/core_arch/src/x86/cpuid.rs
index b35699bd7a..3f13ea8369 100644
--- a/crates/core_arch/src/x86/cpuid.rs
+++ b/crates/core_arch/src/x86/cpuid.rs
@@ -54,7 +54,7 @@ pub struct CpuidResult {
 ///
 /// [wiki_cpuid]: https://en.wikipedia.org/wiki/CPUID
 /// [intel64_ref]: https://cdrdv2-public.intel.com/671110/325383-sdm-vol-2abcd.pdf
-/// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+/// [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 #[inline]
 #[cfg_attr(test, assert_instr(cpuid))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
diff --git a/crates/core_arch/src/x86/fma.rs b/crates/core_arch/src/x86/fma.rs
index abf79f4904..a843993566 100644
--- a/crates/core_arch/src/x86/fma.rs
+++ b/crates/core_arch/src/x86/fma.rs
@@ -15,7 +15,7 @@
 //! instructions available.
 //!
 //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
 
 use crate::core_arch::x86::*;
diff --git a/crates/core_arch/src/x86/tbm.rs b/crates/core_arch/src/x86/tbm.rs
index d7769b916d..1e863fe15c 100644
--- a/crates/core_arch/src/x86/tbm.rs
+++ b/crates/core_arch/src/x86/tbm.rs
@@ -6,7 +6,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the available
 //! instructions.
 //!
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 
diff --git a/crates/core_arch/src/x86_64/abm.rs b/crates/core_arch/src/x86_64/abm.rs
index 63e422864d..2b63cb5dc7 100644
--- a/crates/core_arch/src/x86_64/abm.rs
+++ b/crates/core_arch/src/x86_64/abm.rs
@@ -13,7 +13,7 @@
 //! available.
 //!
 //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 
diff --git a/crates/core_arch/src/x86_64/avx.rs b/crates/core_arch/src/x86_64/avx.rs
index bb8d256207..80ef7fbd60 100644
--- a/crates/core_arch/src/x86_64/avx.rs
+++ b/crates/core_arch/src/x86_64/avx.rs
@@ -10,7 +10,7 @@
 //! [Wikipedia][wiki] provides a quick overview of the instructions available.
 //!
 //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 
 use crate::{core_arch::x86::*, mem::transmute};
diff --git a/crates/core_arch/src/x86_64/tbm.rs b/crates/core_arch/src/x86_64/tbm.rs
index e7d4b8d3e4..031bd32071 100644
--- a/crates/core_arch/src/x86_64/tbm.rs
+++ b/crates/core_arch/src/x86_64/tbm.rs
@@ -6,7 +6,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the available
 //! instructions.
 //!
-//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+//! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 

From 8da7811834dfd33497bfb7c9213c98ec4f2837c8 Mon Sep 17 00:00:00 2001
From: Niko Kajula <niko.kajula@student.oulu.fi>
Date: Thu, 18 Dec 2025 01:00:29 +0200
Subject: [PATCH 080/326] Fix intel manual links

---
 crates/core_arch/src/x86/abm.rs             | 2 +-
 crates/core_arch/src/x86/aes.rs             | 2 +-
 crates/core_arch/src/x86/avx.rs             | 2 +-
 crates/core_arch/src/x86/avx2.rs            | 2 +-
 crates/core_arch/src/x86/avx512bitalg.rs    | 2 +-
 crates/core_arch/src/x86/avx512vpopcntdq.rs | 2 +-
 crates/core_arch/src/x86/bmi1.rs            | 2 +-
 crates/core_arch/src/x86/bmi2.rs            | 2 +-
 crates/core_arch/src/x86/fma.rs             | 2 +-
 crates/core_arch/src/x86/gfni.rs            | 2 +-
 crates/core_arch/src/x86/pclmulqdq.rs       | 2 +-
 crates/core_arch/src/x86/rtm.rs             | 2 +-
 crates/core_arch/src/x86/vaes.rs            | 2 +-
 crates/core_arch/src/x86_64/abm.rs          | 2 +-
 crates/core_arch/src/x86_64/avx.rs          | 2 +-
 crates/core_arch/src/x86_64/bmi.rs          | 2 +-
 crates/core_arch/src/x86_64/bmi2.rs         | 2 +-
 17 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/crates/core_arch/src/x86/abm.rs b/crates/core_arch/src/x86/abm.rs
index 7f46e1a8d0..b73076361d 100644
--- a/crates/core_arch/src/x86/abm.rs
+++ b/crates/core_arch/src/x86/abm.rs
@@ -12,7 +12,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
 //! available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
diff --git a/crates/core_arch/src/x86/aes.rs b/crates/core_arch/src/x86/aes.rs
index 7db743b2cc..be01d6ddd8 100644
--- a/crates/core_arch/src/x86/aes.rs
+++ b/crates/core_arch/src/x86/aes.rs
@@ -5,7 +5,7 @@
 //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
 //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 
 use crate::core_arch::x86::__m128i;
 
diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index bda0b8ac50..6d4f79fc7c 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -9,7 +9,7 @@
 //!
 //! [Wikipedia][wiki] provides a quick overview of the instructions available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 
diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index e7fd19fa2e..a297544e9e 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -13,7 +13,7 @@
 //! Wikipedia's [AVX][wiki_avx] and [FMA][wiki_fma] pages provide a quick
 //! overview of the instructions available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki_avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
diff --git a/crates/core_arch/src/x86/avx512bitalg.rs b/crates/core_arch/src/x86/avx512bitalg.rs
index 832a584322..497fa21c4f 100644
--- a/crates/core_arch/src/x86/avx512bitalg.rs
+++ b/crates/core_arch/src/x86/avx512bitalg.rs
@@ -5,7 +5,7 @@
 //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
 //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 
 use crate::core_arch::simd::i8x16;
 use crate::core_arch::simd::i8x32;
diff --git a/crates/core_arch/src/x86/avx512vpopcntdq.rs b/crates/core_arch/src/x86/avx512vpopcntdq.rs
index 42bff33a28..38ef54b550 100644
--- a/crates/core_arch/src/x86/avx512vpopcntdq.rs
+++ b/crates/core_arch/src/x86/avx512vpopcntdq.rs
@@ -5,7 +5,7 @@
 //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
 //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 
 use crate::core_arch::simd::*;
 use crate::core_arch::x86::__m128i;
diff --git a/crates/core_arch/src/x86/bmi1.rs b/crates/core_arch/src/x86/bmi1.rs
index 08444aaaed..11d66f699a 100644
--- a/crates/core_arch/src/x86/bmi1.rs
+++ b/crates/core_arch/src/x86/bmi1.rs
@@ -6,7 +6,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
 //! available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [wikipedia_bmi]: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 
 #[cfg(test)]
diff --git a/crates/core_arch/src/x86/bmi2.rs b/crates/core_arch/src/x86/bmi2.rs
index b5b7d0f340..54d3b5387e 100644
--- a/crates/core_arch/src/x86/bmi2.rs
+++ b/crates/core_arch/src/x86/bmi2.rs
@@ -6,7 +6,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
 //! available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 
diff --git a/crates/core_arch/src/x86/fma.rs b/crates/core_arch/src/x86/fma.rs
index a843993566..c0900e61d9 100644
--- a/crates/core_arch/src/x86/fma.rs
+++ b/crates/core_arch/src/x86/fma.rs
@@ -14,7 +14,7 @@
 //! Wikipedia's [FMA][wiki_fma] page provides a quick overview of the
 //! instructions available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
 
diff --git a/crates/core_arch/src/x86/gfni.rs b/crates/core_arch/src/x86/gfni.rs
index 8c4d097fee..681b8ae330 100644
--- a/crates/core_arch/src/x86/gfni.rs
+++ b/crates/core_arch/src/x86/gfni.rs
@@ -5,7 +5,7 @@
 //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
 //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 
 use crate::core_arch::simd::i8x16;
 use crate::core_arch::simd::i8x32;
diff --git a/crates/core_arch/src/x86/pclmulqdq.rs b/crates/core_arch/src/x86/pclmulqdq.rs
index cce6a51e2c..efc0119030 100644
--- a/crates/core_arch/src/x86/pclmulqdq.rs
+++ b/crates/core_arch/src/x86/pclmulqdq.rs
@@ -3,7 +3,7 @@
 //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
 //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref] (p. 4-241).
 //!
-//! [intel64_ref]: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 
 use crate::core_arch::x86::__m128i;
 
diff --git a/crates/core_arch/src/x86/rtm.rs b/crates/core_arch/src/x86/rtm.rs
index b807305d6a..b37e7571eb 100644
--- a/crates/core_arch/src/x86/rtm.rs
+++ b/crates/core_arch/src/x86/rtm.rs
@@ -9,7 +9,7 @@
 //! Intel's [programming considerations][intel_consid] details what sorts of instructions within a
 //! transaction are likely to cause an abort.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [wikipedia_rtm]: https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions#Restricted_Transactional_Memory
 //! [intel_consid]: https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-intel-transactional-synchronization-extensions-intel-tsx-programming-considerations
 
diff --git a/crates/core_arch/src/x86/vaes.rs b/crates/core_arch/src/x86/vaes.rs
index b1fe193e3f..561b8b4b30 100644
--- a/crates/core_arch/src/x86/vaes.rs
+++ b/crates/core_arch/src/x86/vaes.rs
@@ -5,7 +5,7 @@
 //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
 //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 
 use crate::core_arch::x86::__m256i;
 use crate::core_arch::x86::__m512i;
diff --git a/crates/core_arch/src/x86_64/abm.rs b/crates/core_arch/src/x86_64/abm.rs
index 2b63cb5dc7..9fb76be4ba 100644
--- a/crates/core_arch/src/x86_64/abm.rs
+++ b/crates/core_arch/src/x86_64/abm.rs
@@ -12,7 +12,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
 //! available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
diff --git a/crates/core_arch/src/x86_64/avx.rs b/crates/core_arch/src/x86_64/avx.rs
index 80ef7fbd60..aae3c981d6 100644
--- a/crates/core_arch/src/x86_64/avx.rs
+++ b/crates/core_arch/src/x86_64/avx.rs
@@ -9,7 +9,7 @@
 //!
 //! [Wikipedia][wiki] provides a quick overview of the instructions available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [amd64_ref]: https://docs.amd.com/v/u/en-US/24594_3.37
 //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 
diff --git a/crates/core_arch/src/x86_64/bmi.rs b/crates/core_arch/src/x86_64/bmi.rs
index ee41d41375..d5fd97583f 100644
--- a/crates/core_arch/src/x86_64/bmi.rs
+++ b/crates/core_arch/src/x86_64/bmi.rs
@@ -6,7 +6,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
 //! available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [wikipedia_bmi]: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 
 #[cfg(test)]
diff --git a/crates/core_arch/src/x86_64/bmi2.rs b/crates/core_arch/src/x86_64/bmi2.rs
index 4eb53ed5ea..be12465c81 100644
--- a/crates/core_arch/src/x86_64/bmi2.rs
+++ b/crates/core_arch/src/x86_64/bmi2.rs
@@ -6,7 +6,7 @@
 //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
 //! available.
 //!
-//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+//! [intel64_ref]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 //! [wikipedia_bmi]:
 //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
 

From 5b7bdb5c9050add28ea029bdb825b322809064e5 Mon Sep 17 00:00:00 2001
From: Tsukasa OI <floss_rust@irq.a4lg.com>
Date: Fri, 19 Sep 2025 21:36:50 +0000
Subject: [PATCH 081/326] RISC-V: Use inline assembly and `zkne_or_zknd` on
 (Zkne or Zknd) intrinsics

Using the inline assembly and `zkne_or_zknd` target feature could avoid
current issues regarding intrinsics available when either Zkne or Zknd
is available.

Before this commit, intrinsics `aes64ks1i` and `aes64ks2` required
both Zkne and Zknd extensions, not either Zkne or Zknd.

Closes: https://github.com/rust-lang/stdarch/issues/1765
---
 crates/core_arch/src/riscv64/zk.rs | 45 +++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/crates/core_arch/src/riscv64/zk.rs b/crates/core_arch/src/riscv64/zk.rs
index a30653cbe0..3aa1ca39b3 100644
--- a/crates/core_arch/src/riscv64/zk.rs
+++ b/crates/core_arch/src/riscv64/zk.rs
@@ -1,6 +1,8 @@
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
+use crate::arch::asm;
+
 unsafe extern "unadjusted" {
     #[link_name = "llvm.riscv.aes64es"]
     fn _aes64es(rs1: i64, rs2: i64) -> i64;
@@ -14,12 +16,6 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.riscv.aes64dsm"]
     fn _aes64dsm(rs1: i64, rs2: i64) -> i64;
 
-    #[link_name = "llvm.riscv.aes64ks1i"]
-    fn _aes64ks1i(rs1: i64, rnum: i32) -> i64;
-
-    #[link_name = "llvm.riscv.aes64ks2"]
-    fn _aes64ks2(rs1: i64, rs2: i64) -> i64;
-
     #[link_name = "llvm.riscv.aes64im"]
     fn _aes64im(rs1: i64) -> i64;
 
@@ -133,15 +129,26 @@ pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
 /// # Note
 ///
 /// The `RNUM` parameter is expected to be a constant value inside the range of `0..=10`.
-#[target_feature(enable = "zkne", enable = "zknd")]
+#[target_feature(enable = "zkne_or_zknd")]
 #[rustc_legacy_const_generics(1)]
-#[cfg_attr(test, assert_instr(aes64ks1i, RNUM = 0))]
 #[inline]
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
     static_assert!(RNUM <= 10);
-
-    unsafe { _aes64ks1i(rs1 as i64, RNUM as i32) as u64 }
+    unsafe {
+        let rd: u64;
+        asm!(
+            ".option push",
+            ".option arch, +zkne",
+            "aes64ks1i {}, {}, {}",
+            ".option pop",
+            lateout(reg) rd,
+            in(reg) rs1,
+            const RNUM,
+            options(pure, nomem, nostack, preserves_flags)
+        );
+        rd
+    }
 }
 
 /// This instruction implements part of the KeySchedule operation for the AES Block cipher.
@@ -155,12 +162,24 @@ pub fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
 /// Version: v1.0.1
 ///
 /// Section: 3.11
-#[target_feature(enable = "zkne", enable = "zknd")]
-#[cfg_attr(test, assert_instr(aes64ks2))]
+#[target_feature(enable = "zkne_or_zknd")]
 #[inline]
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
-    unsafe { _aes64ks2(rs1 as i64, rs2 as i64) as u64 }
+    unsafe {
+        let rd: u64;
+        asm!(
+            ".option push",
+            ".option arch, +zkne",
+            "aes64ks2 {}, {}, {}",
+            ".option pop",
+            lateout(reg) rd,
+            in(reg) rs1,
+            in(reg) rs2,
+            options(pure, nomem, nostack, preserves_flags)
+        );
+        rd
+    }
 }
 
 /// This instruction accelerates the inverse MixColumns step of the AES Block Cipher, and is used to aid creation of

From c65620dc41bed7360695f2928dcae926d0db021d Mon Sep 17 00:00:00 2001
From: Flakebi <flakebi@t-online.de>
Date: Fri, 19 Dec 2025 17:58:08 +0100
Subject: [PATCH 082/326] Add amdgpu intrinsics

Add intrinsics for the amdgpu architecture.
---
 .github/workflows/main.yml             |   15 +-
 ci/docker/amdgcn-amd-amdhsa/Dockerfile |    5 +
 ci/dox.sh                              |   10 +
 ci/run.sh                              |    3 +
 crates/core_arch/src/amdgpu/mod.rs     | 1053 ++++++++++++++++++++++++
 crates/core_arch/src/core_arch_docs.md |    2 +
 crates/core_arch/src/mod.rs            |   14 +
 7 files changed, 1100 insertions(+), 2 deletions(-)
 create mode 100644 ci/docker/amdgcn-amd-amdhsa/Dockerfile
 create mode 100644 crates/core_arch/src/amdgpu/mod.rs

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 28c15cf473..6c8a5694f3 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -84,6 +84,8 @@ jobs:
           os: ubuntu-latest
         - tuple: nvptx64-nvidia-cuda
           os: ubuntu-latest
+        - tuple: amdgcn-amd-amdhsa
+          os: ubuntu-latest
         - tuple: thumbv6m-none-eabi
           os: ubuntu-latest
         - tuple: thumbv7m-none-eabi
@@ -201,6 +203,10 @@ jobs:
             tuple: aarch64-apple-ios-macabi
             os: macos-15
           norun: true # https://github.com/rust-lang/stdarch/issues/1206
+        - target:
+            tuple: amdgcn-amd-amdhsa
+            os: ubuntu-latest
+          norun: true
 
     steps:
     - uses: actions/checkout@v4
@@ -212,12 +218,17 @@ jobs:
 
     - run: rustup target add ${{ matrix.target.tuple }}
       shell: bash
-      if: matrix.build_std == ''
+      if: matrix.build_std == '' && matrix.target.tuple != 'amdgcn-amd-amdhsa'
     - run: |
         rustup component add rust-src
         echo "CARGO_UNSTABLE_BUILD_STD=std" >> $GITHUB_ENV
       shell: bash
       if: matrix.build_std != ''
+    - run: |
+        rustup component add rust-src
+        echo "CARGO_UNSTABLE_BUILD_STD=core,alloc" >> $GITHUB_ENV
+      shell: bash
+      if: matrix.target.tuple == 'amdgcn-amd-amdhsa'
 
     # Configure some env vars based on matrix configuration
     - run: echo "PROFILE=--profile=${{matrix.profile}}" >> $GITHUB_ENV
@@ -233,7 +244,7 @@ jobs:
       if: matrix.disable_assert_instr != ''
     - run: echo "NOSTD=1" >> $GITHUB_ENV
       shell: bash
-      if: startsWith(matrix.target.tuple, 'thumb') || matrix.target.tuple == 'nvptx64-nvidia-cuda'
+      if: startsWith(matrix.target.tuple, 'thumb') || matrix.target.tuple == 'nvptx64-nvidia-cuda' || matrix.target.tuple == 'amdgcn-amd-amdhsa'
 
     # Windows & OSX go straight to `run.sh` ...
     - run: ./ci/run.sh
diff --git a/ci/docker/amdgcn-amd-amdhsa/Dockerfile b/ci/docker/amdgcn-amd-amdhsa/Dockerfile
new file mode 100644
index 0000000000..65cf281b14
--- /dev/null
+++ b/ci/docker/amdgcn-amd-amdhsa/Dockerfile
@@ -0,0 +1,5 @@
+FROM ubuntu:25.10
+RUN apt-get update && apt-get install -y --no-install-recommends \
+  gcc \
+  libc6-dev \
+  ca-certificates
diff --git a/ci/dox.sh b/ci/dox.sh
index 94d76d4304..9803f7e371 100755
--- a/ci/dox.sh
+++ b/ci/dox.sh
@@ -15,6 +15,15 @@ dox() {
 
   cargo clean --target "${1}"
 
+  if [ "${1}" == "amdgcn-amd-amdhsa" ]; then
+    if [ "$CI" != "" ]; then
+      rustup component add rust-src
+    fi
+    export CARGO_UNSTABLE_BUILD_STD=core
+    # amdgpu needs a target-cpu, any is fine
+    export RUSTFLAGS="${RUSTFLAGS} -Ctarget-cpu=gfx900"
+  fi
+
   cargo build --verbose --target "${1}" --manifest-path crates/core_arch/Cargo.toml
   cargo doc --verbose --target "${1}" --manifest-path crates/core_arch/Cargo.toml
 }
@@ -33,6 +42,7 @@ if [ -z "$1" ]; then
   #dox mips64-unknown-linux-gnuabi64
   dox wasm32-unknown-unknown
   dox nvptx64-nvidia-cuda
+  dox amdgcn-amd-amdhsa
 else
   dox "${1}"
 fi
diff --git a/ci/run.sh b/ci/run.sh
index 2bb77bae25..22c6593132 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -42,6 +42,9 @@ case ${TARGET} in
     armv7-*eabihf | thumbv7-*eabihf)
         export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon"
         ;;
+    amdgcn-*)
+        export RUSTFLAGS="${RUSTFLAGS} -Ctarget-cpu=gfx1200"
+        ;;
     # Some of our test dependencies use the deprecated `gcc` crates which
     # doesn't detect RISC-V compilers automatically, so do it manually here.
     riscv*)
diff --git a/crates/core_arch/src/amdgpu/mod.rs b/crates/core_arch/src/amdgpu/mod.rs
new file mode 100644
index 0000000000..40274e4d79
--- /dev/null
+++ b/crates/core_arch/src/amdgpu/mod.rs
@@ -0,0 +1,1053 @@
+//! amdgpu intrinsics
+//!
+//! The reference is the [LLVM amdgpu guide] and the [LLVM implementation].
+//! The order of intrinsics here follows the order in the [LLVM implementation].
+//!
+//! [LLVM amdgpu guide]: https://llvm.org/docs/AMDGPUUsage.html#llvm-ir-intrinsics
+//! [LLVM implementation]: https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+
+#[allow(improper_ctypes)]
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.amdgcn.workitem.id.x"]
+    safe fn llvm_workitem_id_x() -> u32;
+    #[link_name = "llvm.amdgcn.workitem.id.y"]
+    safe fn llvm_workitem_id_y() -> u32;
+    #[link_name = "llvm.amdgcn.workitem.id.z"]
+    safe fn llvm_workitem_id_z() -> u32;
+
+    #[link_name = "llvm.amdgcn.workgroup.id.x"]
+    safe fn llvm_workgroup_id_x() -> u32;
+    #[link_name = "llvm.amdgcn.workgroup.id.y"]
+    safe fn llvm_workgroup_id_y() -> u32;
+    #[link_name = "llvm.amdgcn.workgroup.id.z"]
+    safe fn llvm_workgroup_id_z() -> u32;
+
+    #[link_name = "llvm.amdgcn.groupstaticsize"]
+    safe fn llvm_groupstaticsize() -> u32;
+    #[link_name = "llvm.amdgcn.dispatch.id"]
+    safe fn llvm_dispatch_id() -> u64;
+
+    #[link_name = "llvm.amdgcn.wavefrontsize"]
+    safe fn llvm_wavefrontsize() -> u32;
+
+    #[link_name = "llvm.amdgcn.s.barrier"]
+    safe fn llvm_s_barrier();
+    #[link_name = "llvm.amdgcn.s.barrier.signal"]
+    fn llvm_s_barrier_signal(barrier_type: i32);
+    #[link_name = "llvm.amdgcn.s.barrier.signal.isfirst"]
+    fn llvm_s_barrier_signal_isfirst(barrier_type: i32) -> bool;
+    #[link_name = "llvm.amdgcn.s.barrier.wait"]
+    fn llvm_s_barrier_wait(barrier_type: i16);
+    #[link_name = "llvm.amdgcn.s.get.barrier.state"]
+    fn llvm_s_get_barrier_state(barrier_type: i32) -> u32;
+    #[link_name = "llvm.amdgcn.wave.barrier"]
+    safe fn llvm_wave_barrier();
+    #[link_name = "llvm.amdgcn.sched.barrier"]
+    fn llvm_sched_barrier(mask: u32);
+    #[link_name = "llvm.amdgcn.sched.group.barrier"]
+    fn llvm_sched_group_barrier(mask: u32, size: u32, sync_id: u32);
+
+    #[link_name = "llvm.amdgcn.s.sleep"]
+    safe fn llvm_s_sleep(count: u32);
+
+    #[link_name = "llvm.amdgcn.s.sethalt"]
+    safe fn llvm_s_sethalt(value: u32) -> !;
+
+    #[link_name = "llvm.amdgcn.s.getpc"]
+    safe fn llvm_s_getpc() -> i64;
+
+    #[link_name = "llvm.amdgcn.mbcnt.lo"]
+    safe fn llvm_mbcnt_lo(value: u32, init: u32) -> u32;
+    #[link_name = "llvm.amdgcn.mbcnt.hi"]
+    safe fn llvm_mbcnt_hi(value: u32, init: u32) -> u32;
+
+    #[link_name = "llvm.amdgcn.ballot"]
+    safe fn llvm_ballot(b: bool) -> u64;
+
+    #[link_name = "llvm.amdgcn.inverse.ballot"]
+    safe fn llvm_inverse_ballot(value: u64) -> bool;
+
+    #[link_name = "llvm.amdgcn.wave.reduce.umin"]
+    safe fn llvm_wave_reduce_umin(value: u32, strategy: u32) -> u32;
+    #[link_name = "llvm.amdgcn.wave.reduce.min"]
+    safe fn llvm_wave_reduce_min(value: i32, strategy: u32) -> i32;
+    #[link_name = "llvm.amdgcn.wave.reduce.umax"]
+    safe fn llvm_wave_reduce_umax(value: u32, strategy: u32) -> u32;
+    #[link_name = "llvm.amdgcn.wave.reduce.max"]
+    safe fn llvm_wave_reduce_max(value: i32, strategy: u32) -> i32;
+    #[link_name = "llvm.amdgcn.wave.reduce.add"]
+    safe fn llvm_wave_reduce_add(value: u32, strategy: u32) -> u32;
+    #[link_name = "llvm.amdgcn.wave.reduce.and"]
+    safe fn llvm_wave_reduce_and(value: u32, strategy: u32) -> u32;
+    #[link_name = "llvm.amdgcn.wave.reduce.or"]
+    safe fn llvm_wave_reduce_or(value: u32, strategy: u32) -> u32;
+    #[link_name = "llvm.amdgcn.wave.reduce.xor"]
+    safe fn llvm_wave_reduce_xor(value: u32, strategy: u32) -> u32;
+
+    // The following intrinsics can have multiple sizes
+
+    #[link_name = "llvm.amdgcn.readfirstlane.i32"]
+    safe fn llvm_readfirstlane_u32(value: u32) -> u32;
+    #[link_name = "llvm.amdgcn.readfirstlane.i64"]
+    safe fn llvm_readfirstlane_u64(value: u64) -> u64;
+    #[link_name = "llvm.amdgcn.readlane.i32"]
+    fn llvm_readlane_u32(value: u32, lane: u32) -> u32;
+    #[link_name = "llvm.amdgcn.readlane.i64"]
+    fn llvm_readlane_u64(value: u64, lane: u32) -> u64;
+    #[link_name = "llvm.amdgcn.writelane.i32"]
+    fn llvm_writelane_u32(value: u32, lane: u32, default: u32) -> u32;
+    #[link_name = "llvm.amdgcn.writelane.i64"]
+    fn llvm_writelane_u64(value: u64, lane: u32, default: u64) -> u64;
+
+    #[link_name = "llvm.amdgcn.endpgm"]
+    safe fn llvm_endpgm() -> !;
+
+    #[link_name = "llvm.amdgcn.update.dpp.i32"]
+    fn llvm_update_dpp(
+        old: u32,
+        src: u32,
+        dpp_ctrl: u32,
+        row_mask: u32,
+        bank_mask: u32,
+        bound_control: bool,
+    ) -> u32;
+
+    #[link_name = "llvm.amdgcn.s.memrealtime"]
+    safe fn llvm_s_memrealtime() -> u64;
+
+    #[link_name = "llvm.amdgcn.ds.permute"]
+    fn llvm_ds_permute(lane: u32, value: u32) -> u32;
+    #[link_name = "llvm.amdgcn.ds.bpermute"]
+    fn llvm_ds_bpermute(lane: u32, value: u32) -> u32;
+    #[link_name = "llvm.amdgcn.perm"]
+    fn llvm_perm(src0: u32, src1: u32, selector: u32) -> u32;
+
+    // gfx10
+    #[link_name = "llvm.amdgcn.permlane16.i32"]
+    fn llvm_permlane16_u32(
+        old: u32,
+        src0: u32,
+        src1: u32,
+        src2: u32,
+        fi: bool,
+        bound_control: bool,
+    ) -> u32;
+
+    // gfx10
+    #[link_name = "llvm.amdgcn.permlanex16.i32"]
+    fn llvm_permlanex16_u32(
+        old: u32,
+        src0: u32,
+        src1: u32,
+        src2: u32,
+        fi: bool,
+        bound_control: bool,
+    ) -> u32;
+
+    #[link_name = "llvm.amdgcn.s.get.waveid.in.workgroup"]
+    safe fn llvm_s_get_waveid_in_workgroup() -> u32;
+
+    // gfx11
+    #[link_name = "llvm.amdgcn.permlane64.i32"]
+    fn llvm_permlane64_u32(value: u32) -> u32;
+
+    // gfx12
+    #[link_name = "llvm.amdgcn.permlane16.var"]
+    fn llvm_permlane16_var(old: u32, src0: u32, src1: u32, fi: bool, bound_control: bool) -> u32;
+
+    // gfx12
+    #[link_name = "llvm.amdgcn.permlanex16.var"]
+    fn llvm_permlanex16_var(old: u32, src0: u32, src1: u32, fi: bool, bound_control: bool) -> u32;
+
+    #[link_name = "llvm.amdgcn.wave.id"]
+    safe fn llvm_wave_id() -> u32;
+
+    // gfx950
+    #[link_name = "llvm.amdgcn.permlane16.swap"]
+    fn llvm_permlane16_swap(
+        vdst_old: u32,
+        vsrc_src0: u32,
+        fi: bool,
+        bound_control: bool,
+    ) -> (u32, u32);
+
+    // gfx950
+    #[link_name = "llvm.amdgcn.permlane32.swap"]
+    fn llvm_permlane32_swap(
+        vdst_old: u32,
+        vsrc_src0: u32,
+        fi: bool,
+        bound_control: bool,
+    ) -> (u32, u32);
+}
+
+/// Returns the x coordinate of the workitem index within the workgroup.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn workitem_id_x() -> u32 {
+    llvm_workitem_id_x()
+}
+/// Returns the y coordinate of the workitem index within the workgroup.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn workitem_id_y() -> u32 {
+    llvm_workitem_id_y()
+}
+/// Returns the z coordinate of the workitem index within the workgroup.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn workitem_id_z() -> u32 {
+    llvm_workitem_id_z()
+}
+
+/// Returns the x coordinate of the workgroup index within the dispatch.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn workgroup_id_x() -> u32 {
+    llvm_workgroup_id_x()
+}
+/// Returns the y coordinate of the workgroup index within the dispatch.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn workgroup_id_y() -> u32 {
+    llvm_workgroup_id_y()
+}
+/// Returns the z coordinate of the workgroup index within the dispatch.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn workgroup_id_z() -> u32 {
+    llvm_workgroup_id_z()
+}
+
+/// Returns the size of statically allocated shared memory for this program in bytes.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn groupstaticsize() -> u32 {
+    llvm_groupstaticsize()
+}
+/// Returns the id of the dispatch that is currently executed.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn dispatch_id() -> u64 {
+    llvm_dispatch_id()
+}
+
+/// Returns the number of threads in a wavefront.
+///
+/// Is always a power of 2.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wavefrontsize() -> u32 {
+    llvm_wavefrontsize()
+}
+
+/// Synchronize all wavefronts in a workgroup.
+///
+/// Each wavefronts in a workgroup waits at the barrier until all wavefronts in the workgroup arrive at a barrier.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn s_barrier() {
+    llvm_s_barrier()
+}
+
+/// Signal a specific barrier type.
+///
+/// Only for non-named barriers.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn s_barrier_signal<const BARRIER_TYPE: i32>() {
+    unsafe { llvm_s_barrier_signal(BARRIER_TYPE) }
+}
+
+/// Signal a specific barrier type.
+///
+/// Only for non-named barriers.
+/// Provides access to the s_barrier_signal_first instruction;
+/// additionally ensures that the result value is valid even when
+/// the intrinsic is used from a wavefront that is not running in a workgroup.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn s_barrier_signal_isfirst<const BARRIER_TYPE: i32>() -> bool {
+    unsafe { llvm_s_barrier_signal_isfirst(BARRIER_TYPE) }
+}
+
+/// Wait for a specific barrier type.
+///
+/// Only for non-named barriers.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn s_barrier_wait<const BARRIER_TYPE: i16>() {
+    unsafe { llvm_s_barrier_wait(BARRIER_TYPE) }
+}
+
+/// Get the state of a specific barrier type.
+///
+/// The `barrier_type` argument must be uniform, otherwise behavior is undefined.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn s_get_barrier_state<const BARRIER_TYPE: i32>() -> u32 {
+    unsafe { llvm_s_get_barrier_state(BARRIER_TYPE) }
+}
+
+/// A barrier for only the threads within the current wavefront.
+///
+/// Does not result in an instruction but restricts the compiler.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_barrier() {
+    llvm_wave_barrier()
+}
+
+/// Prevent movement of some instruction types.
+///
+/// Controls the types of instructions that may be allowed to cross the intrinsic during instruction scheduling.
+/// The parameter is a mask for the instruction types that can cross the intrinsic.
+///
+/// - 0x0000: No instructions may be scheduled across `sched_barrier`.
+/// - 0x0001: All, non-memory, non-side-effect producing instructions may be scheduled across `sched_barrier`, i.e. allow ALU instructions to pass.
+/// - 0x0002: VALU instructions may be scheduled across `sched_barrier`.
+/// - 0x0004: SALU instructions may be scheduled across `sched_barrier`.
+/// - 0x0008: MFMA/WMMA instructions may be scheduled across `sched_barrier`.
+/// - 0x0010: All VMEM instructions may be scheduled across `sched_barrier`.
+/// - 0x0020: VMEM read instructions may be scheduled across `sched_barrier`.
+/// - 0x0040: VMEM write instructions may be scheduled across `sched_barrier`.
+/// - 0x0080: All DS instructions may be scheduled across `sched_barrier`.
+/// - 0x0100: All DS read instructions may be scheduled across `sched_barrier`.
+/// - 0x0200: All DS write instructions may be scheduled across `sched_barrier`.
+/// - 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across `sched_barrier`.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn sched_barrier<const MASK: u32>() {
+    static_assert_uimm_bits!(MASK, 11);
+    unsafe { llvm_sched_barrier(MASK) }
+}
+
+/// Creates schedule groups with specific properties to create custom scheduling pipelines.
+///
+/// The ordering between groups is enforced by the instruction scheduler.
+/// The intrinsic applies to the code that precedes the intrinsic.
+/// The intrinsic takes three values that control the behavior of the schedule groups.
+///
+/// - `mask`: Classify instruction groups using the [`sched_barrier`] mask values.
+/// - `size`: The number of instructions that are in the group.
+/// - `sync_id`: Order is enforced between groups with matching values.
+///
+/// The mask can include multiple instruction types. It is undefined behavior to set values beyond the range of valid masks.
+///
+/// Combining multiple `sched_group_barrier` intrinsics enables an ordering of specific instruction types during instruction scheduling.
+/// For example, the following enforces a sequence of 1 VMEM read, followed by 1 VALU instruction, followed by 5 MFMA instructions.
+///
+/// ```rust
+/// // 1 VMEM read
+/// sched_group_barrier::<32, 1, 0>()
+/// // 1 VALU
+/// sched_group_barrier::<2, 1, 0>()
+/// // 5 MFMA
+/// sched_group_barrier::<8, 5, 0>()
+/// ```
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn sched_group_barrier<const MASK: u32, const SIZE: u32, const SYNC_ID: u32>() {
+    static_assert_uimm_bits!(MASK, 11);
+    unsafe { llvm_sched_group_barrier(MASK, SIZE, SYNC_ID) }
+}
+
+/// Sleeps for approximately `COUNT * 64` cycles.
+///
+/// `COUNT` must be a constant.
+/// Only the lower 7 bits of `COUNT` are used.
+/// If `COUNT == 0x8000`, sleep forever until woken up, or killed.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn s_sleep<const COUNT: u32>() {
+    llvm_s_sleep(COUNT)
+}
+
+/// Stop execution of the kernel.
+///
+/// This usually signals an error state.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn s_sethalt<const VALUE: u32>() -> ! {
+    static_assert_uimm_bits!(VALUE, 3);
+    llvm_s_sethalt(VALUE)
+}
+
+/// Returns the current process counter.
+///
+/// Provides access to the s_getpc_b64 instruction, but with the return value sign-extended
+/// from the width of the underlying PC hardware register even on processors where the
+/// s_getpc_b64 instruction returns a zero-extended value.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn s_getpc() -> i64 {
+    llvm_s_getpc()
+}
+
+/// Masked bit count, low 32 lanes.
+///
+/// Computes the number of bits set in `value`, masked with a thread mask
+/// which contains 1 for all active threads less than the current thread within a wavefront.
+/// `init` is added to the result.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn mbcnt_lo(value: u32, init: u32) -> u32 {
+    llvm_mbcnt_lo(value, init)
+}
+/// Masked bit count, high 32 lanes.
+///
+/// Computes the number of bits set in `value`, masked with a thread mask
+/// which contains 1 for all active threads less than the current thread within a wavefront.
+/// `init` is added to the result.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn mbcnt_hi(value: u32, init: u32) -> u32 {
+    llvm_mbcnt_hi(value, init)
+}
+
+/// Returns a bitfield (`u32` or `u64`) containing the result of its i1 argument
+/// in all active lanes, and zero in all inactive lanes.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn ballot(b: bool) -> u64 {
+    llvm_ballot(b)
+}
+
+/// Indexes into the `value` with the current lane id and returns for each lane
+/// if the corresponding bit is set.
+///
+/// While [`ballot`] converts a `bool` to a mask, `inverse_ballot` converts a mask back to a `bool`.
+/// This means `inverse_ballot(ballot(b)) == b`.
+/// The inverse of `ballot(inverse_ballot(value)) ~= value` is not always true as inactive lanes are set to zero by `ballot`.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn inverse_ballot(value: u64) -> bool {
+    llvm_inverse_ballot(value)
+}
+
+/// Performs an arithmetic min reduction on the unsigned values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_umin<const STRATEGY: u32>(value: u32) -> u32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_umin(value, STRATEGY)
+}
+/// Performs an arithmetic min reduction on the signed values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_min<const STRATEGY: u32>(value: i32) -> i32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_min(value, STRATEGY)
+}
+
+/// Performs an arithmetic max reduction on the unsigned values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_umax<const STRATEGY: u32>(value: u32) -> u32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_umax(value, STRATEGY)
+}
+/// Performs an arithmetic max reduction on the signed values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_max<const STRATEGY: u32>(value: i32) -> i32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_max(value, STRATEGY)
+}
+
+/// Performs an arithmetic add reduction on the values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_add<const STRATEGY: u32>(value: u32) -> u32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_add(value, STRATEGY)
+}
+
+/// Performs a logical and reduction on the unsigned values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_and<const STRATEGY: u32>(value: u32) -> u32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_and(value, STRATEGY)
+}
+/// Performs a logical or reduction on the unsigned values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_or<const STRATEGY: u32>(value: u32) -> u32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_or(value, STRATEGY)
+}
+/// Performs a logical xor reduction on the unsigned values provided by each lane in the wavefront.
+///
+/// The `STRATEGY` argument is a hint for the reduction strategy.
+/// - 0: Target default preference
+/// - 1: Iterative strategy
+/// - 2: DPP
+///
+/// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_reduce_xor<const STRATEGY: u32>(value: u32) -> u32 {
+    static_assert!(STRATEGY <= 2);
+    llvm_wave_reduce_xor(value, STRATEGY)
+}
+
+// The following intrinsics can have multiple sizes
+
+/// Get `value` from the first active lane in the wavefront.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn readfirstlane_u32(value: u32) -> u32 {
+    llvm_readfirstlane_u32(value)
+}
+/// Get `value` from the first active lane in the wavefront.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn readfirstlane_u64(value: u64) -> u64 {
+    llvm_readfirstlane_u64(value)
+}
+/// Get `value` from the lane at index `lane` in the wavefront.
+///
+/// The lane argument must be uniform across the currently active threads
+/// of the current wavefront. Otherwise, the result is undefined.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 {
+    unsafe { llvm_readlane_u32(value, lane) }
+}
+/// Get `value` from the lane at index `lane` in the wavefront.
+///
+/// The lane argument must be uniform across the currently active threads
+/// of the current wavefront. Otherwise, the result is undefined.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 {
+    unsafe { llvm_readlane_u64(value, lane) }
+}
+/// Return `value` for the lane at index `lane` in the wavefront.
+/// Return `default` for all other lanes.
+///
+/// The value to write and lane select arguments must be uniform across the
+/// currently active threads of the current wavefront. Otherwise, the result is
+/// undefined.
+///
+/// `value` is the value returned by `lane`.
+/// `default` is the value returned by all lanes other than `lane`.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 {
+    unsafe { llvm_writelane_u32(value, lane, default) }
+}
+/// Return `value` for the lane at index `lane` in the wavefront.
+/// Return `default` for all other lanes.
+///
+/// The value to write and lane select arguments must be uniform across the
+/// currently active threads of the current wavefront. Otherwise, the result is
+/// undefined.
+///
+/// `value` is the value returned by `lane`.
+/// `default` is the value returned by all lanes other than `lane`.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 {
+    unsafe { llvm_writelane_u64(value, lane, default) }
+}
+
+/// Stop execution of the wavefront.
+///
+/// This usually signals the end of a successful execution.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn endpgm() -> ! {
+    llvm_endpgm()
+}
+
+/// The `update_dpp` intrinsic represents the `update.dpp` operation in AMDGPU.
+/// It takes an old value, a source operand, a DPP control operand, a row mask, a bank mask, and a bound control.
+/// This operation is equivalent to a sequence of `v_mov_b32` operations.
+///
+/// `llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
+/// Should be equivalent to:
+/// ```asm
+/// v_mov_b32 <dest> <old>
+/// v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
+/// ```
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn update_dpp<
+    const DPP_CTRL: u32,
+    const ROW_MASK: u32,
+    const BANK_MASK: u32,
+    const BOUND_CONTROL: bool,
+>(
+    old: u32,
+    src: u32,
+) -> u32 {
+    unsafe { llvm_update_dpp(old, src, DPP_CTRL, ROW_MASK, BANK_MASK, BOUND_CONTROL) }
+}
+
+/// Measures time based on a fixed frequency.
+///
+/// Provides a real-time clock counter that runs at constant speed (typically 100 MHz) independent of ALU clock speeds.
+/// The clock is consistent across the chip, so can be used for measuring between different wavefronts.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn s_memrealtime() -> u64 {
+    llvm_s_memrealtime()
+}
+
+/// Scatter data across all lanes in a wavefront.
+///
+/// Writes `value` to the lane `lane`.
+///
+/// Reading from inactive lanes returns `0`.
+/// In case multiple values get written to the same `lane`, the value from the source lane with the higher index is taken.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 {
+    unsafe { llvm_ds_permute(lane, value) }
+}
+/// Gather data across all lanes in a wavefront.
+///
+/// Returns the `value` given to `ds_permute` by lane `lane`.
+///
+/// Reading from inactive lanes returns `0`.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn ds_bpermute(lane: u32, value: u32) -> u32 {
+    unsafe { llvm_ds_bpermute(lane, value) }
+}
+/// Permute a 64-bit value.
+///
+/// `selector` selects between different patterns in which the 64-bit values represented by `src0` and `src1` are permuted.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn perm(src0: u32, src1: u32, selector: u32) -> u32 {
+    unsafe { llvm_perm(src0, src1, selector) }
+}
+
+// gfx10
+/// Performs arbitrary gather-style operation within a row (16 contiguous lanes) of the second input operand.
+///
+/// The third and fourth inputs must be uniform across the current wavefront.
+/// These are combined into a single 64-bit value representing lane selects used to swizzle within each row.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlane16_u32<const FI: bool, const BOUND_CONTROL: bool>(
+    old: u32,
+    src0: u32,
+    src1: u32,
+    src2: u32,
+) -> u32 {
+    unsafe { llvm_permlane16_u32(old, src0, src1, src2, FI, BOUND_CONTROL) }
+}
+
+// gfx10
+/// Performs arbitrary gather-style operation across two rows (16 contiguous lanes) of the second input operand.
+///
+/// The third and fourth inputs must be uniform across the current wavefront.
+/// These are combined into a single 64-bit value representing lane selects used to swizzle within each row.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlanex16_u32<const FI: bool, const BOUND_CONTROL: bool>(
+    old: u32,
+    src0: u32,
+    src1: u32,
+    src2: u32,
+) -> u32 {
+    unsafe { llvm_permlanex16_u32(old, src0, src1, src2, FI, BOUND_CONTROL) }
+}
+
+/// Get the index of the current wavefront in the workgroup.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn s_get_waveid_in_workgroup() -> u32 {
+    llvm_s_get_waveid_in_workgroup()
+}
+
+// gfx11
+/// Swap `value` between upper and lower 32 lanes in a wavefront.
+///
+/// Does nothing for wave32.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlane64_u32(value: u32) -> u32 {
+    unsafe { llvm_permlane64_u32(value) }
+}
+
+// gfx12
+/// Performs arbitrary gather-style operation within a row (16 contiguous lanes) of the second input operand.
+///
+/// In contrast to [`permlane16_u32`], allows each lane to specify its own gather lane.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlane16_var<const FI: bool, const BOUND_CONTROL: bool>(
+    old: u32,
+    src0: u32,
+    src1: u32,
+) -> u32 {
+    unsafe { llvm_permlane16_var(old, src0, src1, FI, BOUND_CONTROL) }
+}
+
+// gfx12
+/// Performs arbitrary gather-style operation across two rows (16 contiguous lanes) of the second input operand.
+///
+/// In contrast to [`permlanex16_u32`], allows each lane to specify its own gather lane.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlanex16_var<const FI: bool, const BOUND_CONTROL: bool>(
+    old: u32,
+    src0: u32,
+    src1: u32,
+) -> u32 {
+    unsafe { llvm_permlanex16_var(old, src0, src1, FI, BOUND_CONTROL) }
+}
+
+/// Get the index of the current wavefront in the workgroup.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub fn wave_id() -> u32 {
+    llvm_wave_id()
+}
+
+// gfx950
+/// Provide direct access to `v_permlane16_swap_b32` instruction on supported targets.
+///
+/// Swaps the values across lanes of first 2 operands.
+/// Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes).
+/// Returns a pair for the swapped registers.
+/// The first element of the return corresponds to the swapped element of the first argument.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlane16_swap<const FI: bool, const BOUND_CONTROL: bool>(
+    vdst_old: u32,
+    vsrc_src0: u32,
+) -> (u32, u32) {
+    unsafe { llvm_permlane16_swap(vdst_old, vsrc_src0, FI, BOUND_CONTROL) }
+}
+
+// gfx950
+/// Provide direct access to `v_permlane32_swap_b32` instruction on supported targets.
+///
+/// Swaps the values across lanes of first 2 operands.
+/// Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes).
+/// Returns a pair for the swapped registers.
+/// The first element of the return corresponds to the swapped element of the first argument.
+#[inline]
+#[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+pub unsafe fn permlane32_swap<const FI: bool, const BOUND_CONTROL: bool>(
+    vdst_old: u32,
+    vsrc_src0: u32,
+) -> (u32, u32) {
+    unsafe { llvm_permlane32_swap(vdst_old, vsrc_src0, FI, BOUND_CONTROL) }
+}
+
+// Functions to generate code, used to check that the intrinsics build.
+// Marked as no_mangle, so the compiler does not remove the functions.
+// To test, uncomment the `#[cfg(test)]` line below and run
+// NORUN=1 NOSTD=1 TARGET=amdgcn-amd-amdhsa CARGO_UNSTABLE_BUILD_STD=core ci/run.sh
+//
+// Note that depending on the target-cpu set in run.sh, some of these intrinsics are not available
+// and compilation fails with `Cannot select: intrinsic %llvm.amdgcn...`.
+// Uncomment these intrinsics to check.
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[unsafe(no_mangle)]
+    fn test_workitem_id_x() -> u32 {
+        workitem_id_x()
+    }
+    #[unsafe(no_mangle)]
+    fn test_workitem_id_y() -> u32 {
+        workitem_id_y()
+    }
+    #[unsafe(no_mangle)]
+    fn test_workitem_id_z() -> u32 {
+        workitem_id_z()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_workgroup_id_x() -> u32 {
+        workgroup_id_x()
+    }
+    #[unsafe(no_mangle)]
+    fn test_workgroup_id_y() -> u32 {
+        workgroup_id_y()
+    }
+    #[unsafe(no_mangle)]
+    fn test_workgroup_id_z() -> u32 {
+        workgroup_id_z()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_groupstaticsize() -> u32 {
+        groupstaticsize()
+    }
+    #[unsafe(no_mangle)]
+    fn test_dispatch_id() -> u64 {
+        dispatch_id()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wavefrontsize() -> u32 {
+        wavefrontsize()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_barrier() {
+        s_barrier()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_barrier_signal() {
+        unsafe { s_barrier_signal::<-1>() }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_barrier_signal_isfirst() -> bool {
+        unsafe { s_barrier_signal_isfirst::<-1>() }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_barrier_wait() {
+        unsafe { s_barrier_wait::<-1>() }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_get_barrier_state() -> u32 {
+        unsafe { s_get_barrier_state::<-1>() }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wave_barrier() {
+        wave_barrier()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_sched_barrier() {
+        unsafe { sched_barrier::<1>() }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_sched_group_barrier() {
+        unsafe { sched_group_barrier::<1, 1, 0>() }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_sleep() {
+        s_sleep::<1>()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_sethalt() -> ! {
+        s_sethalt::<1>()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_getpc() -> i64 {
+        s_getpc()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_mbcnt_lo(value: u32, init: u32) -> u32 {
+        mbcnt_lo(value, init)
+    }
+    #[unsafe(no_mangle)]
+    fn test_mbcnt_hi(value: u32, init: u32) -> u32 {
+        mbcnt_hi(value, init)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_ballot(b: bool) -> u64 {
+        ballot(b)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_inverse_ballot(value: u64) -> bool {
+        inverse_ballot(value)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_umin(value: u32) -> u32 {
+        wave_reduce_umin::<0>(value)
+    }
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_min(value: i32) -> i32 {
+        wave_reduce_min::<0>(value)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_umax(value: u32) -> u32 {
+        wave_reduce_umax::<0>(value)
+    }
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_max(value: i32) -> i32 {
+        wave_reduce_max::<0>(value)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_add(value: u32) -> u32 {
+        wave_reduce_add::<0>(value)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_and(value: u32) -> u32 {
+        wave_reduce_and::<0>(value)
+    }
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_or(value: u32) -> u32 {
+        wave_reduce_or::<0>(value)
+    }
+    #[unsafe(no_mangle)]
+    fn test_wave_reduce_xor(value: u32) -> u32 {
+        wave_reduce_xor::<0>(value)
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_readfirstlane_u32(value: u32) -> u32 {
+        readfirstlane_u32(value)
+    }
+    #[unsafe(no_mangle)]
+    fn test_readfirstlane_u64(value: u64) -> u64 {
+        readfirstlane_u64(value)
+    }
+    #[unsafe(no_mangle)]
+    fn test_readlane_u32(value: u32, lane: u32) -> u32 {
+        unsafe { readlane_u32(value, lane) }
+    }
+    #[unsafe(no_mangle)]
+    fn test_readlane_u64(value: u64, lane: u32) -> u64 {
+        unsafe { readlane_u64(value, lane) }
+    }
+    #[unsafe(no_mangle)]
+    fn test_writelane_u32(value: u32, lane: u32, default: u32) -> u32 {
+        unsafe { writelane_u32(value, lane, default) }
+    }
+    #[unsafe(no_mangle)]
+    fn test_writelane_u64(value: u64, lane: u32, default: u64) -> u64 {
+        unsafe { writelane_u64(value, lane, default) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_endpgm() -> ! {
+        endpgm()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_update_dpp(old: u32, src: u32) -> u32 {
+        unsafe { update_dpp::<0, 0, 0, true>(old, src) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_memrealtime() -> u64 {
+        s_memrealtime()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_ds_permute(lane: u32, value: u32) -> u32 {
+        unsafe { ds_permute(lane, value) }
+    }
+    #[unsafe(no_mangle)]
+    fn test_ds_bpermute(lane: u32, value: u32) -> u32 {
+        unsafe { ds_bpermute(lane, value) }
+    }
+    #[unsafe(no_mangle)]
+    fn test_perm(src0: u32, src1: u32, selector: u32) -> u32 {
+        unsafe { perm(src0, src1, selector) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlane16_u32(old: u32, src0: u32, src1: u32, src2: u32) -> u32 {
+        unsafe { permlane16_u32::<false, true>(old, src0, src1, src2) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlanex16_u32(old: u32, src0: u32, src1: u32, src2: u32) -> u32 {
+        unsafe { permlanex16_u32::<false, true>(old, src0, src1, src2) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_s_get_waveid_in_workgroup() -> u32 {
+        s_get_waveid_in_workgroup()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlane64_u32(value: u32) -> u32 {
+        unsafe { permlane64_u32(value) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlane16_var(old: u32, src0: u32, src1: u32) -> u32 {
+        unsafe { permlane16_var::<false, true>(old, src0, src1) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlanex16_var(old: u32, src0: u32, src1: u32) -> u32 {
+        unsafe { permlanex16_var::<false, true>(old, src0, src1) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_wave_id() -> u32 {
+        wave_id()
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlane16_swap(vdst_old: u32, vsrc_src0: u32) -> (u32, u32) {
+        unsafe { permlane16_swap::<false, true>(vdst_old, vsrc_src0) }
+    }
+
+    #[unsafe(no_mangle)]
+    fn test_permlane32_swap(vdst_old: u32, vsrc_src0: u32) -> (u32, u32) {
+        unsafe { permlane32_swap::<false, true>(vdst_old, vsrc_src0) }
+    }
+}
diff --git a/crates/core_arch/src/core_arch_docs.md b/crates/core_arch/src/core_arch_docs.md
index 6aea2b4618..7075945754 100644
--- a/crates/core_arch/src/core_arch_docs.md
+++ b/crates/core_arch/src/core_arch_docs.md
@@ -185,6 +185,7 @@ others at:
 * [`x86_64`]
 * [`arm`]
 * [`aarch64`]
+* [`amdgpu`]
 * [`riscv32`]
 * [`riscv64`]
 * [`mips`]
@@ -201,6 +202,7 @@ others at:
 [`x86_64`]: ../../core/arch/x86_64/index.html
 [`arm`]: ../../core/arch/arm/index.html
 [`aarch64`]: ../../core/arch/aarch64/index.html
+[`amdgpu`]: ../../core/arch/amdgpu/index.html
 [`riscv32`]: ../../core/arch/riscv32/index.html
 [`riscv64`]: ../../core/arch/riscv64/index.html
 [`mips`]: ../../core/arch/mips/index.html
diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs
index 2105cca1b4..fbb8562d31 100644
--- a/crates/core_arch/src/mod.rs
+++ b/crates/core_arch/src/mod.rs
@@ -274,6 +274,16 @@ pub mod arch {
         pub use crate::core_arch::nvptx::*;
     }
 
+    /// Platform-specific intrinsics for the `amdgpu` platform.
+    ///
+    /// See the [module documentation](../index.html) for more details.
+    #[cfg(any(target_arch = "amdgpu", doc))]
+    #[doc(cfg(target_arch = "amdgpu"))]
+    #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
+    pub mod amdgpu {
+        pub use crate::core_arch::amdgpu::*;
+    }
+
     /// Platform-specific intrinsics for the `loongarch32` platform.
     ///
     /// See the [module documentation](../index.html) for more details.
@@ -349,6 +359,10 @@ mod powerpc64;
 #[doc(cfg(target_arch = "nvptx64"))]
 mod nvptx;
 
+#[cfg(any(target_arch = "amdgpu", doc))]
+#[doc(cfg(target_arch = "amdgpu"))]
+mod amdgpu;
+
 #[cfg(any(target_arch = "loongarch32", doc))]
 #[doc(cfg(target_arch = "loongarch32"))]
 mod loongarch32;

From 0f9516b24064b639d59d190bf9aa577999dc11fc Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Sat, 20 Sep 2025 13:47:33 +0800
Subject: [PATCH 083/326] (partially) stablize stdarch_neon_f16

---
 .../core_arch/src/aarch64/neon/generated.rs   |  266 +--
 .../src/arm_shared/neon/generated.rs          | 1826 +++++++++++++++--
 crates/core_arch/src/arm_shared/neon/mod.rs   |   57 +-
 .../spec/neon/aarch64.spec.yml                |  120 +-
 .../spec/neon/arm_shared.spec.yml             |  180 +-
 5 files changed, 1987 insertions(+), 462 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index da931bdf50..7743e52f4f 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -961,7 +961,7 @@ pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcadd))]
 pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -979,7 +979,7 @@ pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcadd))]
 pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -1045,7 +1045,7 @@ pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcadd))]
 pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -1063,7 +1063,7 @@ pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcadd))]
 pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -1501,7 +1501,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 {
 #[inline]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
     let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
@@ -1512,7 +1512,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t {
     let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
@@ -2837,7 +2837,7 @@ pub fn vcltzh_f16(a: f16) -> u16 {
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
@@ -2855,7 +2855,7 @@ pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
@@ -2923,7 +2923,7 @@ pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -2952,7 +2952,7 @@ pub fn vcmla_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3030,7 +3030,7 @@ pub fn vcmlaq_lane_f32<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3059,7 +3059,7 @@ pub fn vcmla_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3135,7 +3135,7 @@ pub fn vcmlaq_laneq_f32<const LANE: i32>(
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
@@ -3153,7 +3153,7 @@ pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
@@ -3221,7 +3221,7 @@ pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_rot180_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3250,7 +3250,7 @@ pub fn vcmla_rot180_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_rot180_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3328,7 +3328,7 @@ pub fn vcmlaq_rot180_lane_f32<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3357,7 +3357,7 @@ pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_rot180_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3433,7 +3433,7 @@ pub fn vcmlaq_rot180_laneq_f32<const LANE: i32>(
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
@@ -3451,7 +3451,7 @@ pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
@@ -3519,7 +3519,7 @@ pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_rot270_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3548,7 +3548,7 @@ pub fn vcmla_rot270_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_rot270_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3626,7 +3626,7 @@ pub fn vcmlaq_rot270_lane_f32<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3655,7 +3655,7 @@ pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_rot270_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3731,7 +3731,7 @@ pub fn vcmlaq_rot270_laneq_f32<const LANE: i32>(
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
@@ -3749,7 +3749,7 @@ pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1
 #[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fcmla))]
 pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
@@ -3817,7 +3817,7 @@ pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_rot90_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3846,7 +3846,7 @@ pub fn vcmla_rot90_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_rot90_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -3924,7 +3924,7 @@ pub fn vcmlaq_rot90_lane_f32<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -3953,7 +3953,7 @@ pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcmlaq_rot90_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -7219,7 +7219,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
     vcombine_f16(a, vcvt_f16_f32(b))
@@ -7229,7 +7229,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
     vcvt_f32_f16(vget_high_f16(a))
@@ -7468,7 +7468,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -7485,7 +7485,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -7566,7 +7566,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -7583,7 +7583,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -8154,7 +8154,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -8171,7 +8171,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -8252,7 +8252,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -8269,7 +8269,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -8502,7 +8502,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -8519,7 +8519,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -8600,7 +8600,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -8617,7 +8617,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -8850,7 +8850,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -8867,7 +8867,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -8948,7 +8948,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -8965,7 +8965,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -9429,7 +9429,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fdiv))]
 pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -9439,7 +9439,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fdiv))]
 pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -10106,7 +10106,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfma_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10122,7 +10122,7 @@ pub fn vfma_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfma_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10138,7 +10138,7 @@ pub fn vfma_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmaq_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -10154,7 +10154,7 @@ pub fn vfmaq_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmaq_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -10432,7 +10432,7 @@ pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal2))]
 pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10450,7 +10450,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal2))]
 pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10470,7 +10470,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_lane_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10487,7 +10487,7 @@ pub fn vfmlal_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_laneq_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10504,7 +10504,7 @@ pub fn vfmlal_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_lane_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10521,7 +10521,7 @@ pub fn vfmlalq_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10538,7 +10538,7 @@ pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_lane_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10555,7 +10555,7 @@ pub fn vfmlal_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_laneq_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10572,7 +10572,7 @@ pub fn vfmlal_laneq_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_lane_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10589,7 +10589,7 @@ pub fn vfmlalq_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10604,7 +10604,7 @@ pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal))]
 pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10622,7 +10622,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal))]
 pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10640,7 +10640,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl2))]
 pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10658,7 +10658,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl2))]
 pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10678,7 +10678,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_lane_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10695,7 +10695,7 @@ pub fn vfmlsl_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10712,7 +10712,7 @@ pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_lane_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10729,7 +10729,7 @@ pub fn vfmlslq_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10746,7 +10746,7 @@ pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_lane_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10763,7 +10763,7 @@ pub fn vfmlsl_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10780,7 +10780,7 @@ pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_lane_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10797,7 +10797,7 @@ pub fn vfmlslq_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10812,7 +10812,7 @@ pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl))]
 pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10830,7 +10830,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 #[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl))]
 pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10861,7 +10861,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfms_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10877,7 +10877,7 @@ pub fn vfms_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfms_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10893,7 +10893,7 @@ pub fn vfms_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsq_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -10909,7 +10909,7 @@ pub fn vfmsq_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsq_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -14739,7 +14739,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -14756,7 +14756,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -15263,7 +15263,7 @@ pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmulx))]
 pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -15280,7 +15280,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmulx))]
 pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -15363,7 +15363,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
@@ -15380,7 +15380,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -15397,7 +15397,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
@@ -15427,7 +15427,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -15789,7 +15789,7 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(faddp))]
 pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16008,7 +16008,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxp))]
 pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16025,7 +16025,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxp))]
 pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16042,7 +16042,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16059,7 +16059,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16316,7 +16316,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminp))]
 pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16333,7 +16333,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminp))]
 pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16350,7 +16350,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnmp))]
 pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16367,7 +16367,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnmp))]
 pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -21493,7 +21493,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
@@ -21504,7 +21504,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
@@ -21516,7 +21516,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
@@ -21527,7 +21527,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
@@ -21542,7 +21542,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
@@ -21553,7 +21553,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
@@ -21567,7 +21567,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
@@ -21578,7 +21578,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
@@ -23157,7 +23157,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintz))]
 pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
@@ -23167,7 +23167,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintz))]
 pub fn vrndq_f16(a: float16x8_t) -> float16x8_t {
@@ -23213,7 +23213,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinta))]
 pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
@@ -23223,7 +23223,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinta))]
 pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t {
@@ -23289,7 +23289,7 @@ pub fn vrndh_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinti))]
 pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
@@ -23306,7 +23306,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinti))]
 pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t {
@@ -23404,7 +23404,7 @@ pub fn vrndih_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintm))]
 pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
@@ -23414,7 +23414,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintm))]
 pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t {
@@ -23535,7 +23535,7 @@ pub fn vrndns_f32(a: f32) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintp))]
 pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
@@ -23545,7 +23545,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintp))]
 pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t {
@@ -23601,7 +23601,7 @@ pub fn vrndph_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintx))]
 pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
@@ -23611,7 +23611,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintx))]
 pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t {
@@ -25034,7 +25034,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 {
 #[inline]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
     unsafe { simd_fsqrt(a) }
@@ -25044,7 +25044,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
 #[inline]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t {
     unsafe { simd_fsqrt(a) }
@@ -27532,7 +27532,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
 pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -27542,7 +27542,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
 pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -27768,7 +27768,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
 pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -27778,7 +27778,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
 pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -28309,7 +28309,7 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
 pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -28319,7 +28319,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
 pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -28545,7 +28545,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
 pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -28555,7 +28555,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
 pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -28799,7 +28799,7 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
 pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -28809,7 +28809,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
 pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -29035,7 +29035,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
 pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -29045,7 +29045,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
 #[inline]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
 pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 314965cc20..0aeb740efc 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -819,7 +819,14 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
     assert_instr(fabd)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -842,7 +849,14 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fabd)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -1406,7 +1420,14 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
     assert_instr(fabs)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
     unsafe { simd_fabs(a) }
@@ -1421,7 +1442,14 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
     assert_instr(fabs)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
     unsafe { simd_fabs(a) }
@@ -1643,7 +1671,14 @@ pub fn vabsh_f16(a: f16) -> f16 {
     assert_instr(fadd)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_add(a, b) }
@@ -1658,7 +1693,14 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fadd)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_add(a, b) }
@@ -3835,7 +3877,14 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(bsl)
 )]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
     let not = int16x4_t::splat(-1);
@@ -3856,7 +3905,14 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(bsl)
 )]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
     let not = int16x8_t::splat(-1);
@@ -4471,7 +4527,14 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
     assert_instr(facge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -4494,7 +4557,14 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(facge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -4575,7 +4645,14 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
     assert_instr(facgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -4598,7 +4675,14 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(facgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -4679,7 +4763,14 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
     assert_instr(facge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     vcage_f16(b, a)
@@ -4694,7 +4785,14 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(facge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     vcageq_f16(b, a)
@@ -4751,7 +4849,14 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
     assert_instr(facgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     vcagt_f16(b, a)
@@ -4766,7 +4871,14 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(facgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     vcagtq_f16(b, a)
@@ -4823,7 +4935,14 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
     assert_instr(fcmeq)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe { simd_eq(a, b) }
@@ -4838,7 +4957,14 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(fcmeq)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe { simd_eq(a, b) }
@@ -5189,7 +5315,14 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
     assert_instr(fcmge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe { simd_ge(a, b) }
@@ -5204,7 +5337,14 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(fcmge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe { simd_ge(a, b) }
@@ -5513,7 +5653,14 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(fcmge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
     let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
@@ -5529,7 +5676,14 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(fcmge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
     let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
@@ -5545,7 +5699,14 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
     assert_instr(fcmgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe { simd_gt(a, b) }
@@ -5560,7 +5721,14 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(fcmgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe { simd_gt(a, b) }
@@ -5869,7 +6037,14 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(fcmgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
     let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
@@ -5885,7 +6060,14 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(fcmgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
     let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
@@ -5901,7 +6083,14 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
     assert_instr(fcmge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe { simd_le(a, b) }
@@ -5916,7 +6105,14 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(fcmge)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe { simd_le(a, b) }
@@ -6225,7 +6421,14 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(fcmle)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
     let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
@@ -6241,7 +6444,14 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(fcmle)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
     let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
@@ -6557,7 +6767,14 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
     assert_instr(fcmgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     unsafe { simd_lt(a, b) }
@@ -6572,7 +6789,14 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
     assert_instr(fcmgt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
     unsafe { simd_lt(a, b) }
@@ -6881,7 +7105,14 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(fcmlt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
     let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
@@ -6897,7 +7128,14 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(fcmlt)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
     let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
@@ -7572,7 +7810,14 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
@@ -7794,7 +8039,14 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
     assert_instr(nop)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcreate_f16(a: u64) -> float16x4_t {
     unsafe { transmute(a) }
@@ -7811,7 +8063,14 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
     assert_instr(nop)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcreate_f16(a: u64) -> float16x4_t {
     unsafe {
@@ -8316,7 +8575,14 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
     assert_instr(fcvtn)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
     unsafe { simd_cast(a) }
@@ -8331,7 +8597,14 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
     assert_instr(scvtf)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
     unsafe { simd_cast(a) }
@@ -8346,7 +8619,14 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
     assert_instr(scvtf)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
     unsafe { simd_cast(a) }
@@ -8361,7 +8641,14 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
     assert_instr(ucvtf)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
     unsafe { simd_cast(a) }
@@ -8376,7 +8663,14 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
     assert_instr(ucvtf)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
     unsafe { simd_cast(a) }
@@ -8392,7 +8686,14 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
     assert_instr(fcvtl)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
     unsafe { simd_cast(a) }
@@ -8492,7 +8793,14 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8520,7 +8828,14 @@ pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8548,7 +8863,14 @@ pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8576,7 +8898,14 @@ pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8756,7 +9085,14 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8784,7 +9120,14 @@ pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8888,7 +9231,14 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
     static_assert!(N >= 1 && N <= 16);
@@ -8916,7 +9266,14 @@ pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
@@ -9019,7 +9376,14 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
     assert_instr(fcvtzs)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe { simd_cast(a) }
@@ -9034,7 +9398,14 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
     assert_instr(fcvtzs)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe { simd_cast(a) }
@@ -9107,7 +9478,14 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
     assert_instr(fcvtzu)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe { simd_cast(a) }
@@ -9122,7 +9500,14 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(fcvtzu)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe { simd_cast(a) }
@@ -9559,7 +9944,14 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(N, 2);
@@ -9577,7 +9969,14 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(N, 2);
@@ -10124,7 +10523,14 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(N, 3);
@@ -10142,7 +10548,14 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 )]
 #[rustc_legacy_const_generics(1)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(N, 3);
@@ -11652,7 +12065,14 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 )]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(N, 2);
@@ -12024,7 +12444,14 @@ pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 )]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(N, 3);
@@ -12605,7 +13032,14 @@ pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     assert_instr(fmla)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
     unsafe { simd_fma(b, c, a) }
@@ -12620,7 +13054,14 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
     assert_instr(fmla)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
     unsafe { simd_fma(b, c, a) }
@@ -12720,7 +13161,14 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
     assert_instr(fmls)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
     unsafe {
@@ -12739,7 +13187,14 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
     assert_instr(fmls)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
     unsafe {
@@ -12843,7 +13298,14 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
@@ -12855,7 +13317,14 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
@@ -19431,7 +19900,7 @@ unsafe fn vld1q_v8i16<const ALIGN: i32>(a: *const i8) -> int16x8_t {
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg(not(target_arch = "arm64ec"))]
 unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -19445,7 +19914,7 @@ unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg(not(target_arch = "arm64ec"))]
 unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -27522,7 +27991,14 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
     assert_instr(fmax)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -27545,7 +28021,14 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fmax)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -27914,7 +28397,14 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(fmaxnm)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_fmax(a, b) }
@@ -27929,7 +28419,14 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fmaxnm)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_fmax(a, b) }
@@ -27986,7 +28483,14 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     assert_instr(fmin)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -28009,7 +28513,14 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fmin)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -28378,7 +28889,14 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(fminnm)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_fmin(a, b) }
@@ -28393,7 +28911,14 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fminnm)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_fmin(a, b) }
@@ -32322,7 +32847,14 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
     assert_instr(fmul)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_mul(a, b) }
@@ -32337,7 +32869,14 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fmul)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_mul(a, b) }
@@ -32395,7 +32934,14 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 )]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
@@ -32417,7 +32963,14 @@ pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16
 )]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
@@ -34382,7 +34935,14 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
     assert_instr(fneg)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
     unsafe { simd_neg(a) }
@@ -34397,7 +34957,14 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
     assert_instr(fneg)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
     unsafe { simd_neg(a) }
@@ -35628,7 +36195,14 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
     assert_instr(faddp)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -41703,7 +42277,14 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
     assert_instr(frecpe)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -41726,7 +42307,14 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
     assert_instr(frecpe)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -41865,7 +42453,14 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
     assert_instr(frecps)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -41888,7 +42483,14 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(frecps)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -41970,7 +42572,14 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
     unsafe { transmute(a) }
@@ -41986,7 +42595,14 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42006,7 +42622,14 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
     unsafe { transmute(a) }
@@ -42022,7 +42645,14 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42042,7 +42672,14 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe { transmute(a) }
@@ -42058,7 +42695,14 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42078,7 +42722,14 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     unsafe { transmute(a) }
@@ -42094,7 +42745,14 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42114,7 +42772,14 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     unsafe { transmute(a) }
@@ -42130,7 +42795,14 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42147,7 +42819,14 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     unsafe { transmute(a) }
@@ -42163,7 +42842,14 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42183,7 +42869,14 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe { transmute(a) }
@@ -42199,7 +42892,14 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42219,7 +42919,14 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     unsafe { transmute(a) }
@@ -42235,7 +42942,14 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42255,7 +42969,14 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     unsafe { transmute(a) }
@@ -42271,7 +42992,14 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42288,7 +43016,14 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     unsafe { transmute(a) }
@@ -42304,7 +43039,14 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42324,7 +43066,14 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     unsafe { transmute(a) }
@@ -42340,7 +43089,14 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42360,7 +43116,14 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     unsafe { transmute(a) }
@@ -42376,7 +43139,14 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42396,7 +43166,14 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     unsafe { transmute(a) }
@@ -42412,7 +43189,14 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42436,7 +43220,14 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe { transmute(a) }
@@ -42452,7 +43243,14 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42472,7 +43270,14 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     unsafe { transmute(a) }
@@ -42488,7 +43293,14 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42508,7 +43320,14 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     unsafe { transmute(a) }
@@ -42524,7 +43343,14 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42544,7 +43370,14 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     unsafe { transmute(a) }
@@ -42560,7 +43393,14 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42584,7 +43424,14 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe { transmute(a) }
@@ -42600,7 +43447,14 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42620,7 +43474,14 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     unsafe { transmute(a) }
@@ -42636,7 +43497,14 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42656,7 +43524,14 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     unsafe { transmute(a) }
@@ -42672,7 +43547,14 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42692,7 +43574,14 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     unsafe { transmute(a) }
@@ -42708,7 +43597,14 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42732,7 +43628,14 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
     unsafe { transmute(a) }
@@ -42748,7 +43651,14 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42768,7 +43678,14 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -42784,7 +43701,14 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
@@ -42804,7 +43728,14 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -42820,7 +43751,14 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42840,7 +43778,14 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -42856,7 +43801,14 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42876,7 +43828,14 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -42892,7 +43851,14 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     let a: int8x16_t =
@@ -42913,7 +43879,14 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -42929,7 +43902,14 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -42949,7 +43929,14 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -42965,7 +43952,14 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
     let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -42985,7 +43979,14 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43001,7 +44002,14 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
@@ -43021,7 +44029,14 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43037,7 +44052,14 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -43057,7 +44079,14 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43073,7 +44102,14 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     unsafe {
@@ -43092,7 +44128,14 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43108,7 +44151,14 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
@@ -43128,7 +44178,14 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43144,7 +44201,14 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -43164,7 +44228,14 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43180,7 +44251,14 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     let a: uint8x16_t =
@@ -43201,7 +44279,14 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43217,7 +44302,14 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -43237,7 +44329,14 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43253,7 +44352,14 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
     let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -43273,7 +44379,14 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43289,7 +44402,14 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
@@ -43309,7 +44429,14 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43325,7 +44452,14 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -43345,7 +44479,14 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43361,7 +44502,14 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
     unsafe {
@@ -43380,7 +44528,14 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43396,7 +44551,14 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
     let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
@@ -43416,7 +44578,14 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43432,7 +44601,14 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
     let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -43452,7 +44628,14 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43468,7 +44651,14 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
     let a: poly8x16_t =
@@ -43489,7 +44679,14 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43505,7 +44702,14 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
     let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -43525,7 +44729,14 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43541,7 +44752,14 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
     let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -43561,7 +44779,14 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43577,7 +44802,14 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
     unsafe {
@@ -43596,7 +44828,14 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
     unsafe { transmute(a) }
@@ -43612,7 +44851,14 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
     let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
@@ -43629,7 +44875,14 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
     unsafe { transmute(a) }
@@ -43645,7 +44898,14 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -43662,7 +44922,14 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
     unsafe { transmute(a) }
@@ -43678,7 +44945,14 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
     let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
@@ -43698,7 +44972,14 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
     unsafe { transmute(a) }
@@ -43714,7 +44995,14 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
     unsafe {
@@ -43733,7 +45021,14 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
     unsafe { transmute(a) }
@@ -43749,7 +45044,14 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
     assert_instr(nop)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
     let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
@@ -57746,7 +59048,14 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
     assert_instr(rev64)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
@@ -57761,7 +59070,14 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
     assert_instr(rev64)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
@@ -58124,7 +59440,14 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     assert_instr(frintn)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -58146,7 +59469,14 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
     assert_instr(frintn)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -59230,7 +60560,14 @@ pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(frsqrte)
 )]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -59253,7 +60590,14 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(frsqrte)
 )]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -59392,7 +60736,14 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(frsqrts)
 )]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -59415,7 +60766,14 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(frsqrts)
 )]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -66926,7 +68284,7 @@ unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
@@ -66944,7 +68302,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
 unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
@@ -70962,7 +72320,14 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
     assert_instr(fsub)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_sub(a, b) }
@@ -70977,7 +72342,14 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     assert_instr(fsub)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_sub(a, b) }
@@ -72910,7 +74282,14 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
     assert_instr(trn2)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
     unsafe {
@@ -72933,7 +74312,14 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
     assert_instr(trn2)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
     unsafe {
@@ -74112,7 +75498,14 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
     assert_instr(uzp2)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
     unsafe {
@@ -74135,7 +75528,14 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
     assert_instr(uzp2)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
     unsafe {
@@ -74704,7 +76104,14 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
     assert_instr(zip2)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
     unsafe {
@@ -74727,7 +76134,14 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
     assert_instr(zip2)
 )]
 #[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
     unsafe {
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index fbd1967c54..809892e0bf 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -104,7 +104,8 @@ types! {
 }
 
 types! {
-    #![unstable(feature = "stdarch_neon_f16", issue = "136306")]
+    #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))]
+    #![cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))]
 
     /// Arm-specific 64-bit wide vector of four packed `f16`.
     pub struct float16x4_t(4 x pub(crate) f16);
@@ -747,19 +748,40 @@ pub struct uint32x4x4_t(
 /// Arm-specific type containing two `float16x4_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 pub struct float16x4x2_t(pub float16x4_t, pub float16x4_t);
 
 /// Arm-specific type containing three `float16x4_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 pub struct float16x4x3_t(pub float16x4_t, pub float16x4_t, pub float16x4_t);
 
 /// Arm-specific type containing four `float16x4_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 pub struct float16x4x4_t(
     pub float16x4_t,
     pub float16x4_t,
@@ -770,19 +792,40 @@ pub struct float16x4x4_t(
 /// Arm-specific type containing two `float16x8_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 pub struct float16x8x2_t(pub float16x8_t, pub float16x8_t);
 
 /// Arm-specific type containing three `float16x8_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 pub struct float16x8x3_t(pub float16x8_t, pub float16x8_t, pub float16x8_t);
 
 /// Arm-specific type containing four `float16x8_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
 pub struct float16x8x4_t(
     pub float16x8_t,
     pub float16x8_t,
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 2890ac632d..8f36c525fa 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -13,6 +13,10 @@ auto_llvm_sign_conversion: false
 neon-stable: &neon-stable
   FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
 
+# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+neon-stable-fp16: &neon-stable-fp16
+  FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]
+
 # #[cfg(not(target_arch = "arm64ec"))]
 target-not-arm64ec: &target-not-arm64ec
   FnCall: [cfg, [{ FnCall: [not, ['target_arch = "arm64ec"']]}]]
@@ -1506,7 +1510,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1523,7 +1527,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1807,7 +1811,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1977,7 +1981,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1998,7 +2002,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -2112,7 +2116,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -2133,7 +2137,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -2328,7 +2332,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -2349,7 +2353,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -3032,7 +3036,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [frintx]
     safety: safe
@@ -3081,7 +3085,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [frinta]
     safety: safe
@@ -3181,7 +3185,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [frintm]
     safety: safe
@@ -3231,7 +3235,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [frintp]
     safety: safe
@@ -3277,7 +3281,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [frintz]
     safety: safe
@@ -3330,7 +3334,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [frinti]
     safety: safe
@@ -5268,7 +5272,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmulx]
     safety: safe
@@ -5450,7 +5454,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -5651,7 +5655,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fdiv]
     safety: safe
@@ -6000,7 +6004,7 @@ intrinsics:
     attr:
       - *neon-fp16
       - *enable-fcma
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     assert_instr: [fcadd]
     safety: safe
@@ -6021,7 +6025,7 @@ intrinsics:
     attr:
       - *neon-fp16
       - *enable-fcma
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     assert_instr: [fcadd]
     safety: safe
@@ -6062,7 +6066,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "neon,fcma"']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     assert_instr: [fcmla]
     safety: safe
@@ -6103,7 +6107,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "neon,fcma"']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     assert_instr: [fcmla]
     safety: safe
@@ -6145,7 +6149,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "neon,fcma"']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     assert_instr: [fcmla]
     safety: safe
@@ -6190,7 +6194,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6236,7 +6240,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6282,7 +6286,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6325,7 +6329,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "neon,fcma"']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     assert_instr: [fcmla]
     safety: safe
@@ -6371,7 +6375,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6419,7 +6423,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6467,7 +6471,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6514,7 +6518,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6558,7 +6562,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-unstable-fcma
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6969,7 +6973,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [faddp]
     safety: safe
@@ -6989,7 +6993,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmaxp]
     safety: safe
@@ -7010,7 +7014,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmaxnmp]
     safety: safe
@@ -7031,7 +7035,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fminp]
     safety: safe
@@ -7052,7 +7056,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fminnmp]
     safety: safe
@@ -8478,7 +8482,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8791,7 +8795,7 @@ intrinsics:
     arguments: ["a: {type[0]}"]
     return_type: "{type[1]}"
     attr:
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [nop]
     safety: safe
@@ -9691,7 +9695,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]]
     safety: safe
@@ -9753,7 +9757,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]]
     safety: safe
@@ -9822,7 +9826,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
     safety: safe
@@ -9873,7 +9877,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
     safety: safe
@@ -9935,7 +9939,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]]
     safety: safe
@@ -10001,7 +10005,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]]
     safety: safe
@@ -10291,7 +10295,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
@@ -10318,7 +10322,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
@@ -10658,7 +10662,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11248,7 +11252,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
@@ -11862,7 +11866,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
     types:
@@ -13770,7 +13774,7 @@ intrinsics:
     attr:
       - *neon-fp16
       - *enable-fhm
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmlal2]
     safety: safe
@@ -13794,7 +13798,7 @@ intrinsics:
       - *neon-fp16
       - *enable-fhm
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
@@ -13819,7 +13823,7 @@ intrinsics:
     attr:
       - *neon-fp16
       - *enable-fhm
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmlal]
     safety: safe
@@ -13843,7 +13847,7 @@ intrinsics:
       - *neon-fp16
       - *enable-fhm
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
@@ -13868,7 +13872,7 @@ intrinsics:
     attr:
       - *neon-fp16
       - *enable-fhm
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmlsl2]
     safety: safe
@@ -13891,7 +13895,7 @@ intrinsics:
       - *neon-fp16
       - *enable-fhm
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
@@ -13916,7 +13920,7 @@ intrinsics:
     attr:
       - *neon-fp16
       - *enable-fhm
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     assert_instr: [fmlsl]
     safety: safe
@@ -13939,7 +13943,7 @@ intrinsics:
       - *neon-fp16
       - *enable-fhm
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - *neon-unstable-f16
+      - *neon-stable-fp16
       - *target-not-arm64ec
     static_defs: ['const LANE: i32']
     safety: safe
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index e8b31d73f9..c7a333d7f7 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -10,6 +10,10 @@ auto_big_endian: true
 neon-stable: &neon-stable
   FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
 
+# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+neon-stable-fp16: &neon-stable-fp16
+  FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]
+
 # #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))]
 neon-cfg-arm-unstable: &neon-cfg-arm-unstable
   FnCall: ['cfg_attr', ['target_arch = "arm"', {FnCall: ['unstable', ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]]
@@ -51,6 +55,10 @@ neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec
 neon-not-arm-stable: &neon-not-arm-stable
   FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]]
 
+# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))]
+neon-not-arm-stable-fp16: &neon-not-arm-stable-fp16
+  FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]}]]
+
 # #[cfg_attr(all(test, not(target_env = "msvc"))]
 msvc-disabled: &msvc-disabled
   FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]
@@ -285,7 +293,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vabd.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fabd]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -404,7 +413,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vceq.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmeq]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -466,7 +476,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vabs]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fabs]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -566,7 +577,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcgt.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmgt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -585,7 +597,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcgt.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmgt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -664,7 +677,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcge.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmge]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -682,7 +696,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcle.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmle]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -864,7 +879,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vacgt.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [facgt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -911,7 +927,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vacge.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [facge]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -952,7 +969,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vacgt.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [facgt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -988,7 +1006,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vacge.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [facge]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1023,7 +1042,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [scvtf]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1058,7 +1078,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ucvtf]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -1130,7 +1151,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ucvtf, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1162,7 +1184,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtzs, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1194,7 +1217,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtzu, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1253,7 +1277,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [scvtf, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1507,7 +1532,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [dup, 'N = 4']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1546,7 +1572,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [dup, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1768,7 +1795,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ext, 'N = 3']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -1787,7 +1815,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ext, 'N = 7']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ['const N: i32']
     safety: safe
@@ -2237,7 +2266,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vneg.{type[1]}"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fneg]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -2501,7 +2531,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrintn]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frintn]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -6368,7 +6399,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vmul.{type[0]}"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmul]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -6418,7 +6450,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmul, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     static_defs: ["const LANE: i32"]
     safety: safe
@@ -6622,7 +6655,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vfma]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmla]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -6732,7 +6766,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vsub.{type[0]}"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fsub]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -6751,7 +6786,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vadd.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fadd]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -7253,7 +7289,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmax]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmax]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -7296,7 +7333,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmaxnm]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmaxnm]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -7315,7 +7353,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vminnm]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fminnm]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -7402,7 +7441,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmin]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmin]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -7467,7 +7507,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vpadd]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [faddp]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8311,7 +8352,8 @@ intrinsics:
       - *neon-fp16
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrsqrts]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frsqrts]]}]]
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8360,7 +8402,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrecpe]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frecpe]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8409,7 +8452,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrecps]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frecps]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8742,7 +8786,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8805,7 +8850,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -8828,7 +8874,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrev64]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [rev64]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -9144,7 +9191,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -9650,7 +9698,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn1]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn2]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -9806,7 +9855,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -9877,7 +9927,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp1]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp2]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -10456,7 +10507,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcge.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmge]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -10475,7 +10527,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcge.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmge]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -10715,7 +10768,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtzu]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -10735,7 +10789,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtn]]}]]
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -10752,7 +10807,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtl]]}]]
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11227,7 +11283,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vcgt.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmgt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11246,7 +11303,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vclt.f16"']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcmlt]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11359,7 +11417,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmls]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11475,7 +11534,8 @@ intrinsics:
       - *neon-fp16
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrsqrte]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frsqrte]]}]]
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11589,7 +11649,8 @@ intrinsics:
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcvt]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fcvtzs]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:
@@ -11839,7 +11900,7 @@ intrinsics:
       - *enable-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-arm-unstable
       - *target-not-arm64ec
     safety:
       unsafe: [neon]
@@ -13784,7 +13845,7 @@ intrinsics:
       - *target-is-arm
       - *neon-v7
       - *neon-fp16
-      - *neon-unstable-f16
+      - *neon-arm-unstable
       - *target-not-arm64ec
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vst1.{type[4]}"']]}]]
     types:
@@ -14060,7 +14121,8 @@ intrinsics:
     attr:
       - *neon-v7
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     assert_instr: [nop]
     safety: safe
@@ -14076,7 +14138,8 @@ intrinsics:
     attr:
       - *neon-v7
       - *arm-fp16
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     assert_instr: [nop]
     safety: safe
@@ -14731,7 +14794,8 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vbsl']]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, ['bsl']]}]]
-      - *neon-unstable-f16
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
     types:

From cbb1b659458b65f545747fa7415964354c1820e0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Fri, 26 Dec 2025 21:50:27 +0100
Subject: [PATCH 084/326] x86: remove "unsafe" from tests that do not need it

Some test utility functions (e.g., `assert_eq_m128`) have been refactored so they are not unsafe. Many test functions (`test_mm_*`) do not call any unsafe function (besides needing target features) anymore, so they do not need to be `unsafe fn`.
---
 crates/core_arch/src/x86/abm.rs             |    4 +-
 crates/core_arch/src/x86/aes.rs             |   12 +-
 crates/core_arch/src/x86/avx.rs             |  304 +--
 crates/core_arch/src/x86/avx2.rs            |  294 +--
 crates/core_arch/src/x86/avx512bf16.rs      |   22 +-
 crates/core_arch/src/x86/avx512bitalg.rs    |   48 +-
 crates/core_arch/src/x86/avx512bw.rs        | 1558 ++++++------
 crates/core_arch/src/x86/avx512cd.rs        |   84 +-
 crates/core_arch/src/x86/avx512dq.rs        |  786 +++---
 crates/core_arch/src/x86/avx512f.rs         | 2546 +++++++++----------
 crates/core_arch/src/x86/avx512fp16.rs      | 1806 ++++++-------
 crates/core_arch/src/x86/avx512ifma.rs      |   44 +-
 crates/core_arch/src/x86/avx512vbmi.rs      |   60 +-
 crates/core_arch/src/x86/avx512vbmi2.rs     |  264 +-
 crates/core_arch/src/x86/avx512vnni.rs      |  136 +-
 crates/core_arch/src/x86/avx512vpopcntdq.rs |   36 +-
 crates/core_arch/src/x86/bmi1.rs            |   14 +-
 crates/core_arch/src/x86/bmi2.rs            |    8 +-
 crates/core_arch/src/x86/f16c.rs            |    8 +-
 crates/core_arch/src/x86/fma.rs             |   64 +-
 crates/core_arch/src/x86/pclmulqdq.rs       |    2 +-
 crates/core_arch/src/x86/sha.rs             |   90 +-
 crates/core_arch/src/x86/sse.rs             |   90 +-
 crates/core_arch/src/x86/sse2.rs            |  448 ++--
 crates/core_arch/src/x86/sse3.rs            |   18 +-
 crates/core_arch/src/x86/sse41.rs           |  118 +-
 crates/core_arch/src/x86/sse42.rs           |   49 +-
 crates/core_arch/src/x86/sse4a.rs           |    8 +-
 crates/core_arch/src/x86/ssse3.rs           |   32 +-
 crates/core_arch/src/x86/tbm.rs             |   20 +-
 crates/core_arch/src/x86/test.rs            |  247 +-
 crates/core_arch/src/x86/vaes.rs            |   34 +-
 crates/core_arch/src/x86/vpclmulqdq.rs      |   16 +-
 crates/core_arch/src/x86_64/abm.rs          |    4 +-
 crates/core_arch/src/x86_64/avx.rs          |    4 +-
 crates/core_arch/src/x86_64/avx512bw.rs     |    4 +-
 crates/core_arch/src/x86_64/avx512f.rs      | 2130 ++++++++--------
 crates/core_arch/src/x86_64/avx512fp16.rs   |   24 +-
 crates/core_arch/src/x86_64/bmi.rs          |   12 +-
 crates/core_arch/src/x86_64/bmi2.rs         |    8 +-
 crates/core_arch/src/x86_64/sse.rs          |    6 +-
 crates/core_arch/src/x86_64/sse2.rs         |   14 +-
 crates/core_arch/src/x86_64/sse41.rs        |    4 +-
 crates/core_arch/src/x86_64/sse42.rs        |    2 +-
 crates/core_arch/src/x86_64/tbm.rs          |   20 +-
 45 files changed, 5700 insertions(+), 5802 deletions(-)

diff --git a/crates/core_arch/src/x86/abm.rs b/crates/core_arch/src/x86/abm.rs
index b73076361d..078c0c5980 100644
--- a/crates/core_arch/src/x86/abm.rs
+++ b/crates/core_arch/src/x86/abm.rs
@@ -54,12 +54,12 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "lzcnt")]
-    const unsafe fn test_lzcnt_u32() {
+    const fn test_lzcnt_u32() {
         assert_eq!(_lzcnt_u32(0b0101_1010), 25);
     }
 
     #[simd_test(enable = "popcnt")]
-    const unsafe fn test_popcnt32() {
+    const fn test_popcnt32() {
         assert_eq!(_popcnt32(0b0101_1010), 4);
     }
 }
diff --git a/crates/core_arch/src/x86/aes.rs b/crates/core_arch/src/x86/aes.rs
index be01d6ddd8..d07ab4dc2a 100644
--- a/crates/core_arch/src/x86/aes.rs
+++ b/crates/core_arch/src/x86/aes.rs
@@ -112,7 +112,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "aes")]
-    unsafe fn test_mm_aesdec_si128() {
+    fn test_mm_aesdec_si128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664949.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
@@ -122,7 +122,7 @@ mod tests {
     }
 
     #[simd_test(enable = "aes")]
-    unsafe fn test_mm_aesdeclast_si128() {
+    fn test_mm_aesdeclast_si128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714178.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
@@ -132,7 +132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "aes")]
-    unsafe fn test_mm_aesenc_si128() {
+    fn test_mm_aesenc_si128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664810.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
@@ -142,7 +142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "aes")]
-    unsafe fn test_mm_aesenclast_si128() {
+    fn test_mm_aesenclast_si128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714136.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
@@ -152,7 +152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "aes")]
-    unsafe fn test_mm_aesimc_si128() {
+    fn test_mm_aesimc_si128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714195.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let e = _mm_set_epi64x(0xc66c82284ee40aa0, 0x6633441122770055);
@@ -161,7 +161,7 @@ mod tests {
     }
 
     #[simd_test(enable = "aes")]
-    unsafe fn test_mm_aeskeygenassist_si128() {
+    fn test_mm_aeskeygenassist_si128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714138.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let e = _mm_set_epi64x(0x857c266b7c266e85, 0xeac4eea9c4eeacea);
diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index 6d4f79fc7c..94f075894a 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -3364,7 +3364,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_add_pd() {
+    const fn test_mm256_add_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_add_pd(a, b);
@@ -3373,7 +3373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_add_ps() {
+    const fn test_mm256_add_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_add_ps(a, b);
@@ -3382,7 +3382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_and_pd() {
+    const fn test_mm256_and_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(0.6);
         let r = _mm256_and_pd(a, b);
@@ -3391,7 +3391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_and_ps() {
+    const fn test_mm256_and_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(0.6);
         let r = _mm256_and_ps(a, b);
@@ -3400,7 +3400,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_or_pd() {
+    const fn test_mm256_or_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(0.6);
         let r = _mm256_or_pd(a, b);
@@ -3409,7 +3409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_or_ps() {
+    const fn test_mm256_or_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(0.6);
         let r = _mm256_or_ps(a, b);
@@ -3418,7 +3418,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_shuffle_pd() {
+    const fn test_mm256_shuffle_pd() {
         let a = _mm256_setr_pd(1., 4., 5., 8.);
         let b = _mm256_setr_pd(2., 3., 6., 7.);
         let r = _mm256_shuffle_pd::<0b11_11_11_11>(a, b);
@@ -3427,7 +3427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_shuffle_ps() {
+    const fn test_mm256_shuffle_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_shuffle_ps::<0b00_00_11_11>(a, b);
@@ -3436,7 +3436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_andnot_pd() {
+    const fn test_mm256_andnot_pd() {
         let a = _mm256_set1_pd(0.);
         let b = _mm256_set1_pd(0.6);
         let r = _mm256_andnot_pd(a, b);
@@ -3444,7 +3444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_andnot_ps() {
+    const fn test_mm256_andnot_ps() {
         let a = _mm256_set1_ps(0.);
         let b = _mm256_set1_ps(0.6);
         let r = _mm256_andnot_ps(a, b);
@@ -3556,7 +3556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_mul_pd() {
+    const fn test_mm256_mul_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_mul_pd(a, b);
@@ -3565,7 +3565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_mul_ps() {
+    const fn test_mm256_mul_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_mul_ps(a, b);
@@ -3574,7 +3574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_addsub_pd() {
+    const fn test_mm256_addsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_addsub_pd(a, b);
@@ -3583,7 +3583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_addsub_ps() {
+    const fn test_mm256_addsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
         let r = _mm256_addsub_ps(a, b);
@@ -3592,7 +3592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_sub_pd() {
+    const fn test_mm256_sub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_sub_pd(a, b);
@@ -3601,7 +3601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_sub_ps() {
+    const fn test_mm256_sub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., -1., -2., -3., -4.);
         let b = _mm256_setr_ps(5., 6., 7., 8., 3., 2., 1., 0.);
         let r = _mm256_sub_ps(a, b);
@@ -3610,7 +3610,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_round_pd() {
+    fn test_mm256_round_pd() {
         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
         let result_closest = _mm256_round_pd::<0b0000>(a);
         let result_down = _mm256_round_pd::<0b0001>(a);
@@ -3624,7 +3624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_floor_pd() {
+    const fn test_mm256_floor_pd() {
         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
         let result_down = _mm256_floor_pd(a);
         let expected_down = _mm256_setr_pd(1., 2., 3., -2.);
@@ -3632,7 +3632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_ceil_pd() {
+    const fn test_mm256_ceil_pd() {
         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
         let result_up = _mm256_ceil_pd(a);
         let expected_up = _mm256_setr_pd(2., 3., 4., -1.);
@@ -3640,7 +3640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_round_ps() {
+    fn test_mm256_round_ps() {
         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
         let result_closest = _mm256_round_ps::<0b0000>(a);
         let result_down = _mm256_round_ps::<0b0001>(a);
@@ -3654,7 +3654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_floor_ps() {
+    const fn test_mm256_floor_ps() {
         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
         let result_down = _mm256_floor_ps(a);
         let expected_down = _mm256_setr_ps(1., 2., 3., -2., 1., 2., 3., -2.);
@@ -3662,7 +3662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_ceil_ps() {
+    const fn test_mm256_ceil_ps() {
         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
         let result_up = _mm256_ceil_ps(a);
         let expected_up = _mm256_setr_ps(2., 3., 4., -1., 2., 3., 4., -1.);
@@ -3670,7 +3670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_sqrt_pd() {
+    fn test_mm256_sqrt_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let r = _mm256_sqrt_pd(a);
         let e = _mm256_setr_pd(2., 3., 4., 5.);
@@ -3678,7 +3678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_sqrt_ps() {
+    fn test_mm256_sqrt_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let r = _mm256_sqrt_ps(a);
         let e = _mm256_setr_ps(2., 3., 4., 5., 2., 3., 4., 5.);
@@ -3686,7 +3686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_div_ps() {
+    const fn test_mm256_div_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_div_ps(a, b);
@@ -3695,7 +3695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_div_pd() {
+    const fn test_mm256_div_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_div_pd(a, b);
@@ -3704,7 +3704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_blend_pd() {
+    const fn test_mm256_blend_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_blend_pd::<0x0>(a, b);
@@ -3716,7 +3716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_blend_ps() {
+    const fn test_mm256_blend_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_blend_ps::<0x0>(a, b);
@@ -3728,7 +3728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_blendv_pd() {
+    const fn test_mm256_blendv_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let c = _mm256_setr_pd(0., 0., !0 as f64, !0 as f64);
@@ -3738,7 +3738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_blendv_ps() {
+    const fn test_mm256_blendv_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         #[rustfmt::skip]
@@ -3751,7 +3751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_dp_ps() {
+    fn test_mm256_dp_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_dp_ps::<0xFF>(a, b);
@@ -3760,7 +3760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_hadd_pd() {
+    const fn test_mm256_hadd_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_hadd_pd(a, b);
@@ -3775,7 +3775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_hadd_ps() {
+    const fn test_mm256_hadd_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_hadd_ps(a, b);
@@ -3790,7 +3790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_hsub_pd() {
+    const fn test_mm256_hsub_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_hsub_pd(a, b);
@@ -3805,7 +3805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_hsub_ps() {
+    const fn test_mm256_hsub_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_hsub_ps(a, b);
@@ -3820,7 +3820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_xor_pd() {
+    const fn test_mm256_xor_pd() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let b = _mm256_set1_pd(0.);
         let r = _mm256_xor_pd(a, b);
@@ -3828,7 +3828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_xor_ps() {
+    const fn test_mm256_xor_ps() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let b = _mm256_set1_ps(0.);
         let r = _mm256_xor_ps(a, b);
@@ -3836,7 +3836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_cmp_pd() {
+    fn test_mm_cmp_pd() {
         let a = _mm_setr_pd(4., 9.);
         let b = _mm_setr_pd(4., 3.);
         let r = _mm_cmp_pd::<_CMP_GE_OS>(a, b);
@@ -3845,7 +3845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cmp_pd() {
+    fn test_mm256_cmp_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_cmp_pd::<_CMP_GE_OS>(a, b);
@@ -3854,7 +3854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_cmp_ps() {
+    fn test_mm_cmp_ps() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let b = _mm_setr_ps(4., 9., 16., 25.);
         let r = _mm_cmp_ps::<_CMP_GE_OS>(a, b);
@@ -3865,7 +3865,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cmp_ps() {
+    fn test_mm256_cmp_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
         let r = _mm256_cmp_ps::<_CMP_GE_OS>(a, b);
@@ -3874,7 +3874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_cmp_sd() {
+    fn test_mm_cmp_sd() {
         let a = _mm_setr_pd(4., 9.);
         let b = _mm_setr_pd(4., 3.);
         let r = _mm_cmp_sd::<_CMP_GE_OS>(a, b);
@@ -3883,7 +3883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_cmp_ss() {
+    fn test_mm_cmp_ss() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let b = _mm_setr_ps(4., 9., 16., 25.);
         let r = _mm_cmp_ss::<_CMP_GE_OS>(a, b);
@@ -3894,7 +3894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtepi32_pd() {
+    const fn test_mm256_cvtepi32_pd() {
         let a = _mm_setr_epi32(4, 9, 16, 25);
         let r = _mm256_cvtepi32_pd(a);
         let e = _mm256_setr_pd(4., 9., 16., 25.);
@@ -3902,7 +3902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtepi32_ps() {
+    const fn test_mm256_cvtepi32_ps() {
         let a = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
         let r = _mm256_cvtepi32_ps(a);
         let e = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
@@ -3910,7 +3910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtpd_ps() {
+    const fn test_mm256_cvtpd_ps() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let r = _mm256_cvtpd_ps(a);
         let e = _mm_setr_ps(4., 9., 16., 25.);
@@ -3918,7 +3918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtps_epi32() {
+    fn test_mm256_cvtps_epi32() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let r = _mm256_cvtps_epi32(a);
         let e = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
@@ -3926,7 +3926,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtps_pd() {
+    const fn test_mm256_cvtps_pd() {
         let a = _mm_setr_ps(4., 9., 16., 25.);
         let r = _mm256_cvtps_pd(a);
         let e = _mm256_setr_pd(4., 9., 16., 25.);
@@ -3934,14 +3934,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtsd_f64() {
+    const fn test_mm256_cvtsd_f64() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_cvtsd_f64(a);
         assert_eq!(r, 1.);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvttpd_epi32() {
+    fn test_mm256_cvttpd_epi32() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let r = _mm256_cvttpd_epi32(a);
         let e = _mm_setr_epi32(4, 9, 16, 25);
@@ -3949,7 +3949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvtpd_epi32() {
+    fn test_mm256_cvtpd_epi32() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
         let r = _mm256_cvtpd_epi32(a);
         let e = _mm_setr_epi32(4, 9, 16, 25);
@@ -3957,7 +3957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_cvttps_epi32() {
+    fn test_mm256_cvttps_epi32() {
         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
         let r = _mm256_cvttps_epi32(a);
         let e = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
@@ -3965,7 +3965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_extractf128_ps() {
+    const fn test_mm256_extractf128_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_extractf128_ps::<0>(a);
         let e = _mm_setr_ps(4., 3., 2., 5.);
@@ -3973,7 +3973,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_extractf128_pd() {
+    const fn test_mm256_extractf128_pd() {
         let a = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_extractf128_pd::<0>(a);
         let e = _mm_setr_pd(4., 3.);
@@ -3981,7 +3981,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_extractf128_si256() {
+    const fn test_mm256_extractf128_si256() {
         let a = _mm256_setr_epi64x(4, 3, 2, 5);
         let r = _mm256_extractf128_si256::<0>(a);
         let e = _mm_setr_epi64x(4, 3);
@@ -3989,7 +3989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_extract_epi32() {
+    const fn test_mm256_extract_epi32() {
         let a = _mm256_setr_epi32(-1, 1, 2, 3, 4, 5, 6, 7);
         let r1 = _mm256_extract_epi32::<0>(a);
         let r2 = _mm256_extract_epi32::<3>(a);
@@ -3998,7 +3998,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtsi256_si32() {
+    const fn test_mm256_cvtsi256_si32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_cvtsi256_si32(a);
         assert_eq!(r, 1);
@@ -4006,18 +4006,18 @@ mod tests {
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri
-    unsafe fn test_mm256_zeroall() {
+    fn test_mm256_zeroall() {
         _mm256_zeroall();
     }
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri
-    unsafe fn test_mm256_zeroupper() {
+    fn test_mm256_zeroupper() {
         _mm256_zeroupper();
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permutevar_ps() {
+    fn test_mm256_permutevar_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_permutevar_ps(a, b);
@@ -4026,7 +4026,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_permutevar_ps() {
+    fn test_mm_permutevar_ps() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let b = _mm_setr_epi32(1, 2, 3, 4);
         let r = _mm_permutevar_ps(a, b);
@@ -4035,7 +4035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_permute_ps() {
+    const fn test_mm256_permute_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let r = _mm256_permute_ps::<0x1b>(a);
         let e = _mm256_setr_ps(5., 2., 3., 4., 50., 64., 9., 8.);
@@ -4043,7 +4043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_permute_ps() {
+    const fn test_mm_permute_ps() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let r = _mm_permute_ps::<0x1b>(a);
         let e = _mm_setr_ps(5., 2., 3., 4.);
@@ -4051,7 +4051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_permutevar_pd() {
+    fn test_mm256_permutevar_pd() {
         let a = _mm256_setr_pd(4., 3., 2., 5.);
         let b = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_permutevar_pd(a, b);
@@ -4060,7 +4060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_permutevar_pd() {
+    fn test_mm_permutevar_pd() {
         let a = _mm_setr_pd(4., 3.);
         let b = _mm_setr_epi64x(3, 0);
         let r = _mm_permutevar_pd(a, b);
@@ -4069,7 +4069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_permute_pd() {
+    const fn test_mm256_permute_pd() {
         let a = _mm256_setr_pd(4., 3., 2., 5.);
         let r = _mm256_permute_pd::<5>(a);
         let e = _mm256_setr_pd(3., 4., 5., 2.);
@@ -4077,7 +4077,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_permute_pd() {
+    const fn test_mm_permute_pd() {
         let a = _mm_setr_pd(4., 3.);
         let r = _mm_permute_pd::<1>(a);
         let e = _mm_setr_pd(3., 4.);
@@ -4085,7 +4085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_permute2f128_ps() {
+    const fn test_mm256_permute2f128_ps() {
         let a = _mm256_setr_ps(11., 12., 13., 14., 15., 16., 17., 18.);
         let b = _mm256_setr_ps(21., 22., 23., 24., 25., 26., 27., 28.);
         let r = _mm256_permute2f128_ps::<0b0001_0011>(a, b);
@@ -4099,7 +4099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_permute2f128_pd() {
+    const fn test_mm256_permute2f128_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_permute2f128_pd::<0b0011_0001>(a, b);
@@ -4113,7 +4113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_permute2f128_si256() {
+    const fn test_mm256_permute2f128_si256() {
         let a = _mm256_setr_epi32(11, 12, 13, 14, 15, 16, 17, 18);
         let b = _mm256_setr_epi32(21, 22, 23, 24, 25, 26, 27, 28);
         let r = _mm256_permute2f128_si256::<0b0010_0000>(a, b);
@@ -4127,28 +4127,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_broadcast_ss() {
+    const fn test_mm256_broadcast_ss() {
         let r = _mm256_broadcast_ss(&3.);
         let e = _mm256_set1_ps(3.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_broadcast_ss() {
+    const fn test_mm_broadcast_ss() {
         let r = _mm_broadcast_ss(&3.);
         let e = _mm_set1_ps(3.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_broadcast_sd() {
+    const fn test_mm256_broadcast_sd() {
         let r = _mm256_broadcast_sd(&3.);
         let e = _mm256_set1_pd(3.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_broadcast_ps() {
+    const fn test_mm256_broadcast_ps() {
         let a = _mm_setr_ps(4., 3., 2., 5.);
         let r = _mm256_broadcast_ps(&a);
         let e = _mm256_setr_ps(4., 3., 2., 5., 4., 3., 2., 5.);
@@ -4156,7 +4156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_broadcast_pd() {
+    const fn test_mm256_broadcast_pd() {
         let a = _mm_setr_pd(4., 3.);
         let r = _mm256_broadcast_pd(&a);
         let e = _mm256_setr_pd(4., 3., 4., 3.);
@@ -4164,7 +4164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insertf128_ps() {
+    const fn test_mm256_insertf128_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let b = _mm_setr_ps(4., 9., 16., 25.);
         let r = _mm256_insertf128_ps::<0>(a, b);
@@ -4173,7 +4173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insertf128_pd() {
+    const fn test_mm256_insertf128_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm256_insertf128_pd::<0>(a, b);
@@ -4182,7 +4182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insertf128_si256() {
+    const fn test_mm256_insertf128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm_setr_epi64x(5, 6);
         let r = _mm256_insertf128_si256::<0>(a, b);
@@ -4191,7 +4191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insert_epi8() {
+    const fn test_mm256_insert_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4211,7 +4211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insert_epi16() {
+    const fn test_mm256_insert_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4227,7 +4227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insert_epi32() {
+    const fn test_mm256_insert_epi32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_insert_epi32::<7>(a, 0);
         let e = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
@@ -4417,7 +4417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_movehdup_ps() {
+    const fn test_mm256_movehdup_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_movehdup_ps(a);
         let e = _mm256_setr_ps(2., 2., 4., 4., 6., 6., 8., 8.);
@@ -4425,7 +4425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_moveldup_ps() {
+    const fn test_mm256_moveldup_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_moveldup_ps(a);
         let e = _mm256_setr_ps(1., 1., 3., 3., 5., 5., 7., 7.);
@@ -4433,7 +4433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_movedup_pd() {
+    const fn test_mm256_movedup_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_movedup_pd(a);
         let e = _mm256_setr_pd(1., 1., 3., 3.);
@@ -4506,7 +4506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_rcp_ps() {
+    fn test_mm256_rcp_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_rcp_ps(a);
         #[rustfmt::skip]
@@ -4521,7 +4521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_rsqrt_ps() {
+    fn test_mm256_rsqrt_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_rsqrt_ps(a);
         #[rustfmt::skip]
@@ -4536,7 +4536,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_unpackhi_pd() {
+    const fn test_mm256_unpackhi_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_unpackhi_pd(a, b);
@@ -4545,7 +4545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_unpackhi_ps() {
+    const fn test_mm256_unpackhi_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_unpackhi_ps(a, b);
@@ -4554,7 +4554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_unpacklo_pd() {
+    const fn test_mm256_unpacklo_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_unpacklo_pd(a, b);
@@ -4563,7 +4563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_unpacklo_ps() {
+    const fn test_mm256_unpacklo_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm256_unpacklo_ps(a, b);
@@ -4572,7 +4572,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_testz_si256() {
+    const fn test_mm256_testz_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm256_setr_epi64x(5, 6, 7, 8);
         let r = _mm256_testz_si256(a, b);
@@ -4583,7 +4583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_testc_si256() {
+    const fn test_mm256_testc_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm256_setr_epi64x(5, 6, 7, 8);
         let r = _mm256_testc_si256(a, b);
@@ -4594,7 +4594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testnzc_si256() {
+    fn test_mm256_testnzc_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm256_setr_epi64x(5, 6, 7, 8);
         let r = _mm256_testnzc_si256(a, b);
@@ -4606,7 +4606,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testz_pd() {
+    fn test_mm256_testz_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_testz_pd(a, b);
@@ -4617,7 +4617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testc_pd() {
+    fn test_mm256_testc_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_testc_pd(a, b);
@@ -4629,7 +4629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testnzc_pd() {
+    fn test_mm256_testnzc_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 6., 7., 8.);
         let r = _mm256_testnzc_pd(a, b);
@@ -4641,7 +4641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_testz_pd() {
+    const fn test_mm_testz_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm_testz_pd(a, b);
@@ -4652,7 +4652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_testc_pd() {
+    const fn test_mm_testc_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm_testc_pd(a, b);
@@ -4664,7 +4664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_testnzc_pd() {
+    fn test_mm_testnzc_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 6.);
         let r = _mm_testnzc_pd(a, b);
@@ -4676,7 +4676,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testz_ps() {
+    fn test_mm256_testz_ps() {
         let a = _mm256_set1_ps(1.);
         let r = _mm256_testz_ps(a, a);
         assert_eq!(r, 1);
@@ -4686,7 +4686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testc_ps() {
+    fn test_mm256_testc_ps() {
         let a = _mm256_set1_ps(1.);
         let r = _mm256_testc_ps(a, a);
         assert_eq!(r, 1);
@@ -4696,7 +4696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_testnzc_ps() {
+    fn test_mm256_testnzc_ps() {
         let a = _mm256_set1_ps(1.);
         let r = _mm256_testnzc_ps(a, a);
         assert_eq!(r, 0);
@@ -4707,7 +4707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_testz_ps() {
+    const fn test_mm_testz_ps() {
         let a = _mm_set1_ps(1.);
         let r = _mm_testz_ps(a, a);
         assert_eq!(r, 1);
@@ -4717,7 +4717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_testc_ps() {
+    const fn test_mm_testc_ps() {
         let a = _mm_set1_ps(1.);
         let r = _mm_testc_ps(a, a);
         assert_eq!(r, 1);
@@ -4727,7 +4727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm_testnzc_ps() {
+    fn test_mm_testnzc_ps() {
         let a = _mm_set1_ps(1.);
         let r = _mm_testnzc_ps(a, a);
         assert_eq!(r, 0);
@@ -4738,51 +4738,51 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_movemask_pd() {
+    const fn test_mm256_movemask_pd() {
         let a = _mm256_setr_pd(1., -2., 3., -4.);
         let r = _mm256_movemask_pd(a);
         assert_eq!(r, 0xA);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_movemask_ps() {
+    const fn test_mm256_movemask_ps() {
         let a = _mm256_setr_ps(1., -2., 3., -4., 1., -2., 3., -4.);
         let r = _mm256_movemask_ps(a);
         assert_eq!(r, 0xAA);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setzero_pd() {
+    const fn test_mm256_setzero_pd() {
         let r = _mm256_setzero_pd();
         assert_eq_m256d(r, _mm256_set1_pd(0.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setzero_ps() {
+    const fn test_mm256_setzero_ps() {
         let r = _mm256_setzero_ps();
         assert_eq_m256(r, _mm256_set1_ps(0.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setzero_si256() {
+    const fn test_mm256_setzero_si256() {
         let r = _mm256_setzero_si256();
         assert_eq_m256i(r, _mm256_set1_epi8(0));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_pd() {
+    const fn test_mm256_set_pd() {
         let r = _mm256_set_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, _mm256_setr_pd(4., 3., 2., 1.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_ps() {
+    const fn test_mm256_set_ps() {
         let r = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         assert_eq_m256(r, _mm256_setr_ps(8., 7., 6., 5., 4., 3., 2., 1.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_epi8() {
+    const fn test_mm256_set_epi8() {
         #[rustfmt::skip]
         let r = _mm256_set_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4801,7 +4801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_epi16() {
+    const fn test_mm256_set_epi16() {
         #[rustfmt::skip]
         let r = _mm256_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4816,31 +4816,31 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_epi32() {
+    const fn test_mm256_set_epi32() {
         let r = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         assert_eq_m256i(r, _mm256_setr_epi32(8, 7, 6, 5, 4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_epi64x() {
+    const fn test_mm256_set_epi64x() {
         let r = _mm256_set_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, _mm256_setr_epi64x(4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_pd() {
+    const fn test_mm256_setr_pd() {
         let r = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, _mm256_setr_pd(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_ps() {
+    const fn test_mm256_setr_ps() {
         let r = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         assert_eq_m256(r, _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_epi8() {
+    const fn test_mm256_setr_epi8() {
         #[rustfmt::skip]
         let r = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4860,7 +4860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_epi16() {
+    const fn test_mm256_setr_epi16() {
         #[rustfmt::skip]
         let r = _mm256_setr_epi16(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4875,55 +4875,55 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_epi32() {
+    const fn test_mm256_setr_epi32() {
         let r = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         assert_eq_m256i(r, _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_epi64x() {
+    const fn test_mm256_setr_epi64x() {
         let r = _mm256_setr_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, _mm256_setr_epi64x(1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set1_pd() {
+    const fn test_mm256_set1_pd() {
         let r = _mm256_set1_pd(1.);
         assert_eq_m256d(r, _mm256_set1_pd(1.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set1_ps() {
+    const fn test_mm256_set1_ps() {
         let r = _mm256_set1_ps(1.);
         assert_eq_m256(r, _mm256_set1_ps(1.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set1_epi8() {
+    const fn test_mm256_set1_epi8() {
         let r = _mm256_set1_epi8(1);
         assert_eq_m256i(r, _mm256_set1_epi8(1));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set1_epi16() {
+    const fn test_mm256_set1_epi16() {
         let r = _mm256_set1_epi16(1);
         assert_eq_m256i(r, _mm256_set1_epi16(1));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set1_epi32() {
+    const fn test_mm256_set1_epi32() {
         let r = _mm256_set1_epi32(1);
         assert_eq_m256i(r, _mm256_set1_epi32(1));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set1_epi64x() {
+    const fn test_mm256_set1_epi64x() {
         let r = _mm256_set1_epi64x(1);
         assert_eq_m256i(r, _mm256_set1_epi64x(1));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castpd_ps() {
+    const fn test_mm256_castpd_ps() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_castpd_ps(a);
         let e = _mm256_setr_ps(0., 1.875, 0., 2., 0., 2.125, 0., 2.25);
@@ -4931,7 +4931,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castps_pd() {
+    const fn test_mm256_castps_pd() {
         let a = _mm256_setr_ps(0., 1.875, 0., 2., 0., 2.125, 0., 2.25);
         let r = _mm256_castps_pd(a);
         let e = _mm256_setr_pd(1., 2., 3., 4.);
@@ -4939,7 +4939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castps_si256() {
+    const fn test_mm256_castps_si256() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_castps_si256(a);
         #[rustfmt::skip]
@@ -4953,7 +4953,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castsi256_ps() {
+    const fn test_mm256_castsi256_ps() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 0, -128, 63, 0, 0, 0, 64,
@@ -4967,63 +4967,63 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castpd_si256() {
+    const fn test_mm256_castpd_si256() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_castpd_si256(a);
-        assert_eq_m256d(transmute(r), a);
+        assert_eq_m256d(unsafe { transmute(r) }, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castsi256_pd() {
+    const fn test_mm256_castsi256_pd() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_castsi256_pd(a);
-        assert_eq_m256d(r, transmute(a));
+        assert_eq_m256d(r, unsafe { transmute(a) });
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castps256_ps128() {
+    const fn test_mm256_castps256_ps128() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_castps256_ps128(a);
         assert_eq_m128(r, _mm_setr_ps(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castpd256_pd128() {
+    const fn test_mm256_castpd256_pd128() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_castpd256_pd128(a);
         assert_eq_m128d(r, _mm_setr_pd(1., 2.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castsi256_si128() {
+    const fn test_mm256_castsi256_si128() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_castsi256_si128(a);
         assert_eq_m128i(r, _mm_setr_epi64x(1, 2));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castps128_ps256() {
+    const fn test_mm256_castps128_ps256() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let r = _mm256_castps128_ps256(a);
         assert_eq_m128(_mm256_castps256_ps128(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castpd128_pd256() {
+    const fn test_mm256_castpd128_pd256() {
         let a = _mm_setr_pd(1., 2.);
         let r = _mm256_castpd128_pd256(a);
         assert_eq_m128d(_mm256_castpd256_pd128(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_castsi128_si256() {
+    const fn test_mm256_castsi128_si256() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let r = _mm256_castsi128_si256(a);
         assert_eq_m128i(_mm256_castsi256_si128(r), a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_zextps128_ps256() {
+    const fn test_mm256_zextps128_ps256() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let r = _mm256_zextps128_ps256(a);
         let e = _mm256_setr_ps(1., 2., 3., 4., 0., 0., 0., 0.);
@@ -5031,7 +5031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_zextsi128_si256() {
+    const fn test_mm256_zextsi128_si256() {
         let a = _mm_setr_epi64x(1, 2);
         let r = _mm256_zextsi128_si256(a);
         let e = _mm256_setr_epi64x(1, 2, 0, 0);
@@ -5039,7 +5039,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_zextpd128_pd256() {
+    const fn test_mm256_zextpd128_pd256() {
         let a = _mm_setr_pd(1., 2.);
         let r = _mm256_zextpd128_pd256(a);
         let e = _mm256_setr_pd(1., 2., 0., 0.);
@@ -5047,7 +5047,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_m128() {
+    const fn test_mm256_set_m128() {
         let hi = _mm_setr_ps(5., 6., 7., 8.);
         let lo = _mm_setr_ps(1., 2., 3., 4.);
         let r = _mm256_set_m128(hi, lo);
@@ -5056,7 +5056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_m128d() {
+    const fn test_mm256_set_m128d() {
         let hi = _mm_setr_pd(3., 4.);
         let lo = _mm_setr_pd(1., 2.);
         let r = _mm256_set_m128d(hi, lo);
@@ -5065,7 +5065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_set_m128i() {
+    const fn test_mm256_set_m128i() {
         #[rustfmt::skip]
         let hi = _mm_setr_epi8(
             17, 18, 19, 20,
@@ -5092,7 +5092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_m128() {
+    const fn test_mm256_setr_m128() {
         let lo = _mm_setr_ps(1., 2., 3., 4.);
         let hi = _mm_setr_ps(5., 6., 7., 8.);
         let r = _mm256_setr_m128(lo, hi);
@@ -5101,7 +5101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_m128d() {
+    const fn test_mm256_setr_m128d() {
         let lo = _mm_setr_pd(1., 2.);
         let hi = _mm_setr_pd(3., 4.);
         let r = _mm256_setr_m128d(lo, hi);
@@ -5110,7 +5110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_setr_m128i() {
+    const fn test_mm256_setr_m128i() {
         #[rustfmt::skip]
         let lo = _mm_setr_epi8(
             1, 2, 3, 4,
@@ -5235,7 +5235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_cvtss_f32() {
+    const fn test_mm256_cvtss_f32() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_cvtss_f32(a);
         assert_eq!(r, 1.);
diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index a297544e9e..740b09d116 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -3914,7 +3914,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_abs_epi32() {
+    const fn test_mm256_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -3930,7 +3930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_abs_epi16() {
+    const fn test_mm256_abs_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0,  1, -1, 2, -2, 3, -3, 4,
@@ -3946,7 +3946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_abs_epi8() {
+    const fn test_mm256_abs_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, -1, 2, -2, 3, -3, 4,
@@ -3966,7 +3966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_add_epi64() {
+    const fn test_mm256_add_epi64() {
         let a = _mm256_setr_epi64x(-10, 0, 100, 1_000_000_000);
         let b = _mm256_setr_epi64x(-1, 0, 1, 2);
         let r = _mm256_add_epi64(a, b);
@@ -3975,7 +3975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_add_epi32() {
+    const fn test_mm256_add_epi32() {
         let a = _mm256_setr_epi32(-1, 0, 1, 2, 3, 4, 5, 6);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_add_epi32(a, b);
@@ -3984,7 +3984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_add_epi16() {
+    const fn test_mm256_add_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4005,7 +4005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_add_epi8() {
+    const fn test_mm256_add_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4032,7 +4032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_adds_epi8() {
+    const fn test_mm256_adds_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4059,7 +4059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epi8_saturate_positive() {
+    fn test_mm256_adds_epi8_saturate_positive() {
         let a = _mm256_set1_epi8(0x7F);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_adds_epi8(a, b);
@@ -4067,7 +4067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epi8_saturate_negative() {
+    fn test_mm256_adds_epi8_saturate_negative() {
         let a = _mm256_set1_epi8(-0x80);
         let b = _mm256_set1_epi8(-1);
         let r = _mm256_adds_epi8(a, b);
@@ -4075,7 +4075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_adds_epi16() {
+    const fn test_mm256_adds_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4097,7 +4097,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epi16_saturate_positive() {
+    fn test_mm256_adds_epi16_saturate_positive() {
         let a = _mm256_set1_epi16(0x7FFF);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_adds_epi16(a, b);
@@ -4105,7 +4105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epi16_saturate_negative() {
+    fn test_mm256_adds_epi16_saturate_negative() {
         let a = _mm256_set1_epi16(-0x8000);
         let b = _mm256_set1_epi16(-1);
         let r = _mm256_adds_epi16(a, b);
@@ -4113,7 +4113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_adds_epu8() {
+    const fn test_mm256_adds_epu8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4140,7 +4140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epu8_saturate() {
+    fn test_mm256_adds_epu8_saturate() {
         let a = _mm256_set1_epi8(!0);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_adds_epu8(a, b);
@@ -4148,7 +4148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_adds_epu16() {
+    const fn test_mm256_adds_epu16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4170,7 +4170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_adds_epu16_saturate() {
+    fn test_mm256_adds_epu16_saturate() {
         let a = _mm256_set1_epi16(!0);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_adds_epu16(a, b);
@@ -4178,7 +4178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_and_si256() {
+    const fn test_mm256_and_si256() {
         let a = _mm256_set1_epi8(5);
         let b = _mm256_set1_epi8(3);
         let got = _mm256_and_si256(a, b);
@@ -4186,7 +4186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_andnot_si256() {
+    const fn test_mm256_andnot_si256() {
         let a = _mm256_set1_epi8(5);
         let b = _mm256_set1_epi8(3);
         let got = _mm256_andnot_si256(a, b);
@@ -4194,21 +4194,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_avg_epu8() {
+    const fn test_mm256_avg_epu8() {
         let (a, b) = (_mm256_set1_epi8(3), _mm256_set1_epi8(9));
         let r = _mm256_avg_epu8(a, b);
         assert_eq_m256i(r, _mm256_set1_epi8(6));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_avg_epu16() {
+    const fn test_mm256_avg_epu16() {
         let (a, b) = (_mm256_set1_epi16(3), _mm256_set1_epi16(9));
         let r = _mm256_avg_epu16(a, b);
         assert_eq_m256i(r, _mm256_set1_epi16(6));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_blend_epi32() {
+    const fn test_mm_blend_epi32() {
         let (a, b) = (_mm_set1_epi32(3), _mm_set1_epi32(9));
         let e = _mm_setr_epi32(9, 3, 3, 3);
         let r = _mm_blend_epi32::<0x01>(a, b);
@@ -4219,7 +4219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_blend_epi32() {
+    const fn test_mm256_blend_epi32() {
         let (a, b) = (_mm256_set1_epi32(3), _mm256_set1_epi32(9));
         let e = _mm256_setr_epi32(9, 3, 3, 3, 3, 3, 3, 3);
         let r = _mm256_blend_epi32::<0x01>(a, b);
@@ -4235,7 +4235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_blend_epi16() {
+    const fn test_mm256_blend_epi16() {
         let (a, b) = (_mm256_set1_epi16(3), _mm256_set1_epi16(9));
         let e = _mm256_setr_epi16(9, 3, 3, 3, 3, 3, 3, 3, 9, 3, 3, 3, 3, 3, 3, 3);
         let r = _mm256_blend_epi16::<0x01>(a, b);
@@ -4246,7 +4246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_blendv_epi8() {
+    const fn test_mm256_blendv_epi8() {
         let (a, b) = (_mm256_set1_epi8(4), _mm256_set1_epi8(2));
         let mask = _mm256_insert_epi8::<2>(_mm256_set1_epi8(0), -1);
         let e = _mm256_insert_epi8::<2>(_mm256_set1_epi8(4), 2);
@@ -4255,63 +4255,63 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastb_epi8() {
+    const fn test_mm_broadcastb_epi8() {
         let a = _mm_insert_epi8::<0>(_mm_set1_epi8(0x00), 0x2a);
         let res = _mm_broadcastb_epi8(a);
         assert_eq_m128i(res, _mm_set1_epi8(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastb_epi8() {
+    const fn test_mm256_broadcastb_epi8() {
         let a = _mm_insert_epi8::<0>(_mm_set1_epi8(0x00), 0x2a);
         let res = _mm256_broadcastb_epi8(a);
         assert_eq_m256i(res, _mm256_set1_epi8(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastd_epi32() {
+    const fn test_mm_broadcastd_epi32() {
         let a = _mm_setr_epi32(0x2a, 0x8000000, 0, 0);
         let res = _mm_broadcastd_epi32(a);
         assert_eq_m128i(res, _mm_set1_epi32(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastd_epi32() {
+    const fn test_mm256_broadcastd_epi32() {
         let a = _mm_setr_epi32(0x2a, 0x8000000, 0, 0);
         let res = _mm256_broadcastd_epi32(a);
         assert_eq_m256i(res, _mm256_set1_epi32(0x2a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastq_epi64() {
+    const fn test_mm_broadcastq_epi64() {
         let a = _mm_setr_epi64x(0x1ffffffff, 0);
         let res = _mm_broadcastq_epi64(a);
         assert_eq_m128i(res, _mm_set1_epi64x(0x1ffffffff));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastq_epi64() {
+    const fn test_mm256_broadcastq_epi64() {
         let a = _mm_setr_epi64x(0x1ffffffff, 0);
         let res = _mm256_broadcastq_epi64(a);
         assert_eq_m256i(res, _mm256_set1_epi64x(0x1ffffffff));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastsd_pd() {
+    const fn test_mm_broadcastsd_pd() {
         let a = _mm_setr_pd(6.88, 3.44);
         let res = _mm_broadcastsd_pd(a);
         assert_eq_m128d(res, _mm_set1_pd(6.88));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastsd_pd() {
+    const fn test_mm256_broadcastsd_pd() {
         let a = _mm_setr_pd(6.88, 3.44);
         let res = _mm256_broadcastsd_pd(a);
         assert_eq_m256d(res, _mm256_set1_pd(6.88f64));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastsi128_si256() {
+    const fn test_mm_broadcastsi128_si256() {
         let a = _mm_setr_epi64x(0x0987654321012334, 0x5678909876543210);
         let res = _mm_broadcastsi128_si256(a);
         let retval = _mm256_setr_epi64x(
@@ -4324,7 +4324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastsi128_si256() {
+    const fn test_mm256_broadcastsi128_si256() {
         let a = _mm_setr_epi64x(0x0987654321012334, 0x5678909876543210);
         let res = _mm256_broadcastsi128_si256(a);
         let retval = _mm256_setr_epi64x(
@@ -4337,35 +4337,35 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastss_ps() {
+    const fn test_mm_broadcastss_ps() {
         let a = _mm_setr_ps(6.88, 3.44, 0.0, 0.0);
         let res = _mm_broadcastss_ps(a);
         assert_eq_m128(res, _mm_set1_ps(6.88));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastss_ps() {
+    const fn test_mm256_broadcastss_ps() {
         let a = _mm_setr_ps(6.88, 3.44, 0.0, 0.0);
         let res = _mm256_broadcastss_ps(a);
         assert_eq_m256(res, _mm256_set1_ps(6.88));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_broadcastw_epi16() {
+    const fn test_mm_broadcastw_epi16() {
         let a = _mm_insert_epi16::<0>(_mm_set1_epi16(0x2a), 0x22b);
         let res = _mm_broadcastw_epi16(a);
         assert_eq_m128i(res, _mm_set1_epi16(0x22b));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_broadcastw_epi16() {
+    const fn test_mm256_broadcastw_epi16() {
         let a = _mm_insert_epi16::<0>(_mm_set1_epi16(0x2a), 0x22b);
         let res = _mm256_broadcastw_epi16(a);
         assert_eq_m256i(res, _mm256_set1_epi16(0x22b));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpeq_epi8() {
+    const fn test_mm256_cmpeq_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4385,7 +4385,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpeq_epi16() {
+    const fn test_mm256_cmpeq_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4401,7 +4401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpeq_epi32() {
+    const fn test_mm256_cmpeq_epi32() {
         let a = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_setr_epi32(7, 6, 2, 4, 3, 2, 1, 0);
         let r = _mm256_cmpeq_epi32(a, b);
@@ -4411,7 +4411,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpeq_epi64() {
+    const fn test_mm256_cmpeq_epi64() {
         let a = _mm256_setr_epi64x(0, 1, 2, 3);
         let b = _mm256_setr_epi64x(3, 2, 2, 0);
         let r = _mm256_cmpeq_epi64(a, b);
@@ -4419,7 +4419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpgt_epi8() {
+    const fn test_mm256_cmpgt_epi8() {
         let a = _mm256_insert_epi8::<0>(_mm256_set1_epi8(0), 5);
         let b = _mm256_set1_epi8(0);
         let r = _mm256_cmpgt_epi8(a, b);
@@ -4427,7 +4427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpgt_epi16() {
+    const fn test_mm256_cmpgt_epi16() {
         let a = _mm256_insert_epi16::<0>(_mm256_set1_epi16(0), 5);
         let b = _mm256_set1_epi16(0);
         let r = _mm256_cmpgt_epi16(a, b);
@@ -4435,7 +4435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpgt_epi32() {
+    const fn test_mm256_cmpgt_epi32() {
         let a = _mm256_insert_epi32::<0>(_mm256_set1_epi32(0), 5);
         let b = _mm256_set1_epi32(0);
         let r = _mm256_cmpgt_epi32(a, b);
@@ -4443,7 +4443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cmpgt_epi64() {
+    const fn test_mm256_cmpgt_epi64() {
         let a = _mm256_insert_epi64::<0>(_mm256_set1_epi64x(0), 5);
         let b = _mm256_set1_epi64x(0);
         let r = _mm256_cmpgt_epi64(a, b);
@@ -4451,7 +4451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepi8_epi16() {
+    const fn test_mm256_cvtepi8_epi16() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 0, -1, 1, -2, 2, -3, 3,
@@ -4466,7 +4466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepi8_epi32() {
+    const fn test_mm256_cvtepi8_epi32() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 0, -1, 1, -2, 2, -3, 3,
@@ -4477,7 +4477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepi8_epi64() {
+    const fn test_mm256_cvtepi8_epi64() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 0, -1, 1, -2, 2, -3, 3,
@@ -4488,49 +4488,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepi16_epi32() {
+    const fn test_mm256_cvtepi16_epi32() {
         let a = _mm_setr_epi16(0, 0, -1, 1, -2, 2, -3, 3);
         let r = _mm256_setr_epi32(0, 0, -1, 1, -2, 2, -3, 3);
         assert_eq_m256i(r, _mm256_cvtepi16_epi32(a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepi16_epi64() {
+    const fn test_mm256_cvtepi16_epi64() {
         let a = _mm_setr_epi16(0, 0, -1, 1, -2, 2, -3, 3);
         let r = _mm256_setr_epi64x(0, 0, -1, 1);
         assert_eq_m256i(r, _mm256_cvtepi16_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepi32_epi64() {
+    const fn test_mm256_cvtepi32_epi64() {
         let a = _mm_setr_epi32(0, 0, -1, 1);
         let r = _mm256_setr_epi64x(0, 0, -1, 1);
         assert_eq_m256i(r, _mm256_cvtepi32_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepu16_epi32() {
+    const fn test_mm256_cvtepu16_epi32() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m256i(r, _mm256_cvtepu16_epi32(a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepu16_epi64() {
+    const fn test_mm256_cvtepu16_epi64() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_setr_epi64x(0, 1, 2, 3);
         assert_eq_m256i(r, _mm256_cvtepu16_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepu32_epi64() {
+    const fn test_mm256_cvtepu32_epi64() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let r = _mm256_setr_epi64x(0, 1, 2, 3);
         assert_eq_m256i(r, _mm256_cvtepu32_epi64(a));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepu8_epi16() {
+    const fn test_mm256_cvtepu8_epi16() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4545,7 +4545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepu8_epi32() {
+    const fn test_mm256_cvtepu8_epi32() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4556,7 +4556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_cvtepu8_epi64() {
+    const fn test_mm256_cvtepu8_epi64() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4567,7 +4567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_extracti128_si256() {
+    const fn test_mm256_extracti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_extracti128_si256::<1>(a);
         let e = _mm_setr_epi64x(3, 4);
@@ -4575,7 +4575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_hadd_epi16() {
+    const fn test_mm256_hadd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_hadd_epi16(a, b);
@@ -4584,7 +4584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_hadd_epi32() {
+    const fn test_mm256_hadd_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_hadd_epi32(a, b);
@@ -4593,7 +4593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_hadds_epi16() {
+    fn test_mm256_hadds_epi16() {
         let a = _mm256_set1_epi16(2);
         let a = _mm256_insert_epi16::<0>(a, 0x7fff);
         let a = _mm256_insert_epi16::<1>(a, 1);
@@ -4608,7 +4608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_hsub_epi16() {
+    const fn test_mm256_hsub_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_hsub_epi16(a, b);
@@ -4617,7 +4617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_hsub_epi32() {
+    const fn test_mm256_hsub_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_hsub_epi32(a, b);
@@ -4626,7 +4626,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_hsubs_epi16() {
+    fn test_mm256_hsubs_epi16() {
         let a = _mm256_set1_epi16(2);
         let a = _mm256_insert_epi16::<0>(a, 0x7fff);
         let a = _mm256_insert_epi16::<1>(a, -1);
@@ -4637,7 +4637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_madd_epi16() {
+    const fn test_mm256_madd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_madd_epi16(a, b);
@@ -4646,7 +4646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_inserti128_si256() {
+    const fn test_mm256_inserti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let b = _mm_setr_epi64x(7, 8);
         let r = _mm256_inserti128_si256::<1>(a, b);
@@ -4655,7 +4655,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_maddubs_epi16() {
+    fn test_mm256_maddubs_epi16() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_maddubs_epi16(a, b);
@@ -4744,7 +4744,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_max_epi16() {
+    const fn test_mm256_max_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_max_epi16(a, b);
@@ -4752,7 +4752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_max_epi32() {
+    const fn test_mm256_max_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_max_epi32(a, b);
@@ -4760,7 +4760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_max_epi8() {
+    const fn test_mm256_max_epi8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_max_epi8(a, b);
@@ -4768,7 +4768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_max_epu16() {
+    const fn test_mm256_max_epu16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_max_epu16(a, b);
@@ -4776,7 +4776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_max_epu32() {
+    const fn test_mm256_max_epu32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_max_epu32(a, b);
@@ -4784,7 +4784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_max_epu8() {
+    const fn test_mm256_max_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_max_epu8(a, b);
@@ -4792,7 +4792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_min_epi16() {
+    const fn test_mm256_min_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_min_epi16(a, b);
@@ -4800,7 +4800,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_min_epi32() {
+    const fn test_mm256_min_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_min_epi32(a, b);
@@ -4808,7 +4808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_min_epi8() {
+    const fn test_mm256_min_epi8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_min_epi8(a, b);
@@ -4816,7 +4816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_min_epu16() {
+    const fn test_mm256_min_epu16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_min_epu16(a, b);
@@ -4824,7 +4824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_min_epu32() {
+    const fn test_mm256_min_epu32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_min_epu32(a, b);
@@ -4832,7 +4832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_min_epu8() {
+    const fn test_mm256_min_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_min_epu8(a, b);
@@ -4840,7 +4840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_movemask_epi8() {
+    const fn test_mm256_movemask_epi8() {
         let a = _mm256_set1_epi8(-1);
         let r = _mm256_movemask_epi8(a);
         let e = -1;
@@ -4848,7 +4848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mpsadbw_epu8() {
+    fn test_mm256_mpsadbw_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_mpsadbw_epu8::<0>(a, b);
@@ -4857,7 +4857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_mul_epi32() {
+    const fn test_mm256_mul_epi32() {
         let a = _mm256_setr_epi32(0, 0, 0, 0, 2, 2, 2, 2);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mul_epi32(a, b);
@@ -4866,7 +4866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_mul_epu32() {
+    const fn test_mm256_mul_epu32() {
         let a = _mm256_setr_epi32(0, 0, 0, 0, 2, 2, 2, 2);
         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mul_epu32(a, b);
@@ -4875,7 +4875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_mulhi_epi16() {
+    const fn test_mm256_mulhi_epi16() {
         let a = _mm256_set1_epi16(6535);
         let b = _mm256_set1_epi16(6535);
         let r = _mm256_mulhi_epi16(a, b);
@@ -4884,7 +4884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_mulhi_epu16() {
+    const fn test_mm256_mulhi_epu16() {
         let a = _mm256_set1_epi16(6535);
         let b = _mm256_set1_epi16(6535);
         let r = _mm256_mulhi_epu16(a, b);
@@ -4893,7 +4893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_mullo_epi16() {
+    const fn test_mm256_mullo_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_mullo_epi16(a, b);
@@ -4902,7 +4902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_mullo_epi32() {
+    const fn test_mm256_mullo_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_mullo_epi32(a, b);
@@ -4911,7 +4911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mulhrs_epi16() {
+    fn test_mm256_mulhrs_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_mullo_epi16(a, b);
@@ -4920,7 +4920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_or_si256() {
+    const fn test_mm256_or_si256() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(0);
         let r = _mm256_or_si256(a, b);
@@ -4928,7 +4928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_packs_epi16() {
+    fn test_mm256_packs_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_packs_epi16(a, b);
@@ -4944,7 +4944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_packs_epi32() {
+    fn test_mm256_packs_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_packs_epi32(a, b);
@@ -4954,7 +4954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_packus_epi16() {
+    fn test_mm256_packus_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_packus_epi16(a, b);
@@ -4970,7 +4970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_packus_epi32() {
+    fn test_mm256_packus_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_packus_epi32(a, b);
@@ -4980,7 +4980,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sad_epu8() {
+    fn test_mm256_sad_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_sad_epu8(a, b);
@@ -4989,7 +4989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_shufflehi_epi16() {
+    const fn test_mm256_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             0, 1, 2, 3, 11, 22, 33, 44,
@@ -5005,7 +5005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_shufflelo_epi16() {
+    const fn test_mm256_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             11, 22, 33, 44, 0, 1, 2, 3,
@@ -5021,7 +5021,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sign_epi16() {
+    fn test_mm256_sign_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(-1);
         let r = _mm256_sign_epi16(a, b);
@@ -5030,7 +5030,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sign_epi32() {
+    fn test_mm256_sign_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_sign_epi32(a, b);
@@ -5039,7 +5039,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sign_epi8() {
+    fn test_mm256_sign_epi8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(-1);
         let r = _mm256_sign_epi8(a, b);
@@ -5048,7 +5048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sll_epi16() {
+    fn test_mm256_sll_epi16() {
         let a = _mm256_set1_epi16(0xFF);
         let b = _mm_insert_epi16::<0>(_mm_set1_epi16(0), 4);
         let r = _mm256_sll_epi16(a, b);
@@ -5056,7 +5056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sll_epi32() {
+    fn test_mm256_sll_epi32() {
         let a = _mm256_set1_epi32(0xFFFF);
         let b = _mm_insert_epi32::<0>(_mm_set1_epi32(0), 4);
         let r = _mm256_sll_epi32(a, b);
@@ -5064,7 +5064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sll_epi64() {
+    fn test_mm256_sll_epi64() {
         let a = _mm256_set1_epi64x(0xFFFFFFFF);
         let b = _mm_insert_epi64::<0>(_mm_set1_epi64x(0), 4);
         let r = _mm256_sll_epi64(a, b);
@@ -5072,7 +5072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_slli_epi16() {
+    const fn test_mm256_slli_epi16() {
         assert_eq_m256i(
             _mm256_slli_epi16::<4>(_mm256_set1_epi16(0xFF)),
             _mm256_set1_epi16(0xFF0),
@@ -5080,7 +5080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_slli_epi32() {
+    const fn test_mm256_slli_epi32() {
         assert_eq_m256i(
             _mm256_slli_epi32::<4>(_mm256_set1_epi32(0xFFFF)),
             _mm256_set1_epi32(0xFFFF0),
@@ -5088,7 +5088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_slli_epi64() {
+    const fn test_mm256_slli_epi64() {
         assert_eq_m256i(
             _mm256_slli_epi64::<4>(_mm256_set1_epi64x(0xFFFFFFFF)),
             _mm256_set1_epi64x(0xFFFFFFFF0),
@@ -5096,14 +5096,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_slli_si256() {
+    const fn test_mm256_slli_si256() {
         let a = _mm256_set1_epi64x(0xFFFFFFFF);
         let r = _mm256_slli_si256::<3>(a);
         assert_eq_m256i(r, _mm256_set1_epi64x(0xFFFFFFFF000000));
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_sllv_epi32() {
+    const fn test_mm_sllv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(1);
         let r = _mm_sllv_epi32(a, b);
@@ -5112,7 +5112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_sllv_epi32() {
+    const fn test_mm256_sllv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_sllv_epi32(a, b);
@@ -5121,7 +5121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_sllv_epi64() {
+    const fn test_mm_sllv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(1);
         let r = _mm_sllv_epi64(a, b);
@@ -5130,7 +5130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_sllv_epi64() {
+    const fn test_mm256_sllv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_sllv_epi64(a, b);
@@ -5139,7 +5139,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sra_epi16() {
+    fn test_mm256_sra_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_sra_epi16(a, b);
@@ -5147,7 +5147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_sra_epi32() {
+    fn test_mm256_sra_epi32() {
         let a = _mm256_set1_epi32(-1);
         let b = _mm_insert_epi32::<0>(_mm_set1_epi32(0), 1);
         let r = _mm256_sra_epi32(a, b);
@@ -5155,7 +5155,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srai_epi16() {
+    const fn test_mm256_srai_epi16() {
         assert_eq_m256i(
             _mm256_srai_epi16::<1>(_mm256_set1_epi16(-1)),
             _mm256_set1_epi16(-1),
@@ -5163,7 +5163,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srai_epi32() {
+    const fn test_mm256_srai_epi32() {
         assert_eq_m256i(
             _mm256_srai_epi32::<1>(_mm256_set1_epi32(-1)),
             _mm256_set1_epi32(-1),
@@ -5171,7 +5171,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_srav_epi32() {
+    const fn test_mm_srav_epi32() {
         let a = _mm_set1_epi32(4);
         let count = _mm_set1_epi32(1);
         let r = _mm_srav_epi32(a, count);
@@ -5180,7 +5180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srav_epi32() {
+    const fn test_mm256_srav_epi32() {
         let a = _mm256_set1_epi32(4);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_srav_epi32(a, count);
@@ -5189,7 +5189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srli_si256() {
+    const fn test_mm256_srli_si256() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5209,7 +5209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srl_epi16() {
+    fn test_mm256_srl_epi16() {
         let a = _mm256_set1_epi16(0xFF);
         let b = _mm_insert_epi16::<0>(_mm_set1_epi16(0), 4);
         let r = _mm256_srl_epi16(a, b);
@@ -5217,7 +5217,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srl_epi32() {
+    fn test_mm256_srl_epi32() {
         let a = _mm256_set1_epi32(0xFFFF);
         let b = _mm_insert_epi32::<0>(_mm_set1_epi32(0), 4);
         let r = _mm256_srl_epi32(a, b);
@@ -5225,7 +5225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_srl_epi64() {
+    fn test_mm256_srl_epi64() {
         let a = _mm256_set1_epi64x(0xFFFFFFFF);
         let b = _mm_setr_epi64x(4, 0);
         let r = _mm256_srl_epi64(a, b);
@@ -5233,7 +5233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srli_epi16() {
+    const fn test_mm256_srli_epi16() {
         assert_eq_m256i(
             _mm256_srli_epi16::<4>(_mm256_set1_epi16(0xFF)),
             _mm256_set1_epi16(0xF),
@@ -5241,7 +5241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srli_epi32() {
+    const fn test_mm256_srli_epi32() {
         assert_eq_m256i(
             _mm256_srli_epi32::<4>(_mm256_set1_epi32(0xFFFF)),
             _mm256_set1_epi32(0xFFF),
@@ -5249,7 +5249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srli_epi64() {
+    const fn test_mm256_srli_epi64() {
         assert_eq_m256i(
             _mm256_srli_epi64::<4>(_mm256_set1_epi64x(0xFFFFFFFF)),
             _mm256_set1_epi64x(0xFFFFFFF),
@@ -5257,7 +5257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_srlv_epi32() {
+    const fn test_mm_srlv_epi32() {
         let a = _mm_set1_epi32(2);
         let count = _mm_set1_epi32(1);
         let r = _mm_srlv_epi32(a, count);
@@ -5266,7 +5266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srlv_epi32() {
+    const fn test_mm256_srlv_epi32() {
         let a = _mm256_set1_epi32(2);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_srlv_epi32(a, count);
@@ -5275,7 +5275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_srlv_epi64() {
+    const fn test_mm_srlv_epi64() {
         let a = _mm_set1_epi64x(2);
         let count = _mm_set1_epi64x(1);
         let r = _mm_srlv_epi64(a, count);
@@ -5284,7 +5284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_srlv_epi64() {
+    const fn test_mm256_srlv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_srlv_epi64(a, count);
@@ -5300,7 +5300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_sub_epi16() {
+    const fn test_mm256_sub_epi16() {
         let a = _mm256_set1_epi16(4);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_sub_epi16(a, b);
@@ -5308,7 +5308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_sub_epi32() {
+    const fn test_mm256_sub_epi32() {
         let a = _mm256_set1_epi32(4);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_sub_epi32(a, b);
@@ -5316,7 +5316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_sub_epi64() {
+    const fn test_mm256_sub_epi64() {
         let a = _mm256_set1_epi64x(4);
         let b = _mm256_set1_epi64x(2);
         let r = _mm256_sub_epi64(a, b);
@@ -5324,7 +5324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_sub_epi8() {
+    const fn test_mm256_sub_epi8() {
         let a = _mm256_set1_epi8(4);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_sub_epi8(a, b);
@@ -5332,7 +5332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_subs_epi16() {
+    const fn test_mm256_subs_epi16() {
         let a = _mm256_set1_epi16(4);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_subs_epi16(a, b);
@@ -5340,7 +5340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_subs_epi8() {
+    const fn test_mm256_subs_epi8() {
         let a = _mm256_set1_epi8(4);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_subs_epi8(a, b);
@@ -5348,7 +5348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_subs_epu16() {
+    const fn test_mm256_subs_epu16() {
         let a = _mm256_set1_epi16(4);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_subs_epu16(a, b);
@@ -5356,7 +5356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_subs_epu8() {
+    const fn test_mm256_subs_epu8() {
         let a = _mm256_set1_epi8(4);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_subs_epu8(a, b);
@@ -5364,7 +5364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_xor_si256() {
+    const fn test_mm256_xor_si256() {
         let a = _mm256_set1_epi8(5);
         let b = _mm256_set1_epi8(3);
         let r = _mm256_xor_si256(a, b);
@@ -5372,7 +5372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_alignr_epi8() {
+    const fn test_mm256_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5428,7 +5428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_shuffle_epi8() {
+    fn test_mm256_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5455,7 +5455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_permutevar8x32_epi32() {
+    fn test_mm256_permutevar8x32_epi32() {
         let a = _mm256_setr_epi32(100, 200, 300, 400, 500, 600, 700, 800);
         let b = _mm256_setr_epi32(5, 0, 5, 1, 7, 6, 3, 4);
         let expected = _mm256_setr_epi32(600, 100, 600, 200, 800, 700, 400, 500);
@@ -5464,7 +5464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_permute4x64_epi64() {
+    const fn test_mm256_permute4x64_epi64() {
         let a = _mm256_setr_epi64x(100, 200, 300, 400);
         let expected = _mm256_setr_epi64x(400, 100, 200, 100);
         let r = _mm256_permute4x64_epi64::<0b00010011>(a);
@@ -5472,7 +5472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_permute2x128_si256() {
+    const fn test_mm256_permute2x128_si256() {
         let a = _mm256_setr_epi64x(100, 200, 500, 600);
         let b = _mm256_setr_epi64x(300, 400, 700, 800);
         let r = _mm256_permute2x128_si256::<0b00_01_00_11>(a, b);
@@ -5481,7 +5481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_permute4x64_pd() {
+    const fn test_mm256_permute4x64_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let r = _mm256_permute4x64_pd::<0b00_01_00_11>(a);
         let e = _mm256_setr_pd(4., 1., 2., 1.);
@@ -5489,7 +5489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_permutevar8x32_ps() {
+    fn test_mm256_permutevar8x32_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_epi32(5, 0, 5, 1, 7, 6, 3, 4);
         let r = _mm256_permutevar8x32_ps(a, b);
@@ -5839,7 +5839,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_extract_epi8() {
+    const fn test_mm256_extract_epi8() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             -1, 1, 2, 3, 4, 5, 6, 7,
@@ -5854,7 +5854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_extract_epi16() {
+    const fn test_mm256_extract_epi16() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi16(
             -1, 1, 2, 3, 4, 5, 6, 7,
diff --git a/crates/core_arch/src/x86/avx512bf16.rs b/crates/core_arch/src/x86/avx512bf16.rs
index 85afd91fba..83dbc540a0 100644
--- a/crates/core_arch/src/x86/avx512bf16.rs
+++ b/crates/core_arch/src/x86/avx512bf16.rs
@@ -1833,7 +1833,7 @@ mod tests {
     const BF16_EIGHT: u16 = 0b0_10000010_0000000;
 
     #[simd_test(enable = "avx512bf16")]
-    unsafe fn test_mm512_cvtpbh_ps() {
+    fn test_mm512_cvtpbh_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
@@ -1846,7 +1846,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16")]
-    unsafe fn test_mm512_mask_cvtpbh_ps() {
+    fn test_mm512_mask_cvtpbh_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
@@ -1863,7 +1863,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16")]
-    unsafe fn test_mm512_maskz_cvtpbh_ps() {
+    fn test_mm512_maskz_cvtpbh_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
@@ -1877,7 +1877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_cvtpbh_ps() {
+    fn test_mm256_cvtpbh_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
@@ -1887,7 +1887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpbh_ps() {
+    fn test_mm256_mask_cvtpbh_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
@@ -1899,7 +1899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpbh_ps() {
+    fn test_mm256_maskz_cvtpbh_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
@@ -1910,7 +1910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_cvtpbh_ps() {
+    fn test_mm_cvtpbh_ps() {
         let a = __m128bh([BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, 0, 0, 0, 0]);
         let r = _mm_cvtpbh_ps(a);
         let e = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
@@ -1918,7 +1918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_cvtpbh_ps() {
+    fn test_mm_mask_cvtpbh_ps() {
         let a = __m128bh([BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, 0, 0, 0, 0]);
         let src = _mm_setr_ps(9., 10., 11., 12.);
         let k = 0b1010;
@@ -1928,7 +1928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpbh_ps() {
+    fn test_mm_maskz_cvtpbh_ps() {
         let a = __m128bh([BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, 0, 0, 0, 0]);
         let k = 0b1010;
         let r = _mm_maskz_cvtpbh_ps(k, a);
@@ -1937,7 +1937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16")]
-    unsafe fn test_mm_cvtsbh_ss() {
+    fn test_mm_cvtsbh_ss() {
         let r = _mm_cvtsbh_ss(bf16::from_bits(BF16_ONE));
         assert_eq!(r, 1.);
     }
@@ -1970,7 +1970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_cvtness_sbh() {
+    fn test_mm_cvtness_sbh() {
         let r = _mm_cvtness_sbh(1.);
         assert_eq!(r.to_bits(), BF16_ONE);
     }
diff --git a/crates/core_arch/src/x86/avx512bitalg.rs b/crates/core_arch/src/x86/avx512bitalg.rs
index 497fa21c4f..6dd4e6b33a 100644
--- a/crates/core_arch/src/x86/avx512bitalg.rs
+++ b/crates/core_arch/src/x86/avx512bitalg.rs
@@ -460,7 +460,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    const unsafe fn test_mm512_popcnt_epi16() {
+    const fn test_mm512_popcnt_epi16() {
         let test_data = _mm512_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF, 0xFF_FF, -1, -100, 255, 256, 2, 4, 8, 16, 32, 64, 128, 256, 512,
@@ -475,7 +475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    const unsafe fn test_mm512_maskz_popcnt_epi16() {
+    const fn test_mm512_maskz_popcnt_epi16() {
         let test_data = _mm512_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF, 0xFF_FF, -1, -100, 255, 256, 2, 4, 8, 16, 32, 64, 128, 256, 512,
@@ -491,7 +491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    const unsafe fn test_mm512_mask_popcnt_epi16() {
+    const fn test_mm512_mask_popcnt_epi16() {
         let test_data = _mm512_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF, 0xFF_FF, -1, -100, 255, 256, 2, 4, 8, 16, 32, 64, 128, 256, 512,
@@ -507,7 +507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm256_popcnt_epi16() {
+    const fn test_mm256_popcnt_epi16() {
         let test_data = _mm256_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF,
@@ -519,7 +519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_popcnt_epi16() {
+    const fn test_mm256_maskz_popcnt_epi16() {
         let test_data = _mm256_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF,
@@ -531,7 +531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_popcnt_epi16() {
+    const fn test_mm256_mask_popcnt_epi16() {
         let test_data = _mm256_set_epi16(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, 0x1_FF, 0x3_FF, 0x7_FF, 0xF_FF, 0x1F_FF,
             0x3F_FF, 0x7F_FF,
@@ -545,7 +545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm_popcnt_epi16() {
+    const fn test_mm_popcnt_epi16() {
         let test_data = _mm_set_epi16(0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F);
         let actual_result = _mm_popcnt_epi16(test_data);
         let reference_result = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
@@ -553,7 +553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_popcnt_epi16() {
+    const fn test_mm_maskz_popcnt_epi16() {
         let test_data = _mm_set_epi16(0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F);
         let mask = 0xF0;
         let actual_result = _mm_maskz_popcnt_epi16(mask, test_data);
@@ -562,7 +562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_popcnt_epi16() {
+    const fn test_mm_mask_popcnt_epi16() {
         let test_data = _mm_set_epi16(0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F);
         let mask = 0xF0;
         let actual_result = _mm_mask_popcnt_epi16(test_data, mask, test_data);
@@ -571,7 +571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    const unsafe fn test_mm512_popcnt_epi8() {
+    const fn test_mm512_popcnt_epi8() {
         let test_data = _mm512_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172, 183, 154, 84, 56, 227, 189,
@@ -588,7 +588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    const unsafe fn test_mm512_maskz_popcnt_epi8() {
+    const fn test_mm512_maskz_popcnt_epi8() {
         let test_data = _mm512_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172, 183, 154, 84, 56, 227, 189,
@@ -606,7 +606,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    const unsafe fn test_mm512_mask_popcnt_epi8() {
+    const fn test_mm512_mask_popcnt_epi8() {
         let test_data = _mm512_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172, 183, 154, 84, 56, 227, 189,
@@ -624,7 +624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm256_popcnt_epi8() {
+    const fn test_mm256_popcnt_epi8() {
         let test_data = _mm256_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 128, 171, 206, 100,
             217, 109, 253, 190, 177, 254, 179, 215, 230, 68, 201, 172,
@@ -638,7 +638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_popcnt_epi8() {
+    const fn test_mm256_maskz_popcnt_epi8() {
         let test_data = _mm256_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 251, 73, 121, 143,
             145, 85, 91, 137, 90, 225, 21, 249, 211, 155, 228, 70,
@@ -653,7 +653,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_popcnt_epi8() {
+    const fn test_mm256_mask_popcnt_epi8() {
         let test_data = _mm256_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64, 251, 73, 121, 143,
             145, 85, 91, 137, 90, 225, 21, 249, 211, 155, 228, 70,
@@ -668,7 +668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm_popcnt_epi8() {
+    const fn test_mm_popcnt_epi8() {
         let test_data = _mm_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, -1, 2, 4, 8, 16, 32, 64,
         );
@@ -678,7 +678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_popcnt_epi8() {
+    const fn test_mm_maskz_popcnt_epi8() {
         let test_data = _mm_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 90, 225, 21, 249, 211, 155, 228, 70,
         );
@@ -689,7 +689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_popcnt_epi8() {
+    const fn test_mm_mask_popcnt_epi8() {
         let test_data = _mm_set_epi8(
             0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 90, 225, 21, 249, 211, 155, 228, 70,
         );
@@ -701,7 +701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_bitshuffle_epi64_mask() {
+    fn test_mm512_bitshuffle_epi64_mask() {
         let test_indices = _mm512_set_epi8(
             63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59, 58, 57, 56, 32, 32, 16, 16, 0, 0,
             8, 8, 56, 48, 40, 32, 24, 16, 8, 0, 63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59,
@@ -731,7 +731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f")]
-    unsafe fn test_mm512_mask_bitshuffle_epi64_mask() {
+    fn test_mm512_mask_bitshuffle_epi64_mask() {
         let test_indices = _mm512_set_epi8(
             63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59, 58, 57, 56, 32, 32, 16, 16, 0, 0,
             8, 8, 56, 48, 40, 32, 24, 16, 8, 0, 63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59,
@@ -762,7 +762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_bitshuffle_epi64_mask() {
+    fn test_mm256_bitshuffle_epi64_mask() {
         let test_indices = _mm256_set_epi8(
             63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59, 58, 57, 56, 32, 32, 16, 16, 0, 0,
             8, 8, 56, 48, 40, 32, 24, 16, 8, 0,
@@ -780,7 +780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_bitshuffle_epi64_mask() {
+    fn test_mm256_mask_bitshuffle_epi64_mask() {
         let test_indices = _mm256_set_epi8(
             63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59, 58, 57, 56, 32, 32, 16, 16, 0, 0,
             8, 8, 56, 48, 40, 32, 24, 16, 8, 0,
@@ -799,7 +799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_bitshuffle_epi64_mask() {
+    fn test_mm_bitshuffle_epi64_mask() {
         let test_indices = _mm_set_epi8(
             63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59, 58, 57, 56,
         );
@@ -811,7 +811,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bitalg,avx512f,avx512vl")]
-    unsafe fn test_mm_mask_bitshuffle_epi64_mask() {
+    fn test_mm_mask_bitshuffle_epi64_mask() {
         let test_indices = _mm_set_epi8(
             63, 62, 61, 60, 59, 58, 57, 56, 63, 62, 61, 60, 59, 58, 57, 56,
         );
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index b6e941908a..dc86f70c05 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -12662,7 +12662,7 @@ mod tests {
     use crate::mem::{self};
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_abs_epi16() {
+    const fn test_mm512_abs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let r = _mm512_abs_epi16(a);
         let e = _mm512_set1_epi16(1);
@@ -12670,7 +12670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_abs_epi16() {
+    const fn test_mm512_mask_abs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let r = _mm512_mask_abs_epi16(a, 0, a);
         assert_eq_m512i(r, a);
@@ -12682,7 +12682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_abs_epi16() {
+    const fn test_mm512_maskz_abs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let r = _mm512_maskz_abs_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -12694,7 +12694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_abs_epi16() {
+    const fn test_mm256_mask_abs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let r = _mm256_mask_abs_epi16(a, 0, a);
         assert_eq_m256i(r, a);
@@ -12704,7 +12704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_abs_epi16() {
+    const fn test_mm256_maskz_abs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let r = _mm256_maskz_abs_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -12714,7 +12714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_abs_epi16() {
+    const fn test_mm_mask_abs_epi16() {
         let a = _mm_set1_epi16(-1);
         let r = _mm_mask_abs_epi16(a, 0, a);
         assert_eq_m128i(r, a);
@@ -12724,7 +12724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_abs_epi16() {
+    const fn test_mm_maskz_abs_epi16() {
         let a = _mm_set1_epi16(-1);
         let r = _mm_maskz_abs_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -12734,7 +12734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_abs_epi8() {
+    const fn test_mm512_abs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let r = _mm512_abs_epi8(a);
         let e = _mm512_set1_epi8(1);
@@ -12742,7 +12742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_abs_epi8() {
+    const fn test_mm512_mask_abs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let r = _mm512_mask_abs_epi8(a, 0, a);
         assert_eq_m512i(r, a);
@@ -12760,7 +12760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_abs_epi8() {
+    const fn test_mm512_maskz_abs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let r = _mm512_maskz_abs_epi8(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -12777,7 +12777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_abs_epi8() {
+    const fn test_mm256_mask_abs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let r = _mm256_mask_abs_epi8(a, 0, a);
         assert_eq_m256i(r, a);
@@ -12789,7 +12789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_abs_epi8() {
+    const fn test_mm256_maskz_abs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let r = _mm256_maskz_abs_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -12801,7 +12801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_abs_epi8() {
+    const fn test_mm_mask_abs_epi8() {
         let a = _mm_set1_epi8(-1);
         let r = _mm_mask_abs_epi8(a, 0, a);
         assert_eq_m128i(r, a);
@@ -12811,7 +12811,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_abs_epi8() {
+    const fn test_mm_maskz_abs_epi8() {
         let a = _mm_set1_epi8(-1);
         let r = _mm_maskz_abs_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -12822,7 +12822,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_add_epi16() {
+    const fn test_mm512_add_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_add_epi16(a, b);
@@ -12831,7 +12831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_add_epi16() {
+    const fn test_mm512_mask_add_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_mask_add_epi16(a, 0, a, b);
@@ -12844,7 +12844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_add_epi16() {
+    const fn test_mm512_maskz_add_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_maskz_add_epi16(0, a, b);
@@ -12857,7 +12857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_add_epi16() {
+    const fn test_mm256_mask_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_mask_add_epi16(a, 0, a, b);
@@ -12868,7 +12868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_epi16() {
+    const fn test_mm256_maskz_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_maskz_add_epi16(0, a, b);
@@ -12879,7 +12879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_add_epi16() {
+    const fn test_mm_mask_add_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_mask_add_epi16(a, 0, a, b);
@@ -12890,7 +12890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_add_epi16() {
+    const fn test_mm_maskz_add_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_maskz_add_epi16(0, a, b);
@@ -12901,7 +12901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_add_epi8() {
+    const fn test_mm512_add_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_add_epi8(a, b);
@@ -12910,7 +12910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_add_epi8() {
+    const fn test_mm512_mask_add_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_mask_add_epi8(a, 0, a, b);
@@ -12930,7 +12930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_add_epi8() {
+    const fn test_mm512_maskz_add_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_maskz_add_epi8(0, a, b);
@@ -12949,7 +12949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_add_epi8() {
+    const fn test_mm256_mask_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_mask_add_epi8(a, 0, a, b);
@@ -12962,7 +12962,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_epi8() {
+    const fn test_mm256_maskz_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_maskz_add_epi8(0, a, b);
@@ -12975,7 +12975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_add_epi8() {
+    const fn test_mm_mask_add_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_mask_add_epi8(a, 0, a, b);
@@ -12986,7 +12986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_add_epi8() {
+    const fn test_mm_maskz_add_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_maskz_add_epi8(0, a, b);
@@ -12997,7 +12997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_adds_epu16() {
+    const fn test_mm512_adds_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_adds_epu16(a, b);
@@ -13006,7 +13006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_adds_epu16() {
+    const fn test_mm512_mask_adds_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_mask_adds_epu16(a, 0, a, b);
@@ -13019,7 +13019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_adds_epu16() {
+    const fn test_mm512_maskz_adds_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_maskz_adds_epu16(0, a, b);
@@ -13032,7 +13032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_adds_epu16() {
+    const fn test_mm256_mask_adds_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_mask_adds_epu16(a, 0, a, b);
@@ -13044,7 +13044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_adds_epu16() {
+    const fn test_mm256_maskz_adds_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_maskz_adds_epu16(0, a, b);
@@ -13056,7 +13056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_adds_epu16() {
+    const fn test_mm_mask_adds_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_mask_adds_epu16(a, 0, a, b);
@@ -13068,7 +13068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_adds_epu16() {
+    const fn test_mm_maskz_adds_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_maskz_adds_epu16(0, a, b);
@@ -13080,7 +13080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_adds_epu8() {
+    const fn test_mm512_adds_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_adds_epu8(a, b);
@@ -13089,7 +13089,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_adds_epu8() {
+    const fn test_mm512_mask_adds_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_mask_adds_epu8(a, 0, a, b);
@@ -13109,7 +13109,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_adds_epu8() {
+    const fn test_mm512_maskz_adds_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_maskz_adds_epu8(0, a, b);
@@ -13128,7 +13128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_adds_epu8() {
+    const fn test_mm256_mask_adds_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_mask_adds_epu8(a, 0, a, b);
@@ -13141,7 +13141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_adds_epu8() {
+    const fn test_mm256_maskz_adds_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_maskz_adds_epu8(0, a, b);
@@ -13154,7 +13154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_adds_epu8() {
+    const fn test_mm_mask_adds_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_mask_adds_epu8(a, 0, a, b);
@@ -13166,7 +13166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_adds_epu8() {
+    const fn test_mm_maskz_adds_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_maskz_adds_epu8(0, a, b);
@@ -13178,7 +13178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_adds_epi16() {
+    const fn test_mm512_adds_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_adds_epi16(a, b);
@@ -13187,7 +13187,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_adds_epi16() {
+    const fn test_mm512_mask_adds_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_mask_adds_epi16(a, 0, a, b);
@@ -13200,7 +13200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_adds_epi16() {
+    const fn test_mm512_maskz_adds_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_maskz_adds_epi16(0, a, b);
@@ -13213,7 +13213,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_adds_epi16() {
+    const fn test_mm256_mask_adds_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_mask_adds_epi16(a, 0, a, b);
@@ -13225,7 +13225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_adds_epi16() {
+    const fn test_mm256_maskz_adds_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_maskz_adds_epi16(0, a, b);
@@ -13237,7 +13237,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_adds_epi16() {
+    const fn test_mm_mask_adds_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_mask_adds_epi16(a, 0, a, b);
@@ -13248,7 +13248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_adds_epi16() {
+    const fn test_mm_maskz_adds_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_maskz_adds_epi16(0, a, b);
@@ -13259,7 +13259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_adds_epi8() {
+    const fn test_mm512_adds_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_adds_epi8(a, b);
@@ -13268,7 +13268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_adds_epi8() {
+    const fn test_mm512_mask_adds_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_mask_adds_epi8(a, 0, a, b);
@@ -13288,7 +13288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_adds_epi8() {
+    const fn test_mm512_maskz_adds_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_maskz_adds_epi8(0, a, b);
@@ -13307,7 +13307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_adds_epi8() {
+    const fn test_mm256_mask_adds_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_mask_adds_epi8(a, 0, a, b);
@@ -13320,7 +13320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_adds_epi8() {
+    const fn test_mm256_maskz_adds_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_maskz_adds_epi8(0, a, b);
@@ -13333,7 +13333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_adds_epi8() {
+    const fn test_mm_mask_adds_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_mask_adds_epi8(a, 0, a, b);
@@ -13345,7 +13345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_adds_epi8() {
+    const fn test_mm_maskz_adds_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_maskz_adds_epi8(0, a, b);
@@ -13357,7 +13357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_sub_epi16() {
+    const fn test_mm512_sub_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_sub_epi16(a, b);
@@ -13366,7 +13366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_sub_epi16() {
+    const fn test_mm512_mask_sub_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_mask_sub_epi16(a, 0, a, b);
@@ -13379,7 +13379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_sub_epi16() {
+    const fn test_mm512_maskz_sub_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_maskz_sub_epi16(0, a, b);
@@ -13392,7 +13392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_epi16() {
+    const fn test_mm256_mask_sub_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_mask_sub_epi16(a, 0, a, b);
@@ -13403,7 +13403,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_epi16() {
+    const fn test_mm256_maskz_sub_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_maskz_sub_epi16(0, a, b);
@@ -13414,7 +13414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_sub_epi16() {
+    const fn test_mm_mask_sub_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_mask_sub_epi16(a, 0, a, b);
@@ -13425,7 +13425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_epi16() {
+    const fn test_mm_maskz_sub_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_maskz_sub_epi16(0, a, b);
@@ -13436,7 +13436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_sub_epi8() {
+    const fn test_mm512_sub_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_sub_epi8(a, b);
@@ -13445,7 +13445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_sub_epi8() {
+    const fn test_mm512_mask_sub_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_mask_sub_epi8(a, 0, a, b);
@@ -13465,7 +13465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_sub_epi8() {
+    const fn test_mm512_maskz_sub_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_maskz_sub_epi8(0, a, b);
@@ -13484,7 +13484,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_epi8() {
+    const fn test_mm256_mask_sub_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_mask_sub_epi8(a, 0, a, b);
@@ -13497,7 +13497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_epi8() {
+    const fn test_mm256_maskz_sub_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_maskz_sub_epi8(0, a, b);
@@ -13510,7 +13510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_sub_epi8() {
+    const fn test_mm_mask_sub_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_mask_sub_epi8(a, 0, a, b);
@@ -13521,7 +13521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_epi8() {
+    const fn test_mm_maskz_sub_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_maskz_sub_epi8(0, a, b);
@@ -13532,7 +13532,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_subs_epu16() {
+    const fn test_mm512_subs_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_subs_epu16(a, b);
@@ -13541,7 +13541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_subs_epu16() {
+    const fn test_mm512_mask_subs_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_mask_subs_epu16(a, 0, a, b);
@@ -13554,7 +13554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_subs_epu16() {
+    const fn test_mm512_maskz_subs_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(u16::MAX as i16);
         let r = _mm512_maskz_subs_epu16(0, a, b);
@@ -13567,7 +13567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_subs_epu16() {
+    const fn test_mm256_mask_subs_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_mask_subs_epu16(a, 0, a, b);
@@ -13578,7 +13578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_subs_epu16() {
+    const fn test_mm256_maskz_subs_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(u16::MAX as i16);
         let r = _mm256_maskz_subs_epu16(0, a, b);
@@ -13589,7 +13589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_subs_epu16() {
+    const fn test_mm_mask_subs_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_mask_subs_epu16(a, 0, a, b);
@@ -13600,7 +13600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_subs_epu16() {
+    const fn test_mm_maskz_subs_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(u16::MAX as i16);
         let r = _mm_maskz_subs_epu16(0, a, b);
@@ -13611,7 +13611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_subs_epu8() {
+    const fn test_mm512_subs_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_subs_epu8(a, b);
@@ -13620,7 +13620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_subs_epu8() {
+    const fn test_mm512_mask_subs_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_mask_subs_epu8(a, 0, a, b);
@@ -13640,7 +13640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_subs_epu8() {
+    const fn test_mm512_maskz_subs_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(u8::MAX as i8);
         let r = _mm512_maskz_subs_epu8(0, a, b);
@@ -13659,7 +13659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_subs_epu8() {
+    const fn test_mm256_mask_subs_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_mask_subs_epu8(a, 0, a, b);
@@ -13672,7 +13672,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_subs_epu8() {
+    const fn test_mm256_maskz_subs_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(u8::MAX as i8);
         let r = _mm256_maskz_subs_epu8(0, a, b);
@@ -13685,7 +13685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_subs_epu8() {
+    const fn test_mm_mask_subs_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_mask_subs_epu8(a, 0, a, b);
@@ -13696,7 +13696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_subs_epu8() {
+    const fn test_mm_maskz_subs_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(u8::MAX as i8);
         let r = _mm_maskz_subs_epu8(0, a, b);
@@ -13707,7 +13707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_subs_epi16() {
+    const fn test_mm512_subs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_subs_epi16(a, b);
@@ -13716,7 +13716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_subs_epi16() {
+    const fn test_mm512_mask_subs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_mask_subs_epi16(a, 0, a, b);
@@ -13729,7 +13729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_subs_epi16() {
+    const fn test_mm512_maskz_subs_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_maskz_subs_epi16(0, a, b);
@@ -13742,7 +13742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_subs_epi16() {
+    const fn test_mm256_mask_subs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_mask_subs_epi16(a, 0, a, b);
@@ -13754,7 +13754,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_subs_epi16() {
+    const fn test_mm256_maskz_subs_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_maskz_subs_epi16(0, a, b);
@@ -13766,7 +13766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_subs_epi16() {
+    const fn test_mm_mask_subs_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_mask_subs_epi16(a, 0, a, b);
@@ -13777,7 +13777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_subs_epi16() {
+    const fn test_mm_maskz_subs_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(i16::MAX);
         let r = _mm_maskz_subs_epi16(0, a, b);
@@ -13788,7 +13788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_subs_epi8() {
+    const fn test_mm512_subs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_subs_epi8(a, b);
@@ -13797,7 +13797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_subs_epi8() {
+    const fn test_mm512_mask_subs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_mask_subs_epi8(a, 0, a, b);
@@ -13817,7 +13817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_subs_epi8() {
+    const fn test_mm512_maskz_subs_epi8() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(i8::MAX);
         let r = _mm512_maskz_subs_epi8(0, a, b);
@@ -13836,7 +13836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_subs_epi8() {
+    const fn test_mm256_mask_subs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_mask_subs_epi8(a, 0, a, b);
@@ -13849,7 +13849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_subs_epi8() {
+    const fn test_mm256_maskz_subs_epi8() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(i8::MAX);
         let r = _mm256_maskz_subs_epi8(0, a, b);
@@ -13862,7 +13862,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_subs_epi8() {
+    const fn test_mm_mask_subs_epi8() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_mask_subs_epi8(a, 0, a, b);
@@ -13874,7 +13874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_subs_epi8() {
+    const fn test_mm_maskz_subs_epi8() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(i8::MAX);
         let r = _mm_maskz_subs_epi8(0, a, b);
@@ -13886,7 +13886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mulhi_epu16() {
+    const fn test_mm512_mulhi_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mulhi_epu16(a, b);
@@ -13895,7 +13895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_mulhi_epu16() {
+    const fn test_mm512_mask_mulhi_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mulhi_epu16(a, 0, a, b);
@@ -13908,7 +13908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_mulhi_epu16() {
+    const fn test_mm512_maskz_mulhi_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mulhi_epu16(0, a, b);
@@ -13921,7 +13921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_mulhi_epu16() {
+    const fn test_mm256_mask_mulhi_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mulhi_epu16(a, 0, a, b);
@@ -13932,7 +13932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_mulhi_epu16() {
+    const fn test_mm256_maskz_mulhi_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mulhi_epu16(0, a, b);
@@ -13943,7 +13943,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_mulhi_epu16() {
+    const fn test_mm_mask_mulhi_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mulhi_epu16(a, 0, a, b);
@@ -13954,7 +13954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_mulhi_epu16() {
+    const fn test_mm_maskz_mulhi_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mulhi_epu16(0, a, b);
@@ -13965,7 +13965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mulhi_epi16() {
+    const fn test_mm512_mulhi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mulhi_epi16(a, b);
@@ -13974,7 +13974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_mulhi_epi16() {
+    const fn test_mm512_mask_mulhi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mulhi_epi16(a, 0, a, b);
@@ -13987,7 +13987,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_mulhi_epi16() {
+    const fn test_mm512_maskz_mulhi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mulhi_epi16(0, a, b);
@@ -14000,7 +14000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_mulhi_epi16() {
+    const fn test_mm256_mask_mulhi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mulhi_epi16(a, 0, a, b);
@@ -14011,7 +14011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_mulhi_epi16() {
+    const fn test_mm256_maskz_mulhi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mulhi_epi16(0, a, b);
@@ -14022,7 +14022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_mulhi_epi16() {
+    const fn test_mm_mask_mulhi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mulhi_epi16(a, 0, a, b);
@@ -14033,7 +14033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_mulhi_epi16() {
+    const fn test_mm_maskz_mulhi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mulhi_epi16(0, a, b);
@@ -14044,7 +14044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mulhrs_epi16() {
+    fn test_mm512_mulhrs_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mulhrs_epi16(a, b);
@@ -14053,7 +14053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_mulhrs_epi16() {
+    fn test_mm512_mask_mulhrs_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mulhrs_epi16(a, 0, a, b);
@@ -14066,7 +14066,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_mulhrs_epi16() {
+    fn test_mm512_maskz_mulhrs_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mulhrs_epi16(0, a, b);
@@ -14079,7 +14079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_mulhrs_epi16() {
+    fn test_mm256_mask_mulhrs_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mulhrs_epi16(a, 0, a, b);
@@ -14090,7 +14090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_mulhrs_epi16() {
+    fn test_mm256_maskz_mulhrs_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mulhrs_epi16(0, a, b);
@@ -14101,7 +14101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_mulhrs_epi16() {
+    fn test_mm_mask_mulhrs_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mulhrs_epi16(a, 0, a, b);
@@ -14112,7 +14112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_mulhrs_epi16() {
+    fn test_mm_maskz_mulhrs_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mulhrs_epi16(0, a, b);
@@ -14123,7 +14123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mullo_epi16() {
+    const fn test_mm512_mullo_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mullo_epi16(a, b);
@@ -14132,7 +14132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_mullo_epi16() {
+    const fn test_mm512_mask_mullo_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_mullo_epi16(a, 0, a, b);
@@ -14145,7 +14145,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_mullo_epi16() {
+    const fn test_mm512_maskz_mullo_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_mullo_epi16(0, a, b);
@@ -14158,7 +14158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_mullo_epi16() {
+    const fn test_mm256_mask_mullo_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_mullo_epi16(a, 0, a, b);
@@ -14169,7 +14169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_mullo_epi16() {
+    const fn test_mm256_maskz_mullo_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_mullo_epi16(0, a, b);
@@ -14180,7 +14180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_mullo_epi16() {
+    const fn test_mm_mask_mullo_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_mullo_epi16(a, 0, a, b);
@@ -14191,7 +14191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_mullo_epi16() {
+    const fn test_mm_maskz_mullo_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_mullo_epi16(0, a, b);
@@ -14202,7 +14202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_max_epu16() {
+    const fn test_mm512_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14217,7 +14217,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_max_epu16() {
+    const fn test_mm512_mask_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14234,7 +14234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_max_epu16() {
+    const fn test_mm512_maskz_max_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14251,7 +14251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epu16() {
+    const fn test_mm256_mask_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epu16(a, 0, a, b);
@@ -14262,7 +14262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epu16() {
+    const fn test_mm256_maskz_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epu16(0, a, b);
@@ -14273,7 +14273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_max_epu16() {
+    const fn test_mm_mask_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epu16(a, 0, a, b);
@@ -14284,7 +14284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epu16() {
+    const fn test_mm_maskz_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epu16(0, a, b);
@@ -14295,7 +14295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_max_epu8() {
+    const fn test_mm512_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14316,7 +14316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_max_epu8() {
+    const fn test_mm512_mask_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14344,7 +14344,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_max_epu8() {
+    const fn test_mm512_maskz_max_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14371,7 +14371,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epu8() {
+    const fn test_mm256_mask_max_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14388,7 +14388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epu8() {
+    const fn test_mm256_maskz_max_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14405,7 +14405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_max_epu8() {
+    const fn test_mm_mask_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epu8(a, 0, a, b);
@@ -14416,7 +14416,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epu8() {
+    const fn test_mm_maskz_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epu8(0, a, b);
@@ -14427,7 +14427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_max_epi16() {
+    const fn test_mm512_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14442,7 +14442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_max_epi16() {
+    const fn test_mm512_mask_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14459,7 +14459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_max_epi16() {
+    const fn test_mm512_maskz_max_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14476,7 +14476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epi16() {
+    const fn test_mm256_mask_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epi16(a, 0, a, b);
@@ -14487,7 +14487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epi16() {
+    const fn test_mm256_maskz_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epi16(0, a, b);
@@ -14498,7 +14498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_max_epi16() {
+    const fn test_mm_mask_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epi16(a, 0, a, b);
@@ -14509,7 +14509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epi16() {
+    const fn test_mm_maskz_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epi16(0, a, b);
@@ -14520,7 +14520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_max_epi8() {
+    const fn test_mm512_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14541,7 +14541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_max_epi8() {
+    const fn test_mm512_mask_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14569,7 +14569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_max_epi8() {
+    const fn test_mm512_maskz_max_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14596,7 +14596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epi8() {
+    const fn test_mm256_mask_max_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14613,7 +14613,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epi8() {
+    const fn test_mm256_maskz_max_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14630,7 +14630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_max_epi8() {
+    const fn test_mm_mask_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_max_epi8(a, 0, a, b);
@@ -14641,7 +14641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epi8() {
+    const fn test_mm_maskz_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_max_epi8(0, a, b);
@@ -14652,7 +14652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_min_epu16() {
+    const fn test_mm512_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14667,7 +14667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_min_epu16() {
+    const fn test_mm512_mask_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14684,7 +14684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_min_epu16() {
+    const fn test_mm512_maskz_min_epu16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14701,7 +14701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epu16() {
+    const fn test_mm256_mask_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epu16(a, 0, a, b);
@@ -14712,7 +14712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epu16() {
+    const fn test_mm256_maskz_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epu16(0, a, b);
@@ -14723,7 +14723,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_min_epu16() {
+    const fn test_mm_mask_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epu16(a, 0, a, b);
@@ -14734,7 +14734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epu16() {
+    const fn test_mm_maskz_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epu16(0, a, b);
@@ -14745,7 +14745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_min_epu8() {
+    const fn test_mm512_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14766,7 +14766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_min_epu8() {
+    const fn test_mm512_mask_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14794,7 +14794,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_min_epu8() {
+    const fn test_mm512_maskz_min_epu8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14821,7 +14821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epu8() {
+    const fn test_mm256_mask_min_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14838,7 +14838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epu8() {
+    const fn test_mm256_maskz_min_epu8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14855,7 +14855,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_min_epu8() {
+    const fn test_mm_mask_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epu8(a, 0, a, b);
@@ -14866,7 +14866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epu8() {
+    const fn test_mm_maskz_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epu8(0, a, b);
@@ -14877,7 +14877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_min_epi16() {
+    const fn test_mm512_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14892,7 +14892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_min_epi16() {
+    const fn test_mm512_mask_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14909,7 +14909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_min_epi16() {
+    const fn test_mm512_maskz_min_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -14926,7 +14926,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epi16() {
+    const fn test_mm256_mask_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epi16(a, 0, a, b);
@@ -14937,7 +14937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epi16() {
+    const fn test_mm256_maskz_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epi16(0, a, b);
@@ -14948,7 +14948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_min_epi16() {
+    const fn test_mm_mask_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epi16(a, 0, a, b);
@@ -14959,7 +14959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epi16() {
+    const fn test_mm_maskz_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epi16(0, a, b);
@@ -14970,7 +14970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_min_epi8() {
+    const fn test_mm512_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -14991,7 +14991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_min_epi8() {
+    const fn test_mm512_mask_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -15019,7 +15019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_min_epi8() {
+    const fn test_mm512_maskz_min_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -15046,7 +15046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epi8() {
+    const fn test_mm256_mask_min_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -15063,7 +15063,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epi8() {
+    const fn test_mm256_maskz_min_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -15080,7 +15080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_min_epi8() {
+    const fn test_mm_mask_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_mask_min_epi8(a, 0, a, b);
@@ -15091,7 +15091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epi8() {
+    const fn test_mm_maskz_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_maskz_min_epi8(0, a, b);
@@ -15102,7 +15102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmplt_epu16_mask() {
+    const fn test_mm512_cmplt_epu16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmplt_epu16_mask(a, b);
@@ -15110,7 +15110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmplt_epu16_mask() {
+    const fn test_mm512_mask_cmplt_epu16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15119,7 +15119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epu16_mask() {
+    const fn test_mm256_cmplt_epu16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmplt_epu16_mask(a, b);
@@ -15127,7 +15127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epu16_mask() {
+    const fn test_mm256_mask_cmplt_epu16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15136,7 +15136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmplt_epu16_mask() {
+    const fn test_mm_cmplt_epu16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmplt_epu16_mask(a, b);
@@ -15144,7 +15144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epu16_mask() {
+    const fn test_mm_mask_cmplt_epu16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15153,7 +15153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmplt_epu8_mask() {
+    const fn test_mm512_cmplt_epu8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmplt_epu8_mask(a, b);
@@ -15164,7 +15164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmplt_epu8_mask() {
+    const fn test_mm512_mask_cmplt_epu8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15176,7 +15176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epu8_mask() {
+    const fn test_mm256_cmplt_epu8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmplt_epu8_mask(a, b);
@@ -15184,7 +15184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epu8_mask() {
+    const fn test_mm256_mask_cmplt_epu8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15193,7 +15193,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmplt_epu8_mask() {
+    const fn test_mm_cmplt_epu8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmplt_epu8_mask(a, b);
@@ -15201,7 +15201,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epu8_mask() {
+    const fn test_mm_mask_cmplt_epu8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15210,7 +15210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmplt_epi16_mask() {
+    const fn test_mm512_cmplt_epi16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmplt_epi16_mask(a, b);
@@ -15218,7 +15218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmplt_epi16_mask() {
+    const fn test_mm512_mask_cmplt_epi16_mask() {
         let a = _mm512_set1_epi16(-2);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15227,7 +15227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epi16_mask() {
+    const fn test_mm256_cmplt_epi16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmplt_epi16_mask(a, b);
@@ -15235,7 +15235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epi16_mask() {
+    const fn test_mm256_mask_cmplt_epi16_mask() {
         let a = _mm256_set1_epi16(-2);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15244,7 +15244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmplt_epi16_mask() {
+    const fn test_mm_cmplt_epi16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmplt_epi16_mask(a, b);
@@ -15252,7 +15252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epi16_mask() {
+    const fn test_mm_mask_cmplt_epi16_mask() {
         let a = _mm_set1_epi16(-2);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15261,7 +15261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmplt_epi8_mask() {
+    const fn test_mm512_cmplt_epi8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmplt_epi8_mask(a, b);
@@ -15272,7 +15272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmplt_epi8_mask() {
+    const fn test_mm512_mask_cmplt_epi8_mask() {
         let a = _mm512_set1_epi8(-2);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15284,7 +15284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epi8_mask() {
+    const fn test_mm256_cmplt_epi8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmplt_epi8_mask(a, b);
@@ -15292,7 +15292,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epi8_mask() {
+    const fn test_mm256_mask_cmplt_epi8_mask() {
         let a = _mm256_set1_epi8(-2);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15301,7 +15301,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmplt_epi8_mask() {
+    const fn test_mm_cmplt_epi8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmplt_epi8_mask(a, b);
@@ -15309,7 +15309,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epi8_mask() {
+    const fn test_mm_mask_cmplt_epi8_mask() {
         let a = _mm_set1_epi8(-2);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15318,7 +15318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpgt_epu16_mask() {
+    const fn test_mm512_cmpgt_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpgt_epu16_mask(a, b);
@@ -15326,7 +15326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpgt_epu16_mask() {
+    const fn test_mm512_mask_cmpgt_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15335,7 +15335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epu16_mask() {
+    const fn test_mm256_cmpgt_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpgt_epu16_mask(a, b);
@@ -15343,7 +15343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epu16_mask() {
+    const fn test_mm256_mask_cmpgt_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -15352,7 +15352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epu16_mask() {
+    const fn test_mm_cmpgt_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpgt_epu16_mask(a, b);
@@ -15360,7 +15360,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epu16_mask() {
+    const fn test_mm_mask_cmpgt_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -15369,7 +15369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpgt_epu8_mask() {
+    const fn test_mm512_cmpgt_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpgt_epu8_mask(a, b);
@@ -15380,7 +15380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpgt_epu8_mask() {
+    const fn test_mm512_mask_cmpgt_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15392,7 +15392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epu8_mask() {
+    const fn test_mm256_cmpgt_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpgt_epu8_mask(a, b);
@@ -15400,7 +15400,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epu8_mask() {
+    const fn test_mm256_mask_cmpgt_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15409,7 +15409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epu8_mask() {
+    const fn test_mm_cmpgt_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpgt_epu8_mask(a, b);
@@ -15417,7 +15417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epu8_mask() {
+    const fn test_mm_mask_cmpgt_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -15426,7 +15426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpgt_epi16_mask() {
+    const fn test_mm512_cmpgt_epi16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpgt_epi16_mask(a, b);
@@ -15434,7 +15434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpgt_epi16_mask() {
+    const fn test_mm512_mask_cmpgt_epi16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15443,7 +15443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epi16_mask() {
+    const fn test_mm256_cmpgt_epi16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpgt_epi16_mask(a, b);
@@ -15451,7 +15451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epi16_mask() {
+    const fn test_mm256_mask_cmpgt_epi16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b001010101_01010101;
@@ -15460,7 +15460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epi16_mask() {
+    const fn test_mm_cmpgt_epi16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpgt_epi16_mask(a, b);
@@ -15468,7 +15468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epi16_mask() {
+    const fn test_mm_mask_cmpgt_epi16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15477,7 +15477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpgt_epi8_mask() {
+    const fn test_mm512_cmpgt_epi8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpgt_epi8_mask(a, b);
@@ -15488,7 +15488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpgt_epi8_mask() {
+    const fn test_mm512_mask_cmpgt_epi8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15500,7 +15500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epi8_mask() {
+    const fn test_mm256_cmpgt_epi8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpgt_epi8_mask(a, b);
@@ -15508,7 +15508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epi8_mask() {
+    const fn test_mm256_mask_cmpgt_epi8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15517,7 +15517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epi8_mask() {
+    const fn test_mm_cmpgt_epi8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpgt_epi8_mask(a, b);
@@ -15525,7 +15525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epi8_mask() {
+    const fn test_mm_mask_cmpgt_epi8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15534,7 +15534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmple_epu16_mask() {
+    const fn test_mm512_cmple_epu16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmple_epu16_mask(a, b);
@@ -15542,7 +15542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmple_epu16_mask() {
+    const fn test_mm512_mask_cmple_epu16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15551,7 +15551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmple_epu16_mask() {
+    const fn test_mm256_cmple_epu16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmple_epu16_mask(a, b);
@@ -15559,7 +15559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epu16_mask() {
+    const fn test_mm256_mask_cmple_epu16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15568,7 +15568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmple_epu16_mask() {
+    const fn test_mm_cmple_epu16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmple_epu16_mask(a, b);
@@ -15576,7 +15576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epu16_mask() {
+    const fn test_mm_mask_cmple_epu16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15585,7 +15585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmple_epu8_mask() {
+    const fn test_mm512_cmple_epu8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmple_epu8_mask(a, b);
@@ -15596,7 +15596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmple_epu8_mask() {
+    const fn test_mm512_mask_cmple_epu8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15608,7 +15608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmple_epu8_mask() {
+    const fn test_mm256_cmple_epu8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmple_epu8_mask(a, b);
@@ -15616,7 +15616,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epu8_mask() {
+    const fn test_mm256_mask_cmple_epu8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15625,7 +15625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmple_epu8_mask() {
+    const fn test_mm_cmple_epu8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmple_epu8_mask(a, b);
@@ -15633,7 +15633,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epu8_mask() {
+    const fn test_mm_mask_cmple_epu8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15642,7 +15642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmple_epi16_mask() {
+    const fn test_mm512_cmple_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmple_epi16_mask(a, b);
@@ -15650,7 +15650,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmple_epi16_mask() {
+    const fn test_mm512_mask_cmple_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15659,7 +15659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmple_epi16_mask() {
+    const fn test_mm256_cmple_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmple_epi16_mask(a, b);
@@ -15667,7 +15667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epi16_mask() {
+    const fn test_mm256_mask_cmple_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15676,7 +15676,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmple_epi16_mask() {
+    const fn test_mm_cmple_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmple_epi16_mask(a, b);
@@ -15684,7 +15684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epi16_mask() {
+    const fn test_mm_mask_cmple_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15693,7 +15693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmple_epi8_mask() {
+    const fn test_mm512_cmple_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmple_epi8_mask(a, b);
@@ -15704,7 +15704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmple_epi8_mask() {
+    const fn test_mm512_mask_cmple_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15716,7 +15716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmple_epi8_mask() {
+    const fn test_mm256_cmple_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmple_epi8_mask(a, b);
@@ -15724,7 +15724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epi8_mask() {
+    const fn test_mm256_mask_cmple_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15733,7 +15733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmple_epi8_mask() {
+    const fn test_mm_cmple_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmple_epi8_mask(a, b);
@@ -15741,7 +15741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epi8_mask() {
+    const fn test_mm_mask_cmple_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15750,7 +15750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpge_epu16_mask() {
+    const fn test_mm512_cmpge_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpge_epu16_mask(a, b);
@@ -15758,7 +15758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpge_epu16_mask() {
+    const fn test_mm512_mask_cmpge_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15767,7 +15767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epu16_mask() {
+    const fn test_mm256_cmpge_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpge_epu16_mask(a, b);
@@ -15775,7 +15775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epu16_mask() {
+    const fn test_mm256_mask_cmpge_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -15784,7 +15784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpge_epu16_mask() {
+    const fn test_mm_cmpge_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpge_epu16_mask(a, b);
@@ -15792,7 +15792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epu16_mask() {
+    const fn test_mm_mask_cmpge_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -15801,7 +15801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpge_epu8_mask() {
+    const fn test_mm512_cmpge_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpge_epu8_mask(a, b);
@@ -15812,7 +15812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpge_epu8_mask() {
+    const fn test_mm512_mask_cmpge_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15824,7 +15824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epu8_mask() {
+    const fn test_mm256_cmpge_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpge_epu8_mask(a, b);
@@ -15832,7 +15832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epu8_mask() {
+    const fn test_mm256_mask_cmpge_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15841,7 +15841,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpge_epu8_mask() {
+    const fn test_mm_cmpge_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpge_epu8_mask(a, b);
@@ -15849,7 +15849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epu8_mask() {
+    const fn test_mm_mask_cmpge_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -15858,7 +15858,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpge_epi16_mask() {
+    const fn test_mm512_cmpge_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpge_epi16_mask(a, b);
@@ -15866,7 +15866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpge_epi16_mask() {
+    const fn test_mm512_mask_cmpge_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15875,7 +15875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epi16_mask() {
+    const fn test_mm256_cmpge_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpge_epi16_mask(a, b);
@@ -15883,7 +15883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epi16_mask() {
+    const fn test_mm256_mask_cmpge_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -15892,7 +15892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpge_epi16_mask() {
+    const fn test_mm_cmpge_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpge_epi16_mask(a, b);
@@ -15900,7 +15900,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epi16_mask() {
+    const fn test_mm_mask_cmpge_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -15909,7 +15909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpge_epi8_mask() {
+    const fn test_mm512_cmpge_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpge_epi8_mask(a, b);
@@ -15920,7 +15920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpge_epi8_mask() {
+    const fn test_mm512_mask_cmpge_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -15932,7 +15932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epi8_mask() {
+    const fn test_mm256_cmpge_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpge_epi8_mask(a, b);
@@ -15940,7 +15940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epi8_mask() {
+    const fn test_mm256_mask_cmpge_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15949,7 +15949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpge_epi8_mask() {
+    const fn test_mm_cmpge_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpge_epi8_mask(a, b);
@@ -15957,7 +15957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epi8_mask() {
+    const fn test_mm_mask_cmpge_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -15966,7 +15966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpeq_epu16_mask() {
+    const fn test_mm512_cmpeq_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpeq_epu16_mask(a, b);
@@ -15974,7 +15974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpeq_epu16_mask() {
+    const fn test_mm512_mask_cmpeq_epu16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -15983,7 +15983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epu16_mask() {
+    const fn test_mm256_cmpeq_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpeq_epu16_mask(a, b);
@@ -15991,7 +15991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epu16_mask() {
+    const fn test_mm256_mask_cmpeq_epu16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -16000,7 +16000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epu16_mask() {
+    const fn test_mm_cmpeq_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpeq_epu16_mask(a, b);
@@ -16008,7 +16008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epu16_mask() {
+    const fn test_mm_mask_cmpeq_epu16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -16017,7 +16017,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpeq_epu8_mask() {
+    const fn test_mm512_cmpeq_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpeq_epu8_mask(a, b);
@@ -16028,7 +16028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpeq_epu8_mask() {
+    const fn test_mm512_mask_cmpeq_epu8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -16040,7 +16040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epu8_mask() {
+    const fn test_mm256_cmpeq_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpeq_epu8_mask(a, b);
@@ -16048,7 +16048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epu8_mask() {
+    const fn test_mm256_mask_cmpeq_epu8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16057,7 +16057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epu8_mask() {
+    const fn test_mm_cmpeq_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpeq_epu8_mask(a, b);
@@ -16065,7 +16065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epu8_mask() {
+    const fn test_mm_mask_cmpeq_epu8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -16074,7 +16074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpeq_epi16_mask() {
+    const fn test_mm512_cmpeq_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpeq_epi16_mask(a, b);
@@ -16082,7 +16082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpeq_epi16_mask() {
+    const fn test_mm512_mask_cmpeq_epi16_mask() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16091,7 +16091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epi16_mask() {
+    const fn test_mm256_cmpeq_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpeq_epi16_mask(a, b);
@@ -16099,7 +16099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epi16_mask() {
+    const fn test_mm256_mask_cmpeq_epi16_mask() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -16108,7 +16108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epi16_mask() {
+    const fn test_mm_cmpeq_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpeq_epi16_mask(a, b);
@@ -16116,7 +16116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epi16_mask() {
+    const fn test_mm_mask_cmpeq_epi16_mask() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -16125,7 +16125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpeq_epi8_mask() {
+    const fn test_mm512_cmpeq_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpeq_epi8_mask(a, b);
@@ -16136,7 +16136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpeq_epi8_mask() {
+    const fn test_mm512_mask_cmpeq_epi8_mask() {
         let a = _mm512_set1_epi8(-1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -16148,7 +16148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epi8_mask() {
+    const fn test_mm256_cmpeq_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpeq_epi8_mask(a, b);
@@ -16156,7 +16156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epi8_mask() {
+    const fn test_mm256_mask_cmpeq_epi8_mask() {
         let a = _mm256_set1_epi8(-1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16165,7 +16165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epi8_mask() {
+    const fn test_mm_cmpeq_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpeq_epi8_mask(a, b);
@@ -16173,7 +16173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epi8_mask() {
+    const fn test_mm_mask_cmpeq_epi8_mask() {
         let a = _mm_set1_epi8(-1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -16182,7 +16182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpneq_epu16_mask() {
+    const fn test_mm512_cmpneq_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmpneq_epu16_mask(a, b);
@@ -16190,7 +16190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpneq_epu16_mask() {
+    const fn test_mm512_mask_cmpneq_epu16_mask() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16199,7 +16199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epu16_mask() {
+    const fn test_mm256_cmpneq_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmpneq_epu16_mask(a, b);
@@ -16207,7 +16207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epu16_mask() {
+    const fn test_mm256_mask_cmpneq_epu16_mask() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -16216,7 +16216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epu16_mask() {
+    const fn test_mm_cmpneq_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmpneq_epu16_mask(a, b);
@@ -16224,7 +16224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epu16_mask() {
+    const fn test_mm_mask_cmpneq_epu16_mask() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -16233,7 +16233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpneq_epu8_mask() {
+    const fn test_mm512_cmpneq_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmpneq_epu8_mask(a, b);
@@ -16244,7 +16244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpneq_epu8_mask() {
+    const fn test_mm512_mask_cmpneq_epu8_mask() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -16256,7 +16256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epu8_mask() {
+    const fn test_mm256_cmpneq_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmpneq_epu8_mask(a, b);
@@ -16264,7 +16264,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epu8_mask() {
+    const fn test_mm256_mask_cmpneq_epu8_mask() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16273,7 +16273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epu8_mask() {
+    const fn test_mm_cmpneq_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmpneq_epu8_mask(a, b);
@@ -16281,7 +16281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epu8_mask() {
+    const fn test_mm_mask_cmpneq_epu8_mask() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -16290,7 +16290,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpneq_epi16_mask() {
+    const fn test_mm512_cmpneq_epi16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(-1);
         let m = _mm512_cmpneq_epi16_mask(a, b);
@@ -16298,7 +16298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpneq_epi16_mask() {
+    const fn test_mm512_mask_cmpneq_epi16_mask() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16307,7 +16307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epi16_mask() {
+    const fn test_mm256_cmpneq_epi16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(-1);
         let m = _mm256_cmpneq_epi16_mask(a, b);
@@ -16315,7 +16315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epi16_mask() {
+    const fn test_mm256_mask_cmpneq_epi16_mask() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(-1);
         let mask = 0b01010101_01010101;
@@ -16324,7 +16324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epi16_mask() {
+    const fn test_mm_cmpneq_epi16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let m = _mm_cmpneq_epi16_mask(a, b);
@@ -16332,7 +16332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epi16_mask() {
+    const fn test_mm_mask_cmpneq_epi16_mask() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let mask = 0b01010101;
@@ -16341,7 +16341,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmpneq_epi8_mask() {
+    const fn test_mm512_cmpneq_epi8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(-1);
         let m = _mm512_cmpneq_epi8_mask(a, b);
@@ -16352,7 +16352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmpneq_epi8_mask() {
+    const fn test_mm512_mask_cmpneq_epi8_mask() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -16364,7 +16364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epi8_mask() {
+    const fn test_mm256_cmpneq_epi8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(-1);
         let m = _mm256_cmpneq_epi8_mask(a, b);
@@ -16372,7 +16372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epi8_mask() {
+    const fn test_mm256_mask_cmpneq_epi8_mask() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(-1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16381,7 +16381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epi8_mask() {
+    const fn test_mm_cmpneq_epi8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(-1);
         let m = _mm_cmpneq_epi8_mask(a, b);
@@ -16389,7 +16389,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epi8_mask() {
+    const fn test_mm_mask_cmpneq_epi8_mask() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(-1);
         let mask = 0b01010101_01010101;
@@ -16398,7 +16398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmp_epu16_mask() {
+    const fn test_mm512_cmp_epu16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
@@ -16406,7 +16406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmp_epu16_mask() {
+    const fn test_mm512_mask_cmp_epu16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16415,7 +16415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmp_epu16_mask() {
+    const fn test_mm256_cmp_epu16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
@@ -16423,7 +16423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epu16_mask() {
+    const fn test_mm256_mask_cmp_epu16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -16432,7 +16432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmp_epu16_mask() {
+    const fn test_mm_cmp_epu16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
@@ -16440,7 +16440,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epu16_mask() {
+    const fn test_mm_mask_cmp_epu16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -16449,7 +16449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmp_epu8_mask() {
+    const fn test_mm512_cmp_epu8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
@@ -16460,7 +16460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmp_epu8_mask() {
+    const fn test_mm512_mask_cmp_epu8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -16472,7 +16472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmp_epu8_mask() {
+    const fn test_mm256_cmp_epu8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
@@ -16480,7 +16480,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epu8_mask() {
+    const fn test_mm256_mask_cmp_epu8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16489,7 +16489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmp_epu8_mask() {
+    const fn test_mm_cmp_epu8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
@@ -16497,7 +16497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epu8_mask() {
+    const fn test_mm_mask_cmp_epu8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -16506,7 +16506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmp_epi16_mask() {
+    const fn test_mm512_cmp_epi16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let m = _mm512_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
@@ -16514,7 +16514,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmp_epi16_mask() {
+    const fn test_mm512_mask_cmp_epi16_mask() {
         let a = _mm512_set1_epi16(0);
         let b = _mm512_set1_epi16(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16523,7 +16523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmp_epi16_mask() {
+    const fn test_mm256_cmp_epi16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let m = _mm256_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
@@ -16531,7 +16531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epi16_mask() {
+    const fn test_mm256_mask_cmp_epi16_mask() {
         let a = _mm256_set1_epi16(0);
         let b = _mm256_set1_epi16(1);
         let mask = 0b01010101_01010101;
@@ -16540,7 +16540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmp_epi16_mask() {
+    const fn test_mm_cmp_epi16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let m = _mm_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
@@ -16548,7 +16548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epi16_mask() {
+    const fn test_mm_mask_cmp_epi16_mask() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let mask = 0b01010101;
@@ -16557,7 +16557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cmp_epi8_mask() {
+    const fn test_mm512_cmp_epi8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let m = _mm512_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
@@ -16568,7 +16568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cmp_epi8_mask() {
+    const fn test_mm512_mask_cmp_epi8_mask() {
         let a = _mm512_set1_epi8(0);
         let b = _mm512_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
@@ -16580,7 +16580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cmp_epi8_mask() {
+    const fn test_mm256_cmp_epi8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let m = _mm256_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
@@ -16588,7 +16588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epi8_mask() {
+    const fn test_mm256_mask_cmp_epi8_mask() {
         let a = _mm256_set1_epi8(0);
         let b = _mm256_set1_epi8(1);
         let mask = 0b01010101_01010101_01010101_01010101;
@@ -16597,7 +16597,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cmp_epi8_mask() {
+    const fn test_mm_cmp_epi8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let m = _mm_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
@@ -16605,7 +16605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epi8_mask() {
+    const fn test_mm_mask_cmp_epi8_mask() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let mask = 0b01010101_01010101;
@@ -16614,91 +16614,91 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_add_epi16() {
+    const fn test_mm256_reduce_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let e = _mm256_reduce_add_epi16(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_add_epi16() {
+    const fn test_mm256_mask_reduce_add_epi16() {
         let a = _mm256_set1_epi16(1);
         let e = _mm256_mask_reduce_add_epi16(0b11111111_00000000, a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_add_epi16() {
+    const fn test_mm_reduce_add_epi16() {
         let a = _mm_set1_epi16(1);
         let e = _mm_reduce_add_epi16(a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_add_epi16() {
+    const fn test_mm_mask_reduce_add_epi16() {
         let a = _mm_set1_epi16(1);
         let e = _mm_mask_reduce_add_epi16(0b11110000, a);
         assert_eq!(4, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_add_epi8() {
+    const fn test_mm256_reduce_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let e = _mm256_reduce_add_epi8(a);
         assert_eq!(32, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_add_epi8() {
+    const fn test_mm256_mask_reduce_add_epi8() {
         let a = _mm256_set1_epi8(1);
         let e = _mm256_mask_reduce_add_epi8(0b11111111_00000000_11111111_00000000, a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_add_epi8() {
+    const fn test_mm_reduce_add_epi8() {
         let a = _mm_set1_epi8(1);
         let e = _mm_reduce_add_epi8(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_add_epi8() {
+    const fn test_mm_mask_reduce_add_epi8() {
         let a = _mm_set1_epi8(1);
         let e = _mm_mask_reduce_add_epi8(0b11111111_00000000, a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_and_epi16() {
+    const fn test_mm256_reduce_and_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_reduce_and_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_and_epi16() {
+    const fn test_mm256_mask_reduce_and_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_mask_reduce_and_epi16(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_and_epi16() {
+    const fn test_mm_reduce_and_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_reduce_and_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_and_epi16() {
+    const fn test_mm_mask_reduce_and_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_mask_reduce_and_epi16(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_and_epi8() {
+    const fn test_mm256_reduce_and_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -16708,7 +16708,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_and_epi8() {
+    const fn test_mm256_mask_reduce_and_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -16718,49 +16718,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_and_epi8() {
+    const fn test_mm_reduce_and_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_reduce_and_epi8(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_and_epi8() {
+    const fn test_mm_mask_reduce_and_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_mask_reduce_and_epi8(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_mul_epi16() {
+    const fn test_mm256_reduce_mul_epi16() {
         let a = _mm256_set_epi16(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
         let e = _mm256_reduce_mul_epi16(a);
         assert_eq!(256, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_mul_epi16() {
+    const fn test_mm256_mask_reduce_mul_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_mask_reduce_mul_epi16(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_mul_epi16() {
+    const fn test_mm_reduce_mul_epi16() {
         let a = _mm_set_epi16(2, 2, 2, 2, 1, 1, 1, 1);
         let e = _mm_reduce_mul_epi16(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_mul_epi16() {
+    const fn test_mm_mask_reduce_mul_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_mask_reduce_mul_epi16(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_mul_epi8() {
+    const fn test_mm256_reduce_mul_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
             2, 2, 2,
@@ -16770,7 +16770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_mul_epi8() {
+    const fn test_mm256_mask_reduce_mul_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
             2, 2, 2,
@@ -16780,49 +16780,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_mul_epi8() {
+    const fn test_mm_reduce_mul_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2);
         let e = _mm_reduce_mul_epi8(a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_mul_epi8() {
+    const fn test_mm_mask_reduce_mul_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2);
         let e = _mm_mask_reduce_mul_epi8(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_max_epi16() {
+    const fn test_mm256_reduce_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_reduce_max_epi16(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_max_epi16() {
+    const fn test_mm256_mask_reduce_max_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_mask_reduce_max_epi16(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_max_epi16() {
+    const fn test_mm_reduce_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_reduce_max_epi16(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_max_epi16() {
+    const fn test_mm_mask_reduce_max_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_mask_reduce_max_epi16(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_max_epi8() {
+    const fn test_mm256_reduce_max_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16832,7 +16832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_max_epi8() {
+    const fn test_mm256_mask_reduce_max_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16842,49 +16842,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_max_epi8() {
+    const fn test_mm_reduce_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_reduce_max_epi8(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_max_epi8() {
+    const fn test_mm_mask_reduce_max_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_mask_reduce_max_epi8(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_max_epu16() {
+    const fn test_mm256_reduce_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_reduce_max_epu16(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_max_epu16() {
+    const fn test_mm256_mask_reduce_max_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_mask_reduce_max_epu16(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_max_epu16() {
+    const fn test_mm_reduce_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_reduce_max_epu16(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_max_epu16() {
+    const fn test_mm_mask_reduce_max_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_mask_reduce_max_epu16(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_max_epu8() {
+    const fn test_mm256_reduce_max_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16894,7 +16894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_max_epu8() {
+    const fn test_mm256_mask_reduce_max_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16904,49 +16904,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_max_epu8() {
+    const fn test_mm_reduce_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_reduce_max_epu8(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_max_epu8() {
+    const fn test_mm_mask_reduce_max_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_mask_reduce_max_epu8(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_min_epi16() {
+    const fn test_mm256_reduce_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_reduce_min_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_min_epi16() {
+    const fn test_mm256_mask_reduce_min_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i16 = _mm256_mask_reduce_min_epi16(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_min_epi16() {
+    const fn test_mm_reduce_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_reduce_min_epi16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_min_epi16() {
+    const fn test_mm_mask_reduce_min_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i16 = _mm_mask_reduce_min_epi16(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_min_epi8() {
+    const fn test_mm256_reduce_min_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16956,7 +16956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_min_epi8() {
+    const fn test_mm256_mask_reduce_min_epi8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -16966,49 +16966,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_min_epi8() {
+    const fn test_mm_reduce_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_reduce_min_epi8(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_min_epi8() {
+    const fn test_mm_mask_reduce_min_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i8 = _mm_mask_reduce_min_epi8(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_min_epu16() {
+    const fn test_mm256_reduce_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_reduce_min_epu16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_min_epu16() {
+    const fn test_mm256_mask_reduce_min_epu16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u16 = _mm256_mask_reduce_min_epu16(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_min_epu16() {
+    const fn test_mm_reduce_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_reduce_min_epu16(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_min_epu16() {
+    const fn test_mm_mask_reduce_min_epu16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u16 = _mm_mask_reduce_min_epu16(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_min_epu8() {
+    const fn test_mm256_reduce_min_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -17018,7 +17018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_min_epu8() {
+    const fn test_mm256_mask_reduce_min_epu8() {
         let a = _mm256_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31,
@@ -17028,49 +17028,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_min_epu8() {
+    const fn test_mm_reduce_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_reduce_min_epu8(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_min_epu8() {
+    const fn test_mm_mask_reduce_min_epu8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u8 = _mm_mask_reduce_min_epu8(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_or_epi16() {
+    const fn test_mm256_reduce_or_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_reduce_or_epi16(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_or_epi16() {
+    const fn test_mm256_mask_reduce_or_epi16() {
         let a = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm256_mask_reduce_or_epi16(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_or_epi16() {
+    const fn test_mm_reduce_or_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_reduce_or_epi16(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_or_epi16() {
+    const fn test_mm_mask_reduce_or_epi16() {
         let a = _mm_set_epi16(1, 1, 1, 1, 2, 2, 2, 2);
         let e = _mm_mask_reduce_or_epi16(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_reduce_or_epi8() {
+    const fn test_mm256_reduce_or_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -17080,7 +17080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_reduce_or_epi8() {
+    const fn test_mm256_mask_reduce_or_epi8() {
         let a = _mm256_set_epi8(
             1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -17090,14 +17090,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_reduce_or_epi8() {
+    const fn test_mm_reduce_or_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_reduce_or_epi8(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_reduce_or_epi8() {
+    const fn test_mm_mask_reduce_or_epi8() {
         let a = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e = _mm_mask_reduce_or_epi8(0b11111111_00000000, a);
         assert_eq!(1, e);
@@ -17486,7 +17486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_madd_epi16() {
+    const fn test_mm512_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_madd_epi16(a, b);
@@ -17495,7 +17495,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_madd_epi16() {
+    const fn test_mm512_mask_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_madd_epi16(a, 0, a, b);
@@ -17523,7 +17523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_madd_epi16() {
+    const fn test_mm512_maskz_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_madd_epi16(0, a, b);
@@ -17534,7 +17534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_madd_epi16() {
+    const fn test_mm256_mask_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_madd_epi16(a, 0, a, b);
@@ -17554,7 +17554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_madd_epi16() {
+    const fn test_mm256_maskz_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_madd_epi16(0, a, b);
@@ -17565,7 +17565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_madd_epi16() {
+    const fn test_mm_mask_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_madd_epi16(a, 0, a, b);
@@ -17576,7 +17576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_madd_epi16() {
+    const fn test_mm_maskz_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_madd_epi16(0, a, b);
@@ -17587,7 +17587,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maddubs_epi16() {
+    fn test_mm512_maddubs_epi16() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_maddubs_epi16(a, b);
@@ -17596,7 +17596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_maddubs_epi16() {
+    fn test_mm512_mask_maddubs_epi16() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let src = _mm512_set1_epi16(1);
@@ -17610,7 +17610,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_maddubs_epi16() {
+    fn test_mm512_maskz_maddubs_epi16() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_maskz_maddubs_epi16(0, a, b);
@@ -17623,7 +17623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_maddubs_epi16() {
+    fn test_mm256_mask_maddubs_epi16() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let src = _mm256_set1_epi16(1);
@@ -17635,7 +17635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_maddubs_epi16() {
+    fn test_mm256_maskz_maddubs_epi16() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_maskz_maddubs_epi16(0, a, b);
@@ -17646,7 +17646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_maddubs_epi16() {
+    fn test_mm_mask_maddubs_epi16() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let src = _mm_set1_epi16(1);
@@ -17658,7 +17658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_maddubs_epi16() {
+    fn test_mm_maskz_maddubs_epi16() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_maskz_maddubs_epi16(0, a, b);
@@ -17669,7 +17669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_packs_epi32() {
+    fn test_mm512_packs_epi32() {
         let a = _mm512_set1_epi32(i32::MAX);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_packs_epi32(a, b);
@@ -17680,7 +17680,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_packs_epi32() {
+    fn test_mm512_mask_packs_epi32() {
         let a = _mm512_set1_epi32(i32::MAX);
         let b = _mm512_set1_epi32(1 << 16 | 1);
         let r = _mm512_mask_packs_epi32(a, 0, a, b);
@@ -17693,7 +17693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_packs_epi32() {
+    fn test_mm512_maskz_packs_epi32() {
         let a = _mm512_set1_epi32(i32::MAX);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_packs_epi32(0, a, b);
@@ -17706,7 +17706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_packs_epi32() {
+    fn test_mm256_mask_packs_epi32() {
         let a = _mm256_set1_epi32(i32::MAX);
         let b = _mm256_set1_epi32(1 << 16 | 1);
         let r = _mm256_mask_packs_epi32(a, 0, a, b);
@@ -17718,7 +17718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_packs_epi32() {
+    fn test_mm256_maskz_packs_epi32() {
         let a = _mm256_set1_epi32(i32::MAX);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_packs_epi32(0, a, b);
@@ -17730,7 +17730,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_packs_epi32() {
+    fn test_mm_mask_packs_epi32() {
         let a = _mm_set1_epi32(i32::MAX);
         let b = _mm_set1_epi32(1 << 16 | 1);
         let r = _mm_mask_packs_epi32(a, 0, a, b);
@@ -17741,7 +17741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_packs_epi32() {
+    fn test_mm_maskz_packs_epi32() {
         let a = _mm_set1_epi32(i32::MAX);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_packs_epi32(0, a, b);
@@ -17752,7 +17752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_packs_epi16() {
+    fn test_mm512_packs_epi16() {
         let a = _mm512_set1_epi16(i16::MAX);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_packs_epi16(a, b);
@@ -17765,7 +17765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_packs_epi16() {
+    fn test_mm512_mask_packs_epi16() {
         let a = _mm512_set1_epi16(i16::MAX);
         let b = _mm512_set1_epi16(1 << 8 | 1);
         let r = _mm512_mask_packs_epi16(a, 0, a, b);
@@ -17785,7 +17785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_packs_epi16() {
+    fn test_mm512_maskz_packs_epi16() {
         let a = _mm512_set1_epi16(i16::MAX);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_packs_epi16(0, a, b);
@@ -17804,7 +17804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_packs_epi16() {
+    fn test_mm256_mask_packs_epi16() {
         let a = _mm256_set1_epi16(i16::MAX);
         let b = _mm256_set1_epi16(1 << 8 | 1);
         let r = _mm256_mask_packs_epi16(a, 0, a, b);
@@ -17817,7 +17817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_packs_epi16() {
+    fn test_mm256_maskz_packs_epi16() {
         let a = _mm256_set1_epi16(i16::MAX);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_packs_epi16(0, a, b);
@@ -17830,7 +17830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_packs_epi16() {
+    fn test_mm_mask_packs_epi16() {
         let a = _mm_set1_epi16(i16::MAX);
         let b = _mm_set1_epi16(1 << 8 | 1);
         let r = _mm_mask_packs_epi16(a, 0, a, b);
@@ -17842,7 +17842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_packs_epi16() {
+    fn test_mm_maskz_packs_epi16() {
         let a = _mm_set1_epi16(i16::MAX);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_packs_epi16(0, a, b);
@@ -17854,7 +17854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_packus_epi32() {
+    fn test_mm512_packus_epi32() {
         let a = _mm512_set1_epi32(-1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_packus_epi32(a, b);
@@ -17865,7 +17865,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_packus_epi32() {
+    fn test_mm512_mask_packus_epi32() {
         let a = _mm512_set1_epi32(-1);
         let b = _mm512_set1_epi32(1 << 16 | 1);
         let r = _mm512_mask_packus_epi32(a, 0, a, b);
@@ -17878,7 +17878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_packus_epi32() {
+    fn test_mm512_maskz_packus_epi32() {
         let a = _mm512_set1_epi32(-1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_packus_epi32(0, a, b);
@@ -17891,7 +17891,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_packus_epi32() {
+    fn test_mm256_mask_packus_epi32() {
         let a = _mm256_set1_epi32(-1);
         let b = _mm256_set1_epi32(1 << 16 | 1);
         let r = _mm256_mask_packus_epi32(a, 0, a, b);
@@ -17902,7 +17902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_packus_epi32() {
+    fn test_mm256_maskz_packus_epi32() {
         let a = _mm256_set1_epi32(-1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_packus_epi32(0, a, b);
@@ -17913,7 +17913,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_packus_epi32() {
+    fn test_mm_mask_packus_epi32() {
         let a = _mm_set1_epi32(-1);
         let b = _mm_set1_epi32(1 << 16 | 1);
         let r = _mm_mask_packus_epi32(a, 0, a, b);
@@ -17924,7 +17924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_packus_epi32() {
+    fn test_mm_maskz_packus_epi32() {
         let a = _mm_set1_epi32(-1);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_packus_epi32(0, a, b);
@@ -17935,7 +17935,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_packus_epi16() {
+    fn test_mm512_packus_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_packus_epi16(a, b);
@@ -17948,7 +17948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_packus_epi16() {
+    fn test_mm512_mask_packus_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(1 << 8 | 1);
         let r = _mm512_mask_packus_epi16(a, 0, a, b);
@@ -17968,7 +17968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_packus_epi16() {
+    fn test_mm512_maskz_packus_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_packus_epi16(0, a, b);
@@ -17987,7 +17987,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_packus_epi16() {
+    fn test_mm256_mask_packus_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(1 << 8 | 1);
         let r = _mm256_mask_packus_epi16(a, 0, a, b);
@@ -18000,7 +18000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_packus_epi16() {
+    fn test_mm256_maskz_packus_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_packus_epi16(0, a, b);
@@ -18013,7 +18013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_packus_epi16() {
+    fn test_mm_mask_packus_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(1 << 8 | 1);
         let r = _mm_mask_packus_epi16(a, 0, a, b);
@@ -18024,7 +18024,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_packus_epi16() {
+    fn test_mm_maskz_packus_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_packus_epi16(0, a, b);
@@ -18035,7 +18035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_avg_epu16() {
+    const fn test_mm512_avg_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_avg_epu16(a, b);
@@ -18044,7 +18044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_avg_epu16() {
+    const fn test_mm512_mask_avg_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_avg_epu16(a, 0, a, b);
@@ -18057,7 +18057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_avg_epu16() {
+    const fn test_mm512_maskz_avg_epu16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_avg_epu16(0, a, b);
@@ -18070,7 +18070,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_avg_epu16() {
+    const fn test_mm256_mask_avg_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_avg_epu16(a, 0, a, b);
@@ -18081,7 +18081,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_avg_epu16() {
+    const fn test_mm256_maskz_avg_epu16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_avg_epu16(0, a, b);
@@ -18092,7 +18092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_avg_epu16() {
+    const fn test_mm_mask_avg_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_avg_epu16(a, 0, a, b);
@@ -18103,7 +18103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_avg_epu16() {
+    const fn test_mm_maskz_avg_epu16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_avg_epu16(0, a, b);
@@ -18114,7 +18114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_avg_epu8() {
+    const fn test_mm512_avg_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_avg_epu8(a, b);
@@ -18123,7 +18123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_avg_epu8() {
+    const fn test_mm512_mask_avg_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_mask_avg_epu8(a, 0, a, b);
@@ -18143,7 +18143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_avg_epu8() {
+    const fn test_mm512_maskz_avg_epu8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_maskz_avg_epu8(0, a, b);
@@ -18162,7 +18162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_avg_epu8() {
+    const fn test_mm256_mask_avg_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_mask_avg_epu8(a, 0, a, b);
@@ -18175,7 +18175,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_avg_epu8() {
+    const fn test_mm256_maskz_avg_epu8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_maskz_avg_epu8(0, a, b);
@@ -18188,7 +18188,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_avg_epu8() {
+    const fn test_mm_mask_avg_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_mask_avg_epu8(a, 0, a, b);
@@ -18199,7 +18199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_avg_epu8() {
+    const fn test_mm_maskz_avg_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_maskz_avg_epu8(0, a, b);
@@ -18210,7 +18210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_sll_epi16() {
+    fn test_mm512_sll_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm512_sll_epi16(a, count);
@@ -18219,7 +18219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_sll_epi16() {
+    fn test_mm512_mask_sll_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm512_mask_sll_epi16(a, 0, a, count);
@@ -18230,7 +18230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_sll_epi16() {
+    fn test_mm512_maskz_sll_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm512_maskz_sll_epi16(0, a, count);
@@ -18241,7 +18241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_sll_epi16() {
+    fn test_mm256_mask_sll_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm256_mask_sll_epi16(a, 0, a, count);
@@ -18252,7 +18252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_sll_epi16() {
+    fn test_mm256_maskz_sll_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm256_maskz_sll_epi16(0, a, count);
@@ -18263,7 +18263,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_sll_epi16() {
+    fn test_mm_mask_sll_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_sll_epi16(a, 0, a, count);
@@ -18274,7 +18274,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_sll_epi16() {
+    fn test_mm_maskz_sll_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_sll_epi16(0, a, count);
@@ -18285,7 +18285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_slli_epi16() {
+    const fn test_mm512_slli_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_slli_epi16::<1>(a);
         let e = _mm512_set1_epi16(0);
@@ -18293,7 +18293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_slli_epi16() {
+    const fn test_mm512_mask_slli_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_mask_slli_epi16::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -18303,7 +18303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_slli_epi16() {
+    const fn test_mm512_maskz_slli_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_maskz_slli_epi16::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -18313,7 +18313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_slli_epi16() {
+    const fn test_mm256_mask_slli_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let r = _mm256_mask_slli_epi16::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -18323,7 +18323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_slli_epi16() {
+    const fn test_mm256_maskz_slli_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let r = _mm256_maskz_slli_epi16::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -18333,7 +18333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_slli_epi16() {
+    const fn test_mm_mask_slli_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let r = _mm_mask_slli_epi16::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -18343,7 +18343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_slli_epi16() {
+    const fn test_mm_maskz_slli_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let r = _mm_maskz_slli_epi16::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -18353,7 +18353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_sllv_epi16() {
+    const fn test_mm512_sllv_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_sllv_epi16(a, count);
@@ -18362,7 +18362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_sllv_epi16() {
+    const fn test_mm512_mask_sllv_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_mask_sllv_epi16(a, 0, a, count);
@@ -18373,7 +18373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_sllv_epi16() {
+    const fn test_mm512_maskz_sllv_epi16() {
         let a = _mm512_set1_epi16(1 << 15);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_maskz_sllv_epi16(0, a, count);
@@ -18384,7 +18384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_sllv_epi16() {
+    const fn test_mm256_sllv_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_sllv_epi16(a, count);
@@ -18393,7 +18393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_sllv_epi16() {
+    const fn test_mm256_mask_sllv_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_mask_sllv_epi16(a, 0, a, count);
@@ -18404,7 +18404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_sllv_epi16() {
+    const fn test_mm256_maskz_sllv_epi16() {
         let a = _mm256_set1_epi16(1 << 15);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_maskz_sllv_epi16(0, a, count);
@@ -18415,7 +18415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_sllv_epi16() {
+    const fn test_mm_sllv_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_sllv_epi16(a, count);
@@ -18424,7 +18424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_sllv_epi16() {
+    const fn test_mm_mask_sllv_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_sllv_epi16(a, 0, a, count);
@@ -18435,7 +18435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_sllv_epi16() {
+    const fn test_mm_maskz_sllv_epi16() {
         let a = _mm_set1_epi16(1 << 15);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_sllv_epi16(0, a, count);
@@ -18446,7 +18446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_srl_epi16() {
+    fn test_mm512_srl_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm512_srl_epi16(a, count);
@@ -18455,7 +18455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_srl_epi16() {
+    fn test_mm512_mask_srl_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm512_mask_srl_epi16(a, 0, a, count);
@@ -18466,7 +18466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_srl_epi16() {
+    fn test_mm512_maskz_srl_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm512_maskz_srl_epi16(0, a, count);
@@ -18477,7 +18477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_srl_epi16() {
+    fn test_mm256_mask_srl_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm256_mask_srl_epi16(a, 0, a, count);
@@ -18488,7 +18488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_srl_epi16() {
+    fn test_mm256_maskz_srl_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm256_maskz_srl_epi16(0, a, count);
@@ -18499,7 +18499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_srl_epi16() {
+    fn test_mm_mask_srl_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_srl_epi16(a, 0, a, count);
@@ -18510,7 +18510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_srl_epi16() {
+    fn test_mm_maskz_srl_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_srl_epi16(0, a, count);
@@ -18521,7 +18521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_srli_epi16() {
+    const fn test_mm512_srli_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let r = _mm512_srli_epi16::<2>(a);
         let e = _mm512_set1_epi16(0);
@@ -18529,7 +18529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_srli_epi16() {
+    const fn test_mm512_mask_srli_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let r = _mm512_mask_srli_epi16::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -18539,7 +18539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_srli_epi16() {
+    const fn test_mm512_maskz_srli_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let r = _mm512_maskz_srli_epi16::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -18549,7 +18549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_srli_epi16() {
+    const fn test_mm256_mask_srli_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let r = _mm256_mask_srli_epi16::<2>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -18559,7 +18559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_srli_epi16() {
+    const fn test_mm256_maskz_srli_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let r = _mm256_maskz_srli_epi16::<2>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -18569,7 +18569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_srli_epi16() {
+    const fn test_mm_mask_srli_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let r = _mm_mask_srli_epi16::<2>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -18579,7 +18579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_srli_epi16() {
+    const fn test_mm_maskz_srli_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let r = _mm_maskz_srli_epi16::<2>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -18589,7 +18589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_srlv_epi16() {
+    const fn test_mm512_srlv_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_srlv_epi16(a, count);
@@ -18598,7 +18598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_srlv_epi16() {
+    const fn test_mm512_mask_srlv_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_mask_srlv_epi16(a, 0, a, count);
@@ -18609,7 +18609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_srlv_epi16() {
+    const fn test_mm512_maskz_srlv_epi16() {
         let a = _mm512_set1_epi16(1 << 1);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_maskz_srlv_epi16(0, a, count);
@@ -18620,7 +18620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_srlv_epi16() {
+    const fn test_mm256_srlv_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_srlv_epi16(a, count);
@@ -18629,7 +18629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_srlv_epi16() {
+    const fn test_mm256_mask_srlv_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_mask_srlv_epi16(a, 0, a, count);
@@ -18640,7 +18640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_srlv_epi16() {
+    const fn test_mm256_maskz_srlv_epi16() {
         let a = _mm256_set1_epi16(1 << 1);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_maskz_srlv_epi16(0, a, count);
@@ -18651,7 +18651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_srlv_epi16() {
+    const fn test_mm_srlv_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_srlv_epi16(a, count);
@@ -18660,7 +18660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_srlv_epi16() {
+    const fn test_mm_mask_srlv_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_srlv_epi16(a, 0, a, count);
@@ -18671,7 +18671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_srlv_epi16() {
+    const fn test_mm_maskz_srlv_epi16() {
         let a = _mm_set1_epi16(1 << 1);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_srlv_epi16(0, a, count);
@@ -18682,7 +18682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_sra_epi16() {
+    fn test_mm512_sra_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm512_sra_epi16(a, count);
@@ -18691,7 +18691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_sra_epi16() {
+    fn test_mm512_mask_sra_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm512_mask_sra_epi16(a, 0, a, count);
@@ -18702,7 +18702,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_sra_epi16() {
+    fn test_mm512_maskz_sra_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm512_maskz_sra_epi16(0, a, count);
@@ -18713,7 +18713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_sra_epi16() {
+    fn test_mm256_mask_sra_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm256_mask_sra_epi16(a, 0, a, count);
@@ -18724,7 +18724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_sra_epi16() {
+    fn test_mm256_maskz_sra_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm256_maskz_sra_epi16(0, a, count);
@@ -18735,7 +18735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_sra_epi16() {
+    fn test_mm_mask_sra_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm_mask_sra_epi16(a, 0, a, count);
@@ -18746,7 +18746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_sra_epi16() {
+    fn test_mm_maskz_sra_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(1);
         let r = _mm_maskz_sra_epi16(0, a, count);
@@ -18757,7 +18757,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_srai_epi16() {
+    const fn test_mm512_srai_epi16() {
         let a = _mm512_set1_epi16(8);
         let r = _mm512_srai_epi16::<2>(a);
         let e = _mm512_set1_epi16(2);
@@ -18765,7 +18765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_srai_epi16() {
+    const fn test_mm512_mask_srai_epi16() {
         let a = _mm512_set1_epi16(8);
         let r = _mm512_mask_srai_epi16::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -18775,7 +18775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_srai_epi16() {
+    const fn test_mm512_maskz_srai_epi16() {
         let a = _mm512_set1_epi16(8);
         let r = _mm512_maskz_srai_epi16::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -18785,7 +18785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_srai_epi16() {
+    const fn test_mm256_mask_srai_epi16() {
         let a = _mm256_set1_epi16(8);
         let r = _mm256_mask_srai_epi16::<2>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -18795,7 +18795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_srai_epi16() {
+    const fn test_mm256_maskz_srai_epi16() {
         let a = _mm256_set1_epi16(8);
         let r = _mm256_maskz_srai_epi16::<2>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -18805,7 +18805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_srai_epi16() {
+    const fn test_mm_mask_srai_epi16() {
         let a = _mm_set1_epi16(8);
         let r = _mm_mask_srai_epi16::<2>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -18815,7 +18815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_srai_epi16() {
+    const fn test_mm_maskz_srai_epi16() {
         let a = _mm_set1_epi16(8);
         let r = _mm_maskz_srai_epi16::<2>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -18825,7 +18825,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_srav_epi16() {
+    const fn test_mm512_srav_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_srav_epi16(a, count);
@@ -18834,7 +18834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_srav_epi16() {
+    const fn test_mm512_mask_srav_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_mask_srav_epi16(a, 0, a, count);
@@ -18845,7 +18845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_srav_epi16() {
+    const fn test_mm512_maskz_srav_epi16() {
         let a = _mm512_set1_epi16(8);
         let count = _mm512_set1_epi16(2);
         let r = _mm512_maskz_srav_epi16(0, a, count);
@@ -18856,7 +18856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_srav_epi16() {
+    const fn test_mm256_srav_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_srav_epi16(a, count);
@@ -18865,7 +18865,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_srav_epi16() {
+    const fn test_mm256_mask_srav_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_mask_srav_epi16(a, 0, a, count);
@@ -18876,7 +18876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_srav_epi16() {
+    const fn test_mm256_maskz_srav_epi16() {
         let a = _mm256_set1_epi16(8);
         let count = _mm256_set1_epi16(2);
         let r = _mm256_maskz_srav_epi16(0, a, count);
@@ -18887,7 +18887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_srav_epi16() {
+    const fn test_mm_srav_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(2);
         let r = _mm_srav_epi16(a, count);
@@ -18896,7 +18896,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_srav_epi16() {
+    const fn test_mm_mask_srav_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(2);
         let r = _mm_mask_srav_epi16(a, 0, a, count);
@@ -18907,7 +18907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_srav_epi16() {
+    const fn test_mm_maskz_srav_epi16() {
         let a = _mm_set1_epi16(8);
         let count = _mm_set1_epi16(2);
         let r = _mm_maskz_srav_epi16(0, a, count);
@@ -18918,7 +18918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_permutex2var_epi16() {
+    fn test_mm512_permutex2var_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -18936,7 +18936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_permutex2var_epi16() {
+    fn test_mm512_mask_permutex2var_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -18956,7 +18956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_permutex2var_epi16() {
+    fn test_mm512_maskz_permutex2var_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -18976,7 +18976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask2_permutex2var_epi16() {
+    fn test_mm512_mask2_permutex2var_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -18996,7 +18996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_permutex2var_epi16() {
+    fn test_mm256_permutex2var_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
@@ -19009,7 +19009,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_permutex2var_epi16() {
+    fn test_mm256_mask_permutex2var_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
@@ -19024,7 +19024,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex2var_epi16() {
+    fn test_mm256_maskz_permutex2var_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
@@ -19039,7 +19039,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask2_permutex2var_epi16() {
+    fn test_mm256_mask2_permutex2var_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
@@ -19055,7 +19055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_permutex2var_epi16() {
+    fn test_mm_permutex2var_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm_set1_epi16(100);
@@ -19065,7 +19065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_permutex2var_epi16() {
+    fn test_mm_mask_permutex2var_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm_set1_epi16(100);
@@ -19077,7 +19077,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_permutex2var_epi16() {
+    fn test_mm_maskz_permutex2var_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm_set1_epi16(100);
@@ -19089,7 +19089,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask2_permutex2var_epi16() {
+    fn test_mm_mask2_permutex2var_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm_set1_epi16(100);
@@ -19101,7 +19101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_permutexvar_epi16() {
+    fn test_mm512_permutexvar_epi16() {
         let idx = _mm512_set1_epi16(1);
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -19112,7 +19112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_permutexvar_epi16() {
+    fn test_mm512_mask_permutexvar_epi16() {
         let idx = _mm512_set1_epi16(1);
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -19125,7 +19125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_permutexvar_epi16() {
+    fn test_mm512_maskz_permutexvar_epi16() {
         let idx = _mm512_set1_epi16(1);
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -19138,7 +19138,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_permutexvar_epi16() {
+    fn test_mm256_permutexvar_epi16() {
         let idx = _mm256_set1_epi16(1);
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_permutexvar_epi16(idx, a);
@@ -19147,7 +19147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_permutexvar_epi16() {
+    fn test_mm256_mask_permutexvar_epi16() {
         let idx = _mm256_set1_epi16(1);
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_permutexvar_epi16(a, 0, idx, a);
@@ -19158,7 +19158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_permutexvar_epi16() {
+    fn test_mm256_maskz_permutexvar_epi16() {
         let idx = _mm256_set1_epi16(1);
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_permutexvar_epi16(0, idx, a);
@@ -19169,7 +19169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_permutexvar_epi16() {
+    fn test_mm_permutexvar_epi16() {
         let idx = _mm_set1_epi16(1);
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_permutexvar_epi16(idx, a);
@@ -19178,7 +19178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_permutexvar_epi16() {
+    fn test_mm_mask_permutexvar_epi16() {
         let idx = _mm_set1_epi16(1);
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_permutexvar_epi16(a, 0, idx, a);
@@ -19189,7 +19189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_permutexvar_epi16() {
+    fn test_mm_maskz_permutexvar_epi16() {
         let idx = _mm_set1_epi16(1);
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_permutexvar_epi16(0, idx, a);
@@ -19200,7 +19200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_blend_epi16() {
+    const fn test_mm512_mask_blend_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(2);
         let r = _mm512_mask_blend_epi16(0b11111111_00000000_11111111_00000000, a, b);
@@ -19211,7 +19211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_epi16() {
+    const fn test_mm256_mask_blend_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(2);
         let r = _mm256_mask_blend_epi16(0b11111111_00000000, a, b);
@@ -19220,7 +19220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_blend_epi16() {
+    const fn test_mm_mask_blend_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(2);
         let r = _mm_mask_blend_epi16(0b11110000, a, b);
@@ -19229,7 +19229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_blend_epi8() {
+    const fn test_mm512_mask_blend_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(2);
         let r = _mm512_mask_blend_epi8(
@@ -19246,7 +19246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_epi8() {
+    const fn test_mm256_mask_blend_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(2);
         let r = _mm256_mask_blend_epi8(0b11111111_00000000_11111111_00000000, a, b);
@@ -19257,7 +19257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_blend_epi8() {
+    const fn test_mm_mask_blend_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(2);
         let r = _mm_mask_blend_epi8(0b11111111_00000000, a, b);
@@ -19266,7 +19266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_broadcastw_epi16() {
+    const fn test_mm512_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_broadcastw_epi16(a);
         let e = _mm512_set1_epi16(24);
@@ -19274,7 +19274,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_broadcastw_epi16() {
+    const fn test_mm512_mask_broadcastw_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_broadcastw_epi16(src, 0, a);
@@ -19285,7 +19285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_broadcastw_epi16() {
+    const fn test_mm512_maskz_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_broadcastw_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19295,7 +19295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcastw_epi16() {
+    const fn test_mm256_mask_broadcastw_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_mask_broadcastw_epi16(src, 0, a);
@@ -19306,7 +19306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcastw_epi16() {
+    const fn test_mm256_maskz_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_maskz_broadcastw_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19316,7 +19316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_broadcastw_epi16() {
+    const fn test_mm_mask_broadcastw_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm_mask_broadcastw_epi16(src, 0, a);
@@ -19327,7 +19327,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_broadcastw_epi16() {
+    const fn test_mm_maskz_broadcastw_epi16() {
         let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm_maskz_broadcastw_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19337,7 +19337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_broadcastb_epi8() {
+    const fn test_mm512_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -19347,7 +19347,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_broadcastb_epi8() {
+    const fn test_mm512_mask_broadcastb_epi8() {
         let src = _mm512_set1_epi8(1);
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19364,7 +19364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_broadcastb_epi8() {
+    const fn test_mm512_maskz_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -19379,7 +19379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcastb_epi8() {
+    const fn test_mm256_mask_broadcastb_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19392,7 +19392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcastb_epi8() {
+    const fn test_mm256_maskz_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -19404,7 +19404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_broadcastb_epi8() {
+    const fn test_mm_mask_broadcastb_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19417,7 +19417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_broadcastb_epi8() {
+    const fn test_mm_maskz_broadcastb_epi8() {
         let a = _mm_set_epi8(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
         );
@@ -19429,7 +19429,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_unpackhi_epi16() {
+    const fn test_mm512_unpackhi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19444,7 +19444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_unpackhi_epi16() {
+    const fn test_mm512_mask_unpackhi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19461,7 +19461,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_unpackhi_epi16() {
+    const fn test_mm512_maskz_unpackhi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19478,7 +19478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_unpackhi_epi16() {
+    const fn test_mm256_mask_unpackhi_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -19491,7 +19491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpackhi_epi16() {
+    const fn test_mm256_maskz_unpackhi_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -19504,7 +19504,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_unpackhi_epi16() {
+    const fn test_mm_mask_unpackhi_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_mask_unpackhi_epi16(a, 0, a, b);
@@ -19515,7 +19515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_unpackhi_epi16() {
+    const fn test_mm_maskz_unpackhi_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_maskz_unpackhi_epi16(0, a, b);
@@ -19526,7 +19526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_unpackhi_epi8() {
+    const fn test_mm512_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19547,7 +19547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_unpackhi_epi8() {
+    const fn test_mm512_mask_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19575,7 +19575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_unpackhi_epi8() {
+    const fn test_mm512_maskz_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19602,7 +19602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_unpackhi_epi8() {
+    const fn test_mm256_mask_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19619,7 +19619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpackhi_epi8() {
+    const fn test_mm256_maskz_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19636,7 +19636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_unpackhi_epi8() {
+    const fn test_mm_mask_unpackhi_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -19649,7 +19649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_unpackhi_epi8() {
+    const fn test_mm_maskz_unpackhi_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -19662,7 +19662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_unpacklo_epi16() {
+    const fn test_mm512_unpacklo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19677,7 +19677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_unpacklo_epi16() {
+    const fn test_mm512_mask_unpacklo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19694,7 +19694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_unpacklo_epi16() {
+    const fn test_mm512_maskz_unpacklo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19711,7 +19711,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_unpacklo_epi16() {
+    const fn test_mm256_mask_unpacklo_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -19724,7 +19724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpacklo_epi16() {
+    const fn test_mm256_maskz_unpacklo_epi16() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi16(
             33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
@@ -19737,7 +19737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_unpacklo_epi16() {
+    const fn test_mm_mask_unpacklo_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_mask_unpacklo_epi16(a, 0, a, b);
@@ -19748,7 +19748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_unpacklo_epi16() {
+    const fn test_mm_maskz_unpacklo_epi16() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
         let r = _mm_maskz_unpacklo_epi16(0, a, b);
@@ -19759,7 +19759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_unpacklo_epi8() {
+    const fn test_mm512_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19780,7 +19780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_unpacklo_epi8() {
+    const fn test_mm512_mask_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19808,7 +19808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_unpacklo_epi8() {
+    const fn test_mm512_maskz_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -19835,7 +19835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_unpacklo_epi8() {
+    const fn test_mm256_mask_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19852,7 +19852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpacklo_epi8() {
+    const fn test_mm256_maskz_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16,
                                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
@@ -19869,7 +19869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_unpacklo_epi8() {
+    const fn test_mm_mask_unpacklo_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -19884,7 +19884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_unpacklo_epi8() {
+    const fn test_mm_maskz_unpacklo_epi8() {
         let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_set_epi8(
             65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
@@ -19899,7 +19899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_mov_epi16() {
+    const fn test_mm512_mask_mov_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm512_set1_epi16(2);
         let r = _mm512_mask_mov_epi16(src, 0, a);
@@ -19909,7 +19909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_mov_epi16() {
+    const fn test_mm512_maskz_mov_epi16() {
         let a = _mm512_set1_epi16(2);
         let r = _mm512_maskz_mov_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19918,7 +19918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_mov_epi16() {
+    const fn test_mm256_mask_mov_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm256_set1_epi16(2);
         let r = _mm256_mask_mov_epi16(src, 0, a);
@@ -19928,7 +19928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_mov_epi16() {
+    const fn test_mm256_maskz_mov_epi16() {
         let a = _mm256_set1_epi16(2);
         let r = _mm256_maskz_mov_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -19937,7 +19937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_mov_epi16() {
+    const fn test_mm_mask_mov_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi16(2);
         let r = _mm_mask_mov_epi16(src, 0, a);
@@ -19947,7 +19947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_mov_epi16() {
+    const fn test_mm_maskz_mov_epi16() {
         let a = _mm_set1_epi16(2);
         let r = _mm_maskz_mov_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -19956,7 +19956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_mov_epi8() {
+    const fn test_mm512_mask_mov_epi8() {
         let src = _mm512_set1_epi8(1);
         let a = _mm512_set1_epi8(2);
         let r = _mm512_mask_mov_epi8(src, 0, a);
@@ -19970,7 +19970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_mov_epi8() {
+    const fn test_mm512_maskz_mov_epi8() {
         let a = _mm512_set1_epi8(2);
         let r = _mm512_maskz_mov_epi8(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -19982,7 +19982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_mov_epi8() {
+    const fn test_mm256_mask_mov_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm256_set1_epi8(2);
         let r = _mm256_mask_mov_epi8(src, 0, a);
@@ -19992,7 +19992,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_mov_epi8() {
+    const fn test_mm256_maskz_mov_epi8() {
         let a = _mm256_set1_epi8(2);
         let r = _mm256_maskz_mov_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20001,7 +20001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_mov_epi8() {
+    const fn test_mm_mask_mov_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm_set1_epi8(2);
         let r = _mm_mask_mov_epi8(src, 0, a);
@@ -20011,7 +20011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_mov_epi8() {
+    const fn test_mm_maskz_mov_epi8() {
         let a = _mm_set1_epi8(2);
         let r = _mm_maskz_mov_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20020,7 +20020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_set1_epi16() {
+    const fn test_mm512_mask_set1_epi16() {
         let src = _mm512_set1_epi16(2);
         let a: i16 = 11;
         let r = _mm512_mask_set1_epi16(src, 0, a);
@@ -20031,7 +20031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_set1_epi16() {
+    const fn test_mm512_maskz_set1_epi16() {
         let a: i16 = 11;
         let r = _mm512_maskz_set1_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -20041,7 +20041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_set1_epi16() {
+    const fn test_mm256_mask_set1_epi16() {
         let src = _mm256_set1_epi16(2);
         let a: i16 = 11;
         let r = _mm256_mask_set1_epi16(src, 0, a);
@@ -20052,7 +20052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_set1_epi16() {
+    const fn test_mm256_maskz_set1_epi16() {
         let a: i16 = 11;
         let r = _mm256_maskz_set1_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20062,7 +20062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_set1_epi16() {
+    const fn test_mm_mask_set1_epi16() {
         let src = _mm_set1_epi16(2);
         let a: i16 = 11;
         let r = _mm_mask_set1_epi16(src, 0, a);
@@ -20073,7 +20073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_set1_epi16() {
+    const fn test_mm_maskz_set1_epi16() {
         let a: i16 = 11;
         let r = _mm_maskz_set1_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20083,7 +20083,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_set1_epi8() {
+    const fn test_mm512_mask_set1_epi8() {
         let src = _mm512_set1_epi8(2);
         let a: i8 = 11;
         let r = _mm512_mask_set1_epi8(src, 0, a);
@@ -20098,7 +20098,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_set1_epi8() {
+    const fn test_mm512_maskz_set1_epi8() {
         let a: i8 = 11;
         let r = _mm512_maskz_set1_epi8(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -20111,7 +20111,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_set1_epi8() {
+    const fn test_mm256_mask_set1_epi8() {
         let src = _mm256_set1_epi8(2);
         let a: i8 = 11;
         let r = _mm256_mask_set1_epi8(src, 0, a);
@@ -20122,7 +20122,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_set1_epi8() {
+    const fn test_mm256_maskz_set1_epi8() {
         let a: i8 = 11;
         let r = _mm256_maskz_set1_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20132,7 +20132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_set1_epi8() {
+    const fn test_mm_mask_set1_epi8() {
         let src = _mm_set1_epi8(2);
         let a: i8 = 11;
         let r = _mm_mask_set1_epi8(src, 0, a);
@@ -20143,7 +20143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_set1_epi8() {
+    const fn test_mm_maskz_set1_epi8() {
         let a: i8 = 11;
         let r = _mm_maskz_set1_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20153,7 +20153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_shufflelo_epi16() {
+    const fn test_mm512_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -20169,7 +20169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_shufflelo_epi16() {
+    const fn test_mm512_mask_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -20191,7 +20191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_shufflelo_epi16() {
+    const fn test_mm512_maskz_shufflelo_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -20210,7 +20210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_shufflelo_epi16() {
+    const fn test_mm256_mask_shufflelo_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -20220,7 +20220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_shufflelo_epi16() {
+    const fn test_mm256_maskz_shufflelo_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20230,7 +20230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_shufflelo_epi16() {
+    const fn test_mm_mask_shufflelo_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -20240,7 +20240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_shufflelo_epi16() {
+    const fn test_mm_maskz_shufflelo_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20250,7 +20250,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_shufflehi_epi16() {
+    const fn test_mm512_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -20266,7 +20266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_shufflehi_epi16() {
+    const fn test_mm512_mask_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -20288,7 +20288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_shufflehi_epi16() {
+    const fn test_mm512_maskz_shufflehi_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -20307,7 +20307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_shufflehi_epi16() {
+    const fn test_mm256_mask_shufflehi_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -20317,7 +20317,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_shufflehi_epi16() {
+    const fn test_mm256_maskz_shufflehi_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -20327,7 +20327,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_shufflehi_epi16() {
+    const fn test_mm_mask_shufflehi_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -20337,7 +20337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_shufflehi_epi16() {
+    const fn test_mm_maskz_shufflehi_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -20347,7 +20347,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_shuffle_epi8() {
+    fn test_mm512_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -20364,7 +20364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_shuffle_epi8() {
+    fn test_mm512_mask_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -20388,7 +20388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_shuffle_epi8() {
+    fn test_mm512_maskz_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -20411,7 +20411,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_shuffle_epi8() {
+    fn test_mm256_mask_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -20426,7 +20426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_shuffle_epi8() {
+    fn test_mm256_maskz_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -20441,7 +20441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_shuffle_epi8() {
+    fn test_mm_mask_shuffle_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_set1_epi8(1);
         let r = _mm_mask_shuffle_epi8(a, 0, a, b);
@@ -20454,7 +20454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_shuffle_epi8() {
+    fn test_mm_maskz_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15);
         let b = _mm_set1_epi8(1);
@@ -20468,7 +20468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_test_epi16_mask() {
+    const fn test_mm512_test_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_test_epi16_mask(a, b);
@@ -20477,7 +20477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_test_epi16_mask() {
+    const fn test_mm512_mask_test_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi16_mask(0, a, b);
@@ -20488,7 +20488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_test_epi16_mask() {
+    const fn test_mm256_test_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_test_epi16_mask(a, b);
@@ -20497,7 +20497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_test_epi16_mask() {
+    const fn test_mm256_mask_test_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi16_mask(0, a, b);
@@ -20508,7 +20508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_test_epi16_mask() {
+    const fn test_mm_test_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_test_epi16_mask(a, b);
@@ -20517,7 +20517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_test_epi16_mask() {
+    const fn test_mm_mask_test_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi16_mask(0, a, b);
@@ -20528,7 +20528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_test_epi8_mask() {
+    const fn test_mm512_test_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_test_epi8_mask(a, b);
@@ -20538,7 +20538,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_test_epi8_mask() {
+    const fn test_mm512_mask_test_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi8_mask(0, a, b);
@@ -20554,7 +20554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_test_epi8_mask() {
+    const fn test_mm256_test_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_test_epi8_mask(a, b);
@@ -20563,7 +20563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_test_epi8_mask() {
+    const fn test_mm256_mask_test_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi8_mask(0, a, b);
@@ -20574,7 +20574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_test_epi8_mask() {
+    const fn test_mm_test_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_test_epi8_mask(a, b);
@@ -20583,7 +20583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_test_epi8_mask() {
+    const fn test_mm_mask_test_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi8_mask(0, a, b);
@@ -20594,7 +20594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_testn_epi16_mask() {
+    const fn test_mm512_testn_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi16_mask(a, b);
@@ -20603,7 +20603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_testn_epi16_mask() {
+    const fn test_mm512_mask_testn_epi16_mask() {
         let a = _mm512_set1_epi16(1 << 0);
         let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm512_mask_testn_epi16_mask(0, a, b);
@@ -20614,7 +20614,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_testn_epi16_mask() {
+    const fn test_mm256_testn_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_testn_epi16_mask(a, b);
@@ -20623,7 +20623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_testn_epi16_mask() {
+    const fn test_mm256_mask_testn_epi16_mask() {
         let a = _mm256_set1_epi16(1 << 0);
         let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm256_mask_testn_epi16_mask(0, a, b);
@@ -20634,7 +20634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_testn_epi16_mask() {
+    const fn test_mm_testn_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_testn_epi16_mask(a, b);
@@ -20643,7 +20643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_testn_epi16_mask() {
+    const fn test_mm_mask_testn_epi16_mask() {
         let a = _mm_set1_epi16(1 << 0);
         let b = _mm_set1_epi16(1 << 0 | 1 << 1);
         let r = _mm_mask_testn_epi16_mask(0, a, b);
@@ -20654,7 +20654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_testn_epi8_mask() {
+    const fn test_mm512_testn_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi8_mask(a, b);
@@ -20664,7 +20664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_testn_epi8_mask() {
+    const fn test_mm512_mask_testn_epi8_mask() {
         let a = _mm512_set1_epi8(1 << 0);
         let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm512_mask_testn_epi8_mask(0, a, b);
@@ -20680,7 +20680,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_testn_epi8_mask() {
+    const fn test_mm256_testn_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_testn_epi8_mask(a, b);
@@ -20689,7 +20689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_testn_epi8_mask() {
+    const fn test_mm256_mask_testn_epi8_mask() {
         let a = _mm256_set1_epi8(1 << 0);
         let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm256_mask_testn_epi8_mask(0, a, b);
@@ -20700,7 +20700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_testn_epi8_mask() {
+    const fn test_mm_testn_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_testn_epi8_mask(a, b);
@@ -20709,7 +20709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_testn_epi8_mask() {
+    const fn test_mm_mask_testn_epi8_mask() {
         let a = _mm_set1_epi8(1 << 0);
         let b = _mm_set1_epi8(1 << 0 | 1 << 1);
         let r = _mm_mask_testn_epi8_mask(0, a, b);
@@ -20755,7 +20755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_sad_epu8() {
+    fn test_mm512_sad_epu8() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(4);
         let r = _mm512_sad_epu8(a, b);
@@ -20764,7 +20764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_dbsad_epu8() {
+    fn test_mm512_dbsad_epu8() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(4);
         let r = _mm512_dbsad_epu8::<0>(a, b);
@@ -20773,7 +20773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_dbsad_epu8() {
+    fn test_mm512_mask_dbsad_epu8() {
         let src = _mm512_set1_epi16(1);
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(4);
@@ -20785,7 +20785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_dbsad_epu8() {
+    fn test_mm512_maskz_dbsad_epu8() {
         let a = _mm512_set1_epi8(2);
         let b = _mm512_set1_epi8(4);
         let r = _mm512_maskz_dbsad_epu8::<0>(0, a, b);
@@ -20796,7 +20796,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_dbsad_epu8() {
+    fn test_mm256_dbsad_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_dbsad_epu8::<0>(a, b);
@@ -20805,7 +20805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_dbsad_epu8() {
+    fn test_mm256_mask_dbsad_epu8() {
         let src = _mm256_set1_epi16(1);
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
@@ -20817,7 +20817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_dbsad_epu8() {
+    fn test_mm256_maskz_dbsad_epu8() {
         let a = _mm256_set1_epi8(2);
         let b = _mm256_set1_epi8(4);
         let r = _mm256_maskz_dbsad_epu8::<0>(0, a, b);
@@ -20828,7 +20828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_dbsad_epu8() {
+    fn test_mm_dbsad_epu8() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(4);
         let r = _mm_dbsad_epu8::<0>(a, b);
@@ -20837,7 +20837,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_dbsad_epu8() {
+    fn test_mm_mask_dbsad_epu8() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(4);
@@ -20849,7 +20849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_dbsad_epu8() {
+    fn test_mm_maskz_dbsad_epu8() {
         let a = _mm_set1_epi8(2);
         let b = _mm_set1_epi8(4);
         let r = _mm_maskz_dbsad_epu8::<0>(0, a, b);
@@ -20860,7 +20860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_movepi16_mask() {
+    const fn test_mm512_movepi16_mask() {
         let a = _mm512_set1_epi16(1 << 15);
         let r = _mm512_movepi16_mask(a);
         let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
@@ -20868,7 +20868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_movepi16_mask() {
+    const fn test_mm256_movepi16_mask() {
         let a = _mm256_set1_epi16(1 << 15);
         let r = _mm256_movepi16_mask(a);
         let e: __mmask16 = 0b11111111_11111111;
@@ -20876,7 +20876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_movepi16_mask() {
+    const fn test_mm_movepi16_mask() {
         let a = _mm_set1_epi16(1 << 15);
         let r = _mm_movepi16_mask(a);
         let e: __mmask8 = 0b11111111;
@@ -20884,7 +20884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_movepi8_mask() {
+    const fn test_mm512_movepi8_mask() {
         let a = _mm512_set1_epi8(1 << 7);
         let r = _mm512_movepi8_mask(a);
         let e: __mmask64 =
@@ -20893,7 +20893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_movepi8_mask() {
+    const fn test_mm256_movepi8_mask() {
         let a = _mm256_set1_epi8(1 << 7);
         let r = _mm256_movepi8_mask(a);
         let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
@@ -20901,7 +20901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_movepi8_mask() {
+    const fn test_mm_movepi8_mask() {
         let a = _mm_set1_epi8(1 << 7);
         let r = _mm_movepi8_mask(a);
         let e: __mmask16 = 0b11111111_11111111;
@@ -20909,7 +20909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_movm_epi16() {
+    const fn test_mm512_movm_epi16() {
         let a: __mmask32 = 0b11111111_11111111_11111111_11111111;
         let r = _mm512_movm_epi16(a);
         let e = _mm512_set1_epi16(
@@ -20934,7 +20934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_movm_epi16() {
+    const fn test_mm256_movm_epi16() {
         let a: __mmask16 = 0b11111111_11111111;
         let r = _mm256_movm_epi16(a);
         let e = _mm256_set1_epi16(
@@ -20959,7 +20959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_movm_epi16() {
+    const fn test_mm_movm_epi16() {
         let a: __mmask8 = 0b11111111;
         let r = _mm_movm_epi16(a);
         let e = _mm_set1_epi16(
@@ -20984,7 +20984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_movm_epi8() {
+    const fn test_mm512_movm_epi8() {
         let a: __mmask64 =
             0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
         let r = _mm512_movm_epi8(a);
@@ -20994,7 +20994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_movm_epi8() {
+    const fn test_mm256_movm_epi8() {
         let a: __mmask32 = 0b11111111_11111111_11111111_11111111;
         let r = _mm256_movm_epi8(a);
         let e =
@@ -21003,7 +21003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_movm_epi8() {
+    const fn test_mm_movm_epi8() {
         let a: __mmask16 = 0b11111111_11111111;
         let r = _mm_movm_epi8(a);
         let e =
@@ -21012,7 +21012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_cvtmask32_u32() {
+    const fn test_cvtmask32_u32() {
         let a: __mmask32 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtmask32_u32(a);
         let e: u32 = 0b11001100_00110011_01100110_10011001;
@@ -21020,7 +21020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_cvtu32_mask32() {
+    const fn test_cvtu32_mask32() {
         let a: u32 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtu32_mask32(a);
         let e: __mmask32 = 0b11001100_00110011_01100110_10011001;
@@ -21028,7 +21028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kadd_mask32() {
+    const fn test_kadd_mask32() {
         let a: __mmask32 = 11;
         let b: __mmask32 = 22;
         let r = _kadd_mask32(a, b);
@@ -21037,7 +21037,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kadd_mask64() {
+    const fn test_kadd_mask64() {
         let a: __mmask64 = 11;
         let b: __mmask64 = 22;
         let r = _kadd_mask64(a, b);
@@ -21046,7 +21046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kand_mask32() {
+    const fn test_kand_mask32() {
         let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kand_mask32(a, b);
@@ -21055,7 +21055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kand_mask64() {
+    const fn test_kand_mask64() {
         let a: __mmask64 =
             0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
         let b: __mmask64 =
@@ -21067,7 +21067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_knot_mask32() {
+    const fn test_knot_mask32() {
         let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _knot_mask32(a);
         let e: __mmask32 = 0b00110011_11001100_00110011_11001100;
@@ -21075,7 +21075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_knot_mask64() {
+    const fn test_knot_mask64() {
         let a: __mmask64 =
             0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
         let r = _knot_mask64(a);
@@ -21085,7 +21085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kandn_mask32() {
+    const fn test_kandn_mask32() {
         let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kandn_mask32(a, b);
@@ -21094,7 +21094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kandn_mask64() {
+    const fn test_kandn_mask64() {
         let a: __mmask64 =
             0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
         let b: __mmask64 =
@@ -21106,7 +21106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kor_mask32() {
+    const fn test_kor_mask32() {
         let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kor_mask32(a, b);
@@ -21115,7 +21115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kor_mask64() {
+    const fn test_kor_mask64() {
         let a: __mmask64 =
             0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
         let b: __mmask64 =
@@ -21127,7 +21127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kxor_mask32() {
+    const fn test_kxor_mask32() {
         let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kxor_mask32(a, b);
@@ -21136,7 +21136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kxor_mask64() {
+    const fn test_kxor_mask64() {
         let a: __mmask64 =
             0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
         let b: __mmask64 =
@@ -21148,7 +21148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kxnor_mask32() {
+    const fn test_kxnor_mask32() {
         let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
         let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
         let r = _kxnor_mask32(a, b);
@@ -21157,7 +21157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kxnor_mask64() {
+    const fn test_kxnor_mask64() {
         let a: __mmask64 =
             0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
         let b: __mmask64 =
@@ -21189,7 +21189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortestc_mask32_u8() {
+    const fn test_kortestc_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let r = _kortestc_mask32_u8(a, b);
@@ -21197,7 +21197,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortestc_mask64_u8() {
+    const fn test_kortestc_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let r = _kortestc_mask64_u8(a, b);
@@ -21205,7 +21205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortestz_mask32_u8() {
+    const fn test_kortestz_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let r = _kortestz_mask32_u8(a, b);
@@ -21213,7 +21213,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortestz_mask64_u8() {
+    const fn test_kortestz_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let r = _kortestz_mask64_u8(a, b);
@@ -21221,7 +21221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kshiftli_mask32() {
+    const fn test_kshiftli_mask32() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let r = _kshiftli_mask32::<3>(a);
         let e: __mmask32 = 0b0100101101001011_0100101101001000;
@@ -21241,7 +21241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kshiftli_mask64() {
+    const fn test_kshiftli_mask64() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let r = _kshiftli_mask64::<3>(a);
         let e: __mmask64 = 0b0110100101101001011_0100101101001000;
@@ -21261,7 +21261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kshiftri_mask32() {
+    const fn test_kshiftri_mask32() {
         let a: __mmask32 = 0b1010100101101001_0110100101101001;
         let r = _kshiftri_mask32::<3>(a);
         let e: __mmask32 = 0b0001010100101101_0010110100101101;
@@ -21281,7 +21281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kshiftri_mask64() {
+    const fn test_kshiftri_mask64() {
         let a: __mmask64 = 0b1010100101101001011_0100101101001000;
         let r = _kshiftri_mask64::<3>(a);
         let e: __mmask64 = 0b1010100101101001_0110100101101001;
@@ -21315,7 +21315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktestc_mask32_u8() {
+    const fn test_ktestc_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let r = _ktestc_mask32_u8(a, b);
@@ -21323,7 +21323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktestz_mask32_u8() {
+    const fn test_ktestz_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let r = _ktestz_mask32_u8(a, b);
@@ -21341,7 +21341,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktestc_mask64_u8() {
+    const fn test_ktestc_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let r = _ktestc_mask64_u8(a, b);
@@ -21349,7 +21349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktestz_mask64_u8() {
+    const fn test_ktestz_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let r = _ktestz_mask64_u8(a, b);
@@ -21357,7 +21357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_kunpackw() {
+    const fn test_mm512_kunpackw() {
         let a: u32 = 0x00110011;
         let b: u32 = 0x00001011;
         let r = _mm512_kunpackw(a, b);
@@ -21366,7 +21366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_kunpackd() {
+    const fn test_mm512_kunpackd() {
         let a: u64 = 0x11001100_00110011;
         let b: u64 = 0x00101110_00001011;
         let r = _mm512_kunpackd(a, b);
@@ -21375,7 +21375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cvtepi16_epi8() {
+    const fn test_mm512_cvtepi16_epi8() {
         let a = _mm512_set1_epi16(2);
         let r = _mm512_cvtepi16_epi8(a);
         let e = _mm256_set1_epi8(2);
@@ -21383,7 +21383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cvtepi16_epi8() {
+    const fn test_mm512_mask_cvtepi16_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm512_set1_epi16(2);
         let r = _mm512_mask_cvtepi16_epi8(src, 0, a);
@@ -21394,7 +21394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_cvtepi16_epi8() {
+    const fn test_mm512_maskz_cvtepi16_epi8() {
         let a = _mm512_set1_epi16(2);
         let r = _mm512_maskz_cvtepi16_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -21404,7 +21404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_cvtepi16_epi8() {
+    const fn test_mm256_cvtepi16_epi8() {
         let a = _mm256_set1_epi16(2);
         let r = _mm256_cvtepi16_epi8(a);
         let e = _mm_set1_epi8(2);
@@ -21412,7 +21412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi16_epi8() {
+    const fn test_mm256_mask_cvtepi16_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm256_set1_epi16(2);
         let r = _mm256_mask_cvtepi16_epi8(src, 0, a);
@@ -21423,7 +21423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi16_epi8() {
+    const fn test_mm256_maskz_cvtepi16_epi8() {
         let a = _mm256_set1_epi16(2);
         let r = _mm256_maskz_cvtepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21433,7 +21433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_cvtepi16_epi8() {
+    const fn test_mm_cvtepi16_epi8() {
         let a = _mm_set1_epi16(2);
         let r = _mm_cvtepi16_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
@@ -21441,7 +21441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi16_epi8() {
+    const fn test_mm_mask_cvtepi16_epi8() {
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
         let a = _mm_set1_epi16(2);
         let r = _mm_mask_cvtepi16_epi8(src, 0, a);
@@ -21452,7 +21452,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi16_epi8() {
+    const fn test_mm_maskz_cvtepi16_epi8() {
         let a = _mm_set1_epi16(2);
         let r = _mm_maskz_cvtepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21462,7 +21462,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cvtsepi16_epi8() {
+    fn test_mm512_cvtsepi16_epi8() {
         let a = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_cvtsepi16_epi8(a);
         let e = _mm256_set1_epi8(i8::MAX);
@@ -21470,7 +21470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtsepi16_epi8() {
+    fn test_mm512_mask_cvtsepi16_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_mask_cvtsepi16_epi8(src, 0, a);
@@ -21481,7 +21481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cvtsepi16_epi8() {
+    fn test_mm256_cvtsepi16_epi8() {
         let a = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_cvtsepi16_epi8(a);
         let e = _mm_set1_epi8(i8::MAX);
@@ -21489,7 +21489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi16_epi8() {
+    fn test_mm256_mask_cvtsepi16_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_mask_cvtsepi16_epi8(src, 0, a);
@@ -21500,7 +21500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtsepi16_epi8() {
+    fn test_mm256_maskz_cvtsepi16_epi8() {
         let a = _mm256_set1_epi16(i16::MAX);
         let r = _mm256_maskz_cvtsepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21510,7 +21510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cvtsepi16_epi8() {
+    fn test_mm_cvtsepi16_epi8() {
         let a = _mm_set1_epi16(i16::MAX);
         let r = _mm_cvtsepi16_epi8(a);
         #[rustfmt::skip]
@@ -21519,7 +21519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi16_epi8() {
+    fn test_mm_mask_cvtsepi16_epi8() {
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
         let a = _mm_set1_epi16(i16::MAX);
         let r = _mm_mask_cvtsepi16_epi8(src, 0, a);
@@ -21531,7 +21531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsepi16_epi8() {
+    fn test_mm_maskz_cvtsepi16_epi8() {
         let a = _mm_set1_epi16(i16::MAX);
         let r = _mm_maskz_cvtsepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21542,7 +21542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_cvtsepi16_epi8() {
+    fn test_mm512_maskz_cvtsepi16_epi8() {
         let a = _mm512_set1_epi16(i16::MAX);
         let r = _mm512_maskz_cvtsepi16_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -21552,7 +21552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_cvtusepi16_epi8() {
+    fn test_mm512_cvtusepi16_epi8() {
         let a = _mm512_set1_epi16(i16::MIN);
         let r = _mm512_cvtusepi16_epi8(a);
         let e = _mm256_set1_epi8(-1);
@@ -21560,7 +21560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtusepi16_epi8() {
+    fn test_mm512_mask_cvtusepi16_epi8() {
         let src = _mm256_set1_epi8(1);
         let a = _mm512_set1_epi16(i16::MIN);
         let r = _mm512_mask_cvtusepi16_epi8(src, 0, a);
@@ -21571,7 +21571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_maskz_cvtusepi16_epi8() {
+    fn test_mm512_maskz_cvtusepi16_epi8() {
         let a = _mm512_set1_epi16(i16::MIN);
         let r = _mm512_maskz_cvtusepi16_epi8(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -21581,7 +21581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_cvtusepi16_epi8() {
+    fn test_mm256_cvtusepi16_epi8() {
         let a = _mm256_set1_epi16(i16::MIN);
         let r = _mm256_cvtusepi16_epi8(a);
         let e = _mm_set1_epi8(-1);
@@ -21589,7 +21589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi16_epi8() {
+    fn test_mm256_mask_cvtusepi16_epi8() {
         let src = _mm_set1_epi8(1);
         let a = _mm256_set1_epi16(i16::MIN);
         let r = _mm256_mask_cvtusepi16_epi8(src, 0, a);
@@ -21600,7 +21600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtusepi16_epi8() {
+    fn test_mm256_maskz_cvtusepi16_epi8() {
         let a = _mm256_set1_epi16(i16::MIN);
         let r = _mm256_maskz_cvtusepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21610,7 +21610,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_cvtusepi16_epi8() {
+    fn test_mm_cvtusepi16_epi8() {
         let a = _mm_set1_epi16(i16::MIN);
         let r = _mm_cvtusepi16_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
@@ -21618,7 +21618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi16_epi8() {
+    fn test_mm_mask_cvtusepi16_epi8() {
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
         let a = _mm_set1_epi16(i16::MIN);
         let r = _mm_mask_cvtusepi16_epi8(src, 0, a);
@@ -21629,7 +21629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_cvtusepi16_epi8() {
+    fn test_mm_maskz_cvtusepi16_epi8() {
         let a = _mm_set1_epi16(i16::MIN);
         let r = _mm_maskz_cvtusepi16_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21639,7 +21639,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cvtepi8_epi16() {
+    const fn test_mm512_cvtepi8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_cvtepi8_epi16(a);
         let e = _mm512_set1_epi16(2);
@@ -21647,7 +21647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cvtepi8_epi16() {
+    const fn test_mm512_mask_cvtepi8_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm256_set1_epi8(2);
         let r = _mm512_mask_cvtepi8_epi16(src, 0, a);
@@ -21658,7 +21658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_cvtepi8_epi16() {
+    const fn test_mm512_maskz_cvtepi8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_maskz_cvtepi8_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -21668,7 +21668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi8_epi16() {
+    const fn test_mm256_mask_cvtepi8_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm256_mask_cvtepi8_epi16(src, 0, a);
@@ -21679,7 +21679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi8_epi16() {
+    const fn test_mm256_maskz_cvtepi8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm256_maskz_cvtepi8_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -21689,7 +21689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi8_epi16() {
+    const fn test_mm_mask_cvtepi8_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm_mask_cvtepi8_epi16(src, 0, a);
@@ -21700,7 +21700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi8_epi16() {
+    const fn test_mm_maskz_cvtepi8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm_maskz_cvtepi8_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21710,7 +21710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_cvtepu8_epi16() {
+    const fn test_mm512_cvtepu8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_cvtepu8_epi16(a);
         let e = _mm512_set1_epi16(2);
@@ -21718,7 +21718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_cvtepu8_epi16() {
+    const fn test_mm512_mask_cvtepu8_epi16() {
         let src = _mm512_set1_epi16(1);
         let a = _mm256_set1_epi8(2);
         let r = _mm512_mask_cvtepu8_epi16(src, 0, a);
@@ -21729,7 +21729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_cvtepu8_epi16() {
+    const fn test_mm512_maskz_cvtepu8_epi16() {
         let a = _mm256_set1_epi8(2);
         let r = _mm512_maskz_cvtepu8_epi16(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -21739,7 +21739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu8_epi16() {
+    const fn test_mm256_mask_cvtepu8_epi16() {
         let src = _mm256_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm256_mask_cvtepu8_epi16(src, 0, a);
@@ -21750,7 +21750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu8_epi16() {
+    const fn test_mm256_maskz_cvtepu8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm256_maskz_cvtepu8_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -21760,7 +21760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu8_epi16() {
+    const fn test_mm_mask_cvtepu8_epi16() {
         let src = _mm_set1_epi16(1);
         let a = _mm_set1_epi8(2);
         let r = _mm_mask_cvtepu8_epi16(src, 0, a);
@@ -21771,7 +21771,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu8_epi16() {
+    const fn test_mm_maskz_cvtepu8_epi16() {
         let a = _mm_set1_epi8(2);
         let r = _mm_maskz_cvtepu8_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -21781,7 +21781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_bslli_epi128() {
+    const fn test_mm512_bslli_epi128() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21801,7 +21801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_bsrli_epi128() {
+    const fn test_mm512_bsrli_epi128() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@@ -21821,7 +21821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_alignr_epi8() {
+    const fn test_mm512_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21842,7 +21842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_alignr_epi8() {
+    const fn test_mm512_mask_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21870,7 +21870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_alignr_epi8() {
+    const fn test_mm512_maskz_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21897,7 +21897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_alignr_epi8() {
+    const fn test_mm256_mask_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21916,7 +21916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_alignr_epi8() {
+    const fn test_mm256_maskz_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(
             1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
@@ -21935,7 +21935,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_alignr_epi8() {
+    const fn test_mm_mask_alignr_epi8() {
         let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
         let b = _mm_set1_epi8(1);
         let r = _mm_mask_alignr_epi8::<14>(a, 0, a, b);
@@ -21946,7 +21946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_alignr_epi8() {
+    const fn test_mm_maskz_alignr_epi8() {
         let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
         let b = _mm_set1_epi8(1);
         let r = _mm_maskz_alignr_epi8::<14>(0, a, b);
diff --git a/crates/core_arch/src/x86/avx512cd.rs b/crates/core_arch/src/x86/avx512cd.rs
index b163698b56..4082433e70 100644
--- a/crates/core_arch/src/x86/avx512cd.rs
+++ b/crates/core_arch/src/x86/avx512cd.rs
@@ -587,7 +587,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_broadcastmw_epi32() {
+    const fn test_mm512_broadcastmw_epi32() {
         let a: __mmask16 = 2;
         let r = _mm512_broadcastmw_epi32(a);
         let e = _mm512_set1_epi32(2);
@@ -595,7 +595,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_broadcastmw_epi32() {
+    const fn test_mm256_broadcastmw_epi32() {
         let a: __mmask16 = 2;
         let r = _mm256_broadcastmw_epi32(a);
         let e = _mm256_set1_epi32(2);
@@ -603,7 +603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_broadcastmw_epi32() {
+    const fn test_mm_broadcastmw_epi32() {
         let a: __mmask16 = 2;
         let r = _mm_broadcastmw_epi32(a);
         let e = _mm_set1_epi32(2);
@@ -611,7 +611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_broadcastmb_epi64() {
+    const fn test_mm512_broadcastmb_epi64() {
         let a: __mmask8 = 2;
         let r = _mm512_broadcastmb_epi64(a);
         let e = _mm512_set1_epi64(2);
@@ -619,7 +619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_broadcastmb_epi64() {
+    const fn test_mm256_broadcastmb_epi64() {
         let a: __mmask8 = 2;
         let r = _mm256_broadcastmb_epi64(a);
         let e = _mm256_set1_epi64x(2);
@@ -627,7 +627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_broadcastmb_epi64() {
+    const fn test_mm_broadcastmb_epi64() {
         let a: __mmask8 = 2;
         let r = _mm_broadcastmb_epi64(a);
         let e = _mm_set1_epi64x(2);
@@ -635,7 +635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_conflict_epi32() {
+    fn test_mm512_conflict_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_conflict_epi32(a);
         let e = _mm512_set_epi32(
@@ -720,7 +720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_mask_conflict_epi32() {
+    fn test_mm512_mask_conflict_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_mask_conflict_epi32(a, 0, a);
         assert_eq_m512i(r, a);
@@ -807,7 +807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_maskz_conflict_epi32() {
+    fn test_mm512_maskz_conflict_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_maskz_conflict_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -894,7 +894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_conflict_epi32() {
+    fn test_mm256_conflict_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_conflict_epi32(a);
         let e = _mm256_set_epi32(
@@ -911,7 +911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_mask_conflict_epi32() {
+    fn test_mm256_mask_conflict_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_mask_conflict_epi32(a, 0, a);
         assert_eq_m256i(r, a);
@@ -930,7 +930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_maskz_conflict_epi32() {
+    fn test_mm256_maskz_conflict_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_maskz_conflict_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -949,7 +949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_conflict_epi32() {
+    fn test_mm_conflict_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_conflict_epi32(a);
         let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
@@ -957,7 +957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_mask_conflict_epi32() {
+    fn test_mm_mask_conflict_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_mask_conflict_epi32(a, 0, a);
         assert_eq_m128i(r, a);
@@ -967,7 +967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_maskz_conflict_epi32() {
+    fn test_mm_maskz_conflict_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_maskz_conflict_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -977,7 +977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_conflict_epi64() {
+    fn test_mm512_conflict_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_conflict_epi64(a);
         let e = _mm512_set_epi64(
@@ -994,7 +994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_mask_conflict_epi64() {
+    fn test_mm512_mask_conflict_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_mask_conflict_epi64(a, 0, a);
         assert_eq_m512i(r, a);
@@ -1013,7 +1013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    unsafe fn test_mm512_maskz_conflict_epi64() {
+    fn test_mm512_maskz_conflict_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_maskz_conflict_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -1032,7 +1032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_conflict_epi64() {
+    fn test_mm256_conflict_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_conflict_epi64(a);
         let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
@@ -1040,7 +1040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_mask_conflict_epi64() {
+    fn test_mm256_mask_conflict_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_mask_conflict_epi64(a, 0, a);
         assert_eq_m256i(r, a);
@@ -1050,7 +1050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm256_maskz_conflict_epi64() {
+    fn test_mm256_maskz_conflict_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_conflict_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -1060,7 +1060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_conflict_epi64() {
+    fn test_mm_conflict_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_conflict_epi64(a);
         let e = _mm_set_epi64x(1 << 0, 0);
@@ -1068,7 +1068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_mask_conflict_epi64() {
+    fn test_mm_mask_conflict_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_mask_conflict_epi64(a, 0, a);
         assert_eq_m128i(r, a);
@@ -1078,7 +1078,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    unsafe fn test_mm_maskz_conflict_epi64() {
+    fn test_mm_maskz_conflict_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_maskz_conflict_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -1088,7 +1088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_lzcnt_epi32() {
+    const fn test_mm512_lzcnt_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_lzcnt_epi32(a);
         let e = _mm512_set1_epi32(31);
@@ -1096,7 +1096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_mask_lzcnt_epi32() {
+    const fn test_mm512_mask_lzcnt_epi32() {
         let a = _mm512_set1_epi32(1);
         let r = _mm512_mask_lzcnt_epi32(a, 0, a);
         assert_eq_m512i(r, a);
@@ -1106,7 +1106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_maskz_lzcnt_epi32() {
+    const fn test_mm512_maskz_lzcnt_epi32() {
         let a = _mm512_set1_epi32(2);
         let r = _mm512_maskz_lzcnt_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -1116,7 +1116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_lzcnt_epi32() {
+    const fn test_mm256_lzcnt_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_lzcnt_epi32(a);
         let e = _mm256_set1_epi32(31);
@@ -1124,7 +1124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_mask_lzcnt_epi32() {
+    const fn test_mm256_mask_lzcnt_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_mask_lzcnt_epi32(a, 0, a);
         assert_eq_m256i(r, a);
@@ -1134,7 +1134,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_maskz_lzcnt_epi32() {
+    const fn test_mm256_maskz_lzcnt_epi32() {
         let a = _mm256_set1_epi32(1);
         let r = _mm256_maskz_lzcnt_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -1144,7 +1144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_lzcnt_epi32() {
+    const fn test_mm_lzcnt_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_lzcnt_epi32(a);
         let e = _mm_set1_epi32(31);
@@ -1152,7 +1152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_mask_lzcnt_epi32() {
+    const fn test_mm_mask_lzcnt_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_mask_lzcnt_epi32(a, 0, a);
         assert_eq_m128i(r, a);
@@ -1162,7 +1162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_maskz_lzcnt_epi32() {
+    const fn test_mm_maskz_lzcnt_epi32() {
         let a = _mm_set1_epi32(1);
         let r = _mm_maskz_lzcnt_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -1172,7 +1172,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_lzcnt_epi64() {
+    const fn test_mm512_lzcnt_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_lzcnt_epi64(a);
         let e = _mm512_set1_epi64(63);
@@ -1180,7 +1180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_mask_lzcnt_epi64() {
+    const fn test_mm512_mask_lzcnt_epi64() {
         let a = _mm512_set1_epi64(1);
         let r = _mm512_mask_lzcnt_epi64(a, 0, a);
         assert_eq_m512i(r, a);
@@ -1190,7 +1190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd")]
-    const unsafe fn test_mm512_maskz_lzcnt_epi64() {
+    const fn test_mm512_maskz_lzcnt_epi64() {
         let a = _mm512_set1_epi64(2);
         let r = _mm512_maskz_lzcnt_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -1200,7 +1200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_lzcnt_epi64() {
+    const fn test_mm256_lzcnt_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_lzcnt_epi64(a);
         let e = _mm256_set1_epi64x(63);
@@ -1208,7 +1208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_mask_lzcnt_epi64() {
+    const fn test_mm256_mask_lzcnt_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_mask_lzcnt_epi64(a, 0, a);
         assert_eq_m256i(r, a);
@@ -1218,7 +1218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm256_maskz_lzcnt_epi64() {
+    const fn test_mm256_maskz_lzcnt_epi64() {
         let a = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_lzcnt_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -1228,7 +1228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_lzcnt_epi64() {
+    const fn test_mm_lzcnt_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_lzcnt_epi64(a);
         let e = _mm_set1_epi64x(63);
@@ -1236,7 +1236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_mask_lzcnt_epi64() {
+    const fn test_mm_mask_lzcnt_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_mask_lzcnt_epi64(a, 0, a);
         assert_eq_m128i(r, a);
@@ -1246,7 +1246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512cd,avx512vl")]
-    const unsafe fn test_mm_maskz_lzcnt_epi64() {
+    const fn test_mm_maskz_lzcnt_epi64() {
         let a = _mm_set1_epi64x(1);
         let r = _mm_maskz_lzcnt_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
diff --git a/crates/core_arch/src/x86/avx512dq.rs b/crates/core_arch/src/x86/avx512dq.rs
index 4ab5880c55..ebe75cd22d 100644
--- a/crates/core_arch/src/x86/avx512dq.rs
+++ b/crates/core_arch/src/x86/avx512dq.rs
@@ -7424,7 +7424,7 @@ mod tests {
     const XOR_32: f32 = unsafe { transmute(0x66666666_u32) };
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_and_pd() {
+    const fn test_mm_mask_and_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7434,7 +7434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_and_pd() {
+    const fn test_mm_maskz_and_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_and_pd(0b01, a, b);
@@ -7443,7 +7443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_and_pd() {
+    const fn test_mm256_mask_and_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7453,7 +7453,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_and_pd() {
+    const fn test_mm256_maskz_and_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_and_pd(0b0101, a, b);
@@ -7462,7 +7462,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_and_pd() {
+    const fn test_mm512_and_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_and_pd(a, b);
@@ -7471,7 +7471,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_and_pd() {
+    const fn test_mm512_mask_and_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7481,7 +7481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_and_pd() {
+    const fn test_mm512_maskz_and_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_and_pd(0b01010101, a, b);
@@ -7490,7 +7490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_and_ps() {
+    const fn test_mm_mask_and_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7500,7 +7500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_and_ps() {
+    const fn test_mm_maskz_and_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_and_ps(0b0101, a, b);
@@ -7509,7 +7509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_and_ps() {
+    const fn test_mm256_mask_and_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7519,7 +7519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_and_ps() {
+    const fn test_mm256_maskz_and_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_and_ps(0b01010101, a, b);
@@ -7528,7 +7528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_and_ps() {
+    const fn test_mm512_and_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_and_ps(a, b);
@@ -7537,7 +7537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_and_ps() {
+    const fn test_mm512_mask_and_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7552,7 +7552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_and_ps() {
+    const fn test_mm512_maskz_and_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_and_ps(0b0101010101010101, a, b);
@@ -7564,7 +7564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_andnot_pd() {
+    const fn test_mm_mask_andnot_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7574,7 +7574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_andnot_pd() {
+    const fn test_mm_maskz_andnot_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_andnot_pd(0b01, a, b);
@@ -7583,7 +7583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_andnot_pd() {
+    const fn test_mm256_mask_andnot_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7593,7 +7593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_andnot_pd() {
+    const fn test_mm256_maskz_andnot_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_andnot_pd(0b0101, a, b);
@@ -7602,7 +7602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_andnot_pd() {
+    const fn test_mm512_andnot_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_andnot_pd(a, b);
@@ -7611,7 +7611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_andnot_pd() {
+    const fn test_mm512_mask_andnot_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7621,7 +7621,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_andnot_pd() {
+    const fn test_mm512_maskz_andnot_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_andnot_pd(0b01010101, a, b);
@@ -7630,7 +7630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_andnot_ps() {
+    const fn test_mm_mask_andnot_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7640,7 +7640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_andnot_ps() {
+    const fn test_mm_maskz_andnot_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_andnot_ps(0b0101, a, b);
@@ -7649,7 +7649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_andnot_ps() {
+    const fn test_mm256_mask_andnot_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7659,7 +7659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_andnot_ps() {
+    const fn test_mm256_maskz_andnot_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_andnot_ps(0b01010101, a, b);
@@ -7668,7 +7668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_andnot_ps() {
+    const fn test_mm512_andnot_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_andnot_ps(a, b);
@@ -7677,7 +7677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_andnot_ps() {
+    const fn test_mm512_mask_andnot_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7692,7 +7692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_andnot_ps() {
+    const fn test_mm512_maskz_andnot_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_andnot_ps(0b0101010101010101, a, b);
@@ -7704,7 +7704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_or_pd() {
+    const fn test_mm_mask_or_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7714,7 +7714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_or_pd() {
+    const fn test_mm_maskz_or_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_or_pd(0b01, a, b);
@@ -7723,7 +7723,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_or_pd() {
+    const fn test_mm256_mask_or_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7733,7 +7733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_or_pd() {
+    const fn test_mm256_maskz_or_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_or_pd(0b0101, a, b);
@@ -7742,7 +7742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_or_pd() {
+    const fn test_mm512_or_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_or_pd(a, b);
@@ -7751,7 +7751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_or_pd() {
+    const fn test_mm512_mask_or_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7761,7 +7761,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_or_pd() {
+    const fn test_mm512_maskz_or_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_or_pd(0b01010101, a, b);
@@ -7770,7 +7770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_or_ps() {
+    const fn test_mm_mask_or_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7780,7 +7780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_or_ps() {
+    const fn test_mm_maskz_or_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_or_ps(0b0101, a, b);
@@ -7789,7 +7789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_or_ps() {
+    const fn test_mm256_mask_or_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7799,7 +7799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_or_ps() {
+    const fn test_mm256_maskz_or_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_or_ps(0b01010101, a, b);
@@ -7808,7 +7808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_or_ps() {
+    const fn test_mm512_or_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_or_ps(a, b);
@@ -7817,7 +7817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_or_ps() {
+    const fn test_mm512_mask_or_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7832,7 +7832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_or_ps() {
+    const fn test_mm512_maskz_or_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_or_ps(0b0101010101010101, a, b);
@@ -7843,7 +7843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_xor_pd() {
+    const fn test_mm_mask_xor_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let src = _mm_set_pd(1., 2.);
@@ -7853,7 +7853,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_xor_pd() {
+    const fn test_mm_maskz_xor_pd() {
         let a = _mm_set1_pd(OPRND1_64);
         let b = _mm_set1_pd(OPRND2_64);
         let r = _mm_maskz_xor_pd(0b01, a, b);
@@ -7862,7 +7862,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_xor_pd() {
+    const fn test_mm256_mask_xor_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let src = _mm256_set_pd(1., 2., 3., 4.);
@@ -7872,7 +7872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_xor_pd() {
+    const fn test_mm256_maskz_xor_pd() {
         let a = _mm256_set1_pd(OPRND1_64);
         let b = _mm256_set1_pd(OPRND2_64);
         let r = _mm256_maskz_xor_pd(0b0101, a, b);
@@ -7881,7 +7881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_xor_pd() {
+    const fn test_mm512_xor_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_xor_pd(a, b);
@@ -7890,7 +7890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_xor_pd() {
+    const fn test_mm512_mask_xor_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let src = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7900,7 +7900,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_xor_pd() {
+    const fn test_mm512_maskz_xor_pd() {
         let a = _mm512_set1_pd(OPRND1_64);
         let b = _mm512_set1_pd(OPRND2_64);
         let r = _mm512_maskz_xor_pd(0b01010101, a, b);
@@ -7909,7 +7909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_xor_ps() {
+    const fn test_mm_mask_xor_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let src = _mm_set_ps(1., 2., 3., 4.);
@@ -7919,7 +7919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_xor_ps() {
+    const fn test_mm_maskz_xor_ps() {
         let a = _mm_set1_ps(OPRND1_32);
         let b = _mm_set1_ps(OPRND2_32);
         let r = _mm_maskz_xor_ps(0b0101, a, b);
@@ -7928,7 +7928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_xor_ps() {
+    const fn test_mm256_mask_xor_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let src = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -7938,7 +7938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_xor_ps() {
+    const fn test_mm256_maskz_xor_ps() {
         let a = _mm256_set1_ps(OPRND1_32);
         let b = _mm256_set1_ps(OPRND2_32);
         let r = _mm256_maskz_xor_ps(0b01010101, a, b);
@@ -7947,7 +7947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_xor_ps() {
+    const fn test_mm512_xor_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_xor_ps(a, b);
@@ -7956,7 +7956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_xor_ps() {
+    const fn test_mm512_mask_xor_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let src = _mm512_set_ps(
@@ -7971,7 +7971,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_xor_ps() {
+    const fn test_mm512_maskz_xor_ps() {
         let a = _mm512_set1_ps(OPRND1_32);
         let b = _mm512_set1_ps(OPRND2_32);
         let r = _mm512_maskz_xor_ps(0b0101010101010101, a, b);
@@ -7983,7 +7983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_broadcast_f32x2() {
+    const fn test_mm256_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_broadcast_f32x2(a);
         let e = _mm256_set_ps(3., 4., 3., 4., 3., 4., 3., 4.);
@@ -7991,7 +7991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcast_f32x2() {
+    const fn test_mm256_mask_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm256_set_ps(5., 6., 7., 8., 9., 10., 11., 12.);
         let r = _mm256_mask_broadcast_f32x2(b, 0b01101001, a);
@@ -8000,7 +8000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcast_f32x2() {
+    const fn test_mm256_maskz_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_maskz_broadcast_f32x2(0b01101001, a);
         let e = _mm256_set_ps(0., 4., 3., 0., 3., 0., 0., 4.);
@@ -8008,7 +8008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_broadcast_f32x2() {
+    const fn test_mm512_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm512_broadcast_f32x2(a);
         let e = _mm512_set_ps(
@@ -8018,7 +8018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_broadcast_f32x2() {
+    const fn test_mm512_mask_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm512_set_ps(
             5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20.,
@@ -8031,7 +8031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_broadcast_f32x2() {
+    const fn test_mm512_maskz_broadcast_f32x2() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm512_maskz_broadcast_f32x2(0b0110100100111100, a);
         let e = _mm512_set_ps(
@@ -8041,7 +8041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_broadcast_f32x8() {
+    const fn test_mm512_broadcast_f32x8() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_broadcast_f32x8(a);
         let e = _mm512_set_ps(
@@ -8051,7 +8051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_broadcast_f32x8() {
+    const fn test_mm512_mask_broadcast_f32x8() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_ps(
             9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24.,
@@ -8064,7 +8064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_broadcast_f32x8() {
+    const fn test_mm512_maskz_broadcast_f32x8() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_broadcast_f32x8(0b0110100100111100, a);
         let e = _mm512_set_ps(
@@ -8074,7 +8074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_broadcast_f64x2() {
+    const fn test_mm256_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm256_broadcast_f64x2(a);
         let e = _mm256_set_pd(1., 2., 1., 2.);
@@ -8082,7 +8082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcast_f64x2() {
+    const fn test_mm256_mask_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm256_set_pd(3., 4., 5., 6.);
         let r = _mm256_mask_broadcast_f64x2(b, 0b0110, a);
@@ -8091,7 +8091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcast_f64x2() {
+    const fn test_mm256_maskz_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm256_maskz_broadcast_f64x2(0b0110, a);
         let e = _mm256_set_pd(0., 2., 1., 0.);
@@ -8099,7 +8099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_broadcast_f64x2() {
+    const fn test_mm512_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm512_broadcast_f64x2(a);
         let e = _mm512_set_pd(1., 2., 1., 2., 1., 2., 1., 2.);
@@ -8107,7 +8107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_broadcast_f64x2() {
+    const fn test_mm512_mask_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm512_set_pd(3., 4., 5., 6., 7., 8., 9., 10.);
         let r = _mm512_mask_broadcast_f64x2(b, 0b01101001, a);
@@ -8116,7 +8116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_broadcast_f64x2() {
+    const fn test_mm512_maskz_broadcast_f64x2() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm512_maskz_broadcast_f64x2(0b01101001, a);
         let e = _mm512_set_pd(0., 2., 1., 0., 1., 0., 0., 2.);
@@ -8124,7 +8124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_broadcast_i32x2() {
+    const fn test_mm_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_broadcast_i32x2(a);
         let e = _mm_set_epi32(3, 4, 3, 4);
@@ -8132,7 +8132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_broadcast_i32x2() {
+    const fn test_mm_mask_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(5, 6, 7, 8);
         let r = _mm_mask_broadcast_i32x2(b, 0b0110, a);
@@ -8141,7 +8141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_broadcast_i32x2() {
+    const fn test_mm_maskz_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_broadcast_i32x2(0b0110, a);
         let e = _mm_set_epi32(0, 4, 3, 0);
@@ -8149,7 +8149,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_broadcast_i32x2() {
+    const fn test_mm256_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm256_broadcast_i32x2(a);
         let e = _mm256_set_epi32(3, 4, 3, 4, 3, 4, 3, 4);
@@ -8157,7 +8157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcast_i32x2() {
+    const fn test_mm256_mask_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm256_set_epi32(5, 6, 7, 8, 9, 10, 11, 12);
         let r = _mm256_mask_broadcast_i32x2(b, 0b01101001, a);
@@ -8166,7 +8166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcast_i32x2() {
+    const fn test_mm256_maskz_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm256_maskz_broadcast_i32x2(0b01101001, a);
         let e = _mm256_set_epi32(0, 4, 3, 0, 3, 0, 0, 4);
@@ -8174,7 +8174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_broadcast_i32x2() {
+    const fn test_mm512_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm512_broadcast_i32x2(a);
         let e = _mm512_set_epi32(3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4);
@@ -8182,7 +8182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_broadcast_i32x2() {
+    const fn test_mm512_mask_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm512_set_epi32(5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20);
         let r = _mm512_mask_broadcast_i32x2(b, 0b0110100100111100, a);
@@ -8191,7 +8191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_broadcast_i32x2() {
+    const fn test_mm512_maskz_broadcast_i32x2() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm512_maskz_broadcast_i32x2(0b0110100100111100, a);
         let e = _mm512_set_epi32(0, 4, 3, 0, 3, 0, 0, 4, 0, 0, 3, 4, 3, 4, 0, 0);
@@ -8199,7 +8199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_broadcast_i32x8() {
+    const fn test_mm512_broadcast_i32x8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_broadcast_i32x8(a);
         let e = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
@@ -8207,7 +8207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_broadcast_i32x8() {
+    const fn test_mm512_mask_broadcast_i32x8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi32(
             9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
@@ -8218,7 +8218,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_broadcast_i32x8() {
+    const fn test_mm512_maskz_broadcast_i32x8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_broadcast_i32x8(0b0110100100111100, a);
         let e = _mm512_set_epi32(0, 2, 3, 0, 5, 0, 0, 8, 0, 0, 3, 4, 5, 6, 0, 0);
@@ -8226,7 +8226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_broadcast_i64x2() {
+    const fn test_mm256_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm256_broadcast_i64x2(a);
         let e = _mm256_set_epi64x(1, 2, 1, 2);
@@ -8234,7 +8234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcast_i64x2() {
+    const fn test_mm256_mask_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm256_set_epi64x(3, 4, 5, 6);
         let r = _mm256_mask_broadcast_i64x2(b, 0b0110, a);
@@ -8243,7 +8243,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcast_i64x2() {
+    const fn test_mm256_maskz_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm256_maskz_broadcast_i64x2(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 1, 0);
@@ -8251,7 +8251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_broadcast_i64x2() {
+    const fn test_mm512_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm512_broadcast_i64x2(a);
         let e = _mm512_set_epi64(1, 2, 1, 2, 1, 2, 1, 2);
@@ -8259,7 +8259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_broadcast_i64x2() {
+    const fn test_mm512_mask_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm512_set_epi64(3, 4, 5, 6, 7, 8, 9, 10);
         let r = _mm512_mask_broadcast_i64x2(b, 0b01101001, a);
@@ -8268,7 +8268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_broadcast_i64x2() {
+    const fn test_mm512_maskz_broadcast_i64x2() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm512_maskz_broadcast_i64x2(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 1, 0, 1, 0, 0, 2);
@@ -8276,7 +8276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_extractf32x8_ps() {
+    const fn test_mm512_extractf32x8_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8286,7 +8286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_extractf32x8_ps() {
+    const fn test_mm512_mask_extractf32x8_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8297,7 +8297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_extractf32x8_ps() {
+    const fn test_mm512_maskz_extractf32x8_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8307,7 +8307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_extractf64x2_pd() {
+    const fn test_mm256_extractf64x2_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_extractf64x2_pd::<1>(a);
         let e = _mm_set_pd(1., 2.);
@@ -8315,7 +8315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_extractf64x2_pd() {
+    const fn test_mm256_mask_extractf64x2_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let r = _mm256_mask_extractf64x2_pd::<1>(b, 0b01, a);
@@ -8324,7 +8324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_extractf64x2_pd() {
+    const fn test_mm256_maskz_extractf64x2_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_extractf64x2_pd::<1>(0b01, a);
         let e = _mm_set_pd(0., 2.);
@@ -8332,7 +8332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_extractf64x2_pd() {
+    const fn test_mm512_extractf64x2_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_extractf64x2_pd::<2>(a);
         let e = _mm_set_pd(3., 4.);
@@ -8340,7 +8340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_extractf64x2_pd() {
+    const fn test_mm512_mask_extractf64x2_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let r = _mm512_mask_extractf64x2_pd::<2>(b, 0b01, a);
@@ -8349,7 +8349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_extractf64x2_pd() {
+    const fn test_mm512_maskz_extractf64x2_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_extractf64x2_pd::<2>(0b01, a);
         let e = _mm_set_pd(0., 4.);
@@ -8357,7 +8357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_extracti32x8_epi32() {
+    const fn test_mm512_extracti32x8_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_extracti32x8_epi32::<1>(a);
         let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
@@ -8365,7 +8365,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_extracti32x8_epi32() {
+    const fn test_mm512_mask_extracti32x8_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_extracti32x8_epi32::<1>(b, 0b01101001, a);
@@ -8374,7 +8374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_extracti32x8_epi32() {
+    const fn test_mm512_maskz_extracti32x8_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_extracti32x8_epi32::<1>(0b01101001, a);
         let e = _mm256_set_epi32(0, 2, 3, 0, 5, 0, 0, 8);
@@ -8382,7 +8382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_extracti64x2_epi64() {
+    const fn test_mm256_extracti64x2_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_extracti64x2_epi64::<1>(a);
         let e = _mm_set_epi64x(1, 2);
@@ -8390,7 +8390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_extracti64x2_epi64() {
+    const fn test_mm256_mask_extracti64x2_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm256_mask_extracti64x2_epi64::<1>(b, 0b01, a);
@@ -8399,7 +8399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_extracti64x2_epi64() {
+    const fn test_mm256_maskz_extracti64x2_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_extracti64x2_epi64::<1>(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -8407,7 +8407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_extracti64x2_epi64() {
+    const fn test_mm512_extracti64x2_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_extracti64x2_epi64::<2>(a);
         let e = _mm_set_epi64x(3, 4);
@@ -8415,7 +8415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_extracti64x2_epi64() {
+    const fn test_mm512_mask_extracti64x2_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let r = _mm512_mask_extracti64x2_epi64::<2>(b, 0b01, a);
@@ -8424,7 +8424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_extracti64x2_epi64() {
+    const fn test_mm512_maskz_extracti64x2_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_extracti64x2_epi64::<2>(0b01, a);
         let e = _mm_set_epi64x(0, 4);
@@ -8432,7 +8432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_insertf32x8() {
+    const fn test_mm512_insertf32x8() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8445,7 +8445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_insertf32x8() {
+    const fn test_mm512_mask_insertf32x8() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8461,7 +8461,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_insertf32x8() {
+    const fn test_mm512_maskz_insertf32x8() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -8474,7 +8474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_insertf64x2() {
+    const fn test_mm256_insertf64x2() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let r = _mm256_insertf64x2::<1>(a, b);
@@ -8483,7 +8483,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_insertf64x2() {
+    const fn test_mm256_mask_insertf64x2() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let src = _mm256_set_pd(7., 8., 9., 10.);
@@ -8493,7 +8493,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_insertf64x2() {
+    const fn test_mm256_maskz_insertf64x2() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm_set_pd(5., 6.);
         let r = _mm256_maskz_insertf64x2::<1>(0b0110, a, b);
@@ -8502,7 +8502,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_insertf64x2() {
+    const fn test_mm512_insertf64x2() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let r = _mm512_insertf64x2::<2>(a, b);
@@ -8511,7 +8511,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_insertf64x2() {
+    const fn test_mm512_mask_insertf64x2() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let src = _mm512_set_pd(11., 12., 13., 14., 15., 16., 17., 18.);
@@ -8521,7 +8521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_insertf64x2() {
+    const fn test_mm512_maskz_insertf64x2() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_pd(9., 10.);
         let r = _mm512_maskz_insertf64x2::<2>(0b01101001, a, b);
@@ -8530,7 +8530,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_inserti32x8() {
+    const fn test_mm512_inserti32x8() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_inserti32x8::<1>(a, b);
@@ -8541,7 +8541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_inserti32x8() {
+    const fn test_mm512_mask_inserti32x8() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let src = _mm512_set_epi32(
@@ -8555,7 +8555,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_inserti32x8() {
+    const fn test_mm512_maskz_inserti32x8() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_inserti32x8::<1>(0b0110100100111100, a, b);
@@ -8564,7 +8564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_inserti64x2() {
+    const fn test_mm256_inserti64x2() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm256_inserti64x2::<1>(a, b);
@@ -8573,7 +8573,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_inserti64x2() {
+    const fn test_mm256_mask_inserti64x2() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let src = _mm256_set_epi64x(7, 8, 9, 10);
@@ -8583,7 +8583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_inserti64x2() {
+    const fn test_mm256_maskz_inserti64x2() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm256_maskz_inserti64x2::<1>(0b0110, a, b);
@@ -8592,7 +8592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_inserti64x2() {
+    const fn test_mm512_inserti64x2() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let r = _mm512_inserti64x2::<2>(a, b);
@@ -8601,7 +8601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_inserti64x2() {
+    const fn test_mm512_mask_inserti64x2() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let src = _mm512_set_epi64(11, 12, 13, 14, 15, 16, 17, 18);
@@ -8611,7 +8611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_inserti64x2() {
+    const fn test_mm512_maskz_inserti64x2() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi64x(9, 10);
         let r = _mm512_maskz_inserti64x2::<2>(0b01101001, a, b);
@@ -8620,7 +8620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundepi64_pd() {
+    fn test_mm512_cvt_roundepi64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvt_roundepi64_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8628,7 +8628,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundepi64_pd() {
+    fn test_mm512_mask_cvt_roundepi64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_pd(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvt_roundepi64_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -8639,7 +8639,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundepi64_pd() {
+    fn test_mm512_maskz_cvt_roundepi64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvt_roundepi64_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -8649,7 +8649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtepi64_pd() {
+    fn test_mm_cvtepi64_pd() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_cvtepi64_pd(a);
         let e = _mm_set_pd(1., 2.);
@@ -8657,7 +8657,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_pd() {
+    fn test_mm_mask_cvtepi64_pd() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_mask_cvtepi64_pd(b, 0b01, a);
@@ -8666,7 +8666,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi64_pd() {
+    fn test_mm_maskz_cvtepi64_pd() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_maskz_cvtepi64_pd(0b01, a);
         let e = _mm_set_pd(0., 2.);
@@ -8674,7 +8674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtepi64_pd() {
+    fn test_mm256_cvtepi64_pd() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepi64_pd(a);
         let e = _mm256_set_pd(1., 2., 3., 4.);
@@ -8682,7 +8682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_pd() {
+    fn test_mm256_mask_cvtepi64_pd() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_pd(5., 6., 7., 8.);
         let r = _mm256_mask_cvtepi64_pd(b, 0b0110, a);
@@ -8691,7 +8691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi64_pd() {
+    fn test_mm256_maskz_cvtepi64_pd() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepi64_pd(0b0110, a);
         let e = _mm256_set_pd(0., 2., 3., 0.);
@@ -8699,7 +8699,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtepi64_pd() {
+    fn test_mm512_cvtepi64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvtepi64_pd(a);
         let e = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8707,7 +8707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtepi64_pd() {
+    fn test_mm512_mask_cvtepi64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_pd(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvtepi64_pd(b, 0b01101001, a);
@@ -8716,7 +8716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtepi64_pd() {
+    fn test_mm512_maskz_cvtepi64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvtepi64_pd(0b01101001, a);
         let e = _mm512_set_pd(0., 2., 3., 0., 5., 0., 0., 8.);
@@ -8724,7 +8724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundepi64_ps() {
+    fn test_mm512_cvt_roundepi64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvt_roundepi64_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8732,7 +8732,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundepi64_ps() {
+    fn test_mm512_mask_cvt_roundepi64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvt_roundepi64_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -8743,7 +8743,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundepi64_ps() {
+    fn test_mm512_maskz_cvt_roundepi64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvt_roundepi64_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -8753,7 +8753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtepi64_ps() {
+    fn test_mm_cvtepi64_ps() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_cvtepi64_ps(a);
         let e = _mm_set_ps(0., 0., 1., 2.);
@@ -8761,7 +8761,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_ps() {
+    fn test_mm_mask_cvtepi64_ps() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_ps(3., 4., 5., 6.);
         let r = _mm_mask_cvtepi64_ps(b, 0b01, a);
@@ -8770,7 +8770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi64_ps() {
+    fn test_mm_maskz_cvtepi64_ps() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_maskz_cvtepi64_ps(0b01, a);
         let e = _mm_set_ps(0., 0., 0., 2.);
@@ -8778,7 +8778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtepi64_ps() {
+    fn test_mm256_cvtepi64_ps() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepi64_ps(a);
         let e = _mm_set_ps(1., 2., 3., 4.);
@@ -8786,7 +8786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_ps() {
+    fn test_mm256_mask_cvtepi64_ps() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_ps(5., 6., 7., 8.);
         let r = _mm256_mask_cvtepi64_ps(b, 0b0110, a);
@@ -8795,7 +8795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi64_ps() {
+    fn test_mm256_maskz_cvtepi64_ps() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepi64_ps(0b0110, a);
         let e = _mm_set_ps(0., 2., 3., 0.);
@@ -8803,7 +8803,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtepi64_ps() {
+    fn test_mm512_cvtepi64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvtepi64_ps(a);
         let e = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8811,7 +8811,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtepi64_ps() {
+    fn test_mm512_mask_cvtepi64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvtepi64_ps(b, 0b01101001, a);
@@ -8820,7 +8820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtepi64_ps() {
+    fn test_mm512_maskz_cvtepi64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvtepi64_ps(0b01101001, a);
         let e = _mm256_set_ps(0., 2., 3., 0., 5., 0., 0., 8.);
@@ -8828,7 +8828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundepu64_pd() {
+    fn test_mm512_cvt_roundepu64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvt_roundepu64_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8836,7 +8836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundepu64_pd() {
+    fn test_mm512_mask_cvt_roundepu64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_pd(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvt_roundepu64_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -8847,7 +8847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundepu64_pd() {
+    fn test_mm512_maskz_cvt_roundepu64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvt_roundepu64_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -8857,7 +8857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtepu64_pd() {
+    fn test_mm_cvtepu64_pd() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_cvtepu64_pd(a);
         let e = _mm_set_pd(1., 2.);
@@ -8865,7 +8865,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu64_pd() {
+    fn test_mm_mask_cvtepu64_pd() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_mask_cvtepu64_pd(b, 0b01, a);
@@ -8874,7 +8874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu64_pd() {
+    fn test_mm_maskz_cvtepu64_pd() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_maskz_cvtepu64_pd(0b01, a);
         let e = _mm_set_pd(0., 2.);
@@ -8882,7 +8882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtepu64_pd() {
+    fn test_mm256_cvtepu64_pd() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepu64_pd(a);
         let e = _mm256_set_pd(1., 2., 3., 4.);
@@ -8890,7 +8890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu64_pd() {
+    fn test_mm256_mask_cvtepu64_pd() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_pd(5., 6., 7., 8.);
         let r = _mm256_mask_cvtepu64_pd(b, 0b0110, a);
@@ -8899,7 +8899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu64_pd() {
+    fn test_mm256_maskz_cvtepu64_pd() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepu64_pd(0b0110, a);
         let e = _mm256_set_pd(0., 2., 3., 0.);
@@ -8907,7 +8907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtepu64_pd() {
+    fn test_mm512_cvtepu64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvtepu64_pd(a);
         let e = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8915,7 +8915,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtepu64_pd() {
+    fn test_mm512_mask_cvtepu64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_pd(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvtepu64_pd(b, 0b01101001, a);
@@ -8924,7 +8924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtepu64_pd() {
+    fn test_mm512_maskz_cvtepu64_pd() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvtepu64_pd(0b01101001, a);
         let e = _mm512_set_pd(0., 2., 3., 0., 5., 0., 0., 8.);
@@ -8932,7 +8932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundepu64_ps() {
+    fn test_mm512_cvt_roundepu64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvt_roundepu64_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -8940,7 +8940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundepu64_ps() {
+    fn test_mm512_mask_cvt_roundepu64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvt_roundepu64_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -8951,7 +8951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundepu64_ps() {
+    fn test_mm512_maskz_cvt_roundepu64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvt_roundepu64_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -8961,7 +8961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtepu64_ps() {
+    fn test_mm_cvtepu64_ps() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_cvtepu64_ps(a);
         let e = _mm_set_ps(0., 0., 1., 2.);
@@ -8969,7 +8969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu64_ps() {
+    fn test_mm_mask_cvtepu64_ps() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_ps(3., 4., 5., 6.);
         let r = _mm_mask_cvtepu64_ps(b, 0b01, a);
@@ -8978,7 +8978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu64_ps() {
+    fn test_mm_maskz_cvtepu64_ps() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_maskz_cvtepu64_ps(0b01, a);
         let e = _mm_set_ps(0., 0., 0., 2.);
@@ -8986,7 +8986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtepu64_ps() {
+    fn test_mm256_cvtepu64_ps() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepu64_ps(a);
         let e = _mm_set_ps(1., 2., 3., 4.);
@@ -8994,7 +8994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu64_ps() {
+    fn test_mm256_mask_cvtepu64_ps() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm_set_ps(5., 6., 7., 8.);
         let r = _mm256_mask_cvtepu64_ps(b, 0b0110, a);
@@ -9003,7 +9003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu64_ps() {
+    fn test_mm256_maskz_cvtepu64_ps() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepu64_ps(0b0110, a);
         let e = _mm_set_ps(0., 2., 3., 0.);
@@ -9011,7 +9011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtepu64_ps() {
+    fn test_mm512_cvtepu64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvtepu64_ps(a);
         let e = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
@@ -9019,7 +9019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtepu64_ps() {
+    fn test_mm512_mask_cvtepu64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let r = _mm512_mask_cvtepu64_ps(b, 0b01101001, a);
@@ -9028,7 +9028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtepu64_ps() {
+    fn test_mm512_maskz_cvtepu64_ps() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvtepu64_ps(0b01101001, a);
         let e = _mm256_set_ps(0., 2., 3., 0., 5., 0., 0., 8.);
@@ -9036,7 +9036,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundpd_epi64() {
+    fn test_mm512_cvt_roundpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvt_roundpd_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9044,7 +9044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundpd_epi64() {
+    fn test_mm512_mask_cvt_roundpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvt_roundpd_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -9055,7 +9055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundpd_epi64() {
+    fn test_mm512_maskz_cvt_roundpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvt_roundpd_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -9065,7 +9065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtpd_epi64() {
+    fn test_mm_cvtpd_epi64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_cvtpd_epi64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -9073,7 +9073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtpd_epi64() {
+    fn test_mm_mask_cvtpd_epi64() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_mask_cvtpd_epi64(b, 0b01, a);
@@ -9082,7 +9082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpd_epi64() {
+    fn test_mm_maskz_cvtpd_epi64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_maskz_cvtpd_epi64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -9090,7 +9090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtpd_epi64() {
+    fn test_mm256_cvtpd_epi64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_cvtpd_epi64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9098,7 +9098,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpd_epi64() {
+    fn test_mm256_mask_cvtpd_epi64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvtpd_epi64(b, 0b0110, a);
@@ -9107,7 +9107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpd_epi64() {
+    fn test_mm256_maskz_cvtpd_epi64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_cvtpd_epi64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9115,7 +9115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtpd_epi64() {
+    fn test_mm512_cvtpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtpd_epi64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9123,7 +9123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtpd_epi64() {
+    fn test_mm512_mask_cvtpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtpd_epi64(b, 0b01101001, a);
@@ -9132,7 +9132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtpd_epi64() {
+    fn test_mm512_maskz_cvtpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtpd_epi64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9140,7 +9140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundps_epi64() {
+    fn test_mm512_cvt_roundps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvt_roundps_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9148,7 +9148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundps_epi64() {
+    fn test_mm512_mask_cvt_roundps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvt_roundps_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -9159,7 +9159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundps_epi64() {
+    fn test_mm512_maskz_cvt_roundps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvt_roundps_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -9169,7 +9169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtps_epi64() {
+    fn test_mm_cvtps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_cvtps_epi64(a);
         let e = _mm_set_epi64x(3, 4);
@@ -9177,7 +9177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtps_epi64() {
+    fn test_mm_mask_cvtps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm_mask_cvtps_epi64(b, 0b01, a);
@@ -9186,7 +9186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtps_epi64() {
+    fn test_mm_maskz_cvtps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_cvtps_epi64(0b01, a);
         let e = _mm_set_epi64x(0, 4);
@@ -9194,7 +9194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtps_epi64() {
+    fn test_mm256_cvtps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_cvtps_epi64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9202,7 +9202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtps_epi64() {
+    fn test_mm256_mask_cvtps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvtps_epi64(b, 0b0110, a);
@@ -9211,7 +9211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtps_epi64() {
+    fn test_mm256_maskz_cvtps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_maskz_cvtps_epi64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9219,7 +9219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtps_epi64() {
+    fn test_mm512_cvtps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtps_epi64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9227,7 +9227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtps_epi64() {
+    fn test_mm512_mask_cvtps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtps_epi64(b, 0b01101001, a);
@@ -9236,7 +9236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtps_epi64() {
+    fn test_mm512_maskz_cvtps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtps_epi64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9244,7 +9244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundpd_epu64() {
+    fn test_mm512_cvt_roundpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvt_roundpd_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9252,7 +9252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundpd_epu64() {
+    fn test_mm512_mask_cvt_roundpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvt_roundpd_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -9263,7 +9263,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundpd_epu64() {
+    fn test_mm512_maskz_cvt_roundpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvt_roundpd_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -9273,7 +9273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtpd_epu64() {
+    fn test_mm_cvtpd_epu64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_cvtpd_epu64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -9281,7 +9281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtpd_epu64() {
+    fn test_mm_mask_cvtpd_epu64() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_mask_cvtpd_epu64(b, 0b01, a);
@@ -9290,7 +9290,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpd_epu64() {
+    fn test_mm_maskz_cvtpd_epu64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_maskz_cvtpd_epu64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -9298,7 +9298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtpd_epu64() {
+    fn test_mm256_cvtpd_epu64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_cvtpd_epu64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9306,7 +9306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpd_epu64() {
+    fn test_mm256_mask_cvtpd_epu64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvtpd_epu64(b, 0b0110, a);
@@ -9315,7 +9315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpd_epu64() {
+    fn test_mm256_maskz_cvtpd_epu64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_cvtpd_epu64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9323,7 +9323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtpd_epu64() {
+    fn test_mm512_cvtpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtpd_epu64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9331,7 +9331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtpd_epu64() {
+    fn test_mm512_mask_cvtpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtpd_epu64(b, 0b01101001, a);
@@ -9340,7 +9340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtpd_epu64() {
+    fn test_mm512_maskz_cvtpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtpd_epu64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9348,7 +9348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvt_roundps_epu64() {
+    fn test_mm512_cvt_roundps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvt_roundps_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9356,7 +9356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvt_roundps_epu64() {
+    fn test_mm512_mask_cvt_roundps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvt_roundps_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -9367,7 +9367,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvt_roundps_epu64() {
+    fn test_mm512_maskz_cvt_roundps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvt_roundps_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01101001, a,
@@ -9377,7 +9377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvtps_epu64() {
+    fn test_mm_cvtps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_cvtps_epu64(a);
         let e = _mm_set_epi64x(3, 4);
@@ -9385,7 +9385,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvtps_epu64() {
+    fn test_mm_mask_cvtps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm_mask_cvtps_epu64(b, 0b01, a);
@@ -9394,7 +9394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvtps_epu64() {
+    fn test_mm_maskz_cvtps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_cvtps_epu64(0b01, a);
         let e = _mm_set_epi64x(0, 4);
@@ -9402,7 +9402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvtps_epu64() {
+    fn test_mm256_cvtps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_cvtps_epu64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9410,7 +9410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvtps_epu64() {
+    fn test_mm256_mask_cvtps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvtps_epu64(b, 0b0110, a);
@@ -9419,7 +9419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtps_epu64() {
+    fn test_mm256_maskz_cvtps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_maskz_cvtps_epu64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9427,7 +9427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtps_epu64() {
+    fn test_mm512_cvtps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtps_epu64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9435,7 +9435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtps_epu64() {
+    fn test_mm512_mask_cvtps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtps_epu64(b, 0b01101001, a);
@@ -9444,7 +9444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtps_epu64() {
+    fn test_mm512_maskz_cvtps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtps_epu64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9452,7 +9452,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtt_roundpd_epi64() {
+    fn test_mm512_cvtt_roundpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtt_roundpd_epi64::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9460,7 +9460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtt_roundpd_epi64() {
+    fn test_mm512_mask_cvtt_roundpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtt_roundpd_epi64::<_MM_FROUND_NO_EXC>(b, 0b01101001, a);
@@ -9469,7 +9469,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtt_roundpd_epi64() {
+    fn test_mm512_maskz_cvtt_roundpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtt_roundpd_epi64::<_MM_FROUND_NO_EXC>(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9477,7 +9477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvttpd_epi64() {
+    fn test_mm_cvttpd_epi64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_cvttpd_epi64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -9485,7 +9485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvttpd_epi64() {
+    fn test_mm_mask_cvttpd_epi64() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_mask_cvttpd_epi64(b, 0b01, a);
@@ -9494,7 +9494,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvttpd_epi64() {
+    fn test_mm_maskz_cvttpd_epi64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_maskz_cvttpd_epi64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -9502,7 +9502,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvttpd_epi64() {
+    fn test_mm256_cvttpd_epi64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_cvttpd_epi64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9510,7 +9510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvttpd_epi64() {
+    fn test_mm256_mask_cvttpd_epi64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvttpd_epi64(b, 0b0110, a);
@@ -9519,7 +9519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttpd_epi64() {
+    fn test_mm256_maskz_cvttpd_epi64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_cvttpd_epi64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9527,7 +9527,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvttpd_epi64() {
+    fn test_mm512_cvttpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvttpd_epi64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9535,7 +9535,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvttpd_epi64() {
+    fn test_mm512_mask_cvttpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvttpd_epi64(b, 0b01101001, a);
@@ -9544,7 +9544,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvttpd_epi64() {
+    fn test_mm512_maskz_cvttpd_epi64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvttpd_epi64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9552,7 +9552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtt_roundps_epi64() {
+    fn test_mm512_cvtt_roundps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtt_roundps_epi64::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9560,7 +9560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtt_roundps_epi64() {
+    fn test_mm512_mask_cvtt_roundps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtt_roundps_epi64::<_MM_FROUND_NO_EXC>(b, 0b01101001, a);
@@ -9569,7 +9569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtt_roundps_epi64() {
+    fn test_mm512_maskz_cvtt_roundps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtt_roundps_epi64::<_MM_FROUND_NO_EXC>(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9577,7 +9577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvttps_epi64() {
+    fn test_mm_cvttps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_cvttps_epi64(a);
         let e = _mm_set_epi64x(3, 4);
@@ -9585,7 +9585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvttps_epi64() {
+    fn test_mm_mask_cvttps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm_mask_cvttps_epi64(b, 0b01, a);
@@ -9594,7 +9594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvttps_epi64() {
+    fn test_mm_maskz_cvttps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_cvttps_epi64(0b01, a);
         let e = _mm_set_epi64x(0, 4);
@@ -9602,7 +9602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvttps_epi64() {
+    fn test_mm256_cvttps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_cvttps_epi64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9610,7 +9610,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvttps_epi64() {
+    fn test_mm256_mask_cvttps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvttps_epi64(b, 0b0110, a);
@@ -9619,7 +9619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttps_epi64() {
+    fn test_mm256_maskz_cvttps_epi64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_maskz_cvttps_epi64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9627,7 +9627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvttps_epi64() {
+    fn test_mm512_cvttps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvttps_epi64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9635,7 +9635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvttps_epi64() {
+    fn test_mm512_mask_cvttps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvttps_epi64(b, 0b01101001, a);
@@ -9644,7 +9644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvttps_epi64() {
+    fn test_mm512_maskz_cvttps_epi64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvttps_epi64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9652,7 +9652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtt_roundpd_epu64() {
+    fn test_mm512_cvtt_roundpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtt_roundpd_epu64::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9660,7 +9660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtt_roundpd_epu64() {
+    fn test_mm512_mask_cvtt_roundpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtt_roundpd_epu64::<_MM_FROUND_NO_EXC>(b, 0b01101001, a);
@@ -9669,7 +9669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtt_roundpd_epu64() {
+    fn test_mm512_maskz_cvtt_roundpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtt_roundpd_epu64::<_MM_FROUND_NO_EXC>(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9677,7 +9677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvttpd_epu64() {
+    fn test_mm_cvttpd_epu64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_cvttpd_epu64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -9685,7 +9685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvttpd_epu64() {
+    fn test_mm_mask_cvttpd_epu64() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_mask_cvttpd_epu64(b, 0b01, a);
@@ -9694,7 +9694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvttpd_epu64() {
+    fn test_mm_maskz_cvttpd_epu64() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_maskz_cvttpd_epu64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -9702,7 +9702,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvttpd_epu64() {
+    fn test_mm256_cvttpd_epu64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_cvttpd_epu64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9710,7 +9710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvttpd_epu64() {
+    fn test_mm256_mask_cvttpd_epu64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvttpd_epu64(b, 0b0110, a);
@@ -9719,7 +9719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttpd_epu64() {
+    fn test_mm256_maskz_cvttpd_epu64() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_cvttpd_epu64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9727,7 +9727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvttpd_epu64() {
+    fn test_mm512_cvttpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvttpd_epu64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9735,7 +9735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvttpd_epu64() {
+    fn test_mm512_mask_cvttpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvttpd_epu64(b, 0b01101001, a);
@@ -9744,7 +9744,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvttpd_epu64() {
+    fn test_mm512_maskz_cvttpd_epu64() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvttpd_epu64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9752,7 +9752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvtt_roundps_epu64() {
+    fn test_mm512_cvtt_roundps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvtt_roundps_epu64::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9760,7 +9760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvtt_roundps_epu64() {
+    fn test_mm512_mask_cvtt_roundps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvtt_roundps_epu64::<_MM_FROUND_NO_EXC>(b, 0b01101001, a);
@@ -9769,7 +9769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvtt_roundps_epu64() {
+    fn test_mm512_maskz_cvtt_roundps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvtt_roundps_epu64::<_MM_FROUND_NO_EXC>(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9777,7 +9777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_cvttps_epu64() {
+    fn test_mm_cvttps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_cvttps_epu64(a);
         let e = _mm_set_epi64x(3, 4);
@@ -9785,7 +9785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_cvttps_epu64() {
+    fn test_mm_mask_cvttps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_epi64x(5, 6);
         let r = _mm_mask_cvttps_epu64(b, 0b01, a);
@@ -9794,7 +9794,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_cvttps_epu64() {
+    fn test_mm_maskz_cvttps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_cvttps_epu64(0b01, a);
         let e = _mm_set_epi64x(0, 4);
@@ -9802,7 +9802,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_cvttps_epu64() {
+    fn test_mm256_cvttps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_cvttps_epu64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -9810,7 +9810,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_cvttps_epu64() {
+    fn test_mm256_mask_cvttps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mask_cvttps_epu64(b, 0b0110, a);
@@ -9819,7 +9819,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttps_epu64() {
+    fn test_mm256_maskz_cvttps_epu64() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm256_maskz_cvttps_epu64(0b0110, a);
         let e = _mm256_set_epi64x(0, 2, 3, 0);
@@ -9827,7 +9827,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_cvttps_epu64() {
+    fn test_mm512_cvttps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_cvttps_epu64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -9835,7 +9835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_cvttps_epu64() {
+    fn test_mm512_mask_cvttps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_cvttps_epu64(b, 0b01101001, a);
@@ -9844,7 +9844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_cvttps_epu64() {
+    fn test_mm512_maskz_cvttps_epu64() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_cvttps_epu64(0b01101001, a);
         let e = _mm512_set_epi64(0, 2, 3, 0, 5, 0, 0, 8);
@@ -9852,7 +9852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mullo_epi64() {
+    const fn test_mm_mullo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_mullo_epi64(a, b);
@@ -9861,7 +9861,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_mask_mullo_epi64() {
+    const fn test_mm_mask_mullo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(3, 4);
         let c = _mm_set_epi64x(5, 6);
@@ -9871,7 +9871,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_maskz_mullo_epi64() {
+    const fn test_mm_maskz_mullo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(3, 4);
         let r = _mm_maskz_mullo_epi64(0b01, a, b);
@@ -9880,7 +9880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mullo_epi64() {
+    const fn test_mm256_mullo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_mullo_epi64(a, b);
@@ -9889,7 +9889,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_mask_mullo_epi64() {
+    const fn test_mm256_mask_mullo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let c = _mm256_set_epi64x(9, 10, 11, 12);
@@ -9899,7 +9899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_maskz_mullo_epi64() {
+    const fn test_mm256_maskz_mullo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(5, 6, 7, 8);
         let r = _mm256_maskz_mullo_epi64(0b0110, a, b);
@@ -9908,7 +9908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mullo_epi64() {
+    const fn test_mm512_mullo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mullo_epi64(a, b);
@@ -9917,7 +9917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_mask_mullo_epi64() {
+    const fn test_mm512_mask_mullo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let c = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
@@ -9927,7 +9927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_maskz_mullo_epi64() {
+    const fn test_mm512_maskz_mullo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_mullo_epi64(0b01101001, a, b);
@@ -9936,7 +9936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_cvtmask8_u32() {
+    const fn test_cvtmask8_u32() {
         let a: __mmask8 = 0b01101001;
         let r = _cvtmask8_u32(a);
         let e: u32 = 0b01101001;
@@ -9944,7 +9944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_cvtu32_mask8() {
+    const fn test_cvtu32_mask8() {
         let a: u32 = 0b01101001;
         let r = _cvtu32_mask8(a);
         let e: __mmask8 = 0b01101001;
@@ -9952,7 +9952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kadd_mask16() {
+    const fn test_kadd_mask16() {
         let a: __mmask16 = 27549;
         let b: __mmask16 = 23434;
         let r = _kadd_mask16(a, b);
@@ -9961,7 +9961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kadd_mask8() {
+    const fn test_kadd_mask8() {
         let a: __mmask8 = 98;
         let b: __mmask8 = 117;
         let r = _kadd_mask8(a, b);
@@ -9970,7 +9970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kand_mask8() {
+    const fn test_kand_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kand_mask8(a, b);
@@ -9979,7 +9979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kandn_mask8() {
+    const fn test_kandn_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kandn_mask8(a, b);
@@ -9988,7 +9988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_knot_mask8() {
+    const fn test_knot_mask8() {
         let a: __mmask8 = 0b01101001;
         let r = _knot_mask8(a);
         let e: __mmask8 = 0b10010110;
@@ -9996,7 +9996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kor_mask8() {
+    const fn test_kor_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kor_mask8(a, b);
@@ -10005,7 +10005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kxnor_mask8() {
+    const fn test_kxnor_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kxnor_mask8(a, b);
@@ -10014,7 +10014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kxor_mask8() {
+    const fn test_kxor_mask8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110011;
         let r = _kxor_mask8(a, b);
@@ -10033,7 +10033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kortestc_mask8_u8() {
+    const fn test_kortestc_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let r = _kortestc_mask8_u8(a, b);
@@ -10041,7 +10041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kortestz_mask8_u8() {
+    const fn test_kortestz_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let r = _kortestz_mask8_u8(a, b);
@@ -10069,7 +10069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kshiftri_mask8() {
+    const fn test_kshiftri_mask8() {
         let a: __mmask8 = 0b10101001;
         let r = _kshiftri_mask8::<3>(a);
         let e: __mmask8 = 0b00010101;
@@ -10099,7 +10099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktestc_mask8_u8() {
+    const fn test_ktestc_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let r = _ktestc_mask8_u8(a, b);
@@ -10107,7 +10107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktestz_mask8_u8() {
+    const fn test_ktestz_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let r = _ktestz_mask8_u8(a, b);
@@ -10125,7 +10125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktestc_mask16_u8() {
+    const fn test_ktestc_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let r = _ktestc_mask16_u8(a, b);
@@ -10133,7 +10133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktestz_mask16_u8() {
+    const fn test_ktestz_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let r = _ktestz_mask16_u8(a, b);
@@ -10158,7 +10158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_movepi32_mask() {
+    const fn test_mm_movepi32_mask() {
         let a = _mm_set_epi32(0, -2, -3, 4);
         let r = _mm_movepi32_mask(a);
         let e = 0b0110;
@@ -10166,7 +10166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_movepi32_mask() {
+    const fn test_mm256_movepi32_mask() {
         let a = _mm256_set_epi32(0, -2, -3, 4, -5, 6, 7, -8);
         let r = _mm256_movepi32_mask(a);
         let e = 0b01101001;
@@ -10174,7 +10174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_movepi32_mask() {
+    const fn test_mm512_movepi32_mask() {
         let a = _mm512_set_epi32(
             0, -2, -3, 4, -5, 6, 7, -8, 9, 10, -11, -12, -13, -14, 15, 16,
         );
@@ -10184,7 +10184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_movepi64_mask() {
+    const fn test_mm_movepi64_mask() {
         let a = _mm_set_epi64x(0, -2);
         let r = _mm_movepi64_mask(a);
         let e = 0b01;
@@ -10192,7 +10192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_movepi64_mask() {
+    const fn test_mm256_movepi64_mask() {
         let a = _mm256_set_epi64x(0, -2, -3, 4);
         let r = _mm256_movepi64_mask(a);
         let e = 0b0110;
@@ -10200,7 +10200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_movepi64_mask() {
+    const fn test_mm512_movepi64_mask() {
         let a = _mm512_set_epi64(0, -2, -3, 4, -5, 6, 7, -8);
         let r = _mm512_movepi64_mask(a);
         let e = 0b01101001;
@@ -10208,7 +10208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_movm_epi32() {
+    const fn test_mm_movm_epi32() {
         let a = 0b0110;
         let r = _mm_movm_epi32(a);
         let e = _mm_set_epi32(0, -1, -1, 0);
@@ -10216,7 +10216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_movm_epi32() {
+    const fn test_mm256_movm_epi32() {
         let a = 0b01101001;
         let r = _mm256_movm_epi32(a);
         let e = _mm256_set_epi32(0, -1, -1, 0, -1, 0, 0, -1);
@@ -10224,7 +10224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_movm_epi32() {
+    const fn test_mm512_movm_epi32() {
         let a = 0b0110100100111100;
         let r = _mm512_movm_epi32(a);
         let e = _mm512_set_epi32(0, -1, -1, 0, -1, 0, 0, -1, 0, 0, -1, -1, -1, -1, 0, 0);
@@ -10232,7 +10232,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm_movm_epi64() {
+    const fn test_mm_movm_epi64() {
         let a = 0b01;
         let r = _mm_movm_epi64(a);
         let e = _mm_set_epi64x(0, -1);
@@ -10240,7 +10240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    const unsafe fn test_mm256_movm_epi64() {
+    const fn test_mm256_movm_epi64() {
         let a = 0b0110;
         let r = _mm256_movm_epi64(a);
         let e = _mm256_set_epi64x(0, -1, -1, 0);
@@ -10248,7 +10248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_mm512_movm_epi64() {
+    const fn test_mm512_movm_epi64() {
         let a = 0b01101001;
         let r = _mm512_movm_epi64(a);
         let e = _mm512_set_epi64(0, -1, -1, 0, -1, 0, 0, -1);
@@ -10256,7 +10256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_range_round_pd() {
+    fn test_mm512_range_round_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(2., 1., 4., 3., 6., 5., 8., 7.);
         let r = _mm512_range_round_pd::<0b0101, _MM_FROUND_NO_EXC>(a, b);
@@ -10265,7 +10265,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_range_round_pd() {
+    fn test_mm512_mask_range_round_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(2., 1., 4., 3., 6., 5., 8., 7.);
         let c = _mm512_set_pd(9., 10., 11., 12., 13., 14., 15., 16.);
@@ -10275,7 +10275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_range_round_pd() {
+    fn test_mm512_maskz_range_round_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(2., 1., 4., 3., 6., 5., 8., 7.);
         let r = _mm512_maskz_range_round_pd::<0b0101, _MM_FROUND_NO_EXC>(0b01101001, a, b);
@@ -10284,7 +10284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_range_pd() {
+    fn test_mm_range_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(2., 1.);
         let r = _mm_range_pd::<0b0101>(a, b);
@@ -10293,7 +10293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_range_pd() {
+    fn test_mm_mask_range_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(2., 1.);
         let c = _mm_set_pd(3., 4.);
@@ -10303,7 +10303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_range_pd() {
+    fn test_mm_maskz_range_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(2., 1.);
         let r = _mm_maskz_range_pd::<0b0101>(0b01, a, b);
@@ -10312,7 +10312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_range_pd() {
+    fn test_mm256_range_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(2., 1., 4., 3.);
         let r = _mm256_range_pd::<0b0101>(a, b);
@@ -10321,7 +10321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_range_pd() {
+    fn test_mm256_mask_range_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(2., 1., 4., 3.);
         let c = _mm256_set_pd(5., 6., 7., 8.);
@@ -10331,7 +10331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_range_pd() {
+    fn test_mm256_maskz_range_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(2., 1., 4., 3.);
         let r = _mm256_maskz_range_pd::<0b0101>(0b0110, a, b);
@@ -10340,7 +10340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_range_pd() {
+    fn test_mm512_range_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(2., 1., 4., 3., 6., 5., 8., 7.);
         let r = _mm512_range_pd::<0b0101>(a, b);
@@ -10349,7 +10349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_range_pd() {
+    fn test_mm512_mask_range_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(2., 1., 4., 3., 6., 5., 8., 7.);
         let c = _mm512_set_pd(9., 10., 11., 12., 13., 14., 15., 16.);
@@ -10359,7 +10359,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_range_pd() {
+    fn test_mm512_maskz_range_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(2., 1., 4., 3., 6., 5., 8., 7.);
         let r = _mm512_maskz_range_pd::<0b0101>(0b01101001, a, b);
@@ -10368,7 +10368,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_range_round_ps() {
+    fn test_mm512_range_round_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -10383,7 +10383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_range_round_ps() {
+    fn test_mm512_mask_range_round_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -10402,7 +10402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_range_round_ps() {
+    fn test_mm512_maskz_range_round_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -10417,7 +10417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_range_ps() {
+    fn test_mm_range_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(2., 1., 4., 3.);
         let r = _mm_range_ps::<0b0101>(a, b);
@@ -10426,7 +10426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_range_ps() {
+    fn test_mm_mask_range_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(2., 1., 4., 3.);
         let c = _mm_set_ps(5., 6., 7., 8.);
@@ -10436,7 +10436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_range_ps() {
+    fn test_mm_maskz_range_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(2., 1., 4., 3.);
         let r = _mm_maskz_range_ps::<0b0101>(0b0110, a, b);
@@ -10445,7 +10445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_range_ps() {
+    fn test_mm256_range_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(2., 1., 4., 3., 6., 5., 8., 7.);
         let r = _mm256_range_ps::<0b0101>(a, b);
@@ -10454,7 +10454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_range_ps() {
+    fn test_mm256_mask_range_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(2., 1., 4., 3., 6., 5., 8., 7.);
         let c = _mm256_set_ps(9., 10., 11., 12., 13., 14., 15., 16.);
@@ -10464,7 +10464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_range_ps() {
+    fn test_mm256_maskz_range_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(2., 1., 4., 3., 6., 5., 8., 7.);
         let r = _mm256_maskz_range_ps::<0b0101>(0b01101001, a, b);
@@ -10473,7 +10473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_range_ps() {
+    fn test_mm512_range_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -10488,7 +10488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_range_ps() {
+    fn test_mm512_mask_range_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -10506,7 +10506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_range_ps() {
+    fn test_mm512_maskz_range_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -10521,7 +10521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_range_round_sd() {
+    fn test_mm_range_round_sd() {
         let a = _mm_set_sd(1.);
         let b = _mm_set_sd(2.);
         let r = _mm_range_round_sd::<0b0101, _MM_FROUND_NO_EXC>(a, b);
@@ -10530,7 +10530,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_range_round_sd() {
+    fn test_mm_mask_range_round_sd() {
         let a = _mm_set_sd(1.);
         let b = _mm_set_sd(2.);
         let c = _mm_set_sd(3.);
@@ -10540,7 +10540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_range_round_sd() {
+    fn test_mm_maskz_range_round_sd() {
         let a = _mm_set_sd(1.);
         let b = _mm_set_sd(2.);
         let r = _mm_maskz_range_round_sd::<0b0101, _MM_FROUND_NO_EXC>(0b0, a, b);
@@ -10549,7 +10549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_range_sd() {
+    fn test_mm_mask_range_sd() {
         let a = _mm_set_sd(1.);
         let b = _mm_set_sd(2.);
         let c = _mm_set_sd(3.);
@@ -10559,7 +10559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_range_sd() {
+    fn test_mm_maskz_range_sd() {
         let a = _mm_set_sd(1.);
         let b = _mm_set_sd(2.);
         let r = _mm_maskz_range_sd::<0b0101>(0b0, a, b);
@@ -10568,7 +10568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_range_round_ss() {
+    fn test_mm_range_round_ss() {
         let a = _mm_set_ss(1.);
         let b = _mm_set_ss(2.);
         let r = _mm_range_round_ss::<0b0101, _MM_FROUND_NO_EXC>(a, b);
@@ -10577,7 +10577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_range_round_ss() {
+    fn test_mm_mask_range_round_ss() {
         let a = _mm_set_ss(1.);
         let b = _mm_set_ss(2.);
         let c = _mm_set_ss(3.);
@@ -10587,7 +10587,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_range_round_ss() {
+    fn test_mm_maskz_range_round_ss() {
         let a = _mm_set_ss(1.);
         let b = _mm_set_ss(2.);
         let r = _mm_maskz_range_round_ss::<0b0101, _MM_FROUND_NO_EXC>(0b0, a, b);
@@ -10596,7 +10596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_range_ss() {
+    fn test_mm_mask_range_ss() {
         let a = _mm_set_ss(1.);
         let b = _mm_set_ss(2.);
         let c = _mm_set_ss(3.);
@@ -10606,7 +10606,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_range_ss() {
+    fn test_mm_maskz_range_ss() {
         let a = _mm_set_ss(1.);
         let b = _mm_set_ss(2.);
         let r = _mm_maskz_range_ss::<0b0101>(0b0, a, b);
@@ -10615,7 +10615,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_reduce_round_pd() {
+    fn test_mm512_reduce_round_pd() {
         let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let r = _mm512_reduce_round_pd::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_pd(0.25, 0., 0.25, 0., 0.25, 0., 0.25, 0.);
@@ -10623,7 +10623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_reduce_round_pd() {
+    fn test_mm512_mask_reduce_round_pd() {
         let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let src = _mm512_set_pd(3., 4., 5., 6., 7., 8., 9., 10.);
         let r = _mm512_mask_reduce_round_pd::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
@@ -10634,7 +10634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_reduce_round_pd() {
+    fn test_mm512_maskz_reduce_round_pd() {
         let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let r = _mm512_maskz_reduce_round_pd::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
             0b01101001, a,
@@ -10644,7 +10644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_reduce_pd() {
+    fn test_mm_reduce_pd() {
         let a = _mm_set_pd(0.25, 0.50);
         let r = _mm_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm_set_pd(0.25, 0.);
@@ -10652,7 +10652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_reduce_pd() {
+    fn test_mm_mask_reduce_pd() {
         let a = _mm_set_pd(0.25, 0.50);
         let src = _mm_set_pd(3., 4.);
         let r = _mm_mask_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01, a);
@@ -10661,7 +10661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_reduce_pd() {
+    fn test_mm_maskz_reduce_pd() {
         let a = _mm_set_pd(0.25, 0.50);
         let r = _mm_maskz_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(0b01, a);
         let e = _mm_set_pd(0., 0.);
@@ -10669,7 +10669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_reduce_pd() {
+    fn test_mm256_reduce_pd() {
         let a = _mm256_set_pd(0.25, 0.50, 0.75, 1.0);
         let r = _mm256_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm256_set_pd(0.25, 0., 0.25, 0.);
@@ -10677,7 +10677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_pd() {
+    fn test_mm256_mask_reduce_pd() {
         let a = _mm256_set_pd(0.25, 0.50, 0.75, 1.0);
         let src = _mm256_set_pd(3., 4., 5., 6.);
         let r = _mm256_mask_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0110, a);
@@ -10686,7 +10686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_reduce_pd() {
+    fn test_mm256_maskz_reduce_pd() {
         let a = _mm256_set_pd(0.25, 0.50, 0.75, 1.0);
         let r = _mm256_maskz_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(0b0110, a);
         let e = _mm256_set_pd(0., 0., 0.25, 0.);
@@ -10694,7 +10694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_reduce_pd() {
+    fn test_mm512_reduce_pd() {
         let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let r = _mm512_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm512_set_pd(0.25, 0., 0.25, 0., 0.25, 0., 0.25, 0.);
@@ -10702,7 +10702,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_reduce_pd() {
+    fn test_mm512_mask_reduce_pd() {
         let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let src = _mm512_set_pd(3., 4., 5., 6., 7., 8., 9., 10.);
         let r = _mm512_mask_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01101001, a);
@@ -10711,7 +10711,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_reduce_pd() {
+    fn test_mm512_maskz_reduce_pd() {
         let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let r = _mm512_maskz_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(0b01101001, a);
         let e = _mm512_set_pd(0., 0., 0.25, 0., 0.25, 0., 0., 0.);
@@ -10719,7 +10719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_reduce_round_ps() {
+    fn test_mm512_reduce_round_ps() {
         let a = _mm512_set_ps(
             0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0, 2.25, 2.50, 2.75, 3.0, 3.25, 3.50, 3.75,
             4.0,
@@ -10732,7 +10732,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_reduce_round_ps() {
+    fn test_mm512_mask_reduce_round_ps() {
         let a = _mm512_set_ps(
             0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0, 2.25, 2.50, 2.75, 3.0, 3.25, 3.50, 3.75,
             4.0,
@@ -10752,7 +10752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_reduce_round_ps() {
+    fn test_mm512_maskz_reduce_round_ps() {
         let a = _mm512_set_ps(
             0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0, 2.25, 2.50, 2.75, 3.0, 3.25, 3.50, 3.75,
             4.0,
@@ -10768,7 +10768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_reduce_ps() {
+    fn test_mm_reduce_ps() {
         let a = _mm_set_ps(0.25, 0.50, 0.75, 1.0);
         let r = _mm_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm_set_ps(0.25, 0., 0.25, 0.);
@@ -10776,7 +10776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_reduce_ps() {
+    fn test_mm_mask_reduce_ps() {
         let a = _mm_set_ps(0.25, 0.50, 0.75, 1.0);
         let src = _mm_set_ps(2., 3., 4., 5.);
         let r = _mm_mask_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0110, a);
@@ -10785,7 +10785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_maskz_reduce_ps() {
+    fn test_mm_maskz_reduce_ps() {
         let a = _mm_set_ps(0.25, 0.50, 0.75, 1.0);
         let r = _mm_maskz_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(0b0110, a);
         let e = _mm_set_ps(0., 0., 0.25, 0.);
@@ -10793,7 +10793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_reduce_ps() {
+    fn test_mm256_reduce_ps() {
         let a = _mm256_set_ps(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let r = _mm256_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm256_set_ps(0.25, 0., 0.25, 0., 0.25, 0., 0.25, 0.);
@@ -10801,7 +10801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_ps() {
+    fn test_mm256_mask_reduce_ps() {
         let a = _mm256_set_ps(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let src = _mm256_set_ps(3., 4., 5., 6., 7., 8., 9., 10.);
         let r = _mm256_mask_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01101001, a);
@@ -10810,7 +10810,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_maskz_reduce_ps() {
+    fn test_mm256_maskz_reduce_ps() {
         let a = _mm256_set_ps(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0);
         let r = _mm256_maskz_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(0b01101001, a);
         let e = _mm256_set_ps(0., 0., 0.25, 0., 0.25, 0., 0., 0.);
@@ -10818,7 +10818,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_reduce_ps() {
+    fn test_mm512_reduce_ps() {
         let a = _mm512_set_ps(
             0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0, 2.25, 2.50, 2.75, 3.0, 3.25, 3.50, 3.75,
             4.0,
@@ -10831,7 +10831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_reduce_ps() {
+    fn test_mm512_mask_reduce_ps() {
         let a = _mm512_set_ps(
             0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0, 2.25, 2.50, 2.75, 3.0, 3.25, 3.50, 3.75,
             4.0,
@@ -10847,7 +10847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_maskz_reduce_ps() {
+    fn test_mm512_maskz_reduce_ps() {
         let a = _mm512_set_ps(
             0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0, 2.25, 2.50, 2.75, 3.0, 3.25, 3.50, 3.75,
             4.0,
@@ -10860,7 +10860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_reduce_round_sd() {
+    fn test_mm_reduce_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_sd(0.25);
         let r = _mm_reduce_round_sd::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a, b);
@@ -10869,7 +10869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_reduce_round_sd() {
+    fn test_mm_mask_reduce_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_sd(0.25);
         let c = _mm_set_pd(3., 4.);
@@ -10881,7 +10881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_reduce_round_sd() {
+    fn test_mm_maskz_reduce_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_sd(0.25);
         let r =
@@ -10891,7 +10891,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_reduce_sd() {
+    fn test_mm_reduce_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_sd(0.25);
         let r = _mm_reduce_sd::<{ 16 | _MM_FROUND_TO_ZERO }>(a, b);
@@ -10900,7 +10900,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_reduce_sd() {
+    fn test_mm_mask_reduce_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_sd(0.25);
         let c = _mm_set_pd(3., 4.);
@@ -10910,7 +10910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_reduce_sd() {
+    fn test_mm_maskz_reduce_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_sd(0.25);
         let r = _mm_maskz_reduce_sd::<{ 16 | _MM_FROUND_TO_ZERO }>(0b0, a, b);
@@ -10919,7 +10919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_reduce_round_ss() {
+    fn test_mm_reduce_round_ss() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ss(0.25);
         let r = _mm_reduce_round_ss::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a, b);
@@ -10928,7 +10928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_reduce_round_ss() {
+    fn test_mm_mask_reduce_round_ss() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ss(0.25);
         let c = _mm_set_ps(5., 6., 7., 8.);
@@ -10940,7 +10940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_reduce_round_ss() {
+    fn test_mm_maskz_reduce_round_ss() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ss(0.25);
         let r =
@@ -10950,7 +10950,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_reduce_ss() {
+    fn test_mm_reduce_ss() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ss(0.25);
         let r = _mm_reduce_ss::<{ 16 | _MM_FROUND_TO_ZERO }>(a, b);
@@ -10959,7 +10959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_reduce_ss() {
+    fn test_mm_mask_reduce_ss() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ss(0.25);
         let c = _mm_set_ps(5., 6., 7., 8.);
@@ -10969,7 +10969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_maskz_reduce_ss() {
+    fn test_mm_maskz_reduce_ss() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ss(0.25);
         let r = _mm_maskz_reduce_ss::<{ 16 | _MM_FROUND_TO_ZERO }>(0b0, a, b);
@@ -10978,7 +10978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_fpclass_pd_mask() {
+    fn test_mm_fpclass_pd_mask() {
         let a = _mm_set_pd(1., f64::INFINITY);
         let r = _mm_fpclass_pd_mask::<0x18>(a);
         let e = 0b01;
@@ -10986,7 +10986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_fpclass_pd_mask() {
+    fn test_mm_mask_fpclass_pd_mask() {
         let a = _mm_set_pd(1., f64::INFINITY);
         let r = _mm_mask_fpclass_pd_mask::<0x18>(0b10, a);
         let e = 0b00;
@@ -10994,7 +10994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_fpclass_pd_mask() {
+    fn test_mm256_fpclass_pd_mask() {
         let a = _mm256_set_pd(1., f64::INFINITY, f64::NEG_INFINITY, 0.0);
         let r = _mm256_fpclass_pd_mask::<0x18>(a);
         let e = 0b0110;
@@ -11002,7 +11002,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_fpclass_pd_mask() {
+    fn test_mm256_mask_fpclass_pd_mask() {
         let a = _mm256_set_pd(1., f64::INFINITY, f64::NEG_INFINITY, 0.0);
         let r = _mm256_mask_fpclass_pd_mask::<0x18>(0b1010, a);
         let e = 0b0010;
@@ -11010,7 +11010,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_fpclass_pd_mask() {
+    fn test_mm512_fpclass_pd_mask() {
         let a = _mm512_set_pd(
             1.,
             f64::INFINITY,
@@ -11027,7 +11027,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_fpclass_pd_mask() {
+    fn test_mm512_mask_fpclass_pd_mask() {
         let a = _mm512_set_pd(
             1.,
             f64::INFINITY,
@@ -11044,7 +11044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_fpclass_ps_mask() {
+    fn test_mm_fpclass_ps_mask() {
         let a = _mm_set_ps(1., f32::INFINITY, f32::NEG_INFINITY, 0.0);
         let r = _mm_fpclass_ps_mask::<0x18>(a);
         let e = 0b0110;
@@ -11052,7 +11052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm_mask_fpclass_ps_mask() {
+    fn test_mm_mask_fpclass_ps_mask() {
         let a = _mm_set_ps(1., f32::INFINITY, f32::NEG_INFINITY, 0.0);
         let r = _mm_mask_fpclass_ps_mask::<0x18>(0b1010, a);
         let e = 0b0010;
@@ -11060,7 +11060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_fpclass_ps_mask() {
+    fn test_mm256_fpclass_ps_mask() {
         let a = _mm256_set_ps(
             1.,
             f32::INFINITY,
@@ -11077,7 +11077,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq,avx512vl")]
-    unsafe fn test_mm256_mask_fpclass_ps_mask() {
+    fn test_mm256_mask_fpclass_ps_mask() {
         let a = _mm256_set_ps(
             1.,
             f32::INFINITY,
@@ -11094,7 +11094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_fpclass_ps_mask() {
+    fn test_mm512_fpclass_ps_mask() {
         let a = _mm512_set_ps(
             1.,
             f32::INFINITY,
@@ -11119,7 +11119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm512_mask_fpclass_ps_mask() {
+    fn test_mm512_mask_fpclass_ps_mask() {
         let a = _mm512_set_ps(
             1.,
             f32::INFINITY,
@@ -11144,7 +11144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_fpclass_sd_mask() {
+    fn test_mm_fpclass_sd_mask() {
         let a = _mm_set_pd(1., f64::INFINITY);
         let r = _mm_fpclass_sd_mask::<0x18>(a);
         let e = 0b1;
@@ -11152,7 +11152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_fpclass_sd_mask() {
+    fn test_mm_mask_fpclass_sd_mask() {
         let a = _mm_set_sd(f64::INFINITY);
         let r = _mm_mask_fpclass_sd_mask::<0x18>(0b0, a);
         let e = 0b0;
@@ -11160,7 +11160,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_fpclass_ss_mask() {
+    fn test_mm_fpclass_ss_mask() {
         let a = _mm_set_ss(f32::INFINITY);
         let r = _mm_fpclass_ss_mask::<0x18>(a);
         let e = 0b1;
@@ -11168,7 +11168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    unsafe fn test_mm_mask_fpclass_ss_mask() {
+    fn test_mm_mask_fpclass_ss_mask() {
         let a = _mm_set_ss(f32::INFINITY);
         let r = _mm_mask_fpclass_ss_mask::<0x18>(0b0, a);
         let e = 0b0;
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index f300bf48ef..f1e6ea30c4 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -45033,7 +45033,7 @@ mod tests {
     use crate::mem::{self};
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_abs_epi32() {
+    const fn test_mm512_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45053,7 +45053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_abs_epi32() {
+    const fn test_mm512_mask_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45075,7 +45075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_abs_epi32() {
+    const fn test_mm512_maskz_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45097,7 +45097,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_abs_epi32() {
+    const fn test_mm256_mask_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45115,7 +45115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_abs_epi32() {
+    const fn test_mm256_maskz_abs_epi32() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45133,7 +45133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_abs_epi32() {
+    const fn test_mm_mask_abs_epi32() {
         let a = _mm_setr_epi32(i32::MIN, 100, -100, -32);
         let r = _mm_mask_abs_epi32(a, 0, a);
         assert_eq_m128i(r, a);
@@ -45143,7 +45143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_abs_epi32() {
+    const fn test_mm_maskz_abs_epi32() {
         let a = _mm_setr_epi32(i32::MIN, 100, -100, -32);
         let r = _mm_maskz_abs_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -45153,7 +45153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_abs_ps() {
+    const fn test_mm512_abs_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45173,7 +45173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_abs_ps() {
+    const fn test_mm512_mask_abs_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45195,7 +45195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mov_epi32() {
+    const fn test_mm512_mask_mov_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(2);
         let r = _mm512_mask_mov_epi32(src, 0, a);
@@ -45205,7 +45205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mov_epi32() {
+    const fn test_mm512_maskz_mov_epi32() {
         let a = _mm512_set1_epi32(2);
         let r = _mm512_maskz_mov_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -45214,7 +45214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mov_epi32() {
+    const fn test_mm256_mask_mov_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(2);
         let r = _mm256_mask_mov_epi32(src, 0, a);
@@ -45224,7 +45224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mov_epi32() {
+    const fn test_mm256_maskz_mov_epi32() {
         let a = _mm256_set1_epi32(2);
         let r = _mm256_maskz_mov_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -45233,7 +45233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mov_epi32() {
+    const fn test_mm_mask_mov_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(2);
         let r = _mm_mask_mov_epi32(src, 0, a);
@@ -45243,7 +45243,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mov_epi32() {
+    const fn test_mm_maskz_mov_epi32() {
         let a = _mm_set1_epi32(2);
         let r = _mm_maskz_mov_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -45252,7 +45252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mov_ps() {
+    const fn test_mm512_mask_mov_ps() {
         let src = _mm512_set1_ps(1.);
         let a = _mm512_set1_ps(2.);
         let r = _mm512_mask_mov_ps(src, 0, a);
@@ -45262,7 +45262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mov_ps() {
+    const fn test_mm512_maskz_mov_ps() {
         let a = _mm512_set1_ps(2.);
         let r = _mm512_maskz_mov_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -45271,7 +45271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mov_ps() {
+    const fn test_mm256_mask_mov_ps() {
         let src = _mm256_set1_ps(1.);
         let a = _mm256_set1_ps(2.);
         let r = _mm256_mask_mov_ps(src, 0, a);
@@ -45281,7 +45281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mov_ps() {
+    const fn test_mm256_maskz_mov_ps() {
         let a = _mm256_set1_ps(2.);
         let r = _mm256_maskz_mov_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -45290,7 +45290,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mov_ps() {
+    const fn test_mm_mask_mov_ps() {
         let src = _mm_set1_ps(1.);
         let a = _mm_set1_ps(2.);
         let r = _mm_mask_mov_ps(src, 0, a);
@@ -45300,7 +45300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mov_ps() {
+    const fn test_mm_maskz_mov_ps() {
         let a = _mm_set1_ps(2.);
         let r = _mm_maskz_mov_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -45309,7 +45309,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_add_epi32() {
+    const fn test_mm512_add_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45330,7 +45330,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_add_epi32() {
+    const fn test_mm512_mask_add_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45353,7 +45353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_add_epi32() {
+    const fn test_mm512_maskz_add_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45376,7 +45376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_add_epi32() {
+    const fn test_mm256_mask_add_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_add_epi32(a, 0, a, b);
@@ -45387,7 +45387,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_epi32() {
+    const fn test_mm256_maskz_add_epi32() {
         let a = _mm256_setr_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_add_epi32(0, a, b);
@@ -45398,7 +45398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_add_epi32() {
+    const fn test_mm_mask_add_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_add_epi32(a, 0, a, b);
@@ -45409,7 +45409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_add_epi32() {
+    const fn test_mm_maskz_add_epi32() {
         let a = _mm_setr_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_add_epi32(0, a, b);
@@ -45420,7 +45420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_add_ps() {
+    const fn test_mm512_add_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45441,7 +45441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_add_ps() {
+    const fn test_mm512_mask_add_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45464,7 +45464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_add_ps() {
+    const fn test_mm512_maskz_add_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45487,7 +45487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_add_ps() {
+    const fn test_mm256_mask_add_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_mask_add_ps(a, 0, a, b);
@@ -45498,7 +45498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_ps() {
+    const fn test_mm256_maskz_add_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_maskz_add_ps(0, a, b);
@@ -45509,7 +45509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_add_ps() {
+    const fn test_mm_mask_add_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_mask_add_ps(a, 0, a, b);
@@ -45520,7 +45520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_add_ps() {
+    const fn test_mm_maskz_add_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_maskz_add_ps(0, a, b);
@@ -45531,7 +45531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_sub_epi32() {
+    const fn test_mm512_sub_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45552,7 +45552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_sub_epi32() {
+    const fn test_mm512_mask_sub_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45575,7 +45575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_sub_epi32() {
+    const fn test_mm512_maskz_sub_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45598,7 +45598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_epi32() {
+    const fn test_mm256_mask_sub_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_sub_epi32(a, 0, a, b);
@@ -45609,7 +45609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_epi32() {
+    const fn test_mm256_maskz_sub_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_sub_epi32(0, a, b);
@@ -45620,7 +45620,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_sub_epi32() {
+    const fn test_mm_mask_sub_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_sub_epi32(a, 0, a, b);
@@ -45631,7 +45631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_epi32() {
+    const fn test_mm_maskz_sub_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_sub_epi32(0, a, b);
@@ -45642,7 +45642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_sub_ps() {
+    const fn test_mm512_sub_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45663,7 +45663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_sub_ps() {
+    const fn test_mm512_mask_sub_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45686,7 +45686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_sub_ps() {
+    const fn test_mm512_maskz_sub_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45709,7 +45709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_ps() {
+    const fn test_mm256_mask_sub_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_mask_sub_ps(a, 0, a, b);
@@ -45720,7 +45720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_ps() {
+    const fn test_mm256_maskz_sub_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(1.);
         let r = _mm256_maskz_sub_ps(0, a, b);
@@ -45731,7 +45731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_sub_ps() {
+    const fn test_mm_mask_sub_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_mask_sub_ps(a, 0, a, b);
@@ -45742,7 +45742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_ps() {
+    const fn test_mm_maskz_sub_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(1.);
         let r = _mm_maskz_sub_ps(0, a, b);
@@ -45753,7 +45753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mullo_epi32() {
+    const fn test_mm512_mullo_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45770,7 +45770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mullo_epi32() {
+    const fn test_mm512_mask_mullo_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45793,7 +45793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mullo_epi32() {
+    const fn test_mm512_maskz_mullo_epi32() {
         #[rustfmt::skip]
         let a = _mm512_setr_epi32(
             0, 1, -1, i32::MAX,
@@ -45810,7 +45810,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mullo_epi32() {
+    const fn test_mm256_mask_mullo_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_mask_mullo_epi32(a, 0, a, b);
@@ -45821,7 +45821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mullo_epi32() {
+    const fn test_mm256_maskz_mullo_epi32() {
         let a = _mm256_set_epi32(0, 1, -1, i32::MAX, i32::MIN, 100, -100, -32);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_maskz_mullo_epi32(0, a, b);
@@ -45832,7 +45832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mullo_epi32() {
+    const fn test_mm_mask_mullo_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(2);
         let r = _mm_mask_mullo_epi32(a, 0, a, b);
@@ -45843,7 +45843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mullo_epi32() {
+    const fn test_mm_maskz_mullo_epi32() {
         let a = _mm_set_epi32(1, -1, i32::MAX, i32::MIN);
         let b = _mm_set1_epi32(2);
         let r = _mm_maskz_mullo_epi32(0, a, b);
@@ -45854,7 +45854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mul_ps() {
+    const fn test_mm512_mul_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45876,7 +45876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mul_ps() {
+    const fn test_mm512_mask_mul_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45899,7 +45899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mul_ps() {
+    const fn test_mm512_maskz_mul_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1., -1., f32::MAX,
@@ -45922,7 +45922,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mul_ps() {
+    const fn test_mm256_mask_mul_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(2.);
         let r = _mm256_mask_mul_ps(a, 0, a, b);
@@ -45937,7 +45937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mul_ps() {
+    const fn test_mm256_maskz_mul_ps() {
         let a = _mm256_set_ps(0., 1., -1., f32::MAX, f32::MIN, 100., -100., -32.);
         let b = _mm256_set1_ps(2.);
         let r = _mm256_maskz_mul_ps(0, a, b);
@@ -45952,7 +45952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mul_ps() {
+    const fn test_mm_mask_mul_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(2.);
         let r = _mm_mask_mul_ps(a, 0, a, b);
@@ -45963,7 +45963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mul_ps() {
+    const fn test_mm_maskz_mul_ps() {
         let a = _mm_set_ps(1., -1., f32::MAX, f32::MIN);
         let b = _mm_set1_ps(2.);
         let r = _mm_maskz_mul_ps(0, a, b);
@@ -45974,7 +45974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_div_ps() {
+    const fn test_mm512_div_ps() {
         let a = _mm512_setr_ps(
             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
         );
@@ -45993,7 +45993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_div_ps() {
+    const fn test_mm512_mask_div_ps() {
         let a = _mm512_setr_ps(
             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
         );
@@ -46014,7 +46014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_div_ps() {
+    const fn test_mm512_maskz_div_ps() {
         let a = _mm512_setr_ps(
             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
         );
@@ -46035,7 +46035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_div_ps() {
+    const fn test_mm256_mask_div_ps() {
         let a = _mm256_set_ps(0., 1., -1., -2., 100., 100., -100., -32.);
         let b = _mm256_set_ps(2., 2., 2., 2., 2., 0., 2., 2.);
         let r = _mm256_mask_div_ps(a, 0, a, b);
@@ -46046,7 +46046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_div_ps() {
+    const fn test_mm256_maskz_div_ps() {
         let a = _mm256_set_ps(0., 1., -1., -2., 100., 100., -100., -32.);
         let b = _mm256_set_ps(2., 2., 2., 2., 2., 0., 2., 2.);
         let r = _mm256_maskz_div_ps(0, a, b);
@@ -46057,7 +46057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_div_ps() {
+    const fn test_mm_mask_div_ps() {
         let a = _mm_set_ps(100., 100., -100., -32.);
         let b = _mm_set_ps(2., 0., 2., 2.);
         let r = _mm_mask_div_ps(a, 0, a, b);
@@ -46068,7 +46068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_div_ps() {
+    const fn test_mm_maskz_div_ps() {
         let a = _mm_set_ps(100., 100., -100., -32.);
         let b = _mm_set_ps(2., 0., 2., 2.);
         let r = _mm_maskz_div_ps(0, a, b);
@@ -46079,7 +46079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_max_epi32() {
+    const fn test_mm512_max_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epi32(a, b);
@@ -46088,7 +46088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_max_epi32() {
+    const fn test_mm512_mask_max_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epi32(a, 0, a, b);
@@ -46099,7 +46099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_max_epi32() {
+    const fn test_mm512_maskz_max_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epi32(0, a, b);
@@ -46110,7 +46110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epi32() {
+    const fn test_mm256_mask_max_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epi32(a, 0, a, b);
@@ -46121,7 +46121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epi32() {
+    const fn test_mm256_maskz_max_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epi32(0, a, b);
@@ -46132,7 +46132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_max_epi32() {
+    const fn test_mm_mask_max_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_max_epi32(a, 0, a, b);
@@ -46143,7 +46143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epi32() {
+    const fn test_mm_maskz_max_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_max_epi32(0, a, b);
@@ -46154,7 +46154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_ps() {
+    fn test_mm512_max_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -46169,7 +46169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_ps() {
+    fn test_mm512_mask_max_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -46186,7 +46186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_ps() {
+    fn test_mm512_maskz_max_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -46203,7 +46203,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_max_ps() {
+    fn test_mm256_mask_max_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm256_set_ps(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm256_mask_max_ps(a, 0, a, b);
@@ -46214,7 +46214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_max_ps() {
+    fn test_mm256_maskz_max_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm256_set_ps(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm256_maskz_max_ps(0, a, b);
@@ -46225,7 +46225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_max_ps() {
+    fn test_mm_mask_max_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(3., 2., 1., 0.);
         let r = _mm_mask_max_ps(a, 0, a, b);
@@ -46236,7 +46236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_max_ps() {
+    fn test_mm_maskz_max_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(3., 2., 1., 0.);
         let r = _mm_maskz_max_ps(0, a, b);
@@ -46247,7 +46247,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_max_epu32() {
+    const fn test_mm512_max_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epu32(a, b);
@@ -46256,7 +46256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_max_epu32() {
+    const fn test_mm512_mask_max_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epu32(a, 0, a, b);
@@ -46267,7 +46267,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_max_epu32() {
+    const fn test_mm512_maskz_max_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epu32(0, a, b);
@@ -46278,7 +46278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epu32() {
+    const fn test_mm256_mask_max_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_max_epu32(a, 0, a, b);
@@ -46289,7 +46289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epu32() {
+    const fn test_mm256_maskz_max_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_max_epu32(0, a, b);
@@ -46300,7 +46300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_max_epu32() {
+    const fn test_mm_mask_max_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_max_epu32(a, 0, a, b);
@@ -46311,7 +46311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epu32() {
+    const fn test_mm_maskz_max_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_max_epu32(0, a, b);
@@ -46322,7 +46322,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_min_epi32() {
+    const fn test_mm512_min_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epi32(a, b);
@@ -46331,7 +46331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_min_epi32() {
+    const fn test_mm512_mask_min_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epi32(a, 0, a, b);
@@ -46342,7 +46342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_min_epi32() {
+    const fn test_mm512_maskz_min_epi32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epi32(0, a, b);
@@ -46353,7 +46353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epi32() {
+    const fn test_mm256_mask_min_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epi32(a, 0, a, b);
@@ -46364,7 +46364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epi32() {
+    const fn test_mm256_maskz_min_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epi32(0, a, b);
@@ -46375,7 +46375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_min_epi32() {
+    const fn test_mm_mask_min_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_min_epi32(a, 0, a, b);
@@ -46386,7 +46386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epi32() {
+    const fn test_mm_maskz_min_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_min_epi32(0, a, b);
@@ -46397,7 +46397,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_ps() {
+    fn test_mm512_min_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -46412,7 +46412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_ps() {
+    fn test_mm512_mask_min_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -46429,7 +46429,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_ps() {
+    fn test_mm512_maskz_min_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -46446,7 +46446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_min_ps() {
+    fn test_mm256_mask_min_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm256_set_ps(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm256_mask_min_ps(a, 0, a, b);
@@ -46457,7 +46457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_min_ps() {
+    fn test_mm256_maskz_min_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm256_set_ps(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm256_maskz_min_ps(0, a, b);
@@ -46468,7 +46468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_min_ps() {
+    fn test_mm_mask_min_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(3., 2., 1., 0.);
         let r = _mm_mask_min_ps(a, 0, a, b);
@@ -46479,7 +46479,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_min_ps() {
+    fn test_mm_maskz_min_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(3., 2., 1., 0.);
         let r = _mm_maskz_min_ps(0, a, b);
@@ -46490,7 +46490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_min_epu32() {
+    const fn test_mm512_min_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epu32(a, b);
@@ -46499,7 +46499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_min_epu32() {
+    const fn test_mm512_mask_min_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epu32(a, 0, a, b);
@@ -46510,7 +46510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_min_epu32() {
+    const fn test_mm512_maskz_min_epu32() {
         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epu32(0, a, b);
@@ -46521,7 +46521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epu32() {
+    const fn test_mm256_mask_min_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_mask_min_epu32(a, 0, a, b);
@@ -46532,7 +46532,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epu32() {
+    const fn test_mm256_maskz_min_epu32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm256_maskz_min_epu32(0, a, b);
@@ -46543,7 +46543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_min_epu32() {
+    const fn test_mm_mask_min_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_mask_min_epu32(a, 0, a, b);
@@ -46554,7 +46554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epu32() {
+    const fn test_mm_maskz_min_epu32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let b = _mm_set_epi32(3, 2, 1, 0);
         let r = _mm_maskz_min_epu32(0, a, b);
@@ -46565,7 +46565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sqrt_ps() {
+    fn test_mm512_sqrt_ps() {
         let a = _mm512_setr_ps(
             0., 1., 4., 9., 16., 25., 36., 49., 64., 81., 100., 121., 144., 169., 196., 225.,
         );
@@ -46577,7 +46577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sqrt_ps() {
+    fn test_mm512_mask_sqrt_ps() {
         let a = _mm512_setr_ps(
             0., 1., 4., 9., 16., 25., 36., 49., 64., 81., 100., 121., 144., 169., 196., 225.,
         );
@@ -46591,7 +46591,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sqrt_ps() {
+    fn test_mm512_maskz_sqrt_ps() {
         let a = _mm512_setr_ps(
             0., 1., 4., 9., 16., 25., 36., 49., 64., 81., 100., 121., 144., 169., 196., 225.,
         );
@@ -46605,7 +46605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sqrt_ps() {
+    fn test_mm256_mask_sqrt_ps() {
         let a = _mm256_set_ps(0., 1., 4., 9., 16., 25., 36., 49.);
         let r = _mm256_mask_sqrt_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -46615,7 +46615,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sqrt_ps() {
+    fn test_mm256_maskz_sqrt_ps() {
         let a = _mm256_set_ps(0., 1., 4., 9., 16., 25., 36., 49.);
         let r = _mm256_maskz_sqrt_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -46625,7 +46625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sqrt_ps() {
+    fn test_mm_mask_sqrt_ps() {
         let a = _mm_set_ps(0., 1., 4., 9.);
         let r = _mm_mask_sqrt_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -46635,7 +46635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sqrt_ps() {
+    fn test_mm_maskz_sqrt_ps() {
         let a = _mm_set_ps(0., 1., 4., 9.);
         let r = _mm_maskz_sqrt_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -46645,7 +46645,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmadd_ps() {
+    const fn test_mm512_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46659,7 +46659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmadd_ps() {
+    const fn test_mm512_mask_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46675,7 +46675,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmadd_ps() {
+    const fn test_mm512_maskz_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46691,7 +46691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmadd_ps() {
+    const fn test_mm512_mask3_fmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46707,7 +46707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmadd_ps() {
+    const fn test_mm256_mask_fmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46719,7 +46719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmadd_ps() {
+    const fn test_mm256_maskz_fmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46731,7 +46731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmadd_ps() {
+    const fn test_mm256_mask3_fmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46743,7 +46743,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmadd_ps() {
+    const fn test_mm_mask_fmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -46755,7 +46755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmadd_ps() {
+    const fn test_mm_maskz_fmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -46767,7 +46767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmadd_ps() {
+    const fn test_mm_mask3_fmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -46779,7 +46779,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmsub_ps() {
+    const fn test_mm512_fmsub_ps() {
         let a = _mm512_setr_ps(
             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
         );
@@ -46797,7 +46797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmsub_ps() {
+    const fn test_mm512_mask_fmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46813,7 +46813,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmsub_ps() {
+    const fn test_mm512_maskz_fmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46829,7 +46829,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmsub_ps() {
+    const fn test_mm512_mask3_fmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46847,7 +46847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmsub_ps() {
+    const fn test_mm256_mask_fmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46859,7 +46859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmsub_ps() {
+    const fn test_mm256_maskz_fmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46871,7 +46871,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmsub_ps() {
+    const fn test_mm256_mask3_fmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46883,7 +46883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmsub_ps() {
+    const fn test_mm_mask_fmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -46895,7 +46895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsub_ps() {
+    const fn test_mm_maskz_fmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -46907,7 +46907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsub_ps() {
+    const fn test_mm_mask3_fmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -46919,7 +46919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmaddsub_ps() {
+    const fn test_mm512_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46933,7 +46933,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmaddsub_ps() {
+    const fn test_mm512_mask_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46949,7 +46949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmaddsub_ps() {
+    const fn test_mm512_maskz_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46965,7 +46965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmaddsub_ps() {
+    const fn test_mm512_mask3_fmaddsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -46983,7 +46983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmaddsub_ps() {
+    const fn test_mm256_mask_fmaddsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -46995,7 +46995,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmaddsub_ps() {
+    const fn test_mm256_maskz_fmaddsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47007,7 +47007,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmaddsub_ps() {
+    const fn test_mm256_mask3_fmaddsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47019,7 +47019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmaddsub_ps() {
+    const fn test_mm_mask_fmaddsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47031,7 +47031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmaddsub_ps() {
+    const fn test_mm_maskz_fmaddsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47043,7 +47043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmaddsub_ps() {
+    const fn test_mm_mask3_fmaddsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47055,7 +47055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmsubadd_ps() {
+    const fn test_mm512_fmsubadd_ps() {
         let a = _mm512_setr_ps(
             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
         );
@@ -47073,7 +47073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmsubadd_ps() {
+    const fn test_mm512_mask_fmsubadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47089,7 +47089,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmsubadd_ps() {
+    const fn test_mm512_maskz_fmsubadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47105,7 +47105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmsubadd_ps() {
+    const fn test_mm512_mask3_fmsubadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47123,7 +47123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmsubadd_ps() {
+    const fn test_mm256_mask_fmsubadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47135,7 +47135,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmsubadd_ps() {
+    const fn test_mm256_maskz_fmsubadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47147,7 +47147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmsubadd_ps() {
+    const fn test_mm256_mask3_fmsubadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47159,7 +47159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmsubadd_ps() {
+    const fn test_mm_mask_fmsubadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47171,7 +47171,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsubadd_ps() {
+    const fn test_mm_maskz_fmsubadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47183,7 +47183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsubadd_ps() {
+    const fn test_mm_mask3_fmsubadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47195,7 +47195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fnmadd_ps() {
+    const fn test_mm512_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47209,7 +47209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fnmadd_ps() {
+    const fn test_mm512_mask_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47225,7 +47225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fnmadd_ps() {
+    const fn test_mm512_maskz_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47241,7 +47241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fnmadd_ps() {
+    const fn test_mm512_mask3_fnmadd_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47259,7 +47259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fnmadd_ps() {
+    const fn test_mm256_mask_fnmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47271,7 +47271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fnmadd_ps() {
+    const fn test_mm256_maskz_fnmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47283,7 +47283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fnmadd_ps() {
+    const fn test_mm256_mask3_fnmadd_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47295,7 +47295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fnmadd_ps() {
+    const fn test_mm_mask_fnmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47307,7 +47307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmadd_ps() {
+    const fn test_mm_maskz_fnmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47319,7 +47319,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmadd_ps() {
+    const fn test_mm_mask3_fnmadd_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47331,7 +47331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fnmsub_ps() {
+    const fn test_mm512_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47345,7 +47345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fnmsub_ps() {
+    const fn test_mm512_mask_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47361,7 +47361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fnmsub_ps() {
+    const fn test_mm512_maskz_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47377,7 +47377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fnmsub_ps() {
+    const fn test_mm512_mask3_fnmsub_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -47395,7 +47395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fnmsub_ps() {
+    const fn test_mm256_mask_fnmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47407,7 +47407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fnmsub_ps() {
+    const fn test_mm256_maskz_fnmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47419,7 +47419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fnmsub_ps() {
+    const fn test_mm256_mask3_fnmsub_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm256_set1_ps(1.);
@@ -47431,7 +47431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fnmsub_ps() {
+    const fn test_mm_mask_fnmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47443,7 +47443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmsub_ps() {
+    const fn test_mm_maskz_fnmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47455,7 +47455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmsub_ps() {
+    const fn test_mm_mask3_fnmsub_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set_ps(0., 1., 2., 3.);
         let c = _mm_set1_ps(1.);
@@ -47467,7 +47467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rcp14_ps() {
+    fn test_mm512_rcp14_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_rcp14_ps(a);
         let e = _mm512_set1_ps(0.33333206);
@@ -47475,7 +47475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rcp14_ps() {
+    fn test_mm512_mask_rcp14_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_mask_rcp14_ps(a, 0, a);
         assert_eq_m512(r, a);
@@ -47488,7 +47488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rcp14_ps() {
+    fn test_mm512_maskz_rcp14_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_maskz_rcp14_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -47501,7 +47501,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rcp14_ps() {
+    fn test_mm256_rcp14_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_rcp14_ps(a);
         let e = _mm256_set1_ps(0.33333206);
@@ -47509,7 +47509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rcp14_ps() {
+    fn test_mm256_mask_rcp14_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_mask_rcp14_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -47519,7 +47519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rcp14_ps() {
+    fn test_mm256_maskz_rcp14_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_maskz_rcp14_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -47529,7 +47529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rcp14_ps() {
+    fn test_mm_rcp14_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_rcp14_ps(a);
         let e = _mm_set1_ps(0.33333206);
@@ -47537,7 +47537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rcp14_ps() {
+    fn test_mm_mask_rcp14_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_mask_rcp14_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -47547,7 +47547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rcp14_ps() {
+    fn test_mm_maskz_rcp14_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_maskz_rcp14_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -47557,7 +47557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rsqrt14_ps() {
+    fn test_mm512_rsqrt14_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_rsqrt14_ps(a);
         let e = _mm512_set1_ps(0.5773392);
@@ -47565,7 +47565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rsqrt14_ps() {
+    fn test_mm512_mask_rsqrt14_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_mask_rsqrt14_ps(a, 0, a);
         assert_eq_m512(r, a);
@@ -47578,7 +47578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rsqrt14_ps() {
+    fn test_mm512_maskz_rsqrt14_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_maskz_rsqrt14_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -47591,7 +47591,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rsqrt14_ps() {
+    fn test_mm256_rsqrt14_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_rsqrt14_ps(a);
         let e = _mm256_set1_ps(0.5773392);
@@ -47599,7 +47599,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rsqrt14_ps() {
+    fn test_mm256_mask_rsqrt14_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_mask_rsqrt14_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -47609,7 +47609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rsqrt14_ps() {
+    fn test_mm256_maskz_rsqrt14_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_maskz_rsqrt14_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -47619,7 +47619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rsqrt14_ps() {
+    fn test_mm_rsqrt14_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_rsqrt14_ps(a);
         let e = _mm_set1_ps(0.5773392);
@@ -47627,7 +47627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rsqrt14_ps() {
+    fn test_mm_mask_rsqrt14_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_mask_rsqrt14_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -47637,7 +47637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rsqrt14_ps() {
+    fn test_mm_maskz_rsqrt14_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_maskz_rsqrt14_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -47647,7 +47647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getexp_ps() {
+    fn test_mm512_getexp_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_getexp_ps(a);
         let e = _mm512_set1_ps(1.);
@@ -47655,7 +47655,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getexp_ps() {
+    fn test_mm512_mask_getexp_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_mask_getexp_ps(a, 0, a);
         assert_eq_m512(r, a);
@@ -47667,7 +47667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getexp_ps() {
+    fn test_mm512_maskz_getexp_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_maskz_getexp_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -47679,7 +47679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_getexp_ps() {
+    fn test_mm256_getexp_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_getexp_ps(a);
         let e = _mm256_set1_ps(1.);
@@ -47687,7 +47687,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_getexp_ps() {
+    fn test_mm256_mask_getexp_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_mask_getexp_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -47697,7 +47697,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_getexp_ps() {
+    fn test_mm256_maskz_getexp_ps() {
         let a = _mm256_set1_ps(3.);
         let r = _mm256_maskz_getexp_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -47707,7 +47707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_getexp_ps() {
+    fn test_mm_getexp_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_getexp_ps(a);
         let e = _mm_set1_ps(1.);
@@ -47715,7 +47715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_getexp_ps() {
+    fn test_mm_mask_getexp_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_mask_getexp_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -47725,7 +47725,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_getexp_ps() {
+    fn test_mm_maskz_getexp_ps() {
         let a = _mm_set1_ps(3.);
         let r = _mm_maskz_getexp_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -47735,7 +47735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_roundscale_ps() {
+    fn test_mm512_roundscale_ps() {
         let a = _mm512_set1_ps(1.1);
         let r = _mm512_roundscale_ps::<0b00_00_00_00>(a);
         let e = _mm512_set1_ps(1.0);
@@ -47743,7 +47743,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_roundscale_ps() {
+    fn test_mm512_mask_roundscale_ps() {
         let a = _mm512_set1_ps(1.1);
         let r = _mm512_mask_roundscale_ps::<0b00_00_00_00>(a, 0, a);
         let e = _mm512_set1_ps(1.1);
@@ -47754,7 +47754,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_roundscale_ps() {
+    fn test_mm512_maskz_roundscale_ps() {
         let a = _mm512_set1_ps(1.1);
         let r = _mm512_maskz_roundscale_ps::<0b00_00_00_00>(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -47764,7 +47764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_roundscale_ps() {
+    fn test_mm256_roundscale_ps() {
         let a = _mm256_set1_ps(1.1);
         let r = _mm256_roundscale_ps::<0b00_00_00_00>(a);
         let e = _mm256_set1_ps(1.0);
@@ -47772,7 +47772,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_roundscale_ps() {
+    fn test_mm256_mask_roundscale_ps() {
         let a = _mm256_set1_ps(1.1);
         let r = _mm256_mask_roundscale_ps::<0b00_00_00_00>(a, 0, a);
         let e = _mm256_set1_ps(1.1);
@@ -47783,7 +47783,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_roundscale_ps() {
+    fn test_mm256_maskz_roundscale_ps() {
         let a = _mm256_set1_ps(1.1);
         let r = _mm256_maskz_roundscale_ps::<0b00_00_00_00>(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -47793,7 +47793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_roundscale_ps() {
+    fn test_mm_roundscale_ps() {
         let a = _mm_set1_ps(1.1);
         let r = _mm_roundscale_ps::<0b00_00_00_00>(a);
         let e = _mm_set1_ps(1.0);
@@ -47801,7 +47801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_roundscale_ps() {
+    fn test_mm_mask_roundscale_ps() {
         let a = _mm_set1_ps(1.1);
         let r = _mm_mask_roundscale_ps::<0b00_00_00_00>(a, 0, a);
         let e = _mm_set1_ps(1.1);
@@ -47812,7 +47812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_roundscale_ps() {
+    fn test_mm_maskz_roundscale_ps() {
         let a = _mm_set1_ps(1.1);
         let r = _mm_maskz_roundscale_ps::<0b00_00_00_00>(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -47822,7 +47822,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_scalef_ps() {
+    fn test_mm512_scalef_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_scalef_ps(a, b);
@@ -47831,7 +47831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_scalef_ps() {
+    fn test_mm512_mask_scalef_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_mask_scalef_ps(a, 0, a, b);
@@ -47844,7 +47844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_scalef_ps() {
+    fn test_mm512_maskz_scalef_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_maskz_scalef_ps(0, a, b);
@@ -47857,7 +47857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_scalef_ps() {
+    fn test_mm256_scalef_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(3.);
         let r = _mm256_scalef_ps(a, b);
@@ -47866,7 +47866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_scalef_ps() {
+    fn test_mm256_mask_scalef_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(3.);
         let r = _mm256_mask_scalef_ps(a, 0, a, b);
@@ -47877,7 +47877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_scalef_ps() {
+    fn test_mm256_maskz_scalef_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(3.);
         let r = _mm256_maskz_scalef_ps(0, a, b);
@@ -47888,7 +47888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_scalef_ps() {
+    fn test_mm_scalef_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_scalef_ps(a, b);
@@ -47897,7 +47897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_scalef_ps() {
+    fn test_mm_mask_scalef_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_mask_scalef_ps(a, 0, a, b);
@@ -47908,7 +47908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_scalef_ps() {
+    fn test_mm_maskz_scalef_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_maskz_scalef_ps(0, a, b);
@@ -47919,7 +47919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fixupimm_ps() {
+    fn test_mm512_fixupimm_ps() {
         let a = _mm512_set1_ps(f32::NAN);
         let b = _mm512_set1_ps(f32::MAX);
         let c = _mm512_set1_epi32(i32::MAX);
@@ -47930,7 +47930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fixupimm_ps() {
+    fn test_mm512_mask_fixupimm_ps() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(
             f32::NAN, f32::NAN, f32::NAN, f32::NAN,
@@ -47948,7 +47948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fixupimm_ps() {
+    fn test_mm512_maskz_fixupimm_ps() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(
             f32::NAN, f32::NAN, f32::NAN, f32::NAN,
@@ -47966,7 +47966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_fixupimm_ps() {
+    fn test_mm256_fixupimm_ps() {
         let a = _mm256_set1_ps(f32::NAN);
         let b = _mm256_set1_ps(f32::MAX);
         let c = _mm256_set1_epi32(i32::MAX);
@@ -47976,7 +47976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fixupimm_ps() {
+    fn test_mm256_mask_fixupimm_ps() {
         let a = _mm256_set1_ps(f32::NAN);
         let b = _mm256_set1_ps(f32::MAX);
         let c = _mm256_set1_epi32(i32::MAX);
@@ -47986,7 +47986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fixupimm_ps() {
+    fn test_mm256_maskz_fixupimm_ps() {
         let a = _mm256_set1_ps(f32::NAN);
         let b = _mm256_set1_ps(f32::MAX);
         let c = _mm256_set1_epi32(i32::MAX);
@@ -47996,7 +47996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_fixupimm_ps() {
+    fn test_mm_fixupimm_ps() {
         let a = _mm_set1_ps(f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -48006,7 +48006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fixupimm_ps() {
+    fn test_mm_mask_fixupimm_ps() {
         let a = _mm_set1_ps(f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -48016,7 +48016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fixupimm_ps() {
+    fn test_mm_maskz_fixupimm_ps() {
         let a = _mm_set1_ps(f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -48050,7 +48050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_ternarylogic_epi32() {
+    fn test_mm512_mask_ternarylogic_epi32() {
         let src = _mm512_set1_epi32(1 << 2);
         let a = _mm512_set1_epi32(1 << 1);
         let b = _mm512_set1_epi32(1 << 0);
@@ -48062,7 +48062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_ternarylogic_epi32() {
+    fn test_mm512_maskz_ternarylogic_epi32() {
         let a = _mm512_set1_epi32(1 << 2);
         let b = _mm512_set1_epi32(1 << 1);
         let c = _mm512_set1_epi32(1 << 0);
@@ -48100,7 +48100,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_ternarylogic_epi32() {
+    fn test_mm256_mask_ternarylogic_epi32() {
         let src = _mm256_set1_epi32(1 << 2);
         let a = _mm256_set1_epi32(1 << 1);
         let b = _mm256_set1_epi32(1 << 0);
@@ -48112,7 +48112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_ternarylogic_epi32() {
+    fn test_mm256_maskz_ternarylogic_epi32() {
         let a = _mm256_set1_epi32(1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let c = _mm256_set1_epi32(1 << 0);
@@ -48148,7 +48148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_ternarylogic_epi32() {
+    fn test_mm_mask_ternarylogic_epi32() {
         let src = _mm_set1_epi32(1 << 2);
         let a = _mm_set1_epi32(1 << 1);
         let b = _mm_set1_epi32(1 << 0);
@@ -48160,7 +48160,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_ternarylogic_epi32() {
+    fn test_mm_maskz_ternarylogic_epi32() {
         let a = _mm_set1_epi32(1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let c = _mm_set1_epi32(1 << 0);
@@ -48172,7 +48172,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getmant_ps() {
+    fn test_mm512_getmant_ps() {
         let a = _mm512_set1_ps(10.);
         let r = _mm512_getmant_ps::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
         let e = _mm512_set1_ps(1.25);
@@ -48180,7 +48180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getmant_ps() {
+    fn test_mm512_mask_getmant_ps() {
         let a = _mm512_set1_ps(10.);
         let r = _mm512_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
         assert_eq_m512(r, a);
@@ -48196,7 +48196,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getmant_ps() {
+    fn test_mm512_maskz_getmant_ps() {
         let a = _mm512_set1_ps(10.);
         let r = _mm512_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -48209,7 +48209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_getmant_ps() {
+    fn test_mm256_getmant_ps() {
         let a = _mm256_set1_ps(10.);
         let r = _mm256_getmant_ps::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
         let e = _mm256_set1_ps(1.25);
@@ -48217,7 +48217,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_getmant_ps() {
+    fn test_mm256_mask_getmant_ps() {
         let a = _mm256_set1_ps(10.);
         let r = _mm256_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
         assert_eq_m256(r, a);
@@ -48227,7 +48227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_getmant_ps() {
+    fn test_mm256_maskz_getmant_ps() {
         let a = _mm256_set1_ps(10.);
         let r = _mm256_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -48237,7 +48237,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_getmant_ps() {
+    fn test_mm_getmant_ps() {
         let a = _mm_set1_ps(10.);
         let r = _mm_getmant_ps::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
         let e = _mm_set1_ps(1.25);
@@ -48245,7 +48245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_getmant_ps() {
+    fn test_mm_mask_getmant_ps() {
         let a = _mm_set1_ps(10.);
         let r = _mm_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
         assert_eq_m128(r, a);
@@ -48255,7 +48255,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_getmant_ps() {
+    fn test_mm_maskz_getmant_ps() {
         let a = _mm_set1_ps(10.);
         let r = _mm_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -48265,7 +48265,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_add_round_ps() {
+    fn test_mm512_add_round_ps() {
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
         );
@@ -48287,7 +48287,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_add_round_ps() {
+    fn test_mm512_mask_add_round_ps() {
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
         );
@@ -48311,7 +48311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_add_round_ps() {
+    fn test_mm512_maskz_add_round_ps() {
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
         );
@@ -48334,7 +48334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sub_round_ps() {
+    fn test_mm512_sub_round_ps() {
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
         );
@@ -48356,7 +48356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sub_round_ps() {
+    fn test_mm512_mask_sub_round_ps() {
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
         );
@@ -48382,7 +48382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sub_round_ps() {
+    fn test_mm512_maskz_sub_round_ps() {
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
         );
@@ -48406,7 +48406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mul_round_ps() {
+    fn test_mm512_mul_round_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5,
@@ -48436,7 +48436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mul_round_ps() {
+    fn test_mm512_mask_mul_round_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5,
@@ -48466,7 +48466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mul_round_ps() {
+    fn test_mm512_maskz_mul_round_ps() {
         #[rustfmt::skip]
         let a = _mm512_setr_ps(
             0., 1.5, 2., 3.5,
@@ -48494,7 +48494,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_div_round_ps() {
+    fn test_mm512_div_round_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_div_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -48506,7 +48506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_div_round_ps() {
+    fn test_mm512_mask_div_round_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_mask_div_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -48527,7 +48527,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_div_round_ps() {
+    fn test_mm512_maskz_div_round_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r =
@@ -48546,7 +48546,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sqrt_round_ps() {
+    fn test_mm512_sqrt_round_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_sqrt_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set1_ps(1.7320508);
@@ -48557,7 +48557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sqrt_round_ps() {
+    fn test_mm512_mask_sqrt_round_ps() {
         let a = _mm512_set1_ps(3.);
         let r =
             _mm512_mask_sqrt_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
@@ -48575,7 +48575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sqrt_round_ps() {
+    fn test_mm512_maskz_sqrt_round_ps() {
         let a = _mm512_set1_ps(3.);
         let r =
             _mm512_maskz_sqrt_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
@@ -48592,7 +48592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmadd_round_ps() {
+    fn test_mm512_fmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48605,7 +48605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmadd_round_ps() {
+    fn test_mm512_mask_fmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48630,7 +48630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmadd_round_ps() {
+    fn test_mm512_maskz_fmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48656,7 +48656,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmadd_round_ps() {
+    fn test_mm512_mask3_fmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48681,7 +48681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsub_round_ps() {
+    fn test_mm512_fmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -48694,7 +48694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsub_round_ps() {
+    fn test_mm512_mask_fmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -48719,7 +48719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsub_round_ps() {
+    fn test_mm512_maskz_fmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -48744,7 +48744,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsub_round_ps() {
+    fn test_mm512_mask3_fmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -48769,7 +48769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmaddsub_round_ps() {
+    fn test_mm512_fmaddsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48792,7 +48792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmaddsub_round_ps() {
+    fn test_mm512_mask_fmaddsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48817,7 +48817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmaddsub_round_ps() {
+    fn test_mm512_maskz_fmaddsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48842,7 +48842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmaddsub_round_ps() {
+    fn test_mm512_mask3_fmaddsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48867,7 +48867,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsubadd_round_ps() {
+    fn test_mm512_fmsubadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48890,7 +48890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsubadd_round_ps() {
+    fn test_mm512_mask_fmsubadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48915,7 +48915,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsubadd_round_ps() {
+    fn test_mm512_maskz_fmsubadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48940,7 +48940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsubadd_round_ps() {
+    fn test_mm512_mask3_fmsubadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -48965,7 +48965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmadd_round_ps() {
+    fn test_mm512_fnmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -48979,7 +48979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmadd_round_ps() {
+    fn test_mm512_mask_fnmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -49002,7 +49002,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmadd_round_ps() {
+    fn test_mm512_maskz_fnmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -49024,7 +49024,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmadd_round_ps() {
+    fn test_mm512_mask3_fnmadd_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(1.);
@@ -49046,7 +49046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmsub_round_ps() {
+    fn test_mm512_fnmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -49060,7 +49060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmsub_round_ps() {
+    fn test_mm512_mask_fnmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -49083,7 +49083,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmsub_round_ps() {
+    fn test_mm512_maskz_fnmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -49105,7 +49105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmsub_round_ps() {
+    fn test_mm512_mask3_fnmsub_round_ps() {
         let a = _mm512_set1_ps(0.00000007);
         let b = _mm512_set1_ps(1.);
         let c = _mm512_set1_ps(-1.);
@@ -49127,7 +49127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_round_ps() {
+    fn test_mm512_max_round_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -49142,7 +49142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_round_ps() {
+    fn test_mm512_mask_max_round_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -49159,7 +49159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_round_ps() {
+    fn test_mm512_maskz_max_round_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -49176,7 +49176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_round_ps() {
+    fn test_mm512_min_round_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -49191,7 +49191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_round_ps() {
+    fn test_mm512_mask_min_round_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -49208,7 +49208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_round_ps() {
+    fn test_mm512_maskz_min_round_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -49225,7 +49225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getexp_round_ps() {
+    fn test_mm512_getexp_round_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_getexp_round_ps::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm512_set1_ps(1.);
@@ -49233,7 +49233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getexp_round_ps() {
+    fn test_mm512_mask_getexp_round_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_mask_getexp_round_ps::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
         assert_eq_m512(r, a);
@@ -49245,7 +49245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getexp_round_ps() {
+    fn test_mm512_maskz_getexp_round_ps() {
         let a = _mm512_set1_ps(3.);
         let r = _mm512_maskz_getexp_round_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -49257,7 +49257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_roundscale_round_ps() {
+    fn test_mm512_roundscale_round_ps() {
         let a = _mm512_set1_ps(1.1);
         let r = _mm512_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm512_set1_ps(1.0);
@@ -49265,7 +49265,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_roundscale_round_ps() {
+    fn test_mm512_mask_roundscale_round_ps() {
         let a = _mm512_set1_ps(1.1);
         let r = _mm512_mask_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
         let e = _mm512_set1_ps(1.1);
@@ -49280,7 +49280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_roundscale_round_ps() {
+    fn test_mm512_maskz_roundscale_round_ps() {
         let a = _mm512_set1_ps(1.1);
         let r = _mm512_maskz_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -49291,7 +49291,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_scalef_round_ps() {
+    fn test_mm512_scalef_round_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_scalef_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -49300,7 +49300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_scalef_round_ps() {
+    fn test_mm512_mask_scalef_round_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_mask_scalef_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -49320,7 +49320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_scalef_round_ps() {
+    fn test_mm512_maskz_scalef_round_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(3.);
         let r = _mm512_maskz_scalef_round_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -49339,7 +49339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fixupimm_round_ps() {
+    fn test_mm512_fixupimm_round_ps() {
         let a = _mm512_set1_ps(f32::NAN);
         let b = _mm512_set1_ps(f32::MAX);
         let c = _mm512_set1_epi32(i32::MAX);
@@ -49349,7 +49349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fixupimm_round_ps() {
+    fn test_mm512_mask_fixupimm_round_ps() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(
             f32::NAN, f32::NAN, f32::NAN, f32::NAN,
@@ -49372,7 +49372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fixupimm_round_ps() {
+    fn test_mm512_maskz_fixupimm_round_ps() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(
             f32::NAN, f32::NAN, f32::NAN, f32::NAN,
@@ -49395,7 +49395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getmant_round_ps() {
+    fn test_mm512_getmant_round_ps() {
         let a = _mm512_set1_ps(10.);
         let r = _mm512_getmant_round_ps::<
             _MM_MANT_NORM_1_2,
@@ -49407,7 +49407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getmant_round_ps() {
+    fn test_mm512_mask_getmant_round_ps() {
         let a = _mm512_set1_ps(10.);
         let r = _mm512_mask_getmant_round_ps::<
             _MM_MANT_NORM_1_2,
@@ -49427,7 +49427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getmant_round_ps() {
+    fn test_mm512_maskz_getmant_round_ps() {
         let a = _mm512_set1_ps(10.);
         let r = _mm512_maskz_getmant_round_ps::<
             _MM_MANT_NORM_1_2,
@@ -49447,7 +49447,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtps_epi32() {
+    fn test_mm512_cvtps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -49457,7 +49457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtps_epi32() {
+    fn test_mm512_mask_cvtps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -49470,7 +49470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtps_epi32() {
+    fn test_mm512_maskz_cvtps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -49482,7 +49482,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtps_epi32() {
+    fn test_mm256_mask_cvtps_epi32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm256_mask_cvtps_epi32(src, 0, a);
@@ -49493,7 +49493,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtps_epi32() {
+    fn test_mm256_maskz_cvtps_epi32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let r = _mm256_maskz_cvtps_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -49503,7 +49503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtps_epi32() {
+    fn test_mm_mask_cvtps_epi32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtps_epi32(src, 0, a);
@@ -49514,7 +49514,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtps_epi32() {
+    fn test_mm_maskz_cvtps_epi32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let r = _mm_maskz_cvtps_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49524,7 +49524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtps_epu32() {
+    fn test_mm512_cvtps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -49534,7 +49534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtps_epu32() {
+    fn test_mm512_mask_cvtps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -49547,7 +49547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtps_epu32() {
+    fn test_mm512_maskz_cvtps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -49559,7 +49559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtps_epu32() {
+    fn test_mm256_cvtps_epu32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let r = _mm256_cvtps_epu32(a);
         let e = _mm256_set_epi32(8, 10, 10, 12, 12, 14, 14, 16);
@@ -49567,7 +49567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtps_epu32() {
+    fn test_mm256_mask_cvtps_epu32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm256_mask_cvtps_epu32(src, 0, a);
@@ -49578,7 +49578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtps_epu32() {
+    fn test_mm256_maskz_cvtps_epu32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let r = _mm256_maskz_cvtps_epu32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -49588,7 +49588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtps_epu32() {
+    fn test_mm_cvtps_epu32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let r = _mm_cvtps_epu32(a);
         let e = _mm_set_epi32(12, 14, 14, 16);
@@ -49596,7 +49596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtps_epu32() {
+    fn test_mm_mask_cvtps_epu32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtps_epu32(src, 0, a);
@@ -49607,7 +49607,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtps_epu32() {
+    fn test_mm_maskz_cvtps_epu32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let r = _mm_maskz_cvtps_epu32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49617,7 +49617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi8_epi32() {
+    const fn test_mm512_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi8_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -49625,7 +49625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi8_epi32() {
+    const fn test_mm512_mask_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepi8_epi32(src, 0, a);
@@ -49636,7 +49636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi8_epi32() {
+    const fn test_mm512_maskz_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi8_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -49646,7 +49646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi8_epi32() {
+    const fn test_mm256_mask_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepi8_epi32(src, 0, a);
@@ -49657,7 +49657,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi8_epi32() {
+    const fn test_mm256_maskz_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi8_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -49667,7 +49667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi8_epi32() {
+    const fn test_mm_mask_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepi8_epi32(src, 0, a);
@@ -49678,7 +49678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi8_epi32() {
+    const fn test_mm_maskz_cvtepi8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepi8_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49688,7 +49688,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu8_epi32() {
+    const fn test_mm512_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu8_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -49696,7 +49696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu8_epi32() {
+    const fn test_mm512_mask_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepu8_epi32(src, 0, a);
@@ -49707,7 +49707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu8_epi32() {
+    const fn test_mm512_maskz_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu8_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -49717,7 +49717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu8_epi32() {
+    const fn test_mm256_mask_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepu8_epi32(src, 0, a);
@@ -49728,7 +49728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu8_epi32() {
+    const fn test_mm256_maskz_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu8_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -49738,7 +49738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu8_epi32() {
+    const fn test_mm_mask_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepu8_epi32(src, 0, a);
@@ -49749,7 +49749,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu8_epi32() {
+    const fn test_mm_maskz_cvtepu8_epi32() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu8_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49759,7 +49759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi16_epi32() {
+    const fn test_mm512_cvtepi16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi16_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -49767,7 +49767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi16_epi32() {
+    const fn test_mm512_mask_cvtepi16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepi16_epi32(src, 0, a);
@@ -49778,7 +49778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi16_epi32() {
+    const fn test_mm512_maskz_cvtepi16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi16_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -49788,7 +49788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi16_epi32() {
+    const fn test_mm256_mask_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepi16_epi32(src, 0, a);
@@ -49799,7 +49799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi16_epi32() {
+    const fn test_mm256_maskz_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_cvtepi16_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -49809,7 +49809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi16_epi32() {
+    const fn test_mm_mask_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepi16_epi32(src, 0, a);
@@ -49820,7 +49820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi16_epi32() {
+    const fn test_mm_maskz_cvtepi16_epi32() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_cvtepi16_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49830,7 +49830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu16_epi32() {
+    const fn test_mm512_cvtepu16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu16_epi32(a);
         let e = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -49838,7 +49838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu16_epi32() {
+    const fn test_mm512_mask_cvtepu16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi32(-1);
         let r = _mm512_mask_cvtepu16_epi32(src, 0, a);
@@ -49849,7 +49849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu16_epi32() {
+    const fn test_mm512_maskz_cvtepu16_epi32() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu16_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -49859,7 +49859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu16_epi32() {
+    const fn test_mm256_mask_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm256_mask_cvtepu16_epi32(src, 0, a);
@@ -49870,7 +49870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu16_epi32() {
+    const fn test_mm256_maskz_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu16_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -49880,7 +49880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu16_epi32() {
+    const fn test_mm_mask_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi32(-1);
         let r = _mm_mask_cvtepu16_epi32(src, 0, a);
@@ -49891,7 +49891,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu16_epi32() {
+    const fn test_mm_maskz_cvtepu16_epi32() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu16_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -49901,7 +49901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi32_ps() {
+    const fn test_mm512_cvtepi32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_ps(a);
         let e = _mm512_set_ps(
@@ -49911,7 +49911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi32_ps() {
+    const fn test_mm512_mask_cvtepi32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_ps(-1.);
         let r = _mm512_mask_cvtepi32_ps(src, 0, a);
@@ -49924,7 +49924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi32_ps() {
+    const fn test_mm512_maskz_cvtepi32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -49936,7 +49936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi32_ps() {
+    const fn test_mm256_mask_cvtepi32_ps() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm256_set1_ps(-1.);
         let r = _mm256_mask_cvtepi32_ps(src, 0, a);
@@ -49947,7 +49947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi32_ps() {
+    const fn test_mm256_maskz_cvtepi32_ps() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_cvtepi32_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -49957,7 +49957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi32_ps() {
+    const fn test_mm_mask_cvtepi32_ps() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let src = _mm_set1_ps(-1.);
         let r = _mm_mask_cvtepi32_ps(src, 0, a);
@@ -49968,7 +49968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi32_ps() {
+    const fn test_mm_maskz_cvtepi32_ps() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_cvtepi32_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -49978,7 +49978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu32_ps() {
+    const fn test_mm512_cvtepu32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32_ps(a);
         let e = _mm512_set_ps(
@@ -49988,7 +49988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu32_ps() {
+    const fn test_mm512_mask_cvtepu32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_ps(-1.);
         let r = _mm512_mask_cvtepu32_ps(src, 0, a);
@@ -50001,7 +50001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu32_ps() {
+    const fn test_mm512_maskz_cvtepu32_ps() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu32_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -50013,7 +50013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi32_epi16() {
+    const fn test_mm512_cvtepi32_epi16() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_epi16(a);
         let e = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -50021,7 +50021,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi32_epi16() {
+    const fn test_mm512_mask_cvtepi32_epi16() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi16(-1);
         let r = _mm512_mask_cvtepi32_epi16(src, 0, a);
@@ -50032,7 +50032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi32_epi16() {
+    const fn test_mm512_maskz_cvtepi32_epi16() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_epi16(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -50042,7 +50042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cvtepi32_epi16() {
+    const fn test_mm256_cvtepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_cvtepi32_epi16(a);
         let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
@@ -50050,7 +50050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi32_epi16() {
+    const fn test_mm256_mask_cvtepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm_set1_epi16(-1);
         let r = _mm256_mask_cvtepi32_epi16(src, 0, a);
@@ -50061,7 +50061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi32_epi16() {
+    const fn test_mm256_maskz_cvtepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_cvtepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50071,7 +50071,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtepi32_epi16() {
+    fn test_mm_cvtepi32_epi16() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let r = _mm_cvtepi32_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, 7);
@@ -50079,7 +50079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_epi16() {
+    fn test_mm_mask_cvtepi32_epi16() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtepi32_epi16(src, 0, a);
@@ -50090,7 +50090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi32_epi16() {
+    fn test_mm_maskz_cvtepi32_epi16() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let r = _mm_maskz_cvtepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50100,7 +50100,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi32_epi8() {
+    const fn test_mm512_cvtepi32_epi8() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_epi8(a);
         let e = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -50108,7 +50108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi32_epi8() {
+    const fn test_mm512_mask_cvtepi32_epi8() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi8(-1);
         let r = _mm512_mask_cvtepi32_epi8(src, 0, a);
@@ -50119,7 +50119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi32_epi8() {
+    const fn test_mm512_maskz_cvtepi32_epi8() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50129,7 +50129,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtepi32_epi8() {
+    fn test_mm256_cvtepi32_epi8() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_cvtepi32_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7);
@@ -50137,7 +50137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_epi8() {
+    fn test_mm256_mask_cvtepi32_epi8() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm_set1_epi8(0);
         let r = _mm256_mask_cvtepi32_epi8(src, 0, a);
@@ -50148,7 +50148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi32_epi8() {
+    fn test_mm256_maskz_cvtepi32_epi8() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_cvtepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50158,7 +50158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtepi32_epi8() {
+    fn test_mm_cvtepi32_epi8() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let r = _mm_cvtepi32_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, 7);
@@ -50166,7 +50166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_epi8() {
+    fn test_mm_mask_cvtepi32_epi8() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let src = _mm_set1_epi8(0);
         let r = _mm_mask_cvtepi32_epi8(src, 0, a);
@@ -50177,7 +50177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi32_epi8() {
+    fn test_mm_maskz_cvtepi32_epi8() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let r = _mm_maskz_cvtepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50187,7 +50187,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsepi32_epi16() {
+    fn test_mm512_cvtsepi32_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50207,7 +50207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi32_epi16() {
+    fn test_mm512_mask_cvtsepi32_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50230,7 +50230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtsepi32_epi16() {
+    fn test_mm512_maskz_cvtsepi32_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50252,7 +50252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtsepi32_epi16() {
+    fn test_mm256_cvtsepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_cvtsepi32_epi16(a);
         let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
@@ -50260,7 +50260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi32_epi16() {
+    fn test_mm256_mask_cvtsepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let src = _mm_set1_epi16(-1);
         let r = _mm256_mask_cvtsepi32_epi16(src, 0, a);
@@ -50271,7 +50271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtsepi32_epi16() {
+    fn test_mm256_maskz_cvtsepi32_epi16() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_cvtsepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50281,7 +50281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtsepi32_epi16() {
+    fn test_mm_cvtsepi32_epi16() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let r = _mm_cvtsepi32_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, 7);
@@ -50289,7 +50289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi32_epi16() {
+    fn test_mm_mask_cvtsepi32_epi16() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtsepi32_epi16(src, 0, a);
@@ -50300,7 +50300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsepi32_epi16() {
+    fn test_mm_maskz_cvtsepi32_epi16() {
         let a = _mm_set_epi32(4, 5, 6, 7);
         let r = _mm_maskz_cvtsepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50310,7 +50310,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsepi32_epi8() {
+    fn test_mm512_cvtsepi32_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50330,7 +50330,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi32_epi8() {
+    fn test_mm512_mask_cvtsepi32_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50353,7 +50353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtsepi32_epi8() {
+    fn test_mm512_maskz_cvtsepi32_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50375,7 +50375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtsepi32_epi8() {
+    fn test_mm256_cvtsepi32_epi8() {
         let a = _mm256_set_epi32(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm256_cvtsepi32_epi8(a);
         #[rustfmt::skip]
@@ -50389,7 +50389,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi32_epi8() {
+    fn test_mm256_mask_cvtsepi32_epi8() {
         let a = _mm256_set_epi32(9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm_set1_epi8(0);
         let r = _mm256_mask_cvtsepi32_epi8(src, 0, a);
@@ -50406,7 +50406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtsepi32_epi8() {
+    fn test_mm256_maskz_cvtsepi32_epi8() {
         let a = _mm256_set_epi32(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm256_maskz_cvtsepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50422,7 +50422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtsepi32_epi8() {
+    fn test_mm_cvtsepi32_epi8() {
         let a = _mm_set_epi32(13, 14, 15, 16);
         let r = _mm_cvtsepi32_epi8(a);
         #[rustfmt::skip]
@@ -50436,7 +50436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi32_epi8() {
+    fn test_mm_mask_cvtsepi32_epi8() {
         let a = _mm_set_epi32(13, 14, 15, 16);
         let src = _mm_set1_epi8(0);
         let r = _mm_mask_cvtsepi32_epi8(src, 0, a);
@@ -50453,7 +50453,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsepi32_epi8() {
+    fn test_mm_maskz_cvtsepi32_epi8() {
         let a = _mm_set_epi32(13, 14, 15, 16);
         let r = _mm_maskz_cvtsepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50469,7 +50469,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtusepi32_epi16() {
+    fn test_mm512_cvtusepi32_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50483,7 +50483,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi32_epi16() {
+    fn test_mm512_mask_cvtusepi32_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50500,7 +50500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtusepi32_epi16() {
+    fn test_mm512_maskz_cvtusepi32_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50516,7 +50516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtusepi32_epi16() {
+    fn test_mm256_cvtusepi32_epi16() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_cvtusepi32_epi16(a);
         let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
@@ -50524,7 +50524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi32_epi16() {
+    fn test_mm256_mask_cvtusepi32_epi16() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set1_epi16(0);
         let r = _mm256_mask_cvtusepi32_epi16(src, 0, a);
@@ -50535,7 +50535,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtusepi32_epi16() {
+    fn test_mm256_maskz_cvtusepi32_epi16() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_cvtusepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50545,7 +50545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtusepi32_epi16() {
+    fn test_mm_cvtusepi32_epi16() {
         let a = _mm_set_epi32(5, 6, 7, 8);
         let r = _mm_cvtusepi32_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 5, 6, 7, 8);
@@ -50553,7 +50553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi32_epi16() {
+    fn test_mm_mask_cvtusepi32_epi16() {
         let a = _mm_set_epi32(5, 6, 7, 8);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtusepi32_epi16(src, 0, a);
@@ -50564,7 +50564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtusepi32_epi16() {
+    fn test_mm_maskz_cvtusepi32_epi16() {
         let a = _mm_set_epi32(5, 6, 7, 8);
         let r = _mm_maskz_cvtusepi32_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50574,7 +50574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtusepi32_epi8() {
+    fn test_mm512_cvtusepi32_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50588,7 +50588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi32_epi8() {
+    fn test_mm512_mask_cvtusepi32_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50605,7 +50605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtusepi32_epi8() {
+    fn test_mm512_maskz_cvtusepi32_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             0, 1, 2, 3,
@@ -50621,7 +50621,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtusepi32_epi8() {
+    fn test_mm256_cvtusepi32_epi8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, i32::MAX);
         let r = _mm256_cvtusepi32_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, u8::MAX as i8);
@@ -50629,7 +50629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi32_epi8() {
+    fn test_mm256_mask_cvtusepi32_epi8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, i32::MAX);
         let src = _mm_set1_epi8(0);
         let r = _mm256_mask_cvtusepi32_epi8(src, 0, a);
@@ -50640,7 +50640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtusepi32_epi8() {
+    fn test_mm256_maskz_cvtusepi32_epi8() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, i32::MAX);
         let r = _mm256_maskz_cvtusepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50650,7 +50650,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtusepi32_epi8() {
+    fn test_mm_cvtusepi32_epi8() {
         let a = _mm_set_epi32(5, 6, 7, i32::MAX);
         let r = _mm_cvtusepi32_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 6, 7, u8::MAX as i8);
@@ -50658,7 +50658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi32_epi8() {
+    fn test_mm_mask_cvtusepi32_epi8() {
         let a = _mm_set_epi32(5, 6, 7, i32::MAX);
         let src = _mm_set1_epi8(0);
         let r = _mm_mask_cvtusepi32_epi8(src, 0, a);
@@ -50669,7 +50669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtusepi32_epi8() {
+    fn test_mm_maskz_cvtusepi32_epi8() {
         let a = _mm_set_epi32(5, 6, 7, i32::MAX);
         let r = _mm_maskz_cvtusepi32_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50679,7 +50679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundps_epi32() {
+    fn test_mm512_cvt_roundps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -50692,7 +50692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundps_epi32() {
+    fn test_mm512_mask_cvt_roundps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -50711,7 +50711,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundps_epi32() {
+    fn test_mm512_maskz_cvt_roundps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -50728,7 +50728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundps_epu32() {
+    fn test_mm512_cvt_roundps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -50741,7 +50741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundps_epu32() {
+    fn test_mm512_mask_cvt_roundps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -50760,7 +50760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundps_epu32() {
+    fn test_mm512_maskz_cvt_roundps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -50777,7 +50777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundepi32_ps() {
+    fn test_mm512_cvt_roundepi32_ps() {
         let a = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
         let r = _mm512_cvt_roundepi32_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_setr_ps(
@@ -50787,7 +50787,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundepi32_ps() {
+    fn test_mm512_mask_cvt_roundepi32_ps() {
         let a = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
         let src = _mm512_set1_ps(0.);
         let r = _mm512_mask_cvt_roundepi32_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -50806,7 +50806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundepi32_ps() {
+    fn test_mm512_maskz_cvt_roundepi32_ps() {
         let a = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
         let r = _mm512_maskz_cvt_roundepi32_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0, a,
@@ -50823,7 +50823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundepu32_ps() {
+    fn test_mm512_cvt_roundepu32_ps() {
         let a = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
         let r = _mm512_cvt_roundepu32_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         #[rustfmt::skip]
@@ -50837,7 +50837,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundepu32_ps() {
+    fn test_mm512_mask_cvt_roundepu32_ps() {
         let a = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
         let src = _mm512_set1_ps(0.);
         let r = _mm512_mask_cvt_roundepu32_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -50860,7 +50860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundepu32_ps() {
+    fn test_mm512_maskz_cvt_roundepu32_ps() {
         let a = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
         let r = _mm512_maskz_cvt_roundepu32_ps::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0, a,
@@ -50881,7 +50881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundps_ph() {
+    fn test_mm512_cvt_roundps_ph() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(a);
         let e = _mm256_setr_epi64x(
@@ -50894,7 +50894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundps_ph() {
+    fn test_mm512_mask_cvt_roundps_ph() {
         let a = _mm512_set1_ps(1.);
         let src = _mm256_set1_epi16(0);
         let r = _mm512_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -50905,7 +50905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundps_ph() {
+    fn test_mm512_maskz_cvt_roundps_ph() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -50915,7 +50915,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvt_roundps_ph() {
+    fn test_mm256_mask_cvt_roundps_ph() {
         let a = _mm256_set1_ps(1.);
         let src = _mm_set1_epi16(0);
         let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -50926,7 +50926,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvt_roundps_ph() {
+    fn test_mm256_maskz_cvt_roundps_ph() {
         let a = _mm256_set1_ps(1.);
         let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50936,7 +50936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvt_roundps_ph() {
+    fn test_mm_mask_cvt_roundps_ph() {
         let a = _mm_set1_ps(1.);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -50947,7 +50947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvt_roundps_ph() {
+    fn test_mm_maskz_cvt_roundps_ph() {
         let a = _mm_set1_ps(1.);
         let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -50957,7 +50957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtps_ph() {
+    fn test_mm512_cvtps_ph() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_cvtps_ph::<_MM_FROUND_NO_EXC>(a);
         let e = _mm256_setr_epi64x(
@@ -50970,7 +50970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtps_ph() {
+    fn test_mm512_mask_cvtps_ph() {
         let a = _mm512_set1_ps(1.);
         let src = _mm256_set1_epi16(0);
         let r = _mm512_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -50981,7 +50981,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtps_ph() {
+    fn test_mm512_maskz_cvtps_ph() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -50991,7 +50991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtps_ph() {
+    fn test_mm256_mask_cvtps_ph() {
         let a = _mm256_set1_ps(1.);
         let src = _mm_set1_epi16(0);
         let r = _mm256_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -51002,7 +51002,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtps_ph() {
+    fn test_mm256_maskz_cvtps_ph() {
         let a = _mm256_set1_ps(1.);
         let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -51012,7 +51012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtps_ph() {
+    fn test_mm_mask_cvtps_ph() {
         let a = _mm_set1_ps(1.);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -51023,7 +51023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtps_ph() {
+    fn test_mm_maskz_cvtps_ph() {
         let a = _mm_set1_ps(1.);
         let r = _mm_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -51033,7 +51033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundph_ps() {
+    fn test_mm512_cvt_roundph_ps() {
         let a = _mm256_setr_epi64x(
             4323521613979991040,
             4323521613979991040,
@@ -51046,7 +51046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundph_ps() {
+    fn test_mm512_mask_cvt_roundph_ps() {
         let a = _mm256_setr_epi64x(
             4323521613979991040,
             4323521613979991040,
@@ -51064,7 +51064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundph_ps() {
+    fn test_mm512_maskz_cvt_roundph_ps() {
         let a = _mm256_setr_epi64x(
             4323521613979991040,
             4323521613979991040,
@@ -51081,7 +51081,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtph_ps() {
+    fn test_mm512_cvtph_ps() {
         let a = _mm256_setr_epi64x(
             4323521613979991040,
             4323521613979991040,
@@ -51094,7 +51094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtph_ps() {
+    fn test_mm512_mask_cvtph_ps() {
         let a = _mm256_setr_epi64x(
             4323521613979991040,
             4323521613979991040,
@@ -51112,7 +51112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtph_ps() {
+    fn test_mm512_maskz_cvtph_ps() {
         let a = _mm256_setr_epi64x(
             4323521613979991040,
             4323521613979991040,
@@ -51129,7 +51129,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_ps() {
+    fn test_mm256_mask_cvtph_ps() {
         let a = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
         let src = _mm256_set1_ps(0.);
         let r = _mm256_mask_cvtph_ps(src, 0, a);
@@ -51140,7 +51140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_ps() {
+    fn test_mm256_maskz_cvtph_ps() {
         let a = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
         let r = _mm256_maskz_cvtph_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -51150,7 +51150,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_ps() {
+    fn test_mm_mask_cvtph_ps() {
         let a = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
         let src = _mm_set1_ps(0.);
         let r = _mm_mask_cvtph_ps(src, 0, a);
@@ -51161,7 +51161,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_ps() {
+    fn test_mm_maskz_cvtph_ps() {
         let a = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
         let r = _mm_maskz_cvtph_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -51171,7 +51171,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtt_roundps_epi32() {
+    fn test_mm512_cvtt_roundps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51181,7 +51181,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtt_roundps_epi32() {
+    fn test_mm512_mask_cvtt_roundps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51194,7 +51194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtt_roundps_epi32() {
+    fn test_mm512_maskz_cvtt_roundps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51206,7 +51206,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtt_roundps_epu32() {
+    fn test_mm512_cvtt_roundps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51216,7 +51216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtt_roundps_epu32() {
+    fn test_mm512_mask_cvtt_roundps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51229,7 +51229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtt_roundps_epu32() {
+    fn test_mm512_maskz_cvtt_roundps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51241,7 +51241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvttps_epi32() {
+    fn test_mm512_cvttps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51251,7 +51251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvttps_epi32() {
+    fn test_mm512_mask_cvttps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51264,7 +51264,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvttps_epi32() {
+    fn test_mm512_maskz_cvttps_epi32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51276,7 +51276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvttps_epi32() {
+    fn test_mm256_mask_cvttps_epi32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm256_mask_cvttps_epi32(src, 0, a);
@@ -51287,7 +51287,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttps_epi32() {
+    fn test_mm256_maskz_cvttps_epi32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let r = _mm256_maskz_cvttps_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -51297,7 +51297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvttps_epi32() {
+    fn test_mm_mask_cvttps_epi32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvttps_epi32(src, 0, a);
@@ -51308,7 +51308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvttps_epi32() {
+    fn test_mm_maskz_cvttps_epi32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let r = _mm_maskz_cvttps_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -51318,7 +51318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvttps_epu32() {
+    fn test_mm512_cvttps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51328,7 +51328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvttps_epu32() {
+    fn test_mm512_mask_cvttps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51341,7 +51341,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvttps_epu32() {
+    fn test_mm512_maskz_cvttps_epu32() {
         let a = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
         );
@@ -51353,7 +51353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvttps_epu32() {
+    fn test_mm256_cvttps_epu32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let r = _mm256_cvttps_epu32(a);
         let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
@@ -51361,7 +51361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvttps_epu32() {
+    fn test_mm256_mask_cvttps_epu32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm256_mask_cvttps_epu32(src, 0, a);
@@ -51372,7 +51372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttps_epu32() {
+    fn test_mm256_maskz_cvttps_epu32() {
         let a = _mm256_set_ps(8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5);
         let r = _mm256_maskz_cvttps_epu32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -51382,7 +51382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvttps_epu32() {
+    fn test_mm_cvttps_epu32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let r = _mm_cvttps_epu32(a);
         let e = _mm_set_epi32(12, 13, 14, 15);
@@ -51390,7 +51390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvttps_epu32() {
+    fn test_mm_mask_cvttps_epu32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvttps_epu32(src, 0, a);
@@ -51401,7 +51401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvttps_epu32() {
+    fn test_mm_maskz_cvttps_epu32() {
         let a = _mm_set_ps(12., 13.5, 14., 15.5);
         let r = _mm_maskz_cvttps_epu32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -51539,7 +51539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmplt_ps_mask() {
+    fn test_mm512_cmplt_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51549,7 +51549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmplt_ps_mask() {
+    fn test_mm512_mask_cmplt_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51560,7 +51560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpnlt_ps_mask() {
+    fn test_mm512_cmpnlt_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51569,7 +51569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpnlt_ps_mask() {
+    fn test_mm512_mask_cmpnlt_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51579,7 +51579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpnle_ps_mask() {
+    fn test_mm512_cmpnle_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51589,7 +51589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpnle_ps_mask() {
+    fn test_mm512_mask_cmpnle_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51600,7 +51600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmple_ps_mask() {
+    fn test_mm512_cmple_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51609,7 +51609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmple_ps_mask() {
+    fn test_mm512_mask_cmple_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
@@ -51619,7 +51619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpeq_ps_mask() {
+    fn test_mm512_cmpeq_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
@@ -51631,7 +51631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpeq_ps_mask() {
+    fn test_mm512_mask_cmpeq_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
@@ -51644,7 +51644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpneq_ps_mask() {
+    fn test_mm512_cmpneq_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
@@ -51656,7 +51656,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpneq_ps_mask() {
+    fn test_mm512_mask_cmpneq_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
@@ -51669,7 +51669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_ps_mask() {
+    fn test_mm512_cmp_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
@@ -51679,7 +51679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_ps_mask() {
+    fn test_mm512_mask_cmp_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
@@ -51690,7 +51690,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmp_ps_mask() {
+    fn test_mm256_cmp_ps_mask() {
         let a = _mm256_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
         let b = _mm256_set1_ps(-1.);
         let m = _mm256_cmp_ps_mask::<_CMP_LT_OQ>(a, b);
@@ -51698,7 +51698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_ps_mask() {
+    fn test_mm256_mask_cmp_ps_mask() {
         let a = _mm256_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
         let b = _mm256_set1_ps(-1.);
         let mask = 0b01100110;
@@ -51707,7 +51707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmp_ps_mask() {
+    fn test_mm_cmp_ps_mask() {
         let a = _mm_set_ps(0., 1., -1., 13.);
         let b = _mm_set1_ps(1.);
         let m = _mm_cmp_ps_mask::<_CMP_LT_OQ>(a, b);
@@ -51715,7 +51715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmp_ps_mask() {
+    fn test_mm_mask_cmp_ps_mask() {
         let a = _mm_set_ps(0., 1., -1., 13.);
         let b = _mm_set1_ps(1.);
         let mask = 0b11111111;
@@ -51724,7 +51724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_round_ps_mask() {
+    fn test_mm512_cmp_round_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
@@ -51734,7 +51734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_round_ps_mask() {
+    fn test_mm512_mask_cmp_round_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
@@ -51745,7 +51745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpord_ps_mask() {
+    fn test_mm512_cmpord_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
@@ -51757,7 +51757,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpord_ps_mask() {
+    fn test_mm512_mask_cmpord_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
@@ -51770,7 +51770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpunord_ps_mask() {
+    fn test_mm512_cmpunord_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
@@ -51783,7 +51783,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpunord_ps_mask() {
+    fn test_mm512_mask_cmpunord_ps_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
@@ -51796,7 +51796,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cmp_ss_mask() {
+    fn test_mm_cmp_ss_mask() {
         let a = _mm_setr_ps(2., 1., 1., 1.);
         let b = _mm_setr_ps(1., 2., 2., 2.);
         let m = _mm_cmp_ss_mask::<_CMP_GE_OS>(a, b);
@@ -51804,7 +51804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cmp_ss_mask() {
+    fn test_mm_mask_cmp_ss_mask() {
         let a = _mm_setr_ps(2., 1., 1., 1.);
         let b = _mm_setr_ps(1., 2., 2., 2.);
         let m = _mm_mask_cmp_ss_mask::<_CMP_GE_OS>(0b10, a, b);
@@ -51814,7 +51814,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cmp_round_ss_mask() {
+    fn test_mm_cmp_round_ss_mask() {
         let a = _mm_setr_ps(2., 1., 1., 1.);
         let b = _mm_setr_ps(1., 2., 2., 2.);
         let m = _mm_cmp_round_ss_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(a, b);
@@ -51822,7 +51822,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cmp_round_ss_mask() {
+    fn test_mm_mask_cmp_round_ss_mask() {
         let a = _mm_setr_ps(2., 1., 1., 1.);
         let b = _mm_setr_ps(1., 2., 2., 2.);
         let m = _mm_mask_cmp_round_ss_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(0b10, a, b);
@@ -51832,7 +51832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cmp_sd_mask() {
+    fn test_mm_cmp_sd_mask() {
         let a = _mm_setr_pd(2., 1.);
         let b = _mm_setr_pd(1., 2.);
         let m = _mm_cmp_sd_mask::<_CMP_GE_OS>(a, b);
@@ -51840,7 +51840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cmp_sd_mask() {
+    fn test_mm_mask_cmp_sd_mask() {
         let a = _mm_setr_pd(2., 1.);
         let b = _mm_setr_pd(1., 2.);
         let m = _mm_mask_cmp_sd_mask::<_CMP_GE_OS>(0b10, a, b);
@@ -51850,7 +51850,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cmp_round_sd_mask() {
+    fn test_mm_cmp_round_sd_mask() {
         let a = _mm_setr_pd(2., 1.);
         let b = _mm_setr_pd(1., 2.);
         let m = _mm_cmp_round_sd_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(a, b);
@@ -51858,7 +51858,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cmp_round_sd_mask() {
+    fn test_mm_mask_cmp_round_sd_mask() {
         let a = _mm_setr_pd(2., 1.);
         let b = _mm_setr_pd(1., 2.);
         let m = _mm_mask_cmp_round_sd_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(0b10, a, b);
@@ -51868,7 +51868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmplt_epu32_mask() {
+    const fn test_mm512_cmplt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -51878,7 +51878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmplt_epu32_mask() {
+    const fn test_mm512_mask_cmplt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -51889,7 +51889,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epu32_mask() {
+    const fn test_mm256_cmplt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 101, 100, 99);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmplt_epu32_mask(a, b);
@@ -51897,7 +51897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epu32_mask() {
+    const fn test_mm256_mask_cmplt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 101, 100, 99);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -51906,7 +51906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmplt_epu32_mask() {
+    const fn test_mm_cmplt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmplt_epu32_mask(a, b);
@@ -51914,7 +51914,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epu32_mask() {
+    const fn test_mm_mask_cmplt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -51923,7 +51923,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpgt_epu32_mask() {
+    const fn test_mm512_cmpgt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -51933,7 +51933,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpgt_epu32_mask() {
+    const fn test_mm512_mask_cmpgt_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -51944,7 +51944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epu32_mask() {
+    const fn test_mm256_cmpgt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 99, 100, 101);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmpgt_epu32_mask(a, b);
@@ -51952,7 +51952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epu32_mask() {
+    const fn test_mm256_mask_cmpgt_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 99, 100, 101);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -51961,7 +51961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epu32_mask() {
+    const fn test_mm_cmpgt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmpgt_epu32_mask(a, b);
@@ -51969,7 +51969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epu32_mask() {
+    const fn test_mm_mask_cmpgt_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -51978,7 +51978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmple_epu32_mask() {
+    const fn test_mm512_cmple_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -51990,7 +51990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmple_epu32_mask() {
+    const fn test_mm512_mask_cmple_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52003,7 +52003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmple_epu32_mask() {
+    const fn test_mm256_cmple_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 200, 100, 101);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmple_epu32_mask(a, b);
@@ -52011,7 +52011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epu32_mask() {
+    const fn test_mm256_mask_cmple_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 200, 100, 101);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -52020,7 +52020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmple_epu32_mask() {
+    const fn test_mm_cmple_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmple_epu32_mask(a, b);
@@ -52028,7 +52028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epu32_mask() {
+    const fn test_mm_mask_cmple_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -52037,7 +52037,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpge_epu32_mask() {
+    const fn test_mm512_cmpge_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52049,7 +52049,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpge_epu32_mask() {
+    const fn test_mm512_mask_cmpge_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52059,7 +52059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epu32_mask() {
+    const fn test_mm256_cmpge_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 300, 100, 200);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_cmpge_epu32_mask(a, b);
@@ -52067,7 +52067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epu32_mask() {
+    const fn test_mm256_mask_cmpge_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, 2, u32::MAX as i32, i32::MAX, 300, 100, 200);
         let b = _mm256_set1_epi32(1);
         let mask = 0b11111111;
@@ -52076,7 +52076,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpge_epu32_mask() {
+    const fn test_mm_cmpge_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let r = _mm_cmpge_epu32_mask(a, b);
@@ -52084,7 +52084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epu32_mask() {
+    const fn test_mm_mask_cmpge_epu32_mask() {
         let a = _mm_set_epi32(0, 1, 2, u32::MAX as i32);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -52093,7 +52093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpeq_epu32_mask() {
+    const fn test_mm512_cmpeq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52105,7 +52105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpeq_epu32_mask() {
+    const fn test_mm512_mask_cmpeq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52118,7 +52118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epu32_mask() {
+    const fn test_mm256_cmpeq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let m = _mm256_cmpeq_epu32_mask(b, a);
@@ -52126,7 +52126,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epu32_mask() {
+    const fn test_mm256_mask_cmpeq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let mask = 0b01111010;
@@ -52135,7 +52135,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epu32_mask() {
+    const fn test_mm_cmpeq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let m = _mm_cmpeq_epu32_mask(b, a);
@@ -52143,7 +52143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epu32_mask() {
+    const fn test_mm_mask_cmpeq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -52152,7 +52152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpneq_epu32_mask() {
+    const fn test_mm512_cmpneq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52164,7 +52164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpneq_epu32_mask() {
+    const fn test_mm512_mask_cmpneq_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
@@ -52177,7 +52177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epu32_mask() {
+    const fn test_mm256_cmpneq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, -100, 100);
         let r = _mm256_cmpneq_epu32_mask(b, a);
@@ -52185,7 +52185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epu32_mask() {
+    const fn test_mm256_mask_cmpneq_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, -100, 100);
         let mask = 0b11111111;
@@ -52194,7 +52194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epu32_mask() {
+    const fn test_mm_cmpneq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let r = _mm_cmpneq_epu32_mask(b, a);
@@ -52202,7 +52202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epu32_mask() {
+    const fn test_mm_mask_cmpneq_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -52211,7 +52211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmp_epu32_mask() {
+    const fn test_mm512_cmp_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52221,7 +52221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmp_epu32_mask() {
+    const fn test_mm512_mask_cmp_epu32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52232,7 +52232,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmp_epu32_mask() {
+    const fn test_mm256_cmp_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let m = _mm256_cmp_epu32_mask::<_MM_CMPINT_LT>(a, b);
@@ -52240,7 +52240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epu32_mask() {
+    const fn test_mm256_mask_cmp_epu32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52249,7 +52249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmp_epu32_mask() {
+    const fn test_mm_cmp_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, i32::MAX);
         let b = _mm_set1_epi32(1);
         let m = _mm_cmp_epu32_mask::<_MM_CMPINT_LT>(a, b);
@@ -52257,7 +52257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epu32_mask() {
+    const fn test_mm_mask_cmp_epu32_mask() {
         let a = _mm_set_epi32(0, 1, -1, i32::MAX);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -52266,7 +52266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmplt_epi32_mask() {
+    const fn test_mm512_cmplt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52276,7 +52276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmplt_epi32_mask() {
+    const fn test_mm512_mask_cmplt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52287,7 +52287,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epi32_mask() {
+    const fn test_mm256_cmplt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 101, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmplt_epi32_mask(a, b);
@@ -52295,7 +52295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epi32_mask() {
+    const fn test_mm256_mask_cmplt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 101, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52304,7 +52304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmplt_epi32_mask() {
+    const fn test_mm_cmplt_epi32_mask() {
         let a = _mm_set_epi32(i32::MAX, i32::MIN, 100, -100);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmplt_epi32_mask(a, b);
@@ -52312,7 +52312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epi32_mask() {
+    const fn test_mm_mask_cmplt_epi32_mask() {
         let a = _mm_set_epi32(i32::MAX, i32::MIN, 100, -100);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52321,7 +52321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpgt_epi32_mask() {
+    const fn test_mm512_cmpgt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52331,7 +52331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpgt_epi32_mask() {
+    const fn test_mm512_mask_cmpgt_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52342,7 +52342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epi32_mask() {
+    const fn test_mm256_cmpgt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmpgt_epi32_mask(a, b);
@@ -52350,7 +52350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epi32_mask() {
+    const fn test_mm256_mask_cmpgt_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52359,7 +52359,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epi32_mask() {
+    const fn test_mm_cmpgt_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmpgt_epi32_mask(a, b);
@@ -52367,7 +52367,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epi32_mask() {
+    const fn test_mm_mask_cmpgt_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52376,7 +52376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmple_epi32_mask() {
+    const fn test_mm512_cmple_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52388,7 +52388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmple_epi32_mask() {
+    const fn test_mm512_mask_cmple_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52398,7 +52398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmple_epi32_mask() {
+    const fn test_mm256_cmple_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 200, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmple_epi32_mask(a, b);
@@ -52406,7 +52406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epi32_mask() {
+    const fn test_mm256_mask_cmple_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 200, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52415,7 +52415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmple_epi32_mask() {
+    const fn test_mm_cmple_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 200);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmple_epi32_mask(a, b);
@@ -52423,7 +52423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epi32_mask() {
+    const fn test_mm_mask_cmple_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 200);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52432,7 +52432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpge_epi32_mask() {
+    const fn test_mm512_cmpge_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52444,7 +52444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpge_epi32_mask() {
+    const fn test_mm512_mask_cmpge_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
@@ -52457,7 +52457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epi32_mask() {
+    const fn test_mm256_cmpge_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let r = _mm256_cmpge_epi32_mask(a, b);
@@ -52465,7 +52465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epi32_mask() {
+    const fn test_mm256_mask_cmpge_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52474,7 +52474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpge_epi32_mask() {
+    const fn test_mm_cmpge_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set1_epi32(-1);
         let r = _mm_cmpge_epi32_mask(a, b);
@@ -52482,7 +52482,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epi32_mask() {
+    const fn test_mm_mask_cmpge_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, u32::MAX as i32);
         let b = _mm_set1_epi32(-1);
         let mask = 0b11111111;
@@ -52491,7 +52491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpeq_epi32_mask() {
+    const fn test_mm512_cmpeq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52503,7 +52503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpeq_epi32_mask() {
+    const fn test_mm512_mask_cmpeq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52516,7 +52516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epi32_mask() {
+    const fn test_mm256_cmpeq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let m = _mm256_cmpeq_epi32_mask(b, a);
@@ -52524,7 +52524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epi32_mask() {
+    const fn test_mm256_mask_cmpeq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let mask = 0b01111010;
@@ -52533,7 +52533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epi32_mask() {
+    const fn test_mm_cmpeq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let m = _mm_cmpeq_epi32_mask(b, a);
@@ -52541,7 +52541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epi32_mask() {
+    const fn test_mm_mask_cmpeq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -52550,7 +52550,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpneq_epi32_mask() {
+    const fn test_mm512_cmpneq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52562,7 +52562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpneq_epi32_mask() {
+    const fn test_mm512_mask_cmpneq_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100);
@@ -52575,7 +52575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epi32_mask() {
+    const fn test_mm256_cmpneq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let m = _mm256_cmpneq_epi32_mask(b, a);
@@ -52583,7 +52583,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epi32_mask() {
+    const fn test_mm256_mask_cmpneq_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100);
         let b = _mm256_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
         let mask = 0b11111111;
@@ -52592,7 +52592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epi32_mask() {
+    const fn test_mm_cmpneq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let r = _mm_cmpneq_epi32_mask(b, a);
@@ -52600,7 +52600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epi32_mask() {
+    const fn test_mm_mask_cmpneq_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set_epi32(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -52609,7 +52609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmp_epi32_mask() {
+    const fn test_mm512_cmp_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52619,7 +52619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmp_epi32_mask() {
+    const fn test_mm512_mask_cmp_epi32_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
@@ -52630,7 +52630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmp_epi32_mask() {
+    const fn test_mm256_cmp_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let m = _mm256_cmp_epi32_mask::<_MM_CMPINT_LT>(a, b);
@@ -52638,7 +52638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epi32_mask() {
+    const fn test_mm256_mask_cmp_epi32_mask() {
         let a = _mm256_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
         let b = _mm256_set1_epi32(-1);
         let mask = 0b01100110;
@@ -52647,7 +52647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmp_epi32_mask() {
+    const fn test_mm_cmp_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(1);
         let m = _mm_cmp_epi32_mask::<_MM_CMPINT_LT>(a, b);
@@ -52655,7 +52655,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epi32_mask() {
+    const fn test_mm_mask_cmp_epi32_mask() {
         let a = _mm_set_epi32(0, 1, -1, 13);
         let b = _mm_set1_epi32(1);
         let mask = 0b11111111;
@@ -52664,7 +52664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set_epi8() {
+    const fn test_mm512_set_epi8() {
         let r = _mm512_set1_epi8(2);
         assert_eq_m512i(
             r,
@@ -52677,7 +52677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set_epi16() {
+    const fn test_mm512_set_epi16() {
         let r = _mm512_set1_epi16(2);
         assert_eq_m512i(
             r,
@@ -52689,7 +52689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set_epi32() {
+    const fn test_mm512_set_epi32() {
         let r = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         assert_eq_m512i(
             r,
@@ -52698,7 +52698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr_epi32() {
+    const fn test_mm512_setr_epi32() {
         let r = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         assert_eq_m512i(
             r,
@@ -52707,7 +52707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set1_epi8() {
+    const fn test_mm512_set1_epi8() {
         let r = _mm512_set_epi8(
             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
@@ -52717,7 +52717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set1_epi16() {
+    const fn test_mm512_set1_epi16() {
         let r = _mm512_set_epi16(
             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
             2, 2, 2,
@@ -52726,23 +52726,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set1_epi32() {
+    const fn test_mm512_set1_epi32() {
         let r = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         assert_eq_m512i(r, _mm512_set1_epi32(2));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setzero_si512() {
+    const fn test_mm512_setzero_si512() {
         assert_eq_m512i(_mm512_set1_epi32(0), _mm512_setzero_si512());
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setzero_epi32() {
+    const fn test_mm512_setzero_epi32() {
         assert_eq_m512i(_mm512_set1_epi32(0), _mm512_setzero_epi32());
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set_ps() {
+    const fn test_mm512_set_ps() {
         let r = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -52755,7 +52755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr_ps() {
+    const fn test_mm512_setr_ps() {
         let r = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -52768,7 +52768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set1_ps() {
+    const fn test_mm512_set1_ps() {
         #[rustfmt::skip]
         let expected = _mm512_set_ps(2., 2., 2., 2., 2., 2., 2., 2.,
                                      2., 2., 2., 2., 2., 2., 2., 2.);
@@ -52776,13 +52776,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set4_epi32() {
+    const fn test_mm512_set4_epi32() {
         let r = _mm512_set_epi32(4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_set4_epi32(4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set4_ps() {
+    const fn test_mm512_set4_ps() {
         let r = _mm512_set_ps(
             4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1.,
         );
@@ -52790,13 +52790,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr4_epi32() {
+    const fn test_mm512_setr4_epi32() {
         let r = _mm512_set_epi32(4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_setr4_epi32(1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr4_ps() {
+    const fn test_mm512_setr4_ps() {
         let r = _mm512_set_ps(
             4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1., 4., 3., 2., 1.,
         );
@@ -52804,12 +52804,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setzero_ps() {
+    const fn test_mm512_setzero_ps() {
         assert_eq_m512(_mm512_setzero_ps(), _mm512_set1_ps(0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setzero() {
+    const fn test_mm512_setzero() {
         assert_eq_m512(_mm512_setzero(), _mm512_set1_ps(0.));
     }
 
@@ -53899,19 +53899,19 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr_pd() {
+    const fn test_mm512_setr_pd() {
         let r = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         assert_eq_m512d(r, _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set_pd() {
+    const fn test_mm512_set_pd() {
         let r = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         assert_eq_m512d(r, _mm512_set_pd(7., 6., 5., 4., 3., 2., 1., 0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_rol_epi32() {
+    const fn test_mm512_rol_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_rol_epi32::<1>(a);
         let e = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
@@ -53919,7 +53919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_rol_epi32() {
+    const fn test_mm512_mask_rol_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_mask_rol_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -53929,7 +53929,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_rol_epi32() {
+    const fn test_mm512_maskz_rol_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let r = _mm512_maskz_rol_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -53939,7 +53939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_rol_epi32() {
+    const fn test_mm256_rol_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_rol_epi32::<1>(a);
         let e = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
@@ -53947,7 +53947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_rol_epi32() {
+    const fn test_mm256_mask_rol_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_mask_rol_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -53957,7 +53957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_rol_epi32() {
+    const fn test_mm256_maskz_rol_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_maskz_rol_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -53967,7 +53967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_rol_epi32() {
+    const fn test_mm_rol_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_rol_epi32::<1>(a);
         let e = _mm_set_epi32(1 << 0, 2, 2, 2);
@@ -53975,7 +53975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_rol_epi32() {
+    const fn test_mm_mask_rol_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_mask_rol_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -53985,7 +53985,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_rol_epi32() {
+    const fn test_mm_maskz_rol_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_maskz_rol_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -53995,7 +53995,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_ror_epi32() {
+    const fn test_mm512_ror_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_ror_epi32::<1>(a);
         let e = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
@@ -54003,7 +54003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_ror_epi32() {
+    const fn test_mm512_mask_ror_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_mask_ror_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -54013,7 +54013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_ror_epi32() {
+    const fn test_mm512_maskz_ror_epi32() {
         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
         let r = _mm512_maskz_ror_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -54023,7 +54023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_ror_epi32() {
+    const fn test_mm256_ror_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm256_ror_epi32::<1>(a);
         let e = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
@@ -54031,7 +54031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_ror_epi32() {
+    const fn test_mm256_mask_ror_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm256_mask_ror_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -54041,7 +54041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_ror_epi32() {
+    const fn test_mm256_maskz_ror_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm256_maskz_ror_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -54051,7 +54051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_ror_epi32() {
+    const fn test_mm_ror_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let r = _mm_ror_epi32::<1>(a);
         let e = _mm_set_epi32(1 << 31, 1, 1, 1);
@@ -54059,7 +54059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_ror_epi32() {
+    const fn test_mm_mask_ror_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let r = _mm_mask_ror_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -54069,7 +54069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_ror_epi32() {
+    const fn test_mm_maskz_ror_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let r = _mm_maskz_ror_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54079,7 +54079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_slli_epi32() {
+    const fn test_mm512_slli_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_slli_epi32::<1>(a);
         let e = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
@@ -54087,7 +54087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_slli_epi32() {
+    const fn test_mm512_mask_slli_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_mask_slli_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -54097,7 +54097,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_slli_epi32() {
+    const fn test_mm512_maskz_slli_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let r = _mm512_maskz_slli_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -54107,7 +54107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_slli_epi32() {
+    const fn test_mm256_mask_slli_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_mask_slli_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -54117,7 +54117,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_slli_epi32() {
+    const fn test_mm256_maskz_slli_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm256_maskz_slli_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -54127,7 +54127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_slli_epi32() {
+    const fn test_mm_mask_slli_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_mask_slli_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -54137,7 +54137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_slli_epi32() {
+    const fn test_mm_maskz_slli_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let r = _mm_maskz_slli_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54147,7 +54147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srli_epi32() {
+    const fn test_mm512_srli_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_srli_epi32::<1>(a);
         let e = _mm512_set_epi32(0 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
@@ -54155,7 +54155,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srli_epi32() {
+    const fn test_mm512_mask_srli_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let r = _mm512_mask_srli_epi32::<1>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -54165,7 +54165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srli_epi32() {
+    const fn test_mm512_maskz_srli_epi32() {
         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
         let r = _mm512_maskz_srli_epi32::<1>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -54175,7 +54175,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srli_epi32() {
+    const fn test_mm256_mask_srli_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_mask_srli_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -54185,7 +54185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srli_epi32() {
+    const fn test_mm256_maskz_srli_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_maskz_srli_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -54195,7 +54195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srli_epi32() {
+    const fn test_mm_mask_srli_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_mask_srli_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -54205,7 +54205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srli_epi32() {
+    const fn test_mm_maskz_srli_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_maskz_srli_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54215,7 +54215,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_rolv_epi32() {
+    const fn test_mm512_rolv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_rolv_epi32(a, b);
@@ -54224,7 +54224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_rolv_epi32() {
+    const fn test_mm512_mask_rolv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_mask_rolv_epi32(a, 0, a, b);
@@ -54235,7 +54235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_rolv_epi32() {
+    const fn test_mm512_maskz_rolv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_rolv_epi32(0, a, b);
@@ -54246,7 +54246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_rolv_epi32() {
+    const fn test_mm256_rolv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_rolv_epi32(a, b);
@@ -54255,7 +54255,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_rolv_epi32() {
+    const fn test_mm256_mask_rolv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_rolv_epi32(a, 0, a, b);
@@ -54266,7 +54266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_rolv_epi32() {
+    const fn test_mm256_maskz_rolv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_rolv_epi32(0, a, b);
@@ -54277,7 +54277,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_rolv_epi32() {
+    const fn test_mm_rolv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let b = _mm_set1_epi32(1);
         let r = _mm_rolv_epi32(a, b);
@@ -54286,7 +54286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_rolv_epi32() {
+    const fn test_mm_mask_rolv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_rolv_epi32(a, 0, a, b);
@@ -54297,7 +54297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_rolv_epi32() {
+    const fn test_mm_maskz_rolv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_rolv_epi32(0, a, b);
@@ -54308,7 +54308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_rorv_epi32() {
+    const fn test_mm512_rorv_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_rorv_epi32(a, b);
@@ -54317,7 +54317,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_rorv_epi32() {
+    const fn test_mm512_mask_rorv_epi32() {
         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_mask_rorv_epi32(a, 0, a, b);
@@ -54328,7 +54328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_rorv_epi32() {
+    const fn test_mm512_maskz_rorv_epi32() {
         let a = _mm512_set_epi32(3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_rorv_epi32(0, a, b);
@@ -54339,7 +54339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_rorv_epi32() {
+    const fn test_mm256_rorv_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_rorv_epi32(a, b);
@@ -54348,7 +54348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_rorv_epi32() {
+    const fn test_mm256_mask_rorv_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_mask_rorv_epi32(a, 0, a, b);
@@ -54359,7 +54359,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_rorv_epi32() {
+    const fn test_mm256_maskz_rorv_epi32() {
         let a = _mm256_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_rorv_epi32(0, a, b);
@@ -54370,7 +54370,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_rorv_epi32() {
+    const fn test_mm_rorv_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let b = _mm_set1_epi32(1);
         let r = _mm_rorv_epi32(a, b);
@@ -54379,7 +54379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_rorv_epi32() {
+    const fn test_mm_mask_rorv_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let b = _mm_set1_epi32(1);
         let r = _mm_mask_rorv_epi32(a, 0, a, b);
@@ -54390,7 +54390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_rorv_epi32() {
+    const fn test_mm_maskz_rorv_epi32() {
         let a = _mm_set_epi32(1 << 0, 2, 2, 2);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_rorv_epi32(0, a, b);
@@ -54401,7 +54401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_sllv_epi32() {
+    const fn test_mm512_sllv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_sllv_epi32(a, count);
@@ -54410,7 +54410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_sllv_epi32() {
+    const fn test_mm512_mask_sllv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_mask_sllv_epi32(a, 0, a, count);
@@ -54421,7 +54421,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_sllv_epi32() {
+    const fn test_mm512_maskz_sllv_epi32() {
         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
         let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_maskz_sllv_epi32(0, a, count);
@@ -54432,7 +54432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_sllv_epi32() {
+    const fn test_mm256_mask_sllv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_mask_sllv_epi32(a, 0, a, count);
@@ -54443,7 +54443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_sllv_epi32() {
+    const fn test_mm256_maskz_sllv_epi32() {
         let a = _mm256_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_maskz_sllv_epi32(0, a, count);
@@ -54454,7 +54454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_sllv_epi32() {
+    const fn test_mm_mask_sllv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let count = _mm_set1_epi32(1);
         let r = _mm_mask_sllv_epi32(a, 0, a, count);
@@ -54465,7 +54465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_sllv_epi32() {
+    const fn test_mm_maskz_sllv_epi32() {
         let a = _mm_set_epi32(1 << 31, 1, 1, 1);
         let count = _mm_set1_epi32(1);
         let r = _mm_maskz_sllv_epi32(0, a, count);
@@ -54476,7 +54476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srlv_epi32() {
+    const fn test_mm512_srlv_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_srlv_epi32(a, count);
@@ -54485,7 +54485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srlv_epi32() {
+    const fn test_mm512_mask_srlv_epi32() {
         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
         let count = _mm512_set1_epi32(1);
         let r = _mm512_mask_srlv_epi32(a, 0, a, count);
@@ -54496,7 +54496,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srlv_epi32() {
+    const fn test_mm512_maskz_srlv_epi32() {
         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
         let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let r = _mm512_maskz_srlv_epi32(0, a, count);
@@ -54507,7 +54507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srlv_epi32() {
+    const fn test_mm256_mask_srlv_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_mask_srlv_epi32(a, 0, a, count);
@@ -54518,7 +54518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srlv_epi32() {
+    const fn test_mm256_maskz_srlv_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_maskz_srlv_epi32(0, a, count);
@@ -54529,7 +54529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srlv_epi32() {
+    const fn test_mm_mask_srlv_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_mask_srlv_epi32(a, 0, a, count);
@@ -54540,7 +54540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srlv_epi32() {
+    const fn test_mm_maskz_srlv_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_maskz_srlv_epi32(0, a, count);
@@ -54551,7 +54551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sll_epi32() {
+    fn test_mm512_sll_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 31, 1 << 0, 1 << 1, 1 << 2,
@@ -54572,7 +54572,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sll_epi32() {
+    fn test_mm512_mask_sll_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 31, 1 << 0, 1 << 1, 1 << 2,
@@ -54595,7 +54595,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sll_epi32() {
+    fn test_mm512_maskz_sll_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 31, 1 << 0, 1 << 1, 1 << 2,
@@ -54612,7 +54612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sll_epi32() {
+    fn test_mm256_mask_sll_epi32() {
         let a = _mm256_set_epi32(1 << 13, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm256_mask_sll_epi32(a, 0, a, count);
@@ -54623,7 +54623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sll_epi32() {
+    fn test_mm256_maskz_sll_epi32() {
         let a = _mm256_set_epi32(1 << 13, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm256_maskz_sll_epi32(0, a, count);
@@ -54634,7 +54634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sll_epi32() {
+    fn test_mm_mask_sll_epi32() {
         let a = _mm_set_epi32(1 << 13, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm_mask_sll_epi32(a, 0, a, count);
@@ -54645,7 +54645,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sll_epi32() {
+    fn test_mm_maskz_sll_epi32() {
         let a = _mm_set_epi32(1 << 13, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm_maskz_sll_epi32(0, a, count);
@@ -54656,7 +54656,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srl_epi32() {
+    fn test_mm512_srl_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 31, 1 << 0, 1 << 1, 1 << 2,
@@ -54671,7 +54671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srl_epi32() {
+    fn test_mm512_mask_srl_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 31, 1 << 0, 1 << 1, 1 << 2,
@@ -54688,7 +54688,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srl_epi32() {
+    fn test_mm512_maskz_srl_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 31, 1 << 0, 1 << 1, 1 << 2,
@@ -54705,7 +54705,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srl_epi32() {
+    fn test_mm256_mask_srl_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm256_mask_srl_epi32(a, 0, a, count);
@@ -54716,7 +54716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srl_epi32() {
+    fn test_mm256_maskz_srl_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm256_maskz_srl_epi32(0, a, count);
@@ -54727,7 +54727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srl_epi32() {
+    fn test_mm_mask_srl_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm_mask_srl_epi32(a, 0, a, count);
@@ -54738,7 +54738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srl_epi32() {
+    fn test_mm_maskz_srl_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm_maskz_srl_epi32(0, a, count);
@@ -54749,7 +54749,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sra_epi32() {
+    fn test_mm512_sra_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
         let count = _mm_set_epi32(1, 0, 0, 2);
         let r = _mm512_sra_epi32(a, count);
@@ -54758,7 +54758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sra_epi32() {
+    fn test_mm512_mask_sra_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16);
         let count = _mm_set_epi32(0, 0, 0, 2);
         let r = _mm512_mask_sra_epi32(a, 0, a, count);
@@ -54769,7 +54769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sra_epi32() {
+    fn test_mm512_maskz_sra_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -15, -14);
         let count = _mm_set_epi32(2, 0, 0, 2);
         let r = _mm512_maskz_sra_epi32(0, a, count);
@@ -54780,7 +54780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sra_epi32() {
+    fn test_mm256_mask_sra_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm256_mask_sra_epi32(a, 0, a, count);
@@ -54791,7 +54791,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sra_epi32() {
+    fn test_mm256_maskz_sra_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm256_maskz_sra_epi32(0, a, count);
@@ -54802,7 +54802,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sra_epi32() {
+    fn test_mm_mask_sra_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm_mask_sra_epi32(a, 0, a, count);
@@ -54813,7 +54813,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sra_epi32() {
+    fn test_mm_maskz_sra_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set_epi32(0, 0, 0, 1);
         let r = _mm_maskz_sra_epi32(0, a, count);
@@ -54824,7 +54824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srav_epi32() {
+    const fn test_mm512_srav_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm512_srav_epi32(a, count);
@@ -54833,7 +54833,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srav_epi32() {
+    const fn test_mm512_mask_srav_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16);
         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
         let r = _mm512_mask_srav_epi32(a, 0, a, count);
@@ -54844,7 +54844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srav_epi32() {
+    const fn test_mm512_maskz_srav_epi32() {
         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -15, -14);
         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2);
         let r = _mm512_maskz_srav_epi32(0, a, count);
@@ -54855,7 +54855,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srav_epi32() {
+    const fn test_mm256_mask_srav_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_mask_srav_epi32(a, 0, a, count);
@@ -54866,7 +54866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srav_epi32() {
+    const fn test_mm256_maskz_srav_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let count = _mm256_set1_epi32(1);
         let r = _mm256_maskz_srav_epi32(0, a, count);
@@ -54877,7 +54877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srav_epi32() {
+    const fn test_mm_mask_srav_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_mask_srav_epi32(a, 0, a, count);
@@ -54888,7 +54888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srav_epi32() {
+    const fn test_mm_maskz_srav_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let count = _mm_set1_epi32(1);
         let r = _mm_maskz_srav_epi32(0, a, count);
@@ -54899,7 +54899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srai_epi32() {
+    const fn test_mm512_srai_epi32() {
         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, -15);
         let r = _mm512_srai_epi32::<2>(a);
         let e = _mm512_set_epi32(2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, -4);
@@ -54907,7 +54907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srai_epi32() {
+    const fn test_mm512_mask_srai_epi32() {
         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, -15);
         let r = _mm512_mask_srai_epi32::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -54917,7 +54917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srai_epi32() {
+    const fn test_mm512_maskz_srai_epi32() {
         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, -15);
         let r = _mm512_maskz_srai_epi32::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -54927,7 +54927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srai_epi32() {
+    const fn test_mm256_mask_srai_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_mask_srai_epi32::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -54937,7 +54937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srai_epi32() {
+    const fn test_mm256_maskz_srai_epi32() {
         let a = _mm256_set_epi32(1 << 5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm256_maskz_srai_epi32::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -54947,7 +54947,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srai_epi32() {
+    const fn test_mm_mask_srai_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_mask_srai_epi32::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -54957,7 +54957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srai_epi32() {
+    const fn test_mm_maskz_srai_epi32() {
         let a = _mm_set_epi32(1 << 5, 0, 0, 0);
         let r = _mm_maskz_srai_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -54967,7 +54967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_permute_ps() {
+    const fn test_mm512_permute_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -54979,7 +54979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_permute_ps() {
+    const fn test_mm512_mask_permute_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -54993,7 +54993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_permute_ps() {
+    const fn test_mm512_maskz_permute_ps() {
         let a = _mm512_setr_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55007,7 +55007,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_permute_ps() {
+    const fn test_mm256_mask_permute_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_mask_permute_ps::<0b11_11_11_11>(a, 0, a);
         assert_eq_m256(r, a);
@@ -55017,7 +55017,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_permute_ps() {
+    const fn test_mm256_maskz_permute_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_maskz_permute_ps::<0b11_11_11_11>(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -55027,7 +55027,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_permute_ps() {
+    const fn test_mm_mask_permute_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_mask_permute_ps::<0b11_11_11_11>(a, 0, a);
         assert_eq_m128(r, a);
@@ -55037,7 +55037,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_permute_ps() {
+    const fn test_mm_maskz_permute_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_maskz_permute_ps::<0b11_11_11_11>(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -55047,7 +55047,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutevar_epi32() {
+    fn test_mm512_permutevar_epi32() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_permutevar_epi32(idx, a);
@@ -55056,7 +55056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutevar_epi32() {
+    fn test_mm512_mask_permutevar_epi32() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_mask_permutevar_epi32(a, 0, idx, a);
@@ -55067,7 +55067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutevar_ps() {
+    fn test_mm512_permutevar_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55080,7 +55080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutevar_ps() {
+    fn test_mm512_mask_permutevar_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55095,7 +55095,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutevar_ps() {
+    fn test_mm512_maskz_permutevar_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55110,7 +55110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutevar_ps() {
+    fn test_mm256_mask_permutevar_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm256_set1_epi32(0b01);
         let r = _mm256_mask_permutevar_ps(a, 0, a, b);
@@ -55121,7 +55121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutevar_ps() {
+    fn test_mm256_maskz_permutevar_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm256_set1_epi32(0b01);
         let r = _mm256_maskz_permutevar_ps(0, a, b);
@@ -55132,7 +55132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permutevar_ps() {
+    fn test_mm_mask_permutevar_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set1_epi32(0b01);
         let r = _mm_mask_permutevar_ps(a, 0, a, b);
@@ -55143,7 +55143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permutevar_ps() {
+    fn test_mm_maskz_permutevar_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set1_epi32(0b01);
         let r = _mm_maskz_permutevar_ps(0, a, b);
@@ -55154,7 +55154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutexvar_epi32() {
+    fn test_mm512_permutexvar_epi32() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_permutexvar_epi32(idx, a);
@@ -55163,7 +55163,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutexvar_epi32() {
+    fn test_mm512_mask_permutexvar_epi32() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_mask_permutexvar_epi32(a, 0, idx, a);
@@ -55174,7 +55174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutexvar_epi32() {
+    fn test_mm512_maskz_permutexvar_epi32() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_permutexvar_epi32(0, idx, a);
@@ -55185,7 +55185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutexvar_epi32() {
+    fn test_mm256_permutexvar_epi32() {
         let idx = _mm256_set1_epi32(1);
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_permutexvar_epi32(idx, a);
@@ -55194,7 +55194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutexvar_epi32() {
+    fn test_mm256_mask_permutexvar_epi32() {
         let idx = _mm256_set1_epi32(1);
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_mask_permutexvar_epi32(a, 0, idx, a);
@@ -55205,7 +55205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutexvar_epi32() {
+    fn test_mm256_maskz_permutexvar_epi32() {
         let idx = _mm256_set1_epi32(1);
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_permutexvar_epi32(0, idx, a);
@@ -55216,7 +55216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutexvar_ps() {
+    fn test_mm512_permutexvar_ps() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -55227,7 +55227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutexvar_ps() {
+    fn test_mm512_mask_permutexvar_ps() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -55240,7 +55240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutexvar_ps() {
+    fn test_mm512_maskz_permutexvar_ps() {
         let idx = _mm512_set1_epi32(1);
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -55255,7 +55255,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutexvar_ps() {
+    fn test_mm256_permutexvar_ps() {
         let idx = _mm256_set1_epi32(1);
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_permutexvar_ps(idx, a);
@@ -55264,7 +55264,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutexvar_ps() {
+    fn test_mm256_mask_permutexvar_ps() {
         let idx = _mm256_set1_epi32(1);
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_mask_permutexvar_ps(a, 0, idx, a);
@@ -55275,7 +55275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutexvar_ps() {
+    fn test_mm256_maskz_permutexvar_ps() {
         let idx = _mm256_set1_epi32(1);
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_maskz_permutexvar_ps(0, idx, a);
@@ -55286,7 +55286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutex2var_epi32() {
+    fn test_mm512_permutex2var_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm512_set_epi32(
@@ -55304,7 +55304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutex2var_epi32() {
+    fn test_mm512_mask_permutex2var_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm512_set_epi32(
@@ -55324,7 +55324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutex2var_epi32() {
+    fn test_mm512_maskz_permutex2var_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm512_set_epi32(
@@ -55342,7 +55342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask2_permutex2var_epi32() {
+    fn test_mm512_mask2_permutex2var_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm512_set_epi32(
@@ -55366,7 +55366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutex2var_epi32() {
+    fn test_mm256_permutex2var_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_epi32(100);
@@ -55376,7 +55376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutex2var_epi32() {
+    fn test_mm256_mask_permutex2var_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_epi32(100);
@@ -55388,7 +55388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex2var_epi32() {
+    fn test_mm256_maskz_permutex2var_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_epi32(100);
@@ -55400,7 +55400,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask2_permutex2var_epi32() {
+    fn test_mm256_mask2_permutex2var_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_epi32(100);
@@ -55412,7 +55412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_permutex2var_epi32() {
+    fn test_mm_permutex2var_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_epi32(100);
@@ -55422,7 +55422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permutex2var_epi32() {
+    fn test_mm_mask_permutex2var_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_epi32(100);
@@ -55434,7 +55434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permutex2var_epi32() {
+    fn test_mm_maskz_permutex2var_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_epi32(100);
@@ -55446,7 +55446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask2_permutex2var_epi32() {
+    fn test_mm_mask2_permutex2var_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_epi32(100);
@@ -55458,7 +55458,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutex2var_ps() {
+    fn test_mm512_permutex2var_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55478,7 +55478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutex2var_ps() {
+    fn test_mm512_mask_permutex2var_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55500,7 +55500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutex2var_ps() {
+    fn test_mm512_maskz_permutex2var_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55522,7 +55522,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask2_permutex2var_ps() {
+    fn test_mm512_mask2_permutex2var_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -55544,7 +55544,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutex2var_ps() {
+    fn test_mm256_permutex2var_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_ps(100.);
@@ -55554,7 +55554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutex2var_ps() {
+    fn test_mm256_mask_permutex2var_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_ps(100.);
@@ -55566,7 +55566,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex2var_ps() {
+    fn test_mm256_maskz_permutex2var_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_ps(100.);
@@ -55578,7 +55578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask2_permutex2var_ps() {
+    fn test_mm256_mask2_permutex2var_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm256_set_epi32(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm256_set1_ps(100.);
@@ -55590,7 +55590,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_permutex2var_ps() {
+    fn test_mm_permutex2var_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_ps(100.);
@@ -55600,7 +55600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permutex2var_ps() {
+    fn test_mm_mask_permutex2var_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_ps(100.);
@@ -55612,7 +55612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permutex2var_ps() {
+    fn test_mm_maskz_permutex2var_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_ps(100.);
@@ -55624,7 +55624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask2_permutex2var_ps() {
+    fn test_mm_mask2_permutex2var_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let idx = _mm_set_epi32(1, 1 << 2, 2, 1 << 2);
         let b = _mm_set1_ps(100.);
@@ -55636,7 +55636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_epi32() {
+    const fn test_mm512_shuffle_epi32() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm512_shuffle_epi32::<_MM_PERM_AADD>(a);
         let e = _mm512_setr_epi32(8, 8, 1, 1, 16, 16, 9, 9, 8, 8, 1, 1, 16, 16, 9, 9);
@@ -55644,7 +55644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_epi32() {
+    const fn test_mm512_mask_shuffle_epi32() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm512_mask_shuffle_epi32::<_MM_PERM_AADD>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -55654,7 +55654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_epi32() {
+    const fn test_mm512_maskz_shuffle_epi32() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm512_maskz_shuffle_epi32::<_MM_PERM_AADD>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -55664,7 +55664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_epi32() {
+    const fn test_mm256_mask_shuffle_epi32() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm256_mask_shuffle_epi32::<_MM_PERM_AADD>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -55674,7 +55674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_epi32() {
+    const fn test_mm256_maskz_shuffle_epi32() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let r = _mm256_maskz_shuffle_epi32::<_MM_PERM_AADD>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -55684,7 +55684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_shuffle_epi32() {
+    const fn test_mm_mask_shuffle_epi32() {
         let a = _mm_set_epi32(1, 4, 5, 8);
         let r = _mm_mask_shuffle_epi32::<_MM_PERM_AADD>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -55694,7 +55694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_shuffle_epi32() {
+    const fn test_mm_maskz_shuffle_epi32() {
         let a = _mm_set_epi32(1, 4, 5, 8);
         let r = _mm_maskz_shuffle_epi32::<_MM_PERM_AADD>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -55704,7 +55704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_ps() {
+    const fn test_mm512_shuffle_ps() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -55719,7 +55719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_ps() {
+    const fn test_mm512_mask_shuffle_ps() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -55736,7 +55736,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_ps() {
+    const fn test_mm512_maskz_shuffle_ps() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -55753,7 +55753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_ps() {
+    const fn test_mm256_mask_shuffle_ps() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_mask_shuffle_ps::<0b11_11_11_11>(a, 0, a, b);
@@ -55764,7 +55764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_ps() {
+    const fn test_mm256_maskz_shuffle_ps() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_maskz_shuffle_ps::<0b11_11_11_11>(0, a, b);
@@ -55775,7 +55775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_shuffle_ps() {
+    const fn test_mm_mask_shuffle_ps() {
         let a = _mm_set_ps(1., 4., 5., 8.);
         let b = _mm_set_ps(2., 3., 6., 7.);
         let r = _mm_mask_shuffle_ps::<0b11_11_11_11>(a, 0, a, b);
@@ -55786,7 +55786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_shuffle_ps() {
+    const fn test_mm_maskz_shuffle_ps() {
         let a = _mm_set_ps(1., 4., 5., 8.);
         let b = _mm_set_ps(2., 3., 6., 7.);
         let r = _mm_maskz_shuffle_ps::<0b11_11_11_11>(0, a, b);
@@ -55797,7 +55797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_i32x4() {
+    const fn test_mm512_shuffle_i32x4() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_shuffle_i32x4::<0b00_00_00_00>(a, b);
@@ -55806,7 +55806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_i32x4() {
+    const fn test_mm512_mask_shuffle_i32x4() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_mask_shuffle_i32x4::<0b00_00_00_00>(a, 0, a, b);
@@ -55817,7 +55817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_i32x4() {
+    const fn test_mm512_maskz_shuffle_i32x4() {
         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_maskz_shuffle_i32x4::<0b00_00_00_00>(0, a, b);
@@ -55828,7 +55828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_shuffle_i32x4() {
+    const fn test_mm256_shuffle_i32x4() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm256_set_epi32(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm256_shuffle_i32x4::<0b00>(a, b);
@@ -55837,7 +55837,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_i32x4() {
+    const fn test_mm256_mask_shuffle_i32x4() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm256_set_epi32(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm256_mask_shuffle_i32x4::<0b00>(a, 0, a, b);
@@ -55848,7 +55848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_i32x4() {
+    const fn test_mm256_maskz_shuffle_i32x4() {
         let a = _mm256_set_epi32(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm256_set_epi32(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm256_maskz_shuffle_i32x4::<0b00>(0, a, b);
@@ -55859,7 +55859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_f32x4() {
+    const fn test_mm512_shuffle_f32x4() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -55874,7 +55874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_f32x4() {
+    const fn test_mm512_mask_shuffle_f32x4() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -55891,7 +55891,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_f32x4() {
+    const fn test_mm512_maskz_shuffle_f32x4() {
         let a = _mm512_setr_ps(
             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
         );
@@ -55908,7 +55908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_shuffle_f32x4() {
+    const fn test_mm256_shuffle_f32x4() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_shuffle_f32x4::<0b00>(a, b);
@@ -55917,7 +55917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_f32x4() {
+    const fn test_mm256_mask_shuffle_f32x4() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_mask_shuffle_f32x4::<0b00>(a, 0, a, b);
@@ -55928,7 +55928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_f32x4() {
+    const fn test_mm256_maskz_shuffle_f32x4() {
         let a = _mm256_set_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_set_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_maskz_shuffle_f32x4::<0b00>(0, a, b);
@@ -55939,7 +55939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_extractf32x4_ps() {
+    const fn test_mm512_extractf32x4_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -55949,7 +55949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_extractf32x4_ps() {
+    const fn test_mm512_mask_extractf32x4_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -55962,7 +55962,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_extractf32x4_ps() {
+    const fn test_mm512_maskz_extractf32x4_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -55974,7 +55974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_extractf32x4_ps() {
+    const fn test_mm256_extractf32x4_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_extractf32x4_ps::<1>(a);
         let e = _mm_set_ps(1., 2., 3., 4.);
@@ -55982,7 +55982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_extractf32x4_ps() {
+    const fn test_mm256_mask_extractf32x4_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let src = _mm_set1_ps(100.);
         let r = _mm256_mask_extractf32x4_ps::<1>(src, 0, a);
@@ -55993,7 +55993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_extractf32x4_ps() {
+    const fn test_mm256_maskz_extractf32x4_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_maskz_extractf32x4_ps::<1>(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -56003,7 +56003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_extracti32x4_epi32() {
+    const fn test_mm512_extracti32x4_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_extracti32x4_epi32::<1>(a);
         let e = _mm_setr_epi32(5, 6, 7, 8);
@@ -56011,7 +56011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_extracti32x4_epi32() {
+    const fn test_mm512_mask_extracti32x4_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm_set1_epi32(100);
         let r = _mm512_mask_extracti32x4_epi32::<1>(src, 0, a);
@@ -56022,7 +56022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm512_maskz_extracti32x4_epi32() {
+    const fn test_mm512_maskz_extracti32x4_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_extracti32x4_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -56032,7 +56032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_extracti32x4_epi32() {
+    const fn test_mm256_extracti32x4_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_extracti32x4_epi32::<1>(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -56040,7 +56040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_extracti32x4_epi32() {
+    const fn test_mm256_mask_extracti32x4_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set1_epi32(100);
         let r = _mm256_mask_extracti32x4_epi32::<1>(src, 0, a);
@@ -56051,7 +56051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_extracti32x4_epi32() {
+    const fn test_mm256_maskz_extracti32x4_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_extracti32x4_epi32::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -56061,7 +56061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_moveldup_ps() {
+    const fn test_mm512_moveldup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56073,7 +56073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_moveldup_ps() {
+    const fn test_mm512_mask_moveldup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56087,7 +56087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_moveldup_ps() {
+    const fn test_mm512_maskz_moveldup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56101,7 +56101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_moveldup_ps() {
+    const fn test_mm256_mask_moveldup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_mask_moveldup_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -56111,7 +56111,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_moveldup_ps() {
+    const fn test_mm256_maskz_moveldup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_maskz_moveldup_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -56121,7 +56121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_moveldup_ps() {
+    const fn test_mm_mask_moveldup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_mask_moveldup_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -56131,7 +56131,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_moveldup_ps() {
+    const fn test_mm_maskz_moveldup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_moveldup_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -56141,7 +56141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_movehdup_ps() {
+    const fn test_mm512_movehdup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56153,7 +56153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_movehdup_ps() {
+    const fn test_mm512_mask_movehdup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56167,7 +56167,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_movehdup_ps() {
+    const fn test_mm512_maskz_movehdup_ps() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56181,7 +56181,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_movehdup_ps() {
+    const fn test_mm256_mask_movehdup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_mask_movehdup_ps(a, 0, a);
         assert_eq_m256(r, a);
@@ -56191,7 +56191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_movehdup_ps() {
+    const fn test_mm256_maskz_movehdup_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_maskz_movehdup_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -56201,7 +56201,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_movehdup_ps() {
+    const fn test_mm_mask_movehdup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_mask_movehdup_ps(a, 0, a);
         assert_eq_m128(r, a);
@@ -56211,7 +56211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_movehdup_ps() {
+    const fn test_mm_maskz_movehdup_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let r = _mm_maskz_movehdup_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -56221,7 +56221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_inserti32x4() {
+    const fn test_mm512_inserti32x4() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_setr_epi32(17, 18, 19, 20);
         let r = _mm512_inserti32x4::<0>(a, b);
@@ -56230,7 +56230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_inserti32x4() {
+    const fn test_mm512_mask_inserti32x4() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_setr_epi32(17, 18, 19, 20);
         let r = _mm512_mask_inserti32x4::<0>(a, 0, a, b);
@@ -56241,7 +56241,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_inserti32x4() {
+    const fn test_mm512_maskz_inserti32x4() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm_setr_epi32(17, 18, 19, 20);
         let r = _mm512_maskz_inserti32x4::<0>(0, a, b);
@@ -56252,7 +56252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_inserti32x4() {
+    const fn test_mm256_inserti32x4() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_inserti32x4::<1>(a, b);
@@ -56261,7 +56261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_inserti32x4() {
+    const fn test_mm256_mask_inserti32x4() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_mask_inserti32x4::<0>(a, 0, a, b);
@@ -56272,7 +56272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_inserti32x4() {
+    const fn test_mm256_maskz_inserti32x4() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_maskz_inserti32x4::<0>(0, a, b);
@@ -56283,7 +56283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_insertf32x4() {
+    const fn test_mm512_insertf32x4() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56296,7 +56296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_insertf32x4() {
+    const fn test_mm512_mask_insertf32x4() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56311,7 +56311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_insertf32x4() {
+    const fn test_mm512_maskz_insertf32x4() {
         let a = _mm512_setr_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56326,7 +56326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_insertf32x4() {
+    const fn test_mm256_insertf32x4() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_insertf32x4::<1>(a, b);
@@ -56335,7 +56335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_insertf32x4() {
+    const fn test_mm256_mask_insertf32x4() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_mask_insertf32x4::<0>(a, 0, a, b);
@@ -56346,7 +56346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_insertf32x4() {
+    const fn test_mm256_maskz_insertf32x4() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_maskz_insertf32x4::<0>(0, a, b);
@@ -56357,21 +56357,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castps128_ps512() {
+    const fn test_mm512_castps128_ps512() {
         let a = _mm_setr_ps(17., 18., 19., 20.);
         let r = _mm512_castps128_ps512(a);
         assert_eq_m128(_mm512_castps512_ps128(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castps256_ps512() {
+    const fn test_mm512_castps256_ps512() {
         let a = _mm256_setr_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_castps256_ps512(a);
         assert_eq_m256(_mm512_castps512_ps256(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_zextps128_ps512() {
+    const fn test_mm512_zextps128_ps512() {
         let a = _mm_setr_ps(17., 18., 19., 20.);
         let r = _mm512_zextps128_ps512(a);
         let e = _mm512_setr_ps(
@@ -56381,7 +56381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_zextps256_ps512() {
+    const fn test_mm512_zextps256_ps512() {
         let a = _mm256_setr_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_zextps256_ps512(a);
         let e = _mm512_setr_ps(
@@ -56391,7 +56391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castps512_ps128() {
+    const fn test_mm512_castps512_ps128() {
         let a = _mm512_setr_ps(
             17., 18., 19., 20., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1.,
         );
@@ -56401,7 +56401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castps512_ps256() {
+    const fn test_mm512_castps512_ps256() {
         let a = _mm512_setr_ps(
             17., 18., 19., 20., 21., 22., 23., 24., -1., -1., -1., -1., -1., -1., -1., -1.,
         );
@@ -56411,7 +56411,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castps_pd() {
+    const fn test_mm512_castps_pd() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_castps_pd(a);
         let e = _mm512_set1_pd(0.007812501848093234);
@@ -56419,7 +56419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castps_si512() {
+    const fn test_mm512_castps_si512() {
         let a = _mm512_set1_ps(1.);
         let r = _mm512_castps_si512(a);
         let e = _mm512_set1_epi32(1065353216);
@@ -56427,7 +56427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcastd_epi32() {
+    const fn test_mm512_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_broadcastd_epi32(a);
         let e = _mm512_set1_epi32(20);
@@ -56435,7 +56435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcastd_epi32() {
+    const fn test_mm512_mask_broadcastd_epi32() {
         let src = _mm512_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_mask_broadcastd_epi32(src, 0, a);
@@ -56446,7 +56446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcastd_epi32() {
+    const fn test_mm512_maskz_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_maskz_broadcastd_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -56456,7 +56456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcastd_epi32() {
+    const fn test_mm256_mask_broadcastd_epi32() {
         let src = _mm256_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_mask_broadcastd_epi32(src, 0, a);
@@ -56467,7 +56467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcastd_epi32() {
+    const fn test_mm256_maskz_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_maskz_broadcastd_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -56477,7 +56477,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_broadcastd_epi32() {
+    const fn test_mm_mask_broadcastd_epi32() {
         let src = _mm_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_mask_broadcastd_epi32(src, 0, a);
@@ -56488,7 +56488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_broadcastd_epi32() {
+    const fn test_mm_maskz_broadcastd_epi32() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_maskz_broadcastd_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -56498,7 +56498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcastss_ps() {
+    const fn test_mm512_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_broadcastss_ps(a);
         let e = _mm512_set1_ps(20.);
@@ -56506,7 +56506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcastss_ps() {
+    const fn test_mm512_mask_broadcastss_ps() {
         let src = _mm512_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_mask_broadcastss_ps(src, 0, a);
@@ -56517,7 +56517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcastss_ps() {
+    const fn test_mm512_maskz_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_maskz_broadcastss_ps(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -56529,7 +56529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcastss_ps() {
+    const fn test_mm256_mask_broadcastss_ps() {
         let src = _mm256_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_mask_broadcastss_ps(src, 0, a);
@@ -56540,7 +56540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcastss_ps() {
+    const fn test_mm256_maskz_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_maskz_broadcastss_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -56550,7 +56550,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_broadcastss_ps() {
+    const fn test_mm_mask_broadcastss_ps() {
         let src = _mm_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_mask_broadcastss_ps(src, 0, a);
@@ -56561,7 +56561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_broadcastss_ps() {
+    const fn test_mm_maskz_broadcastss_ps() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_maskz_broadcastss_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -56571,7 +56571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcast_i32x4() {
+    const fn test_mm512_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_broadcast_i32x4(a);
         let e = _mm512_set_epi32(
@@ -56581,7 +56581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcast_i32x4() {
+    const fn test_mm512_mask_broadcast_i32x4() {
         let src = _mm512_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_mask_broadcast_i32x4(src, 0, a);
@@ -56594,7 +56594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcast_i32x4() {
+    const fn test_mm512_maskz_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm512_maskz_broadcast_i32x4(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -56604,7 +56604,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_broadcast_i32x4() {
+    const fn test_mm256_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_broadcast_i32x4(a);
         let e = _mm256_set_epi32(17, 18, 19, 20, 17, 18, 19, 20);
@@ -56612,7 +56612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcast_i32x4() {
+    const fn test_mm256_mask_broadcast_i32x4() {
         let src = _mm256_set1_epi32(20);
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_mask_broadcast_i32x4(src, 0, a);
@@ -56623,7 +56623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcast_i32x4() {
+    const fn test_mm256_maskz_broadcast_i32x4() {
         let a = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm256_maskz_broadcast_i32x4(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -56633,7 +56633,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcast_f32x4() {
+    const fn test_mm512_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_broadcast_f32x4(a);
         let e = _mm512_set_ps(
@@ -56643,7 +56643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcast_f32x4() {
+    const fn test_mm512_mask_broadcast_f32x4() {
         let src = _mm512_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_mask_broadcast_f32x4(src, 0, a);
@@ -56656,7 +56656,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcast_f32x4() {
+    const fn test_mm512_maskz_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm512_maskz_broadcast_f32x4(0, a);
         assert_eq_m512(r, _mm512_setzero_ps());
@@ -56668,7 +56668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_broadcast_f32x4() {
+    const fn test_mm256_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_broadcast_f32x4(a);
         let e = _mm256_set_ps(17., 18., 19., 20., 17., 18., 19., 20.);
@@ -56676,7 +56676,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcast_f32x4() {
+    const fn test_mm256_mask_broadcast_f32x4() {
         let src = _mm256_set1_ps(20.);
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_mask_broadcast_f32x4(src, 0, a);
@@ -56687,7 +56687,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcast_f32x4() {
+    const fn test_mm256_maskz_broadcast_f32x4() {
         let a = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm256_maskz_broadcast_f32x4(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -56697,7 +56697,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_blend_epi32() {
+    const fn test_mm512_mask_blend_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(2);
         let r = _mm512_mask_blend_epi32(0b11111111_00000000, a, b);
@@ -56706,7 +56706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_epi32() {
+    const fn test_mm256_mask_blend_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(2);
         let r = _mm256_mask_blend_epi32(0b11111111, a, b);
@@ -56715,7 +56715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_blend_epi32() {
+    const fn test_mm_mask_blend_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(2);
         let r = _mm_mask_blend_epi32(0b00001111, a, b);
@@ -56724,7 +56724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_blend_ps() {
+    const fn test_mm512_mask_blend_ps() {
         let a = _mm512_set1_ps(1.);
         let b = _mm512_set1_ps(2.);
         let r = _mm512_mask_blend_ps(0b11111111_00000000, a, b);
@@ -56735,7 +56735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_ps() {
+    const fn test_mm256_mask_blend_ps() {
         let a = _mm256_set1_ps(1.);
         let b = _mm256_set1_ps(2.);
         let r = _mm256_mask_blend_ps(0b11111111, a, b);
@@ -56744,7 +56744,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_blend_ps() {
+    const fn test_mm_mask_blend_ps() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let r = _mm_mask_blend_ps(0b00001111, a, b);
@@ -56753,7 +56753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpackhi_epi32() {
+    const fn test_mm512_unpackhi_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -56764,7 +56764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpackhi_epi32() {
+    const fn test_mm512_mask_unpackhi_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -56777,7 +56777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpackhi_epi32() {
+    const fn test_mm512_maskz_unpackhi_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -56790,7 +56790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpackhi_epi32() {
+    const fn test_mm256_mask_unpackhi_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_mask_unpackhi_epi32(a, 0, a, b);
@@ -56801,7 +56801,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpackhi_epi32() {
+    const fn test_mm256_maskz_unpackhi_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_maskz_unpackhi_epi32(0, a, b);
@@ -56812,7 +56812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpackhi_epi32() {
+    const fn test_mm_mask_unpackhi_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_mask_unpackhi_epi32(a, 0, a, b);
@@ -56823,7 +56823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpackhi_epi32() {
+    const fn test_mm_maskz_unpackhi_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_maskz_unpackhi_epi32(0, a, b);
@@ -56834,7 +56834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpackhi_ps() {
+    const fn test_mm512_unpackhi_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56849,7 +56849,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpackhi_ps() {
+    const fn test_mm512_mask_unpackhi_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56866,7 +56866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpackhi_ps() {
+    const fn test_mm512_maskz_unpackhi_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -56883,7 +56883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpackhi_ps() {
+    const fn test_mm256_mask_unpackhi_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_mask_unpackhi_ps(a, 0, a, b);
@@ -56894,7 +56894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpackhi_ps() {
+    const fn test_mm256_maskz_unpackhi_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_maskz_unpackhi_ps(0, a, b);
@@ -56905,7 +56905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpackhi_ps() {
+    const fn test_mm_mask_unpackhi_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_mask_unpackhi_ps(a, 0, a, b);
@@ -56916,7 +56916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpackhi_ps() {
+    const fn test_mm_maskz_unpackhi_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_maskz_unpackhi_ps(0, a, b);
@@ -56927,7 +56927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpacklo_epi32() {
+    const fn test_mm512_unpacklo_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -56938,7 +56938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpacklo_epi32() {
+    const fn test_mm512_mask_unpacklo_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -56951,7 +56951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpacklo_epi32() {
+    const fn test_mm512_maskz_unpacklo_epi32() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let b = _mm512_set_epi32(
             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
@@ -56964,7 +56964,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpacklo_epi32() {
+    const fn test_mm256_mask_unpacklo_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_mask_unpacklo_epi32(a, 0, a, b);
@@ -56975,7 +56975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpacklo_epi32() {
+    const fn test_mm256_maskz_unpacklo_epi32() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_set_epi32(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm256_maskz_unpacklo_epi32(0, a, b);
@@ -56986,7 +56986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpacklo_epi32() {
+    const fn test_mm_mask_unpacklo_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_mask_unpacklo_epi32(a, 0, a, b);
@@ -56997,7 +56997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpacklo_epi32() {
+    const fn test_mm_maskz_unpacklo_epi32() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let b = _mm_set_epi32(17, 18, 19, 20);
         let r = _mm_maskz_unpacklo_epi32(0, a, b);
@@ -57008,7 +57008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpacklo_ps() {
+    const fn test_mm512_unpacklo_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -57023,7 +57023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpacklo_ps() {
+    const fn test_mm512_mask_unpacklo_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -57040,7 +57040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpacklo_ps() {
+    const fn test_mm512_maskz_unpacklo_ps() {
         let a = _mm512_set_ps(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -57057,7 +57057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpacklo_ps() {
+    const fn test_mm256_mask_unpacklo_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_mask_unpacklo_ps(a, 0, a, b);
@@ -57068,7 +57068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpacklo_ps() {
+    const fn test_mm256_maskz_unpacklo_ps() {
         let a = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_set_ps(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm256_maskz_unpacklo_ps(0, a, b);
@@ -57079,7 +57079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpacklo_ps() {
+    const fn test_mm_mask_unpacklo_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_mask_unpacklo_ps(a, 0, a, b);
@@ -57090,7 +57090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpacklo_ps() {
+    const fn test_mm_maskz_unpacklo_ps() {
         let a = _mm_set_ps(1., 2., 3., 4.);
         let b = _mm_set_ps(17., 18., 19., 20.);
         let r = _mm_maskz_unpacklo_ps(0, a, b);
@@ -57101,7 +57101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_alignr_epi32() {
+    const fn test_mm512_alignr_epi32() {
         let a = _mm512_set_epi32(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi32(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17,
@@ -57118,7 +57118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_alignr_epi32() {
+    const fn test_mm512_mask_alignr_epi32() {
         let a = _mm512_set_epi32(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi32(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17,
@@ -57133,7 +57133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_alignr_epi32() {
+    const fn test_mm512_maskz_alignr_epi32() {
         let a = _mm512_set_epi32(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi32(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17,
@@ -57146,7 +57146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_alignr_epi32() {
+    const fn test_mm256_alignr_epi32() {
         let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm256_alignr_epi32::<0>(a, b);
@@ -57157,7 +57157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_alignr_epi32() {
+    const fn test_mm256_mask_alignr_epi32() {
         let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm256_mask_alignr_epi32::<1>(a, 0, a, b);
@@ -57168,7 +57168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_alignr_epi32() {
+    const fn test_mm256_maskz_alignr_epi32() {
         let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm256_maskz_alignr_epi32::<1>(0, a, b);
@@ -57179,7 +57179,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_alignr_epi32() {
+    const fn test_mm_alignr_epi32() {
         let a = _mm_set_epi32(4, 3, 2, 1);
         let b = _mm_set_epi32(8, 7, 6, 5);
         let r = _mm_alignr_epi32::<0>(a, b);
@@ -57190,7 +57190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_alignr_epi32() {
+    const fn test_mm_mask_alignr_epi32() {
         let a = _mm_set_epi32(4, 3, 2, 1);
         let b = _mm_set_epi32(8, 7, 6, 5);
         let r = _mm_mask_alignr_epi32::<1>(a, 0, a, b);
@@ -57201,7 +57201,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_alignr_epi32() {
+    const fn test_mm_maskz_alignr_epi32() {
         let a = _mm_set_epi32(4, 3, 2, 1);
         let b = _mm_set_epi32(8, 7, 6, 5);
         let r = _mm_maskz_alignr_epi32::<1>(0, a, b);
@@ -57212,7 +57212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_and_epi32() {
+    const fn test_mm512_and_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57233,7 +57233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_and_epi32() {
+    const fn test_mm512_mask_and_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57262,7 +57262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_and_epi32() {
+    const fn test_mm512_maskz_and_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57285,7 +57285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_and_epi32() {
+    const fn test_mm256_mask_and_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_and_epi32(a, 0, a, b);
@@ -57296,7 +57296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_and_epi32() {
+    const fn test_mm256_maskz_and_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_maskz_and_epi32(0, a, b);
@@ -57307,7 +57307,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_and_epi32() {
+    const fn test_mm_mask_and_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_and_epi32(a, 0, a, b);
@@ -57318,7 +57318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_and_epi32() {
+    const fn test_mm_maskz_and_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_maskz_and_epi32(0, a, b);
@@ -57329,7 +57329,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_and_si512() {
+    const fn test_mm512_and_si512() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57350,7 +57350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_or_epi32() {
+    const fn test_mm512_or_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57377,7 +57377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_or_epi32() {
+    const fn test_mm512_mask_or_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57406,7 +57406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_or_epi32() {
+    const fn test_mm512_maskz_or_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57435,7 +57435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_or_epi32() {
+    const fn test_mm256_or_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_or_epi32(a, b);
@@ -57444,7 +57444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_or_epi32() {
+    const fn test_mm256_mask_or_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_or_epi32(a, 0, a, b);
@@ -57455,7 +57455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_or_epi32() {
+    const fn test_mm256_maskz_or_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_maskz_or_epi32(0, a, b);
@@ -57466,7 +57466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_or_epi32() {
+    const fn test_mm_or_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_or_epi32(a, b);
@@ -57475,7 +57475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_or_epi32() {
+    const fn test_mm_mask_or_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_or_epi32(a, 0, a, b);
@@ -57486,7 +57486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_or_epi32() {
+    const fn test_mm_maskz_or_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_maskz_or_epi32(0, a, b);
@@ -57497,7 +57497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_or_si512() {
+    const fn test_mm512_or_si512() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57524,7 +57524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_xor_epi32() {
+    const fn test_mm512_xor_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57551,7 +57551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_xor_epi32() {
+    const fn test_mm512_mask_xor_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57580,7 +57580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_xor_epi32() {
+    const fn test_mm512_maskz_xor_epi32() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57603,7 +57603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_xor_epi32() {
+    const fn test_mm256_xor_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_xor_epi32(a, b);
@@ -57612,7 +57612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_xor_epi32() {
+    const fn test_mm256_mask_xor_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_xor_epi32(a, 0, a, b);
@@ -57623,7 +57623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_xor_epi32() {
+    const fn test_mm256_maskz_xor_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_maskz_xor_epi32(0, a, b);
@@ -57634,7 +57634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_xor_epi32() {
+    const fn test_mm_xor_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_xor_epi32(a, b);
@@ -57643,7 +57643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_xor_epi32() {
+    const fn test_mm_mask_xor_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_xor_epi32(a, 0, a, b);
@@ -57654,7 +57654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_xor_epi32() {
+    const fn test_mm_maskz_xor_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_maskz_xor_epi32(0, a, b);
@@ -57665,7 +57665,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_xor_si512() {
+    const fn test_mm512_xor_si512() {
         #[rustfmt::skip]
         let a = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57692,7 +57692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_andnot_epi32() {
+    const fn test_mm512_andnot_epi32() {
         let a = _mm512_set1_epi32(0);
         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm512_andnot_epi32(a, b);
@@ -57701,7 +57701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_andnot_epi32() {
+    const fn test_mm512_mask_andnot_epi32() {
         let a = _mm512_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm512_mask_andnot_epi32(a, 0, a, b);
@@ -57712,7 +57712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_andnot_epi32() {
+    const fn test_mm512_maskz_andnot_epi32() {
         let a = _mm512_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm512_maskz_andnot_epi32(0, a, b);
@@ -57729,7 +57729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_andnot_epi32() {
+    const fn test_mm256_mask_andnot_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm256_mask_andnot_epi32(a, 0, a, b);
@@ -57740,7 +57740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_andnot_epi32() {
+    const fn test_mm256_maskz_andnot_epi32() {
         let a = _mm256_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm256_maskz_andnot_epi32(0, a, b);
@@ -57751,7 +57751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_andnot_epi32() {
+    const fn test_mm_mask_andnot_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm_mask_andnot_epi32(a, 0, a, b);
@@ -57762,7 +57762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_andnot_epi32() {
+    const fn test_mm_maskz_andnot_epi32() {
         let a = _mm_set1_epi32(1 << 1 | 1 << 2);
         let b = _mm_set1_epi32(1 << 3 | 1 << 4);
         let r = _mm_maskz_andnot_epi32(0, a, b);
@@ -57773,7 +57773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_cvtmask16_u32() {
+    const fn test_cvtmask16_u32() {
         let a: __mmask16 = 0b11001100_00110011;
         let r = _cvtmask16_u32(a);
         let e: u32 = 0b11001100_00110011;
@@ -57781,7 +57781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_cvtu32_mask16() {
+    const fn test_cvtu32_mask16() {
         let a: u32 = 0b11001100_00110011;
         let r = _cvtu32_mask16(a);
         let e: __mmask16 = 0b11001100_00110011;
@@ -57789,7 +57789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kand() {
+    const fn test_mm512_kand() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b11001100_00110011;
         let r = _mm512_kand(a, b);
@@ -57798,7 +57798,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kand_mask16() {
+    const fn test_kand_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b11001100_00110011;
         let r = _kand_mask16(a, b);
@@ -57807,7 +57807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kor() {
+    const fn test_mm512_kor() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kor(a, b);
@@ -57816,7 +57816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kor_mask16() {
+    const fn test_kor_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kor_mask16(a, b);
@@ -57825,7 +57825,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kxor() {
+    const fn test_mm512_kxor() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kxor(a, b);
@@ -57834,7 +57834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kxor_mask16() {
+    const fn test_kxor_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kxor_mask16(a, b);
@@ -57843,7 +57843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_knot() {
+    const fn test_mm512_knot() {
         let a: u16 = 0b11001100_00110011;
         let r = _mm512_knot(a);
         let e: u16 = 0b00110011_11001100;
@@ -57851,7 +57851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_knot_mask16() {
+    const fn test_knot_mask16() {
         let a: u16 = 0b11001100_00110011;
         let r = _knot_mask16(a);
         let e: u16 = 0b00110011_11001100;
@@ -57859,7 +57859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kandn() {
+    const fn test_mm512_kandn() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kandn(a, b);
@@ -57868,7 +57868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kandn_mask16() {
+    const fn test_kandn_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kandn_mask16(a, b);
@@ -57877,7 +57877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kxnor() {
+    const fn test_mm512_kxnor() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kxnor(a, b);
@@ -57886,7 +57886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kxnor_mask16() {
+    const fn test_kxnor_mask16() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _kxnor_mask16(a, b);
@@ -57905,7 +57905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kortestc_mask16_u8() {
+    const fn test_kortestc_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let r = _kortestc_mask16_u8(a, b);
@@ -57913,7 +57913,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kortestz_mask16_u8() {
+    const fn test_kortestz_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let r = _kortestz_mask16_u8(a, b);
@@ -57921,7 +57921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kshiftli_mask16() {
+    const fn test_kshiftli_mask16() {
         let a: __mmask16 = 0b1001011011000011;
         let r = _kshiftli_mask16::<3>(a);
         let e: __mmask16 = 0b1011011000011000;
@@ -57941,7 +57941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kshiftri_mask16() {
+    const fn test_kshiftri_mask16() {
         let a: __mmask16 = 0b1010100100111100;
         let r = _kshiftri_mask16::<3>(a);
         let e: __mmask16 = 0b0001010100100111;
@@ -57978,7 +57978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kmov() {
+    const fn test_mm512_kmov() {
         let a: u16 = 0b11001100_00110011;
         let r = _mm512_kmov(a);
         let e: u16 = 0b11001100_00110011;
@@ -57986,7 +57986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_int2mask() {
+    const fn test_mm512_int2mask() {
         let a: i32 = 0b11001100_00110011;
         let r = _mm512_int2mask(a);
         let e: u16 = 0b11001100_00110011;
@@ -57994,7 +57994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask2int() {
+    const fn test_mm512_mask2int() {
         let k1: __mmask16 = 0b11001100_00110011;
         let r = _mm512_mask2int(k1);
         let e: i32 = 0b11001100_00110011;
@@ -58002,7 +58002,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kunpackb() {
+    const fn test_mm512_kunpackb() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kunpackb(a, b);
@@ -58011,7 +58011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kortestc() {
+    const fn test_mm512_kortestc() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kortestc(a, b);
@@ -58022,7 +58022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_kortestz() {
+    const fn test_mm512_kortestz() {
         let a: u16 = 0b11001100_00110011;
         let b: u16 = 0b00101110_00001011;
         let r = _mm512_kortestz(a, b);
@@ -58032,7 +58032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_test_epi32_mask() {
+    const fn test_mm512_test_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm512_test_epi32_mask(a, b);
@@ -58041,7 +58041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_test_epi32_mask() {
+    const fn test_mm512_mask_test_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi32_mask(0, a, b);
@@ -58052,7 +58052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_test_epi32_mask() {
+    const fn test_mm256_test_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm256_test_epi32_mask(a, b);
@@ -58061,7 +58061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_test_epi32_mask() {
+    const fn test_mm256_mask_test_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi32_mask(0, a, b);
@@ -58072,7 +58072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_test_epi32_mask() {
+    const fn test_mm_test_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm_test_epi32_mask(a, b);
@@ -58081,7 +58081,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_test_epi32_mask() {
+    const fn test_mm_mask_test_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi32_mask(0, a, b);
@@ -58092,7 +58092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_testn_epi32_mask() {
+    const fn test_mm512_testn_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi32_mask(a, b);
@@ -58101,7 +58101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_testn_epi32_mask() {
+    const fn test_mm512_mask_testn_epi32_mask() {
         let a = _mm512_set1_epi32(1 << 0);
         let b = _mm512_set1_epi32(1 << 1);
         let r = _mm512_mask_test_epi32_mask(0, a, b);
@@ -58112,7 +58112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_testn_epi32_mask() {
+    const fn test_mm256_testn_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_testn_epi32_mask(a, b);
@@ -58121,7 +58121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_testn_epi32_mask() {
+    const fn test_mm256_mask_testn_epi32_mask() {
         let a = _mm256_set1_epi32(1 << 0);
         let b = _mm256_set1_epi32(1 << 1);
         let r = _mm256_mask_test_epi32_mask(0, a, b);
@@ -58132,7 +58132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_testn_epi32_mask() {
+    const fn test_mm_testn_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_testn_epi32_mask(a, b);
@@ -58141,7 +58141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_testn_epi32_mask() {
+    const fn test_mm_mask_testn_epi32_mask() {
         let a = _mm_set1_epi32(1 << 0);
         let b = _mm_set1_epi32(1 << 1);
         let r = _mm_mask_test_epi32_mask(0, a, b);
@@ -58210,91 +58210,91 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_add_epi32() {
+    const fn test_mm512_reduce_add_epi32() {
         let a = _mm512_set1_epi32(1);
         let e: i32 = _mm512_reduce_add_epi32(a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_add_epi32() {
+    const fn test_mm512_mask_reduce_add_epi32() {
         let a = _mm512_set1_epi32(1);
         let e: i32 = _mm512_mask_reduce_add_epi32(0b11111111_00000000, a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_add_ps() {
+    const fn test_mm512_reduce_add_ps() {
         let a = _mm512_set1_ps(1.);
         let e: f32 = _mm512_reduce_add_ps(a);
         assert_eq!(16., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_add_ps() {
+    const fn test_mm512_mask_reduce_add_ps() {
         let a = _mm512_set1_ps(1.);
         let e: f32 = _mm512_mask_reduce_add_ps(0b11111111_00000000, a);
         assert_eq!(8., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_mul_epi32() {
+    const fn test_mm512_reduce_mul_epi32() {
         let a = _mm512_set1_epi32(2);
         let e: i32 = _mm512_reduce_mul_epi32(a);
         assert_eq!(65536, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_mul_epi32() {
+    const fn test_mm512_mask_reduce_mul_epi32() {
         let a = _mm512_set1_epi32(2);
         let e: i32 = _mm512_mask_reduce_mul_epi32(0b11111111_00000000, a);
         assert_eq!(256, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_mul_ps() {
+    const fn test_mm512_reduce_mul_ps() {
         let a = _mm512_set1_ps(2.);
         let e: f32 = _mm512_reduce_mul_ps(a);
         assert_eq!(65536., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_mul_ps() {
+    const fn test_mm512_mask_reduce_mul_ps() {
         let a = _mm512_set1_ps(2.);
         let e: f32 = _mm512_mask_reduce_mul_ps(0b11111111_00000000, a);
         assert_eq!(256., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_max_epi32() {
+    const fn test_mm512_reduce_max_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_reduce_max_epi32(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_max_epi32() {
+    const fn test_mm512_mask_reduce_max_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_mask_reduce_max_epi32(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_max_epu32() {
+    const fn test_mm512_reduce_max_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_reduce_max_epu32(a);
         assert_eq!(15, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_max_epu32() {
+    const fn test_mm512_mask_reduce_max_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_mask_reduce_max_epu32(0b11111111_00000000, a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_max_ps() {
+    fn test_mm512_reduce_max_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -58303,7 +58303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_max_ps() {
+    fn test_mm512_mask_reduce_max_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -58312,35 +58312,35 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_min_epi32() {
+    const fn test_mm512_reduce_min_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_reduce_min_epi32(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_min_epi32() {
+    const fn test_mm512_mask_reduce_min_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: i32 = _mm512_mask_reduce_min_epi32(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_min_epu32() {
+    const fn test_mm512_reduce_min_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_reduce_min_epu32(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_min_epu32() {
+    const fn test_mm512_mask_reduce_min_epu32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e: u32 = _mm512_mask_reduce_min_epu32(0b11111111_00000000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_min_ps() {
+    fn test_mm512_reduce_min_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -58349,7 +58349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_min_ps() {
+    fn test_mm512_mask_reduce_min_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -58358,35 +58358,35 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_and_epi32() {
+    const fn test_mm512_reduce_and_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_reduce_and_epi32(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_and_epi32() {
+    const fn test_mm512_mask_reduce_and_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_mask_reduce_and_epi32(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_or_epi32() {
+    const fn test_mm512_reduce_or_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_reduce_or_epi32(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_or_epi32() {
+    const fn test_mm512_mask_reduce_or_epi32() {
         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2);
         let e: i32 = _mm512_mask_reduce_and_epi32(0b11111111_00000000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compress_epi32() {
+    fn test_mm512_mask_compress_epi32() {
         let src = _mm512_set1_epi32(200);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_mask_compress_epi32(src, 0, a);
@@ -58399,7 +58399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_compress_epi32() {
+    fn test_mm512_maskz_compress_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_compress_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -58409,7 +58409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compress_epi32() {
+    fn test_mm256_mask_compress_epi32() {
         let src = _mm256_set1_epi32(200);
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_mask_compress_epi32(src, 0, a);
@@ -58420,7 +58420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_compress_epi32() {
+    fn test_mm256_maskz_compress_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_compress_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -58430,7 +58430,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compress_epi32() {
+    fn test_mm_mask_compress_epi32() {
         let src = _mm_set1_epi32(200);
         let a = _mm_set_epi32(0, 1, 2, 3);
         let r = _mm_mask_compress_epi32(src, 0, a);
@@ -58441,7 +58441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_compress_epi32() {
+    fn test_mm_maskz_compress_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let r = _mm_maskz_compress_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -58451,7 +58451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compress_ps() {
+    fn test_mm512_mask_compress_ps() {
         let src = _mm512_set1_ps(200.);
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -58466,7 +58466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_compress_ps() {
+    fn test_mm512_maskz_compress_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -58480,7 +58480,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compress_ps() {
+    fn test_mm256_mask_compress_ps() {
         let src = _mm256_set1_ps(200.);
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_mask_compress_ps(src, 0, a);
@@ -58491,7 +58491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_compress_ps() {
+    fn test_mm256_maskz_compress_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_maskz_compress_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -58501,7 +58501,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compress_ps() {
+    fn test_mm_mask_compress_ps() {
         let src = _mm_set1_ps(200.);
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_mask_compress_ps(src, 0, a);
@@ -58512,7 +58512,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_compress_ps() {
+    fn test_mm_maskz_compress_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_maskz_compress_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -58667,7 +58667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expand_epi32() {
+    fn test_mm512_maskz_expand_epi32() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_expand_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -58677,7 +58677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expand_epi32() {
+    fn test_mm256_mask_expand_epi32() {
         let src = _mm256_set1_epi32(200);
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_mask_expand_epi32(src, 0, a);
@@ -58688,7 +58688,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expand_epi32() {
+    fn test_mm256_maskz_expand_epi32() {
         let a = _mm256_set_epi32(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm256_maskz_expand_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -58698,7 +58698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expand_epi32() {
+    fn test_mm_mask_expand_epi32() {
         let src = _mm_set1_epi32(200);
         let a = _mm_set_epi32(0, 1, 2, 3);
         let r = _mm_mask_expand_epi32(src, 0, a);
@@ -58709,7 +58709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expand_epi32() {
+    fn test_mm_maskz_expand_epi32() {
         let a = _mm_set_epi32(0, 1, 2, 3);
         let r = _mm_maskz_expand_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -58719,7 +58719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expand_ps() {
+    fn test_mm512_mask_expand_ps() {
         let src = _mm512_set1_ps(200.);
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
@@ -58734,7 +58734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expand_ps() {
+    fn test_mm512_maskz_expand_ps() {
         let a = _mm512_set_ps(
             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
         );
@@ -58748,7 +58748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expand_ps() {
+    fn test_mm256_mask_expand_ps() {
         let src = _mm256_set1_ps(200.);
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_mask_expand_ps(src, 0, a);
@@ -58759,7 +58759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expand_ps() {
+    fn test_mm256_maskz_expand_ps() {
         let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm256_maskz_expand_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -58769,7 +58769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expand_ps() {
+    fn test_mm_mask_expand_ps() {
         let src = _mm_set1_ps(200.);
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_mask_expand_ps(src, 0, a);
@@ -58780,7 +58780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expand_ps() {
+    fn test_mm_maskz_expand_ps() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let r = _mm_maskz_expand_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -59170,7 +59170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_set1_epi32() {
+    const fn test_mm512_mask_set1_epi32() {
         let src = _mm512_set1_epi32(2);
         let a: i32 = 11;
         let r = _mm512_mask_set1_epi32(src, 0, a);
@@ -59181,7 +59181,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_set1_epi32() {
+    const fn test_mm512_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm512_maskz_set1_epi32(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -59191,7 +59191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_set1_epi32() {
+    const fn test_mm256_mask_set1_epi32() {
         let src = _mm256_set1_epi32(2);
         let a: i32 = 11;
         let r = _mm256_mask_set1_epi32(src, 0, a);
@@ -59202,7 +59202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_set1_epi32() {
+    const fn test_mm256_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm256_maskz_set1_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -59212,7 +59212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_set1_epi32() {
+    const fn test_mm_mask_set1_epi32() {
         let src = _mm_set1_epi32(2);
         let a: i32 = 11;
         let r = _mm_mask_set1_epi32(src, 0, a);
@@ -59223,7 +59223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_set1_epi32() {
+    const fn test_mm_maskz_set1_epi32() {
         let a: i32 = 11;
         let r = _mm_maskz_set1_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -59233,7 +59233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_move_ss() {
+    const fn test_mm_mask_move_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -59246,7 +59246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_move_ss() {
+    const fn test_mm_maskz_move_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_move_ss(0, a, b);
@@ -59258,7 +59258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_move_sd() {
+    const fn test_mm_mask_move_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59271,7 +59271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_move_sd() {
+    const fn test_mm_maskz_move_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_move_sd(0, a, b);
@@ -59283,7 +59283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_add_ss() {
+    const fn test_mm_mask_add_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -59296,7 +59296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_add_ss() {
+    const fn test_mm_maskz_add_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_add_ss(0, a, b);
@@ -59308,7 +59308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_add_sd() {
+    const fn test_mm_mask_add_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59321,7 +59321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_add_sd() {
+    const fn test_mm_maskz_add_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_add_sd(0, a, b);
@@ -59333,7 +59333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_sub_ss() {
+    const fn test_mm_mask_sub_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -59346,7 +59346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_sub_ss() {
+    const fn test_mm_maskz_sub_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_sub_ss(0, a, b);
@@ -59358,7 +59358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_sub_sd() {
+    const fn test_mm_mask_sub_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59371,7 +59371,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_sub_sd() {
+    const fn test_mm_maskz_sub_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_sub_sd(0, a, b);
@@ -59383,7 +59383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_mul_ss() {
+    const fn test_mm_mask_mul_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -59396,7 +59396,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_mul_ss() {
+    const fn test_mm_maskz_mul_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_mul_ss(0, a, b);
@@ -59408,7 +59408,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_mul_sd() {
+    const fn test_mm_mask_mul_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59421,7 +59421,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_mul_sd() {
+    const fn test_mm_maskz_mul_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_mul_sd(0, a, b);
@@ -59433,7 +59433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_div_ss() {
+    const fn test_mm_mask_div_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -59446,7 +59446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_div_ss() {
+    const fn test_mm_maskz_div_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_div_ss(0, a, b);
@@ -59458,7 +59458,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_div_sd() {
+    const fn test_mm_mask_div_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59471,7 +59471,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_div_sd() {
+    const fn test_mm_maskz_div_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_div_sd(0, a, b);
@@ -59483,7 +59483,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_max_ss() {
+    fn test_mm_mask_max_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_mask_max_ss(a, 0, a, b);
@@ -59495,7 +59495,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_max_ss() {
+    fn test_mm_maskz_max_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_maskz_max_ss(0, a, b);
@@ -59507,7 +59507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_max_sd() {
+    fn test_mm_mask_max_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_mask_max_sd(a, 0, a, b);
@@ -59519,7 +59519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_max_sd() {
+    fn test_mm_maskz_max_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_maskz_max_sd(0, a, b);
@@ -59531,7 +59531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_min_ss() {
+    fn test_mm_mask_min_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_mask_min_ss(a, 0, a, b);
@@ -59543,7 +59543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_min_ss() {
+    fn test_mm_maskz_min_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_maskz_min_ss(0, a, b);
@@ -59555,7 +59555,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_min_sd() {
+    fn test_mm_mask_min_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_mask_min_sd(a, 0, a, b);
@@ -59567,7 +59567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_min_sd() {
+    fn test_mm_maskz_min_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_maskz_min_sd(0, a, b);
@@ -59579,7 +59579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sqrt_ss() {
+    fn test_mm_mask_sqrt_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
@@ -59592,7 +59592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sqrt_ss() {
+    fn test_mm_maskz_sqrt_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_maskz_sqrt_ss(0, a, b);
@@ -59604,7 +59604,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sqrt_sd() {
+    fn test_mm_mask_sqrt_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59617,7 +59617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sqrt_sd() {
+    fn test_mm_maskz_sqrt_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_sqrt_sd(0, a, b);
@@ -59629,7 +59629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_rsqrt14_ss() {
+    fn test_mm_rsqrt14_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_rsqrt14_ss(a, b);
@@ -59638,7 +59638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_rsqrt14_ss() {
+    fn test_mm_mask_rsqrt14_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
@@ -59651,7 +59651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_rsqrt14_ss() {
+    fn test_mm_maskz_rsqrt14_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_maskz_rsqrt14_ss(0, a, b);
@@ -59663,7 +59663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_rsqrt14_sd() {
+    fn test_mm_rsqrt14_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_rsqrt14_sd(a, b);
@@ -59672,7 +59672,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_rsqrt14_sd() {
+    fn test_mm_mask_rsqrt14_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59685,7 +59685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_rsqrt14_sd() {
+    fn test_mm_maskz_rsqrt14_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_rsqrt14_sd(0, a, b);
@@ -59697,7 +59697,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_rcp14_ss() {
+    fn test_mm_rcp14_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_rcp14_ss(a, b);
@@ -59706,7 +59706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_rcp14_ss() {
+    fn test_mm_mask_rcp14_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
@@ -59719,7 +59719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_rcp14_ss() {
+    fn test_mm_maskz_rcp14_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_maskz_rcp14_ss(0, a, b);
@@ -59731,7 +59731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_rcp14_sd() {
+    fn test_mm_rcp14_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_rcp14_sd(a, b);
@@ -59740,7 +59740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_rcp14_sd() {
+    fn test_mm_mask_rcp14_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -59753,7 +59753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_rcp14_sd() {
+    fn test_mm_maskz_rcp14_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_rcp14_sd(0, a, b);
@@ -59765,7 +59765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getexp_ss() {
+    fn test_mm_getexp_ss() {
         let a = _mm_set1_ps(2.);
         let b = _mm_set1_ps(3.);
         let r = _mm_getexp_ss(a, b);
@@ -59774,7 +59774,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getexp_ss() {
+    fn test_mm_mask_getexp_ss() {
         let a = _mm_set1_ps(2.);
         let b = _mm_set1_ps(3.);
         let r = _mm_mask_getexp_ss(a, 0, a, b);
@@ -59786,7 +59786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getexp_ss() {
+    fn test_mm_maskz_getexp_ss() {
         let a = _mm_set1_ps(2.);
         let b = _mm_set1_ps(3.);
         let r = _mm_maskz_getexp_ss(0, a, b);
@@ -59798,7 +59798,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getexp_sd() {
+    fn test_mm_getexp_sd() {
         let a = _mm_set1_pd(2.);
         let b = _mm_set1_pd(3.);
         let r = _mm_getexp_sd(a, b);
@@ -59807,7 +59807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getexp_sd() {
+    fn test_mm_mask_getexp_sd() {
         let a = _mm_set1_pd(2.);
         let b = _mm_set1_pd(3.);
         let r = _mm_mask_getexp_sd(a, 0, a, b);
@@ -59819,7 +59819,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getexp_sd() {
+    fn test_mm_maskz_getexp_sd() {
         let a = _mm_set1_pd(2.);
         let b = _mm_set1_pd(3.);
         let r = _mm_maskz_getexp_sd(0, a, b);
@@ -59831,7 +59831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getmant_ss() {
+    fn test_mm_getmant_ss() {
         let a = _mm_set1_ps(20.);
         let b = _mm_set1_ps(10.);
         let r = _mm_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, b);
@@ -59840,7 +59840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getmant_ss() {
+    fn test_mm_mask_getmant_ss() {
         let a = _mm_set1_ps(20.);
         let b = _mm_set1_ps(10.);
         let r = _mm_mask_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a, b);
@@ -59852,7 +59852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getmant_ss() {
+    fn test_mm_maskz_getmant_ss() {
         let a = _mm_set1_ps(20.);
         let b = _mm_set1_ps(10.);
         let r = _mm_maskz_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a, b);
@@ -59864,7 +59864,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getmant_sd() {
+    fn test_mm_getmant_sd() {
         let a = _mm_set1_pd(20.);
         let b = _mm_set1_pd(10.);
         let r = _mm_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, b);
@@ -59873,7 +59873,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getmant_sd() {
+    fn test_mm_mask_getmant_sd() {
         let a = _mm_set1_pd(20.);
         let b = _mm_set1_pd(10.);
         let r = _mm_mask_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a, b);
@@ -59885,7 +59885,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getmant_sd() {
+    fn test_mm_maskz_getmant_sd() {
         let a = _mm_set1_pd(20.);
         let b = _mm_set1_pd(10.);
         let r = _mm_maskz_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a, b);
@@ -59897,7 +59897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_roundscale_ss() {
+    fn test_mm_roundscale_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_roundscale_ss::<0>(a, b);
@@ -59906,7 +59906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_roundscale_ss() {
+    fn test_mm_mask_roundscale_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_mask_roundscale_ss::<0>(a, 0, a, b);
@@ -59918,7 +59918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_roundscale_ss() {
+    fn test_mm_maskz_roundscale_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_maskz_roundscale_ss::<0>(0, a, b);
@@ -59930,7 +59930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_roundscale_sd() {
+    fn test_mm_roundscale_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_roundscale_sd::<0>(a, b);
@@ -59939,7 +59939,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_roundscale_sd() {
+    fn test_mm_mask_roundscale_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_mask_roundscale_sd::<0>(a, 0, a, b);
@@ -59951,7 +59951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_roundscale_sd() {
+    fn test_mm_maskz_roundscale_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_maskz_roundscale_sd::<0>(0, a, b);
@@ -59963,7 +59963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_scalef_ss() {
+    fn test_mm_scalef_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_scalef_ss(a, b);
@@ -59972,7 +59972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_scalef_ss() {
+    fn test_mm_mask_scalef_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_mask_scalef_ss(a, 0, a, b);
@@ -59984,7 +59984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_scalef_ss() {
+    fn test_mm_maskz_scalef_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_maskz_scalef_ss(0, a, b);
@@ -59996,7 +59996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_scalef_sd() {
+    fn test_mm_scalef_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_scalef_sd(a, b);
@@ -60005,7 +60005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_scalef_sd() {
+    fn test_mm_mask_scalef_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_mask_scalef_sd(a, 0, a, b);
@@ -60017,7 +60017,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_scalef_sd() {
+    fn test_mm_maskz_scalef_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_maskz_scalef_sd(0, a, b);
@@ -60029,7 +60029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fmadd_ss() {
+    const fn test_mm_mask_fmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60041,7 +60041,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fmadd_ss() {
+    const fn test_mm_maskz_fmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60054,7 +60054,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fmadd_ss() {
+    const fn test_mm_mask3_fmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60066,7 +60066,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fmadd_sd() {
+    const fn test_mm_mask_fmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60078,7 +60078,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fmadd_sd() {
+    const fn test_mm_maskz_fmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60091,7 +60091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fmadd_sd() {
+    const fn test_mm_mask3_fmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60103,7 +60103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fmsub_ss() {
+    const fn test_mm_mask_fmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60115,7 +60115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fmsub_ss() {
+    const fn test_mm_maskz_fmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60128,7 +60128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fmsub_ss() {
+    const fn test_mm_mask3_fmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60140,7 +60140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fmsub_sd() {
+    const fn test_mm_mask_fmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60152,7 +60152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fmsub_sd() {
+    const fn test_mm_maskz_fmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60165,7 +60165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fmsub_sd() {
+    const fn test_mm_mask3_fmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60177,7 +60177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fnmadd_ss() {
+    const fn test_mm_mask_fnmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60189,7 +60189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fnmadd_ss() {
+    const fn test_mm_maskz_fnmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60202,7 +60202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fnmadd_ss() {
+    const fn test_mm_mask3_fnmadd_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60214,7 +60214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fnmadd_sd() {
+    const fn test_mm_mask_fnmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60226,7 +60226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fnmadd_sd() {
+    const fn test_mm_maskz_fnmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60239,7 +60239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fnmadd_sd() {
+    const fn test_mm_mask3_fnmadd_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60251,7 +60251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fnmsub_ss() {
+    const fn test_mm_mask_fnmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60263,7 +60263,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fnmsub_ss() {
+    const fn test_mm_maskz_fnmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60276,7 +60276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fnmsub_ss() {
+    const fn test_mm_mask3_fnmsub_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -60288,7 +60288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask_fnmsub_sd() {
+    const fn test_mm_mask_fnmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60300,7 +60300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_maskz_fnmsub_sd() {
+    const fn test_mm_maskz_fnmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60313,7 +60313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_mask3_fnmsub_sd() {
+    const fn test_mm_mask3_fnmsub_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -60325,7 +60325,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_add_round_ss() {
+    fn test_mm_add_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_add_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60334,7 +60334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_add_round_ss() {
+    fn test_mm_mask_add_round_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -60349,7 +60349,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_add_round_ss() {
+    fn test_mm_maskz_add_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_add_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60362,7 +60362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_add_round_sd() {
+    fn test_mm_add_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_add_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60371,7 +60371,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_add_round_sd() {
+    fn test_mm_mask_add_round_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -60386,7 +60386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_add_round_sd() {
+    fn test_mm_maskz_add_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_add_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60399,7 +60399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_sub_round_ss() {
+    fn test_mm_sub_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_sub_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60408,7 +60408,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sub_round_ss() {
+    fn test_mm_mask_sub_round_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -60423,7 +60423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sub_round_ss() {
+    fn test_mm_maskz_sub_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_sub_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60436,7 +60436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_sub_round_sd() {
+    fn test_mm_sub_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_sub_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60445,7 +60445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sub_round_sd() {
+    fn test_mm_mask_sub_round_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -60460,7 +60460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sub_round_sd() {
+    fn test_mm_maskz_sub_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_sub_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60473,7 +60473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mul_round_ss() {
+    fn test_mm_mul_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_mul_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60482,7 +60482,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_mul_round_ss() {
+    fn test_mm_mask_mul_round_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -60497,7 +60497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_mul_round_ss() {
+    fn test_mm_maskz_mul_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_mul_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60510,7 +60510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mul_round_sd() {
+    fn test_mm_mul_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_mul_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60519,7 +60519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_mul_round_sd() {
+    fn test_mm_mask_mul_round_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -60534,7 +60534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_mul_round_sd() {
+    fn test_mm_maskz_mul_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_mul_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60547,7 +60547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_div_round_ss() {
+    fn test_mm_div_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_div_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60556,7 +60556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_div_round_ss() {
+    fn test_mm_mask_div_round_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
@@ -60571,7 +60571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_div_round_ss() {
+    fn test_mm_maskz_div_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 40.);
         let r = _mm_maskz_div_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60584,7 +60584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_div_round_sd() {
+    fn test_mm_div_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_div_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60593,7 +60593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_div_round_sd() {
+    fn test_mm_mask_div_round_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -60608,7 +60608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_div_round_sd() {
+    fn test_mm_maskz_div_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_div_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60621,7 +60621,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_max_round_ss() {
+    fn test_mm_max_round_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_max_round_ss::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -60630,7 +60630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_max_round_ss() {
+    fn test_mm_mask_max_round_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_mask_max_round_ss::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -60642,7 +60642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_max_round_ss() {
+    fn test_mm_maskz_max_round_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_maskz_max_round_ss::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -60654,7 +60654,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_max_round_sd() {
+    fn test_mm_max_round_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_max_round_sd::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -60663,7 +60663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_max_round_sd() {
+    fn test_mm_mask_max_round_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_mask_max_round_sd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -60675,7 +60675,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_max_round_sd() {
+    fn test_mm_maskz_max_round_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_maskz_max_round_sd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -60687,7 +60687,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_min_round_ss() {
+    fn test_mm_min_round_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_min_round_ss::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -60696,7 +60696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_min_round_ss() {
+    fn test_mm_mask_min_round_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_mask_min_round_ss::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -60708,7 +60708,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_min_round_ss() {
+    fn test_mm_maskz_min_round_ss() {
         let a = _mm_set_ps(0., 1., 2., 3.);
         let b = _mm_set_ps(4., 5., 6., 7.);
         let r = _mm_maskz_min_round_ss::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -60720,7 +60720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_min_round_sd() {
+    fn test_mm_min_round_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_min_round_sd::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -60729,7 +60729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_min_round_sd() {
+    fn test_mm_mask_min_round_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_mask_min_round_sd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -60741,7 +60741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_min_round_sd() {
+    fn test_mm_maskz_min_round_sd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_maskz_min_round_sd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -60753,7 +60753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_sqrt_round_ss() {
+    fn test_mm_sqrt_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_sqrt_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60762,7 +60762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sqrt_round_ss() {
+    fn test_mm_mask_sqrt_round_ss() {
         let src = _mm_set_ps(10., 11., 100., 110.);
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
@@ -60777,7 +60777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sqrt_round_ss() {
+    fn test_mm_maskz_sqrt_round_ss() {
         let a = _mm_set_ps(1., 2., 10., 20.);
         let b = _mm_set_ps(3., 4., 30., 4.);
         let r = _mm_maskz_sqrt_round_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60790,7 +60790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_sqrt_round_sd() {
+    fn test_mm_sqrt_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_sqrt_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -60799,7 +60799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_sqrt_round_sd() {
+    fn test_mm_mask_sqrt_round_sd() {
         let src = _mm_set_pd(10., 11.);
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
@@ -60814,7 +60814,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_sqrt_round_sd() {
+    fn test_mm_maskz_sqrt_round_sd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(3., 4.);
         let r = _mm_maskz_sqrt_round_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -60827,7 +60827,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getexp_round_ss() {
+    fn test_mm_getexp_round_ss() {
         let a = _mm_set1_ps(2.);
         let b = _mm_set1_ps(3.);
         let r = _mm_getexp_round_ss::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -60836,7 +60836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getexp_round_ss() {
+    fn test_mm_mask_getexp_round_ss() {
         let a = _mm_set1_ps(2.);
         let b = _mm_set1_ps(3.);
         let r = _mm_mask_getexp_round_ss::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -60848,7 +60848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getexp_round_ss() {
+    fn test_mm_maskz_getexp_round_ss() {
         let a = _mm_set1_ps(2.);
         let b = _mm_set1_ps(3.);
         let r = _mm_maskz_getexp_round_ss::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -60860,7 +60860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getexp_round_sd() {
+    fn test_mm_getexp_round_sd() {
         let a = _mm_set1_pd(2.);
         let b = _mm_set1_pd(3.);
         let r = _mm_getexp_round_sd::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -60869,7 +60869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getexp_round_sd() {
+    fn test_mm_mask_getexp_round_sd() {
         let a = _mm_set1_pd(2.);
         let b = _mm_set1_pd(3.);
         let r = _mm_mask_getexp_round_sd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -60881,7 +60881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getexp_round_sd() {
+    fn test_mm_maskz_getexp_round_sd() {
         let a = _mm_set1_pd(2.);
         let b = _mm_set1_pd(3.);
         let r = _mm_maskz_getexp_round_sd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -60893,7 +60893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getmant_round_ss() {
+    fn test_mm_getmant_round_ss() {
         let a = _mm_set1_ps(20.);
         let b = _mm_set1_ps(10.);
         let r =
@@ -60905,7 +60905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getmant_round_ss() {
+    fn test_mm_mask_getmant_round_ss() {
         let a = _mm_set1_ps(20.);
         let b = _mm_set1_ps(10.);
         let r = _mm_mask_getmant_round_ss::<
@@ -60925,7 +60925,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getmant_round_ss() {
+    fn test_mm_maskz_getmant_round_ss() {
         let a = _mm_set1_ps(20.);
         let b = _mm_set1_ps(10.);
         let r = _mm_maskz_getmant_round_ss::<
@@ -60945,7 +60945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_getmant_round_sd() {
+    fn test_mm_getmant_round_sd() {
         let a = _mm_set1_pd(20.);
         let b = _mm_set1_pd(10.);
         let r =
@@ -60957,7 +60957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_getmant_round_sd() {
+    fn test_mm_mask_getmant_round_sd() {
         let a = _mm_set1_pd(20.);
         let b = _mm_set1_pd(10.);
         let r = _mm_mask_getmant_round_sd::<
@@ -60977,7 +60977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_getmant_round_sd() {
+    fn test_mm_maskz_getmant_round_sd() {
         let a = _mm_set1_pd(20.);
         let b = _mm_set1_pd(10.);
         let r = _mm_maskz_getmant_round_sd::<
@@ -60997,7 +60997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_roundscale_round_ss() {
+    fn test_mm_roundscale_round_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, b);
@@ -61006,7 +61006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_roundscale_round_ss() {
+    fn test_mm_mask_roundscale_round_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_mask_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -61018,7 +61018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_roundscale_round_ss() {
+    fn test_mm_maskz_roundscale_round_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_maskz_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -61030,7 +61030,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_roundscale_round_sd() {
+    fn test_mm_roundscale_round_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, b);
@@ -61039,7 +61039,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_roundscale_round_sd() {
+    fn test_mm_mask_roundscale_round_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_mask_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -61051,7 +61051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_roundscale_round_sd() {
+    fn test_mm_maskz_roundscale_round_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_maskz_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -61063,7 +61063,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_scalef_round_ss() {
+    fn test_mm_scalef_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_scalef_round_ss::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -61072,7 +61072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_scalef_round_ss() {
+    fn test_mm_mask_scalef_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r = _mm_mask_scalef_round_ss::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -61088,7 +61088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_scalef_round_ss() {
+    fn test_mm_maskz_scalef_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(3.);
         let r =
@@ -61103,7 +61103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_scalef_round_sd() {
+    fn test_mm_scalef_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_scalef_round_sd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -61112,7 +61112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_scalef_round_sd() {
+    fn test_mm_mask_scalef_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_mask_scalef_round_sd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -61128,7 +61128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_scalef_round_sd() {
+    fn test_mm_maskz_scalef_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r =
@@ -61143,7 +61143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fmadd_round_ss() {
+    fn test_mm_fmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61153,7 +61153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmadd_round_ss() {
+    fn test_mm_mask_fmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61169,7 +61169,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmadd_round_ss() {
+    fn test_mm_maskz_fmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61186,7 +61186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmadd_round_ss() {
+    fn test_mm_mask3_fmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61202,7 +61202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fmadd_round_sd() {
+    fn test_mm_fmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61212,7 +61212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmadd_round_sd() {
+    fn test_mm_mask_fmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61228,7 +61228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmadd_round_sd() {
+    fn test_mm_maskz_fmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61245,7 +61245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmadd_round_sd() {
+    fn test_mm_mask3_fmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61261,7 +61261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fmsub_round_ss() {
+    fn test_mm_fmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61271,7 +61271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmsub_round_ss() {
+    fn test_mm_mask_fmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61287,7 +61287,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmsub_round_ss() {
+    fn test_mm_maskz_fmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61304,7 +61304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmsub_round_ss() {
+    fn test_mm_mask3_fmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61320,7 +61320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fmsub_round_sd() {
+    fn test_mm_fmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61330,7 +61330,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fmsub_round_sd() {
+    fn test_mm_mask_fmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61346,7 +61346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fmsub_round_sd() {
+    fn test_mm_maskz_fmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61363,7 +61363,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fmsub_round_sd() {
+    fn test_mm_mask3_fmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61379,7 +61379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fnmadd_round_ss() {
+    fn test_mm_fnmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61389,7 +61389,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmadd_round_ss() {
+    fn test_mm_mask_fnmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61405,7 +61405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmadd_round_ss() {
+    fn test_mm_maskz_fnmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61422,7 +61422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmadd_round_ss() {
+    fn test_mm_mask3_fnmadd_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61438,7 +61438,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fnmadd_round_sd() {
+    fn test_mm_fnmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61448,7 +61448,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmadd_round_sd() {
+    fn test_mm_mask_fnmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61464,7 +61464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmadd_round_sd() {
+    fn test_mm_maskz_fnmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61481,7 +61481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmadd_round_sd() {
+    fn test_mm_mask3_fnmadd_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61497,7 +61497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fnmsub_round_ss() {
+    fn test_mm_fnmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61507,7 +61507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmsub_round_ss() {
+    fn test_mm_mask_fnmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61523,7 +61523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmsub_round_ss() {
+    fn test_mm_maskz_fnmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61540,7 +61540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmsub_round_ss() {
+    fn test_mm_mask3_fnmsub_round_ss() {
         let a = _mm_set1_ps(1.);
         let b = _mm_set1_ps(2.);
         let c = _mm_set1_ps(3.);
@@ -61556,7 +61556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fnmsub_round_sd() {
+    fn test_mm_fnmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61566,7 +61566,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fnmsub_round_sd() {
+    fn test_mm_mask_fnmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61582,7 +61582,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fnmsub_round_sd() {
+    fn test_mm_maskz_fnmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61599,7 +61599,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask3_fnmsub_round_sd() {
+    fn test_mm_mask3_fnmsub_round_sd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let c = _mm_set1_pd(3.);
@@ -61615,7 +61615,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fixupimm_ss() {
+    fn test_mm_fixupimm_ss() {
         let a = _mm_set_ps(0., 0., 0., f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -61625,7 +61625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fixupimm_ss() {
+    fn test_mm_mask_fixupimm_ss() {
         let a = _mm_set_ps(0., 0., 0., f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -61635,7 +61635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fixupimm_ss() {
+    fn test_mm_maskz_fixupimm_ss() {
         let a = _mm_set_ps(0., 0., 0., f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -61648,7 +61648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fixupimm_sd() {
+    fn test_mm_fixupimm_sd() {
         let a = _mm_set_pd(0., f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -61658,7 +61658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fixupimm_sd() {
+    fn test_mm_mask_fixupimm_sd() {
         let a = _mm_set_pd(0., f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -61668,7 +61668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fixupimm_sd() {
+    fn test_mm_maskz_fixupimm_sd() {
         let a = _mm_set_pd(0., f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -61681,7 +61681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fixupimm_round_ss() {
+    fn test_mm_fixupimm_round_ss() {
         let a = _mm_set_ps(1., 0., 0., f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -61691,7 +61691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fixupimm_round_ss() {
+    fn test_mm_mask_fixupimm_round_ss() {
         let a = _mm_set_ps(0., 0., 0., f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -61701,7 +61701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fixupimm_round_ss() {
+    fn test_mm_maskz_fixupimm_round_ss() {
         let a = _mm_set_ps(0., 0., 0., f32::NAN);
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
@@ -61714,7 +61714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_fixupimm_round_sd() {
+    fn test_mm_fixupimm_round_sd() {
         let a = _mm_set_pd(0., f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -61724,7 +61724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_fixupimm_round_sd() {
+    fn test_mm_mask_fixupimm_round_sd() {
         let a = _mm_set_pd(0., f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -61734,7 +61734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_fixupimm_round_sd() {
+    fn test_mm_maskz_fixupimm_round_sd() {
         let a = _mm_set_pd(0., f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -61747,7 +61747,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cvtss_sd() {
+    fn test_mm_mask_cvtss_sd() {
         let a = _mm_set_pd(6., -7.5);
         let b = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_mask_cvtss_sd(a, 0, a, b);
@@ -61758,7 +61758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_cvtss_sd() {
+    fn test_mm_maskz_cvtss_sd() {
         let a = _mm_set_pd(6., -7.5);
         let b = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_maskz_cvtss_sd(0, a, b);
@@ -61770,7 +61770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cvtsd_ss() {
+    fn test_mm_mask_cvtsd_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b = _mm_set_pd(6., -7.5);
         let r = _mm_mask_cvtsd_ss(a, 0, a, b);
@@ -61781,7 +61781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_cvtsd_ss() {
+    fn test_mm_maskz_cvtsd_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b = _mm_set_pd(6., -7.5);
         let r = _mm_maskz_cvtsd_ss(0, a, b);
@@ -61793,7 +61793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_sd() {
+    fn test_mm_cvt_roundss_sd() {
         let a = _mm_set_pd(6., -7.5);
         let b = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_sd::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -61802,7 +61802,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cvt_roundss_sd() {
+    fn test_mm_mask_cvt_roundss_sd() {
         let a = _mm_set_pd(6., -7.5);
         let b = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_mask_cvt_roundss_sd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -61813,7 +61813,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_cvt_roundss_sd() {
+    fn test_mm_maskz_cvt_roundss_sd() {
         let a = _mm_set_pd(6., -7.5);
         let b = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_maskz_cvt_roundss_sd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -61825,7 +61825,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_ss() {
+    fn test_mm_cvt_roundsd_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b = _mm_set_pd(6., -7.5);
         let r = _mm_cvt_roundsd_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -61834,7 +61834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_cvt_roundsd_ss() {
+    fn test_mm_mask_cvt_roundsd_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b = _mm_set_pd(6., -7.5);
         let r = _mm_mask_cvt_roundsd_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, 0, a, b);
@@ -61847,7 +61847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_cvt_roundsd_ss() {
+    fn test_mm_maskz_cvt_roundsd_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b = _mm_set_pd(6., -7.5);
         let r = _mm_maskz_cvt_roundsd_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(0, a, b);
@@ -61861,7 +61861,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_si32() {
+    fn test_mm_cvt_roundss_si32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_si32::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i32 = -1;
@@ -61869,7 +61869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_i32() {
+    fn test_mm_cvt_roundss_i32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_i32::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i32 = -1;
@@ -61877,7 +61877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_u32() {
+    fn test_mm_cvt_roundss_u32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_u32::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: u32 = u32::MAX;
@@ -61885,7 +61885,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtss_i32() {
+    fn test_mm_cvtss_i32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtss_i32(a);
         let e: i32 = -2;
@@ -61893,7 +61893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtss_u32() {
+    fn test_mm_cvtss_u32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtss_u32(a);
         let e: u32 = u32::MAX;
@@ -61901,7 +61901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_si32() {
+    fn test_mm_cvt_roundsd_si32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvt_roundsd_si32::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i32 = -1;
@@ -61909,7 +61909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_i32() {
+    fn test_mm_cvt_roundsd_i32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvt_roundsd_i32::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i32 = -1;
@@ -61917,7 +61917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_u32() {
+    fn test_mm_cvt_roundsd_u32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvt_roundsd_u32::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: u32 = u32::MAX;
@@ -61925,7 +61925,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtsd_i32() {
+    fn test_mm_cvtsd_i32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtsd_i32(a);
         let e: i32 = -2;
@@ -61933,7 +61933,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtsd_u32() {
+    fn test_mm_cvtsd_u32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtsd_u32(a);
         let e: u32 = u32::MAX;
@@ -61941,7 +61941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundi32_ss() {
+    fn test_mm_cvt_roundi32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i32 = 9;
         let r = _mm_cvt_roundi32_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -61950,7 +61950,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsi32_ss() {
+    fn test_mm_cvt_roundsi32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i32 = 9;
         let r = _mm_cvt_roundsi32_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -61959,7 +61959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundu32_ss() {
+    fn test_mm_cvt_roundu32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: u32 = 9;
         let r = _mm_cvt_roundu32_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -61968,7 +61968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvti32_ss() {
+    const fn test_mm_cvti32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i32 = 9;
         let r = _mm_cvti32_ss(a, b);
@@ -61977,7 +61977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvti32_sd() {
+    const fn test_mm_cvti32_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: i32 = 9;
         let r = _mm_cvti32_sd(a, b);
@@ -61986,7 +61986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundss_si32() {
+    fn test_mm_cvtt_roundss_si32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtt_roundss_si32::<_MM_FROUND_NO_EXC>(a);
         let e: i32 = -1;
@@ -61994,7 +61994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundss_i32() {
+    fn test_mm_cvtt_roundss_i32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtt_roundss_i32::<_MM_FROUND_NO_EXC>(a);
         let e: i32 = -1;
@@ -62002,7 +62002,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundss_u32() {
+    fn test_mm_cvtt_roundss_u32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtt_roundss_u32::<_MM_FROUND_NO_EXC>(a);
         let e: u32 = u32::MAX;
@@ -62010,7 +62010,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttss_i32() {
+    fn test_mm_cvttss_i32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvttss_i32(a);
         let e: i32 = -1;
@@ -62018,7 +62018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttss_u32() {
+    fn test_mm_cvttss_u32() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvttss_u32(a);
         let e: u32 = u32::MAX;
@@ -62026,7 +62026,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundsd_si32() {
+    fn test_mm_cvtt_roundsd_si32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtt_roundsd_si32::<_MM_FROUND_NO_EXC>(a);
         let e: i32 = -1;
@@ -62034,7 +62034,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundsd_i32() {
+    fn test_mm_cvtt_roundsd_i32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtt_roundsd_i32::<_MM_FROUND_NO_EXC>(a);
         let e: i32 = -1;
@@ -62042,7 +62042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundsd_u32() {
+    fn test_mm_cvtt_roundsd_u32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtt_roundsd_u32::<_MM_FROUND_NO_EXC>(a);
         let e: u32 = u32::MAX;
@@ -62050,7 +62050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttsd_i32() {
+    fn test_mm_cvttsd_i32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvttsd_i32(a);
         let e: i32 = -1;
@@ -62058,7 +62058,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttsd_u32() {
+    fn test_mm_cvttsd_u32() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvttsd_u32(a);
         let e: u32 = u32::MAX;
@@ -62066,7 +62066,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvtu32_ss() {
+    const fn test_mm_cvtu32_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: u32 = 9;
         let r = _mm_cvtu32_ss(a, b);
@@ -62075,7 +62075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvtu32_sd() {
+    const fn test_mm_cvtu32_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: u32 = 9;
         let r = _mm_cvtu32_sd(a, b);
@@ -62084,7 +62084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_comi_round_ss() {
+    fn test_mm_comi_round_ss() {
         let a = _mm_set1_ps(2.2);
         let b = _mm_set1_ps(1.1);
         let r = _mm_comi_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, b);
@@ -62093,7 +62093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_comi_round_sd() {
+    fn test_mm_comi_round_sd() {
         let a = _mm_set1_pd(2.2);
         let b = _mm_set1_pd(1.1);
         let r = _mm_comi_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, b);
@@ -62102,7 +62102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtsi512_si32() {
+    const fn test_mm512_cvtsi512_si32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvtsi512_si32(a);
         let e: i32 = 1;
@@ -62110,7 +62110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtss_f32() {
+    const fn test_mm512_cvtss_f32() {
         let a = _mm512_setr_ps(
             312.0134, 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         );
@@ -62118,13 +62118,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtsd_f64() {
+    const fn test_mm512_cvtsd_f64() {
         let r = _mm512_cvtsd_f64(_mm512_setr_pd(-1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8));
         assert_eq!(r, -1.1);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_pd() {
+    const fn test_mm512_shuffle_pd() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
         let r = _mm512_shuffle_pd::<0b11_11_11_11>(a, b);
@@ -62133,7 +62133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_pd() {
+    const fn test_mm512_mask_shuffle_pd() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
         let r = _mm512_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
@@ -62144,7 +62144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_pd() {
+    const fn test_mm512_maskz_shuffle_pd() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
         let r = _mm512_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index de058c3073..7e0d7e1c0b 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -16960,14 +16960,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_set_ph() {
+    const fn test_mm_set_ph() {
         let r = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let e = _mm_setr_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_set_ph() {
+    const fn test_mm256_set_ph() {
         let r = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -16978,7 +16978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_set_ph() {
+    const fn test_mm512_set_ph() {
         let r = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -16993,21 +16993,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_set_sh() {
+    const fn test_mm_set_sh() {
         let r = _mm_set_sh(1.0);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_set1_ph() {
+    const fn test_mm_set1_ph() {
         let r = _mm_set1_ph(1.0);
         let e = _mm_set_ph(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_set1_ph() {
+    const fn test_mm256_set1_ph() {
         let r = _mm256_set1_ph(1.0);
         let e = _mm256_set_ph(
             1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
@@ -17016,7 +17016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_set1_ph() {
+    const fn test_mm512_set1_ph() {
         let r = _mm512_set1_ph(1.0);
         let e = _mm512_set_ph(
             1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0,
@@ -17026,14 +17026,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_setr_ph() {
+    const fn test_mm_setr_ph() {
         let r = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let e = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_setr_ph() {
+    const fn test_mm256_setr_ph() {
         let r = _mm256_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17044,7 +17044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_setr_ph() {
+    const fn test_mm512_setr_ph() {
         let r = _mm512_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17059,28 +17059,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_setzero_ph() {
+    const fn test_mm_setzero_ph() {
         let r = _mm_setzero_ph();
         let e = _mm_set1_ph(0.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_setzero_ph() {
+    const fn test_mm256_setzero_ph() {
         let r = _mm256_setzero_ph();
         let e = _mm256_set1_ph(0.0);
         assert_eq_m256h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_setzero_ph() {
+    const fn test_mm512_setzero_ph() {
         let r = _mm512_setzero_ph();
         let e = _mm512_set1_ph(0.0);
         assert_eq_m512h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_castsi128_ph() {
+    const fn test_mm_castsi128_ph() {
         let a = _mm_set1_epi16(0x3c00);
         let r = _mm_castsi128_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -17088,7 +17088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_castsi256_ph() {
+    const fn test_mm256_castsi256_ph() {
         let a = _mm256_set1_epi16(0x3c00);
         let r = _mm256_castsi256_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -17096,7 +17096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_castsi512_ph() {
+    const fn test_mm512_castsi512_ph() {
         let a = _mm512_set1_epi16(0x3c00);
         let r = _mm512_castsi512_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -17104,7 +17104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm_castph_si128() {
+    const fn test_mm_castph_si128() {
         let a = _mm_set1_ph(1.0);
         let r = _mm_castph_si128(a);
         let e = _mm_set1_epi16(0x3c00);
@@ -17112,7 +17112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm256_castph_si256() {
+    const fn test_mm256_castph_si256() {
         let a = _mm256_set1_ph(1.0);
         let r = _mm256_castph_si256(a);
         let e = _mm256_set1_epi16(0x3c00);
@@ -17120,7 +17120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_castph_si512() {
+    const fn test_mm512_castph_si512() {
         let a = _mm512_set1_ph(1.0);
         let r = _mm512_castph_si512(a);
         let e = _mm512_set1_epi16(0x3c00);
@@ -17128,7 +17128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_castps_ph() {
+    const fn test_mm_castps_ph() {
         let a = _mm_castsi128_ps(_mm_set1_epi16(0x3c00));
         let r = _mm_castps_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -17136,7 +17136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_castps_ph() {
+    const fn test_mm256_castps_ph() {
         let a = _mm256_castsi256_ps(_mm256_set1_epi16(0x3c00));
         let r = _mm256_castps_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -17144,7 +17144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_castps_ph() {
+    const fn test_mm512_castps_ph() {
         let a = _mm512_castsi512_ps(_mm512_set1_epi16(0x3c00));
         let r = _mm512_castps_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -17152,7 +17152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm_castph_ps() {
+    const fn test_mm_castph_ps() {
         let a = _mm_castsi128_ph(_mm_set1_epi32(0x3f800000));
         let r = _mm_castph_ps(a);
         let e = _mm_set1_ps(1.0);
@@ -17160,7 +17160,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm256_castph_ps() {
+    const fn test_mm256_castph_ps() {
         let a = _mm256_castsi256_ph(_mm256_set1_epi32(0x3f800000));
         let r = _mm256_castph_ps(a);
         let e = _mm256_set1_ps(1.0);
@@ -17168,7 +17168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_castph_ps() {
+    const fn test_mm512_castph_ps() {
         let a = _mm512_castsi512_ph(_mm512_set1_epi32(0x3f800000));
         let r = _mm512_castph_ps(a);
         let e = _mm512_set1_ps(1.0);
@@ -17176,7 +17176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_castpd_ph() {
+    const fn test_mm_castpd_ph() {
         let a = _mm_castsi128_pd(_mm_set1_epi16(0x3c00));
         let r = _mm_castpd_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -17184,7 +17184,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_castpd_ph() {
+    const fn test_mm256_castpd_ph() {
         let a = _mm256_castsi256_pd(_mm256_set1_epi16(0x3c00));
         let r = _mm256_castpd_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -17192,7 +17192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_castpd_ph() {
+    const fn test_mm512_castpd_ph() {
         let a = _mm512_castsi512_pd(_mm512_set1_epi16(0x3c00));
         let r = _mm512_castpd_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -17200,7 +17200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm_castph_pd() {
+    const fn test_mm_castph_pd() {
         let a = _mm_castsi128_ph(_mm_set1_epi64x(0x3ff0000000000000));
         let r = _mm_castph_pd(a);
         let e = _mm_set1_pd(1.0);
@@ -17208,7 +17208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm256_castph_pd() {
+    const fn test_mm256_castph_pd() {
         let a = _mm256_castsi256_ph(_mm256_set1_epi64x(0x3ff0000000000000));
         let r = _mm256_castph_pd(a);
         let e = _mm256_set1_pd(1.0);
@@ -17216,7 +17216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_castph_pd() {
+    const fn test_mm512_castph_pd() {
         let a = _mm512_castsi512_ph(_mm512_set1_epi64(0x3ff0000000000000));
         let r = _mm512_castph_pd(a);
         let e = _mm512_set1_pd(1.0);
@@ -17224,7 +17224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_castph256_ph128() {
+    const fn test_mm256_castph256_ph128() {
         let a = _mm256_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -17234,7 +17234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm512_castph512_ph128() {
+    const fn test_mm512_castph512_ph128() {
         let a = _mm512_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19.,
             20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
@@ -17245,7 +17245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm512_castph512_ph256() {
+    const fn test_mm512_castph512_ph256() {
         let a = _mm512_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., 17., 18., 19.,
             20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
@@ -17258,21 +17258,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_castph128_ph256() {
+    const fn test_mm256_castph128_ph256() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_castph128_ph256(a);
         assert_eq_m128h(_mm256_castph256_ph128(r), a);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm512_castph128_ph512() {
+    const fn test_mm512_castph128_ph512() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_castph128_ph512(a);
         assert_eq_m128h(_mm512_castph512_ph128(r), a);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm512_castph256_ph512() {
+    const fn test_mm512_castph256_ph512() {
         let a = _mm256_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -17281,7 +17281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_zextph128_ph256() {
+    const fn test_mm256_zextph128_ph256() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm256_zextph128_ph256(a);
         let e = _mm256_setr_ph(
@@ -17291,7 +17291,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_zextph128_ph512() {
+    const fn test_mm512_zextph128_ph512() {
         let a = _mm_setr_ph(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_zextph128_ph512(a);
         let e = _mm512_setr_ph(
@@ -17302,7 +17302,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_zextph256_ph512() {
+    const fn test_mm512_zextph256_ph512() {
         let a = _mm256_setr_ph(
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
@@ -17315,7 +17315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cmp_ph_mask() {
+    fn test_mm_cmp_ph_mask() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0);
         let r = _mm_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
@@ -17323,7 +17323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cmp_ph_mask() {
+    fn test_mm_mask_cmp_ph_mask() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(1.0, 2.0, 3.0, 4.0, -5.0, -6.0, -7.0, -8.0);
         let r = _mm_mask_cmp_ph_mask::<_CMP_EQ_OQ>(0b01010101, a, b);
@@ -17331,7 +17331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cmp_ph_mask() {
+    fn test_mm256_cmp_ph_mask() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17344,7 +17344,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_ph_mask() {
+    fn test_mm256_mask_cmp_ph_mask() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17357,7 +17357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cmp_ph_mask() {
+    fn test_mm512_cmp_ph_mask() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17373,7 +17373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cmp_ph_mask() {
+    fn test_mm512_mask_cmp_ph_mask() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17389,7 +17389,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cmp_round_ph_mask() {
+    fn test_mm512_cmp_round_ph_mask() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17405,7 +17405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cmp_round_ph_mask() {
+    fn test_mm512_mask_cmp_round_ph_mask() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17425,7 +17425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cmp_round_sh_mask() {
+    fn test_mm_cmp_round_sh_mask() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_cmp_round_sh_mask::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(a, b);
@@ -17433,7 +17433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_cmp_round_sh_mask() {
+    fn test_mm_mask_cmp_round_sh_mask() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_mask_cmp_round_sh_mask::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(0, a, b);
@@ -17441,7 +17441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cmp_sh_mask() {
+    fn test_mm_cmp_sh_mask() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_cmp_sh_mask::<_CMP_EQ_OQ>(a, b);
@@ -17449,7 +17449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_cmp_sh_mask() {
+    fn test_mm_mask_cmp_sh_mask() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_mask_cmp_sh_mask::<_CMP_EQ_OQ>(0, a, b);
@@ -17457,7 +17457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comi_round_sh() {
+    fn test_mm_comi_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_comi_round_sh::<_CMP_EQ_OQ, _MM_FROUND_NO_EXC>(a, b);
@@ -17465,7 +17465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comi_sh() {
+    fn test_mm_comi_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_comi_sh::<_CMP_EQ_OQ>(a, b);
@@ -17473,7 +17473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comieq_sh() {
+    fn test_mm_comieq_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_comieq_sh(a, b);
@@ -17481,7 +17481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comige_sh() {
+    fn test_mm_comige_sh() {
         let a = _mm_set_sh(2.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_comige_sh(a, b);
@@ -17489,7 +17489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comigt_sh() {
+    fn test_mm_comigt_sh() {
         let a = _mm_set_sh(2.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_comigt_sh(a, b);
@@ -17497,7 +17497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comile_sh() {
+    fn test_mm_comile_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_comile_sh(a, b);
@@ -17505,7 +17505,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comilt_sh() {
+    fn test_mm_comilt_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_comilt_sh(a, b);
@@ -17513,7 +17513,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_comineq_sh() {
+    fn test_mm_comineq_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_comineq_sh(a, b);
@@ -17521,7 +17521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_ucomieq_sh() {
+    fn test_mm_ucomieq_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_ucomieq_sh(a, b);
@@ -17529,7 +17529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_ucomige_sh() {
+    fn test_mm_ucomige_sh() {
         let a = _mm_set_sh(2.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_ucomige_sh(a, b);
@@ -17537,7 +17537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_ucomigt_sh() {
+    fn test_mm_ucomigt_sh() {
         let a = _mm_set_sh(2.0);
         let b = _mm_set_sh(1.0);
         let r = _mm_ucomigt_sh(a, b);
@@ -17545,7 +17545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_ucomile_sh() {
+    fn test_mm_ucomile_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_ucomile_sh(a, b);
@@ -17553,7 +17553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_ucomilt_sh() {
+    fn test_mm_ucomilt_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_ucomilt_sh(a, b);
@@ -17561,7 +17561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_ucomineq_sh() {
+    fn test_mm_ucomineq_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_ucomineq_sh(a, b);
@@ -17658,7 +17658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_move_sh() {
+    const fn test_mm_move_sh() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_sh(9.0);
         let r = _mm_move_sh(a, b);
@@ -17667,7 +17667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_move_sh() {
+    const fn test_mm_mask_move_sh() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_sh(9.0);
         let src = _mm_set_sh(10.0);
@@ -17677,7 +17677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_move_sh() {
+    const fn test_mm_maskz_move_sh() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_sh(9.0);
         let r = _mm_maskz_move_sh(0, a, b);
@@ -17764,7 +17764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_add_ph() {
+    const fn test_mm_add_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_add_ph(a, b);
@@ -17773,7 +17773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_add_ph() {
+    const fn test_mm_mask_add_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
@@ -17783,7 +17783,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_add_ph() {
+    const fn test_mm_maskz_add_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_maskz_add_ph(0b01010101, a, b);
@@ -17792,7 +17792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_add_ph() {
+    const fn test_mm256_add_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17805,7 +17805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_add_ph() {
+    const fn test_mm256_mask_add_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17823,7 +17823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_ph() {
+    const fn test_mm256_maskz_add_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17838,7 +17838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_add_ph() {
+    const fn test_mm512_add_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17855,7 +17855,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_add_ph() {
+    const fn test_mm512_mask_add_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17879,7 +17879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_add_ph() {
+    const fn test_mm512_maskz_add_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17899,7 +17899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_add_round_ph() {
+    fn test_mm512_add_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17916,7 +17916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_add_round_ph() {
+    fn test_mm512_mask_add_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17945,7 +17945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_add_round_ph() {
+    fn test_mm512_maskz_add_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17969,7 +17969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_add_round_sh() {
+    fn test_mm_add_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_add_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -17978,7 +17978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_add_round_sh() {
+    fn test_mm_mask_add_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -17995,7 +17995,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_add_round_sh() {
+    fn test_mm_maskz_add_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r =
@@ -18009,7 +18009,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_add_sh() {
+    const fn test_mm_add_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_add_sh(a, b);
@@ -18018,7 +18018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_add_sh() {
+    const fn test_mm_mask_add_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18031,7 +18031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_add_sh() {
+    const fn test_mm_maskz_add_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_add_sh(0, a, b);
@@ -18043,7 +18043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_sub_ph() {
+    const fn test_mm_sub_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_sub_ph(a, b);
@@ -18052,7 +18052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_sub_ph() {
+    const fn test_mm_mask_sub_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
@@ -18062,7 +18062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_ph() {
+    const fn test_mm_maskz_sub_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_maskz_sub_ph(0b01010101, a, b);
@@ -18071,7 +18071,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_sub_ph() {
+    const fn test_mm256_sub_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18087,7 +18087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_ph() {
+    const fn test_mm256_mask_sub_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18105,7 +18105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_ph() {
+    const fn test_mm256_maskz_sub_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18120,7 +18120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_sub_ph() {
+    const fn test_mm512_sub_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18141,7 +18141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_sub_ph() {
+    const fn test_mm512_mask_sub_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18165,7 +18165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_sub_ph() {
+    const fn test_mm512_maskz_sub_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18185,7 +18185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_sub_round_ph() {
+    fn test_mm512_sub_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18206,7 +18206,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_sub_round_ph() {
+    fn test_mm512_mask_sub_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18235,7 +18235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_sub_round_ph() {
+    fn test_mm512_maskz_sub_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18259,7 +18259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_sub_round_sh() {
+    fn test_mm_sub_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_sub_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -18268,7 +18268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_sub_round_sh() {
+    fn test_mm_mask_sub_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18285,7 +18285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_sub_round_sh() {
+    fn test_mm_maskz_sub_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r =
@@ -18299,7 +18299,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_sub_sh() {
+    const fn test_mm_sub_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_sub_sh(a, b);
@@ -18308,7 +18308,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_sub_sh() {
+    const fn test_mm_mask_sub_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18321,7 +18321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_sh() {
+    const fn test_mm_maskz_sub_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_sub_sh(0, a, b);
@@ -18333,7 +18333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mul_ph() {
+    const fn test_mm_mul_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_mul_ph(a, b);
@@ -18342,7 +18342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_mul_ph() {
+    const fn test_mm_mask_mul_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
@@ -18352,7 +18352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_mul_ph() {
+    const fn test_mm_maskz_mul_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(8.0, 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0);
         let r = _mm_maskz_mul_ph(0b01010101, a, b);
@@ -18361,7 +18361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mul_ph() {
+    const fn test_mm256_mul_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18377,7 +18377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_mul_ph() {
+    const fn test_mm256_mask_mul_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18395,7 +18395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_mul_ph() {
+    const fn test_mm256_maskz_mul_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -18410,7 +18410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mul_ph() {
+    const fn test_mm512_mul_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18431,7 +18431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_mul_ph() {
+    const fn test_mm512_mask_mul_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18455,7 +18455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_mul_ph() {
+    const fn test_mm512_maskz_mul_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18475,7 +18475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mul_round_ph() {
+    fn test_mm512_mul_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18496,7 +18496,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_mul_round_ph() {
+    fn test_mm512_mask_mul_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18525,7 +18525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_mul_round_ph() {
+    fn test_mm512_maskz_mul_round_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -18549,7 +18549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mul_round_sh() {
+    fn test_mm_mul_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_mul_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -18558,7 +18558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_mul_round_sh() {
+    fn test_mm_mask_mul_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18575,7 +18575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_mul_round_sh() {
+    fn test_mm_maskz_mul_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r =
@@ -18589,7 +18589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mul_sh() {
+    const fn test_mm_mul_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_mul_sh(a, b);
@@ -18598,7 +18598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_mul_sh() {
+    const fn test_mm_mask_mul_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18611,7 +18611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_mul_sh() {
+    const fn test_mm_maskz_mul_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_mul_sh(0, a, b);
@@ -18623,7 +18623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_div_ph() {
+    const fn test_mm_div_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let r = _mm_div_ph(a, b);
@@ -18632,7 +18632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_div_ph() {
+    const fn test_mm_mask_div_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let src = _mm_set_ph(4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0);
@@ -18642,7 +18642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_div_ph() {
+    const fn test_mm_maskz_div_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let r = _mm_maskz_div_ph(0b01010101, a, b);
@@ -18651,7 +18651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_div_ph() {
+    const fn test_mm256_div_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let r = _mm256_div_ph(a, b);
@@ -18660,7 +18660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_div_ph() {
+    const fn test_mm256_mask_div_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let src = _mm256_set_ph(
@@ -18675,7 +18675,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_div_ph() {
+    const fn test_mm256_maskz_div_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let r = _mm256_maskz_div_ph(0b0101010101010101, a, b);
@@ -18686,7 +18686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_div_ph() {
+    const fn test_mm512_div_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let r = _mm512_div_ph(a, b);
@@ -18695,7 +18695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_div_ph() {
+    const fn test_mm512_mask_div_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let src = _mm512_set_ph(
@@ -18712,7 +18712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_div_ph() {
+    const fn test_mm512_maskz_div_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let r = _mm512_maskz_div_ph(0b01010101010101010101010101010101, a, b);
@@ -18724,7 +18724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_div_round_ph() {
+    fn test_mm512_div_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let r = _mm512_div_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -18733,7 +18733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_div_round_ph() {
+    fn test_mm512_mask_div_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let src = _mm512_set_ph(
@@ -18755,7 +18755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_div_round_ph() {
+    fn test_mm512_maskz_div_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let r = _mm512_maskz_div_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -18771,7 +18771,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_div_round_sh() {
+    fn test_mm_div_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_div_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -18780,7 +18780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_div_round_sh() {
+    fn test_mm_mask_div_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18797,7 +18797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_div_round_sh() {
+    fn test_mm_maskz_div_round_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r =
@@ -18811,7 +18811,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_div_sh() {
+    const fn test_mm_div_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_div_sh(a, b);
@@ -18820,7 +18820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_div_sh() {
+    const fn test_mm_mask_div_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let src = _mm_set_sh(4.0);
@@ -18833,7 +18833,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_div_sh() {
+    const fn test_mm_maskz_div_sh() {
         let a = _mm_set_sh(1.0);
         let b = _mm_set_sh(2.0);
         let r = _mm_maskz_div_sh(0, a, b);
@@ -18845,7 +18845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mul_pch() {
+    fn test_mm_mul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 1.0);
         let r = _mm_mul_pch(a, b);
@@ -18854,7 +18854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_mul_pch() {
+    fn test_mm_mask_mul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 1.0);
         let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
@@ -18864,7 +18864,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_mul_pch() {
+    fn test_mm_maskz_mul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 1.0);
         let r = _mm_maskz_mul_pch(0b0101, a, b);
@@ -18873,7 +18873,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mul_pch() {
+    fn test_mm256_mul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_mul_pch(a, b);
@@ -18882,7 +18882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_mul_pch() {
+    fn test_mm256_mask_mul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 1.0);
         let src = _mm256_setr_ph(
@@ -18896,7 +18896,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_mul_pch() {
+    fn test_mm256_maskz_mul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_maskz_mul_pch(0b01010101, a, b);
@@ -18907,7 +18907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mul_pch() {
+    fn test_mm512_mul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_mul_pch(a, b);
@@ -18916,7 +18916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_mul_pch() {
+    fn test_mm512_mask_mul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let src = _mm512_setr_ph(
@@ -18934,7 +18934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_mul_pch() {
+    fn test_mm512_maskz_mul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_maskz_mul_pch(0b0101010101010101, a, b);
@@ -18946,7 +18946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mul_round_pch() {
+    fn test_mm512_mul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_mul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -18955,7 +18955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_mul_round_pch() {
+    fn test_mm512_mask_mul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let src = _mm512_setr_ph(
@@ -18978,7 +18978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_mul_round_pch() {
+    fn test_mm512_maskz_mul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_maskz_mul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -18994,7 +18994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mul_round_sch() {
+    fn test_mm_mul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r = _mm_mul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19003,7 +19003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_mul_round_sch() {
+    fn test_mm_mask_mul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19015,7 +19015,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_mul_round_sch() {
+    fn test_mm_maskz_mul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r =
@@ -19025,7 +19025,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mul_sch() {
+    fn test_mm_mul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r = _mm_mul_sch(a, b);
@@ -19034,7 +19034,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_mul_sch() {
+    fn test_mm_mask_mul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19044,7 +19044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_mul_sch() {
+    fn test_mm_maskz_mul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r = _mm_maskz_mul_sch(0, a, b);
@@ -19053,7 +19053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmul_pch() {
+    fn test_mm_fmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 1.0);
         let r = _mm_fmul_pch(a, b);
@@ -19062,7 +19062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmul_pch() {
+    fn test_mm_mask_fmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 1.0);
         let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
@@ -19072,7 +19072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmul_pch() {
+    fn test_mm_maskz_fmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 1.0);
         let r = _mm_maskz_fmul_pch(0b0101, a, b);
@@ -19081,7 +19081,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fmul_pch() {
+    fn test_mm256_fmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_fmul_pch(a, b);
@@ -19090,7 +19090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fmul_pch() {
+    fn test_mm256_mask_fmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 1.0);
         let src = _mm256_setr_ph(
@@ -19104,7 +19104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fmul_pch() {
+    fn test_mm256_maskz_fmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_maskz_fmul_pch(0b01010101, a, b);
@@ -19115,7 +19115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmul_pch() {
+    fn test_mm512_fmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_fmul_pch(a, b);
@@ -19124,7 +19124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmul_pch() {
+    fn test_mm512_mask_fmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let src = _mm512_setr_ph(
@@ -19142,7 +19142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmul_pch() {
+    fn test_mm512_maskz_fmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_maskz_fmul_pch(0b0101010101010101, a, b);
@@ -19154,7 +19154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmul_round_pch() {
+    fn test_mm512_fmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_fmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19163,7 +19163,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmul_round_pch() {
+    fn test_mm512_mask_fmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let src = _mm512_setr_ph(
@@ -19186,7 +19186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmul_round_pch() {
+    fn test_mm512_maskz_fmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_maskz_fmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -19202,7 +19202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmul_round_sch() {
+    fn test_mm_fmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r = _mm_fmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19211,7 +19211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmul_round_sch() {
+    fn test_mm_mask_fmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19223,7 +19223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmul_round_sch() {
+    fn test_mm_maskz_fmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r =
@@ -19233,7 +19233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmul_sch() {
+    fn test_mm_fmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r = _mm_fmul_sch(a, b);
@@ -19242,7 +19242,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmul_sch() {
+    fn test_mm_mask_fmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19252,7 +19252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmul_sch() {
+    fn test_mm_maskz_fmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 1.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let r = _mm_maskz_fmul_sch(0, a, b);
@@ -19261,7 +19261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cmul_pch() {
+    fn test_mm_cmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, -1.0);
         let r = _mm_cmul_pch(a, b);
@@ -19270,7 +19270,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cmul_pch() {
+    fn test_mm_mask_cmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, -1.0);
         let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
@@ -19280,7 +19280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cmul_pch() {
+    fn test_mm_maskz_cmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, -1.0);
         let r = _mm_maskz_cmul_pch(0b0101, a, b);
@@ -19289,7 +19289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cmul_pch() {
+    fn test_mm256_cmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, -1.0);
         let r = _mm256_cmul_pch(a, b);
@@ -19298,7 +19298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cmul_pch() {
+    fn test_mm256_mask_cmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, -1.0);
         let src = _mm256_setr_ph(
@@ -19312,7 +19312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cmul_pch() {
+    fn test_mm256_maskz_cmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, -1.0);
         let r = _mm256_maskz_cmul_pch(0b01010101, a, b);
@@ -19323,7 +19323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cmul_pch() {
+    fn test_mm512_cmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_cmul_pch(a, b);
@@ -19332,7 +19332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cmul_pch() {
+    fn test_mm512_mask_cmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let src = _mm512_setr_ph(
@@ -19350,7 +19350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cmul_pch() {
+    fn test_mm512_maskz_cmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_maskz_cmul_pch(0b0101010101010101, a, b);
@@ -19362,7 +19362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cmul_round_pch() {
+    fn test_mm512_cmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_cmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19371,7 +19371,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cmul_round_pch() {
+    fn test_mm512_mask_cmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let src = _mm512_setr_ph(
@@ -19394,7 +19394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cmul_round_pch() {
+    fn test_mm512_maskz_cmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_maskz_cmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -19410,7 +19410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cmul_sch() {
+    fn test_mm_cmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r = _mm_cmul_sch(a, b);
@@ -19419,7 +19419,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cmul_sch() {
+    fn test_mm_mask_cmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19429,7 +19429,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cmul_sch() {
+    fn test_mm_maskz_cmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r = _mm_maskz_cmul_sch(0, a, b);
@@ -19438,7 +19438,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cmul_round_sch() {
+    fn test_mm_cmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r = _mm_cmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19447,7 +19447,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cmul_round_sch() {
+    fn test_mm_mask_cmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19459,7 +19459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cmul_round_sch() {
+    fn test_mm_maskz_cmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r =
@@ -19469,7 +19469,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fcmul_pch() {
+    fn test_mm_fcmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, -1.0);
         let r = _mm_fcmul_pch(a, b);
@@ -19478,7 +19478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fcmul_pch() {
+    fn test_mm_mask_fcmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, -1.0);
         let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
@@ -19488,7 +19488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fcmul_pch() {
+    fn test_mm_maskz_fcmul_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, -1.0);
         let r = _mm_maskz_fcmul_pch(0b0101, a, b);
@@ -19497,7 +19497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fcmul_pch() {
+    fn test_mm256_fcmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, -1.0);
         let r = _mm256_fcmul_pch(a, b);
@@ -19506,7 +19506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fcmul_pch() {
+    fn test_mm256_mask_fcmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, -1.0);
         let src = _mm256_setr_ph(
@@ -19520,7 +19520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fcmul_pch() {
+    fn test_mm256_maskz_fcmul_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, -1.0);
         let r = _mm256_maskz_fcmul_pch(0b01010101, a, b);
@@ -19531,7 +19531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fcmul_pch() {
+    fn test_mm512_fcmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_fcmul_pch(a, b);
@@ -19540,7 +19540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fcmul_pch() {
+    fn test_mm512_mask_fcmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let src = _mm512_setr_ph(
@@ -19558,7 +19558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fcmul_pch() {
+    fn test_mm512_maskz_fcmul_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_maskz_fcmul_pch(0b0101010101010101, a, b);
@@ -19570,7 +19570,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fcmul_round_pch() {
+    fn test_mm512_fcmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_fcmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19579,7 +19579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fcmul_round_pch() {
+    fn test_mm512_mask_fcmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let src = _mm512_setr_ph(
@@ -19602,7 +19602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fcmul_round_pch() {
+    fn test_mm512_maskz_fcmul_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, -1.0);
         let r = _mm512_maskz_fcmul_round_pch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -19618,7 +19618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fcmul_sch() {
+    fn test_mm_fcmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r = _mm_fcmul_sch(a, b);
@@ -19627,7 +19627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fcmul_sch() {
+    fn test_mm_mask_fcmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19637,7 +19637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fcmul_sch() {
+    fn test_mm_maskz_fcmul_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r = _mm_maskz_fcmul_sch(0, a, b);
@@ -19646,7 +19646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fcmul_round_sch() {
+    fn test_mm_fcmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r = _mm_fcmul_round_sch::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -19655,7 +19655,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fcmul_round_sch() {
+    fn test_mm_mask_fcmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let src = _mm_setr_ph(14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0);
@@ -19667,7 +19667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fcmul_round_sch() {
+    fn test_mm_maskz_fcmul_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, -1.0, 8.0, -9.0, 10.0, -11.0, 12.0, -13.0);
         let r =
@@ -19677,7 +19677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_abs_ph() {
+    const fn test_mm_abs_ph() {
         let a = _mm_set_ph(-1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0);
         let r = _mm_abs_ph(a);
         let e = _mm_set_ph(1.0, 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0);
@@ -19685,7 +19685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_abs_ph() {
+    const fn test_mm256_abs_ph() {
         let a = _mm256_set_ph(
             -1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0,
             -14.0,
@@ -19698,7 +19698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_abs_ph() {
+    const fn test_mm512_abs_ph() {
         let a = _mm512_set_ph(
             -1.0, 0.0, 1.0, -2.0, 3.0, -4.0, 5.0, -6.0, 7.0, -8.0, 9.0, -10.0, 11.0, -12.0, 13.0,
             -14.0, 15.0, -16.0, 17.0, -18.0, 19.0, -20.0, 21.0, -22.0, 23.0, -24.0, 25.0, -26.0,
@@ -19714,7 +19714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_conj_pch() {
+    const fn test_mm_conj_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let r = _mm_conj_pch(a);
         let e = _mm_set1_pch(0.0, -1.0);
@@ -19722,7 +19722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_conj_pch() {
+    const fn test_mm_mask_conj_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let src = _mm_setr_ph(2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0);
         let r = _mm_mask_conj_pch(src, 0b0101, a);
@@ -19731,7 +19731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_conj_pch() {
+    const fn test_mm_maskz_conj_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let r = _mm_maskz_conj_pch(0b0101, a);
         let e = _mm_setr_ph(0.0, -1.0, 0.0, 0.0, 0.0, -1.0, 0.0, 0.0);
@@ -19739,7 +19739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_conj_pch() {
+    const fn test_mm256_conj_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_conj_pch(a);
         let e = _mm256_set1_pch(0.0, -1.0);
@@ -19747,7 +19747,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_conj_pch() {
+    const fn test_mm256_mask_conj_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let src = _mm256_setr_ph(
             2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
@@ -19760,7 +19760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_conj_pch() {
+    const fn test_mm256_maskz_conj_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let r = _mm256_maskz_conj_pch(0b01010101, a);
         let e = _mm256_setr_ph(
@@ -19770,7 +19770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_conj_pch() {
+    const fn test_mm512_conj_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_conj_pch(a);
         let e = _mm512_set1_pch(0.0, -1.0);
@@ -19778,7 +19778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_conj_pch() {
+    const fn test_mm512_mask_conj_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let src = _mm512_setr_ph(
             2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0,
@@ -19795,7 +19795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_conj_pch() {
+    const fn test_mm512_maskz_conj_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let r = _mm512_maskz_conj_pch(0b0101010101010101, a);
         let e = _mm512_setr_ph(
@@ -19806,7 +19806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmadd_pch() {
+    fn test_mm_fmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -19816,7 +19816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_pch() {
+    fn test_mm_mask_fmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -19826,7 +19826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_pch() {
+    fn test_mm_mask3_fmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -19836,7 +19836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_pch() {
+    fn test_mm_maskz_fmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -19846,7 +19846,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fmadd_pch() {
+    fn test_mm256_fmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -19856,7 +19856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fmadd_pch() {
+    fn test_mm256_mask_fmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -19868,7 +19868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fmadd_pch() {
+    fn test_mm256_mask3_fmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -19880,7 +19880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fmadd_pch() {
+    fn test_mm256_maskz_fmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -19892,7 +19892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmadd_pch() {
+    fn test_mm512_fmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19902,7 +19902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmadd_pch() {
+    fn test_mm512_mask_fmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19915,7 +19915,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmadd_pch() {
+    fn test_mm512_mask3_fmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19928,7 +19928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmadd_pch() {
+    fn test_mm512_maskz_fmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19941,7 +19941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmadd_round_pch() {
+    fn test_mm512_fmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19952,7 +19952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmadd_round_pch() {
+    fn test_mm512_mask_fmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19970,7 +19970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmadd_round_pch() {
+    fn test_mm512_mask3_fmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -19988,7 +19988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmadd_round_pch() {
+    fn test_mm512_maskz_fmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20006,7 +20006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmadd_sch() {
+    fn test_mm_fmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20016,7 +20016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_sch() {
+    fn test_mm_mask_fmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20029,7 +20029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_sch() {
+    fn test_mm_mask3_fmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20042,7 +20042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_sch() {
+    fn test_mm_maskz_fmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20055,7 +20055,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmadd_round_sch() {
+    fn test_mm_fmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20065,7 +20065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_round_sch() {
+    fn test_mm_mask_fmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20082,7 +20082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_round_sch() {
+    fn test_mm_mask3_fmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20099,7 +20099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_round_sch() {
+    fn test_mm_maskz_fmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20116,7 +20116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fcmadd_pch() {
+    fn test_mm_fcmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -20126,7 +20126,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fcmadd_pch() {
+    fn test_mm_mask_fcmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -20136,7 +20136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fcmadd_pch() {
+    fn test_mm_mask3_fcmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -20146,7 +20146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fcmadd_pch() {
+    fn test_mm_maskz_fcmadd_pch() {
         let a = _mm_set1_pch(0.0, 1.0);
         let b = _mm_set1_pch(0.0, 2.0);
         let c = _mm_set1_pch(0.0, 3.0);
@@ -20156,7 +20156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fcmadd_pch() {
+    fn test_mm256_fcmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -20166,7 +20166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fcmadd_pch() {
+    fn test_mm256_mask_fcmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -20178,7 +20178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask3_fcmadd_pch() {
+    fn test_mm256_mask3_fcmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -20190,7 +20190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_fcmadd_pch() {
+    fn test_mm256_maskz_fcmadd_pch() {
         let a = _mm256_set1_pch(0.0, 1.0);
         let b = _mm256_set1_pch(0.0, 2.0);
         let c = _mm256_set1_pch(0.0, 3.0);
@@ -20202,7 +20202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fcmadd_pch() {
+    fn test_mm512_fcmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20212,7 +20212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fcmadd_pch() {
+    fn test_mm512_mask_fcmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20225,7 +20225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fcmadd_pch() {
+    fn test_mm512_mask3_fcmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20238,7 +20238,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fcmadd_pch() {
+    fn test_mm512_maskz_fcmadd_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20251,7 +20251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fcmadd_round_pch() {
+    fn test_mm512_fcmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20262,7 +20262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fcmadd_round_pch() {
+    fn test_mm512_mask_fcmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20280,7 +20280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fcmadd_round_pch() {
+    fn test_mm512_mask3_fcmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20298,7 +20298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fcmadd_round_pch() {
+    fn test_mm512_maskz_fcmadd_round_pch() {
         let a = _mm512_set1_pch(0.0, 1.0);
         let b = _mm512_set1_pch(0.0, 2.0);
         let c = _mm512_set1_pch(0.0, 3.0);
@@ -20316,7 +20316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fcmadd_sch() {
+    fn test_mm_fcmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20326,7 +20326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fcmadd_sch() {
+    fn test_mm_mask_fcmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20339,7 +20339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fcmadd_sch() {
+    fn test_mm_mask3_fcmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20352,7 +20352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fcmadd_sch() {
+    fn test_mm_maskz_fcmadd_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20365,7 +20365,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fcmadd_round_sch() {
+    fn test_mm_fcmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20375,7 +20375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fcmadd_round_sch() {
+    fn test_mm_mask_fcmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20392,7 +20392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fcmadd_round_sch() {
+    fn test_mm_mask3_fcmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20409,7 +20409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fcmadd_round_sch() {
+    fn test_mm_maskz_fcmadd_round_sch() {
         let a = _mm_setr_ph(0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0);
         let b = _mm_setr_ph(0.0, 2.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0);
         let c = _mm_setr_ph(0.0, 3.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0);
@@ -20426,7 +20426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fmadd_ph() {
+    const fn test_mm_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20436,7 +20436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fmadd_ph() {
+    const fn test_mm_mask_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20446,7 +20446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fmadd_ph() {
+    const fn test_mm_mask3_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20456,7 +20456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fmadd_ph() {
+    const fn test_mm_maskz_fmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20466,7 +20466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_fmadd_ph() {
+    const fn test_mm256_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20476,7 +20476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_fmadd_ph() {
+    const fn test_mm256_mask_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20488,7 +20488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmadd_ph() {
+    const fn test_mm256_mask3_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20500,7 +20500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmadd_ph() {
+    const fn test_mm256_maskz_fmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20512,7 +20512,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_fmadd_ph() {
+    const fn test_mm512_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20522,7 +20522,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_fmadd_ph() {
+    const fn test_mm512_mask_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20535,7 +20535,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask3_fmadd_ph() {
+    const fn test_mm512_mask3_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20548,7 +20548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_fmadd_ph() {
+    const fn test_mm512_maskz_fmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20561,7 +20561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmadd_round_ph() {
+    fn test_mm512_fmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20571,7 +20571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmadd_round_ph() {
+    fn test_mm512_mask_fmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20589,7 +20589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmadd_round_ph() {
+    fn test_mm512_mask3_fmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20607,7 +20607,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmadd_round_ph() {
+    fn test_mm512_maskz_fmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20625,7 +20625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fmadd_sh() {
+    const fn test_mm_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20635,7 +20635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fmadd_sh() {
+    const fn test_mm_mask_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20648,7 +20648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fmadd_sh() {
+    const fn test_mm_mask3_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20661,7 +20661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fmadd_sh() {
+    const fn test_mm_maskz_fmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20674,7 +20674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmadd_round_sh() {
+    fn test_mm_fmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20684,7 +20684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmadd_round_sh() {
+    fn test_mm_mask_fmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20701,7 +20701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmadd_round_sh() {
+    fn test_mm_mask3_fmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20718,7 +20718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmadd_round_sh() {
+    fn test_mm_maskz_fmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20735,7 +20735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fmsub_ph() {
+    const fn test_mm_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20745,7 +20745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fmsub_ph() {
+    const fn test_mm_mask_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20755,7 +20755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsub_ph() {
+    const fn test_mm_mask3_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20765,7 +20765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsub_ph() {
+    const fn test_mm_maskz_fmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -20775,7 +20775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_fmsub_ph() {
+    const fn test_mm256_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20785,7 +20785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_fmsub_ph() {
+    const fn test_mm256_mask_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20797,7 +20797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmsub_ph() {
+    const fn test_mm256_mask3_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20809,7 +20809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmsub_ph() {
+    const fn test_mm256_maskz_fmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -20821,7 +20821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_fmsub_ph() {
+    const fn test_mm512_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20831,7 +20831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_fmsub_ph() {
+    const fn test_mm512_mask_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20844,7 +20844,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask3_fmsub_ph() {
+    const fn test_mm512_mask3_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20857,7 +20857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_fmsub_ph() {
+    const fn test_mm512_maskz_fmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20870,7 +20870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmsub_round_ph() {
+    fn test_mm512_fmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20880,7 +20880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmsub_round_ph() {
+    fn test_mm512_mask_fmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20898,7 +20898,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmsub_round_ph() {
+    fn test_mm512_mask3_fmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20916,7 +20916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmsub_round_ph() {
+    fn test_mm512_maskz_fmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -20934,7 +20934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fmsub_sh() {
+    const fn test_mm_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20944,7 +20944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fmsub_sh() {
+    const fn test_mm_mask_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20957,7 +20957,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsub_sh() {
+    const fn test_mm_mask3_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20970,7 +20970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsub_sh() {
+    const fn test_mm_maskz_fmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20983,7 +20983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fmsub_round_sh() {
+    fn test_mm_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -20993,7 +20993,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fmsub_round_sh() {
+    fn test_mm_mask_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21010,7 +21010,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fmsub_round_sh() {
+    fn test_mm_mask3_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21027,7 +21027,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fmsub_round_sh() {
+    fn test_mm_maskz_fmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21044,7 +21044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fnmadd_ph() {
+    const fn test_mm_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21054,7 +21054,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fnmadd_ph() {
+    const fn test_mm_mask_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21064,7 +21064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmadd_ph() {
+    const fn test_mm_mask3_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21074,7 +21074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmadd_ph() {
+    const fn test_mm_maskz_fnmadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21084,7 +21084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_fnmadd_ph() {
+    const fn test_mm256_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21094,7 +21094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_fnmadd_ph() {
+    const fn test_mm256_mask_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21106,7 +21106,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask3_fnmadd_ph() {
+    const fn test_mm256_mask3_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21118,7 +21118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_fnmadd_ph() {
+    const fn test_mm256_maskz_fnmadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21130,7 +21130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_fnmadd_ph() {
+    const fn test_mm512_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21140,7 +21140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_fnmadd_ph() {
+    const fn test_mm512_mask_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21153,7 +21153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask3_fnmadd_ph() {
+    const fn test_mm512_mask3_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21166,7 +21166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_fnmadd_ph() {
+    const fn test_mm512_maskz_fnmadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21179,7 +21179,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fnmadd_round_ph() {
+    fn test_mm512_fnmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21190,7 +21190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fnmadd_round_ph() {
+    fn test_mm512_mask_fnmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21208,7 +21208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fnmadd_round_ph() {
+    fn test_mm512_mask3_fnmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21226,7 +21226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fnmadd_round_ph() {
+    fn test_mm512_maskz_fnmadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21244,7 +21244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fnmadd_sh() {
+    const fn test_mm_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21254,7 +21254,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fnmadd_sh() {
+    const fn test_mm_mask_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21267,7 +21267,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmadd_sh() {
+    const fn test_mm_mask3_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21280,7 +21280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmadd_sh() {
+    const fn test_mm_maskz_fnmadd_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21293,7 +21293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fnmadd_round_sh() {
+    fn test_mm_fnmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21303,7 +21303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fnmadd_round_sh() {
+    fn test_mm_mask_fnmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21320,7 +21320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fnmadd_round_sh() {
+    fn test_mm_mask3_fnmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21337,7 +21337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fnmadd_round_sh() {
+    fn test_mm_maskz_fnmadd_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21354,7 +21354,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fnmsub_ph() {
+    const fn test_mm_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21364,7 +21364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fnmsub_ph() {
+    const fn test_mm_mask_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21374,7 +21374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmsub_ph() {
+    const fn test_mm_mask3_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21384,7 +21384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmsub_ph() {
+    const fn test_mm_maskz_fnmsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21394,7 +21394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_fnmsub_ph() {
+    const fn test_mm256_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21404,7 +21404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_fnmsub_ph() {
+    const fn test_mm256_mask_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21416,7 +21416,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask3_fnmsub_ph() {
+    const fn test_mm256_mask3_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21428,7 +21428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_fnmsub_ph() {
+    const fn test_mm256_maskz_fnmsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21440,7 +21440,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_fnmsub_ph() {
+    const fn test_mm512_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21450,7 +21450,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_fnmsub_ph() {
+    const fn test_mm512_mask_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21463,7 +21463,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask3_fnmsub_ph() {
+    const fn test_mm512_mask3_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21476,7 +21476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_fnmsub_ph() {
+    const fn test_mm512_maskz_fnmsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21489,7 +21489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fnmsub_round_ph() {
+    fn test_mm512_fnmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21500,7 +21500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fnmsub_round_ph() {
+    fn test_mm512_mask_fnmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21518,7 +21518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fnmsub_round_ph() {
+    fn test_mm512_mask3_fnmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21536,7 +21536,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fnmsub_round_ph() {
+    fn test_mm512_maskz_fnmsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21554,7 +21554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fnmsub_sh() {
+    const fn test_mm_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21564,7 +21564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fnmsub_sh() {
+    const fn test_mm_mask_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21577,7 +21577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmsub_sh() {
+    const fn test_mm_mask3_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21590,7 +21590,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmsub_sh() {
+    const fn test_mm_maskz_fnmsub_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21603,7 +21603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fnmsub_round_sh() {
+    fn test_mm_fnmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21613,7 +21613,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fnmsub_round_sh() {
+    fn test_mm_mask_fnmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21630,7 +21630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask3_fnmsub_round_sh() {
+    fn test_mm_mask3_fnmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21647,7 +21647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_fnmsub_round_sh() {
+    fn test_mm_maskz_fnmsub_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(2.0, 20., 21., 22., 23., 24., 25., 26.);
         let c = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -21664,7 +21664,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fmaddsub_ph() {
+    const fn test_mm_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21674,7 +21674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fmaddsub_ph() {
+    const fn test_mm_mask_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21684,7 +21684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fmaddsub_ph() {
+    const fn test_mm_mask3_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21694,7 +21694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fmaddsub_ph() {
+    const fn test_mm_maskz_fmaddsub_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21704,7 +21704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_fmaddsub_ph() {
+    const fn test_mm256_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21716,7 +21716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_fmaddsub_ph() {
+    const fn test_mm256_mask_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21728,7 +21728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmaddsub_ph() {
+    const fn test_mm256_mask3_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21740,7 +21740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmaddsub_ph() {
+    const fn test_mm256_maskz_fmaddsub_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21752,7 +21752,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_fmaddsub_ph() {
+    const fn test_mm512_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21765,7 +21765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_fmaddsub_ph() {
+    const fn test_mm512_mask_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21778,7 +21778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask3_fmaddsub_ph() {
+    const fn test_mm512_mask3_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21791,7 +21791,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_fmaddsub_ph() {
+    const fn test_mm512_maskz_fmaddsub_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21804,7 +21804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmaddsub_round_ph() {
+    fn test_mm512_fmaddsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21818,7 +21818,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmaddsub_round_ph() {
+    fn test_mm512_mask_fmaddsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21836,7 +21836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmaddsub_round_ph() {
+    fn test_mm512_mask3_fmaddsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21854,7 +21854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmaddsub_round_ph() {
+    fn test_mm512_maskz_fmaddsub_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21872,7 +21872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_fmsubadd_ph() {
+    const fn test_mm_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21882,7 +21882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_fmsubadd_ph() {
+    const fn test_mm_mask_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21892,7 +21892,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsubadd_ph() {
+    const fn test_mm_mask3_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21902,7 +21902,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsubadd_ph() {
+    const fn test_mm_maskz_fmsubadd_ph() {
         let a = _mm_set1_ph(1.0);
         let b = _mm_set1_ph(2.0);
         let c = _mm_set1_ph(3.0);
@@ -21912,7 +21912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_fmsubadd_ph() {
+    const fn test_mm256_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21924,7 +21924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_fmsubadd_ph() {
+    const fn test_mm256_mask_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21936,7 +21936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmsubadd_ph() {
+    const fn test_mm256_mask3_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21948,7 +21948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmsubadd_ph() {
+    const fn test_mm256_maskz_fmsubadd_ph() {
         let a = _mm256_set1_ph(1.0);
         let b = _mm256_set1_ph(2.0);
         let c = _mm256_set1_ph(3.0);
@@ -21960,7 +21960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_fmsubadd_ph() {
+    const fn test_mm512_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21973,7 +21973,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_fmsubadd_ph() {
+    const fn test_mm512_mask_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21986,7 +21986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask3_fmsubadd_ph() {
+    const fn test_mm512_mask3_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -21999,7 +21999,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_maskz_fmsubadd_ph() {
+    const fn test_mm512_maskz_fmsubadd_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -22012,7 +22012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fmsubadd_round_ph() {
+    fn test_mm512_fmsubadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -22026,7 +22026,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fmsubadd_round_ph() {
+    fn test_mm512_mask_fmsubadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -22044,7 +22044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask3_fmsubadd_round_ph() {
+    fn test_mm512_mask3_fmsubadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -22062,7 +22062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_fmsubadd_round_ph() {
+    fn test_mm512_maskz_fmsubadd_round_ph() {
         let a = _mm512_set1_ph(1.0);
         let b = _mm512_set1_ph(2.0);
         let c = _mm512_set1_ph(3.0);
@@ -22080,7 +22080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_rcp_ph() {
+    fn test_mm_rcp_ph() {
         let a = _mm_set1_ph(2.0);
         let r = _mm_rcp_ph(a);
         let e = _mm_set1_ph(0.5);
@@ -22088,7 +22088,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_rcp_ph() {
+    fn test_mm_mask_rcp_ph() {
         let a = _mm_set1_ph(2.0);
         let src = _mm_set1_ph(1.0);
         let r = _mm_mask_rcp_ph(src, 0b01010101, a);
@@ -22097,7 +22097,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_rcp_ph() {
+    fn test_mm_maskz_rcp_ph() {
         let a = _mm_set1_ph(2.0);
         let r = _mm_maskz_rcp_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5);
@@ -22105,7 +22105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_rcp_ph() {
+    fn test_mm256_rcp_ph() {
         let a = _mm256_set1_ph(2.0);
         let r = _mm256_rcp_ph(a);
         let e = _mm256_set1_ph(0.5);
@@ -22113,7 +22113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_rcp_ph() {
+    fn test_mm256_mask_rcp_ph() {
         let a = _mm256_set1_ph(2.0);
         let src = _mm256_set1_ph(1.0);
         let r = _mm256_mask_rcp_ph(src, 0b0101010101010101, a);
@@ -22124,7 +22124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_rcp_ph() {
+    fn test_mm256_maskz_rcp_ph() {
         let a = _mm256_set1_ph(2.0);
         let r = _mm256_maskz_rcp_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -22134,7 +22134,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_rcp_ph() {
+    fn test_mm512_rcp_ph() {
         let a = _mm512_set1_ph(2.0);
         let r = _mm512_rcp_ph(a);
         let e = _mm512_set1_ph(0.5);
@@ -22142,7 +22142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_rcp_ph() {
+    fn test_mm512_mask_rcp_ph() {
         let a = _mm512_set1_ph(2.0);
         let src = _mm512_set1_ph(1.0);
         let r = _mm512_mask_rcp_ph(src, 0b01010101010101010101010101010101, a);
@@ -22154,7 +22154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_rcp_ph() {
+    fn test_mm512_maskz_rcp_ph() {
         let a = _mm512_set1_ph(2.0);
         let r = _mm512_maskz_rcp_ph(0b01010101010101010101010101010101, a);
         let e = _mm512_set_ph(
@@ -22165,7 +22165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_rcp_sh() {
+    fn test_mm_rcp_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_rcp_sh(a, b);
@@ -22174,7 +22174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_rcp_sh() {
+    fn test_mm_mask_rcp_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22187,7 +22187,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_rcp_sh() {
+    fn test_mm_maskz_rcp_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_maskz_rcp_sh(0, a, b);
@@ -22199,7 +22199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_rsqrt_ph() {
+    fn test_mm_rsqrt_ph() {
         let a = _mm_set1_ph(4.0);
         let r = _mm_rsqrt_ph(a);
         let e = _mm_set1_ph(0.5);
@@ -22207,7 +22207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_rsqrt_ph() {
+    fn test_mm_mask_rsqrt_ph() {
         let a = _mm_set1_ph(4.0);
         let src = _mm_set1_ph(1.0);
         let r = _mm_mask_rsqrt_ph(src, 0b01010101, a);
@@ -22216,7 +22216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_rsqrt_ph() {
+    fn test_mm_maskz_rsqrt_ph() {
         let a = _mm_set1_ph(4.0);
         let r = _mm_maskz_rsqrt_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 0.5, 0.0, 0.5, 0.0, 0.5, 0.0, 0.5);
@@ -22224,7 +22224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_rsqrt_ph() {
+    fn test_mm256_rsqrt_ph() {
         let a = _mm256_set1_ph(4.0);
         let r = _mm256_rsqrt_ph(a);
         let e = _mm256_set1_ph(0.5);
@@ -22232,7 +22232,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_rsqrt_ph() {
+    fn test_mm256_mask_rsqrt_ph() {
         let a = _mm256_set1_ph(4.0);
         let src = _mm256_set1_ph(1.0);
         let r = _mm256_mask_rsqrt_ph(src, 0b0101010101010101, a);
@@ -22243,7 +22243,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_rsqrt_ph() {
+    fn test_mm256_maskz_rsqrt_ph() {
         let a = _mm256_set1_ph(4.0);
         let r = _mm256_maskz_rsqrt_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -22253,7 +22253,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_rsqrt_ph() {
+    fn test_mm512_rsqrt_ph() {
         let a = _mm512_set1_ph(4.0);
         let r = _mm512_rsqrt_ph(a);
         let e = _mm512_set1_ph(0.5);
@@ -22261,7 +22261,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_rsqrt_ph() {
+    fn test_mm512_mask_rsqrt_ph() {
         let a = _mm512_set1_ph(4.0);
         let src = _mm512_set1_ph(1.0);
         let r = _mm512_mask_rsqrt_ph(src, 0b01010101010101010101010101010101, a);
@@ -22273,7 +22273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_rsqrt_ph() {
+    fn test_mm512_maskz_rsqrt_ph() {
         let a = _mm512_set1_ph(4.0);
         let r = _mm512_maskz_rsqrt_ph(0b01010101010101010101010101010101, a);
         let e = _mm512_set_ph(
@@ -22284,7 +22284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_rsqrt_sh() {
+    fn test_mm_rsqrt_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let r = _mm_rsqrt_sh(a, b);
@@ -22293,7 +22293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_rsqrt_sh() {
+    fn test_mm_mask_rsqrt_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22306,7 +22306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_rsqrt_sh() {
+    fn test_mm_maskz_rsqrt_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let r = _mm_maskz_rsqrt_sh(0, a, b);
@@ -22318,7 +22318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_sqrt_ph() {
+    fn test_mm_sqrt_ph() {
         let a = _mm_set1_ph(4.0);
         let r = _mm_sqrt_ph(a);
         let e = _mm_set1_ph(2.0);
@@ -22326,7 +22326,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_sqrt_ph() {
+    fn test_mm_mask_sqrt_ph() {
         let a = _mm_set1_ph(4.0);
         let src = _mm_set1_ph(1.0);
         let r = _mm_mask_sqrt_ph(src, 0b01010101, a);
@@ -22335,7 +22335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_sqrt_ph() {
+    fn test_mm_maskz_sqrt_ph() {
         let a = _mm_set1_ph(4.0);
         let r = _mm_maskz_sqrt_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0);
@@ -22343,7 +22343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_sqrt_ph() {
+    fn test_mm256_sqrt_ph() {
         let a = _mm256_set1_ph(4.0);
         let r = _mm256_sqrt_ph(a);
         let e = _mm256_set1_ph(2.0);
@@ -22351,7 +22351,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_sqrt_ph() {
+    fn test_mm256_mask_sqrt_ph() {
         let a = _mm256_set1_ph(4.0);
         let src = _mm256_set1_ph(1.0);
         let r = _mm256_mask_sqrt_ph(src, 0b0101010101010101, a);
@@ -22362,7 +22362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_sqrt_ph() {
+    fn test_mm256_maskz_sqrt_ph() {
         let a = _mm256_set1_ph(4.0);
         let r = _mm256_maskz_sqrt_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -22372,7 +22372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_sqrt_ph() {
+    fn test_mm512_sqrt_ph() {
         let a = _mm512_set1_ph(4.0);
         let r = _mm512_sqrt_ph(a);
         let e = _mm512_set1_ph(2.0);
@@ -22380,7 +22380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_sqrt_ph() {
+    fn test_mm512_mask_sqrt_ph() {
         let a = _mm512_set1_ph(4.0);
         let src = _mm512_set1_ph(1.0);
         let r = _mm512_mask_sqrt_ph(src, 0b01010101010101010101010101010101, a);
@@ -22392,7 +22392,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_sqrt_ph() {
+    fn test_mm512_maskz_sqrt_ph() {
         let a = _mm512_set1_ph(4.0);
         let r = _mm512_maskz_sqrt_ph(0b01010101010101010101010101010101, a);
         let e = _mm512_set_ph(
@@ -22403,7 +22403,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_sqrt_round_ph() {
+    fn test_mm512_sqrt_round_ph() {
         let a = _mm512_set1_ph(4.0);
         let r = _mm512_sqrt_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set1_ph(2.0);
@@ -22411,7 +22411,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_sqrt_round_ph() {
+    fn test_mm512_mask_sqrt_round_ph() {
         let a = _mm512_set1_ph(4.0);
         let src = _mm512_set1_ph(1.0);
         let r = _mm512_mask_sqrt_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -22427,7 +22427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_sqrt_round_ph() {
+    fn test_mm512_maskz_sqrt_round_ph() {
         let a = _mm512_set1_ph(4.0);
         let r = _mm512_maskz_sqrt_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01010101010101010101010101010101,
@@ -22441,7 +22441,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_sqrt_sh() {
+    fn test_mm_sqrt_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let r = _mm_sqrt_sh(a, b);
@@ -22450,7 +22450,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_sqrt_sh() {
+    fn test_mm_mask_sqrt_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22463,7 +22463,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_sqrt_sh() {
+    fn test_mm_maskz_sqrt_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let r = _mm_maskz_sqrt_sh(0, a, b);
@@ -22475,7 +22475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_sqrt_round_sh() {
+    fn test_mm_sqrt_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let r = _mm_sqrt_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -22484,7 +22484,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_sqrt_round_sh() {
+    fn test_mm_mask_sqrt_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22501,7 +22501,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_sqrt_round_sh() {
+    fn test_mm_maskz_sqrt_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(4.0, 40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0);
         let r =
@@ -22515,7 +22515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_max_ph() {
+    fn test_mm_max_ph() {
         let a = _mm_set1_ph(2.0);
         let b = _mm_set1_ph(1.0);
         let r = _mm_max_ph(a, b);
@@ -22524,7 +22524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_max_ph() {
+    fn test_mm_mask_max_ph() {
         let a = _mm_set1_ph(2.0);
         let b = _mm_set1_ph(1.0);
         let src = _mm_set1_ph(3.0);
@@ -22534,7 +22534,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_max_ph() {
+    fn test_mm_maskz_max_ph() {
         let a = _mm_set1_ph(2.0);
         let b = _mm_set1_ph(1.0);
         let r = _mm_maskz_max_ph(0b01010101, a, b);
@@ -22543,7 +22543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_max_ph() {
+    fn test_mm256_max_ph() {
         let a = _mm256_set1_ph(2.0);
         let b = _mm256_set1_ph(1.0);
         let r = _mm256_max_ph(a, b);
@@ -22552,7 +22552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_max_ph() {
+    fn test_mm256_mask_max_ph() {
         let a = _mm256_set1_ph(2.0);
         let b = _mm256_set1_ph(1.0);
         let src = _mm256_set1_ph(3.0);
@@ -22564,7 +22564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_max_ph() {
+    fn test_mm256_maskz_max_ph() {
         let a = _mm256_set1_ph(2.0);
         let b = _mm256_set1_ph(1.0);
         let r = _mm256_maskz_max_ph(0b0101010101010101, a, b);
@@ -22575,7 +22575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_max_ph() {
+    fn test_mm512_max_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_max_ph(a, b);
@@ -22584,7 +22584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_max_ph() {
+    fn test_mm512_mask_max_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let src = _mm512_set1_ph(3.0);
@@ -22597,7 +22597,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_max_ph() {
+    fn test_mm512_maskz_max_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_maskz_max_ph(0b01010101010101010101010101010101, a, b);
@@ -22609,7 +22609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_max_round_ph() {
+    fn test_mm512_max_round_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_max_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -22618,7 +22618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_max_round_ph() {
+    fn test_mm512_mask_max_round_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let src = _mm512_set1_ph(3.0);
@@ -22636,7 +22636,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_max_round_ph() {
+    fn test_mm512_maskz_max_round_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_maskz_max_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -22652,7 +22652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_max_sh() {
+    fn test_mm_max_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_max_sh(a, b);
@@ -22661,7 +22661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_max_sh() {
+    fn test_mm_mask_max_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22674,7 +22674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_max_sh() {
+    fn test_mm_maskz_max_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_maskz_max_sh(0, a, b);
@@ -22686,7 +22686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_max_round_sh() {
+    fn test_mm_max_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_max_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -22695,7 +22695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_max_round_sh() {
+    fn test_mm_mask_max_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22712,7 +22712,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_max_round_sh() {
+    fn test_mm_maskz_max_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r =
@@ -22726,7 +22726,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_min_ph() {
+    fn test_mm_min_ph() {
         let a = _mm_set1_ph(2.0);
         let b = _mm_set1_ph(1.0);
         let r = _mm_min_ph(a, b);
@@ -22735,7 +22735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_min_ph() {
+    fn test_mm_mask_min_ph() {
         let a = _mm_set1_ph(2.0);
         let b = _mm_set1_ph(1.0);
         let src = _mm_set1_ph(3.0);
@@ -22745,7 +22745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_min_ph() {
+    fn test_mm_maskz_min_ph() {
         let a = _mm_set1_ph(2.0);
         let b = _mm_set1_ph(1.0);
         let r = _mm_maskz_min_ph(0b01010101, a, b);
@@ -22754,7 +22754,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_min_ph() {
+    fn test_mm256_min_ph() {
         let a = _mm256_set1_ph(2.0);
         let b = _mm256_set1_ph(1.0);
         let r = _mm256_min_ph(a, b);
@@ -22763,7 +22763,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_min_ph() {
+    fn test_mm256_mask_min_ph() {
         let a = _mm256_set1_ph(2.0);
         let b = _mm256_set1_ph(1.0);
         let src = _mm256_set1_ph(3.0);
@@ -22775,7 +22775,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_min_ph() {
+    fn test_mm256_maskz_min_ph() {
         let a = _mm256_set1_ph(2.0);
         let b = _mm256_set1_ph(1.0);
         let r = _mm256_maskz_min_ph(0b0101010101010101, a, b);
@@ -22786,7 +22786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_min_ph() {
+    fn test_mm512_min_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_min_ph(a, b);
@@ -22795,7 +22795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_min_ph() {
+    fn test_mm512_mask_min_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let src = _mm512_set1_ph(3.0);
@@ -22808,7 +22808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_min_ph() {
+    fn test_mm512_maskz_min_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_maskz_min_ph(0b01010101010101010101010101010101, a, b);
@@ -22820,7 +22820,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_min_round_ph() {
+    fn test_mm512_min_round_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_min_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -22829,7 +22829,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_min_round_ph() {
+    fn test_mm512_mask_min_round_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let src = _mm512_set1_ph(3.0);
@@ -22847,7 +22847,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_min_round_ph() {
+    fn test_mm512_maskz_min_round_ph() {
         let a = _mm512_set1_ph(2.0);
         let b = _mm512_set1_ph(1.0);
         let r = _mm512_maskz_min_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -22863,7 +22863,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_min_sh() {
+    fn test_mm_min_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_min_sh(a, b);
@@ -22872,7 +22872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_min_sh() {
+    fn test_mm_mask_min_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22885,7 +22885,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_min_sh() {
+    fn test_mm_maskz_min_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_maskz_min_sh(0, a, b);
@@ -22897,7 +22897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_min_round_sh() {
+    fn test_mm_min_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r = _mm_min_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -22906,7 +22906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_min_round_sh() {
+    fn test_mm_mask_min_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let src = _mm_setr_ph(3.0, 30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0);
@@ -22923,7 +22923,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_min_round_sh() {
+    fn test_mm_maskz_min_round_sh() {
         let a = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let b = _mm_setr_ph(2.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0);
         let r =
@@ -22937,7 +22937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_getexp_ph() {
+    fn test_mm_getexp_ph() {
         let a = _mm_set1_ph(3.0);
         let r = _mm_getexp_ph(a);
         let e = _mm_set1_ph(1.0);
@@ -22945,7 +22945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_getexp_ph() {
+    fn test_mm_mask_getexp_ph() {
         let a = _mm_set1_ph(3.0);
         let src = _mm_set1_ph(4.0);
         let r = _mm_mask_getexp_ph(src, 0b01010101, a);
@@ -22954,7 +22954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_getexp_ph() {
+    fn test_mm_maskz_getexp_ph() {
         let a = _mm_set1_ph(3.0);
         let r = _mm_maskz_getexp_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0);
@@ -22962,7 +22962,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_getexp_ph() {
+    fn test_mm256_getexp_ph() {
         let a = _mm256_set1_ph(3.0);
         let r = _mm256_getexp_ph(a);
         let e = _mm256_set1_ph(1.0);
@@ -22970,7 +22970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_getexp_ph() {
+    fn test_mm256_mask_getexp_ph() {
         let a = _mm256_set1_ph(3.0);
         let src = _mm256_set1_ph(4.0);
         let r = _mm256_mask_getexp_ph(src, 0b0101010101010101, a);
@@ -22981,7 +22981,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_getexp_ph() {
+    fn test_mm256_maskz_getexp_ph() {
         let a = _mm256_set1_ph(3.0);
         let r = _mm256_maskz_getexp_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -22991,7 +22991,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_getexp_ph() {
+    fn test_mm512_getexp_ph() {
         let a = _mm512_set1_ph(3.0);
         let r = _mm512_getexp_ph(a);
         let e = _mm512_set1_ph(1.0);
@@ -22999,7 +22999,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_getexp_ph() {
+    fn test_mm512_mask_getexp_ph() {
         let a = _mm512_set1_ph(3.0);
         let src = _mm512_set1_ph(4.0);
         let r = _mm512_mask_getexp_ph(src, 0b01010101010101010101010101010101, a);
@@ -23011,7 +23011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_getexp_ph() {
+    fn test_mm512_maskz_getexp_ph() {
         let a = _mm512_set1_ph(3.0);
         let r = _mm512_maskz_getexp_ph(0b01010101010101010101010101010101, a);
         let e = _mm512_set_ph(
@@ -23022,7 +23022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_getexp_round_ph() {
+    fn test_mm512_getexp_round_ph() {
         let a = _mm512_set1_ph(3.0);
         let r = _mm512_getexp_round_ph::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set1_ph(1.0);
@@ -23030,7 +23030,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_getexp_round_ph() {
+    fn test_mm512_mask_getexp_round_ph() {
         let a = _mm512_set1_ph(3.0);
         let src = _mm512_set1_ph(4.0);
         let r = _mm512_mask_getexp_round_ph::<_MM_FROUND_NO_EXC>(
@@ -23046,7 +23046,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_getexp_round_ph() {
+    fn test_mm512_maskz_getexp_round_ph() {
         let a = _mm512_set1_ph(3.0);
         let r = _mm512_maskz_getexp_round_ph::<_MM_FROUND_NO_EXC>(
             0b01010101010101010101010101010101,
@@ -23060,7 +23060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_getexp_sh() {
+    fn test_mm_getexp_sh() {
         let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_getexp_sh(a, b);
@@ -23069,7 +23069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_getexp_sh() {
+    fn test_mm_mask_getexp_sh() {
         let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(4.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23082,7 +23082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_getexp_sh() {
+    fn test_mm_maskz_getexp_sh() {
         let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_getexp_sh(0, a, b);
@@ -23094,7 +23094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_getexp_round_sh() {
+    fn test_mm_getexp_round_sh() {
         let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_getexp_round_sh::<_MM_FROUND_NO_EXC>(a, b);
@@ -23103,7 +23103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_getexp_round_sh() {
+    fn test_mm_mask_getexp_round_sh() {
         let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(4.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23116,7 +23116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_getexp_round_sh() {
+    fn test_mm_maskz_getexp_round_sh() {
         let a = _mm_setr_ph(4.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_getexp_round_sh::<_MM_FROUND_NO_EXC>(0, a, b);
@@ -23128,7 +23128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_getmant_ph() {
+    fn test_mm_getmant_ph() {
         let a = _mm_set1_ph(10.0);
         let r = _mm_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
         let e = _mm_set1_ph(1.25);
@@ -23136,7 +23136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_getmant_ph() {
+    fn test_mm_mask_getmant_ph() {
         let a = _mm_set1_ph(10.0);
         let src = _mm_set1_ph(20.0);
         let r = _mm_mask_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(src, 0b01010101, a);
@@ -23145,7 +23145,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_getmant_ph() {
+    fn test_mm_maskz_getmant_ph() {
         let a = _mm_set1_ph(10.0);
         let r = _mm_maskz_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(0b01010101, a);
         let e = _mm_set_ph(0.0, 1.25, 0.0, 1.25, 0.0, 1.25, 0.0, 1.25);
@@ -23153,7 +23153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_getmant_ph() {
+    fn test_mm256_getmant_ph() {
         let a = _mm256_set1_ph(10.0);
         let r = _mm256_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
         let e = _mm256_set1_ph(1.25);
@@ -23161,7 +23161,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_getmant_ph() {
+    fn test_mm256_mask_getmant_ph() {
         let a = _mm256_set1_ph(10.0);
         let src = _mm256_set1_ph(20.0);
         let r = _mm256_mask_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
@@ -23177,7 +23177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_getmant_ph() {
+    fn test_mm256_maskz_getmant_ph() {
         let a = _mm256_set1_ph(10.0);
         let r = _mm256_maskz_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
             0b0101010101010101,
@@ -23190,7 +23190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_getmant_ph() {
+    fn test_mm512_getmant_ph() {
         let a = _mm512_set1_ph(10.0);
         let r = _mm512_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a);
         let e = _mm512_set1_ph(1.25);
@@ -23198,7 +23198,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_getmant_ph() {
+    fn test_mm512_mask_getmant_ph() {
         let a = _mm512_set1_ph(10.0);
         let src = _mm512_set1_ph(20.0);
         let r = _mm512_mask_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
@@ -23215,7 +23215,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_getmant_ph() {
+    fn test_mm512_maskz_getmant_ph() {
         let a = _mm512_set1_ph(10.0);
         let r = _mm512_maskz_getmant_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(
             0b01010101010101010101010101010101,
@@ -23229,7 +23229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_getmant_round_ph() {
+    fn test_mm512_getmant_round_ph() {
         let a = _mm512_set1_ph(10.0);
         let r =
             _mm512_getmant_round_ph::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN, _MM_FROUND_NO_EXC>(
@@ -23240,7 +23240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_getmant_round_ph() {
+    fn test_mm512_mask_getmant_round_ph() {
         let a = _mm512_set1_ph(10.0);
         let src = _mm512_set1_ph(20.0);
         let r = _mm512_mask_getmant_round_ph::<
@@ -23257,7 +23257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_getmant_round_ph() {
+    fn test_mm512_maskz_getmant_round_ph() {
         let a = _mm512_set1_ph(10.0);
         let r = _mm512_maskz_getmant_round_ph::<
             _MM_MANT_NORM_P75_1P5,
@@ -23272,7 +23272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_getmant_sh() {
+    fn test_mm_getmant_sh() {
         let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a, b);
@@ -23281,7 +23281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_getmant_sh() {
+    fn test_mm_mask_getmant_sh() {
         let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(20.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23294,7 +23294,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_getmant_sh() {
+    fn test_mm_maskz_getmant_sh() {
         let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_getmant_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(0, a, b);
@@ -23306,7 +23306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_getmant_round_sh() {
+    fn test_mm_getmant_round_sh() {
         let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_getmant_round_sh::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN, _MM_FROUND_NO_EXC>(
@@ -23317,7 +23317,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_getmant_round_sh() {
+    fn test_mm_mask_getmant_round_sh() {
         let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(20.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23338,7 +23338,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_getmant_round_sh() {
+    fn test_mm_maskz_getmant_round_sh() {
         let a = _mm_setr_ph(15.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(10.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_getmant_round_sh::<
@@ -23358,7 +23358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_roundscale_ph() {
+    fn test_mm_roundscale_ph() {
         let a = _mm_set1_ph(1.1);
         let r = _mm_roundscale_ph::<0>(a);
         let e = _mm_set1_ph(1.0);
@@ -23366,7 +23366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_roundscale_ph() {
+    fn test_mm_mask_roundscale_ph() {
         let a = _mm_set1_ph(1.1);
         let src = _mm_set1_ph(2.0);
         let r = _mm_mask_roundscale_ph::<0>(src, 0b01010101, a);
@@ -23375,7 +23375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_roundscale_ph() {
+    fn test_mm_maskz_roundscale_ph() {
         let a = _mm_set1_ph(1.1);
         let r = _mm_maskz_roundscale_ph::<0>(0b01010101, a);
         let e = _mm_set_ph(0.0, 1.0, 0.0, 1.0, 0.0, 1.0, 0.0, 1.0);
@@ -23383,7 +23383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_roundscale_ph() {
+    fn test_mm256_roundscale_ph() {
         let a = _mm256_set1_ph(1.1);
         let r = _mm256_roundscale_ph::<0>(a);
         let e = _mm256_set1_ph(1.0);
@@ -23391,7 +23391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_roundscale_ph() {
+    fn test_mm256_mask_roundscale_ph() {
         let a = _mm256_set1_ph(1.1);
         let src = _mm256_set1_ph(2.0);
         let r = _mm256_mask_roundscale_ph::<0>(src, 0b0101010101010101, a);
@@ -23402,7 +23402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_roundscale_ph() {
+    fn test_mm256_maskz_roundscale_ph() {
         let a = _mm256_set1_ph(1.1);
         let r = _mm256_maskz_roundscale_ph::<0>(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -23412,7 +23412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_roundscale_ph() {
+    fn test_mm512_roundscale_ph() {
         let a = _mm512_set1_ph(1.1);
         let r = _mm512_roundscale_ph::<0>(a);
         let e = _mm512_set1_ph(1.0);
@@ -23420,7 +23420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_roundscale_ph() {
+    fn test_mm512_mask_roundscale_ph() {
         let a = _mm512_set1_ph(1.1);
         let src = _mm512_set1_ph(2.0);
         let r = _mm512_mask_roundscale_ph::<0>(src, 0b01010101010101010101010101010101, a);
@@ -23432,7 +23432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_roundscale_ph() {
+    fn test_mm512_maskz_roundscale_ph() {
         let a = _mm512_set1_ph(1.1);
         let r = _mm512_maskz_roundscale_ph::<0>(0b01010101010101010101010101010101, a);
         let e = _mm512_set_ph(
@@ -23443,7 +23443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_roundscale_round_ph() {
+    fn test_mm512_roundscale_round_ph() {
         let a = _mm512_set1_ph(1.1);
         let r = _mm512_roundscale_round_ph::<0, _MM_FROUND_NO_EXC>(a);
         let e = _mm512_set1_ph(1.0);
@@ -23451,7 +23451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_roundscale_round_ph() {
+    fn test_mm512_mask_roundscale_round_ph() {
         let a = _mm512_set1_ph(1.1);
         let src = _mm512_set1_ph(2.0);
         let r = _mm512_mask_roundscale_round_ph::<0, _MM_FROUND_NO_EXC>(
@@ -23467,7 +23467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_roundscale_round_ph() {
+    fn test_mm512_maskz_roundscale_round_ph() {
         let a = _mm512_set1_ph(1.1);
         let r = _mm512_maskz_roundscale_round_ph::<0, _MM_FROUND_NO_EXC>(
             0b01010101010101010101010101010101,
@@ -23481,7 +23481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_roundscale_sh() {
+    fn test_mm_roundscale_sh() {
         let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_roundscale_sh::<0>(a, b);
@@ -23490,7 +23490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_roundscale_sh() {
+    fn test_mm_mask_roundscale_sh() {
         let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23503,7 +23503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_roundscale_sh() {
+    fn test_mm_maskz_roundscale_sh() {
         let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_roundscale_sh::<0>(0, a, b);
@@ -23515,7 +23515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_roundscale_round_sh() {
+    fn test_mm_roundscale_round_sh() {
         let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(a, b);
@@ -23524,7 +23524,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_roundscale_round_sh() {
+    fn test_mm_mask_roundscale_round_sh() {
         let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(3.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23537,7 +23537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_roundscale_round_sh() {
+    fn test_mm_maskz_roundscale_round_sh() {
         let a = _mm_setr_ph(2.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.1, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_roundscale_round_sh::<0, _MM_FROUND_NO_EXC>(0, a, b);
@@ -23549,7 +23549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_scalef_ph() {
+    fn test_mm_scalef_ph() {
         let a = _mm_set1_ph(1.);
         let b = _mm_set1_ph(3.);
         let r = _mm_scalef_ph(a, b);
@@ -23558,7 +23558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_scalef_ph() {
+    fn test_mm_mask_scalef_ph() {
         let a = _mm_set1_ph(1.);
         let b = _mm_set1_ph(3.);
         let src = _mm_set1_ph(2.);
@@ -23568,7 +23568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_scalef_ph() {
+    fn test_mm_maskz_scalef_ph() {
         let a = _mm_set1_ph(1.);
         let b = _mm_set1_ph(3.);
         let r = _mm_maskz_scalef_ph(0b01010101, a, b);
@@ -23577,7 +23577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_scalef_ph() {
+    fn test_mm256_scalef_ph() {
         let a = _mm256_set1_ph(1.);
         let b = _mm256_set1_ph(3.);
         let r = _mm256_scalef_ph(a, b);
@@ -23586,7 +23586,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_scalef_ph() {
+    fn test_mm256_mask_scalef_ph() {
         let a = _mm256_set1_ph(1.);
         let b = _mm256_set1_ph(3.);
         let src = _mm256_set1_ph(2.);
@@ -23598,7 +23598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_scalef_ph() {
+    fn test_mm256_maskz_scalef_ph() {
         let a = _mm256_set1_ph(1.);
         let b = _mm256_set1_ph(3.);
         let r = _mm256_maskz_scalef_ph(0b0101010101010101, a, b);
@@ -23609,7 +23609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_scalef_ph() {
+    fn test_mm512_scalef_ph() {
         let a = _mm512_set1_ph(1.);
         let b = _mm512_set1_ph(3.);
         let r = _mm512_scalef_ph(a, b);
@@ -23618,7 +23618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_scalef_ph() {
+    fn test_mm512_mask_scalef_ph() {
         let a = _mm512_set1_ph(1.);
         let b = _mm512_set1_ph(3.);
         let src = _mm512_set1_ph(2.);
@@ -23631,7 +23631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_scalef_ph() {
+    fn test_mm512_maskz_scalef_ph() {
         let a = _mm512_set1_ph(1.);
         let b = _mm512_set1_ph(3.);
         let r = _mm512_maskz_scalef_ph(0b01010101010101010101010101010101, a, b);
@@ -23643,7 +23643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_scalef_round_ph() {
+    fn test_mm512_scalef_round_ph() {
         let a = _mm512_set1_ph(1.);
         let b = _mm512_set1_ph(3.);
         let r = _mm512_scalef_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -23652,7 +23652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_scalef_round_ph() {
+    fn test_mm512_mask_scalef_round_ph() {
         let a = _mm512_set1_ph(1.);
         let b = _mm512_set1_ph(3.);
         let src = _mm512_set1_ph(2.);
@@ -23670,7 +23670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_scalef_round_ph() {
+    fn test_mm512_maskz_scalef_round_ph() {
         let a = _mm512_set1_ph(1.);
         let b = _mm512_set1_ph(3.);
         let r = _mm512_maskz_scalef_round_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -23686,7 +23686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_scalef_sh() {
+    fn test_mm_scalef_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_scalef_sh(a, b);
@@ -23695,7 +23695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_scalef_sh() {
+    fn test_mm_mask_scalef_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23708,7 +23708,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_scalef_sh() {
+    fn test_mm_maskz_scalef_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_scalef_sh(0, a, b);
@@ -23720,7 +23720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_scalef_round_sh() {
+    fn test_mm_scalef_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_scalef_round_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -23729,7 +23729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_scalef_round_sh() {
+    fn test_mm_mask_scalef_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23746,7 +23746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_scalef_round_sh() {
+    fn test_mm_maskz_scalef_round_sh() {
         let a = _mm_setr_ph(1.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(3.0, 20., 21., 22., 23., 24., 25., 26.);
         let r =
@@ -23760,7 +23760,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_ph() {
+    fn test_mm_reduce_ph() {
         let a = _mm_set1_ph(1.25);
         let r = _mm_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm_set1_ph(0.25);
@@ -23768,7 +23768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_reduce_ph() {
+    fn test_mm_mask_reduce_ph() {
         let a = _mm_set1_ph(1.25);
         let src = _mm_set1_ph(2.0);
         let r = _mm_mask_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01010101, a);
@@ -23777,7 +23777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_reduce_ph() {
+    fn test_mm_maskz_reduce_ph() {
         let a = _mm_set1_ph(1.25);
         let r = _mm_maskz_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(0b01010101, a);
         let e = _mm_set_ph(0.0, 0.25, 0.0, 0.25, 0.0, 0.25, 0.0, 0.25);
@@ -23785,7 +23785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_reduce_ph() {
+    fn test_mm256_reduce_ph() {
         let a = _mm256_set1_ph(1.25);
         let r = _mm256_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm256_set1_ph(0.25);
@@ -23793,7 +23793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_reduce_ph() {
+    fn test_mm256_mask_reduce_ph() {
         let a = _mm256_set1_ph(1.25);
         let src = _mm256_set1_ph(2.0);
         let r = _mm256_mask_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0101010101010101, a);
@@ -23804,7 +23804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_reduce_ph() {
+    fn test_mm256_maskz_reduce_ph() {
         let a = _mm256_set1_ph(1.25);
         let r = _mm256_maskz_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -23814,7 +23814,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_reduce_ph() {
+    fn test_mm512_reduce_ph() {
         let a = _mm512_set1_ph(1.25);
         let r = _mm512_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(a);
         let e = _mm512_set1_ph(0.25);
@@ -23822,7 +23822,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_reduce_ph() {
+    fn test_mm512_mask_reduce_ph() {
         let a = _mm512_set1_ph(1.25);
         let src = _mm512_set1_ph(2.0);
         let r = _mm512_mask_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(
@@ -23838,7 +23838,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_reduce_ph() {
+    fn test_mm512_maskz_reduce_ph() {
         let a = _mm512_set1_ph(1.25);
         let r = _mm512_maskz_reduce_ph::<{ 16 | _MM_FROUND_TO_ZERO }>(
             0b01010101010101010101010101010101,
@@ -23852,7 +23852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_reduce_round_ph() {
+    fn test_mm512_reduce_round_ph() {
         let a = _mm512_set1_ph(1.25);
         let r = _mm512_reduce_round_ph::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a);
         let e = _mm512_set1_ph(0.25);
@@ -23860,7 +23860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_reduce_round_ph() {
+    fn test_mm512_mask_reduce_round_ph() {
         let a = _mm512_set1_ph(1.25);
         let src = _mm512_set1_ph(2.0);
         let r = _mm512_mask_reduce_round_ph::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
@@ -23876,7 +23876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_reduce_round_ph() {
+    fn test_mm512_maskz_reduce_round_ph() {
         let a = _mm512_set1_ph(1.25);
         let r = _mm512_maskz_reduce_round_ph::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(
             0b01010101010101010101010101010101,
@@ -23890,7 +23890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_sh() {
+    fn test_mm_reduce_sh() {
         let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(a, b);
@@ -23899,7 +23899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_reduce_sh() {
+    fn test_mm_mask_reduce_sh() {
         let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23912,7 +23912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_reduce_sh() {
+    fn test_mm_maskz_reduce_sh() {
         let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_maskz_reduce_sh::<{ 16 | _MM_FROUND_TO_ZERO }>(0, a, b);
@@ -23924,7 +23924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_round_sh() {
+    fn test_mm_reduce_round_sh() {
         let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
         let r = _mm_reduce_round_sh::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>(a, b);
@@ -23933,7 +23933,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_reduce_round_sh() {
+    fn test_mm_mask_reduce_round_sh() {
         let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
         let src = _mm_setr_ph(2.0, 30., 31., 32., 33., 34., 35., 36.);
@@ -23950,7 +23950,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_reduce_round_sh() {
+    fn test_mm_maskz_reduce_round_sh() {
         let a = _mm_setr_ph(3.0, 10., 11., 12., 13., 14., 15., 16.);
         let b = _mm_setr_ph(1.25, 20., 21., 22., 23., 24., 25., 26.);
         let r =
@@ -23964,56 +23964,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_reduce_add_ph() {
+    const fn test_mm_reduce_add_ph() {
         let a = _mm_set1_ph(2.0);
         let r = _mm_reduce_add_ph(a);
         assert_eq!(r, 16.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_reduce_add_ph() {
+    const fn test_mm256_reduce_add_ph() {
         let a = _mm256_set1_ph(2.0);
         let r = _mm256_reduce_add_ph(a);
         assert_eq!(r, 32.0);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_reduce_add_ph() {
+    const fn test_mm512_reduce_add_ph() {
         let a = _mm512_set1_ph(2.0);
         let r = _mm512_reduce_add_ph(a);
         assert_eq!(r, 64.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_reduce_mul_ph() {
+    const fn test_mm_reduce_mul_ph() {
         let a = _mm_set1_ph(2.0);
         let r = _mm_reduce_mul_ph(a);
         assert_eq!(r, 256.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_reduce_mul_ph() {
+    const fn test_mm256_reduce_mul_ph() {
         let a = _mm256_set1_ph(2.0);
         let r = _mm256_reduce_mul_ph(a);
         assert_eq!(r, 65536.0);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_reduce_mul_ph() {
+    const fn test_mm512_reduce_mul_ph() {
         let a = _mm512_set1_ph(2.0);
         let r = _mm512_reduce_mul_ph(a);
         assert_eq!(r, 16777216.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_max_ph() {
+    fn test_mm_reduce_max_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_reduce_max_ph(a);
         assert_eq!(r, 8.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_reduce_max_ph() {
+    fn test_mm256_reduce_max_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -24022,7 +24022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_reduce_max_ph() {
+    fn test_mm512_reduce_max_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -24033,14 +24033,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_reduce_min_ph() {
+    fn test_mm_reduce_min_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_reduce_min_ph(a);
         assert_eq!(r, 1.0);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_reduce_min_ph() {
+    fn test_mm256_reduce_min_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -24049,7 +24049,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_reduce_min_ph() {
+    fn test_mm512_reduce_min_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -24060,7 +24060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_fpclass_ph_mask() {
+    fn test_mm_fpclass_ph_mask() {
         let a = _mm_set_ph(
             1.,
             f16::INFINITY,
@@ -24076,7 +24076,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_fpclass_ph_mask() {
+    fn test_mm_mask_fpclass_ph_mask() {
         let a = _mm_set_ph(
             1.,
             f16::INFINITY,
@@ -24092,7 +24092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_fpclass_ph_mask() {
+    fn test_mm256_fpclass_ph_mask() {
         let a = _mm256_set_ph(
             1.,
             f16::INFINITY,
@@ -24116,7 +24116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_fpclass_ph_mask() {
+    fn test_mm256_mask_fpclass_ph_mask() {
         let a = _mm256_set_ph(
             1.,
             f16::INFINITY,
@@ -24140,7 +24140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_fpclass_ph_mask() {
+    fn test_mm512_fpclass_ph_mask() {
         let a = _mm512_set_ph(
             1.,
             f16::INFINITY,
@@ -24180,7 +24180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_fpclass_ph_mask() {
+    fn test_mm512_mask_fpclass_ph_mask() {
         let a = _mm512_set_ph(
             1.,
             f16::INFINITY,
@@ -24220,14 +24220,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_fpclass_sh_mask() {
+    fn test_mm_fpclass_sh_mask() {
         let a = _mm_set_sh(f16::INFINITY);
         let r = _mm_fpclass_sh_mask::<0x18>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_fpclass_sh_mask() {
+    fn test_mm_mask_fpclass_sh_mask() {
         let a = _mm_set_sh(f16::INFINITY);
         let r = _mm_mask_fpclass_sh_mask::<0x18>(0, a);
         assert_eq!(r, 0);
@@ -24236,7 +24236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_mask_blend_ph() {
+    const fn test_mm_mask_blend_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_set_ph(-1.0, -2.0, -3.0, -4.0, -5.0, -6.0, -7.0, -8.0);
         let r = _mm_mask_blend_ph(0b01010101, a, b);
@@ -24245,7 +24245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_ph() {
+    const fn test_mm256_mask_blend_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -24262,7 +24262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_mask_blend_ph() {
+    const fn test_mm512_mask_blend_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -24283,7 +24283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_permutex2var_ph() {
+    fn test_mm_permutex2var_ph() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let b = _mm_setr_ph(9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let idx = _mm_setr_epi16(0, 2, 4, 6, 8, 10, 12, 14);
@@ -24293,7 +24293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_permutex2var_ph() {
+    fn test_mm256_permutex2var_ph() {
         let a = _mm256_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -24311,7 +24311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_permutex2var_ph() {
+    fn test_mm512_permutex2var_ph() {
         let a = _mm512_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -24336,7 +24336,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_permutexvar_ph() {
+    fn test_mm_permutexvar_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let idx = _mm_set_epi16(0, 2, 4, 6, 1, 3, 5, 7);
         let r = _mm_permutexvar_ph(idx, a);
@@ -24345,7 +24345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_permutexvar_ph() {
+    fn test_mm256_permutexvar_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -24358,7 +24358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_permutexvar_ph() {
+    fn test_mm512_permutexvar_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -24378,7 +24378,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtepi16_ph() {
+    fn test_mm_cvtepi16_ph() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_cvtepi16_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24386,7 +24386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi16_ph() {
+    fn test_mm_mask_cvtepi16_ph() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtepi16_ph(src, 0b01010101, a);
@@ -24395,7 +24395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi16_ph() {
+    fn test_mm_maskz_cvtepi16_ph() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_maskz_cvtepi16_ph(0b01010101, a);
         let e = _mm_set_ph(0., 2., 0., 4., 0., 6., 0., 8.);
@@ -24403,7 +24403,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtepi16_ph() {
+    fn test_mm256_cvtepi16_ph() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm256_cvtepi16_ph(a);
         let e = _mm256_set_ph(
@@ -24413,7 +24413,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi16_ph() {
+    fn test_mm256_mask_cvtepi16_ph() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
             10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
@@ -24426,7 +24426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi16_ph() {
+    fn test_mm256_maskz_cvtepi16_ph() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm256_maskz_cvtepi16_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -24436,7 +24436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtepi16_ph() {
+    fn test_mm512_cvtepi16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24451,7 +24451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtepi16_ph() {
+    fn test_mm512_mask_cvtepi16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24469,7 +24469,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtepi16_ph() {
+    fn test_mm512_maskz_cvtepi16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24483,7 +24483,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundepi16_ph() {
+    fn test_mm512_cvt_roundepi16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24498,7 +24498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundepi16_ph() {
+    fn test_mm512_mask_cvt_roundepi16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24520,7 +24520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundepi16_ph() {
+    fn test_mm512_maskz_cvt_roundepi16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24537,7 +24537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtepu16_ph() {
+    fn test_mm_cvtepu16_ph() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_cvtepu16_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24545,7 +24545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu16_ph() {
+    fn test_mm_mask_cvtepu16_ph() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtepu16_ph(src, 0b01010101, a);
@@ -24554,7 +24554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu16_ph() {
+    fn test_mm_maskz_cvtepu16_ph() {
         let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_maskz_cvtepu16_ph(0b01010101, a);
         let e = _mm_set_ph(0., 2., 0., 4., 0., 6., 0., 8.);
@@ -24562,7 +24562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtepu16_ph() {
+    fn test_mm256_cvtepu16_ph() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm256_cvtepu16_ph(a);
         let e = _mm256_set_ph(
@@ -24572,7 +24572,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu16_ph() {
+    fn test_mm256_mask_cvtepu16_ph() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
             10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
@@ -24585,7 +24585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu16_ph() {
+    fn test_mm256_maskz_cvtepu16_ph() {
         let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm256_maskz_cvtepu16_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -24595,7 +24595,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtepu16_ph() {
+    fn test_mm512_cvtepu16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24610,7 +24610,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtepu16_ph() {
+    fn test_mm512_mask_cvtepu16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24628,7 +24628,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtepu16_ph() {
+    fn test_mm512_maskz_cvtepu16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24642,7 +24642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundepu16_ph() {
+    fn test_mm512_cvt_roundepu16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24657,7 +24657,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundepu16_ph() {
+    fn test_mm512_mask_cvt_roundepu16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24679,7 +24679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundepu16_ph() {
+    fn test_mm512_maskz_cvt_roundepu16_ph() {
         let a = _mm512_set_epi16(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
             25, 26, 27, 28, 29, 30, 31, 32,
@@ -24696,7 +24696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtepi32_ph() {
+    fn test_mm_cvtepi32_ph() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_cvtepi32_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
@@ -24704,7 +24704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_ph() {
+    fn test_mm_mask_cvtepi32_ph() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtepi32_ph(src, 0b0101, a);
@@ -24713,7 +24713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi32_ph() {
+    fn test_mm_maskz_cvtepi32_ph() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_cvtepi32_ph(0b0101, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2., 0.0, 4.);
@@ -24721,7 +24721,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtepi32_ph() {
+    fn test_mm256_cvtepi32_ph() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_cvtepi32_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24729,7 +24729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_ph() {
+    fn test_mm256_mask_cvtepi32_ph() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm256_mask_cvtepi32_ph(src, 0b01010101, a);
@@ -24738,7 +24738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi32_ph() {
+    fn test_mm256_maskz_cvtepi32_ph() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_cvtepi32_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
@@ -24746,7 +24746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtepi32_ph() {
+    fn test_mm512_cvtepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvtepi32_ph(a);
         let e = _mm256_set_ph(
@@ -24756,7 +24756,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtepi32_ph() {
+    fn test_mm512_mask_cvtepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
             10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
@@ -24769,7 +24769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtepi32_ph() {
+    fn test_mm512_maskz_cvtepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvtepi32_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -24779,7 +24779,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvt_roundepi32_ph() {
+    fn test_mm512_cvt_roundepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm256_set_ph(
@@ -24789,7 +24789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvt_roundepi32_ph() {
+    fn test_mm512_mask_cvt_roundepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
             10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
@@ -24806,7 +24806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvt_roundepi32_ph() {
+    fn test_mm512_maskz_cvt_roundepi32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvt_roundepi32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b0101010101010101,
@@ -24819,7 +24819,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvti32_sh() {
+    fn test_mm_cvti32_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvti32_sh(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24827,7 +24827,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvt_roundi32_sh() {
+    fn test_mm_cvt_roundi32_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundi32_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24835,7 +24835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtepu32_ph() {
+    fn test_mm_cvtepu32_ph() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_cvtepu32_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
@@ -24843,7 +24843,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu32_ph() {
+    fn test_mm_mask_cvtepu32_ph() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtepu32_ph(src, 0b0101, a);
@@ -24852,7 +24852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu32_ph() {
+    fn test_mm_maskz_cvtepu32_ph() {
         let a = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_cvtepu32_ph(0b0101, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2., 0.0, 4.);
@@ -24860,7 +24860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtepu32_ph() {
+    fn test_mm256_cvtepu32_ph() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_cvtepu32_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24868,7 +24868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu32_ph() {
+    fn test_mm256_mask_cvtepu32_ph() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm256_mask_cvtepu32_ph(src, 0b01010101, a);
@@ -24877,7 +24877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu32_ph() {
+    fn test_mm256_maskz_cvtepu32_ph() {
         let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_cvtepu32_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
@@ -24885,7 +24885,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvtepu32_ph() {
+    fn test_mm512_cvtepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvtepu32_ph(a);
         let e = _mm256_set_ph(
@@ -24895,7 +24895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtepu32_ph() {
+    fn test_mm512_mask_cvtepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
             10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
@@ -24908,7 +24908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtepu32_ph() {
+    fn test_mm512_maskz_cvtepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvtepu32_ph(0b0101010101010101, a);
         let e = _mm256_set_ph(
@@ -24918,7 +24918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvt_roundepu32_ph() {
+    fn test_mm512_cvt_roundepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm256_set_ph(
@@ -24928,7 +24928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvt_roundepu32_ph() {
+    fn test_mm512_mask_cvt_roundepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let src = _mm256_set_ph(
             10., 11., 12., 13., 14., 15., 16., 17., 18., 19., 20., 21., 22., 23., 24., 25.,
@@ -24946,7 +24946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvt_roundepu32_ph() {
+    fn test_mm512_maskz_cvt_roundepu32_ph() {
         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_cvt_roundepu32_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b0101010101010101,
@@ -24959,7 +24959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtu32_sh() {
+    fn test_mm_cvtu32_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtu32_sh(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24967,7 +24967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvt_roundu32_sh() {
+    fn test_mm_cvt_roundu32_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundu32_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -24975,7 +24975,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtepi64_ph() {
+    fn test_mm_cvtepi64_ph() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_cvtepi64_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
@@ -24983,7 +24983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_ph() {
+    fn test_mm_mask_cvtepi64_ph() {
         let a = _mm_set_epi64x(1, 2);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtepi64_ph(src, 0b01, a);
@@ -24992,7 +24992,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi64_ph() {
+    fn test_mm_maskz_cvtepi64_ph() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_maskz_cvtepi64_ph(0b01, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.);
@@ -25000,7 +25000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtepi64_ph() {
+    fn test_mm256_cvtepi64_ph() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepi64_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
@@ -25008,7 +25008,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_ph() {
+    fn test_mm256_mask_cvtepi64_ph() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm256_mask_cvtepi64_ph(src, 0b0101, a);
@@ -25017,7 +25017,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi64_ph() {
+    fn test_mm256_maskz_cvtepi64_ph() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepi64_ph(0b0101, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
@@ -25025,7 +25025,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvtepi64_ph() {
+    fn test_mm512_cvtepi64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvtepi64_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25033,7 +25033,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtepi64_ph() {
+    fn test_mm512_mask_cvtepi64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm512_mask_cvtepi64_ph(src, 0b01010101, a);
@@ -25042,7 +25042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtepi64_ph() {
+    fn test_mm512_maskz_cvtepi64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvtepi64_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
@@ -25050,7 +25050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvt_roundepi64_ph() {
+    fn test_mm512_cvt_roundepi64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvt_roundepi64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25058,7 +25058,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundepi64_ph() {
+    fn test_mm512_mask_cvt_roundepi64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm512_mask_cvt_roundepi64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -25069,7 +25069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvt_roundepi64_ph() {
+    fn test_mm512_maskz_cvt_roundepi64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvt_roundepi64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01010101, a,
@@ -25079,7 +25079,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtepu64_ph() {
+    fn test_mm_cvtepu64_ph() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_cvtepu64_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
@@ -25087,7 +25087,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtepu64_ph() {
+    fn test_mm_mask_cvtepu64_ph() {
         let a = _mm_set_epi64x(1, 2);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtepu64_ph(src, 0b01, a);
@@ -25096,7 +25096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepu64_ph() {
+    fn test_mm_maskz_cvtepu64_ph() {
         let a = _mm_set_epi64x(1, 2);
         let r = _mm_maskz_cvtepu64_ph(0b01, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.0);
@@ -25104,7 +25104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtepu64_ph() {
+    fn test_mm256_cvtepu64_ph() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepu64_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
@@ -25112,7 +25112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepu64_ph() {
+    fn test_mm256_mask_cvtepu64_ph() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm256_mask_cvtepu64_ph(src, 0b0101, a);
@@ -25121,7 +25121,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepu64_ph() {
+    fn test_mm256_maskz_cvtepu64_ph() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepu64_ph(0b0101, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
@@ -25129,7 +25129,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvtepu64_ph() {
+    fn test_mm512_cvtepu64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvtepu64_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25137,7 +25137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtepu64_ph() {
+    fn test_mm512_mask_cvtepu64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm512_mask_cvtepu64_ph(src, 0b01010101, a);
@@ -25146,7 +25146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtepu64_ph() {
+    fn test_mm512_maskz_cvtepu64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvtepu64_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
@@ -25154,7 +25154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvt_roundepu64_ph() {
+    fn test_mm512_cvt_roundepu64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_cvt_roundepu64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25162,7 +25162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvt_roundepu64_ph() {
+    fn test_mm512_mask_cvt_roundepu64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm512_mask_cvt_roundepu64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -25173,7 +25173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvt_roundepu64_ph() {
+    fn test_mm512_maskz_cvt_roundepu64_ph() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_cvt_roundepu64_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01010101, a,
@@ -25183,7 +25183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtxps_ph() {
+    fn test_mm_cvtxps_ph() {
         let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtxps_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
@@ -25191,7 +25191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtxps_ph() {
+    fn test_mm_mask_cvtxps_ph() {
         let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtxps_ph(src, 0b0101, a);
@@ -25200,7 +25200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtxps_ph() {
+    fn test_mm_maskz_cvtxps_ph() {
         let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvtxps_ph(0b0101, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
@@ -25208,7 +25208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtxps_ph() {
+    fn test_mm256_cvtxps_ph() {
         let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvtxps_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25216,7 +25216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtxps_ph() {
+    fn test_mm256_mask_cvtxps_ph() {
         let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm256_mask_cvtxps_ph(src, 0b01010101, a);
@@ -25225,7 +25225,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtxps_ph() {
+    fn test_mm256_maskz_cvtxps_ph() {
         let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_maskz_cvtxps_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
@@ -25233,7 +25233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvtxps_ph() {
+    fn test_mm512_cvtxps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25245,7 +25245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtxps_ph() {
+    fn test_mm512_mask_cvtxps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25260,7 +25260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtxps_ph() {
+    fn test_mm512_maskz_cvtxps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25272,7 +25272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvtx_roundps_ph() {
+    fn test_mm512_cvtx_roundps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25284,7 +25284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtx_roundps_ph() {
+    fn test_mm512_mask_cvtx_roundps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25304,7 +25304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtx_roundps_ph() {
+    fn test_mm512_maskz_cvtx_roundps_ph() {
         let a = _mm512_set_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25319,7 +25319,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtss_sh() {
+    fn test_mm_cvtss_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtss_sh(a, b);
@@ -25328,7 +25328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtss_sh() {
+    fn test_mm_mask_cvtss_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
@@ -25341,7 +25341,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtss_sh() {
+    fn test_mm_maskz_cvtss_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvtss_sh(0, a, b);
@@ -25353,7 +25353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvt_roundss_sh() {
+    fn test_mm_cvt_roundss_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvt_roundss_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -25362,7 +25362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvt_roundss_sh() {
+    fn test_mm_mask_cvt_roundss_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
@@ -25379,7 +25379,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvt_roundss_sh() {
+    fn test_mm_maskz_cvt_roundss_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r =
@@ -25393,7 +25393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtpd_ph() {
+    fn test_mm_cvtpd_ph() {
         let a = _mm_set_pd(1.0, 2.0);
         let r = _mm_cvtpd_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
@@ -25401,7 +25401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtpd_ph() {
+    fn test_mm_mask_cvtpd_ph() {
         let a = _mm_set_pd(1.0, 2.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm_mask_cvtpd_ph(src, 0b01, a);
@@ -25410,7 +25410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpd_ph() {
+    fn test_mm_maskz_cvtpd_ph() {
         let a = _mm_set_pd(1.0, 2.0);
         let r = _mm_maskz_cvtpd_ph(0b01, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.0);
@@ -25418,7 +25418,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtpd_ph() {
+    fn test_mm256_cvtpd_ph() {
         let a = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
         let r = _mm256_cvtpd_ph(a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
@@ -25426,7 +25426,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpd_ph() {
+    fn test_mm256_mask_cvtpd_ph() {
         let a = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm256_mask_cvtpd_ph(src, 0b0101, a);
@@ -25435,7 +25435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpd_ph() {
+    fn test_mm256_maskz_cvtpd_ph() {
         let a = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
         let r = _mm256_maskz_cvtpd_ph(0b0101, a);
         let e = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 0.0, 4.0);
@@ -25443,7 +25443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvtpd_ph() {
+    fn test_mm512_cvtpd_ph() {
         let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvtpd_ph(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25451,7 +25451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvtpd_ph() {
+    fn test_mm512_mask_cvtpd_ph() {
         let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm512_mask_cvtpd_ph(src, 0b01010101, a);
@@ -25460,7 +25460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvtpd_ph() {
+    fn test_mm512_maskz_cvtpd_ph() {
         let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvtpd_ph(0b01010101, a);
         let e = _mm_set_ph(0.0, 2., 0.0, 4., 0.0, 6., 0.0, 8.);
@@ -25468,7 +25468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_cvt_roundpd_ph() {
+    fn test_mm512_cvt_roundpd_ph() {
         let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvt_roundpd_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -25476,7 +25476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_mask_cvt_roundpd_ph() {
+    fn test_mm512_mask_cvt_roundpd_ph() {
         let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let r = _mm512_mask_cvt_roundpd_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -25487,7 +25487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm512_maskz_cvt_roundpd_ph() {
+    fn test_mm512_maskz_cvt_roundpd_ph() {
         let a = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvt_roundpd_ph::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01010101, a,
@@ -25497,7 +25497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtsd_sh() {
+    fn test_mm_cvtsd_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_pd(1.0, 2.0);
         let r = _mm_cvtsd_sh(a, b);
@@ -25506,7 +25506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtsd_sh() {
+    fn test_mm_mask_cvtsd_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_pd(1.0, 2.0);
         let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
@@ -25519,7 +25519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsd_sh() {
+    fn test_mm_maskz_cvtsd_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_pd(1.0, 2.0);
         let r = _mm_maskz_cvtsd_sh(0, a, b);
@@ -25531,7 +25531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvt_roundsd_sh() {
+    fn test_mm_cvt_roundsd_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_pd(1.0, 2.0);
         let r = _mm_cvt_roundsd_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -25540,7 +25540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvt_roundsd_sh() {
+    fn test_mm_mask_cvt_roundsd_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_pd(1.0, 2.0);
         let src = _mm_setr_ph(20., 21., 22., 23., 24., 25., 26., 27.);
@@ -25557,7 +25557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvt_roundsd_sh() {
+    fn test_mm_maskz_cvt_roundsd_sh() {
         let a = _mm_setr_ph(10., 11., 12., 13., 14., 15., 16., 17.);
         let b = _mm_setr_pd(1.0, 2.0);
         let r =
@@ -25571,7 +25571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_epi16() {
+    fn test_mm_cvtph_epi16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttph_epi16(a);
         let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
@@ -25579,7 +25579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_epi16() {
+    fn test_mm_mask_cvtph_epi16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm_mask_cvttph_epi16(src, 0b01010101, a);
@@ -25588,7 +25588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_epi16() {
+    fn test_mm_maskz_cvtph_epi16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_maskz_cvttph_epi16(0b01010101, a);
         let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
@@ -25596,7 +25596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_epi16() {
+    fn test_mm256_cvtph_epi16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25606,7 +25606,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_epi16() {
+    fn test_mm256_mask_cvtph_epi16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25619,7 +25619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_epi16() {
+    fn test_mm256_maskz_cvtph_epi16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25629,7 +25629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_epi16() {
+    fn test_mm512_cvtph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25644,7 +25644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_epi16() {
+    fn test_mm512_mask_cvtph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25663,7 +25663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_epi16() {
+    fn test_mm512_maskz_cvtph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25678,7 +25678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_epi16() {
+    fn test_mm512_cvt_roundph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25693,7 +25693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_epi16() {
+    fn test_mm512_mask_cvt_roundph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25716,7 +25716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_epi16() {
+    fn test_mm512_maskz_cvt_roundph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25734,7 +25734,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_epu16() {
+    fn test_mm_cvtph_epu16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttph_epu16(a);
         let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
@@ -25742,7 +25742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_epu16() {
+    fn test_mm_mask_cvtph_epu16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm_mask_cvttph_epu16(src, 0b01010101, a);
@@ -25751,7 +25751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_epu16() {
+    fn test_mm_maskz_cvtph_epu16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_maskz_cvttph_epu16(0b01010101, a);
         let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
@@ -25759,7 +25759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_epu16() {
+    fn test_mm256_cvtph_epu16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25769,7 +25769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_epu16() {
+    fn test_mm256_mask_cvtph_epu16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25782,7 +25782,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_epu16() {
+    fn test_mm256_maskz_cvtph_epu16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25792,7 +25792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_epu16() {
+    fn test_mm512_cvtph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25807,7 +25807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_epu16() {
+    fn test_mm512_mask_cvtph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25826,7 +25826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_epu16() {
+    fn test_mm512_maskz_cvtph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25841,7 +25841,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_epu16() {
+    fn test_mm512_cvt_roundph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25856,7 +25856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_epu16() {
+    fn test_mm512_mask_cvt_roundph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25879,7 +25879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_epu16() {
+    fn test_mm512_maskz_cvt_roundph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25897,7 +25897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvttph_epi16() {
+    fn test_mm_cvttph_epi16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttph_epi16(a);
         let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
@@ -25905,7 +25905,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvttph_epi16() {
+    fn test_mm_mask_cvttph_epi16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm_mask_cvttph_epi16(src, 0b01010101, a);
@@ -25914,7 +25914,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvttph_epi16() {
+    fn test_mm_maskz_cvttph_epi16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_maskz_cvttph_epi16(0b01010101, a);
         let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
@@ -25922,7 +25922,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvttph_epi16() {
+    fn test_mm256_cvttph_epi16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25932,7 +25932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvttph_epi16() {
+    fn test_mm256_mask_cvttph_epi16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25945,7 +25945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttph_epi16() {
+    fn test_mm256_maskz_cvttph_epi16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -25955,7 +25955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvttph_epi16() {
+    fn test_mm512_cvttph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25970,7 +25970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvttph_epi16() {
+    fn test_mm512_mask_cvttph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -25989,7 +25989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvttph_epi16() {
+    fn test_mm512_maskz_cvttph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26004,7 +26004,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtt_roundph_epi16() {
+    fn test_mm512_cvtt_roundph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26019,7 +26019,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtt_roundph_epi16() {
+    fn test_mm512_mask_cvtt_roundph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26042,7 +26042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtt_roundph_epi16() {
+    fn test_mm512_maskz_cvtt_roundph_epi16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26060,7 +26060,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvttph_epu16() {
+    fn test_mm_cvttph_epu16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttph_epu16(a);
         let e = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26068,7 +26068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvttph_epu16() {
+    fn test_mm_mask_cvttph_epu16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm_set_epi16(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm_mask_cvttph_epu16(src, 0b01010101, a);
@@ -26077,7 +26077,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvttph_epu16() {
+    fn test_mm_maskz_cvttph_epu16() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_maskz_cvttph_epu16(0b01010101, a);
         let e = _mm_set_epi16(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26085,7 +26085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvttph_epu16() {
+    fn test_mm256_cvttph_epu16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26095,7 +26095,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvttph_epu16() {
+    fn test_mm256_mask_cvttph_epu16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26108,7 +26108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttph_epu16() {
+    fn test_mm256_maskz_cvttph_epu16() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26118,7 +26118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvttph_epu16() {
+    fn test_mm512_cvttph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26133,7 +26133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvttph_epu16() {
+    fn test_mm512_mask_cvttph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26152,7 +26152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvttph_epu16() {
+    fn test_mm512_maskz_cvttph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26167,7 +26167,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtt_roundph_epu16() {
+    fn test_mm512_cvtt_roundph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26182,7 +26182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtt_roundph_epu16() {
+    fn test_mm512_mask_cvtt_roundph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26205,7 +26205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtt_roundph_epu16() {
+    fn test_mm512_maskz_cvtt_roundph_epu16() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -26223,7 +26223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_epi32() {
+    fn test_mm_cvtph_epi32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtph_epi32(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -26231,7 +26231,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_epi32() {
+    fn test_mm_mask_cvtph_epi32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let src = _mm_set_epi32(10, 11, 12, 13);
         let r = _mm_mask_cvtph_epi32(src, 0b0101, a);
@@ -26240,7 +26240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_epi32() {
+    fn test_mm_maskz_cvtph_epi32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvtph_epi32(0b0101, a);
         let e = _mm_set_epi32(0, 2, 0, 4);
@@ -26248,7 +26248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_epi32() {
+    fn test_mm256_cvtph_epi32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvtph_epi32(a);
         let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26256,7 +26256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_epi32() {
+    fn test_mm256_mask_cvtph_epi32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm256_mask_cvtph_epi32(src, 0b01010101, a);
@@ -26265,7 +26265,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_epi32() {
+    fn test_mm256_maskz_cvtph_epi32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_maskz_cvtph_epi32(0b01010101, a);
         let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26273,7 +26273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_epi32() {
+    fn test_mm512_cvtph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26283,7 +26283,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_epi32() {
+    fn test_mm512_mask_cvtph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26296,7 +26296,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_epi32() {
+    fn test_mm512_maskz_cvtph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26306,7 +26306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_epi32() {
+    fn test_mm512_cvt_roundph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26316,7 +26316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_epi32() {
+    fn test_mm512_mask_cvt_roundph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26333,7 +26333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_epi32() {
+    fn test_mm512_maskz_cvt_roundph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26346,21 +26346,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_i32() {
+    fn test_mm_cvtsh_i32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtsh_i32(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvt_roundsh_i32() {
+    fn test_mm_cvt_roundsh_i32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundsh_i32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_epu32() {
+    fn test_mm_cvtph_epu32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtph_epu32(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -26368,7 +26368,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_epu32() {
+    fn test_mm_mask_cvtph_epu32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let src = _mm_set_epi32(10, 11, 12, 13);
         let r = _mm_mask_cvtph_epu32(src, 0b0101, a);
@@ -26377,7 +26377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_epu32() {
+    fn test_mm_maskz_cvtph_epu32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvtph_epu32(0b0101, a);
         let e = _mm_set_epi32(0, 2, 0, 4);
@@ -26385,7 +26385,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_epu32() {
+    fn test_mm256_cvtph_epu32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvtph_epu32(a);
         let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26393,7 +26393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_epu32() {
+    fn test_mm256_mask_cvtph_epu32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm256_mask_cvtph_epu32(src, 0b01010101, a);
@@ -26402,7 +26402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_epu32() {
+    fn test_mm256_maskz_cvtph_epu32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_maskz_cvtph_epu32(0b01010101, a);
         let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26410,7 +26410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_epu32() {
+    fn test_mm512_cvtph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26420,7 +26420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_epu32() {
+    fn test_mm512_mask_cvtph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26433,7 +26433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_epu32() {
+    fn test_mm512_maskz_cvtph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26443,7 +26443,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_epu32() {
+    fn test_mm512_cvt_roundph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26453,7 +26453,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_epu32() {
+    fn test_mm512_mask_cvt_roundph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26470,7 +26470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_epu32() {
+    fn test_mm512_maskz_cvt_roundph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26483,21 +26483,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_u32() {
+    fn test_mm_cvtsh_u32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtsh_u32(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvt_roundsh_u32() {
+    fn test_mm_cvt_roundsh_u32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundsh_u32::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvttph_epi32() {
+    fn test_mm_cvttph_epi32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvttph_epi32(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -26505,7 +26505,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvttph_epi32() {
+    fn test_mm_mask_cvttph_epi32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let src = _mm_set_epi32(10, 11, 12, 13);
         let r = _mm_mask_cvttph_epi32(src, 0b0101, a);
@@ -26514,7 +26514,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvttph_epi32() {
+    fn test_mm_maskz_cvttph_epi32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvttph_epi32(0b0101, a);
         let e = _mm_set_epi32(0, 2, 0, 4);
@@ -26522,7 +26522,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvttph_epi32() {
+    fn test_mm256_cvttph_epi32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvttph_epi32(a);
         let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26530,7 +26530,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvttph_epi32() {
+    fn test_mm256_mask_cvttph_epi32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm256_mask_cvttph_epi32(src, 0b01010101, a);
@@ -26539,7 +26539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttph_epi32() {
+    fn test_mm256_maskz_cvttph_epi32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_maskz_cvttph_epi32(0b01010101, a);
         let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26547,7 +26547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvttph_epi32() {
+    fn test_mm512_cvttph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26557,7 +26557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvttph_epi32() {
+    fn test_mm512_mask_cvttph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26570,7 +26570,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvttph_epi32() {
+    fn test_mm512_maskz_cvttph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26580,7 +26580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtt_roundph_epi32() {
+    fn test_mm512_cvtt_roundph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26590,7 +26590,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtt_roundph_epi32() {
+    fn test_mm512_mask_cvtt_roundph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26603,7 +26603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtt_roundph_epi32() {
+    fn test_mm512_maskz_cvtt_roundph_epi32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26613,21 +26613,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvttsh_i32() {
+    fn test_mm_cvttsh_i32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttsh_i32(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtt_roundsh_i32() {
+    fn test_mm_cvtt_roundsh_i32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtt_roundsh_i32::<_MM_FROUND_NO_EXC>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvttph_epu32() {
+    fn test_mm_cvttph_epu32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvttph_epu32(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -26635,7 +26635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvttph_epu32() {
+    fn test_mm_mask_cvttph_epu32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let src = _mm_set_epi32(10, 11, 12, 13);
         let r = _mm_mask_cvttph_epu32(src, 0b0101, a);
@@ -26644,7 +26644,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvttph_epu32() {
+    fn test_mm_maskz_cvttph_epu32() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvttph_epu32(0b0101, a);
         let e = _mm_set_epi32(0, 2, 0, 4);
@@ -26652,7 +26652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvttph_epu32() {
+    fn test_mm256_cvttph_epu32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvttph_epu32(a);
         let e = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26660,7 +26660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvttph_epu32() {
+    fn test_mm256_mask_cvttph_epu32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let src = _mm256_set_epi32(10, 11, 12, 13, 14, 15, 16, 17);
         let r = _mm256_mask_cvttph_epu32(src, 0b01010101, a);
@@ -26669,7 +26669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttph_epu32() {
+    fn test_mm256_maskz_cvttph_epu32() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_maskz_cvttph_epu32(0b01010101, a);
         let e = _mm256_set_epi32(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26677,7 +26677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvttph_epu32() {
+    fn test_mm512_cvttph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26687,7 +26687,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvttph_epu32() {
+    fn test_mm512_mask_cvttph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26700,7 +26700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvttph_epu32() {
+    fn test_mm512_maskz_cvttph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26710,7 +26710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtt_roundph_epu32() {
+    fn test_mm512_cvtt_roundph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26720,7 +26720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtt_roundph_epu32() {
+    fn test_mm512_mask_cvtt_roundph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26733,7 +26733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtt_roundph_epu32() {
+    fn test_mm512_maskz_cvtt_roundph_epu32() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -26743,21 +26743,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvttsh_u32() {
+    fn test_mm_cvttsh_u32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttsh_u32(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtt_roundsh_u32() {
+    fn test_mm_cvtt_roundsh_u32() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtt_roundsh_u32::<_MM_FROUND_NO_EXC>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_epi64() {
+    fn test_mm_cvtph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_cvtph_epi64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -26765,7 +26765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_epi64() {
+    fn test_mm_mask_cvtph_epi64() {
         let src = _mm_set_epi64x(3, 4);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_mask_cvtph_epi64(src, 0b01, a);
@@ -26774,7 +26774,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_epi64() {
+    fn test_mm_maskz_cvtph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_maskz_cvtph_epi64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -26782,7 +26782,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_epi64() {
+    fn test_mm256_cvtph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_cvtph_epi64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -26790,7 +26790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_epi64() {
+    fn test_mm256_mask_cvtph_epi64() {
         let src = _mm256_set_epi64x(5, 6, 7, 8);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_mask_cvtph_epi64(src, 0b0101, a);
@@ -26799,7 +26799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_epi64() {
+    fn test_mm256_maskz_cvtph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_maskz_cvtph_epi64(0b0101, a);
         let e = _mm256_set_epi64x(0, 2, 0, 4);
@@ -26807,7 +26807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_epi64() {
+    fn test_mm512_cvtph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvtph_epi64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26815,7 +26815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_epi64() {
+    fn test_mm512_mask_cvtph_epi64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvtph_epi64(src, 0b01010101, a);
@@ -26824,7 +26824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_epi64() {
+    fn test_mm512_maskz_cvtph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvtph_epi64(0b01010101, a);
         let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26832,7 +26832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_epi64() {
+    fn test_mm512_cvt_roundph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvt_roundph_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26840,7 +26840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_epi64() {
+    fn test_mm512_mask_cvt_roundph_epi64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvt_roundph_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -26851,7 +26851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_epi64() {
+    fn test_mm512_maskz_cvt_roundph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvt_roundph_epi64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01010101, a,
@@ -26861,7 +26861,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_epu64() {
+    fn test_mm_cvtph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_cvtph_epu64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -26869,7 +26869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_epu64() {
+    fn test_mm_mask_cvtph_epu64() {
         let src = _mm_set_epi64x(3, 4);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_mask_cvtph_epu64(src, 0b01, a);
@@ -26878,7 +26878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_epu64() {
+    fn test_mm_maskz_cvtph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_maskz_cvtph_epu64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -26886,7 +26886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_epu64() {
+    fn test_mm256_cvtph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_cvtph_epu64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -26894,7 +26894,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_epu64() {
+    fn test_mm256_mask_cvtph_epu64() {
         let src = _mm256_set_epi64x(5, 6, 7, 8);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_mask_cvtph_epu64(src, 0b0101, a);
@@ -26903,7 +26903,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_epu64() {
+    fn test_mm256_maskz_cvtph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_maskz_cvtph_epu64(0b0101, a);
         let e = _mm256_set_epi64x(0, 2, 0, 4);
@@ -26911,7 +26911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_epu64() {
+    fn test_mm512_cvtph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvtph_epu64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26919,7 +26919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_epu64() {
+    fn test_mm512_mask_cvtph_epu64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvtph_epu64(src, 0b01010101, a);
@@ -26928,7 +26928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_epu64() {
+    fn test_mm512_maskz_cvtph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvtph_epu64(0b01010101, a);
         let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
@@ -26936,7 +26936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_epu64() {
+    fn test_mm512_cvt_roundph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvt_roundph_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -26944,7 +26944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_epu64() {
+    fn test_mm512_mask_cvt_roundph_epu64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvt_roundph_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -26955,7 +26955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_epu64() {
+    fn test_mm512_maskz_cvt_roundph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvt_roundph_epu64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
             0b01010101, a,
@@ -26965,7 +26965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvttph_epi64() {
+    fn test_mm_cvttph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_cvttph_epi64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -26973,7 +26973,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvttph_epi64() {
+    fn test_mm_mask_cvttph_epi64() {
         let src = _mm_set_epi64x(3, 4);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_mask_cvttph_epi64(src, 0b01, a);
@@ -26982,7 +26982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvttph_epi64() {
+    fn test_mm_maskz_cvttph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_maskz_cvttph_epi64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -26990,7 +26990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvttph_epi64() {
+    fn test_mm256_cvttph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_cvttph_epi64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -26998,7 +26998,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvttph_epi64() {
+    fn test_mm256_mask_cvttph_epi64() {
         let src = _mm256_set_epi64x(5, 6, 7, 8);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_mask_cvttph_epi64(src, 0b0101, a);
@@ -27007,7 +27007,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttph_epi64() {
+    fn test_mm256_maskz_cvttph_epi64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_maskz_cvttph_epi64(0b0101, a);
         let e = _mm256_set_epi64x(0, 2, 0, 4);
@@ -27015,7 +27015,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvttph_epi64() {
+    fn test_mm512_cvttph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvttph_epi64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -27023,7 +27023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvttph_epi64() {
+    fn test_mm512_mask_cvttph_epi64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvttph_epi64(src, 0b01010101, a);
@@ -27032,7 +27032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvttph_epi64() {
+    fn test_mm512_maskz_cvttph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvttph_epi64(0b01010101, a);
         let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
@@ -27040,7 +27040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtt_roundph_epi64() {
+    fn test_mm512_cvtt_roundph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvtt_roundph_epi64::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -27048,7 +27048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtt_roundph_epi64() {
+    fn test_mm512_mask_cvtt_roundph_epi64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvtt_roundph_epi64::<_MM_FROUND_NO_EXC>(src, 0b01010101, a);
@@ -27057,7 +27057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtt_roundph_epi64() {
+    fn test_mm512_maskz_cvtt_roundph_epi64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvtt_roundph_epi64::<_MM_FROUND_NO_EXC>(0b01010101, a);
         let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
@@ -27065,7 +27065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvttph_epu64() {
+    fn test_mm_cvttph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_cvttph_epu64(a);
         let e = _mm_set_epi64x(1, 2);
@@ -27073,7 +27073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvttph_epu64() {
+    fn test_mm_mask_cvttph_epu64() {
         let src = _mm_set_epi64x(3, 4);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_mask_cvttph_epu64(src, 0b01, a);
@@ -27082,7 +27082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvttph_epu64() {
+    fn test_mm_maskz_cvttph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_maskz_cvttph_epu64(0b01, a);
         let e = _mm_set_epi64x(0, 2);
@@ -27090,7 +27090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvttph_epu64() {
+    fn test_mm256_cvttph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_cvttph_epu64(a);
         let e = _mm256_set_epi64x(1, 2, 3, 4);
@@ -27098,7 +27098,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvttph_epu64() {
+    fn test_mm256_mask_cvttph_epu64() {
         let src = _mm256_set_epi64x(5, 6, 7, 8);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_mask_cvttph_epu64(src, 0b0101, a);
@@ -27107,7 +27107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttph_epu64() {
+    fn test_mm256_maskz_cvttph_epu64() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_maskz_cvttph_epu64(0b0101, a);
         let e = _mm256_set_epi64x(0, 2, 0, 4);
@@ -27115,7 +27115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvttph_epu64() {
+    fn test_mm512_cvttph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvttph_epu64(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -27123,7 +27123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvttph_epu64() {
+    fn test_mm512_mask_cvttph_epu64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvttph_epu64(src, 0b01010101, a);
@@ -27132,7 +27132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvttph_epu64() {
+    fn test_mm512_maskz_cvttph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvttph_epu64(0b01010101, a);
         let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
@@ -27140,7 +27140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtt_roundph_epu64() {
+    fn test_mm512_cvtt_roundph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvtt_roundph_epu64::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@@ -27148,7 +27148,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtt_roundph_epu64() {
+    fn test_mm512_mask_cvtt_roundph_epu64() {
         let src = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvtt_roundph_epu64::<_MM_FROUND_NO_EXC>(src, 0b01010101, a);
@@ -27157,7 +27157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtt_roundph_epu64() {
+    fn test_mm512_maskz_cvtt_roundph_epu64() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvtt_roundph_epu64::<_MM_FROUND_NO_EXC>(0b01010101, a);
         let e = _mm512_set_epi64(0, 2, 0, 4, 0, 6, 0, 8);
@@ -27165,7 +27165,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtxph_ps() {
+    fn test_mm_cvtxph_ps() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtxph_ps(a);
         let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
@@ -27173,7 +27173,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtxph_ps() {
+    fn test_mm_mask_cvtxph_ps() {
         let src = _mm_set_ps(10.0, 11.0, 12.0, 13.0);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_mask_cvtxph_ps(src, 0b0101, a);
@@ -27182,7 +27182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtxph_ps() {
+    fn test_mm_maskz_cvtxph_ps() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm_maskz_cvtxph_ps(0b0101, a);
         let e = _mm_set_ps(0.0, 2.0, 0.0, 4.0);
@@ -27190,7 +27190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtxph_ps() {
+    fn test_mm256_cvtxph_ps() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvtxph_ps(a);
         let e = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -27198,7 +27198,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtxph_ps() {
+    fn test_mm256_mask_cvtxph_ps() {
         let src = _mm256_set_ps(10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_mask_cvtxph_ps(src, 0b01010101, a);
@@ -27207,7 +27207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtxph_ps() {
+    fn test_mm256_maskz_cvtxph_ps() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_maskz_cvtxph_ps(0b01010101, a);
         let e = _mm256_set_ps(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
@@ -27215,7 +27215,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtxph_ps() {
+    fn test_mm512_cvtxph_ps() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -27227,7 +27227,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtxph_ps() {
+    fn test_mm512_mask_cvtxph_ps() {
         let src = _mm512_set_ps(
             10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0,
             24.0, 25.0,
@@ -27244,7 +27244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtxph_ps() {
+    fn test_mm512_maskz_cvtxph_ps() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -27256,7 +27256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtx_roundph_ps() {
+    fn test_mm512_cvtx_roundph_ps() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -27268,7 +27268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtx_roundph_ps() {
+    fn test_mm512_mask_cvtx_roundph_ps() {
         let src = _mm512_set_ps(
             10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0,
             24.0, 25.0,
@@ -27285,7 +27285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtx_roundph_ps() {
+    fn test_mm512_maskz_cvtx_roundph_ps() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -27297,7 +27297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_ss() {
+    fn test_mm_cvtsh_ss() {
         let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_cvtsh_ss(a, b);
@@ -27306,7 +27306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_cvtsh_ss() {
+    fn test_mm_mask_cvtsh_ss() {
         let src = _mm_setr_ps(3.0, 11.0, 12.0, 13.0);
         let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
@@ -27319,7 +27319,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_maskz_cvtsh_ss() {
+    fn test_mm_maskz_cvtsh_ss() {
         let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_maskz_cvtsh_ss(0, a, b);
@@ -27331,7 +27331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvt_roundsh_ss() {
+    fn test_mm_cvt_roundsh_ss() {
         let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(a, b);
@@ -27340,7 +27340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_cvt_roundsh_ss() {
+    fn test_mm_mask_cvt_roundsh_ss() {
         let src = _mm_setr_ps(3.0, 11.0, 12.0, 13.0);
         let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
@@ -27353,7 +27353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_maskz_cvt_roundsh_ss() {
+    fn test_mm_maskz_cvt_roundsh_ss() {
         let a = _mm_setr_ps(2.0, 20.0, 21.0, 22.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_maskz_cvt_roundsh_ss::<_MM_FROUND_NO_EXC>(0, a, b);
@@ -27365,7 +27365,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtph_pd() {
+    fn test_mm_cvtph_pd() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_cvtph_pd(a);
         let e = _mm_set_pd(1.0, 2.0);
@@ -27373,7 +27373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_cvtph_pd() {
+    fn test_mm_mask_cvtph_pd() {
         let src = _mm_set_pd(10.0, 11.0);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_mask_cvtph_pd(src, 0b01, a);
@@ -27382,7 +27382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtph_pd() {
+    fn test_mm_maskz_cvtph_pd() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 2.0);
         let r = _mm_maskz_cvtph_pd(0b01, a);
         let e = _mm_set_pd(0.0, 2.0);
@@ -27390,7 +27390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_cvtph_pd() {
+    fn test_mm256_cvtph_pd() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_cvtph_pd(a);
         let e = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
@@ -27398,7 +27398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtph_pd() {
+    fn test_mm256_mask_cvtph_pd() {
         let src = _mm256_set_pd(10.0, 11.0, 12.0, 13.0);
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_mask_cvtph_pd(src, 0b0101, a);
@@ -27407,7 +27407,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtph_pd() {
+    fn test_mm256_maskz_cvtph_pd() {
         let a = _mm_set_ph(0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 3.0, 4.0);
         let r = _mm256_maskz_cvtph_pd(0b0101, a);
         let e = _mm256_set_pd(0.0, 2.0, 0.0, 4.0);
@@ -27415,7 +27415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvtph_pd() {
+    fn test_mm512_cvtph_pd() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvtph_pd(a);
         let e = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -27423,7 +27423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvtph_pd() {
+    fn test_mm512_mask_cvtph_pd() {
         let src = _mm512_set_pd(10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvtph_pd(src, 0b01010101, a);
@@ -27432,7 +27432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvtph_pd() {
+    fn test_mm512_maskz_cvtph_pd() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvtph_pd(0b01010101, a);
         let e = _mm512_set_pd(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
@@ -27440,7 +27440,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_cvt_roundph_pd() {
+    fn test_mm512_cvt_roundph_pd() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_cvt_roundph_pd::<_MM_FROUND_NO_EXC>(a);
         let e = _mm512_set_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -27448,7 +27448,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_mask_cvt_roundph_pd() {
+    fn test_mm512_mask_cvt_roundph_pd() {
         let src = _mm512_set_pd(10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0);
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_mask_cvt_roundph_pd::<_MM_FROUND_NO_EXC>(src, 0b01010101, a);
@@ -27457,7 +27457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm512_maskz_cvt_roundph_pd() {
+    fn test_mm512_maskz_cvt_roundph_pd() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm512_maskz_cvt_roundph_pd::<_MM_FROUND_NO_EXC>(0b01010101, a);
         let e = _mm512_set_pd(0.0, 2.0, 0.0, 4.0, 0.0, 6.0, 0.0, 8.0);
@@ -27465,7 +27465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_sd() {
+    fn test_mm_cvtsh_sd() {
         let a = _mm_setr_pd(2.0, 20.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_cvtsh_sd(a, b);
@@ -27474,7 +27474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_cvtsh_sd() {
+    fn test_mm_mask_cvtsh_sd() {
         let src = _mm_setr_pd(3.0, 11.0);
         let a = _mm_setr_pd(2.0, 20.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
@@ -27487,7 +27487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_maskz_cvtsh_sd() {
+    fn test_mm_maskz_cvtsh_sd() {
         let a = _mm_setr_pd(2.0, 20.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_maskz_cvtsh_sd(0, a, b);
@@ -27499,7 +27499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvt_roundsh_sd() {
+    fn test_mm_cvt_roundsh_sd() {
         let a = _mm_setr_pd(2.0, 20.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(a, b);
@@ -27508,7 +27508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_mask_cvt_roundsh_sd() {
+    fn test_mm_mask_cvt_roundsh_sd() {
         let src = _mm_setr_pd(3.0, 11.0);
         let a = _mm_setr_pd(2.0, 20.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
@@ -27521,7 +27521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_maskz_cvt_roundsh_sd() {
+    fn test_mm_maskz_cvt_roundsh_sd() {
         let a = _mm_setr_pd(2.0, 20.0);
         let b = _mm_setr_ph(1.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0);
         let r = _mm_maskz_cvt_roundsh_sd::<_MM_FROUND_NO_EXC>(0, a, b);
@@ -27533,14 +27533,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm_cvtsh_h() {
+    const fn test_mm_cvtsh_h() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtsh_h(a);
         assert_eq!(r, 1.0);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm256_cvtsh_h() {
+    const fn test_mm256_cvtsh_h() {
         let a = _mm256_setr_ph(
             1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -27549,7 +27549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_cvtsh_h() {
+    const fn test_mm512_cvtsh_h() {
         let a = _mm512_setr_ph(
             1.0, 2.0, 3.0, 42.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -27560,14 +27560,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm_cvtsi128_si16() {
+    const fn test_mm_cvtsi128_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm_cvtsi128_si16(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm_cvtsi16_si128() {
+    const fn test_mm_cvtsi16_si128() {
         let a = 1;
         let r = _mm_cvtsi16_si128(a);
         let e = _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0);
diff --git a/crates/core_arch/src/x86/avx512ifma.rs b/crates/core_arch/src/x86/avx512ifma.rs
index 7c9d07f690..5ce28565d1 100644
--- a/crates/core_arch/src/x86/avx512ifma.rs
+++ b/crates/core_arch/src/x86/avx512ifma.rs
@@ -372,7 +372,7 @@ mod tests {
     const K: __mmask8 = 0b01101101;
 
     #[simd_test(enable = "avx512ifma")]
-    unsafe fn test_mm512_madd52hi_epu64() {
+    fn test_mm512_madd52hi_epu64() {
         let a = _mm512_set1_epi64(10 << 40);
         let b = _mm512_set1_epi64((11 << 40) + 4);
         let c = _mm512_set1_epi64((12 << 40) + 3);
@@ -386,7 +386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma")]
-    unsafe fn test_mm512_mask_madd52hi_epu64() {
+    fn test_mm512_mask_madd52hi_epu64() {
         let a = _mm512_set1_epi64(10 << 40);
         let b = _mm512_set1_epi64((11 << 40) + 4);
         let c = _mm512_set1_epi64((12 << 40) + 3);
@@ -401,7 +401,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma")]
-    unsafe fn test_mm512_maskz_madd52hi_epu64() {
+    fn test_mm512_maskz_madd52hi_epu64() {
         let a = _mm512_set1_epi64(10 << 40);
         let b = _mm512_set1_epi64((11 << 40) + 4);
         let c = _mm512_set1_epi64((12 << 40) + 3);
@@ -416,7 +416,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma")]
-    unsafe fn test_mm512_madd52lo_epu64() {
+    fn test_mm512_madd52lo_epu64() {
         let a = _mm512_set1_epi64(10 << 40);
         let b = _mm512_set1_epi64((11 << 40) + 4);
         let c = _mm512_set1_epi64((12 << 40) + 3);
@@ -430,7 +430,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma")]
-    unsafe fn test_mm512_mask_madd52lo_epu64() {
+    fn test_mm512_mask_madd52lo_epu64() {
         let a = _mm512_set1_epi64(10 << 40);
         let b = _mm512_set1_epi64((11 << 40) + 4);
         let c = _mm512_set1_epi64((12 << 40) + 3);
@@ -445,7 +445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma")]
-    unsafe fn test_mm512_maskz_madd52lo_epu64() {
+    fn test_mm512_maskz_madd52lo_epu64() {
         let a = _mm512_set1_epi64(10 << 40);
         let b = _mm512_set1_epi64((11 << 40) + 4);
         let c = _mm512_set1_epi64((12 << 40) + 3);
@@ -460,7 +460,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxifma")]
-    unsafe fn test_mm256_madd52hi_avx_epu64() {
+    fn test_mm256_madd52hi_avx_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -474,7 +474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm256_madd52hi_epu64() {
+    fn test_mm256_madd52hi_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -488,7 +488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm256_mask_madd52hi_epu64() {
+    fn test_mm256_mask_madd52hi_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -503,7 +503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm256_maskz_madd52hi_epu64() {
+    fn test_mm256_maskz_madd52hi_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -518,7 +518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxifma")]
-    unsafe fn test_mm256_madd52lo_avx_epu64() {
+    fn test_mm256_madd52lo_avx_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -532,7 +532,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm256_madd52lo_epu64() {
+    fn test_mm256_madd52lo_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -546,7 +546,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm256_mask_madd52lo_epu64() {
+    fn test_mm256_mask_madd52lo_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -561,7 +561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm256_maskz_madd52lo_epu64() {
+    fn test_mm256_maskz_madd52lo_epu64() {
         let a = _mm256_set1_epi64x(10 << 40);
         let b = _mm256_set1_epi64x((11 << 40) + 4);
         let c = _mm256_set1_epi64x((12 << 40) + 3);
@@ -576,7 +576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxifma")]
-    unsafe fn test_mm_madd52hi_avx_epu64() {
+    fn test_mm_madd52hi_avx_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -590,7 +590,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm_madd52hi_epu64() {
+    fn test_mm_madd52hi_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -604,7 +604,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm_mask_madd52hi_epu64() {
+    fn test_mm_mask_madd52hi_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -619,7 +619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm_maskz_madd52hi_epu64() {
+    fn test_mm_maskz_madd52hi_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -634,7 +634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxifma")]
-    unsafe fn test_mm_madd52lo_avx_epu64() {
+    fn test_mm_madd52lo_avx_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -648,7 +648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm_madd52lo_epu64() {
+    fn test_mm_madd52lo_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -662,7 +662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm_mask_madd52lo_epu64() {
+    fn test_mm_mask_madd52lo_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
@@ -677,7 +677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512ifma,avx512vl")]
-    unsafe fn test_mm_maskz_madd52lo_epu64() {
+    fn test_mm_maskz_madd52lo_epu64() {
         let a = _mm_set1_epi64x(10 << 40);
         let b = _mm_set1_epi64x((11 << 40) + 4);
         let c = _mm_set1_epi64x((12 << 40) + 3);
diff --git a/crates/core_arch/src/x86/avx512vbmi.rs b/crates/core_arch/src/x86/avx512vbmi.rs
index 3527ccc9e4..d9ad14ef00 100644
--- a/crates/core_arch/src/x86/avx512vbmi.rs
+++ b/crates/core_arch/src/x86/avx512vbmi.rs
@@ -484,7 +484,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_permutex2var_epi8() {
+    fn test_mm512_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -508,7 +508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_mask_permutex2var_epi8() {
+    fn test_mm512_mask_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -539,7 +539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_maskz_permutex2var_epi8() {
+    fn test_mm512_maskz_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -570,7 +570,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_mask2_permutex2var_epi8() {
+    fn test_mm512_mask2_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -601,7 +601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_permutex2var_epi8() {
+    fn test_mm256_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -619,7 +619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_mask_permutex2var_epi8() {
+    fn test_mm256_mask_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -639,7 +639,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex2var_epi8() {
+    fn test_mm256_maskz_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -659,7 +659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_mask2_permutex2var_epi8() {
+    fn test_mm256_mask2_permutex2var_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -679,7 +679,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_permutex2var_epi8() {
+    fn test_mm_permutex2var_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm_set_epi8(1, 1 << 4, 2, 1 << 4, 3, 1 << 4, 4, 1 << 4, 5, 1 << 4, 6, 1 << 4, 7, 1 << 4, 8, 1 << 4);
@@ -692,7 +692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_mask_permutex2var_epi8() {
+    fn test_mm_mask_permutex2var_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm_set_epi8(1, 1 << 4, 2, 1 << 4, 3, 1 << 4, 4, 1 << 4, 5, 1 << 4, 6, 1 << 4, 7, 1 << 4, 8, 1 << 4);
@@ -707,7 +707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_maskz_permutex2var_epi8() {
+    fn test_mm_maskz_permutex2var_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm_set_epi8(1, 1 << 4, 2, 1 << 4, 3, 1 << 4, 4, 1 << 4, 5, 1 << 4, 6, 1 << 4, 7, 1 << 4, 8, 1 << 4);
@@ -722,7 +722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_mask2_permutex2var_epi8() {
+    fn test_mm_mask2_permutex2var_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let idx = _mm_set_epi8(1, 1 << 4, 2, 1 << 4, 3, 1 << 4, 4, 1 << 4, 5, 1 << 4, 6, 1 << 4, 7, 1 << 4, 8, 1 << 4);
@@ -737,7 +737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_permutexvar_epi8() {
+    fn test_mm512_permutexvar_epi8() {
         let idx = _mm512_set1_epi8(1);
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -750,7 +750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_mask_permutexvar_epi8() {
+    fn test_mm512_mask_permutexvar_epi8() {
         let idx = _mm512_set1_epi8(1);
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -770,7 +770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_maskz_permutexvar_epi8() {
+    fn test_mm512_maskz_permutexvar_epi8() {
         let idx = _mm512_set1_epi8(1);
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -789,7 +789,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_permutexvar_epi8() {
+    fn test_mm256_permutexvar_epi8() {
         let idx = _mm256_set1_epi8(1);
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -800,7 +800,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_mask_permutexvar_epi8() {
+    fn test_mm256_mask_permutexvar_epi8() {
         let idx = _mm256_set1_epi8(1);
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -813,7 +813,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_maskz_permutexvar_epi8() {
+    fn test_mm256_maskz_permutexvar_epi8() {
         let idx = _mm256_set1_epi8(1);
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -826,7 +826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_permutexvar_epi8() {
+    fn test_mm_permutexvar_epi8() {
         let idx = _mm_set1_epi8(1);
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_permutexvar_epi8(idx, a);
@@ -835,7 +835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_mask_permutexvar_epi8() {
+    fn test_mm_mask_permutexvar_epi8() {
         let idx = _mm_set1_epi8(1);
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_mask_permutexvar_epi8(a, 0, idx, a);
@@ -846,7 +846,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_maskz_permutexvar_epi8() {
+    fn test_mm_maskz_permutexvar_epi8() {
         let idx = _mm_set1_epi8(1);
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_permutexvar_epi8(0, idx, a);
@@ -857,7 +857,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_multishift_epi64_epi8() {
+    fn test_mm512_multishift_epi64_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_multishift_epi64_epi8(a, b);
@@ -866,7 +866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_mask_multishift_epi64_epi8() {
+    fn test_mm512_mask_multishift_epi64_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_mask_multishift_epi64_epi8(a, 0, a, b);
@@ -882,7 +882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi")]
-    unsafe fn test_mm512_maskz_multishift_epi64_epi8() {
+    fn test_mm512_maskz_multishift_epi64_epi8() {
         let a = _mm512_set1_epi8(1);
         let b = _mm512_set1_epi8(1);
         let r = _mm512_maskz_multishift_epi64_epi8(0, a, b);
@@ -897,7 +897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_multishift_epi64_epi8() {
+    fn test_mm256_multishift_epi64_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_multishift_epi64_epi8(a, b);
@@ -906,7 +906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_mask_multishift_epi64_epi8() {
+    fn test_mm256_mask_multishift_epi64_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_mask_multishift_epi64_epi8(a, 0, a, b);
@@ -917,7 +917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm256_maskz_multishift_epi64_epi8() {
+    fn test_mm256_maskz_multishift_epi64_epi8() {
         let a = _mm256_set1_epi8(1);
         let b = _mm256_set1_epi8(1);
         let r = _mm256_maskz_multishift_epi64_epi8(0, a, b);
@@ -928,7 +928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_multishift_epi64_epi8() {
+    fn test_mm_multishift_epi64_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_multishift_epi64_epi8(a, b);
@@ -937,7 +937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_mask_multishift_epi64_epi8() {
+    fn test_mm_mask_multishift_epi64_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_mask_multishift_epi64_epi8(a, 0, a, b);
@@ -948,7 +948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi,avx512vl")]
-    unsafe fn test_mm_maskz_multishift_epi64_epi8() {
+    fn test_mm_maskz_multishift_epi64_epi8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(1);
         let r = _mm_maskz_multishift_epi64_epi8(0, a, b);
diff --git a/crates/core_arch/src/x86/avx512vbmi2.rs b/crates/core_arch/src/x86/avx512vbmi2.rs
index da268f969c..26cef5814e 100644
--- a/crates/core_arch/src/x86/avx512vbmi2.rs
+++ b/crates/core_arch/src/x86/avx512vbmi2.rs
@@ -2450,7 +2450,7 @@ mod tests {
     use crate::hint::black_box;
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_compress_epi16() {
+    fn test_mm512_mask_compress_epi16() {
         let src = _mm512_set1_epi16(200);
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -2465,7 +2465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_compress_epi16() {
+    fn test_mm512_maskz_compress_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -2479,7 +2479,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_compress_epi16() {
+    fn test_mm256_mask_compress_epi16() {
         let src = _mm256_set1_epi16(200);
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_compress_epi16(src, 0b01010101_01010101, a);
@@ -2490,7 +2490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_compress_epi16() {
+    fn test_mm256_maskz_compress_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_compress_epi16(0b01010101_01010101, a);
         let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 5, 7, 9, 11, 13, 15);
@@ -2498,7 +2498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_compress_epi16() {
+    fn test_mm_mask_compress_epi16() {
         let src = _mm_set1_epi16(200);
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_compress_epi16(src, 0b01010101, a);
@@ -2507,7 +2507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_compress_epi16() {
+    fn test_mm_maskz_compress_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_compress_epi16(0b01010101, a);
         let e = _mm_set_epi16(0, 0, 0, 0, 1, 3, 5, 7);
@@ -2515,7 +2515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_compress_epi8() {
+    fn test_mm512_mask_compress_epi8() {
         let src = _mm512_set1_epi8(100);
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -2538,7 +2538,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_compress_epi8() {
+    fn test_mm512_maskz_compress_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -2559,7 +2559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_compress_epi8() {
+    fn test_mm256_mask_compress_epi8() {
         let src = _mm256_set1_epi8(100);
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -2574,7 +2574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_compress_epi8() {
+    fn test_mm256_maskz_compress_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -2588,7 +2588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_compress_epi8() {
+    fn test_mm_mask_compress_epi8() {
         let src = _mm_set1_epi8(100);
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_mask_compress_epi8(src, 0b01010101_01010101, a);
@@ -2599,7 +2599,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_compress_epi8() {
+    fn test_mm_maskz_compress_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_compress_epi8(0b01010101_01010101, a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 5, 7, 9, 11, 13, 15);
@@ -2607,7 +2607,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_expand_epi16() {
+    fn test_mm512_mask_expand_epi16() {
         let src = _mm512_set1_epi16(200);
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -2622,7 +2622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_expand_epi16() {
+    fn test_mm512_maskz_expand_epi16() {
         #[rustfmt::skip]
         let a = _mm512_set_epi16(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -2634,7 +2634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_expand_epi16() {
+    fn test_mm256_mask_expand_epi16() {
         let src = _mm256_set1_epi16(200);
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_mask_expand_epi16(src, 0b01010101_01010101, a);
@@ -2645,7 +2645,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_expand_epi16() {
+    fn test_mm256_maskz_expand_epi16() {
         let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_expand_epi16(0b01010101_01010101, a);
         let e = _mm256_set_epi16(0, 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15);
@@ -2653,7 +2653,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_expand_epi16() {
+    fn test_mm_mask_expand_epi16() {
         let src = _mm_set1_epi16(200);
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_mask_expand_epi16(src, 0b01010101, a);
@@ -2662,7 +2662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_expand_epi16() {
+    fn test_mm_maskz_expand_epi16() {
         let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_maskz_expand_epi16(0b01010101, a);
         let e = _mm_set_epi16(0, 4, 0, 5, 0, 6, 0, 7);
@@ -2670,7 +2670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_expand_epi8() {
+    fn test_mm512_mask_expand_epi8() {
         let src = _mm512_set1_epi8(100);
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -2693,7 +2693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_expand_epi8() {
+    fn test_mm512_maskz_expand_epi8() {
         #[rustfmt::skip]
         let a = _mm512_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
@@ -2714,7 +2714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_expand_epi8() {
+    fn test_mm256_mask_expand_epi8() {
         let src = _mm256_set1_epi8(100);
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
@@ -2729,7 +2729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_expand_epi8() {
+    fn test_mm256_maskz_expand_epi8() {
         #[rustfmt::skip]
         let a = _mm256_set_epi8(0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15,
                                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
@@ -2743,7 +2743,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_expand_epi8() {
+    fn test_mm_mask_expand_epi8() {
         let src = _mm_set1_epi8(100);
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_mask_expand_epi8(src, 0b01010101_01010101, a);
@@ -2754,7 +2754,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_expand_epi8() {
+    fn test_mm_maskz_expand_epi8() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_expand_epi8(0b01010101_01010101, a);
         let e = _mm_set_epi8(0, 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15);
@@ -2762,7 +2762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shldv_epi64() {
+    const fn test_mm512_shldv_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let c = _mm512_set1_epi64(2);
@@ -2772,7 +2772,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shldv_epi64() {
+    const fn test_mm512_mask_shldv_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let c = _mm512_set1_epi64(2);
@@ -2784,7 +2784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shldv_epi64() {
+    const fn test_mm512_maskz_shldv_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let c = _mm512_set1_epi64(2);
@@ -2796,7 +2796,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shldv_epi64() {
+    const fn test_mm256_shldv_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let c = _mm256_set1_epi64x(2);
@@ -2806,7 +2806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shldv_epi64() {
+    const fn test_mm256_mask_shldv_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let c = _mm256_set1_epi64x(2);
@@ -2818,7 +2818,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shldv_epi64() {
+    const fn test_mm256_maskz_shldv_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let c = _mm256_set1_epi64x(2);
@@ -2830,7 +2830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shldv_epi64() {
+    const fn test_mm_shldv_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let c = _mm_set1_epi64x(2);
@@ -2840,7 +2840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shldv_epi64() {
+    const fn test_mm_mask_shldv_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let c = _mm_set1_epi64x(2);
@@ -2852,7 +2852,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shldv_epi64() {
+    const fn test_mm_maskz_shldv_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let c = _mm_set1_epi64x(2);
@@ -2864,7 +2864,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shldv_epi32() {
+    const fn test_mm512_shldv_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let c = _mm512_set1_epi32(2);
@@ -2874,7 +2874,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shldv_epi32() {
+    const fn test_mm512_mask_shldv_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let c = _mm512_set1_epi32(2);
@@ -2886,7 +2886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shldv_epi32() {
+    const fn test_mm512_maskz_shldv_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let c = _mm512_set1_epi32(2);
@@ -2898,7 +2898,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shldv_epi32() {
+    const fn test_mm256_shldv_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let c = _mm256_set1_epi32(2);
@@ -2908,7 +2908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shldv_epi32() {
+    const fn test_mm256_mask_shldv_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let c = _mm256_set1_epi32(2);
@@ -2920,7 +2920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shldv_epi32() {
+    const fn test_mm256_maskz_shldv_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let c = _mm256_set1_epi32(2);
@@ -2932,7 +2932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shldv_epi32() {
+    const fn test_mm_shldv_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let c = _mm_set1_epi32(2);
@@ -2942,7 +2942,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shldv_epi32() {
+    const fn test_mm_mask_shldv_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let c = _mm_set1_epi32(2);
@@ -2954,7 +2954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shldv_epi32() {
+    const fn test_mm_maskz_shldv_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let c = _mm_set1_epi32(2);
@@ -2966,7 +2966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shldv_epi16() {
+    const fn test_mm512_shldv_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let c = _mm512_set1_epi16(2);
@@ -2976,7 +2976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shldv_epi16() {
+    const fn test_mm512_mask_shldv_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let c = _mm512_set1_epi16(2);
@@ -2988,7 +2988,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shldv_epi16() {
+    const fn test_mm512_maskz_shldv_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let c = _mm512_set1_epi16(2);
@@ -3000,7 +3000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shldv_epi16() {
+    const fn test_mm256_shldv_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let c = _mm256_set1_epi16(2);
@@ -3010,7 +3010,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shldv_epi16() {
+    const fn test_mm256_mask_shldv_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let c = _mm256_set1_epi16(2);
@@ -3022,7 +3022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shldv_epi16() {
+    const fn test_mm256_maskz_shldv_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let c = _mm256_set1_epi16(2);
@@ -3034,7 +3034,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shldv_epi16() {
+    const fn test_mm_shldv_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let c = _mm_set1_epi16(2);
@@ -3044,7 +3044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shldv_epi16() {
+    const fn test_mm_mask_shldv_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let c = _mm_set1_epi16(2);
@@ -3056,7 +3056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shldv_epi16() {
+    const fn test_mm_maskz_shldv_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let c = _mm_set1_epi16(2);
@@ -3068,7 +3068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shrdv_epi64() {
+    const fn test_mm512_shrdv_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let c = _mm512_set1_epi64(1);
@@ -3078,7 +3078,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shrdv_epi64() {
+    const fn test_mm512_mask_shrdv_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let c = _mm512_set1_epi64(1);
@@ -3090,7 +3090,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shrdv_epi64() {
+    const fn test_mm512_maskz_shrdv_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let c = _mm512_set1_epi64(1);
@@ -3102,7 +3102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shrdv_epi64() {
+    const fn test_mm256_shrdv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let c = _mm256_set1_epi64x(1);
@@ -3112,7 +3112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shrdv_epi64() {
+    const fn test_mm256_mask_shrdv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let c = _mm256_set1_epi64x(1);
@@ -3124,7 +3124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shrdv_epi64() {
+    const fn test_mm256_maskz_shrdv_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let c = _mm256_set1_epi64x(1);
@@ -3136,7 +3136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shrdv_epi64() {
+    const fn test_mm_shrdv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let c = _mm_set1_epi64x(1);
@@ -3146,7 +3146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shrdv_epi64() {
+    const fn test_mm_mask_shrdv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let c = _mm_set1_epi64x(1);
@@ -3158,7 +3158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shrdv_epi64() {
+    const fn test_mm_maskz_shrdv_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let c = _mm_set1_epi64x(1);
@@ -3170,7 +3170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shrdv_epi32() {
+    const fn test_mm512_shrdv_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let c = _mm512_set1_epi32(1);
@@ -3180,7 +3180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shrdv_epi32() {
+    const fn test_mm512_mask_shrdv_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let c = _mm512_set1_epi32(1);
@@ -3192,7 +3192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shrdv_epi32() {
+    const fn test_mm512_maskz_shrdv_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let c = _mm512_set1_epi32(1);
@@ -3204,7 +3204,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shrdv_epi32() {
+    const fn test_mm256_shrdv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let c = _mm256_set1_epi32(1);
@@ -3214,7 +3214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shrdv_epi32() {
+    const fn test_mm256_mask_shrdv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let c = _mm256_set1_epi32(1);
@@ -3226,7 +3226,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shrdv_epi32() {
+    const fn test_mm256_maskz_shrdv_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let c = _mm256_set1_epi32(1);
@@ -3238,7 +3238,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shrdv_epi32() {
+    const fn test_mm_shrdv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let c = _mm_set1_epi32(1);
@@ -3248,7 +3248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shrdv_epi32() {
+    const fn test_mm_mask_shrdv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let c = _mm_set1_epi32(1);
@@ -3260,7 +3260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shrdv_epi32() {
+    const fn test_mm_maskz_shrdv_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let c = _mm_set1_epi32(1);
@@ -3272,7 +3272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shrdv_epi16() {
+    const fn test_mm512_shrdv_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let c = _mm512_set1_epi16(1);
@@ -3282,7 +3282,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shrdv_epi16() {
+    const fn test_mm512_mask_shrdv_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let c = _mm512_set1_epi16(1);
@@ -3294,7 +3294,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shrdv_epi16() {
+    const fn test_mm512_maskz_shrdv_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let c = _mm512_set1_epi16(1);
@@ -3306,7 +3306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shrdv_epi16() {
+    const fn test_mm256_shrdv_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let c = _mm256_set1_epi16(1);
@@ -3316,7 +3316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shrdv_epi16() {
+    const fn test_mm256_mask_shrdv_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let c = _mm256_set1_epi16(1);
@@ -3328,7 +3328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shrdv_epi16() {
+    const fn test_mm256_maskz_shrdv_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let c = _mm256_set1_epi16(1);
@@ -3340,7 +3340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shrdv_epi16() {
+    const fn test_mm_shrdv_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let c = _mm_set1_epi16(1);
@@ -3350,7 +3350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shrdv_epi16() {
+    const fn test_mm_mask_shrdv_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let c = _mm_set1_epi16(1);
@@ -3362,7 +3362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shrdv_epi16() {
+    const fn test_mm_maskz_shrdv_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let c = _mm_set1_epi16(1);
@@ -3374,7 +3374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shldi_epi64() {
+    const fn test_mm512_shldi_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let r = _mm512_shldi_epi64::<2>(a, b);
@@ -3383,7 +3383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shldi_epi64() {
+    const fn test_mm512_mask_shldi_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let r = _mm512_mask_shldi_epi64::<2>(a, 0, a, b);
@@ -3394,7 +3394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shldi_epi64() {
+    const fn test_mm512_maskz_shldi_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(1 << 63);
         let r = _mm512_maskz_shldi_epi64::<2>(0, a, b);
@@ -3405,7 +3405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shldi_epi64() {
+    const fn test_mm256_shldi_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let r = _mm256_shldi_epi64::<2>(a, b);
@@ -3414,7 +3414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shldi_epi64() {
+    const fn test_mm256_mask_shldi_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let r = _mm256_mask_shldi_epi64::<2>(a, 0, a, b);
@@ -3425,7 +3425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shldi_epi64() {
+    const fn test_mm256_maskz_shldi_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(1 << 63);
         let r = _mm256_maskz_shldi_epi64::<2>(0, a, b);
@@ -3436,7 +3436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shldi_epi64() {
+    const fn test_mm_shldi_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let r = _mm_shldi_epi64::<2>(a, b);
@@ -3445,7 +3445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shldi_epi64() {
+    const fn test_mm_mask_shldi_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let r = _mm_mask_shldi_epi64::<2>(a, 0, a, b);
@@ -3456,7 +3456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shldi_epi64() {
+    const fn test_mm_maskz_shldi_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(1 << 63);
         let r = _mm_maskz_shldi_epi64::<2>(0, a, b);
@@ -3467,7 +3467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shldi_epi32() {
+    const fn test_mm512_shldi_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let r = _mm512_shldi_epi32::<2>(a, b);
@@ -3476,7 +3476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shldi_epi32() {
+    const fn test_mm512_mask_shldi_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let r = _mm512_mask_shldi_epi32::<2>(a, 0, a, b);
@@ -3487,7 +3487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shldi_epi32() {
+    const fn test_mm512_maskz_shldi_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_set1_epi32(1 << 31);
         let r = _mm512_maskz_shldi_epi32::<2>(0, a, b);
@@ -3498,7 +3498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shldi_epi32() {
+    const fn test_mm256_shldi_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let r = _mm256_shldi_epi32::<2>(a, b);
@@ -3507,7 +3507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shldi_epi32() {
+    const fn test_mm256_mask_shldi_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let r = _mm256_mask_shldi_epi32::<2>(a, 0, a, b);
@@ -3518,7 +3518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shldi_epi32() {
+    const fn test_mm256_maskz_shldi_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set1_epi32(1 << 31);
         let r = _mm256_maskz_shldi_epi32::<2>(0, a, b);
@@ -3529,7 +3529,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shldi_epi32() {
+    const fn test_mm_shldi_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let r = _mm_shldi_epi32::<2>(a, b);
@@ -3538,7 +3538,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shldi_epi32() {
+    const fn test_mm_mask_shldi_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let r = _mm_mask_shldi_epi32::<2>(a, 0, a, b);
@@ -3549,7 +3549,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shldi_epi32() {
+    const fn test_mm_maskz_shldi_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set1_epi32(1 << 31);
         let r = _mm_maskz_shldi_epi32::<2>(0, a, b);
@@ -3560,7 +3560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shldi_epi16() {
+    const fn test_mm512_shldi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let r = _mm512_shldi_epi16::<2>(a, b);
@@ -3569,7 +3569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shldi_epi16() {
+    const fn test_mm512_mask_shldi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let r = _mm512_mask_shldi_epi16::<2>(a, 0, a, b);
@@ -3580,7 +3580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shldi_epi16() {
+    const fn test_mm512_maskz_shldi_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1 << 15);
         let r = _mm512_maskz_shldi_epi16::<2>(0, a, b);
@@ -3591,7 +3591,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shldi_epi16() {
+    const fn test_mm256_shldi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let r = _mm256_shldi_epi16::<2>(a, b);
@@ -3600,7 +3600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shldi_epi16() {
+    const fn test_mm256_mask_shldi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let r = _mm256_mask_shldi_epi16::<2>(a, 0, a, b);
@@ -3611,7 +3611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shldi_epi16() {
+    const fn test_mm256_maskz_shldi_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1 << 15);
         let r = _mm256_maskz_shldi_epi16::<2>(0, a, b);
@@ -3622,7 +3622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shldi_epi16() {
+    const fn test_mm_shldi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let r = _mm_shldi_epi16::<2>(a, b);
@@ -3631,7 +3631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shldi_epi16() {
+    const fn test_mm_mask_shldi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let r = _mm_mask_shldi_epi16::<2>(a, 0, a, b);
@@ -3642,7 +3642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shldi_epi16() {
+    const fn test_mm_maskz_shldi_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1 << 15);
         let r = _mm_maskz_shldi_epi16::<2>(0, a, b);
@@ -3653,7 +3653,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shrdi_epi64() {
+    const fn test_mm512_shrdi_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let r = _mm512_shrdi_epi64::<1>(a, b);
@@ -3662,7 +3662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shrdi_epi64() {
+    const fn test_mm512_mask_shrdi_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let r = _mm512_mask_shrdi_epi64::<1>(a, 0, a, b);
@@ -3673,7 +3673,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shrdi_epi64() {
+    const fn test_mm512_maskz_shrdi_epi64() {
         let a = _mm512_set1_epi64(2);
         let b = _mm512_set1_epi64(8);
         let r = _mm512_maskz_shrdi_epi64::<1>(0, a, b);
@@ -3684,7 +3684,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shrdi_epi64() {
+    const fn test_mm256_shrdi_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let r = _mm256_shrdi_epi64::<1>(a, b);
@@ -3693,7 +3693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shrdi_epi64() {
+    const fn test_mm256_mask_shrdi_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let r = _mm256_mask_shrdi_epi64::<1>(a, 0, a, b);
@@ -3704,7 +3704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shrdi_epi64() {
+    const fn test_mm256_maskz_shrdi_epi64() {
         let a = _mm256_set1_epi64x(2);
         let b = _mm256_set1_epi64x(8);
         let r = _mm256_maskz_shrdi_epi64::<1>(0, a, b);
@@ -3715,7 +3715,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shrdi_epi64() {
+    const fn test_mm_shrdi_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let r = _mm_shrdi_epi64::<1>(a, b);
@@ -3724,7 +3724,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shrdi_epi64() {
+    const fn test_mm_mask_shrdi_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let r = _mm_mask_shrdi_epi64::<1>(a, 0, a, b);
@@ -3735,7 +3735,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shrdi_epi64() {
+    const fn test_mm_maskz_shrdi_epi64() {
         let a = _mm_set1_epi64x(2);
         let b = _mm_set1_epi64x(8);
         let r = _mm_maskz_shrdi_epi64::<1>(0, a, b);
@@ -3746,7 +3746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shrdi_epi32() {
+    const fn test_mm512_shrdi_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let r = _mm512_shrdi_epi32::<1>(a, b);
@@ -3755,7 +3755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shrdi_epi32() {
+    const fn test_mm512_mask_shrdi_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let r = _mm512_mask_shrdi_epi32::<1>(a, 0, a, b);
@@ -3766,7 +3766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shrdi_epi32() {
+    const fn test_mm512_maskz_shrdi_epi32() {
         let a = _mm512_set1_epi32(2);
         let b = _mm512_set1_epi32(8);
         let r = _mm512_maskz_shrdi_epi32::<1>(0, a, b);
@@ -3777,7 +3777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shrdi_epi32() {
+    const fn test_mm256_shrdi_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let r = _mm256_shrdi_epi32::<1>(a, b);
@@ -3786,7 +3786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shrdi_epi32() {
+    const fn test_mm256_mask_shrdi_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let r = _mm256_mask_shrdi_epi32::<1>(a, 0, a, b);
@@ -3797,7 +3797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shrdi_epi32() {
+    const fn test_mm256_maskz_shrdi_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(8);
         let r = _mm256_maskz_shrdi_epi32::<1>(0, a, b);
@@ -3808,7 +3808,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shrdi_epi32() {
+    const fn test_mm_shrdi_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let r = _mm_shrdi_epi32::<1>(a, b);
@@ -3817,7 +3817,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shrdi_epi32() {
+    const fn test_mm_mask_shrdi_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let r = _mm_mask_shrdi_epi32::<1>(a, 0, a, b);
@@ -3828,7 +3828,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shrdi_epi32() {
+    const fn test_mm_maskz_shrdi_epi32() {
         let a = _mm_set1_epi32(2);
         let b = _mm_set1_epi32(8);
         let r = _mm_maskz_shrdi_epi32::<1>(0, a, b);
@@ -3839,7 +3839,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_shrdi_epi16() {
+    const fn test_mm512_shrdi_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let r = _mm512_shrdi_epi16::<1>(a, b);
@@ -3848,7 +3848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_mask_shrdi_epi16() {
+    const fn test_mm512_mask_shrdi_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let r = _mm512_mask_shrdi_epi16::<1>(a, 0, a, b);
@@ -3859,7 +3859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    const unsafe fn test_mm512_maskz_shrdi_epi16() {
+    const fn test_mm512_maskz_shrdi_epi16() {
         let a = _mm512_set1_epi16(2);
         let b = _mm512_set1_epi16(8);
         let r = _mm512_maskz_shrdi_epi16::<1>(0, a, b);
@@ -3870,7 +3870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_shrdi_epi16() {
+    const fn test_mm256_shrdi_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let r = _mm256_shrdi_epi16::<1>(a, b);
@@ -3879,7 +3879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_mask_shrdi_epi16() {
+    const fn test_mm256_mask_shrdi_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let r = _mm256_mask_shrdi_epi16::<1>(a, 0, a, b);
@@ -3890,7 +3890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm256_maskz_shrdi_epi16() {
+    const fn test_mm256_maskz_shrdi_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(8);
         let r = _mm256_maskz_shrdi_epi16::<1>(0, a, b);
@@ -3901,7 +3901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_shrdi_epi16() {
+    const fn test_mm_shrdi_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let r = _mm_shrdi_epi16::<1>(a, b);
@@ -3910,7 +3910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_mask_shrdi_epi16() {
+    const fn test_mm_mask_shrdi_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let r = _mm_mask_shrdi_epi16::<1>(a, 0, a, b);
@@ -3921,7 +3921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    const unsafe fn test_mm_maskz_shrdi_epi16() {
+    const fn test_mm_maskz_shrdi_epi16() {
         let a = _mm_set1_epi16(2);
         let b = _mm_set1_epi16(8);
         let r = _mm_maskz_shrdi_epi16::<1>(0, a, b);
diff --git a/crates/core_arch/src/x86/avx512vnni.rs b/crates/core_arch/src/x86/avx512vnni.rs
index 93ea01cbb4..49b790b151 100644
--- a/crates/core_arch/src/x86/avx512vnni.rs
+++ b/crates/core_arch/src/x86/avx512vnni.rs
@@ -970,7 +970,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_dpwssd_epi32() {
+    fn test_mm512_dpwssd_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 16 | 1 << 0);
@@ -980,7 +980,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_mask_dpwssd_epi32() {
+    fn test_mm512_mask_dpwssd_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 16 | 1 << 0);
@@ -992,7 +992,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_maskz_dpwssd_epi32() {
+    fn test_mm512_maskz_dpwssd_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 16 | 1 << 0);
@@ -1004,7 +1004,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm256_dpwssd_avx_epi32() {
+    fn test_mm256_dpwssd_avx_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1014,7 +1014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_dpwssd_epi32() {
+    fn test_mm256_dpwssd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1024,7 +1024,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_mask_dpwssd_epi32() {
+    fn test_mm256_mask_dpwssd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1036,7 +1036,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_maskz_dpwssd_epi32() {
+    fn test_mm256_maskz_dpwssd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1048,7 +1048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm_dpwssd_avx_epi32() {
+    fn test_mm_dpwssd_avx_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1058,7 +1058,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_dpwssd_epi32() {
+    fn test_mm_dpwssd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1068,7 +1068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_mask_dpwssd_epi32() {
+    fn test_mm_mask_dpwssd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1080,7 +1080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_maskz_dpwssd_epi32() {
+    fn test_mm_maskz_dpwssd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1092,7 +1092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_dpwssds_epi32() {
+    fn test_mm512_dpwssds_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 16 | 1 << 0);
@@ -1102,7 +1102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_mask_dpwssds_epi32() {
+    fn test_mm512_mask_dpwssds_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 16 | 1 << 0);
@@ -1114,7 +1114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_maskz_dpwssds_epi32() {
+    fn test_mm512_maskz_dpwssds_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 16 | 1 << 0);
@@ -1126,7 +1126,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm256_dpwssds_avx_epi32() {
+    fn test_mm256_dpwssds_avx_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1136,7 +1136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_dpwssds_epi32() {
+    fn test_mm256_dpwssds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1146,7 +1146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_mask_dpwssds_epi32() {
+    fn test_mm256_mask_dpwssds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1158,7 +1158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_maskz_dpwssds_epi32() {
+    fn test_mm256_maskz_dpwssds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1170,7 +1170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm_dpwssds_avx_epi32() {
+    fn test_mm_dpwssds_avx_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1180,7 +1180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_dpwssds_epi32() {
+    fn test_mm_dpwssds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1190,7 +1190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_mask_dpwssds_epi32() {
+    fn test_mm_mask_dpwssds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1202,7 +1202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_maskz_dpwssds_epi32() {
+    fn test_mm_maskz_dpwssds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1214,7 +1214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_dpbusd_epi32() {
+    fn test_mm512_dpbusd_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1224,7 +1224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_mask_dpbusd_epi32() {
+    fn test_mm512_mask_dpbusd_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1236,7 +1236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_maskz_dpbusd_epi32() {
+    fn test_mm512_maskz_dpbusd_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1248,7 +1248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm256_dpbusd_avx_epi32() {
+    fn test_mm256_dpbusd_avx_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1258,7 +1258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_dpbusd_epi32() {
+    fn test_mm256_dpbusd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1268,7 +1268,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_mask_dpbusd_epi32() {
+    fn test_mm256_mask_dpbusd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1280,7 +1280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_maskz_dpbusd_epi32() {
+    fn test_mm256_maskz_dpbusd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1292,7 +1292,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm_dpbusd_avx_epi32() {
+    fn test_mm_dpbusd_avx_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1302,7 +1302,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_dpbusd_epi32() {
+    fn test_mm_dpbusd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1312,7 +1312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_mask_dpbusd_epi32() {
+    fn test_mm_mask_dpbusd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1324,7 +1324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_maskz_dpbusd_epi32() {
+    fn test_mm_maskz_dpbusd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1336,7 +1336,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_dpbusds_epi32() {
+    fn test_mm512_dpbusds_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1346,7 +1346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_mask_dpbusds_epi32() {
+    fn test_mm512_mask_dpbusds_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1358,7 +1358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni")]
-    unsafe fn test_mm512_maskz_dpbusds_epi32() {
+    fn test_mm512_maskz_dpbusds_epi32() {
         let src = _mm512_set1_epi32(1);
         let a = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm512_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1370,7 +1370,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm256_dpbusds_avx_epi32() {
+    fn test_mm256_dpbusds_avx_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1380,7 +1380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_dpbusds_epi32() {
+    fn test_mm256_dpbusds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1390,7 +1390,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_mask_dpbusds_epi32() {
+    fn test_mm256_mask_dpbusds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1402,7 +1402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm256_maskz_dpbusds_epi32() {
+    fn test_mm256_maskz_dpbusds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1414,7 +1414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnni")]
-    unsafe fn test_mm_dpbusds_avx_epi32() {
+    fn test_mm_dpbusds_avx_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1424,7 +1424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_dpbusds_epi32() {
+    fn test_mm_dpbusds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1434,7 +1434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_mask_dpbusds_epi32() {
+    fn test_mm_mask_dpbusds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1446,7 +1446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vnni,avx512vl")]
-    unsafe fn test_mm_maskz_dpbusds_epi32() {
+    fn test_mm_maskz_dpbusds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1458,7 +1458,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm_dpbssd_epi32() {
+    fn test_mm_dpbssd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1468,7 +1468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm256_dpbssd_epi32() {
+    fn test_mm256_dpbssd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1478,7 +1478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm_dpbssds_epi32() {
+    fn test_mm_dpbssds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1488,7 +1488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm256_dpbssds_epi32() {
+    fn test_mm256_dpbssds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1498,7 +1498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm_dpbsud_epi32() {
+    fn test_mm_dpbsud_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1508,7 +1508,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm256_dpbsud_epi32() {
+    fn test_mm256_dpbsud_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1518,7 +1518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm_dpbsuds_epi32() {
+    fn test_mm_dpbsuds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1528,7 +1528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm256_dpbsuds_epi32() {
+    fn test_mm256_dpbsuds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1538,7 +1538,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm_dpbuud_epi32() {
+    fn test_mm_dpbuud_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1548,7 +1548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm256_dpbuud_epi32() {
+    fn test_mm256_dpbuud_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1558,7 +1558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm_dpbuuds_epi32() {
+    fn test_mm_dpbuuds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1568,7 +1568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint8")]
-    unsafe fn test_mm256_dpbuuds_epi32() {
+    fn test_mm256_dpbuuds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 24 | 1 << 16 | 1 << 8 | 1 << 0);
@@ -1578,7 +1578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm_dpwsud_epi32() {
+    fn test_mm_dpwsud_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1588,7 +1588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm256_dpwsud_epi32() {
+    fn test_mm256_dpwsud_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1598,7 +1598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm_dpwsuds_epi32() {
+    fn test_mm_dpwsuds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1608,7 +1608,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm256_dpwsuds_epi32() {
+    fn test_mm256_dpwsuds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1618,7 +1618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm_dpwusd_epi32() {
+    fn test_mm_dpwusd_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1628,7 +1628,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm256_dpwusd_epi32() {
+    fn test_mm256_dpwusd_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1638,7 +1638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm_dpwusds_epi32() {
+    fn test_mm_dpwusds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1648,7 +1648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm256_dpwusds_epi32() {
+    fn test_mm256_dpwusds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1658,7 +1658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm_dpwuud_epi32() {
+    fn test_mm_dpwuud_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1668,7 +1668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm256_dpwuud_epi32() {
+    fn test_mm256_dpwuud_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
@@ -1678,7 +1678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm_dpwuuds_epi32() {
+    fn test_mm_dpwuuds_epi32() {
         let src = _mm_set1_epi32(1);
         let a = _mm_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm_set1_epi32(1 << 16 | 1 << 0);
@@ -1688,7 +1688,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avxvnniint16")]
-    unsafe fn test_mm256_dpwuuds_epi32() {
+    fn test_mm256_dpwuuds_epi32() {
         let src = _mm256_set1_epi32(1);
         let a = _mm256_set1_epi32(1 << 16 | 1 << 0);
         let b = _mm256_set1_epi32(1 << 16 | 1 << 0);
diff --git a/crates/core_arch/src/x86/avx512vpopcntdq.rs b/crates/core_arch/src/x86/avx512vpopcntdq.rs
index 38ef54b550..476640fab5 100644
--- a/crates/core_arch/src/x86/avx512vpopcntdq.rs
+++ b/crates/core_arch/src/x86/avx512vpopcntdq.rs
@@ -351,7 +351,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    const unsafe fn test_mm512_popcnt_epi32() {
+    const fn test_mm512_popcnt_epi32() {
         let test_data = _mm512_set_epi32(
             0,
             1,
@@ -377,7 +377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    const unsafe fn test_mm512_mask_popcnt_epi32() {
+    const fn test_mm512_mask_popcnt_epi32() {
         let test_data = _mm512_set_epi32(
             0,
             1,
@@ -420,7 +420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    const unsafe fn test_mm512_maskz_popcnt_epi32() {
+    const fn test_mm512_maskz_popcnt_epi32() {
         let test_data = _mm512_set_epi32(
             0,
             1,
@@ -446,7 +446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    const unsafe fn test_mm256_popcnt_epi32() {
+    const fn test_mm256_popcnt_epi32() {
         let test_data = _mm256_set_epi32(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF, -100);
         let actual_result = _mm256_popcnt_epi32(test_data);
         let reference_result = _mm256_set_epi32(0, 1, 32, 1, 3, 15, 31, 28);
@@ -454,7 +454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_popcnt_epi32() {
+    const fn test_mm256_mask_popcnt_epi32() {
         let test_data = _mm256_set_epi32(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm256_mask_popcnt_epi32(test_data, mask, test_data);
@@ -463,7 +463,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_popcnt_epi32() {
+    const fn test_mm256_maskz_popcnt_epi32() {
         let test_data = _mm256_set_epi32(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm256_maskz_popcnt_epi32(mask, test_data);
@@ -472,7 +472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    const unsafe fn test_mm_popcnt_epi32() {
+    const fn test_mm_popcnt_epi32() {
         let test_data = _mm_set_epi32(0, 1, -1, -100);
         let actual_result = _mm_popcnt_epi32(test_data);
         let reference_result = _mm_set_epi32(0, 1, 32, 28);
@@ -480,7 +480,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_popcnt_epi32() {
+    const fn test_mm_mask_popcnt_epi32() {
         let test_data = _mm_set_epi32(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm_mask_popcnt_epi32(test_data, mask, test_data);
@@ -489,7 +489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_popcnt_epi32() {
+    const fn test_mm_maskz_popcnt_epi32() {
         let test_data = _mm_set_epi32(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm_maskz_popcnt_epi32(mask, test_data);
@@ -498,7 +498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    const unsafe fn test_mm512_popcnt_epi64() {
+    const fn test_mm512_popcnt_epi64() {
         let test_data = _mm512_set_epi64(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF_FF_FF_FF_FF, -100);
         let actual_result = _mm512_popcnt_epi64(test_data);
         let reference_result = _mm512_set_epi64(0, 1, 64, 1, 3, 15, 63, 60);
@@ -506,7 +506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    const unsafe fn test_mm512_mask_popcnt_epi64() {
+    const fn test_mm512_mask_popcnt_epi64() {
         let test_data = _mm512_set_epi64(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF_FF_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm512_mask_popcnt_epi64(test_data, mask, test_data);
@@ -516,7 +516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512f")]
-    const unsafe fn test_mm512_maskz_popcnt_epi64() {
+    const fn test_mm512_maskz_popcnt_epi64() {
         let test_data = _mm512_set_epi64(0, 1, -1, 2, 7, 0xFF_FE, 0x7F_FF_FF_FF_FF_FF_FF_FF, -100);
         let mask = 0xF0;
         let actual_result = _mm512_maskz_popcnt_epi64(mask, test_data);
@@ -525,7 +525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    const unsafe fn test_mm256_popcnt_epi64() {
+    const fn test_mm256_popcnt_epi64() {
         let test_data = _mm256_set_epi64x(0, 1, -1, -100);
         let actual_result = _mm256_popcnt_epi64(test_data);
         let reference_result = _mm256_set_epi64x(0, 1, 64, 60);
@@ -533,7 +533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    const unsafe fn test_mm256_mask_popcnt_epi64() {
+    const fn test_mm256_mask_popcnt_epi64() {
         let test_data = _mm256_set_epi64x(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm256_mask_popcnt_epi64(test_data, mask, test_data);
@@ -542,7 +542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    const unsafe fn test_mm256_maskz_popcnt_epi64() {
+    const fn test_mm256_maskz_popcnt_epi64() {
         let test_data = _mm256_set_epi64x(0, 1, -1, -100);
         let mask = 0xE;
         let actual_result = _mm256_maskz_popcnt_epi64(mask, test_data);
@@ -551,7 +551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    const unsafe fn test_mm_popcnt_epi64() {
+    const fn test_mm_popcnt_epi64() {
         let test_data = _mm_set_epi64x(0, 1);
         let actual_result = _mm_popcnt_epi64(test_data);
         let reference_result = _mm_set_epi64x(0, 1);
@@ -563,7 +563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    const unsafe fn test_mm_mask_popcnt_epi64() {
+    const fn test_mm_mask_popcnt_epi64() {
         let test_data = _mm_set_epi64x(0, -100);
         let mask = 0x2;
         let actual_result = _mm_mask_popcnt_epi64(test_data, mask, test_data);
@@ -577,7 +577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vpopcntdq,avx512vl")]
-    const unsafe fn test_mm_maskz_popcnt_epi64() {
+    const fn test_mm_maskz_popcnt_epi64() {
         let test_data = _mm_set_epi64x(0, 1);
         let mask = 0x2;
         let actual_result = _mm_maskz_popcnt_epi64(mask, test_data);
diff --git a/crates/core_arch/src/x86/bmi1.rs b/crates/core_arch/src/x86/bmi1.rs
index 11d66f699a..432051abd1 100644
--- a/crates/core_arch/src/x86/bmi1.rs
+++ b/crates/core_arch/src/x86/bmi1.rs
@@ -144,13 +144,13 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_bextr_u32() {
+    fn test_bextr_u32() {
         let r = _bextr_u32(0b0101_0000u32, 4, 4);
         assert_eq!(r, 0b0000_0101u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_andn_u32() {
+    const fn test_andn_u32() {
         assert_eq!(_andn_u32(0, 0), 0);
         assert_eq!(_andn_u32(0, 1), 1);
         assert_eq!(_andn_u32(1, 0), 0);
@@ -173,32 +173,32 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_blsi_u32() {
+    const fn test_blsi_u32() {
         assert_eq!(_blsi_u32(0b1101_0000u32), 0b0001_0000u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_blsmsk_u32() {
+    const fn test_blsmsk_u32() {
         let r = _blsmsk_u32(0b0011_0000u32);
         assert_eq!(r, 0b0001_1111u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_blsr_u32() {
+    const fn test_blsr_u32() {
         // TODO: test the behavior when the input is `0`.
         let r = _blsr_u32(0b0011_0000u32);
         assert_eq!(r, 0b0010_0000u32);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_tzcnt_u16() {
+    const fn test_tzcnt_u16() {
         assert_eq!(_tzcnt_u16(0b0000_0001u16), 0u16);
         assert_eq!(_tzcnt_u16(0b0000_0000u16), 16u16);
         assert_eq!(_tzcnt_u16(0b1001_0000u16), 4u16);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_tzcnt_u32() {
+    const fn test_tzcnt_u32() {
         assert_eq!(_tzcnt_u32(0b0000_0001u32), 0u32);
         assert_eq!(_tzcnt_u32(0b0000_0000u32), 32u32);
         assert_eq!(_tzcnt_u32(0b1001_0000u32), 4u32);
diff --git a/crates/core_arch/src/x86/bmi2.rs b/crates/core_arch/src/x86/bmi2.rs
index 54d3b5387e..5320640d96 100644
--- a/crates/core_arch/src/x86/bmi2.rs
+++ b/crates/core_arch/src/x86/bmi2.rs
@@ -84,7 +84,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_pext_u32() {
+    fn test_pext_u32() {
         let n = 0b1011_1110_1001_0011u32;
 
         let m0 = 0b0110_0011_1000_0101u32;
@@ -98,7 +98,7 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_pdep_u32() {
+    fn test_pdep_u32() {
         let n = 0b1011_1110_1001_0011u32;
 
         let m0 = 0b0110_0011_1000_0101u32;
@@ -112,14 +112,14 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_bzhi_u32() {
+    fn test_bzhi_u32() {
         let n = 0b1111_0010u32;
         let s = 0b0001_0010u32;
         assert_eq!(_bzhi_u32(n, 5), s);
     }
 
     #[simd_test(enable = "bmi2")]
-    const unsafe fn test_mulx_u32() {
+    const fn test_mulx_u32() {
         let a: u32 = 4_294_967_200;
         let b: u32 = 2;
         let mut hi = 0;
diff --git a/crates/core_arch/src/x86/f16c.rs b/crates/core_arch/src/x86/f16c.rs
index 09971939ba..0a26a9ff8d 100644
--- a/crates/core_arch/src/x86/f16c.rs
+++ b/crates/core_arch/src/x86/f16c.rs
@@ -119,7 +119,7 @@ mod tests {
     const F16_EIGHT: i16 = 0x4800;
 
     #[simd_test(enable = "f16c")]
-    const unsafe fn test_mm_cvtph_ps() {
+    const fn test_mm_cvtph_ps() {
         let a = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
         let r = _mm_cvtph_ps(a);
         let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
@@ -127,7 +127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "f16c")]
-    const unsafe fn test_mm256_cvtph_ps() {
+    const fn test_mm256_cvtph_ps() {
         let a = _mm_set_epi16(
             F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT,
         );
@@ -137,7 +137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "f16c")]
-    unsafe fn test_mm_cvtps_ph() {
+    fn test_mm_cvtps_ph() {
         let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
@@ -145,7 +145,7 @@ mod tests {
     }
 
     #[simd_test(enable = "f16c")]
-    unsafe fn test_mm256_cvtps_ph() {
+    fn test_mm256_cvtps_ph() {
         let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm256_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm_set_epi16(
diff --git a/crates/core_arch/src/x86/fma.rs b/crates/core_arch/src/x86/fma.rs
index c0900e61d9..b95bb331df 100644
--- a/crates/core_arch/src/x86/fma.rs
+++ b/crates/core_arch/src/x86/fma.rs
@@ -560,7 +560,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmadd_pd() {
+    const fn test_mm_fmadd_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -569,7 +569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmadd_pd() {
+    const fn test_mm256_fmadd_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -578,7 +578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmadd_ps() {
+    const fn test_mm_fmadd_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -587,7 +587,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmadd_ps() {
+    const fn test_mm256_fmadd_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -596,7 +596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmadd_sd() {
+    const fn test_mm_fmadd_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -605,7 +605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmadd_ss() {
+    const fn test_mm_fmadd_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -614,7 +614,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmaddsub_pd() {
+    const fn test_mm_fmaddsub_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -623,7 +623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmaddsub_pd() {
+    const fn test_mm256_fmaddsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -632,7 +632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmaddsub_ps() {
+    const fn test_mm_fmaddsub_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -641,7 +641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmaddsub_ps() {
+    const fn test_mm256_fmaddsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -650,7 +650,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmsub_pd() {
+    const fn test_mm_fmsub_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -659,7 +659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmsub_pd() {
+    const fn test_mm256_fmsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -668,7 +668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmsub_ps() {
+    const fn test_mm_fmsub_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -677,7 +677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmsub_ps() {
+    const fn test_mm256_fmsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -686,7 +686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmsub_sd() {
+    const fn test_mm_fmsub_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -695,7 +695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmsub_ss() {
+    const fn test_mm_fmsub_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -704,7 +704,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmsubadd_pd() {
+    const fn test_mm_fmsubadd_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -713,7 +713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmsubadd_pd() {
+    const fn test_mm256_fmsubadd_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -722,7 +722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fmsubadd_ps() {
+    const fn test_mm_fmsubadd_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -731,7 +731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fmsubadd_ps() {
+    const fn test_mm256_fmsubadd_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -740,7 +740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmadd_pd() {
+    const fn test_mm_fnmadd_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -749,7 +749,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fnmadd_pd() {
+    const fn test_mm256_fnmadd_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -758,7 +758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmadd_ps() {
+    const fn test_mm_fnmadd_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -767,7 +767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fnmadd_ps() {
+    const fn test_mm256_fnmadd_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -776,7 +776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmadd_sd() {
+    const fn test_mm_fnmadd_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -785,7 +785,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmadd_ss() {
+    const fn test_mm_fnmadd_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -794,7 +794,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmsub_pd() {
+    const fn test_mm_fnmsub_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -803,7 +803,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fnmsub_pd() {
+    const fn test_mm256_fnmsub_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let b = _mm256_setr_pd(5., 3., 7., 2.);
         let c = _mm256_setr_pd(4., 9., 1., 7.);
@@ -812,7 +812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmsub_ps() {
+    const fn test_mm_fnmsub_ps() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
@@ -821,7 +821,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm256_fnmsub_ps() {
+    const fn test_mm256_fnmsub_ps() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
@@ -830,7 +830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmsub_sd() {
+    const fn test_mm_fnmsub_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(5., 3.);
         let c = _mm_setr_pd(4., 9.);
@@ -839,7 +839,7 @@ mod tests {
     }
 
     #[simd_test(enable = "fma")]
-    const unsafe fn test_mm_fnmsub_ss() {
+    const fn test_mm_fnmsub_ss() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
         let b = _mm_setr_ps(5., 3., 7., 2.);
         let c = _mm_setr_ps(4., 9., 1., 7.);
diff --git a/crates/core_arch/src/x86/pclmulqdq.rs b/crates/core_arch/src/x86/pclmulqdq.rs
index efc0119030..0f2769257f 100644
--- a/crates/core_arch/src/x86/pclmulqdq.rs
+++ b/crates/core_arch/src/x86/pclmulqdq.rs
@@ -45,7 +45,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "pclmulqdq")]
-    unsafe fn test_mm_clmulepi64_si128() {
+    fn test_mm_clmulepi64_si128() {
         // Constants taken from https://software.intel.com/sites/default/files/managed/72/cc/clmul-wp-rev-2.02-2014-04-20.pdf
         let a = _mm_set_epi64x(0x7b5b546573745665, 0x63746f725d53475d);
         let b = _mm_set_epi64x(0x4869285368617929, 0x5b477565726f6e5d);
diff --git a/crates/core_arch/src/x86/sha.rs b/crates/core_arch/src/x86/sha.rs
index 9ad1a9f14c..f8a3295d19 100644
--- a/crates/core_arch/src/x86/sha.rs
+++ b/crates/core_arch/src/x86/sha.rs
@@ -286,7 +286,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha1msg1_epu32() {
+    fn test_mm_sha1msg1_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let expected = _mm_set_epi64x(0x98829f34f74ad457, 0xda2b1a44d0b5ad3c);
@@ -296,7 +296,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha1msg2_epu32() {
+    fn test_mm_sha1msg2_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let expected = _mm_set_epi64x(0xf714b202d863d47d, 0x90c30d946b3d3b35);
@@ -306,7 +306,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha1nexte_epu32() {
+    fn test_mm_sha1nexte_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let expected = _mm_set_epi64x(0x2589d5be923f82a4, 0x59f111f13956c25b);
@@ -316,7 +316,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha1rnds4_epu32() {
+    fn test_mm_sha1rnds4_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let expected = _mm_set_epi64x(0x32b13cd8322f5268, 0xc54420862bd9246f);
@@ -338,7 +338,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha256msg1_epu32() {
+    fn test_mm_sha256msg1_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let expected = _mm_set_epi64x(0xeb84973fd5cda67d, 0x2857b88f406b09ee);
@@ -348,7 +348,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha256msg2_epu32() {
+    fn test_mm_sha256msg2_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let expected = _mm_set_epi64x(0xb58777ce887fd851, 0x15d1ec8b73ac8450);
@@ -358,7 +358,7 @@ mod tests {
 
     #[simd_test(enable = "sha")]
     #[allow(overflowing_literals)]
-    unsafe fn test_mm_sha256rnds2_epu32() {
+    fn test_mm_sha256rnds2_epu32() {
         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
         let k = _mm_set_epi64x(0, 0x12835b01d807aa98);
@@ -381,7 +381,7 @@ mod tests {
     ];
 
     #[simd_test(enable = "sha512,avx")]
-    unsafe fn test_mm256_sha512msg1_epi64() {
+    fn test_mm256_sha512msg1_epi64() {
         fn s0(word: u64) -> u64 {
             word.rotate_right(1) ^ word.rotate_right(8) ^ (word >> 7)
         }
@@ -389,8 +389,8 @@ mod tests {
         let A = &DATA_64[0..4];
         let B = &DATA_64[4..6];
 
-        let a = _mm256_loadu_si256(A.as_ptr().cast());
-        let b = _mm_loadu_si128(B.as_ptr().cast());
+        let a = unsafe { _mm256_loadu_si256(A.as_ptr().cast()) };
+        let b = unsafe { _mm_loadu_si128(B.as_ptr().cast()) };
 
         let r = _mm256_sha512msg1_epi64(a, b);
 
@@ -405,7 +405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sha512,avx")]
-    unsafe fn test_mm256_sha512msg2_epi64() {
+    fn test_mm256_sha512msg2_epi64() {
         fn s1(word: u64) -> u64 {
             word.rotate_right(19) ^ word.rotate_right(61) ^ (word >> 6)
         }
@@ -413,8 +413,8 @@ mod tests {
         let A = &DATA_64[0..4];
         let B = &DATA_64[4..8];
 
-        let a = _mm256_loadu_si256(A.as_ptr().cast());
-        let b = _mm256_loadu_si256(B.as_ptr().cast());
+        let a = unsafe { _mm256_loadu_si256(A.as_ptr().cast()) };
+        let b = unsafe { _mm256_loadu_si256(B.as_ptr().cast()) };
 
         let r = _mm256_sha512msg2_epi64(a, b);
 
@@ -431,7 +431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sha512,avx")]
-    unsafe fn test_mm256_sha512rnds2_epi64() {
+    fn test_mm256_sha512rnds2_epi64() {
         fn cap_sigma0(word: u64) -> u64 {
             word.rotate_right(28) ^ word.rotate_right(34) ^ word.rotate_right(39)
         }
@@ -452,9 +452,9 @@ mod tests {
         let B = &DATA_64[4..8];
         let K = &DATA_64[8..10];
 
-        let a = _mm256_loadu_si256(A.as_ptr().cast());
-        let b = _mm256_loadu_si256(B.as_ptr().cast());
-        let k = _mm_loadu_si128(K.as_ptr().cast());
+        let a = unsafe { _mm256_loadu_si256(A.as_ptr().cast()) };
+        let b = unsafe { _mm256_loadu_si256(B.as_ptr().cast()) };
+        let k = unsafe { _mm_loadu_si128(K.as_ptr().cast()) };
 
         let r = _mm256_sha512rnds2_epi64(a, b, k);
 
@@ -482,7 +482,7 @@ mod tests {
     ];
 
     #[simd_test(enable = "sm3,avx")]
-    unsafe fn test_mm_sm3msg1_epi32() {
+    fn test_mm_sm3msg1_epi32() {
         fn p1(x: u32) -> u32 {
             x ^ x.rotate_left(15) ^ x.rotate_left(23)
         }
@@ -490,9 +490,9 @@ mod tests {
         let B = &DATA_32[4..8];
         let C = &DATA_32[8..12];
 
-        let a = _mm_loadu_si128(A.as_ptr().cast());
-        let b = _mm_loadu_si128(B.as_ptr().cast());
-        let c = _mm_loadu_si128(C.as_ptr().cast());
+        let a = unsafe { _mm_loadu_si128(A.as_ptr().cast()) };
+        let b = unsafe { _mm_loadu_si128(B.as_ptr().cast()) };
+        let c = unsafe { _mm_loadu_si128(C.as_ptr().cast()) };
 
         let r = _mm_sm3msg1_epi32(a, b, c);
 
@@ -507,14 +507,14 @@ mod tests {
     }
 
     #[simd_test(enable = "sm3,avx")]
-    unsafe fn test_mm_sm3msg2_epi32() {
+    fn test_mm_sm3msg2_epi32() {
         let A = &DATA_32[0..4];
         let B = &DATA_32[4..8];
         let C = &DATA_32[8..12];
 
-        let a = _mm_loadu_si128(A.as_ptr().cast());
-        let b = _mm_loadu_si128(B.as_ptr().cast());
-        let c = _mm_loadu_si128(C.as_ptr().cast());
+        let a = unsafe { _mm_loadu_si128(A.as_ptr().cast()) };
+        let b = unsafe { _mm_loadu_si128(B.as_ptr().cast()) };
+        let c = unsafe { _mm_loadu_si128(C.as_ptr().cast()) };
 
         let r = _mm_sm3msg2_epi32(a, b, c);
 
@@ -535,7 +535,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sm3,avx")]
-    unsafe fn test_mm_sm3rnds2_epi32() {
+    fn test_mm_sm3rnds2_epi32() {
         fn p0(x: u32) -> u32 {
             x ^ x.rotate_left(9) ^ x.rotate_left(17)
         }
@@ -560,9 +560,9 @@ mod tests {
         let B = &DATA_32[4..8];
         let C = &DATA_32[8..12];
 
-        let a = _mm_loadu_si128(A.as_ptr().cast());
-        let b = _mm_loadu_si128(B.as_ptr().cast());
-        let c = _mm_loadu_si128(C.as_ptr().cast());
+        let a = unsafe { _mm_loadu_si128(A.as_ptr().cast()) };
+        let b = unsafe { _mm_loadu_si128(B.as_ptr().cast()) };
+        let c = unsafe { _mm_loadu_si128(C.as_ptr().cast()) };
 
         let r = _mm_sm3rnds2_epi32::<{ ROUND as i32 }>(a, b, c);
 
@@ -641,7 +641,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sm4,avx")]
-    unsafe fn test_mm_sm4key4_epi32() {
+    fn test_mm_sm4key4_epi32() {
         fn l_key(x: u32) -> u32 {
             x ^ x.rotate_left(13) ^ x.rotate_left(23)
         }
@@ -652,8 +652,8 @@ mod tests {
         let A = &DATA_32[0..4];
         let B = &DATA_32[4..8];
 
-        let a = _mm_loadu_si128(A.as_ptr().cast());
-        let b = _mm_loadu_si128(B.as_ptr().cast());
+        let a = unsafe { _mm_loadu_si128(A.as_ptr().cast()) };
+        let b = unsafe { _mm_loadu_si128(B.as_ptr().cast()) };
 
         let r = _mm_sm4key4_epi32(a, b);
 
@@ -667,11 +667,11 @@ mod tests {
     }
 
     #[simd_test(enable = "sm4,avx")]
-    unsafe fn test_mm256_sm4key4_epi32() {
-        let a_low = _mm_loadu_si128(DATA_32.as_ptr().cast());
-        let a_high = _mm_loadu_si128(DATA_32[4..].as_ptr().cast());
-        let b_low = _mm_loadu_si128(DATA_32[8..].as_ptr().cast());
-        let b_high = _mm_loadu_si128(DATA_32[12..].as_ptr().cast());
+    fn test_mm256_sm4key4_epi32() {
+        let a_low = unsafe { _mm_loadu_si128(DATA_32.as_ptr().cast()) };
+        let a_high = unsafe { _mm_loadu_si128(DATA_32[4..].as_ptr().cast()) };
+        let b_low = unsafe { _mm_loadu_si128(DATA_32[8..].as_ptr().cast()) };
+        let b_high = unsafe { _mm_loadu_si128(DATA_32[12..].as_ptr().cast()) };
 
         let a = _mm256_set_m128i(a_high, a_low);
         let b = _mm256_set_m128i(b_high, b_low);
@@ -686,7 +686,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sm4,avx")]
-    unsafe fn test_mm_sm4rnds4_epi32() {
+    fn test_mm_sm4rnds4_epi32() {
         fn l_rnd(x: u32) -> u32 {
             x ^ x.rotate_left(2) ^ x.rotate_left(10) ^ x.rotate_left(18) ^ x.rotate_left(24)
         }
@@ -697,8 +697,8 @@ mod tests {
         let A = &DATA_32[0..4];
         let B = &DATA_32[4..8];
 
-        let a = _mm_loadu_si128(A.as_ptr().cast());
-        let b = _mm_loadu_si128(B.as_ptr().cast());
+        let a = unsafe { _mm_loadu_si128(A.as_ptr().cast()) };
+        let b = unsafe { _mm_loadu_si128(B.as_ptr().cast()) };
 
         let r = _mm_sm4rnds4_epi32(a, b);
 
@@ -712,11 +712,11 @@ mod tests {
     }
 
     #[simd_test(enable = "sm4,avx")]
-    unsafe fn test_mm256_sm4rnds4_epi32() {
-        let a_low = _mm_loadu_si128(DATA_32.as_ptr().cast());
-        let a_high = _mm_loadu_si128(DATA_32[4..].as_ptr().cast());
-        let b_low = _mm_loadu_si128(DATA_32[8..].as_ptr().cast());
-        let b_high = _mm_loadu_si128(DATA_32[12..].as_ptr().cast());
+    fn test_mm256_sm4rnds4_epi32() {
+        let a_low = unsafe { _mm_loadu_si128(DATA_32.as_ptr().cast()) };
+        let a_high = unsafe { _mm_loadu_si128(DATA_32[4..].as_ptr().cast()) };
+        let b_low = unsafe { _mm_loadu_si128(DATA_32[8..].as_ptr().cast()) };
+        let b_high = unsafe { _mm_loadu_si128(DATA_32[12..].as_ptr().cast()) };
 
         let a = _mm256_set_m128i(a_high, a_low);
         let b = _mm256_set_m128i(b_high, b_low);
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 165c61104e..55392f9944 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2088,7 +2088,7 @@ mod tests {
     const NAN: f32 = f32::NAN;
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_add_ps() {
+    const fn test_mm_add_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_add_ps(a, b);
@@ -2096,7 +2096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_add_ss() {
+    const fn test_mm_add_ss() {
         let a = _mm_set_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_set_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_add_ss(a, b);
@@ -2104,7 +2104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_sub_ps() {
+    const fn test_mm_sub_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_sub_ps(a, b);
@@ -2112,7 +2112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_sub_ss() {
+    const fn test_mm_sub_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_sub_ss(a, b);
@@ -2120,7 +2120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_mul_ps() {
+    const fn test_mm_mul_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_mul_ps(a, b);
@@ -2128,7 +2128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_mul_ss() {
+    const fn test_mm_mul_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_mul_ss(a, b);
@@ -2136,7 +2136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_div_ps() {
+    const fn test_mm_div_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 2.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.2, -5.0);
         let r = _mm_div_ps(a, b);
@@ -2144,7 +2144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_div_ss() {
+    const fn test_mm_div_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_div_ss(a, b);
@@ -2152,7 +2152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_sqrt_ss() {
+    fn test_mm_sqrt_ss() {
         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
         let r = _mm_sqrt_ss(a);
         let e = _mm_setr_ps(2.0, 13.0, 16.0, 100.0);
@@ -2160,7 +2160,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_sqrt_ps() {
+    fn test_mm_sqrt_ps() {
         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
         let r = _mm_sqrt_ps(a);
         let e = _mm_setr_ps(2.0, 3.6055512, 4.0, 10.0);
@@ -2168,7 +2168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_rcp_ss() {
+    fn test_mm_rcp_ss() {
         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
         let r = _mm_rcp_ss(a);
         let e = _mm_setr_ps(0.24993896, 13.0, 16.0, 100.0);
@@ -2180,7 +2180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_rcp_ps() {
+    fn test_mm_rcp_ps() {
         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
         let r = _mm_rcp_ps(a);
         let e = _mm_setr_ps(0.24993896, 0.0769043, 0.06248474, 0.0099983215);
@@ -2191,7 +2191,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_rsqrt_ss() {
+    fn test_mm_rsqrt_ss() {
         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
         let r = _mm_rsqrt_ss(a);
         let e = _mm_setr_ps(0.49987793, 13.0, 16.0, 100.0);
@@ -2202,7 +2202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_rsqrt_ps() {
+    fn test_mm_rsqrt_ps() {
         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
         let r = _mm_rsqrt_ps(a);
         let e = _mm_setr_ps(0.49987793, 0.2772827, 0.24993896, 0.099990845);
@@ -2213,7 +2213,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_min_ss() {
+    fn test_mm_min_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_min_ss(a, b);
@@ -2244,7 +2244,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_max_ss() {
+    fn test_mm_max_ss() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_max_ss(a, b);
@@ -2749,7 +2749,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_comieq_ss() {
+    fn test_mm_comieq_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2770,7 +2770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_comilt_ss() {
+    fn test_mm_comilt_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2791,7 +2791,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_comile_ss() {
+    fn test_mm_comile_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2812,7 +2812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_comigt_ss() {
+    fn test_mm_comigt_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2833,7 +2833,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_comineq_ss() {
+    fn test_mm_comineq_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2854,7 +2854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_ucomieq_ss() {
+    fn test_mm_ucomieq_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2875,7 +2875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_ucomilt_ss() {
+    fn test_mm_ucomilt_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2896,7 +2896,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_ucomile_ss() {
+    fn test_mm_ucomile_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2917,7 +2917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_ucomigt_ss() {
+    fn test_mm_ucomigt_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2938,7 +2938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_ucomige_ss() {
+    fn test_mm_ucomige_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2959,7 +2959,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_ucomineq_ss() {
+    fn test_mm_ucomineq_ss() {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
@@ -2980,7 +2980,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtss_si32() {
+    fn test_mm_cvtss_si32() {
         let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
         let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
         for i in 0..inputs.len() {
@@ -2996,7 +2996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvttss_si32() {
+    fn test_mm_cvttss_si32() {
         let inputs = &[
             (42.0f32, 42i32),
             (-31.4, -31),
@@ -3021,7 +3021,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_cvtsi32_ss() {
+    const fn test_mm_cvtsi32_ss() {
         let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
         let r = _mm_cvtsi32_ss(a, 4555);
@@ -3042,19 +3042,19 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_cvtss_f32() {
+    const fn test_mm_cvtss_f32() {
         let a = _mm_setr_ps(312.0134, 5.0, 6.0, 7.0);
         assert_eq!(_mm_cvtss_f32(a), 312.0134);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_set_ss() {
+    const fn test_mm_set_ss() {
         let r = _mm_set_ss(black_box(4.25));
         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_set1_ps() {
+    const fn test_mm_set1_ps() {
         let r1 = _mm_set1_ps(black_box(4.25));
         let r2 = _mm_set_ps1(black_box(4.25));
         assert_eq!(get_m128(r1, 0), 4.25);
@@ -3068,7 +3068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_set_ps() {
+    const fn test_mm_set_ps() {
         let r = _mm_set_ps(
             black_box(1.0),
             black_box(2.0),
@@ -3082,7 +3082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_setr_ps() {
+    const fn test_mm_setr_ps() {
         let r = _mm_setr_ps(
             black_box(1.0),
             black_box(2.0),
@@ -3093,7 +3093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_setzero_ps() {
+    const fn test_mm_setzero_ps() {
         let r = *black_box(&_mm_setzero_ps());
         assert_eq_m128(r, _mm_set1_ps(0.0));
     }
@@ -3107,7 +3107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_shuffle_ps() {
+    const fn test_mm_shuffle_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_shuffle_ps::<0b00_01_01_11>(a, b);
@@ -3115,7 +3115,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_unpackhi_ps() {
+    const fn test_mm_unpackhi_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_unpackhi_ps(a, b);
@@ -3123,7 +3123,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_unpacklo_ps() {
+    const fn test_mm_unpacklo_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_unpacklo_ps(a, b);
@@ -3131,7 +3131,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_movehl_ps() {
+    const fn test_mm_movehl_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_movehl_ps(a, b);
@@ -3139,7 +3139,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_movelh_ps() {
+    const fn test_mm_movelh_ps() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let r = _mm_movelh_ps(a, b);
@@ -3266,7 +3266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_move_ss() {
+    const fn test_mm_move_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
@@ -3276,7 +3276,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_movemask_ps() {
+    const fn test_mm_movemask_ps() {
         let r = _mm_movemask_ps(_mm_setr_ps(-1.0, 5.0, -5.0, 0.0));
         assert_eq!(r, 0b0101);
 
@@ -3287,12 +3287,12 @@ mod tests {
     #[simd_test(enable = "sse")]
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_sfence() {
+    fn test_mm_sfence() {
         _mm_sfence();
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_MM_TRANSPOSE4_PS() {
+    const fn test_MM_TRANSPOSE4_PS() {
         let mut a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let mut b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
         let mut c = _mm_setr_ps(9.0, 10.0, 11.0, 12.0);
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index 098cd67c02..d7ac00287f 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -3295,19 +3295,19 @@ mod tests {
     #[simd_test(enable = "sse2")]
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_lfence() {
+    fn test_mm_lfence() {
         _mm_lfence();
     }
 
     #[simd_test(enable = "sse2")]
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_mfence() {
+    fn test_mm_mfence() {
         _mm_mfence();
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_add_epi8() {
+    const fn test_mm_add_epi8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let b = _mm_setr_epi8(
@@ -3322,7 +3322,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_add_epi8_overflow() {
+    fn test_mm_add_epi8_overflow() {
         let a = _mm_set1_epi8(0x7F);
         let b = _mm_set1_epi8(1);
         let r = _mm_add_epi8(a, b);
@@ -3330,7 +3330,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_add_epi16() {
+    const fn test_mm_add_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_add_epi16(a, b);
@@ -3339,7 +3339,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_add_epi32() {
+    const fn test_mm_add_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(4, 5, 6, 7);
         let r = _mm_add_epi32(a, b);
@@ -3348,7 +3348,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_add_epi64() {
+    const fn test_mm_add_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(2, 3);
         let r = _mm_add_epi64(a, b);
@@ -3357,7 +3357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_adds_epi8() {
+    const fn test_mm_adds_epi8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let b = _mm_setr_epi8(
@@ -3372,7 +3372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epi8_saturate_positive() {
+    fn test_mm_adds_epi8_saturate_positive() {
         let a = _mm_set1_epi8(0x7F);
         let b = _mm_set1_epi8(1);
         let r = _mm_adds_epi8(a, b);
@@ -3380,7 +3380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epi8_saturate_negative() {
+    fn test_mm_adds_epi8_saturate_negative() {
         let a = _mm_set1_epi8(-0x80);
         let b = _mm_set1_epi8(-1);
         let r = _mm_adds_epi8(a, b);
@@ -3388,7 +3388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_adds_epi16() {
+    const fn test_mm_adds_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_adds_epi16(a, b);
@@ -3397,7 +3397,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epi16_saturate_positive() {
+    fn test_mm_adds_epi16_saturate_positive() {
         let a = _mm_set1_epi16(0x7FFF);
         let b = _mm_set1_epi16(1);
         let r = _mm_adds_epi16(a, b);
@@ -3405,7 +3405,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epi16_saturate_negative() {
+    fn test_mm_adds_epi16_saturate_negative() {
         let a = _mm_set1_epi16(-0x8000);
         let b = _mm_set1_epi16(-1);
         let r = _mm_adds_epi16(a, b);
@@ -3413,7 +3413,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_adds_epu8() {
+    const fn test_mm_adds_epu8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         #[rustfmt::skip]
         let b = _mm_setr_epi8(
@@ -3428,7 +3428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epu8_saturate() {
+    fn test_mm_adds_epu8_saturate() {
         let a = _mm_set1_epi8(!0);
         let b = _mm_set1_epi8(1);
         let r = _mm_adds_epu8(a, b);
@@ -3436,7 +3436,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_adds_epu16() {
+    const fn test_mm_adds_epu16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_adds_epu16(a, b);
@@ -3445,7 +3445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_adds_epu16_saturate() {
+    fn test_mm_adds_epu16_saturate() {
         let a = _mm_set1_epi16(!0);
         let b = _mm_set1_epi16(1);
         let r = _mm_adds_epu16(a, b);
@@ -3453,21 +3453,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_avg_epu8() {
+    const fn test_mm_avg_epu8() {
         let (a, b) = (_mm_set1_epi8(3), _mm_set1_epi8(9));
         let r = _mm_avg_epu8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(6));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_avg_epu16() {
+    const fn test_mm_avg_epu16() {
         let (a, b) = (_mm_set1_epi16(3), _mm_set1_epi16(9));
         let r = _mm_avg_epu16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(6));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_madd_epi16() {
+    const fn test_mm_madd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm_madd_epi16(a, b);
@@ -3502,7 +3502,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_max_epi16() {
+    const fn test_mm_max_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let r = _mm_max_epi16(a, b);
@@ -3510,7 +3510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_max_epu8() {
+    const fn test_mm_max_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(!0);
         let r = _mm_max_epu8(a, b);
@@ -3518,7 +3518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_min_epi16() {
+    const fn test_mm_min_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(-1);
         let r = _mm_min_epi16(a, b);
@@ -3526,7 +3526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_min_epu8() {
+    const fn test_mm_min_epu8() {
         let a = _mm_set1_epi8(1);
         let b = _mm_set1_epi8(!0);
         let r = _mm_min_epu8(a, b);
@@ -3534,28 +3534,28 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_mulhi_epi16() {
+    const fn test_mm_mulhi_epi16() {
         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(-1001));
         let r = _mm_mulhi_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(-16));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_mulhi_epu16() {
+    const fn test_mm_mulhi_epu16() {
         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(1001));
         let r = _mm_mulhi_epu16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(15));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_mullo_epi16() {
+    const fn test_mm_mullo_epi16() {
         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(-1001));
         let r = _mm_mullo_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(-17960));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_mul_epu32() {
+    const fn test_mm_mul_epu32() {
         let a = _mm_setr_epi64x(1_000_000_000, 1 << 34);
         let b = _mm_setr_epi64x(1_000_000_000, 1 << 35);
         let r = _mm_mul_epu32(a, b);
@@ -3564,7 +3564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sad_epu8() {
+    fn test_mm_sad_epu8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             255u8 as i8, 254u8 as i8, 253u8 as i8, 252u8 as i8,
@@ -3579,42 +3579,42 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_sub_epi8() {
+    const fn test_mm_sub_epi8() {
         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(6));
         let r = _mm_sub_epi8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_sub_epi16() {
+    const fn test_mm_sub_epi16() {
         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(6));
         let r = _mm_sub_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_sub_epi32() {
+    const fn test_mm_sub_epi32() {
         let (a, b) = (_mm_set1_epi32(5), _mm_set1_epi32(6));
         let r = _mm_sub_epi32(a, b);
         assert_eq_m128i(r, _mm_set1_epi32(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_sub_epi64() {
+    const fn test_mm_sub_epi64() {
         let (a, b) = (_mm_set1_epi64x(5), _mm_set1_epi64x(6));
         let r = _mm_sub_epi64(a, b);
         assert_eq_m128i(r, _mm_set1_epi64x(-1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_subs_epi8() {
+    const fn test_mm_subs_epi8() {
         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(2));
         let r = _mm_subs_epi8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(3));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epi8_saturate_positive() {
+    fn test_mm_subs_epi8_saturate_positive() {
         let a = _mm_set1_epi8(0x7F);
         let b = _mm_set1_epi8(-1);
         let r = _mm_subs_epi8(a, b);
@@ -3622,7 +3622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epi8_saturate_negative() {
+    fn test_mm_subs_epi8_saturate_negative() {
         let a = _mm_set1_epi8(-0x80);
         let b = _mm_set1_epi8(1);
         let r = _mm_subs_epi8(a, b);
@@ -3630,14 +3630,14 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_subs_epi16() {
+    const fn test_mm_subs_epi16() {
         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(2));
         let r = _mm_subs_epi16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(3));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epi16_saturate_positive() {
+    fn test_mm_subs_epi16_saturate_positive() {
         let a = _mm_set1_epi16(0x7FFF);
         let b = _mm_set1_epi16(-1);
         let r = _mm_subs_epi16(a, b);
@@ -3645,7 +3645,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epi16_saturate_negative() {
+    fn test_mm_subs_epi16_saturate_negative() {
         let a = _mm_set1_epi16(-0x8000);
         let b = _mm_set1_epi16(1);
         let r = _mm_subs_epi16(a, b);
@@ -3653,14 +3653,14 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_subs_epu8() {
+    const fn test_mm_subs_epu8() {
         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(2));
         let r = _mm_subs_epu8(a, b);
         assert_eq_m128i(r, _mm_set1_epi8(3));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epu8_saturate() {
+    fn test_mm_subs_epu8_saturate() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set1_epi8(1);
         let r = _mm_subs_epu8(a, b);
@@ -3668,14 +3668,14 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_subs_epu16() {
+    const fn test_mm_subs_epu16() {
         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(2));
         let r = _mm_subs_epu16(a, b);
         assert_eq_m128i(r, _mm_set1_epi16(3));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_subs_epu16_saturate() {
+    fn test_mm_subs_epu16_saturate() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let r = _mm_subs_epu16(a, b);
@@ -3683,7 +3683,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_slli_si128() {
+    const fn test_mm_slli_si128() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@@ -3709,7 +3709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_slli_epi16() {
+    const fn test_mm_slli_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_slli_epi16::<4>(a);
         assert_eq_m128i(
@@ -3737,7 +3737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_slli_epi32() {
+    const fn test_mm_slli_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_slli_epi32::<4>(a);
         assert_eq_m128i(r, _mm_setr_epi32(0xEEEE0, -0xEEEE0, 0xFFFF0, -0xFFFF0));
@@ -3746,7 +3746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sll_epi32() {
+    fn test_mm_sll_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_sll_epi32(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(r, _mm_setr_epi32(0xEEEE0, -0xEEEE0, 0xFFFF0, -0xFFFF0));
@@ -3759,7 +3759,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_slli_epi64() {
+    const fn test_mm_slli_epi64() {
         let a = _mm_set_epi64x(0xFFFFFFFF, -0xFFFFFFFF);
         let r = _mm_slli_epi64::<4>(a);
         assert_eq_m128i(r, _mm_set_epi64x(0xFFFFFFFF0, -0xFFFFFFFF0));
@@ -3768,7 +3768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sll_epi64() {
+    fn test_mm_sll_epi64() {
         let a = _mm_set_epi64x(0xFFFFFFFF, -0xFFFFFFFF);
         let r = _mm_sll_epi64(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(r, _mm_set_epi64x(0xFFFFFFFF0, -0xFFFFFFFF0));
@@ -3781,7 +3781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_srai_epi16() {
+    const fn test_mm_srai_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_srai_epi16::<4>(a);
         assert_eq_m128i(
@@ -3793,7 +3793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sra_epi16() {
+    fn test_mm_sra_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_sra_epi16(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(
@@ -3809,7 +3809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_srai_epi32() {
+    const fn test_mm_srai_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_srai_epi32::<4>(a);
         assert_eq_m128i(r, _mm_setr_epi32(0xEEE, -0xEEF, 0xFFF, -0x1000));
@@ -3818,7 +3818,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sra_epi32() {
+    fn test_mm_sra_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_sra_epi32(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(r, _mm_setr_epi32(0xEEE, -0xEEF, 0xFFF, -0x1000));
@@ -3831,7 +3831,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_srli_si128() {
+    const fn test_mm_srli_si128() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@@ -3860,7 +3860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_srli_epi16() {
+    const fn test_mm_srli_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_srli_epi16::<4>(a);
         assert_eq_m128i(
@@ -3872,7 +3872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srl_epi16() {
+    fn test_mm_srl_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_srl_epi16(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(
@@ -3888,7 +3888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_srli_epi32() {
+    const fn test_mm_srli_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_srli_epi32::<4>(a);
         assert_eq_m128i(r, _mm_setr_epi32(0xEEE, 0xFFFF111, 0xFFF, 0xFFFF000));
@@ -3897,7 +3897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srl_epi32() {
+    fn test_mm_srl_epi32() {
         let a = _mm_setr_epi32(0xEEEE, -0xEEEE, 0xFFFF, -0xFFFF);
         let r = _mm_srl_epi32(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(r, _mm_setr_epi32(0xEEE, 0xFFFF111, 0xFFF, 0xFFFF000));
@@ -3910,7 +3910,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_srli_epi64() {
+    const fn test_mm_srli_epi64() {
         let a = _mm_set_epi64x(0xFFFFFFFF, -0xFFFFFFFF);
         let r = _mm_srli_epi64::<4>(a);
         assert_eq_m128i(r, _mm_set_epi64x(0xFFFFFFF, 0xFFFFFFFF0000000));
@@ -3919,7 +3919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_srl_epi64() {
+    fn test_mm_srl_epi64() {
         let a = _mm_set_epi64x(0xFFFFFFFF, -0xFFFFFFFF);
         let r = _mm_srl_epi64(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(r, _mm_set_epi64x(0xFFFFFFF, 0xFFFFFFFF0000000));
@@ -3932,7 +3932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_and_si128() {
+    const fn test_mm_and_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_and_si128(a, b);
@@ -3940,7 +3940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_andnot_si128() {
+    const fn test_mm_andnot_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_andnot_si128(a, b);
@@ -3948,7 +3948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_or_si128() {
+    const fn test_mm_or_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_or_si128(a, b);
@@ -3956,7 +3956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_xor_si128() {
+    const fn test_mm_xor_si128() {
         let a = _mm_set1_epi8(5);
         let b = _mm_set1_epi8(3);
         let r = _mm_xor_si128(a, b);
@@ -3964,7 +3964,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmpeq_epi8() {
+    const fn test_mm_cmpeq_epi8() {
         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = _mm_setr_epi8(15, 14, 2, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm_cmpeq_epi8(a, b);
@@ -3978,7 +3978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmpeq_epi16() {
+    const fn test_mm_cmpeq_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(7, 6, 2, 4, 3, 2, 1, 0);
         let r = _mm_cmpeq_epi16(a, b);
@@ -3986,7 +3986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmpeq_epi32() {
+    const fn test_mm_cmpeq_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(3, 2, 2, 0);
         let r = _mm_cmpeq_epi32(a, b);
@@ -3994,7 +3994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmpgt_epi8() {
+    const fn test_mm_cmpgt_epi8() {
         let a = _mm_set_epi8(5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let b = _mm_set1_epi8(0);
         let r = _mm_cmpgt_epi8(a, b);
@@ -4003,7 +4003,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmpgt_epi16() {
+    const fn test_mm_cmpgt_epi16() {
         let a = _mm_set_epi16(5, 0, 0, 0, 0, 0, 0, 0);
         let b = _mm_set1_epi16(0);
         let r = _mm_cmpgt_epi16(a, b);
@@ -4012,7 +4012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmpgt_epi32() {
+    const fn test_mm_cmpgt_epi32() {
         let a = _mm_set_epi32(5, 0, 0, 0);
         let b = _mm_set1_epi32(0);
         let r = _mm_cmpgt_epi32(a, b);
@@ -4020,7 +4020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmplt_epi8() {
+    const fn test_mm_cmplt_epi8() {
         let a = _mm_set1_epi8(0);
         let b = _mm_set_epi8(5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm_cmplt_epi8(a, b);
@@ -4029,7 +4029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmplt_epi16() {
+    const fn test_mm_cmplt_epi16() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set_epi16(5, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm_cmplt_epi16(a, b);
@@ -4038,7 +4038,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cmplt_epi32() {
+    const fn test_mm_cmplt_epi32() {
         let a = _mm_set1_epi32(0);
         let b = _mm_set_epi32(5, 0, 0, 0);
         let r = _mm_cmplt_epi32(a, b);
@@ -4046,21 +4046,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtepi32_pd() {
+    const fn test_mm_cvtepi32_pd() {
         let a = _mm_set_epi32(35, 25, 15, 5);
         let r = _mm_cvtepi32_pd(a);
         assert_eq_m128d(r, _mm_setr_pd(5.0, 15.0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsi32_sd() {
+    const fn test_mm_cvtsi32_sd() {
         let a = _mm_set1_pd(3.5);
         let r = _mm_cvtsi32_sd(a, 5);
         assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtepi32_ps() {
+    const fn test_mm_cvtepi32_ps() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let r = _mm_cvtepi32_ps(a);
         assert_eq_m128(r, _mm_setr_ps(1.0, 2.0, 3.0, 4.0));
@@ -4074,37 +4074,37 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsi32_si128() {
+    const fn test_mm_cvtsi32_si128() {
         let r = _mm_cvtsi32_si128(5);
         assert_eq_m128i(r, _mm_setr_epi32(5, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsi128_si32() {
+    const fn test_mm_cvtsi128_si32() {
         let r = _mm_cvtsi128_si32(_mm_setr_epi32(5, 0, 0, 0));
         assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_epi64x() {
+    const fn test_mm_set_epi64x() {
         let r = _mm_set_epi64x(0, 1);
         assert_eq_m128i(r, _mm_setr_epi64x(1, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_epi32() {
+    const fn test_mm_set_epi32() {
         let r = _mm_set_epi32(0, 1, 2, 3);
         assert_eq_m128i(r, _mm_setr_epi32(3, 2, 1, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_epi16() {
+    const fn test_mm_set_epi16() {
         let r = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m128i(r, _mm_setr_epi16(7, 6, 5, 4, 3, 2, 1, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_epi8() {
+    const fn test_mm_set_epi8() {
         #[rustfmt::skip]
         let r = _mm_set_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -4118,43 +4118,43 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set1_epi64x() {
+    const fn test_mm_set1_epi64x() {
         let r = _mm_set1_epi64x(1);
         assert_eq_m128i(r, _mm_set1_epi64x(1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set1_epi32() {
+    const fn test_mm_set1_epi32() {
         let r = _mm_set1_epi32(1);
         assert_eq_m128i(r, _mm_set1_epi32(1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set1_epi16() {
+    const fn test_mm_set1_epi16() {
         let r = _mm_set1_epi16(1);
         assert_eq_m128i(r, _mm_set1_epi16(1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set1_epi8() {
+    const fn test_mm_set1_epi8() {
         let r = _mm_set1_epi8(1);
         assert_eq_m128i(r, _mm_set1_epi8(1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_setr_epi32() {
+    const fn test_mm_setr_epi32() {
         let r = _mm_setr_epi32(0, 1, 2, 3);
         assert_eq_m128i(r, _mm_setr_epi32(0, 1, 2, 3));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_setr_epi16() {
+    const fn test_mm_setr_epi16() {
         let r = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m128i(r, _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_setr_epi8() {
+    const fn test_mm_setr_epi8() {
         #[rustfmt::skip]
         let r = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@@ -4168,7 +4168,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_setzero_si128() {
+    const fn test_mm_setzero_si128() {
         let r = _mm_setzero_si128();
         assert_eq_m128i(r, _mm_set1_epi64x(0));
     }
@@ -4261,14 +4261,14 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_move_epi64() {
+    const fn test_mm_move_epi64() {
         let a = _mm_setr_epi64x(5, 6);
         let r = _mm_move_epi64(a);
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_packs_epi16() {
+    fn test_mm_packs_epi16() {
         let a = _mm_setr_epi16(0x80, -0x81, 0, 0, 0, 0, 0, 0);
         let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -0x81, 0x80);
         let r = _mm_packs_epi16(a, b);
@@ -4282,7 +4282,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_packs_epi32() {
+    fn test_mm_packs_epi32() {
         let a = _mm_setr_epi32(0x8000, -0x8001, 0, 0);
         let b = _mm_setr_epi32(0, 0, -0x8001, 0x8000);
         let r = _mm_packs_epi32(a, b);
@@ -4293,7 +4293,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_packus_epi16() {
+    fn test_mm_packus_epi16() {
         let a = _mm_setr_epi16(0x100, -1, 0, 0, 0, 0, 0, 0);
         let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -1, 0x100);
         let r = _mm_packus_epi16(a, b);
@@ -4304,7 +4304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_extract_epi16() {
+    const fn test_mm_extract_epi16() {
         let a = _mm_setr_epi16(-1, 1, 2, 3, 4, 5, 6, 7);
         let r1 = _mm_extract_epi16::<0>(a);
         let r2 = _mm_extract_epi16::<3>(a);
@@ -4313,7 +4313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_insert_epi16() {
+    const fn test_mm_insert_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm_insert_epi16::<0>(a, 9);
         let e = _mm_setr_epi16(9, 1, 2, 3, 4, 5, 6, 7);
@@ -4321,7 +4321,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_movemask_epi8() {
+    const fn test_mm_movemask_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0b1000_0000u8 as i8, 0b0, 0b1000_0000u8 as i8, 0b01,
@@ -4334,7 +4334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_shuffle_epi32() {
+    const fn test_mm_shuffle_epi32() {
         let a = _mm_setr_epi32(5, 10, 15, 20);
         let r = _mm_shuffle_epi32::<0b00_01_01_11>(a);
         let e = _mm_setr_epi32(20, 10, 10, 5);
@@ -4342,7 +4342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_shufflehi_epi16() {
+    const fn test_mm_shufflehi_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 10, 15, 20);
         let r = _mm_shufflehi_epi16::<0b00_01_01_11>(a);
         let e = _mm_setr_epi16(1, 2, 3, 4, 20, 10, 10, 5);
@@ -4350,7 +4350,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_shufflelo_epi16() {
+    const fn test_mm_shufflelo_epi16() {
         let a = _mm_setr_epi16(5, 10, 15, 20, 1, 2, 3, 4);
         let r = _mm_shufflelo_epi16::<0b00_01_01_11>(a);
         let e = _mm_setr_epi16(20, 10, 10, 5, 1, 2, 3, 4);
@@ -4358,7 +4358,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpackhi_epi8() {
+    const fn test_mm_unpackhi_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4377,7 +4377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpackhi_epi16() {
+    const fn test_mm_unpackhi_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_unpackhi_epi16(a, b);
@@ -4386,7 +4386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpackhi_epi32() {
+    const fn test_mm_unpackhi_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(4, 5, 6, 7);
         let r = _mm_unpackhi_epi32(a, b);
@@ -4395,7 +4395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpackhi_epi64() {
+    const fn test_mm_unpackhi_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(2, 3);
         let r = _mm_unpackhi_epi64(a, b);
@@ -4404,7 +4404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpacklo_epi8() {
+    const fn test_mm_unpacklo_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -4424,7 +4424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpacklo_epi16() {
+    const fn test_mm_unpacklo_epi16() {
         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_unpacklo_epi16(a, b);
@@ -4433,7 +4433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpacklo_epi32() {
+    const fn test_mm_unpacklo_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let b = _mm_setr_epi32(4, 5, 6, 7);
         let r = _mm_unpacklo_epi32(a, b);
@@ -4442,7 +4442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpacklo_epi64() {
+    const fn test_mm_unpacklo_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(2, 3);
         let r = _mm_unpacklo_epi64(a, b);
@@ -4451,7 +4451,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_add_sd() {
+    const fn test_mm_add_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_add_sd(a, b);
@@ -4459,7 +4459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_add_pd() {
+    const fn test_mm_add_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_add_pd(a, b);
@@ -4467,7 +4467,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_div_sd() {
+    const fn test_mm_div_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_div_sd(a, b);
@@ -4475,7 +4475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_div_pd() {
+    const fn test_mm_div_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_div_pd(a, b);
@@ -4483,7 +4483,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_max_sd() {
+    fn test_mm_max_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_max_sd(a, b);
@@ -4491,7 +4491,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_max_pd() {
+    fn test_mm_max_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_max_pd(a, b);
@@ -4500,17 +4500,18 @@ mod tests {
         // Check SSE(2)-specific semantics for -0.0 handling.
         let a = _mm_setr_pd(-0.0, 0.0);
         let b = _mm_setr_pd(0.0, 0.0);
-        let r1: [u8; 16] = transmute(_mm_max_pd(a, b));
-        let r2: [u8; 16] = transmute(_mm_max_pd(b, a));
-        let a: [u8; 16] = transmute(a);
-        let b: [u8; 16] = transmute(b);
-        assert_eq!(r1, b);
-        assert_eq!(r2, a);
-        assert_ne!(a, b); // sanity check that -0.0 is actually present
+        // Cast to __m128i to compare exact bit patterns
+        let r1 = _mm_castpd_si128(_mm_max_pd(a, b));
+        let r2 = _mm_castpd_si128(_mm_max_pd(b, a));
+        let a = _mm_castpd_si128(a);
+        let b = _mm_castpd_si128(b);
+        assert_eq_m128i(r1, b);
+        assert_eq_m128i(r2, a);
+        assert_ne!(a.as_u8x16(), b.as_u8x16()); // sanity check that -0.0 is actually present
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_min_sd() {
+    fn test_mm_min_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_min_sd(a, b);
@@ -4518,7 +4519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_min_pd() {
+    fn test_mm_min_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_min_pd(a, b);
@@ -4527,17 +4528,18 @@ mod tests {
         // Check SSE(2)-specific semantics for -0.0 handling.
         let a = _mm_setr_pd(-0.0, 0.0);
         let b = _mm_setr_pd(0.0, 0.0);
-        let r1: [u8; 16] = transmute(_mm_min_pd(a, b));
-        let r2: [u8; 16] = transmute(_mm_min_pd(b, a));
-        let a: [u8; 16] = transmute(a);
-        let b: [u8; 16] = transmute(b);
-        assert_eq!(r1, b);
-        assert_eq!(r2, a);
-        assert_ne!(a, b); // sanity check that -0.0 is actually present
+        // Cast to __m128i to compare exact bit patterns
+        let r1 = _mm_castpd_si128(_mm_min_pd(a, b));
+        let r2 = _mm_castpd_si128(_mm_min_pd(b, a));
+        let a = _mm_castpd_si128(a);
+        let b = _mm_castpd_si128(b);
+        assert_eq_m128i(r1, b);
+        assert_eq_m128i(r2, a);
+        assert_ne!(a.as_u8x16(), b.as_u8x16()); // sanity check that -0.0 is actually present
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_mul_sd() {
+    const fn test_mm_mul_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_mul_sd(a, b);
@@ -4545,7 +4547,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_mul_pd() {
+    const fn test_mm_mul_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_mul_pd(a, b);
@@ -4553,7 +4555,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sqrt_sd() {
+    fn test_mm_sqrt_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_sqrt_sd(a, b);
@@ -4561,13 +4563,13 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sqrt_pd() {
+    fn test_mm_sqrt_pd() {
         let r = _mm_sqrt_pd(_mm_setr_pd(1.0, 2.0));
         assert_eq_m128d(r, _mm_setr_pd(1.0f64.sqrt(), 2.0f64.sqrt()));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_sub_sd() {
+    const fn test_mm_sub_sd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_sub_sd(a, b);
@@ -4575,7 +4577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_sub_pd() {
+    const fn test_mm_sub_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(5.0, 10.0);
         let r = _mm_sub_pd(a, b);
@@ -4619,199 +4621,199 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpeq_sd() {
+    fn test_mm_cmpeq_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpeq_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpeq_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmplt_sd() {
+    fn test_mm_cmplt_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmplt_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmplt_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmple_sd() {
+    fn test_mm_cmple_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmple_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmple_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpgt_sd() {
+    fn test_mm_cmpgt_sd() {
         let (a, b) = (_mm_setr_pd(5.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpgt_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpgt_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpge_sd() {
+    fn test_mm_cmpge_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpge_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpge_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpord_sd() {
+    fn test_mm_cmpord_sd() {
         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpord_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpord_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpunord_sd() {
+    fn test_mm_cmpunord_sd() {
         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpunord_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpunord_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpneq_sd() {
+    fn test_mm_cmpneq_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(!0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpneq_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpneq_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpnlt_sd() {
+    fn test_mm_cmpnlt_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpnlt_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpnlt_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpnle_sd() {
+    fn test_mm_cmpnle_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpnle_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpnle_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpngt_sd() {
+    fn test_mm_cmpngt_sd() {
         let (a, b) = (_mm_setr_pd(5.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpngt_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpngt_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpnge_sd() {
+    fn test_mm_cmpnge_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, 2.0f64.to_bits() as i64);
-        let r = transmute::<_, __m128i>(_mm_cmpnge_sd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpnge_sd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpeq_pd() {
+    fn test_mm_cmpeq_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, 0);
-        let r = transmute::<_, __m128i>(_mm_cmpeq_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpeq_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmplt_pd() {
+    fn test_mm_cmplt_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, !0);
-        let r = transmute::<_, __m128i>(_mm_cmplt_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmplt_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmple_pd() {
+    fn test_mm_cmple_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, !0);
-        let r = transmute::<_, __m128i>(_mm_cmple_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmple_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpgt_pd() {
+    fn test_mm_cmpgt_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, 0);
-        let r = transmute::<_, __m128i>(_mm_cmpgt_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpgt_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpge_pd() {
+    fn test_mm_cmpge_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(!0, 0);
-        let r = transmute::<_, __m128i>(_mm_cmpge_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpge_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpord_pd() {
+    fn test_mm_cmpord_pd() {
         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(0, !0);
-        let r = transmute::<_, __m128i>(_mm_cmpord_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpord_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpunord_pd() {
+    fn test_mm_cmpunord_pd() {
         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(!0, 0);
-        let r = transmute::<_, __m128i>(_mm_cmpunord_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpunord_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpneq_pd() {
+    fn test_mm_cmpneq_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(!0, !0);
-        let r = transmute::<_, __m128i>(_mm_cmpneq_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpneq_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpnlt_pd() {
+    fn test_mm_cmpnlt_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
         let e = _mm_setr_epi64x(0, 0);
-        let r = transmute::<_, __m128i>(_mm_cmpnlt_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpnlt_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpnle_pd() {
+    fn test_mm_cmpnle_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, 0);
-        let r = transmute::<_, __m128i>(_mm_cmpnle_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpnle_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpngt_pd() {
+    fn test_mm_cmpngt_pd() {
         let (a, b) = (_mm_setr_pd(5.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, !0);
-        let r = transmute::<_, __m128i>(_mm_cmpngt_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpngt_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cmpnge_pd() {
+    fn test_mm_cmpnge_pd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         let e = _mm_setr_epi64x(0, !0);
-        let r = transmute::<_, __m128i>(_mm_cmpnge_pd(a, b));
+        let r = _mm_castpd_si128(_mm_cmpnge_pd(a, b));
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_comieq_sd() {
+    fn test_mm_comieq_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_comieq_sd(a, b) != 0);
 
@@ -4820,37 +4822,37 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_comilt_sd() {
+    fn test_mm_comilt_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_comilt_sd(a, b) == 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_comile_sd() {
+    fn test_mm_comile_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_comile_sd(a, b) != 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_comigt_sd() {
+    fn test_mm_comigt_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_comigt_sd(a, b) == 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_comige_sd() {
+    fn test_mm_comige_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_comige_sd(a, b) != 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_comineq_sd() {
+    fn test_mm_comineq_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_comineq_sd(a, b) == 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_ucomieq_sd() {
+    fn test_mm_ucomieq_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_ucomieq_sd(a, b) != 0);
 
@@ -4859,37 +4861,37 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_ucomilt_sd() {
+    fn test_mm_ucomilt_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_ucomilt_sd(a, b) == 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_ucomile_sd() {
+    fn test_mm_ucomile_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_ucomile_sd(a, b) != 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_ucomigt_sd() {
+    fn test_mm_ucomigt_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_ucomigt_sd(a, b) == 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_ucomige_sd() {
+    fn test_mm_ucomige_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_ucomige_sd(a, b) != 0);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_ucomineq_sd() {
+    fn test_mm_ucomineq_sd() {
         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
         assert!(_mm_ucomineq_sd(a, b) == 0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_movemask_pd() {
+    const fn test_mm_movemask_pd() {
         let r = _mm_movemask_pd(_mm_setr_pd(-1.0, 5.0));
         assert_eq!(r, 0b01);
 
@@ -5122,7 +5124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtpd_ps() {
+    const fn test_mm_cvtpd_ps() {
         let r = _mm_cvtpd_ps(_mm_setr_pd(-1.0, 5.0));
         assert_eq_m128(r, _mm_setr_ps(-1.0, 5.0, 0.0, 0.0));
 
@@ -5137,7 +5139,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtps_pd() {
+    const fn test_mm_cvtps_pd() {
         let r = _mm_cvtps_pd(_mm_setr_ps(-1.0, 2.0, -3.0, 5.0));
         assert_eq_m128d(r, _mm_setr_pd(-1.0, 2.0));
 
@@ -5151,7 +5153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtpd_epi32() {
+    fn test_mm_cvtpd_epi32() {
         let r = _mm_cvtpd_epi32(_mm_setr_pd(-1.0, 5.0));
         assert_eq_m128i(r, _mm_setr_epi32(-1, 5, 0, 0));
 
@@ -5169,7 +5171,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsd_si32() {
+    fn test_mm_cvtsd_si32() {
         let r = _mm_cvtsd_si32(_mm_setr_pd(-2.0, 5.0));
         assert_eq!(r, -2);
 
@@ -5181,7 +5183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsd_ss() {
+    fn test_mm_cvtsd_ss() {
         let a = _mm_setr_ps(-1.1, -2.2, 3.3, 4.4);
         let b = _mm_setr_pd(2.0, -5.0);
 
@@ -5206,13 +5208,13 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsd_f64() {
+    const fn test_mm_cvtsd_f64() {
         let r = _mm_cvtsd_f64(_mm_setr_pd(-1.1, 2.2));
         assert_eq!(r, -1.1);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtss_sd() {
+    const fn test_mm_cvtss_sd() {
         let a = _mm_setr_pd(-1.1, 2.2);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
@@ -5227,7 +5229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvttpd_epi32() {
+    fn test_mm_cvttpd_epi32() {
         let a = _mm_setr_pd(-1.1, 2.2);
         let r = _mm_cvttpd_epi32(a);
         assert_eq_m128i(r, _mm_setr_epi32(-1, 2, 0, 0));
@@ -5238,7 +5240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvttsd_si32() {
+    fn test_mm_cvttsd_si32() {
         let a = _mm_setr_pd(-1.1, 2.2);
         let r = _mm_cvttsd_si32(a);
         assert_eq!(r, -1);
@@ -5249,7 +5251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvttps_epi32() {
+    fn test_mm_cvttps_epi32() {
         let a = _mm_setr_ps(-1.1, 2.2, -3.3, 6.6);
         let r = _mm_cvttps_epi32(a);
         assert_eq_m128i(r, _mm_setr_epi32(-1, 2, -3, 6));
@@ -5260,37 +5262,37 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_sd() {
+    const fn test_mm_set_sd() {
         let r = _mm_set_sd(-1.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(-1.0_f64, 0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set1_pd() {
+    const fn test_mm_set1_pd() {
         let r = _mm_set1_pd(-1.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(-1.0_f64, -1.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_pd1() {
+    const fn test_mm_set_pd1() {
         let r = _mm_set_pd1(-2.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(-2.0_f64, -2.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_set_pd() {
+    const fn test_mm_set_pd() {
         let r = _mm_set_pd(1.0_f64, 5.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(5.0_f64, 1.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_setr_pd() {
+    const fn test_mm_setr_pd() {
         let r = _mm_setr_pd(1.0_f64, -5.0_f64);
         assert_eq_m128d(r, _mm_setr_pd(1.0_f64, -5.0_f64));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_setzero_pd() {
+    const fn test_mm_setzero_pd() {
         let r = _mm_setzero_pd();
         assert_eq_m128d(r, _mm_setr_pd(0_f64, 0_f64));
     }
@@ -5310,7 +5312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpackhi_pd() {
+    const fn test_mm_unpackhi_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(3.0, 4.0);
         let r = _mm_unpackhi_pd(a, b);
@@ -5318,7 +5320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_unpacklo_pd() {
+    const fn test_mm_unpacklo_pd() {
         let a = _mm_setr_pd(1.0, 2.0);
         let b = _mm_setr_pd(3.0, 4.0);
         let r = _mm_unpacklo_pd(a, b);
@@ -5326,7 +5328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_shuffle_pd() {
+    const fn test_mm_shuffle_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(3., 4.);
         let expected = _mm_setr_pd(1., 3.);
@@ -5335,7 +5337,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_move_sd() {
+    const fn test_mm_move_sd() {
         let a = _mm_setr_pd(1., 2.);
         let b = _mm_setr_pd(3., 4.);
         let expected = _mm_setr_pd(3., 2.);
@@ -5344,7 +5346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_castpd_ps() {
+    const fn test_mm_castpd_ps() {
         let a = _mm_set1_pd(0.);
         let expected = _mm_set1_ps(0.);
         let r = _mm_castpd_ps(a);
@@ -5352,7 +5354,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_castpd_si128() {
+    const fn test_mm_castpd_si128() {
         let a = _mm_set1_pd(0.);
         let expected = _mm_set1_epi64x(0);
         let r = _mm_castpd_si128(a);
@@ -5360,7 +5362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_castps_pd() {
+    const fn test_mm_castps_pd() {
         let a = _mm_set1_ps(0.);
         let expected = _mm_set1_pd(0.);
         let r = _mm_castps_pd(a);
@@ -5368,7 +5370,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_castps_si128() {
+    const fn test_mm_castps_si128() {
         let a = _mm_set1_ps(0.);
         let expected = _mm_set1_epi32(0);
         let r = _mm_castps_si128(a);
@@ -5376,7 +5378,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_castsi128_pd() {
+    const fn test_mm_castsi128_pd() {
         let a = _mm_set1_epi64x(0);
         let expected = _mm_set1_pd(0.);
         let r = _mm_castsi128_pd(a);
@@ -5384,7 +5386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_castsi128_ps() {
+    const fn test_mm_castsi128_ps() {
         let a = _mm_set1_epi32(0);
         let expected = _mm_set1_ps(0.);
         let r = _mm_castsi128_ps(a);
diff --git a/crates/core_arch/src/x86/sse3.rs b/crates/core_arch/src/x86/sse3.rs
index eebca864f4..68817856f4 100644
--- a/crates/core_arch/src/x86/sse3.rs
+++ b/crates/core_arch/src/x86/sse3.rs
@@ -191,7 +191,7 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_addsub_ps() {
+    const fn test_mm_addsub_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_addsub_ps(a, b);
@@ -199,7 +199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_addsub_pd() {
+    const fn test_mm_addsub_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let b = _mm_setr_pd(-100.0, 20.0);
         let r = _mm_addsub_pd(a, b);
@@ -207,7 +207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_hadd_pd() {
+    const fn test_mm_hadd_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let b = _mm_setr_pd(-100.0, 20.0);
         let r = _mm_hadd_pd(a, b);
@@ -215,7 +215,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_hadd_ps() {
+    const fn test_mm_hadd_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_hadd_ps(a, b);
@@ -223,7 +223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_hsub_pd() {
+    const fn test_mm_hsub_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let b = _mm_setr_pd(-100.0, 20.0);
         let r = _mm_hsub_pd(a, b);
@@ -231,7 +231,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_hsub_ps() {
+    const fn test_mm_hsub_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_hsub_ps(a, b);
@@ -252,21 +252,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_movedup_pd() {
+    const fn test_mm_movedup_pd() {
         let a = _mm_setr_pd(-1.0, 5.0);
         let r = _mm_movedup_pd(a);
         assert_eq_m128d(r, _mm_setr_pd(-1.0, -1.0));
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_movehdup_ps() {
+    const fn test_mm_movehdup_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let r = _mm_movehdup_ps(a);
         assert_eq_m128(r, _mm_setr_ps(5.0, 5.0, -10.0, -10.0));
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_moveldup_ps() {
+    const fn test_mm_moveldup_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let r = _mm_moveldup_ps(a);
         assert_eq_m128(r, _mm_setr_ps(-1.0, -1.0, 0.0, 0.0));
diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
index a83f8cc747..a499bf898b 100644
--- a/crates/core_arch/src/x86/sse41.rs
+++ b/crates/core_arch/src/x86/sse41.rs
@@ -1196,7 +1196,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blendv_epi8() {
+    const fn test_mm_blendv_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -1239,7 +1239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blend_pd() {
+    const fn test_mm_blend_pd() {
         let a = _mm_set1_pd(0.0);
         let b = _mm_set1_pd(1.0);
         let r = _mm_blend_pd::<0b10>(a, b);
@@ -1248,7 +1248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blend_ps() {
+    const fn test_mm_blend_ps() {
         let a = _mm_set1_ps(0.0);
         let b = _mm_set1_ps(1.0);
         let r = _mm_blend_ps::<0b1010>(a, b);
@@ -1257,7 +1257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blend_epi16() {
+    const fn test_mm_blend_epi16() {
         let a = _mm_set1_epi16(0);
         let b = _mm_set1_epi16(1);
         let r = _mm_blend_epi16::<0b1010_1100>(a, b);
@@ -1266,7 +1266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_extract_ps() {
+    const fn test_mm_extract_ps() {
         let a = _mm_setr_ps(0.0, 1.0, 2.0, 3.0);
         let r: f32 = f32::from_bits(_mm_extract_ps::<1>(a) as u32);
         assert_eq!(r, 1.0);
@@ -1275,7 +1275,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_extract_epi8() {
+    const fn test_mm_extract_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             -1, 1, 2, 3, 4, 5, 6, 7,
@@ -1288,7 +1288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_extract_epi32() {
+    const fn test_mm_extract_epi32() {
         let a = _mm_setr_epi32(0, 1, 2, 3);
         let r = _mm_extract_epi32::<1>(a);
         assert_eq!(r, 1);
@@ -1297,7 +1297,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_insert_ps() {
+    fn test_mm_insert_ps() {
         let a = _mm_set1_ps(1.0);
         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_insert_ps::<0b11_00_1100>(a, b);
@@ -1313,7 +1313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_insert_epi8() {
+    const fn test_mm_insert_epi8() {
         let a = _mm_set1_epi8(0);
         let e = _mm_setr_epi8(0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         let r = _mm_insert_epi8::<1>(a, 32);
@@ -1324,7 +1324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_insert_epi32() {
+    const fn test_mm_insert_epi32() {
         let a = _mm_set1_epi32(0);
         let e = _mm_setr_epi32(0, 32, 0, 0);
         let r = _mm_insert_epi32::<1>(a, 32);
@@ -1335,7 +1335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_max_epi8() {
+    const fn test_mm_max_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 4, 5, 8, 9, 12, 13, 16,
@@ -1356,7 +1356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_max_epu16() {
+    const fn test_mm_max_epu16() {
         let a = _mm_setr_epi16(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm_setr_epi16(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm_max_epu16(a, b);
@@ -1365,7 +1365,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_max_epi32() {
+    const fn test_mm_max_epi32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_max_epi32(a, b);
@@ -1374,7 +1374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_max_epu32() {
+    const fn test_mm_max_epu32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_max_epu32(a, b);
@@ -1383,7 +1383,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_min_epi8() {
+    const fn test_mm_min_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 4, 5, 8, 9, 12, 13, 16,
@@ -1422,7 +1422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_min_epu16() {
+    const fn test_mm_min_epu16() {
         let a = _mm_setr_epi16(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm_setr_epi16(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm_min_epu16(a, b);
@@ -1431,7 +1431,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_min_epi32() {
+    const fn test_mm_min_epi32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_min_epi32(a, b);
@@ -1446,7 +1446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_min_epu32() {
+    const fn test_mm_min_epu32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_min_epu32(a, b);
@@ -1455,7 +1455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_packus_epi32() {
+    fn test_mm_packus_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let b = _mm_setr_epi32(-1, -2, -3, -4);
         let r = _mm_packus_epi32(a, b);
@@ -1464,7 +1464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cmpeq_epi64() {
+    const fn test_mm_cmpeq_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let b = _mm_setr_epi64x(0, 0);
         let r = _mm_cmpeq_epi64(a, b);
@@ -1473,7 +1473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepi8_epi16() {
+    const fn test_mm_cvtepi8_epi16() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepi8_epi16(a);
         let e = _mm_set1_epi16(10);
@@ -1485,7 +1485,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepi8_epi32() {
+    const fn test_mm_cvtepi8_epi32() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepi8_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1497,7 +1497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepi8_epi64() {
+    const fn test_mm_cvtepi8_epi64() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepi8_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1509,7 +1509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepi16_epi32() {
+    const fn test_mm_cvtepi16_epi32() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepi16_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1521,7 +1521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepi16_epi64() {
+    const fn test_mm_cvtepi16_epi64() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepi16_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1533,7 +1533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepi32_epi64() {
+    const fn test_mm_cvtepi32_epi64() {
         let a = _mm_set1_epi32(10);
         let r = _mm_cvtepi32_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1545,7 +1545,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepu8_epi16() {
+    const fn test_mm_cvtepu8_epi16() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepu8_epi16(a);
         let e = _mm_set1_epi16(10);
@@ -1553,7 +1553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepu8_epi32() {
+    const fn test_mm_cvtepu8_epi32() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepu8_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1561,7 +1561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepu8_epi64() {
+    const fn test_mm_cvtepu8_epi64() {
         let a = _mm_set1_epi8(10);
         let r = _mm_cvtepu8_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1569,7 +1569,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepu16_epi32() {
+    const fn test_mm_cvtepu16_epi32() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepu16_epi32(a);
         let e = _mm_set1_epi32(10);
@@ -1577,7 +1577,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepu16_epi64() {
+    const fn test_mm_cvtepu16_epi64() {
         let a = _mm_set1_epi16(10);
         let r = _mm_cvtepu16_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1585,7 +1585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_cvtepu32_epi64() {
+    const fn test_mm_cvtepu32_epi64() {
         let a = _mm_set1_epi32(10);
         let r = _mm_cvtepu32_epi64(a);
         let e = _mm_set1_epi64x(10);
@@ -1593,7 +1593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_dp_pd() {
+    fn test_mm_dp_pd() {
         let a = _mm_setr_pd(2.0, 3.0);
         let b = _mm_setr_pd(1.0, 4.0);
         let e = _mm_setr_pd(14.0, 0.0);
@@ -1601,7 +1601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_dp_ps() {
+    fn test_mm_dp_ps() {
         let a = _mm_setr_ps(2.0, 3.0, 1.0, 10.0);
         let b = _mm_setr_ps(1.0, 4.0, 0.5, 10.0);
         let e = _mm_setr_ps(14.5, 0.0, 14.5, 0.0);
@@ -1609,7 +1609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_floor_pd() {
+    const fn test_mm_floor_pd() {
         let a = _mm_setr_pd(2.5, 4.5);
         let r = _mm_floor_pd(a);
         let e = _mm_setr_pd(2.0, 4.0);
@@ -1617,7 +1617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_floor_ps() {
+    const fn test_mm_floor_ps() {
         let a = _mm_setr_ps(2.5, 4.5, 8.5, 16.5);
         let r = _mm_floor_ps(a);
         let e = _mm_setr_ps(2.0, 4.0, 8.0, 16.0);
@@ -1625,7 +1625,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_floor_sd() {
+    fn test_mm_floor_sd() {
         let a = _mm_setr_pd(2.5, 4.5);
         let b = _mm_setr_pd(-1.5, -3.5);
         let r = _mm_floor_sd(a, b);
@@ -1634,7 +1634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_floor_ss() {
+    fn test_mm_floor_ss() {
         let a = _mm_setr_ps(2.5, 4.5, 8.5, 16.5);
         let b = _mm_setr_ps(-1.5, -3.5, -7.5, -15.5);
         let r = _mm_floor_ss(a, b);
@@ -1643,7 +1643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_ceil_pd() {
+    const fn test_mm_ceil_pd() {
         let a = _mm_setr_pd(1.5, 3.5);
         let r = _mm_ceil_pd(a);
         let e = _mm_setr_pd(2.0, 4.0);
@@ -1651,7 +1651,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_ceil_ps() {
+    const fn test_mm_ceil_ps() {
         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
         let r = _mm_ceil_ps(a);
         let e = _mm_setr_ps(2.0, 4.0, 8.0, 16.0);
@@ -1659,7 +1659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_ceil_sd() {
+    fn test_mm_ceil_sd() {
         let a = _mm_setr_pd(1.5, 3.5);
         let b = _mm_setr_pd(-2.5, -4.5);
         let r = _mm_ceil_sd(a, b);
@@ -1668,7 +1668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_ceil_ss() {
+    fn test_mm_ceil_ss() {
         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
         let b = _mm_setr_ps(-2.5, -4.5, -8.5, -16.5);
         let r = _mm_ceil_ss(a, b);
@@ -1677,7 +1677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_round_pd() {
+    fn test_mm_round_pd() {
         let a = _mm_setr_pd(1.25, 3.75);
         let r = _mm_round_pd::<_MM_FROUND_TO_NEAREST_INT>(a);
         let e = _mm_setr_pd(1.0, 4.0);
@@ -1685,7 +1685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_round_ps() {
+    fn test_mm_round_ps() {
         let a = _mm_setr_ps(2.25, 4.75, -1.75, -4.25);
         let r = _mm_round_ps::<_MM_FROUND_TO_ZERO>(a);
         let e = _mm_setr_ps(2.0, 4.0, -1.0, -4.0);
@@ -1693,7 +1693,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_round_sd() {
+    fn test_mm_round_sd() {
         let a = _mm_setr_pd(1.5, 3.5);
         let b = _mm_setr_pd(-2.5, -4.5);
         let r = _mm_round_sd::<_MM_FROUND_TO_NEAREST_INT>(a, b);
@@ -1720,7 +1720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_round_ss() {
+    fn test_mm_round_ss() {
         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
         let b = _mm_setr_ps(-1.75, -4.5, -8.5, -16.5);
         let r = _mm_round_ss::<_MM_FROUND_TO_NEAREST_INT>(a, b);
@@ -1747,7 +1747,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_minpos_epu16_1() {
+    fn test_mm_minpos_epu16_1() {
         let a = _mm_setr_epi16(23, 18, 44, 97, 50, 13, 67, 66);
         let r = _mm_minpos_epu16(a);
         let e = _mm_setr_epi16(13, 5, 0, 0, 0, 0, 0, 0);
@@ -1755,7 +1755,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_minpos_epu16_2() {
+    fn test_mm_minpos_epu16_2() {
         let a = _mm_setr_epi16(0, 18, 44, 97, 50, 13, 67, 66);
         let r = _mm_minpos_epu16(a);
         let e = _mm_setr_epi16(0, 0, 0, 0, 0, 0, 0, 0);
@@ -1763,7 +1763,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_minpos_epu16_3() {
+    fn test_mm_minpos_epu16_3() {
         // Case where the minimum value is repeated
         let a = _mm_setr_epi16(23, 18, 44, 97, 50, 13, 67, 13);
         let r = _mm_minpos_epu16(a);
@@ -1772,7 +1772,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_mul_epi32() {
+    const fn test_mm_mul_epi32() {
         {
             let a = _mm_setr_epi32(1, 1, 1, 1);
             let b = _mm_setr_epi32(1, 2, 3, 4);
@@ -1793,7 +1793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_mullo_epi32() {
+    const fn test_mm_mullo_epi32() {
         {
             let a = _mm_setr_epi32(1, 1, 1, 1);
             let b = _mm_setr_epi32(1, 2, 3, 4);
@@ -1814,7 +1814,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_minpos_epu16() {
+    fn test_mm_minpos_epu16() {
         let a = _mm_setr_epi16(8, 7, 6, 5, 4, 1, 2, 3);
         let r = _mm_minpos_epu16(a);
         let e = _mm_setr_epi16(1, 5, 0, 0, 0, 0, 0, 0);
@@ -1822,7 +1822,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_mpsadbw_epu8() {
+    fn test_mm_mpsadbw_epu8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             0, 1, 2, 3, 4, 5, 6, 7,
@@ -1851,7 +1851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_testz_si128() {
+    const fn test_mm_testz_si128() {
         let a = _mm_set1_epi8(1);
         let mask = _mm_set1_epi8(0);
         let r = _mm_testz_si128(a, mask);
@@ -1867,7 +1867,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_testc_si128() {
+    const fn test_mm_testc_si128() {
         let a = _mm_set1_epi8(-1);
         let mask = _mm_set1_epi8(0);
         let r = _mm_testc_si128(a, mask);
@@ -1883,7 +1883,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_testnzc_si128() {
+    fn test_mm_testnzc_si128() {
         let a = _mm_set1_epi8(0);
         let mask = _mm_set1_epi8(1);
         let r = _mm_testnzc_si128(a, mask);
@@ -1903,7 +1903,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_test_all_zeros() {
+    const fn test_mm_test_all_zeros() {
         let a = _mm_set1_epi8(1);
         let mask = _mm_set1_epi8(0);
         let r = _mm_test_all_zeros(a, mask);
@@ -1919,7 +1919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_test_all_ones() {
+    const fn test_mm_test_all_ones() {
         let a = _mm_set1_epi8(-1);
         let r = _mm_test_all_ones(a);
         assert_eq!(r, 1);
@@ -1929,7 +1929,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_test_mix_ones_zeros() {
+    fn test_mm_test_mix_ones_zeros() {
         let a = _mm_set1_epi8(0);
         let mask = _mm_set1_epi8(1);
         let r = _mm_test_mix_ones_zeros(a, mask);
diff --git a/crates/core_arch/src/x86/sse42.rs b/crates/core_arch/src/x86/sse42.rs
index 4d3c481fe1..65d1fe4d62 100644
--- a/crates/core_arch/src/x86/sse42.rs
+++ b/crates/core_arch/src/x86/sse42.rs
@@ -619,18 +619,17 @@ mod tests {
     // Currently one cannot `load` a &[u8] that is less than 16
     // in length. This makes loading strings less than 16 in length
     // a bit difficult. Rather than `load` and mutate the __m128i,
-    // it is easier to memcpy the given string to a local slice with
-    // length 16 and `load` the local slice.
-    #[target_feature(enable = "sse4.2")]
-    unsafe fn str_to_m128i(s: &[u8]) -> __m128i {
+    // it is easier to memcpy the given string to a zero-padded
+    // 16-byte array and transmute it to `__m128i`.
+    fn str_to_m128i(s: &[u8]) -> __m128i {
         assert!(s.len() <= 16);
-        let slice = &mut [0u8; 16];
-        ptr::copy_nonoverlapping(s.as_ptr(), slice.as_mut_ptr(), s.len());
-        _mm_loadu_si128(slice.as_ptr() as *const _)
+        let mut array = [0u8; 16];
+        array[..s.len()].copy_from_slice(s);
+        unsafe { transmute(array) }
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistrm() {
+    fn test_mm_cmpistrm() {
         let a = str_to_m128i(b"Hello! Good-Bye!");
         let b = str_to_m128i(b"hello! good-bye!");
         let i = _mm_cmpistrm::<_SIDD_UNIT_MASK>(a, b);
@@ -643,7 +642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistri() {
+    fn test_mm_cmpistri() {
         let a = str_to_m128i(b"Hello");
         let b = str_to_m128i(b"   Hello        ");
         let i = _mm_cmpistri::<_SIDD_CMP_EQUAL_ORDERED>(a, b);
@@ -651,7 +650,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistrz() {
+    fn test_mm_cmpistrz() {
         let a = str_to_m128i(b"");
         let b = str_to_m128i(b"Hello");
         let i = _mm_cmpistrz::<_SIDD_CMP_EQUAL_ORDERED>(a, b);
@@ -659,7 +658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistrc() {
+    fn test_mm_cmpistrc() {
         let a = str_to_m128i(b"                ");
         let b = str_to_m128i(b"       !        ");
         let i = _mm_cmpistrc::<_SIDD_UNIT_MASK>(a, b);
@@ -667,7 +666,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistrs() {
+    fn test_mm_cmpistrs() {
         let a = str_to_m128i(b"Hello");
         let b = str_to_m128i(b"");
         let i = _mm_cmpistrs::<_SIDD_CMP_EQUAL_ORDERED>(a, b);
@@ -675,7 +674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistro() {
+    fn test_mm_cmpistro() {
         #[rustfmt::skip]
         let a_bytes = _mm_setr_epi8(
             0x00, 0x47, 0x00, 0x65, 0x00, 0x6c, 0x00, 0x6c,
@@ -693,7 +692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpistra() {
+    fn test_mm_cmpistra() {
         let a = str_to_m128i(b"");
         let b = str_to_m128i(b"Hello!!!!!!!!!!!");
         let i = _mm_cmpistra::<_SIDD_UNIT_MASK>(a, b);
@@ -701,7 +700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestrm() {
+    fn test_mm_cmpestrm() {
         let a = str_to_m128i(b"Hello!");
         let b = str_to_m128i(b"Hello.");
         let i = _mm_cmpestrm::<_SIDD_UNIT_MASK>(a, 5, b, 5);
@@ -714,7 +713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestri() {
+    fn test_mm_cmpestri() {
         let a = str_to_m128i(b"bar - garbage");
         let b = str_to_m128i(b"foobar");
         let i = _mm_cmpestri::<_SIDD_CMP_EQUAL_ORDERED>(a, 3, b, 6);
@@ -722,7 +721,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestrz() {
+    fn test_mm_cmpestrz() {
         let a = str_to_m128i(b"");
         let b = str_to_m128i(b"Hello");
         let i = _mm_cmpestrz::<_SIDD_CMP_EQUAL_ORDERED>(a, 16, b, 6);
@@ -730,7 +729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestrc() {
+    fn test_mm_cmpestrc() {
         let va = str_to_m128i(b"!!!!!!!!");
         let vb = str_to_m128i(b"        ");
         let i = _mm_cmpestrc::<_SIDD_UNIT_MASK>(va, 7, vb, 7);
@@ -738,7 +737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestrs() {
+    fn test_mm_cmpestrs() {
         #[rustfmt::skip]
         let a_bytes = _mm_setr_epi8(
             0x00, 0x48, 0x00, 0x65, 0x00, 0x6c, 0x00, 0x6c,
@@ -751,7 +750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestro() {
+    fn test_mm_cmpestro() {
         let a = str_to_m128i(b"Hello");
         let b = str_to_m128i(b"World");
         let i = _mm_cmpestro::<_SIDD_UBYTE_OPS>(a, 5, b, 5);
@@ -759,7 +758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_cmpestra() {
+    fn test_mm_cmpestra() {
         let a = str_to_m128i(b"Cannot match a");
         let b = str_to_m128i(b"Null after 14");
         let i = _mm_cmpestra::<{ _SIDD_CMP_EQUAL_EACH | _SIDD_UNIT_MASK }>(a, 14, b, 16);
@@ -767,7 +766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_crc32_u8() {
+    fn test_mm_crc32_u8() {
         let crc = 0x2aa1e72b;
         let v = 0x2a;
         let i = _mm_crc32_u8(crc, v);
@@ -775,7 +774,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_crc32_u16() {
+    fn test_mm_crc32_u16() {
         let crc = 0x8ecec3b5;
         let v = 0x22b;
         let i = _mm_crc32_u16(crc, v);
@@ -783,7 +782,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_crc32_u32() {
+    fn test_mm_crc32_u32() {
         let crc = 0xae2912c8;
         let v = 0x845fed;
         let i = _mm_crc32_u32(crc, v);
@@ -791,7 +790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.2")]
-    const unsafe fn test_mm_cmpgt_epi64() {
+    const fn test_mm_cmpgt_epi64() {
         let a = _mm_setr_epi64x(0, 0x2a);
         let b = _mm_set1_epi64x(0x00);
         let i = _mm_cmpgt_epi64(a, b);
diff --git a/crates/core_arch/src/x86/sse4a.rs b/crates/core_arch/src/x86/sse4a.rs
index 7978d018e4..020baeff15 100644
--- a/crates/core_arch/src/x86/sse4a.rs
+++ b/crates/core_arch/src/x86/sse4a.rs
@@ -151,7 +151,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse4a")]
-    unsafe fn test_mm_extract_si64() {
+    fn test_mm_extract_si64() {
         let b = 0b0110_0000_0000_i64;
         //        ^^^^ bit range extracted
         let x = _mm_setr_epi64x(b, 0);
@@ -164,7 +164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4a")]
-    unsafe fn test_mm_extracti_si64() {
+    fn test_mm_extracti_si64() {
         let a = _mm_setr_epi64x(0x0123456789abcdef, 0);
         let r = _mm_extracti_si64::<8, 8>(a);
         let e = _mm_setr_epi64x(0xcd, 0);
@@ -172,7 +172,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4a")]
-    unsafe fn test_mm_insert_si64() {
+    fn test_mm_insert_si64() {
         let i = 0b0110_i64;
         //        ^^^^ bit range inserted
         let z = 0b1010_1010_1010i64;
@@ -189,7 +189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4a")]
-    unsafe fn test_mm_inserti_si64() {
+    fn test_mm_inserti_si64() {
         let a = _mm_setr_epi64x(0x0123456789abcdef, 0);
         let b = _mm_setr_epi64x(0x0011223344556677, 0);
         let r = _mm_inserti_si64::<8, 8>(a, b);
diff --git a/crates/core_arch/src/x86/ssse3.rs b/crates/core_arch/src/x86/ssse3.rs
index c44da6eb97..4426a3274c 100644
--- a/crates/core_arch/src/x86/ssse3.rs
+++ b/crates/core_arch/src/x86/ssse3.rs
@@ -367,25 +367,25 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_abs_epi8() {
+    const fn test_mm_abs_epi8() {
         let r = _mm_abs_epi8(_mm_set1_epi8(-5));
         assert_eq_m128i(r, _mm_set1_epi8(5));
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_abs_epi16() {
+    const fn test_mm_abs_epi16() {
         let r = _mm_abs_epi16(_mm_set1_epi16(-5));
         assert_eq_m128i(r, _mm_set1_epi16(5));
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_abs_epi32() {
+    const fn test_mm_abs_epi32() {
         let r = _mm_abs_epi32(_mm_set1_epi32(-5));
         assert_eq_m128i(r, _mm_set1_epi32(5));
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_shuffle_epi8() {
+    fn test_mm_shuffle_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -409,7 +409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_alignr_epi8() {
+    const fn test_mm_alignr_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -449,7 +449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_hadd_epi16() {
+    const fn test_mm_hadd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 24, 12, 6, 19);
         let expected = _mm_setr_epi16(3, 7, 11, 15, 132, 7, 36, 25);
@@ -474,7 +474,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_hadds_epi16() {
+    fn test_mm_hadds_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 32767, 1, -32768, -1);
         let expected = _mm_setr_epi16(3, 7, 11, 15, 132, 7, 32767, -32768);
@@ -499,7 +499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_hadd_epi32() {
+    const fn test_mm_hadd_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let b = _mm_setr_epi32(4, 128, 4, 3);
         let expected = _mm_setr_epi32(3, 7, 132, 7);
@@ -515,7 +515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_hsub_epi16() {
+    const fn test_mm_hsub_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 24, 12, 6, 19);
         let expected = _mm_setr_epi16(-1, -1, -1, -1, -124, 1, 12, -13);
@@ -540,7 +540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_hsubs_epi16() {
+    fn test_mm_hsubs_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 32767, -1, -32768, 1);
         let expected = _mm_setr_epi16(-1, -1, -1, -1, -124, 1, 32767, -32768);
@@ -565,7 +565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    const unsafe fn test_mm_hsub_epi32() {
+    const fn test_mm_hsub_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let b = _mm_setr_epi32(4, 128, 4, 3);
         let expected = _mm_setr_epi32(-1, -1, -124, 1);
@@ -581,7 +581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_maddubs_epi16() {
+    fn test_mm_maddubs_epi16() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -621,7 +621,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_mulhrs_epi16() {
+    fn test_mm_mulhrs_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 4, 3, 32767, -1, -32768, 1);
         let expected = _mm_setr_epi16(0, 0, 0, 0, 5, 0, -7, 0);
@@ -637,7 +637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_sign_epi8() {
+    fn test_mm_sign_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -658,7 +658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_sign_epi16() {
+    fn test_mm_sign_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, -5, -6, 7, 8);
         let b = _mm_setr_epi16(4, 128, 0, 3, 1, -1, -2, 1);
         let expected = _mm_setr_epi16(1, 2, 0, 4, -5, 6, -7, 8);
@@ -667,7 +667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "ssse3")]
-    unsafe fn test_mm_sign_epi32() {
+    fn test_mm_sign_epi32() {
         let a = _mm_setr_epi32(-1, 2, 3, 4);
         let b = _mm_setr_epi32(1, -1, 1, 0);
         let expected = _mm_setr_epi32(-1, -2, 3, 0);
diff --git a/crates/core_arch/src/x86/tbm.rs b/crates/core_arch/src/x86/tbm.rs
index 1e863fe15c..0ba4572dcd 100644
--- a/crates/core_arch/src/x86/tbm.rs
+++ b/crates/core_arch/src/x86/tbm.rs
@@ -154,18 +154,18 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_bextri_u32() {
+    fn test_bextri_u32() {
         assert_eq!(_bextri_u32::<0x0404>(0b0101_0000u32), 0b0000_0101u32);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcfill_u32() {
+    const fn test_blcfill_u32() {
         assert_eq!(_blcfill_u32(0b0101_0111u32), 0b0101_0000u32);
         assert_eq!(_blcfill_u32(0b1111_1111u32), 0u32);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blci_u32() {
+    const fn test_blci_u32() {
         assert_eq!(
             _blci_u32(0b0101_0000u32),
             0b1111_1111_1111_1111_1111_1111_1111_1110u32
@@ -177,25 +177,25 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcic_u32() {
+    const fn test_blcic_u32() {
         assert_eq!(_blcic_u32(0b0101_0001u32), 0b0000_0010u32);
         assert_eq!(_blcic_u32(0b1111_1111u32), 0b1_0000_0000u32);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcmsk_u32() {
+    const fn test_blcmsk_u32() {
         assert_eq!(_blcmsk_u32(0b0101_0001u32), 0b0000_0011u32);
         assert_eq!(_blcmsk_u32(0b1111_1111u32), 0b1_1111_1111u32);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcs_u32() {
+    const fn test_blcs_u32() {
         assert_eq!(_blcs_u32(0b0101_0001u32), 0b0101_0011u32);
         assert_eq!(_blcs_u32(0b1111_1111u32), 0b1_1111_1111u32);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blsfill_u32() {
+    const fn test_blsfill_u32() {
         assert_eq!(_blsfill_u32(0b0101_0100u32), 0b0101_0111u32);
         assert_eq!(
             _blsfill_u32(0u32),
@@ -204,7 +204,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blsic_u32() {
+    const fn test_blsic_u32() {
         assert_eq!(
             _blsic_u32(0b0101_0100u32),
             0b1111_1111_1111_1111_1111_1111_1111_1011u32
@@ -216,7 +216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_t1mskc_u32() {
+    const fn test_t1mskc_u32() {
         assert_eq!(
             _t1mskc_u32(0b0101_0111u32),
             0b1111_1111_1111_1111_1111_1111_1111_1000u32
@@ -228,7 +228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_tzmsk_u32() {
+    const fn test_tzmsk_u32() {
         assert_eq!(_tzmsk_u32(0b0101_1000u32), 0b0000_0111u32);
         assert_eq!(_tzmsk_u32(0b0101_1001u32), 0b0000_0000u32);
     }
diff --git a/crates/core_arch/src/x86/test.rs b/crates/core_arch/src/x86/test.rs
index 9fa88fc98d..4b2ef26044 100644
--- a/crates/core_arch/src/x86/test.rs
+++ b/crates/core_arch/src/x86/test.rs
@@ -1,225 +1,122 @@
 //! Utilities used in testing the x86 intrinsics
 
 use crate::core_arch::assert_eq_const as assert_eq;
+use crate::core_arch::simd::*;
 use crate::core_arch::x86::*;
 use std::mem::transmute;
 
 #[track_caller]
-#[target_feature(enable = "sse2")]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(crate) const unsafe fn assert_eq_m128i(a: __m128i, b: __m128i) {
-    assert_eq!(transmute::<_, [u64; 2]>(a), transmute::<_, [u64; 2]>(b))
+pub(crate) const fn assert_eq_m128i(a: __m128i, b: __m128i) {
+    assert_eq!(a.as_u32x4(), b.as_u32x4());
 }
 
 #[track_caller]
-#[target_feature(enable = "avx")]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(crate) const unsafe fn assert_eq_m256i(a: __m256i, b: __m256i) {
-    assert_eq!(transmute::<_, [u64; 4]>(a), transmute::<_, [u64; 4]>(b))
+pub(crate) const fn assert_eq_m128(a: __m128, b: __m128) {
+    assert_eq!(a.as_f32x4(), b.as_f32x4());
 }
 
 #[track_caller]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(crate) const unsafe fn assert_eq_m512i(a: __m512i, b: __m512i) {
-    assert_eq!(transmute::<_, [i32; 16]>(a), transmute::<_, [i32; 16]>(b))
-}
-
-macro_rules! make_ct_rt {
-    ($(
-        $( #[$meta:meta] )*
-        $vis:vis unsafe fn $name:ident ($($param:ident : $type:ty),* $(,)?) {
-            ct: $ct:expr;
-            rt: $rt:expr;
-        }
-    )*) => {$(
-        $( #[$meta] )*
-        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-        $vis const unsafe fn $name ($($param : $type),*) {
-            #[inline(always)]
-            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-            const fn ct($($param : $type),*) {
-                $ct
-            }
-            #[inline(always)]
-            fn rt($($param : $type),*) {
-                $rt
-            }
-
-            $crate::intrinsics::const_eval_select(($($param),*), ct, rt)
-        }
-    )*}
-}
-
-make_ct_rt! {
-    // SAFETY: we can use simple float equality because when this should only be used in const
-    // context where Intel peculiarities don't appear
-
-    #[track_caller]
-    #[target_feature(enable = "sse2")]
-    pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f64; 2]>(a), transmute::<_, [f64; 2]>(b))
-        };
-        rt: unsafe {
-            if _mm_movemask_pd(_mm_cmpeq_pd(a, b)) != 0b11 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+pub(crate) const fn assert_eq_m128d(a: __m128d, b: __m128d) {
+    assert_eq!(a.as_f64x2(), b.as_f64x2());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "sse")]
-    pub unsafe fn assert_eq_m128(a: __m128, b: __m128) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f32; 4]>(a), transmute::<_, [f32; 4]>(b))
-        };
-        rt: unsafe {
-            let r = _mm_cmpeq_ps(a, b);
-            if _mm_movemask_ps(r) != 0b1111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m128h(a: __m128h, b: __m128h) {
+    assert_eq!(a.as_f16x8(), b.as_f16x8());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx512fp16,avx512vl")]
-    pub unsafe fn assert_eq_m128h(a: __m128h, b: __m128h) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f16; 8]>(a), transmute::<_, [f16; 8]>(b))
-        };
-        rt: unsafe {
-            let r = _mm_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
-            if r != 0b1111_1111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m256i(a: __m256i, b: __m256i) {
+    assert_eq!(a.as_u32x8(), b.as_u32x8());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx")]
-    pub unsafe fn assert_eq_m256d(a: __m256d, b: __m256d) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f64; 4]>(a), transmute::<_, [f64; 4]>(b))
-        };
-        rt: unsafe {
-            let cmp = _mm256_cmp_pd::<_CMP_EQ_OQ>(a, b);
-            if _mm256_movemask_pd(cmp) != 0b1111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m256(a: __m256, b: __m256) {
+    assert_eq!(a.as_f32x8(), b.as_f32x8());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx")]
-    pub unsafe fn assert_eq_m256(a: __m256, b: __m256) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f32; 8]>(a), transmute::<_, [f32; 8]>(b))
-        };
-        rt: unsafe {
-            let cmp = _mm256_cmp_ps::<_CMP_EQ_OQ>(a, b);
-            if _mm256_movemask_ps(cmp) != 0b11111111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m256d(a: __m256d, b: __m256d) {
+    assert_eq!(a.as_f64x4(), b.as_f64x4());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx512fp16,avx512vl")]
-    pub unsafe fn assert_eq_m256h(a: __m256h, b: __m256h) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f16; 16]>(a), transmute::<_, [f16; 16]>(b))
-        };
-        rt: unsafe {
-            let r = _mm256_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
-            if r != 0b11111111_11111111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m256h(a: __m256h, b: __m256h) {
+    assert_eq!(a.as_f16x16(), b.as_f16x16());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx512f")]
-    pub unsafe fn assert_eq_m512d(a: __m512d, b: __m512d) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f64; 8]>(a), transmute::<_, [f64; 8]>(b))
-        };
-        rt: unsafe {
-            let cmp = _mm512_cmp_pd_mask::<_CMP_EQ_OQ>(a, b);
-            if cmp != 0b11111111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m512i(a: __m512i, b: __m512i) {
+    assert_eq!(a.as_i64x8(), b.as_i64x8());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx512f")]
-    pub unsafe fn assert_eq_m512(a: __m512, b: __m512) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f32; 16]>(a), transmute::<_, [f32; 16]>(b))
-        };
-        rt: unsafe {
-            let cmp = _mm512_cmp_ps_mask::<_CMP_EQ_OQ>(a, b);
-            if cmp != 0b11111111_11111111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m512(a: __m512, b: __m512) {
+    assert_eq!(a.as_f32x16(), b.as_f32x16());
+}
 
-    #[track_caller]
-    #[target_feature(enable = "avx512fp16")]
-    pub unsafe fn assert_eq_m512h(a: __m512h, b: __m512h) {
-        ct: unsafe {
-            assert_eq!(transmute::<_, [f16; 32]>(a), transmute::<_, [f16; 32]>(b))
-        };
-        rt: unsafe {
-            let r = _mm512_cmp_ph_mask::<_CMP_EQ_OQ>(a, b);
-            if r != 0b11111111_11111111_11111111_11111111 {
-                panic!("{:?} != {:?}", a, b);
-            }
-        };
-    }
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m512d(a: __m512d, b: __m512d) {
+    assert_eq!(a.as_f64x8(), b.as_f64x8());
+}
+
+#[track_caller]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const fn assert_eq_m512h(a: __m512h, b: __m512h) {
+    assert_eq!(a.as_f16x32(), b.as_f16x32());
 }
 
 #[target_feature(enable = "sse2")]
-pub(crate) const unsafe fn get_m128d(a: __m128d, idx: usize) -> f64 {
-    transmute::<_, [f64; 2]>(a)[idx]
+pub(crate) const fn get_m128d(a: __m128d, idx: usize) -> f64 {
+    a.as_f64x2().extract(idx)
 }
 
 #[target_feature(enable = "sse")]
-pub(crate) const unsafe fn get_m128(a: __m128, idx: usize) -> f32 {
-    transmute::<_, [f32; 4]>(a)[idx]
+pub(crate) const fn get_m128(a: __m128, idx: usize) -> f32 {
+    a.as_f32x4().extract(idx)
 }
 
 #[target_feature(enable = "avx")]
-pub(crate) const unsafe fn get_m256d(a: __m256d, idx: usize) -> f64 {
-    transmute::<_, [f64; 4]>(a)[idx]
+pub(crate) const fn get_m256d(a: __m256d, idx: usize) -> f64 {
+    a.as_f64x4().extract(idx)
 }
 
 #[target_feature(enable = "avx")]
-pub(crate) const unsafe fn get_m256(a: __m256, idx: usize) -> f32 {
-    transmute::<_, [f32; 8]>(a)[idx]
+pub(crate) const fn get_m256(a: __m256, idx: usize) -> f32 {
+    a.as_f32x8().extract(idx)
 }
 
 #[target_feature(enable = "avx512f")]
-pub(crate) const unsafe fn get_m512(a: __m512, idx: usize) -> f32 {
-    transmute::<_, [f32; 16]>(a)[idx]
+pub(crate) const fn get_m512(a: __m512, idx: usize) -> f32 {
+    a.as_f32x16().extract(idx)
 }
 
 #[target_feature(enable = "avx512f")]
-pub(crate) const unsafe fn get_m512d(a: __m512d, idx: usize) -> f64 {
-    transmute::<_, [f64; 8]>(a)[idx]
+pub(crate) const fn get_m512d(a: __m512d, idx: usize) -> f64 {
+    a.as_f64x8().extract(idx)
 }
 
 #[target_feature(enable = "avx512f")]
-pub(crate) const unsafe fn get_m512i(a: __m512i, idx: usize) -> i64 {
-    transmute::<_, [i64; 8]>(a)[idx]
+pub(crate) const fn get_m512i(a: __m512i, idx: usize) -> i64 {
+    a.as_i64x8().extract(idx)
 }
 
 // not actually an intrinsic but useful in various tests as we ported from
 // `i64x2::new` which is backwards from `_mm_set_epi64x`
 #[target_feature(enable = "sse2")]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub const unsafe fn _mm_setr_epi64x(a: i64, b: i64) -> __m128i {
+pub const fn _mm_setr_epi64x(a: i64, b: i64) -> __m128i {
     _mm_set_epi64x(b, a)
 }
 
@@ -232,17 +129,17 @@ mod x86_polyfill {
 
     #[rustc_legacy_const_generics(2)]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-    pub const unsafe fn _mm_insert_epi64<const INDEX: i32>(a: __m128i, val: i64) -> __m128i {
+    pub const fn _mm_insert_epi64<const INDEX: i32>(a: __m128i, val: i64) -> __m128i {
         static_assert_uimm_bits!(INDEX, 1);
-        transmute(simd_insert!(a.as_i64x2(), INDEX as u32, val))
+        unsafe { transmute(simd_insert!(a.as_i64x2(), INDEX as u32, val)) }
     }
 
     #[target_feature(enable = "avx2")]
     #[rustc_legacy_const_generics(2)]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-    pub const unsafe fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, val: i64) -> __m256i {
+    pub const fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, val: i64) -> __m256i {
         static_assert_uimm_bits!(INDEX, 2);
-        transmute(simd_insert!(a.as_i64x4(), INDEX as u32, val))
+        unsafe { transmute(simd_insert!(a.as_i64x4(), INDEX as u32, val)) }
     }
 }
 
diff --git a/crates/core_arch/src/x86/vaes.rs b/crates/core_arch/src/x86/vaes.rs
index 561b8b4b30..864b1d56d1 100644
--- a/crates/core_arch/src/x86/vaes.rs
+++ b/crates/core_arch/src/x86/vaes.rs
@@ -146,9 +146,9 @@ mod tests {
     // ideally we'd be using quickcheck here instead
 
     #[target_feature(enable = "avx2")]
-    unsafe fn helper_for_256_vaes(
-        linear: unsafe fn(__m128i, __m128i) -> __m128i,
-        vectorized: unsafe fn(__m256i, __m256i) -> __m256i,
+    fn helper_for_256_vaes(
+        linear: fn(__m128i, __m128i) -> __m128i,
+        vectorized: fn(__m256i, __m256i) -> __m256i,
     ) {
         let a = _mm256_set_epi64x(
             0xDCB4DB3657BF0B7D,
@@ -178,7 +178,7 @@ mod tests {
     }
 
     #[target_feature(enable = "sse2")]
-    unsafe fn setup_state_key<T>(broadcast: unsafe fn(__m128i) -> T) -> (T, T) {
+    fn setup_state_key<T>(broadcast: fn(__m128i) -> T) -> (T, T) {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664949.aspx.
         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
@@ -186,17 +186,17 @@ mod tests {
     }
 
     #[target_feature(enable = "avx2")]
-    unsafe fn setup_state_key_256() -> (__m256i, __m256i) {
+    fn setup_state_key_256() -> (__m256i, __m256i) {
         setup_state_key(_mm256_broadcastsi128_si256)
     }
 
     #[target_feature(enable = "avx512f")]
-    unsafe fn setup_state_key_512() -> (__m512i, __m512i) {
+    fn setup_state_key_512() -> (__m512i, __m512i) {
         setup_state_key(_mm512_broadcast_i32x4)
     }
 
     #[simd_test(enable = "vaes,avx512vl")]
-    unsafe fn test_mm256_aesdec_epi128() {
+    fn test_mm256_aesdec_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664949.aspx.
         let (a, k) = setup_state_key_256();
         let e = _mm_set_epi64x(0x044e4f5176fec48f, 0xb57ecfa381da39ee);
@@ -208,7 +208,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512vl")]
-    unsafe fn test_mm256_aesdeclast_epi128() {
+    fn test_mm256_aesdeclast_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714178.aspx.
         let (a, k) = setup_state_key_256();
         let e = _mm_set_epi64x(0x36cad57d9072bf9e, 0xf210dd981fa4a493);
@@ -220,7 +220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512vl")]
-    unsafe fn test_mm256_aesenc_epi128() {
+    fn test_mm256_aesenc_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664810.aspx.
         // they are repeated appropriately
         let (a, k) = setup_state_key_256();
@@ -233,7 +233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512vl")]
-    unsafe fn test_mm256_aesenclast_epi128() {
+    fn test_mm256_aesenclast_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714136.aspx.
         let (a, k) = setup_state_key_256();
         let e = _mm_set_epi64x(0xb6dd7df25d7ab320, 0x4b04f98cf4c860f8);
@@ -245,9 +245,9 @@ mod tests {
     }
 
     #[target_feature(enable = "avx512f")]
-    unsafe fn helper_for_512_vaes(
-        linear: unsafe fn(__m128i, __m128i) -> __m128i,
-        vectorized: unsafe fn(__m512i, __m512i) -> __m512i,
+    fn helper_for_512_vaes(
+        linear: fn(__m128i, __m128i) -> __m128i,
+        vectorized: fn(__m512i, __m512i) -> __m512i,
     ) {
         let a = _mm512_set_epi64(
             0xDCB4DB3657BF0B7D,
@@ -291,7 +291,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512f")]
-    unsafe fn test_mm512_aesdec_epi128() {
+    fn test_mm512_aesdec_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664949.aspx.
         let (a, k) = setup_state_key_512();
         let e = _mm_set_epi64x(0x044e4f5176fec48f, 0xb57ecfa381da39ee);
@@ -303,7 +303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512f")]
-    unsafe fn test_mm512_aesdeclast_epi128() {
+    fn test_mm512_aesdeclast_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714178.aspx.
         let (a, k) = setup_state_key_512();
         let e = _mm_set_epi64x(0x36cad57d9072bf9e, 0xf210dd981fa4a493);
@@ -315,7 +315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512f")]
-    unsafe fn test_mm512_aesenc_epi128() {
+    fn test_mm512_aesenc_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664810.aspx.
         let (a, k) = setup_state_key_512();
         let e = _mm_set_epi64x(0x16ab0e57dfc442ed, 0x28e4ee1884504333);
@@ -327,7 +327,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vaes,avx512f")]
-    unsafe fn test_mm512_aesenclast_epi128() {
+    fn test_mm512_aesenclast_epi128() {
         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714136.aspx.
         let (a, k) = setup_state_key_512();
         let e = _mm_set_epi64x(0xb6dd7df25d7ab320, 0x4b04f98cf4c860f8);
diff --git a/crates/core_arch/src/x86/vpclmulqdq.rs b/crates/core_arch/src/x86/vpclmulqdq.rs
index b1f23bd2f4..ad44e59f3a 100644
--- a/crates/core_arch/src/x86/vpclmulqdq.rs
+++ b/crates/core_arch/src/x86/vpclmulqdq.rs
@@ -124,9 +124,9 @@ mod tests {
     // this function tests one of the possible 4 instances
     // with different inputs across lanes
     #[target_feature(enable = "vpclmulqdq,avx512f")]
-    unsafe fn verify_512_helper(
-        linear: unsafe fn(__m128i, __m128i) -> __m128i,
-        vectorized: unsafe fn(__m512i, __m512i) -> __m512i,
+    fn verify_512_helper(
+        linear: fn(__m128i, __m128i) -> __m128i,
+        vectorized: fn(__m512i, __m512i) -> __m512i,
     ) {
         let a = _mm512_set_epi64(
             0xDCB4DB3657BF0B7D,
@@ -165,9 +165,9 @@ mod tests {
     // this function tests one of the possible 4 instances
     // with different inputs across lanes for the VL version
     #[target_feature(enable = "vpclmulqdq,avx512vl")]
-    unsafe fn verify_256_helper(
-        linear: unsafe fn(__m128i, __m128i) -> __m128i,
-        vectorized: unsafe fn(__m256i, __m256i) -> __m256i,
+    fn verify_256_helper(
+        linear: fn(__m128i, __m128i) -> __m128i,
+        vectorized: fn(__m256i, __m256i) -> __m256i,
     ) {
         let a = _mm512_set_epi64(
             0xDCB4DB3657BF0B7D,
@@ -207,7 +207,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vpclmulqdq,avx512f")]
-    unsafe fn test_mm512_clmulepi64_epi128() {
+    fn test_mm512_clmulepi64_epi128() {
         verify_kat_pclmul!(
             _mm512_broadcast_i32x4,
             _mm512_clmulepi64_epi128,
@@ -233,7 +233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "vpclmulqdq,avx512vl")]
-    unsafe fn test_mm256_clmulepi64_epi128() {
+    fn test_mm256_clmulepi64_epi128() {
         verify_kat_pclmul!(
             _mm256_broadcastsi128_si256,
             _mm256_clmulepi64_epi128,
diff --git a/crates/core_arch/src/x86_64/abm.rs b/crates/core_arch/src/x86_64/abm.rs
index 9fb76be4ba..21b5f26a9b 100644
--- a/crates/core_arch/src/x86_64/abm.rs
+++ b/crates/core_arch/src/x86_64/abm.rs
@@ -54,12 +54,12 @@ mod tests {
     use crate::core_arch::arch::x86_64::*;
 
     #[simd_test(enable = "lzcnt")]
-    const unsafe fn test_lzcnt_u64() {
+    const fn test_lzcnt_u64() {
         assert_eq!(_lzcnt_u64(0b0101_1010), 57);
     }
 
     #[simd_test(enable = "popcnt")]
-    const unsafe fn test_popcnt64() {
+    const fn test_popcnt64() {
         assert_eq!(_popcnt64(0b0101_1010), 4);
     }
 }
diff --git a/crates/core_arch/src/x86_64/avx.rs b/crates/core_arch/src/x86_64/avx.rs
index aae3c981d6..b626c1a592 100644
--- a/crates/core_arch/src/x86_64/avx.rs
+++ b/crates/core_arch/src/x86_64/avx.rs
@@ -52,7 +52,7 @@ mod tests {
     use crate::core_arch::arch::x86_64::*;
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_insert_epi64() {
+    const fn test_mm256_insert_epi64() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let r = _mm256_insert_epi64::<3>(a, 0);
         let e = _mm256_setr_epi64x(1, 2, 3, 0);
@@ -60,7 +60,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_extract_epi64() {
+    const fn test_mm256_extract_epi64() {
         let a = _mm256_setr_epi64x(0, 1, 2, 3);
         let r = _mm256_extract_epi64::<3>(a);
         assert_eq!(r, 3);
diff --git a/crates/core_arch/src/x86_64/avx512bw.rs b/crates/core_arch/src/x86_64/avx512bw.rs
index a8e5183e0c..3450f6e194 100644
--- a/crates/core_arch/src/x86_64/avx512bw.rs
+++ b/crates/core_arch/src/x86_64/avx512bw.rs
@@ -31,7 +31,7 @@ mod tests {
     use crate::core_arch::{x86::*, x86_64::*};
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_cvtmask64_u64() {
+    const fn test_cvtmask64_u64() {
         let a: __mmask64 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtmask64_u64(a);
         let e: u64 = 0b11001100_00110011_01100110_10011001;
@@ -39,7 +39,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_cvtu64_mask64() {
+    const fn test_cvtu64_mask64() {
         let a: u64 = 0b11001100_00110011_01100110_10011001;
         let r = _cvtu64_mask64(a);
         let e: __mmask64 = 0b11001100_00110011_01100110_10011001;
diff --git a/crates/core_arch/src/x86_64/avx512f.rs b/crates/core_arch/src/x86_64/avx512f.rs
index c85a5580c8..368fb0c238 100644
--- a/crates/core_arch/src/x86_64/avx512f.rs
+++ b/crates/core_arch/src/x86_64/avx512f.rs
@@ -567,7 +567,7 @@ mod tests {
     use crate::hint::black_box;
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_abs_epi64() {
+    const fn test_mm512_abs_epi64() {
         let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let r = _mm512_abs_epi64(a);
         let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
@@ -575,7 +575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_abs_epi64() {
+    const fn test_mm512_mask_abs_epi64() {
         let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let r = _mm512_mask_abs_epi64(a, 0, a);
         assert_eq_m512i(r, a);
@@ -585,7 +585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_abs_epi64() {
+    const fn test_mm512_maskz_abs_epi64() {
         let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let r = _mm512_maskz_abs_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -595,7 +595,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_abs_epi64() {
+    const fn test_mm256_abs_epi64() {
         let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
         let r = _mm256_abs_epi64(a);
         let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
@@ -603,7 +603,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_abs_epi64() {
+    const fn test_mm256_mask_abs_epi64() {
         let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
         let r = _mm256_mask_abs_epi64(a, 0, a);
         assert_eq_m256i(r, a);
@@ -613,7 +613,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_abs_epi64() {
+    const fn test_mm256_maskz_abs_epi64() {
         let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
         let r = _mm256_maskz_abs_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -623,7 +623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_abs_epi64() {
+    const fn test_mm_abs_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let r = _mm_abs_epi64(a);
         let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
@@ -635,7 +635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_abs_epi64() {
+    const fn test_mm_mask_abs_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let r = _mm_mask_abs_epi64(a, 0, a);
         assert_eq_m128i(r, a);
@@ -649,7 +649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_abs_epi64() {
+    const fn test_mm_maskz_abs_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let r = _mm_maskz_abs_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -663,7 +663,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_abs_pd() {
+    const fn test_mm512_abs_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let r = _mm512_abs_pd(a);
         let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
@@ -671,7 +671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_abs_pd() {
+    const fn test_mm512_mask_abs_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let r = _mm512_mask_abs_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -681,7 +681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mov_epi64() {
+    const fn test_mm512_mask_mov_epi64() {
         let src = _mm512_set1_epi64(1);
         let a = _mm512_set1_epi64(2);
         let r = _mm512_mask_mov_epi64(src, 0, a);
@@ -691,7 +691,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mov_epi64() {
+    const fn test_mm512_maskz_mov_epi64() {
         let a = _mm512_set1_epi64(2);
         let r = _mm512_maskz_mov_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -700,7 +700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mov_epi64() {
+    const fn test_mm256_mask_mov_epi64() {
         let src = _mm256_set1_epi64x(1);
         let a = _mm256_set1_epi64x(2);
         let r = _mm256_mask_mov_epi64(src, 0, a);
@@ -710,7 +710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mov_epi64() {
+    const fn test_mm256_maskz_mov_epi64() {
         let a = _mm256_set1_epi64x(2);
         let r = _mm256_maskz_mov_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -719,7 +719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mov_epi64() {
+    const fn test_mm_mask_mov_epi64() {
         let src = _mm_set1_epi64x(1);
         let a = _mm_set1_epi64x(2);
         let r = _mm_mask_mov_epi64(src, 0, a);
@@ -729,7 +729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mov_epi64() {
+    const fn test_mm_maskz_mov_epi64() {
         let a = _mm_set1_epi64x(2);
         let r = _mm_maskz_mov_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -738,7 +738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mov_pd() {
+    const fn test_mm512_mask_mov_pd() {
         let src = _mm512_set1_pd(1.);
         let a = _mm512_set1_pd(2.);
         let r = _mm512_mask_mov_pd(src, 0, a);
@@ -748,7 +748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mov_pd() {
+    const fn test_mm512_maskz_mov_pd() {
         let a = _mm512_set1_pd(2.);
         let r = _mm512_maskz_mov_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -757,7 +757,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mov_pd() {
+    const fn test_mm256_mask_mov_pd() {
         let src = _mm256_set1_pd(1.);
         let a = _mm256_set1_pd(2.);
         let r = _mm256_mask_mov_pd(src, 0, a);
@@ -767,7 +767,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mov_pd() {
+    const fn test_mm256_maskz_mov_pd() {
         let a = _mm256_set1_pd(2.);
         let r = _mm256_maskz_mov_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -776,7 +776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mov_pd() {
+    const fn test_mm_mask_mov_pd() {
         let src = _mm_set1_pd(1.);
         let a = _mm_set1_pd(2.);
         let r = _mm_mask_mov_pd(src, 0, a);
@@ -786,7 +786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mov_pd() {
+    const fn test_mm_maskz_mov_pd() {
         let a = _mm_set1_pd(2.);
         let r = _mm_maskz_mov_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -795,7 +795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_add_epi64() {
+    const fn test_mm512_add_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_add_epi64(a, b);
@@ -804,7 +804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_add_epi64() {
+    const fn test_mm512_mask_add_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_mask_add_epi64(a, 0, a, b);
@@ -815,7 +815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_add_epi64() {
+    const fn test_mm512_maskz_add_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_maskz_add_epi64(0, a, b);
@@ -826,7 +826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_add_epi64() {
+    const fn test_mm256_mask_add_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_mask_add_epi64(a, 0, a, b);
@@ -837,7 +837,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_epi64() {
+    const fn test_mm256_maskz_add_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_add_epi64(0, a, b);
@@ -848,7 +848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_add_epi64() {
+    const fn test_mm_mask_add_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_mask_add_epi64(a, 0, a, b);
@@ -859,7 +859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_add_epi64() {
+    const fn test_mm_maskz_add_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_maskz_add_epi64(0, a, b);
@@ -870,7 +870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_add_pd() {
+    const fn test_mm512_add_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_add_pd(a, b);
@@ -879,7 +879,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_add_pd() {
+    const fn test_mm512_mask_add_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_mask_add_pd(a, 0, a, b);
@@ -890,7 +890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_add_pd() {
+    const fn test_mm512_maskz_add_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_maskz_add_pd(0, a, b);
@@ -901,7 +901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_add_pd() {
+    const fn test_mm256_mask_add_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_mask_add_pd(a, 0, a, b);
@@ -912,7 +912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_add_pd() {
+    const fn test_mm256_maskz_add_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_maskz_add_pd(0, a, b);
@@ -923,7 +923,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_add_pd() {
+    const fn test_mm_mask_add_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_mask_add_pd(a, 0, a, b);
@@ -934,7 +934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_add_pd() {
+    const fn test_mm_maskz_add_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_maskz_add_pd(0, a, b);
@@ -945,7 +945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_sub_epi64() {
+    const fn test_mm512_sub_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_sub_epi64(a, b);
@@ -954,7 +954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_sub_epi64() {
+    const fn test_mm512_mask_sub_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_mask_sub_epi64(a, 0, a, b);
@@ -965,7 +965,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_sub_epi64() {
+    const fn test_mm512_maskz_sub_epi64() {
         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
         let b = _mm512_set1_epi64(1);
         let r = _mm512_maskz_sub_epi64(0, a, b);
@@ -976,7 +976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_epi64() {
+    const fn test_mm256_mask_sub_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_mask_sub_epi64(a, 0, a, b);
@@ -987,7 +987,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_epi64() {
+    const fn test_mm256_maskz_sub_epi64() {
         let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_sub_epi64(0, a, b);
@@ -998,7 +998,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_sub_epi64() {
+    const fn test_mm_mask_sub_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_mask_sub_epi64(a, 0, a, b);
@@ -1009,7 +1009,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_epi64() {
+    const fn test_mm_maskz_sub_epi64() {
         let a = _mm_set_epi64x(i64::MAX, i64::MIN);
         let b = _mm_set1_epi64x(1);
         let r = _mm_maskz_sub_epi64(0, a, b);
@@ -1020,7 +1020,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_sub_pd() {
+    const fn test_mm512_sub_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_sub_pd(a, b);
@@ -1029,7 +1029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_sub_pd() {
+    const fn test_mm512_mask_sub_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_mask_sub_pd(a, 0, a, b);
@@ -1040,7 +1040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_sub_pd() {
+    const fn test_mm512_maskz_sub_pd() {
         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_maskz_sub_pd(0, a, b);
@@ -1051,7 +1051,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_sub_pd() {
+    const fn test_mm256_mask_sub_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_mask_sub_pd(a, 0, a, b);
@@ -1062,7 +1062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_sub_pd() {
+    const fn test_mm256_maskz_sub_pd() {
         let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(1.);
         let r = _mm256_maskz_sub_pd(0, a, b);
@@ -1073,7 +1073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_sub_pd() {
+    const fn test_mm_mask_sub_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_mask_sub_pd(a, 0, a, b);
@@ -1084,7 +1084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_sub_pd() {
+    const fn test_mm_maskz_sub_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(1.);
         let r = _mm_maskz_sub_pd(0, a, b);
@@ -1095,7 +1095,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mul_epi32() {
+    const fn test_mm512_mul_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mul_epi32(a, b);
@@ -1104,7 +1104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mul_epi32() {
+    const fn test_mm512_mask_mul_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_mul_epi32(a, 0, a, b);
@@ -1119,7 +1119,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mul_epi32() {
+    const fn test_mm512_maskz_mul_epi32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_mul_epi32(0, a, b);
@@ -1130,7 +1130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mul_epi32() {
+    const fn test_mm256_mask_mul_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mask_mul_epi32(a, 0, a, b);
@@ -1141,7 +1141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mul_epi32() {
+    const fn test_mm256_maskz_mul_epi32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_mul_epi32(0, a, b);
@@ -1152,7 +1152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mul_epi32() {
+    const fn test_mm_mask_mul_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_mask_mul_epi32(a, 0, a, b);
@@ -1163,7 +1163,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mul_epi32() {
+    const fn test_mm_maskz_mul_epi32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_mul_epi32(0, a, b);
@@ -1174,7 +1174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mul_epu32() {
+    const fn test_mm512_mul_epu32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mul_epu32(a, b);
@@ -1183,7 +1183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mul_epu32() {
+    const fn test_mm512_mask_mul_epu32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_mask_mul_epu32(a, 0, a, b);
@@ -1198,7 +1198,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mul_epu32() {
+    const fn test_mm512_maskz_mul_epu32() {
         let a = _mm512_set1_epi32(1);
         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm512_maskz_mul_epu32(0, a, b);
@@ -1209,7 +1209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mul_epu32() {
+    const fn test_mm256_mask_mul_epu32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_mask_mul_epu32(a, 0, a, b);
@@ -1220,7 +1220,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mul_epu32() {
+    const fn test_mm256_maskz_mul_epu32() {
         let a = _mm256_set1_epi32(1);
         let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm256_maskz_mul_epu32(0, a, b);
@@ -1231,7 +1231,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mul_epu32() {
+    const fn test_mm_mask_mul_epu32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_mask_mul_epu32(a, 0, a, b);
@@ -1242,7 +1242,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mul_epu32() {
+    const fn test_mm_maskz_mul_epu32() {
         let a = _mm_set1_epi32(1);
         let b = _mm_set_epi32(1, 2, 3, 4);
         let r = _mm_maskz_mul_epu32(0, a, b);
@@ -1253,7 +1253,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mullox_epi64() {
+    const fn test_mm512_mullox_epi64() {
         let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
         let b = _mm512_set1_epi64(2);
         let r = _mm512_mullox_epi64(a, b);
@@ -1262,7 +1262,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mullox_epi64() {
+    const fn test_mm512_mask_mullox_epi64() {
         let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
         let b = _mm512_set1_epi64(2);
         let r = _mm512_mask_mullox_epi64(a, 0, a, b);
@@ -1273,7 +1273,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mul_pd() {
+    const fn test_mm512_mul_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_mul_pd(a, b);
@@ -1286,7 +1286,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_mul_pd() {
+    const fn test_mm512_mask_mul_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_mask_mul_pd(a, 0, a, b);
@@ -1301,7 +1301,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_mul_pd() {
+    const fn test_mm512_maskz_mul_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_maskz_mul_pd(0, a, b);
@@ -1312,7 +1312,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_mul_pd() {
+    const fn test_mm256_mask_mul_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(2.);
         let r = _mm256_mask_mul_pd(a, 0, a, b);
@@ -1323,7 +1323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_mul_pd() {
+    const fn test_mm256_maskz_mul_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set1_pd(2.);
         let r = _mm256_maskz_mul_pd(0, a, b);
@@ -1334,7 +1334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_mul_pd() {
+    const fn test_mm_mask_mul_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(2.);
         let r = _mm_mask_mul_pd(a, 0, a, b);
@@ -1345,7 +1345,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_mul_pd() {
+    const fn test_mm_maskz_mul_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set1_pd(2.);
         let r = _mm_maskz_mul_pd(0, a, b);
@@ -1356,7 +1356,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_div_pd() {
+    const fn test_mm512_div_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
         let r = _mm512_div_pd(a, b);
@@ -1369,7 +1369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_div_pd() {
+    const fn test_mm512_mask_div_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
         let r = _mm512_mask_div_pd(a, 0, a, b);
@@ -1384,7 +1384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_div_pd() {
+    const fn test_mm512_maskz_div_pd() {
         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
         let r = _mm512_maskz_div_pd(0, a, b);
@@ -1395,7 +1395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_div_pd() {
+    const fn test_mm256_mask_div_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set_pd(2., 2., 0., 0.);
         let r = _mm256_mask_div_pd(a, 0, a, b);
@@ -1406,7 +1406,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_div_pd() {
+    const fn test_mm256_maskz_div_pd() {
         let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
         let b = _mm256_set_pd(2., 2., 0., 0.);
         let r = _mm256_maskz_div_pd(0, a, b);
@@ -1417,7 +1417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_div_pd() {
+    const fn test_mm_mask_div_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set_pd(0., 0.);
         let r = _mm_mask_div_pd(a, 0, a, b);
@@ -1428,7 +1428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_div_pd() {
+    const fn test_mm_maskz_div_pd() {
         let a = _mm_set_pd(f64::MAX, f64::MIN);
         let b = _mm_set_pd(0., 0.);
         let r = _mm_maskz_div_pd(0, a, b);
@@ -1439,7 +1439,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_max_epi64() {
+    const fn test_mm512_max_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epi64(a, b);
@@ -1448,7 +1448,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_max_epi64() {
+    const fn test_mm512_mask_max_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epi64(a, 0, a, b);
@@ -1459,7 +1459,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_max_epi64() {
+    const fn test_mm512_maskz_max_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epi64(0, a, b);
@@ -1470,7 +1470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_max_epi64() {
+    const fn test_mm256_max_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_max_epi64(a, b);
@@ -1479,7 +1479,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epi64() {
+    const fn test_mm256_mask_max_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_max_epi64(a, 0, a, b);
@@ -1490,7 +1490,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epi64() {
+    const fn test_mm256_maskz_max_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_max_epi64(0, a, b);
@@ -1501,7 +1501,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_max_epi64() {
+    const fn test_mm_max_epi64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_max_epi64(a, b);
@@ -1510,7 +1510,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_max_epi64() {
+    const fn test_mm_mask_max_epi64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_mask_max_epi64(a, 0, a, b);
@@ -1521,7 +1521,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epi64() {
+    const fn test_mm_maskz_max_epi64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_maskz_max_epi64(0, a, b);
@@ -1532,7 +1532,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_pd() {
+    fn test_mm512_max_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_max_pd(a, b);
@@ -1541,7 +1541,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_pd() {
+    fn test_mm512_mask_max_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_mask_max_pd(a, 0, a, b);
@@ -1552,7 +1552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_pd() {
+    fn test_mm512_maskz_max_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_maskz_max_pd(0, a, b);
@@ -1563,7 +1563,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_max_pd() {
+    fn test_mm256_mask_max_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let b = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_mask_max_pd(a, 0, a, b);
@@ -1574,7 +1574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_max_pd() {
+    fn test_mm256_maskz_max_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let b = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_maskz_max_pd(0, a, b);
@@ -1585,7 +1585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_max_pd() {
+    fn test_mm_mask_max_pd() {
         let a = _mm_set_pd(2., 3.);
         let b = _mm_set_pd(3., 2.);
         let r = _mm_mask_max_pd(a, 0, a, b);
@@ -1596,7 +1596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_max_pd() {
+    fn test_mm_maskz_max_pd() {
         let a = _mm_set_pd(2., 3.);
         let b = _mm_set_pd(3., 2.);
         let r = _mm_maskz_max_pd(0, a, b);
@@ -1607,7 +1607,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_max_epu64() {
+    const fn test_mm512_max_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_max_epu64(a, b);
@@ -1616,7 +1616,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_max_epu64() {
+    const fn test_mm512_mask_max_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_max_epu64(a, 0, a, b);
@@ -1627,7 +1627,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_max_epu64() {
+    const fn test_mm512_maskz_max_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_max_epu64(0, a, b);
@@ -1638,7 +1638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_max_epu64() {
+    const fn test_mm256_max_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_max_epu64(a, b);
@@ -1647,7 +1647,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_max_epu64() {
+    const fn test_mm256_mask_max_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_max_epu64(a, 0, a, b);
@@ -1658,7 +1658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_max_epu64() {
+    const fn test_mm256_maskz_max_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_max_epu64(0, a, b);
@@ -1669,7 +1669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_max_epu64() {
+    const fn test_mm_max_epu64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_max_epu64(a, b);
@@ -1678,7 +1678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_max_epu64() {
+    const fn test_mm_mask_max_epu64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_mask_max_epu64(a, 0, a, b);
@@ -1689,7 +1689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_max_epu64() {
+    const fn test_mm_maskz_max_epu64() {
         let a = _mm_set_epi64x(2, 3);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_maskz_max_epu64(0, a, b);
@@ -1700,7 +1700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_min_epi64() {
+    const fn test_mm512_min_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epi64(a, b);
@@ -1709,7 +1709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_min_epi64() {
+    const fn test_mm512_mask_min_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epi64(a, 0, a, b);
@@ -1720,7 +1720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_min_epi64() {
+    const fn test_mm512_maskz_min_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epi64(0, a, b);
@@ -1731,7 +1731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_min_epi64() {
+    const fn test_mm256_min_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_min_epi64(a, b);
@@ -1740,7 +1740,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epi64() {
+    const fn test_mm256_mask_min_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_min_epi64(a, 0, a, b);
@@ -1751,7 +1751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epi64() {
+    const fn test_mm256_maskz_min_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_min_epi64(0, a, b);
@@ -1762,7 +1762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_min_epi64() {
+    const fn test_mm_min_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_min_epi64(a, b);
@@ -1776,7 +1776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_min_epi64() {
+    const fn test_mm_mask_min_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_mask_min_epi64(a, 0, a, b);
@@ -1787,7 +1787,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epi64() {
+    const fn test_mm_maskz_min_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(3, 2);
         let r = _mm_maskz_min_epi64(0, a, b);
@@ -1798,7 +1798,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_pd() {
+    fn test_mm512_min_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_min_pd(a, b);
@@ -1807,7 +1807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_pd() {
+    fn test_mm512_mask_min_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_mask_min_pd(a, 0, a, b);
@@ -1818,7 +1818,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_pd() {
+    fn test_mm512_maskz_min_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_maskz_min_pd(0, a, b);
@@ -1829,7 +1829,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_min_pd() {
+    fn test_mm256_mask_min_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let b = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_mask_min_pd(a, 0, a, b);
@@ -1840,7 +1840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_min_pd() {
+    fn test_mm256_maskz_min_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let b = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_maskz_min_pd(0, a, b);
@@ -1851,7 +1851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_min_pd() {
+    fn test_mm_mask_min_pd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(1., 0.);
         let r = _mm_mask_min_pd(a, 0, a, b);
@@ -1862,7 +1862,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_min_pd() {
+    fn test_mm_maskz_min_pd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set_pd(1., 0.);
         let r = _mm_maskz_min_pd(0, a, b);
@@ -1873,7 +1873,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_min_epu64() {
+    const fn test_mm512_min_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_min_epu64(a, b);
@@ -1882,7 +1882,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_min_epu64() {
+    const fn test_mm512_mask_min_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_mask_min_epu64(a, 0, a, b);
@@ -1893,7 +1893,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_min_epu64() {
+    const fn test_mm512_maskz_min_epu64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
         let r = _mm512_maskz_min_epu64(0, a, b);
@@ -1904,7 +1904,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_min_epu64() {
+    const fn test_mm256_min_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_min_epu64(a, b);
@@ -1913,7 +1913,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_min_epu64() {
+    const fn test_mm256_mask_min_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_min_epu64(a, 0, a, b);
@@ -1924,7 +1924,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_min_epu64() {
+    const fn test_mm256_maskz_min_epu64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_min_epu64(0, a, b);
@@ -1935,7 +1935,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_min_epu64() {
+    const fn test_mm_min_epu64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(1, 0);
         let r = _mm_min_epu64(a, b);
@@ -1944,7 +1944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_min_epu64() {
+    const fn test_mm_mask_min_epu64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(1, 0);
         let r = _mm_mask_min_epu64(a, 0, a, b);
@@ -1955,7 +1955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_min_epu64() {
+    const fn test_mm_maskz_min_epu64() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(1, 0);
         let r = _mm_maskz_min_epu64(0, a, b);
@@ -1966,7 +1966,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sqrt_pd() {
+    fn test_mm512_sqrt_pd() {
         let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
         let r = _mm512_sqrt_pd(a);
         let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
@@ -1974,7 +1974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sqrt_pd() {
+    fn test_mm512_mask_sqrt_pd() {
         let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
         let r = _mm512_mask_sqrt_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -1984,7 +1984,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sqrt_pd() {
+    fn test_mm512_maskz_sqrt_pd() {
         let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
         let r = _mm512_maskz_sqrt_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -1994,7 +1994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sqrt_pd() {
+    fn test_mm256_mask_sqrt_pd() {
         let a = _mm256_set_pd(0., 1., 4., 9.);
         let r = _mm256_mask_sqrt_pd(a, 0, a);
         assert_eq_m256d(r, a);
@@ -2004,7 +2004,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sqrt_pd() {
+    fn test_mm256_maskz_sqrt_pd() {
         let a = _mm256_set_pd(0., 1., 4., 9.);
         let r = _mm256_maskz_sqrt_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -2014,7 +2014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sqrt_pd() {
+    fn test_mm_mask_sqrt_pd() {
         let a = _mm_set_pd(0., 1.);
         let r = _mm_mask_sqrt_pd(a, 0, a);
         assert_eq_m128d(r, a);
@@ -2024,7 +2024,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sqrt_pd() {
+    fn test_mm_maskz_sqrt_pd() {
         let a = _mm_set_pd(0., 1.);
         let r = _mm_maskz_sqrt_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -2034,7 +2034,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmadd_pd() {
+    const fn test_mm512_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
@@ -2044,7 +2044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmadd_pd() {
+    const fn test_mm512_mask_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
@@ -2056,7 +2056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmadd_pd() {
+    const fn test_mm512_maskz_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
@@ -2068,7 +2068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmadd_pd() {
+    const fn test_mm512_mask3_fmadd_pd() {
         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2080,7 +2080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmadd_pd() {
+    const fn test_mm256_mask_fmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2092,7 +2092,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmadd_pd() {
+    const fn test_mm256_maskz_fmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2104,7 +2104,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmadd_pd() {
+    const fn test_mm256_mask3_fmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2116,7 +2116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmadd_pd() {
+    const fn test_mm_mask_fmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2128,7 +2128,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmadd_pd() {
+    const fn test_mm_maskz_fmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2140,7 +2140,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmadd_pd() {
+    const fn test_mm_mask3_fmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2152,7 +2152,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmsub_pd() {
+    const fn test_mm512_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2162,7 +2162,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmsub_pd() {
+    const fn test_mm512_mask_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2174,7 +2174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmsub_pd() {
+    const fn test_mm512_maskz_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2186,7 +2186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmsub_pd() {
+    const fn test_mm512_mask3_fmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2198,7 +2198,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmsub_pd() {
+    const fn test_mm256_mask_fmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2210,7 +2210,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmsub_pd() {
+    const fn test_mm256_maskz_fmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2222,7 +2222,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmsub_pd() {
+    const fn test_mm256_mask3_fmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2234,7 +2234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmsub_pd() {
+    const fn test_mm_mask_fmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2246,7 +2246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsub_pd() {
+    const fn test_mm_maskz_fmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2258,7 +2258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsub_pd() {
+    const fn test_mm_mask3_fmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2270,7 +2270,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmaddsub_pd() {
+    const fn test_mm512_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2280,7 +2280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmaddsub_pd() {
+    const fn test_mm512_mask_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2292,7 +2292,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmaddsub_pd() {
+    const fn test_mm512_maskz_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2304,7 +2304,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmaddsub_pd() {
+    const fn test_mm512_mask3_fmaddsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2316,7 +2316,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmaddsub_pd() {
+    const fn test_mm256_mask_fmaddsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2328,7 +2328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmaddsub_pd() {
+    const fn test_mm256_maskz_fmaddsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2340,7 +2340,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmaddsub_pd() {
+    const fn test_mm256_mask3_fmaddsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2352,7 +2352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmaddsub_pd() {
+    const fn test_mm_mask_fmaddsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2364,7 +2364,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmaddsub_pd() {
+    const fn test_mm_maskz_fmaddsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2376,7 +2376,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmaddsub_pd() {
+    const fn test_mm_mask3_fmaddsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2388,7 +2388,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fmsubadd_pd() {
+    const fn test_mm512_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2398,7 +2398,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fmsubadd_pd() {
+    const fn test_mm512_mask_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2410,7 +2410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fmsubadd_pd() {
+    const fn test_mm512_maskz_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2422,7 +2422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fmsubadd_pd() {
+    const fn test_mm512_mask3_fmsubadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2434,7 +2434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fmsubadd_pd() {
+    const fn test_mm256_mask_fmsubadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2446,7 +2446,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fmsubadd_pd() {
+    const fn test_mm256_maskz_fmsubadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2458,7 +2458,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fmsubadd_pd() {
+    const fn test_mm256_mask3_fmsubadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2470,7 +2470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fmsubadd_pd() {
+    const fn test_mm_mask_fmsubadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2482,7 +2482,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fmsubadd_pd() {
+    const fn test_mm_maskz_fmsubadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2494,7 +2494,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fmsubadd_pd() {
+    const fn test_mm_mask3_fmsubadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2506,7 +2506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fnmadd_pd() {
+    const fn test_mm512_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2516,7 +2516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fnmadd_pd() {
+    const fn test_mm512_mask_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2528,7 +2528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fnmadd_pd() {
+    const fn test_mm512_maskz_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2540,7 +2540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fnmadd_pd() {
+    const fn test_mm512_mask3_fnmadd_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2552,7 +2552,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fnmadd_pd() {
+    const fn test_mm256_mask_fnmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2564,7 +2564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fnmadd_pd() {
+    const fn test_mm256_maskz_fnmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2576,7 +2576,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fnmadd_pd() {
+    const fn test_mm256_mask3_fnmadd_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2588,7 +2588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fnmadd_pd() {
+    const fn test_mm_mask_fnmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2600,7 +2600,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmadd_pd() {
+    const fn test_mm_maskz_fnmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2612,7 +2612,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmadd_pd() {
+    const fn test_mm_mask3_fnmadd_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2624,7 +2624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_fnmsub_pd() {
+    const fn test_mm512_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2634,7 +2634,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_fnmsub_pd() {
+    const fn test_mm512_mask_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2646,7 +2646,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_fnmsub_pd() {
+    const fn test_mm512_maskz_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_set1_pd(1.);
@@ -2658,7 +2658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask3_fnmsub_pd() {
+    const fn test_mm512_mask3_fnmsub_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
@@ -2670,7 +2670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_fnmsub_pd() {
+    const fn test_mm256_mask_fnmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2682,7 +2682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_fnmsub_pd() {
+    const fn test_mm256_maskz_fnmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2694,7 +2694,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask3_fnmsub_pd() {
+    const fn test_mm256_mask3_fnmsub_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set_pd(0., 1., 2., 3.);
         let c = _mm256_set1_pd(1.);
@@ -2706,7 +2706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_fnmsub_pd() {
+    const fn test_mm_mask_fnmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2718,7 +2718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_fnmsub_pd() {
+    const fn test_mm_maskz_fnmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2730,7 +2730,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask3_fnmsub_pd() {
+    const fn test_mm_mask3_fnmsub_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set_pd(0., 1.);
         let c = _mm_set1_pd(1.);
@@ -2742,7 +2742,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rcp14_pd() {
+    fn test_mm512_rcp14_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_rcp14_pd(a);
         let e = _mm512_set1_pd(0.3333320617675781);
@@ -2750,7 +2750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rcp14_pd() {
+    fn test_mm512_mask_rcp14_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_mask_rcp14_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -2764,7 +2764,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rcp14_pd() {
+    fn test_mm512_maskz_rcp14_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_maskz_rcp14_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -2778,7 +2778,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rcp14_pd() {
+    fn test_mm256_rcp14_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_rcp14_pd(a);
         let e = _mm256_set1_pd(0.3333320617675781);
@@ -2786,7 +2786,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rcp14_pd() {
+    fn test_mm256_mask_rcp14_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_mask_rcp14_pd(a, 0, a);
         assert_eq_m256d(r, a);
@@ -2796,7 +2796,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rcp14_pd() {
+    fn test_mm256_maskz_rcp14_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_maskz_rcp14_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -2806,7 +2806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rcp14_pd() {
+    fn test_mm_rcp14_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_rcp14_pd(a);
         let e = _mm_set1_pd(0.3333320617675781);
@@ -2814,7 +2814,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rcp14_pd() {
+    fn test_mm_mask_rcp14_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_mask_rcp14_pd(a, 0, a);
         assert_eq_m128d(r, a);
@@ -2824,7 +2824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rcp14_pd() {
+    fn test_mm_maskz_rcp14_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_maskz_rcp14_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -2834,7 +2834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_rsqrt14_pd() {
+    fn test_mm512_rsqrt14_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_rsqrt14_pd(a);
         let e = _mm512_set1_pd(0.5773391723632813);
@@ -2842,7 +2842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_rsqrt14_pd() {
+    fn test_mm512_mask_rsqrt14_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_mask_rsqrt14_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -2856,7 +2856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_rsqrt14_pd() {
+    fn test_mm512_maskz_rsqrt14_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_maskz_rsqrt14_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -2870,7 +2870,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_rsqrt14_pd() {
+    fn test_mm256_rsqrt14_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_rsqrt14_pd(a);
         let e = _mm256_set1_pd(0.5773391723632813);
@@ -2878,7 +2878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_rsqrt14_pd() {
+    fn test_mm256_mask_rsqrt14_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_mask_rsqrt14_pd(a, 0, a);
         assert_eq_m256d(r, a);
@@ -2888,7 +2888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_rsqrt14_pd() {
+    fn test_mm256_maskz_rsqrt14_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_maskz_rsqrt14_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -2898,7 +2898,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_rsqrt14_pd() {
+    fn test_mm_rsqrt14_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_rsqrt14_pd(a);
         let e = _mm_set1_pd(0.5773391723632813);
@@ -2906,7 +2906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_rsqrt14_pd() {
+    fn test_mm_mask_rsqrt14_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_mask_rsqrt14_pd(a, 0, a);
         assert_eq_m128d(r, a);
@@ -2916,7 +2916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_rsqrt14_pd() {
+    fn test_mm_maskz_rsqrt14_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_maskz_rsqrt14_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -2926,7 +2926,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getexp_pd() {
+    fn test_mm512_getexp_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_getexp_pd(a);
         let e = _mm512_set1_pd(1.);
@@ -2934,7 +2934,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getexp_pd() {
+    fn test_mm512_mask_getexp_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_mask_getexp_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -2944,7 +2944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getexp_pd() {
+    fn test_mm512_maskz_getexp_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_maskz_getexp_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -2954,7 +2954,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_getexp_pd() {
+    fn test_mm256_getexp_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_getexp_pd(a);
         let e = _mm256_set1_pd(1.);
@@ -2962,7 +2962,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_getexp_pd() {
+    fn test_mm256_mask_getexp_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_mask_getexp_pd(a, 0, a);
         assert_eq_m256d(r, a);
@@ -2972,7 +2972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_getexp_pd() {
+    fn test_mm256_maskz_getexp_pd() {
         let a = _mm256_set1_pd(3.);
         let r = _mm256_maskz_getexp_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -2982,7 +2982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_getexp_pd() {
+    fn test_mm_getexp_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_getexp_pd(a);
         let e = _mm_set1_pd(1.);
@@ -2990,7 +2990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_getexp_pd() {
+    fn test_mm_mask_getexp_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_mask_getexp_pd(a, 0, a);
         assert_eq_m128d(r, a);
@@ -3000,7 +3000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_getexp_pd() {
+    fn test_mm_maskz_getexp_pd() {
         let a = _mm_set1_pd(3.);
         let r = _mm_maskz_getexp_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -3010,7 +3010,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_roundscale_pd() {
+    fn test_mm512_roundscale_pd() {
         let a = _mm512_set1_pd(1.1);
         let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
         let e = _mm512_set1_pd(1.0);
@@ -3018,7 +3018,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_roundscale_pd() {
+    fn test_mm512_mask_roundscale_pd() {
         let a = _mm512_set1_pd(1.1);
         let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
         let e = _mm512_set1_pd(1.1);
@@ -3029,7 +3029,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_roundscale_pd() {
+    fn test_mm512_maskz_roundscale_pd() {
         let a = _mm512_set1_pd(1.1);
         let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -3039,7 +3039,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_roundscale_pd() {
+    fn test_mm256_roundscale_pd() {
         let a = _mm256_set1_pd(1.1);
         let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
         let e = _mm256_set1_pd(1.0);
@@ -3047,7 +3047,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_roundscale_pd() {
+    fn test_mm256_mask_roundscale_pd() {
         let a = _mm256_set1_pd(1.1);
         let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
         assert_eq_m256d(r, a);
@@ -3057,7 +3057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_roundscale_pd() {
+    fn test_mm256_maskz_roundscale_pd() {
         let a = _mm256_set1_pd(1.1);
         let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -3067,7 +3067,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_roundscale_pd() {
+    fn test_mm_roundscale_pd() {
         let a = _mm_set1_pd(1.1);
         let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
         let e = _mm_set1_pd(1.0);
@@ -3075,7 +3075,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_roundscale_pd() {
+    fn test_mm_mask_roundscale_pd() {
         let a = _mm_set1_pd(1.1);
         let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
         let e = _mm_set1_pd(1.1);
@@ -3086,7 +3086,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_roundscale_pd() {
+    fn test_mm_maskz_roundscale_pd() {
         let a = _mm_set1_pd(1.1);
         let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -3096,7 +3096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_scalef_pd() {
+    fn test_mm512_scalef_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_scalef_pd(a, b);
@@ -3105,7 +3105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_scalef_pd() {
+    fn test_mm512_mask_scalef_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_mask_scalef_pd(a, 0, a, b);
@@ -3116,7 +3116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_scalef_pd() {
+    fn test_mm512_maskz_scalef_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_maskz_scalef_pd(0, a, b);
@@ -3127,7 +3127,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_scalef_pd() {
+    fn test_mm256_scalef_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(3.);
         let r = _mm256_scalef_pd(a, b);
@@ -3136,7 +3136,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_scalef_pd() {
+    fn test_mm256_mask_scalef_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(3.);
         let r = _mm256_mask_scalef_pd(a, 0, a, b);
@@ -3147,7 +3147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_scalef_pd() {
+    fn test_mm256_maskz_scalef_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(3.);
         let r = _mm256_maskz_scalef_pd(0, a, b);
@@ -3158,7 +3158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_scalef_pd() {
+    fn test_mm_scalef_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_scalef_pd(a, b);
@@ -3167,7 +3167,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_scalef_pd() {
+    fn test_mm_mask_scalef_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_mask_scalef_pd(a, 0, a, b);
@@ -3178,7 +3178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_scalef_pd() {
+    fn test_mm_maskz_scalef_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(3.);
         let r = _mm_maskz_scalef_pd(0, a, b);
@@ -3189,7 +3189,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fixupimm_pd() {
+    fn test_mm512_fixupimm_pd() {
         let a = _mm512_set1_pd(f64::NAN);
         let b = _mm512_set1_pd(f64::MAX);
         let c = _mm512_set1_epi64(i32::MAX as i64);
@@ -3199,7 +3199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fixupimm_pd() {
+    fn test_mm512_mask_fixupimm_pd() {
         let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
         let b = _mm512_set1_pd(f64::MAX);
         let c = _mm512_set1_epi64(i32::MAX as i64);
@@ -3209,7 +3209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fixupimm_pd() {
+    fn test_mm512_maskz_fixupimm_pd() {
         let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
         let b = _mm512_set1_pd(f64::MAX);
         let c = _mm512_set1_epi64(i32::MAX as i64);
@@ -3219,7 +3219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_fixupimm_pd() {
+    fn test_mm256_fixupimm_pd() {
         let a = _mm256_set1_pd(f64::NAN);
         let b = _mm256_set1_pd(f64::MAX);
         let c = _mm256_set1_epi64x(i32::MAX as i64);
@@ -3229,7 +3229,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_fixupimm_pd() {
+    fn test_mm256_mask_fixupimm_pd() {
         let a = _mm256_set1_pd(f64::NAN);
         let b = _mm256_set1_pd(f64::MAX);
         let c = _mm256_set1_epi64x(i32::MAX as i64);
@@ -3239,7 +3239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_fixupimm_pd() {
+    fn test_mm256_maskz_fixupimm_pd() {
         let a = _mm256_set1_pd(f64::NAN);
         let b = _mm256_set1_pd(f64::MAX);
         let c = _mm256_set1_epi64x(i32::MAX as i64);
@@ -3249,7 +3249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_fixupimm_pd() {
+    fn test_mm_fixupimm_pd() {
         let a = _mm_set1_pd(f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -3259,7 +3259,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_fixupimm_pd() {
+    fn test_mm_mask_fixupimm_pd() {
         let a = _mm_set1_pd(f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -3269,7 +3269,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_fixupimm_pd() {
+    fn test_mm_maskz_fixupimm_pd() {
         let a = _mm_set1_pd(f64::NAN);
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
@@ -3279,7 +3279,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_ternarylogic_epi64() {
+    fn test_mm512_ternarylogic_epi64() {
         let a = _mm512_set1_epi64(1 << 2);
         let b = _mm512_set1_epi64(1 << 1);
         let c = _mm512_set1_epi64(1 << 0);
@@ -3289,7 +3289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_ternarylogic_epi64() {
+    fn test_mm512_mask_ternarylogic_epi64() {
         let src = _mm512_set1_epi64(1 << 2);
         let a = _mm512_set1_epi64(1 << 1);
         let b = _mm512_set1_epi64(1 << 0);
@@ -3301,7 +3301,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_ternarylogic_epi64() {
+    fn test_mm512_maskz_ternarylogic_epi64() {
         let a = _mm512_set1_epi64(1 << 2);
         let b = _mm512_set1_epi64(1 << 1);
         let c = _mm512_set1_epi64(1 << 0);
@@ -3313,7 +3313,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_ternarylogic_epi64() {
+    fn test_mm256_ternarylogic_epi64() {
         let a = _mm256_set1_epi64x(1 << 2);
         let b = _mm256_set1_epi64x(1 << 1);
         let c = _mm256_set1_epi64x(1 << 0);
@@ -3323,7 +3323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_ternarylogic_epi64() {
+    fn test_mm256_mask_ternarylogic_epi64() {
         let src = _mm256_set1_epi64x(1 << 2);
         let a = _mm256_set1_epi64x(1 << 1);
         let b = _mm256_set1_epi64x(1 << 0);
@@ -3335,7 +3335,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_ternarylogic_epi64() {
+    fn test_mm256_maskz_ternarylogic_epi64() {
         let a = _mm256_set1_epi64x(1 << 2);
         let b = _mm256_set1_epi64x(1 << 1);
         let c = _mm256_set1_epi64x(1 << 0);
@@ -3347,7 +3347,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_ternarylogic_epi64() {
+    fn test_mm_ternarylogic_epi64() {
         let a = _mm_set1_epi64x(1 << 2);
         let b = _mm_set1_epi64x(1 << 1);
         let c = _mm_set1_epi64x(1 << 0);
@@ -3357,7 +3357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_ternarylogic_epi64() {
+    fn test_mm_mask_ternarylogic_epi64() {
         let src = _mm_set1_epi64x(1 << 2);
         let a = _mm_set1_epi64x(1 << 1);
         let b = _mm_set1_epi64x(1 << 0);
@@ -3369,7 +3369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_ternarylogic_epi64() {
+    fn test_mm_maskz_ternarylogic_epi64() {
         let a = _mm_set1_epi64x(1 << 2);
         let b = _mm_set1_epi64x(1 << 1);
         let c = _mm_set1_epi64x(1 << 0);
@@ -3381,7 +3381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getmant_pd() {
+    fn test_mm512_getmant_pd() {
         let a = _mm512_set1_pd(10.);
         let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
         let e = _mm512_set1_pd(1.25);
@@ -3389,7 +3389,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getmant_pd() {
+    fn test_mm512_mask_getmant_pd() {
         let a = _mm512_set1_pd(10.);
         let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
         assert_eq_m512d(r, a);
@@ -3399,7 +3399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getmant_pd() {
+    fn test_mm512_maskz_getmant_pd() {
         let a = _mm512_set1_pd(10.);
         let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -3409,7 +3409,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_getmant_pd() {
+    fn test_mm256_getmant_pd() {
         let a = _mm256_set1_pd(10.);
         let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
         let e = _mm256_set1_pd(1.25);
@@ -3417,7 +3417,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_getmant_pd() {
+    fn test_mm256_mask_getmant_pd() {
         let a = _mm256_set1_pd(10.);
         let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
         assert_eq_m256d(r, a);
@@ -3427,7 +3427,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_getmant_pd() {
+    fn test_mm256_maskz_getmant_pd() {
         let a = _mm256_set1_pd(10.);
         let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -3437,7 +3437,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_getmant_pd() {
+    fn test_mm_getmant_pd() {
         let a = _mm_set1_pd(10.);
         let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
         let e = _mm_set1_pd(1.25);
@@ -3445,7 +3445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_getmant_pd() {
+    fn test_mm_mask_getmant_pd() {
         let a = _mm_set1_pd(10.);
         let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
         assert_eq_m128d(r, a);
@@ -3455,7 +3455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_getmant_pd() {
+    fn test_mm_maskz_getmant_pd() {
         let a = _mm_set1_pd(10.);
         let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -3465,7 +3465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtps_pd() {
+    fn test_mm512_cvtps_pd() {
         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvtps_pd(a);
         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
@@ -3473,7 +3473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtps_pd() {
+    fn test_mm512_mask_cvtps_pd() {
         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm512_set1_pd(0.);
         let r = _mm512_mask_cvtps_pd(src, 0, a);
@@ -3484,7 +3484,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtps_pd() {
+    fn test_mm512_maskz_cvtps_pd() {
         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvtps_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -3494,7 +3494,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtpslo_pd() {
+    fn test_mm512_cvtpslo_pd() {
         let v2 = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
         );
@@ -3504,7 +3504,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtpslo_pd() {
+    fn test_mm512_mask_cvtpslo_pd() {
         let v2 = _mm512_setr_ps(
             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
         );
@@ -3517,7 +3517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtpd_ps() {
+    fn test_mm512_cvtpd_ps() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvtpd_ps(a);
         let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
@@ -3525,7 +3525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtpd_ps() {
+    fn test_mm512_mask_cvtpd_ps() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_ps(0.);
         let r = _mm512_mask_cvtpd_ps(src, 0, a);
@@ -3536,7 +3536,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtpd_ps() {
+    fn test_mm512_maskz_cvtpd_ps() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvtpd_ps(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -3546,7 +3546,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpd_ps() {
+    fn test_mm256_mask_cvtpd_ps() {
         let a = _mm256_set_pd(4., -5.5, 6., -7.5);
         let src = _mm_set1_ps(0.);
         let r = _mm256_mask_cvtpd_ps(src, 0, a);
@@ -3557,7 +3557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpd_ps() {
+    fn test_mm256_maskz_cvtpd_ps() {
         let a = _mm256_set_pd(4., -5.5, 6., -7.5);
         let r = _mm256_maskz_cvtpd_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -3567,7 +3567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtpd_ps() {
+    fn test_mm_mask_cvtpd_ps() {
         let a = _mm_set_pd(6., -7.5);
         let src = _mm_set1_ps(0.);
         let r = _mm_mask_cvtpd_ps(src, 0, a);
@@ -3578,7 +3578,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpd_ps() {
+    fn test_mm_maskz_cvtpd_ps() {
         let a = _mm_set_pd(6., -7.5);
         let r = _mm_maskz_cvtpd_ps(0, a);
         assert_eq_m128(r, _mm_setzero_ps());
@@ -3588,7 +3588,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtpd_epi32() {
+    fn test_mm512_cvtpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvtpd_epi32(a);
         let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
@@ -3596,7 +3596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtpd_epi32() {
+    fn test_mm512_mask_cvtpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvtpd_epi32(src, 0, a);
@@ -3607,7 +3607,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtpd_epi32() {
+    fn test_mm512_maskz_cvtpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvtpd_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3617,7 +3617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpd_epi32() {
+    fn test_mm256_mask_cvtpd_epi32() {
         let a = _mm256_set_pd(4., -5.5, 6., -7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvtpd_epi32(src, 0, a);
@@ -3628,7 +3628,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpd_epi32() {
+    fn test_mm256_maskz_cvtpd_epi32() {
         let a = _mm256_set_pd(4., -5.5, 6., -7.5);
         let r = _mm256_maskz_cvtpd_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3638,7 +3638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtpd_epi32() {
+    fn test_mm_mask_cvtpd_epi32() {
         let a = _mm_set_pd(6., -7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtpd_epi32(src, 0, a);
@@ -3649,7 +3649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpd_epi32() {
+    fn test_mm_maskz_cvtpd_epi32() {
         let a = _mm_set_pd(6., -7.5);
         let r = _mm_maskz_cvtpd_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3659,7 +3659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtpd_epu32() {
+    fn test_mm512_cvtpd_epu32() {
         let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
         let r = _mm512_cvtpd_epu32(a);
         let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
@@ -3667,7 +3667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtpd_epu32() {
+    fn test_mm512_mask_cvtpd_epu32() {
         let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvtpd_epu32(src, 0, a);
@@ -3678,7 +3678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtpd_epu32() {
+    fn test_mm512_maskz_cvtpd_epu32() {
         let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
         let r = _mm512_maskz_cvtpd_epu32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3688,7 +3688,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtpd_epu32() {
+    fn test_mm256_cvtpd_epu32() {
         let a = _mm256_set_pd(4., 5.5, 6., 7.5);
         let r = _mm256_cvtpd_epu32(a);
         let e = _mm_set_epi32(4, 6, 6, 8);
@@ -3696,7 +3696,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtpd_epu32() {
+    fn test_mm256_mask_cvtpd_epu32() {
         let a = _mm256_set_pd(4., 5.5, 6., 7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvtpd_epu32(src, 0, a);
@@ -3707,7 +3707,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtpd_epu32() {
+    fn test_mm256_maskz_cvtpd_epu32() {
         let a = _mm256_set_pd(4., 5.5, 6., 7.5);
         let r = _mm256_maskz_cvtpd_epu32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3717,7 +3717,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtpd_epu32() {
+    fn test_mm_cvtpd_epu32() {
         let a = _mm_set_pd(6., 7.5);
         let r = _mm_cvtpd_epu32(a);
         let e = _mm_set_epi32(0, 0, 6, 8);
@@ -3725,7 +3725,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtpd_epu32() {
+    fn test_mm_mask_cvtpd_epu32() {
         let a = _mm_set_pd(6., 7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtpd_epu32(src, 0, a);
@@ -3736,7 +3736,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtpd_epu32() {
+    fn test_mm_maskz_cvtpd_epu32() {
         let a = _mm_set_pd(6., 7.5);
         let r = _mm_maskz_cvtpd_epu32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3746,7 +3746,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtpd_pslo() {
+    fn test_mm512_cvtpd_pslo() {
         let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvtpd_pslo(v2);
         let e = _mm512_setr_ps(
@@ -3756,7 +3756,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtpd_pslo() {
+    fn test_mm512_mask_cvtpd_pslo() {
         let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm512_set1_ps(0.);
         let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
@@ -3769,7 +3769,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi8_epi64() {
+    const fn test_mm512_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi8_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3777,7 +3777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi8_epi64() {
+    const fn test_mm512_mask_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
@@ -3788,7 +3788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi8_epi64() {
+    const fn test_mm512_maskz_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi8_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -3798,7 +3798,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi8_epi64() {
+    const fn test_mm256_mask_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
@@ -3809,7 +3809,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi8_epi64() {
+    const fn test_mm256_maskz_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi8_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3819,7 +3819,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi8_epi64() {
+    const fn test_mm_mask_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepi8_epi64(src, 0, a);
@@ -3830,7 +3830,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi8_epi64() {
+    const fn test_mm_maskz_cvtepi8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepi8_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3840,7 +3840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu8_epi64() {
+    const fn test_mm512_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu8_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3848,7 +3848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu8_epi64() {
+    const fn test_mm512_mask_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
@@ -3859,7 +3859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu8_epi64() {
+    const fn test_mm512_maskz_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu8_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -3869,7 +3869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu8_epi64() {
+    const fn test_mm256_mask_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
@@ -3880,7 +3880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu8_epi64() {
+    const fn test_mm256_maskz_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu8_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3890,7 +3890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu8_epi64() {
+    const fn test_mm_mask_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepu8_epi64(src, 0, a);
@@ -3901,7 +3901,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu8_epi64() {
+    const fn test_mm_maskz_cvtepu8_epi64() {
         let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu8_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3911,7 +3911,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi16_epi64() {
+    const fn test_mm512_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi16_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3919,7 +3919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi16_epi64() {
+    const fn test_mm512_mask_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
@@ -3930,7 +3930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi16_epi64() {
+    const fn test_mm512_maskz_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi16_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -3940,7 +3940,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi16_epi64() {
+    const fn test_mm256_mask_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
@@ -3951,7 +3951,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi16_epi64() {
+    const fn test_mm256_maskz_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi16_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -3961,7 +3961,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi16_epi64() {
+    const fn test_mm_mask_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepi16_epi64(src, 0, a);
@@ -3972,7 +3972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi16_epi64() {
+    const fn test_mm_maskz_cvtepi16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepi16_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -3982,7 +3982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu16_epi64() {
+    const fn test_mm512_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu16_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -3990,7 +3990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu16_epi64() {
+    const fn test_mm512_mask_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
@@ -4001,7 +4001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu16_epi64() {
+    const fn test_mm512_maskz_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu16_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -4011,7 +4011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu16_epi64() {
+    const fn test_mm256_mask_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
@@ -4022,7 +4022,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu16_epi64() {
+    const fn test_mm256_maskz_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu16_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4032,7 +4032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu16_epi64() {
+    const fn test_mm_mask_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepu16_epi64(src, 0, a);
@@ -4043,7 +4043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu16_epi64() {
+    const fn test_mm_maskz_cvtepu16_epi64() {
         let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm_maskz_cvtepu16_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4053,7 +4053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi32_epi64() {
+    const fn test_mm512_cvtepi32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4061,7 +4061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi32_epi64() {
+    const fn test_mm512_mask_cvtepi32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
@@ -4072,7 +4072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi32_epi64() {
+    const fn test_mm512_maskz_cvtepi32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -4082,7 +4082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi32_epi64() {
+    const fn test_mm256_mask_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
@@ -4093,7 +4093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi32_epi64() {
+    const fn test_mm256_maskz_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let r = _mm256_maskz_cvtepi32_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4103,7 +4103,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi32_epi64() {
+    const fn test_mm_mask_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let src = _mm_set1_epi64x(0);
         let r = _mm_mask_cvtepi32_epi64(src, 0, a);
@@ -4114,7 +4114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi32_epi64() {
+    const fn test_mm_maskz_cvtepi32_epi64() {
         let a = _mm_set_epi32(8, 9, 10, 11);
         let r = _mm_maskz_cvtepi32_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4124,7 +4124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu32_epi64() {
+    const fn test_mm512_cvtepu32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32_epi64(a);
         let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4132,7 +4132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu32_epi64() {
+    const fn test_mm512_mask_cvtepu32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_epi64(-1);
         let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
@@ -4143,7 +4143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu32_epi64() {
+    const fn test_mm512_maskz_cvtepu32_epi64() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu32_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -4153,7 +4153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu32_epi64() {
+    const fn test_mm256_mask_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm256_set1_epi64x(-1);
         let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
@@ -4164,7 +4164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu32_epi64() {
+    const fn test_mm256_maskz_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu32_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4174,7 +4174,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu32_epi64() {
+    const fn test_mm_mask_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm_set1_epi64x(-1);
         let r = _mm_mask_cvtepu32_epi64(src, 0, a);
@@ -4185,7 +4185,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu32_epi64() {
+    const fn test_mm_maskz_cvtepu32_epi64() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_maskz_cvtepu32_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4195,7 +4195,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi32_pd() {
+    const fn test_mm512_cvtepi32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4203,7 +4203,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi32_pd() {
+    const fn test_mm512_mask_cvtepi32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepi32_pd(src, 0, a);
@@ -4214,7 +4214,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi32_pd() {
+    const fn test_mm512_maskz_cvtepi32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi32_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -4224,7 +4224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi32_pd() {
+    const fn test_mm256_mask_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm256_set1_pd(-1.);
         let r = _mm256_mask_cvtepi32_pd(src, 0, a);
@@ -4235,7 +4235,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi32_pd() {
+    const fn test_mm256_maskz_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi32_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -4245,7 +4245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepi32_pd() {
+    const fn test_mm_mask_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm_set1_pd(-1.);
         let r = _mm_mask_cvtepi32_pd(src, 0, a);
@@ -4256,7 +4256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepi32_pd() {
+    const fn test_mm_maskz_cvtepi32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_maskz_cvtepi32_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -4266,7 +4266,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu32_pd() {
+    const fn test_mm512_cvtepu32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4274,7 +4274,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu32_pd() {
+    const fn test_mm512_mask_cvtepu32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepu32_pd(src, 0, a);
@@ -4285,7 +4285,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepu32_pd() {
+    const fn test_mm512_maskz_cvtepu32_pd() {
         let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepu32_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -4295,7 +4295,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cvtepu32_pd() {
+    const fn test_mm256_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_cvtepu32_pd(a);
         let e = _mm256_set_pd(12., 13., 14., 15.);
@@ -4303,7 +4303,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepu32_pd() {
+    const fn test_mm256_mask_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm256_set1_pd(-1.);
         let r = _mm256_mask_cvtepu32_pd(src, 0, a);
@@ -4314,7 +4314,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepu32_pd() {
+    const fn test_mm256_maskz_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepu32_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -4324,7 +4324,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cvtepu32_pd() {
+    const fn test_mm_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_cvtepu32_pd(a);
         let e = _mm_set_pd(14., 15.);
@@ -4332,7 +4332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cvtepu32_pd() {
+    const fn test_mm_mask_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let src = _mm_set1_pd(-1.);
         let r = _mm_mask_cvtepu32_pd(src, 0, a);
@@ -4343,7 +4343,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_cvtepu32_pd() {
+    const fn test_mm_maskz_cvtepu32_pd() {
         let a = _mm_set_epi32(12, 13, 14, 15);
         let r = _mm_maskz_cvtepu32_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -4353,7 +4353,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi32lo_pd() {
+    const fn test_mm512_cvtepi32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi32lo_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4361,7 +4361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi32lo_pd() {
+    const fn test_mm512_mask_cvtepi32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
@@ -4372,7 +4372,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepu32lo_pd() {
+    const fn test_mm512_cvtepu32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepu32lo_pd(a);
         let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
@@ -4380,7 +4380,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepu32lo_pd() {
+    const fn test_mm512_mask_cvtepu32lo_pd() {
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm512_set1_pd(-1.);
         let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
@@ -4391,7 +4391,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi64_epi32() {
+    const fn test_mm512_cvtepi64_epi32() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi64_epi32(a);
         let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4399,7 +4399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi64_epi32() {
+    const fn test_mm512_mask_cvtepi64_epi32() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm256_set1_epi32(-1);
         let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
@@ -4410,7 +4410,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi64_epi32() {
+    const fn test_mm512_maskz_cvtepi64_epi32() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi64_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4420,7 +4420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cvtepi64_epi32() {
+    const fn test_mm256_cvtepi64_epi32() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_cvtepi64_epi32(a);
         let e = _mm_set_epi32(1, 2, 3, 4);
@@ -4428,7 +4428,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cvtepi64_epi32() {
+    const fn test_mm256_mask_cvtepi64_epi32() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
@@ -4439,7 +4439,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_cvtepi64_epi32() {
+    const fn test_mm256_maskz_cvtepi64_epi32() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let r = _mm256_maskz_cvtepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4449,7 +4449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtepi64_epi32() {
+    fn test_mm_cvtepi64_epi32() {
         let a = _mm_set_epi64x(3, 4);
         let r = _mm_cvtepi64_epi32(a);
         let e = _mm_set_epi32(0, 0, 3, 4);
@@ -4457,7 +4457,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_epi32() {
+    fn test_mm_mask_cvtepi64_epi32() {
         let a = _mm_set_epi64x(3, 4);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtepi64_epi32(src, 0, a);
@@ -4468,7 +4468,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi64_epi32() {
+    fn test_mm_maskz_cvtepi64_epi32() {
         let a = _mm_set_epi64x(3, 4);
         let r = _mm_maskz_cvtepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4478,7 +4478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cvtepi64_epi16() {
+    const fn test_mm512_cvtepi64_epi16() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi64_epi16(a);
         let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
@@ -4486,7 +4486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cvtepi64_epi16() {
+    const fn test_mm512_mask_cvtepi64_epi16() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set1_epi16(-1);
         let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
@@ -4497,7 +4497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_cvtepi64_epi16() {
+    const fn test_mm512_maskz_cvtepi64_epi16() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4507,7 +4507,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtepi64_epi16() {
+    fn test_mm256_cvtepi64_epi16() {
         let a = _mm256_set_epi64x(12, 13, 14, 15);
         let r = _mm256_cvtepi64_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
@@ -4515,7 +4515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_epi16() {
+    fn test_mm256_mask_cvtepi64_epi16() {
         let a = _mm256_set_epi64x(12, 13, 14, 15);
         let src = _mm_set1_epi16(0);
         let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
@@ -4526,7 +4526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi64_epi16() {
+    fn test_mm256_maskz_cvtepi64_epi16() {
         let a = _mm256_set_epi64x(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4536,7 +4536,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtepi64_epi16() {
+    fn test_mm_cvtepi64_epi16() {
         let a = _mm_set_epi64x(14, 15);
         let r = _mm_cvtepi64_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
@@ -4544,7 +4544,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_epi16() {
+    fn test_mm_mask_cvtepi64_epi16() {
         let a = _mm_set_epi64x(14, 15);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtepi64_epi16(src, 0, a);
@@ -4555,7 +4555,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi64_epi16() {
+    fn test_mm_maskz_cvtepi64_epi16() {
         let a = _mm_set_epi64x(14, 15);
         let r = _mm_maskz_cvtepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4565,7 +4565,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtepi64_epi8() {
+    fn test_mm512_cvtepi64_epi8() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_cvtepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -4573,7 +4573,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_epi8() {
+    fn test_mm512_mask_cvtepi64_epi8() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
@@ -4584,7 +4584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtepi64_epi8() {
+    fn test_mm512_maskz_cvtepi64_epi8() {
         let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_maskz_cvtepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4594,7 +4594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtepi64_epi8() {
+    fn test_mm256_cvtepi64_epi8() {
         let a = _mm256_set_epi64x(12, 13, 14, 15);
         let r = _mm256_cvtepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
@@ -4602,7 +4602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_epi8() {
+    fn test_mm256_mask_cvtepi64_epi8() {
         let a = _mm256_set_epi64x(12, 13, 14, 15);
         let src = _mm_set1_epi8(0);
         let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
@@ -4613,7 +4613,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtepi64_epi8() {
+    fn test_mm256_maskz_cvtepi64_epi8() {
         let a = _mm256_set_epi64x(12, 13, 14, 15);
         let r = _mm256_maskz_cvtepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4623,7 +4623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtepi64_epi8() {
+    fn test_mm_cvtepi64_epi8() {
         let a = _mm_set_epi64x(14, 15);
         let r = _mm_cvtepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
@@ -4631,7 +4631,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_epi8() {
+    fn test_mm_mask_cvtepi64_epi8() {
         let a = _mm_set_epi64x(14, 15);
         let src = _mm_set1_epi8(0);
         let r = _mm_mask_cvtepi64_epi8(src, 0, a);
@@ -4642,7 +4642,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtepi64_epi8() {
+    fn test_mm_maskz_cvtepi64_epi8() {
         let a = _mm_set_epi64x(14, 15);
         let r = _mm_maskz_cvtepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4652,7 +4652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsepi64_epi32() {
+    fn test_mm512_cvtsepi64_epi32() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let r = _mm512_cvtsepi64_epi32(a);
         let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
@@ -4660,7 +4660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_epi32() {
+    fn test_mm512_mask_cvtsepi64_epi32() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let src = _mm256_set1_epi32(-1);
         let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
@@ -4671,7 +4671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
+    fn test_mm512_maskz_cvtsepi64_epi32() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let r = _mm512_maskz_cvtsepi64_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4681,7 +4681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtsepi64_epi32() {
+    fn test_mm256_cvtsepi64_epi32() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let r = _mm256_cvtsepi64_epi32(a);
         let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
@@ -4689,7 +4689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_epi32() {
+    fn test_mm256_mask_cvtsepi64_epi32() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let src = _mm_set1_epi32(-1);
         let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
@@ -4700,7 +4700,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
+    fn test_mm256_maskz_cvtsepi64_epi32() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let r = _mm256_maskz_cvtsepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4710,7 +4710,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtsepi64_epi32() {
+    fn test_mm_cvtsepi64_epi32() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let r = _mm_cvtsepi64_epi32(a);
         let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
@@ -4718,7 +4718,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_epi32() {
+    fn test_mm_mask_cvtsepi64_epi32() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
@@ -4729,7 +4729,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsepi64_epi32() {
+    fn test_mm_maskz_cvtsepi64_epi32() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let r = _mm_maskz_cvtsepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4739,7 +4739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsepi64_epi16() {
+    fn test_mm512_cvtsepi64_epi16() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let r = _mm512_cvtsepi64_epi16(a);
         let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
@@ -4747,7 +4747,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_epi16() {
+    fn test_mm512_mask_cvtsepi64_epi16() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let src = _mm_set1_epi16(-1);
         let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
@@ -4758,7 +4758,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
+    fn test_mm512_maskz_cvtsepi64_epi16() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let r = _mm512_maskz_cvtsepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4768,7 +4768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtsepi64_epi16() {
+    fn test_mm256_cvtsepi64_epi16() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let r = _mm256_cvtsepi64_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
@@ -4776,7 +4776,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_epi16() {
+    fn test_mm256_mask_cvtsepi64_epi16() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let src = _mm_set1_epi16(0);
         let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
@@ -4787,7 +4787,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
+    fn test_mm256_maskz_cvtsepi64_epi16() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let r = _mm256_maskz_cvtsepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4797,7 +4797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtsepi64_epi16() {
+    fn test_mm_cvtsepi64_epi16() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let r = _mm_cvtsepi64_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
@@ -4805,7 +4805,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_epi16() {
+    fn test_mm_mask_cvtsepi64_epi16() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
@@ -4816,7 +4816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsepi64_epi16() {
+    fn test_mm_maskz_cvtsepi64_epi16() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let r = _mm_maskz_cvtsepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4826,7 +4826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtsepi64_epi8() {
+    fn test_mm512_cvtsepi64_epi8() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let r = _mm512_cvtsepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
@@ -4834,7 +4834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_epi8() {
+    fn test_mm512_mask_cvtsepi64_epi8() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
@@ -4851,7 +4851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
+    fn test_mm512_maskz_cvtsepi64_epi8() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
         let r = _mm512_maskz_cvtsepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4861,7 +4861,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtsepi64_epi8() {
+    fn test_mm256_cvtsepi64_epi8() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let r = _mm256_cvtsepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
@@ -4869,7 +4869,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_epi8() {
+    fn test_mm256_mask_cvtsepi64_epi8() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let src = _mm_set1_epi8(0);
         let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
@@ -4880,7 +4880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
+    fn test_mm256_maskz_cvtsepi64_epi8() {
         let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
         let r = _mm256_maskz_cvtsepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4890,7 +4890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtsepi64_epi8() {
+    fn test_mm_cvtsepi64_epi8() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let r = _mm_cvtsepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
@@ -4898,7 +4898,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_epi8() {
+    fn test_mm_mask_cvtsepi64_epi8() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let src = _mm_set1_epi8(0);
         let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
@@ -4909,7 +4909,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtsepi64_epi8() {
+    fn test_mm_maskz_cvtsepi64_epi8() {
         let a = _mm_set_epi64x(i64::MIN, i64::MAX);
         let r = _mm_maskz_cvtsepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4919,7 +4919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtusepi64_epi32() {
+    fn test_mm512_cvtusepi64_epi32() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let r = _mm512_cvtusepi64_epi32(a);
         let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
@@ -4927,7 +4927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_epi32() {
+    fn test_mm512_mask_cvtusepi64_epi32() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let src = _mm256_set1_epi32(-1);
         let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
@@ -4938,7 +4938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
+    fn test_mm512_maskz_cvtusepi64_epi32() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let r = _mm512_maskz_cvtusepi64_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -4948,7 +4948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtusepi64_epi32() {
+    fn test_mm256_cvtusepi64_epi32() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let r = _mm256_cvtusepi64_epi32(a);
         let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
@@ -4956,7 +4956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_epi32() {
+    fn test_mm256_mask_cvtusepi64_epi32() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
@@ -4967,7 +4967,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
+    fn test_mm256_maskz_cvtusepi64_epi32() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let r = _mm256_maskz_cvtusepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -4977,7 +4977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtusepi64_epi32() {
+    fn test_mm_cvtusepi64_epi32() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let r = _mm_cvtusepi64_epi32(a);
         let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
@@ -4985,7 +4985,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_epi32() {
+    fn test_mm_mask_cvtusepi64_epi32() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
@@ -4996,7 +4996,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtusepi64_epi32() {
+    fn test_mm_maskz_cvtusepi64_epi32() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let r = _mm_maskz_cvtusepi64_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5006,7 +5006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtusepi64_epi16() {
+    fn test_mm512_cvtusepi64_epi16() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let r = _mm512_cvtusepi64_epi16(a);
         let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
@@ -5014,7 +5014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_epi16() {
+    fn test_mm512_mask_cvtusepi64_epi16() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let src = _mm_set1_epi16(-1);
         let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
@@ -5025,7 +5025,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
+    fn test_mm512_maskz_cvtusepi64_epi16() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let r = _mm512_maskz_cvtusepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5035,7 +5035,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtusepi64_epi16() {
+    fn test_mm256_cvtusepi64_epi16() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let r = _mm256_cvtusepi64_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
@@ -5043,7 +5043,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_epi16() {
+    fn test_mm256_mask_cvtusepi64_epi16() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let src = _mm_set1_epi16(0);
         let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
@@ -5054,7 +5054,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
+    fn test_mm256_maskz_cvtusepi64_epi16() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let r = _mm256_maskz_cvtusepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5064,7 +5064,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtusepi64_epi16() {
+    fn test_mm_cvtusepi64_epi16() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let r = _mm_cvtusepi64_epi16(a);
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
@@ -5072,7 +5072,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_epi16() {
+    fn test_mm_mask_cvtusepi64_epi16() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let src = _mm_set1_epi16(0);
         let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
@@ -5083,7 +5083,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtusepi64_epi16() {
+    fn test_mm_maskz_cvtusepi64_epi16() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let r = _mm_maskz_cvtusepi64_epi16(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5093,7 +5093,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtusepi64_epi8() {
+    fn test_mm512_cvtusepi64_epi8() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let r = _mm512_cvtusepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
@@ -5101,7 +5101,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_epi8() {
+    fn test_mm512_mask_cvtusepi64_epi8() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
@@ -5112,7 +5112,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
+    fn test_mm512_maskz_cvtusepi64_epi8() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
         let r = _mm512_maskz_cvtusepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5122,7 +5122,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvtusepi64_epi8() {
+    fn test_mm256_cvtusepi64_epi8() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let r = _mm256_cvtusepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
@@ -5130,7 +5130,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_epi8() {
+    fn test_mm256_mask_cvtusepi64_epi8() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let src = _mm_set1_epi8(0);
         let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
@@ -5141,7 +5141,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
+    fn test_mm256_maskz_cvtusepi64_epi8() {
         let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
         let r = _mm256_maskz_cvtusepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5151,7 +5151,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvtusepi64_epi8() {
+    fn test_mm_cvtusepi64_epi8() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let r = _mm_cvtusepi64_epi8(a);
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
@@ -5159,7 +5159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_epi8() {
+    fn test_mm_mask_cvtusepi64_epi8() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let src = _mm_set1_epi8(0);
         let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
@@ -5170,7 +5170,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvtusepi64_epi8() {
+    fn test_mm_maskz_cvtusepi64_epi8() {
         let a = _mm_set_epi64x(6, i64::MAX);
         let r = _mm_maskz_cvtusepi64_epi8(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5180,7 +5180,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtt_roundpd_epi32() {
+    fn test_mm512_cvtt_roundpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
         let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
@@ -5188,7 +5188,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
+    fn test_mm512_mask_cvtt_roundpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -5199,7 +5199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
+    fn test_mm512_maskz_cvtt_roundpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -5209,7 +5209,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvtt_roundpd_epu32() {
+    fn test_mm512_cvtt_roundpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
         let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
@@ -5217,7 +5217,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
+    fn test_mm512_mask_cvtt_roundpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
@@ -5228,7 +5228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
+    fn test_mm512_maskz_cvtt_roundpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -5238,7 +5238,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvttpd_epi32() {
+    fn test_mm512_cvttpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvttpd_epi32(a);
         let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
@@ -5246,7 +5246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvttpd_epi32() {
+    fn test_mm512_mask_cvttpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvttpd_epi32(src, 0, a);
@@ -5257,7 +5257,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvttpd_epi32() {
+    fn test_mm512_maskz_cvttpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvttpd_epi32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -5267,7 +5267,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvttpd_epi32() {
+    fn test_mm256_mask_cvttpd_epi32() {
         let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvttpd_epi32(src, 0, a);
@@ -5278,7 +5278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttpd_epi32() {
+    fn test_mm256_maskz_cvttpd_epi32() {
         let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
         let r = _mm256_maskz_cvttpd_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5288,7 +5288,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvttpd_epi32() {
+    fn test_mm_mask_cvttpd_epi32() {
         let a = _mm_set_pd(6., -7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvttpd_epi32(src, 0, a);
@@ -5299,7 +5299,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvttpd_epi32() {
+    fn test_mm_maskz_cvttpd_epi32() {
         let a = _mm_set_pd(6., -7.5);
         let r = _mm_maskz_cvttpd_epi32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5309,7 +5309,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvttpd_epu32() {
+    fn test_mm512_cvttpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvttpd_epu32(a);
         let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
@@ -5317,7 +5317,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvttpd_epu32() {
+    fn test_mm512_mask_cvttpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvttpd_epu32(src, 0, a);
@@ -5328,7 +5328,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvttpd_epu32() {
+    fn test_mm512_maskz_cvttpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvttpd_epu32(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -5338,7 +5338,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cvttpd_epu32() {
+    fn test_mm256_cvttpd_epu32() {
         let a = _mm256_set_pd(4., 5.5, 6., 7.5);
         let r = _mm256_cvttpd_epu32(a);
         let e = _mm_set_epi32(4, 5, 6, 7);
@@ -5346,7 +5346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvttpd_epu32() {
+    fn test_mm256_mask_cvttpd_epu32() {
         let a = _mm256_set_pd(4., 5.5, 6., 7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm256_mask_cvttpd_epu32(src, 0, a);
@@ -5357,7 +5357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_cvttpd_epu32() {
+    fn test_mm256_maskz_cvttpd_epu32() {
         let a = _mm256_set_pd(4., 5.5, 6., 7.5);
         let r = _mm256_maskz_cvttpd_epu32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5367,7 +5367,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cvttpd_epu32() {
+    fn test_mm_cvttpd_epu32() {
         let a = _mm_set_pd(6., 7.5);
         let r = _mm_cvttpd_epu32(a);
         let e = _mm_set_epi32(0, 0, 6, 7);
@@ -5375,7 +5375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvttpd_epu32() {
+    fn test_mm_mask_cvttpd_epu32() {
         let a = _mm_set_pd(6., 7.5);
         let src = _mm_set1_epi32(0);
         let r = _mm_mask_cvttpd_epu32(src, 0, a);
@@ -5386,7 +5386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_cvttpd_epu32() {
+    fn test_mm_maskz_cvttpd_epu32() {
         let a = _mm_set_pd(6., 7.5);
         let r = _mm_maskz_cvttpd_epu32(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -5396,7 +5396,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_add_round_pd() {
+    fn test_mm512_add_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
         let b = _mm512_set1_pd(-1.);
         let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -5408,7 +5408,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_add_round_pd() {
+    fn test_mm512_mask_add_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
         let b = _mm512_set1_pd(-1.);
         let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -5423,7 +5423,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_add_round_pd() {
+    fn test_mm512_maskz_add_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
         let b = _mm512_set1_pd(-1.);
         let r =
@@ -5437,7 +5437,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sub_round_pd() {
+    fn test_mm512_sub_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -5449,7 +5449,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sub_round_pd() {
+    fn test_mm512_mask_sub_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -5464,7 +5464,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sub_round_pd() {
+    fn test_mm512_maskz_sub_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let r =
@@ -5478,7 +5478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mul_round_pd() {
+    fn test_mm512_mul_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
         let b = _mm512_set1_pd(0.1);
         let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -5499,7 +5499,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_mul_round_pd() {
+    fn test_mm512_mask_mul_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
         let b = _mm512_set1_pd(0.1);
         let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -5523,7 +5523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_mul_round_pd() {
+    fn test_mm512_maskz_mul_round_pd() {
         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
         let b = _mm512_set1_pd(0.1);
         let r =
@@ -5546,7 +5546,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_div_round_pd() {
+    fn test_mm512_div_round_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -5558,7 +5558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_div_round_pd() {
+    fn test_mm512_mask_div_round_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -5582,7 +5582,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_div_round_pd() {
+    fn test_mm512_maskz_div_round_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r =
@@ -5605,7 +5605,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sqrt_round_pd() {
+    fn test_mm512_sqrt_round_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         let e = _mm512_set1_pd(1.7320508075688772);
@@ -5616,7 +5616,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sqrt_round_pd() {
+    fn test_mm512_mask_sqrt_round_pd() {
         let a = _mm512_set1_pd(3.);
         let r =
             _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
@@ -5638,7 +5638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sqrt_round_pd() {
+    fn test_mm512_maskz_sqrt_round_pd() {
         let a = _mm512_set1_pd(3.);
         let r =
             _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
@@ -5660,7 +5660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmadd_round_pd() {
+    fn test_mm512_fmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5673,7 +5673,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmadd_round_pd() {
+    fn test_mm512_mask_fmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5698,7 +5698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmadd_round_pd() {
+    fn test_mm512_maskz_fmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5714,7 +5714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmadd_round_pd() {
+    fn test_mm512_mask3_fmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5730,7 +5730,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsub_round_pd() {
+    fn test_mm512_fmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -5743,7 +5743,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsub_round_pd() {
+    fn test_mm512_mask_fmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -5768,7 +5768,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsub_round_pd() {
+    fn test_mm512_maskz_fmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -5784,7 +5784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsub_round_pd() {
+    fn test_mm512_mask3_fmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -5800,7 +5800,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmaddsub_round_pd() {
+    fn test_mm512_fmaddsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5823,7 +5823,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmaddsub_round_pd() {
+    fn test_mm512_mask_fmaddsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5848,7 +5848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
+    fn test_mm512_maskz_fmaddsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5864,7 +5864,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
+    fn test_mm512_mask3_fmaddsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5880,7 +5880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fmsubadd_round_pd() {
+    fn test_mm512_fmsubadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5903,7 +5903,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fmsubadd_round_pd() {
+    fn test_mm512_mask_fmsubadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5928,7 +5928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
+    fn test_mm512_maskz_fmsubadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5944,7 +5944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
+    fn test_mm512_mask3_fmsubadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -5960,7 +5960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmadd_round_pd() {
+    fn test_mm512_fnmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -5974,7 +5974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmadd_round_pd() {
+    fn test_mm512_mask_fnmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -5999,7 +5999,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmadd_round_pd() {
+    fn test_mm512_maskz_fnmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -6015,7 +6015,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmadd_round_pd() {
+    fn test_mm512_mask3_fnmadd_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(1.);
@@ -6031,7 +6031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fnmsub_round_pd() {
+    fn test_mm512_fnmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -6045,7 +6045,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fnmsub_round_pd() {
+    fn test_mm512_mask_fnmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -6070,7 +6070,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fnmsub_round_pd() {
+    fn test_mm512_maskz_fnmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -6086,7 +6086,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask3_fnmsub_round_pd() {
+    fn test_mm512_mask3_fnmsub_round_pd() {
         let a = _mm512_set1_pd(0.000000000000000007);
         let b = _mm512_set1_pd(1.);
         let c = _mm512_set1_pd(-1.);
@@ -6102,7 +6102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_max_round_pd() {
+    fn test_mm512_max_round_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -6111,7 +6111,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_max_round_pd() {
+    fn test_mm512_mask_max_round_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -6122,7 +6122,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_max_round_pd() {
+    fn test_mm512_maskz_max_round_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -6133,7 +6133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_min_round_pd() {
+    fn test_mm512_min_round_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
@@ -6142,7 +6142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_min_round_pd() {
+    fn test_mm512_mask_min_round_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
@@ -6153,7 +6153,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_min_round_pd() {
+    fn test_mm512_maskz_min_round_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
         let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
@@ -6164,7 +6164,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getexp_round_pd() {
+    fn test_mm512_getexp_round_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm512_set1_pd(1.);
@@ -6172,7 +6172,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getexp_round_pd() {
+    fn test_mm512_mask_getexp_round_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
         assert_eq_m512d(r, a);
@@ -6182,7 +6182,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getexp_round_pd() {
+    fn test_mm512_maskz_getexp_round_pd() {
         let a = _mm512_set1_pd(3.);
         let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -6192,7 +6192,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_roundscale_round_pd() {
+    fn test_mm512_roundscale_round_pd() {
         let a = _mm512_set1_pd(1.1);
         let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm512_set1_pd(1.0);
@@ -6200,7 +6200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_roundscale_round_pd() {
+    fn test_mm512_mask_roundscale_round_pd() {
         let a = _mm512_set1_pd(1.1);
         let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
         let e = _mm512_set1_pd(1.1);
@@ -6211,7 +6211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_roundscale_round_pd() {
+    fn test_mm512_maskz_roundscale_round_pd() {
         let a = _mm512_set1_pd(1.1);
         let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -6221,7 +6221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_scalef_round_pd() {
+    fn test_mm512_scalef_round_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
@@ -6230,7 +6230,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_scalef_round_pd() {
+    fn test_mm512_mask_scalef_round_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -6245,7 +6245,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_scalef_round_pd() {
+    fn test_mm512_maskz_scalef_round_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(3.);
         let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
@@ -6260,7 +6260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_fixupimm_round_pd() {
+    fn test_mm512_fixupimm_round_pd() {
         let a = _mm512_set1_pd(f64::NAN);
         let b = _mm512_set1_pd(f64::MAX);
         let c = _mm512_set1_epi64(i32::MAX as i64);
@@ -6270,7 +6270,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_fixupimm_round_pd() {
+    fn test_mm512_mask_fixupimm_round_pd() {
         let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
         let b = _mm512_set1_pd(f64::MAX);
         let c = _mm512_set1_epi64(i32::MAX as i64);
@@ -6280,7 +6280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_fixupimm_round_pd() {
+    fn test_mm512_maskz_fixupimm_round_pd() {
         let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
         let b = _mm512_set1_pd(f64::MAX);
         let c = _mm512_set1_epi64(i32::MAX as i64);
@@ -6290,7 +6290,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_getmant_round_pd() {
+    fn test_mm512_getmant_round_pd() {
         let a = _mm512_set1_pd(10.);
         let r = _mm512_getmant_round_pd::<
             _MM_MANT_NORM_1_2,
@@ -6302,7 +6302,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_getmant_round_pd() {
+    fn test_mm512_mask_getmant_round_pd() {
         let a = _mm512_set1_pd(10.);
         let r = _mm512_mask_getmant_round_pd::<
             _MM_MANT_NORM_1_2,
@@ -6320,7 +6320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_getmant_round_pd() {
+    fn test_mm512_maskz_getmant_round_pd() {
         let a = _mm512_set1_pd(10.);
         let r = _mm512_maskz_getmant_round_pd::<
             _MM_MANT_NORM_1_2,
@@ -6338,7 +6338,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundps_pd() {
+    fn test_mm512_cvt_roundps_pd() {
         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
@@ -6346,7 +6346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundps_pd() {
+    fn test_mm512_mask_cvt_roundps_pd() {
         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm512_set1_pd(0.);
         let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
@@ -6357,7 +6357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundps_pd() {
+    fn test_mm512_maskz_cvt_roundps_pd() {
         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -6367,7 +6367,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundpd_ps() {
+    fn test_mm512_cvt_roundpd_ps() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
@@ -6375,7 +6375,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundpd_ps() {
+    fn test_mm512_mask_cvt_roundpd_ps() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_ps(0.);
         let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
@@ -6386,7 +6386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
+    fn test_mm512_maskz_cvt_roundpd_ps() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m256(r, _mm256_setzero_ps());
@@ -6396,7 +6396,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundpd_epi32() {
+    fn test_mm512_cvt_roundpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
@@ -6404,7 +6404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
+    fn test_mm512_mask_cvt_roundpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
@@ -6415,7 +6415,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
+    fn test_mm512_maskz_cvt_roundpd_epi32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -6425,7 +6425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cvt_roundpd_epu32() {
+    fn test_mm512_cvt_roundpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
         let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
@@ -6433,7 +6433,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
+    fn test_mm512_mask_cvt_roundpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let src = _mm256_set1_epi32(0);
         let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
@@ -6444,7 +6444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
+    fn test_mm512_maskz_cvt_roundpd_epu32() {
         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
         let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -6454,48 +6454,48 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setzero_pd() {
+    const fn test_mm512_setzero_pd() {
         assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set1_epi64() {
+    const fn test_mm512_set1_epi64() {
         let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
         assert_eq_m512i(r, _mm512_set1_epi64(2));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set1_pd() {
+    const fn test_mm512_set1_pd() {
         let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
         assert_eq_m512d(expected, _mm512_set1_pd(2.));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set4_epi64() {
+    const fn test_mm512_set4_epi64() {
         let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set4_pd() {
+    const fn test_mm512_set4_pd() {
         let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
         assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr4_epi64() {
+    const fn test_mm512_setr4_epi64() {
         let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
         assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr4_pd() {
+    const fn test_mm512_setr4_pd() {
         let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
         assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmplt_pd_mask() {
+    fn test_mm512_cmplt_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6504,7 +6504,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmplt_pd_mask() {
+    fn test_mm512_mask_cmplt_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6514,7 +6514,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpnlt_pd_mask() {
+    fn test_mm512_cmpnlt_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6522,7 +6522,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
+    fn test_mm512_mask_cmpnlt_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6531,7 +6531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmple_pd_mask() {
+    fn test_mm512_cmple_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6539,7 +6539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmple_pd_mask() {
+    fn test_mm512_mask_cmple_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6548,7 +6548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpnle_pd_mask() {
+    fn test_mm512_cmpnle_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6557,7 +6557,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpnle_pd_mask() {
+    fn test_mm512_mask_cmpnle_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6567,7 +6567,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpeq_pd_mask() {
+    fn test_mm512_cmpeq_pd_mask() {
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
         let m = _mm512_cmpeq_pd_mask(b, a);
@@ -6575,7 +6575,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpeq_pd_mask() {
+    fn test_mm512_mask_cmpeq_pd_mask() {
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
         let mask = 0b01111010;
@@ -6584,7 +6584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpneq_pd_mask() {
+    fn test_mm512_cmpneq_pd_mask() {
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
         let m = _mm512_cmpneq_pd_mask(b, a);
@@ -6592,7 +6592,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpneq_pd_mask() {
+    fn test_mm512_mask_cmpneq_pd_mask() {
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
         let mask = 0b01111010;
@@ -6601,7 +6601,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_pd_mask() {
+    fn test_mm512_cmp_pd_mask() {
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
         let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
@@ -6609,7 +6609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_pd_mask() {
+    fn test_mm512_mask_cmp_pd_mask() {
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
         let mask = 0b01100110;
@@ -6618,7 +6618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_cmp_pd_mask() {
+    fn test_mm256_cmp_pd_mask() {
         let a = _mm256_set_pd(0., 1., -1., 13.);
         let b = _mm256_set1_pd(1.);
         let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
@@ -6626,7 +6626,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cmp_pd_mask() {
+    fn test_mm256_mask_cmp_pd_mask() {
         let a = _mm256_set_pd(0., 1., -1., 13.);
         let b = _mm256_set1_pd(1.);
         let mask = 0b11111111;
@@ -6635,7 +6635,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_cmp_pd_mask() {
+    fn test_mm_cmp_pd_mask() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set1_pd(1.);
         let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
@@ -6643,7 +6643,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cmp_pd_mask() {
+    fn test_mm_mask_cmp_pd_mask() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set1_pd(1.);
         let mask = 0b11111111;
@@ -6652,7 +6652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmp_round_pd_mask() {
+    fn test_mm512_cmp_round_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6661,7 +6661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmp_round_pd_mask() {
+    fn test_mm512_mask_cmp_round_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
         let b = _mm512_set1_pd(-1.);
@@ -6671,7 +6671,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpord_pd_mask() {
+    fn test_mm512_cmpord_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
         #[rustfmt::skip]
@@ -6681,7 +6681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpord_pd_mask() {
+    fn test_mm512_mask_cmpord_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
         #[rustfmt::skip]
@@ -6692,7 +6692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_cmpunord_pd_mask() {
+    fn test_mm512_cmpunord_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
         #[rustfmt::skip]
@@ -6703,7 +6703,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cmpunord_pd_mask() {
+    fn test_mm512_mask_cmpunord_pd_mask() {
         #[rustfmt::skip]
         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
         #[rustfmt::skip]
@@ -6714,7 +6714,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmplt_epu64_mask() {
+    const fn test_mm512_cmplt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmplt_epu64_mask(a, b);
@@ -6722,7 +6722,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmplt_epu64_mask() {
+    const fn test_mm512_mask_cmplt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -6731,7 +6731,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epu64_mask() {
+    const fn test_mm256_cmplt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 100);
         let b = _mm256_set1_epi64x(2);
         let r = _mm256_cmplt_epu64_mask(a, b);
@@ -6739,7 +6739,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epu64_mask() {
+    const fn test_mm256_mask_cmplt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 100);
         let b = _mm256_set1_epi64x(2);
         let mask = 0b11111111;
@@ -6748,7 +6748,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmplt_epu64_mask() {
+    const fn test_mm_cmplt_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(2);
         let r = _mm_cmplt_epu64_mask(a, b);
@@ -6756,7 +6756,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epu64_mask() {
+    const fn test_mm_mask_cmplt_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(2);
         let mask = 0b11111111;
@@ -6765,7 +6765,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpgt_epu64_mask() {
+    const fn test_mm512_cmpgt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmpgt_epu64_mask(b, a);
@@ -6773,7 +6773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
+    const fn test_mm512_mask_cmpgt_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -6782,7 +6782,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epu64_mask() {
+    const fn test_mm256_cmpgt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_cmpgt_epu64_mask(a, b);
@@ -6790,7 +6790,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
+    const fn test_mm256_mask_cmpgt_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6799,7 +6799,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epu64_mask() {
+    const fn test_mm_cmpgt_epu64_mask() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmpgt_epu64_mask(a, b);
@@ -6807,7 +6807,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epu64_mask() {
+    const fn test_mm_mask_cmpgt_epu64_mask() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6816,7 +6816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmple_epu64_mask() {
+    const fn test_mm512_cmple_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -6826,7 +6826,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmple_epu64_mask() {
+    const fn test_mm512_mask_cmple_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -6834,7 +6834,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmple_epu64_mask() {
+    const fn test_mm256_cmple_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 1);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_cmple_epu64_mask(a, b);
@@ -6842,7 +6842,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epu64_mask() {
+    const fn test_mm256_mask_cmple_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, 1);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6851,7 +6851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmple_epu64_mask() {
+    const fn test_mm_cmple_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmple_epu64_mask(a, b);
@@ -6859,7 +6859,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epu64_mask() {
+    const fn test_mm_mask_cmple_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6868,7 +6868,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpge_epu64_mask() {
+    const fn test_mm512_cmpge_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -6878,7 +6878,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpge_epu64_mask() {
+    const fn test_mm512_mask_cmpge_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b11111111;
@@ -6887,7 +6887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epu64_mask() {
+    const fn test_mm256_cmpge_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
         let b = _mm256_set1_epi64x(1);
         let r = _mm256_cmpge_epu64_mask(a, b);
@@ -6895,7 +6895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epu64_mask() {
+    const fn test_mm256_mask_cmpge_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6904,7 +6904,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpge_epu64_mask() {
+    const fn test_mm_cmpge_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmpge_epu64_mask(a, b);
@@ -6912,7 +6912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epu64_mask() {
+    const fn test_mm_mask_cmpge_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -6921,7 +6921,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpeq_epu64_mask() {
+    const fn test_mm512_cmpeq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpeq_epu64_mask(b, a);
@@ -6929,7 +6929,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
+    const fn test_mm512_mask_cmpeq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -6938,7 +6938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epu64_mask() {
+    const fn test_mm256_cmpeq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let m = _mm256_cmpeq_epu64_mask(b, a);
@@ -6946,7 +6946,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
+    const fn test_mm256_mask_cmpeq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -6955,7 +6955,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epu64_mask() {
+    const fn test_mm_cmpeq_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let m = _mm_cmpeq_epu64_mask(b, a);
@@ -6963,7 +6963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epu64_mask() {
+    const fn test_mm_mask_cmpeq_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let mask = 0b11111111;
@@ -6972,7 +6972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpneq_epu64_mask() {
+    const fn test_mm512_cmpneq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpneq_epu64_mask(b, a);
@@ -6980,7 +6980,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
+    const fn test_mm512_mask_cmpneq_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -6989,7 +6989,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epu64_mask() {
+    const fn test_mm256_cmpneq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let r = _mm256_cmpneq_epu64_mask(b, a);
@@ -6997,7 +6997,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
+    const fn test_mm256_mask_cmpneq_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -7006,7 +7006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epu64_mask() {
+    const fn test_mm_cmpneq_epu64_mask() {
         let a = _mm_set_epi64x(-1, u64::MAX as i64);
         let b = _mm_set_epi64x(13, 42);
         let r = _mm_cmpneq_epu64_mask(b, a);
@@ -7014,7 +7014,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epu64_mask() {
+    const fn test_mm_mask_cmpneq_epu64_mask() {
         let a = _mm_set_epi64x(-1, u64::MAX as i64);
         let b = _mm_set_epi64x(13, 42);
         let mask = 0b11111111;
@@ -7023,7 +7023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmp_epu64_mask() {
+    const fn test_mm512_cmp_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7031,7 +7031,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmp_epu64_mask() {
+    const fn test_mm512_mask_cmp_epu64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -7040,7 +7040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmp_epu64_mask() {
+    const fn test_mm256_cmp_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 100);
         let b = _mm256_set1_epi64x(1);
         let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7048,7 +7048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epu64_mask() {
+    const fn test_mm256_mask_cmp_epu64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 100);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7057,7 +7057,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmp_epu64_mask() {
+    const fn test_mm_cmp_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7065,7 +7065,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epu64_mask() {
+    const fn test_mm_mask_cmp_epu64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7074,7 +7074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmplt_epi64_mask() {
+    const fn test_mm512_cmplt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmplt_epi64_mask(a, b);
@@ -7082,7 +7082,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmplt_epi64_mask() {
+    const fn test_mm512_mask_cmplt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01100110;
@@ -7091,7 +7091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmplt_epi64_mask() {
+    const fn test_mm256_cmplt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, -13);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmplt_epi64_mask(a, b);
@@ -7099,7 +7099,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmplt_epi64_mask() {
+    const fn test_mm256_mask_cmplt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, -13);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7108,7 +7108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmplt_epi64_mask() {
+    const fn test_mm_cmplt_epi64_mask() {
         let a = _mm_set_epi64x(-1, -13);
         let b = _mm_set1_epi64x(-1);
         let r = _mm_cmplt_epi64_mask(a, b);
@@ -7116,7 +7116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmplt_epi64_mask() {
+    const fn test_mm_mask_cmplt_epi64_mask() {
         let a = _mm_set_epi64x(-1, -13);
         let b = _mm_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7125,7 +7125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpgt_epi64_mask() {
+    const fn test_mm512_cmpgt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmpgt_epi64_mask(b, a);
@@ -7133,7 +7133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
+    const fn test_mm512_mask_cmpgt_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01100110;
@@ -7142,7 +7142,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpgt_epi64_mask() {
+    const fn test_mm256_cmpgt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmpgt_epi64_mask(a, b);
@@ -7150,7 +7150,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
+    const fn test_mm256_mask_cmpgt_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7159,7 +7159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpgt_epi64_mask() {
+    const fn test_mm_cmpgt_epi64_mask() {
         let a = _mm_set_epi64x(0, -1);
         let b = _mm_set1_epi64x(-1);
         let r = _mm_cmpgt_epi64_mask(a, b);
@@ -7167,7 +7167,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpgt_epi64_mask() {
+    const fn test_mm_mask_cmpgt_epi64_mask() {
         let a = _mm_set_epi64x(0, -1);
         let b = _mm_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7176,7 +7176,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmple_epi64_mask() {
+    const fn test_mm512_cmple_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -7186,7 +7186,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmple_epi64_mask() {
+    const fn test_mm512_mask_cmple_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01111010;
@@ -7194,7 +7194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmple_epi64_mask() {
+    const fn test_mm256_cmple_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmple_epi64_mask(a, b);
@@ -7202,7 +7202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmple_epi64_mask() {
+    const fn test_mm256_mask_cmple_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7211,7 +7211,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmple_epi64_mask() {
+    const fn test_mm_cmple_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let r = _mm_cmple_epi64_mask(a, b);
@@ -7219,7 +7219,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmple_epi64_mask() {
+    const fn test_mm_mask_cmple_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7228,7 +7228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpge_epi64_mask() {
+    const fn test_mm512_cmpge_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         assert_eq!(
@@ -7238,7 +7238,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpge_epi64_mask() {
+    const fn test_mm512_mask_cmpge_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b11111111;
@@ -7247,7 +7247,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpge_epi64_mask() {
+    const fn test_mm256_cmpge_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let r = _mm256_cmpge_epi64_mask(a, b);
@@ -7255,7 +7255,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpge_epi64_mask() {
+    const fn test_mm256_mask_cmpge_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
         let b = _mm256_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7264,7 +7264,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpge_epi64_mask() {
+    const fn test_mm_cmpge_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(-1);
         let r = _mm_cmpge_epi64_mask(a, b);
@@ -7272,7 +7272,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpge_epi64_mask() {
+    const fn test_mm_mask_cmpge_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(-1);
         let mask = 0b11111111;
@@ -7281,7 +7281,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpeq_epi64_mask() {
+    const fn test_mm512_cmpeq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpeq_epi64_mask(b, a);
@@ -7289,7 +7289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
+    const fn test_mm512_mask_cmpeq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -7298,7 +7298,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpeq_epi64_mask() {
+    const fn test_mm256_cmpeq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let m = _mm256_cmpeq_epi64_mask(b, a);
@@ -7306,7 +7306,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
+    const fn test_mm256_mask_cmpeq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -7315,7 +7315,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpeq_epi64_mask() {
+    const fn test_mm_cmpeq_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let m = _mm_cmpeq_epi64_mask(b, a);
@@ -7323,7 +7323,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpeq_epi64_mask() {
+    const fn test_mm_mask_cmpeq_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set_epi64x(0, 1);
         let mask = 0b11111111;
@@ -7332,19 +7332,19 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_set_epi64() {
+    const fn test_mm512_set_epi64() {
         let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_setr_epi64() {
+    const fn test_mm512_setr_epi64() {
         let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmpneq_epi64_mask() {
+    const fn test_mm512_cmpneq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let m = _mm512_cmpneq_epi64_mask(b, a);
@@ -7352,7 +7352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
+    const fn test_mm512_mask_cmpneq_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
         let mask = 0b01111010;
@@ -7361,7 +7361,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmpneq_epi64_mask() {
+    const fn test_mm256_cmpneq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let r = _mm256_cmpneq_epi64_mask(b, a);
@@ -7369,7 +7369,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
+    const fn test_mm256_mask_cmpneq_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set_epi64x(0, 1, 13, 42);
         let mask = 0b11111111;
@@ -7378,7 +7378,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmpneq_epi64_mask() {
+    const fn test_mm_cmpneq_epi64_mask() {
         let a = _mm_set_epi64x(-1, 13);
         let b = _mm_set_epi64x(13, 42);
         let r = _mm_cmpneq_epi64_mask(b, a);
@@ -7386,7 +7386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmpneq_epi64_mask() {
+    const fn test_mm_mask_cmpneq_epi64_mask() {
         let a = _mm_set_epi64x(-1, 13);
         let b = _mm_set_epi64x(13, 42);
         let mask = 0b11111111;
@@ -7395,7 +7395,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_cmp_epi64_mask() {
+    const fn test_mm512_cmp_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7403,7 +7403,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_cmp_epi64_mask() {
+    const fn test_mm512_mask_cmp_epi64_mask() {
         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
         let b = _mm512_set1_epi64(-1);
         let mask = 0b01100110;
@@ -7412,7 +7412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_cmp_epi64_mask() {
+    const fn test_mm256_cmp_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(1);
         let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7420,7 +7420,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_cmp_epi64_mask() {
+    const fn test_mm256_mask_cmp_epi64_mask() {
         let a = _mm256_set_epi64x(0, 1, -1, 13);
         let b = _mm256_set1_epi64x(1);
         let mask = 0b11111111;
@@ -7429,7 +7429,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_cmp_epi64_mask() {
+    const fn test_mm_cmp_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
@@ -7437,7 +7437,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_cmp_epi64_mask() {
+    const fn test_mm_mask_cmp_epi64_mask() {
         let a = _mm_set_epi64x(0, 1);
         let b = _mm_set1_epi64x(1);
         let mask = 0b11111111;
@@ -8318,7 +8318,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_rol_epi64() {
+    const fn test_mm512_rol_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8334,7 +8334,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_rol_epi64() {
+    const fn test_mm512_mask_rol_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8352,7 +8352,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_rol_epi64() {
+    const fn test_mm512_maskz_rol_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8366,7 +8366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_rol_epi64() {
+    const fn test_mm256_rol_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_rol_epi64::<1>(a);
         let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
@@ -8374,7 +8374,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_rol_epi64() {
+    const fn test_mm256_mask_rol_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8384,7 +8384,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_rol_epi64() {
+    const fn test_mm256_maskz_rol_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_maskz_rol_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8394,7 +8394,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_rol_epi64() {
+    const fn test_mm_rol_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_rol_epi64::<1>(a);
         let e = _mm_set_epi64x(1 << 0, 1 << 33);
@@ -8402,7 +8402,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_rol_epi64() {
+    const fn test_mm_mask_rol_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_mask_rol_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8412,7 +8412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_rol_epi64() {
+    const fn test_mm_maskz_rol_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_maskz_rol_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8422,7 +8422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_ror_epi64() {
+    const fn test_mm512_ror_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0,  1 << 32, 1 << 32, 1 << 32,
@@ -8438,7 +8438,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_ror_epi64() {
+    const fn test_mm512_mask_ror_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0,  1 << 32, 1 << 32, 1 << 32,
@@ -8456,7 +8456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_ror_epi64() {
+    const fn test_mm512_maskz_ror_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8470,7 +8470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_ror_epi64() {
+    const fn test_mm256_ror_epi64() {
         let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_ror_epi64::<1>(a);
         let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
@@ -8478,7 +8478,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_ror_epi64() {
+    const fn test_mm256_mask_ror_epi64() {
         let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8488,7 +8488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_ror_epi64() {
+    const fn test_mm256_maskz_ror_epi64() {
         let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_maskz_ror_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8498,7 +8498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_ror_epi64() {
+    const fn test_mm_ror_epi64() {
         let a = _mm_set_epi64x(1 << 0, 1 << 32);
         let r = _mm_ror_epi64::<1>(a);
         let e = _mm_set_epi64x(1 << 63, 1 << 31);
@@ -8506,7 +8506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_ror_epi64() {
+    const fn test_mm_mask_ror_epi64() {
         let a = _mm_set_epi64x(1 << 0, 1 << 32);
         let r = _mm_mask_ror_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8516,7 +8516,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_ror_epi64() {
+    const fn test_mm_maskz_ror_epi64() {
         let a = _mm_set_epi64x(1 << 0, 1 << 32);
         let r = _mm_maskz_ror_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8526,7 +8526,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_slli_epi64() {
+    const fn test_mm512_slli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8542,7 +8542,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_slli_epi64() {
+    const fn test_mm512_mask_slli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -8560,7 +8560,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_slli_epi64() {
+    const fn test_mm512_maskz_slli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8574,7 +8574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_slli_epi64() {
+    const fn test_mm256_mask_slli_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8584,7 +8584,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_slli_epi64() {
+    const fn test_mm256_maskz_slli_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let r = _mm256_maskz_slli_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8594,7 +8594,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_slli_epi64() {
+    const fn test_mm_mask_slli_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_mask_slli_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8604,7 +8604,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_slli_epi64() {
+    const fn test_mm_maskz_slli_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let r = _mm_maskz_slli_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8614,7 +8614,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srli_epi64() {
+    const fn test_mm512_srli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0, 1 << 32, 1 << 32, 1 << 32,
@@ -8630,7 +8630,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srli_epi64() {
+    const fn test_mm512_mask_srli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0, 1 << 32, 1 << 32, 1 << 32,
@@ -8648,7 +8648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srli_epi64() {
+    const fn test_mm512_maskz_srli_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8662,7 +8662,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srli_epi64() {
+    const fn test_mm256_mask_srli_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -8672,7 +8672,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srli_epi64() {
+    const fn test_mm256_maskz_srli_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_maskz_srli_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -8682,7 +8682,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srli_epi64() {
+    const fn test_mm_mask_srli_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_mask_srli_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -8692,7 +8692,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srli_epi64() {
+    const fn test_mm_maskz_srli_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_maskz_srli_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -8702,7 +8702,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_rolv_epi64() {
+    const fn test_mm512_rolv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -8719,7 +8719,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_rolv_epi64() {
+    const fn test_mm512_mask_rolv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -8738,7 +8738,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_rolv_epi64() {
+    const fn test_mm512_maskz_rolv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8753,7 +8753,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_rolv_epi64() {
+    const fn test_mm256_rolv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_rolv_epi64(a, b);
@@ -8762,7 +8762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_rolv_epi64() {
+    const fn test_mm256_mask_rolv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_rolv_epi64(a, 0, a, b);
@@ -8773,7 +8773,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_rolv_epi64() {
+    const fn test_mm256_maskz_rolv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_rolv_epi64(0, a, b);
@@ -8784,7 +8784,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_rolv_epi64() {
+    const fn test_mm_rolv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 63);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_rolv_epi64(a, b);
@@ -8793,7 +8793,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_rolv_epi64() {
+    const fn test_mm_mask_rolv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 63);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_mask_rolv_epi64(a, 0, a, b);
@@ -8804,7 +8804,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_rolv_epi64() {
+    const fn test_mm_maskz_rolv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 63);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_rolv_epi64(0, a, b);
@@ -8815,7 +8815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_rorv_epi64() {
+    const fn test_mm512_rorv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -8832,7 +8832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_rorv_epi64() {
+    const fn test_mm512_mask_rorv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -8851,7 +8851,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_rorv_epi64() {
+    const fn test_mm512_maskz_rorv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8866,7 +8866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_rorv_epi64() {
+    const fn test_mm256_rorv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_rorv_epi64(a, b);
@@ -8875,7 +8875,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_rorv_epi64() {
+    const fn test_mm256_mask_rorv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_rorv_epi64(a, 0, a, b);
@@ -8886,7 +8886,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_rorv_epi64() {
+    const fn test_mm256_maskz_rorv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
         let b = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_rorv_epi64(0, a, b);
@@ -8897,7 +8897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_rorv_epi64() {
+    const fn test_mm_rorv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 0);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_rorv_epi64(a, b);
@@ -8906,7 +8906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_rorv_epi64() {
+    const fn test_mm_mask_rorv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 0);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_mask_rorv_epi64(a, 0, a, b);
@@ -8917,7 +8917,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_rorv_epi64() {
+    const fn test_mm_maskz_rorv_epi64() {
         let a = _mm_set_epi64x(1 << 32, 1 << 0);
         let b = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_rorv_epi64(0, a, b);
@@ -8928,7 +8928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_sllv_epi64() {
+    const fn test_mm512_sllv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 63, 1 << 32, 1 << 32,
@@ -8945,7 +8945,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_sllv_epi64() {
+    const fn test_mm512_mask_sllv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 63, 1 << 32,
@@ -8964,7 +8964,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_sllv_epi64() {
+    const fn test_mm512_maskz_sllv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -8979,7 +8979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_sllv_epi64() {
+    const fn test_mm256_mask_sllv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
         let count = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_sllv_epi64(a, 0, a, count);
@@ -8990,7 +8990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_sllv_epi64() {
+    const fn test_mm256_maskz_sllv_epi64() {
         let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
         let count = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_sllv_epi64(0, a, count);
@@ -9001,7 +9001,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_sllv_epi64() {
+    const fn test_mm_mask_sllv_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let count = _mm_set_epi64x(2, 3);
         let r = _mm_mask_sllv_epi64(a, 0, a, count);
@@ -9012,7 +9012,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_sllv_epi64() {
+    const fn test_mm_maskz_sllv_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let count = _mm_set_epi64x(2, 3);
         let r = _mm_maskz_sllv_epi64(0, a, count);
@@ -9023,7 +9023,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srlv_epi64() {
+    const fn test_mm512_srlv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -9040,7 +9040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srlv_epi64() {
+    const fn test_mm512_mask_srlv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 0, 1 << 32, 1 << 32,
@@ -9059,7 +9059,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srlv_epi64() {
+    const fn test_mm512_maskz_srlv_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -9074,7 +9074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srlv_epi64() {
+    const fn test_mm256_mask_srlv_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_mask_srlv_epi64(a, 0, a, count);
@@ -9085,7 +9085,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srlv_epi64() {
+    const fn test_mm256_maskz_srlv_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_srlv_epi64(0, a, count);
@@ -9096,7 +9096,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srlv_epi64() {
+    const fn test_mm_mask_srlv_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_mask_srlv_epi64(a, 0, a, count);
@@ -9107,7 +9107,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srlv_epi64() {
+    const fn test_mm_maskz_srlv_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_maskz_srlv_epi64(0, a, count);
@@ -9118,7 +9118,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sll_epi64() {
+    fn test_mm512_sll_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -9138,7 +9138,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sll_epi64() {
+    fn test_mm512_mask_sll_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 63, 1 << 32, 1 << 32, 1 << 32,
@@ -9157,7 +9157,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sll_epi64() {
+    fn test_mm512_maskz_sll_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -9172,7 +9172,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sll_epi64() {
+    fn test_mm256_mask_sll_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_mask_sll_epi64(a, 0, a, count);
@@ -9183,7 +9183,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sll_epi64() {
+    fn test_mm256_maskz_sll_epi64() {
         let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_maskz_sll_epi64(0, a, count);
@@ -9194,7 +9194,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sll_epi64() {
+    fn test_mm_mask_sll_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_mask_sll_epi64(a, 0, a, count);
@@ -9205,7 +9205,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sll_epi64() {
+    fn test_mm_maskz_sll_epi64() {
         let a = _mm_set_epi64x(1 << 63, 1 << 32);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_sll_epi64(0, a, count);
@@ -9216,7 +9216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_srl_epi64() {
+    fn test_mm512_srl_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0, 1 << 32, 1 << 32, 1 << 32,
@@ -9233,7 +9233,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_srl_epi64() {
+    fn test_mm512_mask_srl_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 0, 1 << 32, 1 << 32, 1 << 32,
@@ -9252,7 +9252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_srl_epi64() {
+    fn test_mm512_maskz_srl_epi64() {
         #[rustfmt::skip]
         let a = _mm512_set_epi64(
             1 << 32, 1 << 32, 1 << 32, 1 << 32,
@@ -9267,7 +9267,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_srl_epi64() {
+    fn test_mm256_mask_srl_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_mask_srl_epi64(a, 0, a, count);
@@ -9278,7 +9278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_srl_epi64() {
+    fn test_mm256_maskz_srl_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_maskz_srl_epi64(0, a, count);
@@ -9289,7 +9289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_srl_epi64() {
+    fn test_mm_mask_srl_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_mask_srl_epi64(a, 0, a, count);
@@ -9300,7 +9300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_srl_epi64() {
+    fn test_mm_maskz_srl_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_srl_epi64(0, a, count);
@@ -9311,7 +9311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_sra_epi64() {
+    fn test_mm512_sra_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm_set_epi64x(0, 2);
         let r = _mm512_sra_epi64(a, count);
@@ -9320,7 +9320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_sra_epi64() {
+    fn test_mm512_mask_sra_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm_set_epi64x(0, 2);
         let r = _mm512_mask_sra_epi64(a, 0, a, count);
@@ -9331,7 +9331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_sra_epi64() {
+    fn test_mm512_maskz_sra_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm_set_epi64x(0, 2);
         let r = _mm512_maskz_sra_epi64(0, a, count);
@@ -9342,7 +9342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_sra_epi64() {
+    fn test_mm256_sra_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_sra_epi64(a, count);
@@ -9351,7 +9351,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_sra_epi64() {
+    fn test_mm256_mask_sra_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_mask_sra_epi64(a, 0, a, count);
@@ -9362,7 +9362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_sra_epi64() {
+    fn test_mm256_maskz_sra_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm256_maskz_sra_epi64(0, a, count);
@@ -9373,7 +9373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_sra_epi64() {
+    fn test_mm_sra_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_sra_epi64(a, count);
@@ -9382,7 +9382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_sra_epi64() {
+    fn test_mm_mask_sra_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_mask_sra_epi64(a, 0, a, count);
@@ -9393,7 +9393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_sra_epi64() {
+    fn test_mm_maskz_sra_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_sra_epi64(0, a, count);
@@ -9404,7 +9404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srav_epi64() {
+    const fn test_mm512_srav_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
         let r = _mm512_srav_epi64(a, count);
@@ -9413,7 +9413,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srav_epi64() {
+    const fn test_mm512_mask_srav_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
         let r = _mm512_mask_srav_epi64(a, 0, a, count);
@@ -9424,7 +9424,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srav_epi64() {
+    const fn test_mm512_maskz_srav_epi64() {
         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
         let r = _mm512_maskz_srav_epi64(0, a, count);
@@ -9435,7 +9435,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_srav_epi64() {
+    const fn test_mm256_srav_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_srav_epi64(a, count);
@@ -9444,7 +9444,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srav_epi64() {
+    const fn test_mm256_mask_srav_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_mask_srav_epi64(a, 0, a, count);
@@ -9455,7 +9455,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srav_epi64() {
+    const fn test_mm256_maskz_srav_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let count = _mm256_set1_epi64x(1);
         let r = _mm256_maskz_srav_epi64(0, a, count);
@@ -9466,7 +9466,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_srav_epi64() {
+    const fn test_mm_srav_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_srav_epi64(a, count);
@@ -9475,7 +9475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srav_epi64() {
+    const fn test_mm_mask_srav_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_mask_srav_epi64(a, 0, a, count);
@@ -9486,7 +9486,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srav_epi64() {
+    const fn test_mm_maskz_srav_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let count = _mm_set1_epi64x(1);
         let r = _mm_maskz_srav_epi64(0, a, count);
@@ -9497,7 +9497,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_srai_epi64() {
+    const fn test_mm512_srai_epi64() {
         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
         let r = _mm512_srai_epi64::<2>(a);
         let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
@@ -9505,7 +9505,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_srai_epi64() {
+    const fn test_mm512_mask_srai_epi64() {
         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
         let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -9515,7 +9515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_srai_epi64() {
+    const fn test_mm512_maskz_srai_epi64() {
         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
         let r = _mm512_maskz_srai_epi64::<2>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -9525,7 +9525,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_srai_epi64() {
+    const fn test_mm256_srai_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_srai_epi64::<1>(a);
         let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
@@ -9533,7 +9533,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_srai_epi64() {
+    const fn test_mm256_mask_srai_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -9543,7 +9543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_srai_epi64() {
+    const fn test_mm256_maskz_srai_epi64() {
         let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
         let r = _mm256_maskz_srai_epi64::<1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -9553,7 +9553,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_srai_epi64() {
+    const fn test_mm_srai_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_srai_epi64::<1>(a);
         let e = _mm_set_epi64x(1 << 4, 0);
@@ -9561,7 +9561,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_srai_epi64() {
+    const fn test_mm_mask_srai_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_mask_srai_epi64::<1>(a, 0, a);
         assert_eq_m128i(r, a);
@@ -9571,7 +9571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_srai_epi64() {
+    const fn test_mm_maskz_srai_epi64() {
         let a = _mm_set_epi64x(1 << 5, 0);
         let r = _mm_maskz_srai_epi64::<1>(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -9581,7 +9581,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_permute_pd() {
+    const fn test_mm512_permute_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_permute_pd::<0b11_11_11_11>(a);
         let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
@@ -9589,7 +9589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_permute_pd() {
+    const fn test_mm512_mask_permute_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
         assert_eq_m512d(r, a);
@@ -9599,7 +9599,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_permute_pd() {
+    const fn test_mm512_maskz_permute_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -9609,7 +9609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_permute_pd() {
+    const fn test_mm256_mask_permute_pd() {
         let a = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
         assert_eq_m256d(r, a);
@@ -9619,7 +9619,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_permute_pd() {
+    const fn test_mm256_maskz_permute_pd() {
         let a = _mm256_set_pd(3., 2., 1., 0.);
         let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -9629,7 +9629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_permute_pd() {
+    const fn test_mm_mask_permute_pd() {
         let a = _mm_set_pd(1., 0.);
         let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
         assert_eq_m128d(r, a);
@@ -9639,7 +9639,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_permute_pd() {
+    const fn test_mm_maskz_permute_pd() {
         let a = _mm_set_pd(1., 0.);
         let r = _mm_maskz_permute_pd::<0b11>(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -9649,7 +9649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_permutex_epi64() {
+    const fn test_mm512_permutex_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
         let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
@@ -9657,7 +9657,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_permutex_epi64() {
+    const fn test_mm512_mask_permutex_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
         assert_eq_m512i(r, a);
@@ -9667,7 +9667,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_permutex_epi64() {
+    const fn test_mm512_maskz_permutex_epi64() {
         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -9677,7 +9677,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_permutex_epi64() {
+    const fn test_mm256_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
         let e = _mm256_set_epi64x(3, 3, 3, 3);
@@ -9685,7 +9685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_permutex_epi64() {
+    const fn test_mm256_mask_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
         assert_eq_m256i(r, a);
@@ -9695,7 +9695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_permutex_epi64() {
+    const fn test_mm256_maskz_permutex_epi64() {
         let a = _mm256_set_epi64x(3, 2, 1, 0);
         let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -9705,7 +9705,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_permutex_pd() {
+    const fn test_mm512_permutex_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
         let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
@@ -9713,7 +9713,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_permutex_pd() {
+    const fn test_mm512_mask_permutex_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
         assert_eq_m512d(r, a);
@@ -9723,7 +9723,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_permutex_pd() {
+    const fn test_mm512_maskz_permutex_pd() {
         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -9733,7 +9733,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_permutex_pd() {
+    const fn test_mm256_permutex_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
         let e = _mm256_set_pd(0., 0., 0., 0.);
@@ -9741,7 +9741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_permutex_pd() {
+    const fn test_mm256_mask_permutex_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
         assert_eq_m256d(r, a);
@@ -9751,7 +9751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_permutex_pd() {
+    const fn test_mm256_maskz_permutex_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -9761,7 +9761,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutevar_pd() {
+    fn test_mm512_permutevar_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_set1_epi64(0b1);
         let r = _mm512_permutevar_pd(a, b);
@@ -9770,7 +9770,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutevar_pd() {
+    fn test_mm512_mask_permutevar_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_set1_epi64(0b1);
         let r = _mm512_mask_permutevar_pd(a, 0, a, b);
@@ -9781,7 +9781,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutevar_pd() {
+    fn test_mm512_maskz_permutevar_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let b = _mm512_set1_epi64(0b1);
         let r = _mm512_maskz_permutevar_pd(0, a, b);
@@ -9792,7 +9792,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutevar_pd() {
+    fn test_mm256_mask_permutevar_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let b = _mm256_set1_epi64x(0b1);
         let r = _mm256_mask_permutevar_pd(a, 0, a, b);
@@ -9803,7 +9803,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutevar_pd() {
+    fn test_mm256_maskz_permutevar_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let b = _mm256_set1_epi64x(0b1);
         let r = _mm256_maskz_permutevar_pd(0, a, b);
@@ -9814,7 +9814,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permutevar_pd() {
+    fn test_mm_mask_permutevar_pd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set1_epi64x(0b1);
         let r = _mm_mask_permutevar_pd(a, 0, a, b);
@@ -9825,7 +9825,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permutevar_pd() {
+    fn test_mm_maskz_permutevar_pd() {
         let a = _mm_set_pd(0., 1.);
         let b = _mm_set1_epi64x(0b1);
         let r = _mm_maskz_permutevar_pd(0, a, b);
@@ -9836,7 +9836,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutexvar_epi64() {
+    fn test_mm512_permutexvar_epi64() {
         let idx = _mm512_set1_epi64(1);
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_permutexvar_epi64(idx, a);
@@ -9845,7 +9845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutexvar_epi64() {
+    fn test_mm512_mask_permutexvar_epi64() {
         let idx = _mm512_set1_epi64(1);
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
@@ -9856,7 +9856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutexvar_epi64() {
+    fn test_mm512_maskz_permutexvar_epi64() {
         let idx = _mm512_set1_epi64(1);
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
@@ -9867,7 +9867,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutexvar_epi64() {
+    fn test_mm256_permutexvar_epi64() {
         let idx = _mm256_set1_epi64x(1);
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_permutexvar_epi64(idx, a);
@@ -9876,7 +9876,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutexvar_epi64() {
+    fn test_mm256_mask_permutexvar_epi64() {
         let idx = _mm256_set1_epi64x(1);
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
@@ -9887,7 +9887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutexvar_epi64() {
+    fn test_mm256_maskz_permutexvar_epi64() {
         let idx = _mm256_set1_epi64x(1);
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
@@ -9898,7 +9898,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutexvar_pd() {
+    fn test_mm512_permutexvar_pd() {
         let idx = _mm512_set1_epi64(1);
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_permutexvar_pd(idx, a);
@@ -9907,7 +9907,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutexvar_pd() {
+    fn test_mm512_mask_permutexvar_pd() {
         let idx = _mm512_set1_epi64(1);
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
@@ -9918,7 +9918,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutexvar_pd() {
+    fn test_mm512_maskz_permutexvar_pd() {
         let idx = _mm512_set1_epi64(1);
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_permutexvar_pd(0, idx, a);
@@ -9929,7 +9929,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutexvar_pd() {
+    fn test_mm256_permutexvar_pd() {
         let idx = _mm256_set1_epi64x(1);
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_permutexvar_pd(idx, a);
@@ -9938,7 +9938,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutexvar_pd() {
+    fn test_mm256_mask_permutexvar_pd() {
         let idx = _mm256_set1_epi64x(1);
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
@@ -9949,7 +9949,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutexvar_pd() {
+    fn test_mm256_maskz_permutexvar_pd() {
         let idx = _mm256_set1_epi64x(1);
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_maskz_permutexvar_pd(0, idx, a);
@@ -9960,7 +9960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutex2var_epi64() {
+    fn test_mm512_permutex2var_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_epi64(100);
@@ -9970,7 +9970,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutex2var_epi64() {
+    fn test_mm512_mask_permutex2var_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_epi64(100);
@@ -9982,7 +9982,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutex2var_epi64() {
+    fn test_mm512_maskz_permutex2var_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_epi64(100);
@@ -9994,7 +9994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask2_permutex2var_epi64() {
+    fn test_mm512_mask2_permutex2var_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_epi64(100);
@@ -10006,7 +10006,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutex2var_epi64() {
+    fn test_mm256_permutex2var_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_epi64x(100);
@@ -10016,7 +10016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutex2var_epi64() {
+    fn test_mm256_mask_permutex2var_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_epi64x(100);
@@ -10028,7 +10028,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex2var_epi64() {
+    fn test_mm256_maskz_permutex2var_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_epi64x(100);
@@ -10040,7 +10040,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask2_permutex2var_epi64() {
+    fn test_mm256_mask2_permutex2var_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_epi64x(100);
@@ -10052,7 +10052,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_permutex2var_epi64() {
+    fn test_mm_permutex2var_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_epi64x(100);
@@ -10062,7 +10062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permutex2var_epi64() {
+    fn test_mm_mask_permutex2var_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_epi64x(100);
@@ -10074,7 +10074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permutex2var_epi64() {
+    fn test_mm_maskz_permutex2var_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_epi64x(100);
@@ -10086,7 +10086,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask2_permutex2var_epi64() {
+    fn test_mm_mask2_permutex2var_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_epi64x(100);
@@ -10098,7 +10098,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_permutex2var_pd() {
+    fn test_mm512_permutex2var_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_pd(100.);
@@ -10108,7 +10108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_permutex2var_pd() {
+    fn test_mm512_mask_permutex2var_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_pd(100.);
@@ -10120,7 +10120,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_permutex2var_pd() {
+    fn test_mm512_maskz_permutex2var_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_pd(100.);
@@ -10132,7 +10132,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask2_permutex2var_pd() {
+    fn test_mm512_mask2_permutex2var_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
         let b = _mm512_set1_pd(100.);
@@ -10144,7 +10144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_permutex2var_pd() {
+    fn test_mm256_permutex2var_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_pd(100.);
@@ -10154,7 +10154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_permutex2var_pd() {
+    fn test_mm256_mask_permutex2var_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_pd(100.);
@@ -10166,7 +10166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_permutex2var_pd() {
+    fn test_mm256_maskz_permutex2var_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_pd(100.);
@@ -10178,7 +10178,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask2_permutex2var_pd() {
+    fn test_mm256_mask2_permutex2var_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
         let b = _mm256_set1_pd(100.);
@@ -10190,7 +10190,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_permutex2var_pd() {
+    fn test_mm_permutex2var_pd() {
         let a = _mm_set_pd(0., 1.);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_pd(100.);
@@ -10200,7 +10200,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_permutex2var_pd() {
+    fn test_mm_mask_permutex2var_pd() {
         let a = _mm_set_pd(0., 1.);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_pd(100.);
@@ -10212,7 +10212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_permutex2var_pd() {
+    fn test_mm_maskz_permutex2var_pd() {
         let a = _mm_set_pd(0., 1.);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_pd(100.);
@@ -10224,7 +10224,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask2_permutex2var_pd() {
+    fn test_mm_mask2_permutex2var_pd() {
         let a = _mm_set_pd(0., 1.);
         let idx = _mm_set_epi64x(1, 1 << 1);
         let b = _mm_set1_pd(100.);
@@ -10236,7 +10236,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_pd() {
+    const fn test_mm256_mask_shuffle_pd() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
@@ -10247,7 +10247,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_pd() {
+    const fn test_mm256_maskz_shuffle_pd() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
@@ -10258,7 +10258,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_shuffle_pd() {
+    const fn test_mm_mask_shuffle_pd() {
         let a = _mm_set_pd(1., 4.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
@@ -10269,7 +10269,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_shuffle_pd() {
+    const fn test_mm_maskz_shuffle_pd() {
         let a = _mm_set_pd(1., 4.);
         let b = _mm_set_pd(2., 3.);
         let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
@@ -10280,7 +10280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_i64x2() {
+    const fn test_mm512_shuffle_i64x2() {
         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
@@ -10289,7 +10289,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_i64x2() {
+    const fn test_mm512_mask_shuffle_i64x2() {
         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
@@ -10300,7 +10300,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_i64x2() {
+    const fn test_mm512_maskz_shuffle_i64x2() {
         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
         let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
@@ -10311,7 +10311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_shuffle_i64x2() {
+    const fn test_mm256_shuffle_i64x2() {
         let a = _mm256_set_epi64x(1, 4, 5, 8);
         let b = _mm256_set_epi64x(2, 3, 6, 7);
         let r = _mm256_shuffle_i64x2::<0b00>(a, b);
@@ -10320,7 +10320,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_i64x2() {
+    const fn test_mm256_mask_shuffle_i64x2() {
         let a = _mm256_set_epi64x(1, 4, 5, 8);
         let b = _mm256_set_epi64x(2, 3, 6, 7);
         let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
@@ -10331,7 +10331,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_i64x2() {
+    const fn test_mm256_maskz_shuffle_i64x2() {
         let a = _mm256_set_epi64x(1, 4, 5, 8);
         let b = _mm256_set_epi64x(2, 3, 6, 7);
         let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
@@ -10342,7 +10342,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_shuffle_f64x2() {
+    const fn test_mm512_shuffle_f64x2() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
@@ -10351,7 +10351,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_shuffle_f64x2() {
+    const fn test_mm512_mask_shuffle_f64x2() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
@@ -10362,7 +10362,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_shuffle_f64x2() {
+    const fn test_mm512_maskz_shuffle_f64x2() {
         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
@@ -10373,7 +10373,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_shuffle_f64x2() {
+    const fn test_mm256_shuffle_f64x2() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_shuffle_f64x2::<0b00>(a, b);
@@ -10382,7 +10382,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_shuffle_f64x2() {
+    const fn test_mm256_mask_shuffle_f64x2() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
@@ -10393,7 +10393,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_shuffle_f64x2() {
+    const fn test_mm256_maskz_shuffle_f64x2() {
         let a = _mm256_set_pd(1., 4., 5., 8.);
         let b = _mm256_set_pd(2., 3., 6., 7.);
         let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
@@ -10404,7 +10404,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_movedup_pd() {
+    const fn test_mm512_movedup_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_movedup_pd(a);
         let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
@@ -10412,7 +10412,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_movedup_pd() {
+    const fn test_mm512_mask_movedup_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_mask_movedup_pd(a, 0, a);
         assert_eq_m512d(r, a);
@@ -10422,7 +10422,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_movedup_pd() {
+    const fn test_mm512_maskz_movedup_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_movedup_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -10432,7 +10432,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_movedup_pd() {
+    const fn test_mm256_mask_movedup_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_mask_movedup_pd(a, 0, a);
         assert_eq_m256d(r, a);
@@ -10442,7 +10442,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_movedup_pd() {
+    const fn test_mm256_maskz_movedup_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let r = _mm256_maskz_movedup_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -10452,7 +10452,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_movedup_pd() {
+    const fn test_mm_mask_movedup_pd() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_mask_movedup_pd(a, 0, a);
         assert_eq_m128d(r, a);
@@ -10462,7 +10462,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_movedup_pd() {
+    const fn test_mm_maskz_movedup_pd() {
         let a = _mm_set_pd(1., 2.);
         let r = _mm_maskz_movedup_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -10472,7 +10472,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_inserti64x4() {
+    const fn test_mm512_inserti64x4() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_inserti64x4::<1>(a, b);
@@ -10481,7 +10481,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_inserti64x4() {
+    const fn test_mm512_mask_inserti64x4() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
@@ -10492,7 +10492,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_inserti64x4() {
+    const fn test_mm512_maskz_inserti64x4() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
@@ -10503,7 +10503,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_insertf64x4() {
+    const fn test_mm512_insertf64x4() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_insertf64x4::<1>(a, b);
@@ -10512,7 +10512,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_insertf64x4() {
+    const fn test_mm512_mask_insertf64x4() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
@@ -10523,7 +10523,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_insertf64x4() {
+    const fn test_mm512_maskz_insertf64x4() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
@@ -10534,21 +10534,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castpd128_pd512() {
+    const fn test_mm512_castpd128_pd512() {
         let a = _mm_setr_pd(17., 18.);
         let r = _mm512_castpd128_pd512(a);
         assert_eq_m128d(_mm512_castpd512_pd128(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castpd256_pd512() {
+    const fn test_mm512_castpd256_pd512() {
         let a = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_castpd256_pd512(a);
         assert_eq_m256d(_mm512_castpd512_pd256(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_zextpd128_pd512() {
+    const fn test_mm512_zextpd128_pd512() {
         let a = _mm_setr_pd(17., 18.);
         let r = _mm512_zextpd128_pd512(a);
         let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
@@ -10556,7 +10556,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_zextpd256_pd512() {
+    const fn test_mm512_zextpd256_pd512() {
         let a = _mm256_setr_pd(17., 18., 19., 20.);
         let r = _mm512_zextpd256_pd512(a);
         let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
@@ -10564,7 +10564,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castpd512_pd128() {
+    const fn test_mm512_castpd512_pd128() {
         let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
         let r = _mm512_castpd512_pd128(a);
         let e = _mm_setr_pd(17., 18.);
@@ -10572,7 +10572,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castpd512_pd256() {
+    const fn test_mm512_castpd512_pd256() {
         let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
         let r = _mm512_castpd512_pd256(a);
         let e = _mm256_setr_pd(17., 18., 19., 20.);
@@ -10580,7 +10580,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castpd_ps() {
+    const fn test_mm512_castpd_ps() {
         let a = _mm512_set1_pd(1.);
         let r = _mm512_castpd_ps(a);
         let e = _mm512_set_ps(
@@ -10591,7 +10591,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castpd_si512() {
+    const fn test_mm512_castpd_si512() {
         let a = _mm512_set1_pd(1.);
         let r = _mm512_castpd_si512(a);
         let e = _mm512_set_epi32(
@@ -10602,21 +10602,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castsi128_si512() {
+    const fn test_mm512_castsi128_si512() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_castsi128_si512(a);
         assert_eq_m128i(_mm512_castsi512_si128(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castsi256_si512() {
+    const fn test_mm512_castsi256_si512() {
         let a = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_castsi256_si512(a);
         assert_eq_m256i(_mm512_castsi512_si256(r), a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_zextsi128_si512() {
+    const fn test_mm512_zextsi128_si512() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_zextsi128_si512(a);
         let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
@@ -10624,7 +10624,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_zextsi256_si512() {
+    const fn test_mm512_zextsi256_si512() {
         let a = _mm256_setr_epi64x(17, 18, 19, 20);
         let r = _mm512_zextsi256_si512(a);
         let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
@@ -10632,7 +10632,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castsi512_si128() {
+    const fn test_mm512_castsi512_si128() {
         let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
         let r = _mm512_castsi512_si128(a);
         let e = _mm_setr_epi64x(17, 18);
@@ -10640,7 +10640,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castsi512_si256() {
+    const fn test_mm512_castsi512_si256() {
         let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
         let r = _mm512_castsi512_si256(a);
         let e = _mm256_setr_epi64x(17, 18, 19, 20);
@@ -10648,7 +10648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castsi512_ps() {
+    const fn test_mm512_castsi512_ps() {
         let a = _mm512_set1_epi64(1 << 62);
         let r = _mm512_castsi512_ps(a);
         let e = _mm512_set_ps(
@@ -10658,7 +10658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_castsi512_pd() {
+    const fn test_mm512_castsi512_pd() {
         let a = _mm512_set1_epi64(1 << 62);
         let r = _mm512_castsi512_pd(a);
         let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
@@ -10666,7 +10666,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcastq_epi64() {
+    const fn test_mm512_broadcastq_epi64() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_broadcastq_epi64(a);
         let e = _mm512_set1_epi64(17);
@@ -10674,7 +10674,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcastq_epi64() {
+    const fn test_mm512_mask_broadcastq_epi64() {
         let src = _mm512_set1_epi64(18);
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_mask_broadcastq_epi64(src, 0, a);
@@ -10685,7 +10685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcastq_epi64() {
+    const fn test_mm512_maskz_broadcastq_epi64() {
         let a = _mm_setr_epi64x(17, 18);
         let r = _mm512_maskz_broadcastq_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -10695,7 +10695,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcastq_epi64() {
+    const fn test_mm256_mask_broadcastq_epi64() {
         let src = _mm256_set1_epi64x(18);
         let a = _mm_set_epi64x(17, 18);
         let r = _mm256_mask_broadcastq_epi64(src, 0, a);
@@ -10706,7 +10706,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcastq_epi64() {
+    const fn test_mm256_maskz_broadcastq_epi64() {
         let a = _mm_set_epi64x(17, 18);
         let r = _mm256_maskz_broadcastq_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -10716,7 +10716,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_broadcastq_epi64() {
+    const fn test_mm_mask_broadcastq_epi64() {
         let src = _mm_set1_epi64x(18);
         let a = _mm_set_epi64x(17, 18);
         let r = _mm_mask_broadcastq_epi64(src, 0, a);
@@ -10727,7 +10727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_broadcastq_epi64() {
+    const fn test_mm_maskz_broadcastq_epi64() {
         let a = _mm_set_epi64x(17, 18);
         let r = _mm_maskz_broadcastq_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -10737,7 +10737,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcastsd_pd() {
+    const fn test_mm512_broadcastsd_pd() {
         let a = _mm_set_pd(17., 18.);
         let r = _mm512_broadcastsd_pd(a);
         let e = _mm512_set1_pd(18.);
@@ -10745,7 +10745,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcastsd_pd() {
+    const fn test_mm512_mask_broadcastsd_pd() {
         let src = _mm512_set1_pd(18.);
         let a = _mm_set_pd(17., 18.);
         let r = _mm512_mask_broadcastsd_pd(src, 0, a);
@@ -10756,7 +10756,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcastsd_pd() {
+    const fn test_mm512_maskz_broadcastsd_pd() {
         let a = _mm_set_pd(17., 18.);
         let r = _mm512_maskz_broadcastsd_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -10766,7 +10766,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_broadcastsd_pd() {
+    const fn test_mm256_mask_broadcastsd_pd() {
         let src = _mm256_set1_pd(18.);
         let a = _mm_set_pd(17., 18.);
         let r = _mm256_mask_broadcastsd_pd(src, 0, a);
@@ -10777,7 +10777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_broadcastsd_pd() {
+    const fn test_mm256_maskz_broadcastsd_pd() {
         let a = _mm_set_pd(17., 18.);
         let r = _mm256_maskz_broadcastsd_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -10787,7 +10787,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcast_i64x4() {
+    const fn test_mm512_broadcast_i64x4() {
         let a = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm512_broadcast_i64x4(a);
         let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
@@ -10795,7 +10795,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcast_i64x4() {
+    const fn test_mm512_mask_broadcast_i64x4() {
         let src = _mm512_set1_epi64(18);
         let a = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm512_mask_broadcast_i64x4(src, 0, a);
@@ -10806,7 +10806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcast_i64x4() {
+    const fn test_mm512_maskz_broadcast_i64x4() {
         let a = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm512_maskz_broadcast_i64x4(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -10816,7 +10816,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_broadcast_f64x4() {
+    const fn test_mm512_broadcast_f64x4() {
         let a = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm512_broadcast_f64x4(a);
         let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
@@ -10824,7 +10824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_broadcast_f64x4() {
+    const fn test_mm512_mask_broadcast_f64x4() {
         let src = _mm512_set1_pd(18.);
         let a = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm512_mask_broadcast_f64x4(src, 0, a);
@@ -10835,7 +10835,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_broadcast_f64x4() {
+    const fn test_mm512_maskz_broadcast_f64x4() {
         let a = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm512_maskz_broadcast_f64x4(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -10845,7 +10845,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_blend_epi64() {
+    const fn test_mm512_mask_blend_epi64() {
         let a = _mm512_set1_epi64(1);
         let b = _mm512_set1_epi64(2);
         let r = _mm512_mask_blend_epi64(0b11110000, a, b);
@@ -10854,7 +10854,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_epi64() {
+    const fn test_mm256_mask_blend_epi64() {
         let a = _mm256_set1_epi64x(1);
         let b = _mm256_set1_epi64x(2);
         let r = _mm256_mask_blend_epi64(0b00001111, a, b);
@@ -10863,7 +10863,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_blend_epi64() {
+    const fn test_mm_mask_blend_epi64() {
         let a = _mm_set1_epi64x(1);
         let b = _mm_set1_epi64x(2);
         let r = _mm_mask_blend_epi64(0b00000011, a, b);
@@ -10872,7 +10872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_blend_pd() {
+    const fn test_mm512_mask_blend_pd() {
         let a = _mm512_set1_pd(1.);
         let b = _mm512_set1_pd(2.);
         let r = _mm512_mask_blend_pd(0b11110000, a, b);
@@ -10881,7 +10881,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_blend_pd() {
+    const fn test_mm256_mask_blend_pd() {
         let a = _mm256_set1_pd(1.);
         let b = _mm256_set1_pd(2.);
         let r = _mm256_mask_blend_pd(0b00001111, a, b);
@@ -10890,7 +10890,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_blend_pd() {
+    const fn test_mm_mask_blend_pd() {
         let a = _mm_set1_pd(1.);
         let b = _mm_set1_pd(2.);
         let r = _mm_mask_blend_pd(0b00000011, a, b);
@@ -10899,7 +10899,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpackhi_epi64() {
+    const fn test_mm512_unpackhi_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_unpackhi_epi64(a, b);
@@ -10908,7 +10908,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpackhi_epi64() {
+    const fn test_mm512_mask_unpackhi_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
@@ -10919,7 +10919,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpackhi_epi64() {
+    const fn test_mm512_maskz_unpackhi_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_unpackhi_epi64(0, a, b);
@@ -10930,7 +10930,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpackhi_epi64() {
+    const fn test_mm256_mask_unpackhi_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
@@ -10941,7 +10941,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpackhi_epi64() {
+    const fn test_mm256_maskz_unpackhi_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_maskz_unpackhi_epi64(0, a, b);
@@ -10952,7 +10952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpackhi_epi64() {
+    const fn test_mm_mask_unpackhi_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
@@ -10963,7 +10963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpackhi_epi64() {
+    const fn test_mm_maskz_unpackhi_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_maskz_unpackhi_epi64(0, a, b);
@@ -10974,7 +10974,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpackhi_pd() {
+    const fn test_mm512_unpackhi_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_unpackhi_pd(a, b);
@@ -10983,7 +10983,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpackhi_pd() {
+    const fn test_mm512_mask_unpackhi_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
@@ -10994,7 +10994,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpackhi_pd() {
+    const fn test_mm512_maskz_unpackhi_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_maskz_unpackhi_pd(0, a, b);
@@ -11005,7 +11005,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpackhi_pd() {
+    const fn test_mm256_mask_unpackhi_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
@@ -11016,7 +11016,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpackhi_pd() {
+    const fn test_mm256_maskz_unpackhi_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_maskz_unpackhi_pd(0, a, b);
@@ -11027,7 +11027,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpackhi_pd() {
+    const fn test_mm_mask_unpackhi_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_mask_unpackhi_pd(a, 0, a, b);
@@ -11038,7 +11038,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpackhi_pd() {
+    const fn test_mm_maskz_unpackhi_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_maskz_unpackhi_pd(0, a, b);
@@ -11049,7 +11049,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpacklo_epi64() {
+    const fn test_mm512_unpacklo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_unpacklo_epi64(a, b);
@@ -11058,7 +11058,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpacklo_epi64() {
+    const fn test_mm512_mask_unpacklo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
@@ -11069,7 +11069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpacklo_epi64() {
+    const fn test_mm512_maskz_unpacklo_epi64() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
         let r = _mm512_maskz_unpacklo_epi64(0, a, b);
@@ -11080,7 +11080,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpacklo_epi64() {
+    const fn test_mm256_mask_unpacklo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
@@ -11091,7 +11091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpacklo_epi64() {
+    const fn test_mm256_maskz_unpacklo_epi64() {
         let a = _mm256_set_epi64x(1, 2, 3, 4);
         let b = _mm256_set_epi64x(17, 18, 19, 20);
         let r = _mm256_maskz_unpacklo_epi64(0, a, b);
@@ -11102,7 +11102,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpacklo_epi64() {
+    const fn test_mm_mask_unpacklo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
@@ -11113,7 +11113,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpacklo_epi64() {
+    const fn test_mm_maskz_unpacklo_epi64() {
         let a = _mm_set_epi64x(1, 2);
         let b = _mm_set_epi64x(17, 18);
         let r = _mm_maskz_unpacklo_epi64(0, a, b);
@@ -11124,7 +11124,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_unpacklo_pd() {
+    const fn test_mm512_unpacklo_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_unpacklo_pd(a, b);
@@ -11133,7 +11133,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_unpacklo_pd() {
+    const fn test_mm512_mask_unpacklo_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
@@ -11144,7 +11144,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_unpacklo_pd() {
+    const fn test_mm512_maskz_unpacklo_pd() {
         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
         let r = _mm512_maskz_unpacklo_pd(0, a, b);
@@ -11155,7 +11155,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_unpacklo_pd() {
+    const fn test_mm256_mask_unpacklo_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
@@ -11166,7 +11166,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_unpacklo_pd() {
+    const fn test_mm256_maskz_unpacklo_pd() {
         let a = _mm256_set_pd(1., 2., 3., 4.);
         let b = _mm256_set_pd(17., 18., 19., 20.);
         let r = _mm256_maskz_unpacklo_pd(0, a, b);
@@ -11177,7 +11177,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_unpacklo_pd() {
+    const fn test_mm_mask_unpacklo_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_mask_unpacklo_pd(a, 0, a, b);
@@ -11188,7 +11188,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_unpacklo_pd() {
+    const fn test_mm_maskz_unpacklo_pd() {
         let a = _mm_set_pd(1., 2.);
         let b = _mm_set_pd(17., 18.);
         let r = _mm_maskz_unpacklo_pd(0, a, b);
@@ -11199,7 +11199,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_alignr_epi64() {
+    const fn test_mm512_alignr_epi64() {
         let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm512_alignr_epi64::<0>(a, b);
@@ -11212,7 +11212,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_alignr_epi64() {
+    const fn test_mm512_mask_alignr_epi64() {
         let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
@@ -11223,7 +11223,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_alignr_epi64() {
+    const fn test_mm512_maskz_alignr_epi64() {
         let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
         let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
         let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
@@ -11234,7 +11234,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_alignr_epi64() {
+    const fn test_mm256_alignr_epi64() {
         let a = _mm256_set_epi64x(4, 3, 2, 1);
         let b = _mm256_set_epi64x(8, 7, 6, 5);
         let r = _mm256_alignr_epi64::<0>(a, b);
@@ -11249,7 +11249,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_alignr_epi64() {
+    const fn test_mm256_mask_alignr_epi64() {
         let a = _mm256_set_epi64x(4, 3, 2, 1);
         let b = _mm256_set_epi64x(8, 7, 6, 5);
         let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
@@ -11260,7 +11260,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_alignr_epi64() {
+    const fn test_mm256_maskz_alignr_epi64() {
         let a = _mm256_set_epi64x(4, 3, 2, 1);
         let b = _mm256_set_epi64x(8, 7, 6, 5);
         let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
@@ -11271,7 +11271,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_alignr_epi64() {
+    const fn test_mm_alignr_epi64() {
         let a = _mm_set_epi64x(2, 1);
         let b = _mm_set_epi64x(4, 3);
         let r = _mm_alignr_epi64::<0>(a, b);
@@ -11280,7 +11280,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_alignr_epi64() {
+    const fn test_mm_mask_alignr_epi64() {
         let a = _mm_set_epi64x(2, 1);
         let b = _mm_set_epi64x(4, 3);
         let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
@@ -11291,7 +11291,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_alignr_epi64() {
+    const fn test_mm_maskz_alignr_epi64() {
         let a = _mm_set_epi64x(2, 1);
         let b = _mm_set_epi64x(4, 3);
         let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
@@ -11302,7 +11302,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_and_epi64() {
+    const fn test_mm512_and_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_and_epi64(a, b);
@@ -11311,7 +11311,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_and_epi64() {
+    const fn test_mm512_mask_and_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_mask_and_epi64(a, 0, a, b);
@@ -11322,7 +11322,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_and_epi64() {
+    const fn test_mm512_maskz_and_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_maskz_and_epi64(0, a, b);
@@ -11333,7 +11333,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_and_epi64() {
+    const fn test_mm256_mask_and_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 0);
         let r = _mm256_mask_and_epi64(a, 0, a, b);
@@ -11344,7 +11344,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_and_epi64() {
+    const fn test_mm256_maskz_and_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 0);
         let r = _mm256_maskz_and_epi64(0, a, b);
@@ -11355,7 +11355,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_and_epi64() {
+    const fn test_mm_mask_and_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 0);
         let r = _mm_mask_and_epi64(a, 0, a, b);
@@ -11366,7 +11366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_and_epi64() {
+    const fn test_mm_maskz_and_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 0);
         let r = _mm_maskz_and_epi64(0, a, b);
@@ -11377,7 +11377,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_and_si512() {
+    const fn test_mm512_and_si512() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_and_epi64(a, b);
@@ -11386,7 +11386,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_or_epi64() {
+    const fn test_mm512_or_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_or_epi64(a, b);
@@ -11399,7 +11399,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_or_epi64() {
+    const fn test_mm512_mask_or_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_mask_or_epi64(a, 0, a, b);
@@ -11414,7 +11414,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_or_epi64() {
+    const fn test_mm512_maskz_or_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_maskz_or_epi64(0, a, b);
@@ -11425,7 +11425,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_or_epi64() {
+    const fn test_mm256_or_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_or_epi64(a, b);
@@ -11434,7 +11434,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_or_epi64() {
+    const fn test_mm256_mask_or_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_mask_or_epi64(a, 0, a, b);
@@ -11445,7 +11445,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_or_epi64() {
+    const fn test_mm256_maskz_or_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_maskz_or_epi64(0, a, b);
@@ -11456,7 +11456,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_or_epi64() {
+    const fn test_mm_or_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_or_epi64(a, b);
@@ -11465,7 +11465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_or_epi64() {
+    const fn test_mm_mask_or_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_mask_or_epi64(a, 0, a, b);
@@ -11476,7 +11476,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_or_epi64() {
+    const fn test_mm_maskz_or_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_maskz_or_epi64(0, a, b);
@@ -11487,7 +11487,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_or_si512() {
+    const fn test_mm512_or_si512() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_or_epi64(a, b);
@@ -11500,7 +11500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_xor_epi64() {
+    const fn test_mm512_xor_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_xor_epi64(a, b);
@@ -11509,7 +11509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_xor_epi64() {
+    const fn test_mm512_mask_xor_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_mask_xor_epi64(a, 0, a, b);
@@ -11520,7 +11520,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_xor_epi64() {
+    const fn test_mm512_maskz_xor_epi64() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_maskz_xor_epi64(0, a, b);
@@ -11531,7 +11531,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_xor_epi64() {
+    const fn test_mm256_xor_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_xor_epi64(a, b);
@@ -11540,7 +11540,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_xor_epi64() {
+    const fn test_mm256_mask_xor_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_mask_xor_epi64(a, 0, a, b);
@@ -11551,7 +11551,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_xor_epi64() {
+    const fn test_mm256_maskz_xor_epi64() {
         let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm256_set1_epi64x(1 << 13);
         let r = _mm256_maskz_xor_epi64(0, a, b);
@@ -11562,7 +11562,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_xor_epi64() {
+    const fn test_mm_xor_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_xor_epi64(a, b);
@@ -11571,7 +11571,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_xor_epi64() {
+    const fn test_mm_mask_xor_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_mask_xor_epi64(a, 0, a, b);
@@ -11582,7 +11582,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_xor_epi64() {
+    const fn test_mm_maskz_xor_epi64() {
         let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
         let b = _mm_set1_epi64x(1 << 13);
         let r = _mm_maskz_xor_epi64(0, a, b);
@@ -11593,7 +11593,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_xor_si512() {
+    const fn test_mm512_xor_si512() {
         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
         let r = _mm512_xor_epi64(a, b);
@@ -11602,7 +11602,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_andnot_epi64() {
+    const fn test_mm512_andnot_epi64() {
         let a = _mm512_set1_epi64(0);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_andnot_epi64(a, b);
@@ -11611,7 +11611,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_andnot_epi64() {
+    const fn test_mm512_mask_andnot_epi64() {
         let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_mask_andnot_epi64(a, 0, a, b);
@@ -11622,7 +11622,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_andnot_epi64() {
+    const fn test_mm512_maskz_andnot_epi64() {
         let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_maskz_andnot_epi64(0, a, b);
@@ -11637,7 +11637,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_andnot_epi64() {
+    const fn test_mm256_mask_andnot_epi64() {
         let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm256_mask_andnot_epi64(a, 0, a, b);
@@ -11648,7 +11648,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_andnot_epi64() {
+    const fn test_mm256_maskz_andnot_epi64() {
         let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm256_maskz_andnot_epi64(0, a, b);
@@ -11659,7 +11659,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_andnot_epi64() {
+    const fn test_mm_mask_andnot_epi64() {
         let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm_mask_andnot_epi64(a, 0, a, b);
@@ -11670,7 +11670,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_andnot_epi64() {
+    const fn test_mm_maskz_andnot_epi64() {
         let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
         let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
         let r = _mm_maskz_andnot_epi64(0, a, b);
@@ -11681,7 +11681,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_andnot_si512() {
+    const fn test_mm512_andnot_si512() {
         let a = _mm512_set1_epi64(0);
         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
         let r = _mm512_andnot_si512(a, b);
@@ -11690,175 +11690,175 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_add_epi64() {
+    const fn test_mm512_reduce_add_epi64() {
         let a = _mm512_set1_epi64(1);
         let e: i64 = _mm512_reduce_add_epi64(a);
         assert_eq!(8, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_add_epi64() {
+    const fn test_mm512_mask_reduce_add_epi64() {
         let a = _mm512_set1_epi64(1);
         let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
         assert_eq!(4, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_add_pd() {
+    const fn test_mm512_reduce_add_pd() {
         let a = _mm512_set1_pd(1.);
         let e: f64 = _mm512_reduce_add_pd(a);
         assert_eq!(8., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_add_pd() {
+    const fn test_mm512_mask_reduce_add_pd() {
         let a = _mm512_set1_pd(1.);
         let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
         assert_eq!(4., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_mul_epi64() {
+    const fn test_mm512_reduce_mul_epi64() {
         let a = _mm512_set1_epi64(2);
         let e: i64 = _mm512_reduce_mul_epi64(a);
         assert_eq!(256, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_mul_epi64() {
+    const fn test_mm512_mask_reduce_mul_epi64() {
         let a = _mm512_set1_epi64(2);
         let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
         assert_eq!(16, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_mul_pd() {
+    const fn test_mm512_reduce_mul_pd() {
         let a = _mm512_set1_pd(2.);
         let e: f64 = _mm512_reduce_mul_pd(a);
         assert_eq!(256., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_mul_pd() {
+    const fn test_mm512_mask_reduce_mul_pd() {
         let a = _mm512_set1_pd(2.);
         let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
         assert_eq!(16., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_max_epi64() {
+    const fn test_mm512_reduce_max_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_reduce_max_epi64(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_max_epi64() {
+    const fn test_mm512_mask_reduce_max_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_max_epu64() {
+    const fn test_mm512_reduce_max_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_reduce_max_epu64(a);
         assert_eq!(7, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_max_epu64() {
+    const fn test_mm512_mask_reduce_max_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_max_pd() {
+    fn test_mm512_reduce_max_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let e: f64 = _mm512_reduce_max_pd(a);
         assert_eq!(7., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_max_pd() {
+    fn test_mm512_mask_reduce_max_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
         assert_eq!(3., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_min_epi64() {
+    const fn test_mm512_reduce_min_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_reduce_min_epi64(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_min_epi64() {
+    const fn test_mm512_mask_reduce_min_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_min_epu64() {
+    const fn test_mm512_reduce_min_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_reduce_min_epu64(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_min_epu64() {
+    const fn test_mm512_mask_reduce_min_epu64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_reduce_min_pd() {
+    fn test_mm512_reduce_min_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let e: f64 = _mm512_reduce_min_pd(a);
         assert_eq!(0., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_reduce_min_pd() {
+    fn test_mm512_mask_reduce_min_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
         assert_eq!(0., e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_and_epi64() {
+    const fn test_mm512_reduce_and_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_reduce_and_epi64(a);
         assert_eq!(0, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_and_epi64() {
+    const fn test_mm512_mask_reduce_and_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_reduce_or_epi64() {
+    const fn test_mm512_reduce_or_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_reduce_or_epi64(a);
         assert_eq!(3, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_reduce_or_epi64() {
+    const fn test_mm512_mask_reduce_or_epi64() {
         let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
         let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
         assert_eq!(1, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_extractf64x4_pd() {
+    const fn test_mm512_extractf64x4_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_extractf64x4_pd::<1>(a);
         let e = _mm256_setr_pd(5., 6., 7., 8.);
@@ -11866,7 +11866,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_extractf64x4_pd() {
+    const fn test_mm512_mask_extractf64x4_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let src = _mm256_set1_pd(100.);
         let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
@@ -11877,7 +11877,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_extractf64x4_pd() {
+    const fn test_mm512_maskz_extractf64x4_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -11887,7 +11887,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_extracti64x4_epi64() {
+    const fn test_mm512_extracti64x4_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_extracti64x4_epi64::<0x1>(a);
         let e = _mm256_setr_epi64x(5, 6, 7, 8);
@@ -11895,7 +11895,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_extracti64x4_epi64() {
+    const fn test_mm512_mask_extracti64x4_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let src = _mm256_set1_epi64x(100);
         let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
@@ -11906,7 +11906,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_extracti64x4_epi64() {
+    const fn test_mm512_maskz_extracti64x4_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -11916,7 +11916,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compress_epi64() {
+    fn test_mm512_mask_compress_epi64() {
         let src = _mm512_set1_epi64(200);
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_mask_compress_epi64(src, 0, a);
@@ -11927,7 +11927,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_compress_epi64() {
+    fn test_mm512_maskz_compress_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_maskz_compress_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -11937,7 +11937,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compress_epi64() {
+    fn test_mm256_mask_compress_epi64() {
         let src = _mm256_set1_epi64x(200);
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_compress_epi64(src, 0, a);
@@ -11948,7 +11948,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_compress_epi64() {
+    fn test_mm256_maskz_compress_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_compress_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -11958,7 +11958,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compress_epi64() {
+    fn test_mm_mask_compress_epi64() {
         let src = _mm_set1_epi64x(200);
         let a = _mm_set_epi64x(0, 1);
         let r = _mm_mask_compress_epi64(src, 0, a);
@@ -11969,7 +11969,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_compress_epi64() {
+    fn test_mm_maskz_compress_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_compress_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -11979,7 +11979,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compress_pd() {
+    fn test_mm512_mask_compress_pd() {
         let src = _mm512_set1_pd(200.);
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_compress_pd(src, 0, a);
@@ -11990,7 +11990,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_compress_pd() {
+    fn test_mm512_maskz_compress_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_compress_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -12000,7 +12000,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compress_pd() {
+    fn test_mm256_mask_compress_pd() {
         let src = _mm256_set1_pd(200.);
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_mask_compress_pd(src, 0, a);
@@ -12011,7 +12011,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_compress_pd() {
+    fn test_mm256_maskz_compress_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_maskz_compress_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -12021,7 +12021,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compress_pd() {
+    fn test_mm_mask_compress_pd() {
         let src = _mm_set1_pd(200.);
         let a = _mm_set_pd(0., 1.);
         let r = _mm_mask_compress_pd(src, 0, a);
@@ -12032,7 +12032,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_compress_pd() {
+    fn test_mm_maskz_compress_pd() {
         let a = _mm_set_pd(0., 1.);
         let r = _mm_maskz_compress_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -12042,7 +12042,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expand_epi64() {
+    fn test_mm512_mask_expand_epi64() {
         let src = _mm512_set1_epi64(200);
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_mask_expand_epi64(src, 0, a);
@@ -12053,7 +12053,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expand_epi64() {
+    fn test_mm512_maskz_expand_epi64() {
         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
         let r = _mm512_maskz_expand_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -12063,7 +12063,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expand_epi64() {
+    fn test_mm256_mask_expand_epi64() {
         let src = _mm256_set1_epi64x(200);
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_mask_expand_epi64(src, 0, a);
@@ -12074,7 +12074,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expand_epi64() {
+    fn test_mm256_maskz_expand_epi64() {
         let a = _mm256_set_epi64x(0, 1, 2, 3);
         let r = _mm256_maskz_expand_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -12084,7 +12084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expand_epi64() {
+    fn test_mm_mask_expand_epi64() {
         let src = _mm_set1_epi64x(200);
         let a = _mm_set_epi64x(0, 1);
         let r = _mm_mask_expand_epi64(src, 0, a);
@@ -12095,7 +12095,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expand_epi64() {
+    fn test_mm_maskz_expand_epi64() {
         let a = _mm_set_epi64x(0, 1);
         let r = _mm_maskz_expand_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -12105,7 +12105,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expand_pd() {
+    fn test_mm512_mask_expand_pd() {
         let src = _mm512_set1_pd(200.);
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_mask_expand_pd(src, 0, a);
@@ -12116,7 +12116,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expand_pd() {
+    fn test_mm512_maskz_expand_pd() {
         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
         let r = _mm512_maskz_expand_pd(0, a);
         assert_eq_m512d(r, _mm512_setzero_pd());
@@ -12126,7 +12126,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expand_pd() {
+    fn test_mm256_mask_expand_pd() {
         let src = _mm256_set1_pd(200.);
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_mask_expand_pd(src, 0, a);
@@ -12137,7 +12137,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expand_pd() {
+    fn test_mm256_maskz_expand_pd() {
         let a = _mm256_set_pd(0., 1., 2., 3.);
         let r = _mm256_maskz_expand_pd(0, a);
         assert_eq_m256d(r, _mm256_setzero_pd());
@@ -12147,7 +12147,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expand_pd() {
+    fn test_mm_mask_expand_pd() {
         let src = _mm_set1_pd(200.);
         let a = _mm_set_pd(0., 1.);
         let r = _mm_mask_expand_pd(src, 0, a);
@@ -12158,7 +12158,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expand_pd() {
+    fn test_mm_maskz_expand_pd() {
         let a = _mm_set_pd(0., 1.);
         let r = _mm_maskz_expand_pd(0, a);
         assert_eq_m128d(r, _mm_setzero_pd());
@@ -12589,7 +12589,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_test_epi64_mask() {
+    const fn test_mm512_test_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
         let r = _mm512_test_epi64_mask(a, b);
@@ -12598,7 +12598,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_test_epi64_mask() {
+    const fn test_mm512_mask_test_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
         let r = _mm512_mask_test_epi64_mask(0, a, b);
@@ -12609,7 +12609,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_test_epi64_mask() {
+    const fn test_mm256_test_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm256_test_epi64_mask(a, b);
@@ -12618,7 +12618,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_test_epi64_mask() {
+    const fn test_mm256_mask_test_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm256_mask_test_epi64_mask(0, a, b);
@@ -12629,7 +12629,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_test_epi64_mask() {
+    const fn test_mm_test_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm_test_epi64_mask(a, b);
@@ -12638,7 +12638,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_test_epi64_mask() {
+    const fn test_mm_mask_test_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
         let r = _mm_mask_test_epi64_mask(0, a, b);
@@ -12649,7 +12649,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_testn_epi64_mask() {
+    const fn test_mm512_testn_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
         let r = _mm512_testn_epi64_mask(a, b);
@@ -12658,7 +12658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_testn_epi64_mask() {
+    const fn test_mm512_mask_testn_epi64_mask() {
         let a = _mm512_set1_epi64(1 << 0);
         let b = _mm512_set1_epi64(1 << 1);
         let r = _mm512_mask_testn_epi64_mask(0, a, b);
@@ -12669,7 +12669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_testn_epi64_mask() {
+    const fn test_mm256_testn_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 1);
         let r = _mm256_testn_epi64_mask(a, b);
@@ -12678,7 +12678,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_testn_epi64_mask() {
+    const fn test_mm256_mask_testn_epi64_mask() {
         let a = _mm256_set1_epi64x(1 << 0);
         let b = _mm256_set1_epi64x(1 << 1);
         let r = _mm256_mask_testn_epi64_mask(0, a, b);
@@ -12689,7 +12689,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_testn_epi64_mask() {
+    const fn test_mm_testn_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 1);
         let r = _mm_testn_epi64_mask(a, b);
@@ -12698,7 +12698,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_testn_epi64_mask() {
+    const fn test_mm_mask_testn_epi64_mask() {
         let a = _mm_set1_epi64x(1 << 0);
         let b = _mm_set1_epi64x(1 << 1);
         let r = _mm_mask_testn_epi64_mask(0, a, b);
@@ -12709,7 +12709,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_set1_epi64() {
+    const fn test_mm512_mask_set1_epi64() {
         let src = _mm512_set1_epi64(2);
         let a: i64 = 11;
         let r = _mm512_mask_set1_epi64(src, 0, a);
@@ -12720,7 +12720,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_set1_epi64() {
+    const fn test_mm512_maskz_set1_epi64() {
         let a: i64 = 11;
         let r = _mm512_maskz_set1_epi64(0, a);
         assert_eq_m512i(r, _mm512_setzero_si512());
@@ -12730,7 +12730,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_set1_epi64() {
+    const fn test_mm256_mask_set1_epi64() {
         let src = _mm256_set1_epi64x(2);
         let a: i64 = 11;
         let r = _mm256_mask_set1_epi64(src, 0, a);
@@ -12741,7 +12741,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_set1_epi64() {
+    const fn test_mm256_maskz_set1_epi64() {
         let a: i64 = 11;
         let r = _mm256_maskz_set1_epi64(0, a);
         assert_eq_m256i(r, _mm256_setzero_si256());
@@ -12751,7 +12751,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_set1_epi64() {
+    const fn test_mm_mask_set1_epi64() {
         let src = _mm_set1_epi64x(2);
         let a: i64 = 11;
         let r = _mm_mask_set1_epi64(src, 0, a);
@@ -12762,7 +12762,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_set1_epi64() {
+    const fn test_mm_maskz_set1_epi64() {
         let a: i64 = 11;
         let r = _mm_maskz_set1_epi64(0, a);
         assert_eq_m128i(r, _mm_setzero_si128());
@@ -12772,7 +12772,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtsd_i64() {
+    fn test_mm_cvtsd_i64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtsd_i64(a);
         let e: i64 = -2;
@@ -12780,7 +12780,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtss_i64() {
+    fn test_mm_cvtss_i64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtss_i64(a);
         let e: i64 = -2;
@@ -12788,7 +12788,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundi64_ss() {
+    fn test_mm_cvt_roundi64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -12797,7 +12797,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsi64_ss() {
+    fn test_mm_cvt_roundsi64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -12806,7 +12806,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvti64_ss() {
+    const fn test_mm_cvti64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvti64_ss(a, b);
@@ -12815,7 +12815,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvti64_sd() {
+    const fn test_mm_cvti64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvti64_sd(a, b);
@@ -12824,7 +12824,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_si64() {
+    fn test_mm_cvt_roundsd_si64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i64 = -1;
@@ -12832,7 +12832,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_i64() {
+    fn test_mm_cvt_roundsd_i64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i64 = -1;
@@ -12840,7 +12840,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsd_u64() {
+    fn test_mm_cvt_roundsd_u64() {
         let a = _mm_set_pd(1., f64::MAX);
         let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: u64 = u64::MAX;
@@ -12848,7 +12848,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtsd_u64() {
+    fn test_mm_cvtsd_u64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtsd_u64(a);
         let e: u64 = u64::MAX;
@@ -12856,7 +12856,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_i64() {
+    fn test_mm_cvt_roundss_i64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i64 = -1;
@@ -12864,7 +12864,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_si64() {
+    fn test_mm_cvt_roundss_si64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: i64 = -1;
@@ -12872,7 +12872,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundss_u64() {
+    fn test_mm_cvt_roundss_u64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
         let e: u64 = u64::MAX;
@@ -12880,7 +12880,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtss_u64() {
+    fn test_mm_cvtss_u64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtss_u64(a);
         let e: u64 = u64::MAX;
@@ -12888,7 +12888,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttsd_i64() {
+    fn test_mm_cvttsd_i64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvttsd_i64(a);
         let e: i64 = -1;
@@ -12896,7 +12896,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundsd_i64() {
+    fn test_mm_cvtt_roundsd_i64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
         let e: i64 = -1;
@@ -12904,7 +12904,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundsd_si64() {
+    fn test_mm_cvtt_roundsd_si64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
         let e: i64 = -1;
@@ -12912,7 +12912,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundsd_u64() {
+    fn test_mm_cvtt_roundsd_u64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
         let e: u64 = u64::MAX;
@@ -12920,7 +12920,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttsd_u64() {
+    fn test_mm_cvttsd_u64() {
         let a = _mm_set_pd(1., -1.5);
         let r = _mm_cvttsd_u64(a);
         let e: u64 = u64::MAX;
@@ -12928,7 +12928,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttss_i64() {
+    fn test_mm_cvttss_i64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvttss_i64(a);
         let e: i64 = -1;
@@ -12936,7 +12936,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundss_i64() {
+    fn test_mm_cvtt_roundss_i64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
         let e: i64 = -1;
@@ -12944,7 +12944,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundss_si64() {
+    fn test_mm_cvtt_roundss_si64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
         let e: i64 = -1;
@@ -12952,7 +12952,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvtt_roundss_u64() {
+    fn test_mm_cvtt_roundss_u64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
         let e: u64 = u64::MAX;
@@ -12960,7 +12960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvttss_u64() {
+    fn test_mm_cvttss_u64() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let r = _mm_cvttss_u64(a);
         let e: u64 = u64::MAX;
@@ -12968,7 +12968,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvtu64_ss() {
+    const fn test_mm_cvtu64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: u64 = 9;
         let r = _mm_cvtu64_ss(a, b);
@@ -12977,7 +12977,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm_cvtu64_sd() {
+    const fn test_mm_cvtu64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: u64 = 9;
         let r = _mm_cvtu64_sd(a, b);
@@ -12986,7 +12986,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundu64_ss() {
+    fn test_mm_cvt_roundu64_ss() {
         let a = _mm_set_ps(0., -0.5, 1., -1.5);
         let b: u64 = 9;
         let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -12995,7 +12995,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundu64_sd() {
+    fn test_mm_cvt_roundu64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: u64 = 9;
         let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -13004,7 +13004,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundi64_sd() {
+    fn test_mm_cvt_roundi64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
@@ -13013,7 +13013,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_cvt_roundsi64_sd() {
+    fn test_mm_cvt_roundsi64_sd() {
         let a = _mm_set_pd(1., -1.5);
         let b: i64 = 9;
         let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
diff --git a/crates/core_arch/src/x86_64/avx512fp16.rs b/crates/core_arch/src/x86_64/avx512fp16.rs
index 955c6ccc75..e11a5d7c8d 100644
--- a/crates/core_arch/src/x86_64/avx512fp16.rs
+++ b/crates/core_arch/src/x86_64/avx512fp16.rs
@@ -232,7 +232,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvti64_sh() {
+    fn test_mm_cvti64_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvti64_sh(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -240,7 +240,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvt_roundi64_sh() {
+    fn test_mm_cvt_roundi64_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundi64_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -248,7 +248,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvtu64_sh() {
+    fn test_mm_cvtu64_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtu64_sh(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -256,7 +256,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_cvt_roundu64_sh() {
+    fn test_mm_cvt_roundu64_sh() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundu64_sh::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 10);
         let e = _mm_setr_ph(10.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
@@ -264,56 +264,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_i64() {
+    fn test_mm_cvtsh_i64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtsh_i64(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvt_roundsh_i64() {
+    fn test_mm_cvt_roundsh_i64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundsh_i64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtsh_u64() {
+    fn test_mm_cvtsh_u64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtsh_u64(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvt_roundsh_u64() {
+    fn test_mm_cvt_roundsh_u64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvt_roundsh_u64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvttsh_i64() {
+    fn test_mm_cvttsh_i64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttsh_i64(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtt_roundsh_i64() {
+    fn test_mm_cvtt_roundsh_i64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtt_roundsh_i64::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvttsh_u64() {
+    fn test_mm_cvttsh_u64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvttsh_u64(a);
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    unsafe fn test_mm_cvtt_roundsh_u64() {
+    fn test_mm_cvtt_roundsh_u64() {
         let a = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let r = _mm_cvtt_roundsh_u64::<_MM_FROUND_NO_EXC>(a);
         assert_eq!(r, 1);
diff --git a/crates/core_arch/src/x86_64/bmi.rs b/crates/core_arch/src/x86_64/bmi.rs
index d5fd97583f..8d2b22089a 100644
--- a/crates/core_arch/src/x86_64/bmi.rs
+++ b/crates/core_arch/src/x86_64/bmi.rs
@@ -135,13 +135,13 @@ mod tests {
     use crate::core_arch::{x86::*, x86_64::*};
 
     #[simd_test(enable = "bmi1")]
-    unsafe fn test_bextr_u64() {
+    fn test_bextr_u64() {
         let r = _bextr_u64(0b0101_0000u64, 4, 4);
         assert_eq!(r, 0b0000_0101u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_andn_u64() {
+    const fn test_andn_u64() {
         assert_eq!(_andn_u64(0, 0), 0);
         assert_eq!(_andn_u64(0, 1), 1);
         assert_eq!(_andn_u64(1, 0), 0);
@@ -164,25 +164,25 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_blsi_u64() {
+    const fn test_blsi_u64() {
         assert_eq!(_blsi_u64(0b1101_0000u64), 0b0001_0000u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_blsmsk_u64() {
+    const fn test_blsmsk_u64() {
         let r = _blsmsk_u64(0b0011_0000u64);
         assert_eq!(r, 0b0001_1111u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_blsr_u64() {
+    const fn test_blsr_u64() {
         // TODO: test the behavior when the input is `0`.
         let r = _blsr_u64(0b0011_0000u64);
         assert_eq!(r, 0b0010_0000u64);
     }
 
     #[simd_test(enable = "bmi1")]
-    const unsafe fn test_tzcnt_u64() {
+    const fn test_tzcnt_u64() {
         assert_eq!(_tzcnt_u64(0b0000_0001u64), 0u64);
         assert_eq!(_tzcnt_u64(0b0000_0000u64), 64u64);
         assert_eq!(_tzcnt_u64(0b1001_0000u64), 4u64);
diff --git a/crates/core_arch/src/x86_64/bmi2.rs b/crates/core_arch/src/x86_64/bmi2.rs
index be12465c81..6151eee8bd 100644
--- a/crates/core_arch/src/x86_64/bmi2.rs
+++ b/crates/core_arch/src/x86_64/bmi2.rs
@@ -86,7 +86,7 @@ mod tests {
     use crate::core_arch::x86_64::*;
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_pext_u64() {
+    fn test_pext_u64() {
         let n = 0b1011_1110_1001_0011u64;
 
         let m0 = 0b0110_0011_1000_0101u64;
@@ -100,7 +100,7 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_pdep_u64() {
+    fn test_pdep_u64() {
         let n = 0b1011_1110_1001_0011u64;
 
         let m0 = 0b0110_0011_1000_0101u64;
@@ -114,7 +114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "bmi2")]
-    unsafe fn test_bzhi_u64() {
+    fn test_bzhi_u64() {
         let n = 0b1111_0010u64;
         let s = 0b0001_0010u64;
         assert_eq!(_bzhi_u64(n, 5), s);
@@ -122,7 +122,7 @@ mod tests {
 
     #[simd_test(enable = "bmi2")]
     #[rustfmt::skip]
-const     unsafe fn test_mulx_u64() {
+    const fn test_mulx_u64() {
         let a: u64 = 9_223_372_036_854_775_800;
         let b: u64 = 100;
         let mut hi = 0;
diff --git a/crates/core_arch/src/x86_64/sse.rs b/crates/core_arch/src/x86_64/sse.rs
index e5c1f79153..81e1070b55 100644
--- a/crates/core_arch/src/x86_64/sse.rs
+++ b/crates/core_arch/src/x86_64/sse.rs
@@ -74,7 +74,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtss_si64() {
+    fn test_mm_cvtss_si64() {
         let inputs = &[
             (42.0f32, 42i64),
             (-31.4, -31),
@@ -98,7 +98,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvttss_si64() {
+    fn test_mm_cvttss_si64() {
         let inputs = &[
             (42.0f32, 42i64),
             (-31.4, -31),
@@ -125,7 +125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_cvtsi64_ss() {
+    const fn test_mm_cvtsi64_ss() {
         let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
         let r = _mm_cvtsi64_ss(a, 4555);
diff --git a/crates/core_arch/src/x86_64/sse2.rs b/crates/core_arch/src/x86_64/sse2.rs
index 9f350f2368..b156af078a 100644
--- a/crates/core_arch/src/x86_64/sse2.rs
+++ b/crates/core_arch/src/x86_64/sse2.rs
@@ -172,7 +172,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsd_si64() {
+    fn test_mm_cvtsd_si64() {
         let r = _mm_cvtsd_si64(_mm_setr_pd(-2.0, 5.0));
         assert_eq!(r, -2_i64);
 
@@ -181,20 +181,20 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtsd_si64x() {
+    fn test_mm_cvtsd_si64x() {
         let r = _mm_cvtsd_si64x(_mm_setr_pd(f64::NAN, f64::NAN));
         assert_eq!(r, i64::MIN);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvttsd_si64() {
+    fn test_mm_cvttsd_si64() {
         let a = _mm_setr_pd(-1.1, 2.2);
         let r = _mm_cvttsd_si64(a);
         assert_eq!(r, -1_i64);
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvttsd_si64x() {
+    fn test_mm_cvttsd_si64x() {
         let a = _mm_setr_pd(f64::NEG_INFINITY, f64::NAN);
         let r = _mm_cvttsd_si64x(a);
         assert_eq!(r, i64::MIN);
@@ -213,19 +213,19 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsi64_si128() {
+    const fn test_mm_cvtsi64_si128() {
         let r = _mm_cvtsi64_si128(5);
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsi128_si64() {
+    const fn test_mm_cvtsi128_si64() {
         let r = _mm_cvtsi128_si64(_mm_setr_epi64x(5, 0));
         assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_cvtsi64_sd() {
+    const fn test_mm_cvtsi64_sd() {
         let a = _mm_set1_pd(3.5);
         let r = _mm_cvtsi64_sd(a, 5);
         assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));
diff --git a/crates/core_arch/src/x86_64/sse41.rs b/crates/core_arch/src/x86_64/sse41.rs
index 3b1c88ad8c..7732264e20 100644
--- a/crates/core_arch/src/x86_64/sse41.rs
+++ b/crates/core_arch/src/x86_64/sse41.rs
@@ -41,7 +41,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_extract_epi64() {
+    const fn test_mm_extract_epi64() {
         let a = _mm_setr_epi64x(0, 1);
         let r = _mm_extract_epi64::<1>(a);
         assert_eq!(r, 1);
@@ -50,7 +50,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_insert_epi64() {
+    const fn test_mm_insert_epi64() {
         let a = _mm_set1_epi64x(0);
         let e = _mm_setr_epi64x(0, 32);
         let r = _mm_insert_epi64::<1>(a, 32);
diff --git a/crates/core_arch/src/x86_64/sse42.rs b/crates/core_arch/src/x86_64/sse42.rs
index 64a23b2b19..cd32c149af 100644
--- a/crates/core_arch/src/x86_64/sse42.rs
+++ b/crates/core_arch/src/x86_64/sse42.rs
@@ -28,7 +28,7 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse4.2")]
-    unsafe fn test_mm_crc32_u64() {
+    fn test_mm_crc32_u64() {
         let crc = 0x7819dccd3e824;
         let v = 0x2a22b845fed;
         let i = _mm_crc32_u64(crc, v);
diff --git a/crates/core_arch/src/x86_64/tbm.rs b/crates/core_arch/src/x86_64/tbm.rs
index 031bd32071..fe12538b07 100644
--- a/crates/core_arch/src/x86_64/tbm.rs
+++ b/crates/core_arch/src/x86_64/tbm.rs
@@ -154,18 +154,18 @@ mod tests {
     use crate::core_arch::x86_64::*;
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_bextri_u64() {
+    fn test_bextri_u64() {
         assert_eq!(_bextri_u64::<0x0404>(0b0101_0000u64), 0b0000_0101u64);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcfill_u64() {
+    const fn test_blcfill_u64() {
         assert_eq!(_blcfill_u64(0b0101_0111u64), 0b0101_0000u64);
         assert_eq!(_blcfill_u64(0b1111_1111u64), 0u64);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blci_u64() {
+    const fn test_blci_u64() {
         assert_eq!(
             _blci_u64(0b0101_0000u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1110u64
@@ -177,25 +177,25 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcic_u64() {
+    const fn test_blcic_u64() {
         assert_eq!(_blcic_u64(0b0101_0001u64), 0b0000_0010u64);
         assert_eq!(_blcic_u64(0b1111_1111u64), 0b1_0000_0000u64);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcmsk_u64() {
+    const fn test_blcmsk_u64() {
         assert_eq!(_blcmsk_u64(0b0101_0001u64), 0b0000_0011u64);
         assert_eq!(_blcmsk_u64(0b1111_1111u64), 0b1_1111_1111u64);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blcs_u64() {
+    const fn test_blcs_u64() {
         assert_eq!(_blcs_u64(0b0101_0001u64), 0b0101_0011u64);
         assert_eq!(_blcs_u64(0b1111_1111u64), 0b1_1111_1111u64);
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blsfill_u64() {
+    const fn test_blsfill_u64() {
         assert_eq!(_blsfill_u64(0b0101_0100u64), 0b0101_0111u64);
         assert_eq!(
             _blsfill_u64(0u64),
@@ -204,7 +204,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_blsic_u64() {
+    const fn test_blsic_u64() {
         assert_eq!(
             _blsic_u64(0b0101_0100u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1011u64
@@ -216,7 +216,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_t1mskc_u64() {
+    const fn test_t1mskc_u64() {
         assert_eq!(
             _t1mskc_u64(0b0101_0111u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64
@@ -228,7 +228,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    const unsafe fn test_tzmsk_u64() {
+    const fn test_tzmsk_u64() {
         assert_eq!(_tzmsk_u64(0b0101_1000u64), 0b0000_0111u64);
         assert_eq!(_tzmsk_u64(0b0101_1001u64), 0b0000_0000u64);
     }

From 2ca8a44057abe83cb7d632f36388204560620d3e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Sun, 28 Dec 2025 19:32:34 +0100
Subject: [PATCH 085/326] Fix some tests so they test the correct function

---
 crates/core_arch/src/x86/avx512f.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index f300bf48ef..f5100fd1b6 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -57344,7 +57344,7 @@ mod tests {
             0, 0, 0, 0,
             0, 0, 0, 1 << 3 | 1 << 4,
         );
-        let r = _mm512_and_epi32(a, b);
+        let r = _mm512_and_si512(a, b);
         let e = _mm512_set_epi32(1 << 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 << 3);
         assert_eq_m512i(r, e);
     }
@@ -57512,7 +57512,7 @@ mod tests {
             0, 0, 0, 0,
             0, 0, 0, 1 << 3 | 1 << 4,
         );
-        let r = _mm512_or_epi32(a, b);
+        let r = _mm512_or_si512(a, b);
         #[rustfmt::skip]
         let e = _mm512_set_epi32(
             1 << 1 | 1 << 2, 0, 0, 0,
@@ -57680,7 +57680,7 @@ mod tests {
             0, 0, 0, 0,
             0, 0, 0, 1 << 3 | 1 << 4,
         );
-        let r = _mm512_xor_epi32(a, b);
+        let r = _mm512_xor_si512(a, b);
         #[rustfmt::skip]
         let e = _mm512_set_epi32(
             1 << 2, 0, 0, 0,

From 40961300c017ae0edea47424d6f9b57a6d813e21 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Thu, 1 Jan 2026 04:24:07 +0000
Subject: [PATCH 086/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to 48622726c4a91c87bf6cd4dbe1000c95df59906e.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index 04d41c96f5..df8693cd1c 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-8401398e1f14a24670ee1a3203713dc2f0f8b3a8
+48622726c4a91c87bf6cd4dbe1000c95df59906e

From 8f5bd4c55584097e8ff1f64c142eb5220472ba26 Mon Sep 17 00:00:00 2001
From: Luca Versari <veluca@google.com>
Date: Thu, 1 Jan 2026 13:07:02 +0100
Subject: [PATCH 087/326] Clarify documentation around "undefined" bits in
 intrinsics.

---
 crates/core_arch/src/x86/avx.rs     | 18 +++++++++--
 crates/core_arch/src/x86/avx512f.rs | 48 +++++++++++++++++++++++++----
 crates/core_arch/src/x86/sse.rs     |  2 +-
 3 files changed, 58 insertions(+), 10 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index 94f075894a..e0e01ae6d0 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -2946,7 +2946,11 @@ pub const fn _mm256_castsi256_si128(a: __m256i) -> __m128i {
 }
 
 /// Casts vector of type __m128 to type __m256;
-/// the upper 128 bits of the result are undefined.
+/// the upper 128 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_castps128_ps256)
 #[inline]
@@ -2960,7 +2964,11 @@ pub const fn _mm256_castps128_ps256(a: __m128) -> __m256 {
 }
 
 /// Casts vector of type __m128d to type __m256d;
-/// the upper 128 bits of the result are undefined.
+/// the upper 128 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_castpd128_pd256)
 #[inline]
@@ -2974,7 +2982,11 @@ pub const fn _mm256_castpd128_pd256(a: __m128d) -> __m256d {
 }
 
 /// Casts vector of type __m128i to type __m256i;
-/// the upper 128 bits of the result are undefined.
+/// the upper 128 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_castsi128_si256)
 #[inline]
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 5da633f50e..76b7539383 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -27728,7 +27728,13 @@ pub const fn _mm_maskz_unpacklo_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m12
     }
 }
 
-/// Cast vector of type __m128 to type __m512; the upper 384 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+/// Cast vector of type __m128 to type __m512; the upper 384 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
+///
+/// This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps128_ps512&expand=621)
 #[inline]
@@ -27745,7 +27751,13 @@ pub const fn _mm512_castps128_ps512(a: __m128) -> __m512 {
     }
 }
 
-/// Cast vector of type __m256 to type __m512; the upper 256 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+/// Cast vector of type __m256 to type __m512; the upper 256 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
+///
+/// This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps256_ps512&expand=623)
 #[inline]
@@ -27840,7 +27852,13 @@ pub const fn _mm512_castps_si512(a: __m512) -> __m512i {
     unsafe { transmute(a) }
 }
 
-/// Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+/// Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
+///
+/// This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd128_pd512&expand=609)
 #[inline]
@@ -27851,7 +27869,13 @@ pub const fn _mm512_castpd128_pd512(a: __m128d) -> __m512d {
     unsafe { simd_shuffle!(a, _mm_undefined_pd(), [0, 1, 2, 2, 2, 2, 2, 2]) }
 }
 
-/// Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+/// Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
+///
+/// This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd256_pd512&expand=611)
 #[inline]
@@ -27928,7 +27952,13 @@ pub const fn _mm512_castpd_si512(a: __m512d) -> __m512i {
     unsafe { transmute(a) }
 }
 
-/// Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+/// Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
+///
+/// This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi128_si512&expand=629)
 #[inline]
@@ -27939,7 +27969,13 @@ pub const fn _mm512_castsi128_si512(a: __m128i) -> __m512i {
     unsafe { simd_shuffle!(a, _mm_undefined_si128(), [0, 1, 2, 2, 2, 2, 2, 2]) }
 }
 
-/// Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+/// Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are indeterminate.
+///
+/// In the Intel documentation, the upper bits are declared to be "undefined".
+/// This is not equivalent to [`mem::MaybeUninit`]; instead, these bits are non-deterministically
+/// set to some valid value. In practice, this is typically equivalent to [`mem::zeroed`].
+///
+/// This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi256_si512&expand=633)
 #[inline]
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 55392f9944..751f969e50 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -1947,7 +1947,7 @@ pub fn _mm_prefetch<const STRATEGY: i32>(p: *const i8) {
     }
 }
 
-/// Returns vector of type __m128 with indeterminate elements.with indetermination elements.
+/// Returns vector of type __m128 with indeterminate elements.
 /// Despite using the word "undefined" (following Intel's naming scheme), this non-deterministically
 /// picks some valid value and is not equivalent to [`mem::MaybeUninit`].
 /// In practice, this is typically equivalent to [`mem::zeroed`].

From 32146718741ee22ff0d54d21b9ab60353014c980 Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Thu, 1 Jan 2026 19:52:45 +0800
Subject: [PATCH 088/326] Use LLVM intrinsics for `madd` intrinsics

---
 crates/core_arch/src/x86/avx2.rs     | 26 +++++++----
 crates/core_arch/src/x86/avx512bw.rs | 64 +++++++++++++---------------
 crates/core_arch/src/x86/sse2.rs     | 26 +++++++----
 3 files changed, 63 insertions(+), 53 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 740b09d116..6f56e937c6 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -1813,14 +1813,20 @@ pub const fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) ->
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let r: i32x16 = simd_mul(simd_cast(a.as_i16x16()), simd_cast(b.as_i16x16()));
-        let even: i32x8 = simd_shuffle!(r, r, [0, 2, 4, 6, 8, 10, 12, 14]);
-        let odd: i32x8 = simd_shuffle!(r, r, [1, 3, 5, 7, 9, 11, 13, 15]);
-        simd_add(even, odd).as_m256i()
-    }
+pub fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
+    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
+    //
+    // ```rust
+    // #[target_feature(enable = "avx2")]
+    // unsafe fn widening_add(mad: __m256i) -> __m256i {
+    //     _mm256_madd_epi16(mad, _mm256_set1_epi16(1))
+    // }
+    // ```
+    //
+    // If we implement this using generic vector intrinsics, the optimizer
+    // will eliminate this pattern, and `vpmaddwd` will no longer be emitted.
+    // For this reason, we use x86 intrinsics.
+    unsafe { transmute(pmaddwd(a.as_i16x16(), b.as_i16x16())) }
 }
 
 /// Vertically multiplies each unsigned 8-bit integer from `a` with the
@@ -3789,6 +3795,8 @@ unsafe extern "C" {
     fn phaddsw(a: i16x16, b: i16x16) -> i16x16;
     #[link_name = "llvm.x86.avx2.phsub.sw"]
     fn phsubsw(a: i16x16, b: i16x16) -> i16x16;
+    #[link_name = "llvm.x86.avx2.pmadd.wd"]
+    fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
     fn pmaddubsw(a: u8x32, b: i8x32) -> i16x16;
     #[link_name = "llvm.x86.avx2.mpsadbw"]
@@ -4637,7 +4645,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const fn test_mm256_madd_epi16() {
+    fn test_mm256_madd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_madd_epi16(a, b);
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index dc86f70c05..6b4b88621e 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6321,22 +6321,20 @@ pub const unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a:
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let r: i32x32 = simd_mul(simd_cast(a.as_i16x32()), simd_cast(b.as_i16x32()));
-        let even: i32x16 = simd_shuffle!(
-            r,
-            r,
-            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
-        );
-        let odd: i32x16 = simd_shuffle!(
-            r,
-            r,
-            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
-        );
-        simd_add(even, odd).as_m512i()
-    }
+pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
+    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
+    //
+    // ```rust
+    // #[target_feature(enable = "avx512bw")]
+    // unsafe fn widening_add(mad: __m512i) -> __m512i {
+    //     _mm512_madd_epi16(mad, _mm512_set1_epi16(1))
+    // }
+    // ```
+    //
+    // If we implement this using generic vector intrinsics, the optimizer
+    // will eliminate this pattern, and `vpmaddwd` will no longer be emitted.
+    // For this reason, we use x86 intrinsics.
+    unsafe { transmute(vpmaddwd(a.as_i16x32(), b.as_i16x32())) }
 }
 
 /// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6346,8 +6344,7 @@ pub const fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, src.as_i32x16()))
@@ -6361,8 +6358,7 @@ pub const fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: _
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, i32x16::ZERO))
@@ -6376,8 +6372,7 @@ pub const fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, src.as_i32x8()))
@@ -6391,8 +6386,7 @@ pub const fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, i32x8::ZERO))
@@ -6406,8 +6400,7 @@ pub const fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, src.as_i32x4()))
@@ -6421,8 +6414,7 @@ pub const fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m12
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, i32x4::ZERO))
@@ -12582,6 +12574,8 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.pmul.hr.sw.512"]
     fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32;
 
+    #[link_name = "llvm.x86.avx512.pmaddw.d.512"]
+    fn vpmaddwd(a: i16x32, b: i16x32) -> i32x16;
     #[link_name = "llvm.x86.avx512.pmaddubs.w.512"]
     fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32;
 
@@ -17486,7 +17480,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const fn test_mm512_madd_epi16() {
+    fn test_mm512_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_madd_epi16(a, b);
@@ -17495,7 +17489,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const fn test_mm512_mask_madd_epi16() {
+    fn test_mm512_mask_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_madd_epi16(a, 0, a, b);
@@ -17523,7 +17517,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const fn test_mm512_maskz_madd_epi16() {
+    fn test_mm512_maskz_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_madd_epi16(0, a, b);
@@ -17534,7 +17528,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm256_mask_madd_epi16() {
+    fn test_mm256_mask_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_madd_epi16(a, 0, a, b);
@@ -17554,7 +17548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm256_maskz_madd_epi16() {
+    fn test_mm256_maskz_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_madd_epi16(0, a, b);
@@ -17565,7 +17559,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm_mask_madd_epi16() {
+    fn test_mm_mask_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_madd_epi16(a, 0, a, b);
@@ -17576,7 +17570,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm_maskz_madd_epi16() {
+    fn test_mm_maskz_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_madd_epi16(0, a, b);
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index d7ac00287f..eec01ce1db 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -210,14 +210,20 @@ pub const fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let r: i32x8 = simd_mul(simd_cast(a.as_i16x8()), simd_cast(b.as_i16x8()));
-        let even: i32x4 = simd_shuffle!(r, r, [0, 2, 4, 6]);
-        let odd: i32x4 = simd_shuffle!(r, r, [1, 3, 5, 7]);
-        simd_add(even, odd).as_m128i()
-    }
+pub fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
+    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
+    //
+    // ```rust
+    // #[target_feature(enable = "sse2")]
+    // unsafe fn widening_add(mad: __m128i) -> __m128i {
+    //     _mm_madd_epi16(mad, _mm_set1_epi16(1))
+    // }
+    // ```
+    //
+    // If we implement this using generic vector intrinsics, the optimizer
+    // will eliminate this pattern, and `pmaddwd` will no longer be emitted.
+    // For this reason, we use x86 intrinsics.
+    unsafe { transmute(pmaddwd(a.as_i16x8(), b.as_i16x8())) }
 }
 
 /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
@@ -3187,6 +3193,8 @@ unsafe extern "C" {
     fn lfence();
     #[link_name = "llvm.x86.sse2.mfence"]
     fn mfence();
+    #[link_name = "llvm.x86.sse2.pmadd.wd"]
+    fn pmaddwd(a: i16x8, b: i16x8) -> i32x4;
     #[link_name = "llvm.x86.sse2.psad.bw"]
     fn psadbw(a: u8x16, b: u8x16) -> u64x2;
     #[link_name = "llvm.x86.sse2.psll.w"]
@@ -3467,7 +3475,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const fn test_mm_madd_epi16() {
+    fn test_mm_madd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm_madd_epi16(a, b);

From a70dae1116e186a6f63df9527cd09192a3761af3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Fri, 2 Jan 2026 21:18:51 +0100
Subject: [PATCH 089/326] Change `repr(packed)` struct to `repr(C, packed)`

`repr(packed)` structs do not have a well-defined layout
---
 crates/core_arch/src/x86_64/amx.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index 3e0ac8f47c..f372f7066d 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -510,7 +510,7 @@ mod tests {
     use syscalls::{Sysno, syscall};
 
     #[allow(non_camel_case_types)]
-    #[repr(packed)]
+    #[repr(C, packed)]
     #[derive(Copy, Clone, Default, Debug, PartialEq)]
     struct __tilecfg {
         /// 0 `or` 1

From 6da6c06f1c359bdb788177a813a0347f9e563260 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Thu, 1 Jan 2026 22:47:41 +0100
Subject: [PATCH 090/326] Use a generic type to implement SIMD types in
 `core_arch::simd`

This allows the `types` macro to easily implement `From<Simd<T, N>>` and `Into<Simd<T, N>>`
---
 crates/core_arch/rustfmt.toml           |   3 -
 crates/core_arch/src/lib.rs             |   5 +-
 crates/core_arch/src/macros.rs          |  16 ++
 crates/core_arch/src/powerpc/altivec.rs |   2 -
 crates/core_arch/src/powerpc/macros.rs  |  20 --
 crates/core_arch/src/s390x/macros.rs    |  20 --
 crates/core_arch/src/s390x/vector.rs    |   2 -
 crates/core_arch/src/simd.rs            | 298 ++++++++++++++++--------
 8 files changed, 215 insertions(+), 151 deletions(-)

diff --git a/crates/core_arch/rustfmt.toml b/crates/core_arch/rustfmt.toml
index 4ae742ba8d..e69de29bb2 100644
--- a/crates/core_arch/rustfmt.toml
+++ b/crates/core_arch/rustfmt.toml
@@ -1,3 +0,0 @@
-ignore = [
-    "src/simd.rs",
-]
diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 5bedefe42d..d69089b95b 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -37,7 +37,8 @@
     avx10_target_feature,
     const_trait_impl,
     const_cmp,
-    const_eval_select
+    const_eval_select,
+    maybe_uninit_as_bytes
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]
@@ -87,4 +88,4 @@ pub mod arch {
 }
 
 #[allow(unused_imports)]
-use core::{array, convert, ffi, fmt, hint, intrinsics, marker, mem, ops, ptr, sync};
+use core::{array, cmp, convert, ffi, fmt, hint, intrinsics, marker, mem, ops, ptr, sync};
diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 1030d7e974..849297b1fc 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -135,6 +135,22 @@ macro_rules! types {
                 crate::core_arch::simd::debug_simd_finish(f, stringify!($name), self.as_array())
             }
         }
+
+        $(#[$stability])+
+        impl crate::convert::From<crate::core_arch::simd::Simd<$elem_type, $len>> for $name {
+            #[inline(always)]
+            fn from(simd: crate::core_arch::simd::Simd<$elem_type, $len>) -> Self {
+                unsafe { crate::mem::transmute(simd) }
+            }
+        }
+
+        $(#[$stability])+
+        impl crate::convert::From<$name> for crate::core_arch::simd::Simd<$elem_type, $len> {
+            #[inline(always)]
+            fn from(simd: $name) -> Self {
+                unsafe { crate::mem::transmute(simd) }
+            }
+        }
     )*);
 }
 
diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index a7bbf35ed8..37b557c3b2 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -364,8 +364,6 @@ unsafe extern "C" {
     fn vrfin(a: vector_float) -> vector_float;
 }
 
-impl_from! { i8x16, u8x16,  i16x8, u16x8, i32x4, u32x4, f32x4 }
-
 impl_neg! { i8x16 : 0 }
 impl_neg! { i16x8 : 0 }
 impl_neg! { i32x4 : 0 }
diff --git a/crates/core_arch/src/powerpc/macros.rs b/crates/core_arch/src/powerpc/macros.rs
index 24d86f1018..6097ca31ad 100644
--- a/crates/core_arch/src/powerpc/macros.rs
+++ b/crates/core_arch/src/powerpc/macros.rs
@@ -274,25 +274,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_from {
-    ($s: ident) => {
-        #[unstable(feature = "stdarch_powerpc", issue = "111145")]
-        impl From<$s> for s_t_l!($s) {
-            #[inline]
-            fn from (v: $s) -> Self {
-                unsafe {
-                    transmute(v)
-                }
-            }
-        }
-    };
-    ($($s: ident),*) => {
-        $(
-            impl_from! { $s }
-        )*
-    };
-}
-
 macro_rules! impl_neg {
     ($s: ident : $zero: expr) => {
         #[unstable(feature = "stdarch_powerpc", issue = "111145")]
@@ -306,7 +287,6 @@ macro_rules! impl_neg {
     };
 }
 
-pub(crate) use impl_from;
 pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use s_t_l;
diff --git a/crates/core_arch/src/s390x/macros.rs b/crates/core_arch/src/s390x/macros.rs
index 26afbaa45a..b72560396c 100644
--- a/crates/core_arch/src/s390x/macros.rs
+++ b/crates/core_arch/src/s390x/macros.rs
@@ -431,25 +431,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_from {
-    ($s: ident) => {
-        #[unstable(feature = "stdarch_s390x", issue = "135681")]
-        impl From<$s> for s_t_l!($s) {
-            #[inline]
-            fn from (v: $s) -> Self {
-                unsafe {
-                    transmute(v)
-                }
-            }
-        }
-    };
-    ($($s: ident),*) => {
-        $(
-            impl_from! { $s }
-        )*
-    };
-}
-
 macro_rules! impl_neg {
     ($s: ident : $zero: expr) => {
         #[unstable(feature = "stdarch_s390x", issue = "135681")]
@@ -463,7 +444,6 @@ macro_rules! impl_neg {
     };
 }
 
-pub(crate) use impl_from;
 pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use l_t_t;
diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 1366b5c782..d63f37eeb9 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -283,8 +283,6 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
 }
 
-impl_from! { i8x16, u8x16,  i16x8, u16x8, i32x4, u32x4, i64x2, u64x2, f32x4, f64x2 }
-
 impl_neg! { i8x16 : 0 }
 impl_neg! { i16x8 : 0 }
 impl_neg! { i32x4 : 0 }
diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index b9dbde7597..926163ac4c 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -16,129 +16,223 @@ pub(crate) const unsafe fn simd_imin<T: Copy>(a: T, b: T) -> T {
     crate::intrinsics::simd::simd_select(mask, a, b)
 }
 
+/// SAFETY: All bits patterns must be valid
+pub(crate) unsafe trait SimdElement:
+    Copy + const PartialEq + crate::fmt::Debug
+{
+}
+
+unsafe impl SimdElement for u8 {}
+unsafe impl SimdElement for u16 {}
+unsafe impl SimdElement for u32 {}
+unsafe impl SimdElement for u64 {}
+
+unsafe impl SimdElement for i8 {}
+unsafe impl SimdElement for i16 {}
+unsafe impl SimdElement for i32 {}
+unsafe impl SimdElement for i64 {}
+
+unsafe impl SimdElement for f16 {}
+unsafe impl SimdElement for f32 {}
+unsafe impl SimdElement for f64 {}
+
+#[repr(simd)]
+#[derive(Copy)]
+pub(crate) struct Simd<T: SimdElement, const N: usize>([T; N]);
+
+impl<T: SimdElement, const N: usize> Simd<T, N> {
+    /// A value of this type where all elements are zeroed out.
+    // SAFETY: `T` implements `SimdElement`, so it is zeroable.
+    pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() };
+
+    #[inline(always)]
+    pub(crate) const fn from_array(elements: [T; N]) -> Self {
+        Self(elements)
+    }
+
+    // FIXME: Workaround rust@60637
+    #[inline(always)]
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub(crate) const fn splat(value: T) -> Self {
+        let one = Simd([value]);
+        // SAFETY: 0 is always in-bounds because we're shuffling
+        // a simd type with exactly one element.
+        unsafe { simd_shuffle!(one, one, [0; N]) }
+    }
+
+    /// Extract the element at position `index`.
+    /// `index` is not a constant so this is not efficient!
+    /// Use for testing only.
+    // FIXME: Workaround rust@60637
+    #[inline(always)]
+    pub(crate) const fn extract(&self, index: usize) -> T {
+        self.as_array()[index]
+    }
+
+    #[inline]
+    pub(crate) const fn as_array(&self) -> &[T; N] {
+        let simd_ptr: *const Self = self;
+        let array_ptr: *const [T; N] = simd_ptr.cast();
+        // SAFETY: We can always read the prefix of a simd type as an array.
+        // There might be more padding afterwards for some widths, but
+        // that's not a problem for reading less than that.
+        unsafe { &*array_ptr }
+    }
+}
+
+// `#[derive(Clone)]` causes ICE "Projecting into SIMD type core_arch::simd::Simd is banned by MCP#838"
+impl<T: SimdElement, const N: usize> Clone for Simd<T, N> {
+    #[inline]
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+impl<T: SimdElement, const N: usize> const crate::cmp::PartialEq for Simd<T, N> {
+    #[inline]
+    fn eq(&self, other: &Self) -> bool {
+        self.as_array() == other.as_array()
+    }
+}
+
+impl<T: SimdElement, const N: usize> crate::fmt::Debug for Simd<T, N> {
+    #[inline]
+    fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result {
+        debug_simd_finish(f, "Simd", self.as_array())
+    }
+}
+
+impl<const N: usize> Simd<f16, N> {
+    #[inline]
+    pub(crate) const fn to_bits(self) -> Simd<u16, N> {
+        assert!(size_of::<Self>() == size_of::<Simd<u16, N>>());
+        unsafe { crate::mem::transmute_copy(&self) }
+    }
+
+    #[inline]
+    pub(crate) const fn from_bits(bits: Simd<u16, N>) -> Self {
+        assert!(size_of::<Self>() == size_of::<Simd<u16, N>>());
+        unsafe { crate::mem::transmute_copy(&bits) }
+    }
+}
+
+impl<const N: usize> Simd<f32, N> {
+    #[inline]
+    pub(crate) const fn to_bits(self) -> Simd<u32, N> {
+        assert!(size_of::<Self>() == size_of::<Simd<u32, N>>());
+        unsafe { crate::mem::transmute_copy(&self) }
+    }
+
+    #[inline]
+    pub(crate) const fn from_bits(bits: Simd<u32, N>) -> Self {
+        assert!(size_of::<Self>() == size_of::<Simd<u32, N>>());
+        unsafe { crate::mem::transmute_copy(&bits) }
+    }
+}
+
+impl<const N: usize> Simd<f64, N> {
+    #[inline]
+    pub(crate) const fn to_bits(self) -> Simd<u64, N> {
+        assert!(size_of::<Self>() == size_of::<Simd<u64, N>>());
+        unsafe { crate::mem::transmute_copy(&self) }
+    }
+
+    #[inline]
+    pub(crate) const fn from_bits(bits: Simd<u64, N>) -> Self {
+        assert!(size_of::<Self>() == size_of::<Simd<u64, N>>());
+        unsafe { crate::mem::transmute_copy(&bits) }
+    }
+}
+
 macro_rules! simd_ty {
     ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => {
-        #[repr(simd)]
-        #[derive(Copy, Clone)]
-        pub(crate) struct $id([$elem_type; $len]);
+        pub(crate) type $id = Simd<$elem_type, $len>;
 
-        #[allow(clippy::use_self)]
         impl $id {
-            /// A value of this type where all elements are zeroed out.
-            pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() };
-
             #[inline(always)]
             pub(crate) const fn new($($param_name: $elem_type),*) -> Self {
-                $id([$($param_name),*])
-            }
-            #[inline(always)]
-            pub(crate) const fn from_array(elements: [$elem_type; $len]) -> Self {
-                $id(elements)
-            }
-            // FIXME: Workaround rust@60637
-            #[inline(always)]
-            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-            pub(crate) const fn splat(value: $elem_type) -> Self {
-                #[derive(Copy, Clone)]
-                #[repr(simd)]
-                struct JustOne([$elem_type; 1]);
-                let one = JustOne([value]);
-                // SAFETY: 0 is always in-bounds because we're shuffling
-                // a simd type with exactly one element.
-                unsafe { simd_shuffle!(one, one, [0; $len]) }
+                Self([$($param_name),*])
             }
+        }
+    }
+}
 
-            /// Extract the element at position `index`.
-            /// `index` is not a constant so this is not efficient!
-            /// Use for testing only.
-            // FIXME: Workaround rust@60637
-            #[inline(always)]
-            pub(crate) const fn extract(&self, index: usize) -> $elem_type {
-                self.as_array()[index]
-            }
+#[repr(simd)]
+#[derive(Copy)]
+pub(crate) struct SimdM<T: SimdElement, const N: usize>([T; N]);
 
-            #[inline]
-            pub(crate) const fn as_array(&self) -> &[$elem_type; $len] {
-                let simd_ptr: *const Self = self;
-                let array_ptr: *const [$elem_type; $len] = simd_ptr.cast();
-                // SAFETY: We can always read the prefix of a simd type as an array.
-                // There might be more padding afterwards for some widths, but
-                // that's not a problem for reading less than that.
-                unsafe { &*array_ptr }
+impl<T: SimdElement, const N: usize> SimdM<T, N> {
+    #[inline(always)]
+    const fn bool_to_internal(x: bool) -> T {
+        // SAFETY: `T` implements `SimdElement`, so all bit patterns are valid.
+        let zeros = const { unsafe { crate::mem::zeroed::<T>() } };
+        let ones = const {
+            // Ideally, this would be `transmute([0xFFu8; size_of::<T>()])`, but
+            // `size_of::<T>()` is not allowed to use a generic parameter there.
+            let mut r = crate::mem::MaybeUninit::<T>::uninit();
+            let mut i = 0;
+            while i < crate::mem::size_of::<T>() {
+                r.as_bytes_mut()[i] = crate::mem::MaybeUninit::new(0xFF);
+                i += 1;
             }
-        }
+            unsafe { r.assume_init() }
+        };
+        [zeros, ones][x as usize]
+    }
 
-        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-        const impl core::cmp::PartialEq for $id {
-            #[inline]
-            fn eq(&self, other: &Self) -> bool {
-                self.as_array() == other.as_array()
-            }
-        }
+    // FIXME: Workaround rust@60637
+    #[inline(always)]
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub(crate) const fn splat(value: bool) -> Self {
+        let one = SimdM([Self::bool_to_internal(value)]);
+        // SAFETY: 0 is always in-bounds because we're shuffling
+        // a simd type with exactly one element.
+        unsafe { simd_shuffle!(one, one, [0; N]) }
+    }
 
-        impl core::fmt::Debug for $id {
-            #[inline]
-            fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-                debug_simd_finish(f, stringify!($id), self.as_array())
-            }
-        }
+    #[inline]
+    pub(crate) const fn as_array(&self) -> &[T; N] {
+        let simd_ptr: *const Self = self;
+        let array_ptr: *const [T; N] = simd_ptr.cast();
+        // SAFETY: We can always read the prefix of a simd type as an array.
+        // There might be more padding afterwards for some widths, but
+        // that's not a problem for reading less than that.
+        unsafe { &*array_ptr }
+    }
+}
+
+// `#[derive(Clone)]` causes ICE "Projecting into SIMD type core_arch::simd::SimdM is banned by MCP#838"
+impl<T: SimdElement, const N: usize> Clone for SimdM<T, N> {
+    #[inline]
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+impl<T: SimdElement, const N: usize> const crate::cmp::PartialEq for SimdM<T, N> {
+    #[inline]
+    fn eq(&self, other: &Self) -> bool {
+        self.as_array() == other.as_array()
+    }
+}
+
+impl<T: SimdElement, const N: usize> crate::fmt::Debug for SimdM<T, N> {
+    #[inline]
+    fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result {
+        debug_simd_finish(f, "SimdM", self.as_array())
     }
 }
 
 macro_rules! simd_m_ty {
     ($id:ident [$elem_type:ident ; $len:literal]: $($param_name:ident),*) => {
-        #[repr(simd)]
-        #[derive(Copy, Clone)]
-        pub(crate) struct $id([$elem_type; $len]);
+        pub(crate) type $id  = SimdM<$elem_type, $len>;
 
-        #[allow(clippy::use_self)]
         impl $id {
-            #[inline(always)]
-            const fn bool_to_internal(x: bool) -> $elem_type {
-                [0 as $elem_type, !(0 as $elem_type)][x as usize]
-            }
-
             #[inline(always)]
             pub(crate) const fn new($($param_name: bool),*) -> Self {
-                $id([$(Self::bool_to_internal($param_name)),*])
-            }
-
-            // FIXME: Workaround rust@60637
-            #[inline(always)]
-            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-            pub(crate) const fn splat(value: bool) -> Self {
-                #[derive(Copy, Clone)]
-                #[repr(simd)]
-                struct JustOne([$elem_type; 1]);
-                let one = JustOne([Self::bool_to_internal(value)]);
-                // SAFETY: 0 is always in-bounds because we're shuffling
-                // a simd type with exactly one element.
-                unsafe { simd_shuffle!(one, one, [0; $len]) }
-            }
-
-            #[inline]
-            pub(crate) const fn as_array(&self) -> &[$elem_type; $len] {
-                let simd_ptr: *const Self = self;
-                let array_ptr: *const [$elem_type; $len] = simd_ptr.cast();
-                // SAFETY: We can always read the prefix of a simd type as an array.
-                // There might be more padding afterwards for some widths, but
-                // that's not a problem for reading less than that.
-                unsafe { &*array_ptr }
-            }
-        }
-
-        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-        const impl core::cmp::PartialEq for $id {
-            #[inline]
-            fn eq(&self, other: &Self) -> bool {
-                self.as_array() == other.as_array()
-            }
-        }
-
-        impl core::fmt::Debug for $id {
-            #[inline]
-            fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-                debug_simd_finish(f, stringify!($id), self.as_array())
+                Self([$(Self::bool_to_internal($param_name)),*])
             }
         }
     }

From 89037d316924327a7231acb5e93ae33e8af092ee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Thu, 1 Jan 2026 22:48:01 +0100
Subject: [PATCH 091/326] x86: avoid using `transmute` in some tests

---
 crates/core_arch/src/x86/sse.rs  | 266 +++++++++++++++----------------
 crates/core_arch/src/x86/sse2.rs |  38 ++---
 2 files changed, 150 insertions(+), 154 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 751f969e50..f167e8381d 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2079,7 +2079,7 @@ pub unsafe fn _mm_stream_ps(mem_addr: *mut f32, a: __m128) {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
-    use crate::{hint::black_box, mem::transmute, ptr};
+    use crate::{hint::black_box, ptr};
     use std::boxed;
     use stdarch_test::simd_test;
 
@@ -2221,7 +2221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_min_ps() {
+    fn test_mm_min_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_min_ps(a, b);
@@ -2234,10 +2234,10 @@ mod tests {
         // `r1` to `a` and `r2` to `b`.
         let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0);
         let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0);
-        let r1: [u8; 16] = transmute(_mm_min_ps(a, b));
-        let r2: [u8; 16] = transmute(_mm_min_ps(b, a));
-        let a: [u8; 16] = transmute(a);
-        let b: [u8; 16] = transmute(b);
+        let r1 = _mm_min_ps(a, b).as_f32x4().to_bits();
+        let r2 = _mm_min_ps(b, a).as_f32x4().to_bits();
+        let a = a.as_f32x4().to_bits();
+        let b = b.as_f32x4().to_bits();
         assert_eq!(r1, b);
         assert_eq!(r2, a);
         assert_ne!(a, b); // sanity check that -0.0 is actually present
@@ -2252,7 +2252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_max_ps() {
+    fn test_mm_max_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_max_ps(a, b);
@@ -2261,67 +2261,67 @@ mod tests {
         // Check SSE-specific semantics for -0.0 handling.
         let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0);
         let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0);
-        let r1: [u8; 16] = transmute(_mm_max_ps(a, b));
-        let r2: [u8; 16] = transmute(_mm_max_ps(b, a));
-        let a: [u8; 16] = transmute(a);
-        let b: [u8; 16] = transmute(b);
+        let r1 = _mm_max_ps(a, b).as_f32x4().to_bits();
+        let r2 = _mm_max_ps(b, a).as_f32x4().to_bits();
+        let a = a.as_f32x4().to_bits();
+        let b = b.as_f32x4().to_bits();
         assert_eq!(r1, b);
         assert_eq!(r2, a);
         assert_ne!(a, b); // sanity check that -0.0 is actually present
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_and_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_and_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_and_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0001));
+        let e = f32x4::from_bits(u32x4::splat(0b0001)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_andnot_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_andnot_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_andnot_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0100));
+        let e = f32x4::from_bits(u32x4::splat(0b0100)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_or_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_or_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_or_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0111));
+        let e = f32x4::from_bits(u32x4::splat(0b0111)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_xor_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_xor_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_xor_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0110));
+        let e = f32x4::from_bits(u32x4::splat(0b0110)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpeq_ss() {
+    fn test_mm_cmpeq_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(-1.0, 5.0, 6.0, 7.0);
-        let r: u32x4 = transmute(_mm_cmpeq_ss(a, b));
-        let e: u32x4 = transmute(_mm_setr_ps(f32::from_bits(0), 2.0, 3.0, 4.0));
+        let r = _mm_cmpeq_ss(a, b).as_f32x4().to_bits();
+        let e = f32x4::new(f32::from_bits(0), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(r, e);
 
         let b2 = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
-        let r2: u32x4 = transmute(_mm_cmpeq_ss(a, b2));
-        let e2: u32x4 = transmute(_mm_setr_ps(f32::from_bits(0xffffffff), 2.0, 3.0, 4.0));
+        let r2 = _mm_cmpeq_ss(a, b2).as_f32x4().to_bits();
+        let e2 = f32x4::new(f32::from_bits(0xffffffff), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(r2, e2);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmplt_ss() {
+    fn test_mm_cmplt_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2331,21 +2331,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) < c.extract(0)
         let d1 = !0u32; // a.extract(0) < d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmplt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmplt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmplt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmplt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmplt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmplt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmple_ss() {
+    fn test_mm_cmple_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2355,21 +2355,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) <= c.extract(0)
         let d1 = !0u32; // a.extract(0) <= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmple_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmple_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmple_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmple_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmple_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmple_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpgt_ss() {
+    fn test_mm_cmpgt_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2379,21 +2379,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) > c.extract(0)
         let d1 = 0u32; // a.extract(0) > d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpgt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpgt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpgt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpgt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpgt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpgt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpge_ss() {
+    fn test_mm_cmpge_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2403,21 +2403,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) >= c.extract(0)
         let d1 = 0u32; // a.extract(0) >= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpge_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpge_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpge_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpge_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpge_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpge_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpneq_ss() {
+    fn test_mm_cmpneq_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2427,21 +2427,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) != c.extract(0)
         let d1 = !0u32; // a.extract(0) != d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpneq_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpneq_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpneq_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpneq_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpneq_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpneq_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnlt_ss() {
+    fn test_mm_cmpnlt_ss() {
         // TODO: this test is exactly the same as for `_mm_cmpge_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence of NaNs (signaling or quiet). If so, we should add tests
@@ -2456,21 +2456,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) >= c.extract(0)
         let d1 = 0u32; // a.extract(0) >= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpnlt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpnlt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpnlt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpnlt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpnlt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpnlt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnle_ss() {
+    fn test_mm_cmpnle_ss() {
         // TODO: this test is exactly the same as for `_mm_cmpgt_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence
@@ -2485,21 +2485,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) > c.extract(0)
         let d1 = 0u32; // a.extract(0) > d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpnle_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpnle_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpnle_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpnle_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpnle_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpnle_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpngt_ss() {
+    fn test_mm_cmpngt_ss() {
         // TODO: this test is exactly the same as for `_mm_cmple_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence of NaNs (signaling or quiet). If so, we should add tests
@@ -2514,21 +2514,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) <= c.extract(0)
         let d1 = !0u32; // a.extract(0) <= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpngt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpngt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpngt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpngt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpngt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpngt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnge_ss() {
+    fn test_mm_cmpnge_ss() {
         // TODO: this test is exactly the same as for `_mm_cmplt_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence of NaNs (signaling or quiet). If so, we should add tests
@@ -2543,21 +2543,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) < c.extract(0)
         let d1 = !0u32; // a.extract(0) < d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpnge_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpnge_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpnge_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpnge_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpnge_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpnge_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpord_ss() {
+    fn test_mm_cmpord_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(NAN, 5.0, 6.0, 7.0);
@@ -2567,21 +2567,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) ord c.extract(0)
         let d1 = !0u32; // a.extract(0) ord d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpord_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpord_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpord_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpord_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpord_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpord_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpunord_ss() {
+    fn test_mm_cmpunord_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(NAN, 5.0, 6.0, 7.0);
@@ -2591,160 +2591,160 @@ mod tests {
         let c1 = !0u32; // a.extract(0) unord c.extract(0)
         let d1 = 0u32; // a.extract(0) unord d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpunord_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpunord_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpunord_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpunord_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpunord_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpunord_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpeq_ps() {
+    fn test_mm_cmpeq_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, fls, tru, fls);
-        let r: u32x4 = transmute(_mm_cmpeq_ps(a, b));
+        let r = _mm_cmpeq_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmplt_ps() {
+    fn test_mm_cmplt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, fls, fls);
-        let r: u32x4 = transmute(_mm_cmplt_ps(a, b));
+        let r = _mm_cmplt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmple_ps() {
+    fn test_mm_cmple_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, 4.0);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, tru, fls);
-        let r: u32x4 = transmute(_mm_cmple_ps(a, b));
+        let r = _mm_cmple_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpgt_ps() {
+    fn test_mm_cmpgt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 42.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, fls, fls);
-        let r: u32x4 = transmute(_mm_cmpgt_ps(a, b));
+        let r = _mm_cmpgt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpge_ps() {
+    fn test_mm_cmpge_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 42.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, tru, fls);
-        let r: u32x4 = transmute(_mm_cmpge_ps(a, b));
+        let r = _mm_cmpge_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpneq_ps() {
+    fn test_mm_cmpneq_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, tru, fls, tru);
-        let r: u32x4 = transmute(_mm_cmpneq_ps(a, b));
+        let r = _mm_cmpneq_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnlt_ps() {
+    fn test_mm_cmpnlt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, tru, tru);
-        let r: u32x4 = transmute(_mm_cmpnlt_ps(a, b));
+        let r = _mm_cmpnlt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnle_ps() {
+    fn test_mm_cmpnle_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, fls, tru);
-        let r: u32x4 = transmute(_mm_cmpnle_ps(a, b));
+        let r = _mm_cmpnle_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpngt_ps() {
+    fn test_mm_cmpngt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, tru, tru);
-        let r: u32x4 = transmute(_mm_cmpngt_ps(a, b));
+        let r = _mm_cmpngt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnge_ps() {
+    fn test_mm_cmpnge_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, fls, tru);
-        let r: u32x4 = transmute(_mm_cmpnge_ps(a, b));
+        let r = _mm_cmpnge_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpord_ps() {
+    fn test_mm_cmpord_ps() {
         let a = _mm_setr_ps(10.0, 50.0, NAN, NAN);
         let b = _mm_setr_ps(15.0, NAN, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, fls, fls);
-        let r: u32x4 = transmute(_mm_cmpord_ps(a, b));
+        let r = _mm_cmpord_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpunord_ps() {
+    fn test_mm_cmpunord_ps() {
         let a = _mm_setr_ps(10.0, 50.0, NAN, NAN);
         let b = _mm_setr_ps(15.0, NAN, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, tru, tru);
-        let r: u32x4 = transmute(_mm_cmpunord_ps(a, b));
+        let r = _mm_cmpunord_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index d7ac00287f..0850d05445 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -3272,11 +3272,7 @@ mod tests {
         core_arch::{simd::*, x86::*},
         hint::black_box,
     };
-    use std::{
-        boxed, f32, f64,
-        mem::{self, transmute},
-        ptr,
-    };
+    use std::{boxed, f32, f64, mem, ptr};
     use stdarch_test::simd_test;
 
     const NAN: f64 = f64::NAN;
@@ -4585,38 +4581,38 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_and_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_and_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_and_pd(a, b);
-        let e = transmute(u64x2::splat(1));
+        let e = f64x2::from_bits(u64x2::splat(1)).as_m128d();
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_andnot_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_andnot_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_andnot_pd(a, b);
-        let e = transmute(u64x2::splat(2));
+        let e = f64x2::from_bits(u64x2::splat(2)).as_m128d();
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_or_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_or_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_or_pd(a, b);
-        let e = transmute(u64x2::splat(7));
+        let e = f64x2::from_bits(u64x2::splat(7)).as_m128d();
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_xor_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_xor_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_xor_pd(a, b);
-        let e = transmute(u64x2::splat(6));
+        let e = f64x2::from_bits(u64x2::splat(6)).as_m128d();
         assert_eq_m128d(r, e);
     }
 

From a2908735db13a9ce498066ff96f123beb9d3df6e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Thu, 1 Jan 2026 22:48:34 +0100
Subject: [PATCH 092/326] arm_shared: avoid using `transmute` and `unsafe fn`
 in tests

---
 ci/run.sh                                     |    2 +-
 .../src/arm_shared/neon/load_tests.rs         |   97 +-
 crates/core_arch/src/arm_shared/neon/mod.rs   | 1975 ++++++++++-------
 .../src/arm_shared/neon/store_tests.rs        |  144 +-
 .../src/arm_shared/neon/table_lookup_tests.rs |   27 +-
 .../core_arch/src/arm_shared/test_support.rs  |    8 +-
 crates/simd-test-macro/src/lib.rs             |   47 +-
 7 files changed, 1308 insertions(+), 992 deletions(-)

diff --git a/ci/run.sh b/ci/run.sh
index bb3dcf93e7..8a0b5fa26f 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -40,7 +40,7 @@ case ${TARGET} in
 	export RUSTFLAGS="${RUSTFLAGS} -C llvm-args=-fast-isel=false"
 	;;
     armv7-*eabihf | thumbv7-*eabihf)
-        export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon"
+        export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon,+fp16"
         ;;
     amdgcn-*)
         export RUSTFLAGS="${RUSTFLAGS} -Ctarget-cpu=gfx1200"
diff --git a/crates/core_arch/src/arm_shared/neon/load_tests.rs b/crates/core_arch/src/arm_shared/neon/load_tests.rs
index bdf511ecf8..cc821b4af2 100644
--- a/crates/core_arch/src/arm_shared/neon/load_tests.rs
+++ b/crates/core_arch/src/arm_shared/neon/load_tests.rs
@@ -13,194 +13,195 @@ use crate::core_arch::aarch64::*;
 use crate::core_arch::simd::*;
 use std::mem;
 use stdarch_test::simd_test;
+
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s8() {
+fn test_vld1_s8() {
     let a: [i8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: i8x8 = transmute(vld1_s8(a[1..].as_ptr()));
+    let r = unsafe { i8x8::from(vld1_s8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s8() {
+fn test_vld1q_s8() {
     let a: [i8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
     let e = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-    let r: i8x16 = transmute(vld1q_s8(a[1..].as_ptr()));
+    let r = unsafe { i8x16::from(vld1q_s8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s16() {
+fn test_vld1_s16() {
     let a: [i16; 5] = [0, 1, 2, 3, 4];
     let e = i16x4::new(1, 2, 3, 4);
-    let r: i16x4 = transmute(vld1_s16(a[1..].as_ptr()));
+    let r = unsafe { i16x4::from(vld1_s16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s16() {
+fn test_vld1q_s16() {
     let a: [i16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: i16x8 = transmute(vld1q_s16(a[1..].as_ptr()));
+    let r = unsafe { i16x8::from(vld1q_s16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s32() {
+fn test_vld1_s32() {
     let a: [i32; 3] = [0, 1, 2];
     let e = i32x2::new(1, 2);
-    let r: i32x2 = transmute(vld1_s32(a[1..].as_ptr()));
+    let r = unsafe { i32x2::from(vld1_s32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s32() {
+fn test_vld1q_s32() {
     let a: [i32; 5] = [0, 1, 2, 3, 4];
     let e = i32x4::new(1, 2, 3, 4);
-    let r: i32x4 = transmute(vld1q_s32(a[1..].as_ptr()));
+    let r = unsafe { i32x4::from(vld1q_s32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s64() {
+fn test_vld1_s64() {
     let a: [i64; 2] = [0, 1];
     let e = i64x1::new(1);
-    let r: i64x1 = transmute(vld1_s64(a[1..].as_ptr()));
+    let r = unsafe { i64x1::from(vld1_s64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s64() {
+fn test_vld1q_s64() {
     let a: [i64; 3] = [0, 1, 2];
     let e = i64x2::new(1, 2);
-    let r: i64x2 = transmute(vld1q_s64(a[1..].as_ptr()));
+    let r = unsafe { i64x2::from(vld1q_s64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u8() {
+fn test_vld1_u8() {
     let a: [u8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u8x8 = transmute(vld1_u8(a[1..].as_ptr()));
+    let r = unsafe { u8x8::from(vld1_u8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u8() {
+fn test_vld1q_u8() {
     let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
     let e = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-    let r: u8x16 = transmute(vld1q_u8(a[1..].as_ptr()));
+    let r = unsafe { u8x16::from(vld1q_u8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u16() {
+fn test_vld1_u16() {
     let a: [u16; 5] = [0, 1, 2, 3, 4];
     let e = u16x4::new(1, 2, 3, 4);
-    let r: u16x4 = transmute(vld1_u16(a[1..].as_ptr()));
+    let r = unsafe { u16x4::from(vld1_u16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u16() {
+fn test_vld1q_u16() {
     let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u16x8 = transmute(vld1q_u16(a[1..].as_ptr()));
+    let r = unsafe { u16x8::from(vld1q_u16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u32() {
+fn test_vld1_u32() {
     let a: [u32; 3] = [0, 1, 2];
     let e = u32x2::new(1, 2);
-    let r: u32x2 = transmute(vld1_u32(a[1..].as_ptr()));
+    let r = unsafe { u32x2::from(vld1_u32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u32() {
+fn test_vld1q_u32() {
     let a: [u32; 5] = [0, 1, 2, 3, 4];
     let e = u32x4::new(1, 2, 3, 4);
-    let r: u32x4 = transmute(vld1q_u32(a[1..].as_ptr()));
+    let r = unsafe { u32x4::from(vld1q_u32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u64() {
+fn test_vld1_u64() {
     let a: [u64; 2] = [0, 1];
     let e = u64x1::new(1);
-    let r: u64x1 = transmute(vld1_u64(a[1..].as_ptr()));
+    let r = unsafe { u64x1::from(vld1_u64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u64() {
+fn test_vld1q_u64() {
     let a: [u64; 3] = [0, 1, 2];
     let e = u64x2::new(1, 2);
-    let r: u64x2 = transmute(vld1q_u64(a[1..].as_ptr()));
+    let r = unsafe { u64x2::from(vld1q_u64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_p8() {
+fn test_vld1_p8() {
     let a: [p8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u8x8 = transmute(vld1_p8(a[1..].as_ptr()));
+    let r = unsafe { u8x8::from(vld1_p8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_p8() {
+fn test_vld1q_p8() {
     let a: [p8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
     let e = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-    let r: u8x16 = transmute(vld1q_p8(a[1..].as_ptr()));
+    let r = unsafe { u8x16::from(vld1q_p8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_p16() {
+fn test_vld1_p16() {
     let a: [p16; 5] = [0, 1, 2, 3, 4];
     let e = u16x4::new(1, 2, 3, 4);
-    let r: u16x4 = transmute(vld1_p16(a[1..].as_ptr()));
+    let r = unsafe { u16x4::from(vld1_p16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_p16() {
+fn test_vld1q_p16() {
     let a: [p16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u16x8 = transmute(vld1q_p16(a[1..].as_ptr()));
+    let r = unsafe { u16x8::from(vld1q_p16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vld1_p64() {
+fn test_vld1_p64() {
     let a: [p64; 2] = [0, 1];
     let e = u64x1::new(1);
-    let r: u64x1 = transmute(vld1_p64(a[1..].as_ptr()));
+    let r = unsafe { u64x1::from(vld1_p64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vld1q_p64() {
+fn test_vld1q_p64() {
     let a: [p64; 3] = [0, 1, 2];
     let e = u64x2::new(1, 2);
-    let r: u64x2 = transmute(vld1q_p64(a[1..].as_ptr()));
+    let r = unsafe { u64x2::from(vld1q_p64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_f32() {
+fn test_vld1_f32() {
     let a: [f32; 3] = [0., 1., 2.];
     let e = f32x2::new(1., 2.);
-    let r: f32x2 = transmute(vld1_f32(a[1..].as_ptr()));
+    let r = unsafe { f32x2::from(vld1_f32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_f32() {
+fn test_vld1q_f32() {
     let a: [f32; 5] = [0., 1., 2., 3., 4.];
     let e = f32x4::new(1., 2., 3., 4.);
-    let r: f32x4 = transmute(vld1q_f32(a[1..].as_ptr()));
+    let r = unsafe { f32x4::from(vld1q_f32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index 809892e0bf..1ca8ce2b13 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -1247,1268 +1247,1273 @@ mod tests {
     use crate::core_arch::arm::*;
     use crate::core_arch::arm_shared::test_support::*;
     use crate::core_arch::simd::*;
-    use std::{mem::transmute, vec::Vec};
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s8() {
+    fn test_vld1_lane_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: i8 = 42;
         let e = i8x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: i8x8 = transmute(vld1_lane_s8::<7>(&elem, transmute(a)));
+        let r = unsafe { i8x8::from(vld1_lane_s8::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s8() {
+    fn test_vld1q_lane_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let elem: i8 = 42;
         let e = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 42);
-        let r: i8x16 = transmute(vld1q_lane_s8::<15>(&elem, transmute(a)));
+        let r = unsafe { i8x16::from(vld1q_lane_s8::<15>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s16() {
+    fn test_vld1_lane_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let elem: i16 = 42;
         let e = i16x4::new(0, 1, 2, 42);
-        let r: i16x4 = transmute(vld1_lane_s16::<3>(&elem, transmute(a)));
+        let r = unsafe { i16x4::from(vld1_lane_s16::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s16() {
+    fn test_vld1q_lane_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: i16 = 42;
         let e = i16x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: i16x8 = transmute(vld1q_lane_s16::<7>(&elem, transmute(a)));
+        let r = unsafe { i16x8::from(vld1q_lane_s16::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s32() {
+    fn test_vld1_lane_s32() {
         let a = i32x2::new(0, 1);
         let elem: i32 = 42;
         let e = i32x2::new(0, 42);
-        let r: i32x2 = transmute(vld1_lane_s32::<1>(&elem, transmute(a)));
+        let r = unsafe { i32x2::from(vld1_lane_s32::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s32() {
+    fn test_vld1q_lane_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let elem: i32 = 42;
         let e = i32x4::new(0, 1, 2, 42);
-        let r: i32x4 = transmute(vld1q_lane_s32::<3>(&elem, transmute(a)));
+        let r = unsafe { i32x4::from(vld1q_lane_s32::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s64() {
+    fn test_vld1_lane_s64() {
         let a = i64x1::new(0);
         let elem: i64 = 42;
         let e = i64x1::new(42);
-        let r: i64x1 = transmute(vld1_lane_s64::<0>(&elem, transmute(a)));
+        let r = unsafe { i64x1::from(vld1_lane_s64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s64() {
+    fn test_vld1q_lane_s64() {
         let a = i64x2::new(0, 1);
         let elem: i64 = 42;
         let e = i64x2::new(0, 42);
-        let r: i64x2 = transmute(vld1q_lane_s64::<1>(&elem, transmute(a)));
+        let r = unsafe { i64x2::from(vld1q_lane_s64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u8() {
+    fn test_vld1_lane_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: u8 = 42;
         let e = u8x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u8x8 = transmute(vld1_lane_u8::<7>(&elem, transmute(a)));
+        let r = unsafe { u8x8::from(vld1_lane_u8::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u8() {
+    fn test_vld1q_lane_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let elem: u8 = 42;
         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 42);
-        let r: u8x16 = transmute(vld1q_lane_u8::<15>(&elem, transmute(a)));
+        let r = unsafe { u8x16::from(vld1q_lane_u8::<15>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u16() {
+    fn test_vld1_lane_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let elem: u16 = 42;
         let e = u16x4::new(0, 1, 2, 42);
-        let r: u16x4 = transmute(vld1_lane_u16::<3>(&elem, transmute(a)));
+        let r = unsafe { u16x4::from(vld1_lane_u16::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u16() {
+    fn test_vld1q_lane_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: u16 = 42;
         let e = u16x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u16x8 = transmute(vld1q_lane_u16::<7>(&elem, transmute(a)));
+        let r = unsafe { u16x8::from(vld1q_lane_u16::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u32() {
+    fn test_vld1_lane_u32() {
         let a = u32x2::new(0, 1);
         let elem: u32 = 42;
         let e = u32x2::new(0, 42);
-        let r: u32x2 = transmute(vld1_lane_u32::<1>(&elem, transmute(a)));
+        let r = unsafe { u32x2::from(vld1_lane_u32::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u32() {
+    fn test_vld1q_lane_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let elem: u32 = 42;
         let e = u32x4::new(0, 1, 2, 42);
-        let r: u32x4 = transmute(vld1q_lane_u32::<3>(&elem, transmute(a)));
+        let r = unsafe { u32x4::from(vld1q_lane_u32::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u64() {
+    fn test_vld1_lane_u64() {
         let a = u64x1::new(0);
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_lane_u64::<0>(&elem, transmute(a)));
+        let r = unsafe { u64x1::from(vld1_lane_u64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u64() {
+    fn test_vld1q_lane_u64() {
         let a = u64x2::new(0, 1);
         let elem: u64 = 42;
         let e = u64x2::new(0, 42);
-        let r: u64x2 = transmute(vld1q_lane_u64::<1>(&elem, transmute(a)));
+        let r = unsafe { u64x2::from(vld1q_lane_u64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_p8() {
+    fn test_vld1_lane_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: p8 = 42;
         let e = u8x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u8x8 = transmute(vld1_lane_p8::<7>(&elem, transmute(a)));
+        let r = unsafe { u8x8::from(vld1_lane_p8::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_p8() {
+    fn test_vld1q_lane_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let elem: p8 = 42;
         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 42);
-        let r: u8x16 = transmute(vld1q_lane_p8::<15>(&elem, transmute(a)));
+        let r = unsafe { u8x16::from(vld1q_lane_p8::<15>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_p16() {
+    fn test_vld1_lane_p16() {
         let a = u16x4::new(0, 1, 2, 3);
         let elem: p16 = 42;
         let e = u16x4::new(0, 1, 2, 42);
-        let r: u16x4 = transmute(vld1_lane_p16::<3>(&elem, transmute(a)));
+        let r = unsafe { u16x4::from(vld1_lane_p16::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_p16() {
+    fn test_vld1q_lane_p16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: p16 = 42;
         let e = u16x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u16x8 = transmute(vld1q_lane_p16::<7>(&elem, transmute(a)));
+        let r = unsafe { u16x8::from(vld1q_lane_p16::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_lane_p64() {
+    fn test_vld1_lane_p64() {
         let a = u64x1::new(0);
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_lane_p64::<0>(&elem, transmute(a)));
+        let r = unsafe { u64x1::from(vld1_lane_p64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_lane_p64() {
+    fn test_vld1q_lane_p64() {
         let a = u64x2::new(0, 1);
         let elem: u64 = 42;
         let e = u64x2::new(0, 42);
-        let r: u64x2 = transmute(vld1q_lane_p64::<1>(&elem, transmute(a)));
+        let r = unsafe { u64x2::from(vld1q_lane_p64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_f32() {
+    fn test_vld1_lane_f32() {
         let a = f32x2::new(0., 1.);
         let elem: f32 = 42.;
         let e = f32x2::new(0., 42.);
-        let r: f32x2 = transmute(vld1_lane_f32::<1>(&elem, transmute(a)));
+        let r = unsafe { f32x2::from(vld1_lane_f32::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_f32() {
+    fn test_vld1q_lane_f32() {
         let a = f32x4::new(0., 1., 2., 3.);
         let elem: f32 = 42.;
         let e = f32x4::new(0., 1., 2., 42.);
-        let r: f32x4 = transmute(vld1q_lane_f32::<3>(&elem, transmute(a)));
+        let r = unsafe { f32x4::from(vld1q_lane_f32::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s8() {
+    fn test_vld1_dup_s8() {
         let elem: i8 = 42;
         let e = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: i8x8 = transmute(vld1_dup_s8(&elem));
+        let r = unsafe { i8x8::from(vld1_dup_s8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s8() {
+    fn test_vld1q_dup_s8() {
         let elem: i8 = 42;
         let e = i8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: i8x16 = transmute(vld1q_dup_s8(&elem));
+        let r = unsafe { i8x16::from(vld1q_dup_s8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s16() {
+    fn test_vld1_dup_s16() {
         let elem: i16 = 42;
         let e = i16x4::new(42, 42, 42, 42);
-        let r: i16x4 = transmute(vld1_dup_s16(&elem));
+        let r = unsafe { i16x4::from(vld1_dup_s16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s16() {
+    fn test_vld1q_dup_s16() {
         let elem: i16 = 42;
         let e = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: i16x8 = transmute(vld1q_dup_s16(&elem));
+        let r = unsafe { i16x8::from(vld1q_dup_s16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s32() {
+    fn test_vld1_dup_s32() {
         let elem: i32 = 42;
         let e = i32x2::new(42, 42);
-        let r: i32x2 = transmute(vld1_dup_s32(&elem));
+        let r = unsafe { i32x2::from(vld1_dup_s32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s32() {
+    fn test_vld1q_dup_s32() {
         let elem: i32 = 42;
         let e = i32x4::new(42, 42, 42, 42);
-        let r: i32x4 = transmute(vld1q_dup_s32(&elem));
+        let r = unsafe { i32x4::from(vld1q_dup_s32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s64() {
+    fn test_vld1_dup_s64() {
         let elem: i64 = 42;
         let e = i64x1::new(42);
-        let r: i64x1 = transmute(vld1_dup_s64(&elem));
+        let r = unsafe { i64x1::from(vld1_dup_s64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s64() {
+    fn test_vld1q_dup_s64() {
         let elem: i64 = 42;
         let e = i64x2::new(42, 42);
-        let r: i64x2 = transmute(vld1q_dup_s64(&elem));
+        let r = unsafe { i64x2::from(vld1q_dup_s64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u8() {
+    fn test_vld1_dup_u8() {
         let elem: u8 = 42;
         let e = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u8x8 = transmute(vld1_dup_u8(&elem));
+        let r = unsafe { u8x8::from(vld1_dup_u8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u8() {
+    fn test_vld1q_dup_u8() {
         let elem: u8 = 42;
         let e = u8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: u8x16 = transmute(vld1q_dup_u8(&elem));
+        let r = unsafe { u8x16::from(vld1q_dup_u8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u16() {
+    fn test_vld1_dup_u16() {
         let elem: u16 = 42;
         let e = u16x4::new(42, 42, 42, 42);
-        let r: u16x4 = transmute(vld1_dup_u16(&elem));
+        let r = unsafe { u16x4::from(vld1_dup_u16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u16() {
+    fn test_vld1q_dup_u16() {
         let elem: u16 = 42;
         let e = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u16x8 = transmute(vld1q_dup_u16(&elem));
+        let r = unsafe { u16x8::from(vld1q_dup_u16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u32() {
+    fn test_vld1_dup_u32() {
         let elem: u32 = 42;
         let e = u32x2::new(42, 42);
-        let r: u32x2 = transmute(vld1_dup_u32(&elem));
+        let r = unsafe { u32x2::from(vld1_dup_u32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u32() {
+    fn test_vld1q_dup_u32() {
         let elem: u32 = 42;
         let e = u32x4::new(42, 42, 42, 42);
-        let r: u32x4 = transmute(vld1q_dup_u32(&elem));
+        let r = unsafe { u32x4::from(vld1q_dup_u32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u64() {
+    fn test_vld1_dup_u64() {
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_dup_u64(&elem));
+        let r = unsafe { u64x1::from(vld1_dup_u64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u64() {
+    fn test_vld1q_dup_u64() {
         let elem: u64 = 42;
         let e = u64x2::new(42, 42);
-        let r: u64x2 = transmute(vld1q_dup_u64(&elem));
+        let r = unsafe { u64x2::from(vld1q_dup_u64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_p8() {
+    fn test_vld1_dup_p8() {
         let elem: p8 = 42;
         let e = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u8x8 = transmute(vld1_dup_p8(&elem));
+        let r = unsafe { u8x8::from(vld1_dup_p8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_p8() {
+    fn test_vld1q_dup_p8() {
         let elem: p8 = 42;
         let e = u8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: u8x16 = transmute(vld1q_dup_p8(&elem));
+        let r = unsafe { u8x16::from(vld1q_dup_p8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_p16() {
+    fn test_vld1_dup_p16() {
         let elem: p16 = 42;
         let e = u16x4::new(42, 42, 42, 42);
-        let r: u16x4 = transmute(vld1_dup_p16(&elem));
+        let r = unsafe { u16x4::from(vld1_dup_p16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_p16() {
+    fn test_vld1q_dup_p16() {
         let elem: p16 = 42;
         let e = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u16x8 = transmute(vld1q_dup_p16(&elem));
+        let r = unsafe { u16x8::from(vld1q_dup_p16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_dup_p64() {
+    fn test_vld1_dup_p64() {
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_dup_p64(&elem));
+        let r = unsafe { u64x1::from(vld1_dup_p64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_dup_p64() {
+    fn test_vld1q_dup_p64() {
         let elem: u64 = 42;
         let e = u64x2::new(42, 42);
-        let r: u64x2 = transmute(vld1q_dup_p64(&elem));
+        let r = unsafe { u64x2::from(vld1q_dup_p64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_f32() {
+    fn test_vld1_dup_f32() {
         let elem: f32 = 42.;
         let e = f32x2::new(42., 42.);
-        let r: f32x2 = transmute(vld1_dup_f32(&elem));
+        let r = unsafe { f32x2::from(vld1_dup_f32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_f32() {
+    fn test_vld1q_dup_f32() {
         let elem: f32 = 42.;
         let e = f32x4::new(42., 42., 42., 42.);
-        let r: f32x4 = transmute(vld1q_dup_f32(&elem));
+        let r = unsafe { f32x4::from(vld1q_dup_f32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u8() {
-        let v = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = vget_lane_u8::<1>(transmute(v));
+    fn test_vget_lane_u8() {
+        let v = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+        let r = vget_lane_u8::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u32() {
-        let v = i32x4::new(1, 2, 3, 4);
-        let r = vgetq_lane_u32::<1>(transmute(v));
+    fn test_vgetq_lane_u32() {
+        let v = u32x4::new(1, 2, 3, 4);
+        let r = vgetq_lane_u32::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s32() {
+    fn test_vgetq_lane_s32() {
         let v = i32x4::new(1, 2, 3, 4);
-        let r = vgetq_lane_s32::<1>(transmute(v));
+        let r = vgetq_lane_s32::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u64() {
-        let v: u64 = 1;
-        let r = vget_lane_u64::<0>(transmute(v));
+    fn test_vget_lane_u64() {
+        let v = u64x1::new(1);
+        let r = vget_lane_u64::<0>(v.into());
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u16() {
-        let v = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = vgetq_lane_u16::<1>(transmute(v));
+    fn test_vgetq_lane_u16() {
+        let v = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+        let r = vgetq_lane_u16::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s8() {
+    fn test_vget_lane_s8() {
         let v = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vget_lane_s8::<2>(transmute(v));
+        let r = vget_lane_s8::<2>(v.into());
         assert_eq!(r, 2);
-        let r = vget_lane_s8::<4>(transmute(v));
+        let r = vget_lane_s8::<4>(v.into());
         assert_eq!(r, 4);
-        let r = vget_lane_s8::<5>(transmute(v));
+        let r = vget_lane_s8::<5>(v.into());
         assert_eq!(r, 5);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_p8() {
+    fn test_vget_lane_p8() {
         let v = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vget_lane_p8::<2>(transmute(v));
+        let r = vget_lane_p8::<2>(v.into());
         assert_eq!(r, 2);
-        let r = vget_lane_p8::<3>(transmute(v));
+        let r = vget_lane_p8::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vget_lane_p8::<5>(transmute(v));
+        let r = vget_lane_p8::<5>(v.into());
         assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_p16() {
+    fn test_vget_lane_p16() {
         let v = u16x4::new(0, 1, 2, 3);
-        let r = vget_lane_p16::<2>(transmute(v));
+        let r = vget_lane_p16::<2>(v.into());
         assert_eq!(r, 2);
-        let r = vget_lane_p16::<3>(transmute(v));
+        let r = vget_lane_p16::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vget_lane_p16::<0>(transmute(v));
+        let r = vget_lane_p16::<0>(v.into());
         assert_eq!(r, 0);
-        let r = vget_lane_p16::<1>(transmute(v));
+        let r = vget_lane_p16::<1>(v.into());
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s16() {
+    fn test_vget_lane_s16() {
         let v = i16x4::new(0, 1, 2, 3);
-        let r = vget_lane_s16::<2>(transmute(v));
+        let r = vget_lane_s16::<2>(v.into());
         assert_eq!(r, 2);
-        let r = vget_lane_s16::<3>(transmute(v));
+        let r = vget_lane_s16::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vget_lane_s16::<0>(transmute(v));
+        let r = vget_lane_s16::<0>(v.into());
         assert_eq!(r, 0);
-        let r = vget_lane_s16::<1>(transmute(v));
+        let r = vget_lane_s16::<1>(v.into());
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u16() {
+    fn test_vget_lane_u16() {
         let v = u16x4::new(0, 1, 2, 3);
-        let r = vget_lane_u16::<2>(transmute(v));
+        let r = vget_lane_u16::<2>(v.into());
         assert_eq!(r, 2);
-        let r = vget_lane_u16::<3>(transmute(v));
+        let r = vget_lane_u16::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vget_lane_u16::<0>(transmute(v));
+        let r = vget_lane_u16::<0>(v.into());
         assert_eq!(r, 0);
-        let r = vget_lane_u16::<1>(transmute(v));
+        let r = vget_lane_u16::<1>(v.into());
         assert_eq!(r, 1);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_f32() {
+    fn test_vget_lane_f32() {
         let v = f32x2::new(0.0, 1.0);
-        let r = vget_lane_f32::<1>(transmute(v));
+        let r = vget_lane_f32::<1>(v.into());
         assert_eq!(r, 1.0);
-        let r = vget_lane_f32::<0>(transmute(v));
+        let r = vget_lane_f32::<0>(v.into());
         assert_eq!(r, 0.0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s32() {
+    fn test_vget_lane_s32() {
         let v = i32x2::new(0, 1);
-        let r = vget_lane_s32::<1>(transmute(v));
+        let r = vget_lane_s32::<1>(v.into());
         assert_eq!(r, 1);
-        let r = vget_lane_s32::<0>(transmute(v));
+        let r = vget_lane_s32::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u32() {
+    fn test_vget_lane_u32() {
         let v = u32x2::new(0, 1);
-        let r = vget_lane_u32::<1>(transmute(v));
+        let r = vget_lane_u32::<1>(v.into());
         assert_eq!(r, 1);
-        let r = vget_lane_u32::<0>(transmute(v));
+        let r = vget_lane_u32::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s64() {
+    fn test_vget_lane_s64() {
         let v = i64x1::new(1);
-        let r = vget_lane_s64::<0>(transmute(v));
+        let r = vget_lane_s64::<0>(v.into());
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_p64() {
+    fn test_vget_lane_p64() {
         let v = u64x1::new(1);
-        let r = vget_lane_p64::<0>(transmute(v));
+        let r = vget_lane_p64::<0>(v.into());
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s8() {
+    fn test_vgetq_lane_s8() {
         let v = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_s8::<7>(transmute(v));
+        let r = vgetq_lane_s8::<7>(v.into());
         assert_eq!(r, 7);
-        let r = vgetq_lane_s8::<13>(transmute(v));
+        let r = vgetq_lane_s8::<13>(v.into());
         assert_eq!(r, 13);
-        let r = vgetq_lane_s8::<3>(transmute(v));
+        let r = vgetq_lane_s8::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_s8::<0>(transmute(v));
+        let r = vgetq_lane_s8::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_p8() {
+    fn test_vgetq_lane_p8() {
         let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_p8::<7>(transmute(v));
+        let r = vgetq_lane_p8::<7>(v.into());
         assert_eq!(r, 7);
-        let r = vgetq_lane_p8::<13>(transmute(v));
+        let r = vgetq_lane_p8::<13>(v.into());
         assert_eq!(r, 13);
-        let r = vgetq_lane_p8::<3>(transmute(v));
+        let r = vgetq_lane_p8::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_p8::<0>(transmute(v));
+        let r = vgetq_lane_p8::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u8() {
+    fn test_vgetq_lane_u8() {
         let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_u8::<7>(transmute(v));
+        let r = vgetq_lane_u8::<7>(v.into());
         assert_eq!(r, 7);
-        let r = vgetq_lane_u8::<13>(transmute(v));
+        let r = vgetq_lane_u8::<13>(v.into());
         assert_eq!(r, 13);
-        let r = vgetq_lane_u8::<3>(transmute(v));
+        let r = vgetq_lane_u8::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_u8::<0>(transmute(v));
+        let r = vgetq_lane_u8::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s16() {
+    fn test_vgetq_lane_s16() {
         let v = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vgetq_lane_s16::<3>(transmute(v));
+        let r = vgetq_lane_s16::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_s16::<6>(transmute(v));
+        let r = vgetq_lane_s16::<6>(v.into());
         assert_eq!(r, 6);
-        let r = vgetq_lane_s16::<0>(transmute(v));
+        let r = vgetq_lane_s16::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_p16() {
+    fn test_vgetq_lane_p16() {
         let v = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vgetq_lane_p16::<3>(transmute(v));
+        let r = vgetq_lane_p16::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_p16::<7>(transmute(v));
+        let r = vgetq_lane_p16::<7>(v.into());
         assert_eq!(r, 7);
-        let r = vgetq_lane_p16::<1>(transmute(v));
+        let r = vgetq_lane_p16::<1>(v.into());
         assert_eq!(r, 1);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_f32() {
+    fn test_vgetq_lane_f32() {
         let v = f32x4::new(0.0, 1.0, 2.0, 3.0);
-        let r = vgetq_lane_f32::<3>(transmute(v));
+        let r = vgetq_lane_f32::<3>(v.into());
         assert_eq!(r, 3.0);
-        let r = vgetq_lane_f32::<0>(transmute(v));
+        let r = vgetq_lane_f32::<0>(v.into());
         assert_eq!(r, 0.0);
-        let r = vgetq_lane_f32::<2>(transmute(v));
+        let r = vgetq_lane_f32::<2>(v.into());
         assert_eq!(r, 2.0);
-        let r = vgetq_lane_f32::<1>(transmute(v));
+        let r = vgetq_lane_f32::<1>(v.into());
         assert_eq!(r, 1.0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s64() {
+    fn test_vgetq_lane_s64() {
         let v = i64x2::new(0, 1);
-        let r = vgetq_lane_s64::<1>(transmute(v));
+        let r = vgetq_lane_s64::<1>(v.into());
         assert_eq!(r, 1);
-        let r = vgetq_lane_s64::<0>(transmute(v));
+        let r = vgetq_lane_s64::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_p64() {
+    fn test_vgetq_lane_p64() {
         let v = u64x2::new(0, 1);
-        let r = vgetq_lane_p64::<1>(transmute(v));
+        let r = vgetq_lane_p64::<1>(v.into());
         assert_eq!(r, 1);
-        let r = vgetq_lane_p64::<0>(transmute(v));
+        let r = vgetq_lane_p64::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vext_s64() {
+    fn test_vext_s64() {
         let a: i64x1 = i64x1::new(0);
         let b: i64x1 = i64x1::new(1);
         let e: i64x1 = i64x1::new(0);
-        let r: i64x1 = transmute(vext_s64::<0>(transmute(a), transmute(b)));
+        let r = unsafe { i64x1::from(vext_s64::<0>(a.into(), b.into())) };
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vext_u64() {
+    fn test_vext_u64() {
         let a: u64x1 = u64x1::new(0);
         let b: u64x1 = u64x1::new(1);
         let e: u64x1 = u64x1::new(0);
-        let r: u64x1 = transmute(vext_u64::<0>(transmute(a), transmute(b)));
+        let r = unsafe { u64x1::from(vext_u64::<0>(a.into(), b.into())) };
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s8() {
+    fn test_vget_high_s8() {
         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = i8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r: i8x8 = transmute(vget_high_s8(transmute(a)));
+        let r = i8x8::from(vget_high_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s16() {
+    fn test_vget_high_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = i16x4::new(5, 6, 7, 8);
-        let r: i16x4 = transmute(vget_high_s16(transmute(a)));
+        let r = i16x4::from(vget_high_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s32() {
+    fn test_vget_high_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let e = i32x2::new(3, 4);
-        let r: i32x2 = transmute(vget_high_s32(transmute(a)));
+        let r = i32x2::from(vget_high_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s64() {
+    fn test_vget_high_s64() {
         let a = i64x2::new(1, 2);
         let e = i64x1::new(2);
-        let r: i64x1 = transmute(vget_high_s64(transmute(a)));
+        let r = i64x1::from(vget_high_s64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u8() {
+    fn test_vget_high_u8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r: u8x8 = transmute(vget_high_u8(transmute(a)));
+        let r = u8x8::from(vget_high_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u16() {
+    fn test_vget_high_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(5, 6, 7, 8);
-        let r: u16x4 = transmute(vget_high_u16(transmute(a)));
+        let r = u16x4::from(vget_high_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u32() {
+    fn test_vget_high_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let e = u32x2::new(3, 4);
-        let r: u32x2 = transmute(vget_high_u32(transmute(a)));
+        let r = u32x2::from(vget_high_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u64() {
+    fn test_vget_high_u64() {
         let a = u64x2::new(1, 2);
         let e = u64x1::new(2);
-        let r: u64x1 = transmute(vget_high_u64(transmute(a)));
+        let r = u64x1::from(vget_high_u64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_p8() {
+    fn test_vget_high_p8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r: u8x8 = transmute(vget_high_p8(transmute(a)));
+        let r = u8x8::from(vget_high_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_p16() {
+    fn test_vget_high_p16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(5, 6, 7, 8);
-        let r: u16x4 = transmute(vget_high_p16(transmute(a)));
+        let r = u16x4::from(vget_high_p16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_f32() {
+    fn test_vget_high_f32() {
         let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
         let e = f32x2::new(3.0, 4.0);
-        let r: f32x2 = transmute(vget_high_f32(transmute(a)));
+        let r = f32x2::from(vget_high_f32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s8() {
+    fn test_vget_low_s8() {
         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: i8x8 = transmute(vget_low_s8(transmute(a)));
+        let r = i8x8::from(vget_low_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s16() {
+    fn test_vget_low_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = i16x4::new(1, 2, 3, 4);
-        let r: i16x4 = transmute(vget_low_s16(transmute(a)));
+        let r = i16x4::from(vget_low_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s32() {
+    fn test_vget_low_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let e = i32x2::new(1, 2);
-        let r: i32x2 = transmute(vget_low_s32(transmute(a)));
+        let r = i32x2::from(vget_low_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s64() {
+    fn test_vget_low_s64() {
         let a = i64x2::new(1, 2);
         let e = i64x1::new(1);
-        let r: i64x1 = transmute(vget_low_s64(transmute(a)));
+        let r = i64x1::from(vget_low_s64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u8() {
+    fn test_vget_low_u8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u8x8 = transmute(vget_low_u8(transmute(a)));
+        let r = u8x8::from(vget_low_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u16() {
+    fn test_vget_low_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(1, 2, 3, 4);
-        let r: u16x4 = transmute(vget_low_u16(transmute(a)));
+        let r = u16x4::from(vget_low_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u32() {
+    fn test_vget_low_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let e = u32x2::new(1, 2);
-        let r: u32x2 = transmute(vget_low_u32(transmute(a)));
+        let r = u32x2::from(vget_low_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u64() {
+    fn test_vget_low_u64() {
         let a = u64x2::new(1, 2);
         let e = u64x1::new(1);
-        let r: u64x1 = transmute(vget_low_u64(transmute(a)));
+        let r = u64x1::from(vget_low_u64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_p8() {
+    fn test_vget_low_p8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u8x8 = transmute(vget_low_p8(transmute(a)));
+        let r = u8x8::from(vget_low_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_p16() {
+    fn test_vget_low_p16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(1, 2, 3, 4);
-        let r: u16x4 = transmute(vget_low_p16(transmute(a)));
+        let r = u16x4::from(vget_low_p16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_f32() {
+    fn test_vget_low_f32() {
         let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
         let e = f32x2::new(1.0, 2.0);
-        let r: f32x2 = transmute(vget_low_f32(transmute(a)));
+        let r = f32x2::from(vget_low_f32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s8() {
+    fn test_vdupq_n_s8() {
         let v: i8 = 42;
         let e = i8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: i8x16 = transmute(vdupq_n_s8(v));
+        let r = i8x16::from(vdupq_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s16() {
+    fn test_vdupq_n_s16() {
         let v: i16 = 64;
         let e = i16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i16x8 = transmute(vdupq_n_s16(v));
+        let r = i16x8::from(vdupq_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s32() {
+    fn test_vdupq_n_s32() {
         let v: i32 = 64;
         let e = i32x4::new(64, 64, 64, 64);
-        let r: i32x4 = transmute(vdupq_n_s32(v));
+        let r = i32x4::from(vdupq_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s64() {
+    fn test_vdupq_n_s64() {
         let v: i64 = 64;
         let e = i64x2::new(64, 64);
-        let r: i64x2 = transmute(vdupq_n_s64(v));
+        let r = i64x2::from(vdupq_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u8() {
+    fn test_vdupq_n_u8() {
         let v: u8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vdupq_n_u8(v));
+        let r = u8x16::from(vdupq_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u16() {
+    fn test_vdupq_n_u16() {
         let v: u16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vdupq_n_u16(v));
+        let r = u16x8::from(vdupq_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u32() {
+    fn test_vdupq_n_u32() {
         let v: u32 = 64;
         let e = u32x4::new(64, 64, 64, 64);
-        let r: u32x4 = transmute(vdupq_n_u32(v));
+        let r = u32x4::from(vdupq_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u64() {
+    fn test_vdupq_n_u64() {
         let v: u64 = 64;
         let e = u64x2::new(64, 64);
-        let r: u64x2 = transmute(vdupq_n_u64(v));
+        let r = u64x2::from(vdupq_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_p8() {
+    fn test_vdupq_n_p8() {
         let v: p8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vdupq_n_p8(v));
+        let r = u8x16::from(vdupq_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_p16() {
+    fn test_vdupq_n_p16() {
         let v: p16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vdupq_n_p16(v));
+        let r = u16x8::from(vdupq_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_f32() {
+    fn test_vdupq_n_f32() {
         let v: f32 = 64.0;
         let e = f32x4::new(64.0, 64.0, 64.0, 64.0);
-        let r: f32x4 = transmute(vdupq_n_f32(v));
+        let r = f32x4::from(vdupq_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s8() {
+    fn test_vdup_n_s8() {
         let v: i8 = 64;
         let e = i8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i8x8 = transmute(vdup_n_s8(v));
+        let r = i8x8::from(vdup_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s16() {
+    fn test_vdup_n_s16() {
         let v: i16 = 64;
         let e = i16x4::new(64, 64, 64, 64);
-        let r: i16x4 = transmute(vdup_n_s16(v));
+        let r = i16x4::from(vdup_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s32() {
+    fn test_vdup_n_s32() {
         let v: i32 = 64;
         let e = i32x2::new(64, 64);
-        let r: i32x2 = transmute(vdup_n_s32(v));
+        let r = i32x2::from(vdup_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s64() {
+    fn test_vdup_n_s64() {
         let v: i64 = 64;
         let e = i64x1::new(64);
-        let r: i64x1 = transmute(vdup_n_s64(v));
+        let r = i64x1::from(vdup_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u8() {
+    fn test_vdup_n_u8() {
         let v: u8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vdup_n_u8(v));
+        let r = u8x8::from(vdup_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u16() {
+    fn test_vdup_n_u16() {
         let v: u16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vdup_n_u16(v));
+        let r = u16x4::from(vdup_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u32() {
+    fn test_vdup_n_u32() {
         let v: u32 = 64;
         let e = u32x2::new(64, 64);
-        let r: u32x2 = transmute(vdup_n_u32(v));
+        let r = u32x2::from(vdup_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u64() {
+    fn test_vdup_n_u64() {
         let v: u64 = 64;
         let e = u64x1::new(64);
-        let r: u64x1 = transmute(vdup_n_u64(v));
+        let r = u64x1::from(vdup_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_p8() {
+    fn test_vdup_n_p8() {
         let v: p8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vdup_n_p8(v));
+        let r = u8x8::from(vdup_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_p16() {
+    fn test_vdup_n_p16() {
         let v: p16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vdup_n_p16(v));
+        let r = u16x4::from(vdup_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_f32() {
+    fn test_vdup_n_f32() {
         let v: f32 = 64.0;
         let e = f32x2::new(64.0, 64.0);
-        let r: f32x2 = transmute(vdup_n_f32(v));
+        let r = f32x2::from(vdup_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vldrq_p128() {
+    fn test_vldrq_p128() {
         let v: [p128; 2] = [1, 2];
         let e: p128 = 2;
-        let r: p128 = vldrq_p128(v[1..].as_ptr());
+        let r: p128 = unsafe { vldrq_p128(v[1..].as_ptr()) };
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vstrq_p128() {
+    fn test_vstrq_p128() {
         let v: [p128; 2] = [1, 2];
         let e: p128 = 2;
         let mut r: p128 = 1;
-        vstrq_p128(&mut r, v[1]);
+        unsafe {
+            vstrq_p128(&mut r, v[1]);
+        }
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s8() {
+    fn test_vmov_n_s8() {
         let v: i8 = 64;
         let e = i8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i8x8 = transmute(vmov_n_s8(v));
+        let r = i8x8::from(vmov_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s16() {
+    fn test_vmov_n_s16() {
         let v: i16 = 64;
         let e = i16x4::new(64, 64, 64, 64);
-        let r: i16x4 = transmute(vmov_n_s16(v));
+        let r = i16x4::from(vmov_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s32() {
+    fn test_vmov_n_s32() {
         let v: i32 = 64;
         let e = i32x2::new(64, 64);
-        let r: i32x2 = transmute(vmov_n_s32(v));
+        let r = i32x2::from(vmov_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s64() {
+    fn test_vmov_n_s64() {
         let v: i64 = 64;
         let e = i64x1::new(64);
-        let r: i64x1 = transmute(vmov_n_s64(v));
+        let r = i64x1::from(vmov_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u8() {
+    fn test_vmov_n_u8() {
         let v: u8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vmov_n_u8(v));
+        let r = u8x8::from(vmov_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u16() {
+    fn test_vmov_n_u16() {
         let v: u16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vmov_n_u16(v));
+        let r = u16x4::from(vmov_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u32() {
+    fn test_vmov_n_u32() {
         let v: u32 = 64;
         let e = u32x2::new(64, 64);
-        let r: u32x2 = transmute(vmov_n_u32(v));
+        let r = u32x2::from(vmov_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u64() {
+    fn test_vmov_n_u64() {
         let v: u64 = 64;
         let e = u64x1::new(64);
-        let r: u64x1 = transmute(vmov_n_u64(v));
+        let r = u64x1::from(vmov_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_p8() {
+    fn test_vmov_n_p8() {
         let v: p8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vmov_n_p8(v));
+        let r = u8x8::from(vmov_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_p16() {
+    fn test_vmov_n_p16() {
         let v: p16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vmov_n_p16(v));
+        let r = u16x4::from(vmov_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_f32() {
+    fn test_vmov_n_f32() {
         let v: f32 = 64.0;
         let e = f32x2::new(64.0, 64.0);
-        let r: f32x2 = transmute(vmov_n_f32(v));
+        let r = f32x2::from(vmov_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s8() {
+    fn test_vmovq_n_s8() {
         let v: i8 = 64;
         let e = i8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: i8x16 = transmute(vmovq_n_s8(v));
+        let r = i8x16::from(vmovq_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s16() {
+    fn test_vmovq_n_s16() {
         let v: i16 = 64;
         let e = i16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i16x8 = transmute(vmovq_n_s16(v));
+        let r = i16x8::from(vmovq_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s32() {
+    fn test_vmovq_n_s32() {
         let v: i32 = 64;
         let e = i32x4::new(64, 64, 64, 64);
-        let r: i32x4 = transmute(vmovq_n_s32(v));
+        let r = i32x4::from(vmovq_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s64() {
+    fn test_vmovq_n_s64() {
         let v: i64 = 64;
         let e = i64x2::new(64, 64);
-        let r: i64x2 = transmute(vmovq_n_s64(v));
+        let r = i64x2::from(vmovq_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u8() {
+    fn test_vmovq_n_u8() {
         let v: u8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vmovq_n_u8(v));
+        let r = u8x16::from(vmovq_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u16() {
+    fn test_vmovq_n_u16() {
         let v: u16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vmovq_n_u16(v));
+        let r = u16x8::from(vmovq_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u32() {
+    fn test_vmovq_n_u32() {
         let v: u32 = 64;
         let e = u32x4::new(64, 64, 64, 64);
-        let r: u32x4 = transmute(vmovq_n_u32(v));
+        let r = u32x4::from(vmovq_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u64() {
+    fn test_vmovq_n_u64() {
         let v: u64 = 64;
         let e = u64x2::new(64, 64);
-        let r: u64x2 = transmute(vmovq_n_u64(v));
+        let r = u64x2::from(vmovq_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_p8() {
+    fn test_vmovq_n_p8() {
         let v: p8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vmovq_n_p8(v));
+        let r = u8x16::from(vmovq_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_p16() {
+    fn test_vmovq_n_p16() {
         let v: p16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vmovq_n_p16(v));
+        let r = u16x8::from(vmovq_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_f32() {
+    fn test_vmovq_n_f32() {
         let v: f32 = 64.0;
         let e = f32x4::new(64.0, 64.0, 64.0, 64.0);
-        let r: f32x4 = transmute(vmovq_n_f32(v));
+        let r = f32x4::from(vmovq_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u64() {
-        let v = i64x2::new(1, 2);
-        let r = vgetq_lane_u64::<1>(transmute(v));
+    fn test_vgetq_lane_u64() {
+        let v = u64x2::new(1, 2);
+        let r = vgetq_lane_u64::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s8() {
+    fn test_vadd_s8() {
         test_ari_s8(
             |i, j| vadd_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_s8() {
+    fn test_vaddq_s8() {
         testq_ari_s8(
             |i, j| vaddq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s16() {
+    fn test_vadd_s16() {
         test_ari_s16(
             |i, j| vadd_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_s16() {
+    fn test_vaddq_s16() {
         testq_ari_s16(
             |i, j| vaddq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s32() {
+    fn test_vadd_s32() {
         test_ari_s32(
             |i, j| vadd_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_s32() {
+    fn test_vaddq_s32() {
         testq_ari_s32(
             |i, j| vaddq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_add(b).0 },
@@ -2516,42 +2521,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u8() {
+    fn test_vadd_u8() {
         test_ari_u8(
             |i, j| vadd_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_u8() {
+    fn test_vaddq_u8() {
         testq_ari_u8(
             |i, j| vaddq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u16() {
+    fn test_vadd_u16() {
         test_ari_u16(
             |i, j| vadd_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_u16() {
+    fn test_vaddq_u16() {
         testq_ari_u16(
             |i, j| vaddq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u32() {
+    fn test_vadd_u32() {
         test_ari_u32(
             |i, j| vadd_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_u32() {
+    fn test_vaddq_u32() {
         testq_ari_u32(
             |i, j| vaddq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_add(b).0 },
@@ -2559,142 +2569,143 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_f32() {
+    fn test_vadd_f32() {
         test_ari_f32(|i, j| vadd_f32(i, j), |a: f32, b: f32| -> f32 { a + b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_f32() {
+    fn test_vaddq_f32() {
         testq_ari_f32(|i, j| vaddq_f32(i, j), |a: f32, b: f32| -> f32 { a + b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_s8() {
+    fn test_vaddl_s8() {
         let v = i8::MAX;
         let a = i8x8::new(v, v, v, v, v, v, v, v);
         let v = 2 * (v as i16);
         let e = i16x8::new(v, v, v, v, v, v, v, v);
-        let r: i16x8 = transmute(vaddl_s8(transmute(a), transmute(a)));
+        let r = i16x8::from(vaddl_s8(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_s16() {
+    fn test_vaddl_s16() {
         let v = i16::MAX;
         let a = i16x4::new(v, v, v, v);
         let v = 2 * (v as i32);
         let e = i32x4::new(v, v, v, v);
-        let r: i32x4 = transmute(vaddl_s16(transmute(a), transmute(a)));
+        let r = i32x4::from(vaddl_s16(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_s32() {
+    fn test_vaddl_s32() {
         let v = i32::MAX;
         let a = i32x2::new(v, v);
         let v = 2 * (v as i64);
         let e = i64x2::new(v, v);
-        let r: i64x2 = transmute(vaddl_s32(transmute(a), transmute(a)));
+        let r = i64x2::from(vaddl_s32(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_u8() {
+    fn test_vaddl_u8() {
         let v = u8::MAX;
         let a = u8x8::new(v, v, v, v, v, v, v, v);
         let v = 2 * (v as u16);
         let e = u16x8::new(v, v, v, v, v, v, v, v);
-        let r: u16x8 = transmute(vaddl_u8(transmute(a), transmute(a)));
+        let r = u16x8::from(vaddl_u8(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_u16() {
+    fn test_vaddl_u16() {
         let v = u16::MAX;
         let a = u16x4::new(v, v, v, v);
         let v = 2 * (v as u32);
         let e = u32x4::new(v, v, v, v);
-        let r: u32x4 = transmute(vaddl_u16(transmute(a), transmute(a)));
+        let r = u32x4::from(vaddl_u16(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_u32() {
+    fn test_vaddl_u32() {
         let v = u32::MAX;
         let a = u32x2::new(v, v);
         let v = 2 * (v as u64);
         let e = u64x2::new(v, v);
-        let r: u64x2 = transmute(vaddl_u32(transmute(a), transmute(a)));
+        let r = u64x2::from(vaddl_u32(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_s8() {
+    fn test_vaddl_high_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let x = i8::MAX;
         let b = i8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x);
         let x = x as i16;
         let e = i16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15);
-        let r: i16x8 = transmute(vaddl_high_s8(transmute(a), transmute(b)));
+        let r = i16x8::from(vaddl_high_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_s16() {
+    fn test_vaddl_high_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let x = i16::MAX;
         let b = i16x8::new(x, x, x, x, x, x, x, x);
         let x = x as i32;
         let e = i32x4::new(x + 4, x + 5, x + 6, x + 7);
-        let r: i32x4 = transmute(vaddl_high_s16(transmute(a), transmute(b)));
+        let r = i32x4::from(vaddl_high_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_s32() {
+    fn test_vaddl_high_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let x = i32::MAX;
         let b = i32x4::new(x, x, x, x);
         let x = x as i64;
         let e = i64x2::new(x + 2, x + 3);
-        let r: i64x2 = transmute(vaddl_high_s32(transmute(a), transmute(b)));
+        let r = i64x2::from(vaddl_high_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_u8() {
+    fn test_vaddl_high_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let x = u8::MAX;
         let b = u8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x);
         let x = x as u16;
         let e = u16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15);
-        let r: u16x8 = transmute(vaddl_high_u8(transmute(a), transmute(b)));
+        let r = u16x8::from(vaddl_high_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_u16() {
+    fn test_vaddl_high_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let x = u16::MAX;
         let b = u16x8::new(x, x, x, x, x, x, x, x);
         let x = x as u32;
         let e = u32x4::new(x + 4, x + 5, x + 6, x + 7);
-        let r: u32x4 = transmute(vaddl_high_u16(transmute(a), transmute(b)));
+        let r = u32x4::from(vaddl_high_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_u32() {
+    fn test_vaddl_high_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let x = u32::MAX;
         let b = u32x4::new(x, x, x, x);
         let x = x as u64;
         let e = u64x2::new(x + 2, x + 3);
-        let r: u64x2 = transmute(vaddl_high_u32(transmute(a), transmute(b)));
+        let r = u64x2::from(vaddl_high_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_s8() {
+    fn test_vaddw_s8() {
         let x = i16::MAX;
         let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = i8::MAX;
@@ -2710,36 +2721,36 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: i16x8 = transmute(vaddw_s8(transmute(a), transmute(b)));
+        let r = i16x8::from(vaddw_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_s16() {
+    fn test_vaddw_s16() {
         let x = i32::MAX;
         let a = i32x4::new(x, 1, 2, 3);
         let y = i16::MAX;
         let b = i16x4::new(y, y, y, y);
         let y = y as i32;
         let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: i32x4 = transmute(vaddw_s16(transmute(a), transmute(b)));
+        let r = i32x4::from(vaddw_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_s32() {
+    fn test_vaddw_s32() {
         let x = i64::MAX;
         let a = i64x2::new(x, 1);
         let y = i32::MAX;
         let b = i32x2::new(y, y);
         let y = y as i64;
         let e = i64x2::new(x.wrapping_add(y), 1 + y);
-        let r: i64x2 = transmute(vaddw_s32(transmute(a), transmute(b)));
+        let r = i64x2::from(vaddw_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_u8() {
+    fn test_vaddw_u8() {
         let x = u16::MAX;
         let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = u8::MAX;
@@ -2755,36 +2766,36 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: u16x8 = transmute(vaddw_u8(transmute(a), transmute(b)));
+        let r = u16x8::from(vaddw_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_u16() {
+    fn test_vaddw_u16() {
         let x = u32::MAX;
         let a = u32x4::new(x, 1, 2, 3);
         let y = u16::MAX;
         let b = u16x4::new(y, y, y, y);
         let y = y as u32;
         let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: u32x4 = transmute(vaddw_u16(transmute(a), transmute(b)));
+        let r = u32x4::from(vaddw_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_u32() {
+    fn test_vaddw_u32() {
         let x = u64::MAX;
         let a = u64x2::new(x, 1);
         let y = u32::MAX;
         let b = u32x2::new(y, y);
         let y = y as u64;
         let e = u64x2::new(x.wrapping_add(y), 1 + y);
-        let r: u64x2 = transmute(vaddw_u32(transmute(a), transmute(b)));
+        let r = u64x2::from(vaddw_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_s8() {
+    fn test_vaddw_high_s8() {
         let x = i16::MAX;
         let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = i8::MAX;
@@ -2800,36 +2811,36 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: i16x8 = transmute(vaddw_high_s8(transmute(a), transmute(b)));
+        let r = i16x8::from(vaddw_high_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_s16() {
+    fn test_vaddw_high_s16() {
         let x = i32::MAX;
         let a = i32x4::new(x, 1, 2, 3);
         let y = i16::MAX;
         let b = i16x8::new(0, 0, 0, 0, y, y, y, y);
         let y = y as i32;
         let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: i32x4 = transmute(vaddw_high_s16(transmute(a), transmute(b)));
+        let r = i32x4::from(vaddw_high_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_s32() {
+    fn test_vaddw_high_s32() {
         let x = i64::MAX;
         let a = i64x2::new(x, 1);
         let y = i32::MAX;
         let b = i32x4::new(0, 0, y, y);
         let y = y as i64;
         let e = i64x2::new(x.wrapping_add(y), 1 + y);
-        let r: i64x2 = transmute(vaddw_high_s32(transmute(a), transmute(b)));
+        let r = i64x2::from(vaddw_high_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_u8() {
+    fn test_vaddw_high_u8() {
         let x = u16::MAX;
         let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = u8::MAX;
@@ -2845,165 +2856,165 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: u16x8 = transmute(vaddw_high_u8(transmute(a), transmute(b)));
+        let r = u16x8::from(vaddw_high_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_u16() {
+    fn test_vaddw_high_u16() {
         let x = u32::MAX;
         let a = u32x4::new(x, 1, 2, 3);
         let y = u16::MAX;
         let b = u16x8::new(0, 0, 0, 0, y, y, y, y);
         let y = y as u32;
         let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: u32x4 = transmute(vaddw_high_u16(transmute(a), transmute(b)));
+        let r = u32x4::from(vaddw_high_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_u32() {
+    fn test_vaddw_high_u32() {
         let x = u64::MAX;
         let a = u64x2::new(x, 1);
         let y = u32::MAX;
         let b = u32x4::new(0, 0, y, y);
         let y = y as u64;
         let e = u64x2::new(x.wrapping_add(y), 1 + y);
-        let r: u64x2 = transmute(vaddw_high_u32(transmute(a), transmute(b)));
+        let r = u64x2::from(vaddw_high_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_s8() {
+    fn test_vmvn_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = i8x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
-        let r: i8x8 = transmute(vmvn_s8(transmute(a)));
+        let r = i8x8::from(vmvn_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_s8() {
+    fn test_vmvnq_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e = i8x16::new(
             -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16,
         );
-        let r: i8x16 = transmute(vmvnq_s8(transmute(a)));
+        let r = i8x16::from(vmvnq_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_s16() {
+    fn test_vmvn_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let e = i16x4::new(-1, -2, -3, -4);
-        let r: i16x4 = transmute(vmvn_s16(transmute(a)));
+        let r = i16x4::from(vmvn_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_s16() {
+    fn test_vmvnq_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = i16x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
-        let r: i16x8 = transmute(vmvnq_s16(transmute(a)));
+        let r = i16x8::from(vmvnq_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_s32() {
+    fn test_vmvn_s32() {
         let a = i32x2::new(0, 1);
         let e = i32x2::new(-1, -2);
-        let r: i32x2 = transmute(vmvn_s32(transmute(a)));
+        let r = i32x2::from(vmvn_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_s32() {
+    fn test_vmvnq_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let e = i32x4::new(-1, -2, -3, -4);
-        let r: i32x4 = transmute(vmvnq_s32(transmute(a)));
+        let r = i32x4::from(vmvnq_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_u8() {
+    fn test_vmvn_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
-        let r: u8x8 = transmute(vmvn_u8(transmute(a)));
+        let r = u8x8::from(vmvn_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_u8() {
+    fn test_vmvnq_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e = u8x16::new(
             255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
         );
-        let r: u8x16 = transmute(vmvnq_u8(transmute(a)));
+        let r = u8x16::from(vmvnq_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_u16() {
+    fn test_vmvn_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let e = u16x4::new(65_535, 65_534, 65_533, 65_532);
-        let r: u16x4 = transmute(vmvn_u16(transmute(a)));
+        let r = u16x4::from(vmvn_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_u16() {
+    fn test_vmvnq_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = u16x8::new(
             65_535, 65_534, 65_533, 65_532, 65_531, 65_530, 65_529, 65_528,
         );
-        let r: u16x8 = transmute(vmvnq_u16(transmute(a)));
+        let r = u16x8::from(vmvnq_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_u32() {
+    fn test_vmvn_u32() {
         let a = u32x2::new(0, 1);
         let e = u32x2::new(4_294_967_295, 4_294_967_294);
-        let r: u32x2 = transmute(vmvn_u32(transmute(a)));
+        let r = u32x2::from(vmvn_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_u32() {
+    fn test_vmvnq_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let e = u32x4::new(4_294_967_295, 4_294_967_294, 4_294_967_293, 4_294_967_292);
-        let r: u32x4 = transmute(vmvnq_u32(transmute(a)));
+        let r = u32x4::from(vmvnq_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_p8() {
+    fn test_vmvn_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
-        let r: u8x8 = transmute(vmvn_p8(transmute(a)));
+        let r = u8x8::from(vmvn_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_p8() {
+    fn test_vmvnq_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e = u8x16::new(
             255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
         );
-        let r: u8x16 = transmute(vmvnq_p8(transmute(a)));
+        let r = u8x16::from(vmvnq_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s8() {
+    fn test_vbic_s8() {
         let a = i8x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = i8x8::new(0, -2, -2, -4, -4, -6, -6, -8);
-        let r: i8x8 = transmute(vbic_s8(transmute(a), transmute(b)));
+        let r = i8x8::from(vbic_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s8() {
+    fn test_vbicq_s8() {
         let a = i8x16::new(
             0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
         );
@@ -3011,138 +3022,138 @@ mod tests {
         let e = i8x16::new(
             0, -2, -2, -4, -4, -6, -6, -8, -8, -10, -10, -12, -12, -14, -14, -16,
         );
-        let r: i8x16 = transmute(vbicq_s8(transmute(a), transmute(b)));
+        let r = i8x16::from(vbicq_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s16() {
+    fn test_vbic_s16() {
         let a = i16x4::new(0, -1, -2, -3);
         let b = i16x4::new(1, 1, 1, 1);
         let e = i16x4::new(0, -2, -2, -4);
-        let r: i16x4 = transmute(vbic_s16(transmute(a), transmute(b)));
+        let r = i16x4::from(vbic_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s16() {
+    fn test_vbicq_s16() {
         let a = i16x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = i16x8::new(0, -2, -2, -4, -4, -6, -6, -8);
-        let r: i16x8 = transmute(vbicq_s16(transmute(a), transmute(b)));
+        let r = i16x8::from(vbicq_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s32() {
+    fn test_vbic_s32() {
         let a = i32x2::new(0, -1);
         let b = i32x2::new(1, 1);
         let e = i32x2::new(0, -2);
-        let r: i32x2 = transmute(vbic_s32(transmute(a), transmute(b)));
+        let r = i32x2::from(vbic_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s32() {
+    fn test_vbicq_s32() {
         let a = i32x4::new(0, -1, -2, -3);
         let b = i32x4::new(1, 1, 1, 1);
         let e = i32x4::new(0, -2, -2, -4);
-        let r: i32x4 = transmute(vbicq_s32(transmute(a), transmute(b)));
+        let r = i32x4::from(vbicq_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s64() {
+    fn test_vbic_s64() {
         let a = i64x1::new(-1);
         let b = i64x1::new(1);
         let e = i64x1::new(-2);
-        let r: i64x1 = transmute(vbic_s64(transmute(a), transmute(b)));
+        let r = i64x1::from(vbic_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s64() {
+    fn test_vbicq_s64() {
         let a = i64x2::new(0, -1);
         let b = i64x2::new(1, 1);
         let e = i64x2::new(0, -2);
-        let r: i64x2 = transmute(vbicq_s64(transmute(a), transmute(b)));
+        let r = i64x2::from(vbicq_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u8() {
+    fn test_vbic_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let b = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = u8x8::new(0, 0, 2, 2, 4, 4, 6, 6);
-        let r: u8x8 = transmute(vbic_u8(transmute(a), transmute(b)));
+        let r = u8x8::from(vbic_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u8() {
+    fn test_vbicq_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let e = u8x16::new(0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14);
-        let r: u8x16 = transmute(vbicq_u8(transmute(a), transmute(b)));
+        let r = u8x16::from(vbicq_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u16() {
+    fn test_vbic_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let b = u16x4::new(1, 1, 1, 1);
         let e = u16x4::new(0, 0, 2, 2);
-        let r: u16x4 = transmute(vbic_u16(transmute(a), transmute(b)));
+        let r = u16x4::from(vbic_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u16() {
+    fn test_vbicq_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let b = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = u16x8::new(0, 0, 2, 2, 4, 4, 6, 6);
-        let r: u16x8 = transmute(vbicq_u16(transmute(a), transmute(b)));
+        let r = u16x8::from(vbicq_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u32() {
+    fn test_vbic_u32() {
         let a = u32x2::new(0, 1);
         let b = u32x2::new(1, 1);
         let e = u32x2::new(0, 0);
-        let r: u32x2 = transmute(vbic_u32(transmute(a), transmute(b)));
+        let r = u32x2::from(vbic_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u32() {
+    fn test_vbicq_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let b = u32x4::new(1, 1, 1, 1);
         let e = u32x4::new(0, 0, 2, 2);
-        let r: u32x4 = transmute(vbicq_u32(transmute(a), transmute(b)));
+        let r = u32x4::from(vbicq_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u64() {
+    fn test_vbic_u64() {
         let a = u64x1::new(1);
         let b = u64x1::new(1);
         let e = u64x1::new(0);
-        let r: u64x1 = transmute(vbic_u64(transmute(a), transmute(b)));
+        let r = u64x1::from(vbic_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u64() {
+    fn test_vbicq_u64() {
         let a = u64x2::new(0, 1);
         let b = u64x2::new(1, 1);
         let e = u64x2::new(0, 0);
-        let r: u64x2 = transmute(vbicq_u64(transmute(a), transmute(b)));
+        let r = u64x2::from(vbicq_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s8() {
+    fn test_vbsl_s8() {
         let a = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, 0, u8::MAX, 0);
         let b = i8x8::new(
             i8::MAX,
@@ -3174,38 +3185,42 @@ mod tests {
             i8::MAX,
             i8::MIN,
         );
-        let r: i8x8 = transmute(vbsl_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x8::from(vbsl_s8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s16() {
+    fn test_vbsl_s16() {
         let a = u16x4::new(u16::MAX, 0, 1, 2);
         let b = i16x4::new(i16::MAX, i16::MAX, i16::MAX, i16::MAX);
         let c = i16x4::new(i16::MIN, i16::MIN, i16::MIN, i16::MIN);
         let e = i16x4::new(i16::MAX, i16::MIN, i16::MIN | 1, i16::MIN | 2);
-        let r: i16x4 = transmute(vbsl_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x4::from(vbsl_s16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s32() {
+    fn test_vbsl_s32() {
         let a = u32x2::new(u32::MAX, 1);
         let b = i32x2::new(i32::MAX, i32::MAX);
         let c = i32x2::new(i32::MIN, i32::MIN);
         let e = i32x2::new(i32::MAX, i32::MIN | 1);
-        let r: i32x2 = transmute(vbsl_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x2::from(vbsl_s32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s64() {
+    fn test_vbsl_s64() {
         let a = u64x1::new(1);
         let b = i64x1::new(i64::MAX);
         let c = i64x1::new(i64::MIN);
         let e = i64x1::new(i64::MIN | 1);
-        let r: i64x1 = transmute(vbsl_s64(transmute(a), transmute(b), transmute(c)));
+        let r = i64x1::from(vbsl_s64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u8() {
+    fn test_vbsl_u8() {
         let a = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, 0, u8::MAX, 0);
         let b = u8x8::new(
             u8::MAX,
@@ -3228,47 +3243,52 @@ mod tests {
             u8::MIN,
         );
         let e = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, u8::MIN, u8::MAX, u8::MIN);
-        let r: u8x8 = transmute(vbsl_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x8::from(vbsl_u8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u16() {
+    fn test_vbsl_u16() {
         let a = u16x4::new(u16::MAX, 0, 1, 2);
         let b = u16x4::new(u16::MAX, u16::MAX, u16::MAX, u16::MAX);
         let c = u16x4::new(u16::MIN, u16::MIN, u16::MIN, u16::MIN);
         let e = u16x4::new(u16::MAX, 0, 1, 2);
-        let r: u16x4 = transmute(vbsl_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x4::from(vbsl_u16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u32() {
+    fn test_vbsl_u32() {
         let a = u32x2::new(u32::MAX, 2);
         let b = u32x2::new(u32::MAX, u32::MAX);
         let c = u32x2::new(u32::MIN, u32::MIN);
         let e = u32x2::new(u32::MAX, 2);
-        let r: u32x2 = transmute(vbsl_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x2::from(vbsl_u32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u64() {
+    fn test_vbsl_u64() {
         let a = u64x1::new(2);
         let b = u64x1::new(u64::MAX);
         let c = u64x1::new(u64::MIN);
         let e = u64x1::new(2);
-        let r: u64x1 = transmute(vbsl_u64(transmute(a), transmute(b), transmute(c)));
+        let r = u64x1::from(vbsl_u64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_f32() {
+    fn test_vbsl_f32() {
         let a = u32x2::new(1, 0x80000000);
         let b = f32x2::new(8388609f32, -1.23f32);
         let c = f32x2::new(2097152f32, 2.34f32);
         let e = f32x2::new(2097152.25f32, -2.34f32);
-        let r: f32x2 = transmute(vbsl_f32(transmute(a), transmute(b), transmute(c)));
+        let r = f32x2::from(vbsl_f32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_p8() {
+    fn test_vbsl_p8() {
         let a = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, 0, u8::MAX, 0);
         let b = u8x8::new(
             u8::MAX,
@@ -3291,20 +3311,22 @@ mod tests {
             u8::MIN,
         );
         let e = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, u8::MIN, u8::MAX, u8::MIN);
-        let r: u8x8 = transmute(vbsl_p8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x8::from(vbsl_p8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_p16() {
+    fn test_vbsl_p16() {
         let a = u16x4::new(u16::MAX, 0, 1, 2);
         let b = u16x4::new(u16::MAX, u16::MAX, u16::MAX, u16::MAX);
         let c = u16x4::new(u16::MIN, u16::MIN, u16::MIN, u16::MIN);
         let e = u16x4::new(u16::MAX, 0, 1, 2);
-        let r: u16x4 = transmute(vbsl_p16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x4::from(vbsl_p16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s8() {
+    fn test_vbslq_s8() {
         let a = u8x16::new(
             u8::MAX,
             1,
@@ -3377,11 +3399,12 @@ mod tests {
             i8::MAX,
             i8::MIN,
         );
-        let r: i8x16 = transmute(vbslq_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x16::from(vbslq_s8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s16() {
+    fn test_vbslq_s16() {
         let a = u16x8::new(u16::MAX, 1, u16::MAX, 2, u16::MAX, 0, u16::MAX, 0);
         let b = i16x8::new(
             i16::MAX,
@@ -3413,29 +3436,32 @@ mod tests {
             i16::MAX,
             i16::MIN,
         );
-        let r: i16x8 = transmute(vbslq_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x8::from(vbslq_s16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s32() {
+    fn test_vbslq_s32() {
         let a = u32x4::new(u32::MAX, 1, u32::MAX, 2);
         let b = i32x4::new(i32::MAX, i32::MAX, i32::MAX, i32::MAX);
         let c = i32x4::new(i32::MIN, i32::MIN, i32::MIN, i32::MIN);
         let e = i32x4::new(i32::MAX, i32::MIN | 1, i32::MAX, i32::MIN | 2);
-        let r: i32x4 = transmute(vbslq_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x4::from(vbslq_s32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s64() {
+    fn test_vbslq_s64() {
         let a = u64x2::new(u64::MAX, 1);
         let b = i64x2::new(i64::MAX, i64::MAX);
         let c = i64x2::new(i64::MIN, i64::MIN);
         let e = i64x2::new(i64::MAX, i64::MIN | 1);
-        let r: i64x2 = transmute(vbslq_s64(transmute(a), transmute(b), transmute(c)));
+        let r = i64x2::from(vbslq_s64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u8() {
+    fn test_vbslq_u8() {
         let a = u8x16::new(
             u8::MAX,
             1,
@@ -3508,11 +3534,12 @@ mod tests {
             u8::MAX,
             u8::MIN,
         );
-        let r: u8x16 = transmute(vbslq_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x16::from(vbslq_u8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u16() {
+    fn test_vbslq_u16() {
         let a = u16x8::new(u16::MAX, 1, u16::MAX, 2, u16::MAX, 0, u16::MAX, 0);
         let b = u16x8::new(
             u16::MAX,
@@ -3544,38 +3571,42 @@ mod tests {
             u16::MAX,
             u16::MIN,
         );
-        let r: u16x8 = transmute(vbslq_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x8::from(vbslq_u16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u32() {
+    fn test_vbslq_u32() {
         let a = u32x4::new(u32::MAX, 1, u32::MAX, 2);
         let b = u32x4::new(u32::MAX, u32::MAX, u32::MAX, u32::MAX);
         let c = u32x4::new(u32::MIN, u32::MIN, u32::MIN, u32::MIN);
         let e = u32x4::new(u32::MAX, 1, u32::MAX, 2);
-        let r: u32x4 = transmute(vbslq_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x4::from(vbslq_u32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u64() {
+    fn test_vbslq_u64() {
         let a = u64x2::new(u64::MAX, 1);
         let b = u64x2::new(u64::MAX, u64::MAX);
         let c = u64x2::new(u64::MIN, u64::MIN);
         let e = u64x2::new(u64::MAX, 1);
-        let r: u64x2 = transmute(vbslq_u64(transmute(a), transmute(b), transmute(c)));
+        let r = u64x2::from(vbslq_u64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_f32() {
+    fn test_vbslq_f32() {
         let a = u32x4::new(u32::MAX, 0, 1, 0x80000000);
         let b = f32x4::new(-1.23f32, -1.23f32, 8388609f32, -1.23f32);
         let c = f32x4::new(2.34f32, 2.34f32, 2097152f32, 2.34f32);
         let e = f32x4::new(-1.23f32, 2.34f32, 2097152.25f32, -2.34f32);
-        let r: f32x4 = transmute(vbslq_f32(transmute(a), transmute(b), transmute(c)));
+        let r = f32x4::from(vbslq_f32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_p8() {
+    fn test_vbslq_p8() {
         let a = u8x16::new(
             u8::MAX,
             1,
@@ -3648,11 +3679,12 @@ mod tests {
             u8::MAX,
             u8::MIN,
         );
-        let r: u8x16 = transmute(vbslq_p8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x16::from(vbslq_p8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_p16() {
+    fn test_vbslq_p16() {
         let a = u16x8::new(u16::MAX, 1, u16::MAX, 2, u16::MAX, 0, u16::MAX, 0);
         let b = u16x8::new(
             u16::MAX,
@@ -3684,21 +3716,21 @@ mod tests {
             u16::MAX,
             u16::MIN,
         );
-        let r: u16x8 = transmute(vbslq_p16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x8::from(vbslq_p16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s8() {
+    fn test_vorn_s8() {
         let a = i8x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i8x8::new(-2, -2, -2, -2, -2, -2, -2, -2);
         let e = i8x8::new(1, -1, -1, -3, -3, -5, -5, -7);
-        let r: i8x8 = transmute(vorn_s8(transmute(a), transmute(b)));
+        let r = i8x8::from(vorn_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s8() {
+    fn test_vornq_s8() {
         let a = i8x16::new(
             0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
         );
@@ -3708,475 +3740,522 @@ mod tests {
         let e = i8x16::new(
             1, -1, -1, -3, -3, -5, -5, -7, -7, -9, -9, -11, -11, -13, -13, -15,
         );
-        let r: i8x16 = transmute(vornq_s8(transmute(a), transmute(b)));
+        let r = i8x16::from(vornq_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s16() {
+    fn test_vorn_s16() {
         let a = i16x4::new(0, -1, -2, -3);
         let b = i16x4::new(-2, -2, -2, -2);
         let e = i16x4::new(1, -1, -1, -3);
-        let r: i16x4 = transmute(vorn_s16(transmute(a), transmute(b)));
+        let r = i16x4::from(vorn_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s16() {
+    fn test_vornq_s16() {
         let a = i16x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i16x8::new(-2, -2, -2, -2, -2, -2, -2, -2);
         let e = i16x8::new(1, -1, -1, -3, -3, -5, -5, -7);
-        let r: i16x8 = transmute(vornq_s16(transmute(a), transmute(b)));
+        let r = i16x8::from(vornq_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s32() {
+    fn test_vorn_s32() {
         let a = i32x2::new(0, -1);
         let b = i32x2::new(-2, -2);
         let e = i32x2::new(1, -1);
-        let r: i32x2 = transmute(vorn_s32(transmute(a), transmute(b)));
+        let r = i32x2::from(vorn_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s32() {
+    fn test_vornq_s32() {
         let a = i32x4::new(0, -1, -2, -3);
         let b = i32x4::new(-2, -2, -2, -2);
         let e = i32x4::new(1, -1, -1, -3);
-        let r: i32x4 = transmute(vornq_s32(transmute(a), transmute(b)));
+        let r = i32x4::from(vornq_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s64() {
+    fn test_vorn_s64() {
         let a = i64x1::new(0);
         let b = i64x1::new(-2);
         let e = i64x1::new(1);
-        let r: i64x1 = transmute(vorn_s64(transmute(a), transmute(b)));
+        let r = i64x1::from(vorn_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s64() {
+    fn test_vornq_s64() {
         let a = i64x2::new(0, -1);
         let b = i64x2::new(-2, -2);
         let e = i64x2::new(1, -1);
-        let r: i64x2 = transmute(vornq_s64(transmute(a), transmute(b)));
+        let r = i64x2::from(vornq_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u8() {
+    fn test_vorn_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let t = u8::MAX - 1;
         let b = u8x8::new(t, t, t, t, t, t, t, t);
         let e = u8x8::new(1, 1, 3, 3, 5, 5, 7, 7);
-        let r: u8x8 = transmute(vorn_u8(transmute(a), transmute(b)));
+        let r = u8x8::from(vorn_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u8() {
+    fn test_vornq_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let t = u8::MAX - 1;
         let b = u8x16::new(t, t, t, t, t, t, t, t, t, t, t, t, t, t, t, t);
         let e = u8x16::new(1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15);
-        let r: u8x16 = transmute(vornq_u8(transmute(a), transmute(b)));
+        let r = u8x16::from(vornq_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u16() {
+    fn test_vorn_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let t = u16::MAX - 1;
         let b = u16x4::new(t, t, t, t);
         let e = u16x4::new(1, 1, 3, 3);
-        let r: u16x4 = transmute(vorn_u16(transmute(a), transmute(b)));
+        let r = u16x4::from(vorn_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u16() {
+    fn test_vornq_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let t = u16::MAX - 1;
         let b = u16x8::new(t, t, t, t, t, t, t, t);
         let e = u16x8::new(1, 1, 3, 3, 5, 5, 7, 7);
-        let r: u16x8 = transmute(vornq_u16(transmute(a), transmute(b)));
+        let r = u16x8::from(vornq_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u32() {
+    fn test_vorn_u32() {
         let a = u32x2::new(0, 1);
         let t = u32::MAX - 1;
         let b = u32x2::new(t, t);
         let e = u32x2::new(1, 1);
-        let r: u32x2 = transmute(vorn_u32(transmute(a), transmute(b)));
+        let r = u32x2::from(vorn_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u32() {
+    fn test_vornq_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let t = u32::MAX - 1;
         let b = u32x4::new(t, t, t, t);
         let e = u32x4::new(1, 1, 3, 3);
-        let r: u32x4 = transmute(vornq_u32(transmute(a), transmute(b)));
+        let r = u32x4::from(vornq_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u64() {
+    fn test_vorn_u64() {
         let a = u64x1::new(0);
         let t = u64::MAX - 1;
         let b = u64x1::new(t);
         let e = u64x1::new(1);
-        let r: u64x1 = transmute(vorn_u64(transmute(a), transmute(b)));
+        let r = u64x1::from(vorn_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u64() {
+    fn test_vornq_u64() {
         let a = u64x2::new(0, 1);
         let t = u64::MAX - 1;
         let b = u64x2::new(t, t);
         let e = u64x2::new(1, 1);
-        let r: u64x2 = transmute(vornq_u64(transmute(a), transmute(b)));
+        let r = u64x2::from(vornq_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_s16() {
+    fn test_vmovn_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: i8x8 = transmute(vmovn_s16(transmute(a)));
+        let r = i8x8::from(vmovn_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_s32() {
+    fn test_vmovn_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let e = i16x4::new(1, 2, 3, 4);
-        let r: i16x4 = transmute(vmovn_s32(transmute(a)));
+        let r = i16x4::from(vmovn_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_s64() {
+    fn test_vmovn_s64() {
         let a = i64x2::new(1, 2);
         let e = i32x2::new(1, 2);
-        let r: i32x2 = transmute(vmovn_s64(transmute(a)));
+        let r = i32x2::from(vmovn_s64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_u16() {
+    fn test_vmovn_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u8x8 = transmute(vmovn_u16(transmute(a)));
+        let r = u8x8::from(vmovn_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_u32() {
+    fn test_vmovn_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let e = u16x4::new(1, 2, 3, 4);
-        let r: u16x4 = transmute(vmovn_u32(transmute(a)));
+        let r = u16x4::from(vmovn_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_u64() {
+    fn test_vmovn_u64() {
         let a = u64x2::new(1, 2);
         let e = u32x2::new(1, 2);
-        let r: u32x2 = transmute(vmovn_u64(transmute(a)));
+        let r = u32x2::from(vmovn_u64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_s8() {
+    fn test_vmovl_s8() {
         let e = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: i16x8 = transmute(vmovl_s8(transmute(a)));
+        let r = i16x8::from(vmovl_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_s16() {
+    fn test_vmovl_s16() {
         let e = i32x4::new(1, 2, 3, 4);
         let a = i16x4::new(1, 2, 3, 4);
-        let r: i32x4 = transmute(vmovl_s16(transmute(a)));
+        let r = i32x4::from(vmovl_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_s32() {
+    fn test_vmovl_s32() {
         let e = i64x2::new(1, 2);
         let a = i32x2::new(1, 2);
-        let r: i64x2 = transmute(vmovl_s32(transmute(a)));
+        let r = i64x2::from(vmovl_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_u8() {
+    fn test_vmovl_u8() {
         let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u16x8 = transmute(vmovl_u8(transmute(a)));
+        let r = u16x8::from(vmovl_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_u16() {
+    fn test_vmovl_u16() {
         let e = u32x4::new(1, 2, 3, 4);
         let a = u16x4::new(1, 2, 3, 4);
-        let r: u32x4 = transmute(vmovl_u16(transmute(a)));
+        let r = u32x4::from(vmovl_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_u32() {
+    fn test_vmovl_u32() {
         let e = u64x2::new(1, 2);
         let a = u32x2::new(1, 2);
-        let r: u64x2 = transmute(vmovl_u32(transmute(a)));
+        let r = u64x2::from(vmovl_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s8() {
+    fn test_vand_s8() {
         test_bit_s8(|i, j| vand_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s8() {
+    fn test_vandq_s8() {
         testq_bit_s8(|i, j| vandq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s16() {
+    fn test_vand_s16() {
         test_bit_s16(|i, j| vand_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s16() {
+    fn test_vandq_s16() {
         testq_bit_s16(|i, j| vandq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s32() {
+    fn test_vand_s32() {
         test_bit_s32(|i, j| vand_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s32() {
+    fn test_vandq_s32() {
         testq_bit_s32(|i, j| vandq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s64() {
+    fn test_vand_s64() {
         test_bit_s64(|i, j| vand_s64(i, j), |a: i64, b: i64| -> i64 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s64() {
+    fn test_vandq_s64() {
         testq_bit_s64(|i, j| vandq_s64(i, j), |a: i64, b: i64| -> i64 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u8() {
+    fn test_vand_u8() {
         test_bit_u8(|i, j| vand_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u8() {
+    fn test_vandq_u8() {
         testq_bit_u8(|i, j| vandq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u16() {
+    fn test_vand_u16() {
         test_bit_u16(|i, j| vand_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u16() {
+    fn test_vandq_u16() {
         testq_bit_u16(|i, j| vandq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u32() {
+    fn test_vand_u32() {
         test_bit_u32(|i, j| vand_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u32() {
+    fn test_vandq_u32() {
         testq_bit_u32(|i, j| vandq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u64() {
+    fn test_vand_u64() {
         test_bit_u64(|i, j| vand_u64(i, j), |a: u64, b: u64| -> u64 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u64() {
+    fn test_vandq_u64() {
         testq_bit_u64(|i, j| vandq_u64(i, j), |a: u64, b: u64| -> u64 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s8() {
+    fn test_vorr_s8() {
         test_bit_s8(|i, j| vorr_s8(i, j), |a: i8, b: i8| -> i8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s8() {
+    fn test_vorrq_s8() {
         testq_bit_s8(|i, j| vorrq_s8(i, j), |a: i8, b: i8| -> i8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s16() {
+    fn test_vorr_s16() {
         test_bit_s16(|i, j| vorr_s16(i, j), |a: i16, b: i16| -> i16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s16() {
+    fn test_vorrq_s16() {
         testq_bit_s16(|i, j| vorrq_s16(i, j), |a: i16, b: i16| -> i16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s32() {
+    fn test_vorr_s32() {
         test_bit_s32(|i, j| vorr_s32(i, j), |a: i32, b: i32| -> i32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s32() {
+    fn test_vorrq_s32() {
         testq_bit_s32(|i, j| vorrq_s32(i, j), |a: i32, b: i32| -> i32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s64() {
+    fn test_vorr_s64() {
         test_bit_s64(|i, j| vorr_s64(i, j), |a: i64, b: i64| -> i64 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s64() {
+    fn test_vorrq_s64() {
         testq_bit_s64(|i, j| vorrq_s64(i, j), |a: i64, b: i64| -> i64 { a | b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u8() {
+    fn test_vorr_u8() {
         test_bit_u8(|i, j| vorr_u8(i, j), |a: u8, b: u8| -> u8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u8() {
+    fn test_vorrq_u8() {
         testq_bit_u8(|i, j| vorrq_u8(i, j), |a: u8, b: u8| -> u8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u16() {
+    fn test_vorr_u16() {
         test_bit_u16(|i, j| vorr_u16(i, j), |a: u16, b: u16| -> u16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u16() {
+    fn test_vorrq_u16() {
         testq_bit_u16(|i, j| vorrq_u16(i, j), |a: u16, b: u16| -> u16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u32() {
+    fn test_vorr_u32() {
         test_bit_u32(|i, j| vorr_u32(i, j), |a: u32, b: u32| -> u32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u32() {
+    fn test_vorrq_u32() {
         testq_bit_u32(|i, j| vorrq_u32(i, j), |a: u32, b: u32| -> u32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u64() {
+    fn test_vorr_u64() {
         test_bit_u64(|i, j| vorr_u64(i, j), |a: u64, b: u64| -> u64 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u64() {
+    fn test_vorrq_u64() {
         testq_bit_u64(|i, j| vorrq_u64(i, j), |a: u64, b: u64| -> u64 { a | b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s8() {
+    fn test_veor_s8() {
         test_bit_s8(|i, j| veor_s8(i, j), |a: i8, b: i8| -> i8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s8() {
+    fn test_veorq_s8() {
         testq_bit_s8(|i, j| veorq_s8(i, j), |a: i8, b: i8| -> i8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s16() {
+    fn test_veor_s16() {
         test_bit_s16(|i, j| veor_s16(i, j), |a: i16, b: i16| -> i16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s16() {
+    fn test_veorq_s16() {
         testq_bit_s16(|i, j| veorq_s16(i, j), |a: i16, b: i16| -> i16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s32() {
+    fn test_veor_s32() {
         test_bit_s32(|i, j| veor_s32(i, j), |a: i32, b: i32| -> i32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s32() {
+    fn test_veorq_s32() {
         testq_bit_s32(|i, j| veorq_s32(i, j), |a: i32, b: i32| -> i32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s64() {
+    fn test_veor_s64() {
         test_bit_s64(|i, j| veor_s64(i, j), |a: i64, b: i64| -> i64 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s64() {
+    fn test_veorq_s64() {
         testq_bit_s64(|i, j| veorq_s64(i, j), |a: i64, b: i64| -> i64 { a ^ b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u8() {
+    fn test_veor_u8() {
         test_bit_u8(|i, j| veor_u8(i, j), |a: u8, b: u8| -> u8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u8() {
+    fn test_veorq_u8() {
         testq_bit_u8(|i, j| veorq_u8(i, j), |a: u8, b: u8| -> u8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u16() {
+    fn test_veor_u16() {
         test_bit_u16(|i, j| veor_u16(i, j), |a: u16, b: u16| -> u16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u16() {
+    fn test_veorq_u16() {
         testq_bit_u16(|i, j| veorq_u16(i, j), |a: u16, b: u16| -> u16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u32() {
+    fn test_veor_u32() {
         test_bit_u32(|i, j| veor_u32(i, j), |a: u32, b: u32| -> u32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u32() {
+    fn test_veorq_u32() {
         testq_bit_u32(|i, j| veorq_u32(i, j), |a: u32, b: u32| -> u32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u64() {
+    fn test_veor_u64() {
         test_bit_u64(|i, j| veor_u64(i, j), |a: u64, b: u64| -> u64 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u64() {
+    fn test_veorq_u64() {
         testq_bit_u64(|i, j| veorq_u64(i, j), |a: u64, b: u64| -> u64 { a ^ b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_s8() {
+    fn test_vceq_s8() {
         test_cmp_s8(
             |i, j| vceq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_s8() {
+    fn test_vceqq_s8() {
         testq_cmp_s8(
             |i, j| vceqq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_s16() {
+    fn test_vceq_s16() {
         test_cmp_s16(
             |i, j| vceq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_s16() {
+    fn test_vceqq_s16() {
         testq_cmp_s16(
             |i, j| vceqq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_s32() {
+    fn test_vceq_s32() {
         test_cmp_s32(
             |i, j| vceq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_s32() {
+    fn test_vceqq_s32() {
         testq_cmp_s32(
             |i, j| vceqq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
@@ -4184,42 +4263,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_u8() {
+    fn test_vceq_u8() {
         test_cmp_u8(
             |i, j| vceq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_u8() {
+    fn test_vceqq_u8() {
         testq_cmp_u8(
             |i, j| vceqq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_u16() {
+    fn test_vceq_u16() {
         test_cmp_u16(
             |i, j| vceq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_u16() {
+    fn test_vceqq_u16() {
         testq_cmp_u16(
             |i, j| vceqq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_u32() {
+    fn test_vceq_u32() {
         test_cmp_u32(
             |i, j| vceq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_u32() {
+    fn test_vceqq_u32() {
         testq_cmp_u32(
             |i, j| vceqq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
@@ -4227,14 +4311,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_f32() {
+    fn test_vceq_f32() {
         test_cmp_f32(
             |i, j| vcge_f32(i, j),
             |a: f32, b: f32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_f32() {
+    fn test_vceqq_f32() {
         testq_cmp_f32(
             |i, j| vcgeq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
@@ -4242,42 +4327,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_s8() {
+    fn test_vcgt_s8() {
         test_cmp_s8(
             |i, j| vcgt_s8(i, j),
             |a: i8, b: i8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_s8() {
+    fn test_vcgtq_s8() {
         testq_cmp_s8(
             |i, j| vcgtq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_s16() {
+    fn test_vcgt_s16() {
         test_cmp_s16(
             |i, j| vcgt_s16(i, j),
             |a: i16, b: i16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_s16() {
+    fn test_vcgtq_s16() {
         testq_cmp_s16(
             |i, j| vcgtq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_s32() {
+    fn test_vcgt_s32() {
         test_cmp_s32(
             |i, j| vcgt_s32(i, j),
             |a: i32, b: i32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_s32() {
+    fn test_vcgtq_s32() {
         testq_cmp_s32(
             |i, j| vcgtq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
@@ -4285,42 +4375,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_u8() {
+    fn test_vcgt_u8() {
         test_cmp_u8(
             |i, j| vcgt_u8(i, j),
             |a: u8, b: u8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_u8() {
+    fn test_vcgtq_u8() {
         testq_cmp_u8(
             |i, j| vcgtq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_u16() {
+    fn test_vcgt_u16() {
         test_cmp_u16(
             |i, j| vcgt_u16(i, j),
             |a: u16, b: u16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_u16() {
+    fn test_vcgtq_u16() {
         testq_cmp_u16(
             |i, j| vcgtq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_u32() {
+    fn test_vcgt_u32() {
         test_cmp_u32(
             |i, j| vcgt_u32(i, j),
             |a: u32, b: u32| -> u32 { if a > b { 0xFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_u32() {
+    fn test_vcgtq_u32() {
         testq_cmp_u32(
             |i, j| vcgtq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
@@ -4328,14 +4423,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_f32() {
+    fn test_vcgt_f32() {
         test_cmp_f32(
             |i, j| vcgt_f32(i, j),
             |a: f32, b: f32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_f32() {
+    fn test_vcgtq_f32() {
         testq_cmp_f32(
             |i, j| vcgtq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
@@ -4343,42 +4439,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_s8() {
+    fn test_vclt_s8() {
         test_cmp_s8(
             |i, j| vclt_s8(i, j),
             |a: i8, b: i8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_s8() {
+    fn test_vcltq_s8() {
         testq_cmp_s8(
             |i, j| vcltq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_s16() {
+    fn test_vclt_s16() {
         test_cmp_s16(
             |i, j| vclt_s16(i, j),
             |a: i16, b: i16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_s16() {
+    fn test_vcltq_s16() {
         testq_cmp_s16(
             |i, j| vcltq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_s32() {
+    fn test_vclt_s32() {
         test_cmp_s32(
             |i, j| vclt_s32(i, j),
             |a: i32, b: i32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_s32() {
+    fn test_vcltq_s32() {
         testq_cmp_s32(
             |i, j| vcltq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
@@ -4386,42 +4487,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_u8() {
+    fn test_vclt_u8() {
         test_cmp_u8(
             |i, j| vclt_u8(i, j),
             |a: u8, b: u8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_u8() {
+    fn test_vcltq_u8() {
         testq_cmp_u8(
             |i, j| vcltq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_u16() {
+    fn test_vclt_u16() {
         test_cmp_u16(
             |i, j| vclt_u16(i, j),
             |a: u16, b: u16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_u16() {
+    fn test_vcltq_u16() {
         testq_cmp_u16(
             |i, j| vcltq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_u32() {
+    fn test_vclt_u32() {
         test_cmp_u32(
             |i, j| vclt_u32(i, j),
             |a: u32, b: u32| -> u32 { if a < b { 0xFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_u32() {
+    fn test_vcltq_u32() {
         testq_cmp_u32(
             |i, j| vcltq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
@@ -4429,14 +4535,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_f32() {
+    fn test_vclt_f32() {
         test_cmp_f32(
             |i, j| vclt_f32(i, j),
             |a: f32, b: f32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_f32() {
+    fn test_vcltq_f32() {
         testq_cmp_f32(
             |i, j| vcltq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
@@ -4444,42 +4551,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_s8() {
+    fn test_vcle_s8() {
         test_cmp_s8(
             |i, j| vcle_s8(i, j),
             |a: i8, b: i8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_s8() {
+    fn test_vcleq_s8() {
         testq_cmp_s8(
             |i, j| vcleq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_s16() {
+    fn test_vcle_s16() {
         test_cmp_s16(
             |i, j| vcle_s16(i, j),
             |a: i16, b: i16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_s16() {
+    fn test_vcleq_s16() {
         testq_cmp_s16(
             |i, j| vcleq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_s32() {
+    fn test_vcle_s32() {
         test_cmp_s32(
             |i, j| vcle_s32(i, j),
             |a: i32, b: i32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_s32() {
+    fn test_vcleq_s32() {
         testq_cmp_s32(
             |i, j| vcleq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
@@ -4487,42 +4599,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_u8() {
+    fn test_vcle_u8() {
         test_cmp_u8(
             |i, j| vcle_u8(i, j),
             |a: u8, b: u8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_u8() {
+    fn test_vcleq_u8() {
         testq_cmp_u8(
             |i, j| vcleq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_u16() {
+    fn test_vcle_u16() {
         test_cmp_u16(
             |i, j| vcle_u16(i, j),
             |a: u16, b: u16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_u16() {
+    fn test_vcleq_u16() {
         testq_cmp_u16(
             |i, j| vcleq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_u32() {
+    fn test_vcle_u32() {
         test_cmp_u32(
             |i, j| vcle_u32(i, j),
             |a: u32, b: u32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_u32() {
+    fn test_vcleq_u32() {
         testq_cmp_u32(
             |i, j| vcleq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
@@ -4530,14 +4647,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_f32() {
+    fn test_vcle_f32() {
         test_cmp_f32(
             |i, j| vcle_f32(i, j),
             |a: f32, b: f32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_f32() {
+    fn test_vcleq_f32() {
         testq_cmp_f32(
             |i, j| vcleq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
@@ -4545,42 +4663,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_s8() {
+    fn test_vcge_s8() {
         test_cmp_s8(
             |i, j| vcge_s8(i, j),
             |a: i8, b: i8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_s8() {
+    fn test_vcgeq_s8() {
         testq_cmp_s8(
             |i, j| vcgeq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_s16() {
+    fn test_vcge_s16() {
         test_cmp_s16(
             |i, j| vcge_s16(i, j),
             |a: i16, b: i16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_s16() {
+    fn test_vcgeq_s16() {
         testq_cmp_s16(
             |i, j| vcgeq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_s32() {
+    fn test_vcge_s32() {
         test_cmp_s32(
             |i, j| vcge_s32(i, j),
             |a: i32, b: i32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_s32() {
+    fn test_vcgeq_s32() {
         testq_cmp_s32(
             |i, j| vcgeq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
@@ -4588,42 +4711,45 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_u8() {
+    fn test_vcge_u8() {
         test_cmp_u8(
             |i, j| vcge_u8(i, j),
             |a: u8, b: u8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_u8() {
+    fn test_vcgeq_u8() {
         testq_cmp_u8(
             |i, j| vcgeq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_u16() {
+    fn test_vcge_u16() {
         test_cmp_u16(
             |i, j| vcge_u16(i, j),
             |a: u16, b: u16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_u16() {
+    fn test_vcgeq_u16() {
         testq_cmp_u16(
             |i, j| vcgeq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_u32() {
+    fn test_vcge_u32() {
         test_cmp_u32(
             |i, j| vcge_u32(i, j),
             |a: u32, b: u32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_u32() {
+    fn test_vcgeq_u32() {
         testq_cmp_u32(
             |i, j| vcgeq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
@@ -4631,14 +4757,14 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_f32() {
+    fn test_vcge_f32() {
         test_cmp_f32(
             |i, j| vcge_f32(i, j),
             |a: f32, b: f32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_f32() {
+    fn test_vcgeq_f32() {
         testq_cmp_f32(
             |i, j| vcgeq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
@@ -4646,42 +4772,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_s8() {
+    fn test_vqsub_s8() {
         test_ari_s8(
             |i, j| vqsub_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_s8() {
+    fn test_vqsubq_s8() {
         testq_ari_s8(
             |i, j| vqsubq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_s16() {
+    fn test_vqsub_s16() {
         test_ari_s16(
             |i, j| vqsub_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_s16() {
+    fn test_vqsubq_s16() {
         testq_ari_s16(
             |i, j| vqsubq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_s32() {
+    fn test_vqsub_s32() {
         test_ari_s32(
             |i, j| vqsub_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_s32() {
+    fn test_vqsubq_s32() {
         testq_ari_s32(
             |i, j| vqsubq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_sub(b) },
@@ -4689,42 +4820,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_u8() {
+    fn test_vqsub_u8() {
         test_ari_u8(
             |i, j| vqsub_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_u8() {
+    fn test_vqsubq_u8() {
         testq_ari_u8(
             |i, j| vqsubq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_u16() {
+    fn test_vqsub_u16() {
         test_ari_u16(
             |i, j| vqsub_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_u16() {
+    fn test_vqsubq_u16() {
         testq_ari_u16(
             |i, j| vqsubq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_u32() {
+    fn test_vqsub_u32() {
         test_ari_u32(
             |i, j| vqsub_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_u32() {
+    fn test_vqsubq_u32() {
         testq_ari_u32(
             |i, j| vqsubq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_sub(b) },
@@ -4732,142 +4868,166 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_s8() {
+    fn test_vhadd_s8() {
         test_ari_s8(|i, j| vhadd_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_s8() {
+    fn test_vhaddq_s8() {
         testq_ari_s8(|i, j| vhaddq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_s16() {
+    fn test_vhadd_s16() {
         test_ari_s16(|i, j| vhadd_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_s16() {
+    fn test_vhaddq_s16() {
         testq_ari_s16(|i, j| vhaddq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_s32() {
+    fn test_vhadd_s32() {
         test_ari_s32(|i, j| vhadd_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_s32() {
+    fn test_vhaddq_s32() {
         testq_ari_s32(|i, j| vhaddq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_u8() {
+    fn test_vhadd_u8() {
         test_ari_u8(|i, j| vhadd_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_u8() {
+    fn test_vhaddq_u8() {
         testq_ari_u8(|i, j| vhaddq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_u16() {
+    fn test_vhadd_u16() {
         test_ari_u16(|i, j| vhadd_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_u16() {
+    fn test_vhaddq_u16() {
         testq_ari_u16(|i, j| vhaddq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_u32() {
+    fn test_vhadd_u32() {
         test_ari_u32(|i, j| vhadd_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_u32() {
+    fn test_vhaddq_u32() {
         testq_ari_u32(|i, j| vhaddq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_s8() {
+    fn test_vrhadd_s8() {
         test_ari_s8(|i, j| vrhadd_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_s8() {
+    fn test_vrhaddq_s8() {
         testq_ari_s8(|i, j| vrhaddq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_s16() {
+    fn test_vrhadd_s16() {
         test_ari_s16(|i, j| vrhadd_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_s16() {
+    fn test_vrhaddq_s16() {
         testq_ari_s16(|i, j| vrhaddq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_s32() {
+    fn test_vrhadd_s32() {
         test_ari_s32(|i, j| vrhadd_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_s32() {
+    fn test_vrhaddq_s32() {
         testq_ari_s32(|i, j| vrhaddq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_u8() {
+    fn test_vrhadd_u8() {
         test_ari_u8(|i, j| vrhadd_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_u8() {
+    fn test_vrhaddq_u8() {
         testq_ari_u8(|i, j| vrhaddq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_u16() {
+    fn test_vrhadd_u16() {
         test_ari_u16(|i, j| vrhadd_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_u16() {
+    fn test_vrhaddq_u16() {
         testq_ari_u16(|i, j| vrhaddq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_u32() {
+    fn test_vrhadd_u32() {
         test_ari_u32(|i, j| vrhadd_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_u32() {
+    fn test_vrhaddq_u32() {
         testq_ari_u32(|i, j| vrhaddq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_s8() {
+    fn test_vqadd_s8() {
         test_ari_s8(
             |i, j| vqadd_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_s8() {
+    fn test_vqaddq_s8() {
         testq_ari_s8(
             |i, j| vqaddq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_s16() {
+    fn test_vqadd_s16() {
         test_ari_s16(
             |i, j| vqadd_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_s16() {
+    fn test_vqaddq_s16() {
         testq_ari_s16(
             |i, j| vqaddq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_s32() {
+    fn test_vqadd_s32() {
         test_ari_s32(
             |i, j| vqadd_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_add(b) },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_s32() {
+    fn test_vqaddq_s32() {
         testq_ari_s32(
             |i, j| vqaddq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_add(b) },
@@ -4875,42 +5035,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_u8() {
+    fn test_vqadd_u8() {
         test_ari_u8(
             |i, j| vqadd_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_u8() {
+    fn test_vqaddq_u8() {
         testq_ari_u8(
             |i, j| vqaddq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_u16() {
+    fn test_vqadd_u16() {
         test_ari_u16(
             |i, j| vqadd_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_u16() {
+    fn test_vqaddq_u16() {
         testq_ari_u16(
             |i, j| vqaddq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_u32() {
+    fn test_vqadd_u32() {
         test_ari_u32(
             |i, j| vqadd_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_u32() {
+    fn test_vqaddq_u32() {
         testq_ari_u32(
             |i, j| vqaddq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_add(b) },
@@ -4918,42 +5083,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_s8() {
+    fn test_vmul_s8() {
         test_ari_s8(
             |i, j| vmul_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_s8() {
+    fn test_vmulq_s8() {
         testq_ari_s8(
             |i, j| vmulq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_s16() {
+    fn test_vmul_s16() {
         test_ari_s16(
             |i, j| vmul_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_s16() {
+    fn test_vmulq_s16() {
         testq_ari_s16(
             |i, j| vmulq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_s32() {
+    fn test_vmul_s32() {
         test_ari_s32(
             |i, j| vmul_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_s32() {
+    fn test_vmulq_s32() {
         testq_ari_s32(
             |i, j| vmulq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_mul(b).0 },
@@ -4961,42 +5131,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_u8() {
+    fn test_vmul_u8() {
         test_ari_u8(
             |i, j| vmul_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_u8() {
+    fn test_vmulq_u8() {
         testq_ari_u8(
             |i, j| vmulq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_u16() {
+    fn test_vmul_u16() {
         test_ari_u16(
             |i, j| vmul_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_u16() {
+    fn test_vmulq_u16() {
         testq_ari_u16(
             |i, j| vmulq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_u32() {
+    fn test_vmul_u32() {
         test_ari_u32(
             |i, j| vmul_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_u32() {
+    fn test_vmulq_u32() {
         testq_ari_u32(
             |i, j| vmulq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_mul(b).0 },
@@ -5004,110 +5179,127 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_f32() {
+    fn test_vmul_f32() {
         test_ari_f32(|i, j| vmul_f32(i, j), |a: f32, b: f32| -> f32 { a * b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_f32() {
+    fn test_vmulq_f32() {
         testq_ari_f32(|i, j| vmulq_f32(i, j), |a: f32, b: f32| -> f32 { a * b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_s8() {
+    fn test_vsub_s8() {
         test_ari_s8(|i, j| vsub_s8(i, j), |a: i8, b: i8| -> i8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_s8() {
+    fn test_vsubq_s8() {
         testq_ari_s8(|i, j| vsubq_s8(i, j), |a: i8, b: i8| -> i8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_s16() {
+    fn test_vsub_s16() {
         test_ari_s16(|i, j| vsub_s16(i, j), |a: i16, b: i16| -> i16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_s16() {
+    fn test_vsubq_s16() {
         testq_ari_s16(|i, j| vsubq_s16(i, j), |a: i16, b: i16| -> i16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_s32() {
+    fn test_vsub_s32() {
         test_ari_s32(|i, j| vsub_s32(i, j), |a: i32, b: i32| -> i32 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_s32() {
+    fn test_vsubq_s32() {
         testq_ari_s32(|i, j| vsubq_s32(i, j), |a: i32, b: i32| -> i32 { a - b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_u8() {
+    fn test_vsub_u8() {
         test_ari_u8(|i, j| vsub_u8(i, j), |a: u8, b: u8| -> u8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_u8() {
+    fn test_vsubq_u8() {
         testq_ari_u8(|i, j| vsubq_u8(i, j), |a: u8, b: u8| -> u8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_u16() {
+    fn test_vsub_u16() {
         test_ari_u16(|i, j| vsub_u16(i, j), |a: u16, b: u16| -> u16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_u16() {
+    fn test_vsubq_u16() {
         testq_ari_u16(|i, j| vsubq_u16(i, j), |a: u16, b: u16| -> u16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_u32() {
+    fn test_vsub_u32() {
         test_ari_u32(|i, j| vsub_u32(i, j), |a: u32, b: u32| -> u32 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_u32() {
+    fn test_vsubq_u32() {
         testq_ari_u32(|i, j| vsubq_u32(i, j), |a: u32, b: u32| -> u32 { a - b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_f32() {
+    fn test_vsub_f32() {
         test_ari_f32(|i, j| vsub_f32(i, j), |a: f32, b: f32| -> f32 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_f32() {
+    fn test_vsubq_f32() {
         testq_ari_f32(|i, j| vsubq_f32(i, j), |a: f32, b: f32| -> f32 { a - b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_s8() {
+    fn test_vhsub_s8() {
         test_ari_s8(
             |i, j| vhsub_s8(i, j),
             |a: i8, b: i8| -> i8 { (((a as i16) - (b as i16)) / 2) as i8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_s8() {
+    fn test_vhsubq_s8() {
         testq_ari_s8(
             |i, j| vhsubq_s8(i, j),
             |a: i8, b: i8| -> i8 { (((a as i16) - (b as i16)) / 2) as i8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_s16() {
+    fn test_vhsub_s16() {
         test_ari_s16(
             |i, j| vhsub_s16(i, j),
             |a: i16, b: i16| -> i16 { (((a as i32) - (b as i32)) / 2) as i16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_s16() {
+    fn test_vhsubq_s16() {
         testq_ari_s16(
             |i, j| vhsubq_s16(i, j),
             |a: i16, b: i16| -> i16 { (((a as i32) - (b as i32)) / 2) as i16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_s32() {
+    fn test_vhsub_s32() {
         test_ari_s32(
             |i, j| vhsub_s32(i, j),
             |a: i32, b: i32| -> i32 { (((a as i64) - (b as i64)) / 2) as i32 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_s32() {
+    fn test_vhsubq_s32() {
         testq_ari_s32(
             |i, j| vhsubq_s32(i, j),
             |a: i32, b: i32| -> i32 { (((a as i64) - (b as i64)) / 2) as i32 },
@@ -5115,42 +5307,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_u8() {
+    fn test_vhsub_u8() {
         test_ari_u8(
             |i, j| vhsub_u8(i, j),
             |a: u8, b: u8| -> u8 { (((a as u16) - (b as u16)) / 2) as u8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_u8() {
+    fn test_vhsubq_u8() {
         testq_ari_u8(
             |i, j| vhsubq_u8(i, j),
             |a: u8, b: u8| -> u8 { (((a as u16) - (b as u16)) / 2) as u8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_u16() {
+    fn test_vhsub_u16() {
         test_ari_u16(
             |i, j| vhsub_u16(i, j),
             |a: u16, b: u16| -> u16 { (((a as u16) - (b as u16)) / 2) as u16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_u16() {
+    fn test_vhsubq_u16() {
         testq_ari_u16(
             |i, j| vhsubq_u16(i, j),
             |a: u16, b: u16| -> u16 { (((a as u16) - (b as u16)) / 2) as u16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_u32() {
+    fn test_vhsub_u32() {
         test_ari_u32(
             |i, j| vhsub_u32(i, j),
             |a: u32, b: u32| -> u32 { (((a as u64) - (b as u64)) / 2) as u32 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_u32() {
+    fn test_vhsubq_u32() {
         testq_ari_u32(
             |i, j| vhsubq_u32(i, j),
             |a: u32, b: u32| -> u32 { (((a as u64) - (b as u64)) / 2) as u32 },
@@ -5158,368 +5355,414 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_s8() {
+    fn test_vaba_s8() {
         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = i8x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: i8x8 = transmute(vaba_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x8::from(vaba_s8(a.into(), b.into(), c.into()));
         let e = i8x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_s16() {
+    fn test_vaba_s16() {
         let a = i16x4::new(1, 2, 3, 4);
         let b = i16x4::new(1, 1, 1, 1);
         let c = i16x4::new(10, 9, 8, 7);
-        let r: i16x4 = transmute(vaba_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x4::from(vaba_s16(a.into(), b.into(), c.into()));
         let e = i16x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_s32() {
+    fn test_vaba_s32() {
         let a = i32x2::new(1, 2);
         let b = i32x2::new(1, 1);
         let c = i32x2::new(10, 9);
-        let r: i32x2 = transmute(vaba_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x2::from(vaba_s32(a.into(), b.into(), c.into()));
         let e = i32x2::new(10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_u8() {
+    fn test_vaba_u8() {
         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = u8x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: u8x8 = transmute(vaba_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x8::from(vaba_u8(a.into(), b.into(), c.into()));
         let e = u8x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_u16() {
+    fn test_vaba_u16() {
         let a = u16x4::new(1, 2, 3, 4);
         let b = u16x4::new(1, 1, 1, 1);
         let c = u16x4::new(10, 9, 8, 7);
-        let r: u16x4 = transmute(vaba_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x4::from(vaba_u16(a.into(), b.into(), c.into()));
         let e = u16x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_u32() {
+    fn test_vaba_u32() {
         let a = u32x2::new(1, 2);
         let b = u32x2::new(1, 1);
         let c = u32x2::new(10, 9);
-        let r: u32x2 = transmute(vaba_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x2::from(vaba_u32(a.into(), b.into(), c.into()));
         let e = u32x2::new(10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_s8() {
+    fn test_vabaq_s8() {
         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2);
         let b = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let c = i8x16::new(10, 9, 8, 7, 6, 5, 4, 3, 12, 13, 14, 15, 16, 17, 18, 19);
-        let r: i8x16 = transmute(vabaq_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x16::from(vabaq_s8(a.into(), b.into(), c.into()));
         let e = i8x16::new(
             10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20,
         );
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_s16() {
+    fn test_vabaq_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = i16x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: i16x8 = transmute(vabaq_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x8::from(vabaq_s16(a.into(), b.into(), c.into()));
         let e = i16x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_s32() {
+    fn test_vabaq_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let b = i32x4::new(1, 1, 1, 1);
         let c = i32x4::new(10, 9, 8, 7);
-        let r: i32x4 = transmute(vabaq_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x4::from(vabaq_s32(a.into(), b.into(), c.into()));
         let e = i32x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_u8() {
+    fn test_vabaq_u8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2);
         let b = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let c = u8x16::new(10, 9, 8, 7, 6, 5, 4, 3, 12, 13, 14, 15, 16, 17, 18, 19);
-        let r: u8x16 = transmute(vabaq_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x16::from(vabaq_u8(a.into(), b.into(), c.into()));
         let e = u8x16::new(
             10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20,
         );
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_u16() {
+    fn test_vabaq_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = u16x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: u16x8 = transmute(vabaq_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x8::from(vabaq_u16(a.into(), b.into(), c.into()));
         let e = u16x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_u32() {
+    fn test_vabaq_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let b = u32x4::new(1, 1, 1, 1);
         let c = u32x4::new(10, 9, 8, 7);
-        let r: u32x4 = transmute(vabaq_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x4::from(vabaq_u32(a.into(), b.into(), c.into()));
         let e = u32x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16_s8() {
+    fn test_vrev16_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i8x8 = transmute(vrev16_s8(transmute(a)));
+        let e = i8x8::from(vrev16_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16q_s8() {
+    fn test_vrev16q_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = i8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
-        let e: i8x16 = transmute(vrev16q_s8(transmute(a)));
+        let e = i8x16::from(vrev16q_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16_u8() {
+    fn test_vrev16_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: u8x8 = transmute(vrev16_u8(transmute(a)));
+        let e = u8x8::from(vrev16_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16q_u8() {
+    fn test_vrev16q_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
-        let e: u8x16 = transmute(vrev16q_u8(transmute(a)));
+        let e = u8x16::from(vrev16q_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16_p8() {
-        let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = i8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i8x8 = transmute(vrev16_p8(transmute(a)));
+    fn test_vrev16_p8() {
+        let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = u8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
+        let e = u8x8::from(vrev16_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16q_p8() {
+    fn test_vrev16q_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
-        let e: u8x16 = transmute(vrev16q_p8(transmute(a)));
+        let e = u8x16::from(vrev16q_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_s8() {
+    fn test_vrev32_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i8x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: i8x8 = transmute(vrev32_s8(transmute(a)));
+        let e = i8x8::from(vrev32_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_s8() {
+    fn test_vrev32q_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = i8x16::new(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
-        let e: i8x16 = transmute(vrev32q_s8(transmute(a)));
+        let e = i8x16::from(vrev32q_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_u8() {
+    fn test_vrev32_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u8x8 = transmute(vrev32_u8(transmute(a)));
+        let e = u8x8::from(vrev32_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_u8() {
+    fn test_vrev32q_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
-        let e: u8x16 = transmute(vrev32q_u8(transmute(a)));
+        let e = u8x16::from(vrev32q_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_s16() {
+    fn test_vrev32_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let r = i16x4::new(1, 0, 3, 2);
-        let e: i16x4 = transmute(vrev32_s16(transmute(a)));
+        let e = i16x4::from(vrev32_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_s16() {
+    fn test_vrev32q_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i16x8 = transmute(vrev32q_s16(transmute(a)));
+        let e = i16x8::from(vrev32q_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_p16() {
-        let a = i16x4::new(0, 1, 2, 3);
-        let r = i16x4::new(1, 0, 3, 2);
-        let e: i16x4 = transmute(vrev32_p16(transmute(a)));
+    fn test_vrev32_p16() {
+        let a = u16x4::new(0, 1, 2, 3);
+        let r = u16x4::new(1, 0, 3, 2);
+        let e = u16x4::from(vrev32_p16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_p16() {
-        let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = i16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i16x8 = transmute(vrev32q_p16(transmute(a)));
+    fn test_vrev32q_p16() {
+        let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = u16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
+        let e = u16x8::from(vrev32q_p16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_u16() {
+    fn test_vrev32_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let r = u16x4::new(1, 0, 3, 2);
-        let e: u16x4 = transmute(vrev32_u16(transmute(a)));
+        let e = u16x4::from(vrev32_u16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_u16() {
+    fn test_vrev32q_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: u16x8 = transmute(vrev32q_u16(transmute(a)));
+        let e = u16x8::from(vrev32q_u16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_p8() {
+    fn test_vrev32_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u8x8 = transmute(vrev32_p8(transmute(a)));
+        let e = u8x8::from(vrev32_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_p8() {
+    fn test_vrev32q_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
-        let e: u8x16 = transmute(vrev32q_p8(transmute(a)));
+        let e = u8x16::from(vrev32q_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_s8() {
+    fn test_vrev64_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i8x8::new(7, 6, 5, 4, 3, 2, 1, 0);
-        let e: i8x8 = transmute(vrev64_s8(transmute(a)));
+        let e = i8x8::from(vrev64_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_s8() {
+    fn test_vrev64q_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = i8x16::new(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
-        let e: i8x16 = transmute(vrev64q_s8(transmute(a)));
+        let e = i8x16::from(vrev64q_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_s16() {
+    fn test_vrev64_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let r = i16x4::new(3, 2, 1, 0);
-        let e: i16x4 = transmute(vrev64_s16(transmute(a)));
+        let e = i16x4::from(vrev64_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_s16() {
+    fn test_vrev64q_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i16x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: i16x8 = transmute(vrev64q_s16(transmute(a)));
+        let e = i16x8::from(vrev64q_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_s32() {
+    fn test_vrev64_s32() {
         let a = i32x2::new(0, 1);
         let r = i32x2::new(1, 0);
-        let e: i32x2 = transmute(vrev64_s32(transmute(a)));
+        let e = i32x2::from(vrev64_s32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_s32() {
+    fn test_vrev64q_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let r = i32x4::new(1, 0, 3, 2);
-        let e: i32x4 = transmute(vrev64q_s32(transmute(a)));
+        let e = i32x4::from(vrev64q_s32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_u8() {
+    fn test_vrev64_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(7, 6, 5, 4, 3, 2, 1, 0);
-        let e: u8x8 = transmute(vrev64_u8(transmute(a)));
+        let e = u8x8::from(vrev64_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_u8() {
+    fn test_vrev64q_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
-        let e: u8x16 = transmute(vrev64q_u8(transmute(a)));
+        let e = u8x16::from(vrev64q_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_u16() {
+    fn test_vrev64_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let r = u16x4::new(3, 2, 1, 0);
-        let e: u16x4 = transmute(vrev64_u16(transmute(a)));
+        let e = u16x4::from(vrev64_u16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_u16() {
+    fn test_vrev64q_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u16x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u16x8 = transmute(vrev64q_u16(transmute(a)));
+        let e = u16x8::from(vrev64q_u16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_u32() {
+    fn test_vrev64_u32() {
         let a = u32x2::new(0, 1);
         let r = u32x2::new(1, 0);
-        let e: u32x2 = transmute(vrev64_u32(transmute(a)));
+        let e = u32x2::from(vrev64_u32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_u32() {
+    fn test_vrev64q_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let r = u32x4::new(1, 0, 3, 2);
-        let e: u32x4 = transmute(vrev64q_u32(transmute(a)));
+        let e = u32x4::from(vrev64q_u32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_f32() {
+    fn test_vrev64_f32() {
         let a = f32x2::new(1.0, 2.0);
         let r = f32x2::new(2.0, 1.0);
-        let e: f32x2 = transmute(vrev64_f32(transmute(a)));
+        let e = f32x2::from(vrev64_f32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_f32() {
+    fn test_vrev64q_f32() {
         let a = f32x4::new(1.0, 2.0, -2.0, -1.0);
         let r = f32x4::new(2.0, 1.0, -1.0, -2.0);
-        let e: f32x4 = transmute(vrev64q_f32(transmute(a)));
+        let e = f32x4::from(vrev64q_f32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_p8() {
+    fn test_vrev64_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(7, 6, 5, 4, 3, 2, 1, 0);
-        let e: u8x8 = transmute(vrev64_p8(transmute(a)));
+        let e = u8x8::from(vrev64_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_p8() {
+    fn test_vrev64q_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
-        let e: u8x16 = transmute(vrev64q_p8(transmute(a)));
+        let e = u8x16::from(vrev64q_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_p16() {
+    fn test_vrev64_p16() {
         let a = u16x4::new(0, 1, 2, 3);
         let r = u16x4::new(3, 2, 1, 0);
-        let e: u16x4 = transmute(vrev64_p16(transmute(a)));
+        let e = u16x4::from(vrev64_p16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_p16() {
+    fn test_vrev64q_p16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u16x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u16x8 = transmute(vrev64q_p16(transmute(a)));
+        let e = u16x8::from(vrev64q_p16(a.into()));
         assert_eq!(r, e);
     }
 
@@ -5527,13 +5770,13 @@ mod tests {
         ($test_id:ident => $fn_id:ident ([$($a:expr),*], [$($b:expr),*])) => {
             #[allow(unused_assignments)]
             #[simd_test(enable = "neon")]
-            unsafe fn $test_id() {
-                let a = [$($a),*];
-                let b = [$($b),*];
-                let e = [$($a),* $(, $b)*];
-                let c = $fn_id(transmute(a), transmute(b));
+            fn $test_id() {
+                let a = Simd::from_array([$($a),*]);
+                let b = Simd::from_array([$($b),*]);
+                let e = Simd::from_array([$($a),* $(, $b)*]);
+                let c = $fn_id(a.into(), b.into());
                 let mut d = e;
-                d = transmute(c);
+                d = c.into();
                 assert_eq!(d, e);
             }
         }
@@ -5546,11 +5789,19 @@ mod tests {
     test_vcombine!(test_vcombine_s16 => vcombine_s16([3_i16, -4, 5, -6], [13_i16, -14, 15, -16]));
     test_vcombine!(test_vcombine_u16 => vcombine_u16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
     test_vcombine!(test_vcombine_p16 => vcombine_p16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
+
     #[cfg(not(target_arch = "arm64ec"))]
     mod fp16 {
         use super::*;
-        test_vcombine!(test_vcombine_f16 => vcombine_f16([3_f16, 4., 5., 6.],
-        [13_f16, 14., 15., 16.]));
+        #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,fp16"))]
+        #[cfg_attr(not(target_arch = "arm"), simd_test(enable = "neon"))]
+        fn test_vcombine_f16() {
+            let a = f16x4::from_array([3_f16, 4., 5., 6.]);
+            let b = f16x4::from_array([13_f16, 14., 15., 16.]);
+            let e = f16x8::from_array([3_f16, 4., 5., 6., 13_f16, 14., 15., 16.]);
+            let c = f16x8::from(vcombine_f16(a.into(), b.into()));
+            assert_eq!(c, e);
+        }
     }
 
     test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14]));
diff --git a/crates/core_arch/src/arm_shared/neon/store_tests.rs b/crates/core_arch/src/arm_shared/neon/store_tests.rs
index 6b5d4a19ad..2b10b38f2d 100644
--- a/crates/core_arch/src/arm_shared/neon/store_tests.rs
+++ b/crates/core_arch/src/arm_shared/neon/store_tests.rs
@@ -14,11 +14,13 @@ use crate::core_arch::simd::*;
 use stdarch_test::simd_test;
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s8() {
+fn test_vst1_s8() {
     let mut vals = [0_i8; 9];
     let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1_s8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -32,11 +34,13 @@ unsafe fn test_vst1_s8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s8() {
+fn test_vst1q_s8() {
     let mut vals = [0_i8; 17];
     let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
 
-    vst1q_s8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -58,11 +62,13 @@ unsafe fn test_vst1q_s8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s16() {
+fn test_vst1_s16() {
     let mut vals = [0_i16; 5];
     let a = i16x4::new(1, 2, 3, 4);
 
-    vst1_s16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -72,11 +78,13 @@ unsafe fn test_vst1_s16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s16() {
+fn test_vst1q_s16() {
     let mut vals = [0_i16; 9];
     let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1q_s16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -90,11 +98,13 @@ unsafe fn test_vst1q_s16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s32() {
+fn test_vst1_s32() {
     let mut vals = [0_i32; 3];
     let a = i32x2::new(1, 2);
 
-    vst1_s32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -102,11 +112,13 @@ unsafe fn test_vst1_s32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s32() {
+fn test_vst1q_s32() {
     let mut vals = [0_i32; 5];
     let a = i32x4::new(1, 2, 3, 4);
 
-    vst1q_s32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -116,22 +128,26 @@ unsafe fn test_vst1q_s32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s64() {
+fn test_vst1_s64() {
     let mut vals = [0_i64; 2];
     let a = i64x1::new(1);
 
-    vst1_s64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s64() {
+fn test_vst1q_s64() {
     let mut vals = [0_i64; 3];
     let a = i64x2::new(1, 2);
 
-    vst1q_s64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -139,11 +155,13 @@ unsafe fn test_vst1q_s64() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u8() {
+fn test_vst1_u8() {
     let mut vals = [0_u8; 9];
     let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1_u8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -157,11 +175,13 @@ unsafe fn test_vst1_u8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u8() {
+fn test_vst1q_u8() {
     let mut vals = [0_u8; 17];
     let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
 
-    vst1q_u8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -183,11 +203,13 @@ unsafe fn test_vst1q_u8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u16() {
+fn test_vst1_u16() {
     let mut vals = [0_u16; 5];
     let a = u16x4::new(1, 2, 3, 4);
 
-    vst1_u16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -197,11 +219,13 @@ unsafe fn test_vst1_u16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u16() {
+fn test_vst1q_u16() {
     let mut vals = [0_u16; 9];
     let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1q_u16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -215,11 +239,13 @@ unsafe fn test_vst1q_u16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u32() {
+fn test_vst1_u32() {
     let mut vals = [0_u32; 3];
     let a = u32x2::new(1, 2);
 
-    vst1_u32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -227,11 +253,13 @@ unsafe fn test_vst1_u32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u32() {
+fn test_vst1q_u32() {
     let mut vals = [0_u32; 5];
     let a = u32x4::new(1, 2, 3, 4);
 
-    vst1q_u32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -241,22 +269,26 @@ unsafe fn test_vst1q_u32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u64() {
+fn test_vst1_u64() {
     let mut vals = [0_u64; 2];
     let a = u64x1::new(1);
 
-    vst1_u64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u64() {
+fn test_vst1q_u64() {
     let mut vals = [0_u64; 3];
     let a = u64x2::new(1, 2);
 
-    vst1q_u64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -264,11 +296,13 @@ unsafe fn test_vst1q_u64() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_p8() {
+fn test_vst1_p8() {
     let mut vals = [0_u8; 9];
     let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1_p8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_p8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -282,11 +316,13 @@ unsafe fn test_vst1_p8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_p8() {
+fn test_vst1q_p8() {
     let mut vals = [0_u8; 17];
     let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
 
-    vst1q_p8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_p8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -308,11 +344,13 @@ unsafe fn test_vst1q_p8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_p16() {
+fn test_vst1_p16() {
     let mut vals = [0_u16; 5];
     let a = u16x4::new(1, 2, 3, 4);
 
-    vst1_p16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_p16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -322,11 +360,13 @@ unsafe fn test_vst1_p16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_p16() {
+fn test_vst1q_p16() {
     let mut vals = [0_u16; 9];
     let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1q_p16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_p16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -340,22 +380,26 @@ unsafe fn test_vst1q_p16() {
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vst1_p64() {
+fn test_vst1_p64() {
     let mut vals = [0_u64; 2];
     let a = u64x1::new(1);
 
-    vst1_p64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_p64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vst1q_p64() {
+fn test_vst1q_p64() {
     let mut vals = [0_u64; 3];
     let a = u64x2::new(1, 2);
 
-    vst1q_p64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_p64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -363,11 +407,13 @@ unsafe fn test_vst1q_p64() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_f32() {
+fn test_vst1_f32() {
     let mut vals = [0_f32; 3];
     let a = f32x2::new(1., 2.);
 
-    vst1_f32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_f32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0.);
     assert_eq!(vals[1], 1.);
@@ -375,11 +421,13 @@ unsafe fn test_vst1_f32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_f32() {
+fn test_vst1q_f32() {
     let mut vals = [0_f32; 5];
     let a = f32x4::new(1., 2., 3., 4.);
 
-    vst1q_f32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_f32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0.);
     assert_eq!(vals[1], 1.);
diff --git a/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs b/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs
index 9403855f00..1e0333444b 100644
--- a/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs
+++ b/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs
@@ -21,19 +21,19 @@ macro_rules! test_vtbl {
     ) => {
         #[cfg(target_endian = "little")]
         #[simd_test(enable = "neon")]
-        unsafe fn $test_name() {
+        fn $test_name() {
             // create table as array, and transmute it to
             // arm's table type
-            let table: $table_t = mem::transmute([$($table_v),*]);
+            let table: $table_t = unsafe { mem::transmute([$($table_v),*]) };
 
             // For each control vector, perform a table lookup and
             // verify the result:
             $(
                 {
-                    let ctrl: $ctrl_t = mem::transmute([$($ctrl_v),*]);
-                    let result = $fn_id(table, mem::transmute(ctrl));
-                    let result: $ctrl_t = mem::transmute(result);
-                    let expected: $ctrl_t = mem::transmute([$($exp_v),*]);
+                    let ctrl: $ctrl_t = unsafe { mem::transmute([$($ctrl_v),*]) };
+                    let result = $fn_id(table, unsafe { mem::transmute(ctrl) });
+                    let result: $ctrl_t = unsafe { mem::transmute(result) };
+                    let expected: $ctrl_t = unsafe { mem::transmute([$($exp_v),*]) };
                     assert_eq!(result, expected);
                 }
             )*
@@ -171,20 +171,19 @@ macro_rules! test_vtbx {
     ) => {
         #[cfg(target_endian = "little")]
         #[simd_test(enable = "neon")]
-        unsafe fn $test_name() {
+        fn $test_name() {
             // create table as array, and transmute it to
             // arm's table type
-            let table: $table_t = mem::transmute([$($table_v),*]);
-            let ext: $ext_t = mem::transmute([$($ext_v),*]);
-
+            let table: $table_t = unsafe { mem::transmute([$($table_v),*]) };
+            let ext: $ext_t = unsafe { mem::transmute([$($ext_v),*]) };
             // For each control vector, perform a table lookup and
             // verify the result:
             $(
                 {
-                    let ctrl: $ctrl_t = mem::transmute([$($ctrl_v),*]);
-                    let result = $fn_id(ext, table, mem::transmute(ctrl));
-                    let result: $ctrl_t = mem::transmute(result);
-                    let expected: $ctrl_t = mem::transmute([$($exp_v),*]);
+                    let ctrl: $ctrl_t = unsafe { mem::transmute([$($ctrl_v),*]) };
+                    let result = $fn_id(ext, table, unsafe { mem::transmute(ctrl) });
+                    let result: $ctrl_t = unsafe { mem::transmute(result) };
+                    let expected: $ctrl_t = unsafe { mem::transmute([$($exp_v),*]) };
                     assert_eq!(result, expected);
                 }
             )*
diff --git a/crates/core_arch/src/arm_shared/test_support.rs b/crates/core_arch/src/arm_shared/test_support.rs
index e2828f8556..8117b81cd9 100644
--- a/crates/core_arch/src/arm_shared/test_support.rs
+++ b/crates/core_arch/src/arm_shared/test_support.rs
@@ -111,13 +111,13 @@ macro_rules! V_f32 {
 
 macro_rules! to64 {
     ($t : ident) => {
-        |v: $t| -> u64 { transmute(v) }
+        |v: $t| -> u64 { unsafe { transmute(v) } }
     };
 }
 
 macro_rules! to128 {
     ($t : ident) => {
-        |v: $t| -> u128 { transmute(v) }
+        |v: $t| -> u128 { unsafe { transmute(v) } }
     };
 }
 
@@ -158,9 +158,7 @@ pub(crate) fn test<T, U, V, W, X>(
 macro_rules! gen_test_fn {
     ($n: ident, $t: ident, $u: ident, $v: ident, $w: ident, $x: ident, $vals: expr, $fill1: expr, $fill2: expr, $cast: expr) => {
         pub(crate) fn $n(test_fun: fn($v, $v) -> $w, verify_fun: fn($t, $t) -> $u) {
-            unsafe {
-                test::<$t, $u, $v, $w, $x>($vals, $fill1, $fill2, $cast, test_fun, verify_fun)
-            };
+            test::<$t, $u, $v, $w, $x>($vals, $fill1, $fill2, $cast, test_fun, verify_fun);
         }
     };
 }
diff --git a/crates/simd-test-macro/src/lib.rs b/crates/simd-test-macro/src/lib.rs
index b8bb874480..92bb40946e 100644
--- a/crates/simd-test-macro/src/lib.rs
+++ b/crates/simd-test-macro/src/lib.rs
@@ -17,6 +17,15 @@ pub fn simd_test(
     item: proc_macro::TokenStream,
 ) -> proc_macro::TokenStream {
     let tokens = TokenStream::from(attr).into_iter().collect::<Vec<_>>();
+
+    let target = env::var("TARGET").expect(
+        "TARGET environment variable should be set for rustc (e.g. TARGET=x86_64-apple-darwin cargo test)"
+    );
+    let target_arch = target
+        .split('-')
+        .next()
+        .unwrap_or_else(|| panic!("target triple contained no \"-\": {target}"));
+
     let (target_features, target_feature_attr) = match &tokens[..] {
         [] => (Vec::new(), TokenStream::new()),
         [
@@ -24,13 +33,20 @@ pub fn simd_test(
             TokenTree::Punct(equals),
             TokenTree::Literal(literal),
         ] if enable == "enable" && equals.as_char() == '=' => {
-            let enable_feature = literal.to_string();
-            let enable_feature = enable_feature.trim_start_matches('"').trim_end_matches('"');
+            let mut enable_feature = literal
+                .to_string()
+                .trim_start_matches('"')
+                .trim_end_matches('"')
+                .to_string();
             let target_features: Vec<_> = enable_feature
                 .replace('+', "")
                 .split(',')
                 .map(String::from)
                 .collect();
+            // Allows using `#[simd_test(enable = "neon")]` on aarch64/armv7 shared tests.
+            if target_arch == "armv7" && target_features.iter().any(|feat| feat == "neon") {
+                enable_feature.push_str(",v7");
+            }
 
             (
                 target_features,
@@ -46,14 +62,7 @@ pub fn simd_test(
     let item_attrs = std::mem::take(&mut item.attrs);
     let name = &item.sig.ident;
 
-    let target = env::var("TARGET").expect(
-        "TARGET environment variable should be set for rustc (e.g. TARGET=x86_64-apple-darwin cargo test)"
-    );
-    let macro_test = match target
-        .split('-')
-        .next()
-        .unwrap_or_else(|| panic!("target triple contained no \"-\": {target}"))
-    {
+    let macro_test = match target_arch {
         "i686" | "x86_64" | "i586" => "is_x86_feature_detected",
         "arm" | "armv7" | "thumbv7neon" => "is_arm_feature_detected",
         "aarch64" | "arm64ec" | "aarch64_be" => "is_aarch64_feature_detected",
@@ -85,10 +94,20 @@ pub fn simd_test(
 
     let mut detect_missing_features = TokenStream::new();
     for feature in target_features {
-        let q = quote_spanned! {
-            proc_macro2::Span::call_site() =>
-            if !::std::arch::#macro_test!(#feature) {
-                missing_features.push(#feature);
+        let q = if target_arch == "armv7" && feature == "fp16" {
+            // "fp16" cannot be checked at runtime
+            quote_spanned! {
+                proc_macro2::Span::call_site() =>
+                if !cfg!(target_feature = #feature) {
+                    missing_features.push(#feature);
+                }
+            }
+        } else {
+            quote_spanned! {
+                proc_macro2::Span::call_site() =>
+                if !::std::arch::#macro_test!(#feature) {
+                    missing_features.push(#feature);
+                }
             }
         };
         q.to_tokens(&mut detect_missing_features);

From bf6d4ea33f66bbc400fcaa0cca882bceecde9f98 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Tue, 6 Jan 2026 20:01:25 +0100
Subject: [PATCH 093/326] Avoid `unsafe fn` in remaining x86 tests

---
 crates/core_arch/src/x86/avx.rs          | 231 +++---
 crates/core_arch/src/x86/avx2.rs         | 374 +++++----
 crates/core_arch/src/x86/avx512bf16.rs   | 279 +++----
 crates/core_arch/src/x86/avx512bw.rs     | 314 ++++----
 crates/core_arch/src/x86/avx512dq.rs     |  52 +-
 crates/core_arch/src/x86/avx512f.rs      | 966 ++++++++++++++---------
 crates/core_arch/src/x86/avx512fp16.rs   |  99 ++-
 crates/core_arch/src/x86/avx512vbmi2.rs  | 124 +--
 crates/core_arch/src/x86/avxneconvert.rs |  56 +-
 crates/core_arch/src/x86/f16c.rs         |   2 +-
 crates/core_arch/src/x86/fxsr.rs         |  10 +-
 crates/core_arch/src/x86/gfni.rs         | 210 ++---
 crates/core_arch/src/x86/kl.rs           |  88 ++-
 crates/core_arch/src/x86/rtm.rs          |  34 +-
 crates/core_arch/src/x86/sse.rs          |  60 +-
 crates/core_arch/src/x86/sse2.rs         | 178 +++--
 crates/core_arch/src/x86/sse3.rs         |   8 +-
 crates/core_arch/src/x86/sse41.rs        |  12 +-
 crates/core_arch/src/x86/sse42.rs        |   3 +-
 crates/core_arch/src/x86/sse4a.rs        |  12 +-
 crates/core_arch/src/x86/xsave.rs        |  36 +-
 crates/core_arch/src/x86_64/amx.rs       | 858 ++++++++++----------
 crates/core_arch/src/x86_64/avx512f.rs   | 659 ++++++++++------
 crates/core_arch/src/x86_64/fxsr.rs      |  10 +-
 crates/core_arch/src/x86_64/sse2.rs      |   6 +-
 crates/core_arch/src/x86_64/xsave.rs     |  30 +-
 26 files changed, 2693 insertions(+), 2018 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index e0e01ae6d0..c406d537bc 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -3369,6 +3369,7 @@ unsafe extern "C" {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
+    use crate::core_arch::simd::*;
     use crate::hint::black_box;
     use crate::ptr;
     use stdarch_test::simd_test;
@@ -3464,7 +3465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_max_pd() {
+    fn test_mm256_max_pd() {
         let a = _mm256_setr_pd(1., 4., 5., 8.);
         let b = _mm256_setr_pd(2., 3., 6., 7.);
         let r = _mm256_max_pd(a, b);
@@ -3474,23 +3475,22 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0));
         let x = _mm256_max_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0));
-        let wu: [u64; 4] = transmute(w);
-        let xu: [u64; 4] = transmute(x);
-        assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]);
-        assert_eq!(xu, [0u64; 4]);
+        let wu = _mm256_castpd_si256(w).as_u64x4();
+        let xu = _mm256_castpd_si256(x).as_u64x4();
+        assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64));
+        assert_eq!(xu, u64x4::splat(0u64));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_max_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0));
         let z = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN));
-        let yf: [f64; 4] = transmute(y);
-        let zf: [f64; 4] = transmute(z);
-        assert_eq!(yf, [0.0; 4]);
+        assert_eq_m256d(y, _mm256_set1_pd(0.0));
+        let zf = *z.as_f64x4().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_max_ps() {
+    fn test_mm256_max_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_max_ps(a, b);
@@ -3500,23 +3500,22 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0));
         let x = _mm256_max_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0));
-        let wu: [u32; 8] = transmute(w);
-        let xu: [u32; 8] = transmute(x);
-        assert_eq!(wu, [0x8000_0000u32; 8]);
-        assert_eq!(xu, [0u32; 8]);
+        let wu = _mm256_castps_si256(w).as_u32x8();
+        let xu = _mm256_castps_si256(x).as_u32x8();
+        assert_eq!(wu, u32x8::splat(0x8000_0000u32));
+        assert_eq!(xu, u32x8::splat(0u32));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_max_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0));
         let z = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN));
-        let yf: [f32; 8] = transmute(y);
-        let zf: [f32; 8] = transmute(z);
-        assert_eq!(yf, [0.0; 8]);
+        assert_eq_m256(y, _mm256_set1_ps(0.0));
+        let zf = *z.as_f32x8().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_min_pd() {
+    fn test_mm256_min_pd() {
         let a = _mm256_setr_pd(1., 4., 5., 8.);
         let b = _mm256_setr_pd(2., 3., 6., 7.);
         let r = _mm256_min_pd(a, b);
@@ -3526,23 +3525,22 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0));
         let x = _mm256_min_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0));
-        let wu: [u64; 4] = transmute(w);
-        let xu: [u64; 4] = transmute(x);
-        assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]);
-        assert_eq!(xu, [0u64; 4]);
+        let wu = _mm256_castpd_si256(w).as_u64x4();
+        let xu = _mm256_castpd_si256(x).as_u64x4();
+        assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64));
+        assert_eq!(xu, u64x4::splat(0u64));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_min_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0));
         let z = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN));
-        let yf: [f64; 4] = transmute(y);
-        let zf: [f64; 4] = transmute(z);
-        assert_eq!(yf, [0.0; 4]);
+        assert_eq_m256d(y, _mm256_set1_pd(0.0));
+        let zf = *z.as_f64x4().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_min_ps() {
+    fn test_mm256_min_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_min_ps(a, b);
@@ -3552,18 +3550,17 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0));
         let x = _mm256_min_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0));
-        let wu: [u32; 8] = transmute(w);
-        let xu: [u32; 8] = transmute(x);
-        assert_eq!(wu, [0x8000_0000u32; 8]);
-        assert_eq!(xu, [0u32; 8]);
+        let wu = _mm256_castps_si256(w).as_u32x8();
+        let xu = _mm256_castps_si256(x).as_u32x8();
+        assert_eq!(wu, u32x8::splat(0x8000_0000u32));
+        assert_eq!(xu, u32x8::splat(0u32));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_min_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0));
         let z = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN));
-        let yf: [f32; 8] = transmute(y);
-        let zf: [f32; 8] = transmute(z);
-        assert_eq!(yf, [0.0; 8]);
+        assert_eq_m256(y, _mm256_set1_ps(0.0));
+        let zf = *z.as_f32x8().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
@@ -4247,183 +4244,203 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_load_pd() {
+    const fn test_mm256_load_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let p = ptr::addr_of!(a) as *const f64;
-        let r = _mm256_load_pd(p);
+        let r = unsafe { _mm256_load_pd(p) };
         let e = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_store_pd() {
+    const fn test_mm256_store_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut r = _mm256_undefined_pd();
-        _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        unsafe {
+            _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        }
         assert_eq_m256d(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_load_ps() {
+    const fn test_mm256_load_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let p = ptr::addr_of!(a) as *const f32;
-        let r = _mm256_load_ps(p);
+        let r = unsafe { _mm256_load_ps(p) };
         let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_store_ps() {
+    const fn test_mm256_store_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let mut r = _mm256_undefined_ps();
-        _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        unsafe {
+            _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        }
         assert_eq_m256(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu_pd() {
+    const fn test_mm256_loadu_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
-        let r = _mm256_loadu_pd(black_box(p));
+        let r = unsafe { _mm256_loadu_pd(black_box(p)) };
         let e = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu_pd() {
+    const fn test_mm256_storeu_pd() {
         let a = _mm256_set1_pd(9.);
         let mut r = _mm256_undefined_pd();
-        _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        unsafe {
+            _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        }
         assert_eq_m256d(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu_ps() {
+    const fn test_mm256_loadu_ps() {
         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
         let p = a.as_ptr();
-        let r = _mm256_loadu_ps(black_box(p));
+        let r = unsafe { _mm256_loadu_ps(black_box(p)) };
         let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu_ps() {
+    const fn test_mm256_storeu_ps() {
         let a = _mm256_set1_ps(9.);
         let mut r = _mm256_undefined_ps();
-        _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        unsafe {
+            _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        }
         assert_eq_m256(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_load_si256() {
+    const fn test_mm256_load_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let p = ptr::addr_of!(a);
-        let r = _mm256_load_si256(p);
+        let r = unsafe { _mm256_load_si256(p) };
         let e = _mm256_setr_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_store_si256() {
+    const fn test_mm256_store_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = _mm256_undefined_si256();
-        _mm256_store_si256(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm256_store_si256(ptr::addr_of_mut!(r), a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu_si256() {
+    const fn test_mm256_loadu_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let p = ptr::addr_of!(a);
-        let r = _mm256_loadu_si256(black_box(p));
+        let r = unsafe { _mm256_loadu_si256(black_box(p)) };
         let e = _mm256_setr_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu_si256() {
+    const fn test_mm256_storeu_si256() {
         let a = _mm256_set1_epi8(9);
         let mut r = _mm256_undefined_si256();
-        _mm256_storeu_si256(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm256_storeu_si256(ptr::addr_of_mut!(r), a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskload_pd() {
+    const fn test_mm256_maskload_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
-        let r = _mm256_maskload_pd(black_box(p), mask);
+        let r = unsafe { _mm256_maskload_pd(black_box(p), mask) };
         let e = _mm256_setr_pd(0., 2., 0., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskstore_pd() {
+    const fn test_mm256_maskstore_pd() {
         let mut r = _mm256_set1_pd(0.);
         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
         let a = _mm256_setr_pd(1., 2., 3., 4.);
-        _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        unsafe {
+            _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        }
         let e = _mm256_setr_pd(0., 2., 0., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskload_pd() {
+    const fn test_mm_maskload_pd() {
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let mask = _mm_setr_epi64x(0, !0);
-        let r = _mm_maskload_pd(black_box(p), mask);
+        let r = unsafe { _mm_maskload_pd(black_box(p), mask) };
         let e = _mm_setr_pd(0., 2.);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskstore_pd() {
+    const fn test_mm_maskstore_pd() {
         let mut r = _mm_set1_pd(0.);
         let mask = _mm_setr_epi64x(0, !0);
         let a = _mm_setr_pd(1., 2.);
-        _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        unsafe {
+            _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        }
         let e = _mm_setr_pd(0., 2.);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskload_ps() {
+    const fn test_mm256_maskload_ps() {
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
-        let r = _mm256_maskload_ps(black_box(p), mask);
+        let r = unsafe { _mm256_maskload_ps(black_box(p), mask) };
         let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskstore_ps() {
+    const fn test_mm256_maskstore_ps() {
         let mut r = _mm256_set1_ps(0.);
         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
-        _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        unsafe {
+            _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        }
         let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskload_ps() {
+    const fn test_mm_maskload_ps() {
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let mask = _mm_setr_epi32(0, !0, 0, !0);
-        let r = _mm_maskload_ps(black_box(p), mask);
+        let r = unsafe { _mm_maskload_ps(black_box(p), mask) };
         let e = _mm_setr_ps(0., 2., 0., 4.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskstore_ps() {
+    const fn test_mm_maskstore_ps() {
         let mut r = _mm_set1_ps(0.);
         let mask = _mm_setr_epi32(0, !0, 0, !0);
         let a = _mm_setr_ps(1., 2., 3., 4.);
-        _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        unsafe {
+            _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        }
         let e = _mm_setr_ps(0., 2., 0., 4.);
         assert_eq_m128(r, e);
     }
@@ -4453,7 +4470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_lddqu_si256() {
+    fn test_mm256_lddqu_si256() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4462,7 +4479,7 @@ mod tests {
             25, 26, 27, 28, 29, 30, 31, 32,
         );
         let p = ptr::addr_of!(a);
-        let r = _mm256_lddqu_si256(black_box(p));
+        let r = unsafe { _mm256_lddqu_si256(black_box(p)) };
         #[rustfmt::skip]
         let e = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4475,17 +4492,19 @@ mod tests {
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
-    unsafe fn test_mm256_stream_si256() {
+    fn test_mm256_stream_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = _mm256_undefined_si256();
-        _mm256_stream_si256(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm256_stream_si256(ptr::addr_of_mut!(r), a);
+        }
         _mm_sfence();
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
-    unsafe fn test_mm256_stream_pd() {
+    fn test_mm256_stream_pd() {
         #[repr(align(32))]
         struct Memory {
             pub data: [f64; 4],
@@ -4493,7 +4512,9 @@ mod tests {
         let a = _mm256_set1_pd(7.0);
         let mut mem = Memory { data: [-1.0; 4] };
 
-        _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..4 {
             assert_eq!(mem.data[i], get_m256d(a, i));
@@ -4502,7 +4523,7 @@ mod tests {
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
-    unsafe fn test_mm256_stream_ps() {
+    fn test_mm256_stream_ps() {
         #[repr(align(32))]
         struct Memory {
             pub data: [f32; 8],
@@ -4510,7 +4531,9 @@ mod tests {
         let a = _mm256_set1_ps(7.0);
         let mut mem = Memory { data: [-1.0; 8] };
 
-        _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..8 {
             assert_eq!(mem.data[i], get_m256(a, i));
@@ -5147,29 +5170,29 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu2_m128() {
+    const fn test_mm256_loadu2_m128() {
         let hi = &[5., 6., 7., 8.];
         let hiaddr = hi.as_ptr();
         let lo = &[1., 2., 3., 4.];
         let loaddr = lo.as_ptr();
-        let r = _mm256_loadu2_m128(hiaddr, loaddr);
+        let r = unsafe { _mm256_loadu2_m128(hiaddr, loaddr) };
         let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu2_m128d() {
+    const fn test_mm256_loadu2_m128d() {
         let hi = &[3., 4.];
         let hiaddr = hi.as_ptr();
         let lo = &[1., 2.];
         let loaddr = lo.as_ptr();
-        let r = _mm256_loadu2_m128d(hiaddr, loaddr);
+        let r = unsafe { _mm256_loadu2_m128d(hiaddr, loaddr) };
         let e = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu2_m128i() {
+    const fn test_mm256_loadu2_m128i() {
         #[rustfmt::skip]
         let hi = _mm_setr_epi8(
             17, 18, 19, 20, 21, 22, 23, 24,
@@ -5180,7 +5203,9 @@ mod tests {
             1, 2, 3, 4, 5, 6, 7, 8,
             9, 10, 11, 12, 13, 14, 15, 16,
         );
-        let r = _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _);
+        let r = unsafe {
+            _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _)
+        };
         #[rustfmt::skip]
         let e = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5192,35 +5217,39 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu2_m128() {
+    const fn test_mm256_storeu2_m128() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let mut hi = _mm_undefined_ps();
         let mut lo = _mm_undefined_ps();
-        _mm256_storeu2_m128(
-            ptr::addr_of_mut!(hi) as *mut f32,
-            ptr::addr_of_mut!(lo) as *mut f32,
-            a,
-        );
+        unsafe {
+            _mm256_storeu2_m128(
+                ptr::addr_of_mut!(hi) as *mut f32,
+                ptr::addr_of_mut!(lo) as *mut f32,
+                a,
+            );
+        }
         assert_eq_m128(hi, _mm_setr_ps(5., 6., 7., 8.));
         assert_eq_m128(lo, _mm_setr_ps(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu2_m128d() {
+    const fn test_mm256_storeu2_m128d() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut hi = _mm_undefined_pd();
         let mut lo = _mm_undefined_pd();
-        _mm256_storeu2_m128d(
-            ptr::addr_of_mut!(hi) as *mut f64,
-            ptr::addr_of_mut!(lo) as *mut f64,
-            a,
-        );
+        unsafe {
+            _mm256_storeu2_m128d(
+                ptr::addr_of_mut!(hi) as *mut f64,
+                ptr::addr_of_mut!(lo) as *mut f64,
+                a,
+            );
+        }
         assert_eq_m128d(hi, _mm_setr_pd(3., 4.));
         assert_eq_m128d(lo, _mm_setr_pd(1., 2.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu2_m128i() {
+    const fn test_mm256_storeu2_m128i() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5230,7 +5259,9 @@ mod tests {
         );
         let mut hi = _mm_undefined_si128();
         let mut lo = _mm_undefined_si128();
-        _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a);
+        unsafe {
+            _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a);
+        }
         #[rustfmt::skip]
         let e_hi = _mm_setr_epi8(
             17, 18, 19, 20, 21, 22, 23, 24,
diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 6f56e937c6..6a39a0aaf8 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -4672,81 +4672,89 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskload_epi32() {
+    const fn test_mm_maskload_epi32() {
         let nums = [1, 2, 3, 4];
         let a = &nums as *const i32;
         let mask = _mm_setr_epi32(-1, 0, 0, -1);
-        let r = _mm_maskload_epi32(a, mask);
+        let r = unsafe { _mm_maskload_epi32(a, mask) };
         let e = _mm_setr_epi32(1, 0, 0, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskload_epi32() {
+    const fn test_mm256_maskload_epi32() {
         let nums = [1, 2, 3, 4, 5, 6, 7, 8];
         let a = &nums as *const i32;
         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
-        let r = _mm256_maskload_epi32(a, mask);
+        let r = unsafe { _mm256_maskload_epi32(a, mask) };
         let e = _mm256_setr_epi32(1, 0, 0, 4, 0, 6, 7, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskload_epi64() {
+    const fn test_mm_maskload_epi64() {
         let nums = [1_i64, 2_i64];
         let a = &nums as *const i64;
         let mask = _mm_setr_epi64x(0, -1);
-        let r = _mm_maskload_epi64(a, mask);
+        let r = unsafe { _mm_maskload_epi64(a, mask) };
         let e = _mm_setr_epi64x(0, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskload_epi64() {
+    const fn test_mm256_maskload_epi64() {
         let nums = [1_i64, 2_i64, 3_i64, 4_i64];
         let a = &nums as *const i64;
         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
-        let r = _mm256_maskload_epi64(a, mask);
+        let r = unsafe { _mm256_maskload_epi64(a, mask) };
         let e = _mm256_setr_epi64x(0, 2, 3, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskstore_epi32() {
+    const fn test_mm_maskstore_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut arr = [-1, -1, -1, -1];
         let mask = _mm_setr_epi32(-1, 0, 0, -1);
-        _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        }
         let e = [1, -1, -1, 4];
         assert_eq!(arr, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskstore_epi32() {
+    const fn test_mm256_maskstore_epi32() {
         let a = _mm256_setr_epi32(1, 0x6d726f, 3, 42, 0x777161, 6, 7, 8);
         let mut arr = [-1, -1, -1, 0x776173, -1, 0x68657265, -1, -1];
         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
-        _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        }
         let e = [1, -1, -1, 42, -1, 6, 7, -1];
         assert_eq!(arr, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskstore_epi64() {
+    const fn test_mm_maskstore_epi64() {
         let a = _mm_setr_epi64x(1_i64, 2_i64);
         let mut arr = [-1_i64, -1_i64];
         let mask = _mm_setr_epi64x(0, -1);
-        _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        }
         let e = [-1, 2];
         assert_eq!(arr, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskstore_epi64() {
+    const fn test_mm256_maskstore_epi64() {
         let a = _mm256_setr_epi64x(1_i64, 2_i64, 3_i64, 4_i64);
         let mut arr = [-1_i64, -1_i64, -1_i64, -1_i64];
         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
-        _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        }
         let e = [-1, 2, 3, -1];
         assert_eq!(arr, e);
     }
@@ -5301,9 +5309,9 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_stream_load_si256() {
+    fn test_mm256_stream_load_si256() {
         let a = _mm256_set_epi64x(5, 6, 7, 8);
-        let r = _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _) };
         assert_eq_m256i(a, r);
     }
 
@@ -5506,88 +5514,98 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_epi32() {
+    fn test_mm_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_epi32() {
+    fn test_mm_mask_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_mask_i32gather_epi32::<4>(
-            _mm_set1_epi32(256),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm_setr_epi32(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_epi32::<4>(
+                _mm_set1_epi32(256),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm_setr_epi32(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_epi32() {
+    fn test_mm256_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r =
-            _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
+        let r = unsafe {
+            _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4))
+        };
         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_epi32() {
+    fn test_mm256_mask_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm256_mask_i32gather_epi32::<4>(
-            _mm256_set1_epi32(256),
-            arr.as_ptr(),
-            _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
-            _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_epi32::<4>(
+                _mm256_set1_epi32(256),
+                arr.as_ptr(),
+                _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
+                _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0),
+            )
+        };
         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 64, 256, 256, 256, 256, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_ps() {
+    fn test_mm_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_ps() {
+    fn test_mm_mask_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_mask_i32gather_ps::<4>(
-            _mm_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_ps::<4>(
+                _mm_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_ps() {
+    fn test_mm256_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r =
-            _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
+        let r = unsafe {
+            _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4))
+        };
         assert_eq_m256(r, _mm256_setr_ps(0.0, 16.0, 32.0, 48.0, 1.0, 2.0, 3.0, 4.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_ps() {
+    fn test_mm256_mask_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm256_mask_i32gather_ps::<4>(
-            _mm256_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
-            _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_ps::<4>(
+                _mm256_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
+                _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0),
+            )
+        };
         assert_eq_m256(
             r,
             _mm256_setr_ps(0.0, 16.0, 64.0, 256.0, 256.0, 256.0, 256.0, 256.0),
@@ -5595,254 +5613,282 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_epi64() {
+    fn test_mm_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0));
+        let r = unsafe { _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) };
         assert_eq_m128i(r, _mm_setr_epi64x(0, 16));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_epi64() {
+    fn test_mm_mask_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_mask_i32gather_epi64::<8>(
-            _mm_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm_setr_epi32(16, 16, 16, 16),
-            _mm_setr_epi64x(-1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_epi64::<8>(
+                _mm_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm_setr_epi32(16, 16, 16, 16),
+                _mm_setr_epi64x(-1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi64x(16, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_epi64() {
+    fn test_mm256_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_epi64() {
+    fn test_mm256_mask_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_mask_i32gather_epi64::<8>(
-            _mm256_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm256_setr_epi64x(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_epi64::<8>(
+                _mm256_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm256_setr_epi64x(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_pd() {
+    fn test_mm_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0));
+        let r = unsafe { _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) };
         assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_pd() {
+    fn test_mm_mask_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_mask_i32gather_pd::<8>(
-            _mm_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi32(16, 16, 16, 16),
-            _mm_setr_pd(-1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_pd::<8>(
+                _mm_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi32(16, 16, 16, 16),
+                _mm_setr_pd(-1.0, 0.0),
+            )
+        };
         assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_pd() {
+    fn test_mm256_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_pd() {
+    fn test_mm256_mask_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_mask_i32gather_pd::<8>(
-            _mm256_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_pd::<8>(
+                _mm256_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_epi32() {
+    fn test_mm_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 0, 0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_epi32() {
+    fn test_mm_mask_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_mask_i64gather_epi32::<4>(
-            _mm_set1_epi32(256),
-            arr.as_ptr(),
-            _mm_setr_epi64x(0, 16),
-            _mm_setr_epi32(-1, 0, -1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_epi32::<4>(
+                _mm_set1_epi32(256),
+                arr.as_ptr(),
+                _mm_setr_epi64x(0, 16),
+                _mm_setr_epi32(-1, 0, -1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi32(0, 256, 0, 0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_epi32() {
+    fn test_mm256_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_epi32() {
+    fn test_mm256_mask_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm256_mask_i64gather_epi32::<4>(
-            _mm_set1_epi32(256),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm_setr_epi32(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_epi32::<4>(
+                _mm_set1_epi32(256),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm_setr_epi32(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_ps() {
+    fn test_mm_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_ps() {
+    fn test_mm_mask_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_mask_i64gather_ps::<4>(
-            _mm_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi64x(0, 16),
-            _mm_setr_ps(-1.0, 0.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_ps::<4>(
+                _mm_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi64x(0, 16),
+                _mm_setr_ps(-1.0, 0.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m128(r, _mm_setr_ps(0.0, 256.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_ps() {
+    fn test_mm256_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_ps() {
+    fn test_mm256_mask_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm256_mask_i64gather_ps::<4>(
-            _mm_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_ps::<4>(
+                _mm_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_epi64() {
+    fn test_mm_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128i(r, _mm_setr_epi64x(0, 16));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_epi64() {
+    fn test_mm_mask_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_mask_i64gather_epi64::<8>(
-            _mm_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm_setr_epi64x(16, 16),
-            _mm_setr_epi64x(-1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_epi64::<8>(
+                _mm_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm_setr_epi64x(16, 16),
+                _mm_setr_epi64x(-1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi64x(16, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_epi64() {
+    fn test_mm256_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_epi64() {
+    fn test_mm256_mask_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_mask_i64gather_epi64::<8>(
-            _mm256_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm256_setr_epi64x(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_epi64::<8>(
+                _mm256_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm256_setr_epi64x(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_pd() {
+    fn test_mm_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_pd() {
+    fn test_mm_mask_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_mask_i64gather_pd::<8>(
-            _mm_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi64x(16, 16),
-            _mm_setr_pd(-1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_pd::<8>(
+                _mm_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi64x(16, 16),
+                _mm_setr_pd(-1.0, 0.0),
+            )
+        };
         assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_pd() {
+    fn test_mm256_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_pd() {
+    fn test_mm256_mask_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_mask_i64gather_pd::<8>(
-            _mm256_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_pd::<8>(
+                _mm256_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
     }
 
diff --git a/crates/core_arch/src/x86/avx512bf16.rs b/crates/core_arch/src/x86/avx512bf16.rs
index 83dbc540a0..66eef063ee 100644
--- a/crates/core_arch/src/x86/avx512bf16.rs
+++ b/crates/core_arch/src/x86/avx512bf16.rs
@@ -593,7 +593,7 @@ pub fn _mm_cvtness_sbh(a: f32) -> bf16 {
 
 #[cfg(test)]
 mod tests {
-    use crate::core_arch::simd::u16x4;
+    use crate::core_arch::simd::{f32x4, f32x8, f32x16, u16x4, u16x8, u16x16, u16x32};
     use crate::{
         core_arch::x86::*,
         mem::{transmute, transmute_copy},
@@ -601,13 +601,13 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_cvtne2ps_pbh() {
+    fn test_mm_cvtne2ps_pbh() {
         let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
-        let a: __m128 = transmute(a_array);
-        let b: __m128 = transmute(b_array);
+        let a = f32x4::from_array(a_array).as_m128();
+        let b = f32x4::from_array(b_array).as_m128();
         let c: __m128bh = _mm_cvtne2ps_pbh(a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b1_10000110_0110010,
@@ -623,7 +623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_cvtne2ps_pbh() {
+    fn test_mm_mask_cvtne2ps_pbh() {
         let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
         #[rustfmt::skip]
@@ -637,12 +637,12 @@ mod tests {
             0b0_10000000_1110000,
             0b0_10000100_1001001,
         ];
-        let src: __m128bh = transmute(src_array);
-        let a: __m128 = transmute(a_array);
-        let b: __m128 = transmute(b_array);
+        let src = u16x8::from_array(src_array).as_m128bh();
+        let a = f32x4::from_array(a_array).as_m128();
+        let b = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0b1111_1111;
         let c: __m128bh = _mm_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b1_10000110_0110010,
@@ -657,20 +657,20 @@ mod tests {
         assert_eq!(result, expected_result);
         let k = 0b0000_0000;
         let c = _mm_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtne2ps_pbh() {
+    fn test_mm_maskz_cvtne2ps_pbh() {
         let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
-        let a: __m128 = transmute(a_array);
-        let b: __m128 = transmute(b_array);
+        let a = f32x4::from_array(a_array).as_m128();
+        let b = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0b1111_1111;
         let c: __m128bh = _mm_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b1_10000110_0110010,
@@ -685,7 +685,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k = 0b0011_1100;
         let c = _mm_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0,
@@ -701,7 +701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_cvtne2ps_pbh() {
+    fn test_mm256_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -723,10 +723,10 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
-        let b: __m256 = transmute(b_array);
+        let a = f32x8::from_array(a_array).as_m256();
+        let b = f32x8::from_array(b_array).as_m256();
         let c: __m256bh = _mm256_cvtne2ps_pbh(a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b1_10000110_0110010,
@@ -750,7 +750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtne2ps_pbh() {
+    fn test_mm256_mask_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -790,12 +790,12 @@ mod tests {
             0b0_10000000_1110000,
             0b0_10000100_1001001,
         ];
-        let src: __m256bh = transmute(src_array);
-        let a: __m256 = transmute(a_array);
-        let b: __m256 = transmute(b_array);
+        let src = u16x16::from_array(src_array).as_m256bh();
+        let a = f32x8::from_array(a_array).as_m256();
+        let b = f32x8::from_array(b_array).as_m256();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b1_10000110_0110010,
@@ -818,13 +818,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtne2ps_pbh() {
+    fn test_mm256_maskz_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -846,11 +846,11 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
-        let b: __m256 = transmute(b_array);
+        let a = f32x8::from_array(a_array).as_m256();
+        let b = f32x8::from_array(b_array).as_m256();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b1_10000110_0110010,
@@ -873,7 +873,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0b0110_1100_0011_0110;
         let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0,
@@ -897,7 +897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_cvtne2ps_pbh() {
+    fn test_mm512_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -935,10 +935,10 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
-        let b: __m512 = transmute(b_array);
+        let a = f32x16::from_array(a_array).as_m512();
+        let b = f32x16::from_array(b_array).as_m512();
         let c: __m512bh = _mm512_cvtne2ps_pbh(a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0b1_10000110_0110010,
@@ -978,7 +978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_mask_cvtne2ps_pbh() {
+    fn test_mm512_mask_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1050,12 +1050,12 @@ mod tests {
             0b0_10000000_1110000,
             0b0_10000100_1001001,
         ];
-        let src: __m512bh = transmute(src_array);
-        let a: __m512 = transmute(a_array);
-        let b: __m512 = transmute(b_array);
+        let src = u16x32::from_array(src_array).as_m512bh();
+        let a = f32x16::from_array(a_array).as_m512();
+        let b = f32x16::from_array(b_array).as_m512();
         let k: __mmask32 = 0xffffffff;
         let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0b1_10000110_0110010,
@@ -1094,13 +1094,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask32 = 0;
         let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_maskz_cvtne2ps_pbh() {
+    fn test_mm512_maskz_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1138,11 +1138,11 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
-        let b: __m512 = transmute(b_array);
+        let a = f32x16::from_array(a_array).as_m512();
+        let b = f32x16::from_array(b_array).as_m512();
         let k: __mmask32 = 0xffffffff;
         let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0b1_10000110_0110010,
@@ -1181,7 +1181,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask32 = 0b1100_1010_1001_0110_1010_0011_0101_0110;
         let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0,
@@ -1221,7 +1221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_cvtneps_pbh() {
+    fn test_mm256_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1233,9 +1233,9 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
+        let a = f32x8::from_array(a_array).as_m256();
         let c: __m128bh = _mm256_cvtneps_pbh(a);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b0_10000110_0110010,
@@ -1251,7 +1251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtneps_pbh() {
+    fn test_mm256_mask_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1273,11 +1273,11 @@ mod tests {
             0b1_10001000_1111010,
             0b1_10001000_0010000,
         ];
-        let src: __m128bh = transmute(src_array);
-        let a: __m256 = transmute(a_array);
+        let src = u16x8::from_array(src_array).as_m128bh();
+        let a = f32x8::from_array(a_array).as_m256();
         let k: __mmask8 = 0xff;
         let b = _mm256_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b0_10000110_0110010,
@@ -1292,13 +1292,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0x0;
         let b: __m128bh = _mm256_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         let expected_result: [u16; 8] = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtneps_pbh() {
+    fn test_mm256_maskz_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1310,10 +1310,10 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
+        let a = f32x8::from_array(a_array).as_m256();
         let k: __mmask8 = 0xff;
         let b = _mm256_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b0_10000110_0110010,
@@ -1328,14 +1328,14 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0x6;
         let b: __m128bh = _mm256_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         let expected_result: [u16; 8] =
             [0, 0b0_10000010_0101000, 0b0_10000000_1110000, 0, 0, 0, 0, 0];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_cvtneps_pbh() {
+    fn test_mm512_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1355,9 +1355,9 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
+        let a = f32x16::from_array(a_array).as_m512();
         let c: __m256bh = _mm512_cvtneps_pbh(a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b0_10000110_0110010,
@@ -1381,7 +1381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_mask_cvtneps_pbh() {
+    fn test_mm512_mask_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1419,11 +1419,11 @@ mod tests {
             0b1_10001000_1111010,
             0b1_10001000_0010000,
         ];
-        let src: __m256bh = transmute(src_array);
-        let a: __m512 = transmute(a_array);
+        let src = u16x16::from_array(src_array).as_m256bh();
+        let a = f32x16::from_array(a_array).as_m512();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b0_10000110_0110010,
@@ -1446,13 +1446,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_maskz_cvtneps_pbh() {
+    fn test_mm512_maskz_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1472,10 +1472,10 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
+        let a = f32x16::from_array(a_array).as_m512();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b0_10000110_0110010,
@@ -1498,7 +1498,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0x653a;
         let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0,
@@ -1522,74 +1522,74 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_dpbf16_ps() {
+    fn test_mm_dpbf16_ps() {
         let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32];
-        let a1: __m128 = transmute(a_array);
-        let b1: __m128 = transmute(b_array);
-        let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]);
+        let a1 = f32x4::from_array(a_array).as_m128();
+        let b1 = f32x4::from_array(b_array).as_m128();
+        let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128();
         let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1);
         let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1);
         let c: __m128 = _mm_dpbf16_ps(src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_dpbf16_ps() {
+    fn test_mm_mask_dpbf16_ps() {
         let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32];
-        let a1: __m128 = transmute(a_array);
-        let b1: __m128 = transmute(b_array);
+        let a1 = f32x4::from_array(a_array).as_m128();
+        let b1 = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0xf3;
-        let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]);
+        let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128();
         let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1);
         let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1);
         let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_dpbf16_ps() {
+    fn test_mm_maskz_dpbf16_ps() {
         let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32];
-        let a1: __m128 = transmute(a_array);
-        let b1: __m128 = transmute(b_array);
+        let a1 = f32x4::from_array(a_array).as_m128();
+        let b1 = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0xf3;
-        let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]);
+        let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128();
         let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1);
         let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1);
         let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 0.0, 0.0];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [0.0, 0.0, 0.0, 0.0];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_dpbf16_ps() {
+    fn test_mm256_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1597,16 +1597,16 @@ mod tests {
         let b_array = [
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m256 = transmute(a_array);
-        let b1: __m256 = transmute(b_array);
+        let a1 = f32x8::from_array(a_array).as_m256();
+        let b1 = f32x8::from_array(b_array).as_m256();
         #[rustfmt::skip]
-        let src: __m256 = transmute([
+        let src = f32x8::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m256();
         let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1);
         let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
         let c: __m256 = _mm256_dpbf16_ps(src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1615,7 +1615,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_dpbf16_ps() {
+    fn test_mm256_mask_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1623,17 +1623,17 @@ mod tests {
         let b_array = [
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m256 = transmute(a_array);
-        let b1: __m256 = transmute(b_array);
+        let a1 = f32x8::from_array(a_array).as_m256();
+        let b1 = f32x8::from_array(b_array).as_m256();
         let k: __mmask8 = 0x33;
         #[rustfmt::skip]
-        let src: __m256 = transmute([
+        let src = f32x8::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m256();
         let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1);
         let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
         let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
@@ -1641,7 +1641,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1649,7 +1649,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
@@ -1658,7 +1658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_dpbf16_ps() {
+    fn test_mm256_maskz_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1666,17 +1666,17 @@ mod tests {
         let b_array = [
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m256 = transmute(a_array);
-        let b1: __m256 = transmute(b_array);
+        let a1 = f32x8::from_array(a_array).as_m256();
+        let b1 = f32x8::from_array(b_array).as_m256();
         let k: __mmask8 = 0x33;
         #[rustfmt::skip]
-        let src: __m256 = transmute([
+        let src = f32x8::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m256();
         let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1);
         let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
         let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0,
@@ -1684,7 +1684,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1692,13 +1692,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         let expected_result: [f32; 8] = [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_dpbf16_ps() {
+    fn test_mm512_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1708,16 +1708,17 @@ mod tests {
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m512 = transmute(a_array);
-        let b1: __m512 = transmute(b_array);
-        let src: __m512 = transmute([
+        let a1 = f32x16::from_array(a_array).as_m512();
+        let b1 = f32x16::from_array(b_array).as_m512();
+        let src = f32x16::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
             2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ])
+        .as_m512();
         let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1);
         let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
         let c: __m512 = _mm512_dpbf16_ps(src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1727,7 +1728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_mask_dpbf16_ps() {
+    fn test_mm512_mask_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1737,18 +1738,18 @@ mod tests {
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m512 = transmute(a_array);
-        let b1: __m512 = transmute(b_array);
+        let a1 = f32x16::from_array(a_array).as_m512();
+        let b1 = f32x16::from_array(b_array).as_m512();
         let k: __mmask16 = 0x3333;
         #[rustfmt::skip]
-        let src: __m512 = transmute([
+        let src = f32x16::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
             2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m512();
         let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1);
         let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
         let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
@@ -1757,7 +1758,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0xffff;
         let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1766,7 +1767,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
@@ -1776,7 +1777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_maskz_dpbf16_ps() {
+    fn test_mm512_maskz_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1786,18 +1787,18 @@ mod tests {
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m512 = transmute(a_array);
-        let b1: __m512 = transmute(b_array);
+        let a1 = f32x16::from_array(a_array).as_m512();
+        let b1 = f32x16::from_array(b_array).as_m512();
         let k: __mmask16 = 0x3333;
         #[rustfmt::skip]
-        let src: __m512 = transmute([
+        let src = f32x16::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
             2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m512();
         let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1);
         let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
         let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32,
@@ -1806,7 +1807,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0xffff;
         let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1815,7 +1816,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0,
@@ -1943,28 +1944,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_cvtneps_pbh() {
+    fn test_mm_cvtneps_pbh() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-        let r: u16x4 = transmute_copy(&_mm_cvtneps_pbh(a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_pbh(a)) };
         let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_cvtneps_pbh() {
+    fn test_mm_mask_cvtneps_pbh() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let src = __m128bh([5, 6, 7, 8, !0, !0, !0, !0]);
         let k = 0b1010;
-        let r: u16x4 = transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a)) };
         let e = u16x4::new(5, BF16_TWO, 7, BF16_FOUR);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtneps_pbh() {
+    fn test_mm_maskz_cvtneps_pbh() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let k = 0b1010;
-        let r: u16x4 = transmute_copy(&_mm_maskz_cvtneps_pbh(k, a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_maskz_cvtneps_pbh(k, a)) };
         let e = u16x4::new(0, BF16_TWO, 0, BF16_FOUR);
         assert_eq!(r, e);
     }
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 6b4b88621e..8e074fdcfa 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -17098,37 +17098,37 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_loadu_epi16() {
+    const fn test_mm512_loadu_epi16() {
         #[rustfmt::skip]
         let a: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
-        let r = _mm512_loadu_epi16(&a[0]);
+        let r = unsafe { _mm512_loadu_epi16(&a[0]) };
         #[rustfmt::skip]
         let e = _mm512_set_epi16(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi16() {
+    const fn test_mm256_loadu_epi16() {
         let a: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let r = _mm256_loadu_epi16(&a[0]);
+        let r = unsafe { _mm256_loadu_epi16(&a[0]) };
         let e = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_loadu_epi16() {
+    const fn test_mm_loadu_epi16() {
         let a: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
-        let r = _mm_loadu_epi16(&a[0]);
+        let r = unsafe { _mm_loadu_epi16(&a[0]) };
         let e = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_loadu_epi8() {
+    const fn test_mm512_loadu_epi8() {
         #[rustfmt::skip]
         let a: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
                            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
-        let r = _mm512_loadu_epi8(&a[0]);
+        let r = unsafe { _mm512_loadu_epi8(&a[0]) };
         #[rustfmt::skip]
         let e = _mm512_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
                                 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
@@ -17136,73 +17136,85 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi8() {
+    const fn test_mm256_loadu_epi8() {
         #[rustfmt::skip]
         let a: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
-        let r = _mm256_loadu_epi8(&a[0]);
+        let r = unsafe { _mm256_loadu_epi8(&a[0]) };
         #[rustfmt::skip]
         let e = _mm256_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_loadu_epi8() {
+    const fn test_mm_loadu_epi8() {
         let a: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let r = _mm_loadu_epi8(&a[0]);
+        let r = unsafe { _mm_loadu_epi8(&a[0]) };
         let e = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_storeu_epi16() {
+    const fn test_mm512_storeu_epi16() {
         let a = _mm512_set1_epi16(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        unsafe {
+            _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi16() {
+    const fn test_mm256_storeu_epi16() {
         let a = _mm256_set1_epi16(9);
         let mut r = _mm256_set1_epi32(0);
-        _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        unsafe {
+            _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_storeu_epi16() {
+    const fn test_mm_storeu_epi16() {
         let a = _mm_set1_epi16(9);
         let mut r = _mm_set1_epi32(0);
-        _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        unsafe {
+            _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_storeu_epi8() {
+    const fn test_mm512_storeu_epi8() {
         let a = _mm512_set1_epi8(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        unsafe {
+            _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi8() {
+    const fn test_mm256_storeu_epi8() {
         let a = _mm256_set1_epi8(9);
         let mut r = _mm256_set1_epi32(0);
-        _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        unsafe {
+            _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_storeu_epi8() {
+    const fn test_mm_storeu_epi8() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi32(0);
-        _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        unsafe {
+            _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_loadu_epi16() {
+    const fn test_mm512_mask_loadu_epi16() {
         let src = _mm512_set1_epi16(42);
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -17210,52 +17222,54 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm512_mask_loadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi16(src, m, black_box(p)) };
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm512_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_loadu_epi16() {
+    const fn test_mm512_maskz_loadu_epi16() {
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm512_maskz_loadu_epi16(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi16(m, black_box(p)) };
         let e = &[
             0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
             26, 0, 28, 0, 30, 0, 32,
         ];
-        let e = _mm512_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_storeu_epi16() {
+    const fn test_mm512_mask_storeu_epi16() {
         let mut r = [42_i16; 32];
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
-        let a = _mm512_loadu_epi16(a.as_ptr());
+        let a = unsafe { _mm512_loadu_epi16(a.as_ptr()) };
         let m = 0b10101010_11001100_11101000_11001010;
-        _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm512_loadu_epi16(e.as_ptr());
-        assert_eq_m512i(_mm512_loadu_epi16(r.as_ptr()), e);
+        let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) };
+        assert_eq_m512i(unsafe { _mm512_loadu_epi16(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_loadu_epi8() {
+    const fn test_mm512_mask_loadu_epi8() {
         let src = _mm512_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -17264,18 +17278,18 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
-        let r = _mm512_mask_loadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi8(src, m, black_box(p)) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44,
             45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42,
         ];
-        let e = _mm512_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_loadu_epi8() {
+    const fn test_mm512_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
@@ -17283,77 +17297,81 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
-        let r = _mm512_maskz_loadu_epi8(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi8(m, black_box(p)) };
         let e = &[
             0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
             26, 0, 28, 0, 30, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 45, 46, 47, 48, 49,
             50, 51, 52, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0,
         ];
-        let e = _mm512_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_storeu_epi8() {
+    const fn test_mm512_mask_storeu_epi8() {
         let mut r = [42_i8; 64];
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
             46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
         ];
-        let a = _mm512_loadu_epi8(a.as_ptr());
+        let a = unsafe { _mm512_loadu_epi8(a.as_ptr()) };
         let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
-        _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44,
             45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42,
         ];
-        let e = _mm512_loadu_epi8(e.as_ptr());
-        assert_eq_m512i(_mm512_loadu_epi8(r.as_ptr()), e);
+        let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) };
+        assert_eq_m512i(unsafe { _mm512_loadu_epi8(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi16() {
+    const fn test_mm256_mask_loadu_epi16() {
         let src = _mm256_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_mask_loadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi16(src, m, black_box(p)) };
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm256_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi16() {
+    const fn test_mm256_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_maskz_loadu_epi16(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi16(m, black_box(p)) };
         let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16];
-        let e = _mm256_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi16() {
+    const fn test_mm256_mask_storeu_epi16() {
         let mut r = [42_i16; 16];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let a = _mm256_loadu_epi16(a.as_ptr());
+        let a = unsafe { _mm256_loadu_epi16(a.as_ptr()) };
         let m = 0b11101000_11001010;
-        _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm256_loadu_epi16(e.as_ptr());
-        assert_eq_m256i(_mm256_loadu_epi16(r.as_ptr()), e);
+        let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) };
+        assert_eq_m256i(unsafe { _mm256_loadu_epi16(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi8() {
+    const fn test_mm256_mask_loadu_epi8() {
         let src = _mm256_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -17361,122 +17379,124 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm256_mask_loadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi8(src, m, black_box(p)) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm256_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi8() {
+    const fn test_mm256_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm256_maskz_loadu_epi8(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi8(m, black_box(p)) };
         let e = &[
             0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
             26, 0, 28, 0, 30, 0, 32,
         ];
-        let e = _mm256_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi8() {
+    const fn test_mm256_mask_storeu_epi8() {
         let mut r = [42_i8; 32];
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
-        let a = _mm256_loadu_epi8(a.as_ptr());
+        let a = unsafe { _mm256_loadu_epi8(a.as_ptr()) };
         let m = 0b10101010_11001100_11101000_11001010;
-        _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm256_loadu_epi8(e.as_ptr());
-        assert_eq_m256i(_mm256_loadu_epi8(r.as_ptr()), e);
+        let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) };
+        assert_eq_m256i(unsafe { _mm256_loadu_epi8(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi16() {
+    const fn test_mm_mask_loadu_epi16() {
         let src = _mm_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm_mask_loadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi16(src, m, black_box(p)) };
         let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8];
-        let e = _mm_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi16(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi16() {
+    const fn test_mm_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm_maskz_loadu_epi16(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi16(m, black_box(p)) };
         let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8];
-        let e = _mm_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi16(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi16() {
+    const fn test_mm_mask_storeu_epi16() {
         let mut r = [42_i16; 8];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
-        let a = _mm_loadu_epi16(a.as_ptr());
+        let a = unsafe { _mm_loadu_epi16(a.as_ptr()) };
         let m = 0b11001010;
-        _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        unsafe { _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a) };
         let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8];
-        let e = _mm_loadu_epi16(e.as_ptr());
-        assert_eq_m128i(_mm_loadu_epi16(r.as_ptr()), e);
+        let e = unsafe { _mm_loadu_epi16(e.as_ptr()) };
+        assert_eq_m128i(unsafe { _mm_loadu_epi16(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi8() {
+    const fn test_mm_mask_loadu_epi8() {
         let src = _mm_set1_epi8(42);
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_mask_loadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi8(src, m, black_box(p)) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi8(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi8() {
+    const fn test_mm_maskz_loadu_epi8() {
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_maskz_loadu_epi8(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi8(m, black_box(p)) };
         let e = &[0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16];
-        let e = _mm_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi8(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi8() {
+    const fn test_mm_mask_storeu_epi8() {
         let mut r = [42_i8; 16];
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let a = _mm_loadu_epi8(a.as_ptr());
+        let a = unsafe { _mm_loadu_epi8(a.as_ptr()) };
         let m = 0b11101000_11001010;
-        _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        unsafe { _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm_loadu_epi8(e.as_ptr());
-        assert_eq_m128i(_mm_loadu_epi8(r.as_ptr()), e);
+        let e = unsafe { _mm_loadu_epi8(e.as_ptr()) };
+        assert_eq_m128i(unsafe { _mm_loadu_epi8(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw")]
@@ -20714,36 +20734,40 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_store_mask64() {
+    const fn test_store_mask64() {
         let a: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
         let mut r = 0;
-        _store_mask64(&mut r, a);
+        unsafe {
+            _store_mask64(&mut r, a);
+        }
         assert_eq!(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_store_mask32() {
+    const fn test_store_mask32() {
         let a: __mmask32 = 0b11111111_00000000_11111111_00000000;
         let mut r = 0;
-        _store_mask32(&mut r, a);
+        unsafe {
+            _store_mask32(&mut r, a);
+        }
         assert_eq!(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_load_mask64() {
+    const fn test_load_mask64() {
         let p: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
-        let r = _load_mask64(&p);
+        let r = unsafe { _load_mask64(&p) };
         let e: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_load_mask32() {
+    const fn test_load_mask32() {
         let p: __mmask32 = 0b11111111_00000000_11111111_00000000;
-        let r = _load_mask32(&p);
+        let r = unsafe { _load_mask32(&p) };
         let e: __mmask32 = 0b11111111_00000000_11111111_00000000;
         assert_eq!(r, e);
     }
@@ -21163,21 +21187,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortest_mask32_u8() {
+    const fn test_kortest_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask32_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask32_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 1);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortest_mask64_u8() {
+    const fn test_kortest_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask64_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask64_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 0);
     }
@@ -21299,11 +21323,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktest_mask32_u8() {
+    const fn test_ktest_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask32_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask32_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -21325,11 +21349,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktest_mask64_u8() {
+    const fn test_ktest_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask64_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask64_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -21951,32 +21975,38 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtsepi16_storeu_epi8() {
+    fn test_mm512_mask_cvtsepi16_storeu_epi8() {
         let a = _mm512_set1_epi16(i16::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtsepi16_storeu_epi8(
-            &mut r as *mut _ as *mut i8,
-            0b11111111_11111111_11111111_11111111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_cvtsepi16_storeu_epi8(
+                &mut r as *mut _ as *mut i8,
+                0b11111111_11111111_11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi8(i8::MAX);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi16_storeu_epi8() {
+    fn test_mm256_mask_cvtsepi16_storeu_epi8() {
         let a = _mm256_set1_epi16(i16::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(i8::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi16_storeu_epi8() {
+    fn test_mm_mask_cvtsepi16_storeu_epi8() {
         let a = _mm_set1_epi16(i16::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0, 0, 0, 0, 0,
@@ -21986,63 +22016,75 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtepi16_storeu_epi8() {
+    fn test_mm512_mask_cvtepi16_storeu_epi8() {
         let a = _mm512_set1_epi16(8);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtepi16_storeu_epi8(
-            &mut r as *mut _ as *mut i8,
-            0b11111111_11111111_11111111_11111111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_cvtepi16_storeu_epi8(
+                &mut r as *mut _ as *mut i8,
+                0b11111111_11111111_11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi8(8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi16_storeu_epi8() {
+    fn test_mm256_mask_cvtepi16_storeu_epi8() {
         let a = _mm256_set1_epi16(8);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi16_storeu_epi8() {
+    fn test_mm_mask_cvtepi16_storeu_epi8() {
         let a = _mm_set1_epi16(8);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtusepi16_storeu_epi8() {
+    fn test_mm512_mask_cvtusepi16_storeu_epi8() {
         let a = _mm512_set1_epi16(i16::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtusepi16_storeu_epi8(
-            &mut r as *mut _ as *mut i8,
-            0b11111111_11111111_11111111_11111111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_cvtusepi16_storeu_epi8(
+                &mut r as *mut _ as *mut i8,
+                0b11111111_11111111_11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi8(u8::MAX as i8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi16_storeu_epi8() {
+    fn test_mm256_mask_cvtusepi16_storeu_epi8() {
         let a = _mm256_set1_epi16(i16::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(u8::MAX as i8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi16_storeu_epi8() {
+    fn test_mm_mask_cvtusepi16_storeu_epi8() {
         let a = _mm_set1_epi16(i16::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
diff --git a/crates/core_arch/src/x86/avx512dq.rs b/crates/core_arch/src/x86/avx512dq.rs
index ebe75cd22d..9e1a4c0b29 100644
--- a/crates/core_arch/src/x86/avx512dq.rs
+++ b/crates/core_arch/src/x86/avx512dq.rs
@@ -7401,27 +7401,25 @@ unsafe extern "C" {
 mod tests {
     use super::*;
     use crate::core_arch::assert_eq_const as assert_eq;
+    use crate::core_arch::x86::*;
 
     use stdarch_test::simd_test;
 
-    use crate::core_arch::x86::*;
-    use crate::mem::transmute;
-
-    const OPRND1_64: f64 = unsafe { transmute(0x3333333333333333_u64) };
-    const OPRND2_64: f64 = unsafe { transmute(0x5555555555555555_u64) };
+    const OPRND1_64: f64 = f64::from_bits(0x3333333333333333);
+    const OPRND2_64: f64 = f64::from_bits(0x5555555555555555);
 
-    const AND_64: f64 = unsafe { transmute(0x1111111111111111_u64) };
-    const ANDN_64: f64 = unsafe { transmute(0x4444444444444444_u64) };
-    const OR_64: f64 = unsafe { transmute(0x7777777777777777_u64) };
-    const XOR_64: f64 = unsafe { transmute(0x6666666666666666_u64) };
+    const AND_64: f64 = f64::from_bits(0x1111111111111111);
+    const ANDN_64: f64 = f64::from_bits(0x4444444444444444);
+    const OR_64: f64 = f64::from_bits(0x7777777777777777);
+    const XOR_64: f64 = f64::from_bits(0x6666666666666666);
 
-    const OPRND1_32: f32 = unsafe { transmute(0x33333333_u32) };
-    const OPRND2_32: f32 = unsafe { transmute(0x55555555_u32) };
+    const OPRND1_32: f32 = f32::from_bits(0x33333333);
+    const OPRND2_32: f32 = f32::from_bits(0x55555555);
 
-    const AND_32: f32 = unsafe { transmute(0x11111111_u32) };
-    const ANDN_32: f32 = unsafe { transmute(0x44444444_u32) };
-    const OR_32: f32 = unsafe { transmute(0x77777777_u32) };
-    const XOR_32: f32 = unsafe { transmute(0x66666666_u32) };
+    const AND_32: f32 = f32::from_bits(0x11111111);
+    const ANDN_32: f32 = f32::from_bits(0x44444444);
+    const OR_32: f32 = f32::from_bits(0x77777777);
+    const XOR_32: f32 = f32::from_bits(0x66666666);
 
     #[simd_test(enable = "avx512dq,avx512vl")]
     const fn test_mm_mask_and_pd() {
@@ -10023,11 +10021,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kortest_mask8_u8() {
+    const fn test_kortest_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask8_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask8_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 1);
     }
@@ -10049,7 +10047,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kshiftli_mask8() {
+    const fn test_kshiftli_mask8() {
         let a: __mmask8 = 0b01101001;
         let r = _kshiftli_mask8::<3>(a);
         let e: __mmask8 = 0b01001000;
@@ -10089,11 +10087,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktest_mask8_u8() {
+    const fn test_ktest_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask8_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask8_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -10115,11 +10113,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktest_mask16_u8() {
+    const fn test_ktest_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask16_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask16_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -10141,18 +10139,20 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_load_mask8() {
+    const fn test_load_mask8() {
         let a: __mmask8 = 0b01101001;
-        let r = _load_mask8(&a);
+        let r = unsafe { _load_mask8(&a) };
         let e: __mmask8 = 0b01101001;
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_store_mask8() {
+    const fn test_store_mask8() {
         let a: __mmask8 = 0b01101001;
         let mut r = 0;
-        _store_mask8(&mut r, a);
+        unsafe {
+            _store_mask8(&mut r, a);
+        }
         let e: __mmask8 = 0b01101001;
         assert_eq!(r, e);
     }
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 76b7539383..3730496e1e 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -48062,9 +48062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_ternarylogic_epi32() {
-        use core::intrinsics::simd::simd_xor;
-
+    fn test_mm512_ternarylogic_epi32() {
         let a = _mm512_set4_epi32(0b100, 0b110, 0b001, 0b101);
         let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b110);
         let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b111);
@@ -48077,7 +48075,7 @@ mod tests {
         let r = _mm512_ternarylogic_epi32::<0b10010110>(a, b, c);
         let e = _mm512_set4_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m512i(r, e);
-        assert_eq_m512i(r, simd_xor(simd_xor(a, b), c));
+        assert_eq_m512i(r, _mm512_xor_si512(_mm512_xor_si512(a, b), c));
 
         // Majority (2 or more bits set).
         let r = _mm512_ternarylogic_epi32::<0b1110_1000>(a, b, c);
@@ -48110,9 +48108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_ternarylogic_epi32() {
-        use core::intrinsics::simd::simd_xor;
-
+    fn test_mm256_ternarylogic_epi32() {
         let _mm256_set4_epi32 = |a, b, c, d| _mm256_setr_epi32(a, b, c, d, a, b, c, d);
 
         let a = _mm256_set4_epi32(0b100, 0b110, 0b001, 0b101);
@@ -48127,7 +48123,7 @@ mod tests {
         let r = _mm256_ternarylogic_epi32::<0b10010110>(a, b, c);
         let e = _mm256_set4_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m256i(r, e);
-        assert_eq_m256i(r, simd_xor(simd_xor(a, b), c));
+        assert_eq_m256i(r, _mm256_xor_si256(_mm256_xor_si256(a, b), c));
 
         // Majority (2 or more bits set).
         let r = _mm256_ternarylogic_epi32::<0b1110_1000>(a, b, c);
@@ -48160,9 +48156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_ternarylogic_epi32() {
-        use core::intrinsics::simd::simd_xor;
-
+    fn test_mm_ternarylogic_epi32() {
         let a = _mm_setr_epi32(0b100, 0b110, 0b001, 0b101);
         let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b110);
         let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b111);
@@ -48175,7 +48169,7 @@ mod tests {
         let r = _mm_ternarylogic_epi32::<0b10010110>(a, b, c);
         let e = _mm_setr_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m128i(r, e);
-        assert_eq_m128i(r, simd_xor(simd_xor(a, b), c));
+        assert_eq_m128i(r, _mm_xor_si128(_mm_xor_si128(a, b), c));
 
         // Majority (2 or more bits set).
         let r = _mm_ternarylogic_epi32::<0b1110_1000>(a, b, c);
@@ -51447,20 +51441,20 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_ps() {
+    fn test_mm512_i32gather_ps() {
         let arr: [f32; 256] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing
         #[rustfmt::skip]
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                       120, 128, 136, 144, 152, 160, 168, 176);
-        let r = _mm512_i32gather_ps::<4>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_ps::<4>(index, arr.as_ptr()) };
         #[rustfmt::skip]
         assert_eq_m512(r, _mm512_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.,
                                          120., 128., 136., 144., 152., 160., 168., 176.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_ps() {
+    fn test_mm512_mask_i32gather_ps() {
         let arr: [f32; 256] = core::array::from_fn(|i| i as f32);
         let src = _mm512_set1_ps(2.);
         let mask = 0b10101010_10101010;
@@ -51468,27 +51462,27 @@ mod tests {
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                       120, 128, 136, 144, 152, 160, 168, 176);
         // A multiplier of 4 is word-addressing
-        let r = _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr()) };
         #[rustfmt::skip]
         assert_eq_m512(r, _mm512_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.,
                                          2., 128., 2., 144., 2., 160., 2., 176.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_epi32() {
+    fn test_mm512_i32gather_epi32() {
         let arr: [i32; 256] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
         #[rustfmt::skip]
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                       120, 128, 136, 144, 152, 160, 168, 176);
-        let r = _mm512_i32gather_epi32::<4>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_epi32::<4>(index, arr.as_ptr()) };
         #[rustfmt::skip]
         assert_eq_m512i(r, _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                              120, 128, 136, 144, 152, 160, 168, 176));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_epi32() {
+    fn test_mm512_mask_i32gather_epi32() {
         let arr: [i32; 256] = core::array::from_fn(|i| i as i32);
         let src = _mm512_set1_epi32(2);
         let mask = 0b10101010_10101010;
@@ -51496,7 +51490,7 @@ mod tests {
             0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240,
         );
         // A multiplier of 4 is word-addressing
-        let r = _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512i(
             r,
             _mm512_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112, 2, 144, 2, 176, 2, 208, 2, 240),
@@ -51504,7 +51498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_ps() {
+    fn test_mm512_i32scatter_ps() {
         let mut arr = [0f32; 256];
         #[rustfmt::skip]
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
@@ -51513,7 +51507,9 @@ mod tests {
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
         // A multiplier of 4 is word-addressing
-        _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f32; 256];
         for i in 0..16 {
             expected[i * 16] = (i + 1) as f32;
@@ -51522,7 +51518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_ps() {
+    fn test_mm512_mask_i32scatter_ps() {
         let mut arr = [0f32; 256];
         let mask = 0b10101010_10101010;
         #[rustfmt::skip]
@@ -51532,7 +51528,9 @@ mod tests {
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f32; 256];
         for i in 0..8 {
             expected[i * 32 + 16] = 2. * (i + 1) as f32;
@@ -51541,7 +51539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_epi32() {
+    fn test_mm512_i32scatter_epi32() {
         let mut arr = [0i32; 256];
         #[rustfmt::skip]
 
@@ -51549,7 +51547,9 @@ mod tests {
                                       128, 144, 160, 176, 192, 208, 224, 240);
         let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         // A multiplier of 4 is word-addressing
-        _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i32; 256];
         for i in 0..16 {
             expected[i * 16] = (i + 1) as i32;
@@ -51558,7 +51558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_epi32() {
+    fn test_mm512_mask_i32scatter_epi32() {
         let mut arr = [0i32; 256];
         let mask = 0b10101010_10101010;
         #[rustfmt::skip]
@@ -51566,7 +51566,9 @@ mod tests {
                                       128, 144, 160, 176, 192, 208, 224, 240);
         let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i32; 256];
         for i in 0..8 {
             expected[i * 32 + 16] = 2 * (i + 1) as i32;
@@ -52850,29 +52852,31 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_pd() {
+    const fn test_mm512_loadu_pd() {
         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
         let p = a.as_ptr();
-        let r = _mm512_loadu_pd(black_box(p));
+        let r = unsafe { _mm512_loadu_pd(black_box(p)) };
         let e = _mm512_setr_pd(4., 3., 2., 5., 8., 9., 64., 50.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_pd() {
+    const fn test_mm512_storeu_pd() {
         let a = _mm512_set1_pd(9.);
         let mut r = _mm512_undefined_pd();
-        _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a);
+        unsafe {
+            _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a);
+        }
         assert_eq_m512d(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_ps() {
+    const fn test_mm512_loadu_ps() {
         let a = &[
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         ];
         let p = a.as_ptr();
-        let r = _mm512_loadu_ps(black_box(p));
+        let r = unsafe { _mm512_loadu_ps(black_box(p)) };
         let e = _mm512_setr_ps(
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         );
@@ -52880,36 +52884,38 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_ps() {
+    const fn test_mm512_storeu_ps() {
         let a = _mm512_set1_ps(9.);
         let mut r = _mm512_undefined_ps();
-        _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a);
+        unsafe {
+            _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a);
+        }
         assert_eq_m512(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_epi32() {
+    const fn test_mm512_mask_loadu_epi32() {
         let src = _mm512_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_loadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi32(src, m, black_box(p)) };
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_epi32() {
+    const fn test_mm512_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_loadu_epi32(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi32(m, black_box(p)) };
         let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_epi32() {
+    const fn test_mm512_mask_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -52920,13 +52926,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_load_epi32(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_epi32(src, m, black_box(p)) };
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_epi32() {
+    const fn test_mm512_maskz_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -52936,23 +52942,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_load_epi32(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_epi32(m, black_box(p)) };
         let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_epi32() {
+    const fn test_mm512_mask_storeu_epi32() {
         let mut r = [42_i32; 16];
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let m = 0b11101000_11001010;
-        _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
-        assert_eq_m512i(_mm512_loadu_epi32(r.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_loadu_epi32(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_epi32() {
+    const fn test_mm512_mask_store_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16],
@@ -52960,34 +52968,36 @@ mod tests {
         let mut r = Align { data: [42; 16] };
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let m = 0b11101000_11001010;
-        _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
-        assert_eq_m512i(_mm512_load_epi32(r.data.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_load_epi32(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_epi64() {
+    const fn test_mm512_mask_loadu_epi64() {
         let src = _mm512_set1_epi64(42);
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_loadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi64(src, m, black_box(p)) };
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_epi64() {
+    const fn test_mm512_maskz_loadu_epi64() {
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_loadu_epi64(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi64(m, black_box(p)) };
         let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_epi64() {
+    const fn test_mm512_mask_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -52998,13 +53008,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_load_epi64(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_epi64(src, m, black_box(p)) };
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_epi64() {
+    const fn test_mm512_maskz_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -53014,23 +53024,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_load_epi64(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_epi64(m, black_box(p)) };
         let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_epi64() {
+    const fn test_mm512_mask_storeu_epi64() {
         let mut r = [42_i64; 8];
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
-        _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m512i(_mm512_loadu_epi64(r.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_loadu_epi64(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_epi64() {
+    const fn test_mm512_mask_store_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8],
@@ -53039,13 +53051,15 @@ mod tests {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
         let p = r.data.as_mut_ptr();
-        _mm512_mask_store_epi64(p, m, a);
+        unsafe {
+            _mm512_mask_store_epi64(p, m, a);
+        }
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m512i(_mm512_load_epi64(r.data.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_load_epi64(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_ps() {
+    const fn test_mm512_mask_loadu_ps() {
         let src = _mm512_set1_ps(42.0);
         let a = &[
             1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0,
@@ -53053,7 +53067,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_loadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_ps(src, m, black_box(p)) };
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
@@ -53062,14 +53076,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_ps() {
+    const fn test_mm512_maskz_loadu_ps() {
         let a = &[
             1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0,
             16.0,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_loadu_ps(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_ps(m, black_box(p)) };
         let e = _mm512_setr_ps(
             0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0,
         );
@@ -53077,7 +53091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_ps() {
+    const fn test_mm512_mask_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -53091,7 +53105,7 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_load_ps(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_ps(src, m, black_box(p)) };
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
@@ -53100,7 +53114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_ps() {
+    const fn test_mm512_maskz_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -53113,7 +53127,7 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_load_ps(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_ps(m, black_box(p)) };
         let e = _mm512_setr_ps(
             0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0,
         );
@@ -53121,22 +53135,24 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_ps() {
+    const fn test_mm512_mask_storeu_ps() {
         let mut r = [42_f32; 16];
         let a = _mm512_setr_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let m = 0b11101000_11001010;
-        _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
         );
-        assert_eq_m512(_mm512_loadu_ps(r.as_ptr()), e);
+        assert_eq_m512(unsafe { _mm512_loadu_ps(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_ps() {
+    const fn test_mm512_mask_store_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16],
@@ -53146,37 +53162,39 @@ mod tests {
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let m = 0b11101000_11001010;
-        _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
         );
-        assert_eq_m512(_mm512_load_ps(r.data.as_ptr()), e);
+        assert_eq_m512(unsafe { _mm512_load_ps(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_pd() {
+    const fn test_mm512_mask_loadu_pd() {
         let src = _mm512_set1_pd(42.0);
         let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_loadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_pd(src, m, black_box(p)) };
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_pd() {
+    const fn test_mm512_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_loadu_pd(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_pd(m, black_box(p)) };
         let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_pd() {
+    const fn test_mm512_mask_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -53187,13 +53205,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_load_pd(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_pd(src, m, black_box(p)) };
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_pd() {
+    const fn test_mm512_maskz_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -53203,23 +53221,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_load_pd(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_pd(m, black_box(p)) };
         let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_pd() {
+    const fn test_mm512_mask_storeu_pd() {
         let mut r = [42_f64; 8];
         let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m512d(_mm512_loadu_pd(r.as_ptr()), e);
+        assert_eq_m512d(unsafe { _mm512_loadu_pd(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_pd() {
+    const fn test_mm512_mask_store_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8],
@@ -53227,34 +53247,36 @@ mod tests {
         let mut r = Align { data: [42.0; 8] };
         let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m512d(_mm512_load_pd(r.data.as_ptr()), e);
+        assert_eq_m512d(unsafe { _mm512_load_pd(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi32() {
+    const fn test_mm256_mask_loadu_epi32() {
         let src = _mm256_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_loadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi32(src, m, black_box(p)) };
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi32() {
+    const fn test_mm256_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_loadu_epi32(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi32(m, black_box(p)) };
         let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_epi32() {
+    const fn test_mm256_mask_load_epi32() {
         #[repr(align(32))]
         struct Align {
             data: [i32; 8], // 32 bytes
@@ -53265,13 +53287,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_load_epi32(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_epi32(src, m, black_box(p)) };
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_epi32() {
+    const fn test_mm256_maskz_load_epi32() {
         #[repr(align(32))]
         struct Align {
             data: [i32; 8], // 32 bytes
@@ -53281,23 +53303,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_load_epi32(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_epi32(m, black_box(p)) };
         let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi32() {
+    const fn test_mm256_mask_storeu_epi32() {
         let mut r = [42_i32; 8];
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
-        _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m256i(_mm256_loadu_epi32(r.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_loadu_epi32(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_epi32() {
+    const fn test_mm256_mask_store_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 8],
@@ -53305,34 +53329,36 @@ mod tests {
         let mut r = Align { data: [42; 8] };
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
-        _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m256i(_mm256_load_epi32(r.data.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_load_epi32(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi64() {
+    const fn test_mm256_mask_loadu_epi64() {
         let src = _mm256_set1_epi64x(42);
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_loadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi64(src, m, black_box(p)) };
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi64() {
+    const fn test_mm256_maskz_loadu_epi64() {
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_loadu_epi64(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi64(m, black_box(p)) };
         let e = _mm256_setr_epi64x(0, 2, 0, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_epi64() {
+    const fn test_mm256_mask_load_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4], // 32 bytes
@@ -53343,13 +53369,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_load_epi64(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_epi64(src, m, black_box(p)) };
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_epi64() {
+    const fn test_mm256_maskz_load_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4], // 32 bytes
@@ -53359,23 +53385,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_load_epi64(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_epi64(m, black_box(p)) };
         let e = _mm256_setr_epi64x(0, 2, 0, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi64() {
+    const fn test_mm256_mask_storeu_epi64() {
         let mut r = [42_i64; 4];
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let m = 0b1010;
-        _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
-        assert_eq_m256i(_mm256_loadu_epi64(r.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_loadu_epi64(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_epi64() {
+    const fn test_mm256_mask_store_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4],
@@ -53383,34 +53411,36 @@ mod tests {
         let mut r = Align { data: [42; 4] };
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let m = 0b1010;
-        _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
-        assert_eq_m256i(_mm256_load_epi64(r.data.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_load_epi64(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_ps() {
+    const fn test_mm256_mask_loadu_ps() {
         let src = _mm256_set1_ps(42.0);
         let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_loadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_ps(src, m, black_box(p)) };
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_ps() {
+    const fn test_mm256_maskz_loadu_ps() {
         let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_loadu_ps(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_ps(m, black_box(p)) };
         let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_ps() {
+    const fn test_mm256_mask_load_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8], // 32 bytes
@@ -53421,13 +53451,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_load_ps(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_ps(src, m, black_box(p)) };
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_ps() {
+    const fn test_mm256_maskz_load_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8], // 32 bytes
@@ -53437,23 +53467,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_load_ps(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_ps(m, black_box(p)) };
         let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_ps() {
+    const fn test_mm256_mask_storeu_ps() {
         let mut r = [42_f32; 8];
         let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m256(_mm256_loadu_ps(r.as_ptr()), e);
+        assert_eq_m256(unsafe { _mm256_loadu_ps(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_ps() {
+    const fn test_mm256_mask_store_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8],
@@ -53461,34 +53493,36 @@ mod tests {
         let mut r = Align { data: [42.0; 8] };
         let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m256(_mm256_load_ps(r.data.as_ptr()), e);
+        assert_eq_m256(unsafe { _mm256_load_ps(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_pd() {
+    const fn test_mm256_mask_loadu_pd() {
         let src = _mm256_set1_pd(42.0);
         let a = &[1.0_f64, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_loadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_pd(src, m, black_box(p)) };
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_pd() {
+    const fn test_mm256_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_loadu_pd(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_pd(m, black_box(p)) };
         let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_pd() {
+    const fn test_mm256_mask_load_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4], // 32 bytes
@@ -53499,13 +53533,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_load_pd(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_pd(src, m, black_box(p)) };
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_pd() {
+    const fn test_mm256_maskz_load_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4], // 32 bytes
@@ -53515,23 +53549,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_load_pd(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_pd(m, black_box(p)) };
         let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_pd() {
+    const fn test_mm256_mask_storeu_pd() {
         let mut r = [42_f64; 4];
         let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m256d(_mm256_loadu_pd(r.as_ptr()), e);
+        assert_eq_m256d(unsafe { _mm256_loadu_pd(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_pd() {
+    const fn test_mm256_mask_store_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4],
@@ -53539,34 +53575,36 @@ mod tests {
         let mut r = Align { data: [42.0; 4] };
         let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m256d(_mm256_load_pd(r.data.as_ptr()), e);
+        assert_eq_m256d(unsafe { _mm256_load_pd(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi32() {
+    const fn test_mm_mask_loadu_epi32() {
         let src = _mm_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_loadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi32(src, m, black_box(p)) };
         let e = _mm_setr_epi32(42, 2, 42, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi32() {
+    const fn test_mm_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_loadu_epi32(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi32(m, black_box(p)) };
         let e = _mm_setr_epi32(0, 2, 0, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_epi32() {
+    const fn test_mm_mask_load_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 32 bytes
@@ -53577,13 +53615,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_load_epi32(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_epi32(src, m, black_box(p)) };
         let e = _mm_setr_epi32(42, 2, 42, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_epi32() {
+    const fn test_mm_maskz_load_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 16 bytes
@@ -53593,23 +53631,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_load_epi32(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_epi32(m, black_box(p)) };
         let e = _mm_setr_epi32(0, 2, 0, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi32() {
+    const fn test_mm_mask_storeu_epi32() {
         let mut r = [42_i32; 4];
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let m = 0b1010;
-        _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi32(42, 2, 42, 4);
-        assert_eq_m128i(_mm_loadu_epi32(r.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_loadu_epi32(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_epi32() {
+    const fn test_mm_mask_store_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 16 bytes
@@ -53617,34 +53657,36 @@ mod tests {
         let mut r = Align { data: [42; 4] };
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let m = 0b1010;
-        _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi32(42, 2, 42, 4);
-        assert_eq_m128i(_mm_load_epi32(r.data.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_load_epi32(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi64() {
+    const fn test_mm_mask_loadu_epi64() {
         let src = _mm_set1_epi64x(42);
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_loadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi64(src, m, black_box(p)) };
         let e = _mm_setr_epi64x(42, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi64() {
+    const fn test_mm_maskz_loadu_epi64() {
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_loadu_epi64(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi64(m, black_box(p)) };
         let e = _mm_setr_epi64x(0, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_epi64() {
+    const fn test_mm_mask_load_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -53653,13 +53695,13 @@ mod tests {
         let a = Align { data: [1_i64, 2] };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_load_epi64(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_epi64(src, m, black_box(p)) };
         let e = _mm_setr_epi64x(42, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_epi64() {
+    const fn test_mm_maskz_load_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -53667,23 +53709,25 @@ mod tests {
         let a = Align { data: [1_i64, 2] };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_load_epi64(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_epi64(m, black_box(p)) };
         let e = _mm_setr_epi64x(0, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi64() {
+    const fn test_mm_mask_storeu_epi64() {
         let mut r = [42_i64; 2];
         let a = _mm_setr_epi64x(1, 2);
         let m = 0b10;
-        _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi64x(42, 2);
-        assert_eq_m128i(_mm_loadu_epi64(r.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_loadu_epi64(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_epi64() {
+    const fn test_mm_mask_store_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -53691,34 +53735,36 @@ mod tests {
         let mut r = Align { data: [42; 2] };
         let a = _mm_setr_epi64x(1, 2);
         let m = 0b10;
-        _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi64x(42, 2);
-        assert_eq_m128i(_mm_load_epi64(r.data.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_load_epi64(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_ps() {
+    const fn test_mm_mask_loadu_ps() {
         let src = _mm_set1_ps(42.0);
         let a = &[1.0_f32, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_loadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_ps(src, m, black_box(p)) };
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_ps() {
+    const fn test_mm_maskz_loadu_ps() {
         let a = &[1.0_f32, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_loadu_ps(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_ps(m, black_box(p)) };
         let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_ps() {
+    const fn test_mm_mask_load_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -53729,13 +53775,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_load_ps(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_ps(src, m, black_box(p)) };
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_ps() {
+    const fn test_mm_maskz_load_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -53745,23 +53791,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_load_ps(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_ps(m, black_box(p)) };
         let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_ps() {
+    const fn test_mm_mask_storeu_ps() {
         let mut r = [42_f32; 4];
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m128(_mm_loadu_ps(r.as_ptr()), e);
+        assert_eq_m128(unsafe { _mm_loadu_ps(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_ps() {
+    const fn test_mm_mask_store_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -53769,34 +53817,36 @@ mod tests {
         let mut r = Align { data: [42.0; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m128(_mm_load_ps(r.data.as_ptr()), e);
+        assert_eq_m128(unsafe { _mm_load_ps(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_pd() {
+    const fn test_mm_mask_loadu_pd() {
         let src = _mm_set1_pd(42.0);
         let a = &[1.0_f64, 2.0];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_loadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_pd(src, m, black_box(p)) };
         let e = _mm_setr_pd(42.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_pd() {
+    const fn test_mm_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_loadu_pd(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_pd(m, black_box(p)) };
         let e = _mm_setr_pd(0.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_pd() {
+    const fn test_mm_mask_load_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -53807,13 +53857,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_load_pd(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_pd(src, m, black_box(p)) };
         let e = _mm_setr_pd(42.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_pd() {
+    const fn test_mm_maskz_load_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -53823,77 +53873,79 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_load_pd(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_pd(m, black_box(p)) };
         let e = _mm_setr_pd(0.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_load_ss() {
+    fn test_mm_mask_load_ss() {
         #[repr(align(16))]
         struct Align {
             data: f32,
         }
         let src = _mm_set_ss(2.0);
         let mem = Align { data: 1.0 };
-        let r = _mm_mask_load_ss(src, 0b1, &mem.data);
+        let r = unsafe { _mm_mask_load_ss(src, 0b1, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(1.0));
-        let r = _mm_mask_load_ss(src, 0b0, &mem.data);
+        let r = unsafe { _mm_mask_load_ss(src, 0b0, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(2.0));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_load_ss() {
+    fn test_mm_maskz_load_ss() {
         #[repr(align(16))]
         struct Align {
             data: f32,
         }
         let mem = Align { data: 1.0 };
-        let r = _mm_maskz_load_ss(0b1, &mem.data);
+        let r = unsafe { _mm_maskz_load_ss(0b1, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(1.0));
-        let r = _mm_maskz_load_ss(0b0, &mem.data);
+        let r = unsafe { _mm_maskz_load_ss(0b0, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(0.0));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_load_sd() {
+    fn test_mm_mask_load_sd() {
         #[repr(align(16))]
         struct Align {
             data: f64,
         }
         let src = _mm_set_sd(2.0);
         let mem = Align { data: 1.0 };
-        let r = _mm_mask_load_sd(src, 0b1, &mem.data);
+        let r = unsafe { _mm_mask_load_sd(src, 0b1, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(1.0));
-        let r = _mm_mask_load_sd(src, 0b0, &mem.data);
+        let r = unsafe { _mm_mask_load_sd(src, 0b0, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(2.0));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_load_sd() {
+    fn test_mm_maskz_load_sd() {
         #[repr(align(16))]
         struct Align {
             data: f64,
         }
         let mem = Align { data: 1.0 };
-        let r = _mm_maskz_load_sd(0b1, &mem.data);
+        let r = unsafe { _mm_maskz_load_sd(0b1, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(1.0));
-        let r = _mm_maskz_load_sd(0b0, &mem.data);
+        let r = unsafe { _mm_maskz_load_sd(0b0, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(0.0));
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_pd() {
+    const fn test_mm_mask_storeu_pd() {
         let mut r = [42_f64; 2];
         let a = _mm_setr_pd(1.0, 2.0);
         let m = 0b10;
-        _mm_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_pd(42.0, 2.0);
-        assert_eq_m128d(_mm_loadu_pd(r.as_ptr()), e);
+        assert_eq_m128d(unsafe { _mm_loadu_pd(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_pd() {
+    const fn test_mm_mask_store_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -53901,36 +53953,46 @@ mod tests {
         let mut r = Align { data: [42.0; 2] };
         let a = _mm_setr_pd(1.0, 2.0);
         let m = 0b10;
-        _mm_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_pd(42.0, 2.0);
-        assert_eq_m128d(_mm_load_pd(r.data.as_ptr()), e);
+        assert_eq_m128d(unsafe { _mm_load_pd(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_store_ss() {
+    fn test_mm_mask_store_ss() {
         #[repr(align(16))]
         struct Align {
             data: f32,
         }
         let a = _mm_set_ss(2.0);
         let mut mem = Align { data: 1.0 };
-        _mm_mask_store_ss(&mut mem.data, 0b1, a);
+        unsafe {
+            _mm_mask_store_ss(&mut mem.data, 0b1, a);
+        }
         assert_eq!(mem.data, 2.0);
-        _mm_mask_store_ss(&mut mem.data, 0b0, a);
+        unsafe {
+            _mm_mask_store_ss(&mut mem.data, 0b0, a);
+        }
         assert_eq!(mem.data, 2.0);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_store_sd() {
+    fn test_mm_mask_store_sd() {
         #[repr(align(16))]
         struct Align {
             data: f64,
         }
         let a = _mm_set_sd(2.0);
         let mut mem = Align { data: 1.0 };
-        _mm_mask_store_sd(&mut mem.data, 0b1, a);
+        unsafe {
+            _mm_mask_store_sd(&mut mem.data, 0b1, a);
+        }
         assert_eq!(mem.data, 2.0);
-        _mm_mask_store_sd(&mut mem.data, 0b0, a);
+        unsafe {
+            _mm_mask_store_sd(&mut mem.data, 0b0, a);
+        }
         assert_eq!(mem.data, 2.0);
     }
 
@@ -57931,11 +57993,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kortest_mask16_u8() {
+    const fn test_kortest_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask16_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask16_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 1);
     }
@@ -57997,18 +58059,20 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_load_mask16() {
+    const fn test_load_mask16() {
         let a: __mmask16 = 0b1001011011000011;
-        let r = _load_mask16(&a);
+        let r = unsafe { _load_mask16(&a) };
         let e: __mmask16 = 0b1001011011000011;
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_store_mask16() {
+    const fn test_store_mask16() {
         let a: __mmask16 = 0b0110100100111100;
         let mut r = 0;
-        _store_mask16(&mut r, a);
+        unsafe {
+            _store_mask16(&mut r, a);
+        }
         let e: __mmask16 = 0b0110100100111100;
         assert_eq!(r, e);
     }
@@ -58189,7 +58253,7 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm512_stream_ps() {
+    fn test_mm512_stream_ps() {
         #[repr(align(64))]
         struct Memory {
             pub data: [f32; 16], // 64 bytes
@@ -58197,7 +58261,9 @@ mod tests {
         let a = _mm512_set1_ps(7.0);
         let mut mem = Memory { data: [-1.0; 16] };
 
-        _mm512_stream_ps(&mut mem.data[0] as *mut f32, a);
+        unsafe {
+            _mm512_stream_ps(&mut mem.data[0] as *mut f32, a);
+        }
         _mm_sfence();
         for i in 0..16 {
             assert_eq!(mem.data[i], get_m512(a, i));
@@ -58206,7 +58272,7 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm512_stream_pd() {
+    fn test_mm512_stream_pd() {
         #[repr(align(64))]
         struct Memory {
             pub data: [f64; 8],
@@ -58214,7 +58280,9 @@ mod tests {
         let a = _mm512_set1_pd(7.0);
         let mut mem = Memory { data: [-1.0; 8] };
 
-        _mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
+        unsafe {
+            _mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
+        }
         _mm_sfence();
         for i in 0..8 {
             assert_eq!(mem.data[i], get_m512d(a, i));
@@ -58223,7 +58291,7 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm512_stream_si512() {
+    fn test_mm512_stream_si512() {
         #[repr(align(64))]
         struct Memory {
             pub data: [i64; 8],
@@ -58231,7 +58299,9 @@ mod tests {
         let a = _mm512_set1_epi32(7);
         let mut mem = Memory { data: [-1; 8] };
 
-        _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a);
+        unsafe {
+            _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a);
+        }
         _mm_sfence();
         for i in 0..8 {
             assert_eq!(mem.data[i], get_m512i(a, i));
@@ -58239,9 +58309,9 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_stream_load_si512() {
+    fn test_mm512_stream_load_si512() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _) };
         assert_eq_m512i(a, r);
     }
 
@@ -58558,75 +58628,103 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_epi32() {
+    fn test_mm512_mask_compressstoreu_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let mut r = [0_i32; 16];
-        _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i32; 16]);
-        _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi32() {
+    fn test_mm256_mask_compressstoreu_epi32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = [0_i32; 8];
-        _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i32; 8]);
-        _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi32() {
+    fn test_mm_mask_compressstoreu_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = [0_i32; 4];
-        _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i32; 4]);
-        _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1, 2, 4, 0]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_epi64() {
+    fn test_mm512_mask_compressstoreu_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = [0_i64; 8];
-        _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i64; 8]);
-        _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi64() {
+    fn test_mm256_mask_compressstoreu_epi64() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = [0_i64; 4];
-        _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i64; 4]);
-        _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1, 2, 4, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi64() {
+    fn test_mm_mask_compressstoreu_epi64() {
         let a = _mm_setr_epi64x(1, 2);
         let mut r = [0_i64; 2];
-        _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i64; 2]);
-        _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a);
+        }
         assert_eq!(&r, &[2, 0]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_ps() {
+    fn test_mm512_mask_compressstoreu_ps() {
         let a = _mm512_setr_ps(
             1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32, 9_f32, 10_f32, 11_f32, 12_f32,
             13_f32, 14_f32, 15_f32, 16_f32,
         );
         let mut r = [0_f32; 16];
-        _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_f32; 16]);
-        _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a);
+        }
         assert_eq!(
             &r,
             &[
@@ -58637,12 +58735,16 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_ps() {
+    fn test_mm256_mask_compressstoreu_ps() {
         let a = _mm256_setr_ps(1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32);
         let mut r = [0_f32; 8];
-        _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_f32; 8]);
-        _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(
             &r,
             &[2_f32, 4_f32, 7_f32, 8_f32, 0_f32, 0_f32, 0_f32, 0_f32]
@@ -58650,47 +58752,63 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_ps() {
+    fn test_mm_mask_compressstoreu_ps() {
         let a = _mm_setr_ps(1_f32, 2_f32, 3_f32, 4_f32);
         let mut r = [0.; 4];
-        _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 4]);
-        _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1_f32, 2_f32, 4_f32, 0_f32]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_pd() {
+    fn test_mm512_mask_compressstoreu_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let mut r = [0.; 8];
-        _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 8]);
-        _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(&r, &[2., 4., 7., 8., 0., 0., 0., 0.]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_pd() {
+    fn test_mm256_mask_compressstoreu_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut r = [0.; 4];
-        _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 4]);
-        _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1., 2., 4., 0.]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_pd() {
+    fn test_mm_mask_compressstoreu_pd() {
         let a = _mm_setr_pd(1., 2.);
         let mut r = [0.; 2];
-        _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 2]);
-        _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a);
+        unsafe {
+            _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a);
+        }
         assert_eq!(&r, &[2., 0.]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expand_epi32() {
+    fn test_mm512_mask_expand_epi32() {
         let src = _mm512_set1_epi32(200);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_mask_expand_epi32(src, 0, a);
@@ -58826,109 +58944,135 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_epi32() {
+    const fn test_mm512_loadu_epi32() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50];
         let p = a.as_ptr();
-        let r = _mm512_loadu_epi32(black_box(p));
+        let r = unsafe { _mm512_loadu_epi32(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi32() {
+    const fn test_mm256_loadu_epi32() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50];
         let p = a.as_ptr();
-        let r = _mm256_loadu_epi32(black_box(p));
+        let r = unsafe { _mm256_loadu_epi32(black_box(p)) };
         let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_loadu_epi32() {
+    const fn test_mm_loadu_epi32() {
         let a = &[4, 3, 2, 5];
         let p = a.as_ptr();
-        let r = _mm_loadu_epi32(black_box(p));
+        let r = unsafe { _mm_loadu_epi32(black_box(p)) };
         let e = _mm_setr_epi32(4, 3, 2, 5);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_storeu_epi16() {
+    fn test_mm512_mask_cvtepi32_storeu_epi16() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        }
         let e = _mm256_set1_epi16(9);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_storeu_epi16() {
+    fn test_mm256_mask_cvtepi32_storeu_epi16() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_storeu_epi16() {
+    fn test_mm_mask_cvtepi32_storeu_epi16() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi32_storeu_epi16() {
+    fn test_mm512_mask_cvtsepi32_storeu_epi16() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi32_storeu_epi16(
+                &mut r as *mut _ as *mut i16,
+                0b11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi16(i16::MAX);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi32_storeu_epi16() {
+    fn test_mm256_mask_cvtsepi32_storeu_epi16() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi32_storeu_epi16() {
+    fn test_mm_mask_cvtsepi32_storeu_epi16() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi32_storeu_epi16() {
+    fn test_mm512_mask_cvtusepi32_storeu_epi16() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi32_storeu_epi16(
+                &mut r as *mut _ as *mut i16,
+                0b11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi16(u16::MAX as i16);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi32_storeu_epi16() {
+    fn test_mm256_mask_cvtusepi32_storeu_epi16() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(u16::MAX as i16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi32_storeu_epi16() {
+    fn test_mm_mask_cvtusepi32_storeu_epi16() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(
             0,
             0,
@@ -58943,46 +59087,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_storeu_epi8() {
+    fn test_mm512_mask_cvtepi32_storeu_epi8() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_storeu_epi8() {
+    fn test_mm256_mask_cvtepi32_storeu_epi8() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_storeu_epi8() {
+    fn test_mm_mask_cvtepi32_storeu_epi8() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi32_storeu_epi8() {
+    fn test_mm512_mask_cvtsepi32_storeu_epi8() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(i8::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi32_storeu_epi8() {
+    fn test_mm256_mask_cvtsepi32_storeu_epi8() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -58994,10 +59148,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi32_storeu_epi8() {
+    fn test_mm_mask_cvtsepi32_storeu_epi8() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -59009,19 +59165,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi32_storeu_epi8() {
+    fn test_mm512_mask_cvtusepi32_storeu_epi8() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(u8::MAX as i8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi32_storeu_epi8() {
+    fn test_mm256_mask_cvtusepi32_storeu_epi8() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -59033,10 +59193,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi32_storeu_epi8() {
+    fn test_mm_mask_cvtusepi32_storeu_epi8() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -59048,48 +59210,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_epi32() {
+    const fn test_mm512_storeu_epi32() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi32() {
+    const fn test_mm256_storeu_epi32() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
-        _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_storeu_epi32() {
+    const fn test_mm_storeu_epi32() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_si512() {
+    const fn test_mm512_loadu_si512() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50];
         let p = a.as_ptr().cast();
-        let r = _mm512_loadu_si512(black_box(p));
+        let r = unsafe { _mm512_loadu_si512(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_si512() {
+    const fn test_mm512_storeu_si512() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_si512(&mut r as *mut _, a);
+        unsafe {
+            _mm512_storeu_si512(&mut r as *mut _, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_si512() {
+    const fn test_mm512_load_si512() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -59098,21 +59268,23 @@ mod tests {
             data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50],
         };
         let p = (a.data).as_ptr().cast();
-        let r = _mm512_load_si512(black_box(p));
+        let r = unsafe { _mm512_load_si512(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_si512() {
+    const fn test_mm512_store_si512() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_store_si512(&mut r as *mut _, a);
+        unsafe {
+            _mm512_store_si512(&mut r as *mut _, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_epi32() {
+    const fn test_mm512_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -59121,13 +59293,13 @@ mod tests {
             data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_epi32(black_box(p));
+        let r = unsafe { _mm512_load_epi32(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_load_epi32() {
+    const fn test_mm256_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 8],
@@ -59136,50 +59308,56 @@ mod tests {
             data: [4, 3, 2, 5, 8, 9, 64, 50],
         };
         let p = (a.data).as_ptr();
-        let r = _mm256_load_epi32(black_box(p));
+        let r = unsafe { _mm256_load_epi32(black_box(p)) };
         let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_load_epi32() {
+    const fn test_mm_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 4],
         }
         let a = Align { data: [4, 3, 2, 5] };
         let p = (a.data).as_ptr();
-        let r = _mm_load_epi32(black_box(p));
+        let r = unsafe { _mm_load_epi32(black_box(p)) };
         let e = _mm_setr_epi32(4, 3, 2, 5);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_epi32() {
+    const fn test_mm512_store_epi32() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_store_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm512_store_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_store_epi32() {
+    const fn test_mm256_store_epi32() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
-        _mm256_store_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm256_store_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_store_epi32() {
+    const fn test_mm_store_epi32() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm_store_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm_store_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_ps() {
+    const fn test_mm512_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -59190,7 +59368,7 @@ mod tests {
             ],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_ps(black_box(p));
+        let r = unsafe { _mm512_load_ps(black_box(p)) };
         let e = _mm512_setr_ps(
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         );
@@ -59198,10 +59376,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_ps() {
+    const fn test_mm512_store_ps() {
         let a = _mm512_set1_ps(9.);
         let mut r = _mm512_undefined_ps();
-        _mm512_store_ps(&mut r as *mut _ as *mut f32, a);
+        unsafe {
+            _mm512_store_ps(&mut r as *mut _ as *mut f32, a);
+        }
         assert_eq_m512(r, a);
     }
 
@@ -62191,140 +62371,140 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_epi32() {
+    fn test_mm512_mask_expandloadu_epi32() {
         let src = _mm512_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_expandloadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi32(src, m, black_box(p)) };
         let e = _mm512_set_epi32(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_epi32() {
+    fn test_mm512_maskz_expandloadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_expandloadu_epi32(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi32(m, black_box(p)) };
         let e = _mm512_set_epi32(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi32() {
+    fn test_mm256_mask_expandloadu_epi32() {
         let src = _mm256_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi32(src, m, black_box(p)) };
         let e = _mm256_set_epi32(4, 3, 2, 42, 1, 42, 42, 42);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi32() {
+    fn test_mm256_maskz_expandloadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_epi32(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi32(m, black_box(p)) };
         let e = _mm256_set_epi32(4, 3, 2, 0, 1, 0, 0, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi32() {
+    fn test_mm_mask_expandloadu_epi32() {
         let src = _mm_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11111000;
-        let r = _mm_mask_expandloadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi32(src, m, black_box(p)) };
         let e = _mm_set_epi32(1, 42, 42, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi32() {
+    fn test_mm_maskz_expandloadu_epi32() {
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11111000;
-        let r = _mm_maskz_expandloadu_epi32(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi32(m, black_box(p)) };
         let e = _mm_set_epi32(1, 0, 0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_epi64() {
+    fn test_mm512_mask_expandloadu_epi64() {
         let src = _mm512_set1_epi64(42);
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_mask_expandloadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi64(src, m, black_box(p)) };
         let e = _mm512_set_epi64(4, 3, 2, 42, 1, 42, 42, 42);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_epi64() {
+    fn test_mm512_maskz_expandloadu_epi64() {
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_maskz_expandloadu_epi64(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi64(m, black_box(p)) };
         let e = _mm512_set_epi64(4, 3, 2, 0, 1, 0, 0, 0);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi64() {
+    fn test_mm256_mask_expandloadu_epi64() {
         let src = _mm256_set1_epi64x(42);
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi64(src, m, black_box(p)) };
         let e = _mm256_set_epi64x(1, 42, 42, 42);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi64() {
+    fn test_mm256_maskz_expandloadu_epi64() {
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_epi64(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi64(m, black_box(p)) };
         let e = _mm256_set_epi64x(1, 0, 0, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi64() {
+    fn test_mm_mask_expandloadu_epi64() {
         let src = _mm_set1_epi64x(42);
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi64(src, m, black_box(p)) };
         let e = _mm_set_epi64x(42, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi64() {
+    fn test_mm_maskz_expandloadu_epi64() {
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_epi64(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi64(m, black_box(p)) };
         let e = _mm_set_epi64x(0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_ps() {
+    fn test_mm512_mask_expandloadu_ps() {
         let src = _mm512_set1_ps(42.);
         let a = &[
             1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_expandloadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_ps(src, m, black_box(p)) };
         let e = _mm512_set_ps(
             8., 7., 6., 42., 5., 42., 42., 42., 4., 3., 42., 42., 2., 42., 1., 42.,
         );
@@ -62332,13 +62512,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_ps() {
+    fn test_mm512_maskz_expandloadu_ps() {
         let a = &[
             1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_expandloadu_ps(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_ps(m, black_box(p)) };
         let e = _mm512_set_ps(
             8., 7., 6., 0., 5., 0., 0., 0., 4., 3., 0., 0., 2., 0., 1., 0.,
         );
@@ -62346,106 +62526,106 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_ps() {
+    fn test_mm256_mask_expandloadu_ps() {
         let src = _mm256_set1_ps(42.);
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_ps(src, m, black_box(p)) };
         let e = _mm256_set_ps(4., 3., 2., 42., 1., 42., 42., 42.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_ps() {
+    fn test_mm256_maskz_expandloadu_ps() {
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_ps(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_ps(m, black_box(p)) };
         let e = _mm256_set_ps(4., 3., 2., 0., 1., 0., 0., 0.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_ps() {
+    fn test_mm_mask_expandloadu_ps() {
         let src = _mm_set1_ps(42.);
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_ps(src, m, black_box(p)) };
         let e = _mm_set_ps(1., 42., 42., 42.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_ps() {
+    fn test_mm_maskz_expandloadu_ps() {
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_ps(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_ps(m, black_box(p)) };
         let e = _mm_set_ps(1., 0., 0., 0.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_pd() {
+    fn test_mm512_mask_expandloadu_pd() {
         let src = _mm512_set1_pd(42.);
         let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_mask_expandloadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_pd(src, m, black_box(p)) };
         let e = _mm512_set_pd(4., 3., 2., 42., 1., 42., 42., 42.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_pd() {
+    fn test_mm512_maskz_expandloadu_pd() {
         let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_maskz_expandloadu_pd(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_pd(m, black_box(p)) };
         let e = _mm512_set_pd(4., 3., 2., 0., 1., 0., 0., 0.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_pd() {
+    fn test_mm256_mask_expandloadu_pd() {
         let src = _mm256_set1_pd(42.);
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_pd(src, m, black_box(p)) };
         let e = _mm256_set_pd(1., 42., 42., 42.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_pd() {
+    fn test_mm256_maskz_expandloadu_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_pd(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_pd(m, black_box(p)) };
         let e = _mm256_set_pd(1., 0., 0., 0.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_pd() {
+    fn test_mm_mask_expandloadu_pd() {
         let src = _mm_set1_pd(42.);
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_pd(src, m, black_box(p)) };
         let e = _mm_set_pd(42., 42.);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_pd() {
+    fn test_mm_maskz_expandloadu_pd() {
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_pd(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_pd(m, black_box(p)) };
         let e = _mm_set_pd(0., 0.);
         assert_eq_m128d(r, e);
     }
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 57d47c0bb0..f581711a3c 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -16932,7 +16932,6 @@ unsafe extern "C" {
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
     use crate::core_arch::x86::*;
-    use crate::mem::transmute;
     use crate::ptr::{addr_of, addr_of_mut};
     use stdarch_test::simd_test;
 
@@ -17569,72 +17568,72 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_load_ph() {
+    const fn test_mm_load_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
-        let b = _mm_load_ph(addr_of!(a).cast());
+        let b = unsafe { _mm_load_ph(addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_load_ph() {
+    const fn test_mm256_load_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
-        let b = _mm256_load_ph(addr_of!(a).cast());
+        let b = unsafe { _mm256_load_ph(addr_of!(a).cast()) };
         assert_eq_m256h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_load_ph() {
+    const fn test_mm512_load_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         );
-        let b = _mm512_load_ph(addr_of!(a).cast());
+        let b = unsafe { _mm512_load_ph(addr_of!(a).cast()) };
         assert_eq_m512h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_load_sh() {
+    const fn test_mm_load_sh() {
         let a = _mm_set_sh(1.0);
-        let b = _mm_load_sh(addr_of!(a).cast());
+        let b = unsafe { _mm_load_sh(addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_load_sh() {
+    fn test_mm_mask_load_sh() {
         let a = _mm_set_sh(1.0);
         let src = _mm_set_sh(2.);
-        let b = _mm_mask_load_sh(src, 1, addr_of!(a).cast());
+        let b = unsafe { _mm_mask_load_sh(src, 1, addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
-        let b = _mm_mask_load_sh(src, 0, addr_of!(a).cast());
+        let b = unsafe { _mm_mask_load_sh(src, 0, addr_of!(a).cast()) };
         assert_eq_m128h(src, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_load_sh() {
+    fn test_mm_maskz_load_sh() {
         let a = _mm_set_sh(1.0);
-        let b = _mm_maskz_load_sh(1, addr_of!(a).cast());
+        let b = unsafe { _mm_maskz_load_sh(1, addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
-        let b = _mm_maskz_load_sh(0, addr_of!(a).cast());
+        let b = unsafe { _mm_maskz_load_sh(0, addr_of!(a).cast()) };
         assert_eq_m128h(_mm_setzero_ph(), b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_loadu_ph() {
+    const fn test_mm_loadu_ph() {
         let array = [1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
-        let r = _mm_loadu_ph(array.as_ptr());
+        let r = unsafe { _mm_loadu_ph(array.as_ptr()) };
         let e = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_loadu_ph() {
+    const fn test_mm256_loadu_ph() {
         let array = [
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ];
-        let r = _mm256_loadu_ph(array.as_ptr());
+        let r = unsafe { _mm256_loadu_ph(array.as_ptr()) };
         let e = _mm256_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17642,13 +17641,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_loadu_ph() {
+    const fn test_mm512_loadu_ph() {
         let array = [
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         ];
-        let r = _mm512_loadu_ph(array.as_ptr());
+        let r = unsafe { _mm512_loadu_ph(array.as_ptr()) };
         let e = _mm512_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17686,81 +17685,99 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_store_ph() {
+    const fn test_mm_store_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let mut b = _mm_setzero_ph();
-        _mm_store_ph(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm_store_ph(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_store_ph() {
+    const fn test_mm256_store_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let mut b = _mm256_setzero_ph();
-        _mm256_store_ph(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm256_store_ph(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m256h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_store_ph() {
+    const fn test_mm512_store_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         );
         let mut b = _mm512_setzero_ph();
-        _mm512_store_ph(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm512_store_ph(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m512h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_store_sh() {
+    const fn test_mm_store_sh() {
         let a = _mm_set_sh(1.0);
         let mut b = _mm_setzero_ph();
-        _mm_store_sh(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm_store_sh(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_store_sh() {
+    fn test_mm_mask_store_sh() {
         let a = _mm_set_sh(1.0);
         let mut b = _mm_setzero_ph();
-        _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a);
+        unsafe {
+            _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a);
+        }
         assert_eq_m128h(_mm_setzero_ph(), b);
-        _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a);
+        unsafe {
+            _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a);
+        }
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_storeu_ph() {
+    const fn test_mm_storeu_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let mut array = [0.0; 8];
-        _mm_storeu_ph(array.as_mut_ptr(), a);
-        assert_eq_m128h(a, _mm_loadu_ph(array.as_ptr()));
+        unsafe {
+            _mm_storeu_ph(array.as_mut_ptr(), a);
+        }
+        assert_eq_m128h(a, unsafe { _mm_loadu_ph(array.as_ptr()) });
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_storeu_ph() {
+    const fn test_mm256_storeu_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let mut array = [0.0; 16];
-        _mm256_storeu_ph(array.as_mut_ptr(), a);
-        assert_eq_m256h(a, _mm256_loadu_ph(array.as_ptr()));
+        unsafe {
+            _mm256_storeu_ph(array.as_mut_ptr(), a);
+        }
+        assert_eq_m256h(a, unsafe { _mm256_loadu_ph(array.as_ptr()) });
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_storeu_ph() {
+    const fn test_mm512_storeu_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         );
         let mut array = [0.0; 32];
-        _mm512_storeu_ph(array.as_mut_ptr(), a);
-        assert_eq_m512h(a, _mm512_loadu_ph(array.as_ptr()));
+        unsafe {
+            _mm512_storeu_ph(array.as_mut_ptr(), a);
+        }
+        assert_eq_m512h(a, unsafe { _mm512_loadu_ph(array.as_ptr()) });
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
diff --git a/crates/core_arch/src/x86/avx512vbmi2.rs b/crates/core_arch/src/x86/avx512vbmi2.rs
index 26cef5814e..78a50b90c8 100644
--- a/crates/core_arch/src/x86/avx512vbmi2.rs
+++ b/crates/core_arch/src/x86/avx512vbmi2.rs
@@ -3932,7 +3932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_expandloadu_epi16() {
+    fn test_mm512_mask_expandloadu_epi16() {
         let src = _mm512_set1_epi16(42);
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -3940,7 +3940,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm512_mask_expandloadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi16(src, m, black_box(p)) };
         let e = _mm512_set_epi16(
             16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42,
             42, 42, 42, 42, 42, 4, 3, 2, 1,
@@ -3949,14 +3949,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_expandloadu_epi16() {
+    fn test_mm512_maskz_expandloadu_epi16() {
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm512_maskz_expandloadu_epi16(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi16(m, black_box(p)) };
         let e = _mm512_set_epi16(
             16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0,
             0, 4, 3, 2, 1,
@@ -3965,49 +3965,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi16() {
+    fn test_mm256_mask_expandloadu_epi16() {
         let src = _mm256_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_mask_expandloadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi16(src, m, black_box(p)) };
         let e = _mm256_set_epi16(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi16() {
+    fn test_mm256_maskz_expandloadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_maskz_expandloadu_epi16(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi16(m, black_box(p)) };
         let e = _mm256_set_epi16(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi16() {
+    fn test_mm_mask_expandloadu_epi16() {
         let src = _mm_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi16(src, m, black_box(p)) };
         let e = _mm_set_epi16(4, 3, 2, 42, 1, 42, 42, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi16() {
+    fn test_mm_maskz_expandloadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_epi16(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi16(m, black_box(p)) };
         let e = _mm_set_epi16(4, 3, 2, 0, 1, 0, 0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_expandloadu_epi8() {
+    fn test_mm512_mask_expandloadu_epi8() {
         let src = _mm512_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -4016,7 +4016,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101;
-        let r = _mm512_mask_expandloadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi8(src, m, black_box(p)) };
         let e = _mm512_set_epi8(
             32, 31, 30, 42, 29, 42, 42, 42, 28, 27, 42, 42, 26, 42, 25, 42, 24, 23, 22, 21, 42, 42,
             42, 42, 42, 42, 42, 42, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 42, 42, 42, 42,
@@ -4026,7 +4026,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_expandloadu_epi8() {
+    fn test_mm512_maskz_expandloadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
@@ -4034,7 +4034,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101;
-        let r = _mm512_maskz_expandloadu_epi8(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi8(m, black_box(p)) };
         let e = _mm512_set_epi8(
             32, 31, 30, 0, 29, 0, 0, 0, 28, 27, 0, 0, 26, 0, 25, 0, 24, 23, 22, 21, 0, 0, 0, 0, 0,
             0, 0, 0, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0,
@@ -4044,7 +4044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi8() {
+    fn test_mm256_mask_expandloadu_epi8() {
         let src = _mm256_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -4052,7 +4052,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm256_mask_expandloadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi8(src, m, black_box(p)) };
         let e = _mm256_set_epi8(
             16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42,
             42, 42, 42, 42, 42, 4, 3, 2, 1,
@@ -4061,14 +4061,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi8() {
+    fn test_mm256_maskz_expandloadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm256_maskz_expandloadu_epi8(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi8(m, black_box(p)) };
         let e = _mm256_set_epi8(
             16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0,
             0, 4, 3, 2, 1,
@@ -4077,36 +4077,44 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi8() {
+    fn test_mm_mask_expandloadu_epi8() {
         let src = _mm_set1_epi8(42);
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_mask_expandloadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi8(src, m, black_box(p)) };
         let e = _mm_set_epi8(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi8() {
+    fn test_mm_maskz_expandloadu_epi8() {
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_maskz_expandloadu_epi8(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi8(m, black_box(p)) };
         let e = _mm_set_epi8(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_compressstoreu_epi16() {
+    fn test_mm512_mask_compressstoreu_epi16() {
         let a = _mm512_set_epi16(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
             10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
         );
         let mut r = [0_i16; 32];
-        _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i16; 32]);
-        _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi16(
+                r.as_mut_ptr(),
+                0b11110000_11001010_11111111_00000000,
+                a,
+            );
+        }
         assert_eq!(
             &r,
             &[
@@ -4117,40 +4125,52 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi16() {
+    fn test_mm256_mask_compressstoreu_epi16() {
         let a = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let mut r = [0_i16; 16];
-        _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i16; 16]);
-        _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi16() {
+    fn test_mm_mask_compressstoreu_epi16() {
         let a = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1);
         let mut r = [0_i16; 8];
-        _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i16; 8]);
-        _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a);
+        }
         assert_eq!(&r, &[5, 6, 7, 8, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_compressstoreu_epi8() {
+    fn test_mm512_mask_compressstoreu_epi8() {
         let a = _mm512_set_epi8(
             64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43,
             42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21,
             20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
         );
         let mut r = [0_i8; 64];
-        _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i8; 64]);
-        _mm512_mask_compressstoreu_epi8(
-            r.as_mut_ptr(),
-            0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_compressstoreu_epi8(
+                r.as_mut_ptr(),
+                0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111,
+                a,
+            );
+        }
         assert_eq!(
             &r,
             &[
@@ -4162,15 +4182,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi8() {
+    fn test_mm256_mask_compressstoreu_epi8() {
         let a = _mm256_set_epi8(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
             10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
         );
         let mut r = [0_i8; 32];
-        _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i8; 32]);
-        _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi8(
+                r.as_mut_ptr(),
+                0b11110000_11001010_11111111_00000000,
+                a,
+            );
+        }
         assert_eq!(
             &r,
             &[
@@ -4181,12 +4209,16 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi8() {
+    fn test_mm_mask_compressstoreu_epi8() {
         let a = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let mut r = [0_i8; 16];
-        _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i8; 16]);
-        _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]);
     }
 }
diff --git a/crates/core_arch/src/x86/avxneconvert.rs b/crates/core_arch/src/x86/avxneconvert.rs
index a53d6d97e8..91b6be2b09 100644
--- a/crates/core_arch/src/x86/avxneconvert.rs
+++ b/crates/core_arch/src/x86/avxneconvert.rs
@@ -242,127 +242,127 @@ mod tests {
     const BF16_EIGHT: u16 = 0b0_10000010_0000000;
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_bcstnebf16_ps() {
+    fn test_mm_bcstnebf16_ps() {
         let a = bf16::from_bits(BF16_ONE);
-        let r = _mm_bcstnebf16_ps(addr_of!(a));
+        let r = unsafe { _mm_bcstnebf16_ps(addr_of!(a)) };
         let e = _mm_set_ps(1., 1., 1., 1.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_bcstnebf16_ps() {
+    fn test_mm256_bcstnebf16_ps() {
         let a = bf16::from_bits(BF16_ONE);
-        let r = _mm256_bcstnebf16_ps(addr_of!(a));
+        let r = unsafe { _mm256_bcstnebf16_ps(addr_of!(a)) };
         let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_bcstnesh_ps() {
+    fn test_mm_bcstnesh_ps() {
         let a = 1.0_f16;
-        let r = _mm_bcstnesh_ps(addr_of!(a));
+        let r = unsafe { _mm_bcstnesh_ps(addr_of!(a)) };
         let e = _mm_set_ps(1., 1., 1., 1.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_bcstnesh_ps() {
+    fn test_mm256_bcstnesh_ps() {
         let a = 1.0_f16;
-        let r = _mm256_bcstnesh_ps(addr_of!(a));
+        let r = unsafe { _mm256_bcstnesh_ps(addr_of!(a)) };
         let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneebf16_ps() {
+    fn test_mm_cvtneebf16_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm_cvtneebf16_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneebf16_ps(addr_of!(a)) };
         let e = _mm_setr_ps(1., 3., 5., 7.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneebf16_ps() {
+    fn test_mm256_cvtneebf16_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm256_cvtneebf16_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneebf16_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(1., 3., 5., 7., 1., 3., 5., 7.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneeph_ps() {
+    fn test_mm_cvtneeph_ps() {
         let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]);
-        let r = _mm_cvtneeph_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneeph_ps(addr_of!(a)) };
         let e = _mm_setr_ps(1., 3., 5., 7.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneeph_ps() {
+    fn test_mm256_cvtneeph_ps() {
         let a = __m256h([
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ]);
-        let r = _mm256_cvtneeph_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneeph_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(1., 3., 5., 7., 9., 11., 13., 15.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneobf16_ps() {
+    fn test_mm_cvtneobf16_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm_cvtneobf16_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneobf16_ps(addr_of!(a)) };
         let e = _mm_setr_ps(2., 4., 6., 8.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneobf16_ps() {
+    fn test_mm256_cvtneobf16_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm256_cvtneobf16_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneobf16_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(2., 4., 6., 8., 2., 4., 6., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneoph_ps() {
+    fn test_mm_cvtneoph_ps() {
         let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]);
-        let r = _mm_cvtneoph_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneoph_ps(addr_of!(a)) };
         let e = _mm_setr_ps(2., 4., 6., 8.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneoph_ps() {
+    fn test_mm256_cvtneoph_ps() {
         let a = __m256h([
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ]);
-        let r = _mm256_cvtneoph_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneoph_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(2., 4., 6., 8., 10., 12., 14., 16.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneps_avx_pbh() {
+    fn test_mm_cvtneps_avx_pbh() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
-        let r: u16x4 = transmute_copy(&_mm_cvtneps_avx_pbh(a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_avx_pbh(a)) };
         let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneps_avx_pbh() {
+    fn test_mm256_cvtneps_avx_pbh() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
-        let r: u16x8 = transmute(_mm256_cvtneps_avx_pbh(a));
+        let r: u16x8 = _mm256_cvtneps_avx_pbh(a).as_u16x8();
         let e = u16x8::new(
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         );
diff --git a/crates/core_arch/src/x86/f16c.rs b/crates/core_arch/src/x86/f16c.rs
index 0a26a9ff8d..a0bb992bb9 100644
--- a/crates/core_arch/src/x86/f16c.rs
+++ b/crates/core_arch/src/x86/f16c.rs
@@ -106,7 +106,7 @@ pub fn _mm256_cvtps_ph<const IMM_ROUNDING: i32>(a: __m256) -> __m128i {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
-    use crate::{core_arch::x86::*, mem::transmute};
+    use crate::core_arch::x86::*;
     use stdarch_test::simd_test;
 
     const F16_ONE: i16 = 0x3c00;
diff --git a/crates/core_arch/src/x86/fxsr.rs b/crates/core_arch/src/x86/fxsr.rs
index 71fd52ca14..08619efe7c 100644
--- a/crates/core_arch/src/x86/fxsr.rs
+++ b/crates/core_arch/src/x86/fxsr.rs
@@ -77,12 +77,14 @@ mod tests {
 
     #[simd_test(enable = "fxsr")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_fxsave() {
+    fn test_fxsave() {
         let mut a = FxsaveArea::new();
         let mut b = FxsaveArea::new();
 
-        fxsr::_fxsave(a.ptr());
-        fxsr::_fxrstor(a.ptr());
-        fxsr::_fxsave(b.ptr());
+        unsafe {
+            fxsr::_fxsave(a.ptr());
+            fxsr::_fxrstor(a.ptr());
+            fxsr::_fxsave(b.ptr());
+        }
     }
 }
diff --git a/crates/core_arch/src/x86/gfni.rs b/crates/core_arch/src/x86/gfni.rs
index 681b8ae330..e9ee27a7b8 100644
--- a/crates/core_arch/src/x86/gfni.rs
+++ b/crates/core_arch/src/x86/gfni.rs
@@ -898,25 +898,25 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512f")]
-    unsafe fn test_mm512_gf2p8mul_epi8() {
+    fn test_mm512_gf2p8mul_epi8() {
         let (left, right, expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&left, i);
-            let right = load_m512i_word(&right, i);
-            let expected = load_m512i_word(&expected, i);
+            let left = unsafe { load_m512i_word(&left, i) };
+            let right = unsafe { load_m512i_word(&right, i) };
+            let expected = unsafe { load_m512i_word(&expected, i) };
             let result = _mm512_gf2p8mul_epi8(left, right);
             assert_eq_m512i(result, expected);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_maskz_gf2p8mul_epi8() {
+    fn test_mm512_maskz_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&left, i);
-            let right = load_m512i_word(&right, i);
+            let left = unsafe { load_m512i_word(&left, i) };
+            let right = unsafe { load_m512i_word(&right, i) };
             let result_zero = _mm512_maskz_gf2p8mul_epi8(0, left, right);
             assert_eq_m512i(result_zero, _mm512_setzero_si512());
             let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00;
@@ -930,12 +930,12 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_mask_gf2p8mul_epi8() {
+    fn test_mm512_mask_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&left, i);
-            let right = load_m512i_word(&right, i);
+            let left = unsafe { load_m512i_word(&left, i) };
+            let right = unsafe { load_m512i_word(&right, i) };
             let result_left = _mm512_mask_gf2p8mul_epi8(left, 0, left, right);
             assert_eq_m512i(result_left, left);
             let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00;
@@ -948,25 +948,25 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx")]
-    unsafe fn test_mm256_gf2p8mul_epi8() {
+    fn test_mm256_gf2p8mul_epi8() {
         let (left, right, expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&left, i);
-            let right = load_m256i_word(&right, i);
-            let expected = load_m256i_word(&expected, i);
+            let left = unsafe { load_m256i_word(&left, i) };
+            let right = unsafe { load_m256i_word(&right, i) };
+            let expected = unsafe { load_m256i_word(&expected, i) };
             let result = _mm256_gf2p8mul_epi8(left, right);
             assert_eq_m256i(result, expected);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_gf2p8mul_epi8() {
+    fn test_mm256_maskz_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&left, i);
-            let right = load_m256i_word(&right, i);
+            let left = unsafe { load_m256i_word(&left, i) };
+            let right = unsafe { load_m256i_word(&right, i) };
             let result_zero = _mm256_maskz_gf2p8mul_epi8(0, left, right);
             assert_eq_m256i(result_zero, _mm256_setzero_si256());
             let mask_bytes: __mmask32 = 0x0F_F0_FF_00;
@@ -980,12 +980,12 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_gf2p8mul_epi8() {
+    fn test_mm256_mask_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&left, i);
-            let right = load_m256i_word(&right, i);
+            let left = unsafe { load_m256i_word(&left, i) };
+            let right = unsafe { load_m256i_word(&right, i) };
             let result_left = _mm256_mask_gf2p8mul_epi8(left, 0, left, right);
             assert_eq_m256i(result_left, left);
             let mask_bytes: __mmask32 = 0x0F_F0_FF_00;
@@ -998,25 +998,25 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni")]
-    unsafe fn test_mm_gf2p8mul_epi8() {
+    fn test_mm_gf2p8mul_epi8() {
         let (left, right, expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&left, i);
-            let right = load_m128i_word(&right, i);
-            let expected = load_m128i_word(&expected, i);
+            let left = unsafe { load_m128i_word(&left, i) };
+            let right = unsafe { load_m128i_word(&right, i) };
+            let expected = unsafe { load_m128i_word(&expected, i) };
             let result = _mm_gf2p8mul_epi8(left, right);
             assert_eq_m128i(result, expected);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_gf2p8mul_epi8() {
+    fn test_mm_maskz_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&left, i);
-            let right = load_m128i_word(&right, i);
+            let left = unsafe { load_m128i_word(&left, i) };
+            let right = unsafe { load_m128i_word(&right, i) };
             let result_zero = _mm_maskz_gf2p8mul_epi8(0, left, right);
             assert_eq_m128i(result_zero, _mm_setzero_si128());
             let mask_bytes: __mmask16 = 0x0F_F0;
@@ -1030,12 +1030,12 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_gf2p8mul_epi8() {
+    fn test_mm_mask_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&left, i);
-            let right = load_m128i_word(&right, i);
+            let left = unsafe { load_m128i_word(&left, i) };
+            let right = unsafe { load_m128i_word(&right, i) };
             let result_left = _mm_mask_gf2p8mul_epi8(left, 0, left, right);
             assert_eq_m128i(result_left, left);
             let mask_bytes: __mmask16 = 0x0F_F0;
@@ -1048,7 +1048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512f")]
-    unsafe fn test_mm512_gf2p8affine_epi64_epi8() {
+    fn test_mm512_gf2p8affine_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         let constant: i64 = 0;
@@ -1061,20 +1061,20 @@ mod tests {
         let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let data = load_m512i_word(&bytes, i);
+            let data = unsafe { load_m512i_word(&bytes, i) };
             let result = _mm512_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m512i(result, data);
             let result = _mm512_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m512i(result, constant_reference);
-            let data = load_m512i_word(&more_bytes, i);
+            let data = unsafe { load_m512i_word(&more_bytes, i) };
             let result = _mm512_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m512i(result, data);
             let result = _mm512_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m512i(result, constant_reference);
 
-            let matrix = load_m512i_word(&matrices, i);
-            let vector = load_m512i_word(&vectors, i);
-            let reference = load_m512i_word(&references, i);
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
+            let vector = unsafe { load_m512i_word(&vectors, i) };
+            let reference = unsafe { load_m512i_word(&references, i) };
 
             let result = _mm512_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(vector, matrix);
             assert_eq_m512i(result, reference);
@@ -1082,13 +1082,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_maskz_gf2p8affine_epi64_epi8() {
+    fn test_mm512_maskz_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let matrix = load_m512i_word(&matrices, i);
-            let vector = load_m512i_word(&vectors, i);
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
+            let vector = unsafe { load_m512i_word(&vectors, i) };
             let result_zero =
                 _mm512_maskz_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m512i(result_zero, _mm512_setzero_si512());
@@ -1104,13 +1104,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_mask_gf2p8affine_epi64_epi8() {
+    fn test_mm512_mask_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&vectors, i);
-            let right = load_m512i_word(&matrices, i);
+            let left = unsafe { load_m512i_word(&vectors, i) };
+            let right = unsafe { load_m512i_word(&matrices, i) };
             let result_left =
                 _mm512_mask_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m512i(result_left, left);
@@ -1125,7 +1125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx")]
-    unsafe fn test_mm256_gf2p8affine_epi64_epi8() {
+    fn test_mm256_gf2p8affine_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         let constant: i64 = 0;
@@ -1138,20 +1138,20 @@ mod tests {
         let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let data = load_m256i_word(&bytes, i);
+            let data = unsafe { load_m256i_word(&bytes, i) };
             let result = _mm256_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m256i(result, data);
             let result = _mm256_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m256i(result, constant_reference);
-            let data = load_m256i_word(&more_bytes, i);
+            let data = unsafe { load_m256i_word(&more_bytes, i) };
             let result = _mm256_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m256i(result, data);
             let result = _mm256_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m256i(result, constant_reference);
 
-            let matrix = load_m256i_word(&matrices, i);
-            let vector = load_m256i_word(&vectors, i);
-            let reference = load_m256i_word(&references, i);
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
+            let vector = unsafe { load_m256i_word(&vectors, i) };
+            let reference = unsafe { load_m256i_word(&references, i) };
 
             let result = _mm256_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(vector, matrix);
             assert_eq_m256i(result, reference);
@@ -1159,13 +1159,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_gf2p8affine_epi64_epi8() {
+    fn test_mm256_maskz_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let matrix = load_m256i_word(&matrices, i);
-            let vector = load_m256i_word(&vectors, i);
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
+            let vector = unsafe { load_m256i_word(&vectors, i) };
             let result_zero =
                 _mm256_maskz_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m256i(result_zero, _mm256_setzero_si256());
@@ -1181,13 +1181,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_gf2p8affine_epi64_epi8() {
+    fn test_mm256_mask_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&vectors, i);
-            let right = load_m256i_word(&matrices, i);
+            let left = unsafe { load_m256i_word(&vectors, i) };
+            let right = unsafe { load_m256i_word(&matrices, i) };
             let result_left =
                 _mm256_mask_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m256i(result_left, left);
@@ -1202,7 +1202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni")]
-    unsafe fn test_mm_gf2p8affine_epi64_epi8() {
+    fn test_mm_gf2p8affine_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         let constant: i64 = 0;
@@ -1215,20 +1215,20 @@ mod tests {
         let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let data = load_m128i_word(&bytes, i);
+            let data = unsafe { load_m128i_word(&bytes, i) };
             let result = _mm_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m128i(result, data);
             let result = _mm_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m128i(result, constant_reference);
-            let data = load_m128i_word(&more_bytes, i);
+            let data = unsafe { load_m128i_word(&more_bytes, i) };
             let result = _mm_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m128i(result, data);
             let result = _mm_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m128i(result, constant_reference);
 
-            let matrix = load_m128i_word(&matrices, i);
-            let vector = load_m128i_word(&vectors, i);
-            let reference = load_m128i_word(&references, i);
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
+            let vector = unsafe { load_m128i_word(&vectors, i) };
+            let reference = unsafe { load_m128i_word(&references, i) };
 
             let result = _mm_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(vector, matrix);
             assert_eq_m128i(result, reference);
@@ -1236,13 +1236,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_gf2p8affine_epi64_epi8() {
+    fn test_mm_maskz_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let matrix = load_m128i_word(&matrices, i);
-            let vector = load_m128i_word(&vectors, i);
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
+            let vector = unsafe { load_m128i_word(&vectors, i) };
             let result_zero = _mm_maskz_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m128i(result_zero, _mm_setzero_si128());
             let mask_bytes: __mmask16 = 0x0F_F0;
@@ -1257,13 +1257,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_gf2p8affine_epi64_epi8() {
+    fn test_mm_mask_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&vectors, i);
-            let right = load_m128i_word(&matrices, i);
+            let left = unsafe { load_m128i_word(&vectors, i) };
+            let right = unsafe { load_m128i_word(&matrices, i) };
             let result_left =
                 _mm_mask_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m128i(result_left, left);
@@ -1278,7 +1278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512f")]
-    unsafe fn test_mm512_gf2p8affineinv_epi64_epi8() {
+    fn test_mm512_gf2p8affineinv_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         const CONSTANT_BYTE: i32 = 0x63;
@@ -1288,8 +1288,8 @@ mod tests {
         let (inputs, results) = generate_inv_tests_data();
 
         for i in 0..NUM_BYTES_WORDS_512 {
-            let input = load_m512i_word(&inputs, i);
-            let reference = load_m512i_word(&results, i);
+            let input = unsafe { load_m512i_word(&inputs, i) };
+            let reference = unsafe { load_m512i_word(&results, i) };
             let result = _mm512_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(input, identity);
             let remultiplied = _mm512_gf2p8mul_epi8(result, input);
             assert_eq_m512i(remultiplied, reference);
@@ -1300,8 +1300,8 @@ mod tests {
             generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let vector = load_m512i_word(&vectors, i);
-            let matrix = load_m512i_word(&matrices, i);
+            let vector = unsafe { load_m512i_word(&vectors, i) };
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
 
             let inv_vec = _mm512_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(vector, identity);
             let reference = _mm512_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(inv_vec, matrix);
@@ -1314,21 +1314,21 @@ mod tests {
         let sbox_matrix = _mm512_set1_epi64(AES_S_BOX_MATRIX);
 
         for i in 0..NUM_BYTES_WORDS_512 {
-            let reference = load_m512i_word(&AES_S_BOX, i);
-            let input = load_m512i_word(&inputs, i);
+            let reference = unsafe { load_m512i_word(&AES_S_BOX, i) };
+            let input = unsafe { load_m512i_word(&inputs, i) };
             let result = _mm512_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(input, sbox_matrix);
             assert_eq_m512i(result, reference);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() {
+    fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let matrix = load_m512i_word(&matrices, i);
-            let vector = load_m512i_word(&vectors, i);
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
+            let vector = unsafe { load_m512i_word(&vectors, i) };
             let result_zero =
                 _mm512_maskz_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m512i(result_zero, _mm512_setzero_si512());
@@ -1344,13 +1344,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_mask_gf2p8affineinv_epi64_epi8() {
+    fn test_mm512_mask_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&vectors, i);
-            let right = load_m512i_word(&matrices, i);
+            let left = unsafe { load_m512i_word(&vectors, i) };
+            let right = unsafe { load_m512i_word(&matrices, i) };
             let result_left =
                 _mm512_mask_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m512i(result_left, left);
@@ -1366,7 +1366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx")]
-    unsafe fn test_mm256_gf2p8affineinv_epi64_epi8() {
+    fn test_mm256_gf2p8affineinv_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         const CONSTANT_BYTE: i32 = 0x63;
@@ -1376,8 +1376,8 @@ mod tests {
         let (inputs, results) = generate_inv_tests_data();
 
         for i in 0..NUM_BYTES_WORDS_256 {
-            let input = load_m256i_word(&inputs, i);
-            let reference = load_m256i_word(&results, i);
+            let input = unsafe { load_m256i_word(&inputs, i) };
+            let reference = unsafe { load_m256i_word(&results, i) };
             let result = _mm256_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(input, identity);
             let remultiplied = _mm256_gf2p8mul_epi8(result, input);
             assert_eq_m256i(remultiplied, reference);
@@ -1388,8 +1388,8 @@ mod tests {
             generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let vector = load_m256i_word(&vectors, i);
-            let matrix = load_m256i_word(&matrices, i);
+            let vector = unsafe { load_m256i_word(&vectors, i) };
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
 
             let inv_vec = _mm256_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(vector, identity);
             let reference = _mm256_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(inv_vec, matrix);
@@ -1402,21 +1402,21 @@ mod tests {
         let sbox_matrix = _mm256_set1_epi64x(AES_S_BOX_MATRIX);
 
         for i in 0..NUM_BYTES_WORDS_256 {
-            let reference = load_m256i_word(&AES_S_BOX, i);
-            let input = load_m256i_word(&inputs, i);
+            let reference = unsafe { load_m256i_word(&AES_S_BOX, i) };
+            let input = unsafe { load_m256i_word(&inputs, i) };
             let result = _mm256_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(input, sbox_matrix);
             assert_eq_m256i(result, reference);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() {
+    fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let matrix = load_m256i_word(&matrices, i);
-            let vector = load_m256i_word(&vectors, i);
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
+            let vector = unsafe { load_m256i_word(&vectors, i) };
             let result_zero =
                 _mm256_maskz_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m256i(result_zero, _mm256_setzero_si256());
@@ -1432,13 +1432,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_gf2p8affineinv_epi64_epi8() {
+    fn test_mm256_mask_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&vectors, i);
-            let right = load_m256i_word(&matrices, i);
+            let left = unsafe { load_m256i_word(&vectors, i) };
+            let right = unsafe { load_m256i_word(&matrices, i) };
             let result_left =
                 _mm256_mask_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m256i(result_left, left);
@@ -1454,7 +1454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni")]
-    unsafe fn test_mm_gf2p8affineinv_epi64_epi8() {
+    fn test_mm_gf2p8affineinv_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         const CONSTANT_BYTE: i32 = 0x63;
@@ -1464,8 +1464,8 @@ mod tests {
         let (inputs, results) = generate_inv_tests_data();
 
         for i in 0..NUM_BYTES_WORDS_128 {
-            let input = load_m128i_word(&inputs, i);
-            let reference = load_m128i_word(&results, i);
+            let input = unsafe { load_m128i_word(&inputs, i) };
+            let reference = unsafe { load_m128i_word(&results, i) };
             let result = _mm_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(input, identity);
             let remultiplied = _mm_gf2p8mul_epi8(result, input);
             assert_eq_m128i(remultiplied, reference);
@@ -1476,8 +1476,8 @@ mod tests {
             generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let vector = load_m128i_word(&vectors, i);
-            let matrix = load_m128i_word(&matrices, i);
+            let vector = unsafe { load_m128i_word(&vectors, i) };
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
 
             let inv_vec = _mm_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(vector, identity);
             let reference = _mm_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(inv_vec, matrix);
@@ -1490,21 +1490,21 @@ mod tests {
         let sbox_matrix = _mm_set1_epi64x(AES_S_BOX_MATRIX);
 
         for i in 0..NUM_BYTES_WORDS_128 {
-            let reference = load_m128i_word(&AES_S_BOX, i);
-            let input = load_m128i_word(&inputs, i);
+            let reference = unsafe { load_m128i_word(&AES_S_BOX, i) };
+            let input = unsafe { load_m128i_word(&inputs, i) };
             let result = _mm_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(input, sbox_matrix);
             assert_eq_m128i(result, reference);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_gf2p8affineinv_epi64_epi8() {
+    fn test_mm_maskz_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let matrix = load_m128i_word(&matrices, i);
-            let vector = load_m128i_word(&vectors, i);
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
+            let vector = unsafe { load_m128i_word(&vectors, i) };
             let result_zero =
                 _mm_maskz_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m128i(result_zero, _mm_setzero_si128());
@@ -1520,13 +1520,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_gf2p8affineinv_epi64_epi8() {
+    fn test_mm_mask_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&vectors, i);
-            let right = load_m128i_word(&matrices, i);
+            let left = unsafe { load_m128i_word(&vectors, i) };
+            let right = unsafe { load_m128i_word(&matrices, i) };
             let result_left =
                 _mm_mask_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m128i(result_left, left);
diff --git a/crates/core_arch/src/x86/kl.rs b/crates/core_arch/src/x86/kl.rs
index 26e5a46c62..7cb52847f5 100644
--- a/crates/core_arch/src/x86/kl.rs
+++ b/crates/core_arch/src/x86/kl.rs
@@ -352,45 +352,47 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[target_feature(enable = "kl")]
-    unsafe fn encodekey128() -> [u8; 48] {
+    fn encodekey128() -> [u8; 48] {
         let mut handle = [0; 48];
-        let _ = _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr());
+        let _ = unsafe { _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr()) };
         handle
     }
 
     #[target_feature(enable = "kl")]
-    unsafe fn encodekey256() -> [u8; 64] {
+    fn encodekey256() -> [u8; 64] {
         let mut handle = [0; 64];
-        let _ = _mm_encodekey256_u32(
-            0,
-            _mm_setzero_si128(),
-            _mm_setzero_si128(),
-            handle.as_mut_ptr(),
-        );
+        let _ = unsafe {
+            _mm_encodekey256_u32(
+                0,
+                _mm_setzero_si128(),
+                _mm_setzero_si128(),
+                handle.as_mut_ptr(),
+            )
+        };
         handle
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_encodekey128_u32() {
+    fn test_mm_encodekey128_u32() {
         encodekey128();
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_encodekey256_u32() {
+    fn test_mm_encodekey256_u32() {
         encodekey256();
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesenc128kl_u8() {
+    fn test_mm_aesenc128kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -398,16 +400,16 @@ mod tests {
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesdec128kl_u8() {
+    fn test_mm_aesdec128kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -415,16 +417,16 @@ mod tests {
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesenc256kl_u8() {
+    fn test_mm_aesenc256kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -432,16 +434,16 @@ mod tests {
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesdec256kl_u8() {
+    fn test_mm_aesdec256kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -449,16 +451,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesencwide128kl_u8() {
+    fn test_mm_aesencwide128kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
@@ -468,16 +474,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesdecwide128kl_u8() {
+    fn test_mm_aesdecwide128kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
@@ -487,16 +497,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesencwide256kl_u8() {
+    fn test_mm_aesencwide256kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
@@ -506,16 +520,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesdecwide256kl_u8() {
+    fn test_mm_aesdecwide256kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
diff --git a/crates/core_arch/src/x86/rtm.rs b/crates/core_arch/src/x86/rtm.rs
index b37e7571eb..c88bd6592d 100644
--- a/crates/core_arch/src/x86/rtm.rs
+++ b/crates/core_arch/src/x86/rtm.rs
@@ -120,13 +120,15 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xbegin() {
+    fn test_xbegin() {
         let mut x = 0;
         for _ in 0..10 {
-            let code = _xbegin();
+            let code = unsafe { _xbegin() };
             if code == _XBEGIN_STARTED {
                 x += 1;
-                _xend();
+                unsafe {
+                    _xend();
+                }
                 assert_eq!(x, 1);
                 break;
             }
@@ -135,19 +137,23 @@ mod tests {
     }
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xabort() {
+    fn test_xabort() {
         const ABORT_CODE: u32 = 42;
         // aborting outside a transactional region does nothing
-        _xabort::<ABORT_CODE>();
+        unsafe {
+            _xabort::<ABORT_CODE>();
+        }
 
         for _ in 0..10 {
             let mut x = 0;
-            let code = rtm::_xbegin();
+            let code = unsafe { _xbegin() };
             if code == _XBEGIN_STARTED {
                 x += 1;
-                rtm::_xabort::<ABORT_CODE>();
+                unsafe {
+                    _xabort::<ABORT_CODE>();
+                }
             } else if code & _XABORT_EXPLICIT != 0 {
-                let test_abort_code = rtm::_xabort_code(code);
+                let test_abort_code = _xabort_code(code);
                 assert_eq!(test_abort_code, ABORT_CODE);
             }
             assert_eq!(x, 0);
@@ -155,14 +161,16 @@ mod tests {
     }
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xtest() {
-        assert_eq!(_xtest(), 0);
+    fn test_xtest() {
+        assert_eq!(unsafe { _xtest() }, 0);
 
         for _ in 0..10 {
-            let code = rtm::_xbegin();
+            let code = unsafe { _xbegin() };
             if code == _XBEGIN_STARTED {
-                let in_tx = _xtest();
-                rtm::_xend();
+                let in_tx = unsafe { _xtest() };
+                unsafe {
+                    _xend();
+                }
 
                 // putting the assert inside the transaction would abort the transaction on fail
                 // without any output/panic/etc
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index f167e8381d..1812721db4 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3147,21 +3147,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_load_ss() {
+    const fn test_mm_load_ss() {
         let a = 42.0f32;
-        let r = _mm_load_ss(ptr::addr_of!(a));
+        let r = unsafe { _mm_load_ss(ptr::addr_of!(a)) };
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_load1_ps() {
+    const fn test_mm_load1_ps() {
         let a = 42.0f32;
-        let r = _mm_load1_ps(ptr::addr_of!(a));
+        let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) };
         assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_load_ps() {
+    const fn test_mm_load_ps() {
         let vals = Memory {
             data: [1.0f32, 2.0, 3.0, 4.0],
         };
@@ -3169,21 +3169,21 @@ mod tests {
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_ptr();
 
-        let r = _mm_load_ps(p);
+        let r = unsafe { _mm_load_ps(p) };
         let e = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_loadu_ps() {
+    const fn test_mm_loadu_ps() {
         let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
-        let p = vals.as_ptr().add(3);
-        let r = _mm_loadu_ps(black_box(p));
+        let p = unsafe { vals.as_ptr().add(3) };
+        let r = unsafe { _mm_loadu_ps(black_box(p)) };
         assert_eq_m128(r, _mm_setr_ps(4.0, 5.0, 6.0, 7.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_loadr_ps() {
+    const fn test_mm_loadr_ps() {
         let vals = Memory {
             data: [1.0f32, 2.0, 3.0, 4.0],
         };
@@ -3191,16 +3191,18 @@ mod tests {
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_ptr();
 
-        let r = _mm_loadr_ps(p);
+        let r = unsafe { _mm_loadr_ps(p) };
         let e = _mm_setr_ps(4.0, 3.0, 2.0, 1.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_store_ss() {
+    const fn test_mm_store_ss() {
         let mut vals = [0.0f32; 8];
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-        _mm_store_ss(vals.as_mut_ptr().add(1), a);
+        unsafe {
+            _mm_store_ss(vals.as_mut_ptr().add(1), a);
+        }
 
         assert_eq!(vals[0], 0.0);
         assert_eq!(vals[1], 1.0);
@@ -3208,46 +3210,52 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_store1_ps() {
+    const fn test_mm_store1_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_mut_ptr();
 
-        _mm_store1_ps(p, *black_box(&a));
+        unsafe {
+            _mm_store1_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_store_ps() {
+    const fn test_mm_store_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_mut_ptr();
 
-        _mm_store_ps(p, *black_box(&a));
+        unsafe {
+            _mm_store_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_storer_ps() {
+    const fn test_mm_storer_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_mut_ptr();
 
-        _mm_storer_ps(p, *black_box(&a));
+        unsafe {
+            _mm_storer_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [4.0, 3.0, 2.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_storeu_ps() {
+    const fn test_mm_storeu_ps() {
         #[repr(align(16))]
         struct Memory8 {
             data: [f32; 8],
@@ -3258,9 +3266,11 @@ mod tests {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be *not* aligned to 16 bytes
-        let p = vals.data.as_mut_ptr().offset(1);
+        let p = unsafe { vals.data.as_mut_ptr().offset(1) };
 
-        _mm_storeu_ps(p, *black_box(&a));
+        unsafe {
+            _mm_storeu_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]);
     }
@@ -3315,11 +3325,13 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_ps() {
+    fn test_mm_stream_ps() {
         let a = _mm_set1_ps(7.0);
         let mut mem = Memory { data: [-1.0; 4] };
 
-        _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..4 {
             assert_eq!(mem.data[i], get_m128(a, i));
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index fc010e8467..c58e1b86a4 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -3291,9 +3291,11 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_clflush() {
+    fn test_mm_clflush() {
         let x = 0_u8;
-        _mm_clflush(ptr::addr_of!(x));
+        unsafe {
+            _mm_clflush(ptr::addr_of!(x));
+        }
     }
 
     #[simd_test(enable = "sse2")]
@@ -3725,7 +3727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sll_epi16() {
+    fn test_mm_sll_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_sll_epi16(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(
@@ -4071,7 +4073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtps_epi32() {
+    fn test_mm_cvtps_epi32() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtps_epi32(a);
         assert_eq_m128i(r, _mm_setr_epi32(1, 2, 3, 4));
@@ -4178,23 +4180,23 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadl_epi64() {
+    const fn test_mm_loadl_epi64() {
         let a = _mm_setr_epi64x(6, 5);
-        let r = _mm_loadl_epi64(ptr::addr_of!(a));
+        let r = unsafe { _mm_loadl_epi64(ptr::addr_of!(a)) };
         assert_eq_m128i(r, _mm_setr_epi64x(6, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_si128() {
+    const fn test_mm_load_si128() {
         let a = _mm_set_epi64x(5, 6);
-        let r = _mm_load_si128(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_load_si128(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(a, r);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si128() {
+    const fn test_mm_loadu_si128() {
         let a = _mm_set_epi64x(5, 6);
-        let r = _mm_loadu_si128(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si128(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(a, r);
     }
 
@@ -4202,7 +4204,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_maskmoveu_si128() {
+    fn test_mm_maskmoveu_si128() {
         let a = _mm_set1_epi8(9);
         #[rustfmt::skip]
         let mask = _mm_set_epi8(
@@ -4210,33 +4212,41 @@ mod tests {
             0, 0, 0, 0, 0, 0, 0, 0,
         );
         let mut r = _mm_set1_epi8(0);
-        _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8);
+        unsafe {
+            _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8);
+        }
         _mm_sfence();
         let e = _mm_set_epi8(0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_si128() {
+    const fn test_mm_store_si128() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_store_si128(&mut r, a);
+        unsafe {
+            _mm_store_si128(&mut r, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si128() {
+    const fn test_mm_storeu_si128() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_storeu_si128(&mut r, a);
+        unsafe {
+            _mm_storeu_si128(&mut r, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storel_epi64() {
+    const fn test_mm_storel_epi64() {
         let a = _mm_setr_epi64x(2, 9);
         let mut r = _mm_set1_epi8(0);
-        _mm_storel_epi64(&mut r, a);
+        unsafe {
+            _mm_storel_epi64(&mut r, a);
+        }
         assert_eq_m128i(r, _mm_setr_epi64x(2, 0));
     }
 
@@ -4244,10 +4254,12 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_si128() {
+    fn test_mm_stream_si128() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = _mm_undefined_si128();
-        _mm_stream_si128(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm_stream_si128(ptr::addr_of_mut!(r), a);
+        }
         _mm_sfence();
         assert_eq_m128i(r, a);
     }
@@ -4256,10 +4268,12 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_si32() {
+    fn test_mm_stream_si32() {
         let a: i32 = 7;
         let mut mem = boxed::Box::<i32>::new(-1);
-        _mm_stream_si32(ptr::addr_of_mut!(*mem), a);
+        unsafe {
+            _mm_stream_si32(ptr::addr_of_mut!(*mem), a);
+        }
         _mm_sfence();
         assert_eq!(a, *mem);
     }
@@ -4909,40 +4923,40 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_pd() {
+    const fn test_mm_load_pd() {
         let mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
         let vals = &mem.data;
         let d = vals.as_ptr();
 
-        let r = _mm_load_pd(d);
+        let r = unsafe { _mm_load_pd(d) };
         assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_sd() {
+    const fn test_mm_load_sd() {
         let a = 1.;
         let expected = _mm_setr_pd(a, 0.);
-        let r = _mm_load_sd(&a);
+        let r = unsafe { _mm_load_sd(&a) };
         assert_eq_m128d(r, expected);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadh_pd() {
+    const fn test_mm_loadh_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = 3.;
         let expected = _mm_setr_pd(_mm_cvtsd_f64(a), 3.);
-        let r = _mm_loadh_pd(a, &b);
+        let r = unsafe { _mm_loadh_pd(a, &b) };
         assert_eq_m128d(r, expected);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadl_pd() {
+    const fn test_mm_loadl_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = 3.;
         let expected = _mm_setr_pd(3., get_m128d(a, 1));
-        let r = _mm_loadl_pd(a, &b);
+        let r = unsafe { _mm_loadl_pd(a, &b) };
         assert_eq_m128d(r, expected);
     }
 
@@ -4950,7 +4964,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_pd() {
+    fn test_mm_stream_pd() {
         #[repr(align(128))]
         struct Memory {
             pub data: [f64; 2],
@@ -4958,7 +4972,9 @@ mod tests {
         let a = _mm_set1_pd(7.0);
         let mut mem = Memory { data: [-1.0; 2] };
 
-        _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..2 {
             assert_eq!(mem.data[i], get_m128d(a, i));
@@ -4966,132 +4982,154 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_sd() {
+    const fn test_mm_store_sd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
-        _mm_store_sd(&mut dest, a);
+        unsafe {
+            _mm_store_sd(&mut dest, a);
+        }
         assert_eq!(dest, _mm_cvtsd_f64(a));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_pd() {
+    const fn test_mm_store_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_store_pd(d, *black_box(&a));
+        unsafe {
+            _mm_store_pd(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 1.0);
         assert_eq!(vals[1], 2.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_pd() {
+    const fn test_mm_storeu_pd() {
         // guaranteed to be aligned to 16 bytes
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
 
         // so p is *not* aligned to 16 bytes
-        let p = vals.as_mut_ptr().offset(1);
-        _mm_storeu_pd(p, *black_box(&a));
+        unsafe {
+            let p = vals.as_mut_ptr().offset(1);
+            _mm_storeu_pd(p, *black_box(&a));
+        }
 
         assert_eq!(*vals, [0.0, 1.0, 2.0, 0.0]);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si16() {
+    const fn test_mm_storeu_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
-        _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a);
+        unsafe {
+            _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a);
+        }
         let e = _mm_setr_epi16(1, 10, 11, 12, 13, 14, 15, 16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si32() {
+    const fn test_mm_storeu_si32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = _mm_setr_epi32(5, 6, 7, 8);
-        _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a);
+        unsafe {
+            _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a);
+        }
         let e = _mm_setr_epi32(1, 6, 7, 8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si64() {
+    const fn test_mm_storeu_si64() {
         let a = _mm_setr_epi64x(1, 2);
         let mut r = _mm_setr_epi64x(3, 4);
-        _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a);
+        unsafe {
+            _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a);
+        }
         let e = _mm_setr_epi64x(1, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store1_pd() {
+    const fn test_mm_store1_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_store1_pd(d, *black_box(&a));
+        unsafe {
+            _mm_store1_pd(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 1.0);
         assert_eq!(vals[1], 1.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_pd1() {
+    const fn test_mm_store_pd1() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_store_pd1(d, *black_box(&a));
+        unsafe {
+            _mm_store_pd1(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 1.0);
         assert_eq!(vals[1], 1.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storer_pd() {
+    const fn test_mm_storer_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_storer_pd(d, *black_box(&a));
+        unsafe {
+            _mm_storer_pd(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 2.0);
         assert_eq!(vals[1], 1.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeh_pd() {
+    const fn test_mm_storeh_pd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
-        _mm_storeh_pd(&mut dest, a);
+        unsafe {
+            _mm_storeh_pd(&mut dest, a);
+        }
         assert_eq!(dest, get_m128d(a, 1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storel_pd() {
+    const fn test_mm_storel_pd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
-        _mm_storel_pd(&mut dest, a);
+        unsafe {
+            _mm_storel_pd(&mut dest, a);
+        }
         assert_eq!(dest, _mm_cvtsd_f64(a));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadr_pd() {
+    const fn test_mm_loadr_pd() {
         let mut mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
         let vals = &mut mem.data;
         let d = vals.as_ptr();
 
-        let r = _mm_loadr_pd(d);
+        let r = unsafe { _mm_loadr_pd(d) };
         assert_eq_m128d(r, _mm_setr_pd(2.0, 1.0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_pd() {
+    const fn test_mm_loadu_pd() {
         // guaranteed to be aligned to 16 bytes
         let mut mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
@@ -5099,31 +5137,31 @@ mod tests {
         let vals = &mut mem.data;
 
         // so this will *not* be aligned to 16 bytes
-        let d = vals.as_ptr().offset(1);
+        let d = unsafe { vals.as_ptr().offset(1) };
 
-        let r = _mm_loadu_pd(d);
+        let r = unsafe { _mm_loadu_pd(d) };
         let e = _mm_setr_pd(2.0, 3.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si16() {
+    const fn test_mm_loadu_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = _mm_loadu_si16(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si16(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(r, _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si32() {
+    const fn test_mm_loadu_si32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
-        let r = _mm_loadu_si32(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si32(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(r, _mm_setr_epi32(1, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si64() {
+    const fn test_mm_loadu_si64() {
         let a = _mm_setr_epi64x(5, 6);
-        let r = _mm_loadu_si64(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si64(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
     }
 
@@ -5302,16 +5340,16 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load1_pd() {
+    const fn test_mm_load1_pd() {
         let d = -5.0;
-        let r = _mm_load1_pd(&d);
+        let r = unsafe { _mm_load1_pd(&d) };
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_pd1() {
+    const fn test_mm_load_pd1() {
         let d = -5.0;
-        let r = _mm_load_pd1(&d);
+        let r = unsafe { _mm_load_pd1(&d) };
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 
diff --git a/crates/core_arch/src/x86/sse3.rs b/crates/core_arch/src/x86/sse3.rs
index 68817856f4..e4c7570254 100644
--- a/crates/core_arch/src/x86/sse3.rs
+++ b/crates/core_arch/src/x86/sse3.rs
@@ -239,7 +239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_lddqu_si128() {
+    fn test_mm_lddqu_si128() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4,
@@ -247,7 +247,7 @@ mod tests {
             9, 10, 11, 12,
             13, 14, 15, 16,
         );
-        let r = _mm_lddqu_si128(&a);
+        let r = unsafe { _mm_lddqu_si128(&a) };
         assert_eq_m128i(a, r);
     }
 
@@ -273,9 +273,9 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_loaddup_pd() {
+    const fn test_mm_loaddup_pd() {
         let d = -5.0;
-        let r = _mm_loaddup_pd(&d);
+        let r = unsafe { _mm_loaddup_pd(&d) };
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 }
diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
index a499bf898b..7ad4306f36 100644
--- a/crates/core_arch/src/x86/sse41.rs
+++ b/crates/core_arch/src/x86/sse41.rs
@@ -1219,20 +1219,20 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blendv_pd() {
+    const fn test_mm_blendv_pd() {
         let a = _mm_set1_pd(0.0);
         let b = _mm_set1_pd(1.0);
-        let mask = transmute(_mm_setr_epi64x(0, -1));
+        let mask = _mm_castsi128_pd(_mm_setr_epi64x(0, -1));
         let r = _mm_blendv_pd(a, b, mask);
         let e = _mm_setr_pd(0.0, 1.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blendv_ps() {
+    const fn test_mm_blendv_ps() {
         let a = _mm_set1_ps(0.0);
         let b = _mm_set1_ps(1.0);
-        let mask = transmute(_mm_setr_epi32(0, -1, 0, -1));
+        let mask = _mm_castsi128_ps(_mm_setr_epi32(0, -1, 0, -1));
         let r = _mm_blendv_ps(a, b, mask);
         let e = _mm_setr_ps(0.0, 1.0, 0.0, 1.0);
         assert_eq_m128(r, e);
@@ -1949,9 +1949,9 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_stream_load_si128() {
+    fn test_mm_stream_load_si128() {
         let a = _mm_set_epi64x(5, 6);
-        let r = _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(a, r);
     }
 }
diff --git a/crates/core_arch/src/x86/sse42.rs b/crates/core_arch/src/x86/sse42.rs
index 65d1fe4d62..55e2259263 100644
--- a/crates/core_arch/src/x86/sse42.rs
+++ b/crates/core_arch/src/x86/sse42.rs
@@ -613,6 +613,7 @@ mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
+    use crate::core_arch::simd::*;
     use crate::core_arch::x86::*;
     use std::ptr;
 
@@ -625,7 +626,7 @@ mod tests {
         assert!(s.len() <= 16);
         let mut array = [0u8; 16];
         array[..s.len()].copy_from_slice(s);
-        unsafe { transmute(array) }
+        u8x16::from_array(array).as_m128i()
     }
 
     #[simd_test(enable = "sse4.2")]
diff --git a/crates/core_arch/src/x86/sse4a.rs b/crates/core_arch/src/x86/sse4a.rs
index 020baeff15..f36b879a03 100644
--- a/crates/core_arch/src/x86/sse4a.rs
+++ b/crates/core_arch/src/x86/sse4a.rs
@@ -206,7 +206,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_sd() {
+    fn test_mm_stream_sd() {
         let mut mem = MemoryF64 {
             data: [1.0_f64, 2.0],
         };
@@ -216,7 +216,9 @@ mod tests {
 
             let x = _mm_setr_pd(3.0, 4.0);
 
-            _mm_stream_sd(d, x);
+            unsafe {
+                _mm_stream_sd(d, x);
+            }
             _mm_sfence();
         }
         assert_eq!(mem.data[0], 3.0);
@@ -232,7 +234,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_ss() {
+    fn test_mm_stream_ss() {
         let mut mem = MemoryF32 {
             data: [1.0_f32, 2.0, 3.0, 4.0],
         };
@@ -242,7 +244,9 @@ mod tests {
 
             let x = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-            _mm_stream_ss(d, x);
+            unsafe {
+                _mm_stream_ss(d, x);
+            }
             _mm_sfence();
         }
         assert_eq!(mem.data[0], 5.0);
diff --git a/crates/core_arch/src/x86/xsave.rs b/crates/core_arch/src/x86/xsave.rs
index 653eb28c42..e22d3580ff 100644
--- a/crates/core_arch/src/x86/xsave.rs
+++ b/crates/core_arch/src/x86/xsave.rs
@@ -197,47 +197,53 @@ mod tests {
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsave() {
+    fn test_xsave() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsave(a.ptr(), m);
-        _xrstor(a.ptr(), m);
-        _xsave(b.ptr(), m);
+        unsafe {
+            _xsave(a.ptr(), m);
+            _xrstor(a.ptr(), m);
+            _xsave(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xgetbv() {
+    fn test_xgetbv() {
         let xcr_n: u32 = _XCR_XFEATURE_ENABLED_MASK;
 
-        let xcr: u64 = _xgetbv(xcr_n);
-        let xcr_cpy: u64 = _xgetbv(xcr_n);
+        let xcr: u64 = unsafe { _xgetbv(xcr_n) };
+        let xcr_cpy: u64 = unsafe { _xgetbv(xcr_n) };
         assert_eq!(xcr, xcr_cpy);
     }
 
     #[simd_test(enable = "xsave,xsaveopt")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsaveopt() {
+    fn test_xsaveopt() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsaveopt(a.ptr(), m);
-        _xrstor(a.ptr(), m);
-        _xsaveopt(b.ptr(), m);
+        unsafe {
+            _xsaveopt(a.ptr(), m);
+            _xrstor(a.ptr(), m);
+            _xsaveopt(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave,xsavec")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsavec() {
+    fn test_xsavec() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsavec(a.ptr(), m);
-        _xrstor(a.ptr(), m);
-        _xsavec(b.ptr(), m);
+        unsafe {
+            _xsavec(a.ptr(), m);
+            _xrstor(a.ptr(), m);
+            _xsavec(b.ptr(), m);
+        }
     }
 }
diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index f372f7066d..4e20e014cf 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -581,267 +581,297 @@ mod tests {
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_loadconfig() {
-        let config = __tilecfg::default();
-        _tile_loadconfig(config.as_ptr());
-        _tile_release();
+    fn test_tile_loadconfig() {
+        unsafe {
+            let config = __tilecfg::default();
+            _tile_loadconfig(config.as_ptr());
+            _tile_release();
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_storeconfig() {
-        let config = __tilecfg::new(1, 0, [32; 8], [8; 8]);
-        _tile_loadconfig(config.as_ptr());
-        let mut _config = __tilecfg::default();
-        _tile_storeconfig(_config.as_mut_ptr());
-        _tile_release();
-        assert_eq!(config, _config);
+    fn test_tile_storeconfig() {
+        unsafe {
+            let config = __tilecfg::new(1, 0, [32; 8], [8; 8]);
+            _tile_loadconfig(config.as_ptr());
+            let mut _config = __tilecfg::default();
+            _tile_storeconfig(_config.as_mut_ptr());
+            _tile_release();
+            assert_eq!(config, _config);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_zero() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mut out = [[1_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[0; 64]; 16]);
+    fn test_tile_zero() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mut out = [[1_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[0; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_stored() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mut out = [[1_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[0; 64]; 16]);
+    fn test_tile_stored() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mut out = [[1_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[0; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_loadd() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_loadd::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_loadd() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_loadd::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_stream_loadd() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_stream_loadd() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_release() {
-        _tile_release();
+    fn test_tile_release() {
+        unsafe {
+            _tile_release();
+        }
     }
 
     #[simd_test(enable = "amx-bf16,avx512f")]
-    unsafe fn test_tile_dpbf16ps() {
-        _init_amx();
-        let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits();
-        let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits();
-        let ones: [u8; 1024] = transmute([bf16_1; 512]);
-        let twos: [u8; 1024] = transmute([bf16_2; 512]);
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbf16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[64f32; 16]; 16]);
+    fn test_tile_dpbf16ps() {
+        unsafe {
+            _init_amx();
+            let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits();
+            let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits();
+            let ones: [u8; 1024] = transmute([bf16_1; 512]);
+            let twos: [u8; 1024] = transmute([bf16_2; 512]);
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbf16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[64f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbssd() {
-        _init_amx();
-        let ones = [-1_i8; 1024];
-        let twos = [-2_i8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
-        _tile_dpbssd::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[128_i32; 16]; 16]);
+    fn test_tile_dpbssd() {
+        unsafe {
+            _init_amx();
+            let ones = [-1_i8; 1024];
+            let twos = [-2_i8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
+            _tile_dpbssd::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbsud() {
-        _init_amx();
-        let ones = [-1_i8; 1024];
-        let twos = [2_u8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbsud::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[-128_i32; 16]; 16]);
+    fn test_tile_dpbsud() {
+        unsafe {
+            _init_amx();
+            let ones = [-1_i8; 1024];
+            let twos = [2_u8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbsud::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[-128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbusd() {
-        _init_amx();
-        let ones = [1_u8; 1024];
-        let twos = [-2_i8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
-        _tile_dpbusd::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[-128_i32; 16]; 16]);
+    fn test_tile_dpbusd() {
+        unsafe {
+            _init_amx();
+            let ones = [1_u8; 1024];
+            let twos = [-2_i8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
+            _tile_dpbusd::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[-128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbuud() {
-        _init_amx();
-        let ones = [1_u8; 1024];
-        let twos = [2_u8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbuud::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[128_i32; 16]; 16]);
+    fn test_tile_dpbuud() {
+        unsafe {
+            _init_amx();
+            let ones = [1_u8; 1024];
+            let twos = [2_u8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbuud::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp16")]
-    unsafe fn test_tile_dpfp16ps() {
-        _init_amx();
-        let ones = [1f16; 512];
-        let twos = [2f16; 512];
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
-        _tile_dpfp16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[64f32; 16]; 16]);
+    fn test_tile_dpfp16ps() {
+        unsafe {
+            _init_amx();
+            let ones = [1f16; 512];
+            let twos = [2f16; 512];
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
+            _tile_dpfp16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[64f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-complex")]
-    unsafe fn test_tile_cmmimfp16ps() {
-        _init_amx();
-        let ones = [1f16; 512];
-        let twos = [2f16; 512];
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
-        _tile_cmmimfp16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[64f32; 16]; 16]);
+    fn test_tile_cmmimfp16ps() {
+        unsafe {
+            _init_amx();
+            let ones = [1f16; 512];
+            let twos = [2f16; 512];
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
+            _tile_cmmimfp16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[64f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-complex")]
-    unsafe fn test_tile_cmmrlfp16ps() {
-        _init_amx();
-        let ones = [1f16; 512];
-        let twos = [2f16; 512];
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
-        _tile_cmmrlfp16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[0f32; 16]; 16]);
+    fn test_tile_cmmrlfp16ps() {
+        unsafe {
+            _init_amx();
+            let ones = [1f16; 512];
+            let twos = [2f16; 512];
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
+            _tile_cmmrlfp16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[0f32; 16]; 16]);
+        }
     }
 
     const BF8_ONE: u8 = 0x3c;
@@ -850,223 +880,245 @@ mod tests {
     const HF8_TWO: u8 = 0x40;
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dpbf8ps() {
-        _init_amx();
-        let ones = [BF8_ONE; 1024];
-        let twos = [BF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dpbf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [BF8_ONE; 1024];
+            let twos = [BF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dpbhf8ps() {
-        _init_amx();
-        let ones = [BF8_ONE; 1024];
-        let twos = [HF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbhf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dpbhf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [BF8_ONE; 1024];
+            let twos = [HF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbhf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dphbf8ps() {
-        _init_amx();
-        let ones = [HF8_ONE; 1024];
-        let twos = [BF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dphbf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dphbf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [HF8_ONE; 1024];
+            let twos = [BF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dphbf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dphf8ps() {
-        _init_amx();
-        let ones = [HF8_ONE; 1024];
-        let twos = [HF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dphf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dphf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [HF8_ONE; 1024];
+            let twos = [HF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dphf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-movrs")]
-    unsafe fn test_tile_loaddrs() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_loaddrs() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-movrs")]
-    unsafe fn test_tile_stream_loaddrs() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_stream_loaddrs() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_movrow() {
-        _init_amx();
-        let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]);
-
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_movrow::<0>(i);
-            assert_eq!(*row.as_u8x64().as_array(), [i as _; _]);
+    fn test_tile_movrow() {
+        unsafe {
+            _init_amx();
+            let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_movrow::<0>(i);
+                assert_eq!(*row.as_u8x64().as_array(), [i as _; _]);
+            }
         }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_cvtrowd2ps() {
-        _init_amx();
-        let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]);
-
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_cvtrowd2ps::<0>(i);
-            assert_eq!(*row.as_f32x16().as_array(), [i as _; _]);
+    fn test_tile_cvtrowd2ps() {
+        unsafe {
+            _init_amx();
+            let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowd2ps::<0>(i);
+                assert_eq!(*row.as_f32x16().as_array(), [i as _; _]);
+            }
         }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_cvtrowps2phh() {
-        _init_amx();
-        let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
-
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_cvtrowps2phh::<0>(i);
-            assert_eq!(
-                *row.as_f16x32().as_array(),
-                array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ })
-            );
+    fn test_tile_cvtrowps2phh() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowps2phh::<0>(i);
+                assert_eq!(
+                    *row.as_f16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ })
+                );
+            }
         }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_cvtrowps2phl() {
-        _init_amx();
-        let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
-
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_cvtrowps2phl::<0>(i);
-            assert_eq!(
-                *row.as_f16x32().as_array(),
-                array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 })
-            );
+    fn test_tile_cvtrowps2phl() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowps2phl::<0>(i);
+                assert_eq!(
+                    *row.as_f16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 })
+                );
+            }
         }
     }
 
     #[simd_test(enable = "amx-tf32")]
-    unsafe fn test_tile_mmultf32ps() {
-        _init_amx();
-        let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
-        let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _];
-        let mut res = [[0.0; 16]; 16];
-
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(a.as_ptr().cast(), 64);
-        _tile_loadd::<2>(b.as_ptr().cast(), 64);
-        _tile_mmultf32ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-
-        let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32));
-        assert_eq!(res, expected);
+    fn test_tile_mmultf32ps() {
+        unsafe {
+            _init_amx();
+            let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+            let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _];
+            let mut res = [[0.0; 16]; 16];
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(a.as_ptr().cast(), 64);
+            _tile_loadd::<2>(b.as_ptr().cast(), 64);
+            _tile_mmultf32ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+
+            let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32));
+            assert_eq!(res, expected);
+        }
     }
 }
diff --git a/crates/core_arch/src/x86_64/avx512f.rs b/crates/core_arch/src/x86_64/avx512f.rs
index 368fb0c238..0fd9b09363 100644
--- a/crates/core_arch/src/x86_64/avx512f.rs
+++ b/crates/core_arch/src/x86_64/avx512f.rs
@@ -7446,81 +7446,81 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_pd() {
+    fn test_mm512_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_pd::<8>(index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_pd() {
+    fn test_mm512_mask_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         let src = _mm512_set1_pd(2.);
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_pd() {
+    fn test_mm512_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i64gather_pd::<8>(index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_pd() {
+    fn test_mm512_mask_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         let src = _mm512_set1_pd(2.);
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_ps() {
+    fn test_mm512_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing
         #[rustfmt::skip]
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i64gather_ps::<4>(index, arr.as_ptr()) };
         assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_ps() {
+    fn test_mm512_mask_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         let src = _mm256_set1_ps(2.);
         let mask = 0b10101010;
         #[rustfmt::skip]
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 4 is word-addressing
-        let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()) };
         assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_epi64() {
+    fn test_mm512_i32gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_epi64::<8>(index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_epi64() {
+    fn test_mm512_mask_i32gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
@@ -7529,24 +7529,24 @@ mod tests {
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_epi64() {
+    fn test_mm512_i64gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i64gather_epi64::<8>(index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_epi64() {
+    fn test_mm512_mask_i64gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
@@ -7555,24 +7555,24 @@ mod tests {
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_epi32() {
+    fn test_mm512_i64gather_epi32() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32);
+        let r = unsafe { _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32) };
         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_epi32() {
+    fn test_mm512_mask_i64gather_epi32() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
@@ -7581,17 +7581,21 @@ mod tests {
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32);
+        let r = unsafe {
+            _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32)
+        };
         assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_pd() {
+    fn test_mm512_i32scatter_pd() {
         let mut arr = [0f64; 128];
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as f64;
@@ -7600,13 +7604,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_pd() {
+    fn test_mm512_mask_i32scatter_pd() {
         let mut arr = [0f64; 128];
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2. * (i + 1) as f64;
@@ -7615,12 +7621,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_pd() {
+    fn test_mm512_i64scatter_pd() {
         let mut arr = [0f64; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as f64;
@@ -7629,13 +7637,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_pd() {
+    fn test_mm512_mask_i64scatter_pd() {
         let mut arr = [0f64; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2. * (i + 1) as f64;
@@ -7644,12 +7654,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_ps() {
+    fn test_mm512_i64scatter_ps() {
         let mut arr = [0f32; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 4 is word-addressing
-        _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f32; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as f32;
@@ -7658,13 +7670,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_ps() {
+    fn test_mm512_mask_i64scatter_ps() {
         let mut arr = [0f32; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f32; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2. * (i + 1) as f32;
@@ -7673,12 +7687,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_epi64() {
+    fn test_mm512_i32scatter_epi64() {
         let mut arr = [0i64; 128];
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as i64;
@@ -7687,13 +7703,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_epi64() {
+    fn test_mm512_mask_i32scatter_epi64() {
         let mut arr = [0i64; 128];
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2 * (i + 1) as i64;
@@ -7702,12 +7720,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_epi64() {
+    fn test_mm512_i64scatter_epi64() {
         let mut arr = [0i64; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as i64;
@@ -7716,13 +7736,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_epi64() {
+    fn test_mm512_mask_i64scatter_epi64() {
         let mut arr = [0i64; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2 * (i + 1) as i64;
@@ -7731,12 +7753,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_epi32() {
+    fn test_mm512_i64scatter_epi32() {
         let mut arr = [0i32; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 4 is word-addressing
-        _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i32; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as i32;
@@ -7745,13 +7769,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_epi32() {
+    fn test_mm512_mask_i64scatter_epi32() {
         let mut arr = [0i32; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i32; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2 * (i + 1) as i32;
@@ -7760,559 +7786,640 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32logather_epi64() {
+    fn test_mm512_i32logather_epi64() {
         let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr());
+        let r = unsafe { _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()) };
         let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
         assert_eq_m512i(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32logather_epi64() {
+    fn test_mm512_mask_i32logather_epi64() {
         let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r = unsafe {
+            _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr())
+        };
         let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
         assert_eq_m512i(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32logather_pd() {
+    fn test_mm512_i32logather_pd() {
         let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr());
+        let r = unsafe { _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()) };
         let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
         assert_eq_m512d(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32logather_pd() {
+    fn test_mm512_mask_i32logather_pd() {
         let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
         let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) };
         let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
         assert_eq_m512d(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32loscatter_epi64() {
+    fn test_mm512_i32loscatter_epi64() {
         let mut base_addr: [i64; 8] = [0; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4, 5, 6, 7, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32loscatter_epi64() {
+    fn test_mm512_mask_i32loscatter_epi64() {
         let mut base_addr: [i64; 8] = [0; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0, 2, 0, 4, 0, 6, 0, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32loscatter_pd() {
+    fn test_mm512_i32loscatter_pd() {
         let mut base_addr: [f64; 8] = [0.; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32loscatter_pd() {
+    fn test_mm512_mask_i32loscatter_pd() {
         let mut base_addr: [f64; 8] = [0.; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_epi32() {
+    fn test_mm_mmask_i32gather_epi32() {
         let base_addr: [i32; 4] = [1, 2, 3, 4];
         let src = _mm_setr_epi32(5, 6, 7, 8);
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
-        let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi32(2, 6, 4, 8);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_epi64() {
+    fn test_mm_mmask_i32gather_epi64() {
         let base_addr: [i64; 2] = [1, 2];
         let src = _mm_setr_epi64x(5, 6);
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
-        let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi64x(2, 6);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_pd() {
+    fn test_mm_mmask_i32gather_pd() {
         let base_addr: [f64; 2] = [1., 2.];
         let src = _mm_setr_pd(5., 6.);
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
-        let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_pd(2., 6.);
         assert_eq_m128d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_ps() {
+    fn test_mm_mmask_i32gather_ps() {
         let base_addr: [f32; 4] = [1., 2., 3., 4.];
         let src = _mm_setr_ps(5., 6., 7., 8.);
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
-        let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_ps(2., 6., 4., 8.);
         assert_eq_m128(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_epi32() {
+    fn test_mm_mmask_i64gather_epi32() {
         let base_addr: [i32; 2] = [1, 2];
         let src = _mm_setr_epi32(5, 6, 7, 8);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi32(2, 6, 0, 0);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_epi64() {
+    fn test_mm_mmask_i64gather_epi64() {
         let base_addr: [i64; 2] = [1, 2];
         let src = _mm_setr_epi64x(5, 6);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi64x(2, 6);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_pd() {
+    fn test_mm_mmask_i64gather_pd() {
         let base_addr: [f64; 2] = [1., 2.];
         let src = _mm_setr_pd(5., 6.);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_pd(2., 6.);
         assert_eq_m128d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_ps() {
+    fn test_mm_mmask_i64gather_ps() {
         let base_addr: [f32; 2] = [1., 2.];
         let src = _mm_setr_ps(5., 6., 7., 8.);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_ps(2., 6., 0., 0.);
         assert_eq_m128(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_epi32() {
+    fn test_mm256_mmask_i32gather_epi32() {
         let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
-        let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r = unsafe {
+            _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr())
+        };
         let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
         assert_eq_m256i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_epi64() {
+    fn test_mm256_mmask_i32gather_epi64() {
         let base_addr: [i64; 4] = [1, 2, 3, 4];
         let src = _mm256_setr_epi64x(9, 10, 11, 12);
         let vindex = _mm_setr_epi32(1, 2, 3, 4);
-        let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_epi64x(2, 10, 4, 12);
         assert_eq_m256i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_pd() {
+    fn test_mm256_mmask_i32gather_pd() {
         let base_addr: [f64; 4] = [1., 2., 3., 4.];
         let src = _mm256_setr_pd(9., 10., 11., 12.);
         let vindex = _mm_setr_epi32(1, 2, 3, 4);
-        let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_pd(2., 10., 4., 12.);
         assert_eq_m256d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_ps() {
+    fn test_mm256_mmask_i32gather_ps() {
         let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
         let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
-        let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
         assert_eq_m256(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_epi32() {
+    fn test_mm256_mmask_i64gather_epi32() {
         let base_addr: [i32; 4] = [1, 2, 3, 4];
         let src = _mm_setr_epi32(9, 10, 11, 12);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi32(2, 10, 4, 12);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_epi64() {
+    fn test_mm256_mmask_i64gather_epi64() {
         let base_addr: [i64; 4] = [1, 2, 3, 4];
         let src = _mm256_setr_epi64x(9, 10, 11, 12);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_epi64x(2, 10, 4, 12);
         assert_eq_m256i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_pd() {
+    fn test_mm256_mmask_i64gather_pd() {
         let base_addr: [f64; 4] = [1., 2., 3., 4.];
         let src = _mm256_setr_pd(9., 10., 11., 12.);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_pd(2., 10., 4., 12.);
         assert_eq_m256d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_ps() {
+    fn test_mm256_mmask_i64gather_ps() {
         let base_addr: [f32; 4] = [1., 2., 3., 4.];
         let src = _mm_setr_ps(9., 10., 11., 12.);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_ps(2., 10., 4., 12.);
         assert_eq_m128(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_epi32() {
+    fn test_mm_i32scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_epi32() {
+    fn test_mm_mask_i32scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_epi64() {
+    fn test_mm_i32scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_epi64() {
+    fn test_mm_mask_i32scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_pd() {
+    fn test_mm_i32scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_pd(2., 1.);
-        _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_pd() {
+    fn test_mm_mask_i32scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_pd(2., 1.);
-        _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_ps() {
+    fn test_mm_i32scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_ps() {
+    fn test_mm_mask_i32scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_epi32() {
+    fn test_mm_i64scatter_epi32() {
         let mut base_addr: [i32; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi32(2, 1, -1, -1);
-        _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_epi32() {
+    fn test_mm_mask_i64scatter_epi32() {
         let mut base_addr: [i32; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi32(2, 1, -1, -1);
-        _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_epi64() {
+    fn test_mm_i64scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_epi64() {
+    fn test_mm_mask_i64scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_pd() {
+    fn test_mm_i64scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_pd(2., 1.);
-        _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_pd() {
+    fn test_mm_mask_i64scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_pd(2., 1.);
-        _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_ps() {
+    fn test_mm_i64scatter_ps() {
         let mut base_addr: [f32; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_ps(2., 1., -1., -1.);
-        _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_ps() {
+    fn test_mm_mask_i64scatter_ps() {
         let mut base_addr: [f32; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_ps(2., 1., -1., -1.);
-        _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_epi32() {
+    fn test_mm256_i32scatter_epi32() {
         let mut base_addr: [i32; 8] = [0; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4, 5, 6, 7, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_epi32() {
+    fn test_mm256_mask_i32scatter_epi32() {
         let mut base_addr: [i32; 8] = [0; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0, 2, 0, 4, 0, 6, 0, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_epi64() {
+    fn test_mm256_i32scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_epi64() {
+    fn test_mm256_mask_i32scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_pd() {
+    fn test_mm256_i32scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_pd() {
+    fn test_mm256_mask_i32scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_ps() {
+    fn test_mm256_i32scatter_ps() {
         let mut base_addr: [f32; 8] = [0.; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_ps() {
+    fn test_mm256_mask_i32scatter_ps() {
         let mut base_addr: [f32; 8] = [0.; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_epi32() {
+    fn test_mm256_i64scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_epi32() {
+    fn test_mm256_mask_i64scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_epi64() {
+    fn test_mm256_i64scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_epi64() {
+    fn test_mm256_mask_i64scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_pd() {
+    fn test_mm256_i64scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_pd() {
+    fn test_mm256_mask_i64scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_ps() {
+    fn test_mm256_i64scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_ps() {
+    fn test_mm256_mask_i64scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
@@ -12168,100 +12275,116 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_epi64() {
+    const fn test_mm512_loadu_epi64() {
         let a = &[4, 3, 2, 5, -8, -9, -64, -50];
         let p = a.as_ptr();
-        let r = _mm512_loadu_epi64(black_box(p));
+        let r = unsafe { _mm512_loadu_epi64(black_box(p)) };
         let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi64() {
+    const fn test_mm256_loadu_epi64() {
         let a = &[4, 3, 2, 5];
         let p = a.as_ptr();
-        let r = _mm256_loadu_epi64(black_box(p));
+        let r = unsafe { _mm256_loadu_epi64(black_box(p)) };
         let e = _mm256_setr_epi64x(4, 3, 2, 5);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_loadu_epi64() {
+    const fn test_mm_loadu_epi64() {
         let a = &[4, 3];
         let p = a.as_ptr();
-        let r = _mm_loadu_epi64(black_box(p));
+        let r = unsafe { _mm_loadu_epi64(black_box(p)) };
         let e = _mm_setr_epi64x(4, 3);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
+    fn test_mm512_mask_cvtepi64_storeu_epi16() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
+    fn test_mm256_mask_cvtepi64_storeu_epi16() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm_set1_epi16(0);
-        _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
+    fn test_mm_mask_cvtepi64_storeu_epi16() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
+    fn test_mm512_mask_cvtsepi64_storeu_epi16() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
+    fn test_mm256_mask_cvtsepi64_storeu_epi16() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
+    fn test_mm_mask_cvtsepi64_storeu_epi16() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
+    fn test_mm512_mask_cvtusepi64_storeu_epi16() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(u16::MAX as i16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
+    fn test_mm256_mask_cvtusepi64_storeu_epi16() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(
             0,
             0,
@@ -12276,46 +12399,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
+    fn test_mm_mask_cvtusepi64_storeu_epi16() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
+    fn test_mm512_mask_cvtepi64_storeu_epi8() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm_set1_epi8(0);
-        _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
+    fn test_mm256_mask_cvtepi64_storeu_epi8() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
+    fn test_mm_mask_cvtepi64_storeu_epi8() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
+    fn test_mm512_mask_cvtsepi64_storeu_epi8() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12327,10 +12460,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
+    fn test_mm256_mask_cvtsepi64_storeu_epi8() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12342,19 +12477,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
+    fn test_mm_mask_cvtsepi64_storeu_epi8() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
+    fn test_mm512_mask_cvtusepi64_storeu_epi8() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12366,10 +12505,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
+    fn test_mm256_mask_cvtusepi64_storeu_epi8() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12381,10 +12522,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
+    fn test_mm_mask_cvtusepi64_storeu_epi8() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12396,112 +12539,136 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
+    fn test_mm512_mask_cvtepi64_storeu_epi32() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm256_set1_epi32(9);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
+    fn test_mm256_mask_cvtepi64_storeu_epi32() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm_set1_epi32(0);
-        _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm_set_epi32(9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
+    fn test_mm_mask_cvtepi64_storeu_epi32() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm_set_epi32(0, 0, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
+    fn test_mm512_mask_cvtsepi64_storeu_epi32() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm256_set1_epi32(i32::MAX);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
+    fn test_mm256_mask_cvtsepi64_storeu_epi32() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi32(0);
-        _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        unsafe {
+            _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        }
         let e = _mm_set1_epi32(i32::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
+    fn test_mm_mask_cvtsepi64_storeu_epi32() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        unsafe {
+            _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        }
         let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
+    fn test_mm512_mask_cvtusepi64_storeu_epi32() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm256_set1_epi32(u32::MAX as i32);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
+    fn test_mm256_mask_cvtusepi64_storeu_epi32() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi32(0);
-        _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        unsafe {
+            _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        }
         let e = _mm_set1_epi32(u32::MAX as i32);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
+    fn test_mm_mask_cvtusepi64_storeu_epi32() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        unsafe {
+            _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        }
         let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_epi64() {
+    const fn test_mm512_storeu_epi64() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm512_set1_epi64(0);
-        _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi64() {
+    const fn test_mm256_storeu_epi64() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm256_set1_epi64x(0);
-        _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_storeu_epi64() {
+    const fn test_mm_storeu_epi64() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi64x(0);
-        _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_epi64() {
+    const fn test_mm512_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -12510,63 +12677,69 @@ mod tests {
             data: [4, 3, 2, 5, -8, -9, -64, -50],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_epi64(black_box(p));
+        let r = unsafe { _mm512_load_epi64(black_box(p)) };
         let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_load_epi64() {
+    const fn test_mm256_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 4],
         }
         let a = Align { data: [4, 3, 2, 5] };
         let p = (a.data).as_ptr();
-        let r = _mm256_load_epi64(black_box(p));
+        let r = unsafe { _mm256_load_epi64(black_box(p)) };
         let e = _mm256_set_epi64x(5, 2, 3, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_load_epi64() {
+    const fn test_mm_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 2],
         }
         let a = Align { data: [4, 3] };
         let p = (a.data).as_ptr();
-        let r = _mm_load_epi64(black_box(p));
+        let r = unsafe { _mm_load_epi64(black_box(p)) };
         let e = _mm_set_epi64x(3, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_epi64() {
+    const fn test_mm512_store_epi64() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm512_set1_epi64(0);
-        _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_store_epi64() {
+    const fn test_mm256_store_epi64() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm256_set1_epi64x(0);
-        _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_store_epi64() {
+    const fn test_mm_store_epi64() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi64x(0);
-        _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_pd() {
+    const fn test_mm512_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -12575,16 +12748,18 @@ mod tests {
             data: [4., 3., 2., 5., -8., -9., -64., -50.],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_pd(black_box(p));
+        let r = unsafe { _mm512_load_pd(black_box(p)) };
         let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_pd() {
+    const fn test_mm512_store_pd() {
         let a = _mm512_set1_pd(9.);
         let mut r = _mm512_undefined_pd();
-        _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
+        unsafe {
+            _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
+        }
         assert_eq_m512d(r, a);
     }
 
diff --git a/crates/core_arch/src/x86_64/fxsr.rs b/crates/core_arch/src/x86_64/fxsr.rs
index a24b44fb1f..28bf195116 100644
--- a/crates/core_arch/src/x86_64/fxsr.rs
+++ b/crates/core_arch/src/x86_64/fxsr.rs
@@ -77,12 +77,14 @@ mod tests {
 
     #[simd_test(enable = "fxsr")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_fxsave64() {
+    fn test_fxsave64() {
         let mut a = FxsaveArea::new();
         let mut b = FxsaveArea::new();
 
-        fxsr::_fxsave64(a.ptr());
-        fxsr::_fxrstor64(a.ptr());
-        fxsr::_fxsave64(b.ptr());
+        unsafe {
+            fxsr::_fxsave64(a.ptr());
+            fxsr::_fxrstor64(a.ptr());
+            fxsr::_fxsave64(b.ptr());
+        }
     }
 }
diff --git a/crates/core_arch/src/x86_64/sse2.rs b/crates/core_arch/src/x86_64/sse2.rs
index b156af078a..08dabf053d 100644
--- a/crates/core_arch/src/x86_64/sse2.rs
+++ b/crates/core_arch/src/x86_64/sse2.rs
@@ -204,10 +204,12 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_si64() {
+    fn test_mm_stream_si64() {
         let a: i64 = 7;
         let mut mem = boxed::Box::<i64>::new(-1);
-        _mm_stream_si64(ptr::addr_of_mut!(*mem), a);
+        unsafe {
+            _mm_stream_si64(ptr::addr_of_mut!(*mem), a);
+        }
         _mm_sfence();
         assert_eq!(a, *mem);
     }
diff --git a/crates/core_arch/src/x86_64/xsave.rs b/crates/core_arch/src/x86_64/xsave.rs
index fa1454a822..30a7123315 100644
--- a/crates/core_arch/src/x86_64/xsave.rs
+++ b/crates/core_arch/src/x86_64/xsave.rs
@@ -132,37 +132,43 @@ mod tests {
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsave64() {
+    fn test_xsave64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsave64(a.ptr(), m);
-        _xrstor64(a.ptr(), m);
-        _xsave64(b.ptr(), m);
+        unsafe {
+            _xsave64(a.ptr(), m);
+            _xrstor64(a.ptr(), m);
+            _xsave64(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave,xsaveopt")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsaveopt64() {
+    fn test_xsaveopt64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsaveopt64(a.ptr(), m);
-        _xrstor64(a.ptr(), m);
-        _xsaveopt64(b.ptr(), m);
+        unsafe {
+            _xsaveopt64(a.ptr(), m);
+            _xrstor64(a.ptr(), m);
+            _xsaveopt64(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave,xsavec")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsavec64() {
+    fn test_xsavec64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsavec64(a.ptr(), m);
-        _xrstor64(a.ptr(), m);
-        _xsavec64(b.ptr(), m);
+        unsafe {
+            _xsavec64(a.ptr(), m);
+            _xrstor64(a.ptr(), m);
+            _xsavec64(b.ptr(), m);
+        }
     }
 }

From c35c91a381144fd4c87e0ca33d832310d235f7c1 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 11 Jan 2026 21:10:17 +0100
Subject: [PATCH 094/326] remove `impl Neg` on s390x/powerpc vector types

For other targets we don't have such instances. We specifically decided agains implementing arithmetic operators on these low-level vector types
---
 crates/core_arch/src/powerpc/altivec.rs | 51 ++++++++++++++++++++---
 crates/core_arch/src/powerpc/macros.rs  | 14 -------
 crates/core_arch/src/s390x/macros.rs    | 14 -------
 crates/core_arch/src/s390x/vector.rs    | 54 +++++++++++++++++++++----
 4 files changed, 91 insertions(+), 42 deletions(-)

diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index 37b557c3b2..c1881da08f 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -364,15 +364,46 @@ unsafe extern "C" {
     fn vrfin(a: vector_float) -> vector_float;
 }
 
-impl_neg! { i8x16 : 0 }
-impl_neg! { i16x8 : 0 }
-impl_neg! { i32x4 : 0 }
-impl_neg! { f32x4 : 0f32 }
-
 #[macro_use]
 mod sealed {
     use super::*;
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
+    pub trait VectorNeg {
+        unsafe fn vec_neg(self) -> Self;
+    }
+
+    macro_rules! impl_neg {
+        ($($v:ty)*) => {
+            $(
+                #[unstable(feature = "stdarch_powerpc", issue = "111145")]
+                impl VectorNeg for $v {
+                    #[inline]
+                    #[target_feature(enable = "altivec")]
+                    unsafe fn vec_neg(self) -> Self {
+                        simd_neg(self)
+                    }
+                }
+            )*
+        }
+    }
+
+    impl_neg! {
+        vector_signed_char
+        vector_unsigned_char
+        vector_bool_char
+
+        vector_signed_short
+        vector_unsigned_short
+        vector_bool_short
+
+        vector_signed_int
+        vector_unsigned_int
+        vector_bool_int
+
+        vector_float
+    }
+
     #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorInsert {
         type Scalar;
@@ -1378,7 +1409,7 @@ mod sealed {
             #[inline]
             #[target_feature(enable = "altivec")]
             unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
-                v.vec_max(-v)
+                v.vec_max(simd_neg(v))
             }
 
             impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
@@ -4030,6 +4061,14 @@ pub unsafe fn vec_mfvscr() -> vector_unsigned_short {
     mfvscr()
 }
 
+/// Vector Negate
+#[inline]
+#[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+pub unsafe fn vec_neg<T: sealed::VectorNeg>(a: T) -> T {
+    a.vec_neg()
+}
+
 /// Vector add.
 #[inline]
 #[target_feature(enable = "altivec")]
diff --git a/crates/core_arch/src/powerpc/macros.rs b/crates/core_arch/src/powerpc/macros.rs
index 6097ca31ad..f697d4d257 100644
--- a/crates/core_arch/src/powerpc/macros.rs
+++ b/crates/core_arch/src/powerpc/macros.rs
@@ -274,20 +274,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_neg {
-    ($s: ident : $zero: expr) => {
-        #[unstable(feature = "stdarch_powerpc", issue = "111145")]
-        impl crate::ops::Neg for s_t_l!($s) {
-            type Output = s_t_l!($s);
-            #[inline]
-            fn neg(self) -> Self::Output {
-                unsafe { simd_neg(self) }
-            }
-        }
-    };
-}
-
-pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use s_t_l;
 pub(crate) use t_b;
diff --git a/crates/core_arch/src/s390x/macros.rs b/crates/core_arch/src/s390x/macros.rs
index b72560396c..c47f242948 100644
--- a/crates/core_arch/src/s390x/macros.rs
+++ b/crates/core_arch/src/s390x/macros.rs
@@ -431,20 +431,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_neg {
-    ($s: ident : $zero: expr) => {
-        #[unstable(feature = "stdarch_s390x", issue = "135681")]
-        impl crate::ops::Neg for s_t_l!($s) {
-            type Output = s_t_l!($s);
-            #[inline]
-            fn neg(self) -> Self::Output {
-                unsafe { simd_neg(self) }
-            }
-        }
-    };
-}
-
-pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use l_t_t;
 pub(crate) use s_t_l;
diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index d63f37eeb9..97bfa32f17 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -283,13 +283,6 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
 }
 
-impl_neg! { i8x16 : 0 }
-impl_neg! { i16x8 : 0 }
-impl_neg! { i32x4 : 0 }
-impl_neg! { i64x2 : 0 }
-impl_neg! { f32x4 : 0f32 }
-impl_neg! { f64x2 : 0f64 }
-
 #[repr(simd)]
 struct ShuffleMask<const N: usize>([u32; N]);
 
@@ -437,6 +430,43 @@ enum FindImm {
 mod sealed {
     use super::*;
 
+    #[unstable(feature = "stdarch_s390x", issue = "135681")]
+    pub trait VectorNeg {
+        unsafe fn vec_neg(self) -> Self;
+    }
+
+    macro_rules! impl_neg {
+        ($($v:ty)*) => {
+            $(
+                #[unstable(feature = "stdarch_s390x", issue = "135681")]
+                impl VectorNeg for $v {
+                    #[inline]
+                    #[target_feature(enable = "vector")]
+                    unsafe fn vec_neg(self) -> Self {
+                        simd_neg(self)
+                    }
+                }
+            )*
+        }
+    }
+
+    impl_neg! {
+        vector_signed_char
+        vector_unsigned_char
+
+        vector_signed_short
+        vector_unsigned_short
+
+        vector_signed_int
+        vector_unsigned_int
+
+        vector_signed_long_long
+        vector_unsigned_long_long
+
+        vector_float
+        vector_double
+    }
+
     #[unstable(feature = "stdarch_s390x", issue = "135681")]
     pub trait VectorAdd<Other> {
         type Result;
@@ -759,7 +789,7 @@ mod sealed {
             #[inline]
             #[target_feature(enable = "vector")]
             unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
-                v.vec_max(-v)
+                v.vec_max(simd_neg(v))
             }
 
             impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
@@ -4053,6 +4083,14 @@ unsafe fn __lcbb<const BLOCK_BOUNDARY: u16>(ptr: *const u8) -> u32 {
     lcbb(ptr, const { validate_block_boundary(BLOCK_BOUNDARY) })
 }
 
+/// Vector Negate
+#[inline]
+#[target_feature(enable = "vector")]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_neg<T: sealed::VectorNeg>(a: T) -> T {
+    a.vec_neg()
+}
+
 /// Vector Add
 #[inline]
 #[target_feature(enable = "vector")]

From c90221cd1e66a3ac4995464bc97f00a5811bc358 Mon Sep 17 00:00:00 2001
From: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Date: Tue, 9 Dec 2025 16:33:40 +0000
Subject: [PATCH 095/326] Mark the neon intrinsics as inline(always).

The inline(always) attribute is now applied to the call site when a
function has target features enabled so that it can determine that the
call is safe to inline.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 3892 +++++-----
 .../src/arm_shared/neon/generated.rs          | 6530 ++++++++---------
 crates/core_arch/src/lib.rs                   |    1 +
 crates/stdarch-gen-arm/src/intrinsic.rs       |    2 +-
 4 files changed, 5213 insertions(+), 5212 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 7743e52f4f..23b44294aa 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "CRC32-C single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32cx))]
 #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
@@ -30,7 +30,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32 single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32x))]
 #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
@@ -46,7 +46,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 }
 #[doc = "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__jcvt)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "jsconv")]
 #[cfg_attr(test, assert_instr(fjcvtzs))]
 #[unstable(feature = "stdarch_aarch64_jscvt", issue = "147555")]
@@ -62,7 +62,7 @@ pub fn __jcvt(a: f64) -> i32 {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -77,7 +77,7 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -92,7 +92,7 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -107,7 +107,7 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -121,7 +121,7 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -135,7 +135,7 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -149,7 +149,7 @@ pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -165,7 +165,7 @@ pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -181,7 +181,7 @@ pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -190,7 +190,7 @@ pub fn vabdd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -199,7 +199,7 @@ pub fn vabds_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -209,7 +209,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -223,7 +223,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -237,7 +237,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -251,7 +251,7 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -264,7 +264,7 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -277,7 +277,7 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -290,7 +290,7 @@ pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fabs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -299,7 +299,7 @@ pub fn vabs_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fabs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -308,7 +308,7 @@ pub fn vabsq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -321,7 +321,7 @@ pub fn vabs_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -334,7 +334,7 @@ pub fn vabsq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -350,7 +350,7 @@ pub fn vabsd_s64(a: i64) -> i64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -359,7 +359,7 @@ pub fn vaddd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -368,7 +368,7 @@ pub fn vaddd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -384,7 +384,7 @@ pub fn vaddlv_s16(a: int16x4_t) -> i32 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -400,7 +400,7 @@ pub fn vaddlvq_s16(a: int16x8_t) -> i32 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -416,7 +416,7 @@ pub fn vaddlvq_s32(a: int32x4_t) -> i64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlp))]
@@ -432,7 +432,7 @@ pub fn vaddlv_s32(a: int32x2_t) -> i64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -448,7 +448,7 @@ pub fn vaddlv_s8(a: int8x8_t) -> i16 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -464,7 +464,7 @@ pub fn vaddlvq_s8(a: int8x16_t) -> i16 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -480,7 +480,7 @@ pub fn vaddlv_u16(a: uint16x4_t) -> u32 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -496,7 +496,7 @@ pub fn vaddlvq_u16(a: uint16x8_t) -> u32 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -512,7 +512,7 @@ pub fn vaddlvq_u32(a: uint32x4_t) -> u64 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlp))]
@@ -528,7 +528,7 @@ pub fn vaddlv_u32(a: uint32x2_t) -> u64 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -544,7 +544,7 @@ pub fn vaddlv_u8(a: uint8x8_t) -> u16 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -560,7 +560,7 @@ pub fn vaddlvq_u8(a: uint8x16_t) -> u16 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -576,7 +576,7 @@ pub fn vaddv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -592,7 +592,7 @@ pub fn vaddvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -608,7 +608,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -617,7 +617,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -626,7 +626,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -635,7 +635,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -644,7 +644,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -653,7 +653,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -662,7 +662,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -671,7 +671,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -680,7 +680,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -689,7 +689,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -698,7 +698,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -707,7 +707,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -716,7 +716,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -725,7 +725,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -734,7 +734,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -750,7 +750,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -766,7 +766,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -782,7 +782,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -798,7 +798,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -814,7 +814,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -830,7 +830,7 @@ pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -846,7 +846,7 @@ pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -862,7 +862,7 @@ pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -878,7 +878,7 @@ pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -894,7 +894,7 @@ pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -910,7 +910,7 @@ pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -926,7 +926,7 @@ pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -942,7 +942,7 @@ pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -958,7 +958,7 @@ pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -976,7 +976,7 @@ pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -994,7 +994,7 @@ pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1010,7 +1010,7 @@ pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1026,7 +1026,7 @@ pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1042,7 +1042,7 @@ pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1060,7 +1060,7 @@ pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1078,7 +1078,7 @@ pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1094,7 +1094,7 @@ pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1110,7 +1110,7 @@ pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1126,7 +1126,7 @@ pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1142,7 +1142,7 @@ pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1158,7 +1158,7 @@ pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1174,7 +1174,7 @@ pub fn vcaged_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1190,7 +1190,7 @@ pub fn vcages_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facge))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1207,7 +1207,7 @@ pub fn vcageh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1223,7 +1223,7 @@ pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1239,7 +1239,7 @@ pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1255,7 +1255,7 @@ pub fn vcagtd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1271,7 +1271,7 @@ pub fn vcagts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facgt))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1288,7 +1288,7 @@ pub fn vcagth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1297,7 +1297,7 @@ pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1306,7 +1306,7 @@ pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1315,7 +1315,7 @@ pub fn vcaled_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1324,7 +1324,7 @@ pub fn vcales_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facge))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1334,7 +1334,7 @@ pub fn vcaleh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1343,7 +1343,7 @@ pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1352,7 +1352,7 @@ pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1361,7 +1361,7 @@ pub fn vcaltd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1370,7 +1370,7 @@ pub fn vcalts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facgt))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1380,7 +1380,7 @@ pub fn vcalth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1389,7 +1389,7 @@ pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1398,7 +1398,7 @@ pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1407,7 +1407,7 @@ pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1416,7 +1416,7 @@ pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1425,7 +1425,7 @@ pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1434,7 +1434,7 @@ pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1443,7 +1443,7 @@ pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1452,7 +1452,7 @@ pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1461,7 +1461,7 @@ pub fn vceqd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1470,7 +1470,7 @@ pub fn vceqs_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1479,7 +1479,7 @@ pub fn vceqd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1488,7 +1488,7 @@ pub fn vceqd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1498,7 +1498,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -1509,7 +1509,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -1520,7 +1520,7 @@ pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1530,7 +1530,7 @@ pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1540,7 +1540,7 @@ pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1550,7 +1550,7 @@ pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1560,7 +1560,7 @@ pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1570,7 +1570,7 @@ pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1580,7 +1580,7 @@ pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1590,7 +1590,7 @@ pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1600,7 +1600,7 @@ pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1610,7 +1610,7 @@ pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1620,7 +1620,7 @@ pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1630,7 +1630,7 @@ pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1640,7 +1640,7 @@ pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1650,7 +1650,7 @@ pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1660,7 +1660,7 @@ pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1670,7 +1670,7 @@ pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1680,7 +1680,7 @@ pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1690,7 +1690,7 @@ pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1700,7 +1700,7 @@ pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1710,7 +1710,7 @@ pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1720,7 +1720,7 @@ pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1730,7 +1730,7 @@ pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1740,7 +1740,7 @@ pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1750,7 +1750,7 @@ pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1760,7 +1760,7 @@ pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1769,7 +1769,7 @@ pub fn vceqzd_s64(a: i64) -> u64 {
 }
 #[doc = "Compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1778,7 +1778,7 @@ pub fn vceqzd_u64(a: u64) -> u64 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1788,7 +1788,7 @@ pub fn vceqzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1797,7 +1797,7 @@ pub fn vceqzs_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1806,7 +1806,7 @@ pub fn vceqzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1815,7 +1815,7 @@ pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1824,7 +1824,7 @@ pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1833,7 +1833,7 @@ pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1842,7 +1842,7 @@ pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1851,7 +1851,7 @@ pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1860,7 +1860,7 @@ pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1869,7 +1869,7 @@ pub fn vcged_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1878,7 +1878,7 @@ pub fn vcges_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1887,7 +1887,7 @@ pub fn vcged_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1896,7 +1896,7 @@ pub fn vcged_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1906,7 +1906,7 @@ pub fn vcgeh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1916,7 +1916,7 @@ pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1926,7 +1926,7 @@ pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1936,7 +1936,7 @@ pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1946,7 +1946,7 @@ pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1956,7 +1956,7 @@ pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1966,7 +1966,7 @@ pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1976,7 +1976,7 @@ pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1986,7 +1986,7 @@ pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1996,7 +1996,7 @@ pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2006,7 +2006,7 @@ pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2016,7 +2016,7 @@ pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2026,7 +2026,7 @@ pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2035,7 +2035,7 @@ pub fn vcgezd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2044,7 +2044,7 @@ pub fn vcgezs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2053,7 +2053,7 @@ pub fn vcgezd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2063,7 +2063,7 @@ pub fn vcgezh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2072,7 +2072,7 @@ pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2081,7 +2081,7 @@ pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2090,7 +2090,7 @@ pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2099,7 +2099,7 @@ pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2108,7 +2108,7 @@ pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2117,7 +2117,7 @@ pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2126,7 +2126,7 @@ pub fn vcgtd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2135,7 +2135,7 @@ pub fn vcgts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2144,7 +2144,7 @@ pub fn vcgtd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2153,7 +2153,7 @@ pub fn vcgtd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2163,7 +2163,7 @@ pub fn vcgth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2173,7 +2173,7 @@ pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2183,7 +2183,7 @@ pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2193,7 +2193,7 @@ pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2203,7 +2203,7 @@ pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2213,7 +2213,7 @@ pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2223,7 +2223,7 @@ pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2233,7 +2233,7 @@ pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2243,7 +2243,7 @@ pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2253,7 +2253,7 @@ pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2263,7 +2263,7 @@ pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2273,7 +2273,7 @@ pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2283,7 +2283,7 @@ pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2292,7 +2292,7 @@ pub fn vcgtzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2301,7 +2301,7 @@ pub fn vcgtzs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2310,7 +2310,7 @@ pub fn vcgtzd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2320,7 +2320,7 @@ pub fn vcgtzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2329,7 +2329,7 @@ pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2338,7 +2338,7 @@ pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2347,7 +2347,7 @@ pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2356,7 +2356,7 @@ pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2365,7 +2365,7 @@ pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2374,7 +2374,7 @@ pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2383,7 +2383,7 @@ pub fn vcled_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2392,7 +2392,7 @@ pub fn vcles_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2401,7 +2401,7 @@ pub fn vcled_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2410,7 +2410,7 @@ pub fn vcled_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2420,7 +2420,7 @@ pub fn vcleh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2430,7 +2430,7 @@ pub fn vclez_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2440,7 +2440,7 @@ pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2450,7 +2450,7 @@ pub fn vclez_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2460,7 +2460,7 @@ pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2470,7 +2470,7 @@ pub fn vclez_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2480,7 +2480,7 @@ pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2490,7 +2490,7 @@ pub fn vclez_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2500,7 +2500,7 @@ pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2510,7 +2510,7 @@ pub fn vclez_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2520,7 +2520,7 @@ pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2530,7 +2530,7 @@ pub fn vclez_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2540,7 +2540,7 @@ pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2549,7 +2549,7 @@ pub fn vclezd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2558,7 +2558,7 @@ pub fn vclezs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2567,7 +2567,7 @@ pub fn vclezd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2577,7 +2577,7 @@ pub fn vclezh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2586,7 +2586,7 @@ pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2595,7 +2595,7 @@ pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2604,7 +2604,7 @@ pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2613,7 +2613,7 @@ pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2622,7 +2622,7 @@ pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2631,7 +2631,7 @@ pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2640,7 +2640,7 @@ pub fn vcltd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2649,7 +2649,7 @@ pub fn vcltd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2659,7 +2659,7 @@ pub fn vclth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2668,7 +2668,7 @@ pub fn vclts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2677,7 +2677,7 @@ pub fn vcltd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2687,7 +2687,7 @@ pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2697,7 +2697,7 @@ pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2707,7 +2707,7 @@ pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2717,7 +2717,7 @@ pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2727,7 +2727,7 @@ pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2737,7 +2737,7 @@ pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2747,7 +2747,7 @@ pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2757,7 +2757,7 @@ pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2767,7 +2767,7 @@ pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2777,7 +2777,7 @@ pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2787,7 +2787,7 @@ pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2797,7 +2797,7 @@ pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2806,7 +2806,7 @@ pub fn vcltzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2815,7 +2815,7 @@ pub fn vcltzs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(asr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2824,7 +2824,7 @@ pub fn vcltzd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2834,7 +2834,7 @@ pub fn vcltzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -2852,7 +2852,7 @@ pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -2870,7 +2870,7 @@ pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2886,7 +2886,7 @@ pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2902,7 +2902,7 @@ pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2918,7 +2918,7 @@ pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -2947,7 +2947,7 @@ pub fn vcmla_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -2980,7 +2980,7 @@ pub fn vcmlaq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -2998,7 +2998,7 @@ pub fn vcmla_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3025,7 +3025,7 @@ pub fn vcmlaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3054,7 +3054,7 @@ pub fn vcmla_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3087,7 +3087,7 @@ pub fn vcmlaq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3105,7 +3105,7 @@ pub fn vcmla_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3132,7 +3132,7 @@ pub fn vcmlaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3150,7 +3150,7 @@ pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3168,7 +3168,7 @@ pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3184,7 +3184,7 @@ pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3200,7 +3200,7 @@ pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3216,7 +3216,7 @@ pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3245,7 +3245,7 @@ pub fn vcmla_rot180_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3278,7 +3278,7 @@ pub fn vcmlaq_rot180_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3296,7 +3296,7 @@ pub fn vcmla_rot180_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3323,7 +3323,7 @@ pub fn vcmlaq_rot180_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3352,7 +3352,7 @@ pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3385,7 +3385,7 @@ pub fn vcmlaq_rot180_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3403,7 +3403,7 @@ pub fn vcmla_rot180_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3430,7 +3430,7 @@ pub fn vcmlaq_rot180_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3448,7 +3448,7 @@ pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3466,7 +3466,7 @@ pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3482,7 +3482,7 @@ pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3498,7 +3498,7 @@ pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3514,7 +3514,7 @@ pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3543,7 +3543,7 @@ pub fn vcmla_rot270_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3576,7 +3576,7 @@ pub fn vcmlaq_rot270_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3594,7 +3594,7 @@ pub fn vcmla_rot270_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3621,7 +3621,7 @@ pub fn vcmlaq_rot270_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3650,7 +3650,7 @@ pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3683,7 +3683,7 @@ pub fn vcmlaq_rot270_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3701,7 +3701,7 @@ pub fn vcmla_rot270_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3728,7 +3728,7 @@ pub fn vcmlaq_rot270_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3746,7 +3746,7 @@ pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3764,7 +3764,7 @@ pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3780,7 +3780,7 @@ pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3796,7 +3796,7 @@ pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3812,7 +3812,7 @@ pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3841,7 +3841,7 @@ pub fn vcmla_rot90_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3874,7 +3874,7 @@ pub fn vcmlaq_rot90_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3892,7 +3892,7 @@ pub fn vcmla_rot90_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3919,7 +3919,7 @@ pub fn vcmlaq_rot90_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3948,7 +3948,7 @@ pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3981,7 +3981,7 @@ pub fn vcmlaq_rot90_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3999,7 +3999,7 @@ pub fn vcmla_rot90_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -4026,7 +4026,7 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4047,7 +4047,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4071,7 +4071,7 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4091,7 +4091,7 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4109,7 +4109,7 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4133,7 +4133,7 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4156,7 +4156,7 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4177,7 +4177,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4201,7 +4201,7 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4224,7 +4224,7 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4246,7 +4246,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4272,7 +4272,7 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4296,7 +4296,7 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4318,7 +4318,7 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4347,7 +4347,7 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4371,7 +4371,7 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4393,7 +4393,7 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4422,7 +4422,7 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4446,7 +4446,7 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4470,7 +4470,7 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4492,7 +4492,7 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4514,7 +4514,7 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4536,7 +4536,7 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4558,7 +4558,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4928,7 +4928,7 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4956,7 +4956,7 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4980,7 +4980,7 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5353,7 +5353,7 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5381,7 +5381,7 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5405,7 +5405,7 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5778,7 +5778,7 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5806,7 +5806,7 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5829,7 +5829,7 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5850,7 +5850,7 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6221,7 +6221,7 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6248,7 +6248,7 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6271,7 +6271,7 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6292,7 +6292,7 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6663,7 +6663,7 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6690,7 +6690,7 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6713,7 +6713,7 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6734,7 +6734,7 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7105,7 +7105,7 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7132,7 +7132,7 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7153,7 +7153,7 @@ pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7162,7 +7162,7 @@ pub fn vcreate_f64(a: u64) -> float64x1_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7171,7 +7171,7 @@ pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7180,7 +7180,7 @@ pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7189,7 +7189,7 @@ pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7198,7 +7198,7 @@ pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7207,7 +7207,7 @@ pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7216,7 +7216,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point convert to lower precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7226,7 +7226,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 }
 #[doc = "Floating-point convert to higher precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7236,7 +7236,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7245,7 +7245,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7257,7 +7257,7 @@ pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7275,7 +7275,7 @@ pub fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7293,7 +7293,7 @@ pub fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7311,7 +7311,7 @@ pub fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7329,7 +7329,7 @@ pub fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7347,7 +7347,7 @@ pub fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7365,7 +7365,7 @@ pub fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7383,7 +7383,7 @@ pub fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7401,7 +7401,7 @@ pub fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7417,7 +7417,7 @@ pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7433,7 +7433,7 @@ pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7449,7 +7449,7 @@ pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7465,7 +7465,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7482,7 +7482,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7499,7 +7499,7 @@ pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7515,7 +7515,7 @@ pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7531,7 +7531,7 @@ pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7547,7 +7547,7 @@ pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7563,7 +7563,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7580,7 +7580,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7597,7 +7597,7 @@ pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7613,7 +7613,7 @@ pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7629,7 +7629,7 @@ pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7645,7 +7645,7 @@ pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7661,7 +7661,7 @@ pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7671,7 +7671,7 @@ pub fn vcvtah_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7688,7 +7688,7 @@ pub fn vcvtah_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7705,7 +7705,7 @@ pub fn vcvtah_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7715,7 +7715,7 @@ pub fn vcvtah_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7732,7 +7732,7 @@ pub fn vcvtah_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7749,7 +7749,7 @@ pub fn vcvtah_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7765,7 +7765,7 @@ pub fn vcvtas_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7781,7 +7781,7 @@ pub fn vcvtad_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7797,7 +7797,7 @@ pub fn vcvtas_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7813,7 +7813,7 @@ pub fn vcvtad_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7822,7 +7822,7 @@ pub fn vcvtd_f64_s64(a: i64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7831,7 +7831,7 @@ pub fn vcvts_f32_s32(a: i32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7841,7 +7841,7 @@ pub fn vcvth_f16_s16(a: i16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7851,7 +7851,7 @@ pub fn vcvth_f16_s32(a: i32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7861,7 +7861,7 @@ pub fn vcvth_f16_s64(a: i64) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7871,7 +7871,7 @@ pub fn vcvth_f16_u16(a: u16) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7881,7 +7881,7 @@ pub fn vcvth_f16_u32(a: u32) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7891,7 +7891,7 @@ pub fn vcvth_f16_u64(a: u64) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7903,7 +7903,7 @@ pub fn vcvth_n_f16_s16<const N: i32>(a: i16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7922,7 +7922,7 @@ pub fn vcvth_n_f16_s32<const N: i32>(a: i32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7941,7 +7941,7 @@ pub fn vcvth_n_f16_s64<const N: i32>(a: i64) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7953,7 +7953,7 @@ pub fn vcvth_n_f16_u16<const N: i32>(a: u16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7972,7 +7972,7 @@ pub fn vcvth_n_f16_u32<const N: i32>(a: u32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7991,7 +7991,7 @@ pub fn vcvth_n_f16_u64<const N: i32>(a: u64) -> f16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8003,7 +8003,7 @@ pub fn vcvth_n_s16_f16<const N: i32>(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8022,7 +8022,7 @@ pub fn vcvth_n_s32_f16<const N: i32>(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8041,7 +8041,7 @@ pub fn vcvth_n_s64_f16<const N: i32>(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8053,7 +8053,7 @@ pub fn vcvth_n_u16_f16<const N: i32>(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8072,7 +8072,7 @@ pub fn vcvth_n_u32_f16<const N: i32>(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8091,7 +8091,7 @@ pub fn vcvth_n_u64_f16<const N: i32>(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8101,7 +8101,7 @@ pub fn vcvth_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8111,7 +8111,7 @@ pub fn vcvth_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8121,7 +8121,7 @@ pub fn vcvth_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8131,7 +8131,7 @@ pub fn vcvth_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8141,7 +8141,7 @@ pub fn vcvth_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8151,7 +8151,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8168,7 +8168,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8185,7 +8185,7 @@ pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8201,7 +8201,7 @@ pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8217,7 +8217,7 @@ pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8233,7 +8233,7 @@ pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8249,7 +8249,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8266,7 +8266,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8283,7 +8283,7 @@ pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8299,7 +8299,7 @@ pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8315,7 +8315,7 @@ pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8331,7 +8331,7 @@ pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8347,7 +8347,7 @@ pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8357,7 +8357,7 @@ pub fn vcvtmh_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8374,7 +8374,7 @@ pub fn vcvtmh_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8391,7 +8391,7 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8401,7 +8401,7 @@ pub fn vcvtmh_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8418,7 +8418,7 @@ pub fn vcvtmh_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8435,7 +8435,7 @@ pub fn vcvtmh_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8451,7 +8451,7 @@ pub fn vcvtms_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8467,7 +8467,7 @@ pub fn vcvtmd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8483,7 +8483,7 @@ pub fn vcvtms_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8499,7 +8499,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8516,7 +8516,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8533,7 +8533,7 @@ pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8549,7 +8549,7 @@ pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8565,7 +8565,7 @@ pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8581,7 +8581,7 @@ pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8597,7 +8597,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8614,7 +8614,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8631,7 +8631,7 @@ pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8647,7 +8647,7 @@ pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8663,7 +8663,7 @@ pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8679,7 +8679,7 @@ pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8695,7 +8695,7 @@ pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8705,7 +8705,7 @@ pub fn vcvtnh_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8722,7 +8722,7 @@ pub fn vcvtnh_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8739,7 +8739,7 @@ pub fn vcvtnh_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8749,7 +8749,7 @@ pub fn vcvtnh_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8766,7 +8766,7 @@ pub fn vcvtnh_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8783,7 +8783,7 @@ pub fn vcvtnh_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8799,7 +8799,7 @@ pub fn vcvtns_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8815,7 +8815,7 @@ pub fn vcvtnd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8831,7 +8831,7 @@ pub fn vcvtns_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8847,7 +8847,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8864,7 +8864,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8881,7 +8881,7 @@ pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8897,7 +8897,7 @@ pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8913,7 +8913,7 @@ pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8929,7 +8929,7 @@ pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8945,7 +8945,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8962,7 +8962,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8979,7 +8979,7 @@ pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8995,7 +8995,7 @@ pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9011,7 +9011,7 @@ pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9027,7 +9027,7 @@ pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9043,7 +9043,7 @@ pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9053,7 +9053,7 @@ pub fn vcvtph_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9070,7 +9070,7 @@ pub fn vcvtph_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9087,7 +9087,7 @@ pub fn vcvtph_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9097,7 +9097,7 @@ pub fn vcvtph_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9114,7 +9114,7 @@ pub fn vcvtph_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9131,7 +9131,7 @@ pub fn vcvtph_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9147,7 +9147,7 @@ pub fn vcvtps_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9163,7 +9163,7 @@ pub fn vcvtpd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9179,7 +9179,7 @@ pub fn vcvtps_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9195,7 +9195,7 @@ pub fn vcvtpd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9204,7 +9204,7 @@ pub fn vcvts_f32_u32(a: u32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9213,7 +9213,7 @@ pub fn vcvtd_f64_u64(a: u64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9231,7 +9231,7 @@ pub fn vcvts_n_f32_s32<const N: i32>(a: i32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9249,7 +9249,7 @@ pub fn vcvtd_n_f64_s64<const N: i32>(a: i64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9267,7 +9267,7 @@ pub fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9285,7 +9285,7 @@ pub fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9303,7 +9303,7 @@ pub fn vcvts_n_s32_f32<const N: i32>(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9321,7 +9321,7 @@ pub fn vcvtd_n_s64_f64<const N: i32>(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9339,7 +9339,7 @@ pub fn vcvts_n_u32_f32<const N: i32>(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9357,7 +9357,7 @@ pub fn vcvtd_n_u64_f64<const N: i32>(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9366,7 +9366,7 @@ pub fn vcvts_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9375,7 +9375,7 @@ pub fn vcvtd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9384,7 +9384,7 @@ pub fn vcvts_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9393,7 +9393,7 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9409,7 +9409,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9418,7 +9418,7 @@ pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9427,7 +9427,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9437,7 +9437,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9447,7 +9447,7 @@ pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9456,7 +9456,7 @@ pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9465,7 +9465,7 @@ pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9474,7 +9474,7 @@ pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9483,7 +9483,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9493,7 +9493,7 @@ pub fn vdivh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(sdot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9508,7 +9508,7 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(sdot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9524,7 +9524,7 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(udot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9539,7 +9539,7 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(udot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9555,7 +9555,7 @@ pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x1
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9566,7 +9566,7 @@ pub fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9577,7 +9577,7 @@ pub fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9588,7 +9588,7 @@ pub fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9599,7 +9599,7 @@ pub fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9610,7 +9610,7 @@ pub fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9621,7 +9621,7 @@ pub fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9632,7 +9632,7 @@ pub fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9643,7 +9643,7 @@ pub fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9654,7 +9654,7 @@ pub fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9665,7 +9665,7 @@ pub fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9676,7 +9676,7 @@ pub fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9687,7 +9687,7 @@ pub fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9698,7 +9698,7 @@ pub fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9709,7 +9709,7 @@ pub fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9720,7 +9720,7 @@ pub fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9731,7 +9731,7 @@ pub fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -9743,7 +9743,7 @@ pub fn vduph_lane_f16<const N: i32>(a: float16x4_t) -> f16 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -9755,7 +9755,7 @@ pub fn vduph_laneq_f16<const N: i32>(a: float16x8_t) -> f16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9766,7 +9766,7 @@ pub fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9777,7 +9777,7 @@ pub fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9788,7 +9788,7 @@ pub fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9799,7 +9799,7 @@ pub fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9810,7 +9810,7 @@ pub fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9821,7 +9821,7 @@ pub fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9832,7 +9832,7 @@ pub fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9843,7 +9843,7 @@ pub fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9854,7 +9854,7 @@ pub fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9865,7 +9865,7 @@ pub fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9876,7 +9876,7 @@ pub fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9887,7 +9887,7 @@ pub fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9898,7 +9898,7 @@ pub fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9909,7 +9909,7 @@ pub fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9920,7 +9920,7 @@ pub fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9931,7 +9931,7 @@ pub fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9947,7 +9947,7 @@ pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9963,7 +9963,7 @@ pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9979,7 +9979,7 @@ pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9995,7 +9995,7 @@ pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10011,7 +10011,7 @@ pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10027,7 +10027,7 @@ pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10043,7 +10043,7 @@ pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10059,7 +10059,7 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ext, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -10076,7 +10076,7 @@ pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ext, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -10093,7 +10093,7 @@ pub fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmadd))]
@@ -10102,7 +10102,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10118,7 +10118,7 @@ pub fn vfma_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10134,7 +10134,7 @@ pub fn vfma_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10150,7 +10150,7 @@ pub fn vfmaq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10166,7 +10166,7 @@ pub fn vfmaq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10181,7 +10181,7 @@ pub fn vfma_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10196,7 +10196,7 @@ pub fn vfma_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10211,7 +10211,7 @@ pub fn vfmaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10226,7 +10226,7 @@ pub fn vfmaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10241,7 +10241,7 @@ pub fn vfmaq_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10256,7 +10256,7 @@ pub fn vfma_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10271,7 +10271,7 @@ pub fn vfma_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -10281,7 +10281,7 @@ pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -10291,7 +10291,7 @@ pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmadd))]
@@ -10300,7 +10300,7 @@ pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10314,7 +10314,7 @@ pub fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmadd))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10324,7 +10324,7 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10339,7 +10339,7 @@ pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10354,7 +10354,7 @@ pub fn vfmah_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -10363,7 +10363,7 @@ pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10378,7 +10378,7 @@ pub fn vfmaq_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -10387,7 +10387,7 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10401,7 +10401,7 @@ pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10415,7 +10415,7 @@ pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10429,7 +10429,7 @@ pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10447,7 +10447,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10465,7 +10465,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10482,7 +10482,7 @@ pub fn vfmlal_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10499,7 +10499,7 @@ pub fn vfmlal_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10516,7 +10516,7 @@ pub fn vfmlalq_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10533,7 +10533,7 @@ pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10550,7 +10550,7 @@ pub fn vfmlal_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10567,7 +10567,7 @@ pub fn vfmlal_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10584,7 +10584,7 @@ pub fn vfmlalq_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10601,7 +10601,7 @@ pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10619,7 +10619,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10637,7 +10637,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10655,7 +10655,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10673,7 +10673,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10690,7 +10690,7 @@ pub fn vfmlsl_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10707,7 +10707,7 @@ pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10724,7 +10724,7 @@ pub fn vfmlslq_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10741,7 +10741,7 @@ pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10758,7 +10758,7 @@ pub fn vfmlsl_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10775,7 +10775,7 @@ pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10792,7 +10792,7 @@ pub fn vfmlslq_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10809,7 +10809,7 @@ pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10827,7 +10827,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10845,7 +10845,7 @@ pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -10857,7 +10857,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10873,7 +10873,7 @@ pub fn vfms_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10889,7 +10889,7 @@ pub fn vfms_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10905,7 +10905,7 @@ pub fn vfmsq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10921,7 +10921,7 @@ pub fn vfmsq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10936,7 +10936,7 @@ pub fn vfms_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10951,7 +10951,7 @@ pub fn vfms_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10966,7 +10966,7 @@ pub fn vfmsq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10981,7 +10981,7 @@ pub fn vfmsq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10996,7 +10996,7 @@ pub fn vfmsq_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11011,7 +11011,7 @@ pub fn vfms_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11026,7 +11026,7 @@ pub fn vfms_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -11036,7 +11036,7 @@ pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -11046,7 +11046,7 @@ pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11055,7 +11055,7 @@ pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11065,7 +11065,7 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -11080,7 +11080,7 @@ pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -11095,7 +11095,7 @@ pub fn vfmsh_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11107,7 +11107,7 @@ pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11122,7 +11122,7 @@ pub fn vfmsq_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11131,7 +11131,7 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11141,7 +11141,7 @@ pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11151,7 +11151,7 @@ pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11161,7 +11161,7 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11173,7 +11173,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11185,7 +11185,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11197,7 +11197,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11208,7 +11208,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11219,7 +11219,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11230,7 +11230,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11241,7 +11241,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11252,7 +11252,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11263,7 +11263,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11274,7 +11274,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11285,7 +11285,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11296,7 +11296,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11307,7 +11307,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11318,7 +11318,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11329,7 +11329,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11340,7 +11340,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11351,7 +11351,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11362,7 +11362,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11373,7 +11373,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11384,7 +11384,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11395,7 +11395,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11406,7 +11406,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11417,7 +11417,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11428,7 +11428,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11439,7 +11439,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11450,7 +11450,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11461,7 +11461,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11472,7 +11472,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11483,7 +11483,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11501,7 +11501,7 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11519,7 +11519,7 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11537,7 +11537,7 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11555,7 +11555,7 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11573,7 +11573,7 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11591,7 +11591,7 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11609,7 +11609,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11627,7 +11627,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11645,7 +11645,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -11663,7 +11663,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11683,7 +11683,7 @@ pub unsafe fn vld2_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11703,7 +11703,7 @@ pub unsafe fn vld2_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11716,7 +11716,7 @@ pub unsafe fn vld2_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11729,7 +11729,7 @@ pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11741,7 +11741,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11756,7 +11756,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11768,7 +11768,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11783,7 +11783,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11801,7 +11801,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11819,7 +11819,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11840,7 +11840,7 @@ pub unsafe fn vld2q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11860,7 +11860,7 @@ pub unsafe fn vld2q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x2_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11880,7 +11880,7 @@ pub unsafe fn vld2q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11893,7 +11893,7 @@ pub unsafe fn vld2q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11906,7 +11906,7 @@ pub unsafe fn vld2q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x2_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11919,7 +11919,7 @@ pub unsafe fn vld2q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11932,7 +11932,7 @@ pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11944,7 +11944,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11959,7 +11959,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11971,7 +11971,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11986,7 +11986,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -12004,7 +12004,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -12022,7 +12022,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -12040,7 +12040,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -12058,7 +12058,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12084,7 +12084,7 @@ pub unsafe fn vld3_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12097,7 +12097,7 @@ pub unsafe fn vld3_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12123,7 +12123,7 @@ pub unsafe fn vld3_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12136,7 +12136,7 @@ pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12148,7 +12148,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12164,7 +12164,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12176,7 +12176,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12192,7 +12192,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12210,7 +12210,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12228,7 +12228,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12254,7 +12254,7 @@ pub unsafe fn vld3q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12267,7 +12267,7 @@ pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12293,7 +12293,7 @@ pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12319,7 +12319,7 @@ pub unsafe fn vld3q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12332,7 +12332,7 @@ pub unsafe fn vld3q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x3_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12345,7 +12345,7 @@ pub unsafe fn vld3q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12358,7 +12358,7 @@ pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12370,7 +12370,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12386,7 +12386,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12398,7 +12398,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12414,7 +12414,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12432,7 +12432,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12450,7 +12450,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12468,7 +12468,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -12486,7 +12486,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12513,7 +12513,7 @@ pub unsafe fn vld4_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12540,7 +12540,7 @@ pub unsafe fn vld4_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12553,7 +12553,7 @@ pub unsafe fn vld4_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12566,7 +12566,7 @@ pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12578,7 +12578,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12595,7 +12595,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12607,7 +12607,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12624,7 +12624,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12642,7 +12642,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12660,7 +12660,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12687,7 +12687,7 @@ pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12714,7 +12714,7 @@ pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12741,7 +12741,7 @@ pub unsafe fn vld4q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12754,7 +12754,7 @@ pub unsafe fn vld4q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12767,7 +12767,7 @@ pub unsafe fn vld4q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x4_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12780,7 +12780,7 @@ pub unsafe fn vld4q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12793,7 +12793,7 @@ pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -12805,7 +12805,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -12822,7 +12822,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12834,7 +12834,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12851,7 +12851,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12871,7 +12871,7 @@ pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12891,7 +12891,7 @@ pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12911,7 +12911,7 @@ pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12931,7 +12931,7 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12944,7 +12944,7 @@ pub unsafe fn vluti2_lane_u8<const LANE: i32>(a: uint8x8_t, b: uint8x8_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12957,7 +12957,7 @@ pub unsafe fn vluti2q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12970,7 +12970,7 @@ pub unsafe fn vluti2_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12983,7 +12983,7 @@ pub unsafe fn vluti2q_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12996,7 +12996,7 @@ pub unsafe fn vluti2_lane_p8<const LANE: i32>(a: poly8x8_t, b: uint8x8_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13009,7 +13009,7 @@ pub unsafe fn vluti2q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13022,7 +13022,7 @@ pub unsafe fn vluti2_lane_p16<const LANE: i32>(a: poly16x4_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13035,7 +13035,7 @@ pub unsafe fn vluti2q_lane_p16<const LANE: i32>(a: poly16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13048,7 +13048,7 @@ pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13061,7 +13061,7 @@ pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13074,7 +13074,7 @@ pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13094,7 +13094,7 @@ pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13114,7 +13114,7 @@ pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13127,7 +13127,7 @@ pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13140,7 +13140,7 @@ pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13156,7 +13156,7 @@ pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13169,7 +13169,7 @@ pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13182,7 +13182,7 @@ pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13202,7 +13202,7 @@ pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13222,7 +13222,7 @@ pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13235,7 +13235,7 @@ pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13246,7 +13246,7 @@ pub unsafe fn vluti4q_laneq_p8<const LANE: i32>(a: poly8x16_t, b: uint8x16_t) ->
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -13262,7 +13262,7 @@ pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -13278,7 +13278,7 @@ pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13295,7 +13295,7 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -13304,7 +13304,7 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -13313,7 +13313,7 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point Maximum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13323,7 +13323,7 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13333,7 +13333,7 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13343,7 +13343,7 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -13352,7 +13352,7 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -13361,7 +13361,7 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
@@ -13370,7 +13370,7 @@ pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13387,7 +13387,7 @@ pub fn vmaxv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13404,7 +13404,7 @@ pub fn vmaxvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -13420,7 +13420,7 @@ pub fn vmaxv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxv))]
@@ -13436,7 +13436,7 @@ pub fn vmaxvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -13452,7 +13452,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13461,7 +13461,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13470,7 +13470,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13479,7 +13479,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13488,7 +13488,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -13497,7 +13497,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13506,7 +13506,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13515,7 +13515,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13524,7 +13524,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13533,7 +13533,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13542,7 +13542,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -13551,7 +13551,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13560,7 +13560,7 @@ pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -13576,7 +13576,7 @@ pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -13592,7 +13592,7 @@ pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13609,7 +13609,7 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -13618,7 +13618,7 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -13627,7 +13627,7 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point Minimum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13637,7 +13637,7 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13647,7 +13647,7 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13657,7 +13657,7 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13666,7 +13666,7 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13675,7 +13675,7 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmv))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13684,7 +13684,7 @@ pub fn vminnmvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13701,7 +13701,7 @@ pub fn vminv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13718,7 +13718,7 @@ pub fn vminvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -13734,7 +13734,7 @@ pub fn vminv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminv))]
@@ -13750,7 +13750,7 @@ pub fn vminvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -13766,7 +13766,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13775,7 +13775,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13784,7 +13784,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13793,7 +13793,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13802,7 +13802,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -13811,7 +13811,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13820,7 +13820,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13829,7 +13829,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13838,7 +13838,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13847,7 +13847,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13856,7 +13856,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -13865,7 +13865,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13874,7 +13874,7 @@ pub fn vminvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13883,7 +13883,7 @@ pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13892,7 +13892,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13922,7 +13922,7 @@ pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13956,7 +13956,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13973,7 +13973,7 @@ pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13994,7 +13994,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14028,7 +14028,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14062,7 +14062,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14083,7 +14083,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14104,7 +14104,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14113,7 +14113,7 @@ pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14122,7 +14122,7 @@ pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14131,7 +14131,7 @@ pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14140,7 +14140,7 @@ pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14153,7 +14153,7 @@ pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14166,7 +14166,7 @@ pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14179,7 +14179,7 @@ pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14192,7 +14192,7 @@ pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14205,7 +14205,7 @@ pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14218,7 +14218,7 @@ pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14227,7 +14227,7 @@ pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14236,7 +14236,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14266,7 +14266,7 @@ pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14300,7 +14300,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14317,7 +14317,7 @@ pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14338,7 +14338,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14372,7 +14372,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14406,7 +14406,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14427,7 +14427,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14448,7 +14448,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14457,7 +14457,7 @@ pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14466,7 +14466,7 @@ pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14475,7 +14475,7 @@ pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14484,7 +14484,7 @@ pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14497,7 +14497,7 @@ pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14510,7 +14510,7 @@ pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14523,7 +14523,7 @@ pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14536,7 +14536,7 @@ pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14549,7 +14549,7 @@ pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14562,7 +14562,7 @@ pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14574,7 +14574,7 @@ pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14586,7 +14586,7 @@ pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14598,7 +14598,7 @@ pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14610,7 +14610,7 @@ pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14622,7 +14622,7 @@ pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14634,7 +14634,7 @@ pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14646,7 +14646,7 @@ pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14658,7 +14658,7 @@ pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14670,7 +14670,7 @@ pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14682,7 +14682,7 @@ pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14694,7 +14694,7 @@ pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14706,7 +14706,7 @@ pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -14715,7 +14715,7 @@ pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -14724,7 +14724,7 @@ pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14735,7 +14735,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14752,7 +14752,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14782,7 +14782,7 @@ pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14793,7 +14793,7 @@ pub fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float6
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14802,7 +14802,7 @@ pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14811,7 +14811,7 @@ pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14825,7 +14825,7 @@ pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -14835,7 +14835,7 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14850,7 +14850,7 @@ pub fn vmulh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14865,7 +14865,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14894,7 +14894,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14923,7 +14923,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14939,7 +14939,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14955,7 +14955,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14984,7 +14984,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15013,7 +15013,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15029,7 +15029,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15045,7 +15045,7 @@ pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> ui
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15054,7 +15054,7 @@ pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15063,7 +15063,7 @@ pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15072,7 +15072,7 @@ pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15081,7 +15081,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull2))]
@@ -15090,7 +15090,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull2))]
@@ -15103,7 +15103,7 @@ pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15116,7 +15116,7 @@ pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15129,7 +15129,7 @@ pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15142,7 +15142,7 @@ pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15155,7 +15155,7 @@ pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15168,7 +15168,7 @@ pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15181,7 +15181,7 @@ pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull))]
@@ -15197,7 +15197,7 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15208,7 +15208,7 @@ pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float6
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15219,7 +15219,7 @@ pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15233,7 +15233,7 @@ pub fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15247,7 +15247,7 @@ pub fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15261,7 +15261,7 @@ pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15278,7 +15278,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15295,7 +15295,7 @@ pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15311,7 +15311,7 @@ pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15327,7 +15327,7 @@ pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15343,7 +15343,7 @@ pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15359,7 +15359,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15376,7 +15376,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15393,7 +15393,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15423,7 +15423,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15453,7 +15453,7 @@ pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15464,7 +15464,7 @@ pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float3
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15475,7 +15475,7 @@ pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15491,7 +15491,7 @@ pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15507,7 +15507,7 @@ pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15518,7 +15518,7 @@ pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15529,7 +15529,7 @@ pub fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float6
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15540,7 +15540,7 @@ pub fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -15550,7 +15550,7 @@ pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -15560,7 +15560,7 @@ pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15576,7 +15576,7 @@ pub fn vmulxd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15592,7 +15592,7 @@ pub fn vmulxs_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15603,7 +15603,7 @@ pub fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15614,7 +15614,7 @@ pub fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15625,7 +15625,7 @@ pub fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15636,7 +15636,7 @@ pub fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15653,7 +15653,7 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15665,7 +15665,7 @@ pub fn vmulxh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15677,7 +15677,7 @@ pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15688,7 +15688,7 @@ pub fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -15697,7 +15697,7 @@ pub fn vneg_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -15706,7 +15706,7 @@ pub fn vnegq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15715,7 +15715,7 @@ pub fn vneg_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15724,7 +15724,7 @@ pub fn vnegq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15733,7 +15733,7 @@ pub fn vnegd_s64(a: i64) -> i64 {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15743,7 +15743,7 @@ pub fn vnegh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -15756,7 +15756,7 @@ pub fn vpaddd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -15769,7 +15769,7 @@ pub fn vpadds_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15778,7 +15778,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15787,7 +15787,7 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15804,7 +15804,7 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -15820,7 +15820,7 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -15836,7 +15836,7 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15852,7 +15852,7 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15868,7 +15868,7 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15884,7 +15884,7 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15900,7 +15900,7 @@ pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15910,7 +15910,7 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15931,7 +15931,7 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15941,7 +15941,7 @@ pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15956,7 +15956,7 @@ pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15966,7 +15966,7 @@ pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15981,7 +15981,7 @@ pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15991,7 +15991,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16006,7 +16006,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16023,7 +16023,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16040,7 +16040,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16057,7 +16057,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16074,7 +16074,7 @@ pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16090,7 +16090,7 @@ pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16106,7 +16106,7 @@ pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16122,7 +16122,7 @@ pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16138,7 +16138,7 @@ pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16154,7 +16154,7 @@ pub fn vpmaxnms_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16170,7 +16170,7 @@ pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16186,7 +16186,7 @@ pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16202,7 +16202,7 @@ pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16218,7 +16218,7 @@ pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16234,7 +16234,7 @@ pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16250,7 +16250,7 @@ pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16266,7 +16266,7 @@ pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16282,7 +16282,7 @@ pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16298,7 +16298,7 @@ pub fn vpmaxqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16314,7 +16314,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16331,7 +16331,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16348,7 +16348,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16365,7 +16365,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16382,7 +16382,7 @@ pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16398,7 +16398,7 @@ pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16414,7 +16414,7 @@ pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16430,7 +16430,7 @@ pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16446,7 +16446,7 @@ pub fn vpminnmqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16462,7 +16462,7 @@ pub fn vpminnms_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16478,7 +16478,7 @@ pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16494,7 +16494,7 @@ pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16510,7 +16510,7 @@ pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16526,7 +16526,7 @@ pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16542,7 +16542,7 @@ pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16558,7 +16558,7 @@ pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16574,7 +16574,7 @@ pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16590,7 +16590,7 @@ pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16606,7 +16606,7 @@ pub fn vpminqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16622,7 +16622,7 @@ pub fn vpmins_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16638,7 +16638,7 @@ pub fn vqabs_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16654,7 +16654,7 @@ pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16663,7 +16663,7 @@ pub fn vqabsb_s8(a: i8) -> i8 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16672,7 +16672,7 @@ pub fn vqabsh_s16(a: i16) -> i16 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16688,7 +16688,7 @@ pub fn vqabss_s32(a: i32) -> i32 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16704,7 +16704,7 @@ pub fn vqabsd_s64(a: i64) -> i64 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16715,7 +16715,7 @@ pub fn vqaddb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16726,7 +16726,7 @@ pub fn vqaddh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16737,7 +16737,7 @@ pub fn vqaddb_u8(a: u8, b: u8) -> u8 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16748,7 +16748,7 @@ pub fn vqaddh_u16(a: u16, b: u16) -> u16 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16764,7 +16764,7 @@ pub fn vqadds_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16780,7 +16780,7 @@ pub fn vqaddd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16796,7 +16796,7 @@ pub fn vqadds_u32(a: u32, b: u32) -> u32 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16812,7 +16812,7 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16823,7 +16823,7 @@ pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16834,7 +16834,7 @@ pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16845,7 +16845,7 @@ pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16856,7 +16856,7 @@ pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16865,7 +16865,7 @@ pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16874,7 +16874,7 @@ pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16883,7 +16883,7 @@ pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16892,7 +16892,7 @@ pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, N = 2))]
 #[rustc_legacy_const_generics(3)]
@@ -16903,7 +16903,7 @@ pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16914,7 +16914,7 @@ pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16925,7 +16925,7 @@ pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16936,7 +16936,7 @@ pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16947,7 +16947,7 @@ pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16958,7 +16958,7 @@ pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16968,7 +16968,7 @@ pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16978,7 +16978,7 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16989,7 +16989,7 @@ pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17000,7 +17000,7 @@ pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17011,7 +17011,7 @@ pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17022,7 +17022,7 @@ pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17031,7 +17031,7 @@ pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17040,7 +17040,7 @@ pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17049,7 +17049,7 @@ pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17058,7 +17058,7 @@ pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, N = 2))]
 #[rustc_legacy_const_generics(3)]
@@ -17069,7 +17069,7 @@ pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17080,7 +17080,7 @@ pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17091,7 +17091,7 @@ pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17102,7 +17102,7 @@ pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17113,7 +17113,7 @@ pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17124,7 +17124,7 @@ pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17134,7 +17134,7 @@ pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17144,7 +17144,7 @@ pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 {
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17155,7 +17155,7 @@ pub fn vqdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17166,7 +17166,7 @@ pub fn vqdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17177,7 +17177,7 @@ pub fn vqdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17188,7 +17188,7 @@ pub fn vqdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17202,7 +17202,7 @@ pub fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17216,7 +17216,7 @@ pub fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17227,7 +17227,7 @@ pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17238,7 +17238,7 @@ pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17252,7 +17252,7 @@ pub fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17266,7 +17266,7 @@ pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17281,7 +17281,7 @@ pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17296,7 +17296,7 @@ pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17311,7 +17311,7 @@ pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17326,7 +17326,7 @@ pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17339,7 +17339,7 @@ pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17352,7 +17352,7 @@ pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17365,7 +17365,7 @@ pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17378,7 +17378,7 @@ pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17392,7 +17392,7 @@ pub fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17406,7 +17406,7 @@ pub fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17420,7 +17420,7 @@ pub fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17434,7 +17434,7 @@ pub fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17448,7 +17448,7 @@ pub fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17459,7 +17459,7 @@ pub fn vqdmullh_s16(a: i16, b: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17473,7 +17473,7 @@ pub fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17489,7 +17489,7 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17504,7 +17504,7 @@ pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17513,7 +17513,7 @@ pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17522,7 +17522,7 @@ pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17537,7 +17537,7 @@ pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17546,7 +17546,7 @@ pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17555,7 +17555,7 @@ pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17571,7 +17571,7 @@ pub fn vqmovnd_s64(a: i64) -> i32 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17587,7 +17587,7 @@ pub fn vqmovnd_u64(a: u64) -> u32 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17596,7 +17596,7 @@ pub fn vqmovnh_s16(a: i16) -> i8 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17605,7 +17605,7 @@ pub fn vqmovns_s32(a: i32) -> i16 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17614,7 +17614,7 @@ pub fn vqmovnh_u16(a: u16) -> u8 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17623,7 +17623,7 @@ pub fn vqmovns_u32(a: u32) -> u16 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17638,7 +17638,7 @@ pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17647,7 +17647,7 @@ pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17656,7 +17656,7 @@ pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17665,7 +17665,7 @@ pub fn vqmovunh_s16(a: i16) -> u8 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17674,7 +17674,7 @@ pub fn vqmovuns_s32(a: i32) -> u16 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17683,7 +17683,7 @@ pub fn vqmovund_s64(a: i64) -> u32 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17699,7 +17699,7 @@ pub fn vqneg_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17715,7 +17715,7 @@ pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17724,7 +17724,7 @@ pub fn vqnegb_s8(a: i8) -> i8 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17733,7 +17733,7 @@ pub fn vqnegh_s16(a: i16) -> i16 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17742,7 +17742,7 @@ pub fn vqnegs_s32(a: i32) -> i32 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17751,7 +17751,7 @@ pub fn vqnegd_s64(a: i64) -> i64 {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17766,7 +17766,7 @@ pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17780,7 +17780,7 @@ pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17795,7 +17795,7 @@ pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17809,7 +17809,7 @@ pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17836,7 +17836,7 @@ pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17851,7 +17851,7 @@ pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17878,7 +17878,7 @@ pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17893,7 +17893,7 @@ pub fn vqrdmlahq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17909,7 +17909,7 @@ pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17925,7 +17925,7 @@ pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17941,7 +17941,7 @@ pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17957,7 +17957,7 @@ pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17968,7 +17968,7 @@ pub fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17979,7 +17979,7 @@ pub fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17990,7 +17990,7 @@ pub fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18001,7 +18001,7 @@ pub fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18013,7 +18013,7 @@ pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18025,7 +18025,7 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18040,7 +18040,7 @@ pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18054,7 +18054,7 @@ pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18069,7 +18069,7 @@ pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18083,7 +18083,7 @@ pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18110,7 +18110,7 @@ pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18125,7 +18125,7 @@ pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18152,7 +18152,7 @@ pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18167,7 +18167,7 @@ pub fn vqrdmlshq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18183,7 +18183,7 @@ pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18199,7 +18199,7 @@ pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18215,7 +18215,7 @@ pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18231,7 +18231,7 @@ pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18242,7 +18242,7 @@ pub fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18253,7 +18253,7 @@ pub fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18264,7 +18264,7 @@ pub fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18275,7 +18275,7 @@ pub fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18287,7 +18287,7 @@ pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18299,7 +18299,7 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18310,7 +18310,7 @@ pub fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18321,7 +18321,7 @@ pub fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18332,7 +18332,7 @@ pub fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18343,7 +18343,7 @@ pub fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18352,7 +18352,7 @@ pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18361,7 +18361,7 @@ pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18372,7 +18372,7 @@ pub fn vqrshlb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18383,7 +18383,7 @@ pub fn vqrshlh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18394,7 +18394,7 @@ pub fn vqrshlb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18405,7 +18405,7 @@ pub fn vqrshlh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18421,7 +18421,7 @@ pub fn vqrshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18437,7 +18437,7 @@ pub fn vqrshls_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18453,7 +18453,7 @@ pub fn vqrshls_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18469,7 +18469,7 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18486,7 +18486,7 @@ pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18497,7 +18497,7 @@ pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18508,7 +18508,7 @@ pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18525,7 +18525,7 @@ pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18536,7 +18536,7 @@ pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18547,7 +18547,7 @@ pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18559,7 +18559,7 @@ pub fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18571,7 +18571,7 @@ pub fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18583,7 +18583,7 @@ pub fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18595,7 +18595,7 @@ pub fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18607,7 +18607,7 @@ pub fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18619,7 +18619,7 @@ pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18636,7 +18636,7 @@ pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18647,7 +18647,7 @@ pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18658,7 +18658,7 @@ pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18670,7 +18670,7 @@ pub fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18682,7 +18682,7 @@ pub fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18694,7 +18694,7 @@ pub fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18705,7 +18705,7 @@ pub fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18716,7 +18716,7 @@ pub fn vqshld_n_s64<const N: i32>(a: i64) -> i64 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18727,7 +18727,7 @@ pub fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18738,7 +18738,7 @@ pub fn vqshls_n_s32<const N: i32>(a: i32) -> i32 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18749,7 +18749,7 @@ pub fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18760,7 +18760,7 @@ pub fn vqshld_n_u64<const N: i32>(a: u64) -> u64 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18771,7 +18771,7 @@ pub fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18782,7 +18782,7 @@ pub fn vqshls_n_u32<const N: i32>(a: u32) -> u32 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18792,7 +18792,7 @@ pub fn vqshlb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18802,7 +18802,7 @@ pub fn vqshlh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18812,7 +18812,7 @@ pub fn vqshls_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18822,7 +18822,7 @@ pub fn vqshlb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18832,7 +18832,7 @@ pub fn vqshlh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18842,7 +18842,7 @@ pub fn vqshls_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18858,7 +18858,7 @@ pub fn vqshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18874,7 +18874,7 @@ pub fn vqshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18885,7 +18885,7 @@ pub fn vqshlub_n_s8<const N: i32>(a: i8) -> u8 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18896,7 +18896,7 @@ pub fn vqshlud_n_s64<const N: i32>(a: i64) -> u64 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18907,7 +18907,7 @@ pub fn vqshluh_n_s16<const N: i32>(a: i16) -> u16 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18918,7 +18918,7 @@ pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18935,7 +18935,7 @@ pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18946,7 +18946,7 @@ pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18957,7 +18957,7 @@ pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18974,7 +18974,7 @@ pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18985,7 +18985,7 @@ pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18996,7 +18996,7 @@ pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19014,7 +19014,7 @@ pub fn vqshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19032,7 +19032,7 @@ pub fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19043,7 +19043,7 @@ pub fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19054,7 +19054,7 @@ pub fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19065,7 +19065,7 @@ pub fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19076,7 +19076,7 @@ pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -19093,7 +19093,7 @@ pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -19104,7 +19104,7 @@ pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -19115,7 +19115,7 @@ pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19126,7 +19126,7 @@ pub fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19137,7 +19137,7 @@ pub fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19148,7 +19148,7 @@ pub fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19159,7 +19159,7 @@ pub fn vqsubb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19170,7 +19170,7 @@ pub fn vqsubh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19181,7 +19181,7 @@ pub fn vqsubb_u8(a: u8, b: u8) -> u8 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19192,7 +19192,7 @@ pub fn vqsubh_u16(a: u16, b: u16) -> u16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19208,7 +19208,7 @@ pub fn vqsubs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19224,7 +19224,7 @@ pub fn vqsubd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19240,7 +19240,7 @@ pub fn vqsubs_u32(a: u32, b: u32) -> u32 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19256,7 +19256,7 @@ pub fn vqsubd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19272,7 +19272,7 @@ fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19288,7 +19288,7 @@ fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19297,7 +19297,7 @@ pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19306,7 +19306,7 @@ pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19315,7 +19315,7 @@ pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19324,7 +19324,7 @@ pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19333,7 +19333,7 @@ pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19342,7 +19342,7 @@ pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19358,7 +19358,7 @@ fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19374,7 +19374,7 @@ fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19383,7 +19383,7 @@ pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19392,7 +19392,7 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19402,7 +19402,7 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19431,7 +19431,7 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19441,7 +19441,7 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19475,7 +19475,7 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19485,7 +19485,7 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19514,7 +19514,7 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19524,7 +19524,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19558,7 +19558,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19574,7 +19574,7 @@ fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19590,7 +19590,7 @@ fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19599,7 +19599,7 @@ pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19608,7 +19608,7 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19618,7 +19618,7 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19655,7 +19655,7 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19665,7 +19665,7 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19707,7 +19707,7 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19717,7 +19717,7 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19754,7 +19754,7 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19764,7 +19764,7 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19806,7 +19806,7 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19828,7 +19828,7 @@ fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19850,7 +19850,7 @@ fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19859,7 +19859,7 @@ pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19868,7 +19868,7 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19886,7 +19886,7 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19935,7 +19935,7 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19953,7 +19953,7 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20007,7 +20007,7 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20025,7 +20025,7 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20074,7 +20074,7 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20092,7 +20092,7 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20146,7 +20146,7 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20162,7 +20162,7 @@ fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20178,7 +20178,7 @@ fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20187,7 +20187,7 @@ pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20196,7 +20196,7 @@ pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20205,7 +20205,7 @@ pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20214,7 +20214,7 @@ pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20223,7 +20223,7 @@ pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20232,7 +20232,7 @@ pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20248,7 +20248,7 @@ fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20264,7 +20264,7 @@ fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20273,7 +20273,7 @@ pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20282,7 +20282,7 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20292,7 +20292,7 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20322,7 +20322,7 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20332,7 +20332,7 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20369,7 +20369,7 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20379,7 +20379,7 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20409,7 +20409,7 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20419,7 +20419,7 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20456,7 +20456,7 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20473,7 +20473,7 @@ fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20495,7 +20495,7 @@ fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20504,7 +20504,7 @@ pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20513,7 +20513,7 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20531,7 +20531,7 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20574,7 +20574,7 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20592,7 +20592,7 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20641,7 +20641,7 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20659,7 +20659,7 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20702,7 +20702,7 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20720,7 +20720,7 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20769,7 +20769,7 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20799,7 +20799,7 @@ fn vqtbx4(
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20829,7 +20829,7 @@ fn vqtbx4q(
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20838,7 +20838,7 @@ pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20847,7 +20847,7 @@ pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20866,7 +20866,7 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20917,7 +20917,7 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20936,7 +20936,7 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20993,7 +20993,7 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21012,7 +21012,7 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21063,7 +21063,7 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21082,7 +21082,7 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21139,7 +21139,7 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Rotate and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(rax1))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -21155,7 +21155,7 @@ pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -21164,7 +21164,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -21173,7 +21173,7 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21183,7 +21183,7 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21197,7 +21197,7 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21207,7 +21207,7 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21226,7 +21226,7 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21236,7 +21236,7 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21250,7 +21250,7 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21260,7 +21260,7 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21279,7 +21279,7 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21295,7 +21295,7 @@ pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21311,7 +21311,7 @@ pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21327,7 +21327,7 @@ pub fn vrecped_f64(a: f64) -> f64 {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21343,7 +21343,7 @@ pub fn vrecpes_f32(a: f32) -> f32 {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -21360,7 +21360,7 @@ pub fn vrecpeh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21376,7 +21376,7 @@ pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21392,7 +21392,7 @@ pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21408,7 +21408,7 @@ pub fn vrecpsd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21424,7 +21424,7 @@ pub fn vrecpss_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frecps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -21441,7 +21441,7 @@ pub fn vrecpsh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21457,7 +21457,7 @@ pub fn vrecpxd_f64(a: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21473,7 +21473,7 @@ pub fn vrecpxs_f32(a: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -21490,7 +21490,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21501,7 +21501,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21513,7 +21513,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21524,7 +21524,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21539,7 +21539,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21550,7 +21550,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21564,7 +21564,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21575,7 +21575,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21590,7 +21590,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21600,7 +21600,7 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21613,7 +21613,7 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21623,7 +21623,7 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21634,7 +21634,7 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21644,7 +21644,7 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21655,7 +21655,7 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21665,7 +21665,7 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21679,7 +21679,7 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21689,7 +21689,7 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21703,7 +21703,7 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21713,7 +21713,7 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21726,7 +21726,7 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21736,7 +21736,7 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21749,7 +21749,7 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21759,7 +21759,7 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21772,7 +21772,7 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21782,7 +21782,7 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21795,7 +21795,7 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21804,7 +21804,7 @@ pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21814,7 +21814,7 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21827,7 +21827,7 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21837,7 +21837,7 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21850,7 +21850,7 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21860,7 +21860,7 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21873,7 +21873,7 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21882,7 +21882,7 @@ pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21892,7 +21892,7 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21905,7 +21905,7 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21915,7 +21915,7 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21928,7 +21928,7 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21937,7 +21937,7 @@ pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21947,7 +21947,7 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21958,7 +21958,7 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21968,7 +21968,7 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21982,7 +21982,7 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21992,7 +21992,7 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22010,7 +22010,7 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22020,7 +22020,7 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22034,7 +22034,7 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22044,7 +22044,7 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22058,7 +22058,7 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22068,7 +22068,7 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22082,7 +22082,7 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22092,7 +22092,7 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22110,7 +22110,7 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22120,7 +22120,7 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22134,7 +22134,7 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22144,7 +22144,7 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22158,7 +22158,7 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22168,7 +22168,7 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22182,7 +22182,7 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22192,7 +22192,7 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22210,7 +22210,7 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22220,7 +22220,7 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22234,7 +22234,7 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22244,7 +22244,7 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22258,7 +22258,7 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22268,7 +22268,7 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22279,7 +22279,7 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22289,7 +22289,7 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22304,7 +22304,7 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22314,7 +22314,7 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22325,7 +22325,7 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22335,7 +22335,7 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22349,7 +22349,7 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22359,7 +22359,7 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22370,7 +22370,7 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22380,7 +22380,7 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22394,7 +22394,7 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22403,7 +22403,7 @@ pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22412,7 +22412,7 @@ pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22422,7 +22422,7 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22436,7 +22436,7 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22446,7 +22446,7 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22460,7 +22460,7 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22470,7 +22470,7 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22481,7 +22481,7 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22491,7 +22491,7 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22506,7 +22506,7 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22516,7 +22516,7 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22527,7 +22527,7 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22537,7 +22537,7 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22551,7 +22551,7 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22561,7 +22561,7 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22572,7 +22572,7 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22582,7 +22582,7 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22596,7 +22596,7 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22605,7 +22605,7 @@ pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22614,7 +22614,7 @@ pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22624,7 +22624,7 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22638,7 +22638,7 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22648,7 +22648,7 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22662,7 +22662,7 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22672,7 +22672,7 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22683,7 +22683,7 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22693,7 +22693,7 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22708,7 +22708,7 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22718,7 +22718,7 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22729,7 +22729,7 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22739,7 +22739,7 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22753,7 +22753,7 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22763,7 +22763,7 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22776,7 +22776,7 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22785,7 +22785,7 @@ pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22794,7 +22794,7 @@ pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22803,7 +22803,7 @@ pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22813,7 +22813,7 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22827,7 +22827,7 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22837,7 +22837,7 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22851,7 +22851,7 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22861,7 +22861,7 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22875,7 +22875,7 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22885,7 +22885,7 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22899,7 +22899,7 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22915,7 +22915,7 @@ pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22931,7 +22931,7 @@ pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22947,7 +22947,7 @@ pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22963,7 +22963,7 @@ pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -22979,7 +22979,7 @@ pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -22995,7 +22995,7 @@ pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -23011,7 +23011,7 @@ pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -23027,7 +23027,7 @@ pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23043,7 +23043,7 @@ pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23059,7 +23059,7 @@ pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23075,7 +23075,7 @@ pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23091,7 +23091,7 @@ pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23107,7 +23107,7 @@ pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23123,7 +23123,7 @@ pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23139,7 +23139,7 @@ pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23155,7 +23155,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23165,7 +23165,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23175,7 +23175,7 @@ pub fn vrndq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23184,7 +23184,7 @@ pub fn vrnd_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23193,7 +23193,7 @@ pub fn vrndq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23202,7 +23202,7 @@ pub fn vrnd_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23211,7 +23211,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23221,7 +23221,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23231,7 +23231,7 @@ pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23240,7 +23240,7 @@ pub fn vrnda_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23249,7 +23249,7 @@ pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23258,7 +23258,7 @@ pub fn vrnda_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23267,7 +23267,7 @@ pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23277,7 +23277,7 @@ pub fn vrndah_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23287,7 +23287,7 @@ pub fn vrndh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23304,7 +23304,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23321,7 +23321,7 @@ pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23337,7 +23337,7 @@ pub fn vrndi_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23353,7 +23353,7 @@ pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23369,7 +23369,7 @@ pub fn vrndi_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23385,7 +23385,7 @@ pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23402,7 +23402,7 @@ pub fn vrndih_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23412,7 +23412,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23422,7 +23422,7 @@ pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23431,7 +23431,7 @@ pub fn vrndm_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23440,7 +23440,7 @@ pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23449,7 +23449,7 @@ pub fn vrndm_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23458,7 +23458,7 @@ pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23468,7 +23468,7 @@ pub fn vrndmh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -23484,7 +23484,7 @@ pub fn vrndn_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -23500,7 +23500,7 @@ pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23517,7 +23517,7 @@ pub fn vrndnh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -23533,7 +23533,7 @@ pub fn vrndns_f32(a: f32) -> f32 {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23543,7 +23543,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23553,7 +23553,7 @@ pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23562,7 +23562,7 @@ pub fn vrndp_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23571,7 +23571,7 @@ pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23580,7 +23580,7 @@ pub fn vrndp_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23589,7 +23589,7 @@ pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23599,7 +23599,7 @@ pub fn vrndph_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23609,7 +23609,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23619,7 +23619,7 @@ pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23628,7 +23628,7 @@ pub fn vrndx_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23637,7 +23637,7 @@ pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23646,7 +23646,7 @@ pub fn vrndx_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23655,7 +23655,7 @@ pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23665,7 +23665,7 @@ pub fn vrndxh_f16(a: f16) -> f16 {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23681,7 +23681,7 @@ pub fn vrshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23697,7 +23697,7 @@ pub fn vrshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshr, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23708,7 +23708,7 @@ pub fn vrshrd_n_s64<const N: i32>(a: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshr, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23719,7 +23719,7 @@ pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23736,7 +23736,7 @@ pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23747,7 +23747,7 @@ pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23758,7 +23758,7 @@ pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23775,7 +23775,7 @@ pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23786,7 +23786,7 @@ pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23797,7 +23797,7 @@ pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23813,7 +23813,7 @@ pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23829,7 +23829,7 @@ pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23845,7 +23845,7 @@ pub fn vrsqrted_f64(a: f64) -> f64 {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23861,7 +23861,7 @@ pub fn vrsqrtes_f32(a: f32) -> f32 {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -23878,7 +23878,7 @@ pub fn vrsqrteh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23894,7 +23894,7 @@ pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23910,7 +23910,7 @@ pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23926,7 +23926,7 @@ pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23942,7 +23942,7 @@ pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -23959,7 +23959,7 @@ pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed rounding shift right and accumulate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshr, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23971,7 +23971,7 @@ pub fn vrsrad_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift right and accumulate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshr, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23983,7 +23983,7 @@ pub fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -23994,7 +23994,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24005,7 +24005,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24016,7 +24016,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24027,7 +24027,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24038,7 +24038,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24049,7 +24049,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24060,7 +24060,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24071,7 +24071,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24082,7 +24082,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24093,7 +24093,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24104,7 +24104,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24115,7 +24115,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24126,7 +24126,7 @@ pub fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24137,7 +24137,7 @@ pub fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "SHA512 hash update part 2"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h2))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24153,7 +24153,7 @@ pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t
 }
 #[doc = "SHA512 hash update part 1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24169,7 +24169,7 @@ pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t
 }
 #[doc = "SHA512 schedule update 0"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su0))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24185,7 +24185,7 @@ pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "SHA512 schedule update 1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su1))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24201,7 +24201,7 @@ pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24210,7 +24210,7 @@ pub fn vshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24219,7 +24219,7 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24233,7 +24233,7 @@ pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24247,7 +24247,7 @@ pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24261,7 +24261,7 @@ pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24275,7 +24275,7 @@ pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24289,7 +24289,7 @@ pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24303,7 +24303,7 @@ pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24320,7 +24320,7 @@ pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24331,7 +24331,7 @@ pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24342,7 +24342,7 @@ pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24359,7 +24359,7 @@ pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24370,7 +24370,7 @@ pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24381,7 +24381,7 @@ pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24399,7 +24399,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24417,7 +24417,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24435,7 +24435,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24453,7 +24453,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24471,7 +24471,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24489,7 +24489,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24507,7 +24507,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24525,7 +24525,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24536,7 +24536,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24547,7 +24547,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24558,7 +24558,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24569,7 +24569,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24580,7 +24580,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24591,7 +24591,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24602,7 +24602,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24613,7 +24613,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24624,7 +24624,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24635,7 +24635,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24646,7 +24646,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24657,7 +24657,7 @@ pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24668,7 +24668,7 @@ pub fn vsli_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24679,7 +24679,7 @@ pub fn vsliq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -24690,7 +24690,7 @@ pub fn vslid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -24701,7 +24701,7 @@ pub fn vslid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 }
 #[doc = "SM3PARTW1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3partw1))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24717,7 +24717,7 @@ pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_
 }
 #[doc = "SM3PARTW2"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3partw2))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24733,7 +24733,7 @@ pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_
 }
 #[doc = "SM3SS1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3ss1))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24749,7 +24749,7 @@ pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SM3TT1A"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24767,7 +24767,7 @@ pub fn vsm3tt1aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT1B"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24785,7 +24785,7 @@ pub fn vsm3tt1bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT2A"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24803,7 +24803,7 @@ pub fn vsm3tt2aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT2B"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24821,7 +24821,7 @@ pub fn vsm3tt2bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM4 key"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm4ekey))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24837,7 +24837,7 @@ pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SM4 encode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm4e))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24853,7 +24853,7 @@ pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24869,7 +24869,7 @@ pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24885,7 +24885,7 @@ pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24901,7 +24901,7 @@ pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24917,7 +24917,7 @@ pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24933,7 +24933,7 @@ pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24949,7 +24949,7 @@ pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24965,7 +24965,7 @@ pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24981,7 +24981,7 @@ pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24990,7 +24990,7 @@ pub fn vsqaddb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24999,7 +24999,7 @@ pub fn vsqaddh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25015,7 +25015,7 @@ pub fn vsqaddd_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25031,7 +25031,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -25041,7 +25041,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -25051,7 +25051,7 @@ pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25060,7 +25060,7 @@ pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25069,7 +25069,7 @@ pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25078,7 +25078,7 @@ pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25087,7 +25087,7 @@ pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -25097,7 +25097,7 @@ pub fn vsqrth_f16(a: f16) -> f16 {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25115,7 +25115,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25133,7 +25133,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25151,7 +25151,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25169,7 +25169,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25187,7 +25187,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25205,7 +25205,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25223,7 +25223,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25241,7 +25241,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25252,7 +25252,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25263,7 +25263,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25274,7 +25274,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25285,7 +25285,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25296,7 +25296,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25307,7 +25307,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25318,7 +25318,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25329,7 +25329,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25340,7 +25340,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25351,7 +25351,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25362,7 +25362,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25373,7 +25373,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25384,7 +25384,7 @@ pub fn vsri_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25395,7 +25395,7 @@ pub fn vsriq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -25406,7 +25406,7 @@ pub fn vsrid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -25419,7 +25419,7 @@ pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25432,7 +25432,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25445,7 +25445,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25457,7 +25457,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25469,7 +25469,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25481,7 +25481,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25493,7 +25493,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25505,7 +25505,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25517,7 +25517,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25529,7 +25529,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25541,7 +25541,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25553,7 +25553,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25565,7 +25565,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25577,7 +25577,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25589,7 +25589,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25601,7 +25601,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25613,7 +25613,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25625,7 +25625,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25637,7 +25637,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25649,7 +25649,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25661,7 +25661,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25673,7 +25673,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25685,7 +25685,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25697,7 +25697,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25709,7 +25709,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25721,7 +25721,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25733,7 +25733,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25745,7 +25745,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25757,7 +25757,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25775,7 +25775,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25793,7 +25793,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25811,7 +25811,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25829,7 +25829,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25853,7 +25853,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25877,7 +25877,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25890,7 +25890,7 @@ pub unsafe fn vst1_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25903,7 +25903,7 @@ pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -25921,7 +25921,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25941,7 +25941,7 @@ pub unsafe fn vst2_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25961,7 +25961,7 @@ pub unsafe fn vst2_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25974,7 +25974,7 @@ pub unsafe fn vst2_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25987,7 +25987,7 @@ pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26005,7 +26005,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26023,7 +26023,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26043,7 +26043,7 @@ pub unsafe fn vst2q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26063,7 +26063,7 @@ pub unsafe fn vst2q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26083,7 +26083,7 @@ pub unsafe fn vst2q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26096,7 +26096,7 @@ pub unsafe fn vst2q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26109,7 +26109,7 @@ pub unsafe fn vst2q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26122,7 +26122,7 @@ pub unsafe fn vst2q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26135,7 +26135,7 @@ pub unsafe fn vst2q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26146,7 +26146,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26157,7 +26157,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -26175,7 +26175,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26195,7 +26195,7 @@ pub unsafe fn vst3_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26215,7 +26215,7 @@ pub unsafe fn vst3_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26228,7 +26228,7 @@ pub unsafe fn vst3_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26241,7 +26241,7 @@ pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26259,7 +26259,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26277,7 +26277,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26297,7 +26297,7 @@ pub unsafe fn vst3q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26317,7 +26317,7 @@ pub unsafe fn vst3q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26337,7 +26337,7 @@ pub unsafe fn vst3q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26350,7 +26350,7 @@ pub unsafe fn vst3q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26363,7 +26363,7 @@ pub unsafe fn vst3q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26376,7 +26376,7 @@ pub unsafe fn vst3q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26389,7 +26389,7 @@ pub unsafe fn vst3q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26400,7 +26400,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26411,7 +26411,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -26429,7 +26429,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26456,7 +26456,7 @@ pub unsafe fn vst4_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26483,7 +26483,7 @@ pub unsafe fn vst4_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26496,7 +26496,7 @@ pub unsafe fn vst4_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26509,7 +26509,7 @@ pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26527,7 +26527,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26545,7 +26545,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26572,7 +26572,7 @@ pub unsafe fn vst4q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26599,7 +26599,7 @@ pub unsafe fn vst4q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26626,7 +26626,7 @@ pub unsafe fn vst4q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26639,7 +26639,7 @@ pub unsafe fn vst4q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26652,7 +26652,7 @@ pub unsafe fn vst4q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26665,7 +26665,7 @@ pub unsafe fn vst4q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26678,7 +26678,7 @@ pub unsafe fn vst4q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26689,7 +26689,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26698,7 +26698,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -26707,7 +26707,7 @@ pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -26716,7 +26716,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -26725,7 +26725,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -26734,7 +26734,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26744,7 +26744,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -26759,7 +26759,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -26774,7 +26774,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -26789,7 +26789,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -26804,7 +26804,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -26819,7 +26819,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -26834,7 +26834,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -26846,7 +26846,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -26858,7 +26858,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -26870,7 +26870,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -26882,7 +26882,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -26894,7 +26894,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -26906,7 +26906,7 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(sudot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -26921,7 +26921,7 @@ pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(sudot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -26937,7 +26937,7 @@ pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x1
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26950,7 +26950,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26959,7 +26959,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26968,7 +26968,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26977,7 +26977,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -26987,7 +26987,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27004,7 +27004,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27014,7 +27014,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27031,7 +27031,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27044,7 +27044,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27058,7 +27058,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27080,7 +27080,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27094,7 +27094,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27116,7 +27116,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27126,7 +27126,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27137,7 +27137,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27157,7 +27157,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27168,7 +27168,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27188,7 +27188,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27207,7 +27207,7 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27226,7 +27226,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27245,7 +27245,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27254,7 +27254,7 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27264,7 +27264,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27283,7 +27283,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27293,7 +27293,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27312,7 +27312,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27336,7 +27336,7 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27356,7 +27356,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27383,7 +27383,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27403,7 +27403,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27430,7 +27430,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27446,7 +27446,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27463,7 +27463,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27488,7 +27488,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27505,7 +27505,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27530,7 +27530,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27540,7 +27540,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27550,7 +27550,7 @@ pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27559,7 +27559,7 @@ pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27568,7 +27568,7 @@ pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27577,7 +27577,7 @@ pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27586,7 +27586,7 @@ pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27595,7 +27595,7 @@ pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27604,7 +27604,7 @@ pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27613,7 +27613,7 @@ pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27622,7 +27622,7 @@ pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27631,7 +27631,7 @@ pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27646,7 +27646,7 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27655,7 +27655,7 @@ pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27664,7 +27664,7 @@ pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27673,7 +27673,7 @@ pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27682,7 +27682,7 @@ pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27697,7 +27697,7 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27706,7 +27706,7 @@ pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27715,7 +27715,7 @@ pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27724,7 +27724,7 @@ pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27733,7 +27733,7 @@ pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27748,7 +27748,7 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27757,7 +27757,7 @@ pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27766,7 +27766,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27776,7 +27776,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27786,7 +27786,7 @@ pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27795,7 +27795,7 @@ pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27804,7 +27804,7 @@ pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27813,7 +27813,7 @@ pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27822,7 +27822,7 @@ pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27831,7 +27831,7 @@ pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27840,7 +27840,7 @@ pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27849,7 +27849,7 @@ pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27858,7 +27858,7 @@ pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27867,7 +27867,7 @@ pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27882,7 +27882,7 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27891,7 +27891,7 @@ pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27900,7 +27900,7 @@ pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27909,7 +27909,7 @@ pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27918,7 +27918,7 @@ pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27933,7 +27933,7 @@ pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27942,7 +27942,7 @@ pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27951,7 +27951,7 @@ pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27960,7 +27960,7 @@ pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27969,7 +27969,7 @@ pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27984,7 +27984,7 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27993,7 +27993,7 @@ pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -28002,7 +28002,7 @@ pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28015,7 +28015,7 @@ pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28028,7 +28028,7 @@ pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28041,7 +28041,7 @@ pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28054,7 +28054,7 @@ pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28067,7 +28067,7 @@ pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28080,7 +28080,7 @@ pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28089,7 +28089,7 @@ pub fn vtstd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare bitwise test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28098,7 +28098,7 @@ pub fn vtstd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28114,7 +28114,7 @@ pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28130,7 +28130,7 @@ pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28146,7 +28146,7 @@ pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28162,7 +28162,7 @@ pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28178,7 +28178,7 @@ pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28194,7 +28194,7 @@ pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28210,7 +28210,7 @@ pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28226,7 +28226,7 @@ pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28235,7 +28235,7 @@ pub fn vuqaddb_s8(a: i8, b: u8) -> i8 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28244,7 +28244,7 @@ pub fn vuqaddh_s16(a: i16, b: u16) -> i16 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28260,7 +28260,7 @@ pub fn vuqaddd_s64(a: i64, b: u64) -> i64 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28276,7 +28276,7 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(usdot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -28291,7 +28291,7 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(usdot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -28307,7 +28307,7 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28317,7 +28317,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28327,7 +28327,7 @@ pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28336,7 +28336,7 @@ pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28345,7 +28345,7 @@ pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28354,7 +28354,7 @@ pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28363,7 +28363,7 @@ pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28372,7 +28372,7 @@ pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28381,7 +28381,7 @@ pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28390,7 +28390,7 @@ pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28399,7 +28399,7 @@ pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28408,7 +28408,7 @@ pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28423,7 +28423,7 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28432,7 +28432,7 @@ pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28441,7 +28441,7 @@ pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28450,7 +28450,7 @@ pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28459,7 +28459,7 @@ pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28474,7 +28474,7 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28483,7 +28483,7 @@ pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28492,7 +28492,7 @@ pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28501,7 +28501,7 @@ pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28510,7 +28510,7 @@ pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28525,7 +28525,7 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28534,7 +28534,7 @@ pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28543,7 +28543,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28553,7 +28553,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28563,7 +28563,7 @@ pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28572,7 +28572,7 @@ pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28581,7 +28581,7 @@ pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28590,7 +28590,7 @@ pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28599,7 +28599,7 @@ pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28608,7 +28608,7 @@ pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28617,7 +28617,7 @@ pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28626,7 +28626,7 @@ pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28635,7 +28635,7 @@ pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28644,7 +28644,7 @@ pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28659,7 +28659,7 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28668,7 +28668,7 @@ pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28677,7 +28677,7 @@ pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28686,7 +28686,7 @@ pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28695,7 +28695,7 @@ pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28710,7 +28710,7 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28719,7 +28719,7 @@ pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28728,7 +28728,7 @@ pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28737,7 +28737,7 @@ pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28746,7 +28746,7 @@ pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28761,7 +28761,7 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28770,7 +28770,7 @@ pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28779,7 +28779,7 @@ pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Exclusive OR and rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(xar, IMM6 = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -28797,7 +28797,7 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28807,7 +28807,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28817,7 +28817,7 @@ pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28826,7 +28826,7 @@ pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28835,7 +28835,7 @@ pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28844,7 +28844,7 @@ pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28853,7 +28853,7 @@ pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28868,7 +28868,7 @@ pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28877,7 +28877,7 @@ pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28886,7 +28886,7 @@ pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28895,7 +28895,7 @@ pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28904,7 +28904,7 @@ pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28913,7 +28913,7 @@ pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28922,7 +28922,7 @@ pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28937,7 +28937,7 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28946,7 +28946,7 @@ pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28955,7 +28955,7 @@ pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28964,7 +28964,7 @@ pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28973,7 +28973,7 @@ pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28982,7 +28982,7 @@ pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28991,7 +28991,7 @@ pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29006,7 +29006,7 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29015,7 +29015,7 @@ pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29024,7 +29024,7 @@ pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29033,7 +29033,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -29043,7 +29043,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -29053,7 +29053,7 @@ pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29062,7 +29062,7 @@ pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29071,7 +29071,7 @@ pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29080,7 +29080,7 @@ pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29089,7 +29089,7 @@ pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29104,7 +29104,7 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29113,7 +29113,7 @@ pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29122,7 +29122,7 @@ pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29131,7 +29131,7 @@ pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29140,7 +29140,7 @@ pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29149,7 +29149,7 @@ pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29158,7 +29158,7 @@ pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29173,7 +29173,7 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29182,7 +29182,7 @@ pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29191,7 +29191,7 @@ pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29200,7 +29200,7 @@ pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29209,7 +29209,7 @@ pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29218,7 +29218,7 @@ pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29227,7 +29227,7 @@ pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29242,7 +29242,7 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29251,7 +29251,7 @@ pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29260,7 +29260,7 @@ pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 0aeb740efc..324ff73f62 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "CRC32 single round checksum for bytes (8 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32b))]
@@ -39,7 +39,7 @@ pub fn __crc32b(crc: u32, data: u8) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (8 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32cb))]
@@ -64,7 +64,7 @@ pub fn __crc32cb(crc: u32, data: u8) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(crc32cw))]
@@ -83,7 +83,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (16 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32ch))]
@@ -108,7 +108,7 @@ pub fn __crc32ch(crc: u32, data: u16) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (32 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32cw))]
@@ -133,7 +133,7 @@ pub fn __crc32cw(crc: u32, data: u32) -> u32 {
 }
 #[doc = "CRC32 single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(crc32w))]
@@ -152,7 +152,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32 single round checksum for bytes (16 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32h))]
@@ -177,7 +177,7 @@ pub fn __crc32h(crc: u32, data: u16) -> u32 {
 }
 #[doc = "CRC32 single round checksum for bytes (32 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32w))]
@@ -202,7 +202,7 @@ pub fn __crc32w(crc: u32, data: u32) -> u32 {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -220,7 +220,7 @@ fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -238,7 +238,7 @@ fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -256,7 +256,7 @@ fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -274,7 +274,7 @@ fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -292,7 +292,7 @@ fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -310,7 +310,7 @@ fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -328,7 +328,7 @@ fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -346,7 +346,7 @@ fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -364,7 +364,7 @@ fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -382,7 +382,7 @@ fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -400,7 +400,7 @@ fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -418,7 +418,7 @@ fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
@@ -439,7 +439,7 @@ pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
@@ -460,7 +460,7 @@ pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
@@ -481,7 +481,7 @@ pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
@@ -502,7 +502,7 @@ pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
@@ -523,7 +523,7 @@ pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
@@ -544,7 +544,7 @@ pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
@@ -569,7 +569,7 @@ pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
@@ -594,7 +594,7 @@ pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
@@ -619,7 +619,7 @@ pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
@@ -641,7 +641,7 @@ pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
@@ -663,7 +663,7 @@ pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
@@ -685,7 +685,7 @@ pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
@@ -706,7 +706,7 @@ pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
@@ -727,7 +727,7 @@ pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
@@ -748,7 +748,7 @@ pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
@@ -769,7 +769,7 @@ pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
@@ -790,7 +790,7 @@ pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
@@ -811,7 +811,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
 #[cfg_attr(
@@ -841,7 +841,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
 #[cfg_attr(
@@ -871,7 +871,7 @@ pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
@@ -900,7 +900,7 @@ pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
@@ -929,7 +929,7 @@ pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
@@ -958,7 +958,7 @@ pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
@@ -987,7 +987,7 @@ pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
@@ -1016,7 +1016,7 @@ pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
@@ -1045,7 +1045,7 @@ pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
@@ -1074,7 +1074,7 @@ pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
@@ -1103,7 +1103,7 @@ pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
@@ -1132,7 +1132,7 @@ pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
@@ -1161,7 +1161,7 @@ pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
@@ -1190,7 +1190,7 @@ pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
@@ -1219,7 +1219,7 @@ pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
@@ -1248,7 +1248,7 @@ pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
@@ -1277,7 +1277,7 @@ pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
@@ -1301,7 +1301,7 @@ pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
@@ -1325,7 +1325,7 @@ pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
@@ -1349,7 +1349,7 @@ pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
@@ -1370,7 +1370,7 @@ pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
@@ -1391,7 +1391,7 @@ pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
@@ -1412,7 +1412,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1434,7 +1434,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1456,7 +1456,7 @@ pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1477,7 +1477,7 @@ pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1498,7 +1498,7 @@ pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1523,7 +1523,7 @@ pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1548,7 +1548,7 @@ pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1573,7 +1573,7 @@ pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1598,7 +1598,7 @@ pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1623,7 +1623,7 @@ pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1648,7 +1648,7 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1663,7 +1663,7 @@ pub fn vabsh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -1685,7 +1685,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -1707,7 +1707,7 @@ pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1728,7 +1728,7 @@ pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1749,7 +1749,7 @@ pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1770,7 +1770,7 @@ pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1791,7 +1791,7 @@ pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1812,7 +1812,7 @@ pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1833,7 +1833,7 @@ pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1854,7 +1854,7 @@ pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1875,7 +1875,7 @@ pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1896,7 +1896,7 @@ pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1917,7 +1917,7 @@ pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1938,7 +1938,7 @@ pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1959,7 +1959,7 @@ pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1980,7 +1980,7 @@ pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2001,7 +2001,7 @@ pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2022,7 +2022,7 @@ pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2043,7 +2043,7 @@ pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2064,7 +2064,7 @@ pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2085,7 +2085,7 @@ pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2106,7 +2106,7 @@ pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2127,7 +2127,7 @@ pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2148,7 +2148,7 @@ pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2169,7 +2169,7 @@ pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -2184,7 +2184,7 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2208,7 +2208,7 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2232,7 +2232,7 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2256,7 +2256,7 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2280,7 +2280,7 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2304,7 +2304,7 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2328,7 +2328,7 @@ pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2349,7 +2349,7 @@ pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2370,7 +2370,7 @@ pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2391,7 +2391,7 @@ pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2412,7 +2412,7 @@ pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2433,7 +2433,7 @@ pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2454,7 +2454,7 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2481,7 +2481,7 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2508,7 +2508,7 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2535,7 +2535,7 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2562,7 +2562,7 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2589,7 +2589,7 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2616,7 +2616,7 @@ pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2641,7 +2641,7 @@ pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2666,7 +2666,7 @@ pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2691,7 +2691,7 @@ pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2716,7 +2716,7 @@ pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2741,7 +2741,7 @@ pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2766,7 +2766,7 @@ pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2787,7 +2787,7 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2812,7 +2812,7 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2837,7 +2837,7 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2862,7 +2862,7 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2887,7 +2887,7 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2912,7 +2912,7 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2937,7 +2937,7 @@ pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2961,7 +2961,7 @@ pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2985,7 +2985,7 @@ pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3009,7 +3009,7 @@ pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3033,7 +3033,7 @@ pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3057,7 +3057,7 @@ pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3081,7 +3081,7 @@ pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "AES single round encryption."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesd))]
@@ -3106,7 +3106,7 @@ pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES single round encryption."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aese))]
@@ -3131,7 +3131,7 @@ pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES inverse mix columns."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesimc))]
@@ -3156,7 +3156,7 @@ pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES mix columns."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesmc))]
@@ -3181,7 +3181,7 @@ pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3202,7 +3202,7 @@ pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3223,7 +3223,7 @@ pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3244,7 +3244,7 @@ pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3265,7 +3265,7 @@ pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3286,7 +3286,7 @@ pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3307,7 +3307,7 @@ pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3328,7 +3328,7 @@ pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3349,7 +3349,7 @@ pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3370,7 +3370,7 @@ pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3391,7 +3391,7 @@ pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3412,7 +3412,7 @@ pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3433,7 +3433,7 @@ pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3454,7 +3454,7 @@ pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3475,7 +3475,7 @@ pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3496,7 +3496,7 @@ pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3517,7 +3517,7 @@ pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3539,7 +3539,7 @@ pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3561,7 +3561,7 @@ pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3583,7 +3583,7 @@ pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3605,7 +3605,7 @@ pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3627,7 +3627,7 @@ pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3649,7 +3649,7 @@ pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3671,7 +3671,7 @@ pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3693,7 +3693,7 @@ pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3715,7 +3715,7 @@ pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3737,7 +3737,7 @@ pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3759,7 +3759,7 @@ pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3781,7 +3781,7 @@ pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3803,7 +3803,7 @@ pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3825,7 +3825,7 @@ pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3847,7 +3847,7 @@ pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3869,7 +3869,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3897,7 +3897,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3925,7 +3925,7 @@ pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3952,7 +3952,7 @@ pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3979,7 +3979,7 @@ pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4006,7 +4006,7 @@ pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4033,7 +4033,7 @@ pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4060,7 +4060,7 @@ pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4087,7 +4087,7 @@ pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4114,7 +4114,7 @@ pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4141,7 +4141,7 @@ pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4168,7 +4168,7 @@ pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4195,7 +4195,7 @@ pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4222,7 +4222,7 @@ pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4249,7 +4249,7 @@ pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4276,7 +4276,7 @@ pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4303,7 +4303,7 @@ pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4330,7 +4330,7 @@ pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4357,7 +4357,7 @@ pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4384,7 +4384,7 @@ pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4411,7 +4411,7 @@ pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4438,7 +4438,7 @@ pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4465,7 +4465,7 @@ pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4492,7 +4492,7 @@ pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4519,7 +4519,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4549,7 +4549,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4579,7 +4579,7 @@ pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4608,7 +4608,7 @@ pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4637,7 +4637,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4667,7 +4667,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4697,7 +4697,7 @@ pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4726,7 +4726,7 @@ pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4755,7 +4755,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4777,7 +4777,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4799,7 +4799,7 @@ pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4820,7 +4820,7 @@ pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4841,7 +4841,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4863,7 +4863,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4885,7 +4885,7 @@ pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4906,7 +4906,7 @@ pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4927,7 +4927,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
 #[cfg_attr(
@@ -4949,7 +4949,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
 #[cfg_attr(
@@ -4971,7 +4971,7 @@ pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
@@ -4992,7 +4992,7 @@ pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
@@ -5013,7 +5013,7 @@ pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5034,7 +5034,7 @@ pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5055,7 +5055,7 @@ pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5076,7 +5076,7 @@ pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5097,7 +5097,7 @@ pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5118,7 +5118,7 @@ pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5139,7 +5139,7 @@ pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5160,7 +5160,7 @@ pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5181,7 +5181,7 @@ pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5202,7 +5202,7 @@ pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5223,7 +5223,7 @@ pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5244,7 +5244,7 @@ pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5265,7 +5265,7 @@ pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5286,7 +5286,7 @@ pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5307,7 +5307,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5329,7 +5329,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5351,7 +5351,7 @@ pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -5372,7 +5372,7 @@ pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -5393,7 +5393,7 @@ pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -5414,7 +5414,7 @@ pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -5435,7 +5435,7 @@ pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -5456,7 +5456,7 @@ pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -5477,7 +5477,7 @@ pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -5498,7 +5498,7 @@ pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -5519,7 +5519,7 @@ pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -5540,7 +5540,7 @@ pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -5561,7 +5561,7 @@ pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -5582,7 +5582,7 @@ pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -5603,7 +5603,7 @@ pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -5624,7 +5624,7 @@ pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -5645,7 +5645,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5668,7 +5668,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5691,7 +5691,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -5713,7 +5713,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -5735,7 +5735,7 @@ pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -5756,7 +5756,7 @@ pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -5777,7 +5777,7 @@ pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -5798,7 +5798,7 @@ pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -5819,7 +5819,7 @@ pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -5840,7 +5840,7 @@ pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -5861,7 +5861,7 @@ pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -5882,7 +5882,7 @@ pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -5903,7 +5903,7 @@ pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -5924,7 +5924,7 @@ pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -5945,7 +5945,7 @@ pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -5966,7 +5966,7 @@ pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -5987,7 +5987,7 @@ pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -6008,7 +6008,7 @@ pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -6029,7 +6029,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6052,7 +6052,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6075,7 +6075,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -6097,7 +6097,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -6119,7 +6119,7 @@ pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -6140,7 +6140,7 @@ pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -6161,7 +6161,7 @@ pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -6182,7 +6182,7 @@ pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -6203,7 +6203,7 @@ pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -6224,7 +6224,7 @@ pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -6245,7 +6245,7 @@ pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -6266,7 +6266,7 @@ pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -6287,7 +6287,7 @@ pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -6308,7 +6308,7 @@ pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -6329,7 +6329,7 @@ pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -6350,7 +6350,7 @@ pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -6371,7 +6371,7 @@ pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -6392,7 +6392,7 @@ pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -6413,7 +6413,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
 #[cfg_attr(
@@ -6436,7 +6436,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
 #[cfg_attr(
@@ -6459,7 +6459,7 @@ pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
@@ -6488,7 +6488,7 @@ pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
@@ -6517,7 +6517,7 @@ pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
@@ -6546,7 +6546,7 @@ pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
@@ -6575,7 +6575,7 @@ pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
@@ -6604,7 +6604,7 @@ pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
@@ -6633,7 +6633,7 @@ pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6654,7 +6654,7 @@ pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6675,7 +6675,7 @@ pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6696,7 +6696,7 @@ pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6717,7 +6717,7 @@ pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6738,7 +6738,7 @@ pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6759,7 +6759,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6781,7 +6781,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6803,7 +6803,7 @@ pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -6824,7 +6824,7 @@ pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -6845,7 +6845,7 @@ pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -6866,7 +6866,7 @@ pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -6887,7 +6887,7 @@ pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -6908,7 +6908,7 @@ pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -6929,7 +6929,7 @@ pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -6950,7 +6950,7 @@ pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -6971,7 +6971,7 @@ pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -6992,7 +6992,7 @@ pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -7013,7 +7013,7 @@ pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -7034,7 +7034,7 @@ pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -7055,7 +7055,7 @@ pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -7076,7 +7076,7 @@ pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -7097,7 +7097,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
 #[cfg_attr(
@@ -7120,7 +7120,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
 #[cfg_attr(
@@ -7143,7 +7143,7 @@ pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7164,7 +7164,7 @@ pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7185,7 +7185,7 @@ pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7206,7 +7206,7 @@ pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7227,7 +7227,7 @@ pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7248,7 +7248,7 @@ pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7269,7 +7269,7 @@ pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7291,7 +7291,7 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7317,7 +7317,7 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7339,7 +7339,7 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7365,7 +7365,7 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7387,7 +7387,7 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7413,7 +7413,7 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7435,7 +7435,7 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7461,7 +7461,7 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7483,7 +7483,7 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7509,7 +7509,7 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7531,7 +7531,7 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7562,7 +7562,7 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7583,7 +7583,7 @@ pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7604,7 +7604,7 @@ pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7626,7 +7626,7 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7652,7 +7652,7 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7674,7 +7674,7 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7705,7 +7705,7 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7727,7 +7727,7 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7753,7 +7753,7 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7775,7 +7775,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7806,7 +7806,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -7825,7 +7825,7 @@ pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7842,7 +7842,7 @@ pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7859,7 +7859,7 @@ pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7876,7 +7876,7 @@ pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7893,7 +7893,7 @@ pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7910,7 +7910,7 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7927,7 +7927,7 @@ pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7944,7 +7944,7 @@ pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7961,7 +7961,7 @@ pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7978,7 +7978,7 @@ pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7995,7 +7995,7 @@ pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8012,7 +8012,7 @@ pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8029,7 +8029,7 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8053,7 +8053,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8080,7 +8080,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8102,7 +8102,7 @@ pub fn vcreate_f32(a: u64) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8127,7 +8127,7 @@ pub fn vcreate_f32(a: u64) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8149,7 +8149,7 @@ pub fn vcreate_s8(a: u64) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8174,7 +8174,7 @@ pub fn vcreate_s8(a: u64) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8196,7 +8196,7 @@ pub fn vcreate_s16(a: u64) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8221,7 +8221,7 @@ pub fn vcreate_s16(a: u64) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8243,7 +8243,7 @@ pub fn vcreate_s32(a: u64) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8268,7 +8268,7 @@ pub fn vcreate_s32(a: u64) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8289,7 +8289,7 @@ pub fn vcreate_s64(a: u64) -> int64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8311,7 +8311,7 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8336,7 +8336,7 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8358,7 +8358,7 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8383,7 +8383,7 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8405,7 +8405,7 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8430,7 +8430,7 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8451,7 +8451,7 @@ pub fn vcreate_u64(a: u64) -> uint64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8473,7 +8473,7 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8498,7 +8498,7 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8520,7 +8520,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8545,7 +8545,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8566,7 +8566,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
 }
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8589,7 +8589,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8611,7 +8611,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8633,7 +8633,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8655,7 +8655,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8677,7 +8677,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8700,7 +8700,7 @@ pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8721,7 +8721,7 @@ pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8742,7 +8742,7 @@ pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8763,7 +8763,7 @@ pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8784,7 +8784,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8819,7 +8819,7 @@ pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8854,7 +8854,7 @@ pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8889,7 +8889,7 @@ pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8924,7 +8924,7 @@ pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -8943,7 +8943,7 @@ pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -8962,7 +8962,7 @@ pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
@@ -8981,7 +8981,7 @@ pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
@@ -9000,7 +9000,7 @@ pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9019,7 +9019,7 @@ pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9038,7 +9038,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
@@ -9057,7 +9057,7 @@ pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
@@ -9076,7 +9076,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9111,7 +9111,7 @@ pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9146,7 +9146,7 @@ pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9165,7 +9165,7 @@ pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9184,7 +9184,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
@@ -9203,7 +9203,7 @@ pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
@@ -9222,7 +9222,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9257,7 +9257,7 @@ pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9292,7 +9292,7 @@ pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9311,7 +9311,7 @@ pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9330,7 +9330,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
@@ -9349,7 +9349,7 @@ pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
@@ -9368,7 +9368,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9390,7 +9390,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9412,7 +9412,7 @@ pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9441,7 +9441,7 @@ pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9470,7 +9470,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9492,7 +9492,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9514,7 +9514,7 @@ pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9543,7 +9543,7 @@ pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9572,7 +9572,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9600,7 +9600,7 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9632,7 +9632,7 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9661,7 +9661,7 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9695,7 +9695,7 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9723,7 +9723,7 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9755,7 +9755,7 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9784,7 +9784,7 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9818,7 +9818,7 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
@@ -9847,7 +9847,7 @@ pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
@@ -9876,7 +9876,7 @@ pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
@@ -9905,7 +9905,7 @@ pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
@@ -9934,7 +9934,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -9959,7 +9959,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -9990,7 +9990,7 @@ pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10013,7 +10013,7 @@ pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10036,7 +10036,7 @@ pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10059,7 +10059,7 @@ pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10082,7 +10082,7 @@ pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10105,7 +10105,7 @@ pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10128,7 +10128,7 @@ pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10151,7 +10151,7 @@ pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10174,7 +10174,7 @@ pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10197,7 +10197,7 @@ pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10226,7 +10226,7 @@ pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10255,7 +10255,7 @@ pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10284,7 +10284,7 @@ pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10313,7 +10313,7 @@ pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10342,7 +10342,7 @@ pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10371,7 +10371,7 @@ pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10403,7 +10403,7 @@ pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10435,7 +10435,7 @@ pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10467,7 +10467,7 @@ pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -10490,7 +10490,7 @@ pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -10513,7 +10513,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10538,7 +10538,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10569,7 +10569,7 @@ pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10592,7 +10592,7 @@ pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10615,7 +10615,7 @@ pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10638,7 +10638,7 @@ pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10661,7 +10661,7 @@ pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10684,7 +10684,7 @@ pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10707,7 +10707,7 @@ pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10730,7 +10730,7 @@ pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10753,7 +10753,7 @@ pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10776,7 +10776,7 @@ pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10805,7 +10805,7 @@ pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10834,7 +10834,7 @@ pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10863,7 +10863,7 @@ pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10892,7 +10892,7 @@ pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10921,7 +10921,7 @@ pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10950,7 +10950,7 @@ pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10982,7 +10982,7 @@ pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11014,7 +11014,7 @@ pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11046,7 +11046,7 @@ pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11069,7 +11069,7 @@ pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11092,7 +11092,7 @@ pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11108,7 +11108,7 @@ pub fn vdup_n_f16(a: f16) -> float16x4_t {
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11124,7 +11124,7 @@ pub fn vdupq_n_f16(a: f16) -> float16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11145,7 +11145,7 @@ pub fn vdup_n_f32(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11166,7 +11166,7 @@ pub fn vdup_n_p16(value: p16) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11187,7 +11187,7 @@ pub fn vdup_n_p8(value: p8) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11208,7 +11208,7 @@ pub fn vdup_n_s16(value: i16) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11229,7 +11229,7 @@ pub fn vdup_n_s32(value: i32) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11250,7 +11250,7 @@ pub fn vdup_n_s64(value: i64) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11271,7 +11271,7 @@ pub fn vdup_n_s8(value: i8) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11292,7 +11292,7 @@ pub fn vdup_n_u16(value: u16) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11313,7 +11313,7 @@ pub fn vdup_n_u32(value: u32) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11334,7 +11334,7 @@ pub fn vdup_n_u64(value: u64) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11355,7 +11355,7 @@ pub fn vdup_n_u8(value: u8) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11376,7 +11376,7 @@ pub fn vdupq_n_f32(value: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11397,7 +11397,7 @@ pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11418,7 +11418,7 @@ pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11439,7 +11439,7 @@ pub fn vdupq_n_s16(value: i16) -> int16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11460,7 +11460,7 @@ pub fn vdupq_n_s32(value: i32) -> int32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11481,7 +11481,7 @@ pub fn vdupq_n_s64(value: i64) -> int64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11502,7 +11502,7 @@ pub fn vdupq_n_s8(value: i8) -> int8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11523,7 +11523,7 @@ pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11544,7 +11544,7 @@ pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11565,7 +11565,7 @@ pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11586,7 +11586,7 @@ pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11607,7 +11607,7 @@ fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11628,7 +11628,7 @@ fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
@@ -11651,7 +11651,7 @@ pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
@@ -11674,7 +11674,7 @@ pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11697,7 +11697,7 @@ pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11720,7 +11720,7 @@ pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11741,7 +11741,7 @@ pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11762,7 +11762,7 @@ pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11783,7 +11783,7 @@ pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11804,7 +11804,7 @@ pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11825,7 +11825,7 @@ pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11846,7 +11846,7 @@ pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11867,7 +11867,7 @@ pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11888,7 +11888,7 @@ pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11909,7 +11909,7 @@ pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11930,7 +11930,7 @@ pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11951,7 +11951,7 @@ pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11972,7 +11972,7 @@ pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11993,7 +11993,7 @@ pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12014,7 +12014,7 @@ pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12035,7 +12035,7 @@ pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12056,7 +12056,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
 #[cfg_attr(
@@ -12088,7 +12088,7 @@ pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12117,7 +12117,7 @@ pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12146,7 +12146,7 @@ pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12177,7 +12177,7 @@ pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -12202,7 +12202,7 @@ pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -12225,7 +12225,7 @@ pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12260,7 +12260,7 @@ pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12295,7 +12295,7 @@ pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12330,7 +12330,7 @@ pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12365,7 +12365,7 @@ pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12400,7 +12400,7 @@ pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12435,7 +12435,7 @@ pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
 #[cfg_attr(
@@ -12471,7 +12471,7 @@ pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12502,7 +12502,7 @@ pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12533,7 +12533,7 @@ pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12564,7 +12564,7 @@ pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12595,7 +12595,7 @@ pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12626,7 +12626,7 @@ pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12657,7 +12657,7 @@ pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -12686,7 +12686,7 @@ pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -12715,7 +12715,7 @@ pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -12818,7 +12818,7 @@ pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -12921,7 +12921,7 @@ pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -13024,7 +13024,7 @@ pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
 #[cfg_attr(
@@ -13046,7 +13046,7 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
 #[cfg_attr(
@@ -13068,7 +13068,7 @@ pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13089,7 +13089,7 @@ pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13110,7 +13110,7 @@ pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13131,7 +13131,7 @@ pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13152,7 +13152,7 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -13178,7 +13178,7 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -13204,7 +13204,7 @@ pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13228,7 +13228,7 @@ pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13252,7 +13252,7 @@ pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13273,7 +13273,7 @@ pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13294,7 +13294,7 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -13313,7 +13313,7 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -13332,7 +13332,7 @@ pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13353,7 +13353,7 @@ pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13374,7 +13374,7 @@ pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13395,7 +13395,7 @@ pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13416,7 +13416,7 @@ pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13437,7 +13437,7 @@ pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13458,7 +13458,7 @@ pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13479,7 +13479,7 @@ pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13500,7 +13500,7 @@ pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13521,7 +13521,7 @@ pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13542,7 +13542,7 @@ pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13563,7 +13563,7 @@ pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -13581,7 +13581,7 @@ pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
 }
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -13599,7 +13599,7 @@ pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13618,7 +13618,7 @@ pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13637,7 +13637,7 @@ pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13656,7 +13656,7 @@ pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13675,7 +13675,7 @@ pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13694,7 +13694,7 @@ pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13713,7 +13713,7 @@ pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13732,7 +13732,7 @@ pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13751,7 +13751,7 @@ pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13770,7 +13770,7 @@ pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13789,7 +13789,7 @@ pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13808,7 +13808,7 @@ pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13827,7 +13827,7 @@ pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13846,7 +13846,7 @@ pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13865,7 +13865,7 @@ pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13884,7 +13884,7 @@ pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13903,7 +13903,7 @@ pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13922,7 +13922,7 @@ pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13941,7 +13941,7 @@ pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13960,7 +13960,7 @@ pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13979,7 +13979,7 @@ pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13998,7 +13998,7 @@ pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14017,7 +14017,7 @@ pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14036,7 +14036,7 @@ pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14055,7 +14055,7 @@ pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14072,7 +14072,7 @@ pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14089,7 +14089,7 @@ pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14106,7 +14106,7 @@ pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14123,7 +14123,7 @@ pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14140,7 +14140,7 @@ pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14157,7 +14157,7 @@ pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14174,7 +14174,7 @@ pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14191,7 +14191,7 @@ pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14208,7 +14208,7 @@ pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14225,7 +14225,7 @@ pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14242,7 +14242,7 @@ pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
@@ -14271,7 +14271,7 @@ pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
@@ -14300,7 +14300,7 @@ pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
@@ -14329,7 +14329,7 @@ pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
@@ -14358,7 +14358,7 @@ pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
@@ -14387,7 +14387,7 @@ pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
@@ -14416,7 +14416,7 @@ pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
@@ -14445,7 +14445,7 @@ pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
@@ -14474,7 +14474,7 @@ pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
@@ -14503,7 +14503,7 @@ pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
@@ -14532,7 +14532,7 @@ pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
@@ -14561,7 +14561,7 @@ pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
@@ -14590,7 +14590,7 @@ pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
@@ -14619,7 +14619,7 @@ pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
@@ -14648,7 +14648,7 @@ pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
@@ -14677,7 +14677,7 @@ pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
@@ -14706,7 +14706,7 @@ pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
@@ -14735,7 +14735,7 @@ pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
@@ -14764,7 +14764,7 @@ pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
@@ -14793,7 +14793,7 @@ pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
@@ -14822,7 +14822,7 @@ pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
@@ -14851,7 +14851,7 @@ pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
@@ -14880,7 +14880,7 @@ pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
@@ -14909,7 +14909,7 @@ pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
@@ -14940,7 +14940,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -14959,7 +14959,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -14978,7 +14978,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15001,7 +15001,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15024,7 +15024,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15047,7 +15047,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15070,7 +15070,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15093,7 +15093,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15116,7 +15116,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15139,7 +15139,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15162,7 +15162,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15185,7 +15185,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15208,7 +15208,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15231,7 +15231,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15254,7 +15254,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15277,7 +15277,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15300,7 +15300,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
@@ -15323,7 +15323,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15346,7 +15346,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15369,7 +15369,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15392,7 +15392,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
@@ -15415,7 +15415,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15438,7 +15438,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15470,7 +15470,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15502,7 +15502,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15534,7 +15534,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15552,7 +15552,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15571,7 +15571,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15589,7 +15589,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15608,7 +15608,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15634,7 +15634,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15660,7 +15660,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15686,7 +15686,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15712,7 +15712,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15738,7 +15738,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15764,7 +15764,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15777,7 +15777,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15790,7 +15790,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15803,7 +15803,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15816,7 +15816,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15829,7 +15829,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15842,7 +15842,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15855,7 +15855,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15868,7 +15868,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15881,7 +15881,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15894,7 +15894,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15907,7 +15907,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15920,7 +15920,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15933,7 +15933,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15946,7 +15946,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15959,7 +15959,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15990,7 +15990,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16021,7 +16021,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16052,7 +16052,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16083,7 +16083,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16114,7 +16114,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16145,7 +16145,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
@@ -16165,7 +16165,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
@@ -16185,7 +16185,7 @@ pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16210,7 +16210,7 @@ pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16235,7 +16235,7 @@ pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16260,7 +16260,7 @@ pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16285,7 +16285,7 @@ pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16310,7 +16310,7 @@ pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16335,7 +16335,7 @@ pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16360,7 +16360,7 @@ pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16385,7 +16385,7 @@ pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16410,7 +16410,7 @@ pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16435,7 +16435,7 @@ pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16460,7 +16460,7 @@ pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16485,7 +16485,7 @@ pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16510,7 +16510,7 @@ pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16535,7 +16535,7 @@ pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16560,7 +16560,7 @@ pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16585,7 +16585,7 @@ pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16610,7 +16610,7 @@ pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16635,7 +16635,7 @@ pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16660,7 +16660,7 @@ pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16685,7 +16685,7 @@ pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16710,7 +16710,7 @@ pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16735,7 +16735,7 @@ pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16760,7 +16760,7 @@ pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16785,7 +16785,7 @@ pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16803,7 +16803,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16826,7 +16826,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16849,7 +16849,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16872,7 +16872,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16896,7 +16896,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16923,7 +16923,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16947,7 +16947,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16975,7 +16975,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16999,7 +16999,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17028,7 +17028,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17041,7 +17041,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17054,7 +17054,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17067,7 +17067,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17080,7 +17080,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17093,7 +17093,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17106,7 +17106,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17119,7 +17119,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17132,7 +17132,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17163,7 +17163,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17194,7 +17194,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17225,7 +17225,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17256,7 +17256,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17287,7 +17287,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17318,7 +17318,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17349,7 +17349,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17380,7 +17380,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17411,7 +17411,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17442,7 +17442,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17473,7 +17473,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17504,7 +17504,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17535,7 +17535,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17566,7 +17566,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17597,7 +17597,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17628,7 +17628,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17659,7 +17659,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17690,7 +17690,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17721,7 +17721,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17752,7 +17752,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17783,7 +17783,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17814,7 +17814,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17845,7 +17845,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17876,7 +17876,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17900,7 +17900,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17927,7 +17927,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17951,7 +17951,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17979,7 +17979,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18003,7 +18003,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18032,7 +18032,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18056,7 +18056,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18095,7 +18095,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18119,7 +18119,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18165,7 +18165,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18189,7 +18189,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18242,7 +18242,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18266,7 +18266,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18293,7 +18293,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18317,7 +18317,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18345,7 +18345,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18369,7 +18369,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18398,7 +18398,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18422,7 +18422,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18449,7 +18449,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18473,7 +18473,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18501,7 +18501,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18525,7 +18525,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18554,7 +18554,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18578,7 +18578,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18605,7 +18605,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18629,7 +18629,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18657,7 +18657,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18681,7 +18681,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18710,7 +18710,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18734,7 +18734,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18761,7 +18761,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18785,7 +18785,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18813,7 +18813,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18837,7 +18837,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18866,7 +18866,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18889,7 +18889,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18912,7 +18912,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18935,7 +18935,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18959,7 +18959,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18986,7 +18986,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19010,7 +19010,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19038,7 +19038,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19062,7 +19062,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19091,7 +19091,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19115,7 +19115,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19142,7 +19142,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19166,7 +19166,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19194,7 +19194,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19218,7 +19218,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19247,7 +19247,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19271,7 +19271,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19310,7 +19310,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19334,7 +19334,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19380,7 +19380,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19404,7 +19404,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19457,7 +19457,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19481,7 +19481,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19508,7 +19508,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19532,7 +19532,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19560,7 +19560,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19584,7 +19584,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19613,7 +19613,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19637,7 +19637,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19664,7 +19664,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19688,7 +19688,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19716,7 +19716,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19740,7 +19740,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19765,7 +19765,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
     ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
     ret_val
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19778,7 +19778,7 @@ unsafe fn vld1_v1i64<const ALIGN: i32>(a: *const i8) -> int64x1_t {
     }
     _vld1_v1i64(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19791,7 +19791,7 @@ unsafe fn vld1_v2f32<const ALIGN: i32>(a: *const i8) -> float32x2_t {
     }
     _vld1_v2f32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19804,7 +19804,7 @@ unsafe fn vld1_v2i32<const ALIGN: i32>(a: *const i8) -> int32x2_t {
     }
     _vld1_v2i32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19817,7 +19817,7 @@ unsafe fn vld1_v4i16<const ALIGN: i32>(a: *const i8) -> int16x4_t {
     }
     _vld1_v4i16(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19830,7 +19830,7 @@ unsafe fn vld1_v8i8<const ALIGN: i32>(a: *const i8) -> int8x8_t {
     }
     _vld1_v8i8(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19843,7 +19843,7 @@ unsafe fn vld1q_v16i8<const ALIGN: i32>(a: *const i8) -> int8x16_t {
     }
     _vld1q_v16i8(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19856,7 +19856,7 @@ unsafe fn vld1q_v2i64<const ALIGN: i32>(a: *const i8) -> int64x2_t {
     }
     _vld1q_v2i64(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19869,7 +19869,7 @@ unsafe fn vld1q_v4f32<const ALIGN: i32>(a: *const i8) -> float32x4_t {
     }
     _vld1q_v4f32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19882,7 +19882,7 @@ unsafe fn vld1q_v4i32<const ALIGN: i32>(a: *const i8) -> int32x4_t {
     }
     _vld1q_v4i32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19895,7 +19895,7 @@ unsafe fn vld1q_v8i16<const ALIGN: i32>(a: *const i8) -> int16x8_t {
     }
     _vld1q_v8i16(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -19909,7 +19909,7 @@ unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
     }
     _vld1_v4f16(a, b)
 }
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -19927,7 +19927,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -19951,7 +19951,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -19970,7 +19970,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -19989,7 +19989,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20013,7 +20013,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20037,7 +20037,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20053,7 +20053,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20069,7 +20069,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20085,7 +20085,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20101,7 +20101,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20117,7 +20117,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20133,7 +20133,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20149,7 +20149,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20165,7 +20165,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20184,7 +20184,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20203,7 +20203,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20222,7 +20222,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20241,7 +20241,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20260,7 +20260,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20279,7 +20279,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20298,7 +20298,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20317,7 +20317,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -20340,7 +20340,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20356,7 +20356,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20375,7 +20375,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -20398,7 +20398,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20422,7 +20422,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20449,7 +20449,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20473,7 +20473,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20512,7 +20512,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20536,7 +20536,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20563,7 +20563,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20587,7 +20587,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20614,7 +20614,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20638,7 +20638,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20665,7 +20665,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20689,7 +20689,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20716,7 +20716,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20740,7 +20740,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20767,7 +20767,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20791,7 +20791,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20830,7 +20830,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20854,7 +20854,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20881,7 +20881,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20905,7 +20905,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20932,7 +20932,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -20951,7 +20951,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -20970,7 +20970,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20994,7 +20994,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21018,7 +21018,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21034,7 +21034,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21050,7 +21050,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21066,7 +21066,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21082,7 +21082,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21098,7 +21098,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21114,7 +21114,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21130,7 +21130,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21146,7 +21146,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21165,7 +21165,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21184,7 +21184,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21203,7 +21203,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21222,7 +21222,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21241,7 +21241,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21260,7 +21260,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21279,7 +21279,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21298,7 +21298,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21324,7 +21324,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21350,7 +21350,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21377,7 +21377,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21408,7 +21408,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21429,7 +21429,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21451,7 +21451,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21472,7 +21472,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21493,7 +21493,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21514,7 +21514,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21535,7 +21535,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21556,7 +21556,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21580,7 +21580,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21604,7 +21604,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21628,7 +21628,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21652,7 +21652,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21671,7 +21671,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21695,7 +21695,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21719,7 +21719,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21744,7 +21744,7 @@ pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21769,7 +21769,7 @@ pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21794,7 +21794,7 @@ pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21819,7 +21819,7 @@ pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21844,7 +21844,7 @@ pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21869,7 +21869,7 @@ pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21894,7 +21894,7 @@ pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21919,7 +21919,7 @@ pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -21942,7 +21942,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21958,7 +21958,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21977,7 +21977,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22000,7 +22000,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22024,7 +22024,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22051,7 +22051,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22075,7 +22075,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22114,7 +22114,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22138,7 +22138,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22165,7 +22165,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22189,7 +22189,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22216,7 +22216,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22240,7 +22240,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22267,7 +22267,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22291,7 +22291,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22318,7 +22318,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22342,7 +22342,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22369,7 +22369,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22393,7 +22393,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22432,7 +22432,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22456,7 +22456,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22483,7 +22483,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22507,7 +22507,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22534,7 +22534,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -22553,7 +22553,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -22572,7 +22572,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -22596,7 +22596,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -22620,7 +22620,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22639,7 +22639,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22658,7 +22658,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22677,7 +22677,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22696,7 +22696,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22715,7 +22715,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22734,7 +22734,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22753,7 +22753,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22772,7 +22772,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22791,7 +22791,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22807,7 +22807,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22823,7 +22823,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22839,7 +22839,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22855,7 +22855,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22871,7 +22871,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22887,7 +22887,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22903,7 +22903,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22919,7 +22919,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22942,7 +22942,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22958,7 +22958,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22981,7 +22981,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23005,7 +23005,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23033,7 +23033,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23057,7 +23057,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23103,7 +23103,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23127,7 +23127,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23155,7 +23155,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23179,7 +23179,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23207,7 +23207,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23231,7 +23231,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23259,7 +23259,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23283,7 +23283,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23311,7 +23311,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23335,7 +23335,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23363,7 +23363,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23387,7 +23387,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23433,7 +23433,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23457,7 +23457,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23485,7 +23485,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23509,7 +23509,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23537,7 +23537,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -23556,7 +23556,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -23575,7 +23575,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -23599,7 +23599,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -23623,7 +23623,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23642,7 +23642,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23661,7 +23661,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23680,7 +23680,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23699,7 +23699,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23718,7 +23718,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23737,7 +23737,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23756,7 +23756,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23775,7 +23775,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23791,7 +23791,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23807,7 +23807,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23823,7 +23823,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23839,7 +23839,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23855,7 +23855,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23871,7 +23871,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23887,7 +23887,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23903,7 +23903,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -23930,7 +23930,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -23957,7 +23957,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -23989,7 +23989,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -24021,7 +24021,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24048,7 +24048,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24075,7 +24075,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24100,7 +24100,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24127,7 +24127,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24154,7 +24154,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24181,7 +24181,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24208,7 +24208,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24235,7 +24235,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24260,7 +24260,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24285,7 +24285,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24310,7 +24310,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24335,7 +24335,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24360,7 +24360,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24385,7 +24385,7 @@ pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24410,7 +24410,7 @@ pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24435,7 +24435,7 @@ pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24460,7 +24460,7 @@ pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24485,7 +24485,7 @@ pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24510,7 +24510,7 @@ pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24535,7 +24535,7 @@ pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24560,7 +24560,7 @@ pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -24583,7 +24583,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -24602,7 +24602,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24618,7 +24618,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -24641,7 +24641,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24665,7 +24665,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24693,7 +24693,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24717,7 +24717,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24763,7 +24763,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24787,7 +24787,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24815,7 +24815,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24839,7 +24839,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24867,7 +24867,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24891,7 +24891,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24919,7 +24919,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24943,7 +24943,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24971,7 +24971,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24995,7 +24995,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25023,7 +25023,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25047,7 +25047,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25093,7 +25093,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25117,7 +25117,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25145,7 +25145,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25169,7 +25169,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25197,7 +25197,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -25222,7 +25222,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25240,7 +25240,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25258,7 +25258,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -25281,7 +25281,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -25304,7 +25304,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25320,7 +25320,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25336,7 +25336,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25352,7 +25352,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25368,7 +25368,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25384,7 +25384,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25400,7 +25400,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25416,7 +25416,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25432,7 +25432,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25451,7 +25451,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25470,7 +25470,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25489,7 +25489,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25508,7 +25508,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25527,7 +25527,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25546,7 +25546,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25565,7 +25565,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25584,7 +25584,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25603,7 +25603,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25626,7 +25626,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -25642,7 +25642,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25665,7 +25665,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25689,7 +25689,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25718,7 +25718,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25742,7 +25742,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25795,7 +25795,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25819,7 +25819,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25848,7 +25848,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25872,7 +25872,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25901,7 +25901,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25925,7 +25925,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25954,7 +25954,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25978,7 +25978,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26007,7 +26007,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26031,7 +26031,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26060,7 +26060,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26084,7 +26084,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26137,7 +26137,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26161,7 +26161,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26190,7 +26190,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26214,7 +26214,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26243,7 +26243,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26261,7 +26261,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26279,7 +26279,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26302,7 +26302,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26325,7 +26325,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26344,7 +26344,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26363,7 +26363,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26382,7 +26382,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26401,7 +26401,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26420,7 +26420,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26439,7 +26439,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26458,7 +26458,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26477,7 +26477,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26493,7 +26493,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26509,7 +26509,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26525,7 +26525,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26541,7 +26541,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26557,7 +26557,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26573,7 +26573,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26589,7 +26589,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26605,7 +26605,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -26633,7 +26633,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -26661,7 +26661,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26693,7 +26693,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26725,7 +26725,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26753,7 +26753,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26781,7 +26781,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26809,7 +26809,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26837,7 +26837,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26865,7 +26865,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26893,7 +26893,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26921,7 +26921,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -26947,7 +26947,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -26973,7 +26973,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -26999,7 +26999,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27025,7 +27025,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27051,7 +27051,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27077,7 +27077,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27103,7 +27103,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27128,7 +27128,7 @@ pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27153,7 +27153,7 @@ pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27178,7 +27178,7 @@ pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27203,7 +27203,7 @@ pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27228,7 +27228,7 @@ pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27253,7 +27253,7 @@ pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27278,7 +27278,7 @@ pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27303,7 +27303,7 @@ pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -27326,7 +27326,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27345,7 +27345,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -27361,7 +27361,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -27384,7 +27384,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27408,7 +27408,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27437,7 +27437,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27461,7 +27461,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27514,7 +27514,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27538,7 +27538,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27567,7 +27567,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27591,7 +27591,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27620,7 +27620,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27644,7 +27644,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27673,7 +27673,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27697,7 +27697,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27726,7 +27726,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27750,7 +27750,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27779,7 +27779,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27803,7 +27803,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27856,7 +27856,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27880,7 +27880,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27909,7 +27909,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27933,7 +27933,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27962,7 +27962,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -27983,7 +27983,7 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
 #[cfg_attr(
@@ -28013,7 +28013,7 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
 #[cfg_attr(
@@ -28043,7 +28043,7 @@ pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28072,7 +28072,7 @@ pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28101,7 +28101,7 @@ pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28125,7 +28125,7 @@ pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28149,7 +28149,7 @@ pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28173,7 +28173,7 @@ pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28197,7 +28197,7 @@ pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28221,7 +28221,7 @@ pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28245,7 +28245,7 @@ pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28269,7 +28269,7 @@ pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28293,7 +28293,7 @@ pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28317,7 +28317,7 @@ pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28341,7 +28341,7 @@ pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28365,7 +28365,7 @@ pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28389,7 +28389,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
 #[cfg_attr(
@@ -28411,7 +28411,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
 #[cfg_attr(
@@ -28433,7 +28433,7 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
@@ -28454,7 +28454,7 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
@@ -28475,7 +28475,7 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
 #[cfg_attr(
@@ -28505,7 +28505,7 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
 #[cfg_attr(
@@ -28535,7 +28535,7 @@ pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28564,7 +28564,7 @@ pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28593,7 +28593,7 @@ pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28617,7 +28617,7 @@ pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28641,7 +28641,7 @@ pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28665,7 +28665,7 @@ pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28689,7 +28689,7 @@ pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28713,7 +28713,7 @@ pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28737,7 +28737,7 @@ pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28761,7 +28761,7 @@ pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28785,7 +28785,7 @@ pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28809,7 +28809,7 @@ pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28833,7 +28833,7 @@ pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28857,7 +28857,7 @@ pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28881,7 +28881,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
 #[cfg_attr(
@@ -28903,7 +28903,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
 #[cfg_attr(
@@ -28925,7 +28925,7 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
@@ -28946,7 +28946,7 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
@@ -28967,7 +28967,7 @@ pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -28988,7 +28988,7 @@ pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -29009,7 +29009,7 @@ pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29036,7 +29036,7 @@ pub fn vmla_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29063,7 +29063,7 @@ pub fn vmla_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29096,7 +29096,7 @@ pub fn vmlaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29129,7 +29129,7 @@ pub fn vmlaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29158,7 +29158,7 @@ pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29187,7 +29187,7 @@ pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29216,7 +29216,7 @@ pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29245,7 +29245,7 @@ pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29287,7 +29287,7 @@ pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29329,7 +29329,7 @@ pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29371,7 +29371,7 @@ pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29413,7 +29413,7 @@ pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29436,7 +29436,7 @@ pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29459,7 +29459,7 @@ pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29482,7 +29482,7 @@ pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29505,7 +29505,7 @@ pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29534,7 +29534,7 @@ pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29563,7 +29563,7 @@ pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29592,7 +29592,7 @@ pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29621,7 +29621,7 @@ pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -29642,7 +29642,7 @@ pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -29663,7 +29663,7 @@ pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29684,7 +29684,7 @@ pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29705,7 +29705,7 @@ pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29726,7 +29726,7 @@ pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29747,7 +29747,7 @@ pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29768,7 +29768,7 @@ pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29789,7 +29789,7 @@ pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29810,7 +29810,7 @@ pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29831,7 +29831,7 @@ pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29852,7 +29852,7 @@ pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29873,7 +29873,7 @@ pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29894,7 +29894,7 @@ pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29915,7 +29915,7 @@ pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29936,7 +29936,7 @@ pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29957,7 +29957,7 @@ pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29978,7 +29978,7 @@ pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29999,7 +29999,7 @@ pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -30020,7 +30020,7 @@ pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -30041,7 +30041,7 @@ pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -30062,7 +30062,7 @@ pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -30083,7 +30083,7 @@ pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
@@ -30112,7 +30112,7 @@ pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
@@ -30141,7 +30141,7 @@ pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
@@ -30164,7 +30164,7 @@ pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
@@ -30187,7 +30187,7 @@ pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
@@ -30216,7 +30216,7 @@ pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
@@ -30245,7 +30245,7 @@ pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
@@ -30268,7 +30268,7 @@ pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
@@ -30291,7 +30291,7 @@ pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
@@ -30312,7 +30312,7 @@ pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
@@ -30333,7 +30333,7 @@ pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
@@ -30354,7 +30354,7 @@ pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
@@ -30375,7 +30375,7 @@ pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
@@ -30396,7 +30396,7 @@ pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
@@ -30417,7 +30417,7 @@ pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
@@ -30438,7 +30438,7 @@ pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
@@ -30459,7 +30459,7 @@ pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
@@ -30480,7 +30480,7 @@ pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
@@ -30501,7 +30501,7 @@ pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -30522,7 +30522,7 @@ pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -30543,7 +30543,7 @@ pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30570,7 +30570,7 @@ pub fn vmls_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30597,7 +30597,7 @@ pub fn vmls_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30630,7 +30630,7 @@ pub fn vmlsq_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30663,7 +30663,7 @@ pub fn vmlsq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30692,7 +30692,7 @@ pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30721,7 +30721,7 @@ pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30750,7 +30750,7 @@ pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30779,7 +30779,7 @@ pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30821,7 +30821,7 @@ pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30863,7 +30863,7 @@ pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30905,7 +30905,7 @@ pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30947,7 +30947,7 @@ pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -30970,7 +30970,7 @@ pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -30993,7 +30993,7 @@ pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31016,7 +31016,7 @@ pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31039,7 +31039,7 @@ pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31068,7 +31068,7 @@ pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31097,7 +31097,7 @@ pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31126,7 +31126,7 @@ pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31155,7 +31155,7 @@ pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -31176,7 +31176,7 @@ pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -31197,7 +31197,7 @@ pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31218,7 +31218,7 @@ pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31239,7 +31239,7 @@ pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31260,7 +31260,7 @@ pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31281,7 +31281,7 @@ pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31302,7 +31302,7 @@ pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31323,7 +31323,7 @@ pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31344,7 +31344,7 @@ pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31365,7 +31365,7 @@ pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31386,7 +31386,7 @@ pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31407,7 +31407,7 @@ pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31428,7 +31428,7 @@ pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31449,7 +31449,7 @@ pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31470,7 +31470,7 @@ pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31491,7 +31491,7 @@ pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31512,7 +31512,7 @@ pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31533,7 +31533,7 @@ pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31554,7 +31554,7 @@ pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31575,7 +31575,7 @@ pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31596,7 +31596,7 @@ pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31617,7 +31617,7 @@ pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
@@ -31646,7 +31646,7 @@ pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
@@ -31675,7 +31675,7 @@ pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
@@ -31698,7 +31698,7 @@ pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
@@ -31721,7 +31721,7 @@ pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
@@ -31750,7 +31750,7 @@ pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
@@ -31779,7 +31779,7 @@ pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
@@ -31802,7 +31802,7 @@ pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
@@ -31825,7 +31825,7 @@ pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
@@ -31846,7 +31846,7 @@ pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
@@ -31867,7 +31867,7 @@ pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
@@ -31888,7 +31888,7 @@ pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
@@ -31909,7 +31909,7 @@ pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
@@ -31930,7 +31930,7 @@ pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
@@ -31951,7 +31951,7 @@ pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
@@ -31972,7 +31972,7 @@ pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
@@ -31993,7 +31993,7 @@ pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
@@ -32014,7 +32014,7 @@ pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
@@ -32035,7 +32035,7 @@ pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -32064,7 +32064,7 @@ pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -32093,7 +32093,7 @@ pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32109,7 +32109,7 @@ pub fn vmov_n_f16(a: f16) -> float16x4_t {
 }
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32125,7 +32125,7 @@ pub fn vmovq_n_f16(a: f16) -> float16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32146,7 +32146,7 @@ pub fn vmov_n_f32(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32167,7 +32167,7 @@ pub fn vmov_n_p16(value: p16) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32188,7 +32188,7 @@ pub fn vmov_n_p8(value: p8) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32209,7 +32209,7 @@ pub fn vmov_n_s16(value: i16) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32230,7 +32230,7 @@ pub fn vmov_n_s32(value: i32) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32251,7 +32251,7 @@ pub fn vmov_n_s64(value: i64) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32272,7 +32272,7 @@ pub fn vmov_n_s8(value: i8) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32293,7 +32293,7 @@ pub fn vmov_n_u16(value: u16) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32314,7 +32314,7 @@ pub fn vmov_n_u32(value: u32) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32335,7 +32335,7 @@ pub fn vmov_n_u64(value: u64) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32356,7 +32356,7 @@ pub fn vmov_n_u8(value: u8) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32377,7 +32377,7 @@ pub fn vmovq_n_f32(value: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32398,7 +32398,7 @@ pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32419,7 +32419,7 @@ pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32440,7 +32440,7 @@ pub fn vmovq_n_s16(value: i16) -> int16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32461,7 +32461,7 @@ pub fn vmovq_n_s32(value: i32) -> int32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32482,7 +32482,7 @@ pub fn vmovq_n_s64(value: i64) -> int64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32503,7 +32503,7 @@ pub fn vmovq_n_s8(value: i8) -> int8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32524,7 +32524,7 @@ pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32545,7 +32545,7 @@ pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32566,7 +32566,7 @@ pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32587,7 +32587,7 @@ pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32608,7 +32608,7 @@ pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32629,7 +32629,7 @@ pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32650,7 +32650,7 @@ pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32671,7 +32671,7 @@ pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32692,7 +32692,7 @@ pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32713,7 +32713,7 @@ pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32734,7 +32734,7 @@ pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32755,7 +32755,7 @@ pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32776,7 +32776,7 @@ pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32797,7 +32797,7 @@ pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32818,7 +32818,7 @@ pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32839,7 +32839,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
 #[cfg_attr(
@@ -32861,7 +32861,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
 #[cfg_attr(
@@ -32883,7 +32883,7 @@ pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
@@ -32904,7 +32904,7 @@ pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
@@ -32925,7 +32925,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
 #[cfg_attr(
@@ -32954,7 +32954,7 @@ pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
 #[cfg_attr(
@@ -32996,7 +32996,7 @@ pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float1
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33019,7 +33019,7 @@ pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33042,7 +33042,7 @@ pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float3
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33070,7 +33070,7 @@ pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float3
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33098,7 +33098,7 @@ pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33126,7 +33126,7 @@ pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33167,7 +33167,7 @@ pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33190,7 +33190,7 @@ pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33218,7 +33218,7 @@ pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33246,7 +33246,7 @@ pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33287,7 +33287,7 @@ pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33310,7 +33310,7 @@ pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33338,7 +33338,7 @@ pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33366,7 +33366,7 @@ pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33407,7 +33407,7 @@ pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33430,7 +33430,7 @@ pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33458,7 +33458,7 @@ pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33486,7 +33486,7 @@ pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33527,7 +33527,7 @@ pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33550,7 +33550,7 @@ pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33578,7 +33578,7 @@ pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
 #[cfg_attr(
@@ -33593,7 +33593,7 @@ pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
 #[cfg_attr(
@@ -33608,7 +33608,7 @@ pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33629,7 +33629,7 @@ pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33650,7 +33650,7 @@ pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33671,7 +33671,7 @@ pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33692,7 +33692,7 @@ pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33713,7 +33713,7 @@ pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33734,7 +33734,7 @@ pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33755,7 +33755,7 @@ pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33776,7 +33776,7 @@ pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33797,7 +33797,7 @@ pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33818,7 +33818,7 @@ pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33847,7 +33847,7 @@ pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33876,7 +33876,7 @@ pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33897,7 +33897,7 @@ pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33918,7 +33918,7 @@ pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33939,7 +33939,7 @@ pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33960,7 +33960,7 @@ pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -33981,7 +33981,7 @@ pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -34002,7 +34002,7 @@ pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -34023,7 +34023,7 @@ pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -34044,7 +34044,7 @@ pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34065,7 +34065,7 @@ pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34086,7 +34086,7 @@ pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34107,7 +34107,7 @@ pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34128,7 +34128,7 @@ pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34156,7 +34156,7 @@ pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34184,7 +34184,7 @@ pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34207,7 +34207,7 @@ pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34230,7 +34230,7 @@ pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34258,7 +34258,7 @@ pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34286,7 +34286,7 @@ pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34309,7 +34309,7 @@ pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34332,7 +34332,7 @@ pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34353,7 +34353,7 @@ pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34374,7 +34374,7 @@ pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34395,7 +34395,7 @@ pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34416,7 +34416,7 @@ pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
@@ -34445,7 +34445,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
@@ -34474,7 +34474,7 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
@@ -34503,7 +34503,7 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
@@ -34532,7 +34532,7 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
@@ -34561,7 +34561,7 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
@@ -34590,7 +34590,7 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
@@ -34619,7 +34619,7 @@ pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34641,7 +34641,7 @@ pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34663,7 +34663,7 @@ pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34685,7 +34685,7 @@ pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34707,7 +34707,7 @@ pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34729,7 +34729,7 @@ pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34751,7 +34751,7 @@ pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34773,7 +34773,7 @@ pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34795,7 +34795,7 @@ pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34817,7 +34817,7 @@ pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34839,7 +34839,7 @@ pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34861,7 +34861,7 @@ pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34883,7 +34883,7 @@ pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34905,7 +34905,7 @@ pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34927,7 +34927,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
 #[cfg_attr(
@@ -34949,7 +34949,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
 #[cfg_attr(
@@ -34971,7 +34971,7 @@ pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
@@ -34992,7 +34992,7 @@ pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
@@ -35013,7 +35013,7 @@ pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
@@ -35034,7 +35034,7 @@ pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
@@ -35055,7 +35055,7 @@ pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
@@ -35076,7 +35076,7 @@ pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
@@ -35097,7 +35097,7 @@ pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
@@ -35118,7 +35118,7 @@ pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
@@ -35139,7 +35139,7 @@ pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35161,7 +35161,7 @@ pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35183,7 +35183,7 @@ pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35205,7 +35205,7 @@ pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35227,7 +35227,7 @@ pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35249,7 +35249,7 @@ pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35271,7 +35271,7 @@ pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35293,7 +35293,7 @@ pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35315,7 +35315,7 @@ pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35337,7 +35337,7 @@ pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35359,7 +35359,7 @@ pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35381,7 +35381,7 @@ pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35403,7 +35403,7 @@ pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35425,7 +35425,7 @@ pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35447,7 +35447,7 @@ pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35469,7 +35469,7 @@ pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35491,7 +35491,7 @@ pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35512,7 +35512,7 @@ pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35533,7 +35533,7 @@ pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35554,7 +35554,7 @@ pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35575,7 +35575,7 @@ pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35596,7 +35596,7 @@ pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35617,7 +35617,7 @@ pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35638,7 +35638,7 @@ pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35659,7 +35659,7 @@ pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35680,7 +35680,7 @@ pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35701,7 +35701,7 @@ pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35722,7 +35722,7 @@ pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35743,7 +35743,7 @@ pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35764,7 +35764,7 @@ pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35785,7 +35785,7 @@ pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35806,7 +35806,7 @@ pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35827,7 +35827,7 @@ pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
@@ -35857,7 +35857,7 @@ pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
@@ -35887,7 +35887,7 @@ pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
@@ -35917,7 +35917,7 @@ pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
@@ -35947,7 +35947,7 @@ pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
@@ -35977,7 +35977,7 @@ pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
@@ -36007,7 +36007,7 @@ pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
@@ -36037,7 +36037,7 @@ pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
@@ -36067,7 +36067,7 @@ pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
@@ -36097,7 +36097,7 @@ pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
@@ -36127,7 +36127,7 @@ pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
@@ -36157,7 +36157,7 @@ pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
@@ -36187,7 +36187,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
 #[cfg_attr(
@@ -36217,7 +36217,7 @@ pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36246,7 +36246,7 @@ pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36275,7 +36275,7 @@ pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36304,7 +36304,7 @@ pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36333,7 +36333,7 @@ pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36355,7 +36355,7 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36382,7 +36382,7 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36404,7 +36404,7 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36431,7 +36431,7 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36453,7 +36453,7 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36480,7 +36480,7 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
@@ -36509,7 +36509,7 @@ pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
@@ -36538,7 +36538,7 @@ pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
@@ -36567,7 +36567,7 @@ pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
@@ -36596,7 +36596,7 @@ pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
@@ -36625,7 +36625,7 @@ pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
@@ -36654,7 +36654,7 @@ pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
@@ -36683,7 +36683,7 @@ pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
@@ -36712,7 +36712,7 @@ pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
@@ -36741,7 +36741,7 @@ pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
@@ -36770,7 +36770,7 @@ pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
@@ -36799,7 +36799,7 @@ pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
@@ -36828,7 +36828,7 @@ pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36857,7 +36857,7 @@ pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36886,7 +36886,7 @@ pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36915,7 +36915,7 @@ pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36944,7 +36944,7 @@ pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36973,7 +36973,7 @@ pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -37002,7 +37002,7 @@ pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -37031,7 +37031,7 @@ pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37060,7 +37060,7 @@ pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37089,7 +37089,7 @@ pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37118,7 +37118,7 @@ pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37147,7 +37147,7 @@ pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37176,7 +37176,7 @@ pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37205,7 +37205,7 @@ pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37234,7 +37234,7 @@ pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
@@ -37263,7 +37263,7 @@ pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
@@ -37292,7 +37292,7 @@ pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
@@ -37321,7 +37321,7 @@ pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
@@ -37350,7 +37350,7 @@ pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
@@ -37379,7 +37379,7 @@ pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
@@ -37408,7 +37408,7 @@ pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
@@ -37429,7 +37429,7 @@ pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
@@ -37450,7 +37450,7 @@ pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
@@ -37471,7 +37471,7 @@ pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
@@ -37492,7 +37492,7 @@ pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
@@ -37513,7 +37513,7 @@ pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
@@ -37534,7 +37534,7 @@ pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
@@ -37555,7 +37555,7 @@ pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
@@ -37576,7 +37576,7 @@ pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
@@ -37597,7 +37597,7 @@ pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
@@ -37618,7 +37618,7 @@ pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
@@ -37639,7 +37639,7 @@ pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
@@ -37660,7 +37660,7 @@ pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
@@ -37681,7 +37681,7 @@ pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
@@ -37702,7 +37702,7 @@ pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
@@ -37723,7 +37723,7 @@ pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
@@ -37744,7 +37744,7 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
@@ -37767,7 +37767,7 @@ pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
@@ -37790,7 +37790,7 @@ pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37811,7 +37811,7 @@ pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37832,7 +37832,7 @@ pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37853,7 +37853,7 @@ pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37874,7 +37874,7 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
@@ -37897,7 +37897,7 @@ pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
@@ -37920,7 +37920,7 @@ pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -37941,7 +37941,7 @@ pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -37962,7 +37962,7 @@ pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -37983,7 +37983,7 @@ pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -38004,7 +38004,7 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38027,7 +38027,7 @@ pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38050,7 +38050,7 @@ pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38073,7 +38073,7 @@ pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38096,7 +38096,7 @@ pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38118,7 +38118,7 @@ pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38140,7 +38140,7 @@ pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38162,7 +38162,7 @@ pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38184,7 +38184,7 @@ pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38213,7 +38213,7 @@ pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38242,7 +38242,7 @@ pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38271,7 +38271,7 @@ pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38300,7 +38300,7 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
@@ -38326,7 +38326,7 @@ pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
@@ -38352,7 +38352,7 @@ pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38373,7 +38373,7 @@ pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38394,7 +38394,7 @@ pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38423,7 +38423,7 @@ pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38452,7 +38452,7 @@ pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38481,7 +38481,7 @@ pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38510,7 +38510,7 @@ pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38539,7 +38539,7 @@ pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38568,7 +38568,7 @@ pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38597,7 +38597,7 @@ pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38626,7 +38626,7 @@ pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -38655,7 +38655,7 @@ pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -38684,7 +38684,7 @@ pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -38713,7 +38713,7 @@ pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
@@ -38742,7 +38742,7 @@ pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
@@ -38771,7 +38771,7 @@ pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
@@ -38800,7 +38800,7 @@ pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
@@ -38829,7 +38829,7 @@ pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
@@ -38858,7 +38858,7 @@ pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
@@ -38887,7 +38887,7 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38914,7 +38914,7 @@ pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38940,7 +38940,7 @@ pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38967,7 +38967,7 @@ pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38993,7 +38993,7 @@ pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39032,7 +39032,7 @@ pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39059,7 +39059,7 @@ pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39098,7 +39098,7 @@ pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39125,7 +39125,7 @@ pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39146,7 +39146,7 @@ pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39167,7 +39167,7 @@ pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39188,7 +39188,7 @@ pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39209,7 +39209,7 @@ pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39238,7 +39238,7 @@ pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39267,7 +39267,7 @@ pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39296,7 +39296,7 @@ pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39325,7 +39325,7 @@ pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39354,7 +39354,7 @@ pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39383,7 +39383,7 @@ pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39412,7 +39412,7 @@ pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39441,7 +39441,7 @@ pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39470,7 +39470,7 @@ pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39499,7 +39499,7 @@ pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39528,7 +39528,7 @@ pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39557,7 +39557,7 @@ pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39586,7 +39586,7 @@ pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39615,7 +39615,7 @@ pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39644,7 +39644,7 @@ pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39673,7 +39673,7 @@ pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39702,7 +39702,7 @@ pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39731,7 +39731,7 @@ pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39760,7 +39760,7 @@ pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39789,7 +39789,7 @@ pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39805,7 +39805,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39821,7 +39821,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39837,7 +39837,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -39856,7 +39856,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -39875,7 +39875,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -39894,7 +39894,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39920,7 +39920,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39941,7 +39941,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39957,7 +39957,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -39976,7 +39976,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -39995,7 +39995,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -40014,7 +40014,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -40030,7 +40030,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -40046,7 +40046,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -40062,7 +40062,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -40081,7 +40081,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -40100,7 +40100,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -40119,7 +40119,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40142,7 +40142,7 @@ pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40165,7 +40165,7 @@ pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40188,7 +40188,7 @@ pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40211,7 +40211,7 @@ pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40234,7 +40234,7 @@ pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40257,7 +40257,7 @@ pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40280,7 +40280,7 @@ pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40303,7 +40303,7 @@ pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40326,7 +40326,7 @@ pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40349,7 +40349,7 @@ pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40372,7 +40372,7 @@ pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40395,7 +40395,7 @@ pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40418,7 +40418,7 @@ pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40441,7 +40441,7 @@ pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40464,7 +40464,7 @@ pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40487,7 +40487,7 @@ pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40516,7 +40516,7 @@ pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40545,7 +40545,7 @@ pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40574,7 +40574,7 @@ pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40603,7 +40603,7 @@ pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40632,7 +40632,7 @@ pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40661,7 +40661,7 @@ pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40690,7 +40690,7 @@ pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40719,7 +40719,7 @@ pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40748,7 +40748,7 @@ pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40777,7 +40777,7 @@ pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40806,7 +40806,7 @@ pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40835,7 +40835,7 @@ pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40864,7 +40864,7 @@ pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40893,7 +40893,7 @@ pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40922,7 +40922,7 @@ pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40951,7 +40951,7 @@ pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -40967,7 +40967,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -40983,7 +40983,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -40999,7 +40999,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41015,7 +41015,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41031,7 +41031,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41047,7 +41047,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41063,7 +41063,7 @@ pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41079,7 +41079,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41098,7 +41098,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41117,7 +41117,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41136,7 +41136,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41155,7 +41155,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41174,7 +41174,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41193,7 +41193,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41212,7 +41212,7 @@ pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41231,7 +41231,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41247,7 +41247,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41263,7 +41263,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41279,7 +41279,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -41298,7 +41298,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -41317,7 +41317,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -41336,7 +41336,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41362,7 +41362,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41383,7 +41383,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41399,7 +41399,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -41418,7 +41418,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -41437,7 +41437,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -41456,7 +41456,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -41472,7 +41472,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -41488,7 +41488,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -41504,7 +41504,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -41523,7 +41523,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -41542,7 +41542,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -41561,7 +41561,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
@@ -41582,7 +41582,7 @@ pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
@@ -41603,7 +41603,7 @@ pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
@@ -41624,7 +41624,7 @@ pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
@@ -41645,7 +41645,7 @@ pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
@@ -41666,7 +41666,7 @@ pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
@@ -41687,7 +41687,7 @@ pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
@@ -41708,7 +41708,7 @@ pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
@@ -41729,7 +41729,7 @@ pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
@@ -41750,7 +41750,7 @@ pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
@@ -41771,7 +41771,7 @@ pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
@@ -41792,7 +41792,7 @@ pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
@@ -41813,7 +41813,7 @@ pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
@@ -41834,7 +41834,7 @@ pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
@@ -41855,7 +41855,7 @@ pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
@@ -41876,7 +41876,7 @@ pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
@@ -41897,7 +41897,7 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -41919,7 +41919,7 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -41941,7 +41941,7 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -41963,7 +41963,7 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -41987,7 +41987,7 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -42011,7 +42011,7 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -42035,7 +42035,7 @@ pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -42064,7 +42064,7 @@ pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -42093,7 +42093,7 @@ pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -42122,7 +42122,7 @@ pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42144,7 +42144,7 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42171,7 +42171,7 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42193,7 +42193,7 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42220,7 +42220,7 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42242,7 +42242,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42269,7 +42269,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
 #[cfg_attr(
@@ -42299,7 +42299,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
 #[cfg_attr(
@@ -42329,7 +42329,7 @@ pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42358,7 +42358,7 @@ pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42387,7 +42387,7 @@ pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unsigned reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42416,7 +42416,7 @@ pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42445,7 +42445,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
 #[cfg_attr(
@@ -42475,7 +42475,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
 #[cfg_attr(
@@ -42505,7 +42505,7 @@ pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
@@ -42534,7 +42534,7 @@ pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
@@ -42563,7 +42563,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42586,7 +42586,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42613,7 +42613,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42636,7 +42636,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42663,7 +42663,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42686,7 +42686,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42713,7 +42713,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42736,7 +42736,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42763,7 +42763,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42786,7 +42786,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42810,7 +42810,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42833,7 +42833,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42860,7 +42860,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42883,7 +42883,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42910,7 +42910,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42933,7 +42933,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42960,7 +42960,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42983,7 +42983,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43007,7 +43007,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43030,7 +43030,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43057,7 +43057,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43080,7 +43080,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43107,7 +43107,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43130,7 +43130,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43157,7 +43157,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43180,7 +43180,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43211,7 +43211,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43234,7 +43234,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43261,7 +43261,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43284,7 +43284,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43311,7 +43311,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43334,7 +43334,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43361,7 +43361,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43384,7 +43384,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43415,7 +43415,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43438,7 +43438,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43465,7 +43465,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43488,7 +43488,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43515,7 +43515,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43538,7 +43538,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43565,7 +43565,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43588,7 +43588,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43619,7 +43619,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43642,7 +43642,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43669,7 +43669,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43692,7 +43692,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43719,7 +43719,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43742,7 +43742,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43769,7 +43769,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43792,7 +43792,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43819,7 +43819,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43842,7 +43842,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43870,7 +43870,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43893,7 +43893,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43920,7 +43920,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43943,7 +43943,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43970,7 +43970,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43993,7 +43993,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44020,7 +44020,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44043,7 +44043,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44070,7 +44070,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44093,7 +44093,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44119,7 +44119,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44142,7 +44142,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44169,7 +44169,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44192,7 +44192,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44219,7 +44219,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44242,7 +44242,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44270,7 +44270,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44293,7 +44293,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44320,7 +44320,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44343,7 +44343,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44370,7 +44370,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44393,7 +44393,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44420,7 +44420,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44443,7 +44443,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44470,7 +44470,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44493,7 +44493,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44519,7 +44519,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44542,7 +44542,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44569,7 +44569,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44592,7 +44592,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44619,7 +44619,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44642,7 +44642,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44670,7 +44670,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44693,7 +44693,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44720,7 +44720,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44743,7 +44743,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44770,7 +44770,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44793,7 +44793,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44819,7 +44819,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44842,7 +44842,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44866,7 +44866,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44889,7 +44889,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44913,7 +44913,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44936,7 +44936,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44963,7 +44963,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44986,7 +44986,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45012,7 +45012,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45035,7 +45035,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45062,7 +45062,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45084,7 +45084,7 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45109,7 +45109,7 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45131,7 +45131,7 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45157,7 +45157,7 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45179,7 +45179,7 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45205,7 +45205,7 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45227,7 +45227,7 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45253,7 +45253,7 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45275,7 +45275,7 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45298,7 +45298,7 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45320,7 +45320,7 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45346,7 +45346,7 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45368,7 +45368,7 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45394,7 +45394,7 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45416,7 +45416,7 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45442,7 +45442,7 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45464,7 +45464,7 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45487,7 +45487,7 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45509,7 +45509,7 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45535,7 +45535,7 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45557,7 +45557,7 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45583,7 +45583,7 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45605,7 +45605,7 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45628,7 +45628,7 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45650,7 +45650,7 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45680,7 +45680,7 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45702,7 +45702,7 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45728,7 +45728,7 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45750,7 +45750,7 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45776,7 +45776,7 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45798,7 +45798,7 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45824,7 +45824,7 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45846,7 +45846,7 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45876,7 +45876,7 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45898,7 +45898,7 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45924,7 +45924,7 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45946,7 +45946,7 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45972,7 +45972,7 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45994,7 +45994,7 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46020,7 +46020,7 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46042,7 +46042,7 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46072,7 +46072,7 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46094,7 +46094,7 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46120,7 +46120,7 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46142,7 +46142,7 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46168,7 +46168,7 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46190,7 +46190,7 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46216,7 +46216,7 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46238,7 +46238,7 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46264,7 +46264,7 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46286,7 +46286,7 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46309,7 +46309,7 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46331,7 +46331,7 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46357,7 +46357,7 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46379,7 +46379,7 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46405,7 +46405,7 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46427,7 +46427,7 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46453,7 +46453,7 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46475,7 +46475,7 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46498,7 +46498,7 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46520,7 +46520,7 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46546,7 +46546,7 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46568,7 +46568,7 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46594,7 +46594,7 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46616,7 +46616,7 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46643,7 +46643,7 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46665,7 +46665,7 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46692,7 +46692,7 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46714,7 +46714,7 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46741,7 +46741,7 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46763,7 +46763,7 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46790,7 +46790,7 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46812,7 +46812,7 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46843,7 +46843,7 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46865,7 +46865,7 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46892,7 +46892,7 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46914,7 +46914,7 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46941,7 +46941,7 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46963,7 +46963,7 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46990,7 +46990,7 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47012,7 +47012,7 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47043,7 +47043,7 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47065,7 +47065,7 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47092,7 +47092,7 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47114,7 +47114,7 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47140,7 +47140,7 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47162,7 +47162,7 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47188,7 +47188,7 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47210,7 +47210,7 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47236,7 +47236,7 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47258,7 +47258,7 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47281,7 +47281,7 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47303,7 +47303,7 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47329,7 +47329,7 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47351,7 +47351,7 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47377,7 +47377,7 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47399,7 +47399,7 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47425,7 +47425,7 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47447,7 +47447,7 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47470,7 +47470,7 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47492,7 +47492,7 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47518,7 +47518,7 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47540,7 +47540,7 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47566,7 +47566,7 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47588,7 +47588,7 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47614,7 +47614,7 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47636,7 +47636,7 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47666,7 +47666,7 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47688,7 +47688,7 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47714,7 +47714,7 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47736,7 +47736,7 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47762,7 +47762,7 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47784,7 +47784,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47814,7 +47814,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47836,7 +47836,7 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47862,7 +47862,7 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47884,7 +47884,7 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47910,7 +47910,7 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47932,7 +47932,7 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47958,7 +47958,7 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47980,7 +47980,7 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48010,7 +48010,7 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48032,7 +48032,7 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48058,7 +48058,7 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48080,7 +48080,7 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48106,7 +48106,7 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48128,7 +48128,7 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48154,7 +48154,7 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48176,7 +48176,7 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48202,7 +48202,7 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48224,7 +48224,7 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48247,7 +48247,7 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48269,7 +48269,7 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48295,7 +48295,7 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48317,7 +48317,7 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48343,7 +48343,7 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48365,7 +48365,7 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48391,7 +48391,7 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48413,7 +48413,7 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48436,7 +48436,7 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48458,7 +48458,7 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48484,7 +48484,7 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48506,7 +48506,7 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48532,7 +48532,7 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48554,7 +48554,7 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48580,7 +48580,7 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48602,7 +48602,7 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48632,7 +48632,7 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48654,7 +48654,7 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48680,7 +48680,7 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48702,7 +48702,7 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48728,7 +48728,7 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48750,7 +48750,7 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48780,7 +48780,7 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48802,7 +48802,7 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48828,7 +48828,7 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48850,7 +48850,7 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48876,7 +48876,7 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48898,7 +48898,7 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48924,7 +48924,7 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48946,7 +48946,7 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48976,7 +48976,7 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48998,7 +48998,7 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49024,7 +49024,7 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49046,7 +49046,7 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49071,7 +49071,7 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49093,7 +49093,7 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49118,7 +49118,7 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49140,7 +49140,7 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49165,7 +49165,7 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49187,7 +49187,7 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49212,7 +49212,7 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49234,7 +49234,7 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49259,7 +49259,7 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49281,7 +49281,7 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49306,7 +49306,7 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49328,7 +49328,7 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49353,7 +49353,7 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49374,7 +49374,7 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49396,7 +49396,7 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49421,7 +49421,7 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49443,7 +49443,7 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49468,7 +49468,7 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49490,7 +49490,7 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49516,7 +49516,7 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49538,7 +49538,7 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49568,7 +49568,7 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49590,7 +49590,7 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49616,7 +49616,7 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49638,7 +49638,7 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49664,7 +49664,7 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49686,7 +49686,7 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49716,7 +49716,7 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49738,7 +49738,7 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49764,7 +49764,7 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49786,7 +49786,7 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49812,7 +49812,7 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49834,7 +49834,7 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49860,7 +49860,7 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49882,7 +49882,7 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49912,7 +49912,7 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49934,7 +49934,7 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49960,7 +49960,7 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49982,7 +49982,7 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50008,7 +50008,7 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50030,7 +50030,7 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50056,7 +50056,7 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50078,7 +50078,7 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50104,7 +50104,7 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50126,7 +50126,7 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50152,7 +50152,7 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50174,7 +50174,7 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50197,7 +50197,7 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50219,7 +50219,7 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50245,7 +50245,7 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50267,7 +50267,7 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50293,7 +50293,7 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50315,7 +50315,7 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50338,7 +50338,7 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50360,7 +50360,7 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50386,7 +50386,7 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50408,7 +50408,7 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50434,7 +50434,7 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50456,7 +50456,7 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50483,7 +50483,7 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50505,7 +50505,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50536,7 +50536,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50558,7 +50558,7 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50585,7 +50585,7 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50607,7 +50607,7 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50634,7 +50634,7 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50656,7 +50656,7 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50683,7 +50683,7 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50705,7 +50705,7 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50732,7 +50732,7 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50754,7 +50754,7 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50781,7 +50781,7 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50803,7 +50803,7 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50830,7 +50830,7 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50852,7 +50852,7 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50883,7 +50883,7 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50905,7 +50905,7 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50932,7 +50932,7 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50954,7 +50954,7 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50980,7 +50980,7 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51002,7 +51002,7 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51028,7 +51028,7 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51050,7 +51050,7 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51076,7 +51076,7 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51098,7 +51098,7 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51124,7 +51124,7 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51146,7 +51146,7 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51169,7 +51169,7 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51191,7 +51191,7 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51217,7 +51217,7 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51239,7 +51239,7 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51265,7 +51265,7 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51287,7 +51287,7 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51310,7 +51310,7 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51332,7 +51332,7 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51358,7 +51358,7 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51380,7 +51380,7 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51406,7 +51406,7 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51428,7 +51428,7 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51454,7 +51454,7 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51476,7 +51476,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51506,7 +51506,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51528,7 +51528,7 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51554,7 +51554,7 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51576,7 +51576,7 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51602,7 +51602,7 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51624,7 +51624,7 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51650,7 +51650,7 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51672,7 +51672,7 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51702,7 +51702,7 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51724,7 +51724,7 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51750,7 +51750,7 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51772,7 +51772,7 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51798,7 +51798,7 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51820,7 +51820,7 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51850,7 +51850,7 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51872,7 +51872,7 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51898,7 +51898,7 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51920,7 +51920,7 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51946,7 +51946,7 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51968,7 +51968,7 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51994,7 +51994,7 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52016,7 +52016,7 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52042,7 +52042,7 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52064,7 +52064,7 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52090,7 +52090,7 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52112,7 +52112,7 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52135,7 +52135,7 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52157,7 +52157,7 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52183,7 +52183,7 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52205,7 +52205,7 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52231,7 +52231,7 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52253,7 +52253,7 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52276,7 +52276,7 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52298,7 +52298,7 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52324,7 +52324,7 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52346,7 +52346,7 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52372,7 +52372,7 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52394,7 +52394,7 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52420,7 +52420,7 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52442,7 +52442,7 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52472,7 +52472,7 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52494,7 +52494,7 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52520,7 +52520,7 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52542,7 +52542,7 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52568,7 +52568,7 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52590,7 +52590,7 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52616,7 +52616,7 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52638,7 +52638,7 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52668,7 +52668,7 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52690,7 +52690,7 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52716,7 +52716,7 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52738,7 +52738,7 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52764,7 +52764,7 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52786,7 +52786,7 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52816,7 +52816,7 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52838,7 +52838,7 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52864,7 +52864,7 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52886,7 +52886,7 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52911,7 +52911,7 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52933,7 +52933,7 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52958,7 +52958,7 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52980,7 +52980,7 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53005,7 +53005,7 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53027,7 +53027,7 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53052,7 +53052,7 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53073,7 +53073,7 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53095,7 +53095,7 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53120,7 +53120,7 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53142,7 +53142,7 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53167,7 +53167,7 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53189,7 +53189,7 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53214,7 +53214,7 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53236,7 +53236,7 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53261,7 +53261,7 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53283,7 +53283,7 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53308,7 +53308,7 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53330,7 +53330,7 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53356,7 +53356,7 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53378,7 +53378,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53408,7 +53408,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53430,7 +53430,7 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53456,7 +53456,7 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53478,7 +53478,7 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53504,7 +53504,7 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53526,7 +53526,7 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53552,7 +53552,7 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53574,7 +53574,7 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53604,7 +53604,7 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53626,7 +53626,7 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53652,7 +53652,7 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53674,7 +53674,7 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53700,7 +53700,7 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53722,7 +53722,7 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53752,7 +53752,7 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53774,7 +53774,7 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53800,7 +53800,7 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53822,7 +53822,7 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53848,7 +53848,7 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53870,7 +53870,7 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53896,7 +53896,7 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53918,7 +53918,7 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53944,7 +53944,7 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53966,7 +53966,7 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53992,7 +53992,7 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54014,7 +54014,7 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54037,7 +54037,7 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54059,7 +54059,7 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54085,7 +54085,7 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54107,7 +54107,7 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54133,7 +54133,7 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54155,7 +54155,7 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54181,7 +54181,7 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54203,7 +54203,7 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54226,7 +54226,7 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54248,7 +54248,7 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54274,7 +54274,7 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54296,7 +54296,7 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54323,7 +54323,7 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54345,7 +54345,7 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54376,7 +54376,7 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54398,7 +54398,7 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54425,7 +54425,7 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54447,7 +54447,7 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54474,7 +54474,7 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54496,7 +54496,7 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54523,7 +54523,7 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54545,7 +54545,7 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54576,7 +54576,7 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54598,7 +54598,7 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54625,7 +54625,7 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54647,7 +54647,7 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54674,7 +54674,7 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54696,7 +54696,7 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54723,7 +54723,7 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54745,7 +54745,7 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54772,7 +54772,7 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54794,7 +54794,7 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54820,7 +54820,7 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54842,7 +54842,7 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54868,7 +54868,7 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54890,7 +54890,7 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54916,7 +54916,7 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54938,7 +54938,7 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54964,7 +54964,7 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54986,7 +54986,7 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55009,7 +55009,7 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55031,7 +55031,7 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55057,7 +55057,7 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55079,7 +55079,7 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55105,7 +55105,7 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55127,7 +55127,7 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55153,7 +55153,7 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55175,7 +55175,7 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55198,7 +55198,7 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55220,7 +55220,7 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55246,7 +55246,7 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55268,7 +55268,7 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55294,7 +55294,7 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55316,7 +55316,7 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55346,7 +55346,7 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55368,7 +55368,7 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55394,7 +55394,7 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55416,7 +55416,7 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55442,7 +55442,7 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55464,7 +55464,7 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55490,7 +55490,7 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55512,7 +55512,7 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55542,7 +55542,7 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55564,7 +55564,7 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55590,7 +55590,7 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55612,7 +55612,7 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55638,7 +55638,7 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55660,7 +55660,7 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55686,7 +55686,7 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55708,7 +55708,7 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55738,7 +55738,7 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55760,7 +55760,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55789,7 +55789,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55811,7 +55811,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55836,7 +55836,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55858,7 +55858,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55883,7 +55883,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55905,7 +55905,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55930,7 +55930,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55952,7 +55952,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55981,7 +55981,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56003,7 +56003,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56028,7 +56028,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56050,7 +56050,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56075,7 +56075,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56097,7 +56097,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56122,7 +56122,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56144,7 +56144,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56173,7 +56173,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56195,7 +56195,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56220,7 +56220,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56242,7 +56242,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56267,7 +56267,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56289,7 +56289,7 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56312,7 +56312,7 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56334,7 +56334,7 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56358,7 +56358,7 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56380,7 +56380,7 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56407,7 +56407,7 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56429,7 +56429,7 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56452,7 +56452,7 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56474,7 +56474,7 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56497,7 +56497,7 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56519,7 +56519,7 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56545,7 +56545,7 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56567,7 +56567,7 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56590,7 +56590,7 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56612,7 +56612,7 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56635,7 +56635,7 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56657,7 +56657,7 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56683,7 +56683,7 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56705,7 +56705,7 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56728,7 +56728,7 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56750,7 +56750,7 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56773,7 +56773,7 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56795,7 +56795,7 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56819,7 +56819,7 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56841,7 +56841,7 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56868,7 +56868,7 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56890,7 +56890,7 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56913,7 +56913,7 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56935,7 +56935,7 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56958,7 +56958,7 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56980,7 +56980,7 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57006,7 +57006,7 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57028,7 +57028,7 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57051,7 +57051,7 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57073,7 +57073,7 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57096,7 +57096,7 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57118,7 +57118,7 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57144,7 +57144,7 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57166,7 +57166,7 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57189,7 +57189,7 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57211,7 +57211,7 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57234,7 +57234,7 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57256,7 +57256,7 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57280,7 +57280,7 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57302,7 +57302,7 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57329,7 +57329,7 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57351,7 +57351,7 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57374,7 +57374,7 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57396,7 +57396,7 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57419,7 +57419,7 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57441,7 +57441,7 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57467,7 +57467,7 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57489,7 +57489,7 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57514,7 +57514,7 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57536,7 +57536,7 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57561,7 +57561,7 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57583,7 +57583,7 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57608,7 +57608,7 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57630,7 +57630,7 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57655,7 +57655,7 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57677,7 +57677,7 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57702,7 +57702,7 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57724,7 +57724,7 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57749,7 +57749,7 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57771,7 +57771,7 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57796,7 +57796,7 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57818,7 +57818,7 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57843,7 +57843,7 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57865,7 +57865,7 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57888,7 +57888,7 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57910,7 +57910,7 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57940,7 +57940,7 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57962,7 +57962,7 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57988,7 +57988,7 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58010,7 +58010,7 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58036,7 +58036,7 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58058,7 +58058,7 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58088,7 +58088,7 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58110,7 +58110,7 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58136,7 +58136,7 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58158,7 +58158,7 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58184,7 +58184,7 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58206,7 +58206,7 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58236,7 +58236,7 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58258,7 +58258,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58284,7 +58284,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58305,7 +58305,7 @@ pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58326,7 +58326,7 @@ pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58347,7 +58347,7 @@ pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58368,7 +58368,7 @@ pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58389,7 +58389,7 @@ pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58410,7 +58410,7 @@ pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58431,7 +58431,7 @@ pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58452,7 +58452,7 @@ pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58473,7 +58473,7 @@ pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58494,7 +58494,7 @@ pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58515,7 +58515,7 @@ pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58536,7 +58536,7 @@ pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58557,7 +58557,7 @@ pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58578,7 +58578,7 @@ pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58599,7 +58599,7 @@ pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58620,7 +58620,7 @@ pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58641,7 +58641,7 @@ pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58662,7 +58662,7 @@ pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58683,7 +58683,7 @@ pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58704,7 +58704,7 @@ pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58725,7 +58725,7 @@ pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58746,7 +58746,7 @@ pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58767,7 +58767,7 @@ pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58788,7 +58788,7 @@ pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58809,7 +58809,7 @@ pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58830,7 +58830,7 @@ pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58851,7 +58851,7 @@ pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58872,7 +58872,7 @@ pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58893,7 +58893,7 @@ pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58914,7 +58914,7 @@ pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58935,7 +58935,7 @@ pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58956,7 +58956,7 @@ pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58977,7 +58977,7 @@ pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58998,7 +58998,7 @@ pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -59019,7 +59019,7 @@ pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -59040,7 +59040,7 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse elements in 64-bit doublewords"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
 #[cfg_attr(
@@ -59062,7 +59062,7 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reverse elements in 64-bit doublewords"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
 #[cfg_attr(
@@ -59084,7 +59084,7 @@ pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
@@ -59113,7 +59113,7 @@ pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
@@ -59142,7 +59142,7 @@ pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
@@ -59171,7 +59171,7 @@ pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
@@ -59200,7 +59200,7 @@ pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
@@ -59229,7 +59229,7 @@ pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
@@ -59258,7 +59258,7 @@ pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
@@ -59287,7 +59287,7 @@ pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
@@ -59316,7 +59316,7 @@ pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
@@ -59345,7 +59345,7 @@ pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
@@ -59374,7 +59374,7 @@ pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
@@ -59403,7 +59403,7 @@ pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
@@ -59432,7 +59432,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
 #[cfg_attr(
@@ -59461,7 +59461,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
 #[cfg_attr(
@@ -59490,7 +59490,7 @@ pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
@@ -59518,7 +59518,7 @@ pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
@@ -59546,7 +59546,7 @@ pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59575,7 +59575,7 @@ pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59604,7 +59604,7 @@ pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59633,7 +59633,7 @@ pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59662,7 +59662,7 @@ pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59691,7 +59691,7 @@ pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59720,7 +59720,7 @@ pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59749,7 +59749,7 @@ pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59778,7 +59778,7 @@ pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59807,7 +59807,7 @@ pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59836,7 +59836,7 @@ pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59865,7 +59865,7 @@ pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59894,7 +59894,7 @@ pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59923,7 +59923,7 @@ pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59952,7 +59952,7 @@ pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59981,7 +59981,7 @@ pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -60010,7 +60010,7 @@ pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60033,7 +60033,7 @@ pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60056,7 +60056,7 @@ pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60079,7 +60079,7 @@ pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60102,7 +60102,7 @@ pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60125,7 +60125,7 @@ pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60148,7 +60148,7 @@ pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60171,7 +60171,7 @@ pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60194,7 +60194,7 @@ pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60217,7 +60217,7 @@ pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60240,7 +60240,7 @@ pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60263,7 +60263,7 @@ pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60286,7 +60286,7 @@ pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60309,7 +60309,7 @@ pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60332,7 +60332,7 @@ pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60355,7 +60355,7 @@ pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60378,7 +60378,7 @@ pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -60394,7 +60394,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -60410,7 +60410,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -60426,7 +60426,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -60445,7 +60445,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -60464,7 +60464,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -60483,7 +60483,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -60506,7 +60506,7 @@ pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -60529,7 +60529,7 @@ pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -60552,7 +60552,7 @@ pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60582,7 +60582,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60612,7 +60612,7 @@ pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60641,7 +60641,7 @@ pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60670,7 +60670,7 @@ pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unsigned reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60699,7 +60699,7 @@ pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60728,7 +60728,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60758,7 +60758,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60788,7 +60788,7 @@ pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60817,7 +60817,7 @@ pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60846,7 +60846,7 @@ pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60869,7 +60869,7 @@ pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60892,7 +60892,7 @@ pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60915,7 +60915,7 @@ pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60938,7 +60938,7 @@ pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60961,7 +60961,7 @@ pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60984,7 +60984,7 @@ pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61007,7 +61007,7 @@ pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61030,7 +61030,7 @@ pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61053,7 +61053,7 @@ pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61076,7 +61076,7 @@ pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61099,7 +61099,7 @@ pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61122,7 +61122,7 @@ pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61145,7 +61145,7 @@ pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61168,7 +61168,7 @@ pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61191,7 +61191,7 @@ pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61214,7 +61214,7 @@ pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -61243,7 +61243,7 @@ pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -61272,7 +61272,7 @@ pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -61301,7 +61301,7 @@ pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61323,7 +61323,7 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61350,7 +61350,7 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61372,7 +61372,7 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61399,7 +61399,7 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61421,7 +61421,7 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61448,7 +61448,7 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -61465,7 +61465,7 @@ pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -61482,7 +61482,7 @@ pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61505,7 +61505,7 @@ pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61528,7 +61528,7 @@ pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61551,7 +61551,7 @@ pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61574,7 +61574,7 @@ pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61597,7 +61597,7 @@ pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61620,7 +61620,7 @@ pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61643,7 +61643,7 @@ pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61666,7 +61666,7 @@ pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61689,7 +61689,7 @@ pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61712,7 +61712,7 @@ pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61735,7 +61735,7 @@ pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61758,7 +61758,7 @@ pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61781,7 +61781,7 @@ pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61804,7 +61804,7 @@ pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61827,7 +61827,7 @@ pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61850,7 +61850,7 @@ pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61873,7 +61873,7 @@ pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61896,7 +61896,7 @@ pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61919,7 +61919,7 @@ pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61942,7 +61942,7 @@ pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61965,7 +61965,7 @@ pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61988,7 +61988,7 @@ pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -62011,7 +62011,7 @@ pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -62034,7 +62034,7 @@ pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "SHA1 hash update accelerator, choose."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1c))]
@@ -62059,7 +62059,7 @@ pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 fixed rotate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1h))]
@@ -62084,7 +62084,7 @@ pub fn vsha1h_u32(hash_e: u32) -> u32 {
 }
 #[doc = "SHA1 hash update accelerator, majority"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1m))]
@@ -62109,7 +62109,7 @@ pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 hash update accelerator, parity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1p))]
@@ -62134,7 +62134,7 @@ pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1su0))]
@@ -62159,7 +62159,7 @@ pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> u
 }
 #[doc = "SHA1 schedule update accelerator, second part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1su1))]
@@ -62184,7 +62184,7 @@ pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SHA1 schedule update accelerator, upper part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256h2))]
@@ -62213,7 +62213,7 @@ pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4
 }
 #[doc = "SHA1 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256h))]
@@ -62242,7 +62242,7 @@ pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_
 }
 #[doc = "SHA256 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256su0))]
@@ -62267,7 +62267,7 @@ pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SHA256 schedule update accelerator, second part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256su1))]
@@ -62291,7 +62291,7 @@ pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
     }
     unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62304,7 +62304,7 @@ fn vshiftlins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     }
     unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62317,7 +62317,7 @@ fn vshiftlins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     }
     unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62330,7 +62330,7 @@ fn vshiftlins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     }
     unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62343,7 +62343,7 @@ fn vshiftlins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     }
     unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62356,7 +62356,7 @@ fn vshiftlins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     }
     unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62369,7 +62369,7 @@ fn vshiftlins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     }
     unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62382,7 +62382,7 @@ fn vshiftlins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     }
     unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62397,7 +62397,7 @@ fn vshiftlins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62412,7 +62412,7 @@ fn vshiftrins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62427,7 +62427,7 @@ fn vshiftrins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62442,7 +62442,7 @@ fn vshiftrins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62457,7 +62457,7 @@ fn vshiftrins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62472,7 +62472,7 @@ fn vshiftrins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62487,7 +62487,7 @@ fn vshiftrins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62502,7 +62502,7 @@ fn vshiftrins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62517,7 +62517,7 @@ fn vshiftrins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62540,7 +62540,7 @@ pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62563,7 +62563,7 @@ pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62586,7 +62586,7 @@ pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62609,7 +62609,7 @@ pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62632,7 +62632,7 @@ pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62655,7 +62655,7 @@ pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62678,7 +62678,7 @@ pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62701,7 +62701,7 @@ pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62724,7 +62724,7 @@ pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62747,7 +62747,7 @@ pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62770,7 +62770,7 @@ pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62793,7 +62793,7 @@ pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62816,7 +62816,7 @@ pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62839,7 +62839,7 @@ pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62862,7 +62862,7 @@ pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62885,7 +62885,7 @@ pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -62914,7 +62914,7 @@ pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -62943,7 +62943,7 @@ pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -62972,7 +62972,7 @@ pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63001,7 +63001,7 @@ pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63030,7 +63030,7 @@ pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63059,7 +63059,7 @@ pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63088,7 +63088,7 @@ pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63117,7 +63117,7 @@ pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63146,7 +63146,7 @@ pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63175,7 +63175,7 @@ pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63204,7 +63204,7 @@ pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63233,7 +63233,7 @@ pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63262,7 +63262,7 @@ pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63291,7 +63291,7 @@ pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63320,7 +63320,7 @@ pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63349,7 +63349,7 @@ pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
@@ -63372,7 +63372,7 @@ pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
@@ -63395,7 +63395,7 @@ pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
@@ -63418,7 +63418,7 @@ pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
@@ -63441,7 +63441,7 @@ pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
@@ -63464,7 +63464,7 @@ pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
@@ -63487,7 +63487,7 @@ pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
@@ -63511,7 +63511,7 @@ pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
@@ -63535,7 +63535,7 @@ pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
@@ -63559,7 +63559,7 @@ pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
@@ -63583,7 +63583,7 @@ pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
@@ -63607,7 +63607,7 @@ pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
@@ -63631,7 +63631,7 @@ pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
@@ -63655,7 +63655,7 @@ pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
@@ -63679,7 +63679,7 @@ pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
@@ -63707,7 +63707,7 @@ pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
@@ -63735,7 +63735,7 @@ pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
@@ -63763,7 +63763,7 @@ pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
@@ -63791,7 +63791,7 @@ pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
@@ -63819,7 +63819,7 @@ pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
@@ -63847,7 +63847,7 @@ pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
@@ -63875,7 +63875,7 @@ pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
@@ -63903,7 +63903,7 @@ pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
@@ -63926,7 +63926,7 @@ pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
@@ -63949,7 +63949,7 @@ pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
@@ -63972,7 +63972,7 @@ pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
@@ -63995,7 +63995,7 @@ pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
@@ -64018,7 +64018,7 @@ pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
@@ -64041,7 +64041,7 @@ pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64053,7 +64053,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64065,7 +64065,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64077,7 +64077,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64089,7 +64089,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64101,7 +64101,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64113,7 +64113,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64125,7 +64125,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64137,7 +64137,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64149,7 +64149,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64161,7 +64161,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64173,7 +64173,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64185,7 +64185,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64197,7 +64197,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64209,7 +64209,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64221,7 +64221,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64233,7 +64233,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64245,7 +64245,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64257,7 +64257,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64269,7 +64269,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64281,7 +64281,7 @@ pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64304,7 +64304,7 @@ pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64327,7 +64327,7 @@ pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64350,7 +64350,7 @@ pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64373,7 +64373,7 @@ pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64396,7 +64396,7 @@ pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64419,7 +64419,7 @@ pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64442,7 +64442,7 @@ pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64465,7 +64465,7 @@ pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64488,7 +64488,7 @@ pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64511,7 +64511,7 @@ pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64534,7 +64534,7 @@ pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64557,7 +64557,7 @@ pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64580,7 +64580,7 @@ pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64603,7 +64603,7 @@ pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64626,7 +64626,7 @@ pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64649,7 +64649,7 @@ pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64661,7 +64661,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64673,7 +64673,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64685,7 +64685,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64697,7 +64697,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64709,7 +64709,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64721,7 +64721,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64733,7 +64733,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64745,7 +64745,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64757,7 +64757,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64769,7 +64769,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64781,7 +64781,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64793,7 +64793,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64805,7 +64805,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64817,7 +64817,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64829,7 +64829,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64841,7 +64841,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64853,7 +64853,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64865,7 +64865,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64877,7 +64877,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64891,7 +64891,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -64909,7 +64909,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -64927,7 +64927,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -64945,7 +64945,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -64963,7 +64963,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -64983,7 +64983,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65003,7 +65003,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65021,7 +65021,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65039,7 +65039,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65059,7 +65059,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65079,7 +65079,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65104,7 +65104,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65129,7 +65129,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65155,7 +65155,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65181,7 +65181,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65195,7 +65195,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65209,7 +65209,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65223,7 +65223,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65237,7 +65237,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65251,7 +65251,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65265,7 +65265,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65279,7 +65279,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65293,7 +65293,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65307,7 +65307,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65321,7 +65321,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65335,7 +65335,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65349,7 +65349,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65363,7 +65363,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65377,7 +65377,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65391,7 +65391,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65405,7 +65405,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65419,7 +65419,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65433,7 +65433,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65447,7 +65447,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65461,7 +65461,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65475,7 +65475,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65489,7 +65489,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65503,7 +65503,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65517,7 +65517,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65533,7 +65533,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65549,7 +65549,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65568,7 +65568,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65587,7 +65587,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65606,7 +65606,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65625,7 +65625,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65647,7 +65647,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65669,7 +65669,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65694,7 +65694,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65719,7 +65719,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65739,7 +65739,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65759,7 +65759,7 @@ pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65784,7 +65784,7 @@ pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65809,7 +65809,7 @@ pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65834,7 +65834,7 @@ pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65859,7 +65859,7 @@ pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65884,7 +65884,7 @@ pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65909,7 +65909,7 @@ pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65934,7 +65934,7 @@ pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65959,7 +65959,7 @@ pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65984,7 +65984,7 @@ pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66009,7 +66009,7 @@ pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66034,7 +66034,7 @@ pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66059,7 +66059,7 @@ pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66084,7 +66084,7 @@ pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66109,7 +66109,7 @@ pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66134,7 +66134,7 @@ pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66159,7 +66159,7 @@ pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66184,7 +66184,7 @@ pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66209,7 +66209,7 @@ pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66234,7 +66234,7 @@ pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66259,7 +66259,7 @@ pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66284,7 +66284,7 @@ pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66309,7 +66309,7 @@ pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66334,7 +66334,7 @@ pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -66357,7 +66357,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66380,7 +66380,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66403,7 +66403,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66426,7 +66426,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66449,7 +66449,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66472,7 +66472,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66491,7 +66491,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66510,7 +66510,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66529,7 +66529,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66548,7 +66548,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66567,7 +66567,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66586,7 +66586,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66605,7 +66605,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66624,7 +66624,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66640,7 +66640,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66656,7 +66656,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66672,7 +66672,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66688,7 +66688,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66704,7 +66704,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66720,7 +66720,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66736,7 +66736,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66752,7 +66752,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66771,7 +66771,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66790,7 +66790,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66809,7 +66809,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66828,7 +66828,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66847,7 +66847,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66866,7 +66866,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66885,7 +66885,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66904,7 +66904,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66920,7 +66920,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66936,7 +66936,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66952,7 +66952,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66968,7 +66968,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66984,7 +66984,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67000,7 +67000,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67016,7 +67016,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67032,7 +67032,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67051,7 +67051,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67070,7 +67070,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67089,7 +67089,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67108,7 +67108,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67127,7 +67127,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67146,7 +67146,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67165,7 +67165,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67184,7 +67184,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67200,7 +67200,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67216,7 +67216,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67232,7 +67232,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67248,7 +67248,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67264,7 +67264,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67280,7 +67280,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67296,7 +67296,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67312,7 +67312,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67335,7 +67335,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67358,7 +67358,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67381,7 +67381,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67404,7 +67404,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67427,7 +67427,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67450,7 +67450,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67473,7 +67473,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67496,7 +67496,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67519,7 +67519,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67542,7 +67542,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67565,7 +67565,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67588,7 +67588,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67611,7 +67611,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67634,7 +67634,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67657,7 +67657,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67680,7 +67680,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67703,7 +67703,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67726,7 +67726,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67749,7 +67749,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67772,7 +67772,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67795,7 +67795,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67818,7 +67818,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67841,7 +67841,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67864,7 +67864,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67887,7 +67887,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67910,7 +67910,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67933,7 +67933,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67956,7 +67956,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67979,7 +67979,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68002,7 +68002,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68025,7 +68025,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68048,7 +68048,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68071,7 +68071,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68094,7 +68094,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68117,7 +68117,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68136,7 +68136,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
     vst1q_s16_x4(transmute(a), transmute(b))
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68150,7 +68150,7 @@ unsafe fn vst1_v1i64<const ALIGN: i32>(addr: *const i8, val: int64x1_t) {
     }
     _vst1_v1i64(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68164,7 +68164,7 @@ unsafe fn vst1_v2f32<const ALIGN: i32>(addr: *const i8, val: float32x2_t) {
     }
     _vst1_v2f32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68178,7 +68178,7 @@ unsafe fn vst1_v2i32<const ALIGN: i32>(addr: *const i8, val: int32x2_t) {
     }
     _vst1_v2i32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68192,7 +68192,7 @@ unsafe fn vst1_v4i16<const ALIGN: i32>(addr: *const i8, val: int16x4_t) {
     }
     _vst1_v4i16(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68206,7 +68206,7 @@ unsafe fn vst1_v8i8<const ALIGN: i32>(addr: *const i8, val: int8x8_t) {
     }
     _vst1_v8i8(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68220,7 +68220,7 @@ unsafe fn vst1q_v16i8<const ALIGN: i32>(addr: *const i8, val: int8x16_t) {
     }
     _vst1q_v16i8(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68234,7 +68234,7 @@ unsafe fn vst1q_v2i64<const ALIGN: i32>(addr: *const i8, val: int64x2_t) {
     }
     _vst1q_v2i64(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68248,7 +68248,7 @@ unsafe fn vst1q_v4f32<const ALIGN: i32>(addr: *const i8, val: float32x4_t) {
     }
     _vst1q_v4f32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68262,7 +68262,7 @@ unsafe fn vst1q_v4i32<const ALIGN: i32>(addr: *const i8, val: int32x4_t) {
     }
     _vst1q_v4i32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68280,7 +68280,7 @@ unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -68298,7 +68298,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -68316,7 +68316,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -68341,7 +68341,7 @@ pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -68362,7 +68362,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -68383,7 +68383,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68402,7 +68402,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68421,7 +68421,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68440,7 +68440,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68459,7 +68459,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68478,7 +68478,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68497,7 +68497,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68516,7 +68516,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68535,7 +68535,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68554,7 +68554,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68573,7 +68573,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68589,7 +68589,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68605,7 +68605,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68621,7 +68621,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68637,7 +68637,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68653,7 +68653,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68669,7 +68669,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68685,7 +68685,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68701,7 +68701,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68724,7 +68724,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68747,7 +68747,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68768,7 +68768,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68789,7 +68789,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68810,7 +68810,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68831,7 +68831,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68852,7 +68852,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68873,7 +68873,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68894,7 +68894,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68915,7 +68915,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68936,7 +68936,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -68954,7 +68954,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -68972,7 +68972,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -68990,7 +68990,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69008,7 +69008,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69026,7 +69026,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69044,7 +69044,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69062,7 +69062,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69087,7 +69087,7 @@ pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69112,7 +69112,7 @@ pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69137,7 +69137,7 @@ pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69162,7 +69162,7 @@ pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69187,7 +69187,7 @@ pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69212,7 +69212,7 @@ pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69237,7 +69237,7 @@ pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69262,7 +69262,7 @@ pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69285,7 +69285,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69301,7 +69301,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69320,7 +69320,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69343,7 +69343,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69366,7 +69366,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69389,7 +69389,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69412,7 +69412,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69435,7 +69435,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69458,7 +69458,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69481,7 +69481,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69504,7 +69504,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69527,7 +69527,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69550,7 +69550,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69573,7 +69573,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69592,7 +69592,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69611,7 +69611,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -69632,7 +69632,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -69653,7 +69653,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69669,7 +69669,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69685,7 +69685,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69701,7 +69701,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69717,7 +69717,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69733,7 +69733,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69749,7 +69749,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69765,7 +69765,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69781,7 +69781,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69800,7 +69800,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69819,7 +69819,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69838,7 +69838,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69857,7 +69857,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69876,7 +69876,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69895,7 +69895,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69914,7 +69914,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69933,7 +69933,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69961,7 +69961,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69989,7 +69989,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70012,7 +70012,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70035,7 +70035,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70060,7 +70060,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70085,7 +70085,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70103,7 +70103,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70128,7 +70128,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70153,7 +70153,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70178,7 +70178,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70203,7 +70203,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70224,7 +70224,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70245,7 +70245,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70266,7 +70266,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70287,7 +70287,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70308,7 +70308,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70329,7 +70329,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70350,7 +70350,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70375,7 +70375,7 @@ pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70400,7 +70400,7 @@ pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70425,7 +70425,7 @@ pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70450,7 +70450,7 @@ pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70475,7 +70475,7 @@ pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70500,7 +70500,7 @@ pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70525,7 +70525,7 @@ pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70550,7 +70550,7 @@ pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -70573,7 +70573,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -70592,7 +70592,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -70608,7 +70608,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -70631,7 +70631,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70654,7 +70654,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70677,7 +70677,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70700,7 +70700,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70723,7 +70723,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70746,7 +70746,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70769,7 +70769,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70792,7 +70792,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70815,7 +70815,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70838,7 +70838,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70861,7 +70861,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70887,7 +70887,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70913,7 +70913,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -70934,7 +70934,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -70955,7 +70955,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -70978,7 +70978,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71001,7 +71001,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71017,7 +71017,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71040,7 +71040,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71063,7 +71063,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71086,7 +71086,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71109,7 +71109,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71132,7 +71132,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71151,7 +71151,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71170,7 +71170,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71189,7 +71189,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71208,7 +71208,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71227,7 +71227,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71246,7 +71246,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71265,7 +71265,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71284,7 +71284,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71313,7 +71313,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71342,7 +71342,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71372,7 +71372,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71402,7 +71402,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71428,7 +71428,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71454,7 +71454,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71480,7 +71480,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71506,7 +71506,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71532,7 +71532,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71558,7 +71558,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71584,7 +71584,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71612,7 +71612,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71640,7 +71640,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71661,7 +71661,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71689,7 +71689,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71717,7 +71717,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71745,7 +71745,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71773,7 +71773,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71798,7 +71798,7 @@ pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71823,7 +71823,7 @@ pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71848,7 +71848,7 @@ pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71873,7 +71873,7 @@ pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71898,7 +71898,7 @@ pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71923,7 +71923,7 @@ pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71948,7 +71948,7 @@ pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71973,7 +71973,7 @@ pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -71996,7 +71996,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -72019,7 +72019,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -72038,7 +72038,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -72061,7 +72061,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72084,7 +72084,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72107,7 +72107,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72130,7 +72130,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72153,7 +72153,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72176,7 +72176,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72199,7 +72199,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72222,7 +72222,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72245,7 +72245,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72268,7 +72268,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72291,7 +72291,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -72312,7 +72312,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
 #[cfg_attr(
@@ -72334,7 +72334,7 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
 #[cfg_attr(
@@ -72356,7 +72356,7 @@ pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
@@ -72377,7 +72377,7 @@ pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
@@ -72398,7 +72398,7 @@ pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72419,7 +72419,7 @@ pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72440,7 +72440,7 @@ pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72461,7 +72461,7 @@ pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72482,7 +72482,7 @@ pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72503,7 +72503,7 @@ pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72524,7 +72524,7 @@ pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72545,7 +72545,7 @@ pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72566,7 +72566,7 @@ pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72587,7 +72587,7 @@ pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72608,7 +72608,7 @@ pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72629,7 +72629,7 @@ pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72650,7 +72650,7 @@ pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72671,7 +72671,7 @@ pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72692,7 +72692,7 @@ pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72713,7 +72713,7 @@ pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72734,7 +72734,7 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72756,7 +72756,7 @@ pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72778,7 +72778,7 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72800,7 +72800,7 @@ pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72822,7 +72822,7 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72844,7 +72844,7 @@ pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72866,7 +72866,7 @@ pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72888,7 +72888,7 @@ pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72910,7 +72910,7 @@ pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72932,7 +72932,7 @@ pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72954,7 +72954,7 @@ pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72976,7 +72976,7 @@ pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72998,7 +72998,7 @@ pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73023,7 +73023,7 @@ pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73048,7 +73048,7 @@ pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73073,7 +73073,7 @@ pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73098,7 +73098,7 @@ pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73123,7 +73123,7 @@ pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73148,7 +73148,7 @@ pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73169,7 +73169,7 @@ pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73190,7 +73190,7 @@ pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73211,7 +73211,7 @@ pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73232,7 +73232,7 @@ pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73253,7 +73253,7 @@ pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73274,7 +73274,7 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73302,7 +73302,7 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73334,7 +73334,7 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73363,7 +73363,7 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73397,7 +73397,7 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73412,7 +73412,7 @@ fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73423,7 +73423,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73435,7 +73435,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73452,7 +73452,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73464,7 +73464,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73481,7 +73481,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73496,7 +73496,7 @@ fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73507,7 +73507,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73519,7 +73519,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73538,7 +73538,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73550,7 +73550,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73569,7 +73569,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73584,7 +73584,7 @@ fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73595,7 +73595,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73614,7 +73614,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73639,7 +73639,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73658,7 +73658,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73683,7 +73683,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73698,7 +73698,7 @@ fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73709,7 +73709,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73729,7 +73729,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73756,7 +73756,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73776,7 +73776,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73803,7 +73803,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73817,7 +73817,7 @@ fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73827,7 +73827,7 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73838,7 +73838,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73855,7 +73855,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73866,7 +73866,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73883,7 +73883,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73897,7 +73897,7 @@ fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73907,7 +73907,7 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73925,7 +73925,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73949,7 +73949,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73967,7 +73967,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73991,7 +73991,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -74005,7 +74005,7 @@ fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -74015,7 +74015,7 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74034,7 +74034,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74060,7 +74060,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74079,7 +74079,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74105,7 +74105,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -74126,7 +74126,7 @@ fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74146,7 +74146,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74174,7 +74174,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74194,7 +74194,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74222,7 +74222,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74242,7 +74242,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74270,7 +74270,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
@@ -74300,7 +74300,7 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
@@ -74330,7 +74330,7 @@ pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74359,7 +74359,7 @@ pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74388,7 +74388,7 @@ pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74417,7 +74417,7 @@ pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74446,7 +74446,7 @@ pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74475,7 +74475,7 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74512,7 +74512,7 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74541,7 +74541,7 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74570,7 +74570,7 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74599,7 +74599,7 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74628,7 +74628,7 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74665,7 +74665,7 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74694,7 +74694,7 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74723,7 +74723,7 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74752,7 +74752,7 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74781,7 +74781,7 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74818,7 +74818,7 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74847,7 +74847,7 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74876,7 +74876,7 @@ pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74901,7 +74901,7 @@ pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74926,7 +74926,7 @@ pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74951,7 +74951,7 @@ pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74976,7 +74976,7 @@ pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75001,7 +75001,7 @@ pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75026,7 +75026,7 @@ pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75051,7 +75051,7 @@ pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75076,7 +75076,7 @@ pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75101,7 +75101,7 @@ pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75126,7 +75126,7 @@ pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75151,7 +75151,7 @@ pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75176,7 +75176,7 @@ pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75201,7 +75201,7 @@ pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75226,7 +75226,7 @@ pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75251,7 +75251,7 @@ pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75276,7 +75276,7 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75304,7 +75304,7 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75336,7 +75336,7 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75365,7 +75365,7 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75399,7 +75399,7 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
@@ -75428,7 +75428,7 @@ pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
@@ -75457,7 +75457,7 @@ pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -75486,7 +75486,7 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
@@ -75516,7 +75516,7 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
@@ -75546,7 +75546,7 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -75575,7 +75575,7 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -75604,7 +75604,7 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -75633,7 +75633,7 @@ pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75662,7 +75662,7 @@ pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75691,7 +75691,7 @@ pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75728,7 +75728,7 @@ pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75757,7 +75757,7 @@ pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75786,7 +75786,7 @@ pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75815,7 +75815,7 @@ pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75844,7 +75844,7 @@ pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75881,7 +75881,7 @@ pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75910,7 +75910,7 @@ pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75939,7 +75939,7 @@ pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75968,7 +75968,7 @@ pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75997,7 +75997,7 @@ pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -76034,7 +76034,7 @@ pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -76063,7 +76063,7 @@ pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -76092,7 +76092,7 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
@@ -76122,7 +76122,7 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
@@ -76152,7 +76152,7 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -76181,7 +76181,7 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -76210,7 +76210,7 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -76239,7 +76239,7 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76268,7 +76268,7 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76297,7 +76297,7 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76326,7 +76326,7 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76355,7 +76355,7 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76384,7 +76384,7 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76413,7 +76413,7 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76442,7 +76442,7 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76479,7 +76479,7 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76508,7 +76508,7 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76537,7 +76537,7 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76574,7 +76574,7 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76603,7 +76603,7 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76632,7 +76632,7 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76669,7 +76669,7 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index d69089b95b..3992eaee30 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -32,6 +32,7 @@
     x86_amx_intrinsics,
     f16,
     aarch64_unstable_target_feature,
+    target_feature_inline_always,
     bigint_helper_methods,
     funnel_shifts,
     avx10_target_feature,
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index 0cdff6ff6c..71301c5ba6 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1736,7 +1736,7 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok
         );
     }
 
-    tokens.append_all(quote! { #[inline] });
+    tokens.append_all(quote! { #[inline(always)] });
 
     match endianness {
         Endianness::Little => tokens.append_all(quote! { #[cfg(target_endian = "little")] }),

From 006c86da09b589ff79a2ae1a9b58aeda71e12fff Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Mon, 22 Dec 2025 10:31:05 +0000
Subject: [PATCH 096/326] Creates README for stdarch-gen-arm

---
 crates/stdarch-gen-arm/README.md | 300 +++++++++++++++++++++++++++++++
 1 file changed, 300 insertions(+)
 create mode 100644 crates/stdarch-gen-arm/README.md

diff --git a/crates/stdarch-gen-arm/README.md b/crates/stdarch-gen-arm/README.md
new file mode 100644
index 0000000000..4da14bcbb6
--- /dev/null
+++ b/crates/stdarch-gen-arm/README.md
@@ -0,0 +1,300 @@
+# stdarch-gen-arm generator guide
+## Running the generator
+- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec`
+```
+$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
+    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s
+     Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec`
+```
+## Input/Output
+### Input files (intrinsic YAML definitions)
+ - `crates/stdarch-gen-arm/spec/<feature>/*.spec.yml`
+### Output files
+ - Generated intrinsics:
+	 - `crates/core_arch/src/<arch>/<feature>/generated.rs`
+ - Generated load/store tests:
+	 - `crates/core_arch/src/<arch>/<feature>/ld_st_tests_<arch>.rs`
+	 - Only generated when `test: { load: <idx> }` or `test: { store: <idx> }` is set for SVE/SVE2 intrinsics.
+## `.spec.yml` file anatomy
+```
+---
+Configs
+---
+Variable definitions
+---
+
+Intrinsic definitions
+
+---
+```
+- If you're new to YAML syntax, consider [reviewing](https://quickref.me/yaml.html) some of the less obvious syntax and features.
+- For example, mapping an attribute to a sequence can be done in two different ways:
+```yaml
+attribute: [item_a, item_b, item_c]
+```
+or
+```yaml
+attribute:
+    - item_a
+    - item_b
+    - item_c
+``` 
+## Configs
+- Mappings defining top-level settings applied to all intrinsics:
+- `arch_cfgs`
+    - Sequence of mappings specifying `arch_name`, `target_feature` (sequence), and `llvm_prefix`.
+- `uses_neon_types`(_Optional_)
+    - A boolean specifying whether to emit NEON type imports in generated code.
+- `auto_big_endian`(_Optional_)
+    - A boolean specifying whether to auto-generate big-endian shuffles when possible.
+- `auto_llvm_sign_conversion`(_Optional_)
+    - A boolean specifying whether to auto-convert LLVM wrapper args to signed types.
+## Variable definitions
+- Defines YAML anchors/variables to avoid repetition.
+- Commonly used for stability attributes, cfgs and target features.
+## Intrinsic definitions
+### Example
+```yaml
+    - name: "vtst{neon_type[0].no}"
+      doc: "Signed compare bitwise Test bits nonzero"
+      arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+      return_type: "{neon_type[1]}"
+      attr:
+        - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]]
+        - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      safety: safe
+      types:
+        - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)']
+        - [int64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)']
+        - [poly64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)']
+        - [poly64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)']
+      compose:
+        - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}]
+        - Let: [d, "{type[2]}", "{type[3]}"]
+        - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]]
+```
+
+### Explanation of fields
+- `name`
+    - The name of the intrinsic
+    - Often built from a base name followed by a type suffix
+- `doc` (_Optional_)
+    - A string explaining the purpose of the intrinsic
+- `static_defs` (_Optional_)
+    - A sequence of const generics of the format `"const <NAME>: <type>"`
+- `arguments`
+    - A sequence of strings in the format `"<argname>: <argtype>"`
+- `return_type` (_Optional_)
+    - A string specifying the return type. If omitted, the intrinsic returns `()`.
+- `attr` (_Optional_)
+    - A sequence of items defining the attributes to be applied to the intrinsic. Often stability attributes, target features, or `assert_instr` tests. At least one of `attr` or `assert_instr` must be set.
+- `target_features` (_Optional_)
+    - A sequence of target features to enable for this intrinsic (merged with any global `arch_cfgs` settings).
+- `assert_instr` (_Optional_)
+    - A sequence of strings expected to be found in the assembly. Required if `attr` is not set.
+- `safety` (_Optional_)
+    - Use `safe`, or map `unsafe:` to a sequence of unsafety comments:
+        - `custom: "<string>"`
+        - `uninitialized`
+        - `pointer_offset`, `pointer_offset_vnum`, or `dereference` (optionally qualified with `predicated`, `predicated_non_faulting`, or `predicated_first_faulting`)
+        - `unpredictable_on_fault`
+        - `non_temporal`
+        - `neon`
+        - `no_provenance: "<string>"`
+- `substitutions` (_Optional_)
+    - Mappings of custom wildcard names to either `MatchSize` or `MatchKind` expressions
+- `types`
+    - A sequence or sequence of sequences specifying the types to use when producing each intrinsic variant. These sequences can then be indexed by wildcards.
+- `constraints` (_Optional_)
+    - A sequence of mappings. Each specifies a variable and a constraint. The available mappings are:
+    - Assert a variable's value exists in a sequence of i32's
+        - Usage: `{ variable: <name>, any_values: [<i32>,...] }`
+    - Assert a variable's value exists in a range (inclusive)
+        - Usage: `{ variable: <name>, range: [<i32>, <i32>] }`
+    - Assert a variable's value exists in a range via a match (inclusive)
+        - Usage: `{ variable: <name>, range: <MatchSize returning [i32,i32]> }`
+    - Assert a variable's value does not exceed the number of elements in a SVE type `<type>`.
+        - Usage: `{ variable: <name>, sve_max_elems_type: <type> }`
+    - Assert a variable's value does not exceed the number of elements in a vector type `<type>`.
+        - Usage: `{ variable: <name>, vec_max_elems_type: <type> }`
+- `predication_methods` (_Optional_)
+    - Configuration for predicate-form variants. Only used when the intrinsic name includes an `_m*_` wildcard (e.g., `{_mx}`, `{_mxz}`).
+    - `zeroing_method`: Required when requesting `_z`; either `{ drop: <arg> }` to remove an argument and replace it with a zero initialiser, or `{ select: <predicate_var> }` to select zeros into a predicate.
+    - `dont_care_method`: How `_x` should be implemented (`inferred`, `as_zeroing`, or `as_merging`).
+- `compose`
+    - A sequence of expressions that make up the body of the intrinsic
+- `big_endian_inverse` (_Optional_)
+    - A boolean, default false. If true, generates two implementations of each intrinsic variant, one for each endianness, and attempts to automatically generate the required bit swizzles
+- `visibility` (_Optional_)
+    - Function visibility. One of `public` (default) or `private`.
+- `n_variant_op` (_Optional_)
+    - Enables generation of an `_n` variant when the intrinsic name includes the `{_n}` wildcard. Set to the operand name that should be splattered for the `_n` form.
+- `test` (_Optional_)
+	- When set, load/store tests are automatically generated.
+    - A mapping of either `load` or `store` to a number that indexes `types` to specify the type that the test should be addressing in memory. 
+### Expressions
+#### Common
+- `Let`
+    - Defines a variable
+    - Usage: `Let: [<variable>, <type(optional)>, <expression>]`
+- `Const`
+    - Defines a const
+    - Usage: `Const: [<variable>, <type>, <expression>]`
+- `Assign`
+    - Performs variable assignment
+    - Usage: `Assign: [<variable>, <expression>]`
+- `FnCall`
+    - Performs a function call
+    - Usage: `FnCall: [<function pointer: expression>, [<argument: expression>, ... ], [<turbofish argument: expression>, ...](optional), <unsafe wrapper(optional): bool>]`
+- `MacroCall`
+    - Performs a macro call
+    - Usage: `MacroCall: [<macro name>, <token stream>]`
+- `MethodCall`
+    - Performs a method call
+    - Usage: `MethodCall: [<object: expression>, <method name>, [<argument: expression>, ... ]]`
+- `LLVMLink`
+    - Creates an LLVM link and stores the function's name in the wildcard `{llvm_link}` for later use in subsequent expressions.
+    - If left unset, the arguments and return type inherit from the intrinsic's signature by default. The links will also be set automatically if unset.
+    - Usage:
+```yaml
+LLVMLink:
+    name: <name>
+    arguments: [<expression>, ... ](optional)
+    return_type: <return type>(optional)
+    links: (optional)
+        - link: <link>
+          arch: <arch>
+        - ...
+```
+- `Identifier`
+    - Emits a symbol. Prepend with a `$` to treat it as a scope variable, which engages variable tracking and enables inference. For example, `my_function_name` for a generic symbol or `$my_variable` for a variable.
+    - Usage `Identifier: [<symbol name>, <Variable|Symbol>]`
+- `CastAs`
+    - Casts an expression to an unchecked type
+    - Usage: `CastAs: [<expression>, <type>]`
+- `MatchSize`
+    - Allows for conditional generation depending on the size of a specified type
+    - Usage:
+```yaml
+MatchSize:
+    - <type>
+    - default: <expression>
+      byte(optional): <expression>
+      halfword(optional): <expression>
+      doubleword(optional): <expression>
+```
+- `MatchKind`
+    - Allows for conditional generation depending on the kind of a specified type
+```yaml
+MatchKind:
+    - <type>
+    - default: <expression>
+      float(optional): <expression>
+      unsigned(optional): <expression>
+```
+#### Rarely Used
+- `IntConstant`
+    - Constant signed integer expression
+    - Usage: `IntConstant: <i32>`
+- `FloatConstant`
+    - Constant floating-point expression
+    - Usage: `FloatConstant: <f32>`
+- `BoolConstant`
+    - Constant boolean expression
+    - Usage: `BoolConstant: <bool>`
+- `Array`
+    - An array of expressions
+    - Usage: `Array: [<expression>, ...]`
+- `SvUndef`
+    - Returns the LLVM `undef` symbol
+    - Usage: `SvUndef`
+- `Multiply`
+    - Simply `*`
+    - Usage: `Multiply: [<expression>, <expression>]`
+- `Xor`
+    - Simply `^`
+    - Usage: `Xor: [<expression>, <expression>]`
+- `ConvertConst`
+    - Converts the specified constant to the specified type's kind
+    - Usage: `ConvertConst: [<type>, <i32>]`
+- `Type`
+    - Yields the given type in the Rust representation
+    - Usage: `Type: [<type>]`
+
+### Wildstrings
+- Wildstrings let you take advantage of wildcards.
+- For example, they are often used in intrinsic names `name: "vtst{neon_type[0].no}"`
+- As shown above, wildcards are identified by the surrounding curly brackets.
+- Double curly brackets can be used to escape wildcard functionality if you need literal curly brackets in the generated intrinsic.
+### Wildcards
+Wildcards are heavily used in the spec. They let you write generalised definitions for a group of intrinsics that generate multiple variants. The wildcard itself is replaced with the relevant string in each variant.
+Ignoring endianness, for each row in the `types` field of an intrinsic in the spec, a variant of the intrinsic will be generated. That row's contents can be indexed by the wildcards. Below is the behaviour of each wildcard.
+- `type[<index: usize>]`
+    - Replaced in each variant with the value in the indexed position in the relevant row of the `types` field.
+    - For unnested sequences of `types` (i.e., `types` is a sequence where each element is a single item, not another sequence), the square brackets can be omitted. Simply: `type`
+- `neon_type[<index: usize>]`
+    - Extends the behaviour of `type` with some NEON-specific features and inference.
+    - Tuples: This wildcard can also be written as `neon_type_x<n>` where `n` is in the set `{2,3,4}`. This generates the `n`-tuple variant of the (inferred) NEON type.
+    - Suffixes: These modify the behaviour of the wildcard from simple substitution.
+	    - `no` -  normal behaviour. Tries to do as much work as it can for you, inferring when to emit:
+            - Regular type-size suffixes: `_s8`, `_u16`, `_f32`, ...
+            - `q` variants for double-width (128b) vector types: `q_s8`, `q_u16`, `q_f32`, ...
+            - `_x<n>` variants for tuple vector types: `_s8_x2`, `_u32_x3`, `_f64_x4`, ...
+            - As well as any combination of the above: `q_s16_x16` ...
+    - Most of the other suffixes modify the normal behaviour by disabling features or adding new ones. (See table below)
+- `sve_type[<index: usize>]`
+    - Similar to `neon_type`, but without the suffixes.
+- `size[<index: usize>]`
+    - The size (in bits) of the indexed type.
+- `size_minus_one[<index: usize>]`
+    - Emits the size (in bits) of the indexed type minus one.
+- `size_literal[<index: usize>]`
+    - The literal representation of the indexed type.
+    - `b`: byte, `h`: halfword, `w`: word, or `d`: double.
+- `type_kind[<index: usize>]`
+    - The literal representation of the indexed type's kind.
+    - `f`: float, `s`: signed, `u`: unsigned, `p`: polynomial, `b`: boolean.
+- `size_in_bytes_log2[<index: usize>]`
+    - Log2 of the size of the indexed type in *bytes*.
+- `predicate[<index: usize>]`
+    - SVE predicate vector type inferred from the indexed type.
+- `max_predicate`
+    - The same as predicate, but uses the largest type in the relevant `types` sequence/row.
+- `_n`
+    - Emits the current N-variant suffix when `n_variant_op` is configured.
+- `<wildcard> as <type>`
+    - If `<wildcard>` evaluates to a vector, it produces a vector of the same shape, but with `<type>` as the base type.
+- `llvm_link`
+    - If the `LLVMLink` mapping has been set for an intrinsic, this will give the name of the link.
+- `_m*`
+    - Predicate form masks. Use wildcards such as `{_mx}` or `{_mxz}` to expand merging/don't-care/zeroing variants according to the mask.
+- `<custom>`
+    - You may simply call upon wildcards defined under `substitutions`.
+### neon_type suffixes
+
+| suffix            | implication                                   |
+| ----------------- | --------------------------------------------- |
+| `.no`             | Normal                                        |
+| `.noq`            | Never include `q`s                            |
+| `.nox`            | Never include `_x<n>`s                        |
+| `.N`              | Include `_n_`, e.g., `_n_s8`                  |
+| `.noq_N`          | Include `_n_`, but never `q`s                 |
+| `.dup`            | Include `_dup_`, e.g., `_dup_s8`              |
+| `.dup_nox`        | Include `_dup_` but never `_x<n>`s            |
+| `.lane`           | Include `_lane_`, e.g., `_lane_s8`            |
+| `.lane_nox`       | Include `_lane_`, but never `_x<n>`s          |
+| `.rot90`          | Include `_rot90_`, e.g., `_rot90_s8`          |
+| `.rot180`         | Include `_rot180_`, e.g., `_rot180_s8`        |
+| `.rot270`         | Include `_rot270_`, e.g., `_rot270_s8`        |
+| `.rot90_lane`     | Include `_rot90_lane_`                        |
+| `.rot180_lane`    | Include `_rot180_lane_`                       |
+| `.rot270_lane`    | Include `_rot270_lane_`                       |
+| `.rot90_laneq`    | Include `_rot90_laneq_`                       |
+| `.rot180_laneq`   | Include `_rot180_laneq_`                      |
+| `.rot270_laneq`   | Include `_rot270_laneq_`                      |
+| `.base`           | Produce only the size, e.g., `8`, `16`        |
+| `.u`              | Produce the type's unsigned equivalent        |
+| `.laneq_nox`      | Include `_laneq_`, but never `_x<n>`s         |
+| `.tuple`          | Produce only the size of the tuple, e.g., `3` |
+| `.base_byte_size` | Produce only the size in bytes.               |
+ 

From 804f09a0544da009acb3f7d60a8933f4c566f155 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 13 Jan 2026 12:11:18 +0100
Subject: [PATCH 097/326] stabilize `__jscvt`

---
 crates/core_arch/src/aarch64/neon/generated.rs    | 2 +-
 crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 7743e52f4f..90dba4409e 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -49,7 +49,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 #[inline]
 #[target_feature(enable = "jsconv")]
 #[cfg_attr(test, assert_instr(fjcvtzs))]
-#[unstable(feature = "stdarch_aarch64_jscvt", issue = "147555")]
+#[stable(feature = "stdarch_aarch64_jscvt", since = "CURRENT_RUSTC_VERSION")]
 pub fn __jcvt(a: f64) -> i32 {
     unsafe extern "unadjusted" {
         #[cfg_attr(
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 8f36c525fa..a951343e01 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -63,8 +63,8 @@ neon-unstable-f16: &neon-unstable-f16
 neon-unstable-feat-lut: &neon-unstable-feat-lut
   FnCall: [unstable, ['feature = "stdarch_neon_feat_lut"', 'issue = "138050"']]
 
-aarch64-unstable-jscvt: &aarch64-unstable-jscvt
-  FnCall: [unstable, ['feature = "stdarch_aarch64_jscvt"', 'issue = "147555"']]
+aarch64-stable-jscvt: &aarch64-stable-jscvt
+  FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']]
 
 # #[cfg(target_endian = "little")]
 little-endian: &little-endian
@@ -14275,7 +14275,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "jsconv"']]
       - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["fjcvtzs"]] }]]
-      - *aarch64-unstable-jscvt
+      - *aarch64-stable-jscvt
     safety: safe
     types:
       - f64

From e36c3c86b08a655289c8957154ddcd37d2f7813f Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 21 Jan 2026 20:57:49 +0100
Subject: [PATCH 098/326] test `vmulh_lane_f16` in intrinsic test

---
 crates/intrinsic-test/missing_aarch64.txt    | 3 ---
 crates/intrinsic-test/missing_aarch64_be.txt | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/crates/intrinsic-test/missing_aarch64.txt b/crates/intrinsic-test/missing_aarch64.txt
index bbcfc40c69..814756cefa 100644
--- a/crates/intrinsic-test/missing_aarch64.txt
+++ b/crates/intrinsic-test/missing_aarch64.txt
@@ -59,6 +59,3 @@ vluti4q_laneq_u8
 
 # Broken in Clang
 vcvth_s16_f16
-# FIXME: Broken output due to missing f16 printing support in Rust, see git blame for this line
-vmulh_lane_f16
-vmulh_laneq_f16
diff --git a/crates/intrinsic-test/missing_aarch64_be.txt b/crates/intrinsic-test/missing_aarch64_be.txt
index 28e1d9203e..1fa8fb7f16 100644
--- a/crates/intrinsic-test/missing_aarch64_be.txt
+++ b/crates/intrinsic-test/missing_aarch64_be.txt
@@ -100,6 +100,3 @@ vluti4q_laneq_u8
 
 # Broken in Clang
 vcvth_s16_f16
-# FIXME: Broken output due to missing f16 printing support in Rust
-vmulh_lane_f16
-vmulh_laneq_f16

From 0944bd4052265cb804f1d2dc9a31beacca037167 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 21 Jan 2026 13:11:07 +0100
Subject: [PATCH 099/326] use `simd_extract_dyn` for `extract`

---
 crates/core_arch/src/powerpc/altivec.rs |  8 ++++----
 crates/core_arch/src/simd.rs            | 15 ++++++++-------
 crates/core_arch/src/x86/test.rs        | 21 ++++++++++++++-------
 3 files changed, 26 insertions(+), 18 deletions(-)

diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index c1881da08f..b9a25a9d85 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -4740,7 +4740,7 @@ mod tests {
         for off in 0..16 {
             let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off)));
             for i in 0..16 {
-                let v = val.extract(i);
+                let v = val.extract_dyn(i);
                 assert_eq!(off as usize + i, v as usize);
             }
         }
@@ -4795,7 +4795,7 @@ mod tests {
         )];
         for off in 0..16 {
             let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8));
-            assert_eq!(off as u8, v.extract(off as _));
+            assert_eq!(off as u8, v.extract_dyn(off as _));
         }
     }
 
@@ -4804,7 +4804,7 @@ mod tests {
         let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)];
         for off in 0..8 {
             let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16));
-            assert_eq!(off as u16, v.extract(off as _));
+            assert_eq!(off as u16, v.extract_dyn(off as _));
         }
     }
 
@@ -4813,7 +4813,7 @@ mod tests {
         let pat = [u32x4::new(0, 1, 2, 3)];
         for off in 0..4 {
             let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32));
-            assert_eq!(off as u32, v.extract(off as _));
+            assert_eq!(off as u32, v.extract_dyn(off as _));
         }
     }
 
diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index 926163ac4c..b670092f5b 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -60,13 +60,14 @@ impl<T: SimdElement, const N: usize> Simd<T, N> {
         unsafe { simd_shuffle!(one, one, [0; N]) }
     }
 
-    /// Extract the element at position `index`.
-    /// `index` is not a constant so this is not efficient!
-    /// Use for testing only.
-    // FIXME: Workaround rust@60637
-    #[inline(always)]
-    pub(crate) const fn extract(&self, index: usize) -> T {
-        self.as_array()[index]
+    /// Extract the element at position `index`. Note that `index` is not a constant so this
+    /// operation is not efficient on most platforms. Use for testing only.
+    #[inline]
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub(crate) const fn extract_dyn(&self, index: usize) -> T {
+        assert!(index < N);
+        // SAFETY: self is a vector, T its element type.
+        unsafe { crate::intrinsics::simd::simd_extract_dyn(*self, index as u32) }
     }
 
     #[inline]
diff --git a/crates/core_arch/src/x86/test.rs b/crates/core_arch/src/x86/test.rs
index 4b2ef26044..402c2a6a81 100644
--- a/crates/core_arch/src/x86/test.rs
+++ b/crates/core_arch/src/x86/test.rs
@@ -78,38 +78,45 @@ pub(crate) const fn assert_eq_m512h(a: __m512h, b: __m512h) {
 }
 
 #[target_feature(enable = "sse2")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m128d(a: __m128d, idx: usize) -> f64 {
-    a.as_f64x2().extract(idx)
+    a.as_f64x2().extract_dyn(idx)
 }
 
 #[target_feature(enable = "sse")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m128(a: __m128, idx: usize) -> f32 {
-    a.as_f32x4().extract(idx)
+    a.as_f32x4().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m256d(a: __m256d, idx: usize) -> f64 {
-    a.as_f64x4().extract(idx)
+    a.as_f64x4().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m256(a: __m256, idx: usize) -> f32 {
-    a.as_f32x8().extract(idx)
+    a.as_f32x8().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx512f")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m512(a: __m512, idx: usize) -> f32 {
-    a.as_f32x16().extract(idx)
+    a.as_f32x16().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx512f")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m512d(a: __m512d, idx: usize) -> f64 {
-    a.as_f64x8().extract(idx)
+    a.as_f64x8().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx512f")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m512i(a: __m512i, idx: usize) -> i64 {
-    a.as_i64x8().extract(idx)
+    a.as_i64x8().extract_dyn(idx)
 }
 
 // not actually an intrinsic but useful in various tests as we ported from

From 4529b31d6478ff591390e97657abec0781024689 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 17 Jan 2026 17:01:14 +0100
Subject: [PATCH 100/326] s390x: add `nnp-assist` intrinsics

Because `qemu` does not support these (yet), I haven't added any runtime tests
---
 crates/core_arch/src/s390x/vector.rs | 74 ++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 97bfa32f17..e1f841030c 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -281,6 +281,12 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vfenezbs"] fn vfenezbs(a: i8x16, b: i8x16) -> PackedTuple<i8x16, i32>;
     #[link_name = "llvm.s390.vfenezhs"] fn vfenezhs(a: i16x8, b: i16x8) -> PackedTuple<i16x8, i32>;
     #[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
+
+    #[link_name = "llvm.s390.vclfnhs"] fn vclfnhs(a: vector_signed_short, immarg: i32) -> vector_float;
+    #[link_name = "llvm.s390.vclfnls"] fn vclfnls(a: vector_signed_short, immarg: i32) -> vector_float;
+    #[link_name = "llvm.s390.vcfn"] fn vcfn(a: vector_signed_short, immarg: i32) -> vector_signed_short;
+    #[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short;
+    #[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short;
 }
 
 #[repr(simd)]
@@ -5911,6 +5917,74 @@ pub unsafe fn vec_promote<T: sealed::VectorPromote>(a: T::ElementType, b: i32) -
     T::vec_promote(a, b)
 }
 
+/// Converts the left-most half of `a` to a vector of single-precision numbers.
+/// The format of the source vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vclfnh, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_extend_to_fp32_hi<const B: i32>(a: vector_signed_short) -> vector_float {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vclfnhs(a, B)
+}
+
+/// Converts the right-most half of `a` to a vector of single-precision numbers.
+/// The format of the source vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vclfnl, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_extend_to_fp32_lo<const B: i32>(a: vector_signed_short) -> vector_float {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vclfnls(a, B)
+}
+
+/// Converts the elements of vector `a` to the 16-bit IEEE floating point format.
+/// The format of the source vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vcfn, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_convert_to_fp16<const B: i32>(a: vector_signed_short) -> vector_signed_short {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vcfn(a, B)
+}
+
+/// Converts the elements of vector `a` to an internal floating point format.
+/// The format of the target vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vcnf, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_convert_from_fp16<const B: i32>(a: vector_signed_short) -> vector_signed_short {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vcnf(a, B)
+}
+
+/// Converts the elements of single-precision vectors `a` and `b` to an internal floating point
+/// format with 16-bit sized elements. The format of the target vector elements is specified by `C`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+#[cfg_attr(test, assert_instr(vcrnf, C = 0))]
+pub unsafe fn vec_round_from_fp32<const C: i32>(
+    a: vector_float,
+    b: vector_float,
+) -> vector_signed_short {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(C, 4);
+
+    vcrnfs(a, b, C)
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;

From 95d7a3776e594a733cb4900b197faf534486a377 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Sun, 16 Nov 2025 20:21:42 +0000
Subject: [PATCH 101/326] Add ARMv6 bare-metal targets

Three targets, covering A32 and T32 instructions, and soft-float and
hard-float ABIs. Hard-float not available in Thumb mode. Atomics
in Thumb mode require __sync* functions from compiler-builtins.
---
 crates/core_arch/src/arm_shared/hints.rs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/crates/core_arch/src/arm_shared/hints.rs b/crates/core_arch/src/arm_shared/hints.rs
index 54fd78270a..dade0d99e5 100644
--- a/crates/core_arch/src/arm_shared/hints.rs
+++ b/crates/core_arch/src/arm_shared/hints.rs
@@ -83,8 +83,12 @@ pub unsafe fn __sevl() {
 /// improve overall system performance.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
+// On ARMv6 in Thumb mode, T2 is required.
 #[cfg(any(
-    target_feature = "v6",
+    all(target_feature = "v6k", not(target_feature = "thumb-mode")),
+    target_feature = "v6t2",
+    all(target_feature = "v6", target_feature = "mclass"),
+    target_feature = "v7",
     target_arch = "aarch64",
     target_arch = "arm64ec",
     doc

From 186c7ece53d874b9685103bd8f66a8c9733672b7 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Fri, 19 Dec 2025 11:02:19 +0000
Subject: [PATCH 102/326] Revised yield hints

Turns out v7 targets always have v6t2 set, so that line was redundant. Also add a link to the Arm Armv7 A.R.M.
---
 crates/core_arch/src/arm_shared/hints.rs | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/hints.rs b/crates/core_arch/src/arm_shared/hints.rs
index dade0d99e5..8a25cc1163 100644
--- a/crates/core_arch/src/arm_shared/hints.rs
+++ b/crates/core_arch/src/arm_shared/hints.rs
@@ -83,12 +83,11 @@ pub unsafe fn __sevl() {
 /// improve overall system performance.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-// On ARMv6 in Thumb mode, T2 is required.
+// On ARMv6 in Thumb mode, T2 is required (see Arm DDI0406C Section A8.8.427)
 #[cfg(any(
     all(target_feature = "v6k", not(target_feature = "thumb-mode")),
     target_feature = "v6t2",
     all(target_feature = "v6", target_feature = "mclass"),
-    target_feature = "v7",
     target_arch = "aarch64",
     target_arch = "arm64ec",
     doc

From a10002d18941ef5d1bb4dd2cd724f28890735e37 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 26 Jan 2026 04:32:16 +0000
Subject: [PATCH 103/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to 873d4682c7d285540b8f28bfe637006cef8918a6.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index df8693cd1c..ccc0b55d4d 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-48622726c4a91c87bf6cd4dbe1000c95df59906e
+873d4682c7d285540b8f28bfe637006cef8918a6

From a95c0714602e7316a32b3cea317199d7a27fb1e4 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 26 Jan 2026 10:38:04 +0100
Subject: [PATCH 104/326] use `simd_splat`

---
 crates/core_arch/src/macros.rs          | 11 ++---------
 crates/core_arch/src/powerpc/altivec.rs |  6 +++---
 crates/core_arch/src/simd.rs            | 16 ++++------------
 3 files changed, 9 insertions(+), 24 deletions(-)

diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 849297b1fc..353829633f 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -90,17 +90,10 @@ macro_rules! types {
         pub struct $name($v [$elem_type; $len]);
 
         impl $name {
-            /// Using `my_simd([x; N])` seemingly fails tests,
-            /// so use this internal helper for it instead.
+            /// Put the same value in every lane.
             #[inline(always)]
             $v fn splat(value: $elem_type) -> $name {
-                #[derive(Copy, Clone)]
-                #[repr(simd)]
-                struct JustOne([$elem_type; 1]);
-                let one = JustOne([value]);
-                // SAFETY: 0 is always in-bounds because we're shuffling
-                // a simd type with exactly one element.
-                unsafe { simd_shuffle!(one, one, [0; $len]) }
+                unsafe { $crate::intrinsics::simd::simd_splat(value) }
             }
 
             /// Returns an array reference containing the entire SIMD vector.
diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index b9a25a9d85..fb1a9d8ed9 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -1457,7 +1457,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vspltb, IMM4 = 15))]
     unsafe fn vspltb<const IMM4: u32>(a: vector_signed_char) -> vector_signed_char {
         static_assert_uimm_bits!(IMM4, 4);
-        simd_shuffle(a, a, const { u32x16::from_array([IMM4; 16]) })
+        simd_shuffle(a, a, const { u32x16::splat(IMM4) })
     }
 
     #[inline]
@@ -1465,7 +1465,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vsplth, IMM3 = 7))]
     unsafe fn vsplth<const IMM3: u32>(a: vector_signed_short) -> vector_signed_short {
         static_assert_uimm_bits!(IMM3, 3);
-        simd_shuffle(a, a, const { u32x8::from_array([IMM3; 8]) })
+        simd_shuffle(a, a, const { u32x8::splat(IMM3) })
     }
 
     #[inline]
@@ -1474,7 +1474,7 @@ mod sealed {
     #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxspltw, IMM2 = 3))]
     unsafe fn vspltw<const IMM2: u32>(a: vector_signed_int) -> vector_signed_int {
         static_assert_uimm_bits!(IMM2, 2);
-        simd_shuffle(a, a, const { u32x4::from_array([IMM2; 4]) })
+        simd_shuffle(a, a, const { u32x4::splat(IMM2) })
     }
 
     #[unstable(feature = "stdarch_powerpc", issue = "111145")]
diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index b670092f5b..313c474792 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -50,14 +50,10 @@ impl<T: SimdElement, const N: usize> Simd<T, N> {
         Self(elements)
     }
 
-    // FIXME: Workaround rust@60637
-    #[inline(always)]
+    #[inline]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
     pub(crate) const fn splat(value: T) -> Self {
-        let one = Simd([value]);
-        // SAFETY: 0 is always in-bounds because we're shuffling
-        // a simd type with exactly one element.
-        unsafe { simd_shuffle!(one, one, [0; N]) }
+        unsafe { crate::intrinsics::simd::simd_splat(value) }
     }
 
     /// Extract the element at position `index`. Note that `index` is not a constant so this
@@ -182,14 +178,10 @@ impl<T: SimdElement, const N: usize> SimdM<T, N> {
         [zeros, ones][x as usize]
     }
 
-    // FIXME: Workaround rust@60637
-    #[inline(always)]
+    #[inline]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
     pub(crate) const fn splat(value: bool) -> Self {
-        let one = SimdM([Self::bool_to_internal(value)]);
-        // SAFETY: 0 is always in-bounds because we're shuffling
-        // a simd type with exactly one element.
-        unsafe { simd_shuffle!(one, one, [0; N]) }
+        unsafe { crate::intrinsics::simd::simd_splat(value) }
     }
 
     #[inline]

From 93f1c45b7be893343139a40123043a6d59775e56 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 26 Jan 2026 20:42:22 +0100
Subject: [PATCH 105/326] use `simd_splat` for the `set1` functions

---
 crates/core_arch/src/x86/avx.rs  | 18 ++++++------------
 crates/core_arch/src/x86/sse.rs  |  2 +-
 crates/core_arch/src/x86/sse2.rs |  8 ++++----
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index e0e01ae6d0..c8cddad2ef 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -2746,7 +2746,7 @@ pub const fn _mm256_setr_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_pd(a: f64) -> __m256d {
-    _mm256_setr_pd(a, a, a, a)
+    f64x4::splat(a).as_m256d()
 }
 
 /// Broadcasts single-precision (32-bit) floating-point value `a` to all
@@ -2759,7 +2759,7 @@ pub const fn _mm256_set1_pd(a: f64) -> __m256d {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_ps(a: f32) -> __m256 {
-    _mm256_setr_ps(a, a, a, a, a, a, a, a)
+    f32x8::splat(a).as_m256()
 }
 
 /// Broadcasts 8-bit integer `a` to all elements of returned vector.
@@ -2772,13 +2772,7 @@ pub const fn _mm256_set1_ps(a: f32) -> __m256 {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi8(a: i8) -> __m256i {
-    #[rustfmt::skip]
-    _mm256_setr_epi8(
-        a, a, a, a, a, a, a, a,
-        a, a, a, a, a, a, a, a,
-        a, a, a, a, a, a, a, a,
-        a, a, a, a, a, a, a, a,
-    )
+    i8x32::splat(a).as_m256i()
 }
 
 /// Broadcasts 16-bit integer `a` to all elements of returned vector.
@@ -2793,7 +2787,7 @@ pub const fn _mm256_set1_epi8(a: i8) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi16(a: i16) -> __m256i {
-    _mm256_setr_epi16(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
+    i16x16::splat(a).as_m256i()
 }
 
 /// Broadcasts 32-bit integer `a` to all elements of returned vector.
@@ -2806,7 +2800,7 @@ pub const fn _mm256_set1_epi16(a: i16) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi32(a: i32) -> __m256i {
-    _mm256_setr_epi32(a, a, a, a, a, a, a, a)
+    i32x8::splat(a).as_m256i()
 }
 
 /// Broadcasts 64-bit integer `a` to all elements of returned vector.
@@ -2821,7 +2815,7 @@ pub const fn _mm256_set1_epi32(a: i32) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi64x(a: i64) -> __m256i {
-    _mm256_setr_epi64x(a, a, a, a)
+    i64x4::splat(a).as_m256i()
 }
 
 /// Cast vector of type __m256d to type __m256.
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index f167e8381d..38b309c1cb 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -932,7 +932,7 @@ pub const fn _mm_set_ss(a: f32) -> __m128 {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_ps(a: f32) -> __m128 {
-    __m128([a, a, a, a])
+    f32x4::splat(a).as_m128()
 }
 
 /// Alias for [`_mm_set1_ps`](fn._mm_set1_ps.html)
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index fc010e8467..d712c4f4c5 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -1176,7 +1176,7 @@ pub const fn _mm_set_epi8(
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi64x(a: i64) -> __m128i {
-    _mm_set_epi64x(a, a)
+    i64x2::splat(a).as_m128i()
 }
 
 /// Broadcasts 32-bit integer `a` to all elements.
@@ -1188,7 +1188,7 @@ pub const fn _mm_set1_epi64x(a: i64) -> __m128i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi32(a: i32) -> __m128i {
-    _mm_set_epi32(a, a, a, a)
+    i32x4::splat(a).as_m128i()
 }
 
 /// Broadcasts 16-bit integer `a` to all elements.
@@ -1200,7 +1200,7 @@ pub const fn _mm_set1_epi32(a: i32) -> __m128i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi16(a: i16) -> __m128i {
-    _mm_set_epi16(a, a, a, a, a, a, a, a)
+    i16x8::splat(a).as_m128i()
 }
 
 /// Broadcasts 8-bit integer `a` to all elements.
@@ -1212,7 +1212,7 @@ pub const fn _mm_set1_epi16(a: i16) -> __m128i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi8(a: i8) -> __m128i {
-    _mm_set_epi8(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
+    i8x16::splat(a).as_m128i()
 }
 
 /// Sets packed 32-bit integers with the supplied values in reverse order.

From 4b196cdb93e2304d97e8fcd9c0d03078bf3773c4 Mon Sep 17 00:00:00 2001
From: Reuben Cruise <reuben.cruise@arm.com>
Date: Wed, 14 Jan 2026 16:46:45 +0000
Subject: [PATCH 106/326] Adds some arm intrinsics to bring more up-to-date
 with acle

- Adds vluti2 intrinsics
- Adds famin/famax intrinsics
- Adds vstl1(q) intrinsics
- Adds vldap1(q) intrinsics
	- Excludes vldap1_lane_f64 as in testing it fails assert_intr. There seems to be some bad IR gen from rust.
- Adds vscale(q) intrinsics
- Adds new intrinsics to arm_intrinsics.json
	- Had to be done manually as intrinsics are not yet on developer.arm.com
---
 .../core_arch/src/aarch64/neon/generated.rs   |  669 +++++++-
 crates/intrinsic-test/missing_aarch64.txt     |   52 +-
 crates/intrinsic-test/missing_aarch64_be.txt  |   51 +-
 .../spec/neon/aarch64.spec.yml                |  235 ++-
 intrinsics_data/arm_intrinsics.json           | 1385 ++++++++++++++++-
 5 files changed, 2258 insertions(+), 134 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index b042bd0c3c..b763d64ca3 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -733,10 +733,42 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
     unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famax))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famax.v4f16"
+        )]
+        fn _vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
+    }
+    unsafe { _vamax_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famax))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famax.v8f16"
+        )]
+        fn _vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    }
+    unsafe { _vamaxq_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -752,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -768,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -781,10 +813,42 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { _vamaxq_f64(a, b) }
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famin))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famin.v4f16"
+        )]
+        fn _vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
+    }
+    unsafe { _vamin_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famin))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famin.v8f16"
+        )]
+        fn _vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    }
+    unsafe { _vaminq_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -800,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -816,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -12847,6 +12911,237 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
     ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
     ret_val
 }
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
+    static_assert!(LANE == 0);
+    let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
+    simd_insert!(
+        src,
+        LANE as u32,
+        atomic_src.load(crate::sync::atomic::Ordering::Acquire)
+    )
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
+    simd_insert!(
+        src,
+        LANE as u32,
+        atomic_src.load(crate::sync::atomic::Ordering::Acquire)
+    )
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_t) -> float64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
+    static_assert!(LANE == 0);
+    transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
+    static_assert!(LANE == 0);
+    transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2q_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2q_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
+}
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
@@ -12928,108 +13223,214 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
     _vluti2q_lane_s16(a, b, LANE)
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_u8<const LANE: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_f16<const INDEX: i32>(a: float16x4_t, b: uint8x16_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2q_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_f16<const INDEX: i32>(a: float16x8_t, b: uint8x16_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x16_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_laneq_s8::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2q_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_laneq_s8::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_p8<const LANE: i32>(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x16_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2q_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_p16<const LANE: i32>(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x16_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_laneq_s8::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_p16<const LANE: i32>(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2q_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_laneq_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> int8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v8i8"
+        )]
+        fn _vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t, n: i32) -> int8x16_t;
+    }
+    _vluti2_laneq_s8(a, b, INDEX)
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v16i8"
+        )]
+        fn _vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t;
+    }
+    _vluti2q_laneq_s8(a, b, INDEX)
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) -> int16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v4i16"
+        )]
+        fn _vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t, n: i32) -> int16x8_t;
+    }
+    _vluti2_laneq_s16(a, b, INDEX)
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_laneq_s16<const INDEX: i32>(a: int16x8_t, b: uint8x16_t) -> int16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v8i16"
+        )]
+        fn _vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t, n: i32) -> int16x8_t;
+    }
+    _vluti2q_laneq_s16(a, b, INDEX)
 }
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
@@ -24113,6 +24514,86 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
     let x: uint32x2_t = vrsubhn_u64(b, c);
     unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
 }
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v4f16"
+        )]
+        fn _vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t;
+    }
+    unsafe { _vscale_f16(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v8f16"
+        )]
+        fn _vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t;
+    }
+    unsafe { _vscaleq_f16(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v2f32"
+        )]
+        fn _vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t;
+    }
+    unsafe { _vscale_f32(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v4f32"
+        )]
+        fn _vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t;
+    }
+    unsafe { _vscaleq_f32(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v2f64"
+        )]
+        fn _vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t;
+    }
+    unsafe { _vscaleq_f64(vn, vm) }
+}
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"]
 #[inline(always)]
@@ -26696,6 +27177,102 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
     vst4q_s64(transmute(a), transmute(b))
 }
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
+    static_assert!(LANE == 0);
+    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
+    static_assert!(LANE == 0);
+    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
+    static_assert!(LANE == 0);
+    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
+    static_assert!(LANE == 0);
+    let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
+    unsafe {
+        let lane: i64 = simd_extract!(val, LANE as u32);
+        (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
+    }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
+    unsafe {
+        let lane: i64 = simd_extract!(val, LANE as u32);
+        (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
+    }
+}
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
 #[inline(always)]
diff --git a/crates/intrinsic-test/missing_aarch64.txt b/crates/intrinsic-test/missing_aarch64.txt
index 814756cefa..3c1ac59e91 100644
--- a/crates/intrinsic-test/missing_aarch64.txt
+++ b/crates/intrinsic-test/missing_aarch64.txt
@@ -1,3 +1,43 @@
+# Not supported by qemu (will throw illegal instruction)
+vamax_f16
+vamaxq_f16
+vamin_f16
+vaminq_f16
+vscale_f16
+vscale_f32
+vscaleq_f16
+vscaleq_f32
+vscaleq_f64
+vluti2_lane_p16
+vluti2_lane_p8
+vluti2_lane_s16
+vluti2_lane_s8
+vluti2_lane_u16
+vluti2_lane_u8
+vluti2q_lane_p16
+vluti2q_lane_p8
+vluti2q_lane_s16
+vluti2q_lane_s8
+vluti2q_lane_u16
+vluti2_laneq_f16
+vluti2_lane_f16
+vluti2_laneq_f16
+vluti2_laneq_p16
+vluti2_laneq_p8
+vluti2_laneq_s16
+vluti2_laneq_s8
+vluti2_laneq_u16
+vluti2_laneq_u8
+vluti2q_lane_f16
+vluti2q_laneq_f16
+vluti2q_laneq_p16
+vluti2q_laneq_p8
+vluti2q_laneq_s16
+vluti2q_laneq_s8
+vluti2q_laneq_u16
+vluti2q_laneq_u8
+vluti2q_lane_u8
+
 # Not implemented in stdarch yet
 vbfdot_f32
 vbfdot_lane_f32
@@ -30,18 +70,6 @@ vrnd32x_f64
 vrnd32z_f64
 vrnd64x_f64
 vrnd64z_f64
-vluti2_lane_p16
-vluti2_lane_p8
-vluti2_lane_s16
-vluti2_lane_s8
-vluti2_lane_u16
-vluti2_lane_u8
-vluti2q_lane_p16
-vluti2q_lane_p8
-vluti2q_lane_s16
-vluti2q_lane_s8
-vluti2q_lane_u16
-vluti2q_lane_u8
 vluti4q_lane_f16_x2
 vluti4q_lane_p16_x2
 vluti4q_lane_p8
diff --git a/crates/intrinsic-test/missing_aarch64_be.txt b/crates/intrinsic-test/missing_aarch64_be.txt
index 1fa8fb7f16..f3c4ffa3d0 100644
--- a/crates/intrinsic-test/missing_aarch64_be.txt
+++ b/crates/intrinsic-test/missing_aarch64_be.txt
@@ -38,6 +38,45 @@ vusdotq_lane_s32
 vusdotq_laneq_s32
 
 # Below are in common to missing_aarch64.txt
+# Not supported by qemu (will throw illegal instruction)
+vamax_f16
+vamaxq_f16
+vamin_f16
+vaminq_f16
+vscale_f16
+vscale_f32
+vscaleq_f16
+vscaleq_f32
+vscaleq_f64
+vluti2_lane_p16
+vluti2_lane_p8
+vluti2_lane_s16
+vluti2_lane_s8
+vluti2_lane_u16
+vluti2_lane_u8
+vluti2q_lane_p16
+vluti2q_lane_p8
+vluti2q_lane_s16
+vluti2q_lane_s8
+vluti2q_lane_u16
+vluti2_laneq_f16
+vluti2_lane_f16
+vluti2_laneq_f16
+vluti2_laneq_p16
+vluti2_laneq_p8
+vluti2_laneq_s16
+vluti2_laneq_s8
+vluti2_laneq_u16
+vluti2_laneq_u8
+vluti2q_lane_f16
+vluti2q_laneq_f16
+vluti2q_laneq_p16
+vluti2q_laneq_p8
+vluti2q_laneq_s16
+vluti2q_laneq_s8
+vluti2q_laneq_u16
+vluti2q_laneq_u8
+vluti2q_lane_u8
 
 # Not implemented in stdarch yet
 vbfdot_f32
@@ -71,18 +110,6 @@ vrnd32x_f64
 vrnd32z_f64
 vrnd64x_f64
 vrnd64z_f64
-vluti2_lane_p16
-vluti2_lane_p8
-vluti2_lane_s16
-vluti2_lane_s8
-vluti2_lane_u16
-vluti2_lane_u8
-vluti2q_lane_p16
-vluti2q_lane_p8
-vluti2q_lane_s16
-vluti2q_lane_s8
-vluti2q_lane_u16
-vluti2q_lane_u8
 vluti4q_lane_f16_x2
 vluti4q_lane_p16_x2
 vluti4q_lane_p8
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a951343e01..10085422e8 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -66,6 +66,14 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut
 aarch64-stable-jscvt: &aarch64-stable-jscvt
   FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']]
 
+# #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3
+  FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']]
+
+# #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+neon-unstable-fp8: &neon-unstable-fp8
+  FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']]
+
 # #[cfg(target_endian = "little")]
 little-endian: &little-endian
   FnCall: [cfg, ['target_endian = "little"']]
@@ -4398,6 +4406,116 @@ intrinsics:
                 - - FnCall: [transmute, [a]]
                   - FnCall: [transmute, [b]]
 
+  - name: "vldap1{neon_type[1].lane_nox}"
+    doc: "Load-acquire RCpc one single-element structure to one lane of one register"
+    arguments: ["ptr: {type[0]}", "src: {type[1]}"]
+    static_defs: ["const LANE: i32"]
+    return_type: "{type[1]}"
+    safety:
+      unsafe: [neon]
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0']
+      - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - Let:
+          - "atomic_src"
+          - FnCall: ["crate::sync::atomic::AtomicI64::from_ptr", ['ptr as *mut i64']]
+      - Identifier: [';', Symbol]
+      - FnCall:
+        - simd_insert!
+        - - src
+          - "LANE as u32"
+          - MethodCall:
+             - "atomic_src"
+             - load
+             - ["crate::sync::atomic::Ordering::Acquire"]
+
+  - name: "vldap1{neon_type[1].lane_nox}"
+    doc: "Load-acquire RCpc one single-element structure to one lane of one register"
+    arguments: ["ptr: {type[0]}","src: {type[1]}"]
+    static_defs: ["const LANE: i32"]
+    return_type: "{type[1]}"
+    safety:
+      unsafe: [neon]
+    attr:
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0','']
+      #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust
+      - ['*const p64', poly64x1_t,'static_assert!', 'LANE == 0','']
+      - ['*const u64', uint64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*const f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*const p64', poly64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - FnCall:
+        - transmute
+        - - FnCall:
+            - 'vldap1{type[4]}_lane_s64::<LANE>'
+            - - "ptr as *mut i64"
+              - FnCall: [transmute,[src]]
+
+  - name: "vstl1{neon_type[1].lane_nox}"
+    doc: "Store-Release a single-element structure from one lane of one register."
+    arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0']
+      - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - Let:
+          - "atomic_dst"
+          - "ptr as *mut crate::sync::atomic::AtomicI64"
+      - Identifier: [';', Symbol]
+      - Let:
+        - "lane"
+        - i64
+        - FnCall: [simd_extract!, [val, 'LANE as u32']]
+      - MethodCall:
+        - "(*atomic_dst)"
+        - store
+        - [FnCall: [transmute, [lane]],"crate::sync::atomic::Ordering::Release"]
+
+  - name: "vstl1{neon_type[1].lane_nox}"
+    doc: "Store-Release a single-element structure from one lane of one register."
+    arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0','']
+      - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0','']
+      - ['*mut p64', poly64x1_t, 'static_assert!', 'LANE == 0','']
+      - ['*mut u64', uint64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*mut f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*mut p64', poly64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - FnCall:
+        - "vstl1{type[4]}_lane_s64::<LANE>"
+        - - "ptr as *mut i64"
+          - FnCall: [transmute, [val]]
+
   - name: "vst1{neon_type[1].lane_nox}"
     doc: "Store multiple single-element structures from one, two, three, or four registers"
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
@@ -13966,10 +14084,12 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famax]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
+      - float16x4_t
+      - float16x8_t
       - float32x2_t
       - float32x4_t
       - float64x2_t
@@ -13986,10 +14106,12 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famin]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
+      - float16x4_t
+      - float16x8_t
       - float32x2_t
       - float32x4_t
       - float64x2_t
@@ -14030,36 +14152,101 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall: ['_vluti2{neon_type[0].lane_nox}', [a, b, LANE]]
 
+  - name: "vluti2{neon_type[0].laneq_nox}"
+    doc: "Lookup table read with 2-bit indices"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[2]}"
+    attr:
+      - FnCall: [target_feature, ['enable = {type[4]}']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]]
+      - *neon-unstable-feat-lut
+      - FnCall: [rustc_legacy_const_generics, ['2']]
+    static_defs: ["const INDEX: i32"]
+    safety:
+      unsafe: [neon]
+    types:
+      - [int8x8_t,   uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"']
+      - [int8x16_t,  uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"']
+      - [int16x4_t,  uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"']
+      - [int16x8_t,  uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"']
+    compose:
+      - FnCall: ['static_assert!', ['{type[3]}']]
+      - LLVMLink:
+          name: "vluti2{neon_type[0].laneq_nox}"
+          arguments:
+            - 'a: {neon_type[0]}'
+            - 'b: {neon_type[1]}'
+            - 'n: i32'
+          links:
+            - link: "llvm.aarch64.neon.vluti2.laneq.{neon_type[2]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
+      - FnCall: ['_vluti2{neon_type[0].laneq_nox}', [a, b, INDEX]]
+
   - name: "vluti2{neon_type[0].lane_nox}"
     doc: "Lookup table read with 2-bit indices"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,lut"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]]
       - *neon-unstable-feat-lut
       - FnCall: [rustc_legacy_const_generics, ['2']]
-    static_defs: ["const LANE: i32"]
+    static_defs: ["const INDEX: i32"]
     safety:
       unsafe: [neon]
     types:
-      - [uint8x8_t,  uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t']
-      - [uint8x16_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t']
-      - [poly8x8_t,  uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t']
-      - [poly8x16_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t']
-      - [uint16x4_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t']
-      - [uint16x8_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t']
-      - [poly16x4_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t']
-      - [poly16x8_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t']
+      - [uint8x8_t,  uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t']
+      - [uint8x16_t, uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t']
+      - [poly8x8_t,  uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t']
+      - [poly8x16_t, uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t']
+      - [uint16x4_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t']
+      - [uint16x8_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t']
+      - [poly16x4_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t']
+      - [poly16x8_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t']
+      - [float16x4_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t']
+      - [float16x8_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t']
     compose:
       - FnCall: ['static_assert!', ['{type[3]}']]
       - FnCall:
           - transmute
           - - FnCall:
-                - 'vluti2{neon_type[4].lane_nox}::<LANE>'
+                - 'vluti2{neon_type[4].lane_nox}::<INDEX>'
                 - - FnCall: [transmute, [a]]
                   - b
 
+  - name: "vluti2{neon_type[0].laneq_nox}"
+    doc: "Lookup table read with 2-bit indices"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[2]}"
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,lut"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]]
+      - *neon-unstable-feat-lut
+      - FnCall: [rustc_legacy_const_generics, ['2']]
+    static_defs: ["const INDEX: i32"]
+    safety:
+      unsafe: [neon]
+    types:
+      - [uint8x8_t,  uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t']
+      - [uint8x16_t, uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t']
+      - [poly8x8_t,  uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t']
+      - [poly8x16_t, uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t']
+      - [uint16x4_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t']
+      - [uint16x8_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t']
+      - [poly16x4_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t']
+      - [poly16x8_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t']
+      - [float16x4_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t']
+      - [float16x8_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t']
+    compose:
+      - FnCall: ['static_assert!', ['{type[3]}']]
+      - FnCall:
+          - transmute
+          - - FnCall:
+                - 'vluti2{neon_type[4].laneq_nox}::<INDEX>'
+                - - FnCall: [transmute, [a]]
+                  - b
+
+
   - name: "vluti4{neon_type[0].lane_nox}"
     doc: "Lookup table read with 4-bit indices"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
@@ -14268,6 +14455,28 @@ intrinsics:
                 - - FnCall: [transmute, [a]]
                   - b
 
+  - name: "vscale{neon_type[0].no}"
+    doc: "Multi-vector floating-point adjust exponent"
+    arguments: ["vn: {type[0]}", "vm: {type[1]}"]
+    return_type: "{type[0]}"
+    attr:
+      - *neon-unstable-fp8
+      - FnCall: [target_feature, ['enable = "neon,fp8"']]
+    assert_instr: [fscale]
+    safety: safe
+    types:
+      - [float16x4_t, int16x4_t]
+      - [float16x8_t, int16x8_t]
+      - [float32x2_t, int32x2_t]
+      - [float32x4_t, int32x4_t]
+      - [float64x2_t, int64x2_t]
+    compose:
+      - LLVMLink:
+          name: "vscale{neon_type[0].no}"
+          links:
+            - link: "llvm.aarch64.neon.fp8.fscale.{neon_type[0]}"
+              arch: aarch64,arm64ec
+
   - name: "__jcvt"
     doc: "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"
     arguments: ["a: {type}"]
diff --git a/intrinsics_data/arm_intrinsics.json b/intrinsics_data/arm_intrinsics.json
index 19c655cd6d..bce85d19a1 100644
--- a/intrinsics_data/arm_intrinsics.json
+++ b/intrinsics_data/arm_intrinsics.json
@@ -223,6 +223,141 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscale_f16",
+    "arguments": [
+      "float16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscaleq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscale_f32",
+    "arguments": [
+      "float32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscaleq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscaleq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vaba_s16",
@@ -34733,6 +34868,230 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1_lane_u64",
+    "arguments": [
+      "uint64_t const * ptr",
+      "uint64x1_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1_lane_s64",
+    "arguments": [
+      "int64_t const * ptr",
+      "int64x1_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_u64",
+    "arguments": [
+      "uint64_t const * ptr",
+      "uint64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_s64",
+    "arguments": [
+      "int64_t const * ptr",
+      "int64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1_lane_p64",
+    "arguments": [
+      "poly64_t const * ptr",
+      "poly64x1_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_p64",
+    "arguments": [
+      "poly64_t const * ptr",
+      "poly64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_f64",
+    "arguments": [
+      "float64_t const * ptr",
+      "float64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vld1_dup_f16",
@@ -109193,6 +109552,262 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_f64",
+    "arguments": [
+      "float64_t * ptr",
+      "float64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_f64",
+    "arguments": [
+      "float64_t * ptr",
+      "float64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_p64",
+    "arguments": [
+      "poly64_t * ptr",
+      "poly64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_p64",
+    "arguments": [
+      "poly64_t * ptr",
+      "poly64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_u64",
+    "arguments": [
+      "uint64_t * ptr",
+      "uint64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_u64",
+    "arguments": [
+      "uint64_t * ptr",
+      "uint64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_s64",
+    "arguments": [
+      "int64_t * ptr",
+      "int64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_s64",
+    "arguments": [
+      "int64_t * ptr",
+      "int64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vsub_f16",
@@ -118682,6 +119297,60 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamin_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaminq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vamin_f32",
@@ -118763,6 +119432,60 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamax_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamaxq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vamax_f32",
@@ -118844,6 +119567,531 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_f16",
+    "arguments": [
+      "float16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_s16",
+    "arguments": [
+      "int16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_f16",
+    "arguments": [
+      "float16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_s16",
+    "arguments": [
+      "int16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_f16",
+    "arguments": [
+      "float16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_s16",
+    "arguments": [
+      "int16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_p16",
+    "arguments": [
+      "poly16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vluti2_lane_u8",
@@ -118862,7 +120110,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -118897,7 +120145,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -118932,7 +120180,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -118967,7 +120215,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -119002,7 +120250,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -119037,7 +120285,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -119056,28 +120304,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_u16",
+    "name": "vluti2_laneq_u8",
     "arguments": [
-      "uint16x4_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint8x8_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119091,28 +120339,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_u16",
+    "name": "vluti2q_laneq_u8",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119126,28 +120374,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_s16",
+    "name": "vluti2_laneq_s8",
     "arguments": [
-      "int16x4_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int8x8_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119161,28 +120409,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_s16",
+    "name": "vluti2q_laneq_s8",
     "arguments": [
-      "int16x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int8x16_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119196,28 +120444,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_p16",
+    "name": "vluti2_laneq_p8",
     "arguments": [
-      "poly16x4_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "poly8x8_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119231,11 +120479,46 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_p16",
+    "name": "vluti2q_laneq_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_p16",
     "arguments": [
       "poly16x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
       "value": "poly16x8_t"
@@ -119247,9 +120530,9 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "r": {
         "register": "Vd.8H"

From 8291741b9385dd5dfa4a18086030a8a6593204d5 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Wed, 17 Dec 2025 09:41:31 +0000
Subject: [PATCH 107/326] Makes some A64 intrinsics available on A32

Moves the relevant defintions from the aarch64 yaml to the arm_shared.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 204 +++--------
 .../src/arm_shared/neon/generated.rs          | 332 ++++++++++++++++++
 .../spec/neon/aarch64.spec.yml                | 111 ------
 .../spec/neon/arm_shared.spec.yml             | 126 +++++++
 4 files changed, 498 insertions(+), 275 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index b763d64ca3..c4fd6a8cd9 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -734,7 +734,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -750,7 +750,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -814,7 +814,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -830,7 +830,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -9555,68 +9555,6 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 pub fn vdivh_f16(a: f16, b: f16) -> f16 {
     a / b
 }
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(sdot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(sdot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(udot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: uint32x4_t = vreinterpretq_u32_u8(c);
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, vreinterpret_u8_u32(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(udot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: uint32x4_t = vreinterpretq_u32_u8(c);
-    unsafe {
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
-    }
-}
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"]
 #[inline(always)]
@@ -12915,7 +12853,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12933,7 +12871,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12951,7 +12889,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -12964,7 +12902,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -12977,7 +12915,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -12990,7 +12928,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -13003,7 +12941,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -13016,7 +12954,7 @@ pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13029,7 +12967,7 @@ pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13042,7 +12980,7 @@ pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13055,7 +12993,7 @@ pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> ui
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13068,7 +13006,7 @@ pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13081,7 +13019,7 @@ pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13094,7 +13032,7 @@ pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13107,7 +13045,7 @@ pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> po
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13120,7 +13058,7 @@ pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13133,7 +13071,7 @@ pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13330,7 +13268,7 @@ pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13343,7 +13281,7 @@ pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13356,7 +13294,7 @@ pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13376,7 +13314,7 @@ pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13396,7 +13334,7 @@ pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13416,7 +13354,7 @@ pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -24516,7 +24454,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24532,7 +24470,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24548,7 +24486,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24564,7 +24502,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24580,7 +24518,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -27179,7 +27117,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27190,7 +27128,7 @@ pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27201,7 +27139,7 @@ pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27212,7 +27150,7 @@ pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27223,7 +27161,7 @@ pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27234,7 +27172,7 @@ pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27245,7 +27183,7 @@ pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27260,7 +27198,7 @@ pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27481,37 +27419,6 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
         simd_sub(a, simd_cast(c))
     }
 }
-#[doc = "Dot product index form with signed and unsigned integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(sudot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, transmute(c), b)
-    }
-}
-#[doc = "Dot product index form with signed and unsigned integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(sudot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, transmute(c), b)
-    }
-}
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
 #[inline(always)]
@@ -28851,37 +28758,6 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
     }
     unsafe { _vuqadds_s32(a, b) }
 }
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(usdot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
-}
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(usdot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
-}
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
 #[inline(always)]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 324ff73f62..ac3b649fbf 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -9816,6 +9816,200 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vdot_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vdotq_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: int8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vdot_u32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vdotq_u32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: uint8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    }
+}
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
 #[inline(always)]
@@ -73395,6 +73589,47 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
+#[doc = "Dot product index form with signed and unsigned integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
+#[inline(always)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sudot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vusdot_s32(a, transmute(c), b)
+    }
+}
+#[doc = "Dot product index form with signed and unsigned integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
+#[inline(always)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sudot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vusdotq_s32(a, transmute(c), b)
+    }
+}
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
 #[inline(always)]
@@ -75397,6 +75632,103 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vusdot_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vusdotq_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: uint8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    }
+}
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
 #[inline(always)]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 10085422e8..ec5bc8c954 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5199,56 +5199,6 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']]
 
-  - name: "vusdot{neon_type[0].laneq_nox}"
-    doc: "Dot product index form with unsigned and signed integers"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    attr:
-      - *neon-i8mm
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
-    static_defs: ["const LANE: i32"]
-    safety: safe
-    types:
-      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]','']
-      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let: [c, int32x4_t, {FnCall: ['vreinterpretq_s32_s8', [c]]}]
-      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
-
-  - name: "vsudot{neon_type[0].laneq_nox}"
-    doc: "Dot product index form with signed and unsigned integers"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    attr:
-      - *neon-i8mm
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
-    static_defs: ["const LANE: i32"]
-    safety: safe
-    types:
-      - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t]
-      - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t]
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
-      - Let:
-          - c
-          - uint32x4_t
-          - FnCall: [transmute, [c]]
-      - Let:
-          - c
-          - "{type[4]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: 
-          - "vusdot{neon_type[0].no}"
-          - - a
-            - FnCall: [transmute, [c]]
-            - b
-
   - name: "vmul{neon_type.no}"
     doc: Multiply
     arguments: ["a: {neon_type}", "b: {neon_type}"]
@@ -6670,7 +6620,6 @@ intrinsics:
       - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
-
   - name: "vcmla{neon_type[0].rot270_lane}"
     doc: Floating-point complex multiply accumulate
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
@@ -6692,66 +6641,6 @@ intrinsics:
       - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
-  - name: "vdot{neon_type[0].laneq_nox}"
-    doc: Dot product arithmetic (indexed)
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    static_defs: ["const LANE: i32"]
-    attr:
-      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
-    safety: safe
-    types:
-      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', '']
-      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let:
-          - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
-      - FnCall:
-          - "vdot{neon_type[0].no}"
-          - - a
-            - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
-
-  - name: "vdot{neon_type[0].laneq_nox}"
-    doc: Dot product arithmetic (indexed)
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    static_defs: ["const LANE: i32"]
-    attr:
-      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
-    safety: safe
-    types:
-      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]','']
-      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let:
-          - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
-      - FnCall:
-          - "vdot{neon_type[0].no}"
-          - - a
-            - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
-
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)
     arguments: ["a: {neon_type}", "b: {neon_type}"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index c7a333d7f7..2bd1bf2a53 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -7096,6 +7096,132 @@ intrinsics:
           - FnCall: [simd_cast, [b]]
       - FnCall: [simd_sub, [c, d]]
 
+  - name: "vusdot{neon_type[0].laneq_nox}"
+    doc: "Dot product index form with unsigned and signed integers"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
+    attr:
+      - *neon-v8
+      - *neon-i8mm
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot, 'LANE = 3']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    types:
+      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]','']
+      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
+      - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}]
+      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
+      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]]
+      #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] 
+
+  - name: "vsudot{neon_type[0].laneq_nox}"
+    doc: "Dot product index form with signed and unsigned integers"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    attr:
+      - *neon-v8
+      - *neon-i8mm
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    types:
+      - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t]
+      - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t]
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
+      - Let:
+          - c
+          - uint32x4_t
+          - FnCall: [transmute, [c]]
+      - Let:
+          - c
+          - "{type[4]}"
+          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+      - FnCall: 
+          - "vusdot{neon_type[0].no}"
+          - - a
+            - FnCall: [transmute, [c]]
+            - b
+
+  - name: "vdot{neon_type[0].laneq_nox}"
+    doc: Dot product arithmetic (indexed)
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    static_defs: ["const LANE: i32"]
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
+    attr:
+      - *neon-v8
+      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
+    safety: safe
+    types:
+      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', '']
+      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
+      - Let:
+          - c
+          - "{neon_type[3]}"
+          - FnCall: [transmute, [c]]
+          #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+      - Let:
+          - c
+          - "{neon_type[0]}"
+          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+      - FnCall:
+          - "vdot{neon_type[0].no}"
+          - - a
+            - b
+            - FnCall: [transmute, [c]]
+            #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+
+  - name: "vdot{neon_type[0].laneq_nox}"
+    doc: Dot product arithmetic (indexed)
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    static_defs: ["const LANE: i32"]
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
+    attr:
+      - *neon-v8
+      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
+    safety: safe
+    types:
+      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]','']
+      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
+      - Let:
+          - c
+          - "{neon_type[3]}"
+          - FnCall: [transmute, [c]]
+          #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+      - Let:
+          - c
+          - "{neon_type[0]}"
+          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+      - FnCall:
+          - "vdot{neon_type[0].no}"
+          - - a
+            - b
+            - FnCall: [transmute, [c]]
+            #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+
   - name: "vdot{neon_type[0].no}"
     doc: Dot product arithmetic (vector)
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]

From d39e66b1fbf460f7c85aaeeb76168c84afdf9560 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Wed, 14 Jan 2026 13:29:20 +0000
Subject: [PATCH 108/326] Disables `assert_instr` tests on windows msvc

The opcodes for these intructions are not recognised by the dissasembler on the windows msvc toolchain.
As such they are not translated to the relevant mneumonic and the `assert_instr` test fails.
Please see [failing test](https://github.com/rust-lang/stdarch/actions/runs/20992978794/job/60342796821?pr=1994#logs).
---
 .../core_arch/src/aarch64/neon/generated.rs   | 60 +++++++++----------
 .../spec/neon/aarch64.spec.yml                | 14 ++---
 2 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index c4fd6a8cd9..68676ebd2c 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -736,7 +736,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -752,7 +752,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -768,7 +768,7 @@ pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -784,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -800,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -816,7 +816,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -832,7 +832,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -848,7 +848,7 @@ pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -864,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -880,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -12855,7 +12855,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
@@ -12873,7 +12873,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
@@ -12892,7 +12892,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
@@ -12905,7 +12905,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
     static_assert!(LANE == 0);
@@ -12918,7 +12918,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
@@ -12931,7 +12931,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
     static_assert!(LANE == 0);
@@ -12944,7 +12944,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
     static_assert_uimm_bits!(LANE, 1);
@@ -24457,7 +24457,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24473,7 +24473,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24489,7 +24489,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24505,7 +24505,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24521,7 +24521,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -27119,7 +27119,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
@@ -27130,7 +27130,7 @@ pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
@@ -27141,7 +27141,7 @@ pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
@@ -27152,7 +27152,7 @@ pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
@@ -27163,7 +27163,7 @@ pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
@@ -27174,7 +27174,7 @@ pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
@@ -27185,7 +27185,7 @@ pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
@@ -27200,7 +27200,7 @@ pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index ec5bc8c954..a9bc377924 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -4415,7 +4415,7 @@ intrinsics:
       unsafe: [neon]
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
     types:
@@ -4446,7 +4446,7 @@ intrinsics:
     attr:
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
       - *neon-unstable-feat-lrcpc3
     types:
       - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0','']
@@ -4471,7 +4471,7 @@ intrinsics:
     safety: safe
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
     types:
@@ -4499,7 +4499,7 @@ intrinsics:
     safety: safe
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
     types:
@@ -13973,7 +13973,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famax]]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famax]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
@@ -13995,7 +13995,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famin]]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famin]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
@@ -14351,7 +14351,7 @@ intrinsics:
     attr:
       - *neon-unstable-fp8
       - FnCall: [target_feature, ['enable = "neon,fp8"']]
-    assert_instr: [fscale]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [fscale]]}]]
     safety: safe
     types:
       - [float16x4_t, int16x4_t]

From 468e47476b084f8e10db9b218693a866dfd6311b Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Wed, 14 Jan 2026 13:59:59 +0000
Subject: [PATCH 109/326] Ammends typo in generator & generated

---
 .../core_arch/src/aarch64/neon/generated.rs   |  484 ++---
 .../src/arm_shared/neon/generated.rs          | 1772 ++++++++---------
 crates/stdarch-gen-arm/src/intrinsic.rs       |    2 +-
 3 files changed, 1129 insertions(+), 1129 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 68676ebd2c..9507b71106 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11174,7 +11174,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11186,7 +11186,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11198,7 +11198,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11209,7 +11209,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11220,7 +11220,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11231,7 +11231,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11242,7 +11242,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11253,7 +11253,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11264,7 +11264,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11275,7 +11275,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11286,7 +11286,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11297,7 +11297,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11308,7 +11308,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11319,7 +11319,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11330,7 +11330,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11341,7 +11341,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11352,7 +11352,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11363,7 +11363,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11374,7 +11374,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11385,7 +11385,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11396,7 +11396,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11407,7 +11407,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11418,7 +11418,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11429,7 +11429,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11440,7 +11440,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11451,7 +11451,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11462,7 +11462,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11473,7 +11473,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11484,7 +11484,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11502,7 +11502,7 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11520,7 +11520,7 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11538,7 +11538,7 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11556,7 +11556,7 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11574,7 +11574,7 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11592,7 +11592,7 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11610,7 +11610,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11628,7 +11628,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11646,7 +11646,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11664,7 +11664,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11684,7 +11684,7 @@ pub unsafe fn vld2_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11704,7 +11704,7 @@ pub unsafe fn vld2_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11717,7 +11717,7 @@ pub unsafe fn vld2_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11730,7 +11730,7 @@ pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) ->
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -11742,7 +11742,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -11757,7 +11757,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -11769,7 +11769,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -11784,7 +11784,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11802,7 +11802,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11820,7 +11820,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11841,7 +11841,7 @@ pub unsafe fn vld2q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11861,7 +11861,7 @@ pub unsafe fn vld2q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x2_t) -> in
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11881,7 +11881,7 @@ pub unsafe fn vld2q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11894,7 +11894,7 @@ pub unsafe fn vld2q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11907,7 +11907,7 @@ pub unsafe fn vld2q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x2_t) -> u
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11920,7 +11920,7 @@ pub unsafe fn vld2q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11933,7 +11933,7 @@ pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> p
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -11945,7 +11945,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -11960,7 +11960,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -11972,7 +11972,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -11987,7 +11987,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12005,7 +12005,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12023,7 +12023,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12041,7 +12041,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12059,7 +12059,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12085,7 +12085,7 @@ pub unsafe fn vld3_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12098,7 +12098,7 @@ pub unsafe fn vld3_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12124,7 +12124,7 @@ pub unsafe fn vld3_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x3_t) -> i
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12137,7 +12137,7 @@ pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) ->
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -12149,7 +12149,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -12165,7 +12165,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12177,7 +12177,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12193,7 +12193,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12211,7 +12211,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12229,7 +12229,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12255,7 +12255,7 @@ pub unsafe fn vld3q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x3_t) -
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12268,7 +12268,7 @@ pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12294,7 +12294,7 @@ pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> in
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12320,7 +12320,7 @@ pub unsafe fn vld3q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12333,7 +12333,7 @@ pub unsafe fn vld3q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x3_t) -> u
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12346,7 +12346,7 @@ pub unsafe fn vld3q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12359,7 +12359,7 @@ pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> p
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -12371,7 +12371,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -12387,7 +12387,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12399,7 +12399,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12415,7 +12415,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12433,7 +12433,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12451,7 +12451,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12469,7 +12469,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12487,7 +12487,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12514,7 +12514,7 @@ pub unsafe fn vld4_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12541,7 +12541,7 @@ pub unsafe fn vld4_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12554,7 +12554,7 @@ pub unsafe fn vld4_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12567,7 +12567,7 @@ pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) ->
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -12579,7 +12579,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -12596,7 +12596,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12608,7 +12608,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12625,7 +12625,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12643,7 +12643,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12661,7 +12661,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12688,7 +12688,7 @@ pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12715,7 +12715,7 @@ pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> in
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12742,7 +12742,7 @@ pub unsafe fn vld4q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12755,7 +12755,7 @@ pub unsafe fn vld4q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12768,7 +12768,7 @@ pub unsafe fn vld4q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x4_t) -> u
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12781,7 +12781,7 @@ pub unsafe fn vld4q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12794,7 +12794,7 @@ pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> p
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12806,7 +12806,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12823,7 +12823,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12835,7 +12835,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12852,7 +12852,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12870,7 +12870,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12888,7 +12888,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12901,7 +12901,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12914,7 +12914,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12927,7 +12927,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12940,7 +12940,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12953,7 +12953,7 @@ pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -12966,7 +12966,7 @@ pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -12979,7 +12979,7 @@ pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -12992,7 +12992,7 @@ pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> ui
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13005,7 +13005,7 @@ pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13018,7 +13018,7 @@ pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13031,7 +13031,7 @@ pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13044,7 +13044,7 @@ pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> po
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13057,7 +13057,7 @@ pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13070,7 +13070,7 @@ pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13083,7 +13083,7 @@ pub unsafe fn vluti2q_lane_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13103,7 +13103,7 @@ pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13123,7 +13123,7 @@ pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13143,7 +13143,7 @@ pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> in
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13163,7 +13163,7 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13176,7 +13176,7 @@ pub unsafe fn vluti2_laneq_f16<const INDEX: i32>(a: float16x4_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13189,7 +13189,7 @@ pub unsafe fn vluti2q_laneq_f16<const INDEX: i32>(a: float16x8_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13202,7 +13202,7 @@ pub unsafe fn vluti2_laneq_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13215,7 +13215,7 @@ pub unsafe fn vluti2q_laneq_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13228,7 +13228,7 @@ pub unsafe fn vluti2_laneq_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13241,7 +13241,7 @@ pub unsafe fn vluti2q_laneq_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13254,7 +13254,7 @@ pub unsafe fn vluti2_laneq_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13267,7 +13267,7 @@ pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13280,7 +13280,7 @@ pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13293,7 +13293,7 @@ pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13313,7 +13313,7 @@ pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> i
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13333,7 +13333,7 @@ pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13353,7 +13353,7 @@ pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13373,7 +13373,7 @@ pub unsafe fn vluti2q_laneq_s16<const INDEX: i32>(a: int16x8_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13386,7 +13386,7 @@ pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13399,7 +13399,7 @@ pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13412,7 +13412,7 @@ pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13432,7 +13432,7 @@ pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t)
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13452,7 +13452,7 @@ pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13465,7 +13465,7 @@ pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13478,7 +13478,7 @@ pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13494,7 +13494,7 @@ pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13507,7 +13507,7 @@ pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13520,7 +13520,7 @@ pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13540,7 +13540,7 @@ pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13560,7 +13560,7 @@ pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13573,7 +13573,7 @@ pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -25837,7 +25837,7 @@ pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25850,7 +25850,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25863,7 +25863,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25875,7 +25875,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25887,7 +25887,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25899,7 +25899,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25911,7 +25911,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25923,7 +25923,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25935,7 +25935,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25947,7 +25947,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25959,7 +25959,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25971,7 +25971,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25983,7 +25983,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25995,7 +25995,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26007,7 +26007,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26019,7 +26019,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26031,7 +26031,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26043,7 +26043,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26055,7 +26055,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26067,7 +26067,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26079,7 +26079,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26091,7 +26091,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26103,7 +26103,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26115,7 +26115,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26127,7 +26127,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26139,7 +26139,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26151,7 +26151,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26163,7 +26163,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26175,7 +26175,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26193,7 +26193,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26211,7 +26211,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26229,7 +26229,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26247,7 +26247,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26271,7 +26271,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26295,7 +26295,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -26308,7 +26308,7 @@ pub unsafe fn vst1_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -26321,7 +26321,7 @@ pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26339,7 +26339,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26359,7 +26359,7 @@ pub unsafe fn vst2_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26379,7 +26379,7 @@ pub unsafe fn vst2_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26392,7 +26392,7 @@ pub unsafe fn vst2_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26405,7 +26405,7 @@ pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26423,7 +26423,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26441,7 +26441,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26461,7 +26461,7 @@ pub unsafe fn vst2q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26481,7 +26481,7 @@ pub unsafe fn vst2q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26501,7 +26501,7 @@ pub unsafe fn vst2q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26514,7 +26514,7 @@ pub unsafe fn vst2q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26527,7 +26527,7 @@ pub unsafe fn vst2q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26540,7 +26540,7 @@ pub unsafe fn vst2q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26553,7 +26553,7 @@ pub unsafe fn vst2q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26564,7 +26564,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26575,7 +26575,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26593,7 +26593,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26613,7 +26613,7 @@ pub unsafe fn vst3_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26633,7 +26633,7 @@ pub unsafe fn vst3_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26646,7 +26646,7 @@ pub unsafe fn vst3_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26659,7 +26659,7 @@ pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26677,7 +26677,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26695,7 +26695,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26715,7 +26715,7 @@ pub unsafe fn vst3q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26735,7 +26735,7 @@ pub unsafe fn vst3q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26755,7 +26755,7 @@ pub unsafe fn vst3q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26768,7 +26768,7 @@ pub unsafe fn vst3q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26781,7 +26781,7 @@ pub unsafe fn vst3q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26794,7 +26794,7 @@ pub unsafe fn vst3q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26807,7 +26807,7 @@ pub unsafe fn vst3q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26818,7 +26818,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26829,7 +26829,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26847,7 +26847,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26874,7 +26874,7 @@ pub unsafe fn vst4_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26901,7 +26901,7 @@ pub unsafe fn vst4_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26914,7 +26914,7 @@ pub unsafe fn vst4_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26927,7 +26927,7 @@ pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26945,7 +26945,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26963,7 +26963,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26990,7 +26990,7 @@ pub unsafe fn vst4q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -27017,7 +27017,7 @@ pub unsafe fn vst4q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -27044,7 +27044,7 @@ pub unsafe fn vst4q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -27057,7 +27057,7 @@ pub unsafe fn vst4q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27070,7 +27070,7 @@ pub unsafe fn vst4q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27083,7 +27083,7 @@ pub unsafe fn vst4q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27096,7 +27096,7 @@ pub unsafe fn vst4q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -27107,7 +27107,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index ac3b649fbf..5a415acc0c 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -12370,7 +12370,7 @@ pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -12395,7 +12395,7 @@ pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15133,7 +15133,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "Load one single-element structure and replicate to all lanes of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15152,7 +15152,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load one single-element structure and replicate to all lanes of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15171,7 +15171,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15194,7 +15194,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15217,7 +15217,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15240,7 +15240,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15263,7 +15263,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15286,7 +15286,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15309,7 +15309,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15332,7 +15332,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15355,7 +15355,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15378,7 +15378,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15401,7 +15401,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15424,7 +15424,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15447,7 +15447,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15470,7 +15470,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15493,7 +15493,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15516,7 +15516,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15539,7 +15539,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15562,7 +15562,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15585,7 +15585,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15608,7 +15608,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15631,7 +15631,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15663,7 +15663,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15695,7 +15695,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15727,7 +15727,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
@@ -15745,7 +15745,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
@@ -15764,7 +15764,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
@@ -15782,7 +15782,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
@@ -15801,7 +15801,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15827,7 +15827,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15853,7 +15853,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15879,7 +15879,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15905,7 +15905,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15931,7 +15931,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15957,7 +15957,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15970,7 +15970,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15983,7 +15983,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15996,7 +15996,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16009,7 +16009,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16022,7 +16022,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16035,7 +16035,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16048,7 +16048,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16061,7 +16061,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16074,7 +16074,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16087,7 +16087,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16100,7 +16100,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16113,7 +16113,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16126,7 +16126,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16139,7 +16139,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
@@ -16152,7 +16152,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16183,7 +16183,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16214,7 +16214,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16245,7 +16245,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16276,7 +16276,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16307,7 +16307,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16338,7 +16338,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
 #[doc = "Load one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16358,7 +16358,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
 #[doc = "Load one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16378,7 +16378,7 @@ pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16403,7 +16403,7 @@ pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16428,7 +16428,7 @@ pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16453,7 +16453,7 @@ pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> p
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16478,7 +16478,7 @@ pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16503,7 +16503,7 @@ pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16528,7 +16528,7 @@ pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16553,7 +16553,7 @@ pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> in
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16578,7 +16578,7 @@ pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16603,7 +16603,7 @@ pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16628,7 +16628,7 @@ pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16653,7 +16653,7 @@ pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> u
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16678,7 +16678,7 @@ pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16703,7 +16703,7 @@ pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16728,7 +16728,7 @@ pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16753,7 +16753,7 @@ pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16778,7 +16778,7 @@ pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16803,7 +16803,7 @@ pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16828,7 +16828,7 @@ pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16853,7 +16853,7 @@ pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16878,7 +16878,7 @@ pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16903,7 +16903,7 @@ pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16928,7 +16928,7 @@ pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16953,7 +16953,7 @@ pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16978,7 +16978,7 @@ pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t)
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
@@ -16996,7 +16996,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17019,7 +17019,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17042,7 +17042,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17065,7 +17065,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -17089,7 +17089,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -17116,7 +17116,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -17140,7 +17140,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -17168,7 +17168,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -17192,7 +17192,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -17221,7 +17221,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17234,7 +17234,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17247,7 +17247,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17260,7 +17260,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17273,7 +17273,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17286,7 +17286,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17299,7 +17299,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17312,7 +17312,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17325,7 +17325,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17356,7 +17356,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17387,7 +17387,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17418,7 +17418,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17449,7 +17449,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17480,7 +17480,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17511,7 +17511,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17542,7 +17542,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17573,7 +17573,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17604,7 +17604,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17635,7 +17635,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17666,7 +17666,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17697,7 +17697,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17728,7 +17728,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17759,7 +17759,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17790,7 +17790,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17821,7 +17821,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17852,7 +17852,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17883,7 +17883,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17914,7 +17914,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17945,7 +17945,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17976,7 +17976,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18007,7 +18007,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18038,7 +18038,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18069,7 +18069,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18093,7 +18093,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18120,7 +18120,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18144,7 +18144,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18172,7 +18172,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18196,7 +18196,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18225,7 +18225,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18249,7 +18249,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18288,7 +18288,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18312,7 +18312,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18358,7 +18358,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18382,7 +18382,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18435,7 +18435,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18459,7 +18459,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18486,7 +18486,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18510,7 +18510,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18538,7 +18538,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18562,7 +18562,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18591,7 +18591,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18615,7 +18615,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18642,7 +18642,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18666,7 +18666,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18694,7 +18694,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18718,7 +18718,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18747,7 +18747,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18771,7 +18771,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18798,7 +18798,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18822,7 +18822,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18850,7 +18850,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18874,7 +18874,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18903,7 +18903,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18927,7 +18927,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18954,7 +18954,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18978,7 +18978,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19006,7 +19006,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19030,7 +19030,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19059,7 +19059,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19082,7 +19082,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19105,7 +19105,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19128,7 +19128,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19152,7 +19152,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19179,7 +19179,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19203,7 +19203,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19231,7 +19231,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19255,7 +19255,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19284,7 +19284,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19308,7 +19308,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19335,7 +19335,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19359,7 +19359,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19387,7 +19387,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19411,7 +19411,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19440,7 +19440,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19464,7 +19464,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19503,7 +19503,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19527,7 +19527,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19573,7 +19573,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19597,7 +19597,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19650,7 +19650,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19674,7 +19674,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19701,7 +19701,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19725,7 +19725,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19753,7 +19753,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19777,7 +19777,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19806,7 +19806,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19830,7 +19830,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19857,7 +19857,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19881,7 +19881,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19909,7 +19909,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19933,7 +19933,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20120,7 +20120,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20144,7 +20144,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20163,7 +20163,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20182,7 +20182,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20206,7 +20206,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20230,7 +20230,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20246,7 +20246,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20262,7 +20262,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20278,7 +20278,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20294,7 +20294,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20310,7 +20310,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20326,7 +20326,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20342,7 +20342,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20358,7 +20358,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20377,7 +20377,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20396,7 +20396,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20415,7 +20415,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20434,7 +20434,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20453,7 +20453,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20472,7 +20472,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20491,7 +20491,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20510,7 +20510,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -20533,7 +20533,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20549,7 +20549,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20568,7 +20568,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20591,7 +20591,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20615,7 +20615,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20642,7 +20642,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20666,7 +20666,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20705,7 +20705,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20729,7 +20729,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20756,7 +20756,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20780,7 +20780,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20807,7 +20807,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20831,7 +20831,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20858,7 +20858,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20882,7 +20882,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20909,7 +20909,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20933,7 +20933,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20960,7 +20960,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20984,7 +20984,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -21023,7 +21023,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -21047,7 +21047,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -21074,7 +21074,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -21098,7 +21098,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -21125,7 +21125,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21144,7 +21144,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21163,7 +21163,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21187,7 +21187,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21211,7 +21211,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21227,7 +21227,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21243,7 +21243,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21259,7 +21259,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21275,7 +21275,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21291,7 +21291,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21307,7 +21307,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21323,7 +21323,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21339,7 +21339,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21358,7 +21358,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21377,7 +21377,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21396,7 +21396,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21415,7 +21415,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21434,7 +21434,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21453,7 +21453,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21472,7 +21472,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21491,7 +21491,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21517,7 +21517,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21543,7 +21543,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21570,7 +21570,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21601,7 +21601,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21622,7 +21622,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21644,7 +21644,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21665,7 +21665,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21686,7 +21686,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21707,7 +21707,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21728,7 +21728,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21749,7 +21749,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21773,7 +21773,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21797,7 +21797,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21821,7 +21821,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21845,7 +21845,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21864,7 +21864,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21888,7 +21888,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21912,7 +21912,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21937,7 +21937,7 @@ pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uin
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21962,7 +21962,7 @@ pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21987,7 +21987,7 @@ pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22012,7 +22012,7 @@ pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22037,7 +22037,7 @@ pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22062,7 +22062,7 @@ pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> pol
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22087,7 +22087,7 @@ pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22112,7 +22112,7 @@ pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -22135,7 +22135,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -22151,7 +22151,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22170,7 +22170,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22193,7 +22193,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22217,7 +22217,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22244,7 +22244,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22268,7 +22268,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22307,7 +22307,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22331,7 +22331,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22358,7 +22358,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22382,7 +22382,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22409,7 +22409,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22433,7 +22433,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22460,7 +22460,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22484,7 +22484,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22511,7 +22511,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22535,7 +22535,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22562,7 +22562,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22586,7 +22586,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22625,7 +22625,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22649,7 +22649,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22676,7 +22676,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22700,7 +22700,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22727,7 +22727,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22746,7 +22746,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22765,7 +22765,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22789,7 +22789,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22813,7 +22813,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22832,7 +22832,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22851,7 +22851,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22870,7 +22870,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22889,7 +22889,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22908,7 +22908,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22927,7 +22927,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22946,7 +22946,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22965,7 +22965,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22984,7 +22984,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23000,7 +23000,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23016,7 +23016,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23032,7 +23032,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23048,7 +23048,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23064,7 +23064,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23080,7 +23080,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23096,7 +23096,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23112,7 +23112,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -23135,7 +23135,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -23151,7 +23151,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23174,7 +23174,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23198,7 +23198,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23226,7 +23226,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23250,7 +23250,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23296,7 +23296,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23320,7 +23320,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23348,7 +23348,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23372,7 +23372,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23400,7 +23400,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23424,7 +23424,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23452,7 +23452,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23476,7 +23476,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23504,7 +23504,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23528,7 +23528,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23556,7 +23556,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23580,7 +23580,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23626,7 +23626,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23650,7 +23650,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23678,7 +23678,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23702,7 +23702,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23730,7 +23730,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23749,7 +23749,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23768,7 +23768,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -23792,7 +23792,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -23816,7 +23816,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23835,7 +23835,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23854,7 +23854,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23873,7 +23873,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23892,7 +23892,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23911,7 +23911,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23930,7 +23930,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23949,7 +23949,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23968,7 +23968,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -23984,7 +23984,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24000,7 +24000,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24016,7 +24016,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24032,7 +24032,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24048,7 +24048,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24064,7 +24064,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24080,7 +24080,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24096,7 +24096,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -24123,7 +24123,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -24150,7 +24150,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24182,7 +24182,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24214,7 +24214,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24241,7 +24241,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24268,7 +24268,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24293,7 +24293,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24320,7 +24320,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24347,7 +24347,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24374,7 +24374,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24401,7 +24401,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24428,7 +24428,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24453,7 +24453,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24478,7 +24478,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24503,7 +24503,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24528,7 +24528,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24553,7 +24553,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24578,7 +24578,7 @@ pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uin
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24603,7 +24603,7 @@ pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24628,7 +24628,7 @@ pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24653,7 +24653,7 @@ pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24678,7 +24678,7 @@ pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24703,7 +24703,7 @@ pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> pol
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24728,7 +24728,7 @@ pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24753,7 +24753,7 @@ pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -24776,7 +24776,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24795,7 +24795,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24811,7 +24811,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24834,7 +24834,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -24858,7 +24858,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -24886,7 +24886,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -24910,7 +24910,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -24956,7 +24956,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -24980,7 +24980,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25008,7 +25008,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25032,7 +25032,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25060,7 +25060,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25084,7 +25084,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25112,7 +25112,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25136,7 +25136,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25164,7 +25164,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25188,7 +25188,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25216,7 +25216,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25240,7 +25240,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25286,7 +25286,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25310,7 +25310,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25338,7 +25338,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25362,7 +25362,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25390,7 +25390,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25415,7 +25415,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -25433,7 +25433,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -25451,7 +25451,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -25474,7 +25474,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -25497,7 +25497,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25513,7 +25513,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25529,7 +25529,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25545,7 +25545,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25561,7 +25561,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25577,7 +25577,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25593,7 +25593,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25609,7 +25609,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25625,7 +25625,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25644,7 +25644,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25663,7 +25663,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25682,7 +25682,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25701,7 +25701,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25720,7 +25720,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25739,7 +25739,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25758,7 +25758,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25777,7 +25777,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25796,7 +25796,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -25819,7 +25819,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25835,7 +25835,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25858,7 +25858,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25882,7 +25882,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25911,7 +25911,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25935,7 +25935,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25988,7 +25988,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26012,7 +26012,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26041,7 +26041,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26065,7 +26065,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26094,7 +26094,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26118,7 +26118,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26147,7 +26147,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26171,7 +26171,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26200,7 +26200,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26224,7 +26224,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26253,7 +26253,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26277,7 +26277,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26330,7 +26330,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26354,7 +26354,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26383,7 +26383,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26407,7 +26407,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26436,7 +26436,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -26454,7 +26454,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -26472,7 +26472,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26495,7 +26495,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26518,7 +26518,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26537,7 +26537,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26556,7 +26556,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26575,7 +26575,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26594,7 +26594,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26613,7 +26613,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26632,7 +26632,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26651,7 +26651,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26670,7 +26670,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26686,7 +26686,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26702,7 +26702,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26718,7 +26718,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26734,7 +26734,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26750,7 +26750,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26766,7 +26766,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26782,7 +26782,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26798,7 +26798,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26826,7 +26826,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26854,7 +26854,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26886,7 +26886,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26918,7 +26918,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26946,7 +26946,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26974,7 +26974,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27002,7 +27002,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27030,7 +27030,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27058,7 +27058,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27086,7 +27086,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27114,7 +27114,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27140,7 +27140,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27166,7 +27166,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27192,7 +27192,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27218,7 +27218,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27244,7 +27244,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27270,7 +27270,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27296,7 +27296,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27321,7 +27321,7 @@ pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uin
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27346,7 +27346,7 @@ pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27371,7 +27371,7 @@ pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27396,7 +27396,7 @@ pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27421,7 +27421,7 @@ pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27446,7 +27446,7 @@ pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> pol
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27471,7 +27471,7 @@ pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27496,7 +27496,7 @@ pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -27519,7 +27519,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27538,7 +27538,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27554,7 +27554,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27577,7 +27577,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27601,7 +27601,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27630,7 +27630,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27654,7 +27654,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27707,7 +27707,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27731,7 +27731,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27760,7 +27760,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27784,7 +27784,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27813,7 +27813,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27837,7 +27837,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27866,7 +27866,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27890,7 +27890,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27919,7 +27919,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27943,7 +27943,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27972,7 +27972,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27996,7 +27996,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -28049,7 +28049,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -28073,7 +28073,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -28102,7 +28102,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -28126,7 +28126,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -28155,7 +28155,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Store SIMD&FP register (immediate offset)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65084,7 +65084,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65102,7 +65102,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65120,7 +65120,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65138,7 +65138,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65156,7 +65156,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65176,7 +65176,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65196,7 +65196,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65214,7 +65214,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65232,7 +65232,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65252,7 +65252,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65272,7 +65272,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65297,7 +65297,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65322,7 +65322,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65348,7 +65348,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65374,7 +65374,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65388,7 +65388,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65402,7 +65402,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65416,7 +65416,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65430,7 +65430,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65444,7 +65444,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65458,7 +65458,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65472,7 +65472,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65486,7 +65486,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65500,7 +65500,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65514,7 +65514,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65528,7 +65528,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65542,7 +65542,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65556,7 +65556,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65570,7 +65570,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65584,7 +65584,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65598,7 +65598,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65612,7 +65612,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65626,7 +65626,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65640,7 +65640,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65654,7 +65654,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65668,7 +65668,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65682,7 +65682,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65696,7 +65696,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65710,7 +65710,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65726,7 +65726,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65742,7 +65742,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65761,7 +65761,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65780,7 +65780,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65799,7 +65799,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65818,7 +65818,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65840,7 +65840,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65862,7 +65862,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65887,7 +65887,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65912,7 +65912,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65932,7 +65932,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65952,7 +65952,7 @@ pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65977,7 +65977,7 @@ pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66002,7 +66002,7 @@ pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66027,7 +66027,7 @@ pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66052,7 +66052,7 @@ pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66077,7 +66077,7 @@ pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66102,7 +66102,7 @@ pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66127,7 +66127,7 @@ pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66152,7 +66152,7 @@ pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66177,7 +66177,7 @@ pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66202,7 +66202,7 @@ pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66227,7 +66227,7 @@ pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66252,7 +66252,7 @@ pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66277,7 +66277,7 @@ pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66302,7 +66302,7 @@ pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66327,7 +66327,7 @@ pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66352,7 +66352,7 @@ pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66377,7 +66377,7 @@ pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66402,7 +66402,7 @@ pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66427,7 +66427,7 @@ pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66452,7 +66452,7 @@ pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -66477,7 +66477,7 @@ pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66502,7 +66502,7 @@ pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66527,7 +66527,7 @@ pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66550,7 +66550,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66573,7 +66573,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66596,7 +66596,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66619,7 +66619,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66642,7 +66642,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66665,7 +66665,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66684,7 +66684,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66703,7 +66703,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66722,7 +66722,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66741,7 +66741,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66760,7 +66760,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66779,7 +66779,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66798,7 +66798,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66817,7 +66817,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66833,7 +66833,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66849,7 +66849,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66865,7 +66865,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66881,7 +66881,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66897,7 +66897,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66913,7 +66913,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66929,7 +66929,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66945,7 +66945,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66964,7 +66964,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66983,7 +66983,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67002,7 +67002,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67021,7 +67021,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67040,7 +67040,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67059,7 +67059,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67078,7 +67078,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67097,7 +67097,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67113,7 +67113,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67129,7 +67129,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67145,7 +67145,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67161,7 +67161,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67177,7 +67177,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67193,7 +67193,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67209,7 +67209,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67225,7 +67225,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67244,7 +67244,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67263,7 +67263,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67282,7 +67282,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67301,7 +67301,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67320,7 +67320,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67339,7 +67339,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67358,7 +67358,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67377,7 +67377,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67393,7 +67393,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67409,7 +67409,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67425,7 +67425,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67441,7 +67441,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67457,7 +67457,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67473,7 +67473,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67489,7 +67489,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67505,7 +67505,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67528,7 +67528,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67551,7 +67551,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67574,7 +67574,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67597,7 +67597,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67620,7 +67620,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67643,7 +67643,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67666,7 +67666,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67689,7 +67689,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67712,7 +67712,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67735,7 +67735,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67758,7 +67758,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67781,7 +67781,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67804,7 +67804,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67827,7 +67827,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67850,7 +67850,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67873,7 +67873,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67896,7 +67896,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67919,7 +67919,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67942,7 +67942,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67965,7 +67965,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67988,7 +67988,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68011,7 +68011,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68034,7 +68034,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68057,7 +68057,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68080,7 +68080,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68103,7 +68103,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68126,7 +68126,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68149,7 +68149,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68172,7 +68172,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68195,7 +68195,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68218,7 +68218,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68241,7 +68241,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68264,7 +68264,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68287,7 +68287,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68310,7 +68310,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68473,7 +68473,7 @@ unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68491,7 +68491,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68509,7 +68509,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -68534,7 +68534,7 @@ pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68555,7 +68555,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68576,7 +68576,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68595,7 +68595,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68614,7 +68614,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68633,7 +68633,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68652,7 +68652,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68671,7 +68671,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68690,7 +68690,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68709,7 +68709,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68728,7 +68728,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68747,7 +68747,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68766,7 +68766,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68782,7 +68782,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68798,7 +68798,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68814,7 +68814,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68830,7 +68830,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68846,7 +68846,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68862,7 +68862,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68878,7 +68878,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68894,7 +68894,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68917,7 +68917,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68940,7 +68940,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68961,7 +68961,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68982,7 +68982,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69003,7 +69003,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69024,7 +69024,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69045,7 +69045,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69066,7 +69066,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69087,7 +69087,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69108,7 +69108,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69129,7 +69129,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69147,7 +69147,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69165,7 +69165,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69183,7 +69183,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69201,7 +69201,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69219,7 +69219,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69237,7 +69237,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69255,7 +69255,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69280,7 +69280,7 @@ pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69305,7 +69305,7 @@ pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69330,7 +69330,7 @@ pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69355,7 +69355,7 @@ pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69380,7 +69380,7 @@ pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69405,7 +69405,7 @@ pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69430,7 +69430,7 @@ pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69455,7 +69455,7 @@ pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -69478,7 +69478,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69494,7 +69494,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69513,7 +69513,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69536,7 +69536,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69559,7 +69559,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69582,7 +69582,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69605,7 +69605,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69628,7 +69628,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69651,7 +69651,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69674,7 +69674,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69697,7 +69697,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69720,7 +69720,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69743,7 +69743,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69766,7 +69766,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -69785,7 +69785,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -69804,7 +69804,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69825,7 +69825,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69846,7 +69846,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69862,7 +69862,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69878,7 +69878,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69894,7 +69894,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69910,7 +69910,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69926,7 +69926,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69942,7 +69942,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69958,7 +69958,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69974,7 +69974,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69993,7 +69993,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70012,7 +70012,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70031,7 +70031,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70050,7 +70050,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70069,7 +70069,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70088,7 +70088,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70107,7 +70107,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70126,7 +70126,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70154,7 +70154,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70182,7 +70182,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70205,7 +70205,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70228,7 +70228,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70253,7 +70253,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70278,7 +70278,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70296,7 +70296,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70321,7 +70321,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70346,7 +70346,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70371,7 +70371,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70396,7 +70396,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70417,7 +70417,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70438,7 +70438,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70459,7 +70459,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70480,7 +70480,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70501,7 +70501,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70522,7 +70522,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70543,7 +70543,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70568,7 +70568,7 @@ pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70593,7 +70593,7 @@ pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70618,7 +70618,7 @@ pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70643,7 +70643,7 @@ pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70668,7 +70668,7 @@ pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70693,7 +70693,7 @@ pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70718,7 +70718,7 @@ pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70743,7 +70743,7 @@ pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -70766,7 +70766,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70785,7 +70785,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70801,7 +70801,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70824,7 +70824,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70847,7 +70847,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70870,7 +70870,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70893,7 +70893,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70916,7 +70916,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70939,7 +70939,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70962,7 +70962,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70985,7 +70985,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71008,7 +71008,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71031,7 +71031,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71054,7 +71054,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71080,7 +71080,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71106,7 +71106,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71127,7 +71127,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71148,7 +71148,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71171,7 +71171,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71194,7 +71194,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71210,7 +71210,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71233,7 +71233,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71256,7 +71256,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71279,7 +71279,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71302,7 +71302,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71325,7 +71325,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71344,7 +71344,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71363,7 +71363,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71382,7 +71382,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71401,7 +71401,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71420,7 +71420,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71439,7 +71439,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71458,7 +71458,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71477,7 +71477,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71506,7 +71506,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71535,7 +71535,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71565,7 +71565,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71595,7 +71595,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71621,7 +71621,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71647,7 +71647,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71673,7 +71673,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71699,7 +71699,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71725,7 +71725,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71751,7 +71751,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71777,7 +71777,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71805,7 +71805,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71833,7 +71833,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71854,7 +71854,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71882,7 +71882,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71910,7 +71910,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71938,7 +71938,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71966,7 +71966,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71991,7 +71991,7 @@ pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72016,7 +72016,7 @@ pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72041,7 +72041,7 @@ pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72066,7 +72066,7 @@ pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72091,7 +72091,7 @@ pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72116,7 +72116,7 @@ pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72141,7 +72141,7 @@ pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72166,7 +72166,7 @@ pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -72189,7 +72189,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -72212,7 +72212,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -72231,7 +72231,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72254,7 +72254,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72277,7 +72277,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72300,7 +72300,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72323,7 +72323,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72346,7 +72346,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72369,7 +72369,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72392,7 +72392,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72415,7 +72415,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72438,7 +72438,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72461,7 +72461,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72484,7 +72484,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "Store SIMD&FP register (immediate offset)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index 71301c5ba6..ce427d54b3 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -840,7 +840,7 @@ impl fmt::Display for UnsafetyComment {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         match self {
             Self::Custom(s) => s.fmt(f),
-            Self::Neon => write!(f, "Neon instrinsic unsafe"),
+            Self::Neon => write!(f, "Neon intrinsic unsafe"),
             Self::Uninitialized => write!(
                 f,
                 "This creates an uninitialized value, and may be unsound (like \

From 1b44fd088bd50e9da922ce3a5680c5df2fc93e0d Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Sat, 10 Jan 2026 20:53:43 +0800
Subject: [PATCH 110/326] remove fp16 target feature from some vreinterpret
 intrinsics

---
 .../src/arm_shared/neon/generated.rs          | 200 +++++++++---------
 .../spec/neon/arm_shared.spec.yml             |   2 -
 2 files changed, 100 insertions(+), 102 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 0aeb740efc..1a994c153a 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -42565,13 +42565,13 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42588,13 +42588,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42615,13 +42615,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42638,13 +42638,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42665,13 +42665,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42688,13 +42688,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42715,13 +42715,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42738,13 +42738,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42765,13 +42765,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42788,13 +42788,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42812,13 +42812,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42835,13 +42835,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42862,13 +42862,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42885,13 +42885,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42912,13 +42912,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42935,13 +42935,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42962,13 +42962,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42985,13 +42985,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43009,13 +43009,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43032,13 +43032,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43059,13 +43059,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43082,13 +43082,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43109,13 +43109,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43132,13 +43132,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43159,13 +43159,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43182,13 +43182,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43213,13 +43213,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43236,13 +43236,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43263,13 +43263,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43286,13 +43286,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43313,13 +43313,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43336,13 +43336,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43363,13 +43363,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43386,13 +43386,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43417,13 +43417,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43440,13 +43440,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43467,13 +43467,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43490,13 +43490,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43517,13 +43517,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43540,13 +43540,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43567,13 +43567,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43590,13 +43590,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43621,13 +43621,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43644,13 +43644,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43671,13 +43671,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43694,13 +43694,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43721,13 +43721,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43744,13 +43744,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43771,13 +43771,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43794,13 +43794,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43821,13 +43821,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43844,13 +43844,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43872,13 +43872,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43895,13 +43895,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43922,13 +43922,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43945,13 +43945,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43972,13 +43972,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43995,13 +43995,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44022,13 +44022,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44045,13 +44045,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44072,13 +44072,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44095,13 +44095,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44121,13 +44121,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44144,13 +44144,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44171,13 +44171,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44194,13 +44194,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44221,13 +44221,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44244,13 +44244,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44272,13 +44272,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44295,13 +44295,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44322,13 +44322,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44345,13 +44345,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44372,13 +44372,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44395,13 +44395,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44422,13 +44422,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44445,13 +44445,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44472,13 +44472,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44495,13 +44495,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44521,13 +44521,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44544,13 +44544,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44571,13 +44571,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44594,13 +44594,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44621,13 +44621,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44644,13 +44644,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44672,13 +44672,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44695,13 +44695,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44722,13 +44722,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44745,13 +44745,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44772,13 +44772,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44795,13 +44795,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44821,13 +44821,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44844,13 +44844,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44868,13 +44868,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44891,13 +44891,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44915,13 +44915,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44938,13 +44938,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44965,13 +44965,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44988,13 +44988,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -45014,13 +45014,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -45037,13 +45037,13 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index c7a333d7f7..d8e8cd0e7c 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -8785,7 +8785,6 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
-      - *neon-fp16
       - *neon-not-arm-stable-fp16
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec
@@ -8849,7 +8848,6 @@ intrinsics:
       - *neon-v8
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
-      - *neon-fp16
       - *neon-not-arm-stable-fp16
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec

From 2bd539d6bb05bd29e16def4813b1697a0630bc5d Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Wed, 28 Jan 2026 19:15:25 +0800
Subject: [PATCH 111/326] fix overflowing_literals in avx512fp16 tests

---
 crates/core_arch/src/x86/avx512fp16.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 57d47c0bb0..2b80215c41 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -23993,16 +23993,16 @@ mod tests {
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
     const fn test_mm256_reduce_mul_ph() {
-        let a = _mm256_set1_ph(2.0);
+        let a = _mm256_set1_ph(1.2);
         let r = _mm256_reduce_mul_ph(a);
-        assert_eq!(r, 65536.0);
+        assert_eq!(r, 18.5);
     }
 
     #[simd_test(enable = "avx512fp16")]
     const fn test_mm512_reduce_mul_ph() {
-        let a = _mm512_set1_ph(2.0);
+        let a = _mm512_set1_ph(1.2);
         let r = _mm512_reduce_mul_ph(a);
-        assert_eq!(r, 16777216.0);
+        assert_eq!(r, 342.3);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]

From 72f7d39ae9215e862ebe6f14c88b2e17de2599e7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Wed, 28 Jan 2026 22:05:10 +0100
Subject: [PATCH 112/326] Avoid `unsafe fn` in aarch64, powerpc and s390x tests

---
 crates/core_arch/src/aarch64/neon/mod.rs | 264 ++++++------
 crates/core_arch/src/powerpc/altivec.rs  | 528 +++++++++++++----------
 crates/core_arch/src/powerpc/vsx.rs      |  36 +-
 crates/core_arch/src/s390x/vector.rs     | 135 +++---
 4 files changed, 537 insertions(+), 426 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index b172b57f32..bac4574239 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -569,47 +569,46 @@ mod tests {
     use crate::core_arch::aarch64::test_support::*;
     use crate::core_arch::arm_shared::test_support::*;
     use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*};
-    use std::mem::transmute;
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_f64() {
-        let a = 1.;
-        let b = 8.;
-        let e = 9.;
-        let r: f64 = transmute(vadd_f64(transmute(a), transmute(b)));
+    fn test_vadd_f64() {
+        let a = f64x1::from_array([1.]);
+        let b = f64x1::from_array([8.]);
+        let e = f64x1::from_array([9.]);
+        let r = f64x1::from(vadd_f64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_f64() {
+    fn test_vaddq_f64() {
         let a = f64x2::new(1., 2.);
         let b = f64x2::new(8., 7.);
         let e = f64x2::new(9., 9.);
-        let r: f64x2 = transmute(vaddq_f64(transmute(a), transmute(b)));
+        let r = f64x2::from(vaddq_f64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s64() {
-        let a = 1_i64;
-        let b = 8_i64;
-        let e = 9_i64;
-        let r: i64 = transmute(vadd_s64(transmute(a), transmute(b)));
+    fn test_vadd_s64() {
+        let a = i64x1::from_array([1]);
+        let b = i64x1::from_array([8]);
+        let e = i64x1::from_array([9]);
+        let r = i64x1::from(vadd_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u64() {
-        let a = 1_u64;
-        let b = 8_u64;
-        let e = 9_u64;
-        let r: u64 = transmute(vadd_u64(transmute(a), transmute(b)));
+    fn test_vadd_u64() {
+        let a = u64x1::from_array([1]);
+        let b = u64x1::from_array([8]);
+        let e = u64x1::from_array([9]);
+        let r = u64x1::from(vadd_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddd_s64() {
+    fn test_vaddd_s64() {
         let a = 1_i64;
         let b = 8_i64;
         let e = 9_i64;
@@ -618,7 +617,7 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddd_u64() {
+    fn test_vaddd_u64() {
         let a = 1_u64;
         let b = 8_u64;
         let e = 9_u64;
@@ -627,25 +626,25 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vext_p64() {
-        let a: i64x1 = i64x1::new(0);
-        let b: i64x1 = i64x1::new(1);
-        let e: i64x1 = i64x1::new(0);
-        let r: i64x1 = transmute(vext_p64::<0>(transmute(a), transmute(b)));
+    fn test_vext_p64() {
+        let a = u64x1::new(0);
+        let b = u64x1::new(1);
+        let e = u64x1::new(0);
+        let r = u64x1::from(vext_p64::<0>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vext_f64() {
-        let a: f64x1 = f64x1::new(0.);
-        let b: f64x1 = f64x1::new(1.);
-        let e: f64x1 = f64x1::new(0.);
-        let r: f64x1 = transmute(vext_f64::<0>(transmute(a), transmute(b)));
+    fn test_vext_f64() {
+        let a = f64x1::new(0.);
+        let b = f64x1::new(1.);
+        let e = f64x1::new(0.);
+        let r = f64x1::from(vext_f64::<0>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vshld_n_s64() {
+    fn test_vshld_n_s64() {
         let a: i64 = 1;
         let e: i64 = 4;
         let r: i64 = vshld_n_s64::<2>(a);
@@ -653,7 +652,7 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vshld_n_u64() {
+    fn test_vshld_n_u64() {
         let a: u64 = 1;
         let e: u64 = 4;
         let r: u64 = vshld_n_u64::<2>(a);
@@ -661,7 +660,7 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vshrd_n_s64() {
+    fn test_vshrd_n_s64() {
         let a: i64 = 4;
         let e: i64 = 1;
         let r: i64 = vshrd_n_s64::<2>(a);
@@ -669,7 +668,7 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vshrd_n_u64() {
+    fn test_vshrd_n_u64() {
         let a: u64 = 4;
         let e: u64 = 1;
         let r: u64 = vshrd_n_u64::<2>(a);
@@ -677,7 +676,7 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsrad_n_s64() {
+    fn test_vsrad_n_s64() {
         let a: i64 = 1;
         let b: i64 = 4;
         let e: i64 = 2;
@@ -686,7 +685,7 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsrad_n_u64() {
+    fn test_vsrad_n_u64() {
         let a: u64 = 1;
         let b: u64 = 4;
         let e: u64 = 2;
@@ -695,293 +694,300 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_f64() {
+    fn test_vdup_n_f64() {
         let a: f64 = 3.3;
         let e = f64x1::new(3.3);
-        let r: f64x1 = transmute(vdup_n_f64(a));
+        let r = f64x1::from(vdup_n_f64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_p64() {
+    fn test_vdup_n_p64() {
         let a: u64 = 3;
         let e = u64x1::new(3);
-        let r: u64x1 = transmute(vdup_n_p64(a));
+        let r = u64x1::from(vdup_n_p64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_f64() {
+    fn test_vdupq_n_f64() {
         let a: f64 = 3.3;
         let e = f64x2::new(3.3, 3.3);
-        let r: f64x2 = transmute(vdupq_n_f64(a));
+        let r = f64x2::from(vdupq_n_f64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_p64() {
+    fn test_vdupq_n_p64() {
         let a: u64 = 3;
         let e = u64x2::new(3, 3);
-        let r: u64x2 = transmute(vdupq_n_p64(a));
+        let r = u64x2::from(vdupq_n_p64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_p64() {
+    fn test_vmov_n_p64() {
         let a: u64 = 3;
         let e = u64x1::new(3);
-        let r: u64x1 = transmute(vmov_n_p64(a));
+        let r = u64x1::from(vmov_n_p64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_f64() {
+    fn test_vmov_n_f64() {
         let a: f64 = 3.3;
         let e = f64x1::new(3.3);
-        let r: f64x1 = transmute(vmov_n_f64(a));
+        let r = f64x1::from(vmov_n_f64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_p64() {
+    fn test_vmovq_n_p64() {
         let a: u64 = 3;
         let e = u64x2::new(3, 3);
-        let r: u64x2 = transmute(vmovq_n_p64(a));
+        let r = u64x2::from(vmovq_n_p64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_f64() {
+    fn test_vmovq_n_f64() {
         let a: f64 = 3.3;
         let e = f64x2::new(3.3, 3.3);
-        let r: f64x2 = transmute(vmovq_n_f64(a));
+        let r = f64x2::from(vmovq_n_f64(a));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_f64() {
+    fn test_vget_high_f64() {
         let a = f64x2::new(1.0, 2.0);
         let e = f64x1::new(2.0);
-        let r: f64x1 = transmute(vget_high_f64(transmute(a)));
+        let r = f64x1::from(vget_high_f64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_p64() {
+    fn test_vget_high_p64() {
         let a = u64x2::new(1, 2);
         let e = u64x1::new(2);
-        let r: u64x1 = transmute(vget_high_p64(transmute(a)));
+        let r = u64x1::from(vget_high_p64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_f64() {
+    fn test_vget_low_f64() {
         let a = f64x2::new(1.0, 2.0);
         let e = f64x1::new(1.0);
-        let r: f64x1 = transmute(vget_low_f64(transmute(a)));
+        let r = f64x1::from(vget_low_f64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_p64() {
+    fn test_vget_low_p64() {
         let a = u64x2::new(1, 2);
         let e = u64x1::new(1);
-        let r: u64x1 = transmute(vget_low_p64(transmute(a)));
+        let r = u64x1::from(vget_low_p64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_f64() {
+    fn test_vget_lane_f64() {
         let v = f64x1::new(1.0);
-        let r = vget_lane_f64::<0>(transmute(v));
+        let r = vget_lane_f64::<0>(v.into());
         assert_eq!(r, 1.0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_f64() {
+    fn test_vgetq_lane_f64() {
         let v = f64x2::new(0.0, 1.0);
-        let r = vgetq_lane_f64::<1>(transmute(v));
+        let r = vgetq_lane_f64::<1>(v.into());
         assert_eq!(r, 1.0);
-        let r = vgetq_lane_f64::<0>(transmute(v));
+        let r = vgetq_lane_f64::<0>(v.into());
         assert_eq!(r, 0.0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_lane_s64() {
-        let a: i64x1 = i64x1::new(1);
-        let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let r: i64x1 = transmute(vcopy_lane_s64::<0, 0>(transmute(a), transmute(b)));
+    fn test_vcopy_lane_s64() {
+        let a = i64x1::new(1);
+        let b = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let r = i64x1::from(vcopy_lane_s64::<0, 0>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_lane_u64() {
-        let a: u64x1 = u64x1::new(1);
-        let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
-        let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
-        let r: u64x1 = transmute(vcopy_lane_u64::<0, 0>(transmute(a), transmute(b)));
+    fn test_vcopy_lane_u64() {
+        let a = u64x1::new(1);
+        let b = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+        let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+        let r = u64x1::from(vcopy_lane_u64::<0, 0>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_lane_p64() {
-        let a: i64x1 = i64x1::new(1);
-        let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let r: i64x1 = transmute(vcopy_lane_p64::<0, 0>(transmute(a), transmute(b)));
+    fn test_vcopy_lane_p64() {
+        let a = u64x1::new(1);
+        let b = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let r = u64x1::from(vcopy_lane_p64::<0, 0>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_lane_f64() {
-        let a: f64 = 1.;
-        let b: f64 = 0.;
-        let e: f64 = 0.;
-        let r: f64 = transmute(vcopy_lane_f64::<0, 0>(transmute(a), transmute(b)));
+    fn test_vcopy_lane_f64() {
+        let a = f64x1::from_array([1.]);
+        let b = f64x1::from_array([0.]);
+        let e = f64x1::from_array([0.]);
+        let r = f64x1::from(vcopy_lane_f64::<0, 0>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_laneq_s64() {
-        let a: i64x1 = i64x1::new(1);
-        let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let r: i64x1 = transmute(vcopy_laneq_s64::<0, 1>(transmute(a), transmute(b)));
+    fn test_vcopy_laneq_s64() {
+        let a = i64x1::new(1);
+        let b = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let r = i64x1::from(vcopy_laneq_s64::<0, 1>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_laneq_u64() {
-        let a: u64x1 = u64x1::new(1);
-        let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF);
-        let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
-        let r: u64x1 = transmute(vcopy_laneq_u64::<0, 1>(transmute(a), transmute(b)));
+    fn test_vcopy_laneq_u64() {
+        let a = u64x1::new(1);
+        let b = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+        let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+        let r = u64x1::from(vcopy_laneq_u64::<0, 1>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_laneq_p64() {
-        let a: i64x1 = i64x1::new(1);
-        let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let r: i64x1 = transmute(vcopy_laneq_p64::<0, 1>(transmute(a), transmute(b)));
+    fn test_vcopy_laneq_p64() {
+        let a = u64x1::new(1);
+        let b = u64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+        let r = u64x1::from(vcopy_laneq_p64::<0, 1>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcopy_laneq_f64() {
-        let a: f64 = 1.;
-        let b: f64x2 = f64x2::new(0., 0.5);
-        let e: f64 = 0.5;
-        let r: f64 = transmute(vcopy_laneq_f64::<0, 1>(transmute(a), transmute(b)));
+    fn test_vcopy_laneq_f64() {
+        let a = f64x1::from_array([1.]);
+        let b = f64x2::from_array([0., 0.5]);
+        let e = f64x1::from_array([0.5]);
+        let r = f64x1::from(vcopy_laneq_f64::<0, 1>(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_f64() {
+    fn test_vbsl_f64() {
         let a = u64x1::new(0x8000000000000000);
         let b = f64x1::new(-1.23f64);
         let c = f64x1::new(2.34f64);
         let e = f64x1::new(-2.34f64);
-        let r: f64x1 = transmute(vbsl_f64(transmute(a), transmute(b), transmute(c)));
+        let r = f64x1::from(vbsl_f64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_p64() {
+    fn test_vbsl_p64() {
         let a = u64x1::new(1);
         let b = u64x1::new(u64::MAX);
         let c = u64x1::new(u64::MIN);
         let e = u64x1::new(1);
-        let r: u64x1 = transmute(vbsl_p64(transmute(a), transmute(b), transmute(c)));
+        let r = u64x1::from(vbsl_p64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_f64() {
+    fn test_vbslq_f64() {
         let a = u64x2::new(1, 0x8000000000000000);
         let b = f64x2::new(f64::MAX, -1.23f64);
         let c = f64x2::new(f64::MIN, 2.34f64);
         let e = f64x2::new(f64::MIN, -2.34f64);
-        let r: f64x2 = transmute(vbslq_f64(transmute(a), transmute(b), transmute(c)));
+        let r = f64x2::from(vbslq_f64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_p64() {
+    fn test_vbslq_p64() {
         let a = u64x2::new(u64::MAX, 1);
         let b = u64x2::new(u64::MAX, u64::MAX);
         let c = u64x2::new(u64::MIN, u64::MIN);
         let e = u64x2::new(u64::MAX, 1);
-        let r: u64x2 = transmute(vbslq_p64(transmute(a), transmute(b), transmute(c)));
+        let r = u64x2::from(vbslq_p64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_f64() {
+    fn test_vld1_f64() {
         let a: [f64; 2] = [0., 1.];
         let e = f64x1::new(1.);
-        let r: f64x1 = transmute(vld1_f64(a[1..].as_ptr()));
+        let r = unsafe { f64x1::from(vld1_f64(a[1..].as_ptr())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_f64() {
+    fn test_vld1q_f64() {
         let a: [f64; 3] = [0., 1., 2.];
         let e = f64x2::new(1., 2.);
-        let r: f64x2 = transmute(vld1q_f64(a[1..].as_ptr()));
+        let r = unsafe { f64x2::from(vld1q_f64(a[1..].as_ptr())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_f64() {
+    fn test_vld1_dup_f64() {
         let a: [f64; 2] = [1., 42.];
         let e = f64x1::new(42.);
-        let r: f64x1 = transmute(vld1_dup_f64(a[1..].as_ptr()));
+        let r = unsafe { f64x1::from(vld1_dup_f64(a[1..].as_ptr())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_f64() {
+    fn test_vld1q_dup_f64() {
         let elem: f64 = 42.;
         let e = f64x2::new(42., 42.);
-        let r: f64x2 = transmute(vld1q_dup_f64(&elem));
+        let r = unsafe { f64x2::from(vld1q_dup_f64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_f64() {
+    fn test_vld1_lane_f64() {
         let a = f64x1::new(0.);
         let elem: f64 = 42.;
         let e = f64x1::new(42.);
-        let r: f64x1 = transmute(vld1_lane_f64::<0>(&elem, transmute(a)));
+        let r = unsafe { f64x1::from(vld1_lane_f64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_f64() {
+    fn test_vld1q_lane_f64() {
         let a = f64x2::new(0., 1.);
         let elem: f64 = 42.;
         let e = f64x2::new(0., 42.);
-        let r: f64x2 = transmute(vld1q_lane_f64::<1>(&elem, transmute(a)));
+        let r = unsafe { f64x2::from(vld1q_lane_f64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vst1_f64() {
+    fn test_vst1_f64() {
         let mut vals = [0_f64; 2];
         let a = f64x1::new(1.);
 
-        vst1_f64(vals[1..].as_mut_ptr(), transmute(a));
+        unsafe {
+            vst1_f64(vals[1..].as_mut_ptr(), a.into());
+        }
 
         assert_eq!(vals[0], 0.);
         assert_eq!(vals[1], 1.);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vst1q_f64() {
+    fn test_vst1q_f64() {
         let mut vals = [0_f64; 3];
         let a = f64x2::new(1., 2.);
 
-        vst1q_f64(vals[1..].as_mut_ptr(), transmute(a));
+        unsafe {
+            vst1q_f64(vals[1..].as_mut_ptr(), a.into());
+        }
 
         assert_eq!(vals[0], 0.);
         assert_eq!(vals[1], 1.);
diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index fb1a9d8ed9..7786a6731b 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -47,6 +47,54 @@ types! {
     pub struct vector_float(4 x f32);
 }
 
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<m8x16> for vector_bool_char {
+    #[inline]
+    fn from(value: m8x16) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<vector_bool_char> for m8x16 {
+    #[inline]
+    fn from(value: vector_bool_char) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<m16x8> for vector_bool_short {
+    #[inline]
+    fn from(value: m16x8) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<vector_bool_short> for m16x8 {
+    #[inline]
+    fn from(value: vector_bool_short) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<m32x4> for vector_bool_int {
+    #[inline]
+    fn from(value: m32x4) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<vector_bool_int> for m32x4 {
+    #[inline]
+    fn from(value: vector_bool_int) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
 #[allow(improper_ctypes)]
 unsafe extern "C" {
     #[link_name = "llvm.ppc.altivec.lvx"]
@@ -4653,22 +4701,22 @@ mod tests {
         };
         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
-                let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+            fn $name() {
+                let a: s_t_l!($ty) = $ty::new($($a),+).into();
+                let b: s_t_l!($ty) = $ty::new($($b),+).into();
 
                 let d = $ty_out::new($($d),+);
-                let r : $ty_out = transmute($fn(a, b));
+                let r = $ty_out::from(unsafe { $fn(a, b) });
                 assert_eq!(d, r);
             }
          };
          { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
-                let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+            fn $name() {
+                let a: s_t_l!($ty) = $ty::new($($a),+).into();
+                let b: s_t_l!($ty) = $ty::new($($b),+).into();
 
-                let r : $ty_out = transmute($fn(a, b));
+                let r = $ty_out::from(unsafe { $fn(a, b) });
                 assert_eq!($d, r);
             }
          }
@@ -4677,11 +4725,11 @@ mod tests {
     macro_rules! test_vec_1 {
         { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: vector_float = transmute(f32x4::new($($a),+));
+            fn $name() {
+                let a = vector_float::from(f32x4::new($($a),+));
 
-                let d: vector_float = transmute(f32x4::new($($d),+));
-                let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)));
+                let d = vector_float::from(f32x4::new($($d),+));
+                let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) });
                 let e = m32x4::new(true, true, true, true);
                 assert_eq!(e, r);
             }
@@ -4691,18 +4739,18 @@ mod tests {
         };
         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
+            fn $name() {
+                let a: s_t_l!($ty) = $ty::new($($a),+).into();
 
                 let d = $ty_out::new($($d),+);
-                let r : $ty_out = transmute($fn(a));
+                let r = $ty_out::from(unsafe { $fn(a) });
                 assert_eq!(d, r);
             }
         }
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_ld() {
+    fn test_vec_ld() {
         let pat = [
             u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
             u8x16::new(
@@ -4711,14 +4759,14 @@ mod tests {
         ];
 
         for off in 0..16 {
-            let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
+            let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) });
             assert_eq!(
                 v,
                 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
             );
         }
         for off in 16..32 {
-            let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
+            let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) });
             assert_eq!(
                 v,
                 u8x16::new(
@@ -4729,7 +4777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_xl() {
+    fn test_vec_xl() {
         let pat = [
             u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
             u8x16::new(
@@ -4738,7 +4786,7 @@ mod tests {
         ];
 
         for off in 0..16 {
-            let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off)));
+            let val = u8x16::from(unsafe { vec_xl(0, (pat.as_ptr() as *const u8).offset(off)) });
             for i in 0..16 {
                 let v = val.extract_dyn(i);
                 assert_eq!(off as usize + i, v as usize);
@@ -4747,14 +4795,16 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_xst() {
-        let v: vector_unsigned_char = transmute(u8x16::new(
+    fn test_vec_xst() {
+        let v = vector_unsigned_char::from(u8x16::new(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
         ));
 
         for off in 0..16 {
             let mut buf = [0u8; 32];
-            vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off));
+            unsafe {
+                vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off));
+            }
             for i in 0..16 {
                 assert_eq!(i as u8, buf[off as usize..][i]);
             }
@@ -4762,7 +4812,7 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_ldl() {
+    fn test_vec_ldl() {
         let pat = [
             u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
             u8x16::new(
@@ -4771,14 +4821,14 @@ mod tests {
         ];
 
         for off in 0..16 {
-            let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)));
+            let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) });
             assert_eq!(
                 v,
                 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
             );
         }
         for off in 16..32 {
-            let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)));
+            let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) });
             assert_eq!(
                 v,
                 u8x16::new(
@@ -4789,30 +4839,30 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_lde_u8() {
+    fn test_vec_lde_u8() {
         let pat = [u8x16::new(
             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
         )];
         for off in 0..16 {
-            let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8));
+            let v = u8x16::from(unsafe { vec_lde(off, pat.as_ptr() as *const u8) });
             assert_eq!(off as u8, v.extract_dyn(off as _));
         }
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_lde_u16() {
+    fn test_vec_lde_u16() {
         let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)];
         for off in 0..8 {
-            let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16));
+            let v = u16x8::from(unsafe { vec_lde(off * 2, pat.as_ptr() as *const u16) });
             assert_eq!(off as u16, v.extract_dyn(off as _));
         }
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_lde_u32() {
+    fn test_vec_lde_u32() {
         let pat = [u32x4::new(0, 1, 2, 3)];
         for off in 0..4 {
-            let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32));
+            let v = u32x4::from(unsafe { vec_lde(off * 4, pat.as_ptr() as *const u32) });
             assert_eq!(off as u32, v.extract_dyn(off as _));
         }
     }
@@ -5818,9 +5868,9 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_cmpb() {
-        let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
-        let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9));
+    fn test_vec_cmpb() {
+        let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9));
+        let b = vector_float::from(f32x4::new(-0.1, 0.5, -0.6, 0.9));
         let d = i32x4::new(
             -0b10000000000000000000000000000000,
             0,
@@ -5828,15 +5878,15 @@ mod tests {
             0,
         );
 
-        assert_eq!(d, transmute(vec_cmpb(a, b)));
+        assert_eq!(d, i32x4::from(unsafe { vec_cmpb(a, b) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_ceil() {
-        let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
+    fn test_vec_ceil() {
+        let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9));
         let d = f32x4::new(1.0, 1.0, 1.0, 1.0);
 
-        assert_eq!(d, transmute(vec_ceil(a)));
+        assert_eq!(d, f32x4::from(unsafe { vec_ceil(a) }));
     }
 
     test_vec_2! { test_vec_andc, vec_andc, i32x4,
@@ -5926,11 +5976,11 @@ mod tests {
     macro_rules! test_vec_abs {
         { $name: ident, $ty: ident, $a: expr, $d: expr } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a = vec_splats($a);
-                let a: s_t_l!($ty) = vec_abs(a);
+            fn $name() {
+                let a = unsafe { vec_splats($a) };
+                let a: s_t_l!($ty) = unsafe { vec_abs(a) };
                 let d = $ty::splat($d);
-                assert_eq!(d, transmute(a));
+                assert_eq!(d, $ty::from(a));
             }
         }
     }
@@ -5943,11 +5993,11 @@ mod tests {
     macro_rules! test_vec_abss {
         { $name: ident, $ty: ident, $a: expr, $d: expr } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a = vec_splats($a);
-                let a: s_t_l!($ty) = vec_abss(a);
+            fn $name() {
+                let a = unsafe { vec_splats($a) };
+                let a: s_t_l!($ty) = unsafe { vec_abss(a) };
                 let d = $ty::splat($d);
-                assert_eq!(d, transmute(a));
+                assert_eq!(d, $ty::from(a));
             }
         }
     }
@@ -5959,10 +6009,10 @@ mod tests {
     macro_rules! test_vec_splats {
         { $name: ident, $ty: ident, $a: expr } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = vec_splats($a);
+            fn $name() {
+                let a: s_t_l!($ty) = unsafe { vec_splats($a) };
                 let d = $ty::splat($a);
-                assert_eq!(d, transmute(a));
+                assert_eq!(d, $ty::from(a));
             }
         }
     }
@@ -5978,10 +6028,10 @@ mod tests {
     macro_rules! test_vec_splat {
         { $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a = $fun::<$a>();
+            fn $name() {
+                let a = unsafe { $fun::<$a>() };
                 let d = $ty::splat($b);
-                assert_eq!(d, transmute(a));
+                assert_eq!(d, $ty::from(a));
             }
         }
     }
@@ -6073,12 +6123,12 @@ mod tests {
     macro_rules! test_vec_min {
         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
-                let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+            fn $name() {
+                let a: s_t_l!($ty) = $ty::new($($a),+).into();
+                let b: s_t_l!($ty) = $ty::new($($b),+).into();
 
                 let d = $ty::new($($d),+);
-                let r : $ty = transmute(vec_min(a, b));
+                let r = $ty::from(unsafe { vec_min(a, b) });
                 assert_eq!(d, r);
             }
          }
@@ -6117,12 +6167,12 @@ mod tests {
     macro_rules! test_vec_max {
         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
-                let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+            fn $name() {
+                let a: s_t_l!($ty) = $ty::new($($a),+).into();
+                let b: s_t_l!($ty) = $ty::new($($b),+).into();
 
                 let d = $ty::new($($d),+);
-                let r : $ty = transmute(vec_max(a, b));
+                let r = $ty::from(unsafe { vec_max(a, b) });
                 assert_eq!(d, r);
             }
          }
@@ -6163,13 +6213,13 @@ mod tests {
          $shorttype:ident, $longtype:ident,
          [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: $longtype = transmute($shorttype::new($($a),+));
-                let b: $longtype = transmute($shorttype::new($($b),+));
-                let c: vector_unsigned_char = transmute(u8x16::new($($c),+));
+            fn $name() {
+                let a = $longtype::from($shorttype::new($($a),+));
+                let b = $longtype::from($shorttype::new($($b),+));
+                let c = vector_unsigned_char::from(u8x16::new($($c),+));
                 let d = $shorttype::new($($d),+);
 
-                let r: $shorttype = transmute(vec_perm(a, b, c));
+                let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
                 assert_eq!(d, r);
             }
         }
@@ -6249,8 +6299,8 @@ mod tests {
     [0.0, 1.0, 1.0, 1.1]}
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_madds() {
-        let a: vector_signed_short = transmute(i16x8::new(
+    fn test_vec_madds() {
+        let a = vector_signed_short::from(i16x8::new(
             0 * 256,
             1 * 256,
             2 * 256,
@@ -6260,19 +6310,19 @@ mod tests {
             6 * 256,
             7 * 256,
         ));
-        let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
-        let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+        let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
 
         let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21);
 
-        assert_eq!(d, transmute(vec_madds(a, b, c)));
+        assert_eq!(d, i16x8::from(unsafe { vec_madds(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_madd_float() {
-        let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
-        let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
-        let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+    fn test_vec_madd_float() {
+        let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
+        let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
+        let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
         let d = f32x4::new(
             0.1 * 0.1 + 0.1,
             0.2 * 0.2 + 0.2,
@@ -6280,26 +6330,26 @@ mod tests {
             0.4 * 0.4 + 0.4,
         );
 
-        assert_eq!(d, transmute(vec_madd(a, b, c)));
+        assert_eq!(d, f32x4::from(unsafe { vec_madd(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_nmsub_float() {
-        let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
-        let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
-        let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+    fn test_vec_nmsub_float() {
+        let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
+        let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
+        let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
         let d = f32x4::new(
             -(0.1 * 0.1 - 0.1),
             -(0.2 * 0.2 - 0.2),
             -(0.3 * 0.3 - 0.3),
             -(0.4 * 0.4 - 0.4),
         );
-        assert_eq!(d, transmute(vec_nmsub(a, b, c)));
+        assert_eq!(d, f32x4::from(unsafe { vec_nmsub(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mradds() {
-        let a: vector_signed_short = transmute(i16x8::new(
+    fn test_vec_mradds() {
+        let a = vector_signed_short::from(i16x8::new(
             0 * 256,
             1 * 256,
             2 * 256,
@@ -6309,25 +6359,25 @@ mod tests {
             6 * 256,
             7 * 256,
         ));
-        let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
-        let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
+        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+        let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
 
         let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX);
 
-        assert_eq!(d, transmute(vec_mradds(a, b, c)));
+        assert_eq!(d, i16x8::from(unsafe { vec_mradds(a, b, c) }));
     }
 
     macro_rules! test_vec_mladd {
         {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident,
             [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "altivec")]
-            unsafe fn $name() {
-                let a: $la = transmute($sa::new($($a),+));
-                let b: $lbc = transmute($sbc::new($($b),+));
-                let c = transmute($sbc::new($($c),+));
+            fn $name() {
+                let a = $la::from($sa::new($($a),+));
+                let b = $lbc::from($sbc::new($($b),+));
+                let c = $sbc::new($($c),+).into();
                 let d = $sd::new($($d),+);
 
-                assert_eq!(d, transmute(vec_mladd(a, b, c)));
+                assert_eq!(d, $sd::from(unsafe { vec_mladd(a, b, c) }));
             }
         }
     }
@@ -6335,24 +6385,24 @@ mod tests {
     test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8,
         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
     }
-    test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8,
+    test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_signed_short, i16x8,
         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
     }
     test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8,
         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
     }
-    test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8,
+    test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_signed_short, i16x8,
         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_msum_unsigned_char() {
-        let a: vector_unsigned_char =
-            transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
-        let b: vector_unsigned_char = transmute(u8x16::new(
+    fn test_vec_msum_unsigned_char() {
+        let a =
+            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+        let b = vector_unsigned_char::from(u8x16::new(
             255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
         ));
-        let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+        let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
         let d = u32x4::new(
             (0 + 1 + 2 + 3) * 255 + 0,
             (4 + 5 + 6 + 7) * 255 + 1,
@@ -6360,17 +6410,17 @@ mod tests {
             (4 + 5 + 6 + 7) * 255 + 3,
         );
 
-        assert_eq!(d, transmute(vec_msum(a, b, c)));
+        assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_msum_signed_char() {
-        let a: vector_signed_char = transmute(i8x16::new(
+    fn test_vec_msum_signed_char() {
+        let a = vector_signed_char::from(i8x16::new(
             0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7,
         ));
-        let b: vector_unsigned_char =
-            transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
-        let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3));
+        let b =
+            vector_unsigned_char::from(u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
+        let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
         let d = i32x4::new(
             (0 - 1 + 2 - 3) + 0,
             (0) + 1,
@@ -6378,11 +6428,12 @@ mod tests {
             (4 - 5 - 6 - 7) + 3,
         );
 
-        assert_eq!(d, transmute(vec_msum(a, b, c)));
+        assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) }));
     }
+
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_msum_unsigned_short() {
-        let a: vector_unsigned_short = transmute(u16x8::new(
+    fn test_vec_msum_unsigned_short() {
+        let a = vector_unsigned_short::from(u16x8::new(
             0 * 256,
             1 * 256,
             2 * 256,
@@ -6392,9 +6443,8 @@ mod tests {
             6 * 256,
             7 * 256,
         ));
-        let b: vector_unsigned_short =
-            transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
-        let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+        let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+        let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
         let d = u32x4::new(
             (0 + 1) * 256 * 256 + 0,
             (2 + 3) * 256 * 256 + 1,
@@ -6402,12 +6452,12 @@ mod tests {
             (6 + 7) * 256 * 256 + 3,
         );
 
-        assert_eq!(d, transmute(vec_msum(a, b, c)));
+        assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_msum_signed_short() {
-        let a: vector_signed_short = transmute(i16x8::new(
+    fn test_vec_msum_signed_short() {
+        let a = vector_signed_short::from(i16x8::new(
             0 * 256,
             -1 * 256,
             2 * 256,
@@ -6417,8 +6467,8 @@ mod tests {
             6 * 256,
             -7 * 256,
         ));
-        let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
-        let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+        let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
         let d = i32x4::new(
             (0 - 1) * 256 * 256 + 0,
             (2 - 3) * 256 * 256 + 1,
@@ -6426,12 +6476,12 @@ mod tests {
             (6 - 7) * 256 * 256 + 3,
         );
 
-        assert_eq!(d, transmute(vec_msum(a, b, c)));
+        assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_msums_unsigned() {
-        let a: vector_unsigned_short = transmute(u16x8::new(
+    fn test_vec_msums_unsigned() {
+        let a = vector_unsigned_short::from(u16x8::new(
             0 * 256,
             1 * 256,
             2 * 256,
@@ -6441,9 +6491,8 @@ mod tests {
             6 * 256,
             7 * 256,
         ));
-        let b: vector_unsigned_short =
-            transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
-        let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+        let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+        let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
         let d = u32x4::new(
             (0 + 1) * 256 * 256 + 0,
             (2 + 3) * 256 * 256 + 1,
@@ -6451,12 +6500,12 @@ mod tests {
             (6 + 7) * 256 * 256 + 3,
         );
 
-        assert_eq!(d, transmute(vec_msums(a, b, c)));
+        assert_eq!(d, u32x4::from(unsafe { vec_msums(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_msums_signed() {
-        let a: vector_signed_short = transmute(i16x8::new(
+    fn test_vec_msums_signed() {
+        let a = vector_signed_short::from(i16x8::new(
             0 * 256,
             -1 * 256,
             2 * 256,
@@ -6466,8 +6515,8 @@ mod tests {
             6 * 256,
             -7 * 256,
         ));
-        let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
-        let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+        let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
         let d = i32x4::new(
             (0 - 1) * 256 * 256 + 0,
             (2 - 3) * 256 * 256 + 1,
@@ -6475,23 +6524,23 @@ mod tests {
             (6 - 7) * 256 * 256 + 3,
         );
 
-        assert_eq!(d, transmute(vec_msums(a, b, c)));
+        assert_eq!(d, i32x4::from(unsafe { vec_msums(a, b, c) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_sum2s() {
-        let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
-        let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+    fn test_vec_sum2s() {
+        let a = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
+        let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
         let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3);
 
-        assert_eq!(d, transmute(vec_sum2s(a, b)));
+        assert_eq!(d, i32x4::from(unsafe { vec_sum2s(a, b) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_sum4s_unsigned_char() {
-        let a: vector_unsigned_char =
-            transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
-        let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+    fn test_vec_sum4s_unsigned_char() {
+        let a =
+            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+        let b = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
         let d = u32x4::new(
             0 + 1 + 2 + 3 + 0,
             4 + 5 + 6 + 7 + 1,
@@ -6499,13 +6548,13 @@ mod tests {
             4 + 5 + 6 + 7 + 3,
         );
 
-        assert_eq!(d, transmute(vec_sum4s(a, b)));
+        assert_eq!(d, u32x4::from(unsafe { vec_sum4s(a, b) }));
     }
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_sum4s_signed_char() {
-        let a: vector_signed_char =
-            transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
-        let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+    fn test_vec_sum4s_signed_char() {
+        let a =
+            vector_signed_char::from(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+        let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
         let d = i32x4::new(
             0 + 1 + 2 + 3 + 0,
             4 + 5 + 6 + 7 + 1,
@@ -6513,109 +6562,110 @@ mod tests {
             4 + 5 + 6 + 7 + 3,
         );
 
-        assert_eq!(d, transmute(vec_sum4s(a, b)));
+        assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) }));
     }
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_sum4s_signed_short() {
-        let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
-        let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+    fn test_vec_sum4s_signed_short() {
+        let a = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+        let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
         let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3);
 
-        assert_eq!(d, transmute(vec_sum4s(a, b)));
+        assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mule_unsigned_char() {
-        let a: vector_unsigned_char =
-            transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+    fn test_vec_mule_unsigned_char() {
+        let a =
+            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
         let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
 
-        assert_eq!(d, transmute(vec_mule(a, a)));
+        assert_eq!(d, u16x8::from(unsafe { vec_mule(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mule_signed_char() {
-        let a: vector_signed_char = transmute(i8x16::new(
+    fn test_vec_mule_signed_char() {
+        let a = vector_signed_char::from(i8x16::new(
             0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
         ));
         let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
 
-        assert_eq!(d, transmute(vec_mule(a, a)));
+        assert_eq!(d, i16x8::from(unsafe { vec_mule(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mule_unsigned_short() {
-        let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+    fn test_vec_mule_unsigned_short() {
+        let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
         let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
 
-        assert_eq!(d, transmute(vec_mule(a, a)));
+        assert_eq!(d, u32x4::from(unsafe { vec_mule(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mule_signed_short() {
-        let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
+    fn test_vec_mule_signed_short() {
+        let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
         let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
 
-        assert_eq!(d, transmute(vec_mule(a, a)));
+        assert_eq!(d, i32x4::from(unsafe { vec_mule(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mulo_unsigned_char() {
-        let a: vector_unsigned_char =
-            transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+    fn test_vec_mulo_unsigned_char() {
+        let a =
+            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
         let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
 
-        assert_eq!(d, transmute(vec_mulo(a, a)));
+        assert_eq!(d, u16x8::from(unsafe { vec_mulo(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mulo_signed_char() {
-        let a: vector_signed_char = transmute(i8x16::new(
+    fn test_vec_mulo_signed_char() {
+        let a = vector_signed_char::from(i8x16::new(
             0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
         ));
         let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
 
-        assert_eq!(d, transmute(vec_mulo(a, a)));
+        assert_eq!(d, i16x8::from(unsafe { vec_mulo(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mulo_unsigned_short() {
-        let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+    fn test_vec_mulo_unsigned_short() {
+        let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
         let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
 
-        assert_eq!(d, transmute(vec_mulo(a, a)));
+        assert_eq!(d, u32x4::from(unsafe { vec_mulo(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_mulo_signed_short() {
-        let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
+    fn test_vec_mulo_signed_short() {
+        let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
         let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
 
-        assert_eq!(d, transmute(vec_mulo(a, a)));
+        assert_eq!(d, i32x4::from(unsafe { vec_mulo(a, a) }));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn vec_add_i32x4_i32x4() {
+    fn vec_add_i32x4_i32x4() {
         let x = i32x4::new(1, 2, 3, 4);
         let y = i32x4::new(4, 3, 2, 1);
-        let x: vector_signed_int = transmute(x);
-        let y: vector_signed_int = transmute(y);
-        let z = vec_add(x, y);
-        assert_eq!(i32x4::splat(5), transmute(z));
+        let x = vector_signed_int::from(x);
+        let y = vector_signed_int::from(y);
+        let z = unsafe { vec_add(x, y) };
+        assert_eq!(i32x4::splat(5), i32x4::from(z));
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn vec_ctf_u32() {
-        let v: vector_unsigned_int = transmute(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42));
-        let v2 = vec_ctf::<1, _>(v);
-        let r2: vector_float = transmute(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0));
-        let v4 = vec_ctf::<2, _>(v);
-        let r4: vector_float = transmute(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5));
-        let v8 = vec_ctf::<3, _>(v);
-        let r8: vector_float = transmute(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25));
+    fn vec_ctf_u32() {
+        let v = vector_unsigned_int::from(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42));
+        let v2 = unsafe { vec_ctf::<1, _>(v) };
+        let r2 = vector_float::from(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0));
+        let v4 = unsafe { vec_ctf::<2, _>(v) };
+        let r4 = vector_float::from(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5));
+        let v8 = unsafe { vec_ctf::<3, _>(v) };
+        let r8 = vector_float::from(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25));
 
         let check = |a, b| {
-            let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)));
+            let r =
+                m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
             let e = m32x4::new(true, true, true, true);
             assert_eq!(e, r);
         };
@@ -6626,26 +6676,32 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_ctu() {
+    fn test_vec_ctu() {
         let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42);
-        let v2: u32x4 = transmute(vec_ctu::<1>(transmute(f32x4::new(
-            0.0,
-            2147483600.0,
-            2147483600.0,
-            21.0,
-        ))));
-        let v4: u32x4 = transmute(vec_ctu::<2>(transmute(f32x4::new(
-            0.0,
-            1073741800.0,
-            1073741800.0,
-            10.5,
-        ))));
-        let v8: u32x4 = transmute(vec_ctu::<3>(transmute(f32x4::new(
-            0.0,
-            536870900.0,
-            536870900.0,
-            5.25,
-        ))));
+        let v2 = u32x4::from(unsafe {
+            vec_ctu::<1>(vector_float::from(f32x4::new(
+                0.0,
+                2147483600.0,
+                2147483600.0,
+                21.0,
+            )))
+        });
+        let v4 = u32x4::from(unsafe {
+            vec_ctu::<2>(vector_float::from(f32x4::new(
+                0.0,
+                1073741800.0,
+                1073741800.0,
+                10.5,
+            )))
+        });
+        let v8 = u32x4::from(unsafe {
+            vec_ctu::<3>(vector_float::from(f32x4::new(
+                0.0,
+                536870900.0,
+                536870900.0,
+                5.25,
+            )))
+        });
 
         assert_eq!(v2, v);
         assert_eq!(v4, v);
@@ -6653,18 +6709,18 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn vec_ctf_i32() {
-        let v: vector_signed_int = transmute(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42));
-        let v2 = vec_ctf::<1, _>(v);
-        let r2: vector_float =
-            transmute(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0));
-        let v4 = vec_ctf::<2, _>(v);
-        let r4: vector_float = transmute(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5));
-        let v8 = vec_ctf::<3, _>(v);
-        let r8: vector_float = transmute(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25));
+    fn vec_ctf_i32() {
+        let v = vector_signed_int::from(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42));
+        let v2 = unsafe { vec_ctf::<1, _>(v) };
+        let r2 = vector_float::from(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0));
+        let v4 = unsafe { vec_ctf::<2, _>(v) };
+        let r4 = vector_float::from(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5));
+        let v8 = unsafe { vec_ctf::<3, _>(v) };
+        let r8 = vector_float::from(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25));
 
         let check = |a, b| {
-            let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)));
+            let r =
+                m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
             println!("{:?} {:?}", a, b);
             let e = m32x4::new(true, true, true, true);
             assert_eq!(e, r);
@@ -6676,26 +6732,32 @@ mod tests {
     }
 
     #[simd_test(enable = "altivec")]
-    unsafe fn test_vec_cts() {
+    fn test_vec_cts() {
         let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42);
-        let v2: i32x4 = transmute(vec_cts::<1>(transmute(f32x4::new(
-            -1073741800.0,
-            1073741800.0,
-            1073741800.0,
-            21.0,
-        ))));
-        let v4: i32x4 = transmute(vec_cts::<2>(transmute(f32x4::new(
-            -536870900.0,
-            536870900.0,
-            536870900.0,
-            10.5,
-        ))));
-        let v8: i32x4 = transmute(vec_cts::<3>(transmute(f32x4::new(
-            -268435460.0,
-            268435460.0,
-            268435460.0,
-            5.25,
-        ))));
+        let v2 = i32x4::from(unsafe {
+            vec_cts::<1>(transmute(f32x4::new(
+                -1073741800.0,
+                1073741800.0,
+                1073741800.0,
+                21.0,
+            )))
+        });
+        let v4 = i32x4::from(unsafe {
+            vec_cts::<2>(transmute(f32x4::new(
+                -536870900.0,
+                536870900.0,
+                536870900.0,
+                10.5,
+            )))
+        });
+        let v8 = i32x4::from(unsafe {
+            vec_cts::<3>(transmute(f32x4::new(
+                -268435460.0,
+                268435460.0,
+                268435460.0,
+                5.25,
+            )))
+        });
 
         assert_eq!(v2, v);
         assert_eq!(v4, v);
diff --git a/crates/core_arch/src/powerpc/vsx.rs b/crates/core_arch/src/powerpc/vsx.rs
index ca9fcaabe8..0aac236173 100644
--- a/crates/core_arch/src/powerpc/vsx.rs
+++ b/crates/core_arch/src/powerpc/vsx.rs
@@ -9,6 +9,7 @@
 #![allow(non_camel_case_types)]
 
 use crate::core_arch::powerpc::*;
+use crate::core_arch::simd::*;
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
@@ -34,6 +35,22 @@ types! {
     // pub struct vector_unsigned___int128 = i128x1;
 }
 
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<m64x2> for vector_bool_long {
+    #[inline]
+    fn from(value: m64x2) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+impl From<vector_bool_long> for m64x2 {
+    #[inline]
+    fn from(value: vector_bool_long) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
 #[allow(improper_ctypes)]
 unsafe extern "C" {
     #[link_name = "llvm.ppc.altivec.vperm"]
@@ -46,7 +63,6 @@ unsafe extern "C" {
 
 mod sealed {
     use super::*;
-    use crate::core_arch::simd::*;
 
     #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorPermDI {
@@ -221,14 +237,16 @@ mod tests {
     macro_rules! test_vec_xxpermdi {
         {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "vsx")]
-            unsafe fn $name() {
-                let a: $longtype = transmute($shorttype::new($($a),+, $($b),+));
-                let b = transmute($shorttype::new($($c),+, $($d),+));
-
-                assert_eq!($shorttype::new($($a),+, $($c),+), transmute(vec_xxpermdi::<_, 0>(a, b)));
-                assert_eq!($shorttype::new($($b),+, $($c),+), transmute(vec_xxpermdi::<_, 1>(a, b)));
-                assert_eq!($shorttype::new($($a),+, $($d),+), transmute(vec_xxpermdi::<_, 2>(a, b)));
-                assert_eq!($shorttype::new($($b),+, $($d),+), transmute(vec_xxpermdi::<_, 3>(a, b)));
+            fn $name() {
+                let a = $longtype::from($shorttype::new($($a),+, $($b),+));
+                let b = $longtype::from($shorttype::new($($c),+, $($d),+));
+
+                unsafe {
+                    assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b)));
+                    assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b)));
+                    assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b)));
+                    assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b)));
+                }
             }
         }
     }
diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index e1f841030c..346cd674df 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -51,6 +51,54 @@ types! {
     pub struct vector_double(2 x f64);
 }
 
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+impl From<m8x16> for vector_bool_char {
+    #[inline]
+    fn from(value: m8x16) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+impl From<vector_bool_char> for m8x16 {
+    #[inline]
+    fn from(value: vector_bool_char) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+impl From<m16x8> for vector_bool_short {
+    #[inline]
+    fn from(value: m16x8) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+impl From<vector_bool_short> for m16x8 {
+    #[inline]
+    fn from(value: vector_bool_short) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+impl From<m32x4> for vector_bool_int {
+    #[inline]
+    fn from(value: m32x4) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+impl From<vector_bool_int> for m32x4 {
+    #[inline]
+    fn from(value: vector_bool_int) -> Self {
+        unsafe { transmute(value) }
+    }
+}
+
 #[repr(C, packed)]
 struct PackedTuple<T, U> {
     x: T,
@@ -6051,27 +6099,16 @@ mod tests {
     }
 
     macro_rules! test_vec_1 {
-        { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
-            #[simd_test(enable = "vector")]
-            unsafe fn $name() {
-                let a: vector_float = transmute(f32x4::new($($a),+));
-
-                let d: vector_float = transmute(f32x4::new($($d),+));
-                let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)));
-                let e = m32x4::new(true, true, true, true);
-                assert_eq!(e, r);
-            }
-        };
         { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => {
             test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] }
         };
         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "vector")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
+            fn $name() {
+                let a: s_t_l!($ty) = $ty::new($($a),+).into();
 
                 let d = $ty_out::new($($d),+);
-                let r : $ty_out = transmute($fn(a));
+                let r = $ty_out::from(unsafe { $fn(a) });
                 assert_eq!(d, r);
             }
         }
@@ -6086,35 +6123,23 @@ mod tests {
          };
         { $name: ident, $fn:ident, $ty1: ident, $ty2: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "vector")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty1) = transmute($ty1::new($($a),+));
-                let b: s_t_l!($ty2) = transmute($ty2::new($($b),+));
+            fn $name() {
+                let a: s_t_l!($ty1) = $ty1::new($($a),+).into();
+                let b: s_t_l!($ty2) = $ty2::new($($b),+).into();
 
                 let d = $ty_out::new($($d),+);
-                let r : $ty_out = transmute($fn(a, b));
+                let r = $ty_out::from(unsafe { $fn(a, b) });
                 assert_eq!(d, r);
             }
          };
-         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
-            #[simd_test(enable = "vector")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = transmute($ty::new($($a),+));
-                let b: s_t_l!($ty) = transmute($ty::new($($b),+));
-
-                let r : $ty_out = transmute($fn(a, b));
-                assert_eq!($d, r);
-            }
-         }
    }
 
     #[simd_test(enable = "vector")]
-    unsafe fn vec_add_i32x4_i32x4() {
-        let x = i32x4::new(1, 2, 3, 4);
-        let y = i32x4::new(4, 3, 2, 1);
-        let x: vector_signed_int = transmute(x);
-        let y: vector_signed_int = transmute(y);
-        let z = vec_add(x, y);
-        assert_eq!(i32x4::splat(5), transmute(z));
+    fn vec_add_i32x4_i32x4() {
+        let x = vector_signed_int::from(i32x4::new(1, 2, 3, 4));
+        let y = vector_signed_int::from(i32x4::new(4, 3, 2, 1));
+        let z = unsafe { vec_add(x, y) };
+        assert_eq!(i32x4::splat(5), i32x4::from(z));
     }
 
     macro_rules! test_vec_sub {
@@ -6232,11 +6257,11 @@ mod tests {
     macro_rules! test_vec_abs {
         { $name: ident, $ty: ident, $a: expr, $d: expr } => {
             #[simd_test(enable = "vector")]
-            unsafe fn $name() {
-                let a: s_t_l!($ty) = vec_splats($a);
-                let a: s_t_l!($ty) = vec_abs(a);
+            fn $name() {
+                let a: s_t_l!($ty) = unsafe { vec_splats($a) };
+                let a: s_t_l!($ty) = unsafe { vec_abs(a) };
                 let d = $ty::splat($d);
-                assert_eq!(d, transmute(a));
+                assert_eq!(d, $ty::from(a));
             }
         }
     }
@@ -6386,7 +6411,7 @@ mod tests {
     [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16],
     [4, 2, 1, 8] }
 
-    test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> i32x4,
+    test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> u32x4,
     [0b1000, 0b1000, 0b1000, 0b1000],
     [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16],
     [4, 2, 1, 8] }
@@ -6423,13 +6448,13 @@ mod tests {
          $shorttype:ident, $longtype:ident,
          [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "vector")]
-            unsafe fn $name() {
-                let a: $longtype = transmute($shorttype::new($($a),+));
-                let b: $longtype = transmute($shorttype::new($($b),+));
-                let c: vector_unsigned_char = transmute(u8x16::new($($c),+));
+            fn $name() {
+                let a = $longtype::from($shorttype::new($($a),+));
+                let b = $longtype::from($shorttype::new($($b),+));
+                let c = vector_unsigned_char::from(u8x16::new($($c),+));
                 let d = $shorttype::new($($d),+);
 
-                let r: $shorttype = transmute(vec_perm(a, b, c));
+                let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
                 assert_eq!(d, r);
             }
         }
@@ -6512,46 +6537,46 @@ mod tests {
     [core::f32::consts::PI, 1.0, 25.0, 2.0],
     [core::f32::consts::PI.sqrt(), 1.0, 5.0, core::f32::consts::SQRT_2] }
 
-    test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> i32x4,
         [1, -2, 3, -4],
         [-5, 3, -7, 8],
-        [0, 0, 0xFFFFFFFF, 0]
+        [0, 0, !0, 0]
     }
 
-    test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> i32x4,
         [1, -2, 3, -4],
         [-5, 3, -7, 8],
-        [0xFFFFFFFF, 0xFFFFFFFF, 0, 0xFFFFFFFF]
+        [!0, !0, 0, !0]
     }
 
-    test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4,
         [1, 2, 3, 4],
         [5, 3, 7, 8],
         [0, 8, 0, 0]
     }
-    test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4,
         [1, 2, 3, 4],
         [5, 6, 7, 8],
         [0, 16, 0, 0]
     }
 
-    test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4,
         [1, 2, 3, 4],
         [1, 5, 3, 4],
         [0, 4, 0, 0]
     }
-    test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4,
         [1, 2, 3, 4],
         [1, 2, 3, 4],
         [0, 16, 0, 0]
     }
 
-    test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> i32x4,
         [1, 2, 0, 4],
         [5, 6, 7, 8],
         [0, 8, 0, 0]
     }
-    test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> u32x4,
+    test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> i32x4,
         [1, 2, 0, 4],
         [1, 2, 3, 4],
         [0, 8, 0, 0]

From 04cdf31f744a1e48a10af649fae13dc6b9ed193c Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Thu, 29 Jan 2026 10:34:44 +0100
Subject: [PATCH 113/326] Don't expect specific instructions for
 _mm256_set_pd/_mm_set_ps

These don't correspond to specific instructions and will produce
different instructions on x86/x86_64 based on ABI details.
---
 crates/core_arch/src/x86/avx.rs | 1 -
 crates/core_arch/src/x86/sse.rs | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index 7b4b210bac..74fc2db13d 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -2426,7 +2426,6 @@ pub const fn _mm256_setzero_si256() -> __m256i {
 #[inline]
 #[target_feature(enable = "avx")]
 // This intrinsic has no corresponding instruction.
-#[cfg_attr(test, assert_instr(vinsertf128))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index b83274e60e..2c4439a3f3 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -968,7 +968,7 @@ pub const fn _mm_set_ps1(a: f32) -> __m128 {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_ps)
 #[inline]
 #[target_feature(enable = "sse")]
-#[cfg_attr(test, assert_instr(unpcklps))]
+// This intrinsic has no corresponding instruction.
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {

From 5c59176b6ebb98125f69b1b14eb2fb786c0291ab Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Thu, 29 Jan 2026 11:07:06 +0100
Subject: [PATCH 114/326] Ignore non-yml files in generator

Otherwise this picks up vim .swp files.
---
 crates/stdarch-gen-arm/src/main.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/crates/stdarch-gen-arm/src/main.rs b/crates/stdarch-gen-arm/src/main.rs
index 9bf7d0981d..e14e278248 100644
--- a/crates/stdarch-gen-arm/src/main.rs
+++ b/crates/stdarch-gen-arm/src/main.rs
@@ -139,6 +139,7 @@ fn parse_args() -> Vec<(PathBuf, Option<PathBuf>)> {
         .into_iter()
         .filter_map(Result::ok)
         .filter(|f| f.file_type().is_file())
+        .filter(|f| f.file_name().to_string_lossy().ends_with(".yml"))
         .map(|f| (f.into_path(), out_dir.clone()))
         .collect()
 }

From 491d46e8bf2c470466b5ac10b3300a1542c0ab39 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Thu, 29 Jan 2026 11:21:11 +0100
Subject: [PATCH 115/326] Change lanes vcopy_lane tests to avoid zip2

---
 .../core_arch/src/aarch64/neon/generated.rs   | 78 +++++++++----------
 .../spec/neon/aarch64.spec.yml                |  8 +-
 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 9507b71106..3d5d07ac1b 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4092,7 +4092,7 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
@@ -4113,7 +4113,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
@@ -4137,7 +4137,7 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
@@ -4157,7 +4157,7 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
@@ -4175,7 +4175,7 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
@@ -4199,7 +4199,7 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
@@ -4222,7 +4222,7 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
@@ -4243,7 +4243,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
@@ -4267,7 +4267,7 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
@@ -4290,7 +4290,7 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
@@ -4312,7 +4312,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
@@ -4338,7 +4338,7 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
@@ -4362,7 +4362,7 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
@@ -4384,7 +4384,7 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
@@ -4413,7 +4413,7 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
@@ -4437,7 +4437,7 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
@@ -4459,7 +4459,7 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
@@ -4488,7 +4488,7 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
@@ -4624,7 +4624,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
@@ -4994,7 +4994,7 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
@@ -5022,7 +5022,7 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
@@ -5046,7 +5046,7 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
@@ -5419,7 +5419,7 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
@@ -5447,7 +5447,7 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
@@ -5471,7 +5471,7 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
@@ -5844,7 +5844,7 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
@@ -5872,7 +5872,7 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
@@ -5895,7 +5895,7 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
@@ -5916,7 +5916,7 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
@@ -6287,7 +6287,7 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
@@ -6314,7 +6314,7 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
@@ -6337,7 +6337,7 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
@@ -6358,7 +6358,7 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
@@ -6729,7 +6729,7 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
@@ -6756,7 +6756,7 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
@@ -6779,7 +6779,7 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
@@ -6800,7 +6800,7 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
@@ -7171,7 +7171,7 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
@@ -7198,7 +7198,7 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
+#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a9bc377924..a099c2c8d6 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -8958,7 +8958,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -8983,7 +8983,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9008,7 +9008,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9037,7 +9037,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     static_defs: ['const LANE1: i32, const LANE2: i32']

From d36f78a5a311ead2d4fe3c666abda43e708241a1 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Thu, 29 Jan 2026 11:28:32 +0100
Subject: [PATCH 116/326] Adjust expected output for vrfin

It actually generates vrfin now
---
 crates/core_arch/src/powerpc/altivec.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index fb1a9d8ed9..0e238c5325 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -3249,7 +3249,7 @@ mod sealed {
         unsafe fn vec_round(self) -> Self;
     }
 
-    test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, xvrspic] }
+    test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] }
 
     #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     impl VectorRound for vector_float {

From b7aecd96006a8a9259e885e34976878b59573e26 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 31 Jan 2026 17:15:16 +0100
Subject: [PATCH 117/326] powerpc: implement `vnmsubfp` using
 `intrinsics::simd`

---
 crates/core_arch/src/powerpc/altivec.rs | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index fb1a9d8ed9..9d54abc583 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -129,8 +129,6 @@ unsafe extern "C" {
         b: vector_signed_short,
         c: vector_signed_int,
     ) -> vector_signed_int;
-    #[link_name = "llvm.ppc.altivec.vnmsubfp"]
-    fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float;
     #[link_name = "llvm.ppc.altivec.vsum2sws"]
     fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
     #[link_name = "llvm.ppc.altivec.vsum4ubs"]
@@ -1881,9 +1879,9 @@ mod sealed {
 
     #[inline]
     #[target_feature(enable = "altivec")]
-    #[cfg_attr(test, assert_instr(vnmsubfp))]
-    unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
-        vnmsubfp(a, b, c)
+    #[cfg_attr(test, assert_instr(xvnmsubasp))]
+    pub unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
+        simd_neg(simd_fma(a, b, simd_neg(c)))
     }
 
     #[inline]
@@ -4281,7 +4279,7 @@ pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vec
 #[target_feature(enable = "altivec")]
 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
-    vnmsubfp(a, b, c)
+    sealed::vec_vnmsubfp(a, b, c)
 }
 
 /// Vector Select

From 982e2131ac53f7118af112b96076cec7c0fa9888 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 31 Jan 2026 18:47:56 +0100
Subject: [PATCH 118/326] wasm: use `intrinsics::simd` for the narrow functions

---
 crates/core_arch/src/wasm32/simd128.rs | 72 +++++++++++++++++++++-----
 1 file changed, 60 insertions(+), 12 deletions(-)

diff --git a/crates/core_arch/src/wasm32/simd128.rs b/crates/core_arch/src/wasm32/simd128.rs
index c864d6a516..e1a3754965 100644
--- a/crates/core_arch/src/wasm32/simd128.rs
+++ b/crates/core_arch/src/wasm32/simd128.rs
@@ -86,10 +86,6 @@ unsafe extern "unadjusted" {
     fn llvm_i8x16_all_true(x: simd::i8x16) -> i32;
     #[link_name = "llvm.wasm.bitmask.v16i8"]
     fn llvm_bitmask_i8x16(a: simd::i8x16) -> i32;
-    #[link_name = "llvm.wasm.narrow.signed.v16i8.v8i16"]
-    fn llvm_narrow_i8x16_s(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16;
-    #[link_name = "llvm.wasm.narrow.unsigned.v16i8.v8i16"]
-    fn llvm_narrow_i8x16_u(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16;
     #[link_name = "llvm.wasm.avgr.unsigned.v16i8"]
     fn llvm_avgr_u_i8x16(a: simd::i8x16, b: simd::i8x16) -> simd::i8x16;
 
@@ -103,10 +99,6 @@ unsafe extern "unadjusted" {
     fn llvm_i16x8_all_true(x: simd::i16x8) -> i32;
     #[link_name = "llvm.wasm.bitmask.v8i16"]
     fn llvm_bitmask_i16x8(a: simd::i16x8) -> i32;
-    #[link_name = "llvm.wasm.narrow.signed.v8i16.v4i32"]
-    fn llvm_narrow_i16x8_s(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8;
-    #[link_name = "llvm.wasm.narrow.unsigned.v8i16.v4i32"]
-    fn llvm_narrow_i16x8_u(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8;
     #[link_name = "llvm.wasm.avgr.unsigned.v8i16"]
     fn llvm_avgr_u_i16x8(a: simd::i16x8, b: simd::i16x8) -> simd::i16x8;
 
@@ -2281,7 +2273,23 @@ pub use i8x16_bitmask as u8x16_bitmask;
 #[doc(alias("i8x16.narrow_i16x8_s"))]
 #[stable(feature = "wasm_simd", since = "1.54.0")]
 pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 {
-    unsafe { llvm_narrow_i8x16_s(a.as_i16x8(), b.as_i16x8()).v128() }
+    unsafe {
+        let v: simd::i16x16 = simd_shuffle!(
+            a.as_i16x8(),
+            b.as_i16x8(),
+            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
+        );
+
+        let max = simd_splat(i16::from(i8::MAX));
+        let min = simd_splat(i16::from(i8::MIN));
+
+        let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v);
+        let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v);
+
+        let v: simd::i8x16 = simd_cast(v);
+
+        v.v128()
+    }
 }
 
 /// Converts two input vectors into a smaller lane vector by narrowing each
@@ -2295,7 +2303,23 @@ pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 {
 #[doc(alias("i8x16.narrow_i16x8_u"))]
 #[stable(feature = "wasm_simd", since = "1.54.0")]
 pub fn u8x16_narrow_i16x8(a: v128, b: v128) -> v128 {
-    unsafe { llvm_narrow_i8x16_u(a.as_i16x8(), b.as_i16x8()).v128() }
+    unsafe {
+        let v: simd::i16x16 = simd_shuffle!(
+            a.as_i16x8(),
+            b.as_i16x8(),
+            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
+        );
+
+        let max = simd_splat(i16::from(u8::MAX));
+        let min = simd_splat(i16::from(u8::MIN));
+
+        let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v);
+        let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v);
+
+        let v: simd::u8x16 = simd_cast(v);
+
+        v.v128()
+    }
 }
 
 /// Shifts each lane to the left by the specified number of bits.
@@ -2593,7 +2617,19 @@ pub use i16x8_bitmask as u16x8_bitmask;
 #[doc(alias("i16x8.narrow_i32x4_s"))]
 #[stable(feature = "wasm_simd", since = "1.54.0")]
 pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 {
-    unsafe { llvm_narrow_i16x8_s(a.as_i32x4(), b.as_i32x4()).v128() }
+    unsafe {
+        let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]);
+
+        let max = simd_splat(i32::from(i16::MAX));
+        let min = simd_splat(i32::from(i16::MIN));
+
+        let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v);
+        let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v);
+
+        let v: simd::i16x8 = simd_cast(v);
+
+        v.v128()
+    }
 }
 
 /// Converts two input vectors into a smaller lane vector by narrowing each
@@ -2607,7 +2643,19 @@ pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 {
 #[doc(alias("i16x8.narrow_i32x4_u"))]
 #[stable(feature = "wasm_simd", since = "1.54.0")]
 pub fn u16x8_narrow_i32x4(a: v128, b: v128) -> v128 {
-    unsafe { llvm_narrow_i16x8_u(a.as_i32x4(), b.as_i32x4()).v128() }
+    unsafe {
+        let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]);
+
+        let max = simd_splat(i32::from(u16::MAX));
+        let min = simd_splat(i32::from(u16::MIN));
+
+        let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v);
+        let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v);
+
+        let v: simd::u16x8 = simd_cast(v);
+
+        v.v128()
+    }
 }
 
 /// Converts low half of the smaller lane vector to a larger lane

From e940b04f13775f91d1288f92785a2addcb9c4428 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 31 Jan 2026 22:11:50 +0100
Subject: [PATCH 119/326] x86: use `intrinsics::simd` for `hadds`/`hsubs`

---
 crates/core_arch/src/x86/avx2.rs  | 36 +++++++++++++++++++++++++------
 crates/core_arch/src/x86/ssse3.rs | 22 ++++++++++++-------
 2 files changed, 44 insertions(+), 14 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 6a39a0aaf8..83aef753c9 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -991,7 +991,21 @@ pub const fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vphaddsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(phaddsw(a.as_i16x16(), b.as_i16x16())) }
+    let a = a.as_i16x16();
+    let b = b.as_i16x16();
+    unsafe {
+        let even: i16x16 = simd_shuffle!(
+            a,
+            b,
+            [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30]
+        );
+        let odd: i16x16 = simd_shuffle!(
+            a,
+            b,
+            [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31]
+        );
+        simd_saturating_add(even, odd).as_m256i()
+    }
 }
 
 /// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`.
@@ -1047,7 +1061,21 @@ pub const fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vphsubsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_hsubs_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(phsubsw(a.as_i16x16(), b.as_i16x16())) }
+    let a = a.as_i16x16();
+    let b = b.as_i16x16();
+    unsafe {
+        let even: i16x16 = simd_shuffle!(
+            a,
+            b,
+            [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30]
+        );
+        let odd: i16x16 = simd_shuffle!(
+            a,
+            b,
+            [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31]
+        );
+        simd_saturating_sub(even, odd).as_m256i()
+    }
 }
 
 /// Returns values from `slice` at offsets determined by `offsets * scale`,
@@ -3791,10 +3819,6 @@ pub const fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
 
 #[allow(improper_ctypes)]
 unsafe extern "C" {
-    #[link_name = "llvm.x86.avx2.phadd.sw"]
-    fn phaddsw(a: i16x16, b: i16x16) -> i16x16;
-    #[link_name = "llvm.x86.avx2.phsub.sw"]
-    fn phsubsw(a: i16x16, b: i16x16) -> i16x16;
     #[link_name = "llvm.x86.avx2.pmadd.wd"]
     fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
diff --git a/crates/core_arch/src/x86/ssse3.rs b/crates/core_arch/src/x86/ssse3.rs
index 4426a3274c..1d7a97944a 100644
--- a/crates/core_arch/src/x86/ssse3.rs
+++ b/crates/core_arch/src/x86/ssse3.rs
@@ -188,7 +188,13 @@ pub const fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(phaddsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(phaddsw128(a.as_i16x8(), b.as_i16x8())) }
+    let a = a.as_i16x8();
+    let b = b.as_i16x8();
+    unsafe {
+        let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
+        let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
+        simd_saturating_add(even, odd).as_m128i()
+    }
 }
 
 /// Horizontally adds the adjacent pairs of values contained in 2 packed
@@ -240,7 +246,13 @@ pub const fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(phsubsw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(phsubsw128(a.as_i16x8(), b.as_i16x8())) }
+    let a = a.as_i16x8();
+    let b = b.as_i16x8();
+    unsafe {
+        let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
+        let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
+        simd_saturating_sub(even, odd).as_m128i()
+    }
 }
 
 /// Horizontally subtract the adjacent pairs of values contained in 2
@@ -337,12 +349,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.ssse3.pshuf.b.128"]
     fn pshufb128(a: u8x16, b: u8x16) -> u8x16;
 
-    #[link_name = "llvm.x86.ssse3.phadd.sw.128"]
-    fn phaddsw128(a: i16x8, b: i16x8) -> i16x8;
-
-    #[link_name = "llvm.x86.ssse3.phsub.sw.128"]
-    fn phsubsw128(a: i16x8, b: i16x8) -> i16x8;
-
     #[link_name = "llvm.x86.ssse3.pmadd.ub.sw.128"]
     fn pmaddubsw128(a: u8x16, b: i8x16) -> i16x8;
 

From 111e43b77db7e974b420cbc9b14268180a9c34bb Mon Sep 17 00:00:00 2001
From: xtqqczze <45661989+xtqqczze@users.noreply.github.com>
Date: Sat, 24 Jan 2026 02:29:59 +0000
Subject: [PATCH 120/326] ci: use `macos-15-intel` runner

seems unnecessary to use `macos-15-large` just for x86_64 support
---
 .github/workflows/main.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 6cf0e9f02f..2b2f64b74b 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -101,9 +101,9 @@ jobs:
 
         # macOS targets
         - tuple: x86_64-apple-darwin
-          os: macos-15-large
+          os: macos-15-intel
         - tuple: x86_64-apple-ios-macabi
-          os: macos-15-large
+          os: macos-15-intel
         - tuple: aarch64-apple-darwin
           os: macos-15
         - tuple: aarch64-apple-ios-macabi

From 0387e997ec188205dbc21028a52897e4d4dc6701 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Fri, 30 Jan 2026 20:22:18 +0100
Subject: [PATCH 121/326] test the `vld1*` functions

---
 crates/core_arch/src/aarch64/neon/mod.rs | 864 +++++++++++++++++++++++
 1 file changed, 864 insertions(+)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index bac4574239..feaf94a7f9 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -993,6 +993,870 @@ mod tests {
         assert_eq!(vals[1], 1.);
         assert_eq!(vals[2], 2.);
     }
+
+    #[simd_test(enable = "neon,fp16")]
+    #[cfg(not(target_arch = "arm64ec"))]
+    unsafe fn test_vld1_f16_x2() {
+        let vals: [f16; 8] = crate::array::from_fn(|i| i as f16);
+        let a: float16x4x2_t = transmute(vals);
+        let mut tmp = [0_f16; 8];
+        vst1_f16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: float16x4x2_t = vld1_f16_x2(tmp.as_ptr().cast());
+        let out: [f16; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,fp16")]
+    #[cfg(not(target_arch = "arm64ec"))]
+    unsafe fn test_vld1_f16_x3() {
+        let vals: [f16; 12] = crate::array::from_fn(|i| i as f16);
+        let a: float16x4x3_t = transmute(vals);
+        let mut tmp = [0_f16; 12];
+        vst1_f16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: float16x4x3_t = vld1_f16_x3(tmp.as_ptr().cast());
+        let out: [f16; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,fp16")]
+    #[cfg(not(target_arch = "arm64ec"))]
+    unsafe fn test_vld1_f16_x4() {
+        let vals: [f16; 16] = crate::array::from_fn(|i| i as f16);
+        let a: float16x4x4_t = transmute(vals);
+        let mut tmp = [0_f16; 16];
+        vst1_f16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: float16x4x4_t = vld1_f16_x4(tmp.as_ptr().cast());
+        let out: [f16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,fp16")]
+    #[cfg(not(target_arch = "arm64ec"))]
+    unsafe fn test_vld1q_f16_x2() {
+        let vals: [f16; 16] = crate::array::from_fn(|i| i as f16);
+        let a: float16x8x2_t = transmute(vals);
+        let mut tmp = [0_f16; 16];
+        vst1q_f16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: float16x8x2_t = vld1q_f16_x2(tmp.as_ptr().cast());
+        let out: [f16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,fp16")]
+    #[cfg(not(target_arch = "arm64ec"))]
+    unsafe fn test_vld1q_f16_x3() {
+        let vals: [f16; 24] = crate::array::from_fn(|i| i as f16);
+        let a: float16x8x3_t = transmute(vals);
+        let mut tmp = [0_f16; 24];
+        vst1q_f16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: float16x8x3_t = vld1q_f16_x3(tmp.as_ptr().cast());
+        let out: [f16; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,fp16")]
+    #[cfg(not(target_arch = "arm64ec"))]
+    unsafe fn test_vld1q_f16_x4() {
+        let vals: [f16; 32] = crate::array::from_fn(|i| i as f16);
+        let a: float16x8x4_t = transmute(vals);
+        let mut tmp = [0_f16; 32];
+        vst1q_f16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: float16x8x4_t = vld1q_f16_x4(tmp.as_ptr().cast());
+        let out: [f16; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_f32_x2() {
+        let vals: [f32; 4] = crate::array::from_fn(|i| i as f32);
+        let a: float32x2x2_t = transmute(vals);
+        let mut tmp = [0_f32; 4];
+        vst1_f32_x2(tmp.as_mut_ptr().cast(), a);
+        let r: float32x2x2_t = vld1_f32_x2(tmp.as_ptr().cast());
+        let out: [f32; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_f32_x3() {
+        let vals: [f32; 6] = crate::array::from_fn(|i| i as f32);
+        let a: float32x2x3_t = transmute(vals);
+        let mut tmp = [0_f32; 6];
+        vst1_f32_x3(tmp.as_mut_ptr().cast(), a);
+        let r: float32x2x3_t = vld1_f32_x3(tmp.as_ptr().cast());
+        let out: [f32; 6] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_f32_x4() {
+        let vals: [f32; 8] = crate::array::from_fn(|i| i as f32);
+        let a: float32x2x4_t = transmute(vals);
+        let mut tmp = [0_f32; 8];
+        vst1_f32_x4(tmp.as_mut_ptr().cast(), a);
+        let r: float32x2x4_t = vld1_f32_x4(tmp.as_ptr().cast());
+        let out: [f32; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_f32_x2() {
+        let vals: [f32; 8] = crate::array::from_fn(|i| i as f32);
+        let a: float32x4x2_t = transmute(vals);
+        let mut tmp = [0_f32; 8];
+        vst1q_f32_x2(tmp.as_mut_ptr().cast(), a);
+        let r: float32x4x2_t = vld1q_f32_x2(tmp.as_ptr().cast());
+        let out: [f32; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_f32_x3() {
+        let vals: [f32; 12] = crate::array::from_fn(|i| i as f32);
+        let a: float32x4x3_t = transmute(vals);
+        let mut tmp = [0_f32; 12];
+        vst1q_f32_x3(tmp.as_mut_ptr().cast(), a);
+        let r: float32x4x3_t = vld1q_f32_x3(tmp.as_ptr().cast());
+        let out: [f32; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_f32_x4() {
+        let vals: [f32; 16] = crate::array::from_fn(|i| i as f32);
+        let a: float32x4x4_t = transmute(vals);
+        let mut tmp = [0_f32; 16];
+        vst1q_f32_x4(tmp.as_mut_ptr().cast(), a);
+        let r: float32x4x4_t = vld1q_f32_x4(tmp.as_ptr().cast());
+        let out: [f32; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,aes")]
+    unsafe fn test_vld1_p64_x2() {
+        let vals: [p64; 2] = crate::array::from_fn(|i| i as p64);
+        let a: poly64x1x2_t = transmute(vals);
+        let mut tmp = [0 as p64; 2];
+        vst1_p64_x2(tmp.as_mut_ptr().cast(), a);
+        let r: poly64x1x2_t = vld1_p64_x2(tmp.as_ptr().cast());
+        let out: [p64; 2] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,aes")]
+    unsafe fn test_vld1_p64_x3() {
+        let vals: [p64; 3] = crate::array::from_fn(|i| i as p64);
+        let a: poly64x1x3_t = transmute(vals);
+        let mut tmp = [0 as p64; 3];
+        vst1_p64_x3(tmp.as_mut_ptr().cast(), a);
+        let r: poly64x1x3_t = vld1_p64_x3(tmp.as_ptr().cast());
+        let out: [p64; 3] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,aes")]
+    unsafe fn test_vld1_p64_x4() {
+        let vals: [p64; 4] = crate::array::from_fn(|i| i as p64);
+        let a: poly64x1x4_t = transmute(vals);
+        let mut tmp = [0 as p64; 4];
+        vst1_p64_x4(tmp.as_mut_ptr().cast(), a);
+        let r: poly64x1x4_t = vld1_p64_x4(tmp.as_ptr().cast());
+        let out: [p64; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,aes")]
+    unsafe fn test_vld1q_p64_x2() {
+        let vals: [p64; 4] = crate::array::from_fn(|i| i as p64);
+        let a: poly64x2x2_t = transmute(vals);
+        let mut tmp = [0 as p64; 4];
+        vst1q_p64_x2(tmp.as_mut_ptr().cast(), a);
+        let r: poly64x2x2_t = vld1q_p64_x2(tmp.as_ptr().cast());
+        let out: [p64; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,aes")]
+    unsafe fn test_vld1q_p64_x3() {
+        let vals: [p64; 6] = crate::array::from_fn(|i| i as p64);
+        let a: poly64x2x3_t = transmute(vals);
+        let mut tmp = [0 as p64; 6];
+        vst1q_p64_x3(tmp.as_mut_ptr().cast(), a);
+        let r: poly64x2x3_t = vld1q_p64_x3(tmp.as_ptr().cast());
+        let out: [p64; 6] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon,aes")]
+    unsafe fn test_vld1q_p64_x4() {
+        let vals: [p64; 8] = crate::array::from_fn(|i| i as p64);
+        let a: poly64x2x4_t = transmute(vals);
+        let mut tmp = [0 as p64; 8];
+        vst1q_p64_x4(tmp.as_mut_ptr().cast(), a);
+        let r: poly64x2x4_t = vld1q_p64_x4(tmp.as_ptr().cast());
+        let out: [p64; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s8_x2() {
+        let vals: [i8; 16] = crate::array::from_fn(|i| i as i8);
+        let a: int8x8x2_t = transmute(vals);
+        let mut tmp = [0_i8; 16];
+        vst1_s8_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int8x8x2_t = vld1_s8_x2(tmp.as_ptr().cast());
+        let out: [i8; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s8_x3() {
+        let vals: [i8; 24] = crate::array::from_fn(|i| i as i8);
+        let a: int8x8x3_t = transmute(vals);
+        let mut tmp = [0_i8; 24];
+        vst1_s8_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int8x8x3_t = vld1_s8_x3(tmp.as_ptr().cast());
+        let out: [i8; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s8_x4() {
+        let vals: [i8; 32] = crate::array::from_fn(|i| i as i8);
+        let a: int8x8x4_t = transmute(vals);
+        let mut tmp = [0_i8; 32];
+        vst1_s8_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int8x8x4_t = vld1_s8_x4(tmp.as_ptr().cast());
+        let out: [i8; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s8_x2() {
+        let vals: [i8; 32] = crate::array::from_fn(|i| i as i8);
+        let a: int8x16x2_t = transmute(vals);
+        let mut tmp = [0_i8; 32];
+        vst1q_s8_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int8x16x2_t = vld1q_s8_x2(tmp.as_ptr().cast());
+        let out: [i8; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s8_x3() {
+        let vals: [i8; 48] = crate::array::from_fn(|i| i as i8);
+        let a: int8x16x3_t = transmute(vals);
+        let mut tmp = [0_i8; 48];
+        vst1q_s8_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int8x16x3_t = vld1q_s8_x3(tmp.as_ptr().cast());
+        let out: [i8; 48] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s8_x4() {
+        let vals: [i8; 64] = crate::array::from_fn(|i| i as i8);
+        let a: int8x16x4_t = transmute(vals);
+        let mut tmp = [0_i8; 64];
+        vst1q_s8_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int8x16x4_t = vld1q_s8_x4(tmp.as_ptr().cast());
+        let out: [i8; 64] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s16_x2() {
+        let vals: [i16; 8] = crate::array::from_fn(|i| i as i16);
+        let a: int16x4x2_t = transmute(vals);
+        let mut tmp = [0_i16; 8];
+        vst1_s16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int16x4x2_t = vld1_s16_x2(tmp.as_ptr().cast());
+        let out: [i16; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s16_x3() {
+        let vals: [i16; 12] = crate::array::from_fn(|i| i as i16);
+        let a: int16x4x3_t = transmute(vals);
+        let mut tmp = [0_i16; 12];
+        vst1_s16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int16x4x3_t = vld1_s16_x3(tmp.as_ptr().cast());
+        let out: [i16; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s16_x4() {
+        let vals: [i16; 16] = crate::array::from_fn(|i| i as i16);
+        let a: int16x4x4_t = transmute(vals);
+        let mut tmp = [0_i16; 16];
+        vst1_s16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int16x4x4_t = vld1_s16_x4(tmp.as_ptr().cast());
+        let out: [i16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s16_x2() {
+        let vals: [i16; 16] = crate::array::from_fn(|i| i as i16);
+        let a: int16x8x2_t = transmute(vals);
+        let mut tmp = [0_i16; 16];
+        vst1q_s16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int16x8x2_t = vld1q_s16_x2(tmp.as_ptr().cast());
+        let out: [i16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s16_x3() {
+        let vals: [i16; 24] = crate::array::from_fn(|i| i as i16);
+        let a: int16x8x3_t = transmute(vals);
+        let mut tmp = [0_i16; 24];
+        vst1q_s16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int16x8x3_t = vld1q_s16_x3(tmp.as_ptr().cast());
+        let out: [i16; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s16_x4() {
+        let vals: [i16; 32] = crate::array::from_fn(|i| i as i16);
+        let a: int16x8x4_t = transmute(vals);
+        let mut tmp = [0_i16; 32];
+        vst1q_s16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int16x8x4_t = vld1q_s16_x4(tmp.as_ptr().cast());
+        let out: [i16; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s32_x2() {
+        let vals: [i32; 4] = crate::array::from_fn(|i| i as i32);
+        let a: int32x2x2_t = transmute(vals);
+        let mut tmp = [0_i32; 4];
+        vst1_s32_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int32x2x2_t = vld1_s32_x2(tmp.as_ptr().cast());
+        let out: [i32; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s32_x3() {
+        let vals: [i32; 6] = crate::array::from_fn(|i| i as i32);
+        let a: int32x2x3_t = transmute(vals);
+        let mut tmp = [0_i32; 6];
+        vst1_s32_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int32x2x3_t = vld1_s32_x3(tmp.as_ptr().cast());
+        let out: [i32; 6] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s32_x4() {
+        let vals: [i32; 8] = crate::array::from_fn(|i| i as i32);
+        let a: int32x2x4_t = transmute(vals);
+        let mut tmp = [0_i32; 8];
+        vst1_s32_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int32x2x4_t = vld1_s32_x4(tmp.as_ptr().cast());
+        let out: [i32; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s32_x2() {
+        let vals: [i32; 8] = crate::array::from_fn(|i| i as i32);
+        let a: int32x4x2_t = transmute(vals);
+        let mut tmp = [0_i32; 8];
+        vst1q_s32_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int32x4x2_t = vld1q_s32_x2(tmp.as_ptr().cast());
+        let out: [i32; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s32_x3() {
+        let vals: [i32; 12] = crate::array::from_fn(|i| i as i32);
+        let a: int32x4x3_t = transmute(vals);
+        let mut tmp = [0_i32; 12];
+        vst1q_s32_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int32x4x3_t = vld1q_s32_x3(tmp.as_ptr().cast());
+        let out: [i32; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s32_x4() {
+        let vals: [i32; 16] = crate::array::from_fn(|i| i as i32);
+        let a: int32x4x4_t = transmute(vals);
+        let mut tmp = [0_i32; 16];
+        vst1q_s32_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int32x4x4_t = vld1q_s32_x4(tmp.as_ptr().cast());
+        let out: [i32; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s64_x2() {
+        let vals: [i64; 2] = crate::array::from_fn(|i| i as i64);
+        let a: int64x1x2_t = transmute(vals);
+        let mut tmp = [0_i64; 2];
+        vst1_s64_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int64x1x2_t = vld1_s64_x2(tmp.as_ptr().cast());
+        let out: [i64; 2] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s64_x3() {
+        let vals: [i64; 3] = crate::array::from_fn(|i| i as i64);
+        let a: int64x1x3_t = transmute(vals);
+        let mut tmp = [0_i64; 3];
+        vst1_s64_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int64x1x3_t = vld1_s64_x3(tmp.as_ptr().cast());
+        let out: [i64; 3] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_s64_x4() {
+        let vals: [i64; 4] = crate::array::from_fn(|i| i as i64);
+        let a: int64x1x4_t = transmute(vals);
+        let mut tmp = [0_i64; 4];
+        vst1_s64_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int64x1x4_t = vld1_s64_x4(tmp.as_ptr().cast());
+        let out: [i64; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s64_x2() {
+        let vals: [i64; 4] = crate::array::from_fn(|i| i as i64);
+        let a: int64x2x2_t = transmute(vals);
+        let mut tmp = [0_i64; 4];
+        vst1q_s64_x2(tmp.as_mut_ptr().cast(), a);
+        let r: int64x2x2_t = vld1q_s64_x2(tmp.as_ptr().cast());
+        let out: [i64; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s64_x3() {
+        let vals: [i64; 6] = crate::array::from_fn(|i| i as i64);
+        let a: int64x2x3_t = transmute(vals);
+        let mut tmp = [0_i64; 6];
+        vst1q_s64_x3(tmp.as_mut_ptr().cast(), a);
+        let r: int64x2x3_t = vld1q_s64_x3(tmp.as_ptr().cast());
+        let out: [i64; 6] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_s64_x4() {
+        let vals: [i64; 8] = crate::array::from_fn(|i| i as i64);
+        let a: int64x2x4_t = transmute(vals);
+        let mut tmp = [0_i64; 8];
+        vst1q_s64_x4(tmp.as_mut_ptr().cast(), a);
+        let r: int64x2x4_t = vld1q_s64_x4(tmp.as_ptr().cast());
+        let out: [i64; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u8_x2() {
+        let vals: [u8; 16] = crate::array::from_fn(|i| i as u8);
+        let a: uint8x8x2_t = transmute(vals);
+        let mut tmp = [0_u8; 16];
+        vst1_u8_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint8x8x2_t = vld1_u8_x2(tmp.as_ptr().cast());
+        let out: [u8; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u8_x3() {
+        let vals: [u8; 24] = crate::array::from_fn(|i| i as u8);
+        let a: uint8x8x3_t = transmute(vals);
+        let mut tmp = [0_u8; 24];
+        vst1_u8_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint8x8x3_t = vld1_u8_x3(tmp.as_ptr().cast());
+        let out: [u8; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u8_x4() {
+        let vals: [u8; 32] = crate::array::from_fn(|i| i as u8);
+        let a: uint8x8x4_t = transmute(vals);
+        let mut tmp = [0_u8; 32];
+        vst1_u8_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint8x8x4_t = vld1_u8_x4(tmp.as_ptr().cast());
+        let out: [u8; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u8_x2() {
+        let vals: [u8; 32] = crate::array::from_fn(|i| i as u8);
+        let a: uint8x16x2_t = transmute(vals);
+        let mut tmp = [0_u8; 32];
+        vst1q_u8_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint8x16x2_t = vld1q_u8_x2(tmp.as_ptr().cast());
+        let out: [u8; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u8_x3() {
+        let vals: [u8; 48] = crate::array::from_fn(|i| i as u8);
+        let a: uint8x16x3_t = transmute(vals);
+        let mut tmp = [0_u8; 48];
+        vst1q_u8_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint8x16x3_t = vld1q_u8_x3(tmp.as_ptr().cast());
+        let out: [u8; 48] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u8_x4() {
+        let vals: [u8; 64] = crate::array::from_fn(|i| i as u8);
+        let a: uint8x16x4_t = transmute(vals);
+        let mut tmp = [0_u8; 64];
+        vst1q_u8_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint8x16x4_t = vld1q_u8_x4(tmp.as_ptr().cast());
+        let out: [u8; 64] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u16_x2() {
+        let vals: [u16; 8] = crate::array::from_fn(|i| i as u16);
+        let a: uint16x4x2_t = transmute(vals);
+        let mut tmp = [0_u16; 8];
+        vst1_u16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint16x4x2_t = vld1_u16_x2(tmp.as_ptr().cast());
+        let out: [u16; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u16_x3() {
+        let vals: [u16; 12] = crate::array::from_fn(|i| i as u16);
+        let a: uint16x4x3_t = transmute(vals);
+        let mut tmp = [0_u16; 12];
+        vst1_u16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint16x4x3_t = vld1_u16_x3(tmp.as_ptr().cast());
+        let out: [u16; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u16_x4() {
+        let vals: [u16; 16] = crate::array::from_fn(|i| i as u16);
+        let a: uint16x4x4_t = transmute(vals);
+        let mut tmp = [0_u16; 16];
+        vst1_u16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint16x4x4_t = vld1_u16_x4(tmp.as_ptr().cast());
+        let out: [u16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u16_x2() {
+        let vals: [u16; 16] = crate::array::from_fn(|i| i as u16);
+        let a: uint16x8x2_t = transmute(vals);
+        let mut tmp = [0_u16; 16];
+        vst1q_u16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint16x8x2_t = vld1q_u16_x2(tmp.as_ptr().cast());
+        let out: [u16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u16_x3() {
+        let vals: [u16; 24] = crate::array::from_fn(|i| i as u16);
+        let a: uint16x8x3_t = transmute(vals);
+        let mut tmp = [0_u16; 24];
+        vst1q_u16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint16x8x3_t = vld1q_u16_x3(tmp.as_ptr().cast());
+        let out: [u16; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u16_x4() {
+        let vals: [u16; 32] = crate::array::from_fn(|i| i as u16);
+        let a: uint16x8x4_t = transmute(vals);
+        let mut tmp = [0_u16; 32];
+        vst1q_u16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint16x8x4_t = vld1q_u16_x4(tmp.as_ptr().cast());
+        let out: [u16; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u32_x2() {
+        let vals: [u32; 4] = crate::array::from_fn(|i| i as u32);
+        let a: uint32x2x2_t = transmute(vals);
+        let mut tmp = [0_u32; 4];
+        vst1_u32_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint32x2x2_t = vld1_u32_x2(tmp.as_ptr().cast());
+        let out: [u32; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u32_x3() {
+        let vals: [u32; 6] = crate::array::from_fn(|i| i as u32);
+        let a: uint32x2x3_t = transmute(vals);
+        let mut tmp = [0_u32; 6];
+        vst1_u32_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint32x2x3_t = vld1_u32_x3(tmp.as_ptr().cast());
+        let out: [u32; 6] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u32_x4() {
+        let vals: [u32; 8] = crate::array::from_fn(|i| i as u32);
+        let a: uint32x2x4_t = transmute(vals);
+        let mut tmp = [0_u32; 8];
+        vst1_u32_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint32x2x4_t = vld1_u32_x4(tmp.as_ptr().cast());
+        let out: [u32; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u32_x2() {
+        let vals: [u32; 8] = crate::array::from_fn(|i| i as u32);
+        let a: uint32x4x2_t = transmute(vals);
+        let mut tmp = [0_u32; 8];
+        vst1q_u32_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint32x4x2_t = vld1q_u32_x2(tmp.as_ptr().cast());
+        let out: [u32; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u32_x3() {
+        let vals: [u32; 12] = crate::array::from_fn(|i| i as u32);
+        let a: uint32x4x3_t = transmute(vals);
+        let mut tmp = [0_u32; 12];
+        vst1q_u32_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint32x4x3_t = vld1q_u32_x3(tmp.as_ptr().cast());
+        let out: [u32; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u32_x4() {
+        let vals: [u32; 16] = crate::array::from_fn(|i| i as u32);
+        let a: uint32x4x4_t = transmute(vals);
+        let mut tmp = [0_u32; 16];
+        vst1q_u32_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint32x4x4_t = vld1q_u32_x4(tmp.as_ptr().cast());
+        let out: [u32; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u64_x2() {
+        let vals: [u64; 2] = crate::array::from_fn(|i| i as u64);
+        let a: uint64x1x2_t = transmute(vals);
+        let mut tmp = [0_u64; 2];
+        vst1_u64_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint64x1x2_t = vld1_u64_x2(tmp.as_ptr().cast());
+        let out: [u64; 2] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u64_x3() {
+        let vals: [u64; 3] = crate::array::from_fn(|i| i as u64);
+        let a: uint64x1x3_t = transmute(vals);
+        let mut tmp = [0_u64; 3];
+        vst1_u64_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint64x1x3_t = vld1_u64_x3(tmp.as_ptr().cast());
+        let out: [u64; 3] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_u64_x4() {
+        let vals: [u64; 4] = crate::array::from_fn(|i| i as u64);
+        let a: uint64x1x4_t = transmute(vals);
+        let mut tmp = [0_u64; 4];
+        vst1_u64_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint64x1x4_t = vld1_u64_x4(tmp.as_ptr().cast());
+        let out: [u64; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u64_x2() {
+        let vals: [u64; 4] = crate::array::from_fn(|i| i as u64);
+        let a: uint64x2x2_t = transmute(vals);
+        let mut tmp = [0_u64; 4];
+        vst1q_u64_x2(tmp.as_mut_ptr().cast(), a);
+        let r: uint64x2x2_t = vld1q_u64_x2(tmp.as_ptr().cast());
+        let out: [u64; 4] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u64_x3() {
+        let vals: [u64; 6] = crate::array::from_fn(|i| i as u64);
+        let a: uint64x2x3_t = transmute(vals);
+        let mut tmp = [0_u64; 6];
+        vst1q_u64_x3(tmp.as_mut_ptr().cast(), a);
+        let r: uint64x2x3_t = vld1q_u64_x3(tmp.as_ptr().cast());
+        let out: [u64; 6] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_u64_x4() {
+        let vals: [u64; 8] = crate::array::from_fn(|i| i as u64);
+        let a: uint64x2x4_t = transmute(vals);
+        let mut tmp = [0_u64; 8];
+        vst1q_u64_x4(tmp.as_mut_ptr().cast(), a);
+        let r: uint64x2x4_t = vld1q_u64_x4(tmp.as_ptr().cast());
+        let out: [u64; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_p8_x2() {
+        let vals: [p8; 16] = crate::array::from_fn(|i| i as p8);
+        let a: poly8x8x2_t = transmute(vals);
+        let mut tmp = [0 as p8; 16];
+        vst1_p8_x2(tmp.as_mut_ptr().cast(), a);
+        let r: poly8x8x2_t = vld1_p8_x2(tmp.as_ptr().cast());
+        let out: [p8; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_p8_x3() {
+        let vals: [p8; 24] = crate::array::from_fn(|i| i as p8);
+        let a: poly8x8x3_t = transmute(vals);
+        let mut tmp = [0 as p8; 24];
+        vst1_p8_x3(tmp.as_mut_ptr().cast(), a);
+        let r: poly8x8x3_t = vld1_p8_x3(tmp.as_ptr().cast());
+        let out: [p8; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_p8_x4() {
+        let vals: [p8; 32] = crate::array::from_fn(|i| i as p8);
+        let a: poly8x8x4_t = transmute(vals);
+        let mut tmp = [0 as p8; 32];
+        vst1_p8_x4(tmp.as_mut_ptr().cast(), a);
+        let r: poly8x8x4_t = vld1_p8_x4(tmp.as_ptr().cast());
+        let out: [p8; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_p8_x2() {
+        let vals: [p8; 32] = crate::array::from_fn(|i| i as p8);
+        let a: poly8x16x2_t = transmute(vals);
+        let mut tmp = [0 as p8; 32];
+        vst1q_p8_x2(tmp.as_mut_ptr().cast(), a);
+        let r: poly8x16x2_t = vld1q_p8_x2(tmp.as_ptr().cast());
+        let out: [p8; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_p8_x3() {
+        let vals: [p8; 48] = crate::array::from_fn(|i| i as p8);
+        let a: poly8x16x3_t = transmute(vals);
+        let mut tmp = [0 as p8; 48];
+        vst1q_p8_x3(tmp.as_mut_ptr().cast(), a);
+        let r: poly8x16x3_t = vld1q_p8_x3(tmp.as_ptr().cast());
+        let out: [p8; 48] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_p8_x4() {
+        let vals: [p8; 64] = crate::array::from_fn(|i| i as p8);
+        let a: poly8x16x4_t = transmute(vals);
+        let mut tmp = [0 as p8; 64];
+        vst1q_p8_x4(tmp.as_mut_ptr().cast(), a);
+        let r: poly8x16x4_t = vld1q_p8_x4(tmp.as_ptr().cast());
+        let out: [p8; 64] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_p16_x2() {
+        let vals: [p16; 8] = crate::array::from_fn(|i| i as p16);
+        let a: poly16x4x2_t = transmute(vals);
+        let mut tmp = [0 as p16; 8];
+        vst1_p16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: poly16x4x2_t = vld1_p16_x2(tmp.as_ptr().cast());
+        let out: [p16; 8] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_p16_x3() {
+        let vals: [p16; 12] = crate::array::from_fn(|i| i as p16);
+        let a: poly16x4x3_t = transmute(vals);
+        let mut tmp = [0 as p16; 12];
+        vst1_p16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: poly16x4x3_t = vld1_p16_x3(tmp.as_ptr().cast());
+        let out: [p16; 12] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1_p16_x4() {
+        let vals: [p16; 16] = crate::array::from_fn(|i| i as p16);
+        let a: poly16x4x4_t = transmute(vals);
+        let mut tmp = [0 as p16; 16];
+        vst1_p16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: poly16x4x4_t = vld1_p16_x4(tmp.as_ptr().cast());
+        let out: [p16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_p16_x2() {
+        let vals: [p16; 16] = crate::array::from_fn(|i| i as p16);
+        let a: poly16x8x2_t = transmute(vals);
+        let mut tmp = [0 as p16; 16];
+        vst1q_p16_x2(tmp.as_mut_ptr().cast(), a);
+        let r: poly16x8x2_t = vld1q_p16_x2(tmp.as_ptr().cast());
+        let out: [p16; 16] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_p16_x3() {
+        let vals: [p16; 24] = crate::array::from_fn(|i| i as p16);
+        let a: poly16x8x3_t = transmute(vals);
+        let mut tmp = [0 as p16; 24];
+        vst1q_p16_x3(tmp.as_mut_ptr().cast(), a);
+        let r: poly16x8x3_t = vld1q_p16_x3(tmp.as_ptr().cast());
+        let out: [p16; 24] = transmute(r);
+        assert_eq!(out, vals);
+    }
+
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_p16_x4() {
+        let vals: [p16; 32] = crate::array::from_fn(|i| i as p16);
+        let a: poly16x8x4_t = transmute(vals);
+        let mut tmp = [0 as p16; 32];
+        vst1q_p16_x4(tmp.as_mut_ptr().cast(), a);
+        let r: poly16x8x4_t = vld1q_p16_x4(tmp.as_ptr().cast());
+        let out: [p16; 32] = transmute(r);
+        assert_eq!(out, vals);
+    }
 }
 
 #[cfg(test)]

From e3feb19a9edf7530e550d064f5485c99d5abeca9 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Fri, 30 Jan 2026 21:35:56 +0100
Subject: [PATCH 122/326] maybe fix aarch64be unsigned vector tuple loads

---
 .../src/arm_shared/neon/generated.rs          | 1352 ++---------------
 .../spec/neon/arm_shared.spec.yml             |    2 +
 2 files changed, 102 insertions(+), 1252 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 3b67208182..2f52e3b52b 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -17067,7 +17067,6 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -17087,38 +17086,10 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
     transmute(vld1q_s64_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
-    let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -17138,39 +17109,10 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
     transmute(vld1q_s64_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
-    let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -17189,35 +17131,6 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
     transmute(vld1q_s64_x4(transmute(a)))
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
-    let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
-    ret_val
-}
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
@@ -18071,7 +17984,6 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18091,11 +18003,10 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
     transmute(vld1_s8_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18111,18 +18022,14 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
-    let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
+    transmute(vld1_s8_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18138,15 +18045,14 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
-    transmute(vld1_s8_x3(transmute(a)))
+pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
+    transmute(vld1_s8_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18162,19 +18068,14 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
-    let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
+    transmute(vld1q_s8_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18190,15 +18091,14 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
-    transmute(vld1_s8_x4(transmute(a)))
+pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
+    transmute(vld1q_s8_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18214,20 +18114,14 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
-    let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
+    transmute(vld1q_s8_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18243,15 +18137,14 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
-    transmute(vld1q_s8_x2(transmute(a)))
+pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
+    transmute(vld1_s16_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18267,30 +18160,14 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
-    let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
+    transmute(vld1_s16_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18306,15 +18183,14 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
-    transmute(vld1q_s8_x3(transmute(a)))
+pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
+    transmute(vld1_s16_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18330,37 +18206,14 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
-    let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
+    transmute(vld1q_s16_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18376,15 +18229,14 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
-    transmute(vld1q_s8_x4(transmute(a)))
+pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
+    transmute(vld1q_s16_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18400,44 +18252,14 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
-    let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.3 = unsafe {
-        simd_shuffle!(
-            ret_val.3,
-            ret_val.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
+    transmute(vld1q_s16_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18453,15 +18275,14 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
-    transmute(vld1_s16_x2(transmute(a)))
+pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
+    transmute(vld1_s32_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18477,18 +18298,14 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
-    let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
+    transmute(vld1_s32_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18504,840 +18321,14 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
-    transmute(vld1_s16_x3(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
-    let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
-    transmute(vld1_s16_x4(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
-    let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
-    transmute(vld1q_s16_x2(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
-    let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
-    transmute(vld1q_s16_x3(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
-    let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
-    transmute(vld1q_s16_x4(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
-    let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
-    transmute(vld1_s32_x2(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
-    let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
-    transmute(vld1_s32_x3(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
-    let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
-    transmute(vld1_s32_x4(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
-    let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
-    transmute(vld1q_s32_x2(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
-    let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
-    transmute(vld1q_s32_x3(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
-    let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
-    transmute(vld1q_s32_x4(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
-    let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
-    transmute(vld1_s64_x2(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
-    transmute(vld1_s64_x3(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
-    transmute(vld1_s64_x4(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
-    transmute(vld1q_s64_x2(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
-    let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
-    transmute(vld1q_s64_x3(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
-    let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
-    transmute(vld1q_s64_x4(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
-    let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
-    transmute(vld1_s8_x2(transmute(a)))
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
-    let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
+    transmute(vld1_s32_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19353,15 +18344,14 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
-    transmute(vld1_s8_x3(transmute(a)))
+pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
+    transmute(vld1q_s32_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19377,19 +18367,14 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
-    let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
+    transmute(vld1q_s32_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19405,15 +18390,14 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
-    transmute(vld1_s8_x4(transmute(a)))
+pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
+    transmute(vld1q_s32_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19429,20 +18413,14 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
-    let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
+    transmute(vld1_s64_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19458,15 +18436,14 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
-    transmute(vld1q_s8_x2(transmute(a)))
+pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
+    transmute(vld1_s64_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19482,30 +18459,14 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
-    let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
+    transmute(vld1_s64_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19521,15 +18482,14 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
-    transmute(vld1q_s8_x3(transmute(a)))
+pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
+    transmute(vld1q_s64_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19545,37 +18505,14 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
-    let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
+    transmute(vld1q_s64_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19591,15 +18528,14 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
-    transmute(vld1q_s8_x4(transmute(a)))
+pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
+    transmute(vld1q_s64_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19615,44 +18551,14 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
-    let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.3 = unsafe {
-        simd_shuffle!(
-            ret_val.3,
-            ret_val.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
+    transmute(vld1_s8_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19668,15 +18574,14 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
-    transmute(vld1_s16_x2(transmute(a)))
+pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
+    transmute(vld1_s8_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19692,18 +18597,14 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
-    let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
+    transmute(vld1_s8_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19719,15 +18620,14 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
-    transmute(vld1_s16_x3(transmute(a)))
+pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
+    transmute(vld1q_s8_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19743,19 +18643,14 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
-    let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
+    transmute(vld1q_s8_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19771,15 +18666,14 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
-    transmute(vld1_s16_x4(transmute(a)))
+pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
+    transmute(vld1q_s8_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19795,20 +18689,14 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
-    let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
+    transmute(vld1_s16_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19824,15 +18712,14 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
-    transmute(vld1q_s16_x2(transmute(a)))
+pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
+    transmute(vld1_s16_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19848,18 +18735,14 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
-    let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
+    transmute(vld1_s16_x4(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19875,15 +18758,14 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
-    transmute(vld1q_s16_x3(transmute(a)))
+pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
+    transmute(vld1q_s16_x2(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19900,18 +18782,13 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
-    let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+    transmute(vld1q_s16_x3(transmute(a)))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -19930,35 +18807,6 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
     transmute(vld1q_s16_x4(transmute(a)))
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
-    let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
 #[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 52748a4cc0..3ec7ba8814 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -2681,6 +2681,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -2740,6 +2741,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:

From fe9aa9cc5a39291aff9c86c24bff1eba8a1b668b Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 1 Feb 2026 13:50:20 +0100
Subject: [PATCH 123/326] use macro for wide store/load roundtrip tests

---
 crates/core_arch/src/aarch64/neon/mod.rs | 636 ++++-------------------
 1 file changed, 90 insertions(+), 546 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index feaf94a7f9..ee27bef973 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -994,868 +994,412 @@ mod tests {
         assert_eq!(vals[2], 2.);
     }
 
+    macro_rules! wide_store_load_roundtrip {
+        ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => {
+            let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty);
+            let a: $vec_ty = transmute(vals);
+            let mut tmp = [0 as $elem_ty; $len];
+            $store(tmp.as_mut_ptr().cast(), a);
+            let r: $vec_ty = $load(tmp.as_ptr().cast());
+            let out: [$elem_ty; $len] = transmute(r);
+            assert_eq!(out, vals);
+        };
+    }
+
     #[simd_test(enable = "neon,fp16")]
     #[cfg(not(target_arch = "arm64ec"))]
     unsafe fn test_vld1_f16_x2() {
-        let vals: [f16; 8] = crate::array::from_fn(|i| i as f16);
-        let a: float16x4x2_t = transmute(vals);
-        let mut tmp = [0_f16; 8];
-        vst1_f16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: float16x4x2_t = vld1_f16_x2(tmp.as_ptr().cast());
-        let out: [f16; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2);
     }
 
     #[simd_test(enable = "neon,fp16")]
     #[cfg(not(target_arch = "arm64ec"))]
     unsafe fn test_vld1_f16_x3() {
-        let vals: [f16; 12] = crate::array::from_fn(|i| i as f16);
-        let a: float16x4x3_t = transmute(vals);
-        let mut tmp = [0_f16; 12];
-        vst1_f16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: float16x4x3_t = vld1_f16_x3(tmp.as_ptr().cast());
-        let out: [f16; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3);
     }
 
     #[simd_test(enable = "neon,fp16")]
     #[cfg(not(target_arch = "arm64ec"))]
     unsafe fn test_vld1_f16_x4() {
-        let vals: [f16; 16] = crate::array::from_fn(|i| i as f16);
-        let a: float16x4x4_t = transmute(vals);
-        let mut tmp = [0_f16; 16];
-        vst1_f16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: float16x4x4_t = vld1_f16_x4(tmp.as_ptr().cast());
-        let out: [f16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4);
     }
 
     #[simd_test(enable = "neon,fp16")]
     #[cfg(not(target_arch = "arm64ec"))]
     unsafe fn test_vld1q_f16_x2() {
-        let vals: [f16; 16] = crate::array::from_fn(|i| i as f16);
-        let a: float16x8x2_t = transmute(vals);
-        let mut tmp = [0_f16; 16];
-        vst1q_f16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: float16x8x2_t = vld1q_f16_x2(tmp.as_ptr().cast());
-        let out: [f16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2);
     }
 
     #[simd_test(enable = "neon,fp16")]
     #[cfg(not(target_arch = "arm64ec"))]
     unsafe fn test_vld1q_f16_x3() {
-        let vals: [f16; 24] = crate::array::from_fn(|i| i as f16);
-        let a: float16x8x3_t = transmute(vals);
-        let mut tmp = [0_f16; 24];
-        vst1q_f16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: float16x8x3_t = vld1q_f16_x3(tmp.as_ptr().cast());
-        let out: [f16; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3);
     }
 
     #[simd_test(enable = "neon,fp16")]
     #[cfg(not(target_arch = "arm64ec"))]
     unsafe fn test_vld1q_f16_x4() {
-        let vals: [f16; 32] = crate::array::from_fn(|i| i as f16);
-        let a: float16x8x4_t = transmute(vals);
-        let mut tmp = [0_f16; 32];
-        vst1q_f16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: float16x8x4_t = vld1q_f16_x4(tmp.as_ptr().cast());
-        let out: [f16; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_f32_x2() {
-        let vals: [f32; 4] = crate::array::from_fn(|i| i as f32);
-        let a: float32x2x2_t = transmute(vals);
-        let mut tmp = [0_f32; 4];
-        vst1_f32_x2(tmp.as_mut_ptr().cast(), a);
-        let r: float32x2x2_t = vld1_f32_x2(tmp.as_ptr().cast());
-        let out: [f32; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_f32_x3() {
-        let vals: [f32; 6] = crate::array::from_fn(|i| i as f32);
-        let a: float32x2x3_t = transmute(vals);
-        let mut tmp = [0_f32; 6];
-        vst1_f32_x3(tmp.as_mut_ptr().cast(), a);
-        let r: float32x2x3_t = vld1_f32_x3(tmp.as_ptr().cast());
-        let out: [f32; 6] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_f32_x4() {
-        let vals: [f32; 8] = crate::array::from_fn(|i| i as f32);
-        let a: float32x2x4_t = transmute(vals);
-        let mut tmp = [0_f32; 8];
-        vst1_f32_x4(tmp.as_mut_ptr().cast(), a);
-        let r: float32x2x4_t = vld1_f32_x4(tmp.as_ptr().cast());
-        let out: [f32; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_f32_x2() {
-        let vals: [f32; 8] = crate::array::from_fn(|i| i as f32);
-        let a: float32x4x2_t = transmute(vals);
-        let mut tmp = [0_f32; 8];
-        vst1q_f32_x2(tmp.as_mut_ptr().cast(), a);
-        let r: float32x4x2_t = vld1q_f32_x2(tmp.as_ptr().cast());
-        let out: [f32; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_f32_x3() {
-        let vals: [f32; 12] = crate::array::from_fn(|i| i as f32);
-        let a: float32x4x3_t = transmute(vals);
-        let mut tmp = [0_f32; 12];
-        vst1q_f32_x3(tmp.as_mut_ptr().cast(), a);
-        let r: float32x4x3_t = vld1q_f32_x3(tmp.as_ptr().cast());
-        let out: [f32; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_f32_x4() {
-        let vals: [f32; 16] = crate::array::from_fn(|i| i as f32);
-        let a: float32x4x4_t = transmute(vals);
-        let mut tmp = [0_f32; 16];
-        vst1q_f32_x4(tmp.as_mut_ptr().cast(), a);
-        let r: float32x4x4_t = vld1q_f32_x4(tmp.as_ptr().cast());
-        let out: [f32; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4);
     }
 
     #[simd_test(enable = "neon,aes")]
     unsafe fn test_vld1_p64_x2() {
-        let vals: [p64; 2] = crate::array::from_fn(|i| i as p64);
-        let a: poly64x1x2_t = transmute(vals);
-        let mut tmp = [0 as p64; 2];
-        vst1_p64_x2(tmp.as_mut_ptr().cast(), a);
-        let r: poly64x1x2_t = vld1_p64_x2(tmp.as_ptr().cast());
-        let out: [p64; 2] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2);
     }
 
     #[simd_test(enable = "neon,aes")]
     unsafe fn test_vld1_p64_x3() {
-        let vals: [p64; 3] = crate::array::from_fn(|i| i as p64);
-        let a: poly64x1x3_t = transmute(vals);
-        let mut tmp = [0 as p64; 3];
-        vst1_p64_x3(tmp.as_mut_ptr().cast(), a);
-        let r: poly64x1x3_t = vld1_p64_x3(tmp.as_ptr().cast());
-        let out: [p64; 3] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3);
     }
 
     #[simd_test(enable = "neon,aes")]
     unsafe fn test_vld1_p64_x4() {
-        let vals: [p64; 4] = crate::array::from_fn(|i| i as p64);
-        let a: poly64x1x4_t = transmute(vals);
-        let mut tmp = [0 as p64; 4];
-        vst1_p64_x4(tmp.as_mut_ptr().cast(), a);
-        let r: poly64x1x4_t = vld1_p64_x4(tmp.as_ptr().cast());
-        let out: [p64; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4);
     }
 
     #[simd_test(enable = "neon,aes")]
     unsafe fn test_vld1q_p64_x2() {
-        let vals: [p64; 4] = crate::array::from_fn(|i| i as p64);
-        let a: poly64x2x2_t = transmute(vals);
-        let mut tmp = [0 as p64; 4];
-        vst1q_p64_x2(tmp.as_mut_ptr().cast(), a);
-        let r: poly64x2x2_t = vld1q_p64_x2(tmp.as_ptr().cast());
-        let out: [p64; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2);
     }
 
     #[simd_test(enable = "neon,aes")]
     unsafe fn test_vld1q_p64_x3() {
-        let vals: [p64; 6] = crate::array::from_fn(|i| i as p64);
-        let a: poly64x2x3_t = transmute(vals);
-        let mut tmp = [0 as p64; 6];
-        vst1q_p64_x3(tmp.as_mut_ptr().cast(), a);
-        let r: poly64x2x3_t = vld1q_p64_x3(tmp.as_ptr().cast());
-        let out: [p64; 6] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3);
     }
 
     #[simd_test(enable = "neon,aes")]
     unsafe fn test_vld1q_p64_x4() {
-        let vals: [p64; 8] = crate::array::from_fn(|i| i as p64);
-        let a: poly64x2x4_t = transmute(vals);
-        let mut tmp = [0 as p64; 8];
-        vst1q_p64_x4(tmp.as_mut_ptr().cast(), a);
-        let r: poly64x2x4_t = vld1q_p64_x4(tmp.as_ptr().cast());
-        let out: [p64; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s8_x2() {
-        let vals: [i8; 16] = crate::array::from_fn(|i| i as i8);
-        let a: int8x8x2_t = transmute(vals);
-        let mut tmp = [0_i8; 16];
-        vst1_s8_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int8x8x2_t = vld1_s8_x2(tmp.as_ptr().cast());
-        let out: [i8; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s8_x3() {
-        let vals: [i8; 24] = crate::array::from_fn(|i| i as i8);
-        let a: int8x8x3_t = transmute(vals);
-        let mut tmp = [0_i8; 24];
-        vst1_s8_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int8x8x3_t = vld1_s8_x3(tmp.as_ptr().cast());
-        let out: [i8; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s8_x4() {
-        let vals: [i8; 32] = crate::array::from_fn(|i| i as i8);
-        let a: int8x8x4_t = transmute(vals);
-        let mut tmp = [0_i8; 32];
-        vst1_s8_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int8x8x4_t = vld1_s8_x4(tmp.as_ptr().cast());
-        let out: [i8; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s8_x2() {
-        let vals: [i8; 32] = crate::array::from_fn(|i| i as i8);
-        let a: int8x16x2_t = transmute(vals);
-        let mut tmp = [0_i8; 32];
-        vst1q_s8_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int8x16x2_t = vld1q_s8_x2(tmp.as_ptr().cast());
-        let out: [i8; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s8_x3() {
-        let vals: [i8; 48] = crate::array::from_fn(|i| i as i8);
-        let a: int8x16x3_t = transmute(vals);
-        let mut tmp = [0_i8; 48];
-        vst1q_s8_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int8x16x3_t = vld1q_s8_x3(tmp.as_ptr().cast());
-        let out: [i8; 48] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s8_x4() {
-        let vals: [i8; 64] = crate::array::from_fn(|i| i as i8);
-        let a: int8x16x4_t = transmute(vals);
-        let mut tmp = [0_i8; 64];
-        vst1q_s8_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int8x16x4_t = vld1q_s8_x4(tmp.as_ptr().cast());
-        let out: [i8; 64] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s16_x2() {
-        let vals: [i16; 8] = crate::array::from_fn(|i| i as i16);
-        let a: int16x4x2_t = transmute(vals);
-        let mut tmp = [0_i16; 8];
-        vst1_s16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int16x4x2_t = vld1_s16_x2(tmp.as_ptr().cast());
-        let out: [i16; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s16_x3() {
-        let vals: [i16; 12] = crate::array::from_fn(|i| i as i16);
-        let a: int16x4x3_t = transmute(vals);
-        let mut tmp = [0_i16; 12];
-        vst1_s16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int16x4x3_t = vld1_s16_x3(tmp.as_ptr().cast());
-        let out: [i16; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s16_x4() {
-        let vals: [i16; 16] = crate::array::from_fn(|i| i as i16);
-        let a: int16x4x4_t = transmute(vals);
-        let mut tmp = [0_i16; 16];
-        vst1_s16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int16x4x4_t = vld1_s16_x4(tmp.as_ptr().cast());
-        let out: [i16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s16_x2() {
-        let vals: [i16; 16] = crate::array::from_fn(|i| i as i16);
-        let a: int16x8x2_t = transmute(vals);
-        let mut tmp = [0_i16; 16];
-        vst1q_s16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int16x8x2_t = vld1q_s16_x2(tmp.as_ptr().cast());
-        let out: [i16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s16_x3() {
-        let vals: [i16; 24] = crate::array::from_fn(|i| i as i16);
-        let a: int16x8x3_t = transmute(vals);
-        let mut tmp = [0_i16; 24];
-        vst1q_s16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int16x8x3_t = vld1q_s16_x3(tmp.as_ptr().cast());
-        let out: [i16; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s16_x4() {
-        let vals: [i16; 32] = crate::array::from_fn(|i| i as i16);
-        let a: int16x8x4_t = transmute(vals);
-        let mut tmp = [0_i16; 32];
-        vst1q_s16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int16x8x4_t = vld1q_s16_x4(tmp.as_ptr().cast());
-        let out: [i16; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s32_x2() {
-        let vals: [i32; 4] = crate::array::from_fn(|i| i as i32);
-        let a: int32x2x2_t = transmute(vals);
-        let mut tmp = [0_i32; 4];
-        vst1_s32_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int32x2x2_t = vld1_s32_x2(tmp.as_ptr().cast());
-        let out: [i32; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s32_x3() {
-        let vals: [i32; 6] = crate::array::from_fn(|i| i as i32);
-        let a: int32x2x3_t = transmute(vals);
-        let mut tmp = [0_i32; 6];
-        vst1_s32_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int32x2x3_t = vld1_s32_x3(tmp.as_ptr().cast());
-        let out: [i32; 6] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s32_x4() {
-        let vals: [i32; 8] = crate::array::from_fn(|i| i as i32);
-        let a: int32x2x4_t = transmute(vals);
-        let mut tmp = [0_i32; 8];
-        vst1_s32_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int32x2x4_t = vld1_s32_x4(tmp.as_ptr().cast());
-        let out: [i32; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s32_x2() {
-        let vals: [i32; 8] = crate::array::from_fn(|i| i as i32);
-        let a: int32x4x2_t = transmute(vals);
-        let mut tmp = [0_i32; 8];
-        vst1q_s32_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int32x4x2_t = vld1q_s32_x2(tmp.as_ptr().cast());
-        let out: [i32; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s32_x3() {
-        let vals: [i32; 12] = crate::array::from_fn(|i| i as i32);
-        let a: int32x4x3_t = transmute(vals);
-        let mut tmp = [0_i32; 12];
-        vst1q_s32_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int32x4x3_t = vld1q_s32_x3(tmp.as_ptr().cast());
-        let out: [i32; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s32_x4() {
-        let vals: [i32; 16] = crate::array::from_fn(|i| i as i32);
-        let a: int32x4x4_t = transmute(vals);
-        let mut tmp = [0_i32; 16];
-        vst1q_s32_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int32x4x4_t = vld1q_s32_x4(tmp.as_ptr().cast());
-        let out: [i32; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s64_x2() {
-        let vals: [i64; 2] = crate::array::from_fn(|i| i as i64);
-        let a: int64x1x2_t = transmute(vals);
-        let mut tmp = [0_i64; 2];
-        vst1_s64_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int64x1x2_t = vld1_s64_x2(tmp.as_ptr().cast());
-        let out: [i64; 2] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s64_x3() {
-        let vals: [i64; 3] = crate::array::from_fn(|i| i as i64);
-        let a: int64x1x3_t = transmute(vals);
-        let mut tmp = [0_i64; 3];
-        vst1_s64_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int64x1x3_t = vld1_s64_x3(tmp.as_ptr().cast());
-        let out: [i64; 3] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_s64_x4() {
-        let vals: [i64; 4] = crate::array::from_fn(|i| i as i64);
-        let a: int64x1x4_t = transmute(vals);
-        let mut tmp = [0_i64; 4];
-        vst1_s64_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int64x1x4_t = vld1_s64_x4(tmp.as_ptr().cast());
-        let out: [i64; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s64_x2() {
-        let vals: [i64; 4] = crate::array::from_fn(|i| i as i64);
-        let a: int64x2x2_t = transmute(vals);
-        let mut tmp = [0_i64; 4];
-        vst1q_s64_x2(tmp.as_mut_ptr().cast(), a);
-        let r: int64x2x2_t = vld1q_s64_x2(tmp.as_ptr().cast());
-        let out: [i64; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s64_x3() {
-        let vals: [i64; 6] = crate::array::from_fn(|i| i as i64);
-        let a: int64x2x3_t = transmute(vals);
-        let mut tmp = [0_i64; 6];
-        vst1q_s64_x3(tmp.as_mut_ptr().cast(), a);
-        let r: int64x2x3_t = vld1q_s64_x3(tmp.as_ptr().cast());
-        let out: [i64; 6] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_s64_x4() {
-        let vals: [i64; 8] = crate::array::from_fn(|i| i as i64);
-        let a: int64x2x4_t = transmute(vals);
-        let mut tmp = [0_i64; 8];
-        vst1q_s64_x4(tmp.as_mut_ptr().cast(), a);
-        let r: int64x2x4_t = vld1q_s64_x4(tmp.as_ptr().cast());
-        let out: [i64; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u8_x2() {
-        let vals: [u8; 16] = crate::array::from_fn(|i| i as u8);
-        let a: uint8x8x2_t = transmute(vals);
-        let mut tmp = [0_u8; 16];
-        vst1_u8_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint8x8x2_t = vld1_u8_x2(tmp.as_ptr().cast());
-        let out: [u8; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u8_x3() {
-        let vals: [u8; 24] = crate::array::from_fn(|i| i as u8);
-        let a: uint8x8x3_t = transmute(vals);
-        let mut tmp = [0_u8; 24];
-        vst1_u8_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint8x8x3_t = vld1_u8_x3(tmp.as_ptr().cast());
-        let out: [u8; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u8_x4() {
-        let vals: [u8; 32] = crate::array::from_fn(|i| i as u8);
-        let a: uint8x8x4_t = transmute(vals);
-        let mut tmp = [0_u8; 32];
-        vst1_u8_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint8x8x4_t = vld1_u8_x4(tmp.as_ptr().cast());
-        let out: [u8; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u8_x2() {
-        let vals: [u8; 32] = crate::array::from_fn(|i| i as u8);
-        let a: uint8x16x2_t = transmute(vals);
-        let mut tmp = [0_u8; 32];
-        vst1q_u8_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint8x16x2_t = vld1q_u8_x2(tmp.as_ptr().cast());
-        let out: [u8; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u8_x3() {
-        let vals: [u8; 48] = crate::array::from_fn(|i| i as u8);
-        let a: uint8x16x3_t = transmute(vals);
-        let mut tmp = [0_u8; 48];
-        vst1q_u8_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint8x16x3_t = vld1q_u8_x3(tmp.as_ptr().cast());
-        let out: [u8; 48] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u8_x4() {
-        let vals: [u8; 64] = crate::array::from_fn(|i| i as u8);
-        let a: uint8x16x4_t = transmute(vals);
-        let mut tmp = [0_u8; 64];
-        vst1q_u8_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint8x16x4_t = vld1q_u8_x4(tmp.as_ptr().cast());
-        let out: [u8; 64] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u16_x2() {
-        let vals: [u16; 8] = crate::array::from_fn(|i| i as u16);
-        let a: uint16x4x2_t = transmute(vals);
-        let mut tmp = [0_u16; 8];
-        vst1_u16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint16x4x2_t = vld1_u16_x2(tmp.as_ptr().cast());
-        let out: [u16; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u16_x3() {
-        let vals: [u16; 12] = crate::array::from_fn(|i| i as u16);
-        let a: uint16x4x3_t = transmute(vals);
-        let mut tmp = [0_u16; 12];
-        vst1_u16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint16x4x3_t = vld1_u16_x3(tmp.as_ptr().cast());
-        let out: [u16; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u16_x4() {
-        let vals: [u16; 16] = crate::array::from_fn(|i| i as u16);
-        let a: uint16x4x4_t = transmute(vals);
-        let mut tmp = [0_u16; 16];
-        vst1_u16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint16x4x4_t = vld1_u16_x4(tmp.as_ptr().cast());
-        let out: [u16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u16_x2() {
-        let vals: [u16; 16] = crate::array::from_fn(|i| i as u16);
-        let a: uint16x8x2_t = transmute(vals);
-        let mut tmp = [0_u16; 16];
-        vst1q_u16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint16x8x2_t = vld1q_u16_x2(tmp.as_ptr().cast());
-        let out: [u16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u16_x3() {
-        let vals: [u16; 24] = crate::array::from_fn(|i| i as u16);
-        let a: uint16x8x3_t = transmute(vals);
-        let mut tmp = [0_u16; 24];
-        vst1q_u16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint16x8x3_t = vld1q_u16_x3(tmp.as_ptr().cast());
-        let out: [u16; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u16_x4() {
-        let vals: [u16; 32] = crate::array::from_fn(|i| i as u16);
-        let a: uint16x8x4_t = transmute(vals);
-        let mut tmp = [0_u16; 32];
-        vst1q_u16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint16x8x4_t = vld1q_u16_x4(tmp.as_ptr().cast());
-        let out: [u16; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u32_x2() {
-        let vals: [u32; 4] = crate::array::from_fn(|i| i as u32);
-        let a: uint32x2x2_t = transmute(vals);
-        let mut tmp = [0_u32; 4];
-        vst1_u32_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint32x2x2_t = vld1_u32_x2(tmp.as_ptr().cast());
-        let out: [u32; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u32_x3() {
-        let vals: [u32; 6] = crate::array::from_fn(|i| i as u32);
-        let a: uint32x2x3_t = transmute(vals);
-        let mut tmp = [0_u32; 6];
-        vst1_u32_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint32x2x3_t = vld1_u32_x3(tmp.as_ptr().cast());
-        let out: [u32; 6] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u32_x4() {
-        let vals: [u32; 8] = crate::array::from_fn(|i| i as u32);
-        let a: uint32x2x4_t = transmute(vals);
-        let mut tmp = [0_u32; 8];
-        vst1_u32_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint32x2x4_t = vld1_u32_x4(tmp.as_ptr().cast());
-        let out: [u32; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u32_x2() {
-        let vals: [u32; 8] = crate::array::from_fn(|i| i as u32);
-        let a: uint32x4x2_t = transmute(vals);
-        let mut tmp = [0_u32; 8];
-        vst1q_u32_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint32x4x2_t = vld1q_u32_x2(tmp.as_ptr().cast());
-        let out: [u32; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u32_x3() {
-        let vals: [u32; 12] = crate::array::from_fn(|i| i as u32);
-        let a: uint32x4x3_t = transmute(vals);
-        let mut tmp = [0_u32; 12];
-        vst1q_u32_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint32x4x3_t = vld1q_u32_x3(tmp.as_ptr().cast());
-        let out: [u32; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u32_x4() {
-        let vals: [u32; 16] = crate::array::from_fn(|i| i as u32);
-        let a: uint32x4x4_t = transmute(vals);
-        let mut tmp = [0_u32; 16];
-        vst1q_u32_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint32x4x4_t = vld1q_u32_x4(tmp.as_ptr().cast());
-        let out: [u32; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u64_x2() {
-        let vals: [u64; 2] = crate::array::from_fn(|i| i as u64);
-        let a: uint64x1x2_t = transmute(vals);
-        let mut tmp = [0_u64; 2];
-        vst1_u64_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint64x1x2_t = vld1_u64_x2(tmp.as_ptr().cast());
-        let out: [u64; 2] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u64_x3() {
-        let vals: [u64; 3] = crate::array::from_fn(|i| i as u64);
-        let a: uint64x1x3_t = transmute(vals);
-        let mut tmp = [0_u64; 3];
-        vst1_u64_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint64x1x3_t = vld1_u64_x3(tmp.as_ptr().cast());
-        let out: [u64; 3] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_u64_x4() {
-        let vals: [u64; 4] = crate::array::from_fn(|i| i as u64);
-        let a: uint64x1x4_t = transmute(vals);
-        let mut tmp = [0_u64; 4];
-        vst1_u64_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint64x1x4_t = vld1_u64_x4(tmp.as_ptr().cast());
-        let out: [u64; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u64_x2() {
-        let vals: [u64; 4] = crate::array::from_fn(|i| i as u64);
-        let a: uint64x2x2_t = transmute(vals);
-        let mut tmp = [0_u64; 4];
-        vst1q_u64_x2(tmp.as_mut_ptr().cast(), a);
-        let r: uint64x2x2_t = vld1q_u64_x2(tmp.as_ptr().cast());
-        let out: [u64; 4] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u64_x3() {
-        let vals: [u64; 6] = crate::array::from_fn(|i| i as u64);
-        let a: uint64x2x3_t = transmute(vals);
-        let mut tmp = [0_u64; 6];
-        vst1q_u64_x3(tmp.as_mut_ptr().cast(), a);
-        let r: uint64x2x3_t = vld1q_u64_x3(tmp.as_ptr().cast());
-        let out: [u64; 6] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_u64_x4() {
-        let vals: [u64; 8] = crate::array::from_fn(|i| i as u64);
-        let a: uint64x2x4_t = transmute(vals);
-        let mut tmp = [0_u64; 8];
-        vst1q_u64_x4(tmp.as_mut_ptr().cast(), a);
-        let r: uint64x2x4_t = vld1q_u64_x4(tmp.as_ptr().cast());
-        let out: [u64; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_p8_x2() {
-        let vals: [p8; 16] = crate::array::from_fn(|i| i as p8);
-        let a: poly8x8x2_t = transmute(vals);
-        let mut tmp = [0 as p8; 16];
-        vst1_p8_x2(tmp.as_mut_ptr().cast(), a);
-        let r: poly8x8x2_t = vld1_p8_x2(tmp.as_ptr().cast());
-        let out: [p8; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_p8_x3() {
-        let vals: [p8; 24] = crate::array::from_fn(|i| i as p8);
-        let a: poly8x8x3_t = transmute(vals);
-        let mut tmp = [0 as p8; 24];
-        vst1_p8_x3(tmp.as_mut_ptr().cast(), a);
-        let r: poly8x8x3_t = vld1_p8_x3(tmp.as_ptr().cast());
-        let out: [p8; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_p8_x4() {
-        let vals: [p8; 32] = crate::array::from_fn(|i| i as p8);
-        let a: poly8x8x4_t = transmute(vals);
-        let mut tmp = [0 as p8; 32];
-        vst1_p8_x4(tmp.as_mut_ptr().cast(), a);
-        let r: poly8x8x4_t = vld1_p8_x4(tmp.as_ptr().cast());
-        let out: [p8; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_p8_x2() {
-        let vals: [p8; 32] = crate::array::from_fn(|i| i as p8);
-        let a: poly8x16x2_t = transmute(vals);
-        let mut tmp = [0 as p8; 32];
-        vst1q_p8_x2(tmp.as_mut_ptr().cast(), a);
-        let r: poly8x16x2_t = vld1q_p8_x2(tmp.as_ptr().cast());
-        let out: [p8; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_p8_x3() {
-        let vals: [p8; 48] = crate::array::from_fn(|i| i as p8);
-        let a: poly8x16x3_t = transmute(vals);
-        let mut tmp = [0 as p8; 48];
-        vst1q_p8_x3(tmp.as_mut_ptr().cast(), a);
-        let r: poly8x16x3_t = vld1q_p8_x3(tmp.as_ptr().cast());
-        let out: [p8; 48] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_p8_x4() {
-        let vals: [p8; 64] = crate::array::from_fn(|i| i as p8);
-        let a: poly8x16x4_t = transmute(vals);
-        let mut tmp = [0 as p8; 64];
-        vst1q_p8_x4(tmp.as_mut_ptr().cast(), a);
-        let r: poly8x16x4_t = vld1q_p8_x4(tmp.as_ptr().cast());
-        let out: [p8; 64] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_p16_x2() {
-        let vals: [p16; 8] = crate::array::from_fn(|i| i as p16);
-        let a: poly16x4x2_t = transmute(vals);
-        let mut tmp = [0 as p16; 8];
-        vst1_p16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: poly16x4x2_t = vld1_p16_x2(tmp.as_ptr().cast());
-        let out: [p16; 8] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_p16_x3() {
-        let vals: [p16; 12] = crate::array::from_fn(|i| i as p16);
-        let a: poly16x4x3_t = transmute(vals);
-        let mut tmp = [0 as p16; 12];
-        vst1_p16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: poly16x4x3_t = vld1_p16_x3(tmp.as_ptr().cast());
-        let out: [p16; 12] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1_p16_x4() {
-        let vals: [p16; 16] = crate::array::from_fn(|i| i as p16);
-        let a: poly16x4x4_t = transmute(vals);
-        let mut tmp = [0 as p16; 16];
-        vst1_p16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: poly16x4x4_t = vld1_p16_x4(tmp.as_ptr().cast());
-        let out: [p16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_p16_x2() {
-        let vals: [p16; 16] = crate::array::from_fn(|i| i as p16);
-        let a: poly16x8x2_t = transmute(vals);
-        let mut tmp = [0 as p16; 16];
-        vst1q_p16_x2(tmp.as_mut_ptr().cast(), a);
-        let r: poly16x8x2_t = vld1q_p16_x2(tmp.as_ptr().cast());
-        let out: [p16; 16] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_p16_x3() {
-        let vals: [p16; 24] = crate::array::from_fn(|i| i as p16);
-        let a: poly16x8x3_t = transmute(vals);
-        let mut tmp = [0 as p16; 24];
-        vst1q_p16_x3(tmp.as_mut_ptr().cast(), a);
-        let r: poly16x8x3_t = vld1q_p16_x3(tmp.as_ptr().cast());
-        let out: [p16; 24] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3);
     }
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vld1q_p16_x4() {
-        let vals: [p16; 32] = crate::array::from_fn(|i| i as p16);
-        let a: poly16x8x4_t = transmute(vals);
-        let mut tmp = [0 as p16; 32];
-        vst1q_p16_x4(tmp.as_mut_ptr().cast(), a);
-        let r: poly16x8x4_t = vld1q_p16_x4(tmp.as_ptr().cast());
-        let out: [p16; 32] = transmute(r);
-        assert_eq!(out, vals);
+        wide_store_load_roundtrip!(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4);
     }
 }
 

From 5787838c05d0f2805ca9562fdab340f6a33dd15a Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 1 Feb 2026 14:17:35 +0100
Subject: [PATCH 124/326] use more capable macro for wide store/load roundtrip
 tests

---
 crates/core_arch/src/aarch64/neon/mod.rs | 470 ++++++-----------------
 1 file changed, 109 insertions(+), 361 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index ee27bef973..580f203ef0 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -1006,400 +1006,148 @@ mod tests {
         };
     }
 
-    #[simd_test(enable = "neon,fp16")]
-    #[cfg(not(target_arch = "arm64ec"))]
-    unsafe fn test_vld1_f16_x2() {
-        wide_store_load_roundtrip!(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2);
-    }
-
-    #[simd_test(enable = "neon,fp16")]
-    #[cfg(not(target_arch = "arm64ec"))]
-    unsafe fn test_vld1_f16_x3() {
-        wide_store_load_roundtrip!(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3);
-    }
-
-    #[simd_test(enable = "neon,fp16")]
-    #[cfg(not(target_arch = "arm64ec"))]
-    unsafe fn test_vld1_f16_x4() {
-        wide_store_load_roundtrip!(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4);
-    }
-
-    #[simd_test(enable = "neon,fp16")]
-    #[cfg(not(target_arch = "arm64ec"))]
-    unsafe fn test_vld1q_f16_x2() {
-        wide_store_load_roundtrip!(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2);
-    }
-
-    #[simd_test(enable = "neon,fp16")]
-    #[cfg(not(target_arch = "arm64ec"))]
-    unsafe fn test_vld1q_f16_x3() {
-        wide_store_load_roundtrip!(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3);
-    }
-
-    #[simd_test(enable = "neon,fp16")]
-    #[cfg(not(target_arch = "arm64ec"))]
-    unsafe fn test_vld1q_f16_x4() {
-        wide_store_load_roundtrip!(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_f32_x2() {
-        wide_store_load_roundtrip!(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_f32_x3() {
-        wide_store_load_roundtrip!(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_f32_x4() {
-        wide_store_load_roundtrip!(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_f32_x2() {
-        wide_store_load_roundtrip!(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_f32_x3() {
-        wide_store_load_roundtrip!(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_f32_x4() {
-        wide_store_load_roundtrip!(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4);
-    }
-
-    #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_p64_x2() {
-        wide_store_load_roundtrip!(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2);
-    }
-
-    #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_p64_x3() {
-        wide_store_load_roundtrip!(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3);
-    }
-
-    #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_p64_x4() {
-        wide_store_load_roundtrip!(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4);
-    }
-
-    #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_p64_x2() {
-        wide_store_load_roundtrip!(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2);
-    }
-
-    #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_p64_x3() {
-        wide_store_load_roundtrip!(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3);
-    }
-
-    #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_p64_x4() {
-        wide_store_load_roundtrip!(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s8_x2() {
-        wide_store_load_roundtrip!(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s8_x3() {
-        wide_store_load_roundtrip!(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s8_x4() {
-        wide_store_load_roundtrip!(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s8_x2() {
-        wide_store_load_roundtrip!(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s8_x3() {
-        wide_store_load_roundtrip!(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s8_x4() {
-        wide_store_load_roundtrip!(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s16_x2() {
-        wide_store_load_roundtrip!(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s16_x3() {
-        wide_store_load_roundtrip!(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s16_x4() {
-        wide_store_load_roundtrip!(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s16_x2() {
-        wide_store_load_roundtrip!(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s16_x3() {
-        wide_store_load_roundtrip!(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s16_x4() {
-        wide_store_load_roundtrip!(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s32_x2() {
-        wide_store_load_roundtrip!(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s32_x3() {
-        wide_store_load_roundtrip!(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s32_x4() {
-        wide_store_load_roundtrip!(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s32_x2() {
-        wide_store_load_roundtrip!(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s32_x3() {
-        wide_store_load_roundtrip!(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s32_x4() {
-        wide_store_load_roundtrip!(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s64_x2() {
-        wide_store_load_roundtrip!(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s64_x3() {
-        wide_store_load_roundtrip!(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_s64_x4() {
-        wide_store_load_roundtrip!(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s64_x2() {
-        wide_store_load_roundtrip!(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s64_x3() {
-        wide_store_load_roundtrip!(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_s64_x4() {
-        wide_store_load_roundtrip!(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u8_x2() {
-        wide_store_load_roundtrip!(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u8_x3() {
-        wide_store_load_roundtrip!(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u8_x4() {
-        wide_store_load_roundtrip!(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u8_x2() {
-        wide_store_load_roundtrip!(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u8_x3() {
-        wide_store_load_roundtrip!(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u8_x4() {
-        wide_store_load_roundtrip!(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u16_x2() {
-        wide_store_load_roundtrip!(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2);
+    macro_rules! wide_store_load_roundtrip_fp16 {
+        ($( $name:ident $args:tt);* $(;)?) => {
+            $(
+                #[simd_test(enable = "neon,fp16")]
+                #[cfg(not(target_arch = "arm64ec"))]
+                unsafe fn $name() {
+                    wide_store_load_roundtrip! $args;
+                }
+            )*
+        };
     }
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u16_x3() {
-        wide_store_load_roundtrip!(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3);
-    }
+    wide_store_load_roundtrip_fp16! {
+        test_vld1_f16_x2(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2);
+        test_vld1_f16_x3(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3);
+        test_vld1_f16_x4(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u16_x4() {
-        wide_store_load_roundtrip!(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4);
+        test_vld1q_f16_x2(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2);
+        test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3);
+        test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4);
     }
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u16_x2() {
-        wide_store_load_roundtrip!(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2);
+    macro_rules! wide_store_load_roundtrip_aes {
+        ($( $name:ident $args:tt);* $(;)?) => {
+            $(
+                #[simd_test(enable = "neon,aes")]
+                unsafe fn $name() {
+                    wide_store_load_roundtrip! $args;
+                }
+            )*
+        };
     }
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u16_x3() {
-        wide_store_load_roundtrip!(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3);
-    }
+    wide_store_load_roundtrip_aes! {
+        test_vld1_p64_x2(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2);
+        test_vld1_p64_x3(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3);
+        test_vld1_p64_x4(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u16_x4() {
-        wide_store_load_roundtrip!(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4);
+        test_vld1q_p64_x2(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2);
+        test_vld1q_p64_x3(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3);
+        test_vld1q_p64_x4(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4);
     }
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u32_x2() {
-        wide_store_load_roundtrip!(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2);
+    macro_rules! wide_store_load_roundtrip_neon {
+        ($( $name:ident $args:tt);* $(;)?) => {
+            $(
+                #[simd_test(enable = "neon")]
+                unsafe fn $name() {
+                    wide_store_load_roundtrip! $args;
+                }
+            )*
+        };
     }
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u32_x3() {
-        wide_store_load_roundtrip!(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3);
-    }
+    wide_store_load_roundtrip_neon! {
+        test_vld1_f32_x2(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2);
+        test_vld1_f32_x3(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3);
+        test_vld1_f32_x4(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u32_x4() {
-        wide_store_load_roundtrip!(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4);
-    }
+        test_vld1q_f32_x2(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2);
+        test_vld1q_f32_x3(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3);
+        test_vld1q_f32_x4(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u32_x2() {
-        wide_store_load_roundtrip!(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2);
-    }
+        test_vld1_s8_x2(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2);
+        test_vld1_s8_x3(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3);
+        test_vld1_s8_x4(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u32_x3() {
-        wide_store_load_roundtrip!(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3);
-    }
+        test_vld1q_s8_x2(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2);
+        test_vld1q_s8_x3(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3);
+        test_vld1q_s8_x4(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u32_x4() {
-        wide_store_load_roundtrip!(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4);
-    }
+        test_vld1_s16_x2(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2);
+        test_vld1_s16_x3(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3);
+        test_vld1_s16_x4(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u64_x2() {
-        wide_store_load_roundtrip!(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2);
-    }
+        test_vld1q_s16_x2(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2);
+        test_vld1q_s16_x3(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3);
+        test_vld1q_s16_x4(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u64_x3() {
-        wide_store_load_roundtrip!(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3);
-    }
+        test_vld1_s32_x2(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2);
+        test_vld1_s32_x3(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3);
+        test_vld1_s32_x4(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_u64_x4() {
-        wide_store_load_roundtrip!(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4);
-    }
+        test_vld1q_s32_x2(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2);
+        test_vld1q_s32_x3(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3);
+        test_vld1q_s32_x4(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u64_x2() {
-        wide_store_load_roundtrip!(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2);
-    }
+        test_vld1_s64_x2(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2);
+        test_vld1_s64_x3(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3);
+        test_vld1_s64_x4(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u64_x3() {
-        wide_store_load_roundtrip!(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3);
-    }
+        test_vld1q_s64_x2(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2);
+        test_vld1q_s64_x3(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3);
+        test_vld1q_s64_x4(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_u64_x4() {
-        wide_store_load_roundtrip!(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4);
-    }
+        test_vld1_u8_x2(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2);
+        test_vld1_u8_x3(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3);
+        test_vld1_u8_x4(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_p8_x2() {
-        wide_store_load_roundtrip!(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2);
-    }
+        test_vld1q_u8_x2(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2);
+        test_vld1q_u8_x3(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3);
+        test_vld1q_u8_x4(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_p8_x3() {
-        wide_store_load_roundtrip!(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3);
-    }
+        test_vld1_u16_x2(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2);
+        test_vld1_u16_x3(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3);
+        test_vld1_u16_x4(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_p8_x4() {
-        wide_store_load_roundtrip!(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4);
-    }
+        test_vld1q_u16_x2(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2);
+        test_vld1q_u16_x3(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3);
+        test_vld1q_u16_x4(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_p8_x2() {
-        wide_store_load_roundtrip!(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2);
-    }
+        test_vld1_u32_x2(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2);
+        test_vld1_u32_x3(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3);
+        test_vld1_u32_x4(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_p8_x3() {
-        wide_store_load_roundtrip!(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3);
-    }
+        test_vld1q_u32_x2(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2);
+        test_vld1q_u32_x3(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3);
+        test_vld1q_u32_x4(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_p8_x4() {
-        wide_store_load_roundtrip!(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4);
-    }
+        test_vld1_u64_x2(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2);
+        test_vld1_u64_x3(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3);
+        test_vld1_u64_x4(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_p16_x2() {
-        wide_store_load_roundtrip!(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2);
-    }
+        test_vld1q_u64_x2(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2);
+        test_vld1q_u64_x3(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3);
+        test_vld1q_u64_x4(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_p16_x3() {
-        wide_store_load_roundtrip!(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3);
-    }
+        test_vld1_p8_x2(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2);
+        test_vld1_p8_x3(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3);
+        test_vld1_p8_x4(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_p16_x4() {
-        wide_store_load_roundtrip!(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4);
-    }
+        test_vld1q_p8_x2(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2);
+        test_vld1q_p8_x3(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3);
+        test_vld1q_p8_x4(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_p16_x2() {
-        wide_store_load_roundtrip!(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2);
-    }
+        test_vld1_p16_x2(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2);
+        test_vld1_p16_x3(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3);
+        test_vld1_p16_x4(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4);
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_p16_x3() {
-        wide_store_load_roundtrip!(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_p16_x4() {
-        wide_store_load_roundtrip!(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4);
+        test_vld1q_p16_x2(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2);
+        test_vld1q_p16_x3(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3);
+        test_vld1q_p16_x4(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4);
     }
 }
 

From 1a3a6b2dce48c816b4a18920471d1342bbf35b72 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 1 Feb 2026 01:40:06 +0100
Subject: [PATCH 125/326] Revert "Use LLVM intrinsics for `madd` intrinsics"

This reverts commit 32146718741ee22ff0d54d21b9ab60353014c980.
---
 crates/core_arch/src/x86/avx2.rs     | 26 ++++-------
 crates/core_arch/src/x86/avx512bw.rs | 64 +++++++++++++++-------------
 crates/core_arch/src/x86/sse2.rs     | 26 ++++-------
 3 files changed, 53 insertions(+), 63 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 83aef753c9..8e9a56bb85 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -1841,20 +1841,14 @@ pub const fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) ->
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
-    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
-    //
-    // ```rust
-    // #[target_feature(enable = "avx2")]
-    // unsafe fn widening_add(mad: __m256i) -> __m256i {
-    //     _mm256_madd_epi16(mad, _mm256_set1_epi16(1))
-    // }
-    // ```
-    //
-    // If we implement this using generic vector intrinsics, the optimizer
-    // will eliminate this pattern, and `vpmaddwd` will no longer be emitted.
-    // For this reason, we use x86 intrinsics.
-    unsafe { transmute(pmaddwd(a.as_i16x16(), b.as_i16x16())) }
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
+    unsafe {
+        let r: i32x16 = simd_mul(simd_cast(a.as_i16x16()), simd_cast(b.as_i16x16()));
+        let even: i32x8 = simd_shuffle!(r, r, [0, 2, 4, 6, 8, 10, 12, 14]);
+        let odd: i32x8 = simd_shuffle!(r, r, [1, 3, 5, 7, 9, 11, 13, 15]);
+        simd_add(even, odd).as_m256i()
+    }
 }
 
 /// Vertically multiplies each unsigned 8-bit integer from `a` with the
@@ -3819,8 +3813,6 @@ pub const fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
 
 #[allow(improper_ctypes)]
 unsafe extern "C" {
-    #[link_name = "llvm.x86.avx2.pmadd.wd"]
-    fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
     fn pmaddubsw(a: u8x32, b: i8x32) -> i16x16;
     #[link_name = "llvm.x86.avx2.mpsadbw"]
@@ -4669,7 +4661,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    fn test_mm256_madd_epi16() {
+    const fn test_mm256_madd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_madd_epi16(a, b);
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 8e074fdcfa..e2d12cd972 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6321,20 +6321,22 @@ pub const unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a:
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
-    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
-    //
-    // ```rust
-    // #[target_feature(enable = "avx512bw")]
-    // unsafe fn widening_add(mad: __m512i) -> __m512i {
-    //     _mm512_madd_epi16(mad, _mm512_set1_epi16(1))
-    // }
-    // ```
-    //
-    // If we implement this using generic vector intrinsics, the optimizer
-    // will eliminate this pattern, and `vpmaddwd` will no longer be emitted.
-    // For this reason, we use x86 intrinsics.
-    unsafe { transmute(vpmaddwd(a.as_i16x32(), b.as_i16x32())) }
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
+    unsafe {
+        let r: i32x32 = simd_mul(simd_cast(a.as_i16x32()), simd_cast(b.as_i16x32()));
+        let even: i32x16 = simd_shuffle!(
+            r,
+            r,
+            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
+        );
+        let odd: i32x16 = simd_shuffle!(
+            r,
+            r,
+            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
+        );
+        simd_add(even, odd).as_m512i()
+    }
 }
 
 /// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6344,7 +6346,8 @@ pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, src.as_i32x16()))
@@ -6358,7 +6361,8 @@ pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, i32x16::ZERO))
@@ -6372,7 +6376,8 @@ pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, src.as_i32x8()))
@@ -6386,7 +6391,8 @@ pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, i32x8::ZERO))
@@ -6400,7 +6406,8 @@ pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, src.as_i32x4()))
@@ -6414,7 +6421,8 @@ pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) ->
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, i32x4::ZERO))
@@ -12574,8 +12582,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.pmul.hr.sw.512"]
     fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32;
 
-    #[link_name = "llvm.x86.avx512.pmaddw.d.512"]
-    fn vpmaddwd(a: i16x32, b: i16x32) -> i32x16;
     #[link_name = "llvm.x86.avx512.pmaddubs.w.512"]
     fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32;
 
@@ -17500,7 +17506,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_madd_epi16() {
+    const fn test_mm512_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_madd_epi16(a, b);
@@ -17509,7 +17515,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_mask_madd_epi16() {
+    const fn test_mm512_mask_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_madd_epi16(a, 0, a, b);
@@ -17537,7 +17543,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_maskz_madd_epi16() {
+    const fn test_mm512_maskz_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_madd_epi16(0, a, b);
@@ -17548,7 +17554,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_mask_madd_epi16() {
+    const fn test_mm256_mask_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_madd_epi16(a, 0, a, b);
@@ -17568,7 +17574,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_maskz_madd_epi16() {
+    const fn test_mm256_maskz_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_madd_epi16(0, a, b);
@@ -17579,7 +17585,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_mask_madd_epi16() {
+    const fn test_mm_mask_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_madd_epi16(a, 0, a, b);
@@ -17590,7 +17596,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_maskz_madd_epi16() {
+    const fn test_mm_maskz_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_madd_epi16(0, a, b);
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index f339a003df..ecd478511b 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -210,20 +210,14 @@ pub const fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
-    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
-    //
-    // ```rust
-    // #[target_feature(enable = "sse2")]
-    // unsafe fn widening_add(mad: __m128i) -> __m128i {
-    //     _mm_madd_epi16(mad, _mm_set1_epi16(1))
-    // }
-    // ```
-    //
-    // If we implement this using generic vector intrinsics, the optimizer
-    // will eliminate this pattern, and `pmaddwd` will no longer be emitted.
-    // For this reason, we use x86 intrinsics.
-    unsafe { transmute(pmaddwd(a.as_i16x8(), b.as_i16x8())) }
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
+    unsafe {
+        let r: i32x8 = simd_mul(simd_cast(a.as_i16x8()), simd_cast(b.as_i16x8()));
+        let even: i32x4 = simd_shuffle!(r, r, [0, 2, 4, 6]);
+        let odd: i32x4 = simd_shuffle!(r, r, [1, 3, 5, 7]);
+        simd_add(even, odd).as_m128i()
+    }
 }
 
 /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
@@ -3193,8 +3187,6 @@ unsafe extern "C" {
     fn lfence();
     #[link_name = "llvm.x86.sse2.mfence"]
     fn mfence();
-    #[link_name = "llvm.x86.sse2.pmadd.wd"]
-    fn pmaddwd(a: i16x8, b: i16x8) -> i32x4;
     #[link_name = "llvm.x86.sse2.psad.bw"]
     fn psadbw(a: u8x16, b: u8x16) -> u64x2;
     #[link_name = "llvm.x86.sse2.psll.w"]
@@ -3473,7 +3465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    fn test_mm_madd_epi16() {
+    const fn test_mm_madd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm_madd_epi16(a, b);

From 8a883ad68542301aad6e138cdd535cc1f2d410cd Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 1 Feb 2026 01:52:52 +0100
Subject: [PATCH 126/326] add test for multiply by one pattern

---
 crates/core_arch/src/x86/avx2.rs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 8e9a56bb85..e9463d4331 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -4669,6 +4669,16 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
+    #[target_feature(enable = "avx2")]
+    #[cfg_attr(test, assert_instr(vpmaddwd))]
+    unsafe fn test_mm256_madd_epi16_mul_one(mad: __m256i) -> __m256i {
+        // This is a trick used in the adler32 algorithm to get a widening addition. The
+        // multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd
+        // instruction is no longer selected. The assert_instr verifies that this is the case.
+        let one_v = _mm256_set1_epi16(1);
+        _mm256_madd_epi16(mad, one_v)
+    }
+
     #[simd_test(enable = "avx2")]
     const fn test_mm256_inserti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);

From 978690223d2963d04f3eca178dffa6f2ba086272 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Thu, 11 Sep 2025 10:06:04 +0800
Subject: [PATCH 127/326] loongarch: Sync SIMD intrinsics with C

---
 .../src/loongarch64/lasx/generated.rs         | 166 ++++++++++-
 .../core_arch/src/loongarch64/lasx/tests.rs   | 281 ++++++++++++++++++
 .../src/loongarch64/lsx/generated.rs          |   4 +-
 crates/stdarch-gen-loongarch/lasx.spec        |  92 +++++-
 crates/stdarch-gen-loongarch/lasxintrin.h     | 164 +++++++++-
 crates/stdarch-gen-loongarch/lsx.spec         |   2 +-
 crates/stdarch-gen-loongarch/lsxintrin.h      |   8 +-
 crates/stdarch-gen-loongarch/src/main.rs      |   6 +-
 8 files changed, 708 insertions(+), 15 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index cda0ebec67..1d9d4e8248 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -7,7 +7,7 @@
 // ```
 
 use crate::mem::transmute;
-use super::types::*;
+use super::super::*;
 
 #[allow(improper_ctypes)]
 unsafe extern "unadjusted" {
@@ -980,7 +980,7 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.loongarch.lasx.xvssrln.w.d"]
     fn __lasx_xvssrln_w_d(a: __v4i64, b: __v4i64) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvorn.v"]
-    fn __lasx_xvorn_v(a: __v32i8, b: __v32i8) -> __v32i8;
+    fn __lasx_xvorn_v(a: __v32u8, b: __v32u8) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvldi"]
     fn __lasx_xvldi(a: i32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvldx"]
@@ -1491,6 +1491,42 @@ unsafe extern "unadjusted" {
     fn __lasx_xvrepli_h(a: i32) -> __v16i16;
     #[link_name = "llvm.loongarch.lasx.xvrepli.w"]
     fn __lasx_xvrepli_w(a: i32) -> __v8i32;
+    #[link_name = "llvm.loongarch.lasx.cast.128.s"]
+    fn __lasx_cast_128_s(a: __v4f32) -> __v8f32;
+    #[link_name = "llvm.loongarch.lasx.cast.128.d"]
+    fn __lasx_cast_128_d(a: __v2f64) -> __v4f64;
+    #[link_name = "llvm.loongarch.lasx.cast.128"]
+    fn __lasx_cast_128(a: __v2i64) -> __v4i64;
+    #[link_name = "llvm.loongarch.lasx.concat.128.s"]
+    fn __lasx_concat_128_s(a: __v4f32, b: __v4f32) -> __v8f32;
+    #[link_name = "llvm.loongarch.lasx.concat.128.d"]
+    fn __lasx_concat_128_d(a: __v2f64, b: __v2f64) -> __v4f64;
+    #[link_name = "llvm.loongarch.lasx.concat.128"]
+    fn __lasx_concat_128(a: __v2i64, b: __v2i64) -> __v4i64;
+    #[link_name = "llvm.loongarch.lasx.extract.128.lo.s"]
+    fn __lasx_extract_128_lo_s(a: __v8f32) -> __v4f32;
+    #[link_name = "llvm.loongarch.lasx.extract.128.hi.s"]
+    fn __lasx_extract_128_hi_s(a: __v8f32) -> __v4f32;
+    #[link_name = "llvm.loongarch.lasx.extract.128.lo.d"]
+    fn __lasx_extract_128_lo_d(a: __v4f64) -> __v2f64;
+    #[link_name = "llvm.loongarch.lasx.extract.128.hi.d"]
+    fn __lasx_extract_128_hi_d(a: __v4f64) -> __v2f64;
+    #[link_name = "llvm.loongarch.lasx.extract.128.lo"]
+    fn __lasx_extract_128_lo(a: __v4i64) -> __v2i64;
+    #[link_name = "llvm.loongarch.lasx.extract.128.hi"]
+    fn __lasx_extract_128_hi(a: __v4i64) -> __v2i64;
+    #[link_name = "llvm.loongarch.lasx.insert.128.lo.s"]
+    fn __lasx_insert_128_lo_s(a: __v8f32, b: __v4f32) -> __v8f32;
+    #[link_name = "llvm.loongarch.lasx.insert.128.hi.s"]
+    fn __lasx_insert_128_hi_s(a: __v8f32, b: __v4f32) -> __v8f32;
+    #[link_name = "llvm.loongarch.lasx.insert.128.lo.d"]
+    fn __lasx_insert_128_lo_d(a: __v4f64, b: __v2f64) -> __v4f64;
+    #[link_name = "llvm.loongarch.lasx.insert.128.hi.d"]
+    fn __lasx_insert_128_hi_d(a: __v4f64, b: __v2f64) -> __v4f64;
+    #[link_name = "llvm.loongarch.lasx.insert.128.lo"]
+    fn __lasx_insert_128_lo(a: __v4i64, b: __v2i64) -> __v4i64;
+    #[link_name = "llvm.loongarch.lasx.insert.128.hi"]
+    fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64;
 }
 
 #[inline]
@@ -7062,3 +7098,129 @@ pub fn lasx_xvrepli_w<const IMM_S10: i32>() -> m256i {
     static_assert_simm_bits!(IMM_S10, 10);
     unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) }
 }
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_cast_128_s(a: m128) -> m256 {
+    unsafe { transmute(__lasx_cast_128_s(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_cast_128_d(a: m128d) -> m256d {
+    unsafe { transmute(__lasx_cast_128_d(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_cast_128(a: m128i) -> m256i {
+    unsafe { transmute(__lasx_cast_128(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 {
+    unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d {
+    unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i {
+    unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_extract_128_lo_s(a: m256) -> m128 {
+    unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_extract_128_hi_s(a: m256) -> m128 {
+    unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_extract_128_lo_d(a: m256d) -> m128d {
+    unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_extract_128_hi_d(a: m256d) -> m128d {
+    unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_extract_128_lo(a: m256i) -> m128i {
+    unsafe { transmute(__lasx_extract_128_lo(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_extract_128_hi(a: m256i) -> m128i {
+    unsafe { transmute(__lasx_extract_128_hi(transmute(a))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 {
+    unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 {
+    unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d {
+    unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d {
+    unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i {
+    unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) }
+}
+
+#[inline]
+#[target_feature(enable = "lasx")]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i {
+    unsafe { transmute(__lasx_insert_128_hi(transmute(a), transmute(b))) }
+}
diff --git a/crates/core_arch/src/loongarch64/lasx/tests.rs b/crates/core_arch/src/loongarch64/lasx/tests.rs
index 54771d7b51..319ce7cf98 100644
--- a/crates/core_arch/src/loongarch64/lasx/tests.rs
+++ b/crates/core_arch/src/loongarch64/lasx/tests.rs
@@ -14756,3 +14756,284 @@ unsafe fn test_lasx_xvrepli_w() {
 
     assert_eq!(r, transmute(lasx_xvrepli_w::<-388>()));
 }
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_cast_128_s() {
+    let a = u32x4::new(1031165056, 1051966120, 1060984374, 1062536919);
+    let r = i64x4::new(4518160082931176576, 4563561318958585398, 1966080, 1966080);
+
+    assert_eq!(
+        r.as_array()[0..2],
+        transmute::<_, i64x4>(lasx_cast_128_s(transmute(a))).as_array()[0..2]
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_cast_128_d() {
+    let a = u64x2::new(4604694967937271251, 4600904075476555984);
+    let r = i64x4::new(
+        4604694967937271251,
+        4600904075476555984,
+        2910860781861170785,
+        8314045306847701346,
+    );
+
+    assert_eq!(
+        r.as_array()[0..2],
+        transmute::<_, i64x4>(lasx_cast_128_d(transmute(a))).as_array()[0..2]
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_cast_128() {
+    let a = i64x2::new(-5333716211868108402, 2442107533729495827);
+    let r = i64x4::new(
+        -5333716211868108402,
+        2442107533729495827,
+        -1115824375586394527,
+        8314045306157170687,
+    );
+
+    assert_eq!(
+        r.as_array()[0..2],
+        transmute::<_, i64x4>(lasx_cast_128(transmute(a))).as_array()[0..2]
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_concat_128_s() {
+    let a = u32x4::new(1032255272, 1059413818, 1058434362, 1041454056);
+    let b = u32x4::new(1047296252, 1059191602, 1051282752, 1026847376);
+    let r = i64x4::new(
+        4550147702272751400,
+        4473011111864986938,
+        4549193291835144444,
+        4410275898954698048,
+    );
+
+    assert_eq!(r, transmute(lasx_concat_128_s(transmute(a), transmute(b))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_concat_128_d() {
+    let a = u64x2::new(4602341404117999960, 4599751584045405722);
+    let b = u64x2::new(4595947342927040984, 4600308396523102002);
+    let r = i64x4::new(
+        4602341404117999960,
+        4599751584045405722,
+        4595947342927040984,
+        4600308396523102002,
+    );
+
+    assert_eq!(r, transmute(lasx_concat_128_d(transmute(a), transmute(b))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_concat_128() {
+    let a = i64x2::new(3302609705743394573, 8438855426868306143);
+    let b = i64x2::new(8632034656150002181, 7751541408133090748);
+    let r = i64x4::new(
+        3302609705743394573,
+        8438855426868306143,
+        8632034656150002181,
+        7751541408133090748,
+    );
+
+    assert_eq!(r, transmute(lasx_concat_128(transmute(a), transmute(b))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_extract_128_lo_s() {
+    let a = u32x8::new(
+        1038279272, 1053426270, 1062315532, 1055361088, 1061380448, 1052007748, 1063816577,
+        1061671114,
+    );
+    let r = i64x2::new(4524431379435545192, 4532741359493293580);
+
+    assert_eq!(r, transmute(lasx_extract_128_lo_s(transmute(a))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_extract_128_hi_s() {
+    let a = u32x8::new(
+        1059517342, 1052723820, 1053176244, 1060336354, 1058221022, 1064684502, 1061072013,
+        1059238420,
+    );
+    let r = i64x2::new(4572785117706267614, 4549394373627784333);
+
+    assert_eq!(r, transmute(lasx_extract_128_hi_s(transmute(a))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_extract_128_lo_d() {
+    let a = u64x4::new(
+        4606487981487128637,
+        4592443779247846248,
+        4605637448543526041,
+        4604126872543611047,
+    );
+    let r = i64x2::new(4606487981487128637, 4592443779247846248);
+
+    assert_eq!(r, transmute(lasx_extract_128_lo_d(transmute(a))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_extract_128_hi_d() {
+    let a = u64x4::new(
+        4595075050683709816,
+        4603388454656549851,
+        4603881047625519227,
+        4604218419306666352,
+    );
+    let r = i64x2::new(4603881047625519227, 4604218419306666352);
+
+    assert_eq!(r, transmute(lasx_extract_128_hi_d(transmute(a))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_extract_128_lo() {
+    let a = i64x4::new(
+        1690990426210778543,
+        -1056924033489771427,
+        1791197928200737608,
+        2648792885519901423,
+    );
+    let r = i64x2::new(1690990426210778543, -1056924033489771427);
+
+    assert_eq!(r, transmute(lasx_extract_128_lo(transmute(a))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_extract_128_hi() {
+    let a = i64x4::new(
+        1400282616691463341,
+        6677577875527300174,
+        -1903780563362068813,
+        -7449796170151383489,
+    );
+    let r = i64x2::new(-1903780563362068813, -7449796170151383489);
+
+    assert_eq!(r, transmute(lasx_extract_128_hi(transmute(a))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_insert_128_lo_s() {
+    let a = u32x8::new(
+        1063338913, 1017815328, 1065051130, 1040694156, 1059596680, 1048796526, 1058020845,
+        1057822131,
+    );
+    let b = u32x4::new(1052930766, 1021556992, 1050709482, 1059704809);
+    let r = i64x4::new(
+        4387553872693064398,
+        4551397499119635946,
+        4504546780388010376,
+        4543311458688048621,
+    );
+
+    assert_eq!(
+        r,
+        transmute(lasx_insert_128_lo_s(transmute(a), transmute(b)))
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_insert_128_hi_s() {
+    let a = u32x8::new(
+        1018863744, 1064221149, 1048659080, 1057450774, 1049935896, 1034170664, 1059759433,
+        1057849762,
+    );
+    let b = u32x4::new(1060332648, 1063149600, 1051087106, 1060582348);
+    let r = i64x4::new(
+        4570795031685406848,
+        4541716492508546184,
+        4566192763815814248,
+        4555166500425978114,
+    );
+
+    assert_eq!(
+        r,
+        transmute(lasx_insert_128_hi_s(transmute(a), transmute(b)))
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_insert_128_lo_d() {
+    let a = u64x4::new(
+        4601319519422109044,
+        4601506273633970188,
+        4605118087882201940,
+        4605125059076454256,
+    );
+    let b = u64x2::new(4587489919640425888, 4591909120489567808);
+    let r = i64x4::new(
+        4587489919640425888,
+        4591909120489567808,
+        4605118087882201940,
+        4605125059076454256,
+    );
+
+    assert_eq!(
+        r,
+        transmute(lasx_insert_128_lo_d(transmute(a), transmute(b)))
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_insert_128_hi_d() {
+    let a = u64x4::new(
+        4604690660177752777,
+        4593824994203592700,
+        4599958775071728504,
+        4604125324674373728,
+    );
+    let b = u64x2::new(4601718173474385938, 4591758028383494760);
+    let r = i64x4::new(
+        4604690660177752777,
+        4593824994203592700,
+        4601718173474385938,
+        4591758028383494760,
+    );
+
+    assert_eq!(
+        r,
+        transmute(lasx_insert_128_hi_d(transmute(a), transmute(b)))
+    );
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_insert_128_lo() {
+    let a = i64x4::new(
+        8159968186698006293,
+        5648210958959948409,
+        603295919044368378,
+        -4396186135186039276,
+    );
+    let b = i64x2::new(-6258666140812668387, 5822982556977506382);
+    let r = i64x4::new(
+        -6258666140812668387,
+        5822982556977506382,
+        603295919044368378,
+        -4396186135186039276,
+    );
+
+    assert_eq!(r, transmute(lasx_insert_128_lo(transmute(a), transmute(b))));
+}
+
+#[simd_test(enable = "lasx")]
+unsafe fn test_lasx_insert_128_hi() {
+    let a = i64x4::new(
+        2981835982487038158,
+        5258378092714202875,
+        5115371338527125146,
+        -6993491475145500537,
+    );
+    let b = i64x2::new(1176776599938765863, -7502655081590988207);
+    let r = i64x4::new(
+        2981835982487038158,
+        5258378092714202875,
+        1176776599938765863,
+        -7502655081590988207,
+    );
+
+    assert_eq!(r, transmute(lasx_insert_128_hi(transmute(a), transmute(b))));
+}
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 764e69ca05..25efaadb42 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -7,7 +7,7 @@
 // ```
 
 use crate::mem::transmute;
-use super::types::*;
+use super::super::*;
 
 #[allow(improper_ctypes)]
 unsafe extern "unadjusted" {
@@ -1324,7 +1324,7 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.loongarch.lsx.vssrln.w.d"]
     fn __lsx_vssrln_w_d(a: __v2i64, b: __v2i64) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vorn.v"]
-    fn __lsx_vorn_v(a: __v16i8, b: __v16i8) -> __v16i8;
+    fn __lsx_vorn_v(a: __v16u8, b: __v16u8) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vldi"]
     fn __lsx_vldi(a: i32) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vshuf.b"]
diff --git a/crates/stdarch-gen-loongarch/lasx.spec b/crates/stdarch-gen-loongarch/lasx.spec
index e3bdfcb5e9..ac4203a03f 100644
--- a/crates/stdarch-gen-loongarch/lasx.spec
+++ b/crates/stdarch-gen-loongarch/lasx.spec
@@ -2426,7 +2426,7 @@ data-types = V8SI, V4DI, V4DI
 /// lasx_xvorn_v
 name = lasx_xvorn_v
 asm-fmts = xd, xj, xk
-data-types = V32QI, V32QI, V32QI
+data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvldi
 name = lasx_xvldi
@@ -3703,3 +3703,93 @@ name = lasx_xvrepli_w
 asm-fmts = xd, si10
 data-types = V8SI, HI
 
+/// lasx_cast_128_s
+name = lasx_cast_128_s
+asm-fmts = xd, vj
+data-types = V8SF, V4SF
+
+/// lasx_cast_128_d
+name = lasx_cast_128_d
+asm-fmts = xd, vj
+data-types = V4DF, V2DF
+
+/// lasx_cast_128
+name = lasx_cast_128
+asm-fmts = xd, vj
+data-types = V4DI, V2DI
+
+/// lasx_concat_128_s
+name = lasx_concat_128_s
+asm-fmts = xd, vj, vk
+data-types = V8SF, V4SF, V4SF
+
+/// lasx_concat_128_d
+name = lasx_concat_128_d
+asm-fmts = xd, vj, vk
+data-types = V4DF, V2DF, V2DF
+
+/// lasx_concat_128
+name = lasx_concat_128
+asm-fmts = xd, vj, vk
+data-types = V4DI, V2DI, V2DI
+
+/// lasx_extract_128_lo_s
+name = lasx_extract_128_lo_s
+asm-fmts = vd, xj
+data-types = V4SF, V8SF
+
+/// lasx_extract_128_hi_s
+name = lasx_extract_128_hi_s
+asm-fmts = vd, xj
+data-types = V4SF, V8SF
+
+/// lasx_extract_128_lo_d
+name = lasx_extract_128_lo_d
+asm-fmts = vd, xj
+data-types = V2DF, V4DF
+
+/// lasx_extract_128_hi_d
+name = lasx_extract_128_hi_d
+asm-fmts = vd, xj
+data-types = V2DF, V4DF
+
+/// lasx_extract_128_lo
+name = lasx_extract_128_lo
+asm-fmts = vd, xj
+data-types = V2DI, V4DI
+
+/// lasx_extract_128_hi
+name = lasx_extract_128_hi
+asm-fmts = vd, xj
+data-types = V2DI, V4DI
+
+/// lasx_insert_128_lo_s
+name = lasx_insert_128_lo_s
+asm-fmts = xd, xj, vk
+data-types = V8SF, V8SF, V4SF
+
+/// lasx_insert_128_hi_s
+name = lasx_insert_128_hi_s
+asm-fmts = xd, xj, vk
+data-types = V8SF, V8SF, V4SF
+
+/// lasx_insert_128_lo_d
+name = lasx_insert_128_lo_d
+asm-fmts = xd, xj, vk
+data-types = V4DF, V4DF, V2DF
+
+/// lasx_insert_128_hi_d
+name = lasx_insert_128_hi_d
+asm-fmts = xd, xj, vk
+data-types = V4DF, V4DF, V2DF
+
+/// lasx_insert_128_lo
+name = lasx_insert_128_lo
+asm-fmts = xd, xj, vk
+data-types = V4DI, V4DI, V2DI
+
+/// lasx_insert_128_hi
+name = lasx_insert_128_hi
+asm-fmts = xd, xj, vk
+data-types = V4DI, V4DI, V2DI
+
diff --git a/crates/stdarch-gen-loongarch/lasxintrin.h b/crates/stdarch-gen-loongarch/lasxintrin.h
index c525b6106b..02bb97918d 100644
--- a/crates/stdarch-gen-loongarch/lasxintrin.h
+++ b/crates/stdarch-gen-loongarch/lasxintrin.h
@@ -1,10 +1,10 @@
 /*
- * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75
+ * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=c2013267642fea4a6e89b826940c8aa80a76089d
  */
 
 /* LARCH Loongson ASX intrinsics include file.
 
-   Copyright (C) 2018-2024 Free Software Foundation, Inc.
+   Copyright (C) 2018-2025 Free Software Foundation, Inc.
 
    This file is part of GCC.
 
@@ -27,6 +27,8 @@
    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    <http://www.gnu.org/licenses/>.  */
 
+#include <lsxintrin.h>
+
 #ifndef _GCC_LOONGSON_ASXINTRIN_H
 #define _GCC_LOONGSON_ASXINTRIN_H 1
 
@@ -3568,11 +3570,11 @@ __m256i __lasx_xvssrln_w_d (__m256i _1, __m256i _2)
 }
 
 /* Assembly instruction format:	xd, xj, xk.  */
-/* Data types in instruction templates:  V32QI, V32QI, V32QI.  */
+/* Data types in instruction templates:  UV32QI, UV32QI, UV32QI.  */
 extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __m256i __lasx_xvorn_v (__m256i _1, __m256i _2)
 {
-  return (__m256i)__builtin_lasx_xvorn_v ((v32i8)_1, (v32i8)_2);
+  return (__m256i)__builtin_lasx_xvorn_v ((v32u8)_1, (v32u8)_2);
 }
 
 /* Assembly instruction format:	xd, i13.  */
@@ -5372,5 +5374,159 @@ __m256i __lasx_xvfcmp_sun_s (__m256 _1, __m256 _2)
 #define __lasx_xvrepli_w(/*si10*/ _1) \
   ((__m256i)__builtin_lasx_xvrepli_w ((_1)))
 
+#if defined (__loongarch_asx_sx_conv)
+/* Add builtin interfaces for 128 and 256 vector conversions.
+   For the assembly instruction format of some functions of the following vector
+   conversion, it is not described exactly in accordance with the format of the
+   generated assembly instruction.
+   In the front end of the Rust language, different built-in functions are called
+   by analyzing the format of assembly instructions. The data types of instructions
+   are all defined based on the interfaces of the defined functions, in the
+   following order: output, input... .  */
+/* Assembly instruction format:	xd, vj.  */
+/* Data types in instruction templates:  V8SF, V4SF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256 __lasx_cast_128_s (__m128 _1)
+{
+  return  (__m256)__builtin_lasx_cast_128_s ((v4f32)_1);
+}
+
+/* Assembly instruction format:	xd, vj.  */
+/* Data types in instruction templates:  V4DF, V2DF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256d __lasx_cast_128_d (__m128d _1)
+{
+  return  (__m256d)__builtin_lasx_cast_128_d ((v2f64)_1);
+}
+
+/* Assembly instruction format:	xd, vj.  */
+/* Data types in instruction templates:  V4DI, V2DI.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256i __lasx_cast_128 (__m128i _1)
+{
+  return  (__m256i)__builtin_lasx_cast_128 ((v2i64)_1);
+}
+
+/* Assembly instruction format:	xd, vj, vk.  */
+/* Data types in instruction templates:  V8SF, V4SF, V4SF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256 __lasx_concat_128_s (__m128 _1, __m128 _2)
+{
+  return  (__m256)__builtin_lasx_concat_128_s ((v4f32)_1, (v4f32)_2);
+}
+
+/* Assembly instruction format:	xd, vj, vk.  */
+/* Data types in instruction templates:  V4DF, V2DF, V2DF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256d __lasx_concat_128_d (__m128d _1, __m128d _2)
+{
+  return  (__m256d)__builtin_lasx_concat_128_d ((v2f64)_1, (v2f64)_2);
+}
+
+/* Assembly instruction format:	xd, vj, vk.  */
+/* Data types in instruction templates:  V4DI, V2DI, V2DI.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256i __lasx_concat_128 (__m128i _1, __m128i _2)
+{
+  return  (__m256i)__builtin_lasx_concat_128 ((v2i64)_1, (v2i64)_2);
+}
+
+/* Assembly instruction format:	vd, xj.  */
+/* Data types in instruction templates:  V4SF, V8SF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m128 __lasx_extract_128_lo_s (__m256 _1)
+{
+  return  (__m128)__builtin_lasx_extract_128_lo_s ((v8f32)_1);
+}
+
+/* Assembly instruction format:	vd, xj.  */
+/* Data types in instruction templates:  V4SF, V8SF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m128 __lasx_extract_128_hi_s (__m256 _1)
+{
+  return  (__m128)__builtin_lasx_extract_128_hi_s ((v8f32)_1);
+}
+
+/* Assembly instruction format:	vd, xj.  */
+/* Data types in instruction templates:  V2DF, V4DF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m128d __lasx_extract_128_lo_d (__m256d _1)
+{
+  return  (__m128d)__builtin_lasx_extract_128_lo_d ((v4f64)_1);
+}
+
+/* Assembly instruction format:	vd, xj.  */
+/* Data types in instruction templates:  V2DF, V4DF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m128d __lasx_extract_128_hi_d (__m256d _1)
+{
+  return  (__m128d)__builtin_lasx_extract_128_hi_d ((v4f64)_1);
+}
+
+/* Assembly instruction format:	vd, xj.  */
+/* Data types in instruction templates:  V2DI, V4DI.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m128i __lasx_extract_128_lo (__m256i _1)
+{
+  return  (__m128i)__builtin_lasx_extract_128_lo ((v4i64)_1);
+}
+
+/* Assembly instruction format:	vd, xj.  */
+/* Data types in instruction templates:  V2DI, V4DI.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m128i __lasx_extract_128_hi (__m256i _1)
+{
+  return  (__m128i)__builtin_lasx_extract_128_hi ((v4i64)_1);
+}
+
+/* Assembly instruction format:	xd, xj, vk.  */
+/* Data types in instruction templates:  V8SF, V8SF, V4SF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256 __lasx_insert_128_lo_s (__m256 _1, __m128 _2)
+{
+  return  (__m256)__builtin_lasx_insert_128_lo_s ((v8f32)_1, (v4f32)_2);
+}
+
+/* Assembly instruction format:	xd, xj, vk.  */
+/* Data types in instruction templates:  V8SF, V8SF, V4SF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256 __lasx_insert_128_hi_s (__m256 _1, __m128 _2)
+{
+  return  (__m256)__builtin_lasx_insert_128_hi_s ((v8f32)_1, (v4f32)_2);
+}
+
+/* Assembly instruction format:	xd, xj, vk.  */
+/* Data types in instruction templates:  V4DF, V4DF, V2DF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256d __lasx_insert_128_lo_d (__m256d _1, __m128d _2)
+{
+  return  (__m256d)__builtin_lasx_insert_128_lo_d ((v4f64)_1, (v2f64)_2);
+}
+
+/* Assembly instruction format:	xd, xj, vk.  */
+/* Data types in instruction templates:  V4DF, V4DF, V2DF.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256d __lasx_insert_128_hi_d (__m256d _1, __m128d _2)
+{
+  return  (__m256d)__builtin_lasx_insert_128_hi_d ((v4f64)_1, (v2f64)_2);
+}
+
+/* Assembly instruction format:	xd, xj, vk.  */
+/* Data types in instruction templates:  V4DI, V4DI, V2DI.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256i __lasx_insert_128_lo (__m256i _1, __m128i _2)
+{
+  return  (__m256i)__builtin_lasx_insert_128_lo ((v4i64)_1, (v2i64)_2);
+}
+
+/* Assembly instruction format:	xd, xj, vk.  */
+/* Data types in instruction templates:  V4DI, V4DI, V2DI.  */
+extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__m256i __lasx_insert_128_hi (__m256i _1, __m128i _2)
+{
+  return  (__m256i)__builtin_lasx_insert_128_hi ((v4i64)_1, (v2i64)_2);
+}
+
+#endif /* defined(__loongarch_asx_sx_conv).  */
 #endif /* defined(__loongarch_asx).  */
 #endif /* _GCC_LOONGSON_ASXINTRIN_H.  */
diff --git a/crates/stdarch-gen-loongarch/lsx.spec b/crates/stdarch-gen-loongarch/lsx.spec
index dc835770d5..b5497b6e62 100644
--- a/crates/stdarch-gen-loongarch/lsx.spec
+++ b/crates/stdarch-gen-loongarch/lsx.spec
@@ -3286,7 +3286,7 @@ data-types = V4SI, V2DI, V2DI
 /// lsx_vorn_v
 name = lsx_vorn_v
 asm-fmts = vd, vj, vk
-data-types = V16QI, V16QI, V16QI
+data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vldi
 name = lsx_vldi
diff --git a/crates/stdarch-gen-loongarch/lsxintrin.h b/crates/stdarch-gen-loongarch/lsxintrin.h
index 943f2df913..66b7c7e218 100644
--- a/crates/stdarch-gen-loongarch/lsxintrin.h
+++ b/crates/stdarch-gen-loongarch/lsxintrin.h
@@ -1,10 +1,10 @@
 /*
- * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75
+ * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=6441eb6dc020faae0672ea724dfdb38c6a9bf6a1
  */
 
 /* LARCH Loongson SX intrinsics include file.
 
-   Copyright (C) 2018-2024 Free Software Foundation, Inc.
+   Copyright (C) 2018-2025 Free Software Foundation, Inc.
 
    This file is part of GCC.
 
@@ -4749,11 +4749,11 @@ __m128i __lsx_vssrln_w_d (__m128i _1, __m128i _2)
 }
 
 /* Assembly instruction format:	vd, vj, vk.  */
-/* Data types in instruction templates:  V16QI, V16QI, V16QI.  */
+/* Data types in instruction templates:  UV16QI, UV16QI, UV16QI.  */
 extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __m128i __lsx_vorn_v (__m128i _1, __m128i _2)
 {
-  return (__m128i)__builtin_lsx_vorn_v ((v16i8)_1, (v16i8)_2);
+  return (__m128i)__builtin_lsx_vorn_v ((v16u8)_1, (v16u8)_2);
 }
 
 /* Assembly instruction format:	vd, i13.  */
diff --git a/crates/stdarch-gen-loongarch/src/main.rs b/crates/stdarch-gen-loongarch/src/main.rs
index 5076064ffc..10b87c70e9 100644
--- a/crates/stdarch-gen-loongarch/src/main.rs
+++ b/crates/stdarch-gen-loongarch/src/main.rs
@@ -157,7 +157,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> {
 // ```
 
 use crate::mem::transmute;
-use super::types::*;
+use super::super::*;
 "#
     ));
 
@@ -1551,6 +1551,10 @@ fn gen_test_body(
                 format!(
                     "    printf(\"\\n    {current_name}{as_params};\\n    assert_eq!(r, transmute(o));\\n\"{as_args});"
                 )
+            } else if current_name.starts_with("lasx_cast_128") {
+                format!(
+                    "    printf(\"\\n    assert_eq!(r.as_array()[0..2], transmute::<_, i64x4>({current_name}{as_params}).as_array()[0..2]);\\n\"{as_args});"
+                )
             } else {
                 format!(
                     "    printf(\"\\n    assert_eq!(r, transmute({current_name}{as_params}));\\n\"{as_args});"

From 1a103b1c40db229165730d4a26ae75249fac78d7 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <flokkievids@gmail.com>
Date: Mon, 2 Feb 2026 10:51:20 +0100
Subject: [PATCH 128/326] Revert "Revert "Use LLVM intrinsics for `madd`
 intrinsics""

---
 crates/core_arch/src/x86/avx2.rs     | 36 ++++++++--------
 crates/core_arch/src/x86/avx512bw.rs | 64 +++++++++++++---------------
 crates/core_arch/src/x86/sse2.rs     | 26 +++++++----
 3 files changed, 63 insertions(+), 63 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index e9463d4331..83aef753c9 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -1841,14 +1841,20 @@ pub const fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) ->
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe {
-        let r: i32x16 = simd_mul(simd_cast(a.as_i16x16()), simd_cast(b.as_i16x16()));
-        let even: i32x8 = simd_shuffle!(r, r, [0, 2, 4, 6, 8, 10, 12, 14]);
-        let odd: i32x8 = simd_shuffle!(r, r, [1, 3, 5, 7, 9, 11, 13, 15]);
-        simd_add(even, odd).as_m256i()
-    }
+pub fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
+    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
+    //
+    // ```rust
+    // #[target_feature(enable = "avx2")]
+    // unsafe fn widening_add(mad: __m256i) -> __m256i {
+    //     _mm256_madd_epi16(mad, _mm256_set1_epi16(1))
+    // }
+    // ```
+    //
+    // If we implement this using generic vector intrinsics, the optimizer
+    // will eliminate this pattern, and `vpmaddwd` will no longer be emitted.
+    // For this reason, we use x86 intrinsics.
+    unsafe { transmute(pmaddwd(a.as_i16x16(), b.as_i16x16())) }
 }
 
 /// Vertically multiplies each unsigned 8-bit integer from `a` with the
@@ -3813,6 +3819,8 @@ pub const fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
 
 #[allow(improper_ctypes)]
 unsafe extern "C" {
+    #[link_name = "llvm.x86.avx2.pmadd.wd"]
+    fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
     fn pmaddubsw(a: u8x32, b: i8x32) -> i16x16;
     #[link_name = "llvm.x86.avx2.mpsadbw"]
@@ -4661,7 +4669,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const fn test_mm256_madd_epi16() {
+    fn test_mm256_madd_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_madd_epi16(a, b);
@@ -4669,16 +4677,6 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[target_feature(enable = "avx2")]
-    #[cfg_attr(test, assert_instr(vpmaddwd))]
-    unsafe fn test_mm256_madd_epi16_mul_one(mad: __m256i) -> __m256i {
-        // This is a trick used in the adler32 algorithm to get a widening addition. The
-        // multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd
-        // instruction is no longer selected. The assert_instr verifies that this is the case.
-        let one_v = _mm256_set1_epi16(1);
-        _mm256_madd_epi16(mad, one_v)
-    }
-
     #[simd_test(enable = "avx2")]
     const fn test_mm256_inserti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index e2d12cd972..8e074fdcfa 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6321,22 +6321,20 @@ pub const unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a:
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe {
-        let r: i32x32 = simd_mul(simd_cast(a.as_i16x32()), simd_cast(b.as_i16x32()));
-        let even: i32x16 = simd_shuffle!(
-            r,
-            r,
-            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
-        );
-        let odd: i32x16 = simd_shuffle!(
-            r,
-            r,
-            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
-        );
-        simd_add(even, odd).as_m512i()
-    }
+pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
+    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
+    //
+    // ```rust
+    // #[target_feature(enable = "avx512bw")]
+    // unsafe fn widening_add(mad: __m512i) -> __m512i {
+    //     _mm512_madd_epi16(mad, _mm512_set1_epi16(1))
+    // }
+    // ```
+    //
+    // If we implement this using generic vector intrinsics, the optimizer
+    // will eliminate this pattern, and `vpmaddwd` will no longer be emitted.
+    // For this reason, we use x86 intrinsics.
+    unsafe { transmute(vpmaddwd(a.as_i16x32(), b.as_i16x32())) }
 }
 
 /// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6346,8 +6344,7 @@ pub const fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, src.as_i32x16()))
@@ -6361,8 +6358,7 @@ pub const fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: _
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let madd = _mm512_madd_epi16(a, b).as_i32x16();
         transmute(simd_select_bitmask(k, madd, i32x16::ZERO))
@@ -6376,8 +6372,7 @@ pub const fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, src.as_i32x8()))
@@ -6391,8 +6386,7 @@ pub const fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
+pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let madd = _mm256_madd_epi16(a, b).as_i32x8();
         transmute(simd_select_bitmask(k, madd, i32x8::ZERO))
@@ -6406,8 +6400,7 @@ pub const fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, src.as_i32x4()))
@@ -6421,8 +6414,7 @@ pub const fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m12
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmaddwd))]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let madd = _mm_madd_epi16(a, b).as_i32x4();
         transmute(simd_select_bitmask(k, madd, i32x4::ZERO))
@@ -12582,6 +12574,8 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.pmul.hr.sw.512"]
     fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32;
 
+    #[link_name = "llvm.x86.avx512.pmaddw.d.512"]
+    fn vpmaddwd(a: i16x32, b: i16x32) -> i32x16;
     #[link_name = "llvm.x86.avx512.pmaddubs.w.512"]
     fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32;
 
@@ -17506,7 +17500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const fn test_mm512_madd_epi16() {
+    fn test_mm512_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_madd_epi16(a, b);
@@ -17515,7 +17509,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const fn test_mm512_mask_madd_epi16() {
+    fn test_mm512_mask_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_mask_madd_epi16(a, 0, a, b);
@@ -17543,7 +17537,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const fn test_mm512_maskz_madd_epi16() {
+    fn test_mm512_maskz_madd_epi16() {
         let a = _mm512_set1_epi16(1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_madd_epi16(0, a, b);
@@ -17554,7 +17548,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm256_mask_madd_epi16() {
+    fn test_mm256_mask_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_mask_madd_epi16(a, 0, a, b);
@@ -17574,7 +17568,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm256_maskz_madd_epi16() {
+    fn test_mm256_maskz_madd_epi16() {
         let a = _mm256_set1_epi16(1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_madd_epi16(0, a, b);
@@ -17585,7 +17579,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm_mask_madd_epi16() {
+    fn test_mm_mask_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_mask_madd_epi16(a, 0, a, b);
@@ -17596,7 +17590,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const fn test_mm_maskz_madd_epi16() {
+    fn test_mm_maskz_madd_epi16() {
         let a = _mm_set1_epi16(1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_madd_epi16(0, a, b);
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index ecd478511b..f339a003df 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -210,14 +210,20 @@ pub const fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(pmaddwd))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
-pub const fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe {
-        let r: i32x8 = simd_mul(simd_cast(a.as_i16x8()), simd_cast(b.as_i16x8()));
-        let even: i32x4 = simd_shuffle!(r, r, [0, 2, 4, 6]);
-        let odd: i32x4 = simd_shuffle!(r, r, [1, 3, 5, 7]);
-        simd_add(even, odd).as_m128i()
-    }
+pub fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
+    // It's a trick used in the Adler-32 algorithm to perform a widening addition.
+    //
+    // ```rust
+    // #[target_feature(enable = "sse2")]
+    // unsafe fn widening_add(mad: __m128i) -> __m128i {
+    //     _mm_madd_epi16(mad, _mm_set1_epi16(1))
+    // }
+    // ```
+    //
+    // If we implement this using generic vector intrinsics, the optimizer
+    // will eliminate this pattern, and `pmaddwd` will no longer be emitted.
+    // For this reason, we use x86 intrinsics.
+    unsafe { transmute(pmaddwd(a.as_i16x8(), b.as_i16x8())) }
 }
 
 /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
@@ -3187,6 +3193,8 @@ unsafe extern "C" {
     fn lfence();
     #[link_name = "llvm.x86.sse2.mfence"]
     fn mfence();
+    #[link_name = "llvm.x86.sse2.pmadd.wd"]
+    fn pmaddwd(a: i16x8, b: i16x8) -> i32x4;
     #[link_name = "llvm.x86.sse2.psad.bw"]
     fn psadbw(a: u8x16, b: u8x16) -> u64x2;
     #[link_name = "llvm.x86.sse2.psll.w"]
@@ -3465,7 +3473,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const fn test_mm_madd_epi16() {
+    fn test_mm_madd_epi16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let b = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
         let r = _mm_madd_epi16(a, b);

From 4ec72fb99e10bf16302101c9bc01d35e98bc26d3 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 27 Jan 2026 19:06:53 +0100
Subject: [PATCH 129/326] aarch64: use `read_unaligned` for `vld1_*`

---
 .../src/arm_shared/neon/generated.rs          | 734 ++++++------------
 .../spec/neon/arm_shared.spec.yml             |  92 +--
 2 files changed, 266 insertions(+), 560 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 2f52e3b52b..c2e90d41ef 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -15808,21 +15808,13 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0")]
-        fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t;
-    }
-    _vld1_f16_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
@@ -15834,21 +15826,13 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0")]
-        fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t;
-    }
-    _vld1_f16_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
@@ -15860,21 +15844,13 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0")]
-        fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t;
-    }
-    _vld1_f16_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
@@ -15886,21 +15862,13 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0")]
-        fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t;
-    }
-    _vld1q_f16_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
@@ -15912,21 +15880,13 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0")]
-        fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t;
-    }
-    _vld1q_f16_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
@@ -15938,21 +15898,13 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0")]
-        fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t;
-    }
-    _vld1q_f16_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
@@ -16156,10 +16108,10 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -16170,15 +16122,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")]
-        fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t;
-    }
-    _vld1_f32_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
@@ -16187,10 +16131,10 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -16201,15 +16145,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")]
-        fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t;
-    }
-    _vld1_f32_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
@@ -16218,10 +16154,10 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -16232,15 +16168,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")]
-        fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t;
-    }
-    _vld1_f32_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
@@ -16249,10 +16177,10 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -16263,15 +16191,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")]
-        fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t;
-    }
-    _vld1q_f32_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
@@ -16280,10 +16200,10 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -16294,15 +16214,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")]
-        fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t;
-    }
-    _vld1q_f32_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
@@ -16311,10 +16223,10 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -16325,15 +16237,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")]
-        fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t;
-    }
-    _vld1q_f32_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
@@ -17000,10 +16904,10 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17014,7 +16918,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
-    transmute(vld1_s64_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
@@ -17026,7 +16930,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17037,7 +16941,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
-    transmute(vld1_s64_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
@@ -17049,7 +16953,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17060,7 +16964,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
-    transmute(vld1_s64_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
@@ -17072,7 +16976,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17083,7 +16987,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
-    transmute(vld1q_s64_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
@@ -17095,7 +16999,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17106,7 +17010,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
-    transmute(vld1q_s64_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
@@ -17118,7 +17022,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17129,7 +17033,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
-    transmute(vld1q_s64_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
@@ -17242,10 +17146,10 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17256,15 +17160,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")]
-        fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t;
-    }
-    _vld1_s8_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
@@ -17273,10 +17169,10 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17287,15 +17183,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")]
-        fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t;
-    }
-    _vld1_s8_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
@@ -17304,10 +17192,10 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17318,15 +17206,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")]
-        fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t;
-    }
-    _vld1_s8_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
@@ -17335,10 +17215,10 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17349,15 +17229,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")]
-        fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t;
-    }
-    _vld1q_s8_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
@@ -17366,10 +17238,10 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17380,15 +17252,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")]
-        fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t;
-    }
-    _vld1q_s8_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
@@ -17397,10 +17261,10 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17411,15 +17275,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")]
-        fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t;
-    }
-    _vld1q_s8_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
@@ -17428,10 +17284,10 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17442,15 +17298,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")]
-        fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t;
-    }
-    _vld1_s16_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
@@ -17459,10 +17307,10 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17473,15 +17321,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")]
-        fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t;
-    }
-    _vld1_s16_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
@@ -17490,10 +17330,10 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17504,15 +17344,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")]
-        fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t;
-    }
-    _vld1_s16_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
@@ -17521,10 +17353,10 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17535,15 +17367,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")]
-        fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t;
-    }
-    _vld1q_s16_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
@@ -17552,10 +17376,10 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17566,15 +17390,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")]
-        fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t;
-    }
-    _vld1q_s16_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
@@ -17583,10 +17399,10 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17597,15 +17413,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")]
-        fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t;
-    }
-    _vld1q_s16_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
@@ -17614,10 +17422,10 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17628,15 +17436,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")]
-        fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t;
-    }
-    _vld1_s32_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
@@ -17645,10 +17445,10 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17659,15 +17459,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")]
-        fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t;
-    }
-    _vld1_s32_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
@@ -17676,10 +17468,10 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17690,15 +17482,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")]
-        fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t;
-    }
-    _vld1_s32_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
@@ -17707,10 +17491,10 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17721,15 +17505,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")]
-        fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t;
-    }
-    _vld1q_s32_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
@@ -17738,10 +17514,10 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17752,15 +17528,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")]
-        fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t;
-    }
-    _vld1q_s32_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
@@ -17769,10 +17537,10 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17783,15 +17551,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")]
-        fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t;
-    }
-    _vld1q_s32_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
@@ -17800,10 +17560,10 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17814,15 +17574,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")]
-        fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t;
-    }
-    _vld1_s64_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
@@ -17831,10 +17583,10 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17845,15 +17597,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")]
-        fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t;
-    }
-    _vld1_s64_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
@@ -17862,10 +17606,10 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17876,15 +17620,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")]
-        fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t;
-    }
-    _vld1_s64_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
@@ -17893,10 +17629,10 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17907,15 +17643,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")]
-        fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t;
-    }
-    _vld1q_s64_x2(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
@@ -17924,10 +17652,10 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17938,15 +17666,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")]
-        fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t;
-    }
-    _vld1q_s64_x3(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
@@ -17955,10 +17675,10 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -17969,15 +17689,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")]
-        fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t;
-    }
-    _vld1q_s64_x4(a)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
@@ -17986,10 +17698,10 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18000,7 +17712,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
-    transmute(vld1_s8_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
@@ -18009,10 +17721,10 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18023,7 +17735,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
-    transmute(vld1_s8_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
@@ -18032,10 +17744,10 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18046,7 +17758,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
-    transmute(vld1_s8_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
@@ -18055,10 +17767,10 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18069,7 +17781,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
-    transmute(vld1q_s8_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
@@ -18078,10 +17790,10 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18092,7 +17804,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
-    transmute(vld1q_s8_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
@@ -18101,10 +17813,10 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18115,7 +17827,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
-    transmute(vld1q_s8_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
@@ -18124,10 +17836,10 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18138,7 +17850,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
-    transmute(vld1_s16_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
@@ -18147,10 +17859,10 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18161,7 +17873,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
-    transmute(vld1_s16_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
@@ -18170,10 +17882,10 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18184,7 +17896,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
-    transmute(vld1_s16_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
@@ -18193,10 +17905,10 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18207,7 +17919,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
-    transmute(vld1q_s16_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
@@ -18216,10 +17928,10 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18230,7 +17942,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
-    transmute(vld1q_s16_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
@@ -18239,10 +17951,10 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18253,7 +17965,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
-    transmute(vld1q_s16_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
@@ -18262,10 +17974,10 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18276,7 +17988,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
-    transmute(vld1_s32_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
@@ -18285,10 +17997,10 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18299,7 +18011,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
-    transmute(vld1_s32_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
@@ -18308,10 +18020,10 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18322,7 +18034,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
-    transmute(vld1_s32_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
@@ -18331,10 +18043,10 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18345,7 +18057,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
-    transmute(vld1q_s32_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
@@ -18354,10 +18066,10 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18368,7 +18080,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
-    transmute(vld1q_s32_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
@@ -18377,10 +18089,10 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18391,7 +18103,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
-    transmute(vld1q_s32_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
@@ -18400,10 +18112,10 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18414,7 +18126,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
-    transmute(vld1_s64_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
@@ -18423,10 +18135,10 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18437,7 +18149,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
-    transmute(vld1_s64_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
@@ -18446,10 +18158,10 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18460,7 +18172,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
-    transmute(vld1_s64_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
@@ -18469,10 +18181,10 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18483,7 +18195,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
-    transmute(vld1q_s64_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
@@ -18492,10 +18204,10 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18506,7 +18218,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
-    transmute(vld1q_s64_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
@@ -18515,10 +18227,10 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18529,7 +18241,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
-    transmute(vld1q_s64_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
@@ -18538,10 +18250,10 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18552,7 +18264,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
-    transmute(vld1_s8_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
@@ -18561,10 +18273,10 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18575,7 +18287,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
-    transmute(vld1_s8_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
@@ -18584,10 +18296,10 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18598,7 +18310,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
-    transmute(vld1_s8_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
@@ -18607,10 +18319,10 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18621,7 +18333,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
-    transmute(vld1q_s8_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
@@ -18630,10 +18342,10 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18644,7 +18356,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
-    transmute(vld1q_s8_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
@@ -18653,10 +18365,10 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18667,7 +18379,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
-    transmute(vld1q_s8_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
@@ -18676,10 +18388,10 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18690,7 +18402,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
-    transmute(vld1_s16_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
@@ -18699,10 +18411,10 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18713,7 +18425,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
-    transmute(vld1_s16_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
@@ -18722,10 +18434,10 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18736,7 +18448,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
-    transmute(vld1_s16_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
@@ -18745,10 +18457,10 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18759,7 +18471,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
-    transmute(vld1q_s16_x2(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
@@ -18768,10 +18480,10 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18782,7 +18494,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
-    transmute(vld1q_s16_x3(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
@@ -18791,10 +18503,10 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -18805,7 +18517,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
-    transmute(vld1q_s16_x4(transmute(a)))
+    crate::ptr::read_unaligned(a.cast())
 }
 #[inline(always)]
 #[rustc_legacy_const_generics(1)]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 3ec7ba8814..c726d1a028 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -2603,8 +2603,8 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - *neon-v7
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety:
@@ -2617,13 +2617,12 @@ intrinsics:
       - ["*const f32", float32x2x4_t]
       - ["*const f32", float32x4x4_t]
     compose:
-      - LLVMLink:
-          name: "vld1x{neon_type[1].tuple}.{neon_type[1]}"
-          links:
-            - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0"
-              arch: aarch64,arm64ec
-            - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0"
-              arch: arm
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
@@ -2631,8 +2630,8 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - *neon-v7
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety:
@@ -2663,13 +2662,12 @@ intrinsics:
       - ["*const i64", int64x2x3_t]
       - ["*const i64", int64x2x4_t]
     compose:
-      - LLVMLink:
-          name: "ld1x{neon_type[1].tuple}.{neon_type[1]}"
-          links:
-            - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0"
-              arch: aarch64,arm64ec
-            - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0"
-              arch: arm
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
@@ -2677,8 +2675,8 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - *neon-v7
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     big_endian_inverse: false
@@ -2723,12 +2721,11 @@ intrinsics:
       - ["*const p16", poly16x8x4_t, int16x8x4_t]
     compose:
       - FnCall:
-          - transmute
-          - - FnCall:
-                - "vld1{neon_type[2].no}"
-                - - FnCall:
-                      - transmute
-                      - - a
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
@@ -2738,7 +2735,7 @@ intrinsics:
       - *neon-aes
       - *neon-v8
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     big_endian_inverse: false
@@ -2752,12 +2749,11 @@ intrinsics:
       - ["*const p64", poly64x2x4_t, int64x2x4_t]
     compose:
       - FnCall:
-          - transmute
-          - - FnCall:
-                - "vld1{neon_type[2].no}"
-                - - FnCall:
-                      - transmute
-                      - - a
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
@@ -2766,8 +2762,8 @@ intrinsics:
     attr:
       - *neon-aes
       - *neon-v8
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety:
@@ -2776,12 +2772,11 @@ intrinsics:
       - ["*const p64", poly64x1x2_t, int64x1x2_t]
     compose:
       - FnCall:
-          - transmute
-          - - FnCall:
-                - "vld1{neon_type[2].no}"
-                - - FnCall:
-                      - transmute
-                      - - a
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
@@ -2790,7 +2785,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *arm-fp16
       - *neon-unstable-f16
       - *target-not-arm64ec
@@ -2804,13 +2799,12 @@ intrinsics:
       - ["*const f16", float16x4x4_t]
       - ["*const f16", float16x8x4_t]
     compose:
-      - LLVMLink:
-          name: "vld1x{neon_type[1].tuple}.{neon_type[1]}"
-          links:
-            - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0"
-              arch: aarch64,arm64ec
-            - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0"
-              arch: arm
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld1{type[2]}_{neon_type[1]}"
     doc: "Load one single-element structure to one lane of one register"

From 560d9227ff0155aef9930d2035f87497c64a5e62 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 2 Feb 2026 17:01:10 +0100
Subject: [PATCH 130/326] add `vpmaddwd` tests back in

---
 crates/core_arch/src/x86/avx2.rs | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 83aef753c9..04a88e461f 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -4677,6 +4677,26 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
+    #[target_feature(enable = "avx2")]
+    #[cfg_attr(test, assert_instr(vpmaddwd))]
+    unsafe fn test_mm256_madd_epi16_mul_one(v: __m256i) -> __m256i {
+        // This is a trick used in the adler32 algorithm to get a widening addition. The
+        // multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd
+        // instruction is no longer selected. The assert_instr verifies that this is the case.
+        let one_v = _mm256_set1_epi16(1);
+        _mm256_madd_epi16(v, one_v)
+    }
+
+    #[target_feature(enable = "avx2")]
+    #[cfg_attr(test, assert_instr(vpmaddwd))]
+    unsafe fn test_mm256_madd_epi16_shl(v: __m256i) -> __m256i {
+        // This is a trick used in the base64 algorithm to get a widening addition. Instead of a
+        // multiplication, a vector shl is used. In LLVM 22 that breaks the pattern recognition
+        // for the automatic optimization to vpmaddwd.
+        let shift_value = _mm256_set1_epi32(12i32);
+        _mm256_madd_epi16(v, shift_value)
+    }
+
     #[simd_test(enable = "avx2")]
     const fn test_mm256_inserti128_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);

From d4aefd90d863a1320b8c41247e22b0029aa32adc Mon Sep 17 00:00:00 2001
From: ltdk <usr@ltdk.xyz>
Date: Mon, 2 Feb 2026 17:34:15 -0500
Subject: [PATCH 131/326] Move bigint helper tracking issues

---
 crates/core_arch/src/lib.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 3992eaee30..039a4c4411 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -33,7 +33,6 @@
     f16,
     aarch64_unstable_target_feature,
     target_feature_inline_always,
-    bigint_helper_methods,
     funnel_shifts,
     avx10_target_feature,
     const_trait_impl,

From 188d083b4cf30a1e6dc0d675e1afa566b103ecf8 Mon Sep 17 00:00:00 2001
From: Snehal <snehalreddy@google.com>
Date: Tue, 3 Feb 2026 15:32:52 +0000
Subject: [PATCH 132/326] aarch64: Guard RCPC3 intrinsics with
 target_has_atomic = "64"

The `vldap1` and `vstl1` RCPC3 intrinsics introduced in standard library unconditionally use `AtomicI64`. This breaks builds on target that do not support 64-bit atomics, such as `aarch64-unknown-none` with `max-atomic-width` set to 0. This commit adds a `#[cfg(target_has_atomic = "64")]` guard to these intrinsics
---
 crates/core_arch/src/aarch64/neon/generated.rs    | 15 +++++++++++++++
 crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml |  8 ++++++++
 2 files changed, 23 insertions(+)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 3d5d07ac1b..a81914af78 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12858,6 +12858,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
     static_assert!(LANE == 0);
     let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
@@ -12876,6 +12877,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
     let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
@@ -12894,6 +12896,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
     transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
@@ -12907,6 +12910,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
     static_assert!(LANE == 0);
     transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
@@ -12920,6 +12924,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
     transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
@@ -12933,6 +12938,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
     static_assert!(LANE == 0);
     transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
@@ -12946,6 +12952,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
     static_assert_uimm_bits!(LANE, 1);
     transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
@@ -27122,6 +27129,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
     static_assert!(LANE == 0);
     unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
@@ -27133,6 +27141,7 @@ pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
     unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
@@ -27144,6 +27153,7 @@ pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
     static_assert!(LANE == 0);
     unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
@@ -27155,6 +27165,7 @@ pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
     unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
@@ -27166,6 +27177,7 @@ pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
     static_assert!(LANE == 0);
     unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
@@ -27177,6 +27189,7 @@ pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
     unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
@@ -27188,6 +27201,7 @@ pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
     static_assert!(LANE == 0);
     let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
@@ -27203,6 +27217,7 @@ pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+#[cfg(target_has_atomic = "64")]
 pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
     let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a099c2c8d6..1c95bbe3d3 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -70,6 +70,10 @@ aarch64-stable-jscvt: &aarch64-stable-jscvt
 neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3
   FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']]
 
+# #[cfg(target_has_atomic = "64")]
+cfg-target-has-atomic-64: &cfg-target-has-atomic-64
+  FnCall: [cfg, ['target_has_atomic = "64"']]
+
 # #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 neon-unstable-fp8: &neon-unstable-fp8
   FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']]
@@ -4418,6 +4422,7 @@ intrinsics:
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
+      - *cfg-target-has-atomic-64
     types:
       - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0']
       - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1']
@@ -4448,6 +4453,7 @@ intrinsics:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
       - *neon-unstable-feat-lrcpc3
+      - *cfg-target-has-atomic-64
     types:
       - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0','']
       #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust
@@ -4474,6 +4480,7 @@ intrinsics:
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
+      - *cfg-target-has-atomic-64
     types:
       - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0']
       - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1']
@@ -4502,6 +4509,7 @@ intrinsics:
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
+      - *cfg-target-has-atomic-64
     types:
       - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0','']
       - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0','']

From 6f8a9ae5919a546c74f89c864c6d7b6e90f79874 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Thu, 5 Feb 2026 04:37:12 +0000
Subject: [PATCH 133/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to db3e99bbab28c6ca778b13222becdea54533d908.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index ccc0b55d4d..aa3876b14a 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-873d4682c7d285540b8f28bfe637006cef8918a6
+db3e99bbab28c6ca778b13222becdea54533d908

From 9e1f59429a96c3f22b7c9bd9403f4c8365e3de20 Mon Sep 17 00:00:00 2001
From: "Eddy (Eduard) Stefes" <eddy@linux.ibm.com>
Date: Thu, 5 Feb 2026 13:36:18 +0100
Subject: [PATCH 134/326] disable s390x vector intrinsics if softfloat is
 enabled

we will add an explicit incompatibility of softfloat and vector feature
in rutsc s390x-unknown-none-softfloat target specification.
Therefore we need to disable vector intrinsics here to be able to compile
core for this target.
---
 crates/core_arch/src/s390x/mod.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/crates/core_arch/src/s390x/mod.rs b/crates/core_arch/src/s390x/mod.rs
index 7d3b3f2d99..5b85020072 100644
--- a/crates/core_arch/src/s390x/mod.rs
+++ b/crates/core_arch/src/s390x/mod.rs
@@ -2,6 +2,11 @@
 
 pub(crate) mod macros;
 
+/// the float and vector registers overlap therefore we cannot use any vector
+/// extensions if softfloat is enabled.
+
+#[cfg(not(target_abi = "softfloat"))]
 mod vector;
+#[cfg(not(target_abi = "softfloat"))]
 #[unstable(feature = "stdarch_s390x", issue = "130869")]
 pub use self::vector::*;

From ed7b6a3eb80b675bea9f2150e0fefff1afab70aa Mon Sep 17 00:00:00 2001
From: Josh Stone <jistone@redhat.com>
Date: Thu, 5 Feb 2026 11:30:41 -0800
Subject: [PATCH 135/326] Replace `stdarch` version placeholders with 1.94

(cherry picked from commit b90149755ad030e74bc3c198f8c4b90e08be8065)
---
 .../core_arch/src/aarch64/neon/generated.rs   |  210 +-
 .../src/arm_shared/neon/generated.rs          |  404 ++--
 crates/core_arch/src/arm_shared/neon/mod.rs   |   14 +-
 crates/core_arch/src/x86/avx512fp16.rs        | 1762 ++++++++---------
 crates/core_arch/src/x86/avxneconvert.rs      |    8 +-
 crates/core_arch/src/x86/mod.rs               |    4 +-
 crates/core_arch/src/x86_64/avx512fp16.rs     |   24 +-
 crates/core_arch/src/x86_64/mod.rs            |    2 +-
 .../spec/neon/aarch64.spec.yml                |    4 +-
 .../spec/neon/arm_shared.spec.yml             |    8 +-
 10 files changed, 1220 insertions(+), 1220 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 9507b71106..ed50bff5ae 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -1565,7 +1565,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
     let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
@@ -1576,7 +1576,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t {
     let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
@@ -7283,7 +7283,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
     vcombine_f16(a, vcvt_f16_f32(b))
@@ -7293,7 +7293,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
     vcvt_f32_f16(vget_high_f16(a))
@@ -7532,7 +7532,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -7549,7 +7549,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -7630,7 +7630,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -7647,7 +7647,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -8218,7 +8218,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -8235,7 +8235,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -8316,7 +8316,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -8333,7 +8333,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -8566,7 +8566,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -8583,7 +8583,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -8664,7 +8664,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -8681,7 +8681,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -8914,7 +8914,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe extern "unadjusted" {
@@ -8931,7 +8931,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t {
     unsafe extern "unadjusted" {
@@ -9012,7 +9012,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
     unsafe extern "unadjusted" {
@@ -9029,7 +9029,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe extern "unadjusted" {
@@ -9493,7 +9493,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fdiv))]
 pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -9503,7 +9503,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fdiv))]
 pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -10108,7 +10108,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfma_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10124,7 +10124,7 @@ pub fn vfma_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfma_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10140,7 +10140,7 @@ pub fn vfma_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmaq_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -10156,7 +10156,7 @@ pub fn vfmaq_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmaq_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -10434,7 +10434,7 @@ pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal2))]
 pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10452,7 +10452,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal2))]
 pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10472,7 +10472,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_lane_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10489,7 +10489,7 @@ pub fn vfmlal_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_laneq_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10506,7 +10506,7 @@ pub fn vfmlal_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_lane_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10523,7 +10523,7 @@ pub fn vfmlalq_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10540,7 +10540,7 @@ pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_lane_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10557,7 +10557,7 @@ pub fn vfmlal_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlal_laneq_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10574,7 +10574,7 @@ pub fn vfmlal_laneq_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_lane_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10591,7 +10591,7 @@ pub fn vfmlalq_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10606,7 +10606,7 @@ pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal))]
 pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10624,7 +10624,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlal))]
 pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10642,7 +10642,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl2))]
 pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10660,7 +10660,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl2))]
 pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10680,7 +10680,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_lane_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10697,7 +10697,7 @@ pub fn vfmlsl_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10714,7 +10714,7 @@ pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_lane_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10731,7 +10731,7 @@ pub fn vfmlslq_lane_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10748,7 +10748,7 @@ pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_lane_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10765,7 +10765,7 @@ pub fn vfmlsl_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
     r: float32x2_t,
@@ -10782,7 +10782,7 @@ pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_lane_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10799,7 +10799,7 @@ pub fn vfmlslq_lane_low_f16<const LANE: i32>(
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
     r: float32x4_t,
@@ -10814,7 +10814,7 @@ pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl))]
 pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
@@ -10832,7 +10832,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmlsl))]
 pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
@@ -10863,7 +10863,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfms_lane_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10879,7 +10879,7 @@ pub fn vfms_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfms_laneq_f16<const LANE: i32>(
     a: float16x4_t,
@@ -10895,7 +10895,7 @@ pub fn vfms_laneq_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsq_lane_f16<const LANE: i32>(
     a: float16x8_t,
@@ -10911,7 +10911,7 @@ pub fn vfmsq_lane_f16<const LANE: i32>(
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsq_laneq_f16<const LANE: i32>(
     a: float16x8_t,
@@ -15078,7 +15078,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -15095,7 +15095,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -15602,7 +15602,7 @@ pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmulx))]
 pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -15619,7 +15619,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmulx))]
 pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -15702,7 +15702,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
@@ -15719,7 +15719,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -15736,7 +15736,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
@@ -15766,7 +15766,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
@@ -16128,7 +16128,7 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(faddp))]
 pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16347,7 +16347,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxp))]
 pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16364,7 +16364,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxp))]
 pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16381,7 +16381,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16398,7 +16398,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16655,7 +16655,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminp))]
 pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16672,7 +16672,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminp))]
 pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -16689,7 +16689,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnmp))]
 pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -16706,7 +16706,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnmp))]
 pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -21832,7 +21832,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
@@ -21843,7 +21843,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
@@ -21855,7 +21855,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
@@ -21866,7 +21866,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
@@ -21881,7 +21881,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
@@ -21892,7 +21892,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
@@ -21906,7 +21906,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
@@ -21917,7 +21917,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
@@ -23496,7 +23496,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintz))]
 pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
@@ -23506,7 +23506,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintz))]
 pub fn vrndq_f16(a: float16x8_t) -> float16x8_t {
@@ -23552,7 +23552,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinta))]
 pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
@@ -23562,7 +23562,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinta))]
 pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t {
@@ -23628,7 +23628,7 @@ pub fn vrndh_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinti))]
 pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
@@ -23645,7 +23645,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frinti))]
 pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t {
@@ -23743,7 +23743,7 @@ pub fn vrndih_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintm))]
 pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
@@ -23753,7 +23753,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintm))]
 pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t {
@@ -23874,7 +23874,7 @@ pub fn vrndns_f32(a: f32) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintp))]
 pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
@@ -23884,7 +23884,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintp))]
 pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t {
@@ -23940,7 +23940,7 @@ pub fn vrndph_f16(a: f16) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintx))]
 pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
@@ -23950,7 +23950,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(frintx))]
 pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t {
@@ -25453,7 +25453,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
     unsafe { simd_fsqrt(a) }
@@ -25463,7 +25463,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
 #[inline(always)]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t {
     unsafe { simd_fsqrt(a) }
@@ -28016,7 +28016,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
 pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -28026,7 +28026,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
 pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -28252,7 +28252,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
 pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -28262,7 +28262,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
 pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -28762,7 +28762,7 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
 pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -28772,7 +28772,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
 pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -28998,7 +28998,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
 pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -29008,7 +29008,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
 pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -29252,7 +29252,7 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
 pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -29262,7 +29262,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
 pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
@@ -29488,7 +29488,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
 pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
@@ -29498,7 +29498,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
-#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
 pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 3b67208182..c2faf44681 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -821,7 +821,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -851,7 +851,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -1422,7 +1422,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -1444,7 +1444,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -1673,7 +1673,7 @@ pub fn vabsh_f16(a: f16) -> f16 {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -1695,7 +1695,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -3879,7 +3879,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -3907,7 +3907,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4529,7 +4529,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4559,7 +4559,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4647,7 +4647,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4677,7 +4677,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4765,7 +4765,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4787,7 +4787,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4851,7 +4851,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4873,7 +4873,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4937,7 +4937,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -4959,7 +4959,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -5317,7 +5317,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -5339,7 +5339,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -5655,7 +5655,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -5678,7 +5678,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -5701,7 +5701,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -5723,7 +5723,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6039,7 +6039,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6062,7 +6062,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6085,7 +6085,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6107,7 +6107,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6423,7 +6423,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6446,7 +6446,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6769,7 +6769,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -6791,7 +6791,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -7107,7 +7107,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -7130,7 +7130,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -7812,7 +7812,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8041,7 +8041,7 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8065,7 +8065,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8577,7 +8577,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8599,7 +8599,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8621,7 +8621,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8643,7 +8643,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8665,7 +8665,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8688,7 +8688,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8795,7 +8795,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8830,7 +8830,7 @@ pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8865,7 +8865,7 @@ pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -8900,7 +8900,7 @@ pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9087,7 +9087,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9122,7 +9122,7 @@ pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9233,7 +9233,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9268,7 +9268,7 @@ pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9378,7 +9378,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9400,7 +9400,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9480,7 +9480,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -9502,7 +9502,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -10140,7 +10140,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -10165,7 +10165,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -10719,7 +10719,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -10744,7 +10744,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -12261,7 +12261,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -12640,7 +12640,7 @@ pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -13228,7 +13228,7 @@ pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -13250,7 +13250,7 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -13357,7 +13357,7 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -13383,7 +13383,7 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -13494,7 +13494,7 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -13513,7 +13513,7 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -28187,7 +28187,7 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -28217,7 +28217,7 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -28593,7 +28593,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -28615,7 +28615,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -28679,7 +28679,7 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -28709,7 +28709,7 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -29085,7 +29085,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -29107,7 +29107,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -33043,7 +33043,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -33065,7 +33065,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -33130,7 +33130,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -33159,7 +33159,7 @@ pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -35131,7 +35131,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -35153,7 +35153,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -36391,7 +36391,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42473,7 +42473,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42503,7 +42503,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42649,7 +42649,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42679,7 +42679,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42768,7 +42768,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42791,7 +42791,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42818,7 +42818,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42841,7 +42841,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42868,7 +42868,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42891,7 +42891,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42918,7 +42918,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42941,7 +42941,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42968,7 +42968,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -42991,7 +42991,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43015,7 +43015,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43038,7 +43038,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43065,7 +43065,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43088,7 +43088,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43115,7 +43115,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43138,7 +43138,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43165,7 +43165,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43188,7 +43188,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43212,7 +43212,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43235,7 +43235,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43262,7 +43262,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43285,7 +43285,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43312,7 +43312,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43335,7 +43335,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43362,7 +43362,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43385,7 +43385,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43416,7 +43416,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43439,7 +43439,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43466,7 +43466,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43489,7 +43489,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43516,7 +43516,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43539,7 +43539,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43566,7 +43566,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43589,7 +43589,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43620,7 +43620,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43643,7 +43643,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43670,7 +43670,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43693,7 +43693,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43720,7 +43720,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43743,7 +43743,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43770,7 +43770,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43793,7 +43793,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43824,7 +43824,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43847,7 +43847,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43874,7 +43874,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43897,7 +43897,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43924,7 +43924,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43947,7 +43947,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43974,7 +43974,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -43997,7 +43997,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44024,7 +44024,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44047,7 +44047,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44075,7 +44075,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44098,7 +44098,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44125,7 +44125,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44148,7 +44148,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44175,7 +44175,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44198,7 +44198,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44225,7 +44225,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44248,7 +44248,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44275,7 +44275,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44298,7 +44298,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44324,7 +44324,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44347,7 +44347,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44374,7 +44374,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44397,7 +44397,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44424,7 +44424,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44447,7 +44447,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44475,7 +44475,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44498,7 +44498,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44525,7 +44525,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44548,7 +44548,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44575,7 +44575,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44598,7 +44598,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44625,7 +44625,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44648,7 +44648,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44675,7 +44675,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44698,7 +44698,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44724,7 +44724,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44747,7 +44747,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44774,7 +44774,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44797,7 +44797,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44824,7 +44824,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44847,7 +44847,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44875,7 +44875,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44898,7 +44898,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44925,7 +44925,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44948,7 +44948,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44975,7 +44975,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -44998,7 +44998,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45024,7 +45024,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45047,7 +45047,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45071,7 +45071,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45094,7 +45094,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45118,7 +45118,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45141,7 +45141,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45168,7 +45168,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45191,7 +45191,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45217,7 +45217,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -45240,7 +45240,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -59244,7 +59244,7 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -59266,7 +59266,7 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -59636,7 +59636,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -59665,7 +59665,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -60756,7 +60756,7 @@ pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -60786,7 +60786,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -60932,7 +60932,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -60962,7 +60962,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -72516,7 +72516,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -72538,7 +72538,7 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -74519,7 +74519,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -74549,7 +74549,7 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -75832,7 +75832,7 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -75862,7 +75862,7 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -76438,7 +76438,7 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -76468,7 +76468,7 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index 1ca8ce2b13..8a4a6e9228 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -104,7 +104,7 @@ types! {
 }
 
 types! {
-    #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))]
+    #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))]
     #![cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))]
 
     /// Arm-specific 64-bit wide vector of four packed `f16`.
@@ -750,7 +750,7 @@ pub struct uint32x4x4_t(
 #[derive(Copy, Clone, Debug)]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -763,7 +763,7 @@ pub struct float16x4x2_t(pub float16x4_t, pub float16x4_t);
 #[derive(Copy, Clone, Debug)]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -776,7 +776,7 @@ pub struct float16x4x3_t(pub float16x4_t, pub float16x4_t, pub float16x4_t);
 #[derive(Copy, Clone, Debug)]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -794,7 +794,7 @@ pub struct float16x4x4_t(
 #[derive(Copy, Clone, Debug)]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -807,7 +807,7 @@ pub struct float16x8x2_t(pub float16x8_t, pub float16x8_t);
 #[derive(Copy, Clone, Debug)]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
@@ -820,7 +820,7 @@ pub struct float16x8x3_t(pub float16x8_t, pub float16x8_t, pub float16x8_t);
 #[derive(Copy, Clone, Debug)]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 27f06691c5..8ddc3d29a3 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -247,7 +247,7 @@ pub const fn _mm512_setr_ph(
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_setzero_ph() -> __m128h {
     unsafe { transmute(f16x8::ZERO) }
@@ -258,7 +258,7 @@ pub const fn _mm_setzero_ph() -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_setzero_ph() -> __m256h {
     f16x16::ZERO.as_m256h()
@@ -269,7 +269,7 @@ pub const fn _mm256_setzero_ph() -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_setzero_ph() -> __m512h {
     f16x32::ZERO.as_m512h()
@@ -283,7 +283,7 @@ pub const fn _mm512_setzero_ph() -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_undefined_ph() -> __m128h {
     f16x8::ZERO.as_m128h()
@@ -297,7 +297,7 @@ pub const fn _mm_undefined_ph() -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_undefined_ph() -> __m256h {
     f16x16::ZERO.as_m256h()
@@ -311,7 +311,7 @@ pub const fn _mm256_undefined_ph() -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_undefined_ph() -> __m512h {
     f16x32::ZERO.as_m512h()
@@ -323,7 +323,7 @@ pub const fn _mm512_undefined_ph() -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castpd_ph(a: __m128d) -> __m128h {
     unsafe { transmute(a) }
@@ -335,7 +335,7 @@ pub const fn _mm_castpd_ph(a: __m128d) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h {
     unsafe { transmute(a) }
@@ -347,7 +347,7 @@ pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h {
     unsafe { transmute(a) }
@@ -359,7 +359,7 @@ pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_pd)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castph_pd(a: __m128h) -> __m128d {
     unsafe { transmute(a) }
@@ -371,7 +371,7 @@ pub const fn _mm_castph_pd(a: __m128h) -> __m128d {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_pd)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph_pd(a: __m256h) -> __m256d {
     unsafe { transmute(a) }
@@ -383,7 +383,7 @@ pub const fn _mm256_castph_pd(a: __m256h) -> __m256d {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_pd)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph_pd(a: __m512h) -> __m512d {
     unsafe { transmute(a) }
@@ -395,7 +395,7 @@ pub const fn _mm512_castph_pd(a: __m512h) -> __m512d {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castps_ph(a: __m128) -> __m128h {
     unsafe { transmute(a) }
@@ -407,7 +407,7 @@ pub const fn _mm_castps_ph(a: __m128) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castps_ph(a: __m256) -> __m256h {
     unsafe { transmute(a) }
@@ -419,7 +419,7 @@ pub const fn _mm256_castps_ph(a: __m256) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castps_ph(a: __m512) -> __m512h {
     unsafe { transmute(a) }
@@ -431,7 +431,7 @@ pub const fn _mm512_castps_ph(a: __m512) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_ps)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castph_ps(a: __m128h) -> __m128 {
     unsafe { transmute(a) }
@@ -443,7 +443,7 @@ pub const fn _mm_castph_ps(a: __m128h) -> __m128 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_ps)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph_ps(a: __m256h) -> __m256 {
     unsafe { transmute(a) }
@@ -455,7 +455,7 @@ pub const fn _mm256_castph_ps(a: __m256h) -> __m256 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_ps)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph_ps(a: __m512h) -> __m512 {
     unsafe { transmute(a) }
@@ -467,7 +467,7 @@ pub const fn _mm512_castph_ps(a: __m512h) -> __m512 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h {
     unsafe { transmute(a) }
@@ -479,7 +479,7 @@ pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
     unsafe { transmute(a) }
@@ -491,7 +491,7 @@ pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
     unsafe { transmute(a) }
@@ -503,7 +503,7 @@ pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_si128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_castph_si128(a: __m128h) -> __m128i {
     unsafe { transmute(a) }
@@ -515,7 +515,7 @@ pub const fn _mm_castph_si128(a: __m128h) -> __m128i {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_si256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph_si256(a: __m256h) -> __m256i {
     unsafe { transmute(a) }
@@ -527,7 +527,7 @@ pub const fn _mm256_castph_si256(a: __m256h) -> __m256i {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_si512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph_si512(a: __m512h) -> __m512i {
     unsafe { transmute(a) }
@@ -539,7 +539,7 @@ pub const fn _mm512_castph_si512(a: __m512h) -> __m512i {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph256_ph128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -551,7 +551,7 @@ pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -563,7 +563,7 @@ pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
@@ -576,7 +576,7 @@ pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph128_ph256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
     unsafe {
@@ -595,7 +595,7 @@ pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph128_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
     unsafe {
@@ -617,7 +617,7 @@ pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph256_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
     unsafe {
@@ -639,7 +639,7 @@ pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
     unsafe {
@@ -658,7 +658,7 @@ pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph256_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
     unsafe {
@@ -680,7 +680,7 @@ pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph128_ph512)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h {
     unsafe {
@@ -730,7 +730,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -746,7 +746,7 @@ pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -761,7 +761,7 @@ pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -777,7 +777,7 @@ pub fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
     k1: __mmask16,
     a: __m256h,
@@ -796,7 +796,7 @@ pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -812,7 +812,7 @@ pub fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
     k1: __mmask32,
     a: __m512h,
@@ -833,7 +833,7 @@ pub fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
     a: __m512h,
     b: __m512h,
@@ -868,7 +868,7 @@ pub fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
     k1: __mmask32,
     a: __m512h,
@@ -903,7 +903,7 @@ pub fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __mmask8 {
     static_assert_uimm_bits!(IMM5, 5);
     static_assert_sae!(SAE);
@@ -918,7 +918,7 @@ pub fn _mm_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(
     k1: __mmask8,
     a: __m128h,
@@ -938,7 +938,7 @@ pub fn _mm_mask_cmp_round_sh_mask<const IMM5: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmp_sh_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
     static_assert_uimm_bits!(IMM5, 5);
     _mm_cmp_round_sh_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(a, b)
@@ -951,7 +951,7 @@ pub fn _mm_cmp_sh_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cmp_sh_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
     static_assert_uimm_bits!(IMM5, 5);
     _mm_mask_cmp_round_sh_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(k1, a, b)
@@ -965,7 +965,7 @@ pub fn _mm_mask_cmp_sh_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comi_round_sh<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h) -> i32 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
@@ -981,7 +981,7 @@ pub fn _mm_comi_round_sh<const IMM5: i32, const SAE: i32>(a: __m128h, b: __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comi_sh<const IMM5: i32>(a: __m128h, b: __m128h) -> i32 {
     static_assert_uimm_bits!(IMM5, 5);
     _mm_comi_round_sh::<IMM5, _MM_FROUND_CUR_DIRECTION>(a, b)
@@ -993,7 +993,7 @@ pub fn _mm_comi_sh<const IMM5: i32>(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_EQ_OS>(a, b)
 }
@@ -1004,7 +1004,7 @@ pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GE_OS>(a, b)
 }
@@ -1015,7 +1015,7 @@ pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GT_OS>(a, b)
 }
@@ -1026,7 +1026,7 @@ pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LE_OS>(a, b)
 }
@@ -1037,7 +1037,7 @@ pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LT_OS>(a, b)
 }
@@ -1048,7 +1048,7 @@ pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_NEQ_US>(a, b)
 }
@@ -1059,7 +1059,7 @@ pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_EQ_OQ>(a, b)
 }
@@ -1070,7 +1070,7 @@ pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GE_OQ>(a, b)
 }
@@ -1081,7 +1081,7 @@ pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_GT_OQ>(a, b)
 }
@@ -1092,7 +1092,7 @@ pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LE_OQ>(a, b)
 }
@@ -1103,7 +1103,7 @@ pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_LT_OQ>(a, b)
 }
@@ -1114,7 +1114,7 @@ pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 {
     _mm_comi_sh::<_CMP_NEQ_UQ>(a, b)
 }
@@ -1248,7 +1248,7 @@ pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1267,7 +1267,7 @@ pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1285,7 +1285,7 @@ pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sh)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1399,7 +1399,7 @@ pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_add(a, b) }
@@ -1412,7 +1412,7 @@ pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1428,7 +1428,7 @@ pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1443,7 +1443,7 @@ pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_add(a, b) }
@@ -1456,7 +1456,7 @@ pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1472,7 +1472,7 @@ pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1487,7 +1487,7 @@ pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_add(a, b) }
@@ -1500,7 +1500,7 @@ pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1516,7 +1516,7 @@ pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1539,7 +1539,7 @@ pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_add_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -1562,7 +1562,7 @@ pub fn _mm512_add_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_add_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -1590,7 +1590,7 @@ pub fn _mm512_mask_add_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_add_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -1618,7 +1618,7 @@ pub fn _mm512_maskz_add_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_add_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_add_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -1640,7 +1640,7 @@ pub fn _mm_add_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_add_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -1669,7 +1669,7 @@ pub fn _mm_mask_add_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_add_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_add_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -1682,7 +1682,7 @@ pub fn _mm_maskz_add_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) }
@@ -1696,7 +1696,7 @@ pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1719,7 +1719,7 @@ pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vaddsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1739,7 +1739,7 @@ pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_sub(a, b) }
@@ -1752,7 +1752,7 @@ pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1768,7 +1768,7 @@ pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -1783,7 +1783,7 @@ pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_sub(a, b) }
@@ -1796,7 +1796,7 @@ pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1812,7 +1812,7 @@ pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -1827,7 +1827,7 @@ pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_sub(a, b) }
@@ -1840,7 +1840,7 @@ pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1856,7 +1856,7 @@ pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -1879,7 +1879,7 @@ pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_sub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -1902,7 +1902,7 @@ pub fn _mm512_sub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_sub_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -1931,7 +1931,7 @@ pub fn _mm512_mask_sub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_sub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -1959,7 +1959,7 @@ pub fn _mm512_maskz_sub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_sub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_sub_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -1981,7 +1981,7 @@ pub fn _mm_sub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_sub_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -2010,7 +2010,7 @@ pub fn _mm_mask_sub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_sub_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_sub_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -2023,7 +2023,7 @@ pub fn _mm_maskz_sub_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) }
@@ -2037,7 +2037,7 @@ pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2060,7 +2060,7 @@ pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsubsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2080,7 +2080,7 @@ pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_mul(a, b) }
@@ -2093,7 +2093,7 @@ pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2109,7 +2109,7 @@ pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2124,7 +2124,7 @@ pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_mul(a, b) }
@@ -2137,7 +2137,7 @@ pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2153,7 +2153,7 @@ pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2168,7 +2168,7 @@ pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_mul(a, b) }
@@ -2181,7 +2181,7 @@ pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2197,7 +2197,7 @@ pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2220,7 +2220,7 @@ pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mul_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -2243,7 +2243,7 @@ pub fn _mm512_mul_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_mul_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -2272,7 +2272,7 @@ pub fn _mm512_mask_mul_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_mul_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -2300,7 +2300,7 @@ pub fn _mm512_maskz_mul_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mul_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_mul_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -2322,7 +2322,7 @@ pub fn _mm_mul_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_mul_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -2351,7 +2351,7 @@ pub fn _mm_mask_mul_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_mul_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_mul_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -2364,7 +2364,7 @@ pub fn _mm_maskz_mul_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) }
@@ -2378,7 +2378,7 @@ pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2401,7 +2401,7 @@ pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmulsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2421,7 +2421,7 @@ pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_div(a, b) }
@@ -2434,7 +2434,7 @@ pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2450,7 +2450,7 @@ pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2465,7 +2465,7 @@ pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_div(a, b) }
@@ -2478,7 +2478,7 @@ pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2494,7 +2494,7 @@ pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe {
@@ -2509,7 +2509,7 @@ pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_div(a, b) }
@@ -2522,7 +2522,7 @@ pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2538,7 +2538,7 @@ pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
@@ -2561,7 +2561,7 @@ pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_div_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -2584,7 +2584,7 @@ pub fn _mm512_div_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m51
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_div_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -2613,7 +2613,7 @@ pub fn _mm512_mask_div_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_div_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -2641,7 +2641,7 @@ pub fn _mm512_maskz_div_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_div_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_div_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -2663,7 +2663,7 @@ pub fn _mm_div_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_div_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -2692,7 +2692,7 @@ pub fn _mm_mask_div_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_div_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_div_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -2705,7 +2705,7 @@ pub fn _mm_maskz_div_round_sh<const ROUNDING: i32>(k: __mmask8, a: __m128h, b: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) }
@@ -2719,7 +2719,7 @@ pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2742,7 +2742,7 @@ pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vdivsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe {
@@ -2764,7 +2764,7 @@ pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_pch(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -2777,7 +2777,7 @@ pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { transmute(vfmulcph_128(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -2790,7 +2790,7 @@ pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_pch(_mm_setzero_ph(), k, a, b)
 }
@@ -2803,7 +2803,7 @@ pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_mul_pch(_mm256_undefined_ph(), 0xff, a, b)
 }
@@ -2816,7 +2816,7 @@ pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     unsafe { transmute(vfmulcph_256(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -2829,7 +2829,7 @@ pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_mul_pch(_mm256_setzero_ph(), k, a, b)
 }
@@ -2842,7 +2842,7 @@ pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_pch(_mm512_undefined_ph(), 0xffff, a, b)
 }
@@ -2855,7 +2855,7 @@ pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -2868,7 +2868,7 @@ pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_pch(_mm512_setzero_ph(), k, a, b)
 }
@@ -2890,7 +2890,7 @@ pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_mul_round_pch::<ROUNDING>(_mm512_undefined_ph(), 0xffff, a, b)
@@ -2913,7 +2913,7 @@ pub fn _mm512_mul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_mul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -2949,7 +2949,7 @@ pub fn _mm512_mask_mul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_mul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -2968,7 +2968,7 @@ pub fn _mm512_maskz_mul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -2982,7 +2982,7 @@ pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -2996,7 +2996,7 @@ pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -3019,7 +3019,7 @@ pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_mul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -3043,7 +3043,7 @@ pub fn _mm_mul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_mul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -3080,7 +3080,7 @@ pub fn _mm_mask_mul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_mul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -3098,7 +3098,7 @@ pub fn _mm_maskz_mul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mul_pch(a, b)
 }
@@ -3111,7 +3111,7 @@ pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_pch(src, k, a, b)
 }
@@ -3124,7 +3124,7 @@ pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_mul_pch(k, a, b)
 }
@@ -3137,7 +3137,7 @@ pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mul_pch(a, b)
 }
@@ -3150,7 +3150,7 @@ pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_mul_pch(src, k, a, b)
 }
@@ -3163,7 +3163,7 @@ pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_maskz_mul_pch(k, a, b)
 }
@@ -3175,7 +3175,7 @@ pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mul_pch(a, b)
 }
@@ -3188,7 +3188,7 @@ pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_mul_pch(src, k, a, b)
 }
@@ -3201,7 +3201,7 @@ pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_maskz_mul_pch(k, a, b)
 }
@@ -3221,7 +3221,7 @@ pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mul_round_pch::<ROUNDING>(a, b)
@@ -3243,7 +3243,7 @@ pub fn _mm512_fmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -3270,7 +3270,7 @@ pub fn _mm512_mask_fmul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -3288,7 +3288,7 @@ pub fn _mm512_maskz_fmul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mul_sch(a, b)
 }
@@ -3301,7 +3301,7 @@ pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_mul_sch(src, k, a, b)
 }
@@ -3314,7 +3314,7 @@ pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_mul_sch(k, a, b)
 }
@@ -3335,7 +3335,7 @@ pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mul_round_sch::<ROUNDING>(a, b)
@@ -3358,7 +3358,7 @@ pub fn _mm_fmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -3386,7 +3386,7 @@ pub fn _mm_mask_fmul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -3405,7 +3405,7 @@ pub fn _mm_maskz_fmul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_pch(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -3419,7 +3419,7 @@ pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { transmute(vfcmulcph_128(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -3433,7 +3433,7 @@ pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_pch(_mm_setzero_ph(), k, a, b)
 }
@@ -3447,7 +3447,7 @@ pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_cmul_pch(_mm256_undefined_ph(), 0xff, a, b)
 }
@@ -3461,7 +3461,7 @@ pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     unsafe { transmute(vfcmulcph_256(transmute(a), transmute(b), transmute(src), k)) }
 }
@@ -3475,7 +3475,7 @@ pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_cmul_pch(_mm256_setzero_ph(), k, a, b)
 }
@@ -3489,7 +3489,7 @@ pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_pch(_mm512_undefined_ph(), 0xffff, a, b)
 }
@@ -3503,7 +3503,7 @@ pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -3517,7 +3517,7 @@ pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_pch(_mm512_setzero_ph(), k, a, b)
 }
@@ -3540,7 +3540,7 @@ pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cmul_round_pch::<ROUNDING>(_mm512_undefined_ph(), 0xffff, a, b)
@@ -3564,7 +3564,7 @@ pub fn _mm512_cmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cmul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -3601,7 +3601,7 @@ pub fn _mm512_mask_cmul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cmul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -3619,7 +3619,7 @@ pub fn _mm512_maskz_cmul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -3633,7 +3633,7 @@ pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -3647,7 +3647,7 @@ pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -3669,7 +3669,7 @@ pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_cmul_round_sch::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -3693,7 +3693,7 @@ pub fn _mm_cmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cmul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -3730,7 +3730,7 @@ pub fn _mm_mask_cmul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cmul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -3749,7 +3749,7 @@ pub fn _mm_maskz_cmul_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h {
     _mm_cmul_pch(a, b)
 }
@@ -3763,7 +3763,7 @@ pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_pch(src, k, a, b)
 }
@@ -3777,7 +3777,7 @@ pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_cmul_pch(k, a, b)
 }
@@ -3791,7 +3791,7 @@ pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h {
     _mm256_cmul_pch(a, b)
 }
@@ -3805,7 +3805,7 @@ pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_cmul_pch(src, k, a, b)
 }
@@ -3819,7 +3819,7 @@ pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
     _mm256_maskz_cmul_pch(k, a, b)
 }
@@ -3833,7 +3833,7 @@ pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h {
     _mm512_cmul_pch(a, b)
 }
@@ -3847,7 +3847,7 @@ pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_cmul_pch(src, k, a, b)
 }
@@ -3861,7 +3861,7 @@ pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
     _mm512_maskz_cmul_pch(k, a, b)
 }
@@ -3883,7 +3883,7 @@ pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fcmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_cmul_round_pch::<ROUNDING>(a, b)
@@ -3907,7 +3907,7 @@ pub fn _mm512_fcmul_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fcmul_round_pch<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask16,
@@ -3936,7 +3936,7 @@ pub fn _mm512_mask_fcmul_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fcmul_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -3955,7 +3955,7 @@ pub fn _mm512_maskz_fcmul_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h {
     _mm_cmul_sch(a, b)
 }
@@ -3969,7 +3969,7 @@ pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_cmul_sch(src, k, a, b)
 }
@@ -3983,7 +3983,7 @@ pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_maskz_cmul_sch(k, a, b)
 }
@@ -4005,7 +4005,7 @@ pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fcmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_cmul_round_sch::<ROUNDING>(a, b)
@@ -4029,7 +4029,7 @@ pub fn _mm_fcmul_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fcmul_round_sch<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -4058,7 +4058,7 @@ pub fn _mm_mask_fcmul_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fcmul_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -4074,7 +4074,7 @@ pub fn _mm_maskz_fcmul_round_sch<const ROUNDING: i32>(
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_abs_ph(v2: __m128h) -> __m128h {
     unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) }
@@ -4086,7 +4086,7 @@ pub const fn _mm_abs_ph(v2: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h {
     unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) }
@@ -4098,7 +4098,7 @@ pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h {
     unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) }
@@ -4112,7 +4112,7 @@ pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_conj_pch(a: __m128h) -> __m128h {
     unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) }
@@ -4126,7 +4126,7 @@ pub const fn _mm_conj_pch(a: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
@@ -4143,7 +4143,7 @@ pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_conj_pch(_mm_setzero_ph(), k, a)
@@ -4156,7 +4156,7 @@ pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_conj_pch(a: __m256h) -> __m256h {
     unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) }
@@ -4170,7 +4170,7 @@ pub const fn _mm256_conj_pch(a: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h {
     unsafe {
@@ -4187,7 +4187,7 @@ pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m2
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
     _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a)
@@ -4200,7 +4200,7 @@ pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_conj_pch(a: __m512h) -> __m512h {
     unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) }
@@ -4214,7 +4214,7 @@ pub const fn _mm512_conj_pch(a: __m512h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h {
     unsafe {
@@ -4231,7 +4231,7 @@ pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_conj_pch)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
     _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a)
@@ -4245,7 +4245,7 @@ pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask3_fmadd_pch(a, b, c, 0xff)
 }
@@ -4259,7 +4259,7 @@ pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let r: __m128 = transmute(_mm_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4276,7 +4276,7 @@ pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         transmute(vfmaddcph_mask3_128(
@@ -4297,7 +4297,7 @@ pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         transmute(vfmaddcph_maskz_128(
@@ -4317,7 +4317,7 @@ pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_mask3_fmadd_pch(a, b, c, 0xff)
 }
@@ -4331,7 +4331,7 @@ pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         let r: __m256 = transmute(_mm256_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4348,7 +4348,7 @@ pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h {
     unsafe {
         transmute(vfmaddcph_mask3_256(
@@ -4369,7 +4369,7 @@ pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         transmute(vfmaddcph_maskz_256(
@@ -4389,7 +4389,7 @@ pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -4403,7 +4403,7 @@ pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h {
     _mm512_mask_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -4417,7 +4417,7 @@ pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h {
     _mm512_mask3_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -4431,7 +4431,7 @@ pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_maskz_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -4453,7 +4453,7 @@ pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask3_fmadd_round_pch::<ROUNDING>(a, b, c, 0xffff)
@@ -4477,7 +4477,7 @@ pub fn _mm512_fmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask16,
@@ -4509,7 +4509,7 @@ pub fn _mm512_mask_fmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -4546,7 +4546,7 @@ pub fn _mm512_mask3_fmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmadd_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -4574,7 +4574,7 @@ pub fn _mm512_maskz_fmadd_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -4589,7 +4589,7 @@ pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -4604,7 +4604,7 @@ pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     _mm_mask3_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -4619,7 +4619,7 @@ pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_maskz_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -4641,7 +4641,7 @@ pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -4674,7 +4674,7 @@ pub fn _mm_fmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -4708,7 +4708,7 @@ pub fn _mm_mask_fmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -4742,7 +4742,7 @@ pub fn _mm_mask3_fmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmadd_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -4770,7 +4770,7 @@ pub fn _mm_maskz_fmadd_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask3_fcmadd_pch(a, b, c, 0xff)
 }
@@ -4785,7 +4785,7 @@ pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         let r: __m128 = transmute(_mm_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4803,7 +4803,7 @@ pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
         transmute(vfcmaddcph_mask3_128(
@@ -4825,7 +4825,7 @@ pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         transmute(vfcmaddcph_maskz_128(
@@ -4846,7 +4846,7 @@ pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_mask3_fcmadd_pch(a, b, c, 0xff)
 }
@@ -4861,7 +4861,7 @@ pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         let r: __m256 = transmute(_mm256_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does
@@ -4879,7 +4879,7 @@ pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h {
     unsafe {
         transmute(vfcmaddcph_mask3_256(
@@ -4901,7 +4901,7 @@ pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
         transmute(vfcmaddcph_maskz_256(
@@ -4922,7 +4922,7 @@ pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -4937,7 +4937,7 @@ pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h {
     _mm512_mask_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -4952,7 +4952,7 @@ pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h {
     _mm512_mask3_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -4967,7 +4967,7 @@ pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_maskz_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -4990,7 +4990,7 @@ pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fcmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask3_fcmadd_round_pch::<ROUNDING>(a, b, c, 0xffff)
@@ -5015,7 +5015,7 @@ pub fn _mm512_fcmadd_round_pch<const ROUNDING: i32>(a: __m512h, b: __m512h, c: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fcmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask16,
@@ -5048,7 +5048,7 @@ pub fn _mm512_mask_fcmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fcmadd_round_pch<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -5086,7 +5086,7 @@ pub fn _mm512_mask3_fcmadd_round_pch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fcmadd_round_pch<const ROUNDING: i32>(
     k: __mmask16,
     a: __m512h,
@@ -5115,7 +5115,7 @@ pub fn _mm512_maskz_fcmadd_round_pch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c)
 }
@@ -5131,7 +5131,7 @@ pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     _mm_mask_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c)
 }
@@ -5147,7 +5147,7 @@ pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     _mm_mask3_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k)
 }
@@ -5163,7 +5163,7 @@ pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_maskz_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c)
 }
@@ -5187,7 +5187,7 @@ pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fcmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -5221,7 +5221,7 @@ pub fn _mm_fcmadd_round_sch<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m1
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fcmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -5256,7 +5256,7 @@ pub fn _mm_mask_fcmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fcmadd_round_sch<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -5291,7 +5291,7 @@ pub fn _mm_mask3_fcmadd_round_sch<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fcmadd_round_sch<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -5317,7 +5317,7 @@ pub fn _mm_maskz_fcmadd_round_sch<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(a, b, c) }
@@ -5331,7 +5331,7 @@ pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) }
@@ -5345,7 +5345,7 @@ pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) }
@@ -5359,7 +5359,7 @@ pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) }
@@ -5372,7 +5372,7 @@ pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(a, b, c) }
@@ -5386,7 +5386,7 @@ pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) }
@@ -5400,7 +5400,7 @@ pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) }
@@ -5414,7 +5414,7 @@ pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) }
@@ -5427,7 +5427,7 @@ pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(a, b, c) }
@@ -5441,7 +5441,7 @@ pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) }
@@ -5455,7 +5455,7 @@ pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) }
@@ -5469,7 +5469,7 @@ pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) }
@@ -5491,7 +5491,7 @@ pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -5516,7 +5516,7 @@ pub fn _mm512_fmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -5546,7 +5546,7 @@ pub fn _mm512_mask_fmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -5576,7 +5576,7 @@ pub fn _mm512_mask3_fmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmadd_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -5601,7 +5601,7 @@ pub fn _mm512_maskz_fmadd_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -5622,7 +5622,7 @@ pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -5645,7 +5645,7 @@ pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -5668,7 +5668,7 @@ pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -5700,7 +5700,7 @@ pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -5730,7 +5730,7 @@ pub fn _mm_fmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -5767,7 +5767,7 @@ pub fn _mm_mask_fmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -5804,7 +5804,7 @@ pub fn _mm_mask3_fmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmadd_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -5832,7 +5832,7 @@ pub fn _mm_maskz_fmadd_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
@@ -5846,7 +5846,7 @@ pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) }
@@ -5860,7 +5860,7 @@ pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) }
@@ -5874,7 +5874,7 @@ pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) }
@@ -5887,7 +5887,7 @@ pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
@@ -5901,7 +5901,7 @@ pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) }
@@ -5915,7 +5915,7 @@ pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) }
@@ -5929,7 +5929,7 @@ pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) }
@@ -5942,7 +5942,7 @@ pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(a, b, simd_neg(c)) }
@@ -5956,7 +5956,7 @@ pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) }
@@ -5970,7 +5970,7 @@ pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) }
@@ -5984,7 +5984,7 @@ pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) }
@@ -6006,7 +6006,7 @@ pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6031,7 +6031,7 @@ pub fn _mm512_fmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -6061,7 +6061,7 @@ pub fn _mm512_mask_fmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -6091,7 +6091,7 @@ pub fn _mm512_mask3_fmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmsub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -6116,7 +6116,7 @@ pub fn _mm512_maskz_fmsub_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6137,7 +6137,7 @@ pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6160,7 +6160,7 @@ pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -6183,7 +6183,7 @@ pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6215,7 +6215,7 @@ pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6245,7 +6245,7 @@ pub fn _mm_fmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -6282,7 +6282,7 @@ pub fn _mm_mask_fmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -6311,7 +6311,7 @@ pub fn _mm_mask3_fmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fmsub_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -6338,7 +6338,7 @@ pub fn _mm_maskz_fmsub_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(simd_neg(a), b, c) }
@@ -6352,7 +6352,7 @@ pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) }
@@ -6366,7 +6366,7 @@ pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) }
@@ -6380,7 +6380,7 @@ pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) }
@@ -6393,7 +6393,7 @@ pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(simd_neg(a), b, c) }
@@ -6407,7 +6407,7 @@ pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) }
@@ -6421,7 +6421,7 @@ pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) }
@@ -6435,7 +6435,7 @@ pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) }
@@ -6448,7 +6448,7 @@ pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(simd_neg(a), b, c) }
@@ -6462,7 +6462,7 @@ pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) }
@@ -6476,7 +6476,7 @@ pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) }
@@ -6490,7 +6490,7 @@ pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) }
@@ -6512,7 +6512,7 @@ pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fnmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6537,7 +6537,7 @@ pub fn _mm512_fnmadd_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fnmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -6567,7 +6567,7 @@ pub fn _mm512_mask_fnmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fnmadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -6597,7 +6597,7 @@ pub fn _mm512_mask3_fnmadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fnmadd_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -6622,7 +6622,7 @@ pub fn _mm512_maskz_fnmadd_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6643,7 +6643,7 @@ pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6666,7 +6666,7 @@ pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -6689,7 +6689,7 @@ pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -6721,7 +6721,7 @@ pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fnmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -6751,7 +6751,7 @@ pub fn _mm_fnmadd_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fnmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -6788,7 +6788,7 @@ pub fn _mm_mask_fnmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fnmadd_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -6825,7 +6825,7 @@ pub fn _mm_mask3_fnmadd_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fnmadd_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -6852,7 +6852,7 @@ pub fn _mm_maskz_fnmadd_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
@@ -6866,7 +6866,7 @@ pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) }
@@ -6880,7 +6880,7 @@ pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) }
@@ -6894,7 +6894,7 @@ pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) }
@@ -6907,7 +6907,7 @@ pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
@@ -6921,7 +6921,7 @@ pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) }
@@ -6935,7 +6935,7 @@ pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) }
@@ -6949,7 +6949,7 @@ pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) }
@@ -6962,7 +6962,7 @@ pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) }
@@ -6976,7 +6976,7 @@ pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) }
@@ -6990,7 +6990,7 @@ pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) }
@@ -7004,7 +7004,7 @@ pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) }
@@ -7026,7 +7026,7 @@ pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fnmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -7051,7 +7051,7 @@ pub fn _mm512_fnmsub_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h, c: __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fnmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -7081,7 +7081,7 @@ pub fn _mm512_mask_fnmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fnmsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7111,7 +7111,7 @@ pub fn _mm512_mask3_fnmsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fnmsub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -7136,7 +7136,7 @@ pub fn _mm512_maskz_fnmsub_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7157,7 +7157,7 @@ pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7180,7 +7180,7 @@ pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe {
@@ -7203,7 +7203,7 @@ pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7235,7 +7235,7 @@ pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fnmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -7265,7 +7265,7 @@ pub fn _mm_fnmsub_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h, c: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fnmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     k: __mmask8,
@@ -7302,7 +7302,7 @@ pub fn _mm_mask_fnmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask3_fnmsub_round_sh<const ROUNDING: i32>(
     a: __m128h,
     b: __m128h,
@@ -7339,7 +7339,7 @@ pub fn _mm_mask3_fnmsub_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_fnmsub_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -7366,7 +7366,7 @@ pub fn _mm_maskz_fnmsub_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe {
@@ -7384,7 +7384,7 @@ pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) }
@@ -7398,7 +7398,7 @@ pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) }
@@ -7412,7 +7412,7 @@ pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) }
@@ -7425,7 +7425,7 @@ pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe {
@@ -7447,7 +7447,7 @@ pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) }
@@ -7461,7 +7461,7 @@ pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) }
@@ -7475,7 +7475,7 @@ pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) }
@@ -7488,7 +7488,7 @@ pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe {
@@ -7513,7 +7513,7 @@ pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) }
@@ -7527,7 +7527,7 @@ pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) }
@@ -7541,7 +7541,7 @@ pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) }
@@ -7563,7 +7563,7 @@ pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmaddsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7592,7 +7592,7 @@ pub fn _mm512_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmaddsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -7622,7 +7622,7 @@ pub fn _mm512_mask_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fmaddsub_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7652,7 +7652,7 @@ pub fn _mm512_mask3_fmaddsub_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmaddsub_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -7676,7 +7676,7 @@ pub fn _mm512_maskz_fmaddsub_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
@@ -7690,7 +7690,7 @@ pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) }
@@ -7704,7 +7704,7 @@ pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) }
@@ -7718,7 +7718,7 @@ pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) }
@@ -7731,7 +7731,7 @@ pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
@@ -7745,7 +7745,7 @@ pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) }
@@ -7759,7 +7759,7 @@ pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) }
@@ -7773,7 +7773,7 @@ pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) }
@@ -7786,7 +7786,7 @@ pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) })
@@ -7800,7 +7800,7 @@ pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) }
@@ -7814,7 +7814,7 @@ pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) }
@@ -7828,7 +7828,7 @@ pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) }
@@ -7850,7 +7850,7 @@ pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fmsubadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7879,7 +7879,7 @@ pub fn _mm512_fmsubadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fmsubadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     k: __mmask32,
@@ -7909,7 +7909,7 @@ pub fn _mm512_mask_fmsubadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask3_fmsubadd_round_ph<const ROUNDING: i32>(
     a: __m512h,
     b: __m512h,
@@ -7939,7 +7939,7 @@ pub fn _mm512_mask3_fmsubadd_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_fmsubadd_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -7963,7 +7963,7 @@ pub fn _mm512_maskz_fmsubadd_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_rcp_ph(a: __m128h) -> __m128h {
     _mm_mask_rcp_ph(_mm_undefined_ph(), 0xff, a)
 }
@@ -7976,7 +7976,7 @@ pub fn _mm_rcp_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { vrcpph_128(a, src, k) }
 }
@@ -7989,7 +7989,7 @@ pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_rcp_ph(_mm_setzero_ph(), k, a)
 }
@@ -8001,7 +8001,7 @@ pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_rcp_ph(a: __m256h) -> __m256h {
     _mm256_mask_rcp_ph(_mm256_undefined_ph(), 0xffff, a)
 }
@@ -8014,7 +8014,7 @@ pub fn _mm256_rcp_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { vrcpph_256(a, src, k) }
 }
@@ -8027,7 +8027,7 @@ pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h {
     _mm256_mask_rcp_ph(_mm256_setzero_ph(), k, a)
 }
@@ -8039,7 +8039,7 @@ pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_rcp_ph(a: __m512h) -> __m512h {
     _mm512_mask_rcp_ph(_mm512_undefined_ph(), 0xffffffff, a)
 }
@@ -8052,7 +8052,7 @@ pub fn _mm512_rcp_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     unsafe { vrcpph_512(a, src, k) }
 }
@@ -8065,7 +8065,7 @@ pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_rcp_ph(_mm512_setzero_ph(), k, a)
 }
@@ -8079,7 +8079,7 @@ pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -8093,7 +8093,7 @@ pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { vrcpsh(a, b, src, k) }
 }
@@ -8107,7 +8107,7 @@ pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrcpsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8120,7 +8120,7 @@ pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h {
     _mm_mask_rsqrt_ph(_mm_undefined_ph(), 0xff, a)
 }
@@ -8134,7 +8134,7 @@ pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { vrsqrtph_128(a, src, k) }
 }
@@ -8148,7 +8148,7 @@ pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_rsqrt_ph(_mm_setzero_ph(), k, a)
 }
@@ -8161,7 +8161,7 @@ pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h {
     _mm256_mask_rsqrt_ph(_mm256_undefined_ph(), 0xffff, a)
 }
@@ -8175,7 +8175,7 @@ pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { vrsqrtph_256(a, src, k) }
 }
@@ -8189,7 +8189,7 @@ pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
     _mm256_mask_rsqrt_ph(_mm256_setzero_ph(), k, a)
 }
@@ -8202,7 +8202,7 @@ pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h {
     _mm512_mask_rsqrt_ph(_mm512_undefined_ph(), 0xffffffff, a)
 }
@@ -8216,7 +8216,7 @@ pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     unsafe { vrsqrtph_512(a, src, k) }
 }
@@ -8230,7 +8230,7 @@ pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_rsqrt_ph(_mm512_setzero_ph(), k, a)
 }
@@ -8244,7 +8244,7 @@ pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -8258,7 +8258,7 @@ pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { vrsqrtsh(a, b, src, k) }
 }
@@ -8272,7 +8272,7 @@ pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrsqrtsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8284,7 +8284,7 @@ pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_sqrt_ph(a: __m128h) -> __m128h {
     unsafe { simd_fsqrt(a) }
 }
@@ -8296,7 +8296,7 @@ pub fn _mm_sqrt_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), src) }
 }
@@ -8308,7 +8308,7 @@ pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), _mm_setzero_ph()) }
 }
@@ -8320,7 +8320,7 @@ pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h {
     unsafe { simd_fsqrt(a) }
 }
@@ -8332,7 +8332,7 @@ pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), src) }
 }
@@ -8344,7 +8344,7 @@ pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), _mm256_setzero_ph()) }
 }
@@ -8356,7 +8356,7 @@ pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h {
     unsafe { simd_fsqrt(a) }
 }
@@ -8368,7 +8368,7 @@ pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), src) }
 }
@@ -8380,7 +8380,7 @@ pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), _mm512_setzero_ph()) }
 }
@@ -8400,7 +8400,7 @@ pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_sqrt_round_ph<const ROUNDING: i32>(a: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -8423,7 +8423,7 @@ pub fn _mm512_sqrt_round_ph<const ROUNDING: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_sqrt_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -8450,7 +8450,7 @@ pub fn _mm512_mask_sqrt_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_sqrt_round_ph<const ROUNDING: i32>(k: __mmask32, a: __m512h) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -8466,7 +8466,7 @@ pub fn _mm512_maskz_sqrt_round_ph<const ROUNDING: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -8479,7 +8479,7 @@ pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_sqrt_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -8492,7 +8492,7 @@ pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8513,7 +8513,7 @@ pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_sqrt_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_sqrt_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -8535,7 +8535,7 @@ pub fn _mm_sqrt_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_sqrt_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -8564,7 +8564,7 @@ pub fn _mm_mask_sqrt_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_sqrt_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -8582,7 +8582,7 @@ pub fn _mm_maskz_sqrt_round_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { vmaxph_128(a, b) }
 }
@@ -8596,7 +8596,7 @@ pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), src) }
 }
@@ -8610,7 +8610,7 @@ pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), _mm_setzero_ph()) }
 }
@@ -8623,7 +8623,7 @@ pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { vmaxph_256(a, b) }
 }
@@ -8637,7 +8637,7 @@ pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), src) }
 }
@@ -8651,7 +8651,7 @@ pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), _mm256_setzero_ph()) }
 }
@@ -8664,7 +8664,7 @@ pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h {
     _mm512_max_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b)
 }
@@ -8678,7 +8678,7 @@ pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), src) }
 }
@@ -8692,7 +8692,7 @@ pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), _mm512_setzero_ph()) }
 }
@@ -8707,7 +8707,7 @@ pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_max_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -8725,7 +8725,7 @@ pub fn _mm512_max_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_max_round_ph<const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -8748,7 +8748,7 @@ pub fn _mm512_mask_max_round_ph<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_max_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -8765,7 +8765,7 @@ pub fn _mm512_maskz_max_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_max_sh(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -8779,7 +8779,7 @@ pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_max_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -8793,7 +8793,7 @@ pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_max_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -8808,7 +8808,7 @@ pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_max_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_max_round_sh::<SAE>(_mm_undefined_ph(), 0xff, a, b)
@@ -8825,7 +8825,7 @@ pub fn _mm_max_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_max_round_sh<const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -8849,7 +8849,7 @@ pub fn _mm_mask_max_round_sh<const SAE: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_max_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_max_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -8863,7 +8863,7 @@ pub fn _mm_maskz_max_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h {
     unsafe { vminph_128(a, b) }
 }
@@ -8877,7 +8877,7 @@ pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), src) }
 }
@@ -8891,7 +8891,7 @@ pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), _mm_setzero_ph()) }
 }
@@ -8904,7 +8904,7 @@ pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h {
     unsafe { vminph_256(a, b) }
 }
@@ -8918,7 +8918,7 @@ pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), src) }
 }
@@ -8932,7 +8932,7 @@ pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), _mm256_setzero_ph()) }
 }
@@ -8945,7 +8945,7 @@ pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h {
     _mm512_min_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b)
 }
@@ -8959,7 +8959,7 @@ pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), src) }
 }
@@ -8973,7 +8973,7 @@ pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), _mm512_setzero_ph()) }
 }
@@ -8987,7 +8987,7 @@ pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_min_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -9005,7 +9005,7 @@ pub fn _mm512_min_round_ph<const SAE: i32>(a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_min_round_ph<const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -9028,7 +9028,7 @@ pub fn _mm512_mask_min_round_ph<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vminph, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_min_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe {
         static_assert_sae!(SAE);
@@ -9045,7 +9045,7 @@ pub fn _mm512_maskz_min_round_ph<const SAE: i32>(k: __mmask32, a: __m512h, b: __
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_min_sh(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -9059,7 +9059,7 @@ pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_min_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -9073,7 +9073,7 @@ pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_min_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -9088,7 +9088,7 @@ pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_min_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_min_round_sh::<SAE>(_mm_undefined_ph(), 0xff, a, b)
@@ -9105,7 +9105,7 @@ pub fn _mm_min_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_min_round_sh<const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -9129,7 +9129,7 @@ pub fn _mm_mask_min_round_sh<const SAE: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vminsh, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_min_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_min_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -9143,7 +9143,7 @@ pub fn _mm_maskz_min_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_getexp_ph(a: __m128h) -> __m128h {
     _mm_mask_getexp_ph(_mm_undefined_ph(), 0xff, a)
 }
@@ -9157,7 +9157,7 @@ pub fn _mm_getexp_ph(a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe { vgetexpph_128(a, src, k) }
 }
@@ -9171,7 +9171,7 @@ pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h {
     _mm_mask_getexp_ph(_mm_setzero_ph(), k, a)
 }
@@ -9184,7 +9184,7 @@ pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_getexp_ph(a: __m256h) -> __m256h {
     _mm256_mask_getexp_ph(_mm256_undefined_ph(), 0xffff, a)
 }
@@ -9198,7 +9198,7 @@ pub fn _mm256_getexp_ph(a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe { vgetexpph_256(a, src, k) }
 }
@@ -9212,7 +9212,7 @@ pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h {
     _mm256_mask_getexp_ph(_mm256_setzero_ph(), k, a)
 }
@@ -9225,7 +9225,7 @@ pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_getexp_ph(a: __m512h) -> __m512h {
     _mm512_mask_getexp_ph(_mm512_undefined_ph(), 0xffffffff, a)
 }
@@ -9239,7 +9239,7 @@ pub fn _mm512_getexp_ph(a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_getexp_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a)
 }
@@ -9253,7 +9253,7 @@ pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h {
     _mm512_mask_getexp_ph(_mm512_setzero_ph(), k, a)
 }
@@ -9268,7 +9268,7 @@ pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_getexp_round_ph<const SAE: i32>(a: __m512h) -> __m512h {
     static_assert_sae!(SAE);
     _mm512_mask_getexp_round_ph::<SAE>(_mm512_undefined_ph(), 0xffffffff, a)
@@ -9284,7 +9284,7 @@ pub fn _mm512_getexp_round_ph<const SAE: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_getexp_round_ph<const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -9306,7 +9306,7 @@ pub fn _mm512_mask_getexp_round_ph<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_getexp_round_ph<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512h {
     static_assert_sae!(SAE);
     _mm512_mask_getexp_round_ph::<SAE>(_mm512_setzero_ph(), k, a)
@@ -9321,7 +9321,7 @@ pub fn _mm512_maskz_getexp_round_ph<const SAE: i32>(k: __mmask32, a: __m512h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -9336,7 +9336,7 @@ pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_getexp_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -9351,7 +9351,7 @@ pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -9367,7 +9367,7 @@ pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_getexp_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_getexp_round_sh::<SAE>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -9384,7 +9384,7 @@ pub fn _mm_getexp_round_sh<const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_getexp_round_sh<const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -9408,7 +9408,7 @@ pub fn _mm_mask_getexp_round_sh<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_getexp_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_sae!(SAE);
     _mm_mask_getexp_round_sh::<SAE>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -9436,7 +9436,7 @@ pub fn _mm_maskz_getexp_round_sh<const SAE: i32>(k: __mmask8, a: __m128h, b: __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(1, 2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m128h,
 ) -> __m128h {
@@ -9468,7 +9468,7 @@ pub fn _mm_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTIS
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9507,7 +9507,7 @@ pub fn _mm_mask_getmant_ph<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9542,7 +9542,7 @@ pub fn _mm_maskz_getmant_ph<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(1, 2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m256h,
 ) -> __m256h {
@@ -9574,7 +9574,7 @@ pub fn _mm256_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MAN
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9613,7 +9613,7 @@ pub fn _mm256_mask_getmant_ph<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9648,7 +9648,7 @@ pub fn _mm256_maskz_getmant_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(1, 2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m512h,
 ) -> __m512h {
@@ -9680,7 +9680,7 @@ pub fn _mm512_getmant_ph<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MAN
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9717,7 +9717,7 @@ pub fn _mm512_mask_getmant_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_getmant_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9755,7 +9755,7 @@ pub fn _mm512_maskz_getmant_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(1, 2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_getmant_round_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9795,7 +9795,7 @@ pub fn _mm512_getmant_round_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4, 5)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_getmant_round_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9839,7 +9839,7 @@ pub fn _mm512_mask_getmant_round_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_getmant_round_ph<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9877,7 +9877,7 @@ pub fn _mm512_maskz_getmant_round_ph<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_getmant_sh<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTISSA_SIGN_ENUM>(
     a: __m128h,
     b: __m128h,
@@ -9911,7 +9911,7 @@ pub fn _mm_getmant_sh<const NORM: _MM_MANTISSA_NORM_ENUM, const SIGN: _MM_MANTIS
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(4, 5)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_getmant_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9950,7 +9950,7 @@ pub fn _mm_mask_getmant_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_getmant_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -9990,7 +9990,7 @@ pub fn _mm_maskz_getmant_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_getmant_round_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -10031,7 +10031,7 @@ pub fn _mm_getmant_round_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(4, 5, 6)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_getmant_round_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -10076,7 +10076,7 @@ pub fn _mm_mask_getmant_round_sh<
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vgetmantsh, NORM = 0, SIGN = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4, 5)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_getmant_round_sh<
     const NORM: _MM_MANTISSA_NORM_ENUM,
     const SIGN: _MM_MANTISSA_SIGN_ENUM,
@@ -10108,7 +10108,7 @@ pub fn _mm_maskz_getmant_round_sh<
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_roundscale_ph<const IMM8: i32>(a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_ph::<IMM8>(_mm_undefined_ph(), 0xff, a)
@@ -10131,7 +10131,7 @@ pub fn _mm_roundscale_ph<const IMM8: i32>(a: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_roundscale_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -10156,7 +10156,7 @@ pub fn _mm_mask_roundscale_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_roundscale_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_ph::<IMM8>(_mm_setzero_ph(), k, a)
@@ -10178,7 +10178,7 @@ pub fn _mm_maskz_roundscale_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m1
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_roundscale_ph<const IMM8: i32>(a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_roundscale_ph::<IMM8>(_mm256_undefined_ph(), 0xffff, a)
@@ -10201,7 +10201,7 @@ pub fn _mm256_roundscale_ph<const IMM8: i32>(a: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_roundscale_ph<const IMM8: i32>(
     src: __m256h,
     k: __mmask16,
@@ -10230,7 +10230,7 @@ pub fn _mm256_mask_roundscale_ph<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_roundscale_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_roundscale_ph::<IMM8>(_mm256_setzero_ph(), k, a)
@@ -10252,7 +10252,7 @@ pub fn _mm256_maskz_roundscale_ph<const IMM8: i32>(k: __mmask16, a: __m256h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_roundscale_ph<const IMM8: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_roundscale_ph::<IMM8>(_mm512_undefined_ph(), 0xffffffff, a)
@@ -10275,7 +10275,7 @@ pub fn _mm512_roundscale_ph<const IMM8: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_roundscale_ph<const IMM8: i32>(
     src: __m512h,
     k: __mmask32,
@@ -10302,7 +10302,7 @@ pub fn _mm512_mask_roundscale_ph<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_roundscale_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_roundscale_ph::<IMM8>(_mm512_setzero_ph(), k, a)
@@ -10325,7 +10325,7 @@ pub fn _mm512_maskz_roundscale_ph<const IMM8: i32>(k: __mmask32, a: __m512h) ->
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(1, 2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_roundscale_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -10350,7 +10350,7 @@ pub fn _mm512_roundscale_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -10380,7 +10380,7 @@ pub fn _mm512_mask_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
     k: __mmask32,
     a: __m512h,
@@ -10407,7 +10407,7 @@ pub fn _mm512_maskz_roundscale_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_roundscale_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_sh::<IMM8>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -10430,7 +10430,7 @@ pub fn _mm_roundscale_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_roundscale_sh<const IMM8: i32>(
     src: __m128h,
     k: __mmask8,
@@ -10458,7 +10458,7 @@ pub fn _mm_mask_roundscale_sh<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_roundscale_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_roundscale_sh::<IMM8>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -10483,7 +10483,7 @@ pub fn _mm_maskz_roundscale_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m1
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_roundscale_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -10509,7 +10509,7 @@ pub fn _mm_roundscale_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: _
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(4, 5)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -10542,7 +10542,7 @@ pub fn _mm_mask_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
     k: __mmask8,
     a: __m128h,
@@ -10560,7 +10560,7 @@ pub fn _mm_maskz_roundscale_round_sh<const IMM8: i32, const SAE: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_ph(_mm_undefined_ph(), 0xff, a, b)
 }
@@ -10572,7 +10572,7 @@ pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { vscalefph_128(a, b, src, k) }
 }
@@ -10584,7 +10584,7 @@ pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_ph(_mm_setzero_ph(), k, a, b)
 }
@@ -10596,7 +10596,7 @@ pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_scalef_ph(_mm256_undefined_ph(), 0xffff, a, b)
 }
@@ -10608,7 +10608,7 @@ pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { vscalefph_256(a, b, src, k) }
 }
@@ -10620,7 +10620,7 @@ pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     _mm256_mask_scalef_ph(_mm256_setzero_ph(), k, a, b)
 }
@@ -10632,7 +10632,7 @@ pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_scalef_ph(_mm512_undefined_ph(), 0xffffffff, a, b)
 }
@@ -10644,7 +10644,7 @@ pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_scalef_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -10656,7 +10656,7 @@ pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     _mm512_mask_scalef_ph(_mm512_setzero_ph(), k, a, b)
 }
@@ -10677,7 +10677,7 @@ pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_scalef_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_scalef_round_ph::<ROUNDING>(_mm512_undefined_ph(), 0xffffffff, a, b)
@@ -10699,7 +10699,7 @@ pub fn _mm512_scalef_round_ph<const ROUNDING: i32>(a: __m512h, b: __m512h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_scalef_round_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -10728,7 +10728,7 @@ pub fn _mm512_mask_scalef_round_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_scalef_round_ph<const ROUNDING: i32>(
     k: __mmask32,
     a: __m512h,
@@ -10746,7 +10746,7 @@ pub fn _mm512_maskz_scalef_round_ph<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -10759,7 +10759,7 @@ pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b)
 }
@@ -10772,7 +10772,7 @@ pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -10794,7 +10794,7 @@ pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_scalef_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_scalef_round_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -10817,7 +10817,7 @@ pub fn _mm_scalef_round_sh<const ROUNDING: i32>(a: __m128h, b: __m128h) -> __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_scalef_round_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -10847,7 +10847,7 @@ pub fn _mm_mask_scalef_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_scalef_round_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -10873,7 +10873,7 @@ pub fn _mm_maskz_scalef_round_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_reduce_ph<const IMM8: i32>(a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_ph::<IMM8>(_mm_undefined_ph(), 0xff, a)
@@ -10896,7 +10896,7 @@ pub fn _mm_reduce_ph<const IMM8: i32>(a: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_reduce_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h) -> __m128h {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -10921,7 +10921,7 @@ pub fn _mm_mask_reduce_ph<const IMM8: i32>(src: __m128h, k: __mmask8, a: __m128h
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_reduce_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_ph::<IMM8>(_mm_setzero_ph(), k, a)
@@ -10943,7 +10943,7 @@ pub fn _mm_maskz_reduce_ph<const IMM8: i32>(k: __mmask8, a: __m128h) -> __m128h
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_reduce_ph<const IMM8: i32>(a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_reduce_ph::<IMM8>(_mm256_undefined_ph(), 0xffff, a)
@@ -10966,7 +10966,7 @@ pub fn _mm256_reduce_ph<const IMM8: i32>(a: __m256h) -> __m256h {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_reduce_ph<const IMM8: i32>(src: __m256h, k: __mmask16, a: __m256h) -> __m256h {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -10991,7 +10991,7 @@ pub fn _mm256_mask_reduce_ph<const IMM8: i32>(src: __m256h, k: __mmask16, a: __m
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_reduce_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m256h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm256_mask_reduce_ph::<IMM8>(_mm256_setzero_ph(), k, a)
@@ -11013,7 +11013,7 @@ pub fn _mm256_maskz_reduce_ph<const IMM8: i32>(k: __mmask16, a: __m256h) -> __m2
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_reduce_ph<const IMM8: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_reduce_ph::<IMM8>(_mm512_undefined_ph(), 0xffffffff, a)
@@ -11036,7 +11036,7 @@ pub fn _mm512_reduce_ph<const IMM8: i32>(a: __m512h) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_reduce_ph<const IMM8: i32>(src: __m512h, k: __mmask32, a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_reduce_round_ph::<IMM8, _MM_FROUND_CUR_DIRECTION>(src, k, a)
@@ -11059,7 +11059,7 @@ pub fn _mm512_mask_reduce_ph<const IMM8: i32>(src: __m512h, k: __mmask32, a: __m
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_reduce_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm512_mask_reduce_ph::<IMM8>(_mm512_setzero_ph(), k, a)
@@ -11083,7 +11083,7 @@ pub fn _mm512_maskz_reduce_ph<const IMM8: i32>(k: __mmask32, a: __m512h) -> __m5
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(1, 2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_reduce_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __m512h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -11109,7 +11109,7 @@ pub fn _mm512_reduce_round_ph<const IMM8: i32, const SAE: i32>(a: __m512h) -> __
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_reduce_round_ph<const IMM8: i32, const SAE: i32>(
     src: __m512h,
     k: __mmask32,
@@ -11141,7 +11141,7 @@ pub fn _mm512_mask_reduce_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_reduce_round_ph<const IMM8: i32, const SAE: i32>(
     k: __mmask32,
     a: __m512h,
@@ -11168,7 +11168,7 @@ pub fn _mm512_maskz_reduce_round_ph<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_reduce_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_sh::<IMM8>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -11192,7 +11192,7 @@ pub fn _mm_reduce_sh<const IMM8: i32>(a: __m128h, b: __m128h) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_reduce_sh<const IMM8: i32>(
     src: __m128h,
     k: __mmask8,
@@ -11221,7 +11221,7 @@ pub fn _mm_mask_reduce_sh<const IMM8: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_reduce_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     _mm_mask_reduce_sh::<IMM8>(f16x8::ZERO.as_m128h(), k, a, b)
@@ -11246,7 +11246,7 @@ pub fn _mm_maskz_reduce_sh<const IMM8: i32>(k: __mmask8, a: __m128h, b: __m128h)
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(2, 3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_reduce_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m128h) -> __m128h {
     static_assert_uimm_bits!(IMM8, 8);
     static_assert_sae!(SAE);
@@ -11273,7 +11273,7 @@ pub fn _mm_reduce_round_sh<const IMM8: i32, const SAE: i32>(a: __m128h, b: __m12
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(4, 5)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_reduce_round_sh<const IMM8: i32, const SAE: i32>(
     src: __m128h,
     k: __mmask8,
@@ -11307,7 +11307,7 @@ pub fn _mm_mask_reduce_round_sh<const IMM8: i32, const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))]
 #[rustc_legacy_const_generics(3, 4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_reduce_round_sh<const IMM8: i32, const SAE: i32>(
     k: __mmask8,
     a: __m128h,
@@ -11582,7 +11582,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11609,7 +11609,7 @@ pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11635,7 +11635,7 @@ pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11662,7 +11662,7 @@ pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11688,7 +11688,7 @@ pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11715,7 +11715,7 @@ pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask32, a: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11741,7 +11741,7 @@ pub fn _mm512_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask32, a: __m512h) -
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_fpclass_sh_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
     _mm_mask_fpclass_sh_mask::<IMM8>(0xff, a)
 }
@@ -11765,7 +11765,7 @@ pub fn _mm_fpclass_sh_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fpclass_sh_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
@@ -11779,7 +11779,7 @@ pub fn _mm_mask_fpclass_sh_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_blend_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
     unsafe { simd_select_bitmask(k, b, a) }
@@ -11791,7 +11791,7 @@ pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_blend_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h {
     unsafe { simd_select_bitmask(k, b, a) }
@@ -11803,7 +11803,7 @@ pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m25
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h {
     unsafe { simd_select_bitmask(k, b, a) }
@@ -11815,7 +11815,7 @@ pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m51
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutex2var_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h {
     _mm_castsi128_ph(_mm_permutex2var_epi16(
         _mm_castph_si128(a),
@@ -11830,7 +11830,7 @@ pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex2var_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h {
     _mm256_castsi256_ph(_mm256_permutex2var_epi16(
         _mm256_castph_si256(a),
@@ -11845,7 +11845,7 @@ pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h {
     _mm512_castsi512_ph(_mm512_permutex2var_epi16(
         _mm512_castph_si512(a),
@@ -11860,7 +11860,7 @@ pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutexvar_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h {
     _mm_castsi128_ph(_mm_permutexvar_epi16(idx, _mm_castph_si128(a)))
 }
@@ -11871,7 +11871,7 @@ pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutexvar_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h {
     _mm256_castsi256_ph(_mm256_permutexvar_epi16(idx, _mm256_castph_si256(a)))
 }
@@ -11882,7 +11882,7 @@ pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ph)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h {
     _mm512_castsi512_ph(_mm512_permutexvar_epi16(idx, _mm512_castph_si512(a)))
 }
@@ -11894,7 +11894,7 @@ pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h {
     unsafe { vcvtw2ph_128(a.as_i16x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -11907,7 +11907,7 @@ pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_cvtepi16_ph(a), src) }
 }
@@ -11919,7 +11919,7 @@ pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepi16_ph(_mm_setzero_ph(), k, a)
 }
@@ -11931,7 +11931,7 @@ pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h {
     unsafe { vcvtw2ph_256(a.as_i16x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -11944,7 +11944,7 @@ pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepi16_ph(a), src) }
 }
@@ -11956,7 +11956,7 @@ pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h {
     _mm256_mask_cvtepi16_ph(_mm256_setzero_ph(), k, a)
 }
@@ -11968,7 +11968,7 @@ pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h {
     unsafe { vcvtw2ph_512(a.as_i16x32(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -11981,7 +11981,7 @@ pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepi16_ph(a), src) }
 }
@@ -11993,7 +11993,7 @@ pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h {
     _mm512_mask_cvtepi16_ph(_mm512_setzero_ph(), k, a)
 }
@@ -12014,7 +12014,7 @@ pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundepi16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12039,7 +12039,7 @@ pub fn _mm512_cvt_roundepi16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundepi16_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -12067,7 +12067,7 @@ pub fn _mm512_mask_cvt_roundepi16_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundepi16_ph<const ROUNDING: i32>(k: __mmask32, a: __m512i) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepi16_ph::<ROUNDING>(_mm512_setzero_ph(), k, a)
@@ -12080,7 +12080,7 @@ pub fn _mm512_maskz_cvt_roundepi16_ph<const ROUNDING: i32>(k: __mmask32, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h {
     unsafe { vcvtuw2ph_128(a.as_u16x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12093,7 +12093,7 @@ pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm_cvtepu16_ph(a), src) }
 }
@@ -12105,7 +12105,7 @@ pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepu16_ph(_mm_setzero_ph(), k, a)
 }
@@ -12117,7 +12117,7 @@ pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h {
     unsafe { vcvtuw2ph_256(a.as_u16x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12130,7 +12130,7 @@ pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepu16_ph(a), src) }
 }
@@ -12142,7 +12142,7 @@ pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h {
     _mm256_mask_cvtepu16_ph(_mm256_setzero_ph(), k, a)
 }
@@ -12154,7 +12154,7 @@ pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h {
     unsafe { vcvtuw2ph_512(a.as_u16x32(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12167,7 +12167,7 @@ pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepu16_ph(a), src) }
 }
@@ -12179,7 +12179,7 @@ pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h {
     _mm512_mask_cvtepu16_ph(_mm512_setzero_ph(), k, a)
 }
@@ -12200,7 +12200,7 @@ pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundepu16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12225,7 +12225,7 @@ pub fn _mm512_cvt_roundepu16_ph<const ROUNDING: i32>(a: __m512i) -> __m512h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundepu16_ph<const ROUNDING: i32>(
     src: __m512h,
     k: __mmask32,
@@ -12253,7 +12253,7 @@ pub fn _mm512_mask_cvt_roundepu16_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundepu16_ph<const ROUNDING: i32>(k: __mmask32, a: __m512i) -> __m512h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepu16_ph::<ROUNDING>(_mm512_setzero_ph(), k, a)
@@ -12266,7 +12266,7 @@ pub fn _mm512_maskz_cvt_roundepu16_ph<const ROUNDING: i32>(k: __mmask32, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepi32_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12279,7 +12279,7 @@ pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtdq2ph_128(a.as_i32x4(), src, k) }
 }
@@ -12292,7 +12292,7 @@ pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepi32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12304,7 +12304,7 @@ pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h {
     unsafe { vcvtdq2ph_256(a.as_i32x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12317,7 +12317,7 @@ pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepi32_ph(a), src) }
 }
@@ -12329,7 +12329,7 @@ pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepi32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12341,7 +12341,7 @@ pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h {
     unsafe { vcvtdq2ph_512(a.as_i32x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12354,7 +12354,7 @@ pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepi32_ph(a), src) }
 }
@@ -12366,7 +12366,7 @@ pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h {
     _mm512_mask_cvtepi32_ph(f16x16::ZERO.as_m256h(), k, a)
 }
@@ -12387,7 +12387,7 @@ pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundepi32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12412,7 +12412,7 @@ pub fn _mm512_cvt_roundepi32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundepi32_ph<const ROUNDING: i32>(
     src: __m256h,
     k: __mmask16,
@@ -12440,7 +12440,7 @@ pub fn _mm512_mask_cvt_roundepi32_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundepi32_ph<const ROUNDING: i32>(k: __mmask16, a: __m512i) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepi32_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
@@ -12454,7 +12454,7 @@ pub fn _mm512_maskz_cvt_roundepi32_ph<const ROUNDING: i32>(k: __mmask16, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h {
     unsafe { vcvtsi2sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12476,7 +12476,7 @@ pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundi32_sh<const ROUNDING: i32>(a: __m128h, b: i32) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12491,7 +12491,7 @@ pub fn _mm_cvt_roundi32_sh<const ROUNDING: i32>(a: __m128h, b: i32) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepu32_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12504,7 +12504,7 @@ pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtudq2ph_128(a.as_u32x4(), src, k) }
 }
@@ -12517,7 +12517,7 @@ pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepu32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12529,7 +12529,7 @@ pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h {
     unsafe { vcvtudq2ph_256(a.as_u32x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12542,7 +12542,7 @@ pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm256_cvtepu32_ph(a), src) }
 }
@@ -12554,7 +12554,7 @@ pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepu32_ph(_mm_setzero_ph(), k, a)
 }
@@ -12566,7 +12566,7 @@ pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h {
     unsafe { vcvtudq2ph_512(a.as_u32x16(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12579,7 +12579,7 @@ pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepu32_ph(a), src) }
 }
@@ -12591,7 +12591,7 @@ pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h {
     _mm512_mask_cvtepu32_ph(f16x16::ZERO.as_m256h(), k, a)
 }
@@ -12612,7 +12612,7 @@ pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundepu32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12637,7 +12637,7 @@ pub fn _mm512_cvt_roundepu32_ph<const ROUNDING: i32>(a: __m512i) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundepu32_ph<const ROUNDING: i32>(
     src: __m256h,
     k: __mmask16,
@@ -12665,7 +12665,7 @@ pub fn _mm512_mask_cvt_roundepu32_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundepu32_ph<const ROUNDING: i32>(k: __mmask16, a: __m512i) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepu32_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
@@ -12679,7 +12679,7 @@ pub fn _mm512_maskz_cvt_roundepu32_ph<const ROUNDING: i32>(k: __mmask16, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h {
     unsafe { vcvtusi2sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12701,7 +12701,7 @@ pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundu32_sh<const ROUNDING: i32>(a: __m128h, b: u32) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12716,7 +12716,7 @@ pub fn _mm_cvt_roundu32_sh<const ROUNDING: i32>(a: __m128h, b: u32) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12729,7 +12729,7 @@ pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtqq2ph_128(a.as_i64x2(), src, k) }
 }
@@ -12742,7 +12742,7 @@ pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepi64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12754,7 +12754,7 @@ pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h {
     _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12767,7 +12767,7 @@ pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { vcvtqq2ph_256(a.as_i64x4(), src, k) }
 }
@@ -12780,7 +12780,7 @@ pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12792,7 +12792,7 @@ pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h {
     unsafe { vcvtqq2ph_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12805,7 +12805,7 @@ pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepi64_ph(a), src) }
 }
@@ -12817,7 +12817,7 @@ pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h {
     _mm512_mask_cvtepi64_ph(f16x8::ZERO.as_m128h(), k, a)
 }
@@ -12838,7 +12838,7 @@ pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundepi64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -12863,7 +12863,7 @@ pub fn _mm512_cvt_roundepi64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundepi64_ph<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -12891,7 +12891,7 @@ pub fn _mm512_mask_cvt_roundepi64_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundepi64_ph<const ROUNDING: i32>(k: __mmask8, a: __m512i) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepi64_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
@@ -12904,7 +12904,7 @@ pub fn _mm512_maskz_cvt_roundepi64_ph<const ROUNDING: i32>(k: __mmask8, a: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h {
     _mm_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12917,7 +12917,7 @@ pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
     unsafe { vcvtuqq2ph_128(a.as_u64x2(), src, k) }
 }
@@ -12930,7 +12930,7 @@ pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h {
     _mm_mask_cvtepu64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12942,7 +12942,7 @@ pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h {
     _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -12955,7 +12955,7 @@ pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h {
     unsafe { vcvtuqq2ph_256(a.as_u64x4(), src, k) }
 }
@@ -12968,7 +12968,7 @@ pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h {
     _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), k, a)
 }
@@ -12980,7 +12980,7 @@ pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h {
     unsafe { vcvtuqq2ph_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION) }
 }
@@ -12993,7 +12993,7 @@ pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h {
     unsafe { simd_select_bitmask(k, _mm512_cvtepu64_ph(a), src) }
 }
@@ -13005,7 +13005,7 @@ pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h {
     _mm512_mask_cvtepu64_ph(f16x8::ZERO.as_m128h(), k, a)
 }
@@ -13026,7 +13026,7 @@ pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundepu64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -13051,7 +13051,7 @@ pub fn _mm512_cvt_roundepu64_ph<const ROUNDING: i32>(a: __m512i) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundepu64_ph<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13079,7 +13079,7 @@ pub fn _mm512_mask_cvt_roundepu64_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundepu64_ph<const ROUNDING: i32>(k: __mmask8, a: __m512i) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundepu64_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
@@ -13092,7 +13092,7 @@ pub fn _mm512_maskz_cvt_roundepu64_ph<const ROUNDING: i32>(k: __mmask8, a: __m51
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtxps_ph(a: __m128) -> __m128h {
     _mm_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13105,7 +13105,7 @@ pub fn _mm_cvtxps_ph(a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h {
     unsafe { vcvtps2phx_128(a, src, k) }
 }
@@ -13118,7 +13118,7 @@ pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h {
     _mm_mask_cvtxps_ph(_mm_setzero_ph(), k, a)
 }
@@ -13130,7 +13130,7 @@ pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h {
     _mm256_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13143,7 +13143,7 @@ pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h {
     unsafe { vcvtps2phx_256(a, src, k) }
 }
@@ -13156,7 +13156,7 @@ pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h {
     _mm256_mask_cvtxps_ph(_mm_setzero_ph(), k, a)
 }
@@ -13168,7 +13168,7 @@ pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h {
     _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), 0xffff, a)
 }
@@ -13181,7 +13181,7 @@ pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h {
     unsafe { vcvtps2phx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13194,7 +13194,7 @@ pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h {
     _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), k, a)
 }
@@ -13215,7 +13215,7 @@ pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtx_roundps_ph<const ROUNDING: i32>(a: __m512) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvtx_roundps_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), 0xffff, a)
@@ -13238,7 +13238,7 @@ pub fn _mm512_cvtx_roundps_ph<const ROUNDING: i32>(a: __m512) -> __m256h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtx_roundps_ph<const ROUNDING: i32>(
     src: __m256h,
     k: __mmask16,
@@ -13267,7 +13267,7 @@ pub fn _mm512_mask_cvtx_roundps_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtx_roundps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512) -> __m256h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvtx_roundps_ph::<ROUNDING>(f16x16::ZERO.as_m256h(), k, a)
@@ -13281,7 +13281,7 @@ pub fn _mm512_maskz_cvtx_roundps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h {
     _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -13295,7 +13295,7 @@ pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __m128h {
     unsafe { vcvtss2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13309,7 +13309,7 @@ pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h {
     _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -13331,7 +13331,7 @@ pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundss_sh<const ROUNDING: i32>(a: __m128h, b: __m128) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_cvt_roundss_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -13355,7 +13355,7 @@ pub fn _mm_cvt_roundss_sh<const ROUNDING: i32>(a: __m128h, b: __m128) -> __m128h
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvt_roundss_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13386,7 +13386,7 @@ pub fn _mm_mask_cvt_roundss_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvt_roundss_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -13403,7 +13403,7 @@ pub fn _mm_maskz_cvt_roundss_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h {
     _mm_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13416,7 +13416,7 @@ pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h {
     unsafe { vcvtpd2ph_128(a, src, k) }
 }
@@ -13429,7 +13429,7 @@ pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h {
     _mm_mask_cvtpd_ph(_mm_setzero_ph(), k, a)
 }
@@ -13441,7 +13441,7 @@ pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h {
     _mm256_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a)
 }
@@ -13454,7 +13454,7 @@ pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h {
     unsafe { vcvtpd2ph_256(a, src, k) }
 }
@@ -13467,7 +13467,7 @@ pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h {
     _mm256_mask_cvtpd_ph(_mm_setzero_ph(), k, a)
 }
@@ -13479,7 +13479,7 @@ pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h {
     _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), 0xff, a)
 }
@@ -13492,7 +13492,7 @@ pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h {
     unsafe { vcvtpd2ph_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13505,7 +13505,7 @@ pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h {
     _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), k, a)
 }
@@ -13526,7 +13526,7 @@ pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundpd_ph<const ROUNDING: i32>(a: __m512d) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundpd_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a)
@@ -13549,7 +13549,7 @@ pub fn _mm512_cvt_roundpd_ph<const ROUNDING: i32>(a: __m512d) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundpd_ph<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13578,7 +13578,7 @@ pub fn _mm512_mask_cvt_roundpd_ph<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundpd_ph<const ROUNDING: i32>(k: __mmask8, a: __m512d) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundpd_ph::<ROUNDING>(f16x8::ZERO.as_m128h(), k, a)
@@ -13592,7 +13592,7 @@ pub fn _mm512_maskz_cvt_roundpd_ph<const ROUNDING: i32>(k: __mmask8, a: __m512d)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h {
     _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), 0xff, a, b)
 }
@@ -13606,7 +13606,7 @@ pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
     unsafe { vcvtsd2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -13620,7 +13620,7 @@ pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
     _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), k, a, b)
 }
@@ -13642,7 +13642,7 @@ pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsd_sh<const ROUNDING: i32>(a: __m128h, b: __m128d) -> __m128h {
     static_assert_rounding!(ROUNDING);
     _mm_mask_cvt_roundsd_sh::<ROUNDING>(f16x8::ZERO.as_m128h(), 0xff, a, b)
@@ -13666,7 +13666,7 @@ pub fn _mm_cvt_roundsd_sh<const ROUNDING: i32>(a: __m128h, b: __m128d) -> __m128
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvt_roundsd_sh<const ROUNDING: i32>(
     src: __m128h,
     k: __mmask8,
@@ -13697,7 +13697,7 @@ pub fn _mm_mask_cvt_roundsd_sh<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvt_roundsd_sh<const ROUNDING: i32>(
     k: __mmask8,
     a: __m128h,
@@ -13714,7 +13714,7 @@ pub fn _mm_maskz_cvt_roundsd_sh<const ROUNDING: i32>(
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi16(_mm_undefined_si128(), 0xff, a)
 }
@@ -13727,7 +13727,7 @@ pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2w_128(a, src.as_i16x8(), k)) }
 }
@@ -13739,7 +13739,7 @@ pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi16(_mm_setzero_si128(), k, a)
 }
@@ -13751,7 +13751,7 @@ pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epi16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -13764,7 +13764,7 @@ pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvtph2w_256(a, src.as_i16x16(), k)) }
 }
@@ -13776,7 +13776,7 @@ pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epi16(_mm256_setzero_si256(), k, a)
 }
@@ -13788,7 +13788,7 @@ pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epi16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -13801,7 +13801,7 @@ pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvtph2w_512(
@@ -13820,7 +13820,7 @@ pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epi16(_mm512_setzero_si512(), k, a)
 }
@@ -13841,7 +13841,7 @@ pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_epi16<const ROUNDING: i32>(a: __m512h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi16::<ROUNDING>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -13864,7 +13864,7 @@ pub fn _mm512_cvt_roundph_epi16<const ROUNDING: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_epi16<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask32,
@@ -13892,7 +13892,7 @@ pub fn _mm512_mask_cvt_roundph_epi16<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_epi16<const ROUNDING: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi16::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -13905,7 +13905,7 @@ pub fn _mm512_maskz_cvt_roundph_epi16<const ROUNDING: i32>(k: __mmask32, a: __m5
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu16(_mm_undefined_si128(), 0xff, a)
 }
@@ -13918,7 +13918,7 @@ pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2uw_128(a, src.as_u16x8(), k)) }
 }
@@ -13930,7 +13930,7 @@ pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu16(_mm_setzero_si128(), k, a)
 }
@@ -13942,7 +13942,7 @@ pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epu16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -13955,7 +13955,7 @@ pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvtph2uw_256(a, src.as_u16x16(), k)) }
 }
@@ -13967,7 +13967,7 @@ pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvtph_epu16(_mm256_setzero_si256(), k, a)
 }
@@ -13979,7 +13979,7 @@ pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epu16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -13992,7 +13992,7 @@ pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvtph2uw_512(
@@ -14011,7 +14011,7 @@ pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvtph_epu16(_mm512_setzero_si512(), k, a)
 }
@@ -14026,7 +14026,7 @@ pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_epu16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -14043,7 +14043,7 @@ pub fn _mm512_cvt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_epu16<const SAE: i32>(
     src: __m512i,
     k: __mmask32,
@@ -14065,7 +14065,7 @@ pub fn _mm512_mask_cvt_roundph_epu16<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_epu16::<SAE>(_mm512_setzero_si512(), k, a)
@@ -14078,7 +14078,7 @@ pub fn _mm512_maskz_cvt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi16(_mm_undefined_si128(), 0xff, a)
 }
@@ -14091,7 +14091,7 @@ pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2w_128(a, src.as_i16x8(), k)) }
 }
@@ -14104,7 +14104,7 @@ pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi16(_mm_setzero_si128(), k, a)
 }
@@ -14116,7 +14116,7 @@ pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epi16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -14129,7 +14129,7 @@ pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvttph2w_256(a, src.as_i16x16(), k)) }
 }
@@ -14142,7 +14142,7 @@ pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epi16(_mm256_setzero_si256(), k, a)
 }
@@ -14154,7 +14154,7 @@ pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epi16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -14167,7 +14167,7 @@ pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvttph2w_512(
@@ -14187,7 +14187,7 @@ pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epi16(_mm512_setzero_si512(), k, a)
 }
@@ -14202,7 +14202,7 @@ pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtt_roundph_epi16<const SAE: i32>(a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -14219,7 +14219,7 @@ pub fn _mm512_cvtt_roundph_epi16<const SAE: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtt_roundph_epi16<const SAE: i32>(
     src: __m512i,
     k: __mmask32,
@@ -14242,7 +14242,7 @@ pub fn _mm512_mask_cvtt_roundph_epi16<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtt_roundph_epi16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi16::<SAE>(_mm512_setzero_si512(), k, a)
@@ -14255,7 +14255,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi16<const SAE: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu16(_mm_undefined_si128(), 0xff, a)
 }
@@ -14268,7 +14268,7 @@ pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2uw_128(a, src.as_u16x8(), k)) }
 }
@@ -14281,7 +14281,7 @@ pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu16(_mm_setzero_si128(), k, a)
 }
@@ -14293,7 +14293,7 @@ pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epu16(_mm256_undefined_si256(), 0xffff, a)
 }
@@ -14306,7 +14306,7 @@ pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i {
     unsafe { transmute(vcvttph2uw_256(a, src.as_u16x16(), k)) }
 }
@@ -14319,7 +14319,7 @@ pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m25
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i {
     _mm256_mask_cvttph_epu16(_mm256_setzero_si256(), k, a)
 }
@@ -14331,7 +14331,7 @@ pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epu16(_mm512_undefined_epi32(), 0xffffffff, a)
 }
@@ -14344,7 +14344,7 @@ pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i {
     unsafe {
         transmute(vcvttph2uw_512(
@@ -14364,7 +14364,7 @@ pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i {
     _mm512_mask_cvttph_epu16(_mm512_setzero_si512(), k, a)
 }
@@ -14379,7 +14379,7 @@ pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu16::<SAE>(_mm512_undefined_epi32(), 0xffffffff, a)
@@ -14396,7 +14396,7 @@ pub fn _mm512_cvtt_roundph_epu16<const SAE: i32>(a: __m512h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtt_roundph_epu16<const SAE: i32>(
     src: __m512i,
     k: __mmask32,
@@ -14419,7 +14419,7 @@ pub fn _mm512_mask_cvtt_roundph_epu16<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu16::<SAE>(_mm512_setzero_si512(), k, a)
@@ -14432,7 +14432,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu16<const SAE: i32>(k: __mmask32, a: __m512h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi32(_mm_undefined_si128(), 0xff, a)
 }
@@ -14444,7 +14444,7 @@ pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2dq_128(a, src.as_i32x4(), k)) }
 }
@@ -14456,7 +14456,7 @@ pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi32(_mm_setzero_si128(), k, a)
 }
@@ -14468,7 +14468,7 @@ pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -14480,7 +14480,7 @@ pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2dq_256(a, src.as_i32x8(), k)) }
 }
@@ -14492,7 +14492,7 @@ pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi32(_mm256_setzero_si256(), k, a)
 }
@@ -14504,7 +14504,7 @@ pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epi32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -14516,7 +14516,7 @@ pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvtph2dq_512(
@@ -14535,7 +14535,7 @@ pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epi32(_mm512_setzero_si512(), k, a)
 }
@@ -14556,7 +14556,7 @@ pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_epi32<const ROUNDING: i32>(a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi32::<ROUNDING>(_mm512_undefined_epi32(), 0xffff, a)
@@ -14578,7 +14578,7 @@ pub fn _mm512_cvt_roundph_epi32<const ROUNDING: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_epi32<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask16,
@@ -14606,7 +14606,7 @@ pub fn _mm512_mask_cvt_roundph_epi32<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_epi32<const ROUNDING: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi32::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -14619,7 +14619,7 @@ pub fn _mm512_maskz_cvt_roundph_epi32<const ROUNDING: i32>(k: __mmask16, a: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsh_i32(a: __m128h) -> i32 {
     unsafe { vcvtsh2si32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -14640,7 +14640,7 @@ pub fn _mm_cvtsh_i32(a: __m128h) -> i32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsh_i32<const ROUNDING: i32>(a: __m128h) -> i32 {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -14655,7 +14655,7 @@ pub fn _mm_cvt_roundsh_i32<const ROUNDING: i32>(a: __m128h) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu32(_mm_undefined_si128(), 0xff, a)
 }
@@ -14667,7 +14667,7 @@ pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2udq_128(a, src.as_u32x4(), k)) }
 }
@@ -14679,7 +14679,7 @@ pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu32(_mm_setzero_si128(), k, a)
 }
@@ -14691,7 +14691,7 @@ pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -14703,7 +14703,7 @@ pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2udq_256(a, src.as_u32x8(), k)) }
 }
@@ -14715,7 +14715,7 @@ pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu32(_mm256_setzero_si256(), k, a)
 }
@@ -14727,7 +14727,7 @@ pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epu32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -14739,7 +14739,7 @@ pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvtph2udq_512(
@@ -14758,7 +14758,7 @@ pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvtph_epu32(_mm512_setzero_si512(), k, a)
 }
@@ -14779,7 +14779,7 @@ pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_epu32<const ROUNDING: i32>(a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu32::<ROUNDING>(_mm512_undefined_epi32(), 0xffff, a)
@@ -14801,7 +14801,7 @@ pub fn _mm512_cvt_roundph_epu32<const ROUNDING: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_epu32<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask16,
@@ -14829,7 +14829,7 @@ pub fn _mm512_mask_cvt_roundph_epu32<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_epu32<const ROUNDING: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu32::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -14842,7 +14842,7 @@ pub fn _mm512_maskz_cvt_roundph_epu32<const ROUNDING: i32>(k: __mmask16, a: __m2
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsh_u32(a: __m128h) -> u32 {
     unsafe { vcvtsh2usi32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -14857,7 +14857,7 @@ pub fn _mm_cvtsh_u32(a: __m128h) -> u32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
     unsafe {
         static_assert_rounding!(SAE);
@@ -14872,7 +14872,7 @@ pub fn _mm_cvt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi32(_mm_undefined_si128(), 0xff, a)
 }
@@ -14884,7 +14884,7 @@ pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2dq_128(a, src.as_i32x4(), k)) }
 }
@@ -14896,7 +14896,7 @@ pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi32(_mm_setzero_si128(), k, a)
 }
@@ -14908,7 +14908,7 @@ pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -14920,7 +14920,7 @@ pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2dq_256(a, src.as_i32x8(), k)) }
 }
@@ -14932,7 +14932,7 @@ pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi32(_mm256_setzero_si256(), k, a)
 }
@@ -14944,7 +14944,7 @@ pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epi32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -14956,7 +14956,7 @@ pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvttph2dq_512(
@@ -14975,7 +14975,7 @@ pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epi32(_mm512_setzero_si512(), k, a)
 }
@@ -14990,7 +14990,7 @@ pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtt_roundph_epi32<const SAE: i32>(a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi32::<SAE>(_mm512_undefined_epi32(), 0xffff, a)
@@ -15006,7 +15006,7 @@ pub fn _mm512_cvtt_roundph_epi32<const SAE: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtt_roundph_epi32<const SAE: i32>(
     src: __m512i,
     k: __mmask16,
@@ -15028,7 +15028,7 @@ pub fn _mm512_mask_cvtt_roundph_epi32<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtt_roundph_epi32<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi32::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15041,7 +15041,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi32<const SAE: i32>(k: __mmask16, a: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttsh_i32(a: __m128h) -> i32 {
     unsafe { vcvttsh2si32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -15056,7 +15056,7 @@ pub fn _mm_cvttsh_i32(a: __m128h) -> i32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtt_roundsh_i32<const SAE: i32>(a: __m128h) -> i32 {
     unsafe {
         static_assert_sae!(SAE);
@@ -15071,7 +15071,7 @@ pub fn _mm_cvtt_roundsh_i32<const SAE: i32>(a: __m128h) -> i32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu32(_mm_undefined_si128(), 0xff, a)
 }
@@ -15083,7 +15083,7 @@ pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2udq_128(a, src.as_u32x4(), k)) }
 }
@@ -15095,7 +15095,7 @@ pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu32(_mm_setzero_si128(), k, a)
 }
@@ -15107,7 +15107,7 @@ pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu32(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15119,7 +15119,7 @@ pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2udq_256(a, src.as_u32x8(), k)) }
 }
@@ -15131,7 +15131,7 @@ pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu32(_mm256_setzero_si256(), k, a)
 }
@@ -15143,7 +15143,7 @@ pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epu32(_mm512_undefined_epi32(), 0xffff, a)
 }
@@ -15155,7 +15155,7 @@ pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i {
     unsafe {
         transmute(vcvttph2udq_512(
@@ -15174,7 +15174,7 @@ pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m51
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i {
     _mm512_mask_cvttph_epu32(_mm512_setzero_si512(), k, a)
 }
@@ -15189,7 +15189,7 @@ pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtt_roundph_epu32<const SAE: i32>(a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu32::<SAE>(_mm512_undefined_epi32(), 0xffff, a)
@@ -15205,7 +15205,7 @@ pub fn _mm512_cvtt_roundph_epu32<const SAE: i32>(a: __m256h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtt_roundph_epu32<const SAE: i32>(
     src: __m512i,
     k: __mmask16,
@@ -15227,7 +15227,7 @@ pub fn _mm512_mask_cvtt_roundph_epu32<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtt_roundph_epu32<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu32::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15240,7 +15240,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu32<const SAE: i32>(k: __mmask16, a: __m256h)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttsh_u32(a: __m128h) -> u32 {
     unsafe { vcvttsh2usi32(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -15255,7 +15255,7 @@ pub fn _mm_cvttsh_u32(a: __m128h) -> u32 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
     unsafe {
         static_assert_sae!(SAE);
@@ -15270,7 +15270,7 @@ pub fn _mm_cvtt_roundsh_u32<const SAE: i32>(a: __m128h) -> u32 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15282,7 +15282,7 @@ pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2qq_128(a, src.as_i64x2(), k)) }
 }
@@ -15294,7 +15294,7 @@ pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epi64(_mm_setzero_si128(), k, a)
 }
@@ -15306,7 +15306,7 @@ pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15318,7 +15318,7 @@ pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2qq_256(a, src.as_i64x4(), k)) }
 }
@@ -15330,7 +15330,7 @@ pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epi64(_mm256_setzero_si256(), k, a)
 }
@@ -15342,7 +15342,7 @@ pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epi64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15354,7 +15354,7 @@ pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvtph2qq_512(
@@ -15373,7 +15373,7 @@ pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epi64(_mm512_setzero_si512(), k, a)
 }
@@ -15394,7 +15394,7 @@ pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_epi64<const ROUNDING: i32>(a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi64::<ROUNDING>(_mm512_undefined_epi32(), 0xff, a)
@@ -15416,7 +15416,7 @@ pub fn _mm512_cvt_roundph_epi64<const ROUNDING: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_epi64<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15444,7 +15444,7 @@ pub fn _mm512_mask_cvt_roundph_epi64<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_epi64<const ROUNDING: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epi64::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -15457,7 +15457,7 @@ pub fn _mm512_maskz_cvt_roundph_epi64<const ROUNDING: i32>(k: __mmask8, a: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15469,7 +15469,7 @@ pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvtph2uqq_128(a, src.as_u64x2(), k)) }
 }
@@ -15481,7 +15481,7 @@ pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvtph_epu64(_mm_setzero_si128(), k, a)
 }
@@ -15493,7 +15493,7 @@ pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15505,7 +15505,7 @@ pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvtph2uqq_256(a, src.as_u64x4(), k)) }
 }
@@ -15517,7 +15517,7 @@ pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvtph_epu64(_mm256_setzero_si256(), k, a)
 }
@@ -15529,7 +15529,7 @@ pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epu64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15541,7 +15541,7 @@ pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvtph2uqq_512(
@@ -15560,7 +15560,7 @@ pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvtph_epu64(_mm512_setzero_si512(), k, a)
 }
@@ -15581,7 +15581,7 @@ pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_epu64<const ROUNDING: i32>(a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu64::<ROUNDING>(_mm512_undefined_epi32(), 0xff, a)
@@ -15603,7 +15603,7 @@ pub fn _mm512_cvt_roundph_epu64<const ROUNDING: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_epu64<const ROUNDING: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15631,7 +15631,7 @@ pub fn _mm512_mask_cvt_roundph_epu64<const ROUNDING: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_epu64<const ROUNDING: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_rounding!(ROUNDING);
     _mm512_mask_cvt_roundph_epu64::<ROUNDING>(_mm512_setzero_si512(), k, a)
@@ -15644,7 +15644,7 @@ pub fn _mm512_maskz_cvt_roundph_epu64<const ROUNDING: i32>(k: __mmask8, a: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15656,7 +15656,7 @@ pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2qq_128(a, src.as_i64x2(), k)) }
 }
@@ -15668,7 +15668,7 @@ pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epi64(_mm_setzero_si128(), k, a)
 }
@@ -15680,7 +15680,7 @@ pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15692,7 +15692,7 @@ pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2qq_256(a, src.as_i64x4(), k)) }
 }
@@ -15704,7 +15704,7 @@ pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epi64(_mm256_setzero_si256(), k, a)
 }
@@ -15716,7 +15716,7 @@ pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epi64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15728,7 +15728,7 @@ pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvttph2qq_512(
@@ -15747,7 +15747,7 @@ pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epi64(_mm512_setzero_si512(), k, a)
 }
@@ -15762,7 +15762,7 @@ pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtt_roundph_epi64<const SAE: i32>(a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi64::<SAE>(_mm512_undefined_epi32(), 0xff, a)
@@ -15778,7 +15778,7 @@ pub fn _mm512_cvtt_roundph_epi64<const SAE: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtt_roundph_epi64<const SAE: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15800,7 +15800,7 @@ pub fn _mm512_mask_cvtt_roundph_epi64<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtt_roundph_epi64<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epi64::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15813,7 +15813,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi64<const SAE: i32>(k: __mmask8, a: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu64(_mm_undefined_si128(), 0xff, a)
 }
@@ -15825,7 +15825,7 @@ pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
     unsafe { transmute(vcvttph2uqq_128(a, src.as_u64x2(), k)) }
 }
@@ -15837,7 +15837,7 @@ pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i {
     _mm_mask_cvttph_epu64(_mm_setzero_si128(), k, a)
 }
@@ -15849,7 +15849,7 @@ pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu64(_mm256_undefined_si256(), 0xff, a)
 }
@@ -15861,7 +15861,7 @@ pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i {
     unsafe { transmute(vcvttph2uqq_256(a, src.as_u64x4(), k)) }
 }
@@ -15873,7 +15873,7 @@ pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i {
     _mm256_mask_cvttph_epu64(_mm256_setzero_si256(), k, a)
 }
@@ -15885,7 +15885,7 @@ pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epu64(_mm512_undefined_epi32(), 0xff, a)
 }
@@ -15897,7 +15897,7 @@ pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i {
     unsafe {
         transmute(vcvttph2uqq_512(
@@ -15916,7 +15916,7 @@ pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i {
     _mm512_mask_cvttph_epu64(_mm512_setzero_si512(), k, a)
 }
@@ -15931,7 +15931,7 @@ pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtt_roundph_epu64<const SAE: i32>(a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu64::<SAE>(_mm512_undefined_epi32(), 0xff, a)
@@ -15947,7 +15947,7 @@ pub fn _mm512_cvtt_roundph_epu64<const SAE: i32>(a: __m128h) -> __m512i {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtt_roundph_epu64<const SAE: i32>(
     src: __m512i,
     k: __mmask8,
@@ -15969,7 +15969,7 @@ pub fn _mm512_mask_cvtt_roundph_epu64<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtt_roundph_epu64<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512i {
     static_assert_sae!(SAE);
     _mm512_mask_cvtt_roundph_epu64::<SAE>(_mm512_setzero_si512(), k, a)
@@ -15982,7 +15982,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu64<const SAE: i32>(k: __mmask8, a: __m128h)
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 {
     _mm_mask_cvtxph_ps(_mm_setzero_ps(), 0xff, a)
 }
@@ -15995,7 +15995,7 @@ pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 {
     unsafe { vcvtph2psx_128(a, src, k) }
 }
@@ -16008,7 +16008,7 @@ pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 {
     _mm_mask_cvtxph_ps(_mm_setzero_ps(), k, a)
 }
@@ -16020,7 +16020,7 @@ pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 {
     _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), 0xff, a)
 }
@@ -16033,7 +16033,7 @@ pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 {
     unsafe { vcvtph2psx_256(a, src, k) }
 }
@@ -16046,7 +16046,7 @@ pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 {
     _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), k, a)
 }
@@ -16058,7 +16058,7 @@ pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 {
     _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), 0xffff, a)
 }
@@ -16071,7 +16071,7 @@ pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 {
     unsafe { vcvtph2psx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16084,7 +16084,7 @@ pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 {
     _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), k, a)
 }
@@ -16099,7 +16099,7 @@ pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtx_roundph_ps<const SAE: i32>(a: __m256h) -> __m512 {
     static_assert_sae!(SAE);
     _mm512_mask_cvtx_roundph_ps::<SAE>(_mm512_setzero_ps(), 0xffff, a)
@@ -16116,7 +16116,7 @@ pub fn _mm512_cvtx_roundph_ps<const SAE: i32>(a: __m256h) -> __m512 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtx_roundph_ps<const SAE: i32>(
     src: __m512,
     k: __mmask16,
@@ -16139,7 +16139,7 @@ pub fn _mm512_mask_cvtx_roundph_ps<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtx_roundph_ps<const SAE: i32>(k: __mmask16, a: __m256h) -> __m512 {
     static_assert_sae!(SAE);
     _mm512_mask_cvtx_roundph_ps::<SAE>(_mm512_setzero_ps(), k, a)
@@ -16153,7 +16153,7 @@ pub fn _mm512_maskz_cvtx_roundph_ps<const SAE: i32>(k: __mmask16, a: __m256h) ->
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 {
     _mm_mask_cvtsh_ss(a, 0xff, a, b)
 }
@@ -16167,7 +16167,7 @@ pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m128 {
     unsafe { vcvtsh2ss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16181,7 +16181,7 @@ pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
     _mm_mask_cvtsh_ss(_mm_set_ss(0.0), k, a, b)
 }
@@ -16197,7 +16197,7 @@ pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsh_ss<const SAE: i32>(a: __m128, b: __m128h) -> __m128 {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_ss::<SAE>(_mm_undefined_ps(), 0xff, a, b)
@@ -16215,7 +16215,7 @@ pub fn _mm_cvt_roundsh_ss<const SAE: i32>(a: __m128, b: __m128h) -> __m128 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvt_roundsh_ss<const SAE: i32>(
     src: __m128,
     k: __mmask8,
@@ -16240,7 +16240,7 @@ pub fn _mm_mask_cvt_roundsh_ss<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvt_roundsh_ss<const SAE: i32>(k: __mmask8, a: __m128, b: __m128h) -> __m128 {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_ss::<SAE>(_mm_set_ss(0.0), k, a, b)
@@ -16253,7 +16253,7 @@ pub fn _mm_maskz_cvt_roundsh_ss<const SAE: i32>(k: __mmask8, a: __m128, b: __m12
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtph_pd(a: __m128h) -> __m128d {
     _mm_mask_cvtph_pd(_mm_setzero_pd(), 0xff, a)
 }
@@ -16266,7 +16266,7 @@ pub fn _mm_cvtph_pd(a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d {
     unsafe { vcvtph2pd_128(a, src, k) }
 }
@@ -16279,7 +16279,7 @@ pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d {
     _mm_mask_cvtph_pd(_mm_setzero_pd(), k, a)
 }
@@ -16291,7 +16291,7 @@ pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d {
     _mm256_mask_cvtph_pd(_mm256_setzero_pd(), 0xff, a)
 }
@@ -16304,7 +16304,7 @@ pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d {
     unsafe { vcvtph2pd_256(a, src, k) }
 }
@@ -16317,7 +16317,7 @@ pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16,avx512vl")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d {
     _mm256_mask_cvtph_pd(_mm256_setzero_pd(), k, a)
 }
@@ -16329,7 +16329,7 @@ pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d {
     _mm512_mask_cvtph_pd(_mm512_setzero_pd(), 0xff, a)
 }
@@ -16342,7 +16342,7 @@ pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d {
     unsafe { vcvtph2pd_512(a, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16355,7 +16355,7 @@ pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d {
     _mm512_mask_cvtph_pd(_mm512_setzero_pd(), k, a)
 }
@@ -16370,7 +16370,7 @@ pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cvt_roundph_pd<const SAE: i32>(a: __m128h) -> __m512d {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_pd::<SAE>(_mm512_setzero_pd(), 0xff, a)
@@ -16387,7 +16387,7 @@ pub fn _mm512_cvt_roundph_pd<const SAE: i32>(a: __m128h) -> __m512d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_cvt_roundph_pd<const SAE: i32>(
     src: __m512d,
     k: __mmask8,
@@ -16410,7 +16410,7 @@ pub fn _mm512_mask_cvt_roundph_pd<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_maskz_cvt_roundph_pd<const SAE: i32>(k: __mmask8, a: __m128h) -> __m512d {
     static_assert_sae!(SAE);
     _mm512_mask_cvt_roundph_pd::<SAE>(_mm512_setzero_pd(), k, a)
@@ -16424,7 +16424,7 @@ pub fn _mm512_maskz_cvt_roundph_pd<const SAE: i32>(k: __mmask8, a: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d {
     _mm_mask_cvtsh_sd(a, 0xff, a, b)
 }
@@ -16438,7 +16438,7 @@ pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
     unsafe { vcvtsh2sd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -16451,7 +16451,7 @@ pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> _
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
     _mm_mask_cvtsh_sd(_mm_set_sd(0.0), k, a, b)
 }
@@ -16467,7 +16467,7 @@ pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsh_sd<const SAE: i32>(a: __m128d, b: __m128h) -> __m128d {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_sd::<SAE>(a, 0xff, a, b)
@@ -16485,7 +16485,7 @@ pub fn _mm_cvt_roundsh_sd<const SAE: i32>(a: __m128d, b: __m128h) -> __m128d {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
 #[rustc_legacy_const_generics(4)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_cvt_roundsh_sd<const SAE: i32>(
     src: __m128d,
     k: __mmask8,
@@ -16509,7 +16509,7 @@ pub fn _mm_mask_cvt_roundsh_sd<const SAE: i32>(
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))]
 #[rustc_legacy_const_generics(3)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_maskz_cvt_roundsh_sd<const SAE: i32>(k: __mmask8, a: __m128d, b: __m128h) -> __m128d {
     static_assert_sae!(SAE);
     _mm_mask_cvt_roundsh_sd::<SAE>(_mm_set_sd(0.0), k, a, b)
@@ -16553,7 +16553,7 @@ pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si16)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
     unsafe { simd_extract!(a.as_i16x8(), 0) }
@@ -16564,7 +16564,7 @@ pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 {
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi16_si128)
 #[inline]
 #[target_feature(enable = "avx512fp16")]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i {
     unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) }
diff --git a/crates/core_arch/src/x86/avxneconvert.rs b/crates/core_arch/src/x86/avxneconvert.rs
index 91b6be2b09..b8a3b9473a 100644
--- a/crates/core_arch/src/x86/avxneconvert.rs
+++ b/crates/core_arch/src/x86/avxneconvert.rs
@@ -87,7 +87,7 @@ pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneeph2ps))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 {
     transmute(cvtneeph2ps_128(a))
 }
@@ -99,7 +99,7 @@ pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneeph2ps))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 {
     transmute(cvtneeph2ps_256(a))
 }
@@ -135,7 +135,7 @@ pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneoph2ps))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 {
     transmute(cvtneoph2ps_128(a))
 }
@@ -147,7 +147,7 @@ pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 {
 #[inline]
 #[target_feature(enable = "avxneconvert")]
 #[cfg_attr(test, assert_instr(vcvtneoph2ps))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 {
     transmute(cvtneoph2ps_256(a))
 }
diff --git a/crates/core_arch/src/x86/mod.rs b/crates/core_arch/src/x86/mod.rs
index c40fbd3ca3..9396507f08 100644
--- a/crates/core_arch/src/x86/mod.rs
+++ b/crates/core_arch/src/x86/mod.rs
@@ -401,7 +401,7 @@ types! {
 }
 
 types! {
-    #![stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+    #![stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 
     /// 128-bit wide set of 8 `f16` types, x86-specific
     ///
@@ -768,7 +768,7 @@ mod avxneconvert;
 pub use self::avxneconvert::*;
 
 mod avx512fp16;
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub use self::avx512fp16::*;
 
 mod kl;
diff --git a/crates/core_arch/src/x86_64/avx512fp16.rs b/crates/core_arch/src/x86_64/avx512fp16.rs
index 87e3651ba7..2a511328bb 100644
--- a/crates/core_arch/src/x86_64/avx512fp16.rs
+++ b/crates/core_arch/src/x86_64/avx512fp16.rs
@@ -10,7 +10,7 @@ use stdarch_test::assert_instr;
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h {
     unsafe { vcvtsi642sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -32,7 +32,7 @@ pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundi64_sh<const ROUNDING: i32>(a: __m128h, b: i64) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -48,7 +48,7 @@ pub fn _mm_cvt_roundi64_sh<const ROUNDING: i32>(a: __m128h, b: i64) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h {
     unsafe { vcvtusi642sh(a, b, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -70,7 +70,7 @@ pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))]
 #[rustc_legacy_const_generics(2)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundu64_sh<const ROUNDING: i32>(a: __m128h, b: u64) -> __m128h {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -85,7 +85,7 @@ pub fn _mm_cvt_roundu64_sh<const ROUNDING: i32>(a: __m128h, b: u64) -> __m128h {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsh_i64(a: __m128h) -> i64 {
     unsafe { vcvtsh2si64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -106,7 +106,7 @@ pub fn _mm_cvtsh_i64(a: __m128h) -> i64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsh_i64<const ROUNDING: i32>(a: __m128h) -> i64 {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -121,7 +121,7 @@ pub fn _mm_cvt_roundsh_i64<const ROUNDING: i32>(a: __m128h) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtsh_u64(a: __m128h) -> u64 {
     unsafe { vcvtsh2usi64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -142,7 +142,7 @@ pub fn _mm_cvtsh_u64(a: __m128h) -> u64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvtsh2usi, ROUNDING = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvt_roundsh_u64<const ROUNDING: i32>(a: __m128h) -> u64 {
     unsafe {
         static_assert_rounding!(ROUNDING);
@@ -157,7 +157,7 @@ pub fn _mm_cvt_roundsh_u64<const ROUNDING: i32>(a: __m128h) -> u64 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttsh_i64(a: __m128h) -> i64 {
     unsafe { vcvttsh2si64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -172,7 +172,7 @@ pub fn _mm_cvttsh_i64(a: __m128h) -> i64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtt_roundsh_i64<const SAE: i32>(a: __m128h) -> i64 {
     unsafe {
         static_assert_sae!(SAE);
@@ -187,7 +187,7 @@ pub fn _mm_cvtt_roundsh_i64<const SAE: i32>(a: __m128h) -> i64 {
 #[inline]
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi))]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvttsh_u64(a: __m128h) -> u64 {
     unsafe { vcvttsh2usi64(a, _MM_FROUND_CUR_DIRECTION) }
 }
@@ -202,7 +202,7 @@ pub fn _mm_cvttsh_u64(a: __m128h) -> u64 {
 #[target_feature(enable = "avx512fp16")]
 #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))]
 #[rustc_legacy_const_generics(1)]
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cvtt_roundsh_u64<const SAE: i32>(a: __m128h) -> u64 {
     unsafe {
         static_assert_sae!(SAE);
diff --git a/crates/core_arch/src/x86_64/mod.rs b/crates/core_arch/src/x86_64/mod.rs
index c6dc7a85e7..9caab44e46 100644
--- a/crates/core_arch/src/x86_64/mod.rs
+++ b/crates/core_arch/src/x86_64/mod.rs
@@ -75,7 +75,7 @@ mod bt;
 pub use self::bt::*;
 
 mod avx512fp16;
-#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub use self::avx512fp16::*;
 
 mod amx;
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a9bc377924..be19d34f91 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -13,9 +13,9 @@ auto_llvm_sign_conversion: false
 neon-stable: &neon-stable
   FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
 
-# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 neon-stable-fp16: &neon-stable-fp16
-  FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]
+  FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']]
 
 # #[cfg(not(target_arch = "arm64ec"))]
 target-not-arm64ec: &target-not-arm64ec
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 52748a4cc0..9c922d1a65 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -10,9 +10,9 @@ auto_big_endian: true
 neon-stable: &neon-stable
   FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
 
-# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
+# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 neon-stable-fp16: &neon-stable-fp16
-  FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]
+  FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']]
 
 # #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))]
 neon-cfg-arm-unstable: &neon-cfg-arm-unstable
@@ -55,9 +55,9 @@ neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec
 neon-not-arm-stable: &neon-not-arm-stable
   FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]]
 
-# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))]
+# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))]
 neon-not-arm-stable-fp16: &neon-not-arm-stable-fp16
-  FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]}]]
+  FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']]}]]
 
 # #[cfg_attr(all(test, not(target_env = "msvc"))]
 msvc-disabled: &msvc-disabled

From 3c618ba910b85d07fece23f550c29b9a173dbd2f Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 31 Jan 2026 22:33:56 +0100
Subject: [PATCH 136/326] x86: use `intrinsics::simd` for masked truncated
 saturating stores

---
 crates/core_arch/src/x86/avx512bw.rs | 43 ++++++++++++++++++++--------
 1 file changed, 31 insertions(+), 12 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 8e074fdcfa..3ba171c0fa 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -12476,7 +12476,14 @@ pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32,
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
-    vpmovswbmem256(mem_addr, a.as_i16x16(), k);
+    let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO);
+
+    let max = simd_splat(i16::from(i8::MAX));
+    let min = simd_splat(i16::from(i8::MIN));
+
+    let v = simd_imax(simd_imin(a.as_i16x16(), max), min);
+    let truncated: i8x16 = simd_cast(v);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated);
 }
 
 /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
@@ -12487,7 +12494,14 @@ pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16,
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
 pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
-    vpmovswbmem128(mem_addr, a.as_i16x8(), k);
+    let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO);
+
+    let max = simd_splat(i16::from(i8::MAX));
+    let min = simd_splat(i16::from(i8::MIN));
+
+    let v = simd_imax(simd_imin(a.as_i16x8(), max), min);
+    let truncated: i8x8 = simd_cast(v);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated);
 }
 
 /// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
@@ -12555,7 +12569,12 @@ pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
-    vpmovuswbmem256(mem_addr, a.as_i16x16(), k);
+    let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO);
+    let mem_addr = mem_addr.cast::<u8>();
+    let max = simd_splat(u16::from(u8::MAX));
+
+    let truncated: u8x16 = simd_cast(simd_imin(a.as_u16x16(), max));
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated);
 }
 
 /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
@@ -12566,7 +12585,15 @@ pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
 pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
-    vpmovuswbmem128(mem_addr, a.as_i16x8(), k);
+    let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO);
+    let mem_addr = mem_addr.cast::<u8>();
+    let max = simd_splat(u16::from(u8::MAX));
+
+    let v = a.as_u16x8();
+    let v = simd_imin(v, max);
+
+    let truncated: u8x8 = simd_cast(v);
+    simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated);
 }
 
 #[allow(improper_ctypes)]
@@ -12632,17 +12659,9 @@ unsafe extern "C" {
 
     #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.512"]
     fn vpmovswbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
-    #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.256"]
-    fn vpmovswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.128"]
-    fn vpmovswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
 
     #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.512"]
     fn vpmovuswbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
-    #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.256"]
-    fn vpmovuswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
-    #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.128"]
-    fn vpmovuswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
 }
 
 #[cfg(test)]

From 5c9f9969c323a8d124d5a3dbd517e6d4191f80ae Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Thu, 22 Jan 2026 09:30:20 -0600
Subject: [PATCH 137/326] arch: Add Hexagon HVX instructions

---
 .github/workflows/main.yml                    |   13 +-
 Cargo.lock                                    |  448 +
 .../hexagon-unknown-linux-musl/Dockerfile     |   46 +
 ci/run.sh                                     |    3 +
 crates/core_arch/src/core_arch_docs.md        |    2 +
 crates/core_arch/src/hexagon/hvx.rs           | 8488 +++++++++++++++++
 crates/core_arch/src/hexagon/mod.rs           |   12 +
 crates/core_arch/src/lib.rs                   |    1 +
 crates/core_arch/src/mod.rs                   |   17 +
 crates/stdarch-gen-hexagon/Cargo.toml         |   10 +
 crates/stdarch-gen-hexagon/src/main.rs        | 1697 ++++
 examples/Cargo.toml                           |    4 +
 examples/gaussian.rs                          |  358 +
 13 files changed, 11098 insertions(+), 1 deletion(-)
 create mode 100644 ci/docker/hexagon-unknown-linux-musl/Dockerfile
 create mode 100644 crates/core_arch/src/hexagon/hvx.rs
 create mode 100644 crates/core_arch/src/hexagon/mod.rs
 create mode 100644 crates/stdarch-gen-hexagon/Cargo.toml
 create mode 100644 crates/stdarch-gen-hexagon/src/main.rs
 create mode 100644 examples/gaussian.rs

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 6cf0e9f02f..0ec355aa3c 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -96,6 +96,8 @@ jobs:
           os: ubuntu-latest
         - tuple: loongarch64-unknown-linux-gnu
           os: ubuntu-latest
+        - tuple: hexagon-unknown-linux-musl
+          os: ubuntu-latest
         - tuple: wasm32-wasip1
           os: ubuntu-latest
 
@@ -207,6 +209,11 @@ jobs:
             tuple: amdgcn-amd-amdhsa
             os: ubuntu-latest
           norun: true
+        - target:
+            tuple: hexagon-unknown-linux-musl
+            os: ubuntu-latest
+          norun: true
+          build_std: true
 
     steps:
     - uses: actions/checkout@v4
@@ -300,7 +307,7 @@ jobs:
   # Check that the generated files agree with the checked-in versions.
   check-stdarch-gen:
     needs: [style]
-    name: Check stdarch-gen-{arm, loongarch} output
+    name: Check stdarch-gen-{arm, loongarch, hexagon} output
     runs-on: ubuntu-latest
     steps:
     - uses: actions/checkout@v4
@@ -318,6 +325,10 @@ jobs:
       run: |
         cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec
         git diff --exit-code
+    - name: Check hexagon
+      run: |
+        cargo run -p stdarch-gen-hexagon --release
+        git diff --exit-code
 
   conclusion:
     needs:
diff --git a/Cargo.lock b/Cargo.lock
index 70f09adf2c..66dd59a379 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2,6 +2,12 @@
 # It is not intended for manual editing.
 version = 4
 
+[[package]]
+name = "adler2"
+version = "2.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa"
+
 [[package]]
 name = "aho-corasick"
 version = "1.1.3"
@@ -82,6 +88,12 @@ version = "1.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8"
 
+[[package]]
+name = "base64"
+version = "0.22.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6"
+
 [[package]]
 name = "bitflags"
 version = "2.9.4"
@@ -158,6 +170,15 @@ dependencies = [
  "syscalls",
 ]
 
+[[package]]
+name = "crc32fast"
+version = "1.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511"
+dependencies = [
+ "cfg-if",
+]
+
 [[package]]
 name = "crossbeam-deque"
 version = "0.8.6"
@@ -224,6 +245,17 @@ version = "0.1.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "56254986775e3233ffa9c4d7d3faaf6d36a2c09d30b20687e9f88bc8bafc16c8"
 
+[[package]]
+name = "displaydoc"
+version = "0.2.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "97369cbbc041bc366949bc74d34658d6cda5621039731c6310521892a3a20ae0"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "either"
 version = "1.15.0"
@@ -265,12 +297,31 @@ version = "0.1.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7fd99930f64d146689264c637b5af2f0233a933bef0d8570e2526bf9e083192d"
 
+[[package]]
+name = "flate2"
+version = "1.1.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b375d6465b98090a5f25b1c7703f3859783755aa9a80433b36e0379a3ec2f369"
+dependencies = [
+ "crc32fast",
+ "miniz_oxide",
+]
+
 [[package]]
 name = "fnv"
 version = "1.0.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1"
 
+[[package]]
+name = "form_urlencoded"
+version = "1.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cb4cb245038516f5f85277875cdaa4f7d2c9a0fa0468de06ed190163b1581fcf"
+dependencies = [
+ "percent-encoding",
+]
+
 [[package]]
 name = "getrandom"
 version = "0.2.16"
@@ -312,12 +363,114 @@ version = "2.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "9b112acc8b3adf4b107a8ec20977da0273a8c386765a3ec0229bd500a1443f9f"
 
+[[package]]
+name = "icu_collections"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4c6b649701667bbe825c3b7e6388cb521c23d88644678e83c0c4d0a621a34b43"
+dependencies = [
+ "displaydoc",
+ "potential_utf",
+ "yoke",
+ "zerofrom",
+ "zerovec",
+]
+
+[[package]]
+name = "icu_locale_core"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "edba7861004dd3714265b4db54a3c390e880ab658fec5f7db895fae2046b5bb6"
+dependencies = [
+ "displaydoc",
+ "litemap",
+ "tinystr",
+ "writeable",
+ "zerovec",
+]
+
+[[package]]
+name = "icu_normalizer"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5f6c8828b67bf8908d82127b2054ea1b4427ff0230ee9141c54251934ab1b599"
+dependencies = [
+ "icu_collections",
+ "icu_normalizer_data",
+ "icu_properties",
+ "icu_provider",
+ "smallvec",
+ "zerovec",
+]
+
+[[package]]
+name = "icu_normalizer_data"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7aedcccd01fc5fe81e6b489c15b247b8b0690feb23304303a9e560f37efc560a"
+
+[[package]]
+name = "icu_properties"
+version = "2.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "020bfc02fe870ec3a66d93e677ccca0562506e5872c650f893269e08615d74ec"
+dependencies = [
+ "icu_collections",
+ "icu_locale_core",
+ "icu_properties_data",
+ "icu_provider",
+ "zerotrie",
+ "zerovec",
+]
+
+[[package]]
+name = "icu_properties_data"
+version = "2.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "616c294cf8d725c6afcd8f55abc17c56464ef6211f9ed59cccffe534129c77af"
+
+[[package]]
+name = "icu_provider"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "85962cf0ce02e1e0a629cc34e7ca3e373ce20dda4c4d7294bbd0bf1fdb59e614"
+dependencies = [
+ "displaydoc",
+ "icu_locale_core",
+ "writeable",
+ "yoke",
+ "zerofrom",
+ "zerotrie",
+ "zerovec",
+]
+
 [[package]]
 name = "ident_case"
 version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39"
 
+[[package]]
+name = "idna"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3b0875f23caa03898994f6ddc501886a45c7d3d62d04d2d90788d47be1b1e4de"
+dependencies = [
+ "idna_adapter",
+ "smallvec",
+ "utf8_iter",
+]
+
+[[package]]
+name = "idna_adapter"
+version = "1.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3acae9609540aa318d1bc588455225fb2085b9ed0c4f6bd0d9d5bcd86f1a0344"
+dependencies = [
+ "icu_normalizer",
+ "icu_properties",
+]
+
 [[package]]
 name = "indexmap"
 version = "1.9.3"
@@ -399,6 +552,12 @@ version = "0.5.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0717cef1bc8b636c6e1c1bbdefc09e6322da8a9321966e8928ef80d20f7f770f"
 
+[[package]]
+name = "litemap"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6373607a59f0be73a39b6fe456b8192fcc3585f602af20751600e974dd455e77"
+
 [[package]]
 name = "log"
 version = "0.4.28"
@@ -411,12 +570,43 @@ version = "2.7.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273"
 
+[[package]]
+name = "miniz_oxide"
+version = "0.8.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316"
+dependencies = [
+ "adler2",
+ "simd-adler32",
+]
+
+[[package]]
+name = "once_cell"
+version = "1.21.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d"
+
 [[package]]
 name = "once_cell_polyfill"
 version = "1.70.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "a4895175b425cb1f87721b59f0f286c2092bd4af812243672510e1ac53e2e0ad"
 
+[[package]]
+name = "percent-encoding"
+version = "2.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220"
+
+[[package]]
+name = "potential_utf"
+version = "0.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b73949432f5e2a09657003c25bca5e19a0e9c84f8058ca374f49e0ebe605af77"
+dependencies = [
+ "zerovec",
+]
+
 [[package]]
 name = "ppv-lite86"
 version = "0.2.21"
@@ -564,12 +754,61 @@ version = "0.8.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "caf4aa5b0f434c91fe5c7f1ecb6a5ece2130b02ad2a590589dda5146df959001"
 
+[[package]]
+name = "ring"
+version = "0.17.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7"
+dependencies = [
+ "cc",
+ "cfg-if",
+ "getrandom",
+ "libc",
+ "untrusted",
+ "windows-sys 0.52.0",
+]
+
 [[package]]
 name = "rustc-demangle"
 version = "0.1.26"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "56f7d92ca342cea22a06f2121d944b4fd82af56988c270852495420f961d4ace"
 
+[[package]]
+name = "rustls"
+version = "0.23.36"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c665f33d38cea657d9614f766881e4d510e0eda4239891eea56b4cadcf01801b"
+dependencies = [
+ "log",
+ "once_cell",
+ "ring",
+ "rustls-pki-types",
+ "rustls-webpki",
+ "subtle",
+ "zeroize",
+]
+
+[[package]]
+name = "rustls-pki-types"
+version = "1.14.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "be040f8b0a225e40375822a563fa9524378b9d63112f53e19ffff34df5d33fdd"
+dependencies = [
+ "zeroize",
+]
+
+[[package]]
+name = "rustls-webpki"
+version = "0.103.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d7df23109aa6c1567d1c575b9952556388da57401e4ace1d15f79eedad0d8f53"
+dependencies = [
+ "ring",
+ "rustls-pki-types",
+ "untrusted",
+]
+
 [[package]]
 name = "ryu"
 version = "1.0.20"
@@ -676,6 +915,12 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
 
+[[package]]
+name = "simd-adler32"
+version = "0.3.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2"
+
 [[package]]
 name = "simd-test-macro"
 version = "0.1.0"
@@ -685,6 +930,18 @@ dependencies = [
  "syn",
 ]
 
+[[package]]
+name = "smallvec"
+version = "1.15.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "67b1b7a3b5fe4f1376887184045fcf45c69e92af734b7aaddc05fb777b6fbd03"
+
+[[package]]
+name = "stable_deref_trait"
+version = "1.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596"
+
 [[package]]
 name = "stdarch-gen-arm"
 version = "0.1.0"
@@ -699,6 +956,14 @@ dependencies = [
  "walkdir",
 ]
 
+[[package]]
+name = "stdarch-gen-hexagon"
+version = "0.1.0"
+dependencies = [
+ "regex",
+ "ureq",
+]
+
 [[package]]
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
@@ -745,6 +1010,12 @@ version = "0.11.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
+[[package]]
+name = "subtle"
+version = "2.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292"
+
 [[package]]
 name = "syn"
 version = "2.0.106"
@@ -756,6 +1027,17 @@ dependencies = [
  "unicode-ident",
 ]
 
+[[package]]
+name = "synstructure"
+version = "0.13.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "728a70f3dbaf5bab7f0c4b1ac8d7ae5ea60a4b5549c8a5914361c99147a709d2"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "syscalls"
 version = "0.6.18"
@@ -791,12 +1073,62 @@ dependencies = [
  "syn",
 ]
 
+[[package]]
+name = "tinystr"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "42d3e9c45c09de15d06dd8acf5f4e0e399e85927b7f00711024eb7ae10fa4869"
+dependencies = [
+ "displaydoc",
+ "zerovec",
+]
+
 [[package]]
 name = "unicode-ident"
 version = "1.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512"
 
+[[package]]
+name = "untrusted"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1"
+
+[[package]]
+name = "ureq"
+version = "2.12.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "02d1a66277ed75f640d608235660df48c8e3c19f3b4edb6a263315626cc3c01d"
+dependencies = [
+ "base64",
+ "flate2",
+ "log",
+ "once_cell",
+ "rustls",
+ "rustls-pki-types",
+ "url",
+ "webpki-roots 0.26.11",
+]
+
+[[package]]
+name = "url"
+version = "2.5.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ff67a8a4397373c3ef660812acab3268222035010ab8680ec4215f38ba3d0eed"
+dependencies = [
+ "form_urlencoded",
+ "idna",
+ "percent-encoding",
+ "serde",
+]
+
+[[package]]
+name = "utf8_iter"
+version = "1.0.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b6c140620e7ffbb22c2dee59cafe6084a59b5ffc27a8859a5f0d494b5d52b6be"
+
 [[package]]
 name = "utf8parse"
 version = "0.2.2"
@@ -841,6 +1173,24 @@ dependencies = [
  "wasmparser",
 ]
 
+[[package]]
+name = "webpki-roots"
+version = "0.26.11"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "521bc38abb08001b01866da9f51eb7c5d647a19260e00054a8c7fd5f9e57f7a9"
+dependencies = [
+ "webpki-roots 1.0.5",
+]
+
+[[package]]
+name = "webpki-roots"
+version = "1.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "12bed680863276c63889429bfd6cab3b99943659923822de1c8a39c49e4d722c"
+dependencies = [
+ "rustls-pki-types",
+]
+
 [[package]]
 name = "winapi-util"
 version = "0.1.10"
@@ -856,6 +1206,15 @@ version = "0.1.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "5e6ad25900d524eaabdbbb96d20b4311e1e7ae1699af4fb28c17ae66c80d798a"
 
+[[package]]
+name = "windows-sys"
+version = "0.52.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d"
+dependencies = [
+ "windows-targets 0.52.6",
+]
+
 [[package]]
 name = "windows-sys"
 version = "0.59.0"
@@ -1003,6 +1362,12 @@ version = "0.53.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486"
 
+[[package]]
+name = "writeable"
+version = "0.6.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9edde0db4769d2dc68579893f2306b26c6ecfbe0ef499b013d731b7b9247e0b9"
+
 [[package]]
 name = "xml-rs"
 version = "0.8.27"
@@ -1018,6 +1383,29 @@ dependencies = [
  "linked-hash-map",
 ]
 
+[[package]]
+name = "yoke"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "72d6e5c6afb84d73944e5cedb052c4680d5657337201555f9f2a16b7406d4954"
+dependencies = [
+ "stable_deref_trait",
+ "yoke-derive",
+ "zerofrom",
+]
+
+[[package]]
+name = "yoke-derive"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b659052874eb698efe5b9e8cf382204678a0086ebf46982b79d6ca3182927e5d"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+ "synstructure",
+]
+
 [[package]]
 name = "zerocopy"
 version = "0.8.27"
@@ -1037,3 +1425,63 @@ dependencies = [
  "quote",
  "syn",
 ]
+
+[[package]]
+name = "zerofrom"
+version = "0.1.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "50cc42e0333e05660c3587f3bf9d0478688e15d870fab3346451ce7f8c9fbea5"
+dependencies = [
+ "zerofrom-derive",
+]
+
+[[package]]
+name = "zerofrom-derive"
+version = "0.1.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d71e5d6e06ab090c67b5e44993ec16b72dcbaabc526db883a360057678b48502"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+ "synstructure",
+]
+
+[[package]]
+name = "zeroize"
+version = "1.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0"
+
+[[package]]
+name = "zerotrie"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2a59c17a5562d507e4b54960e8569ebee33bee890c70aa3fe7b97e85a9fd7851"
+dependencies = [
+ "displaydoc",
+ "yoke",
+ "zerofrom",
+]
+
+[[package]]
+name = "zerovec"
+version = "0.11.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6c28719294829477f525be0186d13efa9a3c602f7ec202ca9e353d310fb9a002"
+dependencies = [
+ "yoke",
+ "zerofrom",
+ "zerovec-derive",
+]
+
+[[package]]
+name = "zerovec-derive"
+version = "0.11.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "eadce39539ca5cb3985590102671f2567e659fca9666581ad3411d59207951f3"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
diff --git a/ci/docker/hexagon-unknown-linux-musl/Dockerfile b/ci/docker/hexagon-unknown-linux-musl/Dockerfile
new file mode 100644
index 0000000000..f6c0efd946
--- /dev/null
+++ b/ci/docker/hexagon-unknown-linux-musl/Dockerfile
@@ -0,0 +1,46 @@
+FROM ubuntu:25.10
+
+RUN apt-get update && apt-get install -y --no-install-recommends \
+  gcc \
+  libc6-dev \
+  ca-certificates \
+  curl \
+  zstd \
+  file \
+  make \
+  libc++1 \
+  libglib2.0-0t64 \
+  libunwind-20 \
+  liburing2 \
+  llvm
+
+# The Hexagon toolchain requires libc++ and libunwind at runtime - create symlinks from versioned files
+RUN cd /usr/lib/x86_64-linux-gnu && \
+    for f in libc++.so.1.0.*; do ln -sf "$f" libc++.so.1; done && \
+    for f in libc++abi.so.1.0.*; do ln -sf "$f" libc++abi.so.1; done && \
+    for f in libunwind.so.1.0.*; do ln -sf "$f" libunwind.so.1; done
+
+# Download and install the Hexagon cross toolchain from
+# https://github.com/quic/toolchain_for_hexagon/releases/tag/v21.1.8
+# Includes clang cross-compiler, musl sysroot, and qemu-hexagon.
+#
+# The tarball contains directories with restrictive (0700) permissions.
+# In rootless Podman, chmod fails on tar-extracted files within the same
+# layer due to overlayfs limitations in user namespaces. Splitting into
+# two RUN steps lets chmod work via overlayfs copy-up from the lower layer.
+RUN curl -L -o /tmp/hexagon-toolchain.tar.zst \
+    https://artifacts.codelinaro.org/artifactory/codelinaro-toolchain-for-hexagon/21.1.8/clang+llvm-21.1.8-cross-hexagon-unknown-linux-musl.tar.zst && \
+    mkdir -p /opt/hexagon-toolchain && \
+    cd /opt/hexagon-toolchain && \
+    (unzstd -c /tmp/hexagon-toolchain.tar.zst | tar -xf - --strip-components=2 --no-same-permissions || true) && \
+    rm /tmp/hexagon-toolchain.tar.zst
+RUN find /opt/hexagon-toolchain -type d -exec chmod a+rx {} + 2>/dev/null; \
+    find /opt/hexagon-toolchain -type f -exec chmod a+r {} + 2>/dev/null; \
+    find /opt/hexagon-toolchain -type f -perm /111 -exec chmod a+rx {} + 2>/dev/null; \
+    /opt/hexagon-toolchain/bin/hexagon-unknown-linux-musl-clang --version
+
+ENV PATH="/opt/hexagon-toolchain/bin:${PATH}" \
+    CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_LINKER=hexagon-unknown-linux-musl-clang \
+    CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_RUNNER="qemu-hexagon -L /opt/hexagon-toolchain/target/hexagon-unknown-linux-musl" \
+    CARGO_UNSTABLE_BUILD_STD_FEATURES=llvm-libunwind \
+    OBJDUMP=llvm-objdump
diff --git a/ci/run.sh b/ci/run.sh
index 8a0b5fa26f..ea012b42f9 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -50,6 +50,9 @@ case ${TARGET} in
     riscv*)
         export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+zk,+zks,+zbb,+zbc"
         ;;
+    hexagon*)
+        export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+hvxv60,+hvx-length128b"
+        ;;
 esac
 
 echo "RUSTFLAGS=${RUSTFLAGS}"
diff --git a/crates/core_arch/src/core_arch_docs.md b/crates/core_arch/src/core_arch_docs.md
index 7075945754..9b52fb2af1 100644
--- a/crates/core_arch/src/core_arch_docs.md
+++ b/crates/core_arch/src/core_arch_docs.md
@@ -186,6 +186,7 @@ others at:
 * [`arm`]
 * [`aarch64`]
 * [`amdgpu`]
+* [`hexagon`]
 * [`riscv32`]
 * [`riscv64`]
 * [`mips`]
@@ -203,6 +204,7 @@ others at:
 [`arm`]: ../../core/arch/arm/index.html
 [`aarch64`]: ../../core/arch/aarch64/index.html
 [`amdgpu`]: ../../core/arch/amdgpu/index.html
+[`hexagon`]: ../../core/arch/hexagon/index.html
 [`riscv32`]: ../../core/arch/riscv32/index.html
 [`riscv64`]: ../../core/arch/riscv64/index.html
 [`mips`]: ../../core/arch/mips/index.html
diff --git a/crates/core_arch/src/hexagon/hvx.rs b/crates/core_arch/src/hexagon/hvx.rs
new file mode 100644
index 0000000000..24d42ea1fc
--- /dev/null
+++ b/crates/core_arch/src/hexagon/hvx.rs
@@ -0,0 +1,8488 @@
+//! Hexagon HVX intrinsics
+//!
+//! This module provides intrinsics for the Hexagon Vector Extensions (HVX).
+//! HVX is a wide vector extension designed for high-performance signal processing.
+//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61)
+//!
+//! ## Vector Types
+//!
+//! HVX supports different vector lengths depending on the configuration:
+//! - 128-byte mode: `HvxVector` is 1024 bits (128 bytes)
+//! - 64-byte mode: `HvxVector` is 512 bits (64 bytes)
+//!
+//! This implementation targets 128-byte mode by default. To change the vector
+//! length mode, use the appropriate target feature when compiling:
+//! - For 128-byte mode: `-C target-feature=+hvx-length128b`
+//! - For 64-byte mode: `-C target-feature=+hvx-length64b`
+//!
+//! Note that HVX v66 and later default to 128-byte mode, while earlier versions
+//! default to 64-byte mode.
+//!
+//! ## Architecture Versions
+//!
+//! Different intrinsics require different HVX architecture versions. Use the
+//! appropriate target feature to enable the required version:
+//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations)
+//! - HVX v62: `-C target-feature=+hvxv62`
+//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support)
+//! - HVX v66: `-C target-feature=+hvxv66`
+//! - HVX v68: `-C target-feature=+hvxv68`
+//! - HVX v69: `-C target-feature=+hvxv69`
+//! - HVX v73: `-C target-feature=+hvxv73`
+//! - HVX v79: `-C target-feature=+hvxv79`
+//! - HVX v81: `-C target-feature=+hvxv81`
+//!
+//! Each version includes all features from previous versions.
+
+#![allow(non_camel_case_types)]
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor};
+
+// HVX type definitions for 128-byte vector mode (default for v66+)
+// Use -C target-feature=+hvx-length128b to enable
+#[cfg(target_feature = "hvx-length128b")]
+types! {
+    #![unstable(feature = "stdarch_hexagon", issue = "151523")]
+
+    /// HVX vector type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a single HVX vector register containing 32 x 32-bit values.
+    pub struct HvxVector(32 x i32);
+
+    /// HVX vector pair type (2048 bits / 256 bytes)
+    ///
+    /// This type represents a pair of HVX vector registers, often used for
+    /// operations that produce double-width results.
+    pub struct HvxVectorPair(64 x i32);
+
+    /// HVX vector predicate type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a predicate vector used for conditional operations.
+    /// Each bit corresponds to a lane in the vector.
+    pub struct HvxVectorPred(32 x i32);
+}
+
+// HVX type definitions for 64-byte vector mode (default for v60-v65)
+// Use -C target-feature=+hvx-length64b to enable, or omit hvx-length128b
+#[cfg(not(target_feature = "hvx-length128b"))]
+types! {
+    #![unstable(feature = "stdarch_hexagon", issue = "151523")]
+
+    /// HVX vector type (512 bits / 64 bytes)
+    ///
+    /// This type represents a single HVX vector register containing 16 x 32-bit values.
+    pub struct HvxVector(16 x i32);
+
+    /// HVX vector pair type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a pair of HVX vector registers, often used for
+    /// operations that produce double-width results.
+    pub struct HvxVectorPair(32 x i32);
+
+    /// HVX vector predicate type (512 bits / 64 bytes)
+    ///
+    /// This type represents a predicate vector used for conditional operations.
+    /// Each bit corresponds to a lane in the vector.
+    pub struct HvxVectorPred(16 x i32);
+}
+
+// LLVM intrinsic declarations for 128-byte vector mode
+#[cfg(target_feature = "hvx-length128b")]
+#[allow(improper_ctypes)]
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.hexagon.V6.extractw.128B"]
+    fn extractw(_: HvxVector, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.V6.get.qfext.128B"]
+    fn get_qfext(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.hi.128B"]
+    fn hi(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lo.128B"]
+    fn lo(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplatb.128B"]
+    fn lvsplatb(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplath.128B"]
+    fn lvsplath(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplatw.128B"]
+    fn lvsplatw(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.and.128B"]
+    fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.and.n.128B"]
+    fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.not.128B"]
+    fn pred_not(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.or.128B"]
+    fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.or.n.128B"]
+    fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.scalar2.128B"]
+    fn pred_scalar2(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.scalar2v2.128B"]
+    fn pred_scalar2v2(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.xor.128B"]
+    fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.set.qfext.128B"]
+    fn set_qfext(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.shuffeqh.128B"]
+    fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.shuffeqw.128B"]
+    fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.128B"]
+    fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx.128B"]
+    fn v6mpyhubs10_vxx(
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: i32,
+    ) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.128B"]
+    fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx.128B"]
+    fn v6mpyvubs10_vxx(
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: i32,
+    ) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai.128B"]
+    fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B"]
+    fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai.128B"]
+    fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai.128B"]
+    fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vabs.f8.128B"]
+    fn vabs_f8(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabs.hf.128B"]
+    fn vabs_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabs.sf.128B"]
+    fn vabs_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsb.128B"]
+    fn vabsb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsb.sat.128B"]
+    fn vabsb_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffh.128B"]
+    fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffub.128B"]
+    fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffuh.128B"]
+    fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffw.128B"]
+    fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsh.128B"]
+    fn vabsh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsh.sat.128B"]
+    fn vabsh_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsw.128B"]
+    fn vabsw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsw.sat.128B"]
+    fn vabsw_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.hf.128B"]
+    fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.hf.hf.128B"]
+    fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf16.128B"]
+    fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf16.mix.128B"]
+    fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf32.128B"]
+    fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf32.mix.128B"]
+    fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.128B"]
+    fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.hf.128B"]
+    fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.sf.128B"]
+    fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddb.128B"]
+    fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddb.dv.128B"]
+    fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddbnq.128B"]
+    fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbq.128B"]
+    fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbsat.128B"]
+    fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbsat.dv.128B"]
+    fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddcarrysat.128B"]
+    fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddclbh.128B"]
+    fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddclbw.128B"]
+    fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddh.128B"]
+    fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddh.dv.128B"]
+    fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhnq.128B"]
+    fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhq.128B"]
+    fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhsat.128B"]
+    fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhsat.dv.128B"]
+    fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhw.128B"]
+    fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhw.acc.128B"]
+    fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubh.128B"]
+    fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubh.acc.128B"]
+    fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubsat.128B"]
+    fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddubsat.dv.128B"]
+    fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddububb.sat.128B"]
+    fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduhsat.128B"]
+    fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduhsat.dv.128B"]
+    fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduhw.128B"]
+    fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduhw.acc.128B"]
+    fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduwsat.128B"]
+    fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduwsat.dv.128B"]
+    fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddw.128B"]
+    fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddw.dv.128B"]
+    fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddwnq.128B"]
+    fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwq.128B"]
+    fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwsat.128B"]
+    fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwsat.dv.128B"]
+    fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.valignb.128B"]
+    fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.valignbi.128B"]
+    fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vand.128B"]
+    fn vand(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandnqrt.128B"]
+    fn vandnqrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandnqrt.acc.128B"]
+    fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandqrt.128B"]
+    fn vandqrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandqrt.acc.128B"]
+    fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvnqv.128B"]
+    fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvqv.128B"]
+    fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvrt.128B"]
+    fn vandvrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvrt.acc.128B"]
+    fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslh.128B"]
+    fn vaslh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslh.acc.128B"]
+    fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslhv.128B"]
+    fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslw.128B"]
+    fn vaslw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslw.acc.128B"]
+    fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslwv.128B"]
+    fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasr.into.128B"]
+    fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vasrh.128B"]
+    fn vasrh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrh.acc.128B"]
+    fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhbrndsat.128B"]
+    fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhbsat.128B"]
+    fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhubrndsat.128B"]
+    fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhubsat.128B"]
+    fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhv.128B"]
+    fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruhubrndsat.128B"]
+    fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruhubsat.128B"]
+    fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruwuhrndsat.128B"]
+    fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruwuhsat.128B"]
+    fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat.128B"]
+    fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvuhubsat.128B"]
+    fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat.128B"]
+    fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvwuhsat.128B"]
+    fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrw.128B"]
+    fn vasrw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrw.acc.128B"]
+    fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwh.128B"]
+    fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwhrndsat.128B"]
+    fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwhsat.128B"]
+    fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwuhrndsat.128B"]
+    fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwuhsat.128B"]
+    fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwv.128B"]
+    fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassign.128B"]
+    fn vassign(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassign.fp.128B"]
+    fn vassign_fp(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassignp.128B"]
+    fn vassignp(_: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vavgb.128B"]
+    fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgbrnd.128B"]
+    fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgh.128B"]
+    fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavghrnd.128B"]
+    fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgub.128B"]
+    fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgubrnd.128B"]
+    fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguh.128B"]
+    fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguhrnd.128B"]
+    fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguw.128B"]
+    fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguwrnd.128B"]
+    fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgw.128B"]
+    fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgwrnd.128B"]
+    fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcl0h.128B"]
+    fn vcl0h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcl0w.128B"]
+    fn vcl0w(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcombine.128B"]
+    fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vconv.h.hf.128B"]
+    fn vconv_h_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.h.128B"]
+    fn vconv_hf_h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.qf16.128B"]
+    fn vconv_hf_qf16(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.qf32.128B"]
+    fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.sf.qf32.128B"]
+    fn vconv_sf_qf32(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.sf.w.128B"]
+    fn vconv_sf_w(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.w.sf.128B"]
+    fn vconv_w_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt2.hf.b.128B"]
+    fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub.128B"]
+    fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.b.hf.128B"]
+    fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.h.hf.128B"]
+    fn vcvt_h_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.b.128B"]
+    fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.f8.128B"]
+    fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.h.128B"]
+    fn vcvt_hf_h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.sf.128B"]
+    fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.ub.128B"]
+    fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.uh.128B"]
+    fn vcvt_hf_uh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.sf.hf.128B"]
+    fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.ub.hf.128B"]
+    fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.uh.hf.128B"]
+    fn vcvt_uh_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vd0.128B"]
+    fn vd0() -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdd0.128B"]
+    fn vdd0() -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdealb.128B"]
+    fn vdealb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealb4w.128B"]
+    fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealh.128B"]
+    fn vdealh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealvdd.128B"]
+    fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdelta.128B"]
+    fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.128B"]
+    fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B"]
+    fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.128B"]
+    fn vdmpybus(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.acc.128B"]
+    fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.128B"]
+    fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc.128B"]
+    fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.128B"]
+    fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.acc.128B"]
+    fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.128B"]
+    fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc.128B"]
+    fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhisat.128B"]
+    fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc.128B"]
+    fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsat.128B"]
+    fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc.128B"]
+    fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.128B"]
+    fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc.128B"]
+    fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.128B"]
+    fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc.128B"]
+    fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.128B"]
+    fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc.128B"]
+    fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdsaduh.128B"]
+    fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdsaduh.acc.128B"]
+    fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.veqb.128B"]
+    fn veqb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.and.128B"]
+    fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.or.128B"]
+    fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.xor.128B"]
+    fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.128B"]
+    fn veqh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.and.128B"]
+    fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.or.128B"]
+    fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.xor.128B"]
+    fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.128B"]
+    fn veqw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.and.128B"]
+    fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.or.128B"]
+    fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.xor.128B"]
+    fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.f8.128B"]
+    fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.hf.128B"]
+    fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.sf.128B"]
+    fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.f8.128B"]
+    fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.hf.128B"]
+    fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.sf.128B"]
+    fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.f8.128B"]
+    fn vfneg_f8(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.hf.128B"]
+    fn vfneg_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.sf.128B"]
+    fn vfneg_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgathermh.128B"]
+    fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhq.128B"]
+    fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhw.128B"]
+    fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhwq.128B"]
+    fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermw.128B"]
+    fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermwq.128B"]
+    fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgtb.128B"]
+    fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.and.128B"]
+    fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.or.128B"]
+    fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.xor.128B"]
+    fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.128B"]
+    fn vgth(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.and.128B"]
+    fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.or.128B"]
+    fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.xor.128B"]
+    fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.128B"]
+    fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.and.128B"]
+    fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.or.128B"]
+    fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.xor.128B"]
+    fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.128B"]
+    fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.and.128B"]
+    fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.or.128B"]
+    fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.xor.128B"]
+    fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.128B"]
+    fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.and.128B"]
+    fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.or.128B"]
+    fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.xor.128B"]
+    fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.128B"]
+    fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.and.128B"]
+    fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.or.128B"]
+    fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.xor.128B"]
+    fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.128B"]
+    fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.and.128B"]
+    fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.or.128B"]
+    fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.xor.128B"]
+    fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.128B"]
+    fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.and.128B"]
+    fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.or.128B"]
+    fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.xor.128B"]
+    fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vinsertwr.128B"]
+    fn vinsertwr(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlalignb.128B"]
+    fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlalignbi.128B"]
+    fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrb.128B"]
+    fn vlsrb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrh.128B"]
+    fn vlsrh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrhv.128B"]
+    fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrw.128B"]
+    fn vlsrw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrwv.128B"]
+    fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.128B"]
+    fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.nm.128B"]
+    fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.oracc.128B"]
+    fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.oracci.128B"]
+    fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvbi.128B"]
+    fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.128B"]
+    fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.nm.128B"]
+    fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.oracc.128B"]
+    fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.oracci.128B"]
+    fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwhi.128B"]
+    fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmax.hf.128B"]
+    fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmax.sf.128B"]
+    fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxb.128B"]
+    fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxh.128B"]
+    fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxub.128B"]
+    fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxuh.128B"]
+    fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxw.128B"]
+    fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmin.hf.128B"]
+    fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmin.sf.128B"]
+    fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminb.128B"]
+    fn vminb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminh.128B"]
+    fn vminh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminub.128B"]
+    fn vminub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminuh.128B"]
+    fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminw.128B"]
+    fn vminw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpabus.128B"]
+    fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabus.acc.128B"]
+    fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabusv.128B"]
+    fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuu.128B"]
+    fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuu.acc.128B"]
+    fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuuv.128B"]
+    fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpahb.128B"]
+    fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpahb.acc.128B"]
+    fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpauhb.128B"]
+    fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpauhb.acc.128B"]
+    fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.128B"]
+    fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc.128B"]
+    fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.128B"]
+    fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf.128B"]
+    fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B"]
+    fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.128B"]
+    fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf.128B"]
+    fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B"]
+    fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16.128B"]
+    fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf.128B"]
+    fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.128B"]
+    fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc.128B"]
+    fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.sf.128B"]
+    fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpybus.128B"]
+    fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybus.acc.128B"]
+    fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybusv.128B"]
+    fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybusv.acc.128B"]
+    fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybv.128B"]
+    fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybv.acc.128B"]
+    fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyewuh.128B"]
+    fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyewuh.64.128B"]
+    fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyh.128B"]
+    fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyh.acc.128B"]
+    fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhsat.acc.128B"]
+    fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhsrs.128B"]
+    fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyhss.128B"]
+    fn vmpyhss(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyhus.128B"]
+    fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhus.acc.128B"]
+    fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhv.128B"]
+    fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhv.acc.128B"]
+    fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhvsrs.128B"]
+    fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyieoh.128B"]
+    fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewh.acc.128B"]
+    fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewuh.128B"]
+    fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc.128B"]
+    fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyih.128B"]
+    fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyih.acc.128B"]
+    fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyihb.128B"]
+    fn vmpyihb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyihb.acc.128B"]
+    fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiowh.128B"]
+    fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwb.128B"]
+    fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwb.acc.128B"]
+    fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwh.128B"]
+    fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwh.acc.128B"]
+    fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwub.128B"]
+    fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwub.acc.128B"]
+    fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.128B"]
+    fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc.128B"]
+    fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.128B"]
+    fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B"]
+    fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.sacc.128B"]
+    fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyub.128B"]
+    fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyub.acc.128B"]
+    fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyubv.128B"]
+    fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyubv.acc.128B"]
+    fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuh.128B"]
+    fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuh.acc.128B"]
+    fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhe.128B"]
+    fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyuhe.acc.128B"]
+    fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyuhv.128B"]
+    fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhv.acc.128B"]
+    fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhvs.128B"]
+    fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmux.128B"]
+    fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgb.128B"]
+    fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgh.128B"]
+    fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgub.128B"]
+    fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgw.128B"]
+    fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnormamth.128B"]
+    fn vnormamth(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnormamtw.128B"]
+    fn vnormamtw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnot.128B"]
+    fn vnot(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vor.128B"]
+    fn vor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackeb.128B"]
+    fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackeh.128B"]
+    fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackhb.sat.128B"]
+    fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackhub.sat.128B"]
+    fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackob.128B"]
+    fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackoh.128B"]
+    fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackwh.sat.128B"]
+    fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackwuh.sat.128B"]
+    fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpopcounth.128B"]
+    fn vpopcounth(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqb.128B"]
+    fn vprefixqb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqh.128B"]
+    fn vprefixqh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqw.128B"]
+    fn vprefixqw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrdelta.128B"]
+    fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybus.128B"]
+    fn vrmpybus(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybus.acc.128B"]
+    fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybusi.128B"]
+    fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpybusi.acc.128B"]
+    fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpybusv.128B"]
+    fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybusv.acc.128B"]
+    fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybv.128B"]
+    fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybv.acc.128B"]
+    fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyub.128B"]
+    fn vrmpyub(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyub.acc.128B"]
+    fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyubi.128B"]
+    fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpyubi.acc.128B"]
+    fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpyubv.128B"]
+    fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyubv.acc.128B"]
+    fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vror.128B"]
+    fn vror(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrotr.128B"]
+    fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundhb.128B"]
+    fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundhub.128B"]
+    fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrounduhub.128B"]
+    fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrounduwuh.128B"]
+    fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundwh.128B"]
+    fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundwuh.128B"]
+    fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrsadubi.128B"]
+    fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrsadubi.acc.128B"]
+    fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsatdw.128B"]
+    fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsathub.128B"]
+    fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsatuwuh.128B"]
+    fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsatwh.128B"]
+    fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsb.128B"]
+    fn vsb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vscattermh.128B"]
+    fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermh.add.128B"]
+    fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhq.128B"]
+    fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhw.128B"]
+    fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhw.add.128B"]
+    fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhwq.128B"]
+    fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermw.128B"]
+    fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermw.add.128B"]
+    fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermwq.128B"]
+    fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vsh.128B"]
+    fn vsh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufeh.128B"]
+    fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffb.128B"]
+    fn vshuffb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffeb.128B"]
+    fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffh.128B"]
+    fn vshuffh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffob.128B"]
+    fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffvdd.128B"]
+    fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoeb.128B"]
+    fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoeh.128B"]
+    fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoh.128B"]
+    fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.hf.128B"]
+    fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.hf.hf.128B"]
+    fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf16.128B"]
+    fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf16.mix.128B"]
+    fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf32.128B"]
+    fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf32.mix.128B"]
+    fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.128B"]
+    fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.hf.128B"]
+    fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.sf.128B"]
+    fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubb.128B"]
+    fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubb.dv.128B"]
+    fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubbnq.128B"]
+    fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbq.128B"]
+    fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbsat.128B"]
+    fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbsat.dv.128B"]
+    fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubh.128B"]
+    fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubh.dv.128B"]
+    fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubhnq.128B"]
+    fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhq.128B"]
+    fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhsat.128B"]
+    fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhsat.dv.128B"]
+    fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubhw.128B"]
+    fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsububh.128B"]
+    fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsububsat.128B"]
+    fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsububsat.dv.128B"]
+    fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubububb.sat.128B"]
+    fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuhsat.128B"]
+    fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuhsat.dv.128B"]
+    fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubuhw.128B"]
+    fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubuwsat.128B"]
+    fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuwsat.dv.128B"]
+    fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubw.128B"]
+    fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubw.dv.128B"]
+    fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubwnq.128B"]
+    fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwq.128B"]
+    fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwsat.128B"]
+    fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwsat.dv.128B"]
+    fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vswap.128B"]
+    fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyb.128B"]
+    fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyb.acc.128B"]
+    fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpybus.128B"]
+    fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpybus.acc.128B"]
+    fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyhb.128B"]
+    fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyhb.acc.128B"]
+    fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackb.128B"]
+    fn vunpackb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackh.128B"]
+    fn vunpackh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackob.128B"]
+    fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackoh.128B"]
+    fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackub.128B"]
+    fn vunpackub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackuh.128B"]
+    fn vunpackuh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vxor.128B"]
+    fn vxor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vzb.128B"]
+    fn vzb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vzh.128B"]
+    fn vzh(_: HvxVector) -> HvxVectorPair;
+}
+
+// LLVM intrinsic declarations for 64-byte vector mode
+#[cfg(not(target_feature = "hvx-length128b"))]
+#[allow(improper_ctypes)]
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.hexagon.V6.extractw"]
+    fn extractw(_: HvxVector, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.V6.get.qfext"]
+    fn get_qfext(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.hi"]
+    fn hi(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lo"]
+    fn lo(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplatb"]
+    fn lvsplatb(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplath"]
+    fn lvsplath(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplatw"]
+    fn lvsplatw(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.and"]
+    fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.and.n"]
+    fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.not"]
+    fn pred_not(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.or"]
+    fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.or.n"]
+    fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.scalar2"]
+    fn pred_scalar2(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.scalar2v2"]
+    fn pred_scalar2v2(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.xor"]
+    fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.set.qfext"]
+    fn set_qfext(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.shuffeqh"]
+    fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.shuffeqw"]
+    fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.v6mpyhubs10"]
+    fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx"]
+    fn v6mpyhubs10_vxx(
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: i32,
+    ) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyvubs10"]
+    fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx"]
+    fn v6mpyvubs10_vxx(
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: i32,
+    ) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai"]
+    fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai"]
+    fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai"]
+    fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai"]
+    fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vabs.f8"]
+    fn vabs_f8(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabs.hf"]
+    fn vabs_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabs.sf"]
+    fn vabs_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsb"]
+    fn vabsb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsb.sat"]
+    fn vabsb_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffh"]
+    fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffub"]
+    fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffuh"]
+    fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffw"]
+    fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsh"]
+    fn vabsh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsh.sat"]
+    fn vabsh_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsw"]
+    fn vabsw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsw.sat"]
+    fn vabsw_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.hf"]
+    fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.hf.hf"]
+    fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf16"]
+    fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf16.mix"]
+    fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf32"]
+    fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf32.mix"]
+    fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.sf"]
+    fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.hf"]
+    fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.sf"]
+    fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddb"]
+    fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddb.dv"]
+    fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddbnq"]
+    fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbq"]
+    fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbsat"]
+    fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbsat.dv"]
+    fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddcarrysat"]
+    fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddclbh"]
+    fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddclbw"]
+    fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddh"]
+    fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddh.dv"]
+    fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhnq"]
+    fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhq"]
+    fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhsat"]
+    fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhsat.dv"]
+    fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhw"]
+    fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhw.acc"]
+    fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubh"]
+    fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubh.acc"]
+    fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubsat"]
+    fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddubsat.dv"]
+    fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddububb.sat"]
+    fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduhsat"]
+    fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduhsat.dv"]
+    fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduhw"]
+    fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduhw.acc"]
+    fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduwsat"]
+    fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduwsat.dv"]
+    fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddw"]
+    fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddw.dv"]
+    fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddwnq"]
+    fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwq"]
+    fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwsat"]
+    fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwsat.dv"]
+    fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.valignb"]
+    fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.valignbi"]
+    fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vand"]
+    fn vand(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandnqrt"]
+    fn vandnqrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandnqrt.acc"]
+    fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandqrt"]
+    fn vandqrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandqrt.acc"]
+    fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvnqv"]
+    fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvqv"]
+    fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvrt"]
+    fn vandvrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvrt.acc"]
+    fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslh"]
+    fn vaslh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslh.acc"]
+    fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslhv"]
+    fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslw"]
+    fn vaslw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslw.acc"]
+    fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslwv"]
+    fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasr.into"]
+    fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vasrh"]
+    fn vasrh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrh.acc"]
+    fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhbrndsat"]
+    fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhbsat"]
+    fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhubrndsat"]
+    fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhubsat"]
+    fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhv"]
+    fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruhubrndsat"]
+    fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruhubsat"]
+    fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruwuhrndsat"]
+    fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruwuhsat"]
+    fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat"]
+    fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvuhubsat"]
+    fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat"]
+    fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvwuhsat"]
+    fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrw"]
+    fn vasrw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrw.acc"]
+    fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwh"]
+    fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwhrndsat"]
+    fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwhsat"]
+    fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwuhrndsat"]
+    fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwuhsat"]
+    fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwv"]
+    fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassign"]
+    fn vassign(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassign.fp"]
+    fn vassign_fp(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassignp"]
+    fn vassignp(_: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vavgb"]
+    fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgbrnd"]
+    fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgh"]
+    fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavghrnd"]
+    fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgub"]
+    fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgubrnd"]
+    fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguh"]
+    fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguhrnd"]
+    fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguw"]
+    fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguwrnd"]
+    fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgw"]
+    fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgwrnd"]
+    fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcl0h"]
+    fn vcl0h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcl0w"]
+    fn vcl0w(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcombine"]
+    fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vconv.h.hf"]
+    fn vconv_h_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.h"]
+    fn vconv_hf_h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.qf16"]
+    fn vconv_hf_qf16(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.qf32"]
+    fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.sf.qf32"]
+    fn vconv_sf_qf32(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.sf.w"]
+    fn vconv_sf_w(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.w.sf"]
+    fn vconv_w_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt2.hf.b"]
+    fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub"]
+    fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.b.hf"]
+    fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.h.hf"]
+    fn vcvt_h_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.b"]
+    fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.f8"]
+    fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.h"]
+    fn vcvt_hf_h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.sf"]
+    fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.ub"]
+    fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.uh"]
+    fn vcvt_hf_uh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.sf.hf"]
+    fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.ub.hf"]
+    fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.uh.hf"]
+    fn vcvt_uh_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vd0"]
+    fn vd0() -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdd0"]
+    fn vdd0() -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdealb"]
+    fn vdealb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealb4w"]
+    fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealh"]
+    fn vdealh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealvdd"]
+    fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdelta"]
+    fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf"]
+    fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc"]
+    fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus"]
+    fn vdmpybus(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.acc"]
+    fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.dv"]
+    fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc"]
+    fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb"]
+    fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.acc"]
+    fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv"]
+    fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc"]
+    fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhisat"]
+    fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc"]
+    fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsat"]
+    fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc"]
+    fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat"]
+    fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc"]
+    fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsusat"]
+    fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc"]
+    fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhvsat"]
+    fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc"]
+    fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdsaduh"]
+    fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdsaduh.acc"]
+    fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.veqb"]
+    fn veqb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.and"]
+    fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.or"]
+    fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.xor"]
+    fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh"]
+    fn veqh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.and"]
+    fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.or"]
+    fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.xor"]
+    fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw"]
+    fn veqw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.and"]
+    fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.or"]
+    fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.xor"]
+    fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.f8"]
+    fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.hf"]
+    fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.sf"]
+    fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.f8"]
+    fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.hf"]
+    fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.sf"]
+    fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.f8"]
+    fn vfneg_f8(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.hf"]
+    fn vfneg_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.sf"]
+    fn vfneg_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgathermh"]
+    fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhq"]
+    fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhw"]
+    fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhwq"]
+    fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermw"]
+    fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermwq"]
+    fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgtb"]
+    fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.and"]
+    fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.or"]
+    fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.xor"]
+    fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth"]
+    fn vgth(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.and"]
+    fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.or"]
+    fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.xor"]
+    fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf"]
+    fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.and"]
+    fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.or"]
+    fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.xor"]
+    fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf"]
+    fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.and"]
+    fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.or"]
+    fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.xor"]
+    fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub"]
+    fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.and"]
+    fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.or"]
+    fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.xor"]
+    fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh"]
+    fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.and"]
+    fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.or"]
+    fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.xor"]
+    fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw"]
+    fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.and"]
+    fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.or"]
+    fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.xor"]
+    fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw"]
+    fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.and"]
+    fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.or"]
+    fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.xor"]
+    fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vinsertwr"]
+    fn vinsertwr(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlalignb"]
+    fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlalignbi"]
+    fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrb"]
+    fn vlsrb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrh"]
+    fn vlsrh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrhv"]
+    fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrw"]
+    fn vlsrw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrwv"]
+    fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb"]
+    fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.nm"]
+    fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.oracc"]
+    fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.oracci"]
+    fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvbi"]
+    fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvwh"]
+    fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.nm"]
+    fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.oracc"]
+    fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.oracci"]
+    fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwhi"]
+    fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmax.hf"]
+    fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmax.sf"]
+    fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxb"]
+    fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxh"]
+    fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxub"]
+    fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxuh"]
+    fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxw"]
+    fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmin.hf"]
+    fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmin.sf"]
+    fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminb"]
+    fn vminb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminh"]
+    fn vminh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminub"]
+    fn vminub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminuh"]
+    fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminw"]
+    fn vminw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpabus"]
+    fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabus.acc"]
+    fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabusv"]
+    fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuu"]
+    fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuu.acc"]
+    fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuuv"]
+    fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpahb"]
+    fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpahb.acc"]
+    fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpauhb"]
+    fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpauhb.acc"]
+    fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf"]
+    fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc"]
+    fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16"]
+    fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf"]
+    fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf"]
+    fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32"]
+    fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf"]
+    fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf"]
+    fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16"]
+    fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf"]
+    fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf"]
+    fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc"]
+    fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.sf"]
+    fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpybus"]
+    fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybus.acc"]
+    fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybusv"]
+    fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybusv.acc"]
+    fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybv"]
+    fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybv.acc"]
+    fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyewuh"]
+    fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyewuh.64"]
+    fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyh"]
+    fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyh.acc"]
+    fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhsat.acc"]
+    fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhsrs"]
+    fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyhss"]
+    fn vmpyhss(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyhus"]
+    fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhus.acc"]
+    fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhv"]
+    fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhv.acc"]
+    fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhvsrs"]
+    fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyieoh"]
+    fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewh.acc"]
+    fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewuh"]
+    fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc"]
+    fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyih"]
+    fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyih.acc"]
+    fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyihb"]
+    fn vmpyihb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyihb.acc"]
+    fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiowh"]
+    fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwb"]
+    fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwb.acc"]
+    fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwh"]
+    fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwh.acc"]
+    fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwub"]
+    fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwub.acc"]
+    fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh"]
+    fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc"]
+    fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd"]
+    fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc"]
+    fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.sacc"]
+    fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyub"]
+    fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyub.acc"]
+    fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyubv"]
+    fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyubv.acc"]
+    fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuh"]
+    fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuh.acc"]
+    fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhe"]
+    fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyuhe.acc"]
+    fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyuhv"]
+    fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhv.acc"]
+    fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhvs"]
+    fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmux"]
+    fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgb"]
+    fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgh"]
+    fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgub"]
+    fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgw"]
+    fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnormamth"]
+    fn vnormamth(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnormamtw"]
+    fn vnormamtw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnot"]
+    fn vnot(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vor"]
+    fn vor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackeb"]
+    fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackeh"]
+    fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackhb.sat"]
+    fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackhub.sat"]
+    fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackob"]
+    fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackoh"]
+    fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackwh.sat"]
+    fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackwuh.sat"]
+    fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpopcounth"]
+    fn vpopcounth(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqb"]
+    fn vprefixqb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqh"]
+    fn vprefixqh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqw"]
+    fn vprefixqw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrdelta"]
+    fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybus"]
+    fn vrmpybus(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybus.acc"]
+    fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybusi"]
+    fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpybusi.acc"]
+    fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpybusv"]
+    fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybusv.acc"]
+    fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybv"]
+    fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybv.acc"]
+    fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyub"]
+    fn vrmpyub(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyub.acc"]
+    fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyubi"]
+    fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpyubi.acc"]
+    fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpyubv"]
+    fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyubv.acc"]
+    fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vror"]
+    fn vror(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrotr"]
+    fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundhb"]
+    fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundhub"]
+    fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrounduhub"]
+    fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrounduwuh"]
+    fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundwh"]
+    fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundwuh"]
+    fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrsadubi"]
+    fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrsadubi.acc"]
+    fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsatdw"]
+    fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsathub"]
+    fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsatuwuh"]
+    fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsatwh"]
+    fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsb"]
+    fn vsb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vscattermh"]
+    fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermh.add"]
+    fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhq"]
+    fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhw"]
+    fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhw.add"]
+    fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhwq"]
+    fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermw"]
+    fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermw.add"]
+    fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermwq"]
+    fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vsh"]
+    fn vsh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufeh"]
+    fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffb"]
+    fn vshuffb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffeb"]
+    fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffh"]
+    fn vshuffh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffob"]
+    fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffvdd"]
+    fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoeb"]
+    fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoeh"]
+    fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoh"]
+    fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.hf"]
+    fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.hf.hf"]
+    fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf16"]
+    fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf16.mix"]
+    fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf32"]
+    fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf32.mix"]
+    fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.sf"]
+    fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.hf"]
+    fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.sf"]
+    fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubb"]
+    fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubb.dv"]
+    fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubbnq"]
+    fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbq"]
+    fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbsat"]
+    fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbsat.dv"]
+    fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubh"]
+    fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubh.dv"]
+    fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubhnq"]
+    fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhq"]
+    fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhsat"]
+    fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhsat.dv"]
+    fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubhw"]
+    fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsububh"]
+    fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsububsat"]
+    fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsububsat.dv"]
+    fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubububb.sat"]
+    fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuhsat"]
+    fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuhsat.dv"]
+    fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubuhw"]
+    fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubuwsat"]
+    fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuwsat.dv"]
+    fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubw"]
+    fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubw.dv"]
+    fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubwnq"]
+    fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwq"]
+    fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwsat"]
+    fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwsat.dv"]
+    fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vswap"]
+    fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyb"]
+    fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyb.acc"]
+    fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpybus"]
+    fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpybus.acc"]
+    fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyhb"]
+    fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyhb.acc"]
+    fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackb"]
+    fn vunpackb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackh"]
+    fn vunpackh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackob"]
+    fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackoh"]
+    fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackub"]
+    fn vunpackub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackuh"]
+    fn vunpackuh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vxor"]
+    fn vxor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vzb"]
+    fn vzb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vzh"]
+    fn vzh(_: HvxVector) -> HvxVectorPair;
+}
+
+/// `Rd32=vextract(Vu32,Rs32)`
+///
+/// Instruction Type: LD
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(extractw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 {
+    extractw(vu, rs)
+}
+
+/// `Vd32=hi(Vss32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(hi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector {
+    hi(vss)
+}
+
+/// `Vd32=lo(Vss32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(lo))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector {
+    lo(vss)
+}
+
+/// `Vd32=vsplat(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(lvsplatw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector {
+    lvsplatw(rt)
+}
+
+/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffh(vu, vv)
+}
+
+/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffub(vu, vv)
+}
+
+/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffuh(vu, vv)
+}
+
+/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffw(vu, vv)
+}
+
+/// `Vd32.h=vabs(Vu32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector {
+    vabsh(vu)
+}
+
+/// `Vd32.h=vabs(Vu32.h):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsh_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector {
+    vabsh_sat(vu)
+}
+
+/// `Vd32.w=vabs(Vu32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector {
+    vabsw(vu)
+}
+
+/// `Vd32.w=vabs(Vu32.w):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsw_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector {
+    vabsw_sat(vu)
+}
+
+/// `Vd32.b=vadd(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddb(vu, vv)
+}
+
+/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddb_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddb_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vadd(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddh(vu, vv)
+}
+
+/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddh_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddh_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddhsat(vu, vv)
+}
+
+/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vadd(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vaddhw(vu, vv)
+}
+
+/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vaddubh(vu, vv)
+}
+
+/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddubsat(vu, vv)
+}
+
+/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddubsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddubsat_dv(vuu, vvv)
+}
+
+/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vadduhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadduhsat(vu, vv)
+}
+
+/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vadduhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vadduhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vadduhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vadduhw(vu, vv)
+}
+
+/// `Vd32.w=vadd(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_add(vu, vv)
+}
+
+/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddw_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddw_dv(vuu, vvv)
+}
+
+/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddwsat(vu, vv)
+}
+
+/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddwsat_dv(vuu, vvv)
+}
+
+/// `Vd32=valign(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(valignb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    valignb(vu, vv, rt)
+}
+
+/// `Vd32=valign(Vu32,Vv32,#u3)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(valignbi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+    valignbi(vu, vv, iu3)
+}
+
+/// `Vd32=vand(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vand))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_and(vu, vv)
+}
+
+/// `Vd32.h=vasl(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+    vaslh(vu, rt)
+}
+
+/// `Vd32.h=vasl(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaslhv(vu, vv)
+}
+
+/// `Vd32.w=vasl(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+    vaslw(vu, rt)
+}
+
+/// `Vx32.w+=vasl(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vaslw_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vasl(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslwv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaslwv(vu, vv)
+}
+
+/// `Vd32.h=vasr(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+    vasrh(vu, rt)
+}
+
+/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhbrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhbrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhubrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhubrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhubsat(vu, vv, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vasrhv(vu, vv)
+}
+
+/// `Vd32.w=vasr(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+    vasrw(vu, rt)
+}
+
+/// `Vx32.w+=vasr(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vasrw_acc(vx, vu, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwh(vu, vv, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwhrndsat(vu, vv, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwhsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwuhsat(vu, vv, rt)
+}
+
+/// `Vd32.w=vasr(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vasrwv(vu, vv)
+}
+
+/// `Vd32=Vu32`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vassign))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector {
+    vassign(vu)
+}
+
+/// `Vdd32=Vuu32`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vassignp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair {
+    vassignp(vuu)
+}
+
+/// `Vd32.h=vavg(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgh(vu, vv)
+}
+
+/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavghrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavghrnd(vu, vv)
+}
+
+/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgub(vu, vv)
+}
+
+/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgubrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgubrnd(vu, vv)
+}
+
+/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavguh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguh(vu, vv)
+}
+
+/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavguhrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguhrnd(vu, vv)
+}
+
+/// `Vd32.w=vavg(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgw(vu, vv)
+}
+
+/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgwrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgwrnd(vu, vv)
+}
+
+/// `Vd32.uh=vcl0(Vu32.uh)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vcl0h))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector {
+    vcl0h(vu)
+}
+
+/// `Vd32.uw=vcl0(Vu32.uw)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vcl0w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector {
+    vcl0w(vu)
+}
+
+/// `Vdd32=vcombine(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vcombine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vcombine(vu, vv)
+}
+
+/// `Vd32=#0`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vd0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vzero() -> HvxVector {
+    vd0()
+}
+
+/// `Vd32.b=vdeal(Vu32.b)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector {
+    vdealb(vu)
+}
+
+/// `Vd32.b=vdeale(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealb4w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdealb4w(vu, vv)
+}
+
+/// `Vd32.h=vdeal(Vu32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector {
+    vdealh(vu)
+}
+
+/// `Vdd32=vdeal(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealvdd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vdealvdd(vu, vv, rt)
+}
+
+/// `Vd32=vdelta(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdelta))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdelta(vu, vv)
+}
+
+/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpybus(vu, rt)
+}
+
+/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpybus_acc(vx, vu, rt)
+}
+
+/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vdmpybus_dv(vuu, rt)
+}
+
+/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vdmpyacc_whwubrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vdmpybus_dv_acc(vxx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhb(vu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhb_acc(vx, vu, rt)
+}
+
+/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vdmpyhb_dv(vuu, rt)
+}
+
+/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vdmpyacc_wwwhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vdmpyhb_dv_acc(vxx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhisat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhisat(vuu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhisat_acc(vx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsat(vu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsat_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsuisat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhsuisat(vuu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhsuisat_acc(vx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsusat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsusat(vu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsusat_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhvsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpyhvsat(vu, vv)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpyhvsat_acc(vx, vu, vv)
+}
+
+/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdsaduh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vdsaduh(vuu, rt)
+}
+
+/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdsaduh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vdsaduh_acc(vxx, vuu, rt)
+}
+
+/// `Vx32.w=vinsert(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vinsertwr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector {
+    vinsertwr(vx, rt)
+}
+
+/// `Vd32=vlalign(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlalignb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vlalignb(vu, vv, rt)
+}
+
+/// `Vd32=vlalign(Vu32,Vv32,#u3)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlalignbi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+    vlalignbi(vu, vv, iu3)
+}
+
+/// `Vd32.uh=vlsr(Vu32.uh,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector {
+    vlsrh(vu, rt)
+}
+
+/// `Vd32.h=vlsr(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vlsrhv(vu, vv)
+}
+
+/// `Vd32.uw=vlsr(Vu32.uw,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector {
+    vlsrw(vu, rt)
+}
+
+/// `Vd32.w=vlsr(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrwv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vlsrwv(vu, vv)
+}
+
+/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvvb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vlutvvb(vu, vv, rt)
+}
+
+/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvvb_oracc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32or_vbvbvbr(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+    rt: i32,
+) -> HvxVector {
+    vlutvvb_oracc(vx, vu, vv, rt)
+}
+
+/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vlutvwh(vu, vv, rt)
+}
+
+/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvwh_oracc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16or_whvbvhr(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vlutvwh_oracc(vxx, vu, vv, rt)
+}
+
+/// `Vd32.h=vmax(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxh(vu, vv)
+}
+
+/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxub(vu, vv)
+}
+
+/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxuh(vu, vv)
+}
+
+/// `Vd32.w=vmax(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxw(vu, vv)
+}
+
+/// `Vd32.h=vmin(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminh(vu, vv)
+}
+
+/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminub(vu, vv)
+}
+
+/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminuh(vu, vv)
+}
+
+/// `Vd32.w=vmin(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminw(vu, vv)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpabus(vuu, rt)
+}
+
+/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpaacc_whwubrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpabus_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabusv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vmpabusv(vuu, vvv)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabuuv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vmpabuuv(vuu, vvv)
+}
+
+/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpahb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpahb(vuu, rt)
+}
+
+/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpahb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpaacc_wwwhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpahb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpybus(vu, rt)
+}
+
+/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpybus_acc(vxx, vu, rt)
+}
+
+/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybusv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpybusv(vu, vv)
+}
+
+/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybusv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpyacc_whvubvb(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpybusv_acc(vxx, vu, vv)
+}
+
+/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpybv(vu, vv)
+}
+
+/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpyacc_whvbvb(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpybv_acc(vxx, vu, vv)
+}
+
+/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyewuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyewuh(vu, vv)
+}
+
+/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyh(vu, rt)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhsat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpyhsat_acc(vxx, vu, rt)
+}
+
+/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhsrs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyhsrs(vu, rt)
+}
+
+/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhss))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyhss(vu, rt)
+}
+
+/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyhus(vu, vv)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhvuh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyhus_acc(vxx, vu, vv)
+}
+
+/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyhv(vu, vv)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhvh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyhv_acc(vxx, vu, vv)
+}
+
+/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhvsrs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyhvsrs(vu, vv)
+}
+
+/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyieoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyieoh(vu, vv)
+}
+
+/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiewh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiewh_acc(vx, vu, vv)
+}
+
+/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiewuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiewuh(vu, vv)
+}
+
+/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiewuh_acc(vx, vu, vv)
+}
+
+/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyih))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyih(vu, vv)
+}
+
+/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyih_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyih_acc(vx, vu, vv)
+}
+
+/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyihb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyihb(vu, rt)
+}
+
+/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyihb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyihb_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiowh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiowh(vu, vv)
+}
+
+/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwb(vu, rt)
+}
+
+/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwb_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwh(vu, rt)
+}
+
+/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwh_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyowh(vu, vv)
+}
+
+/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh_rnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyowh_rnd(vu, vv)
+}
+
+/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVector {
+    vmpyowh_rnd_sacc(vx, vu, vv)
+}
+
+/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh_sacc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVector {
+    vmpyowh_sacc(vx, vu, vv)
+}
+
+/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyub(vu, rt)
+}
+
+/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyub_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpyacc_wuhvubrub(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpyub_acc(vxx, vu, rt)
+}
+
+/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyubv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyubv(vu, vv)
+}
+
+/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyubv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpyacc_wuhvubvub(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyubv_acc(vxx, vu, vv)
+}
+
+/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyuh(vu, rt)
+}
+
+/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpyuh_acc(vxx, vu, rt)
+}
+
+/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyuhv(vu, vv)
+}
+
+/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuhv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyuhv_acc(vxx, vu, vv)
+}
+
+/// `Vd32.h=vnavg(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgh(vu, vv)
+}
+
+/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnavgub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgub(vu, vv)
+}
+
+/// `Vd32.w=vnavg(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgw(vu, vv)
+}
+
+/// `Vd32.h=vnormamt(Vu32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnormamth))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector {
+    vnormamth(vu)
+}
+
+/// `Vd32.w=vnormamt(Vu32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnormamtw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector {
+    vnormamtw(vu)
+}
+
+/// `Vd32=vnot(Vu32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnot))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector {
+    vnot(vu)
+}
+
+/// `Vd32=vor(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_or(vu, vv)
+}
+
+/// `Vd32.b=vpacke(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackeb(vu, vv)
+}
+
+/// `Vd32.h=vpacke(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackeh(vu, vv)
+}
+
+/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackhb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackhb_sat(vu, vv)
+}
+
+/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackhub_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackhub_sat(vu, vv)
+}
+
+/// `Vd32.b=vpacko(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackob(vu, vv)
+}
+
+/// `Vd32.h=vpacko(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackoh(vu, vv)
+}
+
+/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackwh_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackwh_sat(vu, vv)
+}
+
+/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackwuh_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackwuh_sat(vu, vv)
+}
+
+/// `Vd32.h=vpopcount(Vu32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpopcounth))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector {
+    vpopcounth(vu)
+}
+
+/// `Vd32=vrdelta(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrdelta))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrdelta(vu, vv)
+}
+
+/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpybus(vu, rt)
+}
+
+/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpybus_acc(vx, vu, rt)
+}
+
+/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+    vrmpybusi(vuu, rt, iu1)
+}
+
+/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusi_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vrmpyacc_wwwubrbi(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+    iu1: i32,
+) -> HvxVectorPair {
+    vrmpybusi_acc(vxx, vuu, rt, iu1)
+}
+
+/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybusv(vu, vv)
+}
+
+/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybusv_acc(vx, vu, vv)
+}
+
+/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybv(vu, vv)
+}
+
+/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybv_acc(vx, vu, vv)
+}
+
+/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpyub(vu, rt)
+}
+
+/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyub_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpyub_acc(vx, vu, rt)
+}
+
+/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+    vrmpyubi(vuu, rt, iu1)
+}
+
+/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubi_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+    iu1: i32,
+) -> HvxVectorPair {
+    vrmpyubi_acc(vxx, vuu, rt, iu1)
+}
+
+/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpyubv(vu, vv)
+}
+
+/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpyubv_acc(vx, vu, vv)
+}
+
+/// `Vd32=vror(Vu32,Rt32)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vror))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector {
+    vror(vu, rt)
+}
+
+/// `Vd32.b=vround(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundhb(vu, vv)
+}
+
+/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundhub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundhub(vu, vv)
+}
+
+/// `Vd32.h=vround(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundwh(vu, vv)
+}
+
+/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundwuh(vu, vv)
+}
+
+/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrsadubi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+    vrsadubi(vuu, rt, iu1)
+}
+
+/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrsadubi_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+    iu1: i32,
+) -> HvxVectorPair {
+    vrsadubi_acc(vxx, vuu, rt, iu1)
+}
+
+/// `Vd32.ub=vsat(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsathub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsathub(vu, vv)
+}
+
+/// `Vd32.h=vsat(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsatwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsatwh(vu, vv)
+}
+
+/// `Vdd32.h=vsxt(Vu32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair {
+    vsb(vu)
+}
+
+/// `Vdd32.w=vsxt(Vu32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair {
+    vsh(vu)
+}
+
+/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshufeh(vu, vv)
+}
+
+/// `Vd32.b=vshuff(Vu32.b)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector {
+    vshuffb(vu)
+}
+
+/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshuffeb(vu, vv)
+}
+
+/// `Vd32.h=vshuff(Vu32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector {
+    vshuffh(vu)
+}
+
+/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshuffob(vu, vv)
+}
+
+/// `Vdd32=vshuff(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffvdd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vshuffvdd(vu, vv, rt)
+}
+
+/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufoeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vshufoeb(vu, vv)
+}
+
+/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufoeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vshufoeh(vu, vv)
+}
+
+/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshufoh(vu, vv)
+}
+
+/// `Vd32.b=vsub(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubb(vu, vv)
+}
+
+/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubb_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubb_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vsub(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubh(vu, vv)
+}
+
+/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubh_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubh_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubhsat(vu, vv)
+}
+
+/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vsub(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsubhw(vu, vv)
+}
+
+/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsububh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsububh(vu, vv)
+}
+
+/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsububsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsububsat(vu, vv)
+}
+
+/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsububsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsububsat_dv(vuu, vvv)
+}
+
+/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubuhsat(vu, vv)
+}
+
+/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubuhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubuhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubuhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsubuhw(vu, vv)
+}
+
+/// `Vd32.w=vsub(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_sub(vu, vv)
+}
+
+/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubw_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubw_dv(vuu, vvv)
+}
+
+/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubwsat(vu, vv)
+}
+
+/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubwsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vtmpyb(vuu, rt)
+}
+
+/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpyacc_whwbrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vtmpyb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vtmpybus(vuu, rt)
+}
+
+/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpyacc_whwubrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vtmpybus_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vtmpyhb(vuu, rt)
+}
+
+/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyhb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vtmpyacc_wwwhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vtmpyhb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vunpack(Vu32.b)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair {
+    vunpackb(vu)
+}
+
+/// `Vdd32.w=vunpack(Vu32.h)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair {
+    vunpackh(vu)
+}
+
+/// `Vxx32.h|=vunpacko(Vu32.b)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+    vunpackob(vxx, vu)
+}
+
+/// `Vxx32.w|=vunpacko(Vu32.h)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+    vunpackoh(vxx, vu)
+}
+
+/// `Vdd32.uh=vunpack(Vu32.ub)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair {
+    vunpackub(vu)
+}
+
+/// `Vdd32.uw=vunpack(Vu32.uh)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair {
+    vunpackuh(vu)
+}
+
+/// `Vd32=vxor(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vxor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_xor(vu, vv)
+}
+
+/// `Vdd32.uh=vzxt(Vu32.ub)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vzb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair {
+    vzb(vu)
+}
+
+/// `Vdd32.uw=vzxt(Vu32.uh)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vzh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair {
+    vzh(vu)
+}
+
+/// `Vd32.b=vsplat(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(lvsplatb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector {
+    lvsplatb(rt)
+}
+
+/// `Vd32.h=vsplat(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(lvsplath))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector {
+    lvsplath(rt)
+}
+
+/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddbsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddbsat(vu, vv)
+}
+
+/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddbsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddbsat_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddclbh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddclbh(vu, vv)
+}
+
+/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddclbw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddclbw(vu, vv)
+}
+
+/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddhw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vaddacc_wwvhvh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vaddhw_acc(vxx, vu, vv)
+}
+
+/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddubh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vaddacc_whvubvub(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vaddubh_acc(vxx, vu, vv)
+}
+
+/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddububb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddububb_sat(vu, vv)
+}
+
+/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vadduhw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vaddacc_wwvuhvuh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vadduhw_acc(vxx, vu, vv)
+}
+
+/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vadduwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadduwsat(vu, vv)
+}
+
+/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vadduwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vadduwsat_dv(vuu, vvv)
+}
+
+/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vasrhbsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhbsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vasruwuhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruwuhrndsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vasrwuhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwuhrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vlsr(Vu32.ub,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlsrb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector {
+    vlsrb(vu, rt)
+}
+
+/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvvb_nm))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vlutvvb_nm(vu, vv, rt)
+}
+
+/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvvb_oracci))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32or_vbvbvbi(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+    iu3: i32,
+) -> HvxVector {
+    vlutvvb_oracci(vx, vu, vv, iu3)
+}
+
+/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvvbi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+    vlutvvbi(vu, vv, iu3)
+}
+
+/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvwh_nm))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vlutvwh_nm(vu, vv, rt)
+}
+
+/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvwh_oracci))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16or_whvbvhi(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+    iu3: i32,
+) -> HvxVectorPair {
+    vlutvwh_oracci(vxx, vu, vv, iu3)
+}
+
+/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvwhi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
+    vlutvwhi(vu, vv, iu3)
+}
+
+/// `Vd32.b=vmax(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmaxb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxb(vu, vv)
+}
+
+/// `Vd32.b=vmin(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vminb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminb(vu, vv)
+}
+
+/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpauhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpauhb(vuu, rt)
+}
+
+/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpauhb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpaacc_wwwuhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpauhb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32=vmpye(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyewuh_64))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyewuh_64(vu, vv)
+}
+
+/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyiwub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwub(vu, rt)
+}
+
+/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyiwub_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwub_acc(vx, vu, rt)
+}
+
+/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vmpyoacc_wvwvh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyowh_64_acc(vxx, vu, vv)
+}
+
+/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vrounduhub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrounduhub(vu, vv)
+}
+
+/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vrounduwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrounduwuh(vu, vv)
+}
+
+/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsatuwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsatuwuh(vu, vv)
+}
+
+/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubbsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubbsat(vu, vv)
+}
+
+/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubbsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubbsat_dv(vuu, vvv)
+}
+
+/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubububb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubububb_sat(vu, vv)
+}
+
+/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubuwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubuwsat(vu, vv)
+}
+
+/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubuwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubuwsat_dv(vuu, vvv)
+}
+
+/// `Vd32.b=vabs(Vu32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vabsb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector {
+    vabsb(vu)
+}
+
+/// `Vd32.b=vabs(Vu32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vabsb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector {
+    vabsb_sat(vu)
+}
+
+/// `Vx32.h+=vasl(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vaslh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vaslh_acc(vx, vu, rt)
+}
+
+/// `Vx32.h+=vasr(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasrh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vasrh_acc(vx, vu, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasruhubrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruhubrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasruhubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruhubsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasruwuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruwuhsat(vu, vv, rt)
+}
+
+/// `Vd32.b=vavg(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavgb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgb(vu, vv)
+}
+
+/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavgbrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgbrnd(vu, vv)
+}
+
+/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavguw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguw(vu, vv)
+}
+
+/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavguwrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguwrnd(vu, vv)
+}
+
+/// `Vdd32=#0`
+///
+/// Instruction Type: MAPPING
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vdd0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vzero() -> HvxVectorPair {
+    vdd0()
+}
+
+/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h`
+///
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vgathermh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+    vgathermh(rs, rt, mu, vv)
+}
+
+/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h`
+///
+/// Instruction Type: CVI_GATHER_DV
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vgathermhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
+    vgathermhw(rs, rt, mu, vvv)
+}
+
+/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w`
+///
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vgathermw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+    vgathermw(rs, rt, mu, vv)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpabuu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpabuu(vuu, rt)
+}
+
+/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpabuu_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpaacc_whwubrub(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpabuu_acc(vxx, vuu, rt)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpyh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyh_acc(vxx, vu, rt)
+}
+
+/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpyuhe))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyuhe(vu, rt)
+}
+
+/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpyuhe_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyuhe_acc(vx, vu, rt)
+}
+
+/// `Vd32.b=vnavg(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vnavgb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgb(vu, vv)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermh(rt, mu, vv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermh_add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermh_add(rt, mu, vv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32`
+///
+/// Instruction Type: CVI_SCATTER_DV
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+    vscattermhw(rt, mu, vvv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32`
+///
+/// Instruction Type: CVI_SCATTER_DV
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermhw_add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+    vscattermhw_add(rt, mu, vvv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermw(rt, mu, vv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermw_add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermw_add(rt, mu, vv, vw)
+}
+
+/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[cfg_attr(test, assert_instr(vasr_into))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vasrinto_wwvwvw(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vasr_into(vxx, vu, vv)
+}
+
+/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[cfg_attr(test, assert_instr(vrotr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrotr(vu, vv)
+}
+
+/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[cfg_attr(test, assert_instr(vsatdw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsatdw(vu, vv)
+}
+
+/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyhubs10))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpy_wubwbi_h(
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyhubs10(vuu, vvv, iu2)
+}
+
+/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyhubs10_vxx(vxx, vuu, vvv, iu2)
+}
+
+/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyvubs10))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpy_wubwbi_v(
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyvubs10(vuu, vvv, iu2)
+}
+
+/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyvubs10_vxx(vxx, vuu, vvv, iu2)
+}
+
+/// `Vd32.hf=vabs(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vabs_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector {
+    vabs_hf(vu)
+}
+
+/// `Vd32.sf=vabs(Vu32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vabs_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector {
+    vabs_sf(vu)
+}
+
+/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_hf(vu, vv)
+}
+
+/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_hf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_hf_hf(vu, vv)
+}
+
+/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf16(vu, vv)
+}
+
+/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf16_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf16_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf32(vu, vv)
+}
+
+/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf32_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf32_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_sf(vu, vv)
+}
+
+/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vadd_sf_hf(vu, vv)
+}
+
+/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_sf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_sf_sf(vu, vv)
+}
+
+/// `Vd32.w=vfmv(Vu32.w)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vassign_fp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector {
+    vassign_fp(vu)
+}
+
+/// `Vd32.hf=Vu32.qf16`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vconv_hf_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector {
+    vconv_hf_qf16(vu)
+}
+
+/// `Vd32.hf=Vuu32.qf32`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vconv_hf_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector {
+    vconv_hf_qf32(vuu)
+}
+
+/// `Vd32.sf=Vu32.qf32`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vconv_sf_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector {
+    vconv_sf_qf32(vu)
+}
+
+/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_b_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vcvt_b_hf(vu, vv)
+}
+
+/// `Vd32.h=vcvt(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_h_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+    vcvt_h_hf(vu)
+}
+
+/// `Vdd32.hf=vcvt(Vu32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_b))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair {
+    vcvt_hf_b(vu)
+}
+
+/// `Vd32.hf=vcvt(Vu32.h)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_h))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector {
+    vcvt_hf_h(vu)
+}
+
+/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vcvt_hf_sf(vu, vv)
+}
+
+/// `Vdd32.hf=vcvt(Vu32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_ub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair {
+    vcvt_hf_ub(vu)
+}
+
+/// `Vd32.hf=vcvt(Vu32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_uh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector {
+    vcvt_hf_uh(vu)
+}
+
+/// `Vdd32.sf=vcvt(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair {
+    vcvt_sf_hf(vu)
+}
+
+/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_ub_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vcvt_ub_hf(vu, vv)
+}
+
+/// `Vd32.uh=vcvt(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_uh_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+    vcvt_uh_hf(vu)
+}
+
+/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpy_sf_hf(vu, vv)
+}
+
+/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpy_sf_hf_acc(vx, vu, vv)
+}
+
+/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmax_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmax_hf(vu, vv)
+}
+
+/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmax_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmax_sf(vu, vv)
+}
+
+/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmin_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmin_hf(vu, vv)
+}
+
+/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmin_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmin_sf(vu, vv)
+}
+
+/// `Vd32.hf=vfneg(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfneg_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector {
+    vfneg_hf(vu)
+}
+
+/// `Vd32.sf=vfneg(Vu32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfneg_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector {
+    vfneg_sf(vu)
+}
+
+/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmax_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmax_hf(vu, vv)
+}
+
+/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmax_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmax_sf(vu, vv)
+}
+
+/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmin_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmin_hf(vu, vv)
+}
+
+/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmin_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmin_sf(vu, vv)
+}
+
+/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_hf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_hf_hf(vu, vv)
+}
+
+/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_hf_hf_acc(vx, vu, vv)
+}
+
+/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf16(vu, vv)
+}
+
+/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf16_hf(vu, vv)
+}
+
+/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf16_mix_hf(vu, vv)
+}
+
+/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf32(vu, vv)
+}
+
+/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_qf32_hf(vu, vv)
+}
+
+/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_qf32_mix_hf(vu, vv)
+}
+
+/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_qf32_qf16(vu, vv)
+}
+
+/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf32_sf(vu, vv)
+}
+
+/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_sf_hf(vu, vv)
+}
+
+/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpy_sf_hf_acc(vxx, vu, vv)
+}
+
+/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_sf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_sf_sf(vu, vv)
+}
+
+/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_hf(vu, vv)
+}
+
+/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_hf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_hf_hf(vu, vv)
+}
+
+/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf16(vu, vv)
+}
+
+/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf16_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf16_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf32(vu, vv)
+}
+
+/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf32_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf32_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_sf(vu, vv)
+}
+
+/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsub_sf_hf(vu, vv)
+}
+
+/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_sf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_sf_sf(vu, vv)
+}
+
+/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvuhubrndsat(vuu, vv)
+}
+
+/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvuhubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvuhubsat(vuu, vv)
+}
+
+/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvwuhrndsat(vuu, vv)
+}
+
+/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvwuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvwuhsat(vuu, vv)
+}
+
+/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vmpyuhvs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyuhvs(vu, vv)
+}
+
+/// `Vd32.h=Vu32.hf`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_h_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector {
+    vconv_h_hf(vu)
+}
+
+/// `Vd32.hf=Vu32.h`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_hf_h))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector {
+    vconv_hf_h(vu)
+}
+
+/// `Vd32.sf=Vu32.w`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_sf_w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector {
+    vconv_sf_w(vu)
+}
+
+/// `Vd32.w=Vu32.sf`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_w_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector {
+    vconv_w_sf(vu)
+}
+
+/// `Vd32=vgetqfext(Vu32.x,Rt32)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(get_qfext))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+    get_qfext(vu, rt)
+}
+
+/// `Vd32.x=vsetqfext(Vu32,Rt32)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(set_qfext))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+    set_qfext(vu, rt)
+}
+
+/// `Vd32.f8=vabs(Vu32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vabs_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector {
+    vabs_f8(vu)
+}
+
+/// `Vdd32.hf=vcvt2(Vu32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vcvt2_hf_b))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair {
+    vcvt2_hf_b(vu)
+}
+
+/// `Vdd32.hf=vcvt2(Vu32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair {
+    vcvt2_hf_ub(vu)
+}
+
+/// `Vdd32.hf=vcvt(Vu32.f8)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair {
+    vcvt_hf_f8(vu)
+}
+
+/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vfmax_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmax_f8(vu, vv)
+}
+
+/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vfmin_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmin_f8(vu, vv)
+}
+
+/// `Vd32.f8=vfneg(Vu32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vfneg_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector {
+    vfneg_f8(vu)
+}
+
+/// `Qd4=and(Qs4,Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=and(Qs4,!Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_and_n(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=not(Qs4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_not(vandvrt(
+            core::mem::transmute::<HvxVectorPred, HvxVector>(qs),
+            -1,
+        )),
+        -1,
+    ))
+}
+
+/// `Qd4=or(Qs4,Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=or(Qs4,!Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_or_n(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vsetq(Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2(rt), -1))
+}
+
+/// `Qd4=xor(Qs4,Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `if (!Qv4) vmem(Rt32+#s4)=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_nqpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_nt_nqpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_nt_qpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (Qv4) vmem(Rt32+#s4)=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_qpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (!Qv4) Vx32.b+=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddbnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.b+=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddbq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.h+=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddhnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.h+=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddhq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.w+=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddwnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.w+=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `Vd32=vand(Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
+}
+
+/// `Vx32|=vand(Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandvrt_acc(vx, core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
+}
+
+/// `Qd4=vand(Vu32,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vu, rt))
+}
+
+/// `Qx4|=vand(Vu32,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt_acc(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qx),
+        vu,
+        rt,
+    ))
+}
+
+/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqb(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqand_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqb_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqor_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqb_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqxacc_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqb_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqh(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqand_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqh_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqor_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqh_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqxacc_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqh_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqw(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqand_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqw_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqor_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqw_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqxacc_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqw_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtb(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtb_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtb_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtb_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgth(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgth_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgth_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgth_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtub(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvubvub(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtub_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvubvub(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtub_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvubvub(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtub_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuh(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvuhvuh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuh_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvuhvuh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuh_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuh_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuw(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvuwvuw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuw_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvuwvuw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuw_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuw_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtw(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtw_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtw_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtw_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Vd32=vmux(Qt4,Vu32,Vv32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmux(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        vu,
+        vv,
+    )
+}
+
+/// `if (!Qv4) Vx32.b-=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubbnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.b-=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubbq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.h-=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubhnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.h-=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubhq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.w-=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubwnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.w-=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `Vdd32=vswap(Qt4,Vu32,Vv32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vswap(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        vu,
+        vv,
+    )
+}
+
+/// `Qd4=vsetq2(Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2v2(rt), -1))
+}
+
+/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        shuffeqh(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        shuffeqw(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Vd32=vand(!Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandnqrt(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
+        rt,
+    )
+}
+
+/// `Vx32|=vand(!Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandnqrt_acc(
+        vx,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
+        rt,
+    )
+}
+
+/// `Vd32=vand(!Qv4,Vu32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+    vandvnqv(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vu,
+    )
+}
+
+/// `Vd32=vand(Qv4,Vu32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+    vandvqv(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vu,
+    )
+}
+
+/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_aqrmvh(
+    rs: *mut HvxVector,
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+) {
+    vgathermhq(
+        rs,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+    )
+}
+
+/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_GATHER_DV
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_aqrmww(
+    rs: *mut HvxVector,
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vvv: HvxVectorPair,
+) {
+    vgathermhwq(
+        rs,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vvv,
+    )
+}
+
+/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_aqrmvw(
+    rs: *mut HvxVector,
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+) {
+    vgathermwq(
+        rs,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+    )
+}
+
+/// `Vd32.b=prefixsum(Qv4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+    vprefixqb(vandvrt(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
+        -1,
+    ))
+}
+
+/// `Vd32.h=prefixsum(Qv4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+    vprefixqh(vandvrt(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
+        -1,
+    ))
+}
+
+/// `Vd32.w=prefixsum(Qv4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+    vprefixqw(vandvrt(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
+        -1,
+    ))
+}
+
+/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_qrmvhv(
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+    vw: HvxVector,
+) {
+    vscattermhq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+        vw,
+    )
+}
+
+/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_SCATTER_DV
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_qrmwwv(
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vvv: HvxVectorPair,
+    vw: HvxVector,
+) {
+    vscattermhwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vvv,
+        vw,
+    )
+}
+
+/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_qrmvwv(
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+    vw: HvxVector,
+) {
+    vscattermwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+        vw,
+    )
+}
+
+/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vwvwq_carry_sat(
+    vu: HvxVector,
+    vv: HvxVector,
+    qs: HvxVectorPred,
+) -> HvxVector {
+    vaddcarrysat(
+        vu,
+        vv,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+    )
+}
+
+/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgthf(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvhfvhf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgthf_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvhfvhf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgthf_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgthf_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtsf(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvsfvsf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtsf_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvsfvsf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtsf_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtsf_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
diff --git a/crates/core_arch/src/hexagon/mod.rs b/crates/core_arch/src/hexagon/mod.rs
new file mode 100644
index 0000000000..a9c53d6efe
--- /dev/null
+++ b/crates/core_arch/src/hexagon/mod.rs
@@ -0,0 +1,12 @@
+//! Hexagon architecture intrinsics
+//!
+//! This module contains intrinsics for the Qualcomm Hexagon DSP architecture,
+//! including the Hexagon Vector Extensions (HVX).
+//!
+//! HVX is a wide SIMD architecture designed for high-performance signal processing,
+//! machine learning, and image processing workloads.
+
+mod hvx;
+
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub use self::hvx::*;
diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 039a4c4411..8a1bead7c4 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -23,6 +23,7 @@
     mips_target_feature,
     powerpc_target_feature,
     loongarch_target_feature,
+    hexagon_target_feature,
     wasm_target_feature,
     abi_unadjusted,
     rtm_target_feature,
diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs
index 3577175ae3..f8ea68b35c 100644
--- a/crates/core_arch/src/mod.rs
+++ b/crates/core_arch/src/mod.rs
@@ -320,6 +320,19 @@ pub mod arch {
     pub mod s390x {
         pub use crate::core_arch::s390x::*;
     }
+
+    /// Platform-specific intrinsics for the `hexagon` platform.
+    ///
+    /// This module provides intrinsics for the Qualcomm Hexagon DSP architecture,
+    /// including the Hexagon Vector Extensions (HVX).
+    ///
+    /// See the [module documentation](../index.html) for more details.
+    #[cfg(any(target_arch = "hexagon", doc))]
+    #[doc(cfg(target_arch = "hexagon"))]
+    #[unstable(feature = "stdarch_hexagon", issue = "none")]
+    pub mod hexagon {
+        pub use crate::core_arch::hexagon::*;
+    }
 }
 
 #[cfg(any(target_arch = "x86", target_arch = "x86_64", doc))]
@@ -379,3 +392,7 @@ mod loongarch64;
 #[cfg(any(target_arch = "s390x", doc))]
 #[doc(cfg(target_arch = "s390x"))]
 mod s390x;
+
+#[cfg(any(target_arch = "hexagon", doc))]
+#[doc(cfg(target_arch = "hexagon"))]
+mod hexagon;
diff --git a/crates/stdarch-gen-hexagon/Cargo.toml b/crates/stdarch-gen-hexagon/Cargo.toml
new file mode 100644
index 0000000000..f8c446c1d1
--- /dev/null
+++ b/crates/stdarch-gen-hexagon/Cargo.toml
@@ -0,0 +1,10 @@
+[package]
+name = "stdarch-gen-hexagon"
+version = "0.1.0"
+authors = ["The Rust Project Developers"]
+license = "MIT OR Apache-2.0"
+edition = "2021"
+
+[dependencies]
+regex = "1.10"
+ureq = "2.9"
diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
new file mode 100644
index 0000000000..2f8dec75b7
--- /dev/null
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -0,0 +1,1697 @@
+//! Hexagon HVX Code Generator
+//!
+//! This generator creates hvx.rs from scratch using the LLVM HVX header file
+//! as the sole source of truth. It parses the C intrinsic prototypes and
+//! generates Rust wrapper functions with appropriate attributes.
+//!
+//! Usage:
+//!     cd crates/stdarch-gen-hexagon
+//!     cargo run
+//!     # Output is written directly to ../core_arch/src/hexagon/hvx.rs
+
+use regex::Regex;
+use std::collections::{HashMap, HashSet};
+use std::fs::File;
+use std::io::Write;
+use std::path::Path;
+
+/// Mappings from HVX intrinsics to architecture-independent SIMD intrinsics.
+/// These intrinsics have equivalent semantics and can be lowered to the generic form.
+fn get_simd_intrinsic_mappings() -> HashMap<&'static str, &'static str> {
+    let mut map = HashMap::new();
+    // Bitwise operations (element-size independent)
+    map.insert("vxor", "simd_xor");
+    map.insert("vand", "simd_and");
+    map.insert("vor", "simd_or");
+    // Word (32-bit) arithmetic operations
+    map.insert("vaddw", "simd_add");
+    map.insert("vsubw", "simd_sub");
+    map
+}
+
+/// The tracking issue number for the stdarch_hexagon feature
+const TRACKING_ISSUE: &str = "151523";
+
+/// LLVM tag to fetch the header from
+const LLVM_TAG: &str = "llvmorg-22.1.0-rc1";
+
+/// Maximum HVX architecture version supported by rustc
+/// Check with: rustc --target=hexagon-unknown-linux-musl --print target-features
+const MAX_SUPPORTED_ARCH: u32 = 79;
+
+/// URL template for the HVX header file
+const HEADER_URL: &str =
+    "https://raw.githubusercontent.com/llvm/llvm-project/{tag}/clang/lib/Headers/hvx_hexagon_protos.h";
+
+/// Intrinsic information parsed from the LLVM header
+#[derive(Debug, Clone)]
+struct IntrinsicInfo {
+    /// The Q6_* intrinsic name (e.g., "Q6_V_vadd_VV")
+    q6_name: String,
+    /// The LLVM builtin name without prefix (e.g., "V6_vaddb")
+    builtin_name: String,
+    /// The short instruction name for assert_instr (e.g., "vaddb")
+    instr_name: String,
+    /// The assembly syntax from the comment
+    asm_syntax: String,
+    /// Instruction type
+    instr_type: String,
+    /// Execution slots
+    exec_slots: String,
+    /// Minimum HVX architecture version required
+    min_arch: u32,
+    /// Return type
+    return_type: RustType,
+    /// Parameters (name, type)
+    params: Vec<(String, RustType)>,
+    /// Whether this is a compound intrinsic (multiple builtins)
+    is_compound: bool,
+    /// For compound intrinsics: the parsed expression tree
+    compound_expr: Option<CompoundExpr>,
+}
+
+/// Expression tree for compound intrinsics
+#[derive(Debug, Clone)]
+enum CompoundExpr {
+    /// A call to a builtin: (builtin_name without V6_ prefix, arguments)
+    BuiltinCall(String, Vec<CompoundExpr>),
+    /// A parameter reference by name
+    Param(String),
+    /// An integer literal (like -1)
+    IntLiteral(i32),
+}
+
+/// Rust type mappings
+#[derive(Debug, Clone, PartialEq)]
+enum RustType {
+    HvxVector,
+    HvxVectorPair,
+    HvxVectorPred,
+    I32,
+    MutPtrHvxVector,
+    Unit,
+}
+
+impl RustType {
+    fn from_c_type(c_type: &str) -> Option<Self> {
+        match c_type.trim() {
+            "HVX_Vector" => Some(RustType::HvxVector),
+            "HVX_VectorPair" => Some(RustType::HvxVectorPair),
+            "HVX_VectorPred" => Some(RustType::HvxVectorPred),
+            "Word32" => Some(RustType::I32),
+            "HVX_Vector*" => Some(RustType::MutPtrHvxVector),
+            "void" => Some(RustType::Unit),
+            _ => None,
+        }
+    }
+
+    fn to_rust_str(&self) -> &'static str {
+        match self {
+            RustType::HvxVector => "HvxVector",
+            RustType::HvxVectorPair => "HvxVectorPair",
+            RustType::HvxVectorPred => "HvxVectorPred",
+            RustType::I32 => "i32",
+            RustType::MutPtrHvxVector => "*mut HvxVector",
+            RustType::Unit => "()",
+        }
+    }
+
+    fn to_extern_str(&self) -> &'static str {
+        match self {
+            RustType::HvxVector => "HvxVector",
+            RustType::HvxVectorPair => "HvxVectorPair",
+            RustType::HvxVectorPred => "HvxVectorPred",
+            RustType::I32 => "i32",
+            RustType::MutPtrHvxVector => "*mut HvxVector",
+            RustType::Unit => "()",
+        }
+    }
+}
+
+/// Parse a compound macro expression into an expression tree
+fn parse_compound_expr(expr: &str) -> Option<CompoundExpr> {
+    let expr = expr.trim();
+
+    // Try to match an integer literal (like -1)
+    if let Ok(n) = expr.parse::<i32>() {
+        return Some(CompoundExpr::IntLiteral(n));
+    }
+
+    // Try to match a simple parameter name (Vu, Vv, Rt, Qs, Qt, Qx, Vx, etc.)
+    // These are typically short identifiers in the macro
+    if expr.len() <= 3
+        && expr.chars().all(|c| c.is_ascii_alphanumeric() || c == '_')
+        && !expr.contains("__")
+    {
+        return Some(CompoundExpr::Param(expr.to_lowercase()));
+    }
+
+    // Check if it's wrapped in extra parens first
+    if expr.starts_with('(') && expr.ends_with(')') {
+        // Check if these parens wrap the entire expression
+        let inner = &expr[1..expr.len() - 1];
+        // Count depth: if after removing outer parens the expression is balanced,
+        // the outer parens were enclosing everything
+        if is_balanced_parens(inner) {
+            // But we also need to verify these aren't part of a function call
+            // If the inner expression is balanced and the whole thing starts with (
+            // and ends with ), it's a paren wrapper
+            let result = parse_compound_expr(inner);
+            if result.is_some() {
+                return result;
+            }
+        }
+    }
+
+    // Try to match __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args)
+    // The args portion may contain nested calls, so we need to find the matching paren
+    if expr.starts_with("__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_") {
+        // Find the end of the builtin name (after V6_)
+        let prefix = "__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_";
+        let after_prefix = &expr[prefix.len()..];
+        if let Some(paren_pos) = after_prefix.find(')') {
+            let builtin_name = &after_prefix[..paren_pos];
+            let rest = &after_prefix[paren_pos + 1..]; // Skip the closing ) of the WRAP
+                                                       // rest should now be "(args)"
+            if rest.starts_with('(') && rest.ends_with(')') {
+                let args_str = &rest[1..rest.len() - 1];
+                let args = parse_compound_args(args_str)?;
+                return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args));
+            }
+        }
+    }
+
+    // Try to match __builtin_HEXAGON_V6_xxx(args) without wrap
+    if expr.starts_with("__builtin_HEXAGON_V6_") {
+        let prefix = "__builtin_HEXAGON_V6_";
+        let after_prefix = &expr[prefix.len()..];
+        if let Some(paren_pos) = after_prefix.find('(') {
+            let builtin_name = &after_prefix[..paren_pos];
+            let rest = &after_prefix[paren_pos..];
+            if rest.starts_with('(') && rest.ends_with(')') {
+                let args_str = &rest[1..rest.len() - 1];
+                let args = parse_compound_args(args_str)?;
+                return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args));
+            }
+        }
+    }
+
+    None
+}
+
+/// Check if parentheses are balanced in a string
+fn is_balanced_parens(s: &str) -> bool {
+    let mut depth = 0;
+    for c in s.chars() {
+        match c {
+            '(' => depth += 1,
+            ')' => {
+                depth -= 1;
+                if depth < 0 {
+                    return false;
+                }
+            }
+            _ => {}
+        }
+    }
+    depth == 0
+}
+
+/// Parse comma-separated arguments, respecting nested parentheses
+fn parse_compound_args(args_str: &str) -> Option<Vec<CompoundExpr>> {
+    let mut args = Vec::new();
+    let mut current = String::new();
+    let mut depth = 0;
+
+    for c in args_str.chars() {
+        match c {
+            '(' => {
+                depth += 1;
+                current.push(c);
+            }
+            ')' => {
+                depth -= 1;
+                current.push(c);
+            }
+            ',' if depth == 0 => {
+                let arg = current.trim().to_string();
+                if !arg.is_empty() {
+                    args.push(parse_compound_expr(&arg)?);
+                }
+                current.clear();
+            }
+            _ => current.push(c),
+        }
+    }
+
+    // Don't forget the last argument
+    let arg = current.trim().to_string();
+    if !arg.is_empty() {
+        args.push(parse_compound_expr(&arg)?);
+    }
+
+    Some(args)
+}
+
+/// Extract all builtin names used in a compound expression
+fn collect_builtins_from_expr(expr: &CompoundExpr, builtins: &mut HashSet<String>) {
+    match expr {
+        CompoundExpr::BuiltinCall(name, args) => {
+            builtins.insert(name.clone());
+            for arg in args {
+                collect_builtins_from_expr(arg, builtins);
+            }
+        }
+        CompoundExpr::Param(_) | CompoundExpr::IntLiteral(_) => {}
+    }
+}
+
+/// Download the LLVM HVX header file
+fn download_header() -> Result<String, String> {
+    let url = HEADER_URL.replace("{tag}", LLVM_TAG);
+    println!("Downloading HVX header from: {}", url);
+
+    let response = ureq::get(&url)
+        .call()
+        .map_err(|e| format!("Failed to download header: {}", e))?;
+
+    response
+        .into_string()
+        .map_err(|e| format!("Failed to read response: {}", e))
+}
+
+/// Parse a C function prototype to extract return type and parameters
+fn parse_prototype(prototype: &str) -> Option<(RustType, Vec<(String, RustType)>)> {
+    // Pattern: ReturnType FunctionName(ParamType1 Param1, ParamType2 Param2, ...)
+    let proto_re = Regex::new(r"(\w+(?:\*)?)\s+Q6_\w+\(([^)]*)\)").unwrap();
+
+    if let Some(caps) = proto_re.captures(prototype) {
+        let return_type_str = caps[1].trim();
+        let params_str = &caps[2];
+
+        let return_type = RustType::from_c_type(return_type_str)?;
+
+        let mut params = Vec::new();
+        if !params_str.trim().is_empty() {
+            for param in params_str.split(',') {
+                let param = param.trim();
+                // Pattern: Type Name or Type* Name
+                let param_re = Regex::new(r"(\w+\*?)\s+(\w+)").unwrap();
+                if let Some(pcaps) = param_re.captures(param) {
+                    let ptype_str = pcaps[1].trim();
+                    let pname = pcaps[2].to_lowercase();
+                    if let Some(ptype) = RustType::from_c_type(ptype_str) {
+                        params.push((pname, ptype));
+                    } else {
+                        return None; // Unknown type
+                    }
+                }
+            }
+        }
+
+        Some((return_type, params))
+    } else {
+        None
+    }
+}
+
+/// Parse the LLVM header file to extract intrinsic information
+fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
+    let mut intrinsics = Vec::new();
+
+    let arch_re = Regex::new(r"#if __HVX_ARCH__ >= (\d+)").unwrap();
+
+    // Regex to extract the simple builtin name from a macro body
+    // Match: __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args)
+    let simple_builtin_re =
+        Regex::new(r"__BUILTIN_VECTOR_WRAP\(__builtin_HEXAGON_(\w+)\)\([^)]*\)\s*$").unwrap();
+
+    // Also handle builtins without VECTOR_WRAP
+    let simple_builtin_re2 = Regex::new(r"__builtin_HEXAGON_(\w+)\([^)]*\)\s*$").unwrap();
+
+    let lines: Vec<&str> = content.lines().collect();
+    let mut current_arch: u32 = 60;
+    let mut i = 0;
+
+    while i < lines.len() {
+        // Track architecture version
+        if let Some(caps) = arch_re.captures(lines[i]) {
+            if let Ok(arch) = caps[1].parse() {
+                current_arch = arch;
+            }
+        }
+
+        // Look for Assembly Syntax comment block
+        if lines[i].contains("Assembly Syntax:") {
+            let mut asm_syntax = String::new();
+            let mut prototype = String::new();
+            let mut instr_type = String::new();
+            let mut exec_slots = String::new();
+
+            // Parse the comment block
+            let mut j = i;
+            while j < lines.len() && !lines[j].starts_with("#define") {
+                let line = lines[j];
+                if line.contains("Assembly Syntax:") {
+                    if let Some(pos) = line.find("Assembly Syntax:") {
+                        asm_syntax = line[pos + 16..].trim().to_string();
+                    }
+                } else if line.contains("C Intrinsic Prototype:") {
+                    if let Some(pos) = line.find("C Intrinsic Prototype:") {
+                        prototype = line[pos + 22..].trim().to_string();
+                    }
+                } else if line.contains("Instruction Type:") {
+                    if let Some(pos) = line.find("Instruction Type:") {
+                        instr_type = line[pos + 17..].trim().to_string();
+                    }
+                } else if line.contains("Execution Slots:") {
+                    if let Some(pos) = line.find("Execution Slots:") {
+                        exec_slots = line[pos + 16..].trim().to_string();
+                    }
+                }
+                j += 1;
+            }
+
+            // Now find the #define line
+            while j < lines.len() && !lines[j].starts_with("#define") {
+                j += 1;
+            }
+
+            if j < lines.len() {
+                let define_line = lines[j];
+
+                // Extract Q6 name and check if it's simple or compound
+                let q6_name_re = Regex::new(r"#define\s+(Q6_\w+)").unwrap();
+                if let Some(caps) = q6_name_re.captures(define_line) {
+                    let q6_name = caps[1].to_string();
+
+                    // Get the full macro body (handle line continuations)
+                    let mut macro_body = define_line.to_string();
+                    let mut k = j;
+                    while macro_body.trim_end().ends_with('\\') && k + 1 < lines.len() {
+                        k += 1;
+                        macro_body.push_str(lines[k]);
+                    }
+
+                    // Try to extract simple builtin name
+                    let builtin_name = if let Some(bcaps) = simple_builtin_re.captures(&macro_body)
+                    {
+                        Some(bcaps[1].to_string())
+                    } else if let Some(bcaps) = simple_builtin_re2.captures(&macro_body) {
+                        Some(bcaps[1].to_string())
+                    } else {
+                        None
+                    };
+
+                    // Check if it's a compound intrinsic (multiple __builtin calls)
+                    let builtin_count = macro_body.matches("__builtin_HEXAGON_").count();
+                    let is_compound = builtin_count > 1;
+
+                    // Parse prototype
+                    if let Some((return_type, params)) = parse_prototype(&prototype) {
+                        if is_compound {
+                            // For compound intrinsics, parse the expression
+                            // Extract the macro body after the parameter list
+                            let macro_expr_re =
+                                Regex::new(r"#define\s+Q6_\w+\([^)]*\)\s+(.+)").unwrap();
+                            if let Some(expr_caps) = macro_expr_re.captures(&macro_body) {
+                                let expr_str =
+                                    expr_caps[1].trim().replace('\n', " ").replace('\\', " ");
+                                let expr_str = expr_str.trim();
+
+                                if let Some(compound_expr) = parse_compound_expr(expr_str) {
+                                    // For compound intrinsics, we use the outermost builtin
+                                    // as the "primary" for the instruction name
+                                    let (primary_builtin, instr_name) = match &compound_expr {
+                                        CompoundExpr::BuiltinCall(name, _) => {
+                                            (name.clone(), name.clone())
+                                        }
+                                        _ => continue,
+                                    };
+
+                                    intrinsics.push(IntrinsicInfo {
+                                        q6_name,
+                                        builtin_name: format!("V6_{}", primary_builtin),
+                                        instr_name,
+                                        asm_syntax,
+                                        instr_type,
+                                        exec_slots,
+                                        min_arch: current_arch,
+                                        return_type,
+                                        params,
+                                        is_compound: true,
+                                        compound_expr: Some(compound_expr),
+                                    });
+                                }
+                            }
+                        } else if let Some(builtin) = builtin_name {
+                            // Extract short instruction name
+                            let instr_name = if builtin.starts_with("V6_") {
+                                builtin[3..].to_string()
+                            } else {
+                                builtin.clone()
+                            };
+
+                            intrinsics.push(IntrinsicInfo {
+                                q6_name,
+                                builtin_name: builtin,
+                                instr_name,
+                                asm_syntax,
+                                instr_type,
+                                exec_slots,
+                                min_arch: current_arch,
+                                return_type,
+                                params,
+                                is_compound: false,
+                                compound_expr: None,
+                            });
+                        }
+                    }
+                }
+            }
+            i = j;
+        }
+        i += 1;
+    }
+
+    intrinsics
+}
+
+/// Convert Q6 name to Rust function name (lowercase with underscores)
+fn q6_to_rust_name(q6_name: &str) -> String {
+    // Q6_V_hi_W -> q6_v_hi_w
+    q6_name.to_lowercase()
+}
+
+/// Generate the module documentation
+fn generate_module_doc() -> String {
+    r#"//! Hexagon HVX intrinsics
+//!
+//! This module provides intrinsics for the Hexagon Vector Extensions (HVX).
+//! HVX is a wide vector extension designed for high-performance signal processing.
+//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61)
+//!
+//! ## Vector Types
+//!
+//! HVX supports different vector lengths depending on the configuration:
+//! - 128-byte mode: `HvxVector` is 1024 bits (128 bytes)
+//! - 64-byte mode: `HvxVector` is 512 bits (64 bytes)
+//!
+//! This implementation targets 128-byte mode by default. To change the vector
+//! length mode, use the appropriate target feature when compiling:
+//! - For 128-byte mode: `-C target-feature=+hvx-length128b`
+//! - For 64-byte mode: `-C target-feature=+hvx-length64b`
+//!
+//! Note that HVX v66 and later default to 128-byte mode, while earlier versions
+//! default to 64-byte mode.
+//!
+//! ## Architecture Versions
+//!
+//! Different intrinsics require different HVX architecture versions. Use the
+//! appropriate target feature to enable the required version:
+//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations)
+//! - HVX v62: `-C target-feature=+hvxv62`
+//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support)
+//! - HVX v66: `-C target-feature=+hvxv66`
+//! - HVX v68: `-C target-feature=+hvxv68`
+//! - HVX v69: `-C target-feature=+hvxv69`
+//! - HVX v73: `-C target-feature=+hvxv73`
+//! - HVX v79: `-C target-feature=+hvxv79`
+//! - HVX v81: `-C target-feature=+hvxv81`
+//!
+//! Each version includes all features from previous versions.
+"#
+    .to_string()
+}
+
+/// Generate the type definitions
+fn generate_types() -> String {
+    format!(
+        r#"
+#![allow(non_camel_case_types)]
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+use crate::intrinsics::simd::{{simd_add, simd_and, simd_or, simd_sub, simd_xor}};
+
+// HVX type definitions for 128-byte vector mode (default for v66+)
+// Use -C target-feature=+hvx-length128b to enable
+#[cfg(target_feature = "hvx-length128b")]
+types! {{
+    #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")]
+
+    /// HVX vector type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a single HVX vector register containing 32 x 32-bit values.
+    pub struct HvxVector(32 x i32);
+
+    /// HVX vector pair type (2048 bits / 256 bytes)
+    ///
+    /// This type represents a pair of HVX vector registers, often used for
+    /// operations that produce double-width results.
+    pub struct HvxVectorPair(64 x i32);
+
+    /// HVX vector predicate type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a predicate vector used for conditional operations.
+    /// Each bit corresponds to a lane in the vector.
+    pub struct HvxVectorPred(32 x i32);
+}}
+
+// HVX type definitions for 64-byte vector mode (default for v60-v65)
+// Use -C target-feature=+hvx-length64b to enable, or omit hvx-length128b
+#[cfg(not(target_feature = "hvx-length128b"))]
+types! {{
+    #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")]
+
+    /// HVX vector type (512 bits / 64 bytes)
+    ///
+    /// This type represents a single HVX vector register containing 16 x 32-bit values.
+    pub struct HvxVector(16 x i32);
+
+    /// HVX vector pair type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a pair of HVX vector registers, often used for
+    /// operations that produce double-width results.
+    pub struct HvxVectorPair(32 x i32);
+
+    /// HVX vector predicate type (512 bits / 64 bytes)
+    ///
+    /// This type represents a predicate vector used for conditional operations.
+    /// Each bit corresponds to a lane in the vector.
+    pub struct HvxVectorPred(16 x i32);
+}}
+"#
+    )
+}
+
+/// Builtin signature information for extern declarations
+struct BuiltinSignature {
+    /// The V6_ prefixed name
+    full_name: String,
+    /// The short name (without V6_)
+    short_name: String,
+    /// Return type
+    return_type: RustType,
+    /// Parameter types
+    param_types: Vec<RustType>,
+}
+
+/// Get known signatures for builtins used in compound operations
+/// These are the helper builtins that don't have their own Q6_ wrapper
+fn get_compound_helper_signatures() -> HashMap<String, BuiltinSignature> {
+    let mut map = HashMap::new();
+
+    // vandvrt: HVX_Vector -> i32 -> HVX_Vector
+    // Converts predicate to vector representation. LLVM uses HVX_Vector for both.
+    map.insert(
+        "vandvrt".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandvrt".to_string(),
+            short_name: "vandvrt".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::I32],
+        },
+    );
+
+    // vandqrt: HVX_Vector -> i32 -> HVX_Vector
+    // Converts vector representation back to predicate. LLVM uses HVX_Vector for both.
+    map.insert(
+        "vandqrt".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandqrt".to_string(),
+            short_name: "vandqrt".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::I32],
+        },
+    );
+
+    // vandvrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector
+    map.insert(
+        "vandvrt_acc".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandvrt_acc".to_string(),
+            short_name: "vandvrt_acc".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32],
+        },
+    );
+
+    // vandqrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector
+    map.insert(
+        "vandqrt_acc".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandqrt_acc".to_string(),
+            short_name: "vandqrt_acc".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32],
+        },
+    );
+
+    // pred_and: HVX_Vector -> HVX_Vector -> HVX_Vector
+    map.insert(
+        "pred_and".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_and".to_string(),
+            short_name: "pred_and".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    // pred_and_n: HVX_Vector -> HVX_Vector -> HVX_Vector
+    map.insert(
+        "pred_and_n".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_and_n".to_string(),
+            short_name: "pred_and_n".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    // pred_or: HVX_Vector -> HVX_Vector -> HVX_Vector
+    map.insert(
+        "pred_or".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_or".to_string(),
+            short_name: "pred_or".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    // pred_or_n: HVX_Vector -> HVX_Vector -> HVX_Vector
+    map.insert(
+        "pred_or_n".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_or_n".to_string(),
+            short_name: "pred_or_n".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    // pred_xor: HVX_Vector -> HVX_Vector -> HVX_Vector
+    map.insert(
+        "pred_xor".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_xor".to_string(),
+            short_name: "pred_xor".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    // pred_not: HVX_Vector -> HVX_Vector
+    map.insert(
+        "pred_not".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_not".to_string(),
+            short_name: "pred_not".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector],
+        },
+    );
+
+    // pred_scalar2: i32 -> HVX_Vector
+    map.insert(
+        "pred_scalar2".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_scalar2".to_string(),
+            short_name: "pred_scalar2".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::I32],
+        },
+    );
+
+    // Conditional store operations
+    map.insert(
+        "vS32b_qpred_ai".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vS32b_qpred_ai".to_string(),
+            short_name: "vS32b_qpred_ai".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    map.insert(
+        "vS32b_nqpred_ai".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vS32b_nqpred_ai".to_string(),
+            short_name: "vS32b_nqpred_ai".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    map.insert(
+        "vS32b_nt_qpred_ai".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vS32b_nt_qpred_ai".to_string(),
+            short_name: "vS32b_nt_qpred_ai".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    map.insert(
+        "vS32b_nt_nqpred_ai".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vS32b_nt_nqpred_ai".to_string(),
+            short_name: "vS32b_nt_nqpred_ai".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    // Conditional accumulation operations
+    for (suffix, _elem) in [("b", "byte"), ("h", "halfword"), ("w", "word")] {
+        // vaddbq, vaddhq, vaddwq
+        map.insert(
+            format!("vadd{}q", suffix),
+            BuiltinSignature {
+                full_name: format!("V6_vadd{}q", suffix),
+                short_name: format!("vadd{}q", suffix),
+                return_type: RustType::HvxVector,
+                param_types: vec![
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                ],
+            },
+        );
+        // vaddbnq, vaddhnq, vaddwnq
+        map.insert(
+            format!("vadd{}nq", suffix),
+            BuiltinSignature {
+                full_name: format!("V6_vadd{}nq", suffix),
+                short_name: format!("vadd{}nq", suffix),
+                return_type: RustType::HvxVector,
+                param_types: vec![
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                ],
+            },
+        );
+    }
+
+    // Comparison operations with accumulation
+    // veqb_and, veqb_or, veqb_xor, etc.
+    for elem in ["b", "h", "w", "ub", "uh", "uw"] {
+        for op in ["and", "or", "xor"] {
+            // veq*_and, veq*_or, veq*_xor
+            map.insert(
+                format!("veq{}_{}", elem, op),
+                BuiltinSignature {
+                    full_name: format!("V6_veq{}_{}", elem, op),
+                    short_name: format!("veq{}_{}", elem, op),
+                    return_type: RustType::HvxVector,
+                    param_types: vec![
+                        RustType::HvxVector,
+                        RustType::HvxVector,
+                        RustType::HvxVector,
+                    ],
+                },
+            );
+            // vgt*_and, vgt*_or, vgt*_xor
+            map.insert(
+                format!("vgt{}_{}", elem, op),
+                BuiltinSignature {
+                    full_name: format!("V6_vgt{}_{}", elem, op),
+                    short_name: format!("vgt{}_{}", elem, op),
+                    return_type: RustType::HvxVector,
+                    param_types: vec![
+                        RustType::HvxVector,
+                        RustType::HvxVector,
+                        RustType::HvxVector,
+                    ],
+                },
+            );
+        }
+    }
+
+    // Floating-point comparison operations (hf = half-float, sf = single-float)
+    for elem in ["hf", "sf"] {
+        // Basic comparison: vgt*
+        map.insert(
+            format!("vgt{}", elem),
+            BuiltinSignature {
+                full_name: format!("V6_vgt{}", elem),
+                short_name: format!("vgt{}", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![RustType::HvxVector, RustType::HvxVector],
+            },
+        );
+
+        for op in ["and", "or", "xor"] {
+            // vgt*_and, vgt*_or, vgt*_xor
+            map.insert(
+                format!("vgt{}_{}", elem, op),
+                BuiltinSignature {
+                    full_name: format!("V6_vgt{}_{}", elem, op),
+                    short_name: format!("vgt{}_{}", elem, op),
+                    return_type: RustType::HvxVector,
+                    param_types: vec![
+                        RustType::HvxVector,
+                        RustType::HvxVector,
+                        RustType::HvxVector,
+                    ],
+                },
+            );
+        }
+    }
+
+    // Prefix operations with predicate
+    for elem in ["b", "h", "w"] {
+        map.insert(
+            format!("vprefixq{}", elem),
+            BuiltinSignature {
+                full_name: format!("V6_vprefixq{}", elem),
+                short_name: format!("vprefixq{}", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![RustType::HvxVector],
+            },
+        );
+    }
+
+    // Scatter operations with predicate
+    map.insert(
+        "vscattermhq".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vscattermhq".to_string(),
+            short_name: "vscattermhq".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::I32,
+                RustType::I32,
+                RustType::HvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    map.insert(
+        "vscattermhwq".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vscattermhwq".to_string(),
+            short_name: "vscattermhwq".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::I32,
+                RustType::I32,
+                RustType::HvxVectorPair,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    map.insert(
+        "vscattermwq".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vscattermwq".to_string(),
+            short_name: "vscattermwq".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::I32,
+                RustType::I32,
+                RustType::HvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    // Add with carry saturation
+    map.insert(
+        "vaddcarrysat".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vaddcarrysat".to_string(),
+            short_name: "vaddcarrysat".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::HvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    // Gather operations with predicate
+    map.insert(
+        "vgathermhq".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vgathermhq".to_string(),
+            short_name: "vgathermhq".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+                RustType::I32,
+                RustType::I32,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    map.insert(
+        "vgathermhwq".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vgathermhwq".to_string(),
+            short_name: "vgathermhwq".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+                RustType::I32,
+                RustType::I32,
+                RustType::HvxVectorPair,
+            ],
+        },
+    );
+
+    map.insert(
+        "vgathermwq".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vgathermwq".to_string(),
+            short_name: "vgathermwq".to_string(),
+            return_type: RustType::Unit,
+            param_types: vec![
+                RustType::MutPtrHvxVector,
+                RustType::HvxVector,
+                RustType::I32,
+                RustType::I32,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    // Basic comparison operations (without accumulation)
+    for elem in ["b", "h", "w", "ub", "uh", "uw"] {
+        // vgt* - greater than
+        map.insert(
+            format!("vgt{}", elem),
+            BuiltinSignature {
+                full_name: format!("V6_vgt{}", elem),
+                short_name: format!("vgt{}", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![RustType::HvxVector, RustType::HvxVector],
+            },
+        );
+        // veq* - equal
+        map.insert(
+            format!("veq{}", elem),
+            BuiltinSignature {
+                full_name: format!("V6_veq{}", elem),
+                short_name: format!("veq{}", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![RustType::HvxVector, RustType::HvxVector],
+            },
+        );
+    }
+
+    // Conditional subtraction operations (vsub*q, vsub*nq)
+    for elem in ["b", "h", "w"] {
+        map.insert(
+            format!("vsub{}q", elem),
+            BuiltinSignature {
+                full_name: format!("V6_vsub{}q", elem),
+                short_name: format!("vsub{}q", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                ],
+            },
+        );
+        map.insert(
+            format!("vsub{}nq", elem),
+            BuiltinSignature {
+                full_name: format!("V6_vsub{}nq", elem),
+                short_name: format!("vsub{}nq", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                    RustType::HvxVector,
+                ],
+            },
+        );
+    }
+
+    // vmux - vector mux (select based on predicate)
+    map.insert(
+        "vmux".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vmux".to_string(),
+            short_name: "vmux".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::HvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    // vswap - vector swap based on predicate
+    map.insert(
+        "vswap".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vswap".to_string(),
+            short_name: "vswap".to_string(),
+            return_type: RustType::HvxVectorPair,
+            param_types: vec![
+                RustType::HvxVector,
+                RustType::HvxVector,
+                RustType::HvxVector,
+            ],
+        },
+    );
+
+    // shuffeq operations - take vectors (internal pred representation) and return vector
+    for elem in ["h", "w"] {
+        map.insert(
+            format!("shuffeq{}", elem),
+            BuiltinSignature {
+                full_name: format!("V6_shuffeq{}", elem),
+                short_name: format!("shuffeq{}", elem),
+                return_type: RustType::HvxVector,
+                param_types: vec![RustType::HvxVector, RustType::HvxVector],
+            },
+        );
+    }
+
+    // Predicate AND with vector operations
+    map.insert(
+        "vandvqv".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandvqv".to_string(),
+            short_name: "vandvqv".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    map.insert(
+        "vandvnqv".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandvnqv".to_string(),
+            short_name: "vandvnqv".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector],
+        },
+    );
+
+    // vandnqrt and vandnqrt_acc
+    map.insert(
+        "vandnqrt".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandnqrt".to_string(),
+            short_name: "vandnqrt".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::I32],
+        },
+    );
+
+    map.insert(
+        "vandnqrt_acc".to_string(),
+        BuiltinSignature {
+            full_name: "V6_vandnqrt_acc".to_string(),
+            short_name: "vandnqrt_acc".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32],
+        },
+    );
+
+    // pred_scalar2v2
+    map.insert(
+        "pred_scalar2v2".to_string(),
+        BuiltinSignature {
+            full_name: "V6_pred_scalar2v2".to_string(),
+            short_name: "pred_scalar2v2".to_string(),
+            return_type: RustType::HvxVector,
+            param_types: vec![RustType::I32],
+        },
+    );
+
+    map
+}
+
+/// Generate extern declarations for all intrinsics
+fn generate_extern_block(intrinsics: &[IntrinsicInfo]) -> String {
+    let mut output = String::new();
+
+    // Collect unique builtins to avoid duplicates
+    let mut seen_builtins: HashSet<String> = HashSet::new();
+    let mut decls: Vec<(String, String, RustType, Vec<RustType>)> = Vec::new();
+
+    // First, add simple intrinsics
+    for info in intrinsics.iter().filter(|i| !i.is_compound) {
+        if seen_builtins.contains(&info.builtin_name) {
+            continue;
+        }
+        seen_builtins.insert(info.builtin_name.clone());
+
+        let param_types: Vec<RustType> = info.params.iter().map(|(_, t)| t.clone()).collect();
+        decls.push((
+            info.builtin_name.clone(),
+            info.instr_name.clone(),
+            info.return_type.clone(),
+            param_types,
+        ));
+    }
+
+    // Then, collect all builtins used in compound expressions
+    let helper_sigs = get_compound_helper_signatures();
+    let mut compound_builtins: HashSet<String> = HashSet::new();
+
+    for info in intrinsics.iter().filter(|i| i.is_compound) {
+        if let Some(ref expr) = info.compound_expr {
+            collect_builtins_from_expr(expr, &mut compound_builtins);
+        }
+    }
+
+    // Add compound helper builtins
+    let mut missing_builtins = Vec::new();
+    for builtin_name in compound_builtins {
+        let full_name = format!("V6_{}", builtin_name);
+        if seen_builtins.contains(&full_name) {
+            continue;
+        }
+        seen_builtins.insert(full_name.clone());
+
+        if let Some(sig) = helper_sigs.get(&builtin_name) {
+            decls.push((
+                sig.full_name.clone(),
+                sig.short_name.clone(),
+                sig.return_type.clone(),
+                sig.param_types.clone(),
+            ));
+        } else {
+            missing_builtins.push(builtin_name);
+        }
+    }
+
+    // Report missing builtins (for development purposes)
+    if !missing_builtins.is_empty() {
+        eprintln!("Warning: Missing helper signatures for compound builtins:");
+        for name in &missing_builtins {
+            eprintln!("  - {}", name);
+        }
+    }
+
+    // Sort by builtin name for consistent output
+    decls.sort_by(|a, b| a.0.cmp(&b.0));
+
+    // Generate 128-byte mode intrinsics (default for v66+)
+    output.push_str("// LLVM intrinsic declarations for 128-byte vector mode\n");
+    output.push_str("#[cfg(target_feature = \"hvx-length128b\")]\n");
+    output.push_str("#[allow(improper_ctypes)]\n");
+    output.push_str("unsafe extern \"unadjusted\" {\n");
+
+    for (builtin_name, instr_name, return_type, param_types) in &decls {
+        let base_link = builtin_name.replace('_', ".");
+        let link_name = if builtin_name.starts_with("V6_") {
+            format!("llvm.hexagon.{}.128B", base_link)
+        } else {
+            format!("llvm.hexagon.{}", base_link)
+        };
+
+        let params_str = if param_types.is_empty() {
+            String::new()
+        } else {
+            param_types
+                .iter()
+                .map(|t| format!("_: {}", t.to_extern_str()))
+                .collect::<Vec<_>>()
+                .join(", ")
+        };
+
+        let return_str = if *return_type == RustType::Unit {
+            " -> ()".to_string()
+        } else {
+            format!(" -> {}", return_type.to_extern_str())
+        };
+
+        output.push_str(&format!(
+            "    #[link_name = \"{}\"]\n    fn {}({}){};\n",
+            link_name, instr_name, params_str, return_str
+        ));
+    }
+
+    output.push_str("}\n\n");
+
+    // Generate 64-byte mode intrinsics (default for v60-v65)
+    output.push_str("// LLVM intrinsic declarations for 64-byte vector mode\n");
+    output.push_str("#[cfg(not(target_feature = \"hvx-length128b\"))]\n");
+    output.push_str("#[allow(improper_ctypes)]\n");
+    output.push_str("unsafe extern \"unadjusted\" {\n");
+
+    for (builtin_name, instr_name, return_type, param_types) in &decls {
+        let base_link = builtin_name.replace('_', ".");
+        // 64-byte mode uses intrinsics without the .128B suffix
+        let link_name = format!("llvm.hexagon.{}", base_link);
+
+        let params_str = if param_types.is_empty() {
+            String::new()
+        } else {
+            param_types
+                .iter()
+                .map(|t| format!("_: {}", t.to_extern_str()))
+                .collect::<Vec<_>>()
+                .join(", ")
+        };
+
+        let return_str = if *return_type == RustType::Unit {
+            " -> ()".to_string()
+        } else {
+            format!(" -> {}", return_type.to_extern_str())
+        };
+
+        output.push_str(&format!(
+            "    #[link_name = \"{}\"]\n    fn {}({}){};\n",
+            link_name, instr_name, params_str, return_str
+        ));
+    }
+
+    output.push_str("}\n");
+    output
+}
+
+/// Generate Rust code for a compound expression
+/// `params` maps parameter names to their types in the function signature
+/// Get the type of an expression
+fn get_expr_type(
+    expr: &CompoundExpr,
+    params: &HashMap<String, RustType>,
+    helper_sigs: &HashMap<String, BuiltinSignature>,
+) -> Option<RustType> {
+    match expr {
+        CompoundExpr::BuiltinCall(name, _) => {
+            helper_sigs.get(name).map(|sig| sig.return_type.clone())
+        }
+        CompoundExpr::Param(name) => params.get(name).cloned(),
+        CompoundExpr::IntLiteral(_) => Some(RustType::I32),
+    }
+}
+
+fn generate_compound_expr_code(
+    expr: &CompoundExpr,
+    params: &HashMap<String, RustType>,
+    helper_sigs: &HashMap<String, BuiltinSignature>,
+) -> String {
+    match expr {
+        CompoundExpr::BuiltinCall(name, args) => {
+            // Get the expected parameter types for this builtin
+            let expected_types = helper_sigs
+                .get(name)
+                .map(|sig| sig.param_types.clone())
+                .unwrap_or_default();
+
+            let args_code: Vec<String> = args
+                .iter()
+                .enumerate()
+                .map(|(i, arg)| {
+                    let arg_code = generate_compound_expr_code(arg, params, helper_sigs);
+
+                    // Check if we need to transmute this argument
+                    let expected_type = expected_types.get(i);
+                    let actual_type = get_expr_type(arg, params, helper_sigs);
+
+                    // If the builtin expects HvxVector but the arg is HvxVectorPred, transmute
+                    if expected_type == Some(&RustType::HvxVector)
+                        && actual_type == Some(RustType::HvxVectorPred)
+                    {
+                        format!(
+                            "core::mem::transmute::<HvxVectorPred, HvxVector>({})",
+                            arg_code
+                        )
+                    } else {
+                        arg_code
+                    }
+                })
+                .collect();
+            format!("{}({})", name, args_code.join(", "))
+        }
+        CompoundExpr::Param(name) => name.clone(),
+        CompoundExpr::IntLiteral(n) => n.to_string(),
+    }
+}
+
+/// Get the primary instruction name from a compound expression (innermost significant op)
+fn get_compound_primary_instr(expr: &CompoundExpr) -> Option<String> {
+    match expr {
+        CompoundExpr::BuiltinCall(name, args) => {
+            // For vandqrt wrapper, look inside
+            if name == "vandqrt" && args.len() >= 1 {
+                if let Some(inner) = get_compound_primary_instr(&args[0]) {
+                    return Some(inner);
+                }
+            }
+            // For store operations, use the store name
+            if name.starts_with("vS32b") {
+                return Some(name.clone());
+            }
+            // For conditional accumulation, use the add name
+            if name.starts_with("vadd") && (name.ends_with("q") || name.ends_with("nq")) {
+                return Some(name.clone());
+            }
+            // For predicate operations
+            if name.starts_with("pred_") {
+                return Some(name.clone());
+            }
+            // For comparison operations with accumulation
+            if (name.starts_with("veq") || name.starts_with("vgt"))
+                && (name.ends_with("_and") || name.ends_with("_or") || name.ends_with("_xor"))
+            {
+                return Some(name.clone());
+            }
+            Some(name.clone())
+        }
+        _ => None,
+    }
+}
+
+/// Get override implementations for specific compound intrinsics.
+/// Some C macros rely on implicit type conversions that don't work with
+/// our stricter Rust types, so we provide corrected implementations.
+fn get_compound_overrides() -> HashMap<&'static str, &'static str> {
+    let mut map = HashMap::new();
+
+    // Q6_V_vand_QR: takes pred, returns vec
+    // Use transmute to convert pred to vec for LLVM, call vandvrt
+    map.insert(
+        "Q6_V_vand_QR",
+        "vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)",
+    );
+
+    // Q6_V_vandor_VQR: takes vec and pred, returns vec
+    map.insert(
+        "Q6_V_vandor_VQR",
+        "vandvrt_acc(vx, core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)",
+    );
+
+    // Q6_Q_vand_VR: takes vec, returns pred
+    map.insert(
+        "Q6_Q_vand_VR",
+        "core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vu, rt))",
+    );
+
+    // Q6_Q_vandor_QVR: takes pred and vec, returns pred
+    map.insert(
+        "Q6_Q_vandor_QVR",
+        "core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt_acc(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), vu, rt))",
+    );
+
+    map
+}
+
+/// Generate wrapper functions for all intrinsics
+fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String {
+    let mut output = String::new();
+    let simd_mappings = get_simd_intrinsic_mappings();
+
+    // Generate simple intrinsics
+    for info in intrinsics.iter().filter(|i| !i.is_compound) {
+        let rust_name = q6_to_rust_name(&info.q6_name);
+
+        // Generate doc comment
+        output.push_str(&format!("/// `{}`\n", info.asm_syntax));
+        output.push_str("///\n");
+        output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type));
+        output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots));
+
+        // Generate attributes
+        output.push_str("#[inline(always)]\n");
+        output.push_str(&format!(
+            "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n",
+            info.min_arch
+        ));
+
+        // Check if we should use simd intrinsic instead
+        let use_simd = simd_mappings.get(info.instr_name.as_str());
+
+        // assert_instr uses the original instruction name
+        output.push_str(&format!(
+            "#[cfg_attr(test, assert_instr({}))]\n",
+            info.instr_name
+        ));
+
+        output.push_str(&format!(
+            "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n",
+            TRACKING_ISSUE
+        ));
+
+        // Generate function signature
+        let params_str = info
+            .params
+            .iter()
+            .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str()))
+            .collect::<Vec<_>>()
+            .join(", ");
+
+        let return_str = if info.return_type == RustType::Unit {
+            String::new()
+        } else {
+            format!(" -> {}", info.return_type.to_rust_str())
+        };
+
+        output.push_str(&format!(
+            "pub unsafe fn {}({}){} {{\n",
+            rust_name, params_str, return_str
+        ));
+
+        // Generate function body
+        let args_str = info
+            .params
+            .iter()
+            .map(|(name, _)| name.as_str())
+            .collect::<Vec<_>>()
+            .join(", ");
+
+        if let Some(simd_fn) = use_simd {
+            // Use architecture-independent simd intrinsic
+            output.push_str(&format!("    {}({})\n", simd_fn, args_str));
+        } else {
+            // Use the LLVM intrinsic
+            output.push_str(&format!("    {}({})\n", info.instr_name, args_str));
+        }
+
+        output.push_str("}\n\n");
+    }
+
+    // Generate compound intrinsics
+    let helper_sigs = get_compound_helper_signatures();
+    let overrides = get_compound_overrides();
+    for info in intrinsics.iter().filter(|i| i.is_compound) {
+        if let Some(ref compound_expr) = info.compound_expr {
+            let rust_name = q6_to_rust_name(&info.q6_name);
+
+            // Get the primary instruction for assert_instr
+            let _primary_instr = get_compound_primary_instr(compound_expr)
+                .unwrap_or_else(|| info.instr_name.clone());
+
+            // Generate doc comment
+            output.push_str(&format!("/// `{}`\n", info.asm_syntax));
+            output.push_str("///\n");
+            output.push_str(
+                "/// This is a compound operation composed of multiple HVX instructions.\n",
+            );
+            if !info.instr_type.is_empty() {
+                output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type));
+            }
+            if !info.exec_slots.is_empty() {
+                output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots));
+            }
+
+            // Generate attributes
+            output.push_str("#[inline(always)]\n");
+            output.push_str(&format!(
+                "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n",
+                info.min_arch
+            ));
+
+            // For compound ops, we skip assert_instr since they emit multiple instructions
+            // output.push_str(&format!(
+            //     "#[cfg_attr(test, assert_instr({}))]\n",
+            //     primary_instr
+            // ));
+
+            output.push_str(&format!(
+                "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n",
+                TRACKING_ISSUE
+            ));
+
+            // Generate function signature
+            let params_str = info
+                .params
+                .iter()
+                .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str()))
+                .collect::<Vec<_>>()
+                .join(", ");
+
+            let return_str = if info.return_type == RustType::Unit {
+                String::new()
+            } else {
+                format!(" -> {}", info.return_type.to_rust_str())
+            };
+
+            output.push_str(&format!(
+                "pub unsafe fn {}({}){} {{\n",
+                rust_name, params_str, return_str
+            ));
+
+            // Check if we have an override for this intrinsic
+            let body = if let Some(override_body) = overrides.get(info.q6_name.as_str()) {
+                override_body.to_string()
+            } else {
+                // Build param type map for expression code generation
+                let param_types: HashMap<String, RustType> = info.params.iter().cloned().collect();
+                // Generate function body from compound expression
+                let expr_body =
+                    generate_compound_expr_code(compound_expr, &param_types, &helper_sigs);
+
+                // Check if we need to transmute the result
+                let expr_return_type = get_expr_type(compound_expr, &param_types, &helper_sigs);
+                if info.return_type == RustType::HvxVectorPred
+                    && expr_return_type == Some(RustType::HvxVector)
+                {
+                    format!(
+                        "core::mem::transmute::<HvxVector, HvxVectorPred>({})",
+                        expr_body
+                    )
+                } else {
+                    expr_body
+                }
+            };
+            output.push_str(&format!("    {}\n", body));
+
+            output.push_str("}\n\n");
+        }
+    }
+
+    output
+}
+
+/// Generate the complete hvx.rs file
+fn generate_hvx_rs(intrinsics: &[IntrinsicInfo], output_path: &Path) -> Result<(), String> {
+    let mut output =
+        File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?;
+
+    writeln!(output, "{}", generate_module_doc()).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_types()).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_extern_block(intrinsics)).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?;
+
+    // Ensure file is flushed before running rustfmt
+    drop(output);
+
+    // Run rustfmt on the generated file
+    let status = std::process::Command::new("rustfmt")
+        .arg(output_path)
+        .status()
+        .map_err(|e| format!("Failed to run rustfmt: {}", e))?;
+
+    if !status.success() {
+        return Err("rustfmt failed".to_string());
+    }
+
+    Ok(())
+}
+
+fn main() -> Result<(), String> {
+    println!("=== Hexagon HVX Code Generator ===\n");
+
+    // Download and parse the LLVM header
+    println!("Step 1: Downloading LLVM HVX header...");
+    let header_content = download_header()?;
+    println!("  Downloaded {} bytes", header_content.len());
+
+    println!("\nStep 2: Parsing intrinsic definitions...");
+    let all_intrinsics = parse_header(&header_content);
+    println!("  Found {} intrinsic definitions", all_intrinsics.len());
+
+    // Filter out intrinsics requiring architecture versions not yet supported by rustc
+    let intrinsics: Vec<_> = all_intrinsics
+        .into_iter()
+        .filter(|i| i.min_arch <= MAX_SUPPORTED_ARCH)
+        .collect();
+    let filtered_count = intrinsics.len();
+    println!(
+        "  Filtered to {} intrinsics (max supported: hvxv{})",
+        filtered_count, MAX_SUPPORTED_ARCH
+    );
+
+    // Count simple vs compound
+    let simple_count = intrinsics.iter().filter(|i| !i.is_compound).count();
+    let compound_count = intrinsics.iter().filter(|i| i.is_compound).count();
+    println!("  Simple intrinsics: {}", simple_count);
+    println!("  Compound intrinsics: {}", compound_count);
+
+    // Print some sample intrinsics for verification
+    println!("\n  Sample simple intrinsics:");
+    for info in intrinsics.iter().filter(|i| !i.is_compound).take(5) {
+        println!(
+            "    {} -> {} ({})",
+            info.q6_name, info.builtin_name, info.asm_syntax
+        );
+    }
+
+    println!("\n  Sample compound intrinsics:");
+    for info in intrinsics.iter().filter(|i| i.is_compound).take(5) {
+        println!("    {} ({})", info.q6_name, info.asm_syntax);
+    }
+
+    // Count architecture versions
+    let mut arch_counts: HashMap<u32, usize> = HashMap::new();
+    for info in &intrinsics {
+        *arch_counts.entry(info.min_arch).or_insert(0) += 1;
+    }
+    println!("\n  By architecture version:");
+    let mut archs: Vec<_> = arch_counts.iter().collect();
+    archs.sort_by_key(|(k, _)| *k);
+    for (arch, count) in archs {
+        println!("    HVX v{}: {} intrinsics", arch, count);
+    }
+
+    // Generate output
+    let crate_dir = std::env::var("CARGO_MANIFEST_DIR")
+        .map(std::path::PathBuf::from)
+        .unwrap_or_else(|_| std::env::current_dir().unwrap());
+
+    let output_path = crate_dir.join("../core_arch/src/hexagon/hvx.rs");
+
+    println!("\nStep 3: Generating hvx.rs...");
+    generate_hvx_rs(&intrinsics, &output_path)?;
+
+    println!("\n=== Results ===");
+    println!("  Generated {} simple wrapper functions", simple_count);
+    println!("  Generated {} compound wrapper functions", compound_count);
+    println!("  Total: {} functions", simple_count + compound_count);
+    println!("  Output: {}", output_path.display());
+
+    Ok(())
+}
diff --git a/examples/Cargo.toml b/examples/Cargo.toml
index 61451edee8..1e893dc15f 100644
--- a/examples/Cargo.toml
+++ b/examples/Cargo.toml
@@ -23,6 +23,10 @@ path = "hex.rs"
 name = "connect5"
 path = "connect5.rs"
 
+[[bin]]
+name = "gaussian"
+path = "gaussian.rs"
+
 [[example]]
 name = "wasm"
 crate-type = ["cdylib"]
diff --git a/examples/gaussian.rs b/examples/gaussian.rs
new file mode 100644
index 0000000000..1891f194ed
--- /dev/null
+++ b/examples/gaussian.rs
@@ -0,0 +1,358 @@
+//! Hexagon HVX Gaussian 3x3 blur example
+//!
+//! This example demonstrates the use of Hexagon HVX intrinsics to implement
+//! a 3x3 Gaussian blur filter on unsigned 8-bit images.
+//!
+//! The 3x3 Gaussian kernel is:
+//!     1 2 1
+//!     2 4 2  / 16
+//!     1 2 1
+//!
+//! This is a separable filter: `[1 2 1]^T * [1 2 1] / 16`.
+//! Each 1D pass of `[1 2 1] / 4` is computed using byte averaging:
+//!     avg(avg(a, c), b) ≈ (a + 2b + c) / 4
+//!
+//! This approach uses only `HvxVector` (single-vector) operations, avoiding
+//! `HvxVectorPair` which currently has ABI limitations in the Rust/LLVM
+//! Hexagon backend.
+//!
+//! To build:
+//!
+//!     RUSTFLAGS="-C target-feature=+hvxv60,+hvx-length128b \
+//!         -C linker=hexagon-unknown-linux-musl-clang" \
+//!         cargo +nightly build --bin gaussian -p stdarch_examples \
+//!         --target hexagon-unknown-linux-musl \
+//!         -Zbuild-std -Zbuild-std-features=llvm-libunwind
+//!
+//! To run under QEMU:
+//!
+//!     qemu-hexagon -L <sysroot>/target/hexagon-unknown-linux-musl \
+//!         target/hexagon-unknown-linux-musl/debug/gaussian
+
+#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))]
+#![cfg_attr(target_arch = "hexagon", feature(hexagon_target_feature))]
+#![allow(
+    unsafe_op_in_unsafe_fn,
+    clippy::unwrap_used,
+    clippy::print_stdout,
+    clippy::missing_docs_in_private_items,
+    clippy::cast_possible_wrap,
+    clippy::cast_ptr_alignment,
+    dead_code
+)]
+
+#[cfg(target_arch = "hexagon")]
+use core_arch::arch::hexagon::*;
+
+/// Vector length in bytes for HVX 128-byte mode
+#[cfg(all(target_arch = "hexagon", target_feature = "hvx-length128b"))]
+const VLEN: usize = 128;
+
+/// Vector length in bytes for HVX 64-byte mode
+#[cfg(all(target_arch = "hexagon", not(target_feature = "hvx-length128b")))]
+const VLEN: usize = 64;
+
+/// Vertical 1-2-1 filter pass using byte averaging
+///
+/// Computes: dst[x] = avg(avg(row_above[x], row_below[x]), center[x])
+///                   ≈ (row_above[x] + 2*center[x] + row_below[x]) / 4
+///
+/// # Safety
+///
+/// - `src` must point to the center row with valid data at -stride and +stride
+/// - `dst` must point to a valid output buffer for `width` bytes
+/// - `width` must be a multiple of VLEN
+/// - All pointers must be HVX-aligned (128-byte for 128B mode)
+#[cfg(target_arch = "hexagon")]
+#[target_feature(enable = "hvxv60")]
+unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) {
+    let inp0 = src.offset(-stride) as *const HvxVector;
+    let inp1 = src as *const HvxVector;
+    let inp2 = src.offset(stride) as *const HvxVector;
+    let outp = dst as *mut HvxVector;
+
+    let n_chunks = width / VLEN;
+    for i in 0..n_chunks {
+        let above = *inp0.add(i);
+        let center = *inp1.add(i);
+        let below = *inp2.add(i);
+
+        // avg(above, below) ≈ (above + below) / 2
+        let avg_ab = q6_vub_vavg_vubvub_rnd(above, below);
+        // avg(avg_ab, center) ≈ ((above + below)/2 + center) / 2
+        //                     ≈ (above + 2*center + below) / 4
+        let result = q6_vub_vavg_vubvub_rnd(avg_ab, center);
+
+        *outp.add(i) = result;
+    }
+}
+
+/// Horizontal 1-2-1 filter pass using byte averaging with vector alignment
+///
+/// Computes: dst[x] = avg(avg(src[x-1], src[x+1]), src[x])
+///                   ≈ (src[x-1] + 2*src[x] + src[x+1]) / 4
+///
+/// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access.
+///
+/// # Safety
+///
+/// - `src` and `dst` must point to valid buffers of `width` bytes
+/// - `width` must be a multiple of VLEN
+/// - All pointers must be HVX-aligned
+#[cfg(target_arch = "hexagon")]
+#[target_feature(enable = "hvxv60")]
+unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
+    let inp = src as *const HvxVector;
+    let outp = dst as *mut HvxVector;
+
+    let n_chunks = width / VLEN;
+    let mut prev = q6_v_vzero();
+
+    for i in 0..n_chunks {
+        let curr = *inp.add(i);
+        let next = if i + 1 < n_chunks {
+            *inp.add(i + 1)
+        } else {
+            q6_v_vzero()
+        };
+
+        // Left neighbor (x-1): shift curr right by 1 byte, filling from prev
+        // vlalign(curr, prev, 1) = { prev[VLEN-1], curr[0], curr[1], ..., curr[VLEN-2] }
+        let left = q6_v_vlalign_vvr(curr, prev, 1);
+
+        // Right neighbor (x+1): shift curr left by 1 byte, filling from next
+        // valign(next, curr, 1) = { curr[1], curr[2], ..., curr[VLEN-1], next[0] }
+        let right = q6_v_valign_vvr(next, curr, 1);
+
+        // avg(left, right) ≈ (src[x-1] + src[x+1]) / 2
+        let avg_lr = q6_vub_vavg_vubvub_rnd(left, right);
+        // avg(avg_lr, curr) ≈ ((src[x-1] + src[x+1])/2 + src[x]) / 2
+        //                   ≈ (src[x-1] + 2*src[x] + src[x+1]) / 4
+        let result = q6_vub_vavg_vubvub_rnd(avg_lr, curr);
+
+        *outp.add(i) = result;
+
+        prev = curr;
+    }
+}
+
+/// Apply Gaussian 3x3 blur to an entire image using separable filtering
+///
+/// Two-pass approach:
+/// 1. Vertical pass: apply 1-2-1 filter across rows
+/// 2. Horizontal pass: apply 1-2-1 filter across columns
+///
+/// Combined effect: 3x3 Gaussian kernel [1 2 1; 2 4 2; 1 2 1] / 16
+///
+/// # Safety
+///
+/// - `src` and `dst` must point to valid image buffers of `stride * height` bytes
+/// - `tmp` must point to a valid temporary buffer of `width` bytes, HVX-aligned
+/// - `width` must be a multiple of VLEN and >= VLEN
+/// - `stride` must be >= `width`
+/// - All buffers must be HVX-aligned (128-byte for 128B mode)
+#[cfg(target_arch = "hexagon")]
+#[target_feature(enable = "hvxv60")]
+pub unsafe fn gaussian3x3u8(
+    src: *const u8,
+    stride: usize,
+    width: usize,
+    height: usize,
+    dst: *mut u8,
+    tmp: *mut u8,
+) {
+    let stride_i = stride as isize;
+
+    // Process interior rows (skip first and last which lack vertical neighbors)
+    for y in 1..height - 1 {
+        let row_src = src.offset(y as isize * stride_i);
+        let row_dst = dst.offset(y as isize * stride_i);
+
+        // Pass 1: vertical 1-2-1 into tmp
+        vertical_121_pass(row_src, stride_i, width, tmp);
+
+        // Pass 2: horizontal 1-2-1 from tmp into dst
+        horizontal_121_pass(tmp, width, row_dst);
+    }
+}
+
+/// Scalar reference implementation of Gaussian 3x3 blur for verification
+///
+/// Applies the exact 3x3 Gaussian kernel:
+///     out[y][x] = (1*p[-1][-1] + 2*p[-1][0] + 1*p[-1][1] +
+///                  2*p[ 0][-1] + 4*p[ 0][0] + 2*p[ 0][1] +
+///                  1*p[ 1][-1] + 2*p[ 1][0] + 1*p[ 1][1] + 8) / 16
+fn gaussian3x3u8_scalar(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) {
+    for y in 1..height - 1 {
+        for x in 1..width - 1 {
+            let sum = src[(y - 1) * stride + (x - 1)] as u32
+                + src[(y - 1) * stride + x] as u32 * 2
+                + src[(y - 1) * stride + (x + 1)] as u32
+                + src[y * stride + (x - 1)] as u32 * 2
+                + src[y * stride + x] as u32 * 4
+                + src[y * stride + (x + 1)] as u32 * 2
+                + src[(y + 1) * stride + (x - 1)] as u32
+                + src[(y + 1) * stride + x] as u32 * 2
+                + src[(y + 1) * stride + (x + 1)] as u32;
+            // Divide by 16 with rounding, saturate to u8
+            dst[y * stride + x] = ((sum + 8) >> 4).min(255) as u8;
+        }
+    }
+}
+
+/// Scalar approximation matching the HVX byte-averaging approach
+///
+/// This matches the HVX implementation's behavior:
+/// - Vertical: avg_rnd(avg_rnd(above, below), center)
+/// - Horizontal: avg_rnd(avg_rnd(left, right), center)
+/// where avg_rnd(a, b) = (a + b + 1) / 2
+fn gaussian3x3u8_scalar_approx(
+    src: &[u8],
+    stride: usize,
+    width: usize,
+    height: usize,
+    dst: &mut [u8],
+) {
+    // Temporary buffer for vertical pass output
+    let mut tmp = vec![0u8; width * height];
+
+    // Vertical pass: 1-2-1 using rounding average
+    for y in 1..height - 1 {
+        for x in 0..width {
+            let above = src[(y - 1) * stride + x] as u16;
+            let center = src[y * stride + x] as u16;
+            let below = src[(y + 1) * stride + x] as u16;
+            let avg_ab = ((above + below + 1) / 2) as u8;
+            tmp[y * width + x] = ((avg_ab as u16 + center + 1) / 2) as u8;
+        }
+    }
+
+    // Horizontal pass: 1-2-1 using rounding average
+    for y in 1..height - 1 {
+        for x in 1..width - 1 {
+            let left = tmp[y * width + (x - 1)] as u16;
+            let center = tmp[y * width + x] as u16;
+            let right = tmp[y * width + (x + 1)] as u16;
+            let avg_lr = ((left + right + 1) / 2) as u8;
+            dst[y * stride + x] = ((avg_lr as u16 + center + 1) / 2) as u8;
+        }
+    }
+}
+
+fn main() {
+    println!("HVX Gaussian 3x3 blur example");
+    println!("Separable filter using byte averaging (HvxVector only)");
+    println!();
+
+    #[cfg(not(target_arch = "hexagon"))]
+    {
+        const WIDTH: usize = 128;
+        const HEIGHT: usize = 16;
+
+        let mut src = vec![0u8; WIDTH * HEIGHT];
+        let mut dst_exact = vec![0u8; WIDTH * HEIGHT];
+        let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
+
+        // Create test pattern
+        for y in 0..HEIGHT {
+            for x in 0..WIDTH {
+                src[y * WIDTH + x] = ((x + y * 7) % 256) as u8;
+            }
+        }
+
+        // Run exact Gaussian
+        gaussian3x3u8_scalar(&src, WIDTH, WIDTH, HEIGHT, &mut dst_exact);
+
+        // Run approximate version (matches HVX behavior)
+        gaussian3x3u8_scalar_approx(&src, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
+
+        // Compare exact vs approximate
+        let mut max_diff = 0u8;
+        for y in 1..HEIGHT - 1 {
+            for x in 1..WIDTH - 1 {
+                let idx = y * WIDTH + x;
+                let diff = (dst_exact[idx] as i16 - dst_approx[idx] as i16).unsigned_abs() as u8;
+                if diff > max_diff {
+                    max_diff = diff;
+                }
+            }
+        }
+
+        println!("Scalar implementations completed.");
+        println!(
+            "Input sample  (row 2, cols 1..9): {:?}",
+            &src[2 * WIDTH + 1..2 * WIDTH + 9]
+        );
+        println!(
+            "Exact output  (row 2, cols 1..9): {:?}",
+            &dst_exact[2 * WIDTH + 1..2 * WIDTH + 9]
+        );
+        println!(
+            "Approx output (row 2, cols 1..9): {:?}",
+            &dst_approx[2 * WIDTH + 1..2 * WIDTH + 9]
+        );
+        println!("Max diff between exact and approx: {}", max_diff);
+    }
+
+    #[cfg(target_arch = "hexagon")]
+    {
+        const WIDTH: usize = 256; // Must be multiple of VLEN (128)
+        const HEIGHT: usize = 16;
+
+        // Aligned buffers for HVX
+        #[repr(align(128))]
+        struct AlignedBuf<const N: usize>([u8; N]);
+
+        let mut src = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
+        let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
+        let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]);
+        let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
+
+        // Create test pattern
+        for y in 0..HEIGHT {
+            for x in 0..WIDTH {
+                src.0[y * WIDTH + x] = ((x + y * 7) % 256) as u8;
+            }
+        }
+
+        // Run HVX version
+        unsafe {
+            gaussian3x3u8(
+                src.0.as_ptr(),
+                WIDTH,
+                WIDTH,
+                HEIGHT,
+                dst_hvx.0.as_mut_ptr(),
+                tmp.0.as_mut_ptr(),
+            );
+        }
+
+        // Run scalar approximate reference (should match HVX closely)
+        gaussian3x3u8_scalar_approx(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
+
+        // Compare results (skip edges)
+        let mut max_diff = 0u8;
+        let mut diff_count = 0usize;
+        for y in 1..HEIGHT - 1 {
+            for x in 1..WIDTH - 1 {
+                let idx = y * WIDTH + x;
+                let diff = (dst_hvx.0[idx] as i16 - dst_ref[idx] as i16).unsigned_abs() as u8;
+                if diff > max_diff {
+                    max_diff = diff;
+                }
+                if diff > 0 {
+                    diff_count += 1;
+                }
+            }
+        }
+
+        println!("HVX implementation completed.");
+        println!("Max difference from scalar reference: {}", max_diff);
+        println!("Pixels with any difference: {}", diff_count);
+        if max_diff <= 1 {
+            println!("Results match within rounding tolerance!");
+        } else {
+            println!("WARNING: Results differ more than expected.");
+        }
+    }
+}

From 1157c4d8782b0f0fdcd04854763dcd598fda9524 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Fri, 30 Jan 2026 19:19:41 -0600
Subject: [PATCH 138/326] Switched to 64b and 128b crate definitions

---
 crates/core_arch/src/hexagon/mod.rs           |   21 +-
 .../core_arch/src/hexagon/{hvx.rs => v128.rs} | 1019 +--
 crates/core_arch/src/hexagon/v64.rs           | 7489 +++++++++++++++++
 crates/stdarch-gen-hexagon/src/main.rs        |  250 +-
 examples/gaussian.rs                          |    6 +-
 5 files changed, 7661 insertions(+), 1124 deletions(-)
 rename crates/core_arch/src/hexagon/{hvx.rs => v128.rs} (82%)
 create mode 100644 crates/core_arch/src/hexagon/v64.rs

diff --git a/crates/core_arch/src/hexagon/mod.rs b/crates/core_arch/src/hexagon/mod.rs
index a9c53d6efe..c370f3da15 100644
--- a/crates/core_arch/src/hexagon/mod.rs
+++ b/crates/core_arch/src/hexagon/mod.rs
@@ -5,8 +5,25 @@
 //!
 //! HVX is a wide SIMD architecture designed for high-performance signal processing,
 //! machine learning, and image processing workloads.
+//!
+//! ## Vector Length Modes
+//!
+//! HVX supports two vector length modes:
+//! - 64-byte mode (512-bit vectors): Use the [`v64`] module
+//! - 128-byte mode (1024-bit vectors): Use the [`v128`] module
+//!
+//! Both modules are available unconditionally, but require the appropriate
+//! target features to actually use the intrinsics:
+//! - For 64-byte mode: `-C target-feature=+hvx-length64b`
+//! - For 128-byte mode: `-C target-feature=+hvx-length128b`
+//!
+//! Note that HVX v66 and later default to 128-byte mode, while earlier versions
+//! (v60-v65) default to 64-byte mode.
 
-mod hvx;
+/// HVX intrinsics for 64-byte vector mode (512-bit vectors)
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub mod v64;
 
+/// HVX intrinsics for 128-byte vector mode (1024-bit vectors)
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub use self::hvx::*;
+pub mod v128;
diff --git a/crates/core_arch/src/hexagon/hvx.rs b/crates/core_arch/src/hexagon/v128.rs
similarity index 82%
rename from crates/core_arch/src/hexagon/hvx.rs
rename to crates/core_arch/src/hexagon/v128.rs
index 24d42ea1fc..ef7ff4205c 100644
--- a/crates/core_arch/src/hexagon/hvx.rs
+++ b/crates/core_arch/src/hexagon/v128.rs
@@ -1,22 +1,19 @@
-//! Hexagon HVX intrinsics
+//! Hexagon HVX 128-byte vector mode intrinsics
+//!
+//! This module provides intrinsics for the Hexagon Vector Extensions (HVX)
+//! in 128-byte vector mode (1024-bit vectors).
 //!
-//! This module provides intrinsics for the Hexagon Vector Extensions (HVX).
 //! HVX is a wide vector extension designed for high-performance signal processing.
 //! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61)
 //!
 //! ## Vector Types
 //!
-//! HVX supports different vector lengths depending on the configuration:
-//! - 128-byte mode: `HvxVector` is 1024 bits (128 bytes)
-//! - 64-byte mode: `HvxVector` is 512 bits (64 bytes)
-//!
-//! This implementation targets 128-byte mode by default. To change the vector
-//! length mode, use the appropriate target feature when compiling:
-//! - For 128-byte mode: `-C target-feature=+hvx-length128b`
-//! - For 64-byte mode: `-C target-feature=+hvx-length64b`
+//! In 128-byte mode:
+//! - `HvxVector` is 1024 bits (128 bytes) containing 32 x 32-bit values
+//! - `HvxVectorPair` is 2048 bits (256 bytes)
+//! - `HvxVectorPred` is 1024 bits (128 bytes) for predicate operations
 //!
-//! Note that HVX v66 and later default to 128-byte mode, while earlier versions
-//! default to 64-byte mode.
+//! To use this module, compile with `-C target-feature=+hvx-length128b`.
 //!
 //! ## Architecture Versions
 //!
@@ -30,7 +27,6 @@
 //! - HVX v69: `-C target-feature=+hvxv69`
 //! - HVX v73: `-C target-feature=+hvxv73`
 //! - HVX v79: `-C target-feature=+hvxv79`
-//! - HVX v81: `-C target-feature=+hvxv81`
 //!
 //! Each version includes all features from previous versions.
 
@@ -41,9 +37,7 @@ use stdarch_test::assert_instr;
 
 use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor};
 
-// HVX type definitions for 128-byte vector mode (default for v66+)
-// Use -C target-feature=+hvx-length128b to enable
-#[cfg(target_feature = "hvx-length128b")]
+// HVX type definitions for 128-byte vector mode
 types! {
     #![unstable(feature = "stdarch_hexagon", issue = "151523")]
 
@@ -65,32 +59,7 @@ types! {
     pub struct HvxVectorPred(32 x i32);
 }
 
-// HVX type definitions for 64-byte vector mode (default for v60-v65)
-// Use -C target-feature=+hvx-length64b to enable, or omit hvx-length128b
-#[cfg(not(target_feature = "hvx-length128b"))]
-types! {
-    #![unstable(feature = "stdarch_hexagon", issue = "151523")]
-
-    /// HVX vector type (512 bits / 64 bytes)
-    ///
-    /// This type represents a single HVX vector register containing 16 x 32-bit values.
-    pub struct HvxVector(16 x i32);
-
-    /// HVX vector pair type (1024 bits / 128 bytes)
-    ///
-    /// This type represents a pair of HVX vector registers, often used for
-    /// operations that produce double-width results.
-    pub struct HvxVectorPair(32 x i32);
-
-    /// HVX vector predicate type (512 bits / 64 bytes)
-    ///
-    /// This type represents a predicate vector used for conditional operations.
-    /// Each bit corresponds to a lane in the vector.
-    pub struct HvxVectorPred(16 x i32);
-}
-
 // LLVM intrinsic declarations for 128-byte vector mode
-#[cfg(target_feature = "hvx-length128b")]
 #[allow(improper_ctypes)]
 unsafe extern "unadjusted" {
     #[link_name = "llvm.hexagon.V6.extractw.128B"]
@@ -1057,974 +1026,6 @@ unsafe extern "unadjusted" {
     fn vzh(_: HvxVector) -> HvxVectorPair;
 }
 
-// LLVM intrinsic declarations for 64-byte vector mode
-#[cfg(not(target_feature = "hvx-length128b"))]
-#[allow(improper_ctypes)]
-unsafe extern "unadjusted" {
-    #[link_name = "llvm.hexagon.V6.extractw"]
-    fn extractw(_: HvxVector, _: i32) -> i32;
-    #[link_name = "llvm.hexagon.V6.get.qfext"]
-    fn get_qfext(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.hi"]
-    fn hi(_: HvxVectorPair) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.lo"]
-    fn lo(_: HvxVectorPair) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.lvsplatb"]
-    fn lvsplatb(_: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.lvsplath"]
-    fn lvsplath(_: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.lvsplatw"]
-    fn lvsplatw(_: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.and"]
-    fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.and.n"]
-    fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.not"]
-    fn pred_not(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.or"]
-    fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.or.n"]
-    fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.scalar2"]
-    fn pred_scalar2(_: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.scalar2v2"]
-    fn pred_scalar2v2(_: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.pred.xor"]
-    fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.set.qfext"]
-    fn set_qfext(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.shuffeqh"]
-    fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.shuffeqw"]
-    fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.v6mpyhubs10"]
-    fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx"]
-    fn v6mpyhubs10_vxx(
-        _: HvxVectorPair,
-        _: HvxVectorPair,
-        _: HvxVectorPair,
-        _: i32,
-    ) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.v6mpyvubs10"]
-    fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx"]
-    fn v6mpyvubs10_vxx(
-        _: HvxVectorPair,
-        _: HvxVectorPair,
-        _: HvxVectorPair,
-        _: i32,
-    ) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai"]
-    fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai"]
-    fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai"]
-    fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai"]
-    fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vabs.f8"]
-    fn vabs_f8(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabs.hf"]
-    fn vabs_hf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabs.sf"]
-    fn vabs_sf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsb"]
-    fn vabsb(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsb.sat"]
-    fn vabsb_sat(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsdiffh"]
-    fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsdiffub"]
-    fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsdiffuh"]
-    fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsdiffw"]
-    fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsh"]
-    fn vabsh(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsh.sat"]
-    fn vabsh_sat(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsw"]
-    fn vabsw(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vabsw.sat"]
-    fn vabsw_sat(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.hf"]
-    fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.hf.hf"]
-    fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.qf16"]
-    fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.qf16.mix"]
-    fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.qf32"]
-    fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.qf32.mix"]
-    fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.sf"]
-    fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadd.sf.hf"]
-    fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vadd.sf.sf"]
-    fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddb"]
-    fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddb.dv"]
-    fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddbnq"]
-    fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddbq"]
-    fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddbsat"]
-    fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddbsat.dv"]
-    fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddcarrysat"]
-    fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddclbh"]
-    fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddclbw"]
-    fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddh"]
-    fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddh.dv"]
-    fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddhnq"]
-    fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddhq"]
-    fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddhsat"]
-    fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddhsat.dv"]
-    fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddhw"]
-    fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddhw.acc"]
-    fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddubh"]
-    fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddubh.acc"]
-    fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddubsat"]
-    fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddubsat.dv"]
-    fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddububb.sat"]
-    fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadduhsat"]
-    fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadduhsat.dv"]
-    fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vadduhw"]
-    fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vadduhw.acc"]
-    fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vadduwsat"]
-    fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vadduwsat.dv"]
-    fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddw"]
-    fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddw.dv"]
-    fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vaddwnq"]
-    fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddwq"]
-    fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddwsat"]
-    fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaddwsat.dv"]
-    fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.valignb"]
-    fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.valignbi"]
-    fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vand"]
-    fn vand(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandnqrt"]
-    fn vandnqrt(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandnqrt.acc"]
-    fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandqrt"]
-    fn vandqrt(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandqrt.acc"]
-    fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandvnqv"]
-    fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandvqv"]
-    fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandvrt"]
-    fn vandvrt(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vandvrt.acc"]
-    fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaslh"]
-    fn vaslh(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaslh.acc"]
-    fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaslhv"]
-    fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaslw"]
-    fn vaslw(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaslw.acc"]
-    fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vaslwv"]
-    fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasr.into"]
-    fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vasrh"]
-    fn vasrh(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrh.acc"]
-    fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrhbrndsat"]
-    fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrhbsat"]
-    fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrhubrndsat"]
-    fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrhubsat"]
-    fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrhv"]
-    fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasruhubrndsat"]
-    fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasruhubsat"]
-    fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasruwuhrndsat"]
-    fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasruwuhsat"]
-    fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat"]
-    fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrvuhubsat"]
-    fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat"]
-    fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrvwuhsat"]
-    fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrw"]
-    fn vasrw(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrw.acc"]
-    fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrwh"]
-    fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrwhrndsat"]
-    fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrwhsat"]
-    fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrwuhrndsat"]
-    fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrwuhsat"]
-    fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vasrwv"]
-    fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vassign"]
-    fn vassign(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vassign.fp"]
-    fn vassign_fp(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vassignp"]
-    fn vassignp(_: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vavgb"]
-    fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavgbrnd"]
-    fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavgh"]
-    fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavghrnd"]
-    fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavgub"]
-    fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavgubrnd"]
-    fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavguh"]
-    fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavguhrnd"]
-    fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavguw"]
-    fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavguwrnd"]
-    fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavgw"]
-    fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vavgwrnd"]
-    fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcl0h"]
-    fn vcl0h(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcl0w"]
-    fn vcl0w(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcombine"]
-    fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vconv.h.hf"]
-    fn vconv_h_hf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vconv.hf.h"]
-    fn vconv_hf_h(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vconv.hf.qf16"]
-    fn vconv_hf_qf16(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vconv.hf.qf32"]
-    fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vconv.sf.qf32"]
-    fn vconv_sf_qf32(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vconv.sf.w"]
-    fn vconv_sf_w(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vconv.w.sf"]
-    fn vconv_w_sf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt2.hf.b"]
-    fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub"]
-    fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vcvt.b.hf"]
-    fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt.h.hf"]
-    fn vcvt_h_hf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt.hf.b"]
-    fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vcvt.hf.f8"]
-    fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vcvt.hf.h"]
-    fn vcvt_hf_h(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt.hf.sf"]
-    fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt.hf.ub"]
-    fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vcvt.hf.uh"]
-    fn vcvt_hf_uh(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt.sf.hf"]
-    fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vcvt.ub.hf"]
-    fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vcvt.uh.hf"]
-    fn vcvt_uh_hf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vd0"]
-    fn vd0() -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdd0"]
-    fn vdd0() -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdealb"]
-    fn vdealb(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdealb4w"]
-    fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdealh"]
-    fn vdealh(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdealvdd"]
-    fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdelta"]
-    fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf"]
-    fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc"]
-    fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpybus"]
-    fn vdmpybus(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpybus.acc"]
-    fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpybus.dv"]
-    fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc"]
-    fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdmpyhb"]
-    fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhb.acc"]
-    fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv"]
-    fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc"]
-    fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdmpyhisat"]
-    fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc"]
-    fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhsat"]
-    fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc"]
-    fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat"]
-    fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc"]
-    fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhsusat"]
-    fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc"]
-    fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhvsat"]
-    fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc"]
-    fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vdsaduh"]
-    fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vdsaduh.acc"]
-    fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.veqb"]
-    fn veqb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqb.and"]
-    fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqb.or"]
-    fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqb.xor"]
-    fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqh"]
-    fn veqh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqh.and"]
-    fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqh.or"]
-    fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqh.xor"]
-    fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqw"]
-    fn veqw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqw.and"]
-    fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqw.or"]
-    fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.veqw.xor"]
-    fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfmax.f8"]
-    fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfmax.hf"]
-    fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfmax.sf"]
-    fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfmin.f8"]
-    fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfmin.hf"]
-    fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfmin.sf"]
-    fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfneg.f8"]
-    fn vfneg_f8(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfneg.hf"]
-    fn vfneg_hf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vfneg.sf"]
-    fn vfneg_sf(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgathermh"]
-    fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vgathermhq"]
-    fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vgathermhw"]
-    fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
-    #[link_name = "llvm.hexagon.V6.vgathermhwq"]
-    fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
-    #[link_name = "llvm.hexagon.V6.vgathermw"]
-    fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vgathermwq"]
-    fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vgtb"]
-    fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtb.and"]
-    fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtb.or"]
-    fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtb.xor"]
-    fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgth"]
-    fn vgth(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgth.and"]
-    fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgth.or"]
-    fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgth.xor"]
-    fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgthf"]
-    fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgthf.and"]
-    fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgthf.or"]
-    fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgthf.xor"]
-    fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtsf"]
-    fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtsf.and"]
-    fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtsf.or"]
-    fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtsf.xor"]
-    fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtub"]
-    fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtub.and"]
-    fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtub.or"]
-    fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtub.xor"]
-    fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuh"]
-    fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuh.and"]
-    fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuh.or"]
-    fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuh.xor"]
-    fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuw"]
-    fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuw.and"]
-    fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuw.or"]
-    fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtuw.xor"]
-    fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtw"]
-    fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtw.and"]
-    fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtw.or"]
-    fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vgtw.xor"]
-    fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vinsertwr"]
-    fn vinsertwr(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlalignb"]
-    fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlalignbi"]
-    fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlsrb"]
-    fn vlsrb(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlsrh"]
-    fn vlsrh(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlsrhv"]
-    fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlsrw"]
-    fn vlsrw(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlsrwv"]
-    fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlutvvb"]
-    fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlutvvb.nm"]
-    fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlutvvb.oracc"]
-    fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlutvvb.oracci"]
-    fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlutvvbi"]
-    fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vlutvwh"]
-    fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vlutvwh.nm"]
-    fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vlutvwh.oracc"]
-    fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vlutvwh.oracci"]
-    fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vlutvwhi"]
-    fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmax.hf"]
-    fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmax.sf"]
-    fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmaxb"]
-    fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmaxh"]
-    fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmaxub"]
-    fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmaxuh"]
-    fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmaxw"]
-    fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmin.hf"]
-    fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmin.sf"]
-    fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vminb"]
-    fn vminb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vminh"]
-    fn vminh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vminub"]
-    fn vminub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vminuh"]
-    fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vminw"]
-    fn vminw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpabus"]
-    fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpabus.acc"]
-    fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpabusv"]
-    fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpabuu"]
-    fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpabuu.acc"]
-    fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpabuuv"]
-    fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpahb"]
-    fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpahb.acc"]
-    fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpauhb"]
-    fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpauhb.acc"]
-    fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf"]
-    fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc"]
-    fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf16"]
-    fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf"]
-    fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf"]
-    fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf32"]
-    fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf"]
-    fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf"]
-    fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16"]
-    fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf"]
-    fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf"]
-    fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc"]
-    fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpy.sf.sf"]
-    fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpybus"]
-    fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpybus.acc"]
-    fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpybusv"]
-    fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpybusv.acc"]
-    fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpybv"]
-    fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpybv.acc"]
-    fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyewuh"]
-    fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyewuh.64"]
-    fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyh"]
-    fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyh.acc"]
-    fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyhsat.acc"]
-    fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyhsrs"]
-    fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyhss"]
-    fn vmpyhss(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyhus"]
-    fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyhus.acc"]
-    fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyhv"]
-    fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyhv.acc"]
-    fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyhvsrs"]
-    fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyieoh"]
-    fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiewh.acc"]
-    fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiewuh"]
-    fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc"]
-    fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyih"]
-    fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyih.acc"]
-    fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyihb"]
-    fn vmpyihb(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyihb.acc"]
-    fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiowh"]
-    fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiwb"]
-    fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiwb.acc"]
-    fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiwh"]
-    fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiwh.acc"]
-    fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiwub"]
-    fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyiwub.acc"]
-    fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyowh"]
-    fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc"]
-    fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd"]
-    fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc"]
-    fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyowh.sacc"]
-    fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyub"]
-    fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyub.acc"]
-    fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyubv"]
-    fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyubv.acc"]
-    fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyuh"]
-    fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyuh.acc"]
-    fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyuhe"]
-    fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyuhe.acc"]
-    fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmpyuhv"]
-    fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyuhv.acc"]
-    fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vmpyuhvs"]
-    fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vmux"]
-    fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnavgb"]
-    fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnavgh"]
-    fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnavgub"]
-    fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnavgw"]
-    fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnormamth"]
-    fn vnormamth(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnormamtw"]
-    fn vnormamtw(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vnot"]
-    fn vnot(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vor"]
-    fn vor(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackeb"]
-    fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackeh"]
-    fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackhb.sat"]
-    fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackhub.sat"]
-    fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackob"]
-    fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackoh"]
-    fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackwh.sat"]
-    fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpackwuh.sat"]
-    fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vpopcounth"]
-    fn vpopcounth(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vprefixqb"]
-    fn vprefixqb(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vprefixqh"]
-    fn vprefixqh(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vprefixqw"]
-    fn vprefixqw(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrdelta"]
-    fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpybus"]
-    fn vrmpybus(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpybus.acc"]
-    fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpybusi"]
-    fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vrmpybusi.acc"]
-    fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vrmpybusv"]
-    fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpybusv.acc"]
-    fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpybv"]
-    fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpybv.acc"]
-    fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpyub"]
-    fn vrmpyub(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpyub.acc"]
-    fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpyubi"]
-    fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vrmpyubi.acc"]
-    fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vrmpyubv"]
-    fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrmpyubv.acc"]
-    fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vror"]
-    fn vror(_: HvxVector, _: i32) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrotr"]
-    fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vroundhb"]
-    fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vroundhub"]
-    fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrounduhub"]
-    fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrounduwuh"]
-    fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vroundwh"]
-    fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vroundwuh"]
-    fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vrsadubi"]
-    fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vrsadubi.acc"]
-    fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsatdw"]
-    fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsathub"]
-    fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsatuwuh"]
-    fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsatwh"]
-    fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsb"]
-    fn vsb(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vscattermh"]
-    fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermh.add"]
-    fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermhq"]
-    fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermhw"]
-    fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermhw.add"]
-    fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermhwq"]
-    fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermw"]
-    fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermw.add"]
-    fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vscattermwq"]
-    fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
-    #[link_name = "llvm.hexagon.V6.vsh"]
-    fn vsh(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vshufeh"]
-    fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vshuffb"]
-    fn vshuffb(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vshuffeb"]
-    fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vshuffh"]
-    fn vshuffh(_: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vshuffob"]
-    fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vshuffvdd"]
-    fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vshufoeb"]
-    fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vshufoeh"]
-    fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vshufoh"]
-    fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.hf"]
-    fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.hf.hf"]
-    fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.qf16"]
-    fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.qf16.mix"]
-    fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.qf32"]
-    fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.qf32.mix"]
-    fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.sf"]
-    fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsub.sf.hf"]
-    fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsub.sf.sf"]
-    fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubb"]
-    fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubb.dv"]
-    fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubbnq"]
-    fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubbq"]
-    fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubbsat"]
-    fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubbsat.dv"]
-    fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubh"]
-    fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubh.dv"]
-    fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubhnq"]
-    fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubhq"]
-    fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubhsat"]
-    fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubhsat.dv"]
-    fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubhw"]
-    fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsububh"]
-    fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsububsat"]
-    fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsububsat.dv"]
-    fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubububb.sat"]
-    fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubuhsat"]
-    fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubuhsat.dv"]
-    fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubuhw"]
-    fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubuwsat"]
-    fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubuwsat.dv"]
-    fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubw"]
-    fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubw.dv"]
-    fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vsubwnq"]
-    fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubwq"]
-    fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubwsat"]
-    fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vsubwsat.dv"]
-    fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vswap"]
-    fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vtmpyb"]
-    fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vtmpyb.acc"]
-    fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vtmpybus"]
-    fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vtmpybus.acc"]
-    fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vtmpyhb"]
-    fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vtmpyhb.acc"]
-    fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vunpackb"]
-    fn vunpackb(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vunpackh"]
-    fn vunpackh(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vunpackob"]
-    fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vunpackoh"]
-    fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vunpackub"]
-    fn vunpackub(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vunpackuh"]
-    fn vunpackuh(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vxor"]
-    fn vxor(_: HvxVector, _: HvxVector) -> HvxVector;
-    #[link_name = "llvm.hexagon.V6.vzb"]
-    fn vzb(_: HvxVector) -> HvxVectorPair;
-    #[link_name = "llvm.hexagon.V6.vzh"]
-    fn vzh(_: HvxVector) -> HvxVectorPair;
-}
-
 /// `Rd32=vextract(Vu32,Rs32)`
 ///
 /// Instruction Type: LD
diff --git a/crates/core_arch/src/hexagon/v64.rs b/crates/core_arch/src/hexagon/v64.rs
new file mode 100644
index 0000000000..023a8711d2
--- /dev/null
+++ b/crates/core_arch/src/hexagon/v64.rs
@@ -0,0 +1,7489 @@
+//! Hexagon HVX 64-byte vector mode intrinsics
+//!
+//! This module provides intrinsics for the Hexagon Vector Extensions (HVX)
+//! in 64-byte vector mode (512-bit vectors).
+//!
+//! HVX is a wide vector extension designed for high-performance signal processing.
+//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61)
+//!
+//! ## Vector Types
+//!
+//! In 64-byte mode:
+//! - `HvxVector` is 512 bits (64 bytes) containing 16 x 32-bit values
+//! - `HvxVectorPair` is 1024 bits (128 bytes)
+//! - `HvxVectorPred` is 512 bits (64 bytes) for predicate operations
+//!
+//! To use this module, compile with `-C target-feature=+hvx-length64b`.
+//!
+//! ## Architecture Versions
+//!
+//! Different intrinsics require different HVX architecture versions. Use the
+//! appropriate target feature to enable the required version:
+//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations)
+//! - HVX v62: `-C target-feature=+hvxv62`
+//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support)
+//! - HVX v66: `-C target-feature=+hvxv66`
+//! - HVX v68: `-C target-feature=+hvxv68`
+//! - HVX v69: `-C target-feature=+hvxv69`
+//! - HVX v73: `-C target-feature=+hvxv73`
+//! - HVX v79: `-C target-feature=+hvxv79`
+//!
+//! Each version includes all features from previous versions.
+
+#![allow(non_camel_case_types)]
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor};
+
+// HVX type definitions for 64-byte vector mode
+types! {
+    #![unstable(feature = "stdarch_hexagon", issue = "151523")]
+
+    /// HVX vector type (512 bits / 64 bytes)
+    ///
+    /// This type represents a single HVX vector register containing 16 x 32-bit values.
+    pub struct HvxVector(16 x i32);
+
+    /// HVX vector pair type (1024 bits / 128 bytes)
+    ///
+    /// This type represents a pair of HVX vector registers, often used for
+    /// operations that produce double-width results.
+    pub struct HvxVectorPair(32 x i32);
+
+    /// HVX vector predicate type (512 bits / 64 bytes)
+    ///
+    /// This type represents a predicate vector used for conditional operations.
+    /// Each bit corresponds to a lane in the vector.
+    pub struct HvxVectorPred(16 x i32);
+}
+
+// LLVM intrinsic declarations for 64-byte vector mode
+#[allow(improper_ctypes)]
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.hexagon.V6.extractw"]
+    fn extractw(_: HvxVector, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.V6.get.qfext"]
+    fn get_qfext(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.hi"]
+    fn hi(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lo"]
+    fn lo(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplatb"]
+    fn lvsplatb(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplath"]
+    fn lvsplath(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.lvsplatw"]
+    fn lvsplatw(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.and"]
+    fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.and.n"]
+    fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.not"]
+    fn pred_not(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.or"]
+    fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.or.n"]
+    fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.scalar2"]
+    fn pred_scalar2(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.scalar2v2"]
+    fn pred_scalar2v2(_: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.pred.xor"]
+    fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.set.qfext"]
+    fn set_qfext(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.shuffeqh"]
+    fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.shuffeqw"]
+    fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.v6mpyhubs10"]
+    fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx"]
+    fn v6mpyhubs10_vxx(
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: i32,
+    ) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyvubs10"]
+    fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx"]
+    fn v6mpyvubs10_vxx(
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: HvxVectorPair,
+        _: i32,
+    ) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai"]
+    fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai"]
+    fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai"]
+    fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai"]
+    fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vabs.f8"]
+    fn vabs_f8(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabs.hf"]
+    fn vabs_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabs.sf"]
+    fn vabs_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsb"]
+    fn vabsb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsb.sat"]
+    fn vabsb_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffh"]
+    fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffub"]
+    fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffuh"]
+    fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsdiffw"]
+    fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsh"]
+    fn vabsh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsh.sat"]
+    fn vabsh_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsw"]
+    fn vabsw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vabsw.sat"]
+    fn vabsw_sat(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.hf"]
+    fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.hf.hf"]
+    fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf16"]
+    fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf16.mix"]
+    fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf32"]
+    fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.qf32.mix"]
+    fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.sf"]
+    fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.hf"]
+    fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadd.sf.sf"]
+    fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddb"]
+    fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddb.dv"]
+    fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddbnq"]
+    fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbq"]
+    fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbsat"]
+    fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddbsat.dv"]
+    fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddcarrysat"]
+    fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddclbh"]
+    fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddclbw"]
+    fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddh"]
+    fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddh.dv"]
+    fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhnq"]
+    fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhq"]
+    fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhsat"]
+    fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddhsat.dv"]
+    fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhw"]
+    fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddhw.acc"]
+    fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubh"]
+    fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubh.acc"]
+    fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddubsat"]
+    fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddubsat.dv"]
+    fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddububb.sat"]
+    fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduhsat"]
+    fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduhsat.dv"]
+    fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduhw"]
+    fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduhw.acc"]
+    fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vadduwsat"]
+    fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vadduwsat.dv"]
+    fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddw"]
+    fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddw.dv"]
+    fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vaddwnq"]
+    fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwq"]
+    fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwsat"]
+    fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaddwsat.dv"]
+    fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.valignb"]
+    fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.valignbi"]
+    fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vand"]
+    fn vand(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandnqrt"]
+    fn vandnqrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandnqrt.acc"]
+    fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandqrt"]
+    fn vandqrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandqrt.acc"]
+    fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvnqv"]
+    fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvqv"]
+    fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvrt"]
+    fn vandvrt(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vandvrt.acc"]
+    fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslh"]
+    fn vaslh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslh.acc"]
+    fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslhv"]
+    fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslw"]
+    fn vaslw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslw.acc"]
+    fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vaslwv"]
+    fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasr.into"]
+    fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vasrh"]
+    fn vasrh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrh.acc"]
+    fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhbrndsat"]
+    fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhbsat"]
+    fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhubrndsat"]
+    fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhubsat"]
+    fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrhv"]
+    fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruhubrndsat"]
+    fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruhubsat"]
+    fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruwuhrndsat"]
+    fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasruwuhsat"]
+    fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat"]
+    fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvuhubsat"]
+    fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat"]
+    fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrvwuhsat"]
+    fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrw"]
+    fn vasrw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrw.acc"]
+    fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwh"]
+    fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwhrndsat"]
+    fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwhsat"]
+    fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwuhrndsat"]
+    fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwuhsat"]
+    fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vasrwv"]
+    fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassign"]
+    fn vassign(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassign.fp"]
+    fn vassign_fp(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vassignp"]
+    fn vassignp(_: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vavgb"]
+    fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgbrnd"]
+    fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgh"]
+    fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavghrnd"]
+    fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgub"]
+    fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgubrnd"]
+    fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguh"]
+    fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguhrnd"]
+    fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguw"]
+    fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavguwrnd"]
+    fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgw"]
+    fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vavgwrnd"]
+    fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcl0h"]
+    fn vcl0h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcl0w"]
+    fn vcl0w(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcombine"]
+    fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vconv.h.hf"]
+    fn vconv_h_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.h"]
+    fn vconv_hf_h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.qf16"]
+    fn vconv_hf_qf16(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.hf.qf32"]
+    fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.sf.qf32"]
+    fn vconv_sf_qf32(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.sf.w"]
+    fn vconv_sf_w(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vconv.w.sf"]
+    fn vconv_w_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt2.hf.b"]
+    fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub"]
+    fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.b.hf"]
+    fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.h.hf"]
+    fn vcvt_h_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.b"]
+    fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.f8"]
+    fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.h"]
+    fn vcvt_hf_h(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.sf"]
+    fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.ub"]
+    fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.hf.uh"]
+    fn vcvt_hf_uh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.sf.hf"]
+    fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vcvt.ub.hf"]
+    fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vcvt.uh.hf"]
+    fn vcvt_uh_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vd0"]
+    fn vd0() -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdd0"]
+    fn vdd0() -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdealb"]
+    fn vdealb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealb4w"]
+    fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealh"]
+    fn vdealh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdealvdd"]
+    fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdelta"]
+    fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf"]
+    fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc"]
+    fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus"]
+    fn vdmpybus(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.acc"]
+    fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.dv"]
+    fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc"]
+    fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb"]
+    fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.acc"]
+    fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv"]
+    fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc"]
+    fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdmpyhisat"]
+    fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc"]
+    fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsat"]
+    fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc"]
+    fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat"]
+    fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc"]
+    fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsusat"]
+    fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc"]
+    fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhvsat"]
+    fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc"]
+    fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vdsaduh"]
+    fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vdsaduh.acc"]
+    fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.veqb"]
+    fn veqb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.and"]
+    fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.or"]
+    fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqb.xor"]
+    fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh"]
+    fn veqh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.and"]
+    fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.or"]
+    fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqh.xor"]
+    fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw"]
+    fn veqw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.and"]
+    fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.or"]
+    fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.veqw.xor"]
+    fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.f8"]
+    fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.hf"]
+    fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmax.sf"]
+    fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.f8"]
+    fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.hf"]
+    fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfmin.sf"]
+    fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.f8"]
+    fn vfneg_f8(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.hf"]
+    fn vfneg_hf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vfneg.sf"]
+    fn vfneg_sf(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgathermh"]
+    fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhq"]
+    fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhw"]
+    fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermhwq"]
+    fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermw"]
+    fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgathermwq"]
+    fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vgtb"]
+    fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.and"]
+    fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.or"]
+    fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtb.xor"]
+    fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth"]
+    fn vgth(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.and"]
+    fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.or"]
+    fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgth.xor"]
+    fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf"]
+    fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.and"]
+    fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.or"]
+    fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgthf.xor"]
+    fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf"]
+    fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.and"]
+    fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.or"]
+    fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtsf.xor"]
+    fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub"]
+    fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.and"]
+    fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.or"]
+    fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtub.xor"]
+    fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh"]
+    fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.and"]
+    fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.or"]
+    fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuh.xor"]
+    fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw"]
+    fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.and"]
+    fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.or"]
+    fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtuw.xor"]
+    fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw"]
+    fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.and"]
+    fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.or"]
+    fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vgtw.xor"]
+    fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vinsertwr"]
+    fn vinsertwr(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlalignb"]
+    fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlalignbi"]
+    fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrb"]
+    fn vlsrb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrh"]
+    fn vlsrh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrhv"]
+    fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrw"]
+    fn vlsrw(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlsrwv"]
+    fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb"]
+    fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.nm"]
+    fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.oracc"]
+    fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvb.oracci"]
+    fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvvbi"]
+    fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vlutvwh"]
+    fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.nm"]
+    fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.oracc"]
+    fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwh.oracci"]
+    fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vlutvwhi"]
+    fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmax.hf"]
+    fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmax.sf"]
+    fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxb"]
+    fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxh"]
+    fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxub"]
+    fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxuh"]
+    fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmaxw"]
+    fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmin.hf"]
+    fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmin.sf"]
+    fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminb"]
+    fn vminb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminh"]
+    fn vminh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminub"]
+    fn vminub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminuh"]
+    fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vminw"]
+    fn vminw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpabus"]
+    fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabus.acc"]
+    fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabusv"]
+    fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuu"]
+    fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuu.acc"]
+    fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpabuuv"]
+    fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpahb"]
+    fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpahb.acc"]
+    fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpauhb"]
+    fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpauhb.acc"]
+    fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf"]
+    fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc"]
+    fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16"]
+    fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf"]
+    fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf"]
+    fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32"]
+    fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf"]
+    fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf"]
+    fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16"]
+    fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf"]
+    fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf"]
+    fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc"]
+    fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpy.sf.sf"]
+    fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpybus"]
+    fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybus.acc"]
+    fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybusv"]
+    fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybusv.acc"]
+    fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybv"]
+    fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpybv.acc"]
+    fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyewuh"]
+    fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyewuh.64"]
+    fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyh"]
+    fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyh.acc"]
+    fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhsat.acc"]
+    fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhsrs"]
+    fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyhss"]
+    fn vmpyhss(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyhus"]
+    fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhus.acc"]
+    fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhv"]
+    fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhv.acc"]
+    fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyhvsrs"]
+    fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyieoh"]
+    fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewh.acc"]
+    fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewuh"]
+    fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc"]
+    fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyih"]
+    fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyih.acc"]
+    fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyihb"]
+    fn vmpyihb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyihb.acc"]
+    fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiowh"]
+    fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwb"]
+    fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwb.acc"]
+    fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwh"]
+    fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwh.acc"]
+    fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwub"]
+    fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyiwub.acc"]
+    fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh"]
+    fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc"]
+    fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd"]
+    fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc"]
+    fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyowh.sacc"]
+    fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyub"]
+    fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyub.acc"]
+    fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyubv"]
+    fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyubv.acc"]
+    fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuh"]
+    fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuh.acc"]
+    fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhe"]
+    fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyuhe.acc"]
+    fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmpyuhv"]
+    fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhv.acc"]
+    fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vmpyuhvs"]
+    fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vmux"]
+    fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgb"]
+    fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgh"]
+    fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgub"]
+    fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnavgw"]
+    fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnormamth"]
+    fn vnormamth(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnormamtw"]
+    fn vnormamtw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vnot"]
+    fn vnot(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vor"]
+    fn vor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackeb"]
+    fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackeh"]
+    fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackhb.sat"]
+    fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackhub.sat"]
+    fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackob"]
+    fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackoh"]
+    fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackwh.sat"]
+    fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpackwuh.sat"]
+    fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vpopcounth"]
+    fn vpopcounth(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqb"]
+    fn vprefixqb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqh"]
+    fn vprefixqh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vprefixqw"]
+    fn vprefixqw(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrdelta"]
+    fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybus"]
+    fn vrmpybus(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybus.acc"]
+    fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybusi"]
+    fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpybusi.acc"]
+    fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpybusv"]
+    fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybusv.acc"]
+    fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybv"]
+    fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpybv.acc"]
+    fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyub"]
+    fn vrmpyub(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyub.acc"]
+    fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyubi"]
+    fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpyubi.acc"]
+    fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrmpyubv"]
+    fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrmpyubv.acc"]
+    fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vror"]
+    fn vror(_: HvxVector, _: i32) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrotr"]
+    fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundhb"]
+    fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundhub"]
+    fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrounduhub"]
+    fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrounduwuh"]
+    fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundwh"]
+    fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vroundwuh"]
+    fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vrsadubi"]
+    fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vrsadubi.acc"]
+    fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsatdw"]
+    fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsathub"]
+    fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsatuwuh"]
+    fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsatwh"]
+    fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsb"]
+    fn vsb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vscattermh"]
+    fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermh.add"]
+    fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhq"]
+    fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhw"]
+    fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhw.add"]
+    fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermhwq"]
+    fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermw"]
+    fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermw.add"]
+    fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vscattermwq"]
+    fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> ();
+    #[link_name = "llvm.hexagon.V6.vsh"]
+    fn vsh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufeh"]
+    fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffb"]
+    fn vshuffb(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffeb"]
+    fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffh"]
+    fn vshuffh(_: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffob"]
+    fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vshuffvdd"]
+    fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoeb"]
+    fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoeh"]
+    fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vshufoh"]
+    fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.hf"]
+    fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.hf.hf"]
+    fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf16"]
+    fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf16.mix"]
+    fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf32"]
+    fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.qf32.mix"]
+    fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.sf"]
+    fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.hf"]
+    fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsub.sf.sf"]
+    fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubb"]
+    fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubb.dv"]
+    fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubbnq"]
+    fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbq"]
+    fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbsat"]
+    fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubbsat.dv"]
+    fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubh"]
+    fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubh.dv"]
+    fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubhnq"]
+    fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhq"]
+    fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhsat"]
+    fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubhsat.dv"]
+    fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubhw"]
+    fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsububh"]
+    fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsububsat"]
+    fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsububsat.dv"]
+    fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubububb.sat"]
+    fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuhsat"]
+    fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuhsat.dv"]
+    fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubuhw"]
+    fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubuwsat"]
+    fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubuwsat.dv"]
+    fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubw"]
+    fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubw.dv"]
+    fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vsubwnq"]
+    fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwq"]
+    fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwsat"]
+    fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vsubwsat.dv"]
+    fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vswap"]
+    fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyb"]
+    fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyb.acc"]
+    fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpybus"]
+    fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpybus.acc"]
+    fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyhb"]
+    fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vtmpyhb.acc"]
+    fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackb"]
+    fn vunpackb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackh"]
+    fn vunpackh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackob"]
+    fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackoh"]
+    fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackub"]
+    fn vunpackub(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vunpackuh"]
+    fn vunpackuh(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vxor"]
+    fn vxor(_: HvxVector, _: HvxVector) -> HvxVector;
+    #[link_name = "llvm.hexagon.V6.vzb"]
+    fn vzb(_: HvxVector) -> HvxVectorPair;
+    #[link_name = "llvm.hexagon.V6.vzh"]
+    fn vzh(_: HvxVector) -> HvxVectorPair;
+}
+
+/// `Rd32=vextract(Vu32,Rs32)`
+///
+/// Instruction Type: LD
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(extractw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 {
+    extractw(vu, rs)
+}
+
+/// `Vd32=hi(Vss32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(hi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector {
+    hi(vss)
+}
+
+/// `Vd32=lo(Vss32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(lo))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector {
+    lo(vss)
+}
+
+/// `Vd32=vsplat(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(lvsplatw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector {
+    lvsplatw(rt)
+}
+
+/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffh(vu, vv)
+}
+
+/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffub(vu, vv)
+}
+
+/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffuh(vu, vv)
+}
+
+/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsdiffw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vabsdiffw(vu, vv)
+}
+
+/// `Vd32.h=vabs(Vu32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector {
+    vabsh(vu)
+}
+
+/// `Vd32.h=vabs(Vu32.h):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsh_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector {
+    vabsh_sat(vu)
+}
+
+/// `Vd32.w=vabs(Vu32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector {
+    vabsw(vu)
+}
+
+/// `Vd32.w=vabs(Vu32.w):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vabsw_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector {
+    vabsw_sat(vu)
+}
+
+/// `Vd32.b=vadd(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddb(vu, vv)
+}
+
+/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddb_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddb_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vadd(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddh(vu, vv)
+}
+
+/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddh_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddh_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddhsat(vu, vv)
+}
+
+/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vadd(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vaddhw(vu, vv)
+}
+
+/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vaddubh(vu, vv)
+}
+
+/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddubsat(vu, vv)
+}
+
+/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddubsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddubsat_dv(vuu, vvv)
+}
+
+/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vadduhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadduhsat(vu, vv)
+}
+
+/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vadduhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vadduhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vadduhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vadduhw(vu, vv)
+}
+
+/// `Vd32.w=vadd(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_add(vu, vv)
+}
+
+/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddw_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddw_dv(vuu, vvv)
+}
+
+/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddwsat(vu, vv)
+}
+
+/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaddwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddwsat_dv(vuu, vvv)
+}
+
+/// `Vd32=valign(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(valignb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    valignb(vu, vv, rt)
+}
+
+/// `Vd32=valign(Vu32,Vv32,#u3)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(valignbi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+    valignbi(vu, vv, iu3)
+}
+
+/// `Vd32=vand(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vand))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_and(vu, vv)
+}
+
+/// `Vd32.h=vasl(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+    vaslh(vu, rt)
+}
+
+/// `Vd32.h=vasl(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaslhv(vu, vv)
+}
+
+/// `Vd32.w=vasl(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+    vaslw(vu, rt)
+}
+
+/// `Vx32.w+=vasl(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vaslw_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vasl(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vaslwv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaslwv(vu, vv)
+}
+
+/// `Vd32.h=vasr(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+    vasrh(vu, rt)
+}
+
+/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhbrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhbrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhubrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhubrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhubsat(vu, vv, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vasrhv(vu, vv)
+}
+
+/// `Vd32.w=vasr(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+    vasrw(vu, rt)
+}
+
+/// `Vx32.w+=vasr(Vu32.w,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vasrw_acc(vx, vu, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwh(vu, vv, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwhrndsat(vu, vv, rt)
+}
+
+/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwhsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwuhsat(vu, vv, rt)
+}
+
+/// `Vd32.w=vasr(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vasrwv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vasrwv(vu, vv)
+}
+
+/// `Vd32=Vu32`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vassign))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector {
+    vassign(vu)
+}
+
+/// `Vdd32=Vuu32`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vassignp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair {
+    vassignp(vuu)
+}
+
+/// `Vd32.h=vavg(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgh(vu, vv)
+}
+
+/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavghrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavghrnd(vu, vv)
+}
+
+/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgub(vu, vv)
+}
+
+/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgubrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgubrnd(vu, vv)
+}
+
+/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavguh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguh(vu, vv)
+}
+
+/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavguhrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguhrnd(vu, vv)
+}
+
+/// `Vd32.w=vavg(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgw(vu, vv)
+}
+
+/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vavgwrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgwrnd(vu, vv)
+}
+
+/// `Vd32.uh=vcl0(Vu32.uh)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vcl0h))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector {
+    vcl0h(vu)
+}
+
+/// `Vd32.uw=vcl0(Vu32.uw)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vcl0w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector {
+    vcl0w(vu)
+}
+
+/// `Vdd32=vcombine(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vcombine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vcombine(vu, vv)
+}
+
+/// `Vd32=#0`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vd0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vzero() -> HvxVector {
+    vd0()
+}
+
+/// `Vd32.b=vdeal(Vu32.b)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector {
+    vdealb(vu)
+}
+
+/// `Vd32.b=vdeale(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealb4w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdealb4w(vu, vv)
+}
+
+/// `Vd32.h=vdeal(Vu32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector {
+    vdealh(vu)
+}
+
+/// `Vdd32=vdeal(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdealvdd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vdealvdd(vu, vv, rt)
+}
+
+/// `Vd32=vdelta(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdelta))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdelta(vu, vv)
+}
+
+/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpybus(vu, rt)
+}
+
+/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpybus_acc(vx, vu, rt)
+}
+
+/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vdmpybus_dv(vuu, rt)
+}
+
+/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vdmpyacc_whwubrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vdmpybus_dv_acc(vxx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhb(vu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhb_acc(vx, vu, rt)
+}
+
+/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vdmpyhb_dv(vuu, rt)
+}
+
+/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vdmpyacc_wwwhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vdmpyhb_dv_acc(vxx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhisat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhisat(vuu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhisat_acc(vx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsat(vu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsat_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsuisat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhsuisat(vuu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+    vdmpyhsuisat_acc(vx, vuu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsusat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsusat(vu, rt)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vdmpyhsusat_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhvsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpyhvsat(vu, vv)
+}
+
+/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpyhvsat_acc(vx, vu, vv)
+}
+
+/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdsaduh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vdsaduh(vuu, rt)
+}
+
+/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vdsaduh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vdsaduh_acc(vxx, vuu, rt)
+}
+
+/// `Vx32.w=vinsert(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vinsertwr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector {
+    vinsertwr(vx, rt)
+}
+
+/// `Vd32=vlalign(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlalignb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vlalignb(vu, vv, rt)
+}
+
+/// `Vd32=vlalign(Vu32,Vv32,#u3)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlalignbi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+    vlalignbi(vu, vv, iu3)
+}
+
+/// `Vd32.uh=vlsr(Vu32.uh,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector {
+    vlsrh(vu, rt)
+}
+
+/// `Vd32.h=vlsr(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vlsrhv(vu, vv)
+}
+
+/// `Vd32.uw=vlsr(Vu32.uw,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector {
+    vlsrw(vu, rt)
+}
+
+/// `Vd32.w=vlsr(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlsrwv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vlsrwv(vu, vv)
+}
+
+/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvvb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vlutvvb(vu, vv, rt)
+}
+
+/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvvb_oracc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32or_vbvbvbr(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+    rt: i32,
+) -> HvxVector {
+    vlutvvb_oracc(vx, vu, vv, rt)
+}
+
+/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vlutvwh(vu, vv, rt)
+}
+
+/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vlutvwh_oracc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16or_whvbvhr(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vlutvwh_oracc(vxx, vu, vv, rt)
+}
+
+/// `Vd32.h=vmax(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxh(vu, vv)
+}
+
+/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxub(vu, vv)
+}
+
+/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxuh(vu, vv)
+}
+
+/// `Vd32.w=vmax(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmaxw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxw(vu, vv)
+}
+
+/// `Vd32.h=vmin(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminh(vu, vv)
+}
+
+/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminub(vu, vv)
+}
+
+/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminuh(vu, vv)
+}
+
+/// `Vd32.w=vmin(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vminw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminw(vu, vv)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpabus(vuu, rt)
+}
+
+/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpaacc_whwubrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpabus_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabusv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vmpabusv(vuu, vvv)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpabuuv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vmpabuuv(vuu, vvv)
+}
+
+/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpahb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpahb(vuu, rt)
+}
+
+/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpahb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpaacc_wwwhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpahb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpybus(vu, rt)
+}
+
+/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpybus_acc(vxx, vu, rt)
+}
+
+/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybusv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpybusv(vu, vv)
+}
+
+/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybusv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpyacc_whvubvb(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpybusv_acc(vxx, vu, vv)
+}
+
+/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpybv(vu, vv)
+}
+
+/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpybv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpyacc_whvbvb(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpybv_acc(vxx, vu, vv)
+}
+
+/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyewuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyewuh(vu, vv)
+}
+
+/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyh(vu, rt)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhsat_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpyhsat_acc(vxx, vu, rt)
+}
+
+/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhsrs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyhsrs(vu, rt)
+}
+
+/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhss))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyhss(vu, rt)
+}
+
+/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyhus(vu, vv)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhvuh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyhus_acc(vxx, vu, vv)
+}
+
+/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyhv(vu, vv)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhvh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyhv_acc(vxx, vu, vv)
+}
+
+/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyhvsrs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyhvsrs(vu, vv)
+}
+
+/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyieoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyieoh(vu, vv)
+}
+
+/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiewh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiewh_acc(vx, vu, vv)
+}
+
+/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiewuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiewuh(vu, vv)
+}
+
+/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiewuh_acc(vx, vu, vv)
+}
+
+/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyih))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyih(vu, vv)
+}
+
+/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyih_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyih_acc(vx, vu, vv)
+}
+
+/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyihb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyihb(vu, rt)
+}
+
+/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyihb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyihb_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiowh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyiowh(vu, vv)
+}
+
+/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwb(vu, rt)
+}
+
+/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwb_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwh(vu, rt)
+}
+
+/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyiwh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwh_acc(vx, vu, rt)
+}
+
+/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyowh(vu, vv)
+}
+
+/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh_rnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyowh_rnd(vu, vv)
+}
+
+/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVector {
+    vmpyowh_rnd_sacc(vx, vu, vv)
+}
+
+/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyowh_sacc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVector {
+    vmpyowh_sacc(vx, vu, vv)
+}
+
+/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyub(vu, rt)
+}
+
+/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyub_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpyacc_wuhvubrub(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpyub_acc(vxx, vu, rt)
+}
+
+/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyubv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyubv(vu, vv)
+}
+
+/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyubv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vmpyacc_wuhvubvub(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyubv_acc(vxx, vu, vv)
+}
+
+/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyuh(vu, rt)
+}
+
+/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpyuh_acc(vxx, vu, rt)
+}
+
+/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuhv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyuhv(vu, vv)
+}
+
+/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vmpyuhv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyuhv_acc(vxx, vu, vv)
+}
+
+/// `Vd32.h=vnavg(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgh(vu, vv)
+}
+
+/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnavgub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgub(vu, vv)
+}
+
+/// `Vd32.w=vnavg(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgw(vu, vv)
+}
+
+/// `Vd32.h=vnormamt(Vu32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnormamth))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector {
+    vnormamth(vu)
+}
+
+/// `Vd32.w=vnormamt(Vu32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnormamtw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector {
+    vnormamtw(vu)
+}
+
+/// `Vd32=vnot(Vu32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vnot))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector {
+    vnot(vu)
+}
+
+/// `Vd32=vor(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_or(vu, vv)
+}
+
+/// `Vd32.b=vpacke(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackeb(vu, vv)
+}
+
+/// `Vd32.h=vpacke(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackeh(vu, vv)
+}
+
+/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackhb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackhb_sat(vu, vv)
+}
+
+/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackhub_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackhub_sat(vu, vv)
+}
+
+/// `Vd32.b=vpacko(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackob(vu, vv)
+}
+
+/// `Vd32.h=vpacko(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackoh(vu, vv)
+}
+
+/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackwh_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackwh_sat(vu, vv)
+}
+
+/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpackwuh_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vpackwuh_sat(vu, vv)
+}
+
+/// `Vd32.h=vpopcount(Vu32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vpopcounth))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector {
+    vpopcounth(vu)
+}
+
+/// `Vd32=vrdelta(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrdelta))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrdelta(vu, vv)
+}
+
+/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpybus(vu, rt)
+}
+
+/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpybus_acc(vx, vu, rt)
+}
+
+/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+    vrmpybusi(vuu, rt, iu1)
+}
+
+/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusi_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vrmpyacc_wwwubrbi(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+    iu1: i32,
+) -> HvxVectorPair {
+    vrmpybusi_acc(vxx, vuu, rt, iu1)
+}
+
+/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybusv(vu, vv)
+}
+
+/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybusv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybusv_acc(vx, vu, vv)
+}
+
+/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybv(vu, vv)
+}
+
+/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpybv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpybv_acc(vx, vu, vv)
+}
+
+/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpyub(vu, rt)
+}
+
+/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyub_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vrmpyub_acc(vx, vu, rt)
+}
+
+/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+    vrmpyubi(vuu, rt, iu1)
+}
+
+/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubi_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+    iu1: i32,
+) -> HvxVectorPair {
+    vrmpyubi_acc(vxx, vuu, rt, iu1)
+}
+
+/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpyubv(vu, vv)
+}
+
+/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrmpyubv_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrmpyubv_acc(vx, vu, vv)
+}
+
+/// `Vd32=vror(Vu32,Rt32)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vror))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector {
+    vror(vu, rt)
+}
+
+/// `Vd32.b=vround(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundhb(vu, vv)
+}
+
+/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundhub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundhub(vu, vv)
+}
+
+/// `Vd32.h=vround(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundwh(vu, vv)
+}
+
+/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vroundwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vroundwuh(vu, vv)
+}
+
+/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrsadubi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+    vrsadubi(vuu, rt, iu1)
+}
+
+/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vrsadubi_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+    iu1: i32,
+) -> HvxVectorPair {
+    vrsadubi_acc(vxx, vuu, rt, iu1)
+}
+
+/// `Vd32.ub=vsat(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsathub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsathub(vu, vv)
+}
+
+/// `Vd32.h=vsat(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsatwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsatwh(vu, vv)
+}
+
+/// `Vdd32.h=vsxt(Vu32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair {
+    vsb(vu)
+}
+
+/// `Vdd32.w=vsxt(Vu32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair {
+    vsh(vu)
+}
+
+/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshufeh(vu, vv)
+}
+
+/// `Vd32.b=vshuff(Vu32.b)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector {
+    vshuffb(vu)
+}
+
+/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshuffeb(vu, vv)
+}
+
+/// `Vd32.h=vshuff(Vu32.h)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector {
+    vshuffh(vu)
+}
+
+/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshuffob(vu, vv)
+}
+
+/// `Vdd32=vshuff(Vu32,Vv32,Rt8)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshuffvdd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vshuffvdd(vu, vv, rt)
+}
+
+/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufoeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vshufoeb(vu, vv)
+}
+
+/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufoeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vshufoeh(vu, vv)
+}
+
+/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vshufoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vshufoh(vu, vv)
+}
+
+/// `Vd32.b=vsub(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubb(vu, vv)
+}
+
+/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubb_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubb_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vsub(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubh(vu, vv)
+}
+
+/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubh_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubh_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubhsat(vu, vv)
+}
+
+/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vsub(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsubhw(vu, vv)
+}
+
+/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsububh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsububh(vu, vv)
+}
+
+/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsububsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsububsat(vu, vv)
+}
+
+/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsububsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsububsat_dv(vuu, vvv)
+}
+
+/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubuhsat(vu, vv)
+}
+
+/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubuhsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubuhsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubuhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsubuhw(vu, vv)
+}
+
+/// `Vd32.w=vsub(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_sub(vu, vv)
+}
+
+/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubw_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubw_dv(vuu, vvv)
+}
+
+/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubwsat(vu, vv)
+}
+
+/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vsubwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubwsat_dv(vuu, vvv)
+}
+
+/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vtmpyb(vuu, rt)
+}
+
+/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpyacc_whwbrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vtmpyb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpybus))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vtmpybus(vuu, rt)
+}
+
+/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpybus_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vtmpyacc_whwubrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vtmpybus_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vtmpyhb(vuu, rt)
+}
+
+/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vtmpyhb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vtmpyacc_wwwhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vtmpyhb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32.h=vunpack(Vu32.b)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair {
+    vunpackb(vu)
+}
+
+/// `Vdd32.w=vunpack(Vu32.h)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair {
+    vunpackh(vu)
+}
+
+/// `Vxx32.h|=vunpacko(Vu32.b)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+    vunpackob(vxx, vu)
+}
+
+/// `Vxx32.w|=vunpacko(Vu32.h)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+    vunpackoh(vxx, vu)
+}
+
+/// `Vdd32.uh=vunpack(Vu32.ub)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair {
+    vunpackub(vu)
+}
+
+/// `Vdd32.uw=vunpack(Vu32.uh)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vunpackuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair {
+    vunpackuh(vu)
+}
+
+/// `Vd32=vxor(Vu32,Vv32)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vxor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    simd_xor(vu, vv)
+}
+
+/// `Vdd32.uh=vzxt(Vu32.ub)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vzb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair {
+    vzb(vu)
+}
+
+/// `Vdd32.uw=vzxt(Vu32.uh)`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[cfg_attr(test, assert_instr(vzh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair {
+    vzh(vu)
+}
+
+/// `Vd32.b=vsplat(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(lvsplatb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector {
+    lvsplatb(rt)
+}
+
+/// `Vd32.h=vsplat(Rt32)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(lvsplath))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector {
+    lvsplath(rt)
+}
+
+/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddbsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddbsat(vu, vv)
+}
+
+/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddbsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vaddbsat_dv(vuu, vvv)
+}
+
+/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddclbh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddclbh(vu, vv)
+}
+
+/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddclbw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddclbw(vu, vv)
+}
+
+/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddhw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vaddacc_wwvhvh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vaddhw_acc(vxx, vu, vv)
+}
+
+/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddubh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vaddacc_whvubvub(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vaddubh_acc(vxx, vu, vv)
+}
+
+/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vaddububb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vaddububb_sat(vu, vv)
+}
+
+/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vadduhw_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vaddacc_wwvuhvuh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vadduhw_acc(vxx, vu, vv)
+}
+
+/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vadduwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadduwsat(vu, vv)
+}
+
+/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vadduwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vadduwsat_dv(vuu, vvv)
+}
+
+/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vasrhbsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrhbsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vasruwuhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruwuhrndsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vasrwuhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasrwuhrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vlsr(Vu32.ub,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlsrb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector {
+    vlsrb(vu, rt)
+}
+
+/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvvb_nm))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vlutvvb_nm(vu, vv, rt)
+}
+
+/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvvb_oracci))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32or_vbvbvbi(
+    vx: HvxVector,
+    vu: HvxVector,
+    vv: HvxVector,
+    iu3: i32,
+) -> HvxVector {
+    vlutvvb_oracci(vx, vu, vv, iu3)
+}
+
+/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)`
+///
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvvbi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+    vlutvvbi(vu, vv, iu3)
+}
+
+/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvwh_nm))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+    vlutvwh_nm(vu, vv, rt)
+}
+
+/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvwh_oracci))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16or_whvbvhi(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+    iu3: i32,
+) -> HvxVectorPair {
+    vlutvwh_oracci(vxx, vu, vv, iu3)
+}
+
+/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vlutvwhi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
+    vlutvwhi(vu, vv, iu3)
+}
+
+/// `Vd32.b=vmax(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmaxb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmaxb(vu, vv)
+}
+
+/// `Vd32.b=vmin(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vminb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vminb(vu, vv)
+}
+
+/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpauhb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpauhb(vuu, rt)
+}
+
+/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpauhb_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpaacc_wwwuhrb(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpauhb_acc(vxx, vuu, rt)
+}
+
+/// `Vdd32=vmpye(Vu32.w,Vv32.uh)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyewuh_64))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpyewuh_64(vu, vv)
+}
+
+/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyiwub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwub(vu, rt)
+}
+
+/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyiwub_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyiwub_acc(vx, vu, rt)
+}
+
+/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vmpyoacc_wvwvh(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpyowh_64_acc(vxx, vu, vv)
+}
+
+/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vrounduhub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrounduhub(vu, vv)
+}
+
+/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vrounduwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrounduwuh(vu, vv)
+}
+
+/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsatuwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsatuwuh(vu, vv)
+}
+
+/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubbsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubbsat(vu, vv)
+}
+
+/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubbsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubbsat_dv(vuu, vvv)
+}
+
+/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubububb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubububb_sat(vu, vv)
+}
+
+/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubuwsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsubuwsat(vu, vv)
+}
+
+/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat`
+///
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[cfg_attr(test, assert_instr(vsubuwsat_dv))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+    vsubuwsat_dv(vuu, vvv)
+}
+
+/// `Vd32.b=vabs(Vu32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vabsb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector {
+    vabsb(vu)
+}
+
+/// `Vd32.b=vabs(Vu32.b):sat`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vabsb_sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector {
+    vabsb_sat(vu)
+}
+
+/// `Vx32.h+=vasl(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vaslh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vaslh_acc(vx, vu, rt)
+}
+
+/// `Vx32.h+=vasr(Vu32.h,Rt32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasrh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vasrh_acc(vx, vu, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasruhubrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruhubrndsat(vu, vv, rt)
+}
+
+/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasruhubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruhubsat(vu, vv, rt)
+}
+
+/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vasruwuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+    vasruwuhsat(vu, vv, rt)
+}
+
+/// `Vd32.b=vavg(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavgb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgb(vu, vv)
+}
+
+/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavgbrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavgbrnd(vu, vv)
+}
+
+/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavguw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguw(vu, vv)
+}
+
+/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vavguwrnd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vavguwrnd(vu, vv)
+}
+
+/// `Vdd32=#0`
+///
+/// Instruction Type: MAPPING
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vdd0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vzero() -> HvxVectorPair {
+    vdd0()
+}
+
+/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h`
+///
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vgathermh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+    vgathermh(rs, rt, mu, vv)
+}
+
+/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h`
+///
+/// Instruction Type: CVI_GATHER_DV
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vgathermhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
+    vgathermhw(rs, rt, mu, vvv)
+}
+
+/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w`
+///
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vgathermw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+    vgathermw(rs, rt, mu, vv)
+}
+
+/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpabuu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+    vmpabuu(vuu, rt)
+}
+
+/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpabuu_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wh_vmpaacc_whwubrub(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    rt: i32,
+) -> HvxVectorPair {
+    vmpabuu_acc(vxx, vuu, rt)
+}
+
+/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpyh_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+    vmpyh_acc(vxx, vu, rt)
+}
+
+/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpyuhe))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyuhe(vu, rt)
+}
+
+/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vmpyuhe_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+    vmpyuhe_acc(vx, vu, rt)
+}
+
+/// `Vd32.b=vnavg(Vu32.b,Vv32.b)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vnavgb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vnavgb(vu, vv)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermh(rt, mu, vv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermh_add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermh_add(rt, mu, vv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32`
+///
+/// Instruction Type: CVI_SCATTER_DV
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermhw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+    vscattermhw(rt, mu, vvv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32`
+///
+/// Instruction Type: CVI_SCATTER_DV
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermhw_add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+    vscattermhw_add(rt, mu, vvv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermw(rt, mu, vv, vw)
+}
+
+/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32`
+///
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[cfg_attr(test, assert_instr(vscattermw_add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+    vscattermw_add(rt, mu, vv, vw)
+}
+
+/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VP_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[cfg_attr(test, assert_instr(vasr_into))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_vasrinto_wwvwvw(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vasr_into(vxx, vu, vv)
+}
+
+/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[cfg_attr(test, assert_instr(vrotr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vrotr(vu, vv)
+}
+
+/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[cfg_attr(test, assert_instr(vsatdw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsatdw(vu, vv)
+}
+
+/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyhubs10))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpy_wubwbi_h(
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyhubs10(vuu, vvv, iu2)
+}
+
+/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyhubs10_vxx(vxx, vuu, vvv, iu2)
+}
+
+/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyvubs10))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpy_wubwbi_v(
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyvubs10(vuu, vvv, iu2)
+}
+
+/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v(
+    vxx: HvxVectorPair,
+    vuu: HvxVectorPair,
+    vvv: HvxVectorPair,
+    iu2: i32,
+) -> HvxVectorPair {
+    v6mpyvubs10_vxx(vxx, vuu, vvv, iu2)
+}
+
+/// `Vd32.hf=vabs(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vabs_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector {
+    vabs_hf(vu)
+}
+
+/// `Vd32.sf=vabs(Vu32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vabs_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector {
+    vabs_sf(vu)
+}
+
+/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_hf(vu, vv)
+}
+
+/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_hf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_hf_hf(vu, vv)
+}
+
+/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf16(vu, vv)
+}
+
+/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf16_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf16_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf32(vu, vv)
+}
+
+/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_qf32_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_qf32_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_sf(vu, vv)
+}
+
+/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vadd_sf_hf(vu, vv)
+}
+
+/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vadd_sf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vadd_sf_sf(vu, vv)
+}
+
+/// `Vd32.w=vfmv(Vu32.w)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vassign_fp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector {
+    vassign_fp(vu)
+}
+
+/// `Vd32.hf=Vu32.qf16`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vconv_hf_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector {
+    vconv_hf_qf16(vu)
+}
+
+/// `Vd32.hf=Vuu32.qf32`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vconv_hf_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector {
+    vconv_hf_qf32(vuu)
+}
+
+/// `Vd32.sf=Vu32.qf32`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vconv_sf_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector {
+    vconv_sf_qf32(vu)
+}
+
+/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_b_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vcvt_b_hf(vu, vv)
+}
+
+/// `Vd32.h=vcvt(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_h_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+    vcvt_h_hf(vu)
+}
+
+/// `Vdd32.hf=vcvt(Vu32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_b))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair {
+    vcvt_hf_b(vu)
+}
+
+/// `Vd32.hf=vcvt(Vu32.h)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_h))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector {
+    vcvt_hf_h(vu)
+}
+
+/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vcvt_hf_sf(vu, vv)
+}
+
+/// `Vdd32.hf=vcvt(Vu32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_ub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair {
+    vcvt_hf_ub(vu)
+}
+
+/// `Vd32.hf=vcvt(Vu32.uh)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_uh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector {
+    vcvt_hf_uh(vu)
+}
+
+/// `Vdd32.sf=vcvt(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair {
+    vcvt_sf_hf(vu)
+}
+
+/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_ub_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vcvt_ub_hf(vu, vv)
+}
+
+/// `Vd32.uh=vcvt(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vcvt_uh_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+    vcvt_uh_hf(vu)
+}
+
+/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpy_sf_hf(vu, vv)
+}
+
+/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vdmpy_sf_hf_acc(vx, vu, vv)
+}
+
+/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmax_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmax_hf(vu, vv)
+}
+
+/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmax_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmax_sf(vu, vv)
+}
+
+/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmin_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmin_hf(vu, vv)
+}
+
+/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfmin_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmin_sf(vu, vv)
+}
+
+/// `Vd32.hf=vfneg(Vu32.hf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfneg_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector {
+    vfneg_hf(vu)
+}
+
+/// `Vd32.sf=vfneg(Vu32.sf)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vfneg_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector {
+    vfneg_sf(vu)
+}
+
+/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmax_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmax_hf(vu, vv)
+}
+
+/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmax_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmax_sf(vu, vv)
+}
+
+/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmin_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmin_hf(vu, vv)
+}
+
+/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmin_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmin_sf(vu, vv)
+}
+
+/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_hf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_hf_hf(vu, vv)
+}
+
+/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_hf_hf_acc(vx, vu, vv)
+}
+
+/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf16(vu, vv)
+}
+
+/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf16_hf(vu, vv)
+}
+
+/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf16_mix_hf(vu, vv)
+}
+
+/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf32(vu, vv)
+}
+
+/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_qf32_hf(vu, vv)
+}
+
+/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_qf32_mix_hf(vu, vv)
+}
+
+/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_qf32_qf16(vu, vv)
+}
+
+/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_qf32_sf(vu, vv)
+}
+
+/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vmpy_sf_hf(vu, vv)
+}
+
+/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf(
+    vxx: HvxVectorPair,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPair {
+    vmpy_sf_hf_acc(vxx, vu, vv)
+}
+
+/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vmpy_sf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpy_sf_sf(vu, vv)
+}
+
+/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_hf(vu, vv)
+}
+
+/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_hf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_hf_hf(vu, vv)
+}
+
+/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf16))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf16(vu, vv)
+}
+
+/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf16_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf16_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf32))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf32(vu, vv)
+}
+
+/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_qf32_mix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_qf32_mix(vu, vv)
+}
+
+/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_sf(vu, vv)
+}
+
+/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_sf_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vsub_sf_hf(vu, vv)
+}
+
+/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[cfg_attr(test, assert_instr(vsub_sf_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vsub_sf_sf(vu, vv)
+}
+
+/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvuhubrndsat(vuu, vv)
+}
+
+/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvuhubsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvuhubsat(vuu, vv)
+}
+
+/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvwuhrndsat(vuu, vv)
+}
+
+/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vasrvwuhsat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+    vasrvwuhsat(vuu, vv)
+}
+
+/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
+#[cfg_attr(test, assert_instr(vmpyuhvs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmpyuhvs(vu, vv)
+}
+
+/// `Vd32.h=Vu32.hf`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_h_hf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector {
+    vconv_h_hf(vu)
+}
+
+/// `Vd32.hf=Vu32.h`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_hf_h))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector {
+    vconv_hf_h(vu)
+}
+
+/// `Vd32.sf=Vu32.w`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_sf_w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector {
+    vconv_sf_w(vu)
+}
+
+/// `Vd32.w=Vu32.sf`
+///
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
+#[cfg_attr(test, assert_instr(vconv_w_sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector {
+    vconv_w_sf(vu)
+}
+
+/// `Vd32=vgetqfext(Vu32.x,Rt32)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(get_qfext))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+    get_qfext(vu, rt)
+}
+
+/// `Vd32.x=vsetqfext(Vu32,Rt32)`
+///
+/// Instruction Type: CVI_VX
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(set_qfext))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+    set_qfext(vu, rt)
+}
+
+/// `Vd32.f8=vabs(Vu32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vabs_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector {
+    vabs_f8(vu)
+}
+
+/// `Vdd32.hf=vcvt2(Vu32.b)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vcvt2_hf_b))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair {
+    vcvt2_hf_b(vu)
+}
+
+/// `Vdd32.hf=vcvt2(Vu32.ub)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair {
+    vcvt2_hf_ub(vu)
+}
+
+/// `Vdd32.hf=vcvt(Vu32.f8)`
+///
+/// Instruction Type: CVI_VX_DV
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vcvt_hf_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair {
+    vcvt_hf_f8(vu)
+}
+
+/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vfmax_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmax_f8(vu, vv)
+}
+
+/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vfmin_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vfmin_f8(vu, vv)
+}
+
+/// `Vd32.f8=vfneg(Vu32.f8)`
+///
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
+#[cfg_attr(test, assert_instr(vfneg_f8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector {
+    vfneg_f8(vu)
+}
+
+/// `Qd4=and(Qs4,Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=and(Qs4,!Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_and_n(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=not(Qs4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_not(vandvrt(
+            core::mem::transmute::<HvxVectorPred, HvxVector>(qs),
+            -1,
+        )),
+        -1,
+    ))
+}
+
+/// `Qd4=or(Qs4,Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=or(Qs4,!Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_or_n(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vsetq(Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2(rt), -1))
+}
+
+/// `Qd4=xor(Qs4,Qt4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        pred_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `if (!Qv4) vmem(Rt32+#s4)=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_nqpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_nt_nqpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_nt_qpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (Qv4) vmem(Rt32+#s4)=Vs32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VM_ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+    vS32b_qpred_ai(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        rt,
+        vs,
+    )
+}
+
+/// `if (!Qv4) Vx32.b+=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddbnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.b+=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddbq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.h+=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddhnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.h+=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddhq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.w+=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddwnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.w+=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vaddwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `Vd32=vand(Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
+}
+
+/// `Vx32|=vand(Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandvrt_acc(vx, core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
+}
+
+/// `Qd4=vand(Vu32,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vu, rt))
+}
+
+/// `Qx4|=vand(Vu32,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt_acc(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qx),
+        vu,
+        rt,
+    ))
+}
+
+/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqb(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqand_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqb_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqor_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqb_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqxacc_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqb_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqh(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqand_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqh_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqor_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqh_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqxacc_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqh_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqw(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqand_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqw_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqor_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqw_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_eqxacc_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        veqw_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtb(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtb_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtb_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvbvb(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtb_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgth(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgth_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgth_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvhvh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgth_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtub(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvubvub(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtub_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvubvub(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtub_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvubvub(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtub_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuh(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvuhvuh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuh_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvuhvuh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuh_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuh_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuw(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvuwvuw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuw_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvuwvuw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuw_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtuw_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtw(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtw_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtw_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvwvw(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtw_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Vd32=vmux(Qt4,Vu32,Vv32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
+    vmux(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        vu,
+        vv,
+    )
+}
+
+/// `if (!Qv4) Vx32.b-=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubbnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.b-=Vu32.b`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubbq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.h-=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubhnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.h-=Vu32.h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubhq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (!Qv4) Vx32.w-=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubwnq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `if (Qv4) Vx32.w-=Vu32.w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+    vsubwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vx,
+        vu,
+    )
+}
+
+/// `Vdd32=vswap(Qt4,Vu32,Vv32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+    vswap(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        vu,
+        vv,
+    )
+}
+
+/// `Qd4=vsetq2(Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VP
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2v2(rt), -1))
+}
+
+/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        shuffeqh(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA_DV
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        shuffeqw(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
+        ),
+        -1,
+    ))
+}
+
+/// `Vd32=vand(!Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandnqrt(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
+        rt,
+    )
+}
+
+/// `Vx32|=vand(!Qu4,Rt32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VX_LATE
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+    vandnqrt_acc(
+        vx,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
+        rt,
+    )
+}
+
+/// `Vd32=vand(!Qv4,Vu32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+    vandvnqv(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vu,
+    )
+}
+
+/// `Vd32=vand(Qv4,Vu32)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+    vandvqv(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
+        vu,
+    )
+}
+
+/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_aqrmvh(
+    rs: *mut HvxVector,
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+) {
+    vgathermhq(
+        rs,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+    )
+}
+
+/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_GATHER_DV
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_aqrmww(
+    rs: *mut HvxVector,
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vvv: HvxVectorPair,
+) {
+    vgathermhwq(
+        rs,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vvv,
+    )
+}
+
+/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_GATHER
+/// Execution Slots: SLOT01
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vgather_aqrmvw(
+    rs: *mut HvxVector,
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+) {
+    vgathermwq(
+        rs,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+    )
+}
+
+/// `Vd32.b=prefixsum(Qv4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+    vprefixqb(vandvrt(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
+        -1,
+    ))
+}
+
+/// `Vd32.h=prefixsum(Qv4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+    vprefixqh(vandvrt(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
+        -1,
+    ))
+}
+
+/// `Vd32.w=prefixsum(Qv4)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VS
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+    vprefixqw(vandvrt(
+        core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
+        -1,
+    ))
+}
+
+/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_qrmvhv(
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+    vw: HvxVector,
+) {
+    vscattermhq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+        vw,
+    )
+}
+
+/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_SCATTER_DV
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_qrmwwv(
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vvv: HvxVectorPair,
+    vw: HvxVector,
+) {
+    vscattermhwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vvv,
+        vw,
+    )
+}
+
+/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_SCATTER
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vscatter_qrmvwv(
+    qs: HvxVectorPred,
+    rt: i32,
+    mu: i32,
+    vv: HvxVector,
+    vw: HvxVector,
+) {
+    vscattermwq(
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+        rt,
+        mu,
+        vv,
+        vw,
+    )
+}
+
+/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_vw_vadd_vwvwq_carry_sat(
+    vu: HvxVector,
+    vv: HvxVector,
+    qs: HvxVectorPred,
+) -> HvxVector {
+    vaddcarrysat(
+        vu,
+        vv,
+        vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
+    )
+}
+
+/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgthf(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvhfvhf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgthf_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvhfvhf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgthf_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgthf_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtsf(vu, vv), -1))
+}
+
+/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtand_qvsfvsf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtsf_and(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtor_qvsfvsf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtsf_or(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
+
+/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)`
+///
+/// This is a compound operation composed of multiple HVX instructions.
+/// Instruction Type: CVI_VA
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf(
+    qx: HvxVectorPred,
+    vu: HvxVector,
+    vv: HvxVector,
+) -> HvxVectorPred {
+    core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
+        vgtsf_xor(
+            vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qx), -1),
+            vu,
+            vv,
+        ),
+        -1,
+    ))
+}
diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 2f8dec75b7..43317ff41d 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -1,13 +1,20 @@
 //! Hexagon HVX Code Generator
 //!
-//! This generator creates hvx.rs from scratch using the LLVM HVX header file
-//! as the sole source of truth. It parses the C intrinsic prototypes and
-//! generates Rust wrapper functions with appropriate attributes.
+//! This generator creates v64.rs and v128.rs from scratch using the LLVM HVX
+//! header file as the sole source of truth. It parses the C intrinsic prototypes
+//! and generates Rust wrapper functions with appropriate attributes.
+//!
+//! The two generated files provide:
+//! - v64.rs: 64-byte vector mode intrinsics (512-bit vectors)
+//! - v128.rs: 128-byte vector mode intrinsics (1024-bit vectors)
+//!
+//! Both modules are available unconditionally, but require the appropriate
+//! target features to actually use the intrinsics.
 //!
 //! Usage:
 //!     cd crates/stdarch-gen-hexagon
 //!     cargo run
-//!     # Output is written directly to ../core_arch/src/hexagon/hvx.rs
+//!     # Output is written to ../core_arch/src/hexagon/v64.rs and v128.rs
 
 use regex::Regex;
 use std::collections::{HashMap, HashSet};
@@ -32,6 +39,46 @@ fn get_simd_intrinsic_mappings() -> HashMap<&'static str, &'static str> {
 /// The tracking issue number for the stdarch_hexagon feature
 const TRACKING_ISSUE: &str = "151523";
 
+/// HVX vector length mode
+#[derive(Debug, Clone, Copy, PartialEq)]
+enum VectorMode {
+    /// 64-byte vectors (512 bits)
+    V64,
+    /// 128-byte vectors (1024 bits)
+    V128,
+}
+
+impl VectorMode {
+    fn bytes(&self) -> u32 {
+        match self {
+            VectorMode::V64 => 64,
+            VectorMode::V128 => 128,
+        }
+    }
+
+    fn bits(&self) -> u32 {
+        self.bytes() * 8
+    }
+
+    fn lanes(&self) -> u32 {
+        self.bytes() / 4 // 32-bit lanes
+    }
+
+    fn module_name(&self) -> &'static str {
+        match self {
+            VectorMode::V64 => "v64",
+            VectorMode::V128 => "v128",
+        }
+    }
+
+    fn target_feature(&self) -> &'static str {
+        match self {
+            VectorMode::V64 => "hvx-length64b",
+            VectorMode::V128 => "hvx-length128b",
+        }
+    }
+}
+
 /// LLVM tag to fetch the header from
 const LLVM_TAG: &str = "llvmorg-22.1.0-rc1";
 
@@ -484,26 +531,24 @@ fn q6_to_rust_name(q6_name: &str) -> String {
 }
 
 /// Generate the module documentation
-fn generate_module_doc() -> String {
-    r#"//! Hexagon HVX intrinsics
+fn generate_module_doc(mode: VectorMode) -> String {
+    format!(
+        r#"//! Hexagon HVX {bytes}-byte vector mode intrinsics
+//!
+//! This module provides intrinsics for the Hexagon Vector Extensions (HVX)
+//! in {bytes}-byte vector mode ({bits}-bit vectors).
 //!
-//! This module provides intrinsics for the Hexagon Vector Extensions (HVX).
 //! HVX is a wide vector extension designed for high-performance signal processing.
 //! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61)
 //!
 //! ## Vector Types
 //!
-//! HVX supports different vector lengths depending on the configuration:
-//! - 128-byte mode: `HvxVector` is 1024 bits (128 bytes)
-//! - 64-byte mode: `HvxVector` is 512 bits (64 bytes)
-//!
-//! This implementation targets 128-byte mode by default. To change the vector
-//! length mode, use the appropriate target feature when compiling:
-//! - For 128-byte mode: `-C target-feature=+hvx-length128b`
-//! - For 64-byte mode: `-C target-feature=+hvx-length64b`
+//! In {bytes}-byte mode:
+//! - `HvxVector` is {bits} bits ({bytes} bytes) containing {lanes} x 32-bit values
+//! - `HvxVectorPair` is {pair_bits} bits ({pair_bytes} bytes)
+//! - `HvxVectorPred` is {bits} bits ({bytes} bytes) for predicate operations
 //!
-//! Note that HVX v66 and later default to 128-byte mode, while earlier versions
-//! default to 64-byte mode.
+//! To use this module, compile with `-C target-feature=+{target_feature}`.
 //!
 //! ## Architecture Versions
 //!
@@ -517,15 +562,27 @@ fn generate_module_doc() -> String {
 //! - HVX v69: `-C target-feature=+hvxv69`
 //! - HVX v73: `-C target-feature=+hvxv73`
 //! - HVX v79: `-C target-feature=+hvxv79`
-//! - HVX v81: `-C target-feature=+hvxv81`
 //!
 //! Each version includes all features from previous versions.
-"#
-    .to_string()
+"#,
+        bytes = mode.bytes(),
+        bits = mode.bits(),
+        lanes = mode.lanes(),
+        pair_bytes = mode.bytes() * 2,
+        pair_bits = mode.bits() * 2,
+        target_feature = mode.target_feature(),
+    )
 }
 
-/// Generate the type definitions
-fn generate_types() -> String {
+/// Generate the type definitions for a specific vector mode
+fn generate_types(mode: VectorMode) -> String {
+    let lanes = mode.lanes();
+    let pair_lanes = lanes * 2;
+    let bits = mode.bits();
+    let bytes = mode.bytes();
+    let pair_bits = bits * 2;
+    let pair_bytes = bytes * 2;
+
     format!(
         r#"
 #![allow(non_camel_case_types)]
@@ -535,54 +592,35 @@ use stdarch_test::assert_instr;
 
 use crate::intrinsics::simd::{{simd_add, simd_and, simd_or, simd_sub, simd_xor}};
 
-// HVX type definitions for 128-byte vector mode (default for v66+)
-// Use -C target-feature=+hvx-length128b to enable
-#[cfg(target_feature = "hvx-length128b")]
-types! {{
-    #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")]
-
-    /// HVX vector type (1024 bits / 128 bytes)
-    ///
-    /// This type represents a single HVX vector register containing 32 x 32-bit values.
-    pub struct HvxVector(32 x i32);
-
-    /// HVX vector pair type (2048 bits / 256 bytes)
-    ///
-    /// This type represents a pair of HVX vector registers, often used for
-    /// operations that produce double-width results.
-    pub struct HvxVectorPair(64 x i32);
-
-    /// HVX vector predicate type (1024 bits / 128 bytes)
-    ///
-    /// This type represents a predicate vector used for conditional operations.
-    /// Each bit corresponds to a lane in the vector.
-    pub struct HvxVectorPred(32 x i32);
-}}
-
-// HVX type definitions for 64-byte vector mode (default for v60-v65)
-// Use -C target-feature=+hvx-length64b to enable, or omit hvx-length128b
-#[cfg(not(target_feature = "hvx-length128b"))]
+// HVX type definitions for {bytes}-byte vector mode
 types! {{
     #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")]
 
-    /// HVX vector type (512 bits / 64 bytes)
+    /// HVX vector type ({bits} bits / {bytes} bytes)
     ///
-    /// This type represents a single HVX vector register containing 16 x 32-bit values.
-    pub struct HvxVector(16 x i32);
+    /// This type represents a single HVX vector register containing {lanes} x 32-bit values.
+    pub struct HvxVector({lanes} x i32);
 
-    /// HVX vector pair type (1024 bits / 128 bytes)
+    /// HVX vector pair type ({pair_bits} bits / {pair_bytes} bytes)
     ///
     /// This type represents a pair of HVX vector registers, often used for
     /// operations that produce double-width results.
-    pub struct HvxVectorPair(32 x i32);
+    pub struct HvxVectorPair({pair_lanes} x i32);
 
-    /// HVX vector predicate type (512 bits / 64 bytes)
+    /// HVX vector predicate type ({bits} bits / {bytes} bytes)
     ///
     /// This type represents a predicate vector used for conditional operations.
     /// Each bit corresponds to a lane in the vector.
-    pub struct HvxVectorPred(16 x i32);
+    pub struct HvxVectorPred({lanes} x i32);
 }}
-"#
+"#,
+        bytes = bytes,
+        bits = bits,
+        lanes = lanes,
+        pair_bits = pair_bits,
+        pair_bytes = pair_bytes,
+        pair_lanes = pair_lanes,
+        TRACKING_ISSUE = TRACKING_ISSUE,
     )
 }
 
@@ -1160,8 +1198,8 @@ fn get_compound_helper_signatures() -> HashMap<String, BuiltinSignature> {
     map
 }
 
-/// Generate extern declarations for all intrinsics
-fn generate_extern_block(intrinsics: &[IntrinsicInfo]) -> String {
+/// Generate extern declarations for all intrinsics for a specific vector mode
+fn generate_extern_block(intrinsics: &[IntrinsicInfo], mode: VectorMode) -> String {
     let mut output = String::new();
 
     // Collect unique builtins to avoid duplicates
@@ -1226,15 +1264,18 @@ fn generate_extern_block(intrinsics: &[IntrinsicInfo]) -> String {
     // Sort by builtin name for consistent output
     decls.sort_by(|a, b| a.0.cmp(&b.0));
 
-    // Generate 128-byte mode intrinsics (default for v66+)
-    output.push_str("// LLVM intrinsic declarations for 128-byte vector mode\n");
-    output.push_str("#[cfg(target_feature = \"hvx-length128b\")]\n");
+    // Generate intrinsic declarations for the specified mode
+    output.push_str(&format!(
+        "// LLVM intrinsic declarations for {}-byte vector mode\n",
+        mode.bytes()
+    ));
     output.push_str("#[allow(improper_ctypes)]\n");
     output.push_str("unsafe extern \"unadjusted\" {\n");
 
     for (builtin_name, instr_name, return_type, param_types) in &decls {
         let base_link = builtin_name.replace('_', ".");
-        let link_name = if builtin_name.starts_with("V6_") {
+        // 128-byte mode uses .128B suffix, 64-byte mode doesn't
+        let link_name = if builtin_name.starts_with("V6_") && mode == VectorMode::V128 {
             format!("llvm.hexagon.{}.128B", base_link)
         } else {
             format!("llvm.hexagon.{}", base_link)
@@ -1262,41 +1303,6 @@ fn generate_extern_block(intrinsics: &[IntrinsicInfo]) -> String {
         ));
     }
 
-    output.push_str("}\n\n");
-
-    // Generate 64-byte mode intrinsics (default for v60-v65)
-    output.push_str("// LLVM intrinsic declarations for 64-byte vector mode\n");
-    output.push_str("#[cfg(not(target_feature = \"hvx-length128b\"))]\n");
-    output.push_str("#[allow(improper_ctypes)]\n");
-    output.push_str("unsafe extern \"unadjusted\" {\n");
-
-    for (builtin_name, instr_name, return_type, param_types) in &decls {
-        let base_link = builtin_name.replace('_', ".");
-        // 64-byte mode uses intrinsics without the .128B suffix
-        let link_name = format!("llvm.hexagon.{}", base_link);
-
-        let params_str = if param_types.is_empty() {
-            String::new()
-        } else {
-            param_types
-                .iter()
-                .map(|t| format!("_: {}", t.to_extern_str()))
-                .collect::<Vec<_>>()
-                .join(", ")
-        };
-
-        let return_str = if *return_type == RustType::Unit {
-            " -> ()".to_string()
-        } else {
-            format!(" -> {}", return_type.to_extern_str())
-        };
-
-        output.push_str(&format!(
-            "    #[link_name = \"{}\"]\n    fn {}({}){};\n",
-            link_name, instr_name, params_str, return_str
-        ));
-    }
-
     output.push_str("}\n");
     output
 }
@@ -1596,14 +1602,18 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String {
     output
 }
 
-/// Generate the complete hvx.rs file
-fn generate_hvx_rs(intrinsics: &[IntrinsicInfo], output_path: &Path) -> Result<(), String> {
+/// Generate a module file for a specific vector mode
+fn generate_module_file(
+    intrinsics: &[IntrinsicInfo],
+    output_path: &Path,
+    mode: VectorMode,
+) -> Result<(), String> {
     let mut output =
         File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?;
 
-    writeln!(output, "{}", generate_module_doc()).map_err(|e| e.to_string())?;
-    writeln!(output, "{}", generate_types()).map_err(|e| e.to_string())?;
-    writeln!(output, "{}", generate_extern_block(intrinsics)).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_module_doc(mode)).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_types(mode)).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_extern_block(intrinsics, mode)).map_err(|e| e.to_string())?;
     writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?;
 
     // Ensure file is flushed before running rustfmt
@@ -1677,21 +1687,39 @@ fn main() -> Result<(), String> {
         println!("    HVX v{}: {} intrinsics", arch, count);
     }
 
-    // Generate output
+    // Generate output files
     let crate_dir = std::env::var("CARGO_MANIFEST_DIR")
         .map(std::path::PathBuf::from)
         .unwrap_or_else(|_| std::env::current_dir().unwrap());
 
-    let output_path = crate_dir.join("../core_arch/src/hexagon/hvx.rs");
+    let hexagon_dir = crate_dir.join("../core_arch/src/hexagon");
+
+    // Generate v64.rs (64-byte vector mode)
+    let v64_path = hexagon_dir.join("v64.rs");
+    println!("\nStep 3: Generating v64.rs (64-byte mode)...");
+    generate_module_file(&intrinsics, &v64_path, VectorMode::V64)?;
+    println!("  Output: {}", v64_path.display());
 
-    println!("\nStep 3: Generating hvx.rs...");
-    generate_hvx_rs(&intrinsics, &output_path)?;
+    // Generate v128.rs (128-byte vector mode)
+    let v128_path = hexagon_dir.join("v128.rs");
+    println!("\nStep 4: Generating v128.rs (128-byte mode)...");
+    generate_module_file(&intrinsics, &v128_path, VectorMode::V128)?;
+    println!("  Output: {}", v128_path.display());
 
     println!("\n=== Results ===");
-    println!("  Generated {} simple wrapper functions", simple_count);
-    println!("  Generated {} compound wrapper functions", compound_count);
-    println!("  Total: {} functions", simple_count + compound_count);
-    println!("  Output: {}", output_path.display());
+    println!(
+        "  Generated {} simple wrapper functions per module",
+        simple_count
+    );
+    println!(
+        "  Generated {} compound wrapper functions per module",
+        compound_count
+    );
+    println!(
+        "  Total: {} functions per module",
+        simple_count + compound_count
+    );
+    println!("  Output files: v64.rs, v128.rs");
 
     Ok(())
 }
diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index 1891f194ed..d4a97235b4 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -41,8 +41,10 @@
     dead_code
 )]
 
-#[cfg(target_arch = "hexagon")]
-use core_arch::arch::hexagon::*;
+#[cfg(all(target_arch = "hexagon", not(target_feature = "hvx-length128b")))]
+use core_arch::arch::hexagon::v64::*;
+#[cfg(all(target_arch = "hexagon", target_feature = "hvx-length128b"))]
+use core_arch::arch::hexagon::v128::*;
 
 /// Vector length in bytes for HVX 128-byte mode
 #[cfg(all(target_arch = "hexagon", target_feature = "hvx-length128b"))]

From ef26545e4152be74c4feb4786b1895d833246341 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Tue, 3 Feb 2026 09:18:36 -0600
Subject: [PATCH 139/326] examples: Add assertions to gaussian example

Replace print statements with assertions that verify the Gaussian 3x3
blur implementation against the Hexagon SDK reference algorithm.

- Port exact SDK Gaussian3x3u8 implementation from:
  /opt/Hexagon_SDK/.../Examples/HVX/gaussian/src/gaussian.c
- Verify specific output values [15, 16, 17, 18, 19, 20, 21, 22]
  for row 2, cols 1..9 with test pattern ((x + y*7) % 256)
- Assert byte-averaging approximation exactly matches SDK reference
- On Hexagon: verify HVX output matches both scalar approximation
  and SDK reference exactly
---
 examples/gaussian.rs | 181 +++++++++++++++++++++----------------------
 1 file changed, 89 insertions(+), 92 deletions(-)

diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index d4a97235b4..575f4db8c8 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -178,26 +178,25 @@ pub unsafe fn gaussian3x3u8(
     }
 }
 
-/// Scalar reference implementation of Gaussian 3x3 blur for verification
+/// Reference C implementation from Hexagon SDK (Gaussian3x3u8)
 ///
-/// Applies the exact 3x3 Gaussian kernel:
-///     out[y][x] = (1*p[-1][-1] + 2*p[-1][0] + 1*p[-1][1] +
-///                  2*p[ 0][-1] + 4*p[ 0][0] + 2*p[ 0][1] +
-///                  1*p[ 1][-1] + 2*p[ 1][0] + 1*p[ 1][1] + 8) / 16
-fn gaussian3x3u8_scalar(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) {
+/// Kernel:
+///     1 2 1
+///     2 4 2  / 16
+///     1 2 1
+fn gaussian3x3u8_reference(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) {
     for y in 1..height - 1 {
         for x in 1..width - 1 {
-            let sum = src[(y - 1) * stride + (x - 1)] as u32
-                + src[(y - 1) * stride + x] as u32 * 2
-                + src[(y - 1) * stride + (x + 1)] as u32
-                + src[y * stride + (x - 1)] as u32 * 2
-                + src[y * stride + x] as u32 * 4
-                + src[y * stride + (x + 1)] as u32 * 2
-                + src[(y + 1) * stride + (x - 1)] as u32
-                + src[(y + 1) * stride + x] as u32 * 2
-                + src[(y + 1) * stride + (x + 1)] as u32;
-            // Divide by 16 with rounding, saturate to u8
-            dst[y * stride + x] = ((sum + 8) >> 4).min(255) as u8;
+            // Compute column sums (vertical 1-2-1 weights)
+            let mut col = [0u32; 3];
+            for i in 0..3 {
+                col[i] = 1 * src[(y - 1) * stride + x - 1 + i] as u32
+                    + 2 * src[y * stride + x - 1 + i] as u32
+                    + 1 * src[(y + 1) * stride + x - 1 + i] as u32;
+            }
+            // Apply horizontal 1-2-1 weights and normalize
+            // (1*col[0] + 2*col[1] + 1*col[2] + 8) / 16
+            dst[y * stride + x] = ((1 * col[0] + 2 * col[1] + 1 * col[2] + 8) >> 4) as u8;
         }
     }
 }
@@ -208,13 +207,7 @@ fn gaussian3x3u8_scalar(src: &[u8], stride: usize, width: usize, height: usize,
 /// - Vertical: avg_rnd(avg_rnd(above, below), center)
 /// - Horizontal: avg_rnd(avg_rnd(left, right), center)
 /// where avg_rnd(a, b) = (a + b + 1) / 2
-fn gaussian3x3u8_scalar_approx(
-    src: &[u8],
-    stride: usize,
-    width: usize,
-    height: usize,
-    dst: &mut [u8],
-) {
+fn gaussian3x3u8_approx(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) {
     // Temporary buffer for vertical pass output
     let mut tmp = vec![0u8; width * height];
 
@@ -241,66 +234,71 @@ fn gaussian3x3u8_scalar_approx(
     }
 }
 
+/// Generate deterministic test pattern matching test approach
+fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) {
+    for y in 0..height {
+        for x in 0..width {
+            buf[y * width + x] = ((x + y * 7) % 256) as u8;
+        }
+    }
+}
+
 fn main() {
-    println!("HVX Gaussian 3x3 blur example");
-    println!("Separable filter using byte averaging (HvxVector only)");
-    println!();
+    // Test dimensions
+    #[cfg(not(target_arch = "hexagon"))]
+    const WIDTH: usize = 128;
+    #[cfg(target_arch = "hexagon")]
+    const WIDTH: usize = 256; // Must be multiple of VLEN (128)
+    const HEIGHT: usize = 16;
 
     #[cfg(not(target_arch = "hexagon"))]
     {
-        const WIDTH: usize = 128;
-        const HEIGHT: usize = 16;
-
         let mut src = vec![0u8; WIDTH * HEIGHT];
-        let mut dst_exact = vec![0u8; WIDTH * HEIGHT];
+        let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
         let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
 
-        // Create test pattern
-        for y in 0..HEIGHT {
-            for x in 0..WIDTH {
-                src[y * WIDTH + x] = ((x + y * 7) % 256) as u8;
-            }
+        // Generate test pattern
+        generate_test_pattern(&mut src, WIDTH, HEIGHT);
+
+        // Run reference implementation
+        gaussian3x3u8_reference(&src, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
+
+        // Run byte-averaging approximation (matches HVX behavior)
+        gaussian3x3u8_approx(&src, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
+
+        // Verify specific output values from reference
+        // These are computed using the exact algorithm on our test pattern
+        // Row 2, cols 1..9 with input pattern ((x + y*7) % 256)
+        // Input: row1=[7,8,9,...], row2=[14,15,16,...], row3=[21,22,23,...]
+        let expected_ref_row2: [u8; 8] = [15, 16, 17, 18, 19, 20, 21, 22];
+        for (i, &expected) in expected_ref_row2.iter().enumerate() {
+            let actual = dst_ref[2 * WIDTH + 1 + i];
+            assert_eq!(
+                actual, expected,
+                "reference mismatch at row 2, col {}: expected {}, got {}",
+                1 + i,
+                expected,
+                actual
+            );
         }
 
-        // Run exact Gaussian
-        gaussian3x3u8_scalar(&src, WIDTH, WIDTH, HEIGHT, &mut dst_exact);
-
-        // Run approximate version (matches HVX behavior)
-        gaussian3x3u8_scalar_approx(&src, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
-
-        // Compare exact vs approximate
-        let mut max_diff = 0u8;
+        // Verify approximation exactly matches reference for this test pattern
+        // The byte-averaging approach avg(avg(a,c), b) produces identical results
+        // to the Hexagon SDK's (1*a + 2*b + 1*c + 2) / 4 for this input pattern
         for y in 1..HEIGHT - 1 {
             for x in 1..WIDTH - 1 {
                 let idx = y * WIDTH + x;
-                let diff = (dst_exact[idx] as i16 - dst_approx[idx] as i16).unsigned_abs() as u8;
-                if diff > max_diff {
-                    max_diff = diff;
-                }
+                assert_eq!(
+                    dst_approx[idx], dst_ref[idx],
+                    "Approximation differs from reference at ({}, {}): approx={}, ref={}",
+                    x, y, dst_approx[idx], dst_ref[idx]
+                );
             }
         }
-
-        println!("Scalar implementations completed.");
-        println!(
-            "Input sample  (row 2, cols 1..9): {:?}",
-            &src[2 * WIDTH + 1..2 * WIDTH + 9]
-        );
-        println!(
-            "Exact output  (row 2, cols 1..9): {:?}",
-            &dst_exact[2 * WIDTH + 1..2 * WIDTH + 9]
-        );
-        println!(
-            "Approx output (row 2, cols 1..9): {:?}",
-            &dst_approx[2 * WIDTH + 1..2 * WIDTH + 9]
-        );
-        println!("Max diff between exact and approx: {}", max_diff);
     }
 
     #[cfg(target_arch = "hexagon")]
     {
-        const WIDTH: usize = 256; // Must be multiple of VLEN (128)
-        const HEIGHT: usize = 16;
-
         // Aligned buffers for HVX
         #[repr(align(128))]
         struct AlignedBuf<const N: usize>([u8; N]);
@@ -309,15 +307,12 @@ fn main() {
         let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
         let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]);
         let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
+        let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
 
-        // Create test pattern
-        for y in 0..HEIGHT {
-            for x in 0..WIDTH {
-                src.0[y * WIDTH + x] = ((x + y * 7) % 256) as u8;
-            }
-        }
+        // Generate test pattern
+        generate_test_pattern(&mut src.0, WIDTH, HEIGHT);
 
-        // Run HVX version
+        // Run HVX implementation
         unsafe {
             gaussian3x3u8(
                 src.0.as_ptr(),
@@ -329,32 +324,34 @@ fn main() {
             );
         }
 
-        // Run scalar approximate reference (should match HVX closely)
-        gaussian3x3u8_scalar_approx(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
+        // Run reference
+        gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
+
+        // Run scalar approximation (should match HVX exactly)
+        gaussian3x3u8_approx(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
 
-        // Compare results (skip edges)
-        let mut max_diff = 0u8;
-        let mut diff_count = 0usize;
+        // Verify HVX matches the byte-averaging approximation exactly
         for y in 1..HEIGHT - 1 {
             for x in 1..WIDTH - 1 {
                 let idx = y * WIDTH + x;
-                let diff = (dst_hvx.0[idx] as i16 - dst_ref[idx] as i16).unsigned_abs() as u8;
-                if diff > max_diff {
-                    max_diff = diff;
-                }
-                if diff > 0 {
-                    diff_count += 1;
-                }
+                assert_eq!(
+                    dst_hvx.0[idx], dst_approx[idx],
+                    "HVX output differs from scalar approximation at ({}, {}): hvx={}, approx={}",
+                    x, y, dst_hvx.0[idx], dst_approx[idx]
+                );
             }
         }
 
-        println!("HVX implementation completed.");
-        println!("Max difference from scalar reference: {}", max_diff);
-        println!("Pixels with any difference: {}", diff_count);
-        if max_diff <= 1 {
-            println!("Results match within rounding tolerance!");
-        } else {
-            println!("WARNING: Results differ more than expected.");
+        // Verify HVX exactly matches reference for this test pattern
+        for y in 1..HEIGHT - 1 {
+            for x in 1..WIDTH - 1 {
+                let idx = y * WIDTH + x;
+                assert_eq!(
+                    dst_hvx.0[idx], dst_ref[idx],
+                    "HVX differs from reference at ({}, {}): hvx={}, ref={}",
+                    x, y, dst_hvx.0[idx], dst_ref[idx]
+                );
+            }
         }
     }
 }

From c1ed719fe0f1bb80b3398692438ce79507774239 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Thu, 12 Feb 2026 07:47:01 -0600
Subject: [PATCH 140/326] examples: Fix rustfmt formatting in gaussian.rs

---
 examples/gaussian.rs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index 575f4db8c8..b7d8cad805 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -274,7 +274,8 @@ fn main() {
         for (i, &expected) in expected_ref_row2.iter().enumerate() {
             let actual = dst_ref[2 * WIDTH + 1 + i];
             assert_eq!(
-                actual, expected,
+                actual,
+                expected,
                 "reference mismatch at row 2, col {}: expected {}, got {}",
                 1 + i,
                 expected,

From 13a192b08ce2e69675fa49000dfafeacfcf69145 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Thu, 12 Feb 2026 07:54:58 -0600
Subject: [PATCH 141/326] stdarch-gen-hexagon: Remove unused module_name method

---
 crates/stdarch-gen-hexagon/src/main.rs | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 43317ff41d..590042c37c 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -64,13 +64,6 @@ impl VectorMode {
         self.bytes() / 4 // 32-bit lanes
     }
 
-    fn module_name(&self) -> &'static str {
-        match self {
-            VectorMode::V64 => "v64",
-            VectorMode::V128 => "v128",
-        }
-    }
-
     fn target_feature(&self) -> &'static str {
         match self {
             VectorMode::V64 => "hvx-length64b",

From 66391da0f3cca2794fcc3faec98717c533ad6306 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Thu, 12 Feb 2026 08:03:13 -0600
Subject: [PATCH 142/326] stdarch-gen-hexagon: Fix clippy warnings

- Move regex compilations outside loops
- Use Option::map and or_else instead of manual if-let chains
- Use strip_prefix instead of manual starts_with + slice
- Use !is_empty() instead of len() >= 1
- Combine consecutive str::replace calls
---
 crates/stdarch-gen-hexagon/src/main.rs | 39 ++++++++++++--------------
 1 file changed, 18 insertions(+), 21 deletions(-)

diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 590042c37c..9d4e80f8f2 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -333,10 +333,10 @@ fn parse_prototype(prototype: &str) -> Option<(RustType, Vec<(String, RustType)>
 
         let mut params = Vec::new();
         if !params_str.trim().is_empty() {
+            // Pattern: Type Name or Type* Name
+            let param_re = Regex::new(r"(\w+\*?)\s+(\w+)").unwrap();
             for param in params_str.split(',') {
                 let param = param.trim();
-                // Pattern: Type Name or Type* Name
-                let param_re = Regex::new(r"(\w+\*?)\s+(\w+)").unwrap();
                 if let Some(pcaps) = param_re.captures(param) {
                     let ptype_str = pcaps[1].trim();
                     let pname = pcaps[2].to_lowercase();
@@ -369,6 +369,12 @@ fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
     // Also handle builtins without VECTOR_WRAP
     let simple_builtin_re2 = Regex::new(r"__builtin_HEXAGON_(\w+)\([^)]*\)\s*$").unwrap();
 
+    // Regex to extract Q6 name from #define
+    let q6_name_re = Regex::new(r"#define\s+(Q6_\w+)").unwrap();
+
+    // Regex to extract macro expression body
+    let macro_expr_re = Regex::new(r"#define\s+Q6_\w+\([^)]*\)\s+(.+)").unwrap();
+
     let lines: Vec<&str> = content.lines().collect();
     let mut current_arch: u32 = 60;
     let mut i = 0;
@@ -421,7 +427,6 @@ fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
                 let define_line = lines[j];
 
                 // Extract Q6 name and check if it's simple or compound
-                let q6_name_re = Regex::new(r"#define\s+(Q6_\w+)").unwrap();
                 if let Some(caps) = q6_name_re.captures(define_line) {
                     let q6_name = caps[1].to_string();
 
@@ -434,14 +439,10 @@ fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
                     }
 
                     // Try to extract simple builtin name
-                    let builtin_name = if let Some(bcaps) = simple_builtin_re.captures(&macro_body)
-                    {
-                        Some(bcaps[1].to_string())
-                    } else if let Some(bcaps) = simple_builtin_re2.captures(&macro_body) {
-                        Some(bcaps[1].to_string())
-                    } else {
-                        None
-                    };
+                    let builtin_name = simple_builtin_re
+                        .captures(&macro_body)
+                        .or_else(|| simple_builtin_re2.captures(&macro_body))
+                        .map(|bcaps| bcaps[1].to_string());
 
                     // Check if it's a compound intrinsic (multiple __builtin calls)
                     let builtin_count = macro_body.matches("__builtin_HEXAGON_").count();
@@ -452,11 +453,8 @@ fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
                         if is_compound {
                             // For compound intrinsics, parse the expression
                             // Extract the macro body after the parameter list
-                            let macro_expr_re =
-                                Regex::new(r"#define\s+Q6_\w+\([^)]*\)\s+(.+)").unwrap();
                             if let Some(expr_caps) = macro_expr_re.captures(&macro_body) {
-                                let expr_str =
-                                    expr_caps[1].trim().replace('\n', " ").replace('\\', " ");
+                                let expr_str = expr_caps[1].trim().replace(['\n', '\\'], " ");
                                 let expr_str = expr_str.trim();
 
                                 if let Some(compound_expr) = parse_compound_expr(expr_str) {
@@ -486,11 +484,10 @@ fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
                             }
                         } else if let Some(builtin) = builtin_name {
                             // Extract short instruction name
-                            let instr_name = if builtin.starts_with("V6_") {
-                                builtin[3..].to_string()
-                            } else {
-                                builtin.clone()
-                            };
+                            let instr_name = builtin
+                                .strip_prefix("V6_")
+                                .map(|s| s.to_string())
+                                .unwrap_or_else(|| builtin.clone());
 
                             intrinsics.push(IntrinsicInfo {
                                 q6_name,
@@ -1365,7 +1362,7 @@ fn get_compound_primary_instr(expr: &CompoundExpr) -> Option<String> {
     match expr {
         CompoundExpr::BuiltinCall(name, args) => {
             // For vandqrt wrapper, look inside
-            if name == "vandqrt" && args.len() >= 1 {
+            if name == "vandqrt" && !args.is_empty() {
                 if let Some(inner) = get_compound_primary_instr(&args[0]) {
                     return Some(inner);
                 }

From 1c1b1cfd9d113cee7f267c2c5913c3a1adc980e0 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Thu, 12 Feb 2026 10:41:53 -0600
Subject: [PATCH 143/326] Update Cargo.lock

Updates cc crate to 1.2.55 which fixes macabi target triple
handling for x86_64-apple-ios-macabi builds.
---
 Cargo.lock | 595 ++++++++++++++++++++++++++++++++++-------------------
 1 file changed, 384 insertions(+), 211 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 66dd59a379..36b2b09acb 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -10,18 +10,18 @@ checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa"
 
 [[package]]
 name = "aho-corasick"
-version = "1.1.3"
+version = "1.1.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916"
+checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301"
 dependencies = [
  "memchr",
 ]
 
 [[package]]
 name = "anstream"
-version = "0.6.20"
+version = "0.6.21"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3ae563653d1938f79b1ab1b5e668c87c76a9930414574a6583a7b7e11a8e6192"
+checksum = "43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a"
 dependencies = [
  "anstyle",
  "anstyle-parse",
@@ -34,9 +34,9 @@ dependencies = [
 
 [[package]]
 name = "anstyle"
-version = "1.0.11"
+version = "1.0.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "862ed96ca487e809f1c8e5a8447f6ee2cf102f846893800b20cebdf541fc6bbd"
+checksum = "5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78"
 
 [[package]]
 name = "anstyle-parse"
@@ -49,29 +49,29 @@ dependencies = [
 
 [[package]]
 name = "anstyle-query"
-version = "1.1.4"
+version = "1.1.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9e231f6134f61b71076a3eab506c379d4f36122f2af15a9ff04415ea4c3339e2"
+checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc"
 dependencies = [
- "windows-sys 0.60.2",
+ "windows-sys 0.61.2",
 ]
 
 [[package]]
 name = "anstyle-wincon"
-version = "3.0.10"
+version = "3.0.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3e0633414522a32ffaac8ac6cc8f748e090c5717661fddeea04219e2344f5f2a"
+checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d"
 dependencies = [
  "anstyle",
  "once_cell_polyfill",
- "windows-sys 0.60.2",
+ "windows-sys 0.61.2",
 ]
 
 [[package]]
 name = "anyhow"
-version = "1.0.99"
+version = "1.0.101"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b0674a1ddeecb70197781e945de4b3b8ffb61fa939a5597bcf48503737663100"
+checksum = "5f0e0fee31ef5ed1ba1316088939cea399010ed7731dba877ed44aeb407a75ea"
 
 [[package]]
 name = "assert-instr-macro"
@@ -96,15 +96,15 @@ checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6"
 
 [[package]]
 name = "bitflags"
-version = "2.9.4"
+version = "2.10.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2261d10cca569e4643e526d8dc2e62e433cc8aba21ab764233731f8d369bf394"
+checksum = "812e12b5285cc515a9c72a5c1d3b6d46a19dac5acfef5265968c166106e31dd3"
 
 [[package]]
 name = "cc"
-version = "1.2.36"
+version = "1.2.55"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5252b3d2648e5eedbc1a6f501e3c795e07025c1e93bbf8bbdd6eef7f447a6d54"
+checksum = "47b26a0954ae34af09b50f0de26458fa95369a0d478d8236d3f93082b219bd29"
 dependencies = [
  "find-msvc-tools",
  "shlex",
@@ -112,15 +112,15 @@ dependencies = [
 
 [[package]]
 name = "cfg-if"
-version = "1.0.3"
+version = "1.0.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2fd1289c04a9ea8cb22300a459a72a385d7c73d3259e2ed7dcb2af674838cfa9"
+checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801"
 
 [[package]]
 name = "clap"
-version = "4.5.47"
+version = "4.5.58"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7eac00902d9d136acd712710d71823fb8ac8004ca445a89e73a41d45aa712931"
+checksum = "63be97961acde393029492ce0be7a1af7e323e6bae9511ebfac33751be5e6806"
 dependencies = [
  "clap_builder",
  "clap_derive",
@@ -128,9 +128,9 @@ dependencies = [
 
 [[package]]
 name = "clap_builder"
-version = "4.5.47"
+version = "4.5.58"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2ad9bbf750e73b5884fb8a211a9424a1906c1e156724260fdae972f31d70e1d6"
+checksum = "7f13174bda5dfd69d7e947827e5af4b0f2f94a4a3ee92912fba07a66150f21e2"
 dependencies = [
  "anstream",
  "anstyle",
@@ -140,9 +140,9 @@ dependencies = [
 
 [[package]]
 name = "clap_derive"
-version = "4.5.47"
+version = "4.5.55"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bbfd7eae0b0f1a6e63d4b13c9c478de77c2eb546fba158ad50b4203dc24b9f9c"
+checksum = "a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5"
 dependencies = [
  "heck",
  "proc-macro2",
@@ -152,9 +152,9 @@ dependencies = [
 
 [[package]]
 name = "clap_lex"
-version = "0.7.5"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b94f61472cee1439c0b966b47e3aca9ae07e45d070759512cd390ea2bebc6675"
+checksum = "3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831"
 
 [[package]]
 name = "colorchoice"
@@ -206,9 +206,9 @@ checksum = "d0a5c400df2834b80a4c3327b3aad3a4c4cd4de0629063962b03235697506a28"
 
 [[package]]
 name = "darling"
-version = "0.20.11"
+version = "0.21.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fc7f46116c46ff9ab3eb1597a45688b6715c6e628b5c133e288e709a29bcb4ee"
+checksum = "9cdf337090841a411e2a7f3deb9187445851f91b309c0c0a29e05f74a00a48c0"
 dependencies = [
  "darling_core",
  "darling_macro",
@@ -216,9 +216,9 @@ dependencies = [
 
 [[package]]
 name = "darling_core"
-version = "0.20.11"
+version = "0.21.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0d00b9596d185e565c2207a0b01f8bd1a135483d02d9b7b0a54b11da8d53412e"
+checksum = "1247195ecd7e3c85f83c8d2a366e4210d588e802133e1e355180a9870b517ea4"
 dependencies = [
  "fnv",
  "ident_case",
@@ -230,9 +230,9 @@ dependencies = [
 
 [[package]]
 name = "darling_macro"
-version = "0.20.11"
+version = "0.21.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fc34b93ccb385b40dc71c6fceac4b2ad23662c7eeb248cf10d529b7e055b6ead"
+checksum = "d38308df82d1080de0afee5d069fa14b0326a88c14f15c5ccda35b4a6c414c81"
 dependencies = [
  "darling_core",
  "quote",
@@ -263,10 +263,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719"
 
 [[package]]
-name = "env_logger"
-version = "0.8.4"
+name = "env_filter"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a19187fea3ac7e84da7dacf48de0c45d63c6a76f9490dae389aead16c243fce3"
+checksum = "7a1c3cc8e57274ec99de65301228b537f1e4eedc1b8e0f9411c6caac8ae7308f"
 dependencies = [
  "log",
  "regex",
@@ -285,6 +285,16 @@ dependencies = [
  "termcolor",
 ]
 
+[[package]]
+name = "env_logger"
+version = "0.11.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b2daee4ea451f429a58296525ddf28b45a3b64f1acf6587e2067437bb11e218d"
+dependencies = [
+ "env_filter",
+ "log",
+]
+
 [[package]]
 name = "equivalent"
 version = "1.0.2"
@@ -293,15 +303,15 @@ checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f"
 
 [[package]]
 name = "find-msvc-tools"
-version = "0.1.1"
+version = "0.1.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7fd99930f64d146689264c637b5af2f0233a933bef0d8570e2526bf9e083192d"
+checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582"
 
 [[package]]
 name = "flate2"
-version = "1.1.8"
+version = "1.1.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b375d6465b98090a5f25b1c7703f3859783755aa9a80433b36e0379a3ec2f369"
+checksum = "843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c"
 dependencies = [
  "crc32fast",
  "miniz_oxide",
@@ -313,6 +323,12 @@ version = "1.0.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1"
 
+[[package]]
+name = "foldhash"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
+
 [[package]]
 name = "form_urlencoded"
 version = "1.2.2"
@@ -324,15 +340,29 @@ dependencies = [
 
 [[package]]
 name = "getrandom"
-version = "0.2.16"
+version = "0.2.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "335ff9f135e4384c8150d6f27c6daed433577f86b4750418338c01a1a2528592"
+checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0"
 dependencies = [
  "cfg-if",
  "libc",
  "wasi",
 ]
 
+[[package]]
+name = "getrandom"
+version = "0.4.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "139ef39800118c7683f2fd3c98c1b23c09ae076556b435f8e9064ae108aaeeec"
+dependencies = [
+ "cfg-if",
+ "libc",
+ "r-efi",
+ "rand_core 0.10.0",
+ "wasip2",
+ "wasip3",
+]
+
 [[package]]
 name = "hashbrown"
 version = "0.12.3"
@@ -344,6 +374,15 @@ name = "hashbrown"
 version = "0.15.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1"
+dependencies = [
+ "foldhash",
+]
+
+[[package]]
+name = "hashbrown"
+version = "0.16.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100"
 
 [[package]]
 name = "heck"
@@ -359,9 +398,9 @@ checksum = "fc0fef456e4baa96da950455cd02c081ca953b141298e41db3fc7e36b1da849c"
 
 [[package]]
 name = "humantime"
-version = "2.2.0"
+version = "2.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9b112acc8b3adf4b107a8ec20977da0273a8c386765a3ec0229bd500a1443f9f"
+checksum = "135b12329e5e3ce057a9f972339ea52bc954fe1e9358ef27f95e89716fbc5424"
 
 [[package]]
 name = "icu_collections"
@@ -444,6 +483,12 @@ dependencies = [
  "zerovec",
 ]
 
+[[package]]
+name = "id-arena"
+version = "2.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3d3067d79b975e8844ca9eb072e16b31c3c1c36928edf9c6789548c524d0d954"
+
 [[package]]
 name = "ident_case"
 version = "1.0.1"
@@ -483,12 +528,14 @@ dependencies = [
 
 [[package]]
 name = "indexmap"
-version = "2.11.0"
+version = "2.13.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f2481980430f9f78649238835720ddccc57e52df14ffce1c6f37391d61b563e9"
+checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017"
 dependencies = [
  "equivalent",
- "hashbrown 0.15.5",
+ "hashbrown 0.16.1",
+ "serde",
+ "serde_core",
 ]
 
 [[package]]
@@ -510,20 +557,20 @@ dependencies = [
 
 [[package]]
 name = "is-terminal"
-version = "0.4.16"
+version = "0.4.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e04d7f318608d35d4b61ddd75cbdaee86b023ebe2bd5a66ee0915f0bf93095a9"
+checksum = "3640c1c38b8e4e43584d8df18be5fc6b0aa314ce6ebf51b53313d4306cca8e46"
 dependencies = [
  "hermit-abi",
  "libc",
- "windows-sys 0.59.0",
+ "windows-sys 0.61.2",
 ]
 
 [[package]]
 name = "is_terminal_polyfill"
-version = "1.70.1"
+version = "1.70.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf"
+checksum = "a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695"
 
 [[package]]
 name = "itertools"
@@ -536,15 +583,21 @@ dependencies = [
 
 [[package]]
 name = "itoa"
-version = "1.0.15"
+version = "1.0.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4a5f13b858c8d314ee3e8f639011f7ccefe71f97f96e50151fb991f267928e2c"
+checksum = "92ecc6618181def0457392ccd0ee51198e065e016d1d527a7ac1b6dc7c1f09d2"
+
+[[package]]
+name = "leb128fmt"
+version = "0.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "09edd9e8b54e49e587e4f6295a7d29c3ea94d469cb40ab8ca70b288248a81db2"
 
 [[package]]
 name = "libc"
-version = "0.2.175"
+version = "0.2.181"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6a82ae493e598baaea5209805c49bbf2ea7de956d50d7da0da1164f9c6d28543"
+checksum = "459427e2af2b9c839b132acb702a1c654d95e10f8c326bfc2ad11310e458b1c5"
 
 [[package]]
 name = "linked-hash-map"
@@ -560,15 +613,15 @@ checksum = "6373607a59f0be73a39b6fe456b8192fcc3585f602af20751600e974dd455e77"
 
 [[package]]
 name = "log"
-version = "0.4.28"
+version = "0.4.29"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "34080505efa8e45a4b816c349525ebe327ceaa8559756f0356cba97ef3bf7432"
+checksum = "5e5032e24019045c762d3c0f28f5b6b8bbf38563a65908389bf7978758920897"
 
 [[package]]
 name = "memchr"
-version = "2.7.6"
+version = "2.8.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273"
+checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79"
 
 [[package]]
 name = "miniz_oxide"
@@ -588,9 +641,9 @@ checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d"
 
 [[package]]
 name = "once_cell_polyfill"
-version = "1.70.1"
+version = "1.70.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a4895175b425cb1f87721b59f0f286c2092bd4af812243672510e1ac53e2e0ad"
+checksum = "384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe"
 
 [[package]]
 name = "percent-encoding"
@@ -626,11 +679,21 @@ dependencies = [
  "log",
 ]
 
+[[package]]
+name = "prettyplease"
+version = "0.2.37"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "479ca8adacdd7ce8f1fb39ce9ecccbfe93a3f1344b3d0d97f20bc0196208f62b"
+dependencies = [
+ "proc-macro2",
+ "syn",
+]
+
 [[package]]
 name = "proc-macro2"
-version = "1.0.101"
+version = "1.0.106"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "89ae43fd86e4158d6db51ad8e2b80f313af9cc74f5c0e03ccb87de09998732de"
+checksum = "8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934"
 dependencies = [
  "unicode-ident",
 ]
@@ -657,24 +720,30 @@ dependencies = [
 
 [[package]]
 name = "quickcheck"
-version = "1.0.3"
+version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "588f6378e4dd99458b60ec275b4477add41ce4fa9f64dcba6f15adccb19b50d6"
+checksum = "95c589f335db0f6aaa168a7cd27b1fc6920f5e1470c804f814d9cd6e62a0f70b"
 dependencies = [
- "env_logger 0.8.4",
+ "env_logger 0.11.9",
  "log",
- "rand",
+ "rand 0.10.0",
 ]
 
 [[package]]
 name = "quote"
-version = "1.0.40"
+version = "1.0.44"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1885c039570dc00dcb4ff087a89e185fd56bae234ddc7f056a945bf36467248d"
+checksum = "21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4"
 dependencies = [
  "proc-macro2",
 ]
 
+[[package]]
+name = "r-efi"
+version = "5.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
+
 [[package]]
 name = "rand"
 version = "0.8.5"
@@ -683,7 +752,17 @@ checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404"
 dependencies = [
  "libc",
  "rand_chacha",
- "rand_core",
+ "rand_core 0.6.4",
+]
+
+[[package]]
+name = "rand"
+version = "0.10.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bc266eb313df6c5c09c1c7b1fbe2510961e5bcd3add930c1e31f7ed9da0feff8"
+dependencies = [
+ "getrandom 0.4.1",
+ "rand_core 0.10.0",
 ]
 
 [[package]]
@@ -693,7 +772,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e6c10a63a0fa32252be49d21e7709d4d4baf8d231c2dbce1eaa8141b9b127d88"
 dependencies = [
  "ppv-lite86",
- "rand_core",
+ "rand_core 0.6.4",
 ]
 
 [[package]]
@@ -702,9 +781,15 @@ version = "0.6.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c"
 dependencies = [
- "getrandom",
+ "getrandom 0.2.17",
 ]
 
+[[package]]
+name = "rand_core"
+version = "0.10.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0c8d0fd677905edcbeedbf2edb6494d676f0e98d54d5cf9bda0b061cb8fb8aba"
+
 [[package]]
 name = "rayon"
 version = "1.11.0"
@@ -727,9 +812,9 @@ dependencies = [
 
 [[package]]
 name = "regex"
-version = "1.11.2"
+version = "1.12.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "23d7fd106d8c02486a8d64e778353d1cffe08ce79ac2e82f540c86d0facf6912"
+checksum = "e10754a14b9137dd7b1e3e5b0493cc9171fdd105e0ab477f51b72e7f3ac0e276"
 dependencies = [
  "aho-corasick",
  "memchr",
@@ -739,9 +824,9 @@ dependencies = [
 
 [[package]]
 name = "regex-automata"
-version = "0.4.10"
+version = "0.4.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6b9458fa0bfeeac22b5ca447c63aaf45f28439a709ccd244698632f9aa6394d6"
+checksum = "6e1dd4122fc1595e8162618945476892eefca7b88c52820e74af6262213cae8f"
 dependencies = [
  "aho-corasick",
  "memchr",
@@ -750,9 +835,9 @@ dependencies = [
 
 [[package]]
 name = "regex-syntax"
-version = "0.8.6"
+version = "0.8.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "caf4aa5b0f434c91fe5c7f1ecb6a5ece2130b02ad2a590589dda5146df959001"
+checksum = "a96887878f22d7bad8a3b6dc5b7440e0ada9a245242924394987b21cf2210a4c"
 
 [[package]]
 name = "ring"
@@ -762,7 +847,7 @@ checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7"
 dependencies = [
  "cc",
  "cfg-if",
- "getrandom",
+ "getrandom 0.2.17",
  "libc",
  "untrusted",
  "windows-sys 0.52.0",
@@ -770,9 +855,9 @@ dependencies = [
 
 [[package]]
 name = "rustc-demangle"
-version = "0.1.26"
+version = "0.1.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "56f7d92ca342cea22a06f2121d944b4fd82af56988c270852495420f961d4ace"
+checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d"
 
 [[package]]
 name = "rustls"
@@ -811,9 +896,9 @@ dependencies = [
 
 [[package]]
 name = "ryu"
-version = "1.0.20"
+version = "1.0.23"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "28d3b2b1366ec20994f1fd18c3c594f05c5dd4bc44d8bb0c1c632c8d6829481f"
+checksum = "9774ba4a74de5f7b1c1451ed6cd5285a32eddb5cccb8cc655a4e50009e06477f"
 
 [[package]]
 name = "same-file"
@@ -826,36 +911,46 @@ dependencies = [
 
 [[package]]
 name = "semver"
-version = "1.0.26"
+version = "1.0.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "56e6fa9c48d24d85fb3de5ad847117517440f6beceb7798af16b4a87d616b8d0"
+checksum = "d767eb0aabc880b29956c35734170f26ed551a859dbd361d140cdbeca61ab1e2"
 
 [[package]]
 name = "serde"
-version = "1.0.219"
+version = "1.0.228"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5f0e2c6ed6606019b4e29e69dbaba95b11854410e5347d525002456dbbb786b6"
+checksum = "9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e"
 dependencies = [
+ "serde_core",
  "serde_derive",
 ]
 
 [[package]]
 name = "serde-xml-rs"
-version = "0.8.1"
+version = "0.8.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "53630160a98edebde0123eb4dfd0fce6adff091b2305db3154a9e920206eb510"
+checksum = "cc2215ce3e6a77550b80a1c37251b7d294febaf42e36e21b7b411e0bf54d540d"
 dependencies = [
  "log",
  "serde",
  "thiserror",
- "xml-rs",
+ "xml",
+]
+
+[[package]]
+name = "serde_core"
+version = "1.0.228"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad"
+dependencies = [
+ "serde_derive",
 ]
 
 [[package]]
 name = "serde_derive"
-version = "1.0.219"
+version = "1.0.228"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5b0276cf7f2c73365f7157c8123c21cd9a50fbbd844757af28ca1f5925fc2a00"
+checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -864,32 +959,32 @@ dependencies = [
 
 [[package]]
 name = "serde_json"
-version = "1.0.143"
+version = "1.0.149"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d401abef1d108fbd9cbaebc3e46611f4b1021f714a0597a71f41ee463f5f4a5a"
+checksum = "83fc039473c5595ace860d8c4fafa220ff474b3fc6bfdb4293327f1a37e94d86"
 dependencies = [
  "itoa",
  "memchr",
- "ryu",
  "serde",
+ "serde_core",
+ "zmij",
 ]
 
 [[package]]
 name = "serde_with"
-version = "3.14.0"
+version = "3.16.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f2c45cd61fefa9db6f254525d46e392b852e0e61d9a1fd36e5bd183450a556d5"
+checksum = "4fa237f2807440d238e0364a218270b98f767a00d3dada77b1c53ae88940e2e7"
 dependencies = [
- "serde",
- "serde_derive",
+ "serde_core",
  "serde_with_macros",
 ]
 
 [[package]]
 name = "serde_with_macros"
-version = "3.14.0"
+version = "3.16.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "de90945e6565ce0d9a25098082ed4ee4002e047cb59892c318d66821e14bb30f"
+checksum = "52a8e3ca0ca629121f70ab50f95249e5a6f925cc0f6ffe8256c45b728875706c"
 dependencies = [
  "darling",
  "proc-macro2",
@@ -968,7 +1063,7 @@ dependencies = [
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
 dependencies = [
- "rand",
+ "rand 0.8.5",
 ]
 
 [[package]]
@@ -1001,7 +1096,7 @@ version = "0.0.0"
 dependencies = [
  "core_arch",
  "quickcheck",
- "rand",
+ "rand 0.8.5",
 ]
 
 [[package]]
@@ -1018,9 +1113,9 @@ checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292"
 
 [[package]]
 name = "syn"
-version = "2.0.106"
+version = "2.0.115"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ede7c438028d4436d71104916910f5bb611972c5cfd7f89b8300a8186e6fada6"
+checksum = "6e614ed320ac28113fa64972c4262d5dbc89deacdfd00c34a3e4cea073243c12"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -1055,18 +1150,18 @@ dependencies = [
 
 [[package]]
 name = "thiserror"
-version = "1.0.69"
+version = "2.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b6aaf5339b578ea85b50e080feb250a3e8ae8cfcdff9a461c9ec2904bc923f52"
+checksum = "4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4"
 dependencies = [
  "thiserror-impl",
 ]
 
 [[package]]
 name = "thiserror-impl"
-version = "1.0.69"
+version = "2.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4fee6c4efc90059e10f81e6d42c60a18f76588c3d74cb83a0b242a2b6c7504c1"
+checksum = "ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -1085,9 +1180,15 @@ dependencies = [
 
 [[package]]
 name = "unicode-ident"
-version = "1.0.18"
+version = "1.0.23"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "537dd038a89878be9b64dd4bd1b260315c1bb94f4d784956b81e27a088d9a09e"
+
+[[package]]
+name = "unicode-xid"
+version = "0.2.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512"
+checksum = "ebc1c04c71510c7f702b52b7c350734c9ff1295c464a03335b00bb84fc54f853"
 
 [[package]]
 name = "untrusted"
@@ -1151,6 +1252,46 @@ version = "0.11.1+wasi-snapshot-preview1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
 
+[[package]]
+name = "wasip2"
+version = "1.0.2+wasi-0.2.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9517f9239f02c069db75e65f174b3da828fe5f5b945c4dd26bd25d89c03ebcf5"
+dependencies = [
+ "wit-bindgen",
+]
+
+[[package]]
+name = "wasip3"
+version = "0.4.0+wasi-0.3.0-rc-2026-01-06"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5428f8bf88ea5ddc08faddef2ac4a67e390b88186c703ce6dbd955e1c145aca5"
+dependencies = [
+ "wit-bindgen",
+]
+
+[[package]]
+name = "wasm-encoder"
+version = "0.244.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "990065f2fe63003fe337b932cfb5e3b80e0b4d0f5ff650e6985b1048f62c8319"
+dependencies = [
+ "leb128fmt",
+ "wasmparser 0.244.0",
+]
+
+[[package]]
+name = "wasm-metadata"
+version = "0.244.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bb0e353e6a2fbdc176932bbaab493762eb1255a7900fe0fea1a2f96c296cc909"
+dependencies = [
+ "anyhow",
+ "indexmap 2.13.0",
+ "wasm-encoder",
+ "wasmparser 0.244.0",
+]
+
 [[package]]
 name = "wasmparser"
 version = "0.235.0"
@@ -1158,7 +1299,19 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917"
 dependencies = [
  "bitflags",
- "indexmap 2.11.0",
+ "indexmap 2.13.0",
+ "semver",
+]
+
+[[package]]
+name = "wasmparser"
+version = "0.244.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "47b807c72e1bac69382b3a6fb3dbe8ea4c0ed87ff5629b8685ae6b9a611028fe"
+dependencies = [
+ "bitflags",
+ "hashbrown 0.15.5",
+ "indexmap 2.13.0",
  "semver",
 ]
 
@@ -1170,7 +1323,7 @@ checksum = "75aa8e9076de6b9544e6dab4badada518cca0bf4966d35b131bbd057aed8fa0a"
 dependencies = [
  "anyhow",
  "termcolor",
- "wasmparser",
+ "wasmparser 0.235.0",
 ]
 
 [[package]]
@@ -1179,32 +1332,32 @@ version = "0.26.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "521bc38abb08001b01866da9f51eb7c5d647a19260e00054a8c7fd5f9e57f7a9"
 dependencies = [
- "webpki-roots 1.0.5",
+ "webpki-roots 1.0.6",
 ]
 
 [[package]]
 name = "webpki-roots"
-version = "1.0.5"
+version = "1.0.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "12bed680863276c63889429bfd6cab3b99943659923822de1c8a39c49e4d722c"
+checksum = "22cfaf3c063993ff62e73cb4311efde4db1efb31ab78a3e5c457939ad5cc0bed"
 dependencies = [
  "rustls-pki-types",
 ]
 
 [[package]]
 name = "winapi-util"
-version = "0.1.10"
+version = "0.1.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0978bf7171b3d90bac376700cb56d606feb40f251a475a5d6634613564460b22"
+checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22"
 dependencies = [
- "windows-sys 0.60.2",
+ "windows-sys 0.61.2",
 ]
 
 [[package]]
 name = "windows-link"
-version = "0.1.3"
+version = "0.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5e6ad25900d524eaabdbbb96d20b4311e1e7ae1699af4fb28c17ae66c80d798a"
+checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
 
 [[package]]
 name = "windows-sys"
@@ -1212,25 +1365,16 @@ version = "0.52.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d"
 dependencies = [
- "windows-targets 0.52.6",
+ "windows-targets",
 ]
 
 [[package]]
 name = "windows-sys"
-version = "0.59.0"
+version = "0.61.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1e38bc4d79ed67fd075bcc251a1c39b32a1776bbe92e5bef1f0bf1f8c531853b"
+checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc"
 dependencies = [
- "windows-targets 0.52.6",
-]
-
-[[package]]
-name = "windows-sys"
-version = "0.60.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb"
-dependencies = [
- "windows-targets 0.53.3",
+ "windows-link",
 ]
 
 [[package]]
@@ -1239,31 +1383,14 @@ version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973"
 dependencies = [
- "windows_aarch64_gnullvm 0.52.6",
- "windows_aarch64_msvc 0.52.6",
- "windows_i686_gnu 0.52.6",
- "windows_i686_gnullvm 0.52.6",
- "windows_i686_msvc 0.52.6",
- "windows_x86_64_gnu 0.52.6",
- "windows_x86_64_gnullvm 0.52.6",
- "windows_x86_64_msvc 0.52.6",
-]
-
-[[package]]
-name = "windows-targets"
-version = "0.53.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d5fe6031c4041849d7c496a8ded650796e7b6ecc19df1a431c1a363342e5dc91"
-dependencies = [
- "windows-link",
- "windows_aarch64_gnullvm 0.53.0",
- "windows_aarch64_msvc 0.53.0",
- "windows_i686_gnu 0.53.0",
- "windows_i686_gnullvm 0.53.0",
- "windows_i686_msvc 0.53.0",
- "windows_x86_64_gnu 0.53.0",
- "windows_x86_64_gnullvm 0.53.0",
- "windows_x86_64_msvc 0.53.0",
+ "windows_aarch64_gnullvm",
+ "windows_aarch64_msvc",
+ "windows_i686_gnu",
+ "windows_i686_gnullvm",
+ "windows_i686_msvc",
+ "windows_x86_64_gnu",
+ "windows_x86_64_gnullvm",
+ "windows_x86_64_msvc",
 ]
 
 [[package]]
@@ -1272,36 +1399,18 @@ version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3"
 
-[[package]]
-name = "windows_aarch64_gnullvm"
-version = "0.53.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "86b8d5f90ddd19cb4a147a5fa63ca848db3df085e25fee3cc10b39b6eebae764"
-
 [[package]]
 name = "windows_aarch64_msvc"
 version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469"
 
-[[package]]
-name = "windows_aarch64_msvc"
-version = "0.53.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c7651a1f62a11b8cbd5e0d42526e55f2c99886c77e007179efff86c2b137e66c"
-
 [[package]]
 name = "windows_i686_gnu"
 version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b"
 
-[[package]]
-name = "windows_i686_gnu"
-version = "0.53.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c1dc67659d35f387f5f6c479dc4e28f1d4bb90ddd1a5d3da2e5d97b42d6272c3"
-
 [[package]]
 name = "windows_i686_gnullvm"
 version = "0.52.6"
@@ -1309,58 +1418,116 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66"
 
 [[package]]
-name = "windows_i686_gnullvm"
-version = "0.53.0"
+name = "windows_i686_msvc"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ce6ccbdedbf6d6354471319e781c0dfef054c81fbc7cf83f338a4296c0cae11"
+checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66"
 
 [[package]]
-name = "windows_i686_msvc"
+name = "windows_x86_64_gnu"
 version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66"
+checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78"
 
 [[package]]
-name = "windows_i686_msvc"
-version = "0.53.0"
+name = "windows_x86_64_gnullvm"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "581fee95406bb13382d2f65cd4a908ca7b1e4c2f1917f143ba16efe98a589b5d"
+checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
 
 [[package]]
-name = "windows_x86_64_gnu"
+name = "windows_x86_64_msvc"
 version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78"
+checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
 
 [[package]]
-name = "windows_x86_64_gnu"
-version = "0.53.0"
+name = "wit-bindgen"
+version = "0.51.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2e55b5ac9ea33f2fc1716d1742db15574fd6fc8dadc51caab1c16a3d3b4190ba"
+checksum = "d7249219f66ced02969388cf2bb044a09756a083d0fab1e566056b04d9fbcaa5"
+dependencies = [
+ "wit-bindgen-rust-macro",
+]
 
 [[package]]
-name = "windows_x86_64_gnullvm"
-version = "0.52.6"
+name = "wit-bindgen-core"
+version = "0.51.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
+checksum = "ea61de684c3ea68cb082b7a88508a8b27fcc8b797d738bfc99a82facf1d752dc"
+dependencies = [
+ "anyhow",
+ "heck",
+ "wit-parser",
+]
 
 [[package]]
-name = "windows_x86_64_gnullvm"
-version = "0.53.0"
+name = "wit-bindgen-rust"
+version = "0.51.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0a6e035dd0599267ce1ee132e51c27dd29437f63325753051e71dd9e42406c57"
+checksum = "b7c566e0f4b284dd6561c786d9cb0142da491f46a9fbed79ea69cdad5db17f21"
+dependencies = [
+ "anyhow",
+ "heck",
+ "indexmap 2.13.0",
+ "prettyplease",
+ "syn",
+ "wasm-metadata",
+ "wit-bindgen-core",
+ "wit-component",
+]
 
 [[package]]
-name = "windows_x86_64_msvc"
-version = "0.52.6"
+name = "wit-bindgen-rust-macro"
+version = "0.51.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
+checksum = "0c0f9bfd77e6a48eccf51359e3ae77140a7f50b1e2ebfe62422d8afdaffab17a"
+dependencies = [
+ "anyhow",
+ "prettyplease",
+ "proc-macro2",
+ "quote",
+ "syn",
+ "wit-bindgen-core",
+ "wit-bindgen-rust",
+]
 
 [[package]]
-name = "windows_x86_64_msvc"
-version = "0.53.0"
+name = "wit-component"
+version = "0.244.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9d66ea20e9553b30172b5e831994e35fbde2d165325bec84fc43dbf6f4eb9cb2"
+dependencies = [
+ "anyhow",
+ "bitflags",
+ "indexmap 2.13.0",
+ "log",
+ "serde",
+ "serde_derive",
+ "serde_json",
+ "wasm-encoder",
+ "wasm-metadata",
+ "wasmparser 0.244.0",
+ "wit-parser",
+]
+
+[[package]]
+name = "wit-parser"
+version = "0.244.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486"
+checksum = "ecc8ac4bc1dc3381b7f59c34f00b67e18f910c2c0f50015669dde7def656a736"
+dependencies = [
+ "anyhow",
+ "id-arena",
+ "indexmap 2.13.0",
+ "log",
+ "semver",
+ "serde",
+ "serde_derive",
+ "serde_json",
+ "unicode-xid",
+ "wasmparser 0.244.0",
+]
 
 [[package]]
 name = "writeable"
@@ -1369,10 +1536,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "9edde0db4769d2dc68579893f2306b26c6ecfbe0ef499b013d731b7b9247e0b9"
 
 [[package]]
-name = "xml-rs"
-version = "0.8.27"
+name = "xml"
+version = "1.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6fd8403733700263c6eb89f192880191f1b83e332f7a20371ddcf421c4a337c7"
+checksum = "b8aa498d22c9bbaf482329839bc5620c46be275a19a812e9a22a2b07529a642a"
 
 [[package]]
 name = "yaml-rust"
@@ -1408,18 +1575,18 @@ dependencies = [
 
 [[package]]
 name = "zerocopy"
-version = "0.8.27"
+version = "0.8.39"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c"
+checksum = "db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a"
 dependencies = [
  "zerocopy-derive",
 ]
 
 [[package]]
 name = "zerocopy-derive"
-version = "0.8.27"
+version = "0.8.39"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831"
+checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -1485,3 +1652,9 @@ dependencies = [
  "quote",
  "syn",
 ]
+
+[[package]]
+name = "zmij"
+version = "1.0.21"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa"

From 046bb76c50ba54776264c26896261989e46a93c3 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Thu, 12 Feb 2026 11:39:37 -0600
Subject: [PATCH 144/326] examples: Simplify gaussian.rs with cfg gate

Add `#![cfg(target_arch = "hexagon")]`

- Remove redundant #[cfg(target_arch = "hexagon")] from functions
- Simplify import and constant cfg conditions
- Remove non-Hexagon test code branch from main()
---
 examples/gaussian.rs | 171 +++++++++++++++----------------------------
 1 file changed, 58 insertions(+), 113 deletions(-)

diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index b7d8cad805..3e9d89db97 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -29,8 +29,9 @@
 //!     qemu-hexagon -L <sysroot>/target/hexagon-unknown-linux-musl \
 //!         target/hexagon-unknown-linux-musl/debug/gaussian
 
-#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))]
-#![cfg_attr(target_arch = "hexagon", feature(hexagon_target_feature))]
+#![cfg(target_arch = "hexagon")]
+#![feature(stdarch_hexagon)]
+#![feature(hexagon_target_feature)]
 #![allow(
     unsafe_op_in_unsafe_fn,
     clippy::unwrap_used,
@@ -41,19 +42,23 @@
     dead_code
 )]
 
-#[cfg(all(target_arch = "hexagon", not(target_feature = "hvx-length128b")))]
+#[cfg(not(target_feature = "hvx-length128b"))]
 use core_arch::arch::hexagon::v64::*;
-#[cfg(all(target_arch = "hexagon", target_feature = "hvx-length128b"))]
+#[cfg(target_feature = "hvx-length128b")]
 use core_arch::arch::hexagon::v128::*;
 
 /// Vector length in bytes for HVX 128-byte mode
-#[cfg(all(target_arch = "hexagon", target_feature = "hvx-length128b"))]
+#[cfg(target_feature = "hvx-length128b")]
 const VLEN: usize = 128;
 
 /// Vector length in bytes for HVX 64-byte mode
-#[cfg(all(target_arch = "hexagon", not(target_feature = "hvx-length128b")))]
+#[cfg(not(target_feature = "hvx-length128b"))]
 const VLEN: usize = 64;
 
+/// Image width - must be multiple of VLEN
+const WIDTH: usize = 256;
+const HEIGHT: usize = 16;
+
 /// Vertical 1-2-1 filter pass using byte averaging
 ///
 /// Computes: dst[x] = avg(avg(row_above[x], row_below[x]), center[x])
@@ -65,7 +70,6 @@ const VLEN: usize = 64;
 /// - `dst` must point to a valid output buffer for `width` bytes
 /// - `width` must be a multiple of VLEN
 /// - All pointers must be HVX-aligned (128-byte for 128B mode)
-#[cfg(target_arch = "hexagon")]
 #[target_feature(enable = "hvxv60")]
 unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) {
     let inp0 = src.offset(-stride) as *const HvxVector;
@@ -101,7 +105,6 @@ unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *m
 /// - `src` and `dst` must point to valid buffers of `width` bytes
 /// - `width` must be a multiple of VLEN
 /// - All pointers must be HVX-aligned
-#[cfg(target_arch = "hexagon")]
 #[target_feature(enable = "hvxv60")]
 unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
     let inp = src as *const HvxVector;
@@ -153,7 +156,6 @@ unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
 /// - `width` must be a multiple of VLEN and >= VLEN
 /// - `stride` must be >= `width`
 /// - All buffers must be HVX-aligned (128-byte for 128B mode)
-#[cfg(target_arch = "hexagon")]
 #[target_feature(enable = "hvxv60")]
 pub unsafe fn gaussian3x3u8(
     src: *const u8,
@@ -234,7 +236,7 @@ fn gaussian3x3u8_approx(src: &[u8], stride: usize, width: usize, height: usize,
     }
 }
 
-/// Generate deterministic test pattern matching test approach
+/// Generate deterministic test pattern
 fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) {
     for y in 0..height {
         for x in 0..width {
@@ -244,115 +246,58 @@ fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) {
 }
 
 fn main() {
-    // Test dimensions
-    #[cfg(not(target_arch = "hexagon"))]
-    const WIDTH: usize = 128;
-    #[cfg(target_arch = "hexagon")]
-    const WIDTH: usize = 256; // Must be multiple of VLEN (128)
-    const HEIGHT: usize = 16;
-
-    #[cfg(not(target_arch = "hexagon"))]
-    {
-        let mut src = vec![0u8; WIDTH * HEIGHT];
-        let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
-        let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
-
-        // Generate test pattern
-        generate_test_pattern(&mut src, WIDTH, HEIGHT);
-
-        // Run reference implementation
-        gaussian3x3u8_reference(&src, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
-
-        // Run byte-averaging approximation (matches HVX behavior)
-        gaussian3x3u8_approx(&src, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
-
-        // Verify specific output values from reference
-        // These are computed using the exact algorithm on our test pattern
-        // Row 2, cols 1..9 with input pattern ((x + y*7) % 256)
-        // Input: row1=[7,8,9,...], row2=[14,15,16,...], row3=[21,22,23,...]
-        let expected_ref_row2: [u8; 8] = [15, 16, 17, 18, 19, 20, 21, 22];
-        for (i, &expected) in expected_ref_row2.iter().enumerate() {
-            let actual = dst_ref[2 * WIDTH + 1 + i];
+    // Aligned buffers for HVX
+    #[repr(align(128))]
+    struct AlignedBuf<const N: usize>([u8; N]);
+
+    let mut src = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
+    let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
+    let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]);
+    let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
+    let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
+
+    // Generate test pattern
+    generate_test_pattern(&mut src.0, WIDTH, HEIGHT);
+
+    // Run HVX implementation
+    unsafe {
+        gaussian3x3u8(
+            src.0.as_ptr(),
+            WIDTH,
+            WIDTH,
+            HEIGHT,
+            dst_hvx.0.as_mut_ptr(),
+            tmp.0.as_mut_ptr(),
+        );
+    }
+
+    // Run reference
+    gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
+
+    // Run scalar approximation (should match HVX exactly)
+    gaussian3x3u8_approx(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
+
+    // Verify HVX matches the byte-averaging approximation exactly
+    for y in 1..HEIGHT - 1 {
+        for x in 1..WIDTH - 1 {
+            let idx = y * WIDTH + x;
             assert_eq!(
-                actual,
-                expected,
-                "reference mismatch at row 2, col {}: expected {}, got {}",
-                1 + i,
-                expected,
-                actual
+                dst_hvx.0[idx], dst_approx[idx],
+                "HVX output differs from scalar approximation at ({}, {}): hvx={}, approx={}",
+                x, y, dst_hvx.0[idx], dst_approx[idx]
             );
         }
-
-        // Verify approximation exactly matches reference for this test pattern
-        // The byte-averaging approach avg(avg(a,c), b) produces identical results
-        // to the Hexagon SDK's (1*a + 2*b + 1*c + 2) / 4 for this input pattern
-        for y in 1..HEIGHT - 1 {
-            for x in 1..WIDTH - 1 {
-                let idx = y * WIDTH + x;
-                assert_eq!(
-                    dst_approx[idx], dst_ref[idx],
-                    "Approximation differs from reference at ({}, {}): approx={}, ref={}",
-                    x, y, dst_approx[idx], dst_ref[idx]
-                );
-            }
-        }
     }
 
-    #[cfg(target_arch = "hexagon")]
-    {
-        // Aligned buffers for HVX
-        #[repr(align(128))]
-        struct AlignedBuf<const N: usize>([u8; N]);
-
-        let mut src = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
-        let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
-        let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]);
-        let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
-        let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
-
-        // Generate test pattern
-        generate_test_pattern(&mut src.0, WIDTH, HEIGHT);
-
-        // Run HVX implementation
-        unsafe {
-            gaussian3x3u8(
-                src.0.as_ptr(),
-                WIDTH,
-                WIDTH,
-                HEIGHT,
-                dst_hvx.0.as_mut_ptr(),
-                tmp.0.as_mut_ptr(),
+    // Verify HVX exactly matches reference for this test pattern
+    for y in 1..HEIGHT - 1 {
+        for x in 1..WIDTH - 1 {
+            let idx = y * WIDTH + x;
+            assert_eq!(
+                dst_hvx.0[idx], dst_ref[idx],
+                "HVX differs from reference at ({}, {}): hvx={}, ref={}",
+                x, y, dst_hvx.0[idx], dst_ref[idx]
             );
         }
-
-        // Run reference
-        gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
-
-        // Run scalar approximation (should match HVX exactly)
-        gaussian3x3u8_approx(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
-
-        // Verify HVX matches the byte-averaging approximation exactly
-        for y in 1..HEIGHT - 1 {
-            for x in 1..WIDTH - 1 {
-                let idx = y * WIDTH + x;
-                assert_eq!(
-                    dst_hvx.0[idx], dst_approx[idx],
-                    "HVX output differs from scalar approximation at ({}, {}): hvx={}, approx={}",
-                    x, y, dst_hvx.0[idx], dst_approx[idx]
-                );
-            }
-        }
-
-        // Verify HVX exactly matches reference for this test pattern
-        for y in 1..HEIGHT - 1 {
-            for x in 1..WIDTH - 1 {
-                let idx = y * WIDTH + x;
-                assert_eq!(
-                    dst_hvx.0[idx], dst_ref[idx],
-                    "HVX differs from reference at ({}, {}): hvx={}, ref={}",
-                    x, y, dst_hvx.0[idx], dst_ref[idx]
-                );
-            }
-        }
     }
 }

From 26b5826d7e4043dd608ab1469ff6a06cdf29f893 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 14 Feb 2026 18:54:35 +0100
Subject: [PATCH 145/326] use `intrinsics::simd` for 'shift right and insert'

---
 .../core_arch/src/aarch64/neon/generated.rs   | 76 +++----------------
 crates/core_arch/src/aarch64/neon/mod.rs      | 24 ++++++
 .../spec/neon/aarch64.spec.yml                | 31 +++-----
 3 files changed, 45 insertions(+), 86 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index a81914af78..30c7db3f27 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -25530,14 +25530,7 @@ pub fn vsqrth_f16(a: f16) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v8i8"
-        )]
-        fn _vsri_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t;
-    }
-    unsafe { _vsri_n_s8(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u8, 8, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
@@ -25548,14 +25541,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v16i8"
-        )]
-        fn _vsriq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t;
-    }
-    unsafe { _vsriq_n_s8(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u8, 16, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
@@ -25566,14 +25552,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v4i16"
-        )]
-        fn _vsri_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t;
-    }
-    unsafe { _vsri_n_s16(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u16, 4, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
@@ -25584,14 +25563,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v8i16"
-        )]
-        fn _vsriq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t;
-    }
-    unsafe { _vsriq_n_s16(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u16, 8, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
@@ -25602,14 +25574,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v2i32"
-        )]
-        fn _vsri_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t;
-    }
-    unsafe { _vsri_n_s32(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u32, 2, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
@@ -25620,14 +25585,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v4i32"
-        )]
-        fn _vsriq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t;
-    }
-    unsafe { _vsriq_n_s32(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u32, 4, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
@@ -25638,14 +25596,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     static_assert!(N >= 1 && N <= 64);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v1i64"
-        )]
-        fn _vsri_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t;
-    }
-    unsafe { _vsri_n_s64(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u64, 1, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
@@ -25656,14 +25607,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     static_assert!(N >= 1 && N <= 64);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.vsri.v2i64"
-        )]
-        fn _vsriq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t;
-    }
-    unsafe { _vsriq_n_s64(a, b, N) }
+    unsafe { super::shift_right_and_insert!(u64, 2, N, a, b) }
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
@@ -25825,7 +25769,7 @@ pub fn vsriq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))]
 pub fn vsrid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
     static_assert!(N >= 1 && N <= 64);
     unsafe { transmute(vsri_n_s64::<N>(transmute(a), transmute(b))) }
@@ -25836,7 +25780,7 @@ pub fn vsrid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))]
 pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
     static_assert!(N >= 1 && N <= 64);
     unsafe { transmute(vsri_n_u64::<N>(transmute(a), transmute(b))) }
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 580f203ef0..135d0a156d 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -70,6 +70,30 @@ pub struct float64x2x4_t(
     pub float64x2_t,
 );
 
+/// Helper for the 'shift right and insert' functions.
+macro_rules! shift_right_and_insert {
+    ($ty:ty, $width:literal, $N:expr, $a:expr, $b:expr) => {{
+        type V = Simd<$ty, $width>;
+
+        if $N as u32 == <$ty>::BITS {
+            $a
+        } else {
+            let a: V = transmute($a);
+            let b: V = transmute($b);
+
+            let mask = <$ty>::MAX >> $N;
+            let kept: V = simd_and(a, V::splat(!mask));
+
+            let shift_counts = V::splat($N as $ty);
+            let shifted = simd_shr(b, shift_counts);
+
+            transmute(simd_or(kept, shifted))
+        }
+    }};
+}
+
+pub(crate) use shift_right_and_insert;
+
 /// Duplicate vector element to vector or scalar
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 1c95bbe3d3..ed6989d44a 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -10166,7 +10166,7 @@ intrinsics:
     attr:
       - *neon-stable
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sri, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [bfxil, 'N = 2']]}]]
     safety: safe
     types:
       - i64
@@ -13722,26 +13722,17 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x8_t,  'N >= 1 && N <= 8']
-      - [int8x16_t, 'N >= 1 && N <= 8']
-      - [int16x4_t, 'N >= 1 && N <= 16']
-      - [int16x8_t, 'N >= 1 && N <= 16']
-      - [int32x2_t, 'N >= 1 && N <= 32']
-      - [int32x4_t, 'N >= 1 && N <= 32']
-      - [int64x1_t, 'N >= 1 && N <= 64']
-      - [int64x2_t, 'N >= 1 && N <= 64']
+      - [int8x8_t, u8, '8', 'N >= 1 && N <= 8']
+      - [int8x16_t, u8, '16', 'N >= 1 && N <= 8']
+      - [int16x4_t, u16, '4', 'N >= 1 && N <= 16']
+      - [int16x8_t, u16, '8', 'N >= 1 && N <= 16']
+      - [int32x2_t, u32, '2', 'N >= 1 && N <= 32']
+      - [int32x4_t, u32, '4', 'N >= 1 && N <= 32']
+      - [int64x1_t, u64, '1', 'N >= 1 && N <= 64']
+      - [int64x2_t, u64, '2', 'N >= 1 && N <= 64']
     compose:
-      - FnCall: ['static_assert!', ['{type[1]}']]
-      - LLVMLink:
-          name: "vsri{neon_type[0].N}"
-          arguments:
-            - "a: {neon_type[0]}"
-            - "b: {neon_type[0]}"
-            - "n: i32"
-          links:
-            - link: "llvm.aarch64.neon.vsri.{neon_type[0]}"
-              arch: aarch64,arm64ec
-      - FnCall: ["_vsri{neon_type[0].N}", [a, b, N], [], true]
+      - FnCall: ['static_assert!', ['{type[3]}']]
+      - FnCall: ["super::shift_right_and_insert!", ['{type[1]}', '{type[2]}', N, a, b], [], true]
 
   - name: "vsri{neon_type[0].N}"
     doc: "Shift Right and Insert (immediate)"

From dbd7c8659b43c7e3e98de9fd4fe06c18dd9c740e Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Sun, 15 Feb 2026 00:17:18 -0600
Subject: [PATCH 146/326] examples: Use HvxVectorPair for precise Gaussian blur
 arithmetic

Update the Gaussian 3x3 blur example to use HvxVectorPair widening
operations. This demonstrates that HvxVectorPair intrinsics now work
 correctly with the updated nightly.

- Add #![cfg(target_arch = "hexagon")] crate-level gate
---
 examples/Cargo.toml  |   5 ++
 examples/gaussian.rs | 173 ++++++++++++++++++++++---------------------
 2 files changed, 92 insertions(+), 86 deletions(-)

diff --git a/examples/Cargo.toml b/examples/Cargo.toml
index 1e893dc15f..8ac14d3e44 100644
--- a/examples/Cargo.toml
+++ b/examples/Cargo.toml
@@ -10,6 +10,10 @@ description = "Examples of the stdarch crate."
 edition = "2024"
 default-run = "hex"
 
+[features]
+# Enable to build Hexagon-specific examples (requires hexagon target)
+hexagon = []
+
 [dependencies]
 core_arch = { path = "../crates/core_arch" }
 quickcheck = "1.0"
@@ -26,6 +30,7 @@ path = "connect5.rs"
 [[bin]]
 name = "gaussian"
 path = "gaussian.rs"
+required-features = ["hexagon"]
 
 [[example]]
 name = "wasm"
diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index 3e9d89db97..61fb5e68c6 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -9,19 +9,19 @@
 //!     1 2 1
 //!
 //! This is a separable filter: `[1 2 1]^T * [1 2 1] / 16`.
-//! Each 1D pass of `[1 2 1] / 4` is computed using byte averaging:
-//!     avg(avg(a, c), b) ≈ (a + 2b + c) / 4
 //!
-//! This approach uses only `HvxVector` (single-vector) operations, avoiding
-//! `HvxVectorPair` which currently has ABI limitations in the Rust/LLVM
-//! Hexagon backend.
+//! This implementation uses `HvxVectorPair` for widening arithmetic to achieve
+//! full precision in the Gaussian computation, avoiding the approximation errors
+//! of byte-averaging approaches.
 //!
-//! To build:
+//! # Building and Running
 //!
-//!     RUSTFLAGS="-C target-feature=+hvxv60,+hvx-length128b \
+//! To build (requires Hexagon toolchain):
+//!
+//!     RUSTFLAGS="-C target-feature=+hvxv62,+hvx-length128b \
 //!         -C linker=hexagon-unknown-linux-musl-clang" \
 //!         cargo +nightly build --bin gaussian -p stdarch_examples \
-//!         --target hexagon-unknown-linux-musl \
+//!         --features hexagon --target hexagon-unknown-linux-musl \
 //!         -Zbuild-std -Zbuild-std-features=llvm-libunwind
 //!
 //! To run under QEMU:
@@ -29,6 +29,7 @@
 //!     qemu-hexagon -L <sysroot>/target/hexagon-unknown-linux-musl \
 //!         target/hexagon-unknown-linux-musl/debug/gaussian
 
+// This example only compiles on Hexagon targets
 #![cfg(target_arch = "hexagon")]
 #![feature(stdarch_hexagon)]
 #![feature(hexagon_target_feature)]
@@ -38,8 +39,7 @@
     clippy::print_stdout,
     clippy::missing_docs_in_private_items,
     clippy::cast_possible_wrap,
-    clippy::cast_ptr_alignment,
-    dead_code
+    clippy::cast_ptr_alignment
 )]
 
 #[cfg(not(target_feature = "hvx-length128b"))]
@@ -59,10 +59,12 @@ const VLEN: usize = 64;
 const WIDTH: usize = 256;
 const HEIGHT: usize = 16;
 
-/// Vertical 1-2-1 filter pass using byte averaging
+/// Vertical 1-2-1 filter pass using HvxVectorPair widening arithmetic
+///
+/// Computes: dst[x] = (row_above[x] + 2*center[x] + row_below[x] + 2) >> 2
 ///
-/// Computes: dst[x] = avg(avg(row_above[x], row_below[x]), center[x])
-///                   ≈ (row_above[x] + 2*center[x] + row_below[x]) / 4
+/// Uses HvxVectorPair to widen u8 to u16 for precise arithmetic, avoiding
+/// the rounding errors of byte-averaging approximations.
 ///
 /// # Safety
 ///
@@ -70,7 +72,7 @@ const HEIGHT: usize = 16;
 /// - `dst` must point to a valid output buffer for `width` bytes
 /// - `width` must be a multiple of VLEN
 /// - All pointers must be HVX-aligned (128-byte for 128B mode)
-#[target_feature(enable = "hvxv60")]
+#[target_feature(enable = "hvxv62")]
 unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) {
     let inp0 = src.offset(-stride) as *const HvxVector;
     let inp1 = src as *const HvxVector;
@@ -83,29 +85,49 @@ unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *m
         let center = *inp1.add(i);
         let below = *inp2.add(i);
 
-        // avg(above, below) ≈ (above + below) / 2
-        let avg_ab = q6_vub_vavg_vubvub_rnd(above, below);
-        // avg(avg_ab, center) ≈ ((above + below)/2 + center) / 2
-        //                     ≈ (above + 2*center + below) / 4
-        let result = q6_vub_vavg_vubvub_rnd(avg_ab, center);
+        // Widen above + below to 16-bit using HvxVectorPair
+        // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair
+        let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below);
+
+        // Widen center * 2 (add center to itself)
+        let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center);
+
+        // Add them: (above + below) + (center * 2) = above + 2*center + below
+        let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2);
+
+        // Extract high and low vectors from the pair (each contains u16 values)
+        let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16
+        let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16
+
+        // Arithmetic right shift by 2 (divide by 4) with rounding
+        // Add 2 for rounding before shift: (sum + 2) >> 2
+        let two = q6_vh_vsplat_r(2);
+        let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
+        let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
+        let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
+        let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
+
+        // Pack back to u8 with saturation: takes hi and lo halfword vectors,
+        // saturates to u8, and interleaves them back to original order
+        let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
 
         *outp.add(i) = result;
     }
 }
 
-/// Horizontal 1-2-1 filter pass using byte averaging with vector alignment
+/// Horizontal 1-2-1 filter pass using HvxVectorPair widening arithmetic
 ///
-/// Computes: dst[x] = avg(avg(src[x-1], src[x+1]), src[x])
-///                   ≈ (src[x-1] + 2*src[x] + src[x+1]) / 4
+/// Computes: dst[x] = (src[x-1] + 2*src[x] + src[x+1] + 2) >> 2
 ///
-/// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access.
+/// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access,
+/// then HvxVectorPair for precise widening arithmetic.
 ///
 /// # Safety
 ///
 /// - `src` and `dst` must point to valid buffers of `width` bytes
 /// - `width` must be a multiple of VLEN
 /// - All pointers must be HVX-aligned
-#[target_feature(enable = "hvxv60")]
+#[target_feature(enable = "hvxv62")]
 unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
     let inp = src as *const HvxVector;
     let outp = dst as *mut HvxVector;
@@ -122,18 +144,33 @@ unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
         };
 
         // Left neighbor (x-1): shift curr right by 1 byte, filling from prev
-        // vlalign(curr, prev, 1) = { prev[VLEN-1], curr[0], curr[1], ..., curr[VLEN-2] }
         let left = q6_v_vlalign_vvr(curr, prev, 1);
 
         // Right neighbor (x+1): shift curr left by 1 byte, filling from next
-        // valign(next, curr, 1) = { curr[1], curr[2], ..., curr[VLEN-1], next[0] }
         let right = q6_v_valign_vvr(next, curr, 1);
 
-        // avg(left, right) ≈ (src[x-1] + src[x+1]) / 2
-        let avg_lr = q6_vub_vavg_vubvub_rnd(left, right);
-        // avg(avg_lr, curr) ≈ ((src[x-1] + src[x+1])/2 + src[x]) / 2
-        //                   ≈ (src[x-1] + 2*src[x] + src[x+1]) / 4
-        let result = q6_vub_vavg_vubvub_rnd(avg_lr, curr);
+        // Widen left + right to 16-bit
+        let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right);
+
+        // Widen center * 2
+        let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr);
+
+        // Add: left + 2*center + right
+        let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2);
+
+        // Extract high and low vectors
+        let sum_lo = q6_v_lo_w(sum);
+        let sum_hi = q6_v_hi_w(sum);
+
+        // Arithmetic right shift by 2 with rounding
+        let two = q6_vh_vsplat_r(2);
+        let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
+        let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
+        let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
+        let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
+
+        // Pack back to u8 with saturation
+        let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
 
         *outp.add(i) = result;
 
@@ -156,7 +193,7 @@ unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
 /// - `width` must be a multiple of VLEN and >= VLEN
 /// - `stride` must be >= `width`
 /// - All buffers must be HVX-aligned (128-byte for 128B mode)
-#[target_feature(enable = "hvxv60")]
+#[target_feature(enable = "hvxv62")]
 pub unsafe fn gaussian3x3u8(
     src: *const u8,
     stride: usize,
@@ -180,7 +217,7 @@ pub unsafe fn gaussian3x3u8(
     }
 }
 
-/// Reference C implementation from Hexagon SDK (Gaussian3x3u8)
+/// Reference implementation from Hexagon SDK (Gaussian3x3u8)
 ///
 /// Kernel:
 ///     1 2 1
@@ -203,39 +240,6 @@ fn gaussian3x3u8_reference(src: &[u8], stride: usize, width: usize, height: usiz
     }
 }
 
-/// Scalar approximation matching the HVX byte-averaging approach
-///
-/// This matches the HVX implementation's behavior:
-/// - Vertical: avg_rnd(avg_rnd(above, below), center)
-/// - Horizontal: avg_rnd(avg_rnd(left, right), center)
-/// where avg_rnd(a, b) = (a + b + 1) / 2
-fn gaussian3x3u8_approx(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) {
-    // Temporary buffer for vertical pass output
-    let mut tmp = vec![0u8; width * height];
-
-    // Vertical pass: 1-2-1 using rounding average
-    for y in 1..height - 1 {
-        for x in 0..width {
-            let above = src[(y - 1) * stride + x] as u16;
-            let center = src[y * stride + x] as u16;
-            let below = src[(y + 1) * stride + x] as u16;
-            let avg_ab = ((above + below + 1) / 2) as u8;
-            tmp[y * width + x] = ((avg_ab as u16 + center + 1) / 2) as u8;
-        }
-    }
-
-    // Horizontal pass: 1-2-1 using rounding average
-    for y in 1..height - 1 {
-        for x in 1..width - 1 {
-            let left = tmp[y * width + (x - 1)] as u16;
-            let center = tmp[y * width + x] as u16;
-            let right = tmp[y * width + (x + 1)] as u16;
-            let avg_lr = ((left + right + 1) / 2) as u8;
-            dst[y * stride + x] = ((avg_lr as u16 + center + 1) / 2) as u8;
-        }
-    }
-}
-
 /// Generate deterministic test pattern
 fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) {
     for y in 0..height {
@@ -254,7 +258,6 @@ fn main() {
     let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]);
     let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]);
     let mut dst_ref = vec![0u8; WIDTH * HEIGHT];
-    let mut dst_approx = vec![0u8; WIDTH * HEIGHT];
 
     // Generate test pattern
     generate_test_pattern(&mut src.0, WIDTH, HEIGHT);
@@ -274,30 +277,28 @@ fn main() {
     // Run reference
     gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
 
-    // Run scalar approximation (should match HVX exactly)
-    gaussian3x3u8_approx(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_approx);
-
-    // Verify HVX matches the byte-averaging approximation exactly
+    // Verify HVX matches reference (allowing small rounding differences)
+    let mut max_diff = 0i32;
     for y in 1..HEIGHT - 1 {
         for x in 1..WIDTH - 1 {
             let idx = y * WIDTH + x;
-            assert_eq!(
-                dst_hvx.0[idx], dst_approx[idx],
-                "HVX output differs from scalar approximation at ({}, {}): hvx={}, approx={}",
-                x, y, dst_hvx.0[idx], dst_approx[idx]
+            let diff = (dst_hvx.0[idx] as i32 - dst_ref[idx] as i32).abs();
+            max_diff = max_diff.max(diff);
+            // Allow up to 1 LSB difference due to rounding
+            assert!(
+                diff <= 1,
+                "HVX differs from reference at ({}, {}): hvx={}, ref={}, diff={}",
+                x,
+                y,
+                dst_hvx.0[idx],
+                dst_ref[idx],
+                diff
             );
         }
     }
 
-    // Verify HVX exactly matches reference for this test pattern
-    for y in 1..HEIGHT - 1 {
-        for x in 1..WIDTH - 1 {
-            let idx = y * WIDTH + x;
-            assert_eq!(
-                dst_hvx.0[idx], dst_ref[idx],
-                "HVX differs from reference at ({}, {}): hvx={}, ref={}",
-                x, y, dst_hvx.0[idx], dst_ref[idx]
-            );
-        }
-    }
+    println!(
+        "Gaussian 3x3 HVX test passed! Max difference from reference: {}",
+        max_diff
+    );
 }

From da94360a459751938eea298e536ba7dc2435963b Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Sun, 15 Feb 2026 07:03:46 -0600
Subject: [PATCH 147/326] examples: Make gaussian build on all targets

Restructure gaussian.rs to follow the pattern used by hex.rs and
connect5.rs.

Remove the 'hexagon' feature gate.
---
 examples/Cargo.toml  |   6 +-
 examples/gaussian.rs | 401 ++++++++++++++++++++++++-------------------
 2 files changed, 225 insertions(+), 182 deletions(-)

diff --git a/examples/Cargo.toml b/examples/Cargo.toml
index 8ac14d3e44..c4fc4c7e37 100644
--- a/examples/Cargo.toml
+++ b/examples/Cargo.toml
@@ -10,10 +10,6 @@ description = "Examples of the stdarch crate."
 edition = "2024"
 default-run = "hex"
 
-[features]
-# Enable to build Hexagon-specific examples (requires hexagon target)
-hexagon = []
-
 [dependencies]
 core_arch = { path = "../crates/core_arch" }
 quickcheck = "1.0"
@@ -27,10 +23,10 @@ path = "hex.rs"
 name = "connect5"
 path = "connect5.rs"
 
+# Hexagon-only: requires --target hexagon-unknown-linux-musl
 [[bin]]
 name = "gaussian"
 path = "gaussian.rs"
-required-features = ["hexagon"]
 
 [[example]]
 name = "wasm"
diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index 61fb5e68c6..dea16f797a 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -10,29 +10,32 @@
 //!
 //! This is a separable filter: `[1 2 1]^T * [1 2 1] / 16`.
 //!
-//! This implementation uses `HvxVectorPair` for widening arithmetic to achieve
-//! full precision in the Gaussian computation, avoiding the approximation errors
-//! of byte-averaging approaches.
+//! On Hexagon targets, this implementation uses `HvxVectorPair` for widening
+//! arithmetic to achieve full precision in the Gaussian computation, avoiding
+//! the approximation errors of byte-averaging approaches. On other targets,
+//! it runs a reference implementation in pure Rust.
 //!
-//! # Building and Running
+//! # Building and Running (Hexagon)
 //!
 //! To build (requires Hexagon toolchain):
 //!
 //!     RUSTFLAGS="-C target-feature=+hvxv62,+hvx-length128b \
 //!         -C linker=hexagon-unknown-linux-musl-clang" \
-//!         cargo +nightly build --bin gaussian -p stdarch_examples \
-//!         --features hexagon --target hexagon-unknown-linux-musl \
+//!         cargo +nightly build -p stdarch_examples --bin gaussian \
+//!         --target hexagon-unknown-linux-musl \
 //!         -Zbuild-std -Zbuild-std-features=llvm-libunwind
 //!
 //! To run under QEMU:
 //!
 //!     qemu-hexagon -L <sysroot>/target/hexagon-unknown-linux-musl \
 //!         target/hexagon-unknown-linux-musl/debug/gaussian
+//!
+//! # Building and Running (Other targets)
+//!
+//!     cargo +nightly run -p stdarch_examples --bin gaussian
 
-// This example only compiles on Hexagon targets
-#![cfg(target_arch = "hexagon")]
-#![feature(stdarch_hexagon)]
-#![feature(hexagon_target_feature)]
+#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))]
+#![cfg_attr(target_arch = "hexagon", feature(hexagon_target_feature))]
 #![allow(
     unsafe_op_in_unsafe_fn,
     clippy::unwrap_used,
@@ -42,182 +45,193 @@
     clippy::cast_ptr_alignment
 )]
 
-#[cfg(not(target_feature = "hvx-length128b"))]
-use core_arch::arch::hexagon::v64::*;
-#[cfg(target_feature = "hvx-length128b")]
-use core_arch::arch::hexagon::v128::*;
-
-/// Vector length in bytes for HVX 128-byte mode
-#[cfg(target_feature = "hvx-length128b")]
-const VLEN: usize = 128;
-
-/// Vector length in bytes for HVX 64-byte mode
-#[cfg(not(target_feature = "hvx-length128b"))]
-const VLEN: usize = 64;
-
-/// Image width - must be multiple of VLEN
+/// Image width - must be multiple of HVX vector length on Hexagon
 const WIDTH: usize = 256;
 const HEIGHT: usize = 16;
 
-/// Vertical 1-2-1 filter pass using HvxVectorPair widening arithmetic
-///
-/// Computes: dst[x] = (row_above[x] + 2*center[x] + row_below[x] + 2) >> 2
-///
-/// Uses HvxVectorPair to widen u8 to u16 for precise arithmetic, avoiding
-/// the rounding errors of byte-averaging approximations.
-///
-/// # Safety
-///
-/// - `src` must point to the center row with valid data at -stride and +stride
-/// - `dst` must point to a valid output buffer for `width` bytes
-/// - `width` must be a multiple of VLEN
-/// - All pointers must be HVX-aligned (128-byte for 128B mode)
-#[target_feature(enable = "hvxv62")]
-unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) {
-    let inp0 = src.offset(-stride) as *const HvxVector;
-    let inp1 = src as *const HvxVector;
-    let inp2 = src.offset(stride) as *const HvxVector;
-    let outp = dst as *mut HvxVector;
-
-    let n_chunks = width / VLEN;
-    for i in 0..n_chunks {
-        let above = *inp0.add(i);
-        let center = *inp1.add(i);
-        let below = *inp2.add(i);
-
-        // Widen above + below to 16-bit using HvxVectorPair
-        // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair
-        let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below);
-
-        // Widen center * 2 (add center to itself)
-        let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center);
-
-        // Add them: (above + below) + (center * 2) = above + 2*center + below
-        let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2);
-
-        // Extract high and low vectors from the pair (each contains u16 values)
-        let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16
-        let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16
-
-        // Arithmetic right shift by 2 (divide by 4) with rounding
-        // Add 2 for rounding before shift: (sum + 2) >> 2
-        let two = q6_vh_vsplat_r(2);
-        let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
-        let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
-        let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
-        let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
-
-        // Pack back to u8 with saturation: takes hi and lo halfword vectors,
-        // saturates to u8, and interleaves them back to original order
-        let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
-
-        *outp.add(i) = result;
+// ============================================================================
+// Hexagon HVX implementation
+// ============================================================================
+
+#[cfg(target_arch = "hexagon")]
+mod hvx {
+    #[cfg(not(target_feature = "hvx-length128b"))]
+    use core_arch::arch::hexagon::v64::*;
+    #[cfg(target_feature = "hvx-length128b")]
+    use core_arch::arch::hexagon::v128::*;
+
+    /// Vector length in bytes for HVX 128-byte mode
+    #[cfg(target_feature = "hvx-length128b")]
+    const VLEN: usize = 128;
+
+    /// Vector length in bytes for HVX 64-byte mode
+    #[cfg(not(target_feature = "hvx-length128b"))]
+    const VLEN: usize = 64;
+
+    /// Vertical 1-2-1 filter pass using HvxVectorPair widening arithmetic
+    ///
+    /// Computes: dst[x] = (row_above[x] + 2*center[x] + row_below[x] + 2) >> 2
+    ///
+    /// Uses HvxVectorPair to widen u8 to u16 for precise arithmetic, avoiding
+    /// the rounding errors of byte-averaging approximations.
+    ///
+    /// # Safety
+    ///
+    /// - `src` must point to the center row with valid data at -stride and +stride
+    /// - `dst` must point to a valid output buffer for `width` bytes
+    /// - `width` must be a multiple of VLEN
+    /// - All pointers must be HVX-aligned (128-byte for 128B mode)
+    #[target_feature(enable = "hvxv62")]
+    unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) {
+        let inp0 = src.offset(-stride) as *const HvxVector;
+        let inp1 = src as *const HvxVector;
+        let inp2 = src.offset(stride) as *const HvxVector;
+        let outp = dst as *mut HvxVector;
+
+        let n_chunks = width / VLEN;
+        for i in 0..n_chunks {
+            let above = *inp0.add(i);
+            let center = *inp1.add(i);
+            let below = *inp2.add(i);
+
+            // Widen above + below to 16-bit using HvxVectorPair
+            // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair
+            let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below);
+
+            // Widen center * 2 (add center to itself)
+            let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center);
+
+            // Add them: (above + below) + (center * 2) = above + 2*center + below
+            let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2);
+
+            // Extract high and low vectors from the pair (each contains u16 values)
+            let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16
+            let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16
+
+            // Arithmetic right shift by 2 (divide by 4) with rounding
+            // Add 2 for rounding before shift: (sum + 2) >> 2
+            let two = q6_vh_vsplat_r(2);
+            let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
+            let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
+            let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
+            let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
+
+            // Pack back to u8 with saturation: takes hi and lo halfword vectors,
+            // saturates to u8, and interleaves them back to original order
+            let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
+
+            *outp.add(i) = result;
+        }
     }
-}
-
-/// Horizontal 1-2-1 filter pass using HvxVectorPair widening arithmetic
-///
-/// Computes: dst[x] = (src[x-1] + 2*src[x] + src[x+1] + 2) >> 2
-///
-/// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access,
-/// then HvxVectorPair for precise widening arithmetic.
-///
-/// # Safety
-///
-/// - `src` and `dst` must point to valid buffers of `width` bytes
-/// - `width` must be a multiple of VLEN
-/// - All pointers must be HVX-aligned
-#[target_feature(enable = "hvxv62")]
-unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
-    let inp = src as *const HvxVector;
-    let outp = dst as *mut HvxVector;
-
-    let n_chunks = width / VLEN;
-    let mut prev = q6_v_vzero();
-
-    for i in 0..n_chunks {
-        let curr = *inp.add(i);
-        let next = if i + 1 < n_chunks {
-            *inp.add(i + 1)
-        } else {
-            q6_v_vzero()
-        };
-
-        // Left neighbor (x-1): shift curr right by 1 byte, filling from prev
-        let left = q6_v_vlalign_vvr(curr, prev, 1);
-
-        // Right neighbor (x+1): shift curr left by 1 byte, filling from next
-        let right = q6_v_valign_vvr(next, curr, 1);
-
-        // Widen left + right to 16-bit
-        let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right);
 
-        // Widen center * 2
-        let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr);
-
-        // Add: left + 2*center + right
-        let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2);
-
-        // Extract high and low vectors
-        let sum_lo = q6_v_lo_w(sum);
-        let sum_hi = q6_v_hi_w(sum);
-
-        // Arithmetic right shift by 2 with rounding
-        let two = q6_vh_vsplat_r(2);
-        let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
-        let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
-        let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
-        let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
-
-        // Pack back to u8 with saturation
-        let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
-
-        *outp.add(i) = result;
-
-        prev = curr;
+    /// Horizontal 1-2-1 filter pass using HvxVectorPair widening arithmetic
+    ///
+    /// Computes: dst[x] = (src[x-1] + 2*src[x] + src[x+1] + 2) >> 2
+    ///
+    /// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access,
+    /// then HvxVectorPair for precise widening arithmetic.
+    ///
+    /// # Safety
+    ///
+    /// - `src` and `dst` must point to valid buffers of `width` bytes
+    /// - `width` must be a multiple of VLEN
+    /// - All pointers must be HVX-aligned
+    #[target_feature(enable = "hvxv62")]
+    unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) {
+        let inp = src as *const HvxVector;
+        let outp = dst as *mut HvxVector;
+
+        let n_chunks = width / VLEN;
+        let mut prev = q6_v_vzero();
+
+        for i in 0..n_chunks {
+            let curr = *inp.add(i);
+            let next = if i + 1 < n_chunks {
+                *inp.add(i + 1)
+            } else {
+                q6_v_vzero()
+            };
+
+            // Left neighbor (x-1): shift curr right by 1 byte, filling from prev
+            let left = q6_v_vlalign_vvr(curr, prev, 1);
+
+            // Right neighbor (x+1): shift curr left by 1 byte, filling from next
+            let right = q6_v_valign_vvr(next, curr, 1);
+
+            // Widen left + right to 16-bit
+            let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right);
+
+            // Widen center * 2
+            let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr);
+
+            // Add: left + 2*center + right
+            let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2);
+
+            // Extract high and low vectors
+            let sum_lo = q6_v_lo_w(sum);
+            let sum_hi = q6_v_hi_w(sum);
+
+            // Arithmetic right shift by 2 with rounding
+            let two = q6_vh_vsplat_r(2);
+            let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
+            let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
+            let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
+            let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
+
+            // Pack back to u8 with saturation
+            let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
+
+            *outp.add(i) = result;
+
+            prev = curr;
+        }
     }
-}
-
-/// Apply Gaussian 3x3 blur to an entire image using separable filtering
-///
-/// Two-pass approach:
-/// 1. Vertical pass: apply 1-2-1 filter across rows
-/// 2. Horizontal pass: apply 1-2-1 filter across columns
-///
-/// Combined effect: 3x3 Gaussian kernel [1 2 1; 2 4 2; 1 2 1] / 16
-///
-/// # Safety
-///
-/// - `src` and `dst` must point to valid image buffers of `stride * height` bytes
-/// - `tmp` must point to a valid temporary buffer of `width` bytes, HVX-aligned
-/// - `width` must be a multiple of VLEN and >= VLEN
-/// - `stride` must be >= `width`
-/// - All buffers must be HVX-aligned (128-byte for 128B mode)
-#[target_feature(enable = "hvxv62")]
-pub unsafe fn gaussian3x3u8(
-    src: *const u8,
-    stride: usize,
-    width: usize,
-    height: usize,
-    dst: *mut u8,
-    tmp: *mut u8,
-) {
-    let stride_i = stride as isize;
-
-    // Process interior rows (skip first and last which lack vertical neighbors)
-    for y in 1..height - 1 {
-        let row_src = src.offset(y as isize * stride_i);
-        let row_dst = dst.offset(y as isize * stride_i);
 
-        // Pass 1: vertical 1-2-1 into tmp
-        vertical_121_pass(row_src, stride_i, width, tmp);
-
-        // Pass 2: horizontal 1-2-1 from tmp into dst
-        horizontal_121_pass(tmp, width, row_dst);
+    /// Apply Gaussian 3x3 blur to an entire image using separable filtering
+    ///
+    /// Two-pass approach:
+    /// 1. Vertical pass: apply 1-2-1 filter across rows
+    /// 2. Horizontal pass: apply 1-2-1 filter across columns
+    ///
+    /// Combined effect: 3x3 Gaussian kernel [1 2 1; 2 4 2; 1 2 1] / 16
+    ///
+    /// # Safety
+    ///
+    /// - `src` and `dst` must point to valid image buffers of `stride * height` bytes
+    /// - `tmp` must point to a valid temporary buffer of `width` bytes, HVX-aligned
+    /// - `width` must be a multiple of VLEN and >= VLEN
+    /// - `stride` must be >= `width`
+    /// - All buffers must be HVX-aligned (128-byte for 128B mode)
+    #[target_feature(enable = "hvxv62")]
+    pub unsafe fn gaussian3x3u8(
+        src: *const u8,
+        stride: usize,
+        width: usize,
+        height: usize,
+        dst: *mut u8,
+        tmp: *mut u8,
+    ) {
+        let stride_i = stride as isize;
+
+        // Process interior rows (skip first and last which lack vertical neighbors)
+        for y in 1..height - 1 {
+            let row_src = src.offset(y as isize * stride_i);
+            let row_dst = dst.offset(y as isize * stride_i);
+
+            // Pass 1: vertical 1-2-1 into tmp
+            vertical_121_pass(row_src, stride_i, width, tmp);
+
+            // Pass 2: horizontal 1-2-1 from tmp into dst
+            horizontal_121_pass(tmp, width, row_dst);
+        }
     }
 }
 
-/// Reference implementation from Hexagon SDK (Gaussian3x3u8)
+// ============================================================================
+// Reference implementation (works on all targets)
+// ============================================================================
+
+/// Reference implementation of Gaussian 3x3 blur
 ///
 /// Kernel:
 ///     1 2 1
@@ -249,6 +263,11 @@ fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) {
     }
 }
 
+// ============================================================================
+// Main: runs HVX + reference on Hexagon, reference-only on other targets
+// ============================================================================
+
+#[cfg(target_arch = "hexagon")]
 fn main() {
     // Aligned buffers for HVX
     #[repr(align(128))]
@@ -264,7 +283,7 @@ fn main() {
 
     // Run HVX implementation
     unsafe {
-        gaussian3x3u8(
+        hvx::gaussian3x3u8(
             src.0.as_ptr(),
             WIDTH,
             WIDTH,
@@ -302,3 +321,31 @@ fn main() {
         max_diff
     );
 }
+
+#[cfg(not(target_arch = "hexagon"))]
+fn main() {
+    let mut src = vec![0u8; WIDTH * HEIGHT];
+    let mut dst = vec![0u8; WIDTH * HEIGHT];
+
+    // Generate test pattern
+    generate_test_pattern(&mut src, WIDTH, HEIGHT);
+
+    // Run reference implementation
+    gaussian3x3u8_reference(&src, WIDTH, WIDTH, HEIGHT, &mut dst);
+
+    // Verify output is non-trivial (blurred values differ from input)
+    let mut changed = 0;
+    for y in 1..HEIGHT - 1 {
+        for x in 1..WIDTH - 1 {
+            let idx = y * WIDTH + x;
+            if src[idx] != dst[idx] {
+                changed += 1;
+            }
+        }
+    }
+
+    println!(
+        "Gaussian 3x3 reference test passed! {} pixels changed by blur",
+        changed
+    );
+}

From bd7456696f428950c8e81c9f09be3f108126c36b Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Sun, 15 Feb 2026 11:57:54 -0600
Subject: [PATCH 148/326] stdarch-gen-hexagon: Use checked-in header file
 instead of downloading

Check in the LLVM HVX header file (hvx_hexagon_protos.h) from LLVM
22.1.0-rc1 and modify the generator to read from this local copy
instead of downloading it at runtime. This removes the ureq dependency
and makes the build more reproducible.
---
 Cargo.lock                                    |  513 +-
 crates/stdarch-gen-hexagon/Cargo.toml         |    1 -
 .../stdarch-gen-hexagon/hvx_hexagon_protos.h  | 6003 +++++++++++++++++
 crates/stdarch-gen-hexagon/src/main.rs        |   45 +-
 4 files changed, 6028 insertions(+), 534 deletions(-)
 create mode 100644 crates/stdarch-gen-hexagon/hvx_hexagon_protos.h

diff --git a/Cargo.lock b/Cargo.lock
index 36b2b09acb..7e7cb59288 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2,12 +2,6 @@
 # It is not intended for manual editing.
 version = 4
 
-[[package]]
-name = "adler2"
-version = "2.0.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa"
-
 [[package]]
 name = "aho-corasick"
 version = "1.1.4"
@@ -53,7 +47,7 @@ version = "1.1.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc"
 dependencies = [
- "windows-sys 0.61.2",
+ "windows-sys",
 ]
 
 [[package]]
@@ -64,7 +58,7 @@ checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d"
 dependencies = [
  "anstyle",
  "once_cell_polyfill",
- "windows-sys 0.61.2",
+ "windows-sys",
 ]
 
 [[package]]
@@ -88,12 +82,6 @@ version = "1.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8"
 
-[[package]]
-name = "base64"
-version = "0.22.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6"
-
 [[package]]
 name = "bitflags"
 version = "2.10.0"
@@ -170,15 +158,6 @@ dependencies = [
  "syscalls",
 ]
 
-[[package]]
-name = "crc32fast"
-version = "1.5.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511"
-dependencies = [
- "cfg-if",
-]
-
 [[package]]
 name = "crossbeam-deque"
 version = "0.8.6"
@@ -245,17 +224,6 @@ version = "0.1.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "56254986775e3233ffa9c4d7d3faaf6d36a2c09d30b20687e9f88bc8bafc16c8"
 
-[[package]]
-name = "displaydoc"
-version = "0.2.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "97369cbbc041bc366949bc74d34658d6cda5621039731c6310521892a3a20ae0"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
 [[package]]
 name = "either"
 version = "1.15.0"
@@ -307,16 +275,6 @@ version = "0.1.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582"
 
-[[package]]
-name = "flate2"
-version = "1.1.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c"
-dependencies = [
- "crc32fast",
- "miniz_oxide",
-]
-
 [[package]]
 name = "fnv"
 version = "1.0.7"
@@ -329,15 +287,6 @@ version = "0.1.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
 
-[[package]]
-name = "form_urlencoded"
-version = "1.2.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cb4cb245038516f5f85277875cdaa4f7d2c9a0fa0468de06ed190163b1581fcf"
-dependencies = [
- "percent-encoding",
-]
-
 [[package]]
 name = "getrandom"
 version = "0.2.17"
@@ -402,87 +351,6 @@ version = "2.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "135b12329e5e3ce057a9f972339ea52bc954fe1e9358ef27f95e89716fbc5424"
 
-[[package]]
-name = "icu_collections"
-version = "2.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4c6b649701667bbe825c3b7e6388cb521c23d88644678e83c0c4d0a621a34b43"
-dependencies = [
- "displaydoc",
- "potential_utf",
- "yoke",
- "zerofrom",
- "zerovec",
-]
-
-[[package]]
-name = "icu_locale_core"
-version = "2.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "edba7861004dd3714265b4db54a3c390e880ab658fec5f7db895fae2046b5bb6"
-dependencies = [
- "displaydoc",
- "litemap",
- "tinystr",
- "writeable",
- "zerovec",
-]
-
-[[package]]
-name = "icu_normalizer"
-version = "2.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5f6c8828b67bf8908d82127b2054ea1b4427ff0230ee9141c54251934ab1b599"
-dependencies = [
- "icu_collections",
- "icu_normalizer_data",
- "icu_properties",
- "icu_provider",
- "smallvec",
- "zerovec",
-]
-
-[[package]]
-name = "icu_normalizer_data"
-version = "2.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7aedcccd01fc5fe81e6b489c15b247b8b0690feb23304303a9e560f37efc560a"
-
-[[package]]
-name = "icu_properties"
-version = "2.1.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "020bfc02fe870ec3a66d93e677ccca0562506e5872c650f893269e08615d74ec"
-dependencies = [
- "icu_collections",
- "icu_locale_core",
- "icu_properties_data",
- "icu_provider",
- "zerotrie",
- "zerovec",
-]
-
-[[package]]
-name = "icu_properties_data"
-version = "2.1.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "616c294cf8d725c6afcd8f55abc17c56464ef6211f9ed59cccffe534129c77af"
-
-[[package]]
-name = "icu_provider"
-version = "2.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "85962cf0ce02e1e0a629cc34e7ca3e373ce20dda4c4d7294bbd0bf1fdb59e614"
-dependencies = [
- "displaydoc",
- "icu_locale_core",
- "writeable",
- "yoke",
- "zerofrom",
- "zerotrie",
- "zerovec",
-]
-
 [[package]]
 name = "id-arena"
 version = "2.3.0"
@@ -495,27 +363,6 @@ version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39"
 
-[[package]]
-name = "idna"
-version = "1.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3b0875f23caa03898994f6ddc501886a45c7d3d62d04d2d90788d47be1b1e4de"
-dependencies = [
- "idna_adapter",
- "smallvec",
- "utf8_iter",
-]
-
-[[package]]
-name = "idna_adapter"
-version = "1.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3acae9609540aa318d1bc588455225fb2085b9ed0c4f6bd0d9d5bcd86f1a0344"
-dependencies = [
- "icu_normalizer",
- "icu_properties",
-]
-
 [[package]]
 name = "indexmap"
 version = "1.9.3"
@@ -563,7 +410,7 @@ checksum = "3640c1c38b8e4e43584d8df18be5fc6b0aa314ce6ebf51b53313d4306cca8e46"
 dependencies = [
  "hermit-abi",
  "libc",
- "windows-sys 0.61.2",
+ "windows-sys",
 ]
 
 [[package]]
@@ -605,12 +452,6 @@ version = "0.5.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0717cef1bc8b636c6e1c1bbdefc09e6322da8a9321966e8928ef80d20f7f770f"
 
-[[package]]
-name = "litemap"
-version = "0.8.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6373607a59f0be73a39b6fe456b8192fcc3585f602af20751600e974dd455e77"
-
 [[package]]
 name = "log"
 version = "0.4.29"
@@ -623,43 +464,12 @@ version = "2.8.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79"
 
-[[package]]
-name = "miniz_oxide"
-version = "0.8.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316"
-dependencies = [
- "adler2",
- "simd-adler32",
-]
-
-[[package]]
-name = "once_cell"
-version = "1.21.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d"
-
 [[package]]
 name = "once_cell_polyfill"
 version = "1.70.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe"
 
-[[package]]
-name = "percent-encoding"
-version = "2.3.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220"
-
-[[package]]
-name = "potential_utf"
-version = "0.1.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b73949432f5e2a09657003c25bca5e19a0e9c84f8058ca374f49e0ebe605af77"
-dependencies = [
- "zerovec",
-]
-
 [[package]]
 name = "ppv-lite86"
 version = "0.2.21"
@@ -839,61 +649,12 @@ version = "0.8.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "a96887878f22d7bad8a3b6dc5b7440e0ada9a245242924394987b21cf2210a4c"
 
-[[package]]
-name = "ring"
-version = "0.17.14"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7"
-dependencies = [
- "cc",
- "cfg-if",
- "getrandom 0.2.17",
- "libc",
- "untrusted",
- "windows-sys 0.52.0",
-]
-
 [[package]]
 name = "rustc-demangle"
 version = "0.1.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d"
 
-[[package]]
-name = "rustls"
-version = "0.23.36"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c665f33d38cea657d9614f766881e4d510e0eda4239891eea56b4cadcf01801b"
-dependencies = [
- "log",
- "once_cell",
- "ring",
- "rustls-pki-types",
- "rustls-webpki",
- "subtle",
- "zeroize",
-]
-
-[[package]]
-name = "rustls-pki-types"
-version = "1.14.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "be040f8b0a225e40375822a563fa9524378b9d63112f53e19ffff34df5d33fdd"
-dependencies = [
- "zeroize",
-]
-
-[[package]]
-name = "rustls-webpki"
-version = "0.103.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d7df23109aa6c1567d1c575b9952556388da57401e4ace1d15f79eedad0d8f53"
-dependencies = [
- "ring",
- "rustls-pki-types",
- "untrusted",
-]
-
 [[package]]
 name = "ryu"
 version = "1.0.23"
@@ -1010,12 +771,6 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
 
-[[package]]
-name = "simd-adler32"
-version = "0.3.8"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2"
-
 [[package]]
 name = "simd-test-macro"
 version = "0.1.0"
@@ -1025,18 +780,6 @@ dependencies = [
  "syn",
 ]
 
-[[package]]
-name = "smallvec"
-version = "1.15.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "67b1b7a3b5fe4f1376887184045fcf45c69e92af734b7aaddc05fb777b6fbd03"
-
-[[package]]
-name = "stable_deref_trait"
-version = "1.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596"
-
 [[package]]
 name = "stdarch-gen-arm"
 version = "0.1.0"
@@ -1056,7 +799,6 @@ name = "stdarch-gen-hexagon"
 version = "0.1.0"
 dependencies = [
  "regex",
- "ureq",
 ]
 
 [[package]]
@@ -1105,12 +847,6 @@ version = "0.11.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
-[[package]]
-name = "subtle"
-version = "2.6.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292"
-
 [[package]]
 name = "syn"
 version = "2.0.115"
@@ -1122,17 +858,6 @@ dependencies = [
  "unicode-ident",
 ]
 
-[[package]]
-name = "synstructure"
-version = "0.13.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "728a70f3dbaf5bab7f0c4b1ac8d7ae5ea60a4b5549c8a5914361c99147a709d2"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
 [[package]]
 name = "syscalls"
 version = "0.6.18"
@@ -1168,16 +893,6 @@ dependencies = [
  "syn",
 ]
 
-[[package]]
-name = "tinystr"
-version = "0.8.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "42d3e9c45c09de15d06dd8acf5f4e0e399e85927b7f00711024eb7ae10fa4869"
-dependencies = [
- "displaydoc",
- "zerovec",
-]
-
 [[package]]
 name = "unicode-ident"
 version = "1.0.23"
@@ -1190,46 +905,6 @@ version = "0.2.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ebc1c04c71510c7f702b52b7c350734c9ff1295c464a03335b00bb84fc54f853"
 
-[[package]]
-name = "untrusted"
-version = "0.9.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1"
-
-[[package]]
-name = "ureq"
-version = "2.12.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "02d1a66277ed75f640d608235660df48c8e3c19f3b4edb6a263315626cc3c01d"
-dependencies = [
- "base64",
- "flate2",
- "log",
- "once_cell",
- "rustls",
- "rustls-pki-types",
- "url",
- "webpki-roots 0.26.11",
-]
-
-[[package]]
-name = "url"
-version = "2.5.8"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ff67a8a4397373c3ef660812acab3268222035010ab8680ec4215f38ba3d0eed"
-dependencies = [
- "form_urlencoded",
- "idna",
- "percent-encoding",
- "serde",
-]
-
-[[package]]
-name = "utf8_iter"
-version = "1.0.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b6c140620e7ffbb22c2dee59cafe6084a59b5ffc27a8859a5f0d494b5d52b6be"
-
 [[package]]
 name = "utf8parse"
 version = "0.2.2"
@@ -1326,31 +1001,13 @@ dependencies = [
  "wasmparser 0.235.0",
 ]
 
-[[package]]
-name = "webpki-roots"
-version = "0.26.11"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "521bc38abb08001b01866da9f51eb7c5d647a19260e00054a8c7fd5f9e57f7a9"
-dependencies = [
- "webpki-roots 1.0.6",
-]
-
-[[package]]
-name = "webpki-roots"
-version = "1.0.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "22cfaf3c063993ff62e73cb4311efde4db1efb31ab78a3e5c457939ad5cc0bed"
-dependencies = [
- "rustls-pki-types",
-]
-
 [[package]]
 name = "winapi-util"
 version = "0.1.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22"
 dependencies = [
- "windows-sys 0.61.2",
+ "windows-sys",
 ]
 
 [[package]]
@@ -1359,15 +1016,6 @@ version = "0.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
 
-[[package]]
-name = "windows-sys"
-version = "0.52.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d"
-dependencies = [
- "windows-targets",
-]
-
 [[package]]
 name = "windows-sys"
 version = "0.61.2"
@@ -1377,70 +1025,6 @@ dependencies = [
  "windows-link",
 ]
 
-[[package]]
-name = "windows-targets"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973"
-dependencies = [
- "windows_aarch64_gnullvm",
- "windows_aarch64_msvc",
- "windows_i686_gnu",
- "windows_i686_gnullvm",
- "windows_i686_msvc",
- "windows_x86_64_gnu",
- "windows_x86_64_gnullvm",
- "windows_x86_64_msvc",
-]
-
-[[package]]
-name = "windows_aarch64_gnullvm"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3"
-
-[[package]]
-name = "windows_aarch64_msvc"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469"
-
-[[package]]
-name = "windows_i686_gnu"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b"
-
-[[package]]
-name = "windows_i686_gnullvm"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66"
-
-[[package]]
-name = "windows_i686_msvc"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66"
-
-[[package]]
-name = "windows_x86_64_gnu"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78"
-
-[[package]]
-name = "windows_x86_64_gnullvm"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
-
-[[package]]
-name = "windows_x86_64_msvc"
-version = "0.52.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
-
 [[package]]
 name = "wit-bindgen"
 version = "0.51.0"
@@ -1529,12 +1113,6 @@ dependencies = [
  "wasmparser 0.244.0",
 ]
 
-[[package]]
-name = "writeable"
-version = "0.6.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9edde0db4769d2dc68579893f2306b26c6ecfbe0ef499b013d731b7b9247e0b9"
-
 [[package]]
 name = "xml"
 version = "1.2.1"
@@ -1550,29 +1128,6 @@ dependencies = [
  "linked-hash-map",
 ]
 
-[[package]]
-name = "yoke"
-version = "0.8.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "72d6e5c6afb84d73944e5cedb052c4680d5657337201555f9f2a16b7406d4954"
-dependencies = [
- "stable_deref_trait",
- "yoke-derive",
- "zerofrom",
-]
-
-[[package]]
-name = "yoke-derive"
-version = "0.8.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b659052874eb698efe5b9e8cf382204678a0086ebf46982b79d6ca3182927e5d"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
- "synstructure",
-]
-
 [[package]]
 name = "zerocopy"
 version = "0.8.39"
@@ -1593,66 +1148,6 @@ dependencies = [
  "syn",
 ]
 
-[[package]]
-name = "zerofrom"
-version = "0.1.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "50cc42e0333e05660c3587f3bf9d0478688e15d870fab3346451ce7f8c9fbea5"
-dependencies = [
- "zerofrom-derive",
-]
-
-[[package]]
-name = "zerofrom-derive"
-version = "0.1.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d71e5d6e06ab090c67b5e44993ec16b72dcbaabc526db883a360057678b48502"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
- "synstructure",
-]
-
-[[package]]
-name = "zeroize"
-version = "1.8.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0"
-
-[[package]]
-name = "zerotrie"
-version = "0.2.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2a59c17a5562d507e4b54960e8569ebee33bee890c70aa3fe7b97e85a9fd7851"
-dependencies = [
- "displaydoc",
- "yoke",
- "zerofrom",
-]
-
-[[package]]
-name = "zerovec"
-version = "0.11.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6c28719294829477f525be0186d13efa9a3c602f7ec202ca9e353d310fb9a002"
-dependencies = [
- "yoke",
- "zerofrom",
- "zerovec-derive",
-]
-
-[[package]]
-name = "zerovec-derive"
-version = "0.11.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "eadce39539ca5cb3985590102671f2567e659fca9666581ad3411d59207951f3"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
 [[package]]
 name = "zmij"
 version = "1.0.21"
diff --git a/crates/stdarch-gen-hexagon/Cargo.toml b/crates/stdarch-gen-hexagon/Cargo.toml
index f8c446c1d1..397c7816f8 100644
--- a/crates/stdarch-gen-hexagon/Cargo.toml
+++ b/crates/stdarch-gen-hexagon/Cargo.toml
@@ -7,4 +7,3 @@ edition = "2021"
 
 [dependencies]
 regex = "1.10"
-ureq = "2.9"
diff --git a/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h b/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h
new file mode 100644
index 0000000000..19309a40d6
--- /dev/null
+++ b/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h
@@ -0,0 +1,6003 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// Automatically generated file, do not edit!
+//===----------------------------------------------------------------------===//
+
+
+#ifndef _HVX_HEXAGON_PROTOS_H_
+#define _HVX_HEXAGON_PROTOS_H_ 1
+
+#ifdef __HVX__
+#if __HVX_LENGTH__ == 128
+#define __BUILTIN_VECTOR_WRAP(a) a ## _128B
+#else
+#define __BUILTIN_VECTOR_WRAP(a) a
+#endif
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vextract(Vu32,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs)
+   Instruction Type:      LD
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=hi(Vss32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=lo(Vss32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vsplat(Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=and(Qs4,Qt4)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=and(Qs4,!Qt4)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=not(Qs4)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=or(Qs4,Qt4)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=or(Qs4,!Qt4)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vsetq(Rt32)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=xor(Qs4,Qt4)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4)=Vs32
+   C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
+   Instruction Type:      CVI_VM_ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4):nt=Vs32
+   C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
+   Instruction Type:      CVI_VM_ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) vmem(Rt32+#s4):nt=Vs32
+   C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
+   Instruction Type:      CVI_VM_ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) vmem(Rt32+#s4)=Vs32
+   C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
+   Instruction Type:      CVI_VM_ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vabsdiff(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vabs(Vu32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vabs(Vu32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vabs(Vu32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vabs(Vu32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vadd(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.b=vadd(Vuu32.b,Vvv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) Vx32.b+=Vu32.b
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) Vx32.b+=Vu32.b
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) Vx32.h+=Vu32.h
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) Vx32.h+=Vu32.h
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vadd(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vadd(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vadd(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vadd(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vadd(Vuu32.w,Vvv32.w)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) Vx32.w+=Vu32.w
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) Vx32.w+=Vu32.w
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vadd(Vu32.w,Vv32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=valign(Vu32,Vv32,Rt8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=valign(Vu32,Vv32,#u3)
+   C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vand(Vu32,Vv32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vand(Qu4,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32|=vand(Qu4,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vand(Vu32,Rt32)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vand(Vu32,Rt32)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasl(Vu32.h,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasl(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vasl(Vu32.w,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vasl(Vu32.w,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vasl(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasr(Vu32.h,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasr(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vasr(Vu32.w,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vasr(Vu32.w,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vasr(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=Vu32
+   C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=Vuu32
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vavg(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vavg(Vu32.h,Vv32.h):rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vavg(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vavg(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vavg(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vavg(Vu32.w,Vv32.w):rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vcl0(Vu32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vcl0(Vu32.uw)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=vcombine(Vu32,Vv32)
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=#0
+   C Intrinsic Prototype: HVX_Vector Q6_V_vzero()
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)()
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vdeal(Vu32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vdeale(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vdeal(Vu32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=vdeal(Vu32,Vv32,Rt8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vdelta(Vu32,Vv32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vdmpy(Vu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h+=vdmpy(Vu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vdmpy(Vu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vdmpy(Vu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vdmpy(Vuu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vdmpy(Vu32.h,Rt32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vdmpy(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.eq(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.eq(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.eq(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.eq(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.eq(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.eq(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.eq(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.eq(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.eq(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.eq(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.eq(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.eq(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w=vinsert(Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vlalign(Vu32,Vv32,Rt8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vlalign(Vu32,Vv32,#u3)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vlsr(Vu32.uh,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vlsr(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vlsr(Vu32.uw,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vlsr(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmax(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vmax(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vmax(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmax(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmin(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vmin(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vmin(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmin(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpa(Vuu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vmpa(Vuu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vmpa(Vuu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpy(Vu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vmpy(Vu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpy(Vu32.ub,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vmpy(Vu32.ub,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpy(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vmpy(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpye(Vu32.w,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vmpy(Vu32.h,Rt32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vmpy(Vu32.h,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vmpy(Vu32.h,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vmpy(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vmpy(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyieo(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyie(Vu32.w,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyie(Vu32.w,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyie(Vu32.w,Vv32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmpyi(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h+=vmpyi(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vmpyi(Vu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h+=vmpyi(Vu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyio(Vu32.w,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyi(Vu32.w,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyi(Vu32.w,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyi(Vu32.w,Rt32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyi(Vu32.w,Rt32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vmux(Qt4,Vu32,Vv32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vnavg(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vnavg(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vnavg(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vnormamt(Vu32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vnormamt(Vu32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vnot(Vu32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vor(Vu32,Vv32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vpacke(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vpacke(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vpack(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vpack(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vpacko(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vpacko(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vpack(Vu32.w,Vv32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vpack(Vu32.w,Vv32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vpopcount(Vu32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vrdelta(Vu32,Vv32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vrmpy(Vu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vrmpy(Vu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vrmpy(Vu32.ub,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vrmpy(Vu32.ub,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vrmpy(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vrmpy(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vror(Vu32,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vround(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vround(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vround(Vu32.w,Vv32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vround(Vu32.w,Vv32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vsat(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vsat(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vsxt(Vu32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vsxt(Vu32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vshuffe(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vshuff(Vu32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vshuffe(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vshuff(Vu32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vshuffo(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=vshuff(Vu32,Vv32,Rt8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.b=vshuffoe(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vshuffoe(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vshuffo(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vsub(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.b=vsub(Vuu32.b,Vvv32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) Vx32.b-=Vu32.b
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) Vx32.b-=Vu32.b
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vsub(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vsub(Vuu32.h,Vvv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) Vx32.h-=Vu32.h
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) Vx32.h-=Vu32.h
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vsub(Vu32.h,Vv32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vsub(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vsub(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vsub(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vsub(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vsub(Vuu32.w,Vvv32.w)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (!Qv4) Vx32.w-=Vu32.w
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       if (Qv4) Vx32.w-=Vu32.w
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vsub(Vu32.w,Vv32.w):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=vswap(Qt4,Vu32,Vv32)
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vtmpy(Vuu32.b,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vtmpy(Vuu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vunpack(Vu32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vunpack(Vu32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h|=vunpacko(Vu32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w|=vunpacko(Vu32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uh=vunpack(Vu32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vunpack(Vu32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vxor(Vu32,Vv32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uh=vzxt(Vu32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vzxt(Vu32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vsplat(Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vsplat(Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vsetq2(Rt32)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Qd4.b=vshuffe(Qs4.h,Qt4.h)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Qd4.h=vshuffe(Qs4.w,Qt4.w)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vadd(Vu32.b,Vv32.b):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vadd(vclb(Vu32.h),Vv32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vadd(vclb(Vu32.w),Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vadd(Vu32.h,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vadd(Vu32.ub,Vv32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vadd(Vu32.ub,Vv32.b):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vadd(Vu32.uh,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vand(!Qu4,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vx32|=vand(!Qu4,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vand(!Qv4,Vu32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vand(Qv4,Vu32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vlsr(Vu32.ub,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
+   Instruction Type:      CVI_VP
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vmax(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vmin(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=vmpa(Vuu32.uh,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=vmpye(Vu32.w,Vv32.uh)
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vmpyi(Vu32.w,Rt32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vx32.w+=vmpyi(Vu32.w,Rt32.ub)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vxx32+=vmpyo(Vu32.w,Vv32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vround(Vu32.uh,Vv32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vround(Vu32.uw,Vv32.uw):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vsat(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vsub(Vu32.b,Vv32.b):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vsub(Vu32.ub,Vv32.b):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_VA_DV
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vabs(Vu32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vabs(Vu32.b):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h+=vasl(Vu32.h,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h+=vasr(Vu32.h,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vavg(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vavg(Vu32.b,Vv32.b):rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vavg(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vdd32=#0
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero()
+   Instruction Type:      MAPPING
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)()
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vtmp.h=vgather(Rt32,Mu2,Vv32.h).h
+   C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
+   Instruction Type:      CVI_GATHER
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h
+   C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
+   Instruction Type:      CVI_GATHER
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h
+   C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_GATHER_DV
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h
+   C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)
+   Instruction Type:      CVI_GATHER_DV
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vtmp.w=vgather(Rt32,Mu2,Vv32.w).w
+   C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
+   Instruction Type:      CVI_GATHER
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w
+   C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
+   Instruction Type:      CVI_GATHER
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vlut4(Vu32.uh,Rtt32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT2
+   ========================================================================== */
+
+#define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT2
+   ========================================================================== */
+
+#define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT2
+   ========================================================================== */
+
+#define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT2
+   ========================================================================== */
+
+#define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=vmpy(Vu32.h,Rt32.h)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vmpye(Vu32.uh,Rt32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vnavg(Vu32.b,Vv32.b)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=prefixsum(Qv4)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=prefixsum(Qv4)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=prefixsum(Qv4)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vscatter(Rt32,Mu2,Vv32.h).h=Vw32
+   C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vscatter(Rt32,Mu2,Vv32.h).h+=Vw32
+   C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32
+   C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vscatter(Rt32,Mu2,Vvv32.w).h=Vw32
+   C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER_DV
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32
+   C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER_DV
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32
+   C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER_DV
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vscatter(Rt32,Mu2,Vv32.w).w=Vw32
+   C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       vscatter(Rt32,Mu2,Vv32.w).w+=Vw32
+   C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32
+   C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
+   Instruction Type:      CVI_SCATTER
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw)
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HVX_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HVX_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w=vasrinto(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HVX_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uw=vrotr(Vu32.uw,Vv32.uw)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HVX_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vsatdw(Vu32.w,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vabs(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vabs(Vu32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vadd(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vadd(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vadd(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vadd(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vadd(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vfmv(Vu32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=Vu32.qf16
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=Vuu32.qf32
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=Vu32.qf32
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vcvt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=vcvt(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vcvt(Vu32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vcvt(Vu32.h)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vcvt(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vcvt(Vu32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vcvt(Vu32.uh)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vcvt(Vu32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vcvt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vcvt(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vfmax(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vfmax(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vfmin(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vfmin(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vfneg(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vfneg(Vu32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vmax(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vmax(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vmin(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vmin(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vmpy(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vsub(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=vsub(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vsub(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vsub(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=vsub(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HVX_ARCH__ >= 69
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 69 */
+
+#if __HVX_ARCH__ >= 69
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 69 */
+
+#if __HVX_ARCH__ >= 69
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 69 */
+
+#if __HVX_ARCH__ >= 69
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 69 */
+
+#if __HVX_ARCH__ >= 69
+/* ==========================================================================
+   Assembly Syntax:       Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv)
+#endif /* __HEXAGON_ARCH___ >= 69 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vadd(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vadd_VbfVbf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_bf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=Vu32.hf
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_equals_Vhf(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.hf=Vu32.h
+   C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vh(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vhf_equals_Vh(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_h)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.sf=Vu32.w
+   C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vw(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vsf_equals_Vw(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_w)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=Vu32.sf
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_equals_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_equals_Vsf(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_w_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.bf=vcvt(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vbf_vcvt_VsfVsf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_bf_sf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.gt(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv)                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)                          \
+  ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf)(Vu, Vv)), -1)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.gt(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv)                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)                          \
+  ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_and)(                     \
+       __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,      \
+       Vv)),                                                                   \
+   -1)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.gt(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv)                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)                          \
+  ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_or)(                      \
+       __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,      \
+       Vv)),                                                                   \
+   -1)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.gt(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv)                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)                          \
+  ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_xor)(                     \
+       __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,      \
+       Vv)),                                                                   \
+   -1)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.bf=vmax(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_LATE Execution Slots: SLOT23
+   ========================================================================== */
+
+#define Q6_Vbf_vmax_VbfVbf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_bf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vd32.bf=vmin(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_LATE Execution Slots: SLOT23
+   ========================================================================== */
+
+#define Q6_Vbf_vmin_VbfVbf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_bf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vmpy(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vmpy_VbfVbf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv)                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf_acc)(Vxx, Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 73
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.sf=vsub(Vu32.bf,Vv32.bf)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Wsf_vsub_VbfVbf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_bf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 73 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vgetqfext(Vu32.x,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfext_VR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vgetqfext_VR(Vu, Rt)                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext)(Vu, Rt)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vx32|=vgetqfext(Vu32.x,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
+   ========================================================================== */
+
+#define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt)                                       \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext_oracc)(Vx, Vu, Rt)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.x=vsetqfext(Vu32,Rt32)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vsetqfext_VR(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vsetqfext_VR(Vu, Rt)                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_set_qfext)(Vu, Rt)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.f8=vabs(Vu32.f8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vabs_V(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vabs_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_f8)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vadd(Vu32.f8,Vv32.f8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vadd_VV(Vu, Vv)                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_f8)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.b=vcvt2(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vb_vcvt2_VhfVhf(Vu, Vv)                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_b_hf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vcvt2(Vu32.b)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vb(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vcvt2_Vb(Vu)                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_b)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vcvt2(Vu32.ub)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vub(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vcvt2_Vub(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_ub)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.ub=vcvt2(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vub_vcvt2_VhfVhf(Vu, Vv)                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_ub_hf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.f8=vcvt(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vcvt_VhfVhf(Vu, Vv)                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_f8_hf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vcvt(Vu32.f8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_V(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vcvt_V(Vu)                                                      \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_f8)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.f8=vfmax(Vu32.f8,Vv32.f8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vfmax_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vfmax_VV(Vu, Vv)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_f8)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.f8=vfmin(Vu32.f8,Vv32.f8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vfmin_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vfmin_VV(Vu, Vv)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_f8)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.f8=vfneg(Vu32.f8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vfneg_V(HVX_Vector Vu)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_V_vfneg_V(Vu)                                                       \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_f8)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32=vmerge(Vu32.x,Vv32.w)
+   C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_vmerge_VVw(Vu, Vv)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmerge_qf)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vmpy(Vu32.f8,Vv32.f8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vmpy_VV(Vu, Vv)                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv)                                      \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8_acc)(Vxx, Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vmpy(Vu32.hf,Rt32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt)                                           \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_hf)(Vu, Rt)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt)                                         \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_qf16)(Vu, Rt)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vmpy(Vu32.sf,Rt32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt)                                           \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_sf)(Vu, Rt)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 79
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.hf=vsub(Vu32.f8,Vv32.f8)
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_Whf_vsub_VV(Vu, Vv)                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 79 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vabs(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vabs_Vhf(Vu)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vabs(Vu32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vabs_Vqf16(Vu)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vabs(Vu32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vabs_Vqf32(Vu)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vabs(Vu32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vabs_Vsf(Vu)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32=valign4(Vu32,Vv32,Rt8)
+   C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector
+   Vv, Word32 Rt) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_valign4_VVR(Vu, Vv, Rt)                                           \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.bf=Vuu32.qf32
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vbf_equals_Wqf32(Vuu)                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.f8=Vu32.qf16
+   C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_V_equals_Vqf16(Vu)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.h=Vu32.hf:rnd
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vh_equals_Vhf_rnd(Vu)                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vdd32.qf16=Vu32.f8
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu)
+   Instruction Type:      CVI_VP_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Wqf16_equals_V(Vu)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=Vu32.hf
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_equals_Vhf(Vu)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=Vu32.qf16
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_equals_Vqf16(Vu)                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=Vu32.qf32
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_equals_Vqf32(Vu)                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=Vu32.sf
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_equals_Vsf(Vu)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv)                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv)                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)(                  \
+          __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,   \
+          Vv)),                                                                \
+      -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv)                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)(                   \
+          __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,   \
+          Vv)),                                                                \
+      -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv)                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)(                  \
+          __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,   \
+          Vv)),                                                                \
+      -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv)                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv)                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)(                  \
+          __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,   \
+          Vv)),                                                                \
+      -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv)                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)(                   \
+          __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,   \
+          Vv)),                                                                \
+      -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv)                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(                         \
+      (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)(                  \
+          __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,   \
+          Vv)),                                                                \
+      -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vilog2(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vilog2_Vhf(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vilog2(Vu32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vilog2_Vqf16(Vu)                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vilog2(Vu32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vilog2_Vqf32(Vu)                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.w=vilog2(Vu32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vw_vilog2_Vsf(Vu)                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vneg(Vu32.hf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vneg_Vhf(Vu)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vneg(Vu32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vneg_Vqf16(Vu)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vneg(Vu32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vneg_Vqf32(Vu)                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vneg(Vu32.sf)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vneg_Vsf(Vu)                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv)                                         \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+   Assembly Syntax:       Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv)                                         \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#endif /* __HVX__ */
+
+#endif
diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 9d4e80f8f2..4bd5a35549 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -72,16 +72,16 @@ impl VectorMode {
     }
 }
 
-/// LLVM tag to fetch the header from
-const LLVM_TAG: &str = "llvmorg-22.1.0-rc1";
+/// LLVM version the header file is from (for reference)
+/// Source: https://github.com/llvm/llvm-project/blob/llvmorg-22.1.0-rc1/clang/lib/Headers/hvx_hexagon_protos.h
+const LLVM_VERSION: &str = "22.1.0-rc1";
 
 /// Maximum HVX architecture version supported by rustc
 /// Check with: rustc --target=hexagon-unknown-linux-musl --print target-features
 const MAX_SUPPORTED_ARCH: u32 = 79;
 
-/// URL template for the HVX header file
-const HEADER_URL: &str =
-    "https://raw.githubusercontent.com/llvm/llvm-project/{tag}/clang/lib/Headers/hvx_hexagon_protos.h";
+/// Local header file path (checked into the repository)
+const HEADER_FILE: &str = "hvx_hexagon_protos.h";
 
 /// Intrinsic information parsed from the LLVM header
 #[derive(Debug, Clone)]
@@ -306,18 +306,14 @@ fn collect_builtins_from_expr(expr: &CompoundExpr, builtins: &mut HashSet<String
     }
 }
 
-/// Download the LLVM HVX header file
-fn download_header() -> Result<String, String> {
-    let url = HEADER_URL.replace("{tag}", LLVM_TAG);
-    println!("Downloading HVX header from: {}", url);
+/// Read the local HVX header file
+fn read_header(crate_dir: &Path) -> Result<String, String> {
+    let header_path = crate_dir.join(HEADER_FILE);
+    println!("Reading HVX header from: {}", header_path.display());
+    println!("  (LLVM version: {})", LLVM_VERSION);
 
-    let response = ureq::get(&url)
-        .call()
-        .map_err(|e| format!("Failed to download header: {}", e))?;
-
-    response
-        .into_string()
-        .map_err(|e| format!("Failed to read response: {}", e))
+    std::fs::read_to_string(&header_path)
+        .map_err(|e| format!("Failed to read header file {}: {}", header_path.display(), e))
 }
 
 /// Parse a C function prototype to extract return type and parameters
@@ -1625,10 +1621,15 @@ fn generate_module_file(
 fn main() -> Result<(), String> {
     println!("=== Hexagon HVX Code Generator ===\n");
 
-    // Download and parse the LLVM header
-    println!("Step 1: Downloading LLVM HVX header...");
-    let header_content = download_header()?;
-    println!("  Downloaded {} bytes", header_content.len());
+    // Get the crate directory first (needed for both reading header and writing output)
+    let crate_dir = std::env::var("CARGO_MANIFEST_DIR")
+        .map(std::path::PathBuf::from)
+        .unwrap_or_else(|_| std::env::current_dir().unwrap());
+
+    // Read and parse the local LLVM header
+    println!("Step 1: Reading LLVM HVX header...");
+    let header_content = read_header(&crate_dir)?;
+    println!("  Read {} bytes", header_content.len());
 
     println!("\nStep 2: Parsing intrinsic definitions...");
     let all_intrinsics = parse_header(&header_content);
@@ -1678,10 +1679,6 @@ fn main() -> Result<(), String> {
     }
 
     // Generate output files
-    let crate_dir = std::env::var("CARGO_MANIFEST_DIR")
-        .map(std::path::PathBuf::from)
-        .unwrap_or_else(|_| std::env::current_dir().unwrap());
-
     let hexagon_dir = crate_dir.join("../core_arch/src/hexagon");
 
     // Generate v64.rs (64-byte vector mode)

From fd0f53cc69962be59d82ed3b51f0c064f0ee515d Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Sun, 15 Feb 2026 12:13:00 -0600
Subject: [PATCH 149/326] core_arch: Add tracking issue to hexagon module
 declaration

Update the unstable attribute for the hexagon module to use the
proper tracking issue number (151523) instead of "none".
---
 crates/core_arch/src/mod.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs
index f8ea68b35c..2483d07b23 100644
--- a/crates/core_arch/src/mod.rs
+++ b/crates/core_arch/src/mod.rs
@@ -329,7 +329,7 @@ pub mod arch {
     /// See the [module documentation](../index.html) for more details.
     #[cfg(any(target_arch = "hexagon", doc))]
     #[doc(cfg(target_arch = "hexagon"))]
-    #[unstable(feature = "stdarch_hexagon", issue = "none")]
+    #[unstable(feature = "stdarch_hexagon", issue = "151523")]
     pub mod hexagon {
         pub use crate::core_arch::hexagon::*;
     }

From 1f3d1eb2424a1e3c9aebf45f9425daa7402d0775 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Sun, 15 Feb 2026 12:18:19 -0600
Subject: [PATCH 150/326] stdarch-gen-hexagon: Fix formatting

---
 crates/stdarch-gen-hexagon/src/main.rs | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 4bd5a35549..3cfbabfe0a 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -312,8 +312,13 @@ fn read_header(crate_dir: &Path) -> Result<String, String> {
     println!("Reading HVX header from: {}", header_path.display());
     println!("  (LLVM version: {})", LLVM_VERSION);
 
-    std::fs::read_to_string(&header_path)
-        .map_err(|e| format!("Failed to read header file {}: {}", header_path.display(), e))
+    std::fs::read_to_string(&header_path).map_err(|e| {
+        format!(
+            "Failed to read header file {}: {}",
+            header_path.display(),
+            e
+        )
+    })
 }
 
 /// Parse a C function prototype to extract return type and parameters

From 40c62a4e6969a7f65b6331f70a07f10be3c509ce Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 16 Feb 2026 04:48:11 +0000
Subject: [PATCH 151/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to 139651428df86cf88443295542c12ea617cbb587.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index aa3876b14a..b22c6c3869 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-db3e99bbab28c6ca778b13222becdea54533d908
+139651428df86cf88443295542c12ea617cbb587

From db675e42af95a964d98ee61d0861574e25ebbcd8 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 14 Feb 2026 15:43:32 +0100
Subject: [PATCH 152/326] use `intrinsics::simd` for `vmull_*`

---
 .../src/arm_shared/neon/generated.rs          | 60 ++-----------------
 .../spec/neon/arm_shared.spec.yml             | 22 +++----
 2 files changed, 14 insertions(+), 68 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index c2e90d41ef..a578f6c158 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -33216,15 +33216,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smull.v4i32"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i32")]
-        fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
-    }
-    unsafe { _vmull_s16(a, b) }
+    unsafe { simd_mul(simd_cast(a), simd_cast(b)) }
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
@@ -33245,15 +33237,7 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smull.v2i64"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i64")]
-        fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
-    }
-    unsafe { _vmull_s32(a, b) }
+    unsafe { simd_mul(simd_cast(a), simd_cast(b)) }
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
@@ -33274,15 +33258,7 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smull.v8i16"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i16")]
-        fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t;
-    }
-    unsafe { _vmull_s8(a, b) }
+    unsafe { simd_mul(simd_cast(a), simd_cast(b)) }
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
@@ -33303,15 +33279,7 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umull.v8i16"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i16")]
-        fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t;
-    }
-    unsafe { _vmull_u8(a, b) }
+    unsafe { simd_mul(simd_cast(a), simd_cast(b)) }
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
@@ -33332,15 +33300,7 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umull.v4i32"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i32")]
-        fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t;
-    }
-    unsafe { _vmull_u16(a, b) }
+    unsafe { simd_mul(simd_cast(a), simd_cast(b)) }
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
@@ -33361,15 +33321,7 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umull.v2i64"
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i64")]
-        fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t;
-    }
-    unsafe { _vmull_u32(a, b) }
+    unsafe { simd_mul(simd_cast(a), simd_cast(b)) }
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index c726d1a028..404e67b3c5 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6507,13 +6507,10 @@ intrinsics:
       - ["s16", int16x4_t, int32x4_t]
       - ["s32", int32x2_t, int64x2_t]
     compose:
-      - LLVMLink:
-          name: "smull.{neon_type[1]}"
-          links:
-            - link: "llvm.aarch64.neon.smull.{neon_type[2]}"
-              arch: aarch64,arm64ec
-            - link: "llvm.arm.neon.vmulls.{neon_type[2]}"
-              arch: arm
+      - FnCall:
+          - simd_mul
+          - - FnCall: ['simd_cast', [a]]
+            - FnCall: ['simd_cast', [b]]
 
   - name: "vmull{neon_type[1].no}"
     doc: "Unsigned multiply long"
@@ -6531,13 +6528,10 @@ intrinsics:
       - ["u16", uint16x4_t, uint32x4_t]
       - ["u32", uint32x2_t, uint64x2_t]
     compose:
-      - LLVMLink:
-          name: "smull.{neon_type[1]}"
-          links:
-            - link: "llvm.aarch64.neon.umull.{neon_type[2]}"
-              arch: aarch64,arm64ec
-            - link: "llvm.arm.neon.vmullu.{neon_type[2]}"
-              arch: arm
+      - FnCall:
+          - simd_mul
+          - - FnCall: ['simd_cast', [a]]
+            - FnCall: ['simd_cast', [b]]
 
   - name: "vmull{neon_type[1].no}"
     doc: "Polynomial multiply long"

From adb550afcc5e7612adf79cbdbf7d0e0b10e1ceb1 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 17 Feb 2026 11:29:05 +0100
Subject: [PATCH 153/326] use `read_unaligned` for f64 `vld` and `vldq`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 78 +++++--------------
 crates/core_arch/src/aarch64/neon/mod.rs      |  8 ++
 .../spec/neon/aarch64.spec.yml                | 15 ++--
 3 files changed, 34 insertions(+), 67 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index a0647551e4..28db407924 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11488,16 +11488,9 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld1))]
-pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v1f64.p0"
-        )]
-        fn _vld1_f64_x2(a: *const f64) -> float64x1x2_t;
-    }
-    _vld1_f64_x2(a)
+#[cfg_attr(test, assert_instr(ld))]
+pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t {
+    crate::ptr::read_unaligned(ptr.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
@@ -11506,16 +11499,9 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld1))]
-pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v1f64.p0"
-        )]
-        fn _vld1_f64_x3(a: *const f64) -> float64x1x3_t;
-    }
-    _vld1_f64_x3(a)
+#[cfg_attr(test, assert_instr(ld))]
+pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t {
+    crate::ptr::read_unaligned(ptr.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
@@ -11524,16 +11510,9 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld1))]
-pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v1f64.p0"
-        )]
-        fn _vld1_f64_x4(a: *const f64) -> float64x1x4_t;
-    }
-    _vld1_f64_x4(a)
+#[cfg_attr(test, assert_instr(ld))]
+pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t {
+    crate::ptr::read_unaligned(ptr.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
@@ -11542,16 +11521,9 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld1))]
-pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x2.v2f64.p0"
-        )]
-        fn _vld1q_f64_x2(a: *const f64) -> float64x2x2_t;
-    }
-    _vld1q_f64_x2(a)
+#[cfg_attr(test, assert_instr(ld))]
+pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t {
+    crate::ptr::read_unaligned(ptr.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
@@ -11560,16 +11532,9 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld1))]
-pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x3.v2f64.p0"
-        )]
-        fn _vld1q_f64_x3(a: *const f64) -> float64x2x3_t;
-    }
-    _vld1q_f64_x3(a)
+#[cfg_attr(test, assert_instr(ld))]
+pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t {
+    crate::ptr::read_unaligned(ptr.cast())
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
@@ -11578,16 +11543,9 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld1))]
-pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld1x4.v2f64.p0"
-        )]
-        fn _vld1q_f64_x4(a: *const f64) -> float64x2x4_t;
-    }
-    _vld1q_f64_x4(a)
+#[cfg_attr(test, assert_instr(ld))]
+pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t {
+    crate::ptr::read_unaligned(ptr.cast())
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 135d0a156d..c39b3e93af 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -1093,6 +1093,14 @@ mod tests {
         test_vld1q_f32_x3(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3);
         test_vld1q_f32_x4(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4);
 
+        test_vld1_f64_x2(f64, 2, float64x1x2_t, vst1_f64_x2, vld1_f64_x2);
+        test_vld1_f64_x3(f64, 3, float64x1x3_t, vst1_f64_x3, vld1_f64_x3);
+        test_vld1_f64_x4(f64, 4, float64x1x4_t, vst1_f64_x4, vld1_f64_x4);
+
+        test_vld1q_f64_x2(f64, 4, float64x2x2_t, vst1q_f64_x2, vld1q_f64_x2);
+        test_vld1q_f64_x3(f64, 6, float64x2x3_t, vst1q_f64_x3, vld1q_f64_x3);
+        test_vld1q_f64_x4(f64, 8, float64x2x4_t, vst1q_f64_x4, vld1q_f64_x4);
+
         test_vld1_s8_x2(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2);
         test_vld1_s8_x3(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3);
         test_vld1_s8_x4(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4);
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 95f23ebd9a..ec9d49a510 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -3479,10 +3479,10 @@ intrinsics:
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
-    arguments: ["a: {type[0]}"]
+    arguments: ["ptr: {type[0]}"]
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
-    assert_instr: [ld1]
+    assert_instr: [ld]
     safety:
       unsafe: [neon]
     types:
@@ -3493,11 +3493,12 @@ intrinsics:
       - ["*const f64", float64x1x4_t]
       - ["*const f64", float64x2x4_t]
     compose:
-      - LLVMLink:
-          name: "vld1{neon_type[1].no}"
-          links:
-            - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0"
-              arch: aarch64,arm64ec
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - ptr
+                - cast
+                - []
 
   - name: "vld2{neon_type[1].lane_nox}"
     doc: Load multiple 2-element structures to two registers

From 20df9649b3dfe78a6a57435fe394f91d5f9e58a3 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 17 Feb 2026 17:22:33 +0100
Subject: [PATCH 154/326] test interleaving load/store roundtrip

---
 crates/core_arch/src/aarch64/neon/mod.rs | 98 ++++++++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 135d0a156d..3777cc7bdf 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -1173,6 +1173,104 @@ mod tests {
         test_vld1q_p16_x3(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3);
         test_vld1q_p16_x4(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4);
     }
+
+    wide_store_load_roundtrip_neon! {
+        test_vld2_f32_x2(f32, 4, float32x2x2_t, vst2_f32, vld2_f32);
+        test_vld2_f32_x3(f32, 6, float32x2x3_t, vst3_f32, vld3_f32);
+        test_vld2_f32_x4(f32, 8, float32x2x4_t, vst4_f32, vld4_f32);
+
+        test_vld2q_f32_x2(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32);
+        test_vld3q_f32_x3(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32);
+        test_vld4q_f32_x4(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32);
+
+        test_vld2_f64_x2(f64, 2, float64x1x2_t, vst2_f64, vld2_f64);
+        test_vld2_f64_x3(f64, 3, float64x1x3_t, vst3_f64, vld3_f64);
+        test_vld2_f64_x4(f64, 4, float64x1x4_t, vst4_f64, vld4_f64);
+
+        test_vld2q_f64_x2(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64);
+        test_vld3q_f64_x3(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64);
+        test_vld4q_f64_x4(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64);
+
+        test_vld2_s8_x2(i8, 16, int8x8x2_t, vst2_s8, vld2_s8);
+        test_vld2_s8_x3(i8, 24, int8x8x3_t, vst3_s8, vld3_s8);
+        test_vld2_s8_x4(i8, 32, int8x8x4_t, vst4_s8, vld4_s8);
+
+        test_vld2q_s8_x2(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8);
+        test_vld3q_s8_x3(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8);
+        test_vld4q_s8_x4(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8);
+
+        test_vld2_s16_x2(i16, 8, int16x4x2_t, vst2_s16, vld2_s16);
+        test_vld2_s16_x3(i16, 12, int16x4x3_t, vst3_s16, vld3_s16);
+        test_vld2_s16_x4(i16, 16, int16x4x4_t, vst4_s16, vld4_s16);
+
+        test_vld2q_s16_x2(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16);
+        test_vld3q_s16_x3(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16);
+        test_vld4q_s16_x4(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16);
+
+        test_vld2_s32_x2(i32, 4, int32x2x2_t, vst2_s32, vld2_s32);
+        test_vld2_s32_x3(i32, 6, int32x2x3_t, vst3_s32, vld3_s32);
+        test_vld2_s32_x4(i32, 8, int32x2x4_t, vst4_s32, vld4_s32);
+
+        test_vld2q_s32_x2(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32);
+        test_vld3q_s32_x3(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32);
+        test_vld4q_s32_x4(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32);
+
+        test_vld2_s64_x2(i64, 2, int64x1x2_t, vst2_s64, vld2_s64);
+        test_vld2_s64_x3(i64, 3, int64x1x3_t, vst3_s64, vld3_s64);
+        test_vld2_s64_x4(i64, 4, int64x1x4_t, vst4_s64, vld4_s64);
+
+        test_vld2q_s64_x2(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64);
+        test_vld3q_s64_x3(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64);
+        test_vld4q_s64_x4(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64);
+
+        test_vld2_u8_x2(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8);
+        test_vld2_u8_x3(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8);
+        test_vld2_u8_x4(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8);
+
+        test_vld2q_u8_x2(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8);
+        test_vld3q_u8_x3(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8);
+        test_vld4q_u8_x4(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8);
+
+        test_vld2_u16_x2(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16);
+        test_vld2_u16_x3(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16);
+        test_vld2_u16_x4(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16);
+
+        test_vld2q_u16_x2(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16);
+        test_vld3q_u16_x3(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16);
+        test_vld4q_u16_x4(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16);
+
+        test_vld2_u32_x2(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32);
+        test_vld2_u32_x3(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32);
+        test_vld2_u32_x4(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32);
+
+        test_vld2q_u32_x2(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32);
+        test_vld3q_u32_x3(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32);
+        test_vld4q_u32_x4(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32);
+
+        test_vld2_u64_x2(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64);
+        test_vld2_u64_x3(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64);
+        test_vld2_u64_x4(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64);
+
+        test_vld2q_u64_x2(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64);
+        test_vld3q_u64_x3(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64);
+        test_vld4q_u64_x4(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64);
+
+        test_vld2_p8_x2(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8);
+        test_vld2_p8_x3(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8);
+        test_vld2_p8_x4(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8);
+
+        test_vld2q_p8_x2(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8);
+        test_vld3q_p8_x3(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8);
+        test_vld4q_p8_x4(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8);
+
+        test_vld2_p16_x2(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16);
+        test_vld2_p16_x3(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16);
+        test_vld2_p16_x4(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16);
+
+        test_vld2q_p16_x2(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16);
+        test_vld3q_p16_x3(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16);
+        test_vld4q_p16_x4(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16);
+    }
 }
 
 #[cfg(test)]

From 965ef664256ce36103e80423ba06da0fde9ce1e2 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 17 Feb 2026 18:18:10 +0100
Subject: [PATCH 155/326] fix interleaving read/write not roundtripping on
 aarch64_be

---
 .../core_arch/src/aarch64/neon/generated.rs   | 1413 +-------------
 .../src/arm_shared/neon/generated.rs          | 1642 ++++-------------
 .../spec/neon/aarch64.spec.yml                |   24 +-
 .../spec/neon/arm_shared.spec.yml             |    7 +
 4 files changed, 381 insertions(+), 2705 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index a0647551e4..9a8a9ad59e 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11962,28 +11962,12 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
 pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
     transmute(vld2q_s64(transmute(a)))
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld2))]
-pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
-    let mut ret_val: uint64x2x2_t = transmute(vld2q_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val
-}
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
 #[doc = "## Safety"]
@@ -12389,29 +12373,12 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
     transmute(vld3q_s64(transmute(a)))
 }
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld3))]
-pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
-    let mut ret_val: uint64x2x3_t = transmute(vld3q_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val
-}
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
 #[doc = "## Safety"]
@@ -12825,30 +12792,12 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
     transmute(vld4q_s64(transmute(a)))
 }
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld4))]
-pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
-    let mut ret_val: uint64x2x4_t = transmute(vld4q_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
-    ret_val
-}
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
 #[doc = "## Safety"]
@@ -19739,7 +19688,6 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19747,38 +19695,8 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x16x2_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19786,43 +19704,8 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
     unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
-    let mut a: uint8x16x2_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19830,38 +19713,8 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x16x2_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19869,40 +19722,6 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
     unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
-    let mut a: poly8x16x2_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -19955,7 +19774,6 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19963,46 +19781,8 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x16x3_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t =
-            transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20010,51 +19790,8 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
     unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
-    let mut a: uint8x16x3_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x16_t =
-            transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20062,46 +19799,8 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x16x3_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t =
-            transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20109,48 +19808,6 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
     unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
-    let mut a: poly8x16x3_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x16_t =
-            transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -20215,7 +19872,6 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20231,64 +19887,14 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x16x4_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.3 = unsafe {
-        simd_shuffle!(
-            a.3,
-            a.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbl4(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(a.3),
-            b,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
-    unsafe {
-        transmute(vqtbl4q(
+        transmute(vqtbl4q(
             transmute(a.0),
             transmute(a.1),
             transmute(a.2),
@@ -20298,63 +19904,8 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
     }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
-    let mut a: uint8x16x4_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.3 = unsafe {
-        simd_shuffle!(
-            a.3,
-            a.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x16_t = transmute(vqtbl4q(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(a.3),
-            b,
-        ));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20370,58 +19921,8 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x16x4_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.3 = unsafe {
-        simd_shuffle!(
-            a.3,
-            a.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbl4(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(a.3),
-            b,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20436,60 +19937,6 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
         ))
     }
 }
-#[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
-    let mut a: poly8x16x4_t = a;
-    a.0 = unsafe {
-        simd_shuffle!(
-            a.0,
-            a.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.1 = unsafe {
-        simd_shuffle!(
-            a.1,
-            a.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.2 = unsafe {
-        simd_shuffle!(
-            a.2,
-            a.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    a.3 = unsafe {
-        simd_shuffle!(
-            a.3,
-            a.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x16_t = transmute(vqtbl4q(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(a.3),
-            b,
-        ));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"]
 #[inline(always)]
@@ -20629,7 +20076,6 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20637,39 +20083,8 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x16x2_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20677,46 +20092,8 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
     unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
-    let mut b: uint8x16x2_t = b;
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x16_t =
-            transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20724,39 +20101,8 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x16x2_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20764,43 +20110,6 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
     unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
-    let mut b: poly8x16x2_t = b;
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x16_t =
-            transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -20860,7 +20169,6 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20876,52 +20184,8 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x16x3_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbx3(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            c,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20937,58 +20201,8 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
-    let mut b: uint8x16x3_t = b;
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x16_t = transmute(vqtbx3q(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            c,
-        ));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21004,52 +20218,8 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x16x3_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbx3(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            c,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21065,55 +20235,6 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
-    let mut b: poly8x16x3_t = b;
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x16_t = transmute(vqtbx3q(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            c,
-        ));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -21183,168 +20304,21 @@ pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t {
     vqtbx4(a, b.0, b.1, b.2, b.3, c)
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
-    vqtbx4q(a, b.0, b.1, b.2, b.3, c)
-}
-#[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
-    unsafe {
-        transmute(vqtbx4(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(b.3),
-            c,
-        ))
-    }
-}
-#[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x16x4_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.3 = unsafe {
-        simd_shuffle!(
-            b.3,
-            b.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbx4(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(b.3),
-            c,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
-    unsafe {
-        transmute(vqtbx4q(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(b.3),
-            c,
-        ))
-    }
-}
-#[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
-    let mut b: uint8x16x4_t = b;
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.3 = unsafe {
-        simd_shuffle!(
-            b.3,
-            b.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x16_t = transmute(vqtbx4q(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(b.3),
-            c,
-        ));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
+#[inline(always)]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(tbx))]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
+    vqtbx4q(a, b.0, b.1, b.2, b.3, c)
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
+pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
     unsafe {
         transmute(vqtbx4(
             transmute(a),
@@ -21357,66 +20331,32 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x16x4_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.3 = unsafe {
-        simd_shuffle!(
-            b.3,
-            b.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
+pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
     unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbx4(
+        transmute(vqtbx4q(
             transmute(a),
             transmute(b.0),
             transmute(b.1),
             transmute(b.2),
             transmute(b.3),
             c,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        ))
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
+pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
     unsafe {
-        transmute(vqtbx4q(
+        transmute(vqtbx4(
             transmute(a),
             transmute(b.0),
             transmute(b.1),
@@ -21429,58 +20369,19 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
-    let mut b: poly8x16x4_t = b;
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe {
-        simd_shuffle!(
-            b.0,
-            b.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.1 = unsafe {
-        simd_shuffle!(
-            b.1,
-            b.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.2 = unsafe {
-        simd_shuffle!(
-            b.2,
-            b.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    b.3 = unsafe {
-        simd_shuffle!(
-            b.3,
-            b.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
-        let ret_val: poly8x16_t = transmute(vqtbx4q(
+        transmute(vqtbx4q(
             transmute(a),
             transmute(b.0),
             transmute(b.1),
             transmute(b.2),
             transmute(b.3),
             c,
-        ));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        ))
     }
 }
 #[doc = "Rotate and exclusive OR"]
@@ -27421,7 +26322,6 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27429,26 +26329,8 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x8x2_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27456,23 +26338,6 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x8x2_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -27488,7 +26353,6 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27500,31 +26364,8 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x8x3_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let x = uint8x16x2_t(
-        vcombine_u8(a.0, a.1),
-        vcombine_u8(a.2, unsafe { crate::mem::zeroed() }),
-    );
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27536,28 +26377,6 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x8x3_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let x = poly8x16x2_t(
-        vcombine_p8(a.0, a.1),
-        vcombine_p8(a.2, unsafe { crate::mem::zeroed() }),
-    );
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -27570,7 +26389,6 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27579,29 +26397,8 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x8x4_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3));
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27609,26 +26406,6 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
     let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3));
     unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
 }
-#[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbl))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x8x4_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3));
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
 #[inline(always)]
@@ -27698,7 +26475,6 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27706,28 +26482,8 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x8x2_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t =
-            transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27735,25 +26491,6 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x8x2_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t =
-            transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -27780,7 +26517,6 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27798,36 +26534,8 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x8x3_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let x = uint8x16x2_t(
-        vcombine_u8(b.0, b.1),
-        vcombine_u8(b.2, unsafe { crate::mem::zeroed() }),
-    );
-    unsafe {
-        let ret_val: uint8x8_t = transmute(simd_select(
-            simd_lt::<uint8x8_t, int8x8_t>(transmute(c), transmute(u8x8::splat(24))),
-            transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)),
-            a,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27845,33 +26553,6 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x8x3_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let x = poly8x16x2_t(
-        vcombine_p8(b.0, b.1),
-        vcombine_p8(b.2, unsafe { crate::mem::zeroed() }),
-    );
-    unsafe {
-        let ret_val: poly8x8_t = transmute(simd_select(
-            simd_lt::<poly8x8_t, int8x8_t>(transmute(c), transmute(u8x8::splat(24))),
-            transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)),
-            a,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
@@ -27890,7 +26571,6 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27905,34 +26585,8 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x8x4_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vqtbx2(
-            transmute(a),
-            transmute(vcombine_u8(b.0, b.1)),
-            transmute(vcombine_u8(b.2, b.3)),
-            c,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27946,31 +26600,6 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
         ))
     }
 }
-#[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(tbx))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x8x4_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: poly8x8_t = transmute(vqtbx2(
-            transmute(a),
-            transmute(vcombine_p8(b.0, b.1)),
-            transmute(vcombine_p8(b.2, b.3)),
-            c,
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
 #[inline(always)]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index d05d376402..06a6381ccd 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -20755,7 +20755,6 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20775,11 +20774,10 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
     transmute(vld2_s8(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20795,18 +20793,14 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
-    let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
+    transmute(vld2q_s8(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20822,15 +20816,14 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
-    transmute(vld2q_s8(transmute(a)))
+pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
+    transmute(vld2_s16(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20846,30 +20839,14 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
-    let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
+    transmute(vld2q_s16(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20885,15 +20862,14 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
-    transmute(vld2_s16(transmute(a)))
+pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
+    transmute(vld2_s32(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20909,18 +20885,14 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
-    let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
+    transmute(vld2q_s32(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20936,15 +20908,14 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
-    transmute(vld2q_s16(transmute(a)))
+pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
+    transmute(vld2_s8(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20960,18 +20931,14 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
-    let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
+    transmute(vld2q_s8(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20987,15 +20954,14 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
-    transmute(vld2_s32(transmute(a)))
+pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
+    transmute(vld2_s16(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -21011,386 +20977,116 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
-    let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val
+pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
+    transmute(vld2q_s16(transmute(a)))
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
+#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
-    transmute(vld2q_s32(transmute(a)))
+#[cfg(target_arch = "arm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")]
+        fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
+    }
+    _vld3_dup_f16(a as _, 2)
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
+#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
-    let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val
+#[cfg(target_arch = "arm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")]
+        fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
+    }
+    _vld3q_dup_f16(a as _, 2)
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
+#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
+#[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+    assert_instr(ld3r)
 )]
-pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
-    transmute(vld2_s8(transmute(a)))
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.ld3r.v4f16.p0"
+        )]
+        fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
+    }
+    _vld3_dup_f16(a as _)
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
+#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
+#[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+    assert_instr(ld3r)
 )]
-pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
-    let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.ld3r.v8f16.p0"
+        )]
+        fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
+    }
+    _vld3q_dup_f16(a as _)
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
+#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
-    transmute(vld2q_s8(transmute(a)))
+#[cfg(not(target_arch = "arm"))]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(ld3r))]
+pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
+        )]
+        fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
+    }
+    _vld3_dup_f32(a as _)
 }
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
-    let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
-}
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
-    transmute(vld2_s16(transmute(a)))
-}
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
-    let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
-    transmute(vld2q_s16(transmute(a)))
-}
-#[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
-    let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")]
-        fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
-    }
-    _vld3_dup_f16(a as _, 2)
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")]
-        fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
-    }
-    _vld3q_dup_f16(a as _, 2)
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg(not(target_arch = "arm"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3r.v4f16.p0"
-        )]
-        fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
-    }
-    _vld3_dup_f16(a as _)
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg(not(target_arch = "arm"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3r.v8f16.p0"
-        )]
-        fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
-    }
-    _vld3q_dup_f16(a as _)
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg(not(target_arch = "arm"))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld3r))]
-pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
-        )]
-        fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
-    }
-    _vld3_dup_f32(a as _)
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
+#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
@@ -23396,7 +23092,6 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23416,11 +23111,10 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
     transmute(vld3_s8(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23436,19 +23130,14 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
-    let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
+    transmute(vld3q_s8(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23464,15 +23153,14 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
-    transmute(vld3q_s8(transmute(a)))
+pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
+    transmute(vld3_s16(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23488,37 +23176,14 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
-    let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
+    transmute(vld3q_s16(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23534,15 +23199,14 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
-    transmute(vld3_s16(transmute(a)))
+pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
+    transmute(vld3_s32(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23558,19 +23222,14 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
-    let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
+    transmute(vld3q_s32(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23586,15 +23245,14 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
-    transmute(vld3q_s16(transmute(a)))
+pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
+    transmute(vld3_s8(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23610,19 +23268,14 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
-    let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
+    transmute(vld3q_s8(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23638,15 +23291,14 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
-    transmute(vld3_s32(transmute(a)))
+pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
+    transmute(vld3_s16(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23662,397 +23314,115 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
-    let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val
+pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
+    transmute(vld3q_s16(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
-    transmute(vld3q_s32(transmute(a)))
+#[cfg(target_arch = "arm")]
+#[target_feature(enable = "neon,v7")]
+#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
+        fn _vld3q_lane_f32(
+            ptr: *const i8,
+            a: float32x4_t,
+            b: float32x4_t,
+            c: float32x4_t,
+            n: i32,
+            size: i32,
+        ) -> float32x4x3_t;
+    }
+    _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
 }
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
+#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
-    let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val
+#[cfg(target_arch = "arm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[target_feature(enable = "neon,fp16")]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")]
+        fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
+    }
+    _vld4_dup_f16(a as _, 2)
 }
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
+#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
-    transmute(vld3_s8(transmute(a)))
+#[cfg(target_arch = "arm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[target_feature(enable = "neon,fp16")]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")]
+        fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
+    }
+    _vld4q_dup_f16(a as _, 2)
 }
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
+#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
+#[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+    assert_instr(ld4r)
 )]
-pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
-    let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+#[target_feature(enable = "neon,fp16")]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.ld4r.v4f16.p0"
+        )]
+        fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
+    }
+    _vld4_dup_f16(a as _)
 }
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
+#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
+#[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+    assert_instr(ld4r)
 )]
-pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
-    transmute(vld3q_s8(transmute(a)))
-}
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
-    let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
-}
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
-    transmute(vld3_s16(transmute(a)))
-}
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
-    let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
-    transmute(vld3q_s16(transmute(a)))
-}
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
-    let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
-#[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
-        fn _vld3q_lane_f32(
-            ptr: *const i8,
-            a: float32x4_t,
-            b: float32x4_t,
-            c: float32x4_t,
-            n: i32,
-            size: i32,
-        ) -> float32x4x3_t;
-    }
-    _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")]
-        fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
-    }
-    _vld4_dup_f16(a as _, 2)
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")]
-        fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
-    }
-    _vld4q_dup_f16(a as _, 2)
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(not(target_arch = "arm"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4r.v4f16.p0"
-        )]
-        fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
-    }
-    _vld4_dup_f16(a as _)
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(not(target_arch = "arm"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4r.v8f16.p0"
-        )]
-        fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
-    }
-    _vld4q_dup_f16(a as _)
+#[target_feature(enable = "neon,fp16")]
+#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
+#[cfg(not(target_arch = "arm64ec"))]
+pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.ld4r.v8f16.p0"
+        )]
+        fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
+    }
+    _vld4q_dup_f16(a as _)
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
@@ -25929,354 +25299,18 @@ pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) ->
     transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4, LANE = 0)
-)]
-#[rustc_legacy_const_generics(2)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
-    static_assert_uimm_bits!(LANE, 1);
-    transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4, LANE = 0)
-)]
-#[rustc_legacy_const_generics(2)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4, LANE = 0)
-)]
-#[rustc_legacy_const_generics(2)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
-    static_assert_uimm_bits!(LANE, 3);
-    transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4, LANE = 0)
-)]
-#[rustc_legacy_const_generics(2)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4, LANE = 0)
-)]
-#[rustc_legacy_const_generics(2)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
-    static_assert_uimm_bits!(LANE, 3);
-    transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
-    transmute(vld4_s64(transmute(a)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg(not(target_arch = "arm"))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
-        )]
-        fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
-    }
-    _vld4_s64(a as _)
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(nop))]
-pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
-        fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
-    }
-    _vld4_s64(a as *const i8, 8)
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
-    transmute(vld4_s64(transmute(a)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
-    transmute(vld4_s8(transmute(a)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
-    let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
-    transmute(vld4q_s8(transmute(a)))
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
-    let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.3 = unsafe {
-        simd_shuffle!(
-            ret_val.3,
-            ret_val.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
-}
-#[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
+    assert_instr(ld4, LANE = 0)
 )]
+#[rustc_legacy_const_generics(2)]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -26285,22 +25319,23 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
-    transmute(vld4_s16(transmute(a)))
+pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
+    assert_instr(ld4, LANE = 0)
 )]
+#[rustc_legacy_const_generics(2)]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -26309,27 +25344,23 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
-    let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
+    assert_instr(ld4, LANE = 0)
 )]
+#[rustc_legacy_const_generics(2)]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -26338,22 +25369,23 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
-    transmute(vld4q_s16(transmute(a)))
+pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
+    static_assert_uimm_bits!(LANE, 3);
+    transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
+    assert_instr(ld4, LANE = 0)
 )]
+#[rustc_legacy_const_generics(2)]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -26362,27 +25394,23 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
-    let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
+    assert_instr(ld4, LANE = 0)
 )]
+#[rustc_legacy_const_generics(2)]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -26391,21 +25419,79 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
-    transmute(vld4_s32(transmute(a)))
+pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
+    static_assert_uimm_bits!(LANE, 3);
+    transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon intrinsic unsafe"]
+#[inline(always)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,aes")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(nop)
+)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "neon_intrinsics", since = "1.59.0")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
+    transmute(vld4_s64(transmute(a)))
+}
+#[doc = "Load multiple 4-element structures to four registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon intrinsic unsafe"]
+#[inline(always)]
+#[target_feature(enable = "neon")]
+#[cfg(not(target_arch = "arm"))]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
+        )]
+        fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
+    }
+    _vld4_s64(a as _)
+}
+#[doc = "Load multiple 4-element structures to four registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon intrinsic unsafe"]
+#[inline(always)]
+#[target_feature(enable = "neon,v7")]
+#[cfg(target_arch = "arm")]
+#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
+#[cfg_attr(test, assert_instr(nop))]
+pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
+        fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
+    }
+    _vld4_s64(a as *const i8, 8)
+}
+#[doc = "Load multiple 4-element structures to four registers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4)
+    assert_instr(nop)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
@@ -26415,20 +25501,14 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
-    let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
-    ret_val
+pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
+    transmute(vld4_s64(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26444,15 +25524,14 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
-    transmute(vld4q_s32(transmute(a)))
+pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
+    transmute(vld4_s8(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26468,20 +25547,14 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
-    let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
+    transmute(vld4q_s8(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26497,15 +25570,14 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
-    transmute(vld4_s8(transmute(a)))
+pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
+    transmute(vld4_s16(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26521,20 +25593,14 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
-    let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
+    transmute(vld4q_s16(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26550,15 +25616,14 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
-    transmute(vld4q_s8(transmute(a)))
+pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
+    transmute(vld4_s32(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26574,44 +25639,14 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
-    let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.3 = unsafe {
-        simd_shuffle!(
-            ret_val.3,
-            ret_val.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val
+pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
+    transmute(vld4q_s32(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26627,15 +25662,14 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
-    transmute(vld4_s16(transmute(a)))
+pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
+    transmute(vld4_s8(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26651,20 +25685,14 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
-    let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
-    ret_val
+pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
+    transmute(vld4q_s8(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26680,15 +25708,14 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
-    transmute(vld4q_s16(transmute(a)))
+pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
+    transmute(vld4_s16(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26705,12 +25732,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
-    let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val
+    transmute(vld4q_s16(transmute(a)))
 }
 #[doc = "Store SIMD&FP register (immediate offset)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 95f23ebd9a..a10403de41 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -3715,6 +3715,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
     assert_instr: [ld2]
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4070,6 +4071,7 @@ intrinsics:
     arguments: ["a: {type[0]}"]
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     assert_instr: [ld3]
@@ -4216,6 +4218,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
     assert_instr: [ld4]
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4323,6 +4326,7 @@ intrinsics:
       - *neon-stable
     static_defs:
       - "const LANE: i32"
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4372,6 +4376,7 @@ intrinsics:
       - *neon-stable
     static_defs:
       - "const LANE: i32"
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -12176,6 +12181,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, uint8x8x4_t, uint8x8_t]
@@ -12243,6 +12249,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t']
@@ -12296,7 +12303,7 @@ intrinsics:
     types:
       - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t']
       - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t']
-    big_endian_inverse: true
+    big_endian_inverse: false
     compose:
       - Let:
           - x
@@ -12348,7 +12355,7 @@ intrinsics:
     types:
       - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t']
       - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t']
-    big_endian_inverse: true
+    big_endian_inverse: false
     compose:
       - Let:
           - x
@@ -12457,6 +12464,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x8x2_t', uint8x8_t]
@@ -12518,7 +12526,7 @@ intrinsics:
     types:
       - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8']
       - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8']
-    big_endian_inverse: true
+    big_endian_inverse: false
     compose:
       - Let:
          - x
@@ -12601,6 +12609,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t']
@@ -12637,6 +12646,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2']
@@ -12660,6 +12670,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3']
@@ -12674,6 +12685,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3']
@@ -12711,6 +12723,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3']
@@ -12735,6 +12748,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t']
@@ -12749,6 +12763,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t']
@@ -12787,6 +12802,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4']
@@ -12851,6 +12867,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t]
@@ -12870,6 +12887,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+    big_endian_inverse: false
     safety: safe
     types:
       - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 2dd2fb0d3f..76718dceca 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -2976,6 +2976,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -3006,6 +3007,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -3102,6 +3104,7 @@ intrinsics:
       - *neon-cfg-arm-unstable
     static_defs:
       - "const LANE: i32"
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4106,6 +4109,7 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     static_defs: ['const LANE: i32']
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4136,6 +4140,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4508,6 +4513,7 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4629,6 +4635,7 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     static_defs: ["const LANE: i32"]
+    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:

From 7fec806dc68d17e6a9c90acf0e1f489111a0d635 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 15 Feb 2026 00:22:53 +0100
Subject: [PATCH 156/326] lock stdout when printing a intrinsic test failure

---
 crates/intrinsic-test/src/common/compare.rs | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 5214349171..c22d7fd4ec 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -109,13 +109,26 @@ pub fn compare_outputs(
             }
         })
         .inspect(|(intrinsic, diffs)| {
-            println!("Difference for intrinsic: {intrinsic}");
+            use std::io::Write;
+
+            let stdout = std::io::stdout();
+            let mut out = stdout.lock();
+
+            writeln!(out, "Difference for intrinsic: {intrinsic}").unwrap();
             diffs.into_iter().for_each(|diff| match diff {
-                diff::Result::Left(c) => println!("C: {c}"),
-                diff::Result::Right(rust) => println!("Rust: {rust}"),
+                diff::Result::Left(c) => {
+                    writeln!(out, "C: {c}").unwrap();
+                }
+                diff::Result::Right(rust) => {
+                    writeln!(out, "Rust: {rust}").unwrap();
+                }
                 _ => (),
             });
-            println!("****************************************************************");
+            writeln!(
+                out,
+                "****************************************************************"
+            )
+            .unwrap();
         })
         .count();
 

From 7ee9c7776d098916b375d0a3f44454e9c83bc6f5 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 14 Feb 2026 22:11:00 +0100
Subject: [PATCH 157/326] use `intrinsics::simd` for aarch64 deinterleaving
 loads

---
 .../src/arm_shared/neon/generated.rs          | 72 +++----------------
 crates/core_arch/src/macros.rs                | 69 ++++++++++++++++++
 .../spec/neon/arm_shared.spec.yml             | 26 +++----
 3 files changed, 87 insertions(+), 80 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index b6951907eb..7b4f69a375 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -22079,14 +22079,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
-        )]
-        fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
-    }
-    _vld3_f32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
@@ -22098,14 +22091,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
-        )]
-        fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
-    }
-    _vld3q_f32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
@@ -22117,14 +22103,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
-        )]
-        fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
-    }
-    _vld3_s8(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
@@ -22136,14 +22115,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
-        )]
-        fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
-    }
-    _vld3q_s8(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
@@ -22155,14 +22127,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
-        )]
-        fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
-    }
-    _vld3_s16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
@@ -22174,14 +22139,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
-        )]
-        fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
-    }
-    _vld3q_s16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
@@ -22193,14 +22151,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
-        )]
-        fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
-    }
-    _vld3_s32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
@@ -22212,14 +22163,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
-        )]
-        fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
-    }
-    _vld3q_s32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 353829633f..d40ce51c74 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -186,3 +186,72 @@ macro_rules! simd_masked_store {
         $crate::intrinsics::simd::simd_masked_store::<_, _, _, { $align }>($mask, $ptr, $default)
     };
 }
+
+pub(crate) const fn deinterleave_mask<const LANES: usize, const N: usize, const K: usize>()
+-> [u32; LANES] {
+    // Produces: [K, K+N, K+2N, ...]
+    let mut out = [0u32; LANES];
+    let mut i = 0usize;
+    while i < LANES {
+        out[i] = (i * N + K) as u32;
+        i += 1;
+    }
+    out
+}
+
+#[allow(unused)]
+macro_rules! deinterleaving_load {
+    ($elem:ty, $lanes:literal, 2, $ptr:expr) => {{
+        use $crate::core_arch::macros::deinterleave_mask;
+        use $crate::core_arch::simd::Simd;
+        use $crate::{mem::transmute, ptr};
+
+        type V = Simd<$elem, $lanes>;
+        type W = Simd<$elem, { $lanes * 2 }>;
+
+        let w: W = ptr::read_unaligned($ptr as *const W);
+
+        let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 0>());
+        let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 1>());
+
+        transmute((v0, v1))
+    }};
+
+    ($elem:ty, $lanes:literal, 3, $ptr:expr) => {{
+        use $crate::core_arch::macros::deinterleave_mask;
+        use $crate::core_arch::simd::Simd;
+        use $crate::{mem::transmute, ptr};
+
+        type V = Simd<$elem, $lanes>;
+        type W = Simd<$elem, { $lanes * 3 }>;
+
+        let w: W = ptr::read_unaligned($ptr as *const W);
+
+        let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 0>());
+        let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 1>());
+        let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 2>());
+
+        transmute((v0, v1, v2))
+    }};
+
+    ($elem:ty, $lanes:literal, 4, $ptr:expr) => {{
+        use $crate::core_arch::macros::deinterleave_mask;
+        use $crate::core_arch::simd::Simd;
+        use $crate::{mem::transmute, ptr};
+
+        type V = Simd<$elem, $lanes>;
+        type W = Simd<$elem, { $lanes * 4 }>;
+
+        let w: W = ptr::read_unaligned($ptr as *const W);
+
+        let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 0>());
+        let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 1>());
+        let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 2>());
+        let v3: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 3>());
+
+        transmute((v0, v1, v2, v3))
+    }};
+}
+
+#[allow(unused)]
+pub(crate) use deinterleaving_load;
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 3f7adbc278..3b2e9f25ae 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -3875,23 +3875,17 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ['*const i8', int8x8x3_t, '*const int8x8_t', i8]
-      - ['*const i16', int16x4x3_t, '*const int16x4_t', i16]
-      - ['*const i32', int32x2x3_t, '*const int32x2_t', i32]
-      - ['*const i8', int8x16x3_t, '*const int8x16_t', i8]
-      - ['*const i16', int16x8x3_t, '*const int16x8_t', i16]
-      - ['*const i32', int32x4x3_t, '*const int32x4_t', i32]
-      - ['*const f32', float32x2x3_t, '*const float32x2_t', f32]
-      - ['*const f32', float32x4x3_t, '*const float32x4_t', f32]
+      - ['*const i8', int8x8x3_t, i8, "8"]
+      - ['*const i16', int16x4x3_t, i16, "4"]
+      - ['*const i32', int32x2x3_t, i32, "2"]
+      - ['*const i8', int8x16x3_t, i8, "16"]
+      - ['*const i16', int16x8x3_t, i16, "8"]
+      - ['*const i32', int32x4x3_t, i32, "4"]
+      - ['*const f32', float32x2x3_t, f32, "2"]
+      - ['*const f32', float32x4x3_t, f32, "4"]
     compose:
-      - LLVMLink:
-          name: 'vld3{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[2]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']]
+      - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true]
+
 
   - name: "vld3{neon_type[1].nox}"
     doc: Load multiple 3-element structures to three registers

From f2a3de279aa3706c20aec0bb8cb75de755b8a0e8 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 14 Feb 2026 22:46:20 +0100
Subject: [PATCH 158/326] neon `ld3`

---
 .../src/arm_shared/neon/generated.rs          | 27 ++---------------
 .../spec/neon/arm_shared.spec.yml             | 30 +++++++------------
 2 files changed, 13 insertions(+), 44 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 7b4f69a375..33213e58ff 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -22036,14 +22036,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v4f16.p0"
-        )]
-        fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
-    }
-    _vld3_f16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a)
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
@@ -22060,14 +22053,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v8f16.p0"
-        )]
-        fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
-    }
-    _vld3q_f16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
@@ -22983,14 +22969,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
-        )]
-        fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
-    }
-    _vld3_s64(a as _)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 3b2e9f25ae..968d5f99de 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -3669,19 +3669,11 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ["*const f16", float16x4x3_t, f16]
-      - ["*const f16", float16x8x3_t, f16]
+      - ["*const f16", float16x4x3_t, f16, "4"]
+      - ["*const f16", float16x8x3_t, f16, "8"]
     compose:
-      - LLVMLink:
-          name: "vld3.{neon_type[1]}"
-          arguments:
-            - "ptr: {type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[2]}.p0"
-              arch: aarch64,arm64ec
-      - FnCall:
-          - "_vld3{neon_type[1].nox}"
-          - - "a as _"
+      - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true]
+
 
   - name: "vld3{neon_type[1].dup_nox}"
     doc: Load single 3-element structure and replicate to all lanes of two registers
@@ -3900,14 +3892,12 @@ intrinsics:
     types:
       - ['*const i64', int64x1x3_t, '*const int64x1_t', i64]
     compose:
-      - LLVMLink:
-          name: "vld3{neon_type[1].nox}"
-          arguments:
-            - 'ptr: {type[2]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']]
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld3{neon_type[1].nox}"
     doc: Load multiple 3-element structures to three registers

From 1ccf7b7a61ba0367a102449527c03fd65acd2549 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 14 Feb 2026 23:03:39 +0100
Subject: [PATCH 159/326] neon `ld4`

---
 .../src/arm_shared/neon/generated.rs          | 99 +++----------------
 .../spec/neon/arm_shared.spec.yml             | 54 ++++------
 2 files changed, 29 insertions(+), 124 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 33213e58ff..45c83b880e 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -24336,14 +24336,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v4f16.p0"
-        )]
-        fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
-    }
-    _vld4_f16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a)
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
@@ -24359,14 +24352,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v8f16.p0"
-        )]
-        fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
-    }
-    _vld4q_f16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
@@ -24378,14 +24364,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
-        )]
-        fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
-    }
-    _vld4_f32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
@@ -24397,14 +24376,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
-        )]
-        fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
-    }
-    _vld4q_f32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
@@ -24416,14 +24388,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
-        )]
-        fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
-    }
-    _vld4_s8(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
@@ -24435,14 +24400,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
-        )]
-        fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
-    }
-    _vld4q_s8(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
@@ -24454,14 +24412,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
-        )]
-        fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
-    }
-    _vld4_s16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
@@ -24473,14 +24424,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
-        )]
-        fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
-    }
-    _vld4q_s16(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
@@ -24492,14 +24436,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
-        )]
-        fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
-    }
-    _vld4_s32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
@@ -24511,14 +24448,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
-        )]
-        fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
-    }
-    _vld4q_s32(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
@@ -25379,14 +25309,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
-        )]
-        fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
-    }
-    _vld4_s64(a as _)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 968d5f99de..8e10fff984 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -4357,23 +4357,16 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ['*const i8', int8x8x4_t, i8, '*const int8x8_t']
-      - ['*const i32', int32x4x4_t, i32, '*const int32x4_t']
-      - ['*const i16', int16x4x4_t, i16, '*const int16x4_t']
-      - ['*const i32', int32x2x4_t, i32, '*const int32x2_t']
-      - ['*const i8', int8x16x4_t, i8, '*const int8x16_t']
-      - ['*const i16', int16x8x4_t, i16, '*const int16x8_t']
-      - ['*const f32', float32x2x4_t, f32, '*const float32x2_t']
-      - ['*const f32', float32x4x4_t, f32, '*const float32x4_t']
+      - ['*const i8', int8x8x4_t, i8, "8"]
+      - ['*const i32', int32x4x4_t, i32, "4"]
+      - ['*const i16', int16x4x4_t, i16, "4"]
+      - ['*const i32', int32x2x4_t, i32, "2"]
+      - ['*const i8', int8x16x4_t, i8, "16"]
+      - ['*const i16', int16x8x4_t, i16, "8"]
+      - ['*const f32', float32x2x4_t, f32, "2"]
+      - ['*const f32', float32x4x4_t, f32, "4"]
     compose:
-      - LLVMLink:
-          name: 'vld4{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[3]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']]
+      - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true]
 
   - name: "vld4{neon_type[1].nox}"
     doc: Load multiple 4-element structures to four registers
@@ -4386,14 +4379,12 @@ intrinsics:
     types:
       - ['*const i64', int64x1x4_t, i64, '*const int64x1_t']
     compose:
-      - LLVMLink:
-          name: 'vld4{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[3]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']]
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld4{neon_type[1].lane_nox}"
     doc: Load multiple 4-element structures to four registers
@@ -12418,19 +12409,10 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ["*const f16", float16x4x4_t, f16]
-      - ["*const f16", float16x8x4_t, f16]
+      - ["*const f16", float16x4x4_t, f16, "4"]
+      - ["*const f16", float16x8x4_t, f16, "8"]
     compose:
-      - LLVMLink:
-          name: "vld4.{neon_type[1]}"
-          arguments:
-            - "ptr: {type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0"
-              arch: aarch64,arm64ec
-      - FnCall:
-          - "_vld4{neon_type[1].nox}"
-          - - "a as _"
+      - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true]
 
   - name: "vld4{neon_type[1].dup_nox}"
     doc: Load single 4-element structure and replicate to all lanes of two registers

From 8ba832904a299714f4b7254831c65fb38b7b72da Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 14 Feb 2026 23:09:35 +0100
Subject: [PATCH 160/326] neon `ld1`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 27 ++----------
 .../spec/neon/aarch64.spec.yml                | 42 ++++++++-----------
 2 files changed, 20 insertions(+), 49 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 9a8a9ad59e..119f903de7 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11652,14 +11652,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld2.v1f64.p0"
-        )]
-        fn _vld2_f64(ptr: *const float64x1_t) -> float64x1x2_t;
-    }
-    _vld2_f64(a as _)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
@@ -12031,14 +12024,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v1f64.p0"
-        )]
-        fn _vld3_f64(ptr: *const float64x1_t) -> float64x1x3_t;
-    }
-    _vld3_f64(a as _)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
@@ -12442,14 +12428,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v1f64.p0"
-        )]
-        fn _vld4_f64(ptr: *const float64x1_t) -> float64x1x4_t;
-    }
-    _vld4_f64(a as _)
+    crate::ptr::read_unaligned(a.cast())
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a10403de41..b81f04ebc0 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -3698,16 +3698,12 @@ intrinsics:
     types:
       - ["*const f64", float64x1x2_t, f64, float64x1_t]
     compose:
-      - LLVMLink:
-          name: "vld2.{neon_type[1]}"
-          arguments:
-            - "ptr: *const {neon_type[3]}"
-          links:
-            - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0"
-              arch: aarch64,arm64ec
       - FnCall:
-          - "_vld2{neon_type[1].nox}"
-          - - "a as _"
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld2{neon_type[1].nox}"
     doc: Load multiple 2-element structures to two registers
@@ -4057,14 +4053,12 @@ intrinsics:
     types:
       - ['*const f64', float64x1x3_t, '*const float64x1_t', f64]
     compose:
-      - LLVMLink:
-          name: 'vld3{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[2]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']]
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld3{neon_type[1].nox}"
     doc: Load multiple 3-element structures to three registers
@@ -4203,14 +4197,12 @@ intrinsics:
     types:
       - ['*const f64', float64x1x4_t, f64, '*const float64x1_t']
     compose:
-      - LLVMLink:
-          name: 'vld4{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[3]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']]
+      - FnCall:
+          - 'crate::ptr::read_unaligned'
+          - - MethodCall:
+                - a
+                - cast
+                - []
 
   - name: "vld4{neon_type[1].nox}"
     doc: Load multiple 4-element structures to four registers

From 6897f50fb22fb0148e62973120c37c897fb4afc9 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 15 Feb 2026 13:22:01 +0100
Subject: [PATCH 161/326] use `intrinsics::simd` for vpadd

---
 .../core_arch/src/aarch64/neon/generated.rs   | 155 +++++-------------
 crates/core_arch/src/macros.rs                |  24 ++-
 .../spec/neon/aarch64.spec.yml                |  91 +++++-----
 3 files changed, 102 insertions(+), 168 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 119f903de7..c0e46c30ef 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -16067,14 +16067,11 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(faddp))]
 pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.faddp.v8f16"
-        )]
-        fn _vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_f16(a, b) }
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"]
@@ -16083,14 +16080,11 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
 pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.faddp.v4f32"
-        )]
-        fn _vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_f32(a, b) }
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"]
@@ -16099,14 +16093,11 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
 pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.faddp.v2f64"
-        )]
-        fn _vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_f64(a, b) }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"]
@@ -16115,14 +16106,11 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.addp.v16i8"
-        )]
-        fn _vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_s8(a, b) }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"]
@@ -16131,14 +16119,11 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.addp.v8i16"
-        )]
-        fn _vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_s16(a, b) }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"]
@@ -16147,14 +16132,11 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.addp.v4i32"
-        )]
-        fn _vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_s32(a, b) }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"]
@@ -16163,119 +16145,62 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.addp.v2i64"
-        )]
-        fn _vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
+    unsafe {
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
+        simd_add(even, odd)
     }
-    unsafe { _vpaddq_s64(a, b) }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(addp))]
-pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
-    unsafe { transmute(vpaddq_s8(transmute(a), transmute(b))) }
-}
-#[doc = "Add Pairwise"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
-        let ret_val: uint8x16_t = transmute(vpaddq_s8(transmute(a), transmute(b)));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>());
+        simd_add(even, odd)
     }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(addp))]
-pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
-    unsafe { transmute(vpaddq_s16(transmute(a), transmute(b))) }
-}
-#[doc = "Add Pairwise"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
-        let ret_val: uint16x8_t = transmute(vpaddq_s16(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
+        simd_add(even, odd)
     }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(addp))]
-pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
-    unsafe { transmute(vpaddq_s32(transmute(a), transmute(b))) }
-}
-#[doc = "Add Pairwise"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
     unsafe {
-        let ret_val: uint32x4_t = transmute(vpaddq_s32(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
+        simd_add(even, odd)
     }
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(addp))]
-pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
-    unsafe { transmute(vpaddq_s64(transmute(a), transmute(b))) }
-}
-#[doc = "Add Pairwise"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
     unsafe {
-        let ret_val: uint64x2_t = transmute(vpaddq_s64(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
+        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
+        simd_add(even, odd)
     }
 }
 #[doc = "Floating-point add pairwise"]
diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index d40ce51c74..9f6922efee 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -187,9 +187,31 @@ macro_rules! simd_masked_store {
     };
 }
 
+/// The first N even indices `[0, 2, 4, ...]`.
+pub(crate) const fn even<const N: usize>() -> [u32; N] {
+    let mut out = [0u32; N];
+    let mut i = 0usize;
+    while i < N {
+        out[i] = (2 * i) as u32;
+        i += 1;
+    }
+    out
+}
+
+/// The first N odd indices `[1, 3, 5, ...]`.
+pub(crate) const fn odd<const N: usize>() -> [u32; N] {
+    let mut out = [0u32; N];
+    let mut i = 0usize;
+    while i < N {
+        out[i] = (2 * i + 1) as u32;
+        i += 1;
+    }
+    out
+}
+
+/// Multiples of N offset by K `[K, K+N, K+2N, ...]`.
 pub(crate) const fn deinterleave_mask<const LANES: usize, const N: usize, const K: usize>()
 -> [u32; LANES] {
-    // Produces: [K, K+N, K+2N, ...]
     let mut out = [0u32; LANES];
     let mut i = 0usize;
     while i < LANES {
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index b81f04ebc0..7ab68ff5f2 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -6961,28 +6961,29 @@ intrinsics:
           - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]
       - FnCall: ["vmovl{neon_type[0].noq}", [a]]
 
-  - name: "vpadd{neon_type.no}"
-    doc: Floating-point add pairwise
-    arguments: ["a: {neon_type}", "b: {neon_type}"]
-    return_type: "{type}"
+  - name: "vpadd{neon_type[0].no}"
+    doc: "Floating-point add pairwise"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[0]}"
     attr: [*neon-stable]
     assert_instr: [faddp]
     safety: safe
     types:
-      - float32x4_t
-      - float64x2_t
+      - [float32x4_t, "4"]
+      - [float64x2_t, "2"]
     compose:
-      - LLVMLink:
-          name: "faddp.{neon_type}"
-          links:
-            - link: "llvm.aarch64.neon.faddp.{neon_type}"
-              arch: aarch64,arm64ec
-
+      - Let:
+        - even
+        - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]]
+      - Let:
+        - odd
+        - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]]
+      - FnCall: [simd_add, [even, odd]]
 
-  - name: "vpadd{neon_type.no}"
+  - name: "vpadd{neon_type[0].no}"
     doc: Floating-point add pairwise
-    arguments: ["a: {neon_type}", "b: {neon_type}"]
-    return_type: "{type}"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[0]}"
     attr:
       - *neon-fp16
       - *neon-stable-fp16
@@ -6990,14 +6991,15 @@ intrinsics:
     assert_instr: [faddp]
     safety: safe
     types:
-      - float16x8_t
+      - [float16x8_t, "8"]
     compose:
-      - LLVMLink:
-          name: "faddp.{neon_type}"
-          links:
-            - link: "llvm.aarch64.neon.faddp.{neon_type}"
-              arch: aarch64,arm64ec
-
+      - Let:
+        - even
+        - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]]
+      - Let:
+        - odd
+        - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]]
+      - FnCall: [simd_add, [even, odd]]
 
   - name: "vpmax{neon_type.no}"
     doc: Floating-point add pairwise
@@ -13235,26 +13237,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.usqadd.{neon_type[1]}"
               arch: aarch64,arm64ec
 
-  - name: "vpadd{neon_type.no}"
-    doc: "Add Pairwise"
-    arguments: ["a: {neon_type}", "b: {neon_type}"]
-    return_type: "{neon_type}"
-    attr:
-      - *neon-stable
-    assert_instr: [addp]
-    safety: safe
-    types:
-      - int8x16_t
-      - int16x8_t
-      - int32x4_t
-      - int64x2_t
-    compose:
-      - LLVMLink:
-          name: "vpadd{neon_type.no}"
-          links:
-            - link: "llvm.aarch64.neon.addp.{neon_type}"
-              arch: aarch64,arm64ec
-
   - name: "vpadd{neon_type[0].no}"
     doc: "Add Pairwise"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
@@ -13264,17 +13246,22 @@ intrinsics:
     assert_instr: [addp]
     safety: safe
     types:
-      - [uint8x16_t, int8x16_t]
-      - [uint16x8_t, int16x8_t]
-      - [uint32x4_t, int32x4_t]
-      - [uint64x2_t, int64x2_t]
+      - [int8x16_t, "16"]
+      - [int16x8_t, "8"]
+      - [int32x4_t, "4"]
+      - [int64x2_t, "2"]
+      - [uint8x16_t, "16"]
+      - [uint16x8_t, "8"]
+      - [uint32x4_t, "4"]
+      - [uint64x2_t, "2"]
     compose:
-      - FnCall:
-          - transmute
-          - - FnCall:
-                - 'vpadd{neon_type[1].no}'
-                - - FnCall: [transmute, [a]]
-                  - FnCall: [transmute, [b]]
+      - Let:
+        - even
+        - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]]
+      - Let:
+        - odd
+        - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]]
+      - FnCall: [simd_add, [even, odd]]
 
   - name: "vpaddd_s64"
     doc: "Add pairwise"

From dc6bbbf8f458cbfe8a502179926fca275b6fd939 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 18 Feb 2026 21:28:03 +0100
Subject: [PATCH 162/326] cleanup long shuffle mask literals

---
 .../src/arm_shared/neon/generated.rs          | 240 +++---------------
 .../spec/neon/arm_shared.spec.yml             |  72 +++---
 2 files changed, 72 insertions(+), 240 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 45c83b880e..13dee7a6e6 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -10149,7 +10149,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
@@ -10174,13 +10174,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
@@ -10341,7 +10335,7 @@ pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
 )]
 pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
@@ -10364,7 +10358,7 @@ pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
 )]
 pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
@@ -10387,7 +10381,7 @@ pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 )]
 pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
@@ -10410,13 +10404,7 @@ pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 )]
 pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
@@ -10439,13 +10427,7 @@ pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
 )]
 pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
@@ -10468,13 +10450,7 @@ pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
 )]
 pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
@@ -10497,13 +10473,7 @@ pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
 )]
 pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
@@ -10526,13 +10496,7 @@ pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
 )]
 pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
@@ -10555,13 +10519,7 @@ pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 )]
 pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
@@ -10584,16 +10542,7 @@ pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 )]
 pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
-            ]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 16]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
@@ -10616,16 +10565,7 @@ pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
 )]
 pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
-            ]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 16]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
@@ -10648,16 +10588,7 @@ pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
 )]
 pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
-            ]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 16]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
@@ -10728,7 +10659,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
@@ -10753,13 +10684,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
@@ -10920,7 +10845,7 @@ pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
@@ -10943,7 +10868,7 @@ pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
 )]
 pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
@@ -10966,7 +10891,7 @@ pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
 )]
 pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
+    unsafe { simd_shuffle!(a, a, [N as u32; 4]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
@@ -10989,13 +10914,7 @@ pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
 )]
 pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
@@ -11018,13 +10937,7 @@ pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
 )]
 pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
@@ -11047,13 +10960,7 @@ pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 )]
 pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
@@ -11076,13 +10983,7 @@ pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 )]
 pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
@@ -11105,13 +11006,7 @@ pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
 )]
 pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
@@ -11134,13 +11029,7 @@ pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
 )]
 pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 8]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
@@ -11163,16 +11052,7 @@ pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
 )]
 pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
-            ]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 16]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
@@ -11195,16 +11075,7 @@ pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
 )]
 pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
-            ]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 16]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
@@ -11227,16 +11098,7 @@ pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 )]
 pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
     static_assert_uimm_bits!(N, 4);
-    unsafe {
-        simd_shuffle!(
-            a,
-            a,
-            [
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
-                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
-            ]
-        )
-    }
+    unsafe { simd_shuffle!(a, a, [N as u32; 16]) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
@@ -35894,7 +35756,7 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(N, 2);
     unsafe {
-        let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
+        let b: int16x4_t = simd_shuffle!(b, b, [N as u32; 4]);
         vqdmull_s16(a, b)
     }
 }
@@ -35920,7 +35782,7 @@ pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(N, 1);
     unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
+        let b: int32x2_t = simd_shuffle!(b, b, [N as u32; 2]);
         vqdmull_s32(a, b)
     }
 }
@@ -37480,17 +37342,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
         fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
     }
-    unsafe {
-        _vqrshrn_n_u16(
-            a,
-            const {
-                uint16x8_t([
-                    -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
-                    -N as u16,
-                ])
-            },
-        )
-    }
+    unsafe { _vqrshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) }
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
@@ -37506,12 +37358,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
         fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
     }
-    unsafe {
-        _vqrshrn_n_u32(
-            a,
-            const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
-        )
-    }
+    unsafe { _vqrshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) }
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
@@ -37527,7 +37374,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
         fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
     }
-    unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
+    unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) }
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
@@ -38922,17 +38769,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")]
         fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
     }
-    unsafe {
-        _vqshrn_n_u16(
-            a,
-            const {
-                uint16x8_t([
-                    -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
-                    -N as u16,
-                ])
-            },
-        )
-    }
+    unsafe { _vqshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) }
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
@@ -38948,12 +38785,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")]
         fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
     }
-    unsafe {
-        _vqshrn_n_u32(
-            a,
-            const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
-        )
-    }
+    unsafe { _vqshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) }
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
@@ -38969,7 +38801,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
         fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
     }
-    unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
+    unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) }
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 8e10fff984..90cd0c80a1 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -1439,12 +1439,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
+      - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32; 8]']
+      - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32; 16]']
+      - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32; 8]']
+      - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32; 16]']
+      - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32; 8]']
+      - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32; 16]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]
@@ -1463,12 +1463,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
+      - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32; 16]']
+      - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32; 8]']
+      - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32; 16]']
+      - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32; 8]']
+      - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32; 16]']
+      - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32; 8]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]
@@ -1487,12 +1487,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
+      - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32; 4]']
+      - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32; 8]']
+      - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32; 4]']
+      - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32; 8]']
+      - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32; 4]']
+      - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32; 8]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]
@@ -1511,12 +1511,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]']
-      - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]']
-      - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]']
+      - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32; 8]']
+      - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32; 4]']
+      - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32; 8]']
+      - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32; 4]']
+      - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32; 8]']
+      - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]
@@ -1538,8 +1538,8 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
-      - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]']
+      - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32; 8]']
+      - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]
@@ -1578,8 +1578,8 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]']
-      - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]']
+      - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32; 4]']
+      - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32; 8]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]
@@ -7675,7 +7675,7 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x4_t, int16x4_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]']
+      - [int16x4_t, int16x4_t, int32x4_t, '[N as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '2']]
       - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
@@ -7695,7 +7695,7 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int32x2_t, int32x2_t, int64x2_t, '[N as u32, N as u32]']
+      - [int32x2_t, int32x2_t, int64x2_t, '[N as u32; 2]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '1']]
       - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
@@ -8320,9 +8320,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }']
-      - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }']
-      - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }']
+      - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16; 8]) }']
+      - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32; 4]) }']
+      - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64; 2]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
@@ -10789,9 +10789,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }']
-      - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }']
-      - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }']
+      - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16; 8]) }']
+      - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32; 4]) }']
+      - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64; 2]) }']
     compose:
       - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']]
       - LLVMLink:

From 567e428c40f1dec9340afafdae19ae04679002c6 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 18 Feb 2026 21:23:00 +0100
Subject: [PATCH 163/326] use `intrinsics::simd` for interleaving store

---
 .../src/arm_shared/neon/generated.rs          | 192 +++---------------
 crates/core_arch/src/macros.rs                |  67 ++++++
 .../spec/neon/arm_shared.spec.yml             |  86 +++-----
 3 files changed, 118 insertions(+), 227 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 45c83b880e..37c7ef8fea 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -66001,14 +66001,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v2f32.p0"
-        )]
-        fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8);
-    }
-    _vst2_f32(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(f32, 2, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
@@ -66020,14 +66013,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v4f32.p0"
-        )]
-        fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8);
-    }
-    _vst2q_f32(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(f32, 4, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
@@ -66039,14 +66025,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v8i8.p0"
-        )]
-        fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
-    }
-    _vst2_s8(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i8, 8, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
@@ -66058,14 +66037,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v16i8.p0"
-        )]
-        fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
-    }
-    _vst2q_s8(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i8, 16, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
@@ -66077,14 +66049,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v4i16.p0"
-        )]
-        fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8);
-    }
-    _vst2_s16(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i16, 4, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
@@ -66096,14 +66061,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v8i16.p0"
-        )]
-        fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8);
-    }
-    _vst2q_s16(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i16, 8, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
@@ -66115,14 +66073,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v2i32.p0"
-        )]
-        fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8);
-    }
-    _vst2_s32(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i32, 2, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
@@ -66134,14 +66085,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v4i32.p0"
-        )]
-        fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8);
-    }
-    _vst2q_s32(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i32, 4, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
@@ -67233,11 +67177,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2f32")]
-        fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32);
-    }
-    _vst3_f32(a as _, b.0, b.1, b.2, 4)
+    crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
@@ -67249,11 +67189,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f32")]
-        fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32);
-    }
-    _vst3q_f32(a as _, b.0, b.1, b.2, 4)
+    crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
@@ -67265,11 +67201,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i8")]
-        fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32);
-    }
-    _vst3_s8(a as _, b.0, b.1, b.2, 1)
+    crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
@@ -67281,11 +67213,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v16i8")]
-        fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32);
-    }
-    _vst3q_s8(a as _, b.0, b.1, b.2, 1)
+    crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
@@ -67297,11 +67225,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i16")]
-        fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32);
-    }
-    _vst3_s16(a as _, b.0, b.1, b.2, 2)
+    crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
@@ -67313,11 +67237,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i16")]
-        fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32);
-    }
-    _vst3q_s16(a as _, b.0, b.1, b.2, 2)
+    crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
@@ -67329,11 +67249,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2i32")]
-        fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32);
-    }
-    _vst3_s32(a as _, b.0, b.1, b.2, 4)
+    crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
@@ -67345,11 +67261,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vst3))]
 pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i32")]
-        fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32);
-    }
-    _vst3q_s32(a as _, b.0, b.1, b.2, 4)
+    crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
@@ -68712,14 +68624,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v2f32.p0"
-        )]
-        fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8);
-    }
-    _vst4_f32(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(f32, 2, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
@@ -68731,14 +68636,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v4f32.p0"
-        )]
-        fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8);
-    }
-    _vst4q_f32(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(f32, 4, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
@@ -68750,14 +68648,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v8i8.p0"
-        )]
-        fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
-    }
-    _vst4_s8(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i8, 8, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
@@ -68769,14 +68660,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v16i8.p0"
-        )]
-        fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
-    }
-    _vst4q_s8(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i8, 16, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
@@ -68788,14 +68672,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v4i16.p0"
-        )]
-        fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8);
-    }
-    _vst4_s16(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i16, 4, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
@@ -68807,14 +68684,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v8i16.p0"
-        )]
-        fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8);
-    }
-    _vst4q_s16(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i16, 8, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
@@ -68826,14 +68696,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v2i32.p0"
-        )]
-        fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8);
-    }
-    _vst4_s32(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i32, 2, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
@@ -68845,14 +68708,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v4i32.p0"
-        )]
-        fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8);
-    }
-    _vst4q_s32(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i32, 4, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 9f6922efee..5a582fe177 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -187,6 +187,17 @@ macro_rules! simd_masked_store {
     };
 }
 
+/// The first N indices `[0, 1, 2, ...]`.
+pub(crate) const fn identity<const N: usize>() -> [u32; N] {
+    let mut out = [0u32; N];
+    let mut i = 0usize;
+    while i < N {
+        out[i] = i as u32;
+        i += 1;
+    }
+    out
+}
+
 /// The first N even indices `[0, 2, 4, ...]`.
 pub(crate) const fn even<const N: usize>() -> [u32; N] {
     let mut out = [0u32; N];
@@ -277,3 +288,59 @@ macro_rules! deinterleaving_load {
 
 #[allow(unused)]
 pub(crate) use deinterleaving_load;
+
+pub(crate) const fn interleave_mask<const LANES: usize, const N: usize, const K: usize>()
+-> [u32; LANES] {
+    let mut out = [0u32; LANES];
+    let mut j = 0usize;
+    while j < LANES {
+        out[j] = ((j % K) * N + j / K) as u32;
+        j += 1;
+    }
+    out
+}
+
+#[allow(unused)]
+macro_rules! interleaving_store {
+    ($elem:ty, $lanes:literal, 2, $ptr:expr, $v:expr) => {{
+        use $crate::core_arch::macros::interleave_mask;
+        use $crate::core_arch::simd::Simd;
+
+        type W = Simd<$elem, { $lanes * 2 }>;
+        let w: W = simd_shuffle!($v.0, $v.1, interleave_mask::<{ $lanes * 2 }, $lanes, 2>());
+        $crate::ptr::write_unaligned($ptr as *mut W, w);
+    }};
+
+    // N = 3
+    ($elem:ty, $lanes:literal, 3, $ptr:expr, $v:expr) => {{
+        use $crate::core_arch::macros::{identity, interleave_mask};
+        use $crate::core_arch::simd::Simd;
+
+        let v0v1: Simd<$elem, { $lanes * 2 }> =
+            simd_shuffle!($v.0, $v.1, identity::<{ $lanes * 2 }>());
+        let v2v2: Simd<$elem, { $lanes * 2 }> =
+            simd_shuffle!($v.2, $v.2, identity::<{ $lanes * 2 }>());
+
+        type W = Simd<$elem, { $lanes * 3 }>;
+        let w: W = simd_shuffle!(v0v1, v2v2, interleave_mask::<{ $lanes * 3 }, $lanes, 3>());
+        $crate::ptr::write_unaligned($ptr as *mut W, w);
+    }};
+
+    // N = 4
+    ($elem:ty, $lanes:literal, 4, $ptr:expr, $v:expr) => {{
+        use $crate::core_arch::macros::{identity, interleave_mask};
+        use $crate::core_arch::simd::Simd;
+
+        let v0v1: Simd<$elem, { $lanes * 2 }> =
+            simd_shuffle!($v.0, $v.1, identity::<{ $lanes * 2 }>());
+        let v2v3: Simd<$elem, { $lanes * 2 }> =
+            simd_shuffle!($v.2, $v.3, identity::<{ $lanes * 2 }>());
+
+        type W = Simd<$elem, { $lanes * 4 }>;
+        let w: W = simd_shuffle!(v0v1, v2v3, interleave_mask::<{ $lanes * 4 }, $lanes, 4>());
+        $crate::ptr::write_unaligned($ptr as *mut W, w);
+    }};
+}
+
+#[allow(unused)]
+pub(crate) use interleaving_store;
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 8e10fff984..f890b39f07 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -5113,26 +5113,16 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [i8, int8x8x2_t, int8x8_t]
-      - [i16, int16x4x2_t, int16x4_t]
-      - [i32, int32x2x2_t, int32x2_t]
-      - [i8, int8x16x2_t, int8x16_t]
-      - [i16, int16x8x2_t, int16x8_t]
-      - [i32, int32x4x2_t, int32x4_t]
-      - [f32, float32x2x2_t, float32x2_t]
-      - [f32, float32x4x2_t, float32x4_t]
+      - [i8, int8x8x2_t, "8"]
+      - [i16, int16x4x2_t, "4"]
+      - [i32, int32x2x2_t, "2"]
+      - [i8, int8x16x2_t, "16"]
+      - [i16, int16x8x2_t, "8"]
+      - [i32, int32x4x2_t, "4"]
+      - [f32, float32x2x2_t, "2"]
+      - [f32, float32x4x2_t, "4"]
     compose:
-      - LLVMLink:
-          name: 'st2.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']]
-
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "2", a, b], [], true]
 
   - name: "vst2{neon_type[1].nox}"
     doc: "Store multiple 2-element structures from two registers"
@@ -5571,27 +5561,16 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [i8, int8x8x3_t, int8x8_t, '1']
-      - [i16, int16x4x3_t, int16x4_t, '2']
-      - [i32, int32x2x3_t, int32x2_t, '4']
-      - [i8, int8x16x3_t, int8x16_t, '1']
-      - [i16, int16x8x3_t, int16x8_t, '2']
-      - [i32, int32x4x3_t, int32x4_t, '4']
-      - [f32, float32x2x3_t, float32x2_t, '4']
-      - [f32, float32x4x3_t, float32x4_t, '4']
+      - [i8, int8x8x3_t, '8']
+      - [i16, int16x4x3_t, '4']
+      - [i32, int32x2x3_t, '2']
+      - [i8, int8x16x3_t, '16']
+      - [i16, int16x8x3_t, '8']
+      - [i32, int32x4x3_t, '4']
+      - [f32, float32x2x3_t, '2']
+      - [f32, float32x4x3_t, '4']
     compose:
-      - LLVMLink:
-          name: 'vst3.{neon_type[1]}'
-          arguments:
-            - 'ptr: *mut i8'
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'size: i32'
-          links:
-            - link: 'llvm.arm.neon.vst3.p0.v{neon_type[1].lane}{type[0]}'
-              arch: arm
-      - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', "{type[3]}"]]
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true]
 
 
   - name: "vst3{neon_type[1].nox}"
@@ -6114,27 +6093,16 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [i8, int8x8x4_t, int8x8_t]
-      - [i16, int16x4x4_t, int16x4_t]
-      - [i32, int32x2x4_t, int32x2_t]
-      - [i8, int8x16x4_t, int8x16_t]
-      - [i16, int16x8x4_t, int16x8_t]
-      - [i32, int32x4x4_t, int32x4_t]
-      - [f32, float32x2x4_t, float32x2_t]
-      - [f32, float32x4x4_t, float32x4_t]
+      - [i8, int8x8x4_t, "8"]
+      - [i16, int16x4x4_t, "4"]
+      - [i32, int32x2x4_t, "2"]
+      - [i8, int8x16x4_t, "16"]
+      - [i16, int16x8x4_t, "8"]
+      - [i32, int32x4x4_t, "4"]
+      - [f32, float32x2x4_t, "2"]
+      - [f32, float32x4x4_t, "4"]
     compose:
-      - LLVMLink:
-          name: 'vst4.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'd: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']]
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "4", a, b], [], true]
 
 
   - name: "vst4{neon_type[1].nox}"

From 04451c84d4e389ec46ef089df454f5be40b2ec21 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 18 Feb 2026 21:40:50 +0100
Subject: [PATCH 164/326] use `intrinsics::simd` for interleaving store of
 `int64x1`

---
 .../src/arm_shared/neon/generated.rs          | 52 ++-----------
 .../spec/neon/arm_shared.spec.yml             | 75 ++-----------------
 2 files changed, 12 insertions(+), 115 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 37c7ef8fea..62201edfda 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -66809,11 +66809,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")]
-        fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32);
-    }
-    _vst2_s64(a as _, b.0, b.1, 8)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
@@ -66825,14 +66821,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v1i64.p0"
-        )]
-        fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8);
-    }
-    _vst2_s64(b.0, b.1, a as _)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
@@ -68065,14 +68054,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v1i64.p0"
-        )]
-        fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8);
-    }
-    _vst3_s64(b.0, b.1, b.2, a as _)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
@@ -68084,11 +68066,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v1i64")]
-        fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32);
-    }
-    _vst3_s64(a as _, b.0, b.1, b.2, 8)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
@@ -69432,18 +69410,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v1i64")]
-        fn _vst4_s64(
-            ptr: *mut i8,
-            a: int64x1_t,
-            b: int64x1_t,
-            c: int64x1_t,
-            d: int64x1_t,
-            size: i32,
-        );
-    }
-    _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
@@ -69455,14 +69422,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v1i64.p0"
-        )]
-        fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8);
-    }
-    _vst4_s64(b.0, b.1, b.2, b.3, a as _)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index f890b39f07..23145d6d66 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -5049,17 +5049,7 @@ intrinsics:
     types:
       - [i64, int64x1x2_t, int64x1_t]
     compose:
-      - LLVMLink:
-          name: 'vst2.{neon_type[1]}'
-          arguments:
-            - 'ptr: *mut i8'
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'size: i32'
-          links:
-            - link: 'llvm.arm.neon.vst2.v{neon_type[1].lane}{type[0]}.p0'
-              arch: arm
-      - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', '8']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst2{neon_type[1].nox}"
     doc: "Store multiple 2-element structures from two registers"
@@ -5092,16 +5082,7 @@ intrinsics:
     types:
       - [i64, int64x1x2_t, int64x1_t]
     compose:
-      - LLVMLink:
-          name: 'st2.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst2{neon_type[1].nox}"
     doc: "Store multiple 2-element structures from two registers"
@@ -5416,17 +5397,7 @@ intrinsics:
     types:
       - [i64, int64x1x3_t, int64x1_t]
     compose:
-      - LLVMLink:
-          name: 'st3.{neon_type[1].nox}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst3{neon_type[1].nox}"
     doc: "Store multiple 3-element structures from three registers"
@@ -5461,18 +5432,7 @@ intrinsics:
     types:
       - [i64, int64x1x3_t, int64x1_t]
     compose:
-      - LLVMLink:
-          name: 'vst3.{neon_type[1]}'
-          arguments:
-            - 'ptr: *mut i8'
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'size: i32'
-          links:
-            - link: 'llvm.arm.neon.vst3.p0.v{neon_type[1].lane}{type[0]}'
-              arch: arm
-      - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', '8']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst3{neon_type[1].nox}"
     doc: "Store multiple 3-element structures from three registers"
@@ -5832,19 +5792,7 @@ intrinsics:
     types:
       - [i64, int64x1x4_t, int64x1_t]
     compose:
-      - LLVMLink:
-          name: 'vst4.{neon_type[1]}'
-          arguments:
-            - 'ptr: *mut i8'
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'd: {type[2]}'
-            - 'size: i32'
-          links:
-            - link: 'llvm.arm.neon.vst4.p0.v{neon_type[1].lane}{type[0]}'
-              arch: arm
-      - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', '8']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst4{neon_type[1].nox}"
     doc: "Store multiple 4-element structures from four registers"
@@ -5858,18 +5806,7 @@ intrinsics:
     types:
       - [i64, int64x1x4_t, int64x1_t]
     compose:
-      - LLVMLink:
-          name: 'vst4.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'd: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st4.{neon_type[2]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst4{neon_type[1].nox}"
     doc: "Store multiple 4-element structures from four registers"

From 0c452e4cafc1976e5589a2bcab2d90adf34cc5df Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 18 Feb 2026 21:51:54 +0100
Subject: [PATCH 165/326] use `intrinsics::simd` for interleaving store of f16

---
 crates/core_arch/src/aarch64/neon/mod.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 2df4ba7443..2fbd2255aa 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -1050,6 +1050,14 @@ mod tests {
         test_vld1q_f16_x2(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2);
         test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3);
         test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4);
+
+        test_vld2_f16_x2(f16, 8, float16x4x2_t, vst2_f16, vld2_f16);
+        test_vld2_f16_x3(f16, 12, float16x4x3_t, vst3_f16, vld3_f16);
+        test_vld2_f16_x4(f16, 16, float16x4x4_t, vst4_f16, vld4_f16);
+
+        test_vld2q_f16_x2(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16);
+        test_vld3q_f16_x3(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16);
+        test_vld4q_f16_x4(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16);
     }
 
     macro_rules! wide_store_load_roundtrip_aes {

From 281d367843ca150720fa1ca03a13372081150679 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 18 Feb 2026 22:27:23 +0100
Subject: [PATCH 166/326] use `intrinsics::simd` for aarch64 interleaving `st`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 83 ++---------------
 .../spec/neon/aarch64.spec.yml                | 92 ++++---------------
 2 files changed, 26 insertions(+), 149 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 88afaae8b8..41f01d445f 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -25039,16 +25039,9 @@ pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(st1))]
+#[cfg_attr(test, assert_instr(stp))]
 pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v1f64.p0"
-        )]
-        fn _vst2_f64(a: float64x1_t, b: float64x1_t, ptr: *mut i8);
-    }
-    _vst2_f64(b.0, b.1, a as _)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
@@ -25125,14 +25118,7 @@ pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v2f64.p0"
-        )]
-        fn _vst2q_f64(a: float64x2_t, b: float64x2_t, ptr: *mut i8);
-    }
-    _vst2q_f64(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(f64, 2, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
@@ -25143,14 +25129,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
 pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st2.v2i64.p0"
-        )]
-        fn _vst2q_s64(a: int64x2_t, b: int64x2_t, ptr: *mut i8);
-    }
-    _vst2q_s64(b.0, b.1, a as _)
+    crate::core_arch::macros::interleaving_store!(i64, 2, 2, a, b)
 }
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
@@ -25295,14 +25274,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v1f64.p0"
-        )]
-        fn _vst3_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut i8);
-    }
-    _vst3_f64(b.0, b.1, b.2, a as _)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
@@ -25379,14 +25351,7 @@ pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v2f64.p0"
-        )]
-        fn _vst3q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut i8);
-    }
-    _vst3q_f64(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(f64, 2, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
@@ -25397,14 +25362,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v2i64.p0"
-        )]
-        fn _vst3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i8);
-    }
-    _vst3q_s64(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i64, 2, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
@@ -25549,14 +25507,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v1f64.p0"
-        )]
-        fn _vst4_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, ptr: *mut i8);
-    }
-    _vst4_f64(b.0, b.1, b.2, b.3, a as _)
+    core::ptr::write_unaligned(a.cast(), b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
@@ -25647,14 +25598,7 @@ pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v2f64.p0"
-        )]
-        fn _vst4q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, ptr: *mut i8);
-    }
-    _vst4q_f64(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(f64, 2, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
@@ -25665,14 +25609,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
 pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st4.v2i64.p0"
-        )]
-        fn _vst4q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i8);
-    }
-    _vst4q_s64(b.0, b.1, b.2, b.3, a as _)
+    crate::core_arch::macros::interleaving_store!(i64, 2, 4, a, b)
 }
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 9190c8518a..0ec8024fdf 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -4567,20 +4567,11 @@ intrinsics:
       unsafe: [neon]
     attr:
       - *neon-stable
-    assert_instr: [st1]
+    assert_instr: [stp]
     types:
-      - ['f64', float64x1x2_t, float64x1_t]
+      - ['f64', float64x1x2_t]
     compose:
-      - LLVMLink:
-          name: 'st2.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst2{neon_type[1].nox}"
     doc: "Store multiple 2-element structures from two registers"
@@ -4591,19 +4582,10 @@ intrinsics:
       - *neon-stable
     assert_instr: [st2]
     types:
-      - [i64, int64x2x2_t, int64x2_t]
-      - [f64, float64x2x2_t, float64x2_t]
+      - [i64, int64x2x2_t, "2"]
+      - [f64, float64x2x2_t, "2"]
     compose:
-      - LLVMLink:
-          name: 'st2.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']]
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "2", a, b], [], true]
 
   - name: "vst2{neon_type[1].lane_nox}"
     doc: "Store multiple 2-element structures from two registers"
@@ -4781,19 +4763,9 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [f64, float64x1x3_t, float64x1_t]
+      - [f64, float64x1x3_t]
     compose:
-      - LLVMLink:
-          name: 'st3.{neon_type[1].nox}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst3{neon_type[1].lane_nox}"
     doc: "Store multiple 3-element structures from three registers"
@@ -4860,20 +4832,10 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [i64, int64x2x3_t, int64x2_t]
-      - [f64, float64x2x3_t, float64x2_t]
+      - [i64, int64x2x3_t, "2"]
+      - [f64, float64x2x3_t, "2"]
     compose:
-      - LLVMLink:
-          name: 'st3.{neon_type[1].nox}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']]
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true]
 
   - name: "vst3{neon_type[1].nox}"
     doc: "Store multiple 3-element structures from three registers"
@@ -4995,20 +4957,9 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [f64, float64x1x4_t, float64x1_t]
+      - [f64, float64x1x4_t]
     compose:
-      - LLVMLink:
-          name: 'st4.{neon_type[1].nox}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'd: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']]
+      - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]]
 
   - name: "vst4{neon_type[1].lane_nox}"
     doc: "Store multiple 4-element structures from four registers"
@@ -5075,21 +5026,10 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [i64, int64x2x4_t, int64x2_t]
-      - [f64, float64x2x4_t, float64x2_t]
+      - [i64, int64x2x4_t, "2"]
+      - [f64, float64x2x4_t, "2"]
     compose:
-      - LLVMLink:
-          name: 'st4.{neon_type[1].nox}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'd: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']]
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "4", a, b], [], true]
 
   - name: "vst4{neon_type[1].nox}"
     doc: "Store multiple 4-element structures from four registers"

From b9b67268a3c444e977dca08cb7a6a32471ee0680 Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Thu, 19 Feb 2026 06:50:17 -0500
Subject: [PATCH 167/326] x86: use `simd::intrinsics` for saturating packs

Use intrinsics for `sse2`, `sse41`, `avx2`, `avx512bw`

The majority of implementations make use of `simd_shuffle` since that
optimized through to the avx512 intrinsics that made use of the lower
target feature intrinsics. Combined with masked stores, instruction
tests would fail presumably due to the casting and clamping that
the compiler couldn't see through. This is a known weakness as seen
in the other masked stores like the truncating conversion stores.
---
 crates/core_arch/src/x86/sse2.rs | 67 ++++++++++++++++++++++++++------
 1 file changed, 55 insertions(+), 12 deletions(-)

diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index f339a003df..fbf62c362f 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -1484,7 +1484,7 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i {
     }
 }
 
-/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers
 /// using signed saturation.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi16)
@@ -1493,10 +1493,27 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(packsswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(packsswb(a.as_i16x8(), b.as_i16x8())) }
+    unsafe {
+        let max = simd_splat(i16::from(i8::MAX));
+        let min = simd_splat(i16::from(i8::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min)
+            .as_m128i()
+            .as_i8x16();
+        let clamped_b = simd_imax(simd_imin(b.as_i16x8(), max), min)
+            .as_m128i()
+            .as_i8x16();
+
+        // Shuffle the low i8 of each i16 from two concatenated vectors into
+        // the low bits of the result register.
+        const IDXS: [u32; 16] = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30];
+        let result: i8x16 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m128i()
+    }
 }
 
-/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers
 /// using signed saturation.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32)
@@ -1505,10 +1522,23 @@ pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(packssdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(packssdw(a.as_i32x4(), b.as_i32x4())) }
+    unsafe {
+        let max = simd_splat(i32::from(i16::MAX));
+        let min = simd_splat(i32::from(i16::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min);
+        let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min);
+
+        let clamped_a: i16x4 = simd_cast(clamped_a);
+        let clamped_b: i16x4 = simd_cast(clamped_b);
+
+        let a: i64 = transmute(clamped_a);
+        let b: i64 = transmute(clamped_b);
+        i64x2::new(a, b).as_m128i()
+    }
 }
 
-/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers
 /// using unsigned saturation.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16)
@@ -1517,7 +1547,26 @@ pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(packuswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(packuswb(a.as_i16x8(), b.as_i16x8())) }
+    unsafe {
+        let max = simd_splat(i16::from(u8::MAX));
+        let min = simd_splat(i16::from(u8::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min)
+            .as_m128i()
+            .as_i8x16();
+        let clamped_b = simd_imax(simd_imin(b.as_i16x8(), max), min)
+            .as_m128i()
+            .as_i8x16();
+
+        // Shuffle the low bytes of each i16 from two concatenated vectors into
+        // the low bits of the result register.
+        // Without `simd_shuffle`, this intrinsic will cause the AVX-512BW
+        // `_mm_mask_packus_epi16` and `_mm_maskz_packus_epi16` tests to fail.
+        const IDXS: [u32; 16] = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30];
+        let result: i8x16 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m128i()
+    }
 }
 
 /// Returns the `imm8` element of `a`.
@@ -3217,12 +3266,6 @@ unsafe extern "C" {
     fn cvtps2dq(a: __m128) -> i32x4;
     #[link_name = "llvm.x86.sse2.maskmov.dqu"]
     fn maskmovdqu(a: i8x16, mask: i8x16, mem_addr: *mut i8);
-    #[link_name = "llvm.x86.sse2.packsswb.128"]
-    fn packsswb(a: i16x8, b: i16x8) -> i8x16;
-    #[link_name = "llvm.x86.sse2.packssdw.128"]
-    fn packssdw(a: i32x4, b: i32x4) -> i16x8;
-    #[link_name = "llvm.x86.sse2.packuswb.128"]
-    fn packuswb(a: i16x8, b: i16x8) -> u8x16;
     #[link_name = "llvm.x86.sse2.max.sd"]
     fn maxsd(a: __m128d, b: __m128d) -> __m128d;
     #[link_name = "llvm.x86.sse2.max.pd"]

From 31ce954e7852322e6663523d9ea11cbfedce803d Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Thu, 19 Feb 2026 07:05:07 -0500
Subject: [PATCH 168/326] Use intrinsics for `sse41`

---
 crates/core_arch/src/x86/sse41.rs | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
index 7ad4306f36..8036f24e24 100644
--- a/crates/core_arch/src/x86/sse41.rs
+++ b/crates/core_arch/src/x86/sse41.rs
@@ -418,7 +418,7 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { simd_imin(a.as_u32x4(), b.as_u32x4()).as_m128i() }
 }
 
-/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers
 /// using unsigned saturation
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi32)
@@ -427,7 +427,24 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(packusdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(packusdw(a.as_i32x4(), b.as_i32x4())) }
+    unsafe {
+        let max = simd_splat(i32::from(u16::MAX));
+        let min = simd_splat(i32::from(u16::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min)
+            .as_m128i()
+            .as_i16x8();
+        let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min)
+            .as_m128i()
+            .as_i16x8();
+
+        // Shuffle the low u16 of each i32 from two concatenated vectors into
+        // the low bits of the result register.
+        const IDXS: [u32; 8] = [0, 2, 4, 6, 8, 10, 12, 14];
+        let result: i16x8 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m128i()
+    }
 }
 
 /// Compares packed 64-bit integers in `a` and `b` for equality
@@ -1166,8 +1183,6 @@ pub unsafe fn _mm_stream_load_si128(mem_addr: *const __m128i) -> __m128i {
 unsafe extern "C" {
     #[link_name = "llvm.x86.sse41.insertps"]
     fn insertps(a: __m128, b: __m128, imm8: u8) -> __m128;
-    #[link_name = "llvm.x86.sse41.packusdw"]
-    fn packusdw(a: i32x4, b: i32x4) -> u16x8;
     #[link_name = "llvm.x86.sse41.dppd"]
     fn dppd(a: __m128d, b: __m128d, imm8: u8) -> __m128d;
     #[link_name = "llvm.x86.sse41.dpps"]

From 348737da241a2364f01ef66e60329e5038de480c Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Thu, 19 Feb 2026 08:06:24 -0500
Subject: [PATCH 169/326] Use intrinsics for `avx2`

---
 crates/core_arch/src/x86/avx2.rs | 108 ++++++++++++++++++++++++++-----
 1 file changed, 92 insertions(+), 16 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index 04a88e461f..ca4ca9a2de 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -2315,7 +2315,7 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(simd_or(a.as_i32x8(), b.as_i32x8())) }
 }
 
-/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers
 /// using signed saturation
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi16)
@@ -2324,10 +2324,31 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpacksswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(packsswb(a.as_i16x16(), b.as_i16x16())) }
+    unsafe {
+        let max = simd_splat(i16::from(i8::MAX));
+        let min = simd_splat(i16::from(i8::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min)
+            .as_m256i()
+            .as_i8x32();
+        let clamped_b = simd_imax(simd_imin(b.as_i16x16(), max), min)
+            .as_m256i()
+            .as_i8x32();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 32] = [
+            00, 02, 04, 06, 08, 10, 12, 14, // a-lo i16 to i8 conversions
+            32, 34, 36, 38, 40, 42, 44, 46, // b-lo
+            16, 18, 20, 22, 24, 26, 28, 30, // a-hi
+            48, 50, 52, 54, 56, 58, 60, 62, // b-hi
+        ];
+        let result: i8x32 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m256i()
+    }
 }
 
-/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers
 /// using signed saturation
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32)
@@ -2336,10 +2357,31 @@ pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpackssdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(packssdw(a.as_i32x8(), b.as_i32x8())) }
+    unsafe {
+        let max = simd_splat(i32::from(i16::MAX));
+        let min = simd_splat(i32::from(i16::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min)
+            .as_m256i()
+            .as_i16x16();
+        let clamped_b = simd_imax(simd_imin(b.as_i32x8(), max), min)
+            .as_m256i()
+            .as_i16x16();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 16] = [
+            00, 02, 04, 06, // a-lo i32 to i16 conversions
+            16, 18, 20, 22, // b-lo
+            08, 10, 12, 14, // a-hi
+            24, 26, 28, 30, // b-hi
+        ];
+        let result: i16x16 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m256i()
+    }
 }
 
-/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers
 /// using unsigned saturation
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi16)
@@ -2348,10 +2390,31 @@ pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpackuswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(packuswb(a.as_i16x16(), b.as_i16x16())) }
+    unsafe {
+        let max = simd_splat(i16::from(u8::MAX));
+        let min = simd_splat(i16::from(u8::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min)
+            .as_m256i()
+            .as_i8x32();
+        let clamped_b = simd_imax(simd_imin(b.as_i16x16(), max), min)
+            .as_m256i()
+            .as_i8x32();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 32] = [
+            00, 02, 04, 06, 08, 10, 12, 14, // a-lo i16 to u8 conversions
+            32, 34, 36, 38, 40, 42, 44, 46, // b-lo
+            16, 18, 20, 22, 24, 26, 28, 30, // a-hi
+            48, 50, 52, 54, 56, 58, 60, 62, // b-hi
+        ];
+        let result: i8x32 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m256i()
+    }
 }
 
-/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers
 /// using unsigned saturation
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi32)
@@ -2360,7 +2423,28 @@ pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpackusdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(packusdw(a.as_i32x8(), b.as_i32x8())) }
+    unsafe {
+        let max = simd_splat(i32::from(u16::MAX));
+        let min = simd_splat(i32::from(u16::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min)
+            .as_m256i()
+            .as_i16x16();
+        let clamped_b = simd_imax(simd_imin(b.as_i32x8(), max), min)
+            .as_m256i()
+            .as_i16x16();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 16] = [
+            00, 02, 04, 06, // a-lo i32 to u16 conversions
+            16, 18, 20, 22, // b-lo
+            08, 10, 12, 14, // a-hi
+            24, 26, 28, 30, // b-hi
+        ];
+        let result: i16x16 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m256i()
+    }
 }
 
 /// Permutes packed 32-bit integers from `a` according to the content of `b`.
@@ -3827,14 +3911,6 @@ unsafe extern "C" {
     fn mpsadbw(a: u8x32, b: u8x32, imm8: i8) -> u16x16;
     #[link_name = "llvm.x86.avx2.pmul.hr.sw"]
     fn pmulhrsw(a: i16x16, b: i16x16) -> i16x16;
-    #[link_name = "llvm.x86.avx2.packsswb"]
-    fn packsswb(a: i16x16, b: i16x16) -> i8x32;
-    #[link_name = "llvm.x86.avx2.packssdw"]
-    fn packssdw(a: i32x8, b: i32x8) -> i16x16;
-    #[link_name = "llvm.x86.avx2.packuswb"]
-    fn packuswb(a: i16x16, b: i16x16) -> u8x32;
-    #[link_name = "llvm.x86.avx2.packusdw"]
-    fn packusdw(a: i32x8, b: i32x8) -> u16x16;
     #[link_name = "llvm.x86.avx2.psad.bw"]
     fn psadbw(a: u8x32, b: u8x32) -> u64x4;
     #[link_name = "llvm.x86.avx2.psign.b"]

From 56d4241471a12c5660076492ea1401d1fb92dfb1 Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Thu, 19 Feb 2026 08:42:08 -0500
Subject: [PATCH 170/326] Use intrinsics for `avx512bw`

---
 crates/core_arch/src/x86/avx512bw.rs | 117 ++++++++++++++++++++++++---
 1 file changed, 104 insertions(+), 13 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 3ba171c0fa..78801e8902 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6524,7 +6524,32 @@ pub fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
 pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpackssdw(a.as_i32x16(), b.as_i32x16())) }
+    unsafe {
+        let max = simd_splat(i32::from(i16::MAX));
+        let min = simd_splat(i32::from(i16::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min)
+            .as_m512i()
+            .as_i16x32();
+        let clamped_b = simd_imax(simd_imin(b.as_i32x16(), max), min)
+            .as_m512i()
+            .as_i16x32();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 32] = [
+            00, 02, 04, 06,
+            32, 34, 36, 38,
+            08, 10, 12, 14,
+            40, 42, 44, 46,
+            16, 18, 20, 22,
+            48, 50, 52, 54,
+            24, 26, 28, 30,
+            56, 58, 60, 62,
+        ];
+        let result: i16x32 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m512i()
+    }
 }
 
 /// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6619,7 +6644,32 @@ pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
 pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpacksswb(a.as_i16x32(), b.as_i16x32())) }
+    unsafe {
+        let max = simd_splat(i16::from(i8::MAX));
+        let min = simd_splat(i16::from(i8::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min)
+            .as_m512i()
+            .as_i8x64();
+        let clamped_b = simd_imax(simd_imin(b.as_i16x32(), max), min)
+            .as_m512i()
+            .as_i8x64();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 64] = [
+            000, 002, 004, 006, 008, 010, 012, 014,
+            064, 066, 068, 070, 072, 074, 076, 078,
+            016, 018, 020, 022, 024, 026, 028, 030,
+            080, 082, 084, 086, 088, 090, 092, 094,
+            032, 034, 036, 038, 040, 042, 044, 046,
+            096, 098, 100, 102, 104, 106, 108, 110,
+            048, 050, 052, 054, 056, 058, 060, 062,
+            112, 114, 116, 118, 120, 122, 124, 126,
+        ];
+        let result: i8x64 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m512i()
+    }
 }
 
 /// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6714,7 +6764,32 @@ pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
 pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpackusdw(a.as_i32x16(), b.as_i32x16())) }
+    unsafe {
+        let max = simd_splat(i32::from(u16::MAX));
+        let min = simd_splat(i32::from(u16::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min)
+            .as_m512i()
+            .as_i16x32();
+        let clamped_b = simd_imax(simd_imin(b.as_i32x16(), max), min)
+            .as_m512i()
+            .as_i16x32();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 32] = [
+            00, 02, 04, 06,
+            32, 34, 36, 38,
+            08, 10, 12, 14,
+            40, 42, 44, 46,
+            16, 18, 20, 22,
+            48, 50, 52, 54,
+            24, 26, 28, 30,
+            56, 58, 60, 62,
+        ];
+        let result: i16x32 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m512i()
+    }
 }
 
 /// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -6809,7 +6884,32 @@ pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
 pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpackuswb(a.as_i16x32(), b.as_i16x32())) }
+    unsafe {
+        let max = simd_splat(i16::from(u8::MAX));
+        let min = simd_splat(i16::from(u8::MIN));
+
+        let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min)
+            .as_m512i()
+            .as_i8x64();
+        let clamped_b = simd_imax(simd_imin(b.as_i16x32(), max), min)
+            .as_m512i()
+            .as_i8x64();
+
+        #[rustfmt::skip]
+        const IDXS: [u32; 64] = [
+            000, 002, 004, 006, 008, 010, 012, 014,
+            064, 066, 068, 070, 072, 074, 076, 078,
+            016, 018, 020, 022, 024, 026, 028, 030,
+            080, 082, 084, 086, 088, 090, 092, 094,
+            032, 034, 036, 038, 040, 042, 044, 046,
+            096, 098, 100, 102, 104, 106, 108, 110,
+            048, 050, 052, 054, 056, 058, 060, 062,
+            112, 114, 116, 118, 120, 122, 124, 126,
+        ];
+        let result: i8x64 = simd_shuffle!(clamped_a, clamped_b, IDXS);
+
+        result.as_m512i()
+    }
 }
 
 /// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -12606,15 +12706,6 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.pmaddubs.w.512"]
     fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32;
 
-    #[link_name = "llvm.x86.avx512.packssdw.512"]
-    fn vpackssdw(a: i32x16, b: i32x16) -> i16x32;
-    #[link_name = "llvm.x86.avx512.packsswb.512"]
-    fn vpacksswb(a: i16x32, b: i16x32) -> i8x64;
-    #[link_name = "llvm.x86.avx512.packusdw.512"]
-    fn vpackusdw(a: i32x16, b: i32x16) -> u16x32;
-    #[link_name = "llvm.x86.avx512.packuswb.512"]
-    fn vpackuswb(a: i16x32, b: i16x32) -> u8x64;
-
     #[link_name = "llvm.x86.avx512.psll.w.512"]
     fn vpsllw(a: i16x32, count: i16x8) -> i16x32;
 

From 6c53ca2c5666e5b641f3c90c2d9bbe4435cd38a3 Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Fri, 20 Feb 2026 06:53:07 -0500
Subject: [PATCH 171/326] x86: Followup to add const for pack intrinsics

Add const to `sse2`, `sse41`, `avx2`, and `avx512bw` functions and tests
---
 crates/core_arch/src/x86/avx512bw.rs | 30 +++++++++++++++++-----------
 crates/core_arch/src/x86/sse2.rs     | 27 ++++++++++++++-----------
 2 files changed, 33 insertions(+), 24 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 78801e8902..8481edcdb3 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6615,7 +6615,8 @@ pub fn _mm256_maskz_packs_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
-pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packs_epi32(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, pack, src.as_i16x8()))
@@ -6629,7 +6630,8 @@ pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
-pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packs_epi32(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, pack, i16x8::ZERO))
@@ -6735,7 +6737,8 @@ pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packs_epi16(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, pack, src.as_i8x16()))
@@ -6749,7 +6752,8 @@ pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packs_epi16(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, pack, i8x16::ZERO))
@@ -6975,7 +6979,8 @@ pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packus_epi16(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, pack, src.as_i8x16()))
@@ -6989,7 +6994,8 @@ pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packus_epi16(a, b).as_i8x16();
         transmute(simd_select_bitmask(k, pack, i8x16::ZERO))
@@ -17854,7 +17860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_mask_packs_epi32() {
+    const fn test_mm_mask_packs_epi32() {
         let a = _mm_set1_epi32(i32::MAX);
         let b = _mm_set1_epi32(1 << 16 | 1);
         let r = _mm_mask_packs_epi32(a, 0, a, b);
@@ -17865,7 +17871,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_maskz_packs_epi32() {
+    const fn test_mm_maskz_packs_epi32() {
         let a = _mm_set1_epi32(i32::MAX);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_packs_epi32(0, a, b);
@@ -17954,7 +17960,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_mask_packs_epi16() {
+    const fn test_mm_mask_packs_epi16() {
         let a = _mm_set1_epi16(i16::MAX);
         let b = _mm_set1_epi16(1 << 8 | 1);
         let r = _mm_mask_packs_epi16(a, 0, a, b);
@@ -17966,7 +17972,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_maskz_packs_epi16() {
+    const fn test_mm_maskz_packs_epi16() {
         let a = _mm_set1_epi16(i16::MAX);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_packs_epi16(0, a, b);
@@ -18137,7 +18143,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_mask_packus_epi16() {
+    const fn test_mm_mask_packus_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(1 << 8 | 1);
         let r = _mm_mask_packus_epi16(a, 0, a, b);
@@ -18148,7 +18154,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_maskz_packus_epi16() {
+    const fn test_mm_maskz_packus_epi16() {
         let a = _mm_set1_epi16(-1);
         let b = _mm_set1_epi16(1);
         let r = _mm_maskz_packus_epi16(0, a, b);
diff --git a/crates/core_arch/src/x86/sse2.rs b/crates/core_arch/src/x86/sse2.rs
index fbf62c362f..1f97f3c69d 100644
--- a/crates/core_arch/src/x86/sse2.rs
+++ b/crates/core_arch/src/x86/sse2.rs
@@ -1492,10 +1492,11 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(packsswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
-        let max = simd_splat(i16::from(i8::MAX));
-        let min = simd_splat(i16::from(i8::MIN));
+        let max = simd_splat(i8::MAX as i16);
+        let min = simd_splat(i8::MIN as i16);
 
         let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min)
             .as_m128i()
@@ -1521,10 +1522,11 @@ pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(packssdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
-        let max = simd_splat(i32::from(i16::MAX));
-        let min = simd_splat(i32::from(i16::MIN));
+        let max = simd_splat(i16::MAX as i32);
+        let min = simd_splat(i16::MIN as i32);
 
         let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min);
         let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min);
@@ -1546,10 +1548,11 @@ pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse2")]
 #[cfg_attr(test, assert_instr(packuswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
-        let max = simd_splat(i16::from(u8::MAX));
-        let min = simd_splat(i16::from(u8::MIN));
+        let max = simd_splat(u8::MAX as i16);
+        let min = simd_splat(u8::MIN as i16);
 
         let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min)
             .as_m128i()
@@ -4329,7 +4332,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    fn test_mm_packs_epi16() {
+    const fn test_mm_packs_epi16() {
         let a = _mm_setr_epi16(0x80, -0x81, 0, 0, 0, 0, 0, 0);
         let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -0x81, 0x80);
         let r = _mm_packs_epi16(a, b);
@@ -4343,7 +4346,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    fn test_mm_packs_epi32() {
+    const fn test_mm_packs_epi32() {
         let a = _mm_setr_epi32(0x8000, -0x8001, 0, 0);
         let b = _mm_setr_epi32(0, 0, -0x8001, 0x8000);
         let r = _mm_packs_epi32(a, b);
@@ -4354,7 +4357,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    fn test_mm_packus_epi16() {
+    const fn test_mm_packus_epi16() {
         let a = _mm_setr_epi16(0x100, -1, 0, 0, 0, 0, 0, 0);
         let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -1, 0x100);
         let r = _mm_packus_epi16(a, b);

From 3f65d5130b43dcb841fbc3be7e3f799cba9711dc Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Fri, 20 Feb 2026 07:02:29 -0500
Subject: [PATCH 172/326] Add const to `sse41` intrinsics

---
 crates/core_arch/src/x86/avx512bw.rs | 10 ++++++----
 crates/core_arch/src/x86/sse41.rs    |  9 +++++----
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 8481edcdb3..360b755d58 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6859,7 +6859,8 @@ pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packus_epi32(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, pack, src.as_i16x8()))
@@ -6873,7 +6874,8 @@ pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
     unsafe {
         let pack = _mm_packus_epi32(a, b).as_i16x8();
         transmute(simd_select_bitmask(k, pack, i16x8::ZERO))
@@ -18043,7 +18045,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_mask_packus_epi32() {
+    const fn test_mm_mask_packus_epi32() {
         let a = _mm_set1_epi32(-1);
         let b = _mm_set1_epi32(1 << 16 | 1);
         let r = _mm_mask_packus_epi32(a, 0, a, b);
@@ -18054,7 +18056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm_maskz_packus_epi32() {
+    const fn test_mm_maskz_packus_epi32() {
         let a = _mm_set1_epi32(-1);
         let b = _mm_set1_epi32(1);
         let r = _mm_maskz_packus_epi32(0, a, b);
diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
index 8036f24e24..4ebf7d3bd3 100644
--- a/crates/core_arch/src/x86/sse41.rs
+++ b/crates/core_arch/src/x86/sse41.rs
@@ -426,10 +426,11 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "sse4.1")]
 #[cfg_attr(test, assert_instr(packusdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe {
-        let max = simd_splat(i32::from(u16::MAX));
-        let min = simd_splat(i32::from(u16::MIN));
+        let max = simd_splat(u16::MAX as i32);
+        let min = simd_splat(u16::MIN as i32);
 
         let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min)
             .as_m128i()
@@ -1470,7 +1471,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    fn test_mm_packus_epi32() {
+    const fn test_mm_packus_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let b = _mm_setr_epi32(-1, -2, -3, -4);
         let r = _mm_packus_epi32(a, b);

From a188c12de48fbae8a9ebc22ec9070e0d21c5332d Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Fri, 20 Feb 2026 07:10:51 -0500
Subject: [PATCH 173/326] Add const to `avx2` intrinsics

---
 crates/core_arch/src/x86/avx2.rs     | 36 ++++++++++--------
 crates/core_arch/src/x86/avx512bw.rs | 55 +++++++++++++++++++++-------
 2 files changed, 61 insertions(+), 30 deletions(-)

diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs
index ca4ca9a2de..b49ad9522a 100644
--- a/crates/core_arch/src/x86/avx2.rs
+++ b/crates/core_arch/src/x86/avx2.rs
@@ -2323,10 +2323,11 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
-        let max = simd_splat(i16::from(i8::MAX));
-        let min = simd_splat(i16::from(i8::MIN));
+        let max = simd_splat(i8::MAX as i16);
+        let min = simd_splat(i8::MIN as i16);
 
         let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min)
             .as_m256i()
@@ -2356,10 +2357,11 @@ pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
-        let max = simd_splat(i32::from(i16::MAX));
-        let min = simd_splat(i32::from(i16::MIN));
+        let max = simd_splat(i16::MAX as i32);
+        let min = simd_splat(i16::MIN as i32);
 
         let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min)
             .as_m256i()
@@ -2389,10 +2391,11 @@ pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
-        let max = simd_splat(i16::from(u8::MAX));
-        let min = simd_splat(i16::from(u8::MIN));
+        let max = simd_splat(u8::MAX as i16);
+        let min = simd_splat(u8::MIN as i16);
 
         let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min)
             .as_m256i()
@@ -2422,10 +2425,11 @@ pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
 #[target_feature(enable = "avx2")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe {
-        let max = simd_splat(i32::from(u16::MAX));
-        let min = simd_splat(i32::from(u16::MIN));
+        let max = simd_splat(u16::MAX as i32);
+        let min = simd_splat(u16::MIN as i32);
 
         let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min)
             .as_m256i()
@@ -5064,7 +5068,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    fn test_mm256_packs_epi16() {
+    const fn test_mm256_packs_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_packs_epi16(a, b);
@@ -5080,7 +5084,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    fn test_mm256_packs_epi32() {
+    const fn test_mm256_packs_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_packs_epi32(a, b);
@@ -5090,7 +5094,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    fn test_mm256_packus_epi16() {
+    const fn test_mm256_packus_epi16() {
         let a = _mm256_set1_epi16(2);
         let b = _mm256_set1_epi16(4);
         let r = _mm256_packus_epi16(a, b);
@@ -5106,7 +5110,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    fn test_mm256_packus_epi32() {
+    const fn test_mm256_packus_epi32() {
         let a = _mm256_set1_epi32(2);
         let b = _mm256_set1_epi32(4);
         let r = _mm256_packus_epi32(a, b);
diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 360b755d58..8c7921fc18 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6587,7 +6587,13 @@ pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
-pub fn _mm256_mask_packs_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_packs_epi32(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let pack = _mm256_packs_epi32(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, pack, src.as_i16x16()))
@@ -6709,7 +6715,13 @@ pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_packs_epi16(
+    src: __m256i,
+    k: __mmask32,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let pack = _mm256_packs_epi16(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, pack, src.as_i8x32()))
@@ -6723,7 +6735,8 @@ pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let pack = _mm256_packs_epi16(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, pack, i8x32::ZERO))
@@ -6831,7 +6844,13 @@ pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_packus_epi32(
+    src: __m256i,
+    k: __mmask16,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let pack = _mm256_packus_epi32(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, pack, src.as_i16x16()))
@@ -6845,7 +6864,8 @@ pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m25
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let pack = _mm256_packus_epi32(a, b).as_i16x16();
         transmute(simd_select_bitmask(k, pack, i16x16::ZERO))
@@ -6953,7 +6973,13 @@ pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_mask_packus_epi16(
+    src: __m256i,
+    k: __mmask32,
+    a: __m256i,
+    b: __m256i,
+) -> __m256i {
     unsafe {
         let pack = _mm256_packus_epi16(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, pack, src.as_i8x32()))
@@ -6967,7 +6993,8 @@ pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m25
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
     unsafe {
         let pack = _mm256_packus_epi16(a, b).as_i8x32();
         transmute(simd_select_bitmask(k, pack, i8x32::ZERO))
@@ -17838,7 +17865,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_mask_packs_epi32() {
+    const fn test_mm256_mask_packs_epi32() {
         let a = _mm256_set1_epi32(i32::MAX);
         let b = _mm256_set1_epi32(1 << 16 | 1);
         let r = _mm256_mask_packs_epi32(a, 0, a, b);
@@ -17936,7 +17963,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_mask_packs_epi16() {
+    const fn test_mm256_mask_packs_epi16() {
         let a = _mm256_set1_epi16(i16::MAX);
         let b = _mm256_set1_epi16(1 << 8 | 1);
         let r = _mm256_mask_packs_epi16(a, 0, a, b);
@@ -17949,7 +17976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_maskz_packs_epi16() {
+    const fn test_mm256_maskz_packs_epi16() {
         let a = _mm256_set1_epi16(i16::MAX);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_packs_epi16(0, a, b);
@@ -18023,7 +18050,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_mask_packus_epi32() {
+    const fn test_mm256_mask_packus_epi32() {
         let a = _mm256_set1_epi32(-1);
         let b = _mm256_set1_epi32(1 << 16 | 1);
         let r = _mm256_mask_packus_epi32(a, 0, a, b);
@@ -18034,7 +18061,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_maskz_packus_epi32() {
+    const fn test_mm256_maskz_packus_epi32() {
         let a = _mm256_set1_epi32(-1);
         let b = _mm256_set1_epi32(1);
         let r = _mm256_maskz_packus_epi32(0, a, b);
@@ -18119,7 +18146,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_mask_packus_epi16() {
+    const fn test_mm256_mask_packus_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(1 << 8 | 1);
         let r = _mm256_mask_packus_epi16(a, 0, a, b);
@@ -18132,7 +18159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    fn test_mm256_maskz_packus_epi16() {
+    const fn test_mm256_maskz_packus_epi16() {
         let a = _mm256_set1_epi16(-1);
         let b = _mm256_set1_epi16(1);
         let r = _mm256_maskz_packus_epi16(0, a, b);

From 9fe604f6b5fa2619252cd4dcc52139480310ea5b Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Fri, 20 Feb 2026 07:30:10 -0500
Subject: [PATCH 174/326] Add const to `avx512bw` intrinsics

---
 crates/core_arch/src/x86/avx512bw.rs | 96 ++++++++++++++++++----------
 1 file changed, 64 insertions(+), 32 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index 8c7921fc18..b41f8576cf 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -6523,10 +6523,11 @@ pub fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
-pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
-        let max = simd_splat(i32::from(i16::MAX));
-        let min = simd_splat(i32::from(i16::MIN));
+        let max = simd_splat(i16::MAX as i32);
+        let min = simd_splat(i16::MIN as i32);
 
         let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min)
             .as_m512i()
@@ -6559,7 +6560,13 @@ pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
-pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_packs_epi32(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let pack = _mm512_packs_epi32(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, pack, src.as_i16x32()))
@@ -6573,7 +6580,8 @@ pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackssdw))]
-pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let pack = _mm512_packs_epi32(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, pack, i16x32::ZERO))
@@ -6651,10 +6659,11 @@ pub const fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m12
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
-        let max = simd_splat(i16::from(i8::MAX));
-        let min = simd_splat(i16::from(i8::MIN));
+        let max = simd_splat(i8::MAX as i16);
+        let min = simd_splat(i8::MIN as i16);
 
         let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min)
             .as_m512i()
@@ -6687,7 +6696,13 @@ pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_packs_epi16(
+    src: __m512i,
+    k: __mmask64,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let pack = _mm512_packs_epi16(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, pack, src.as_i8x64()))
@@ -6701,7 +6716,8 @@ pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpacksswb))]
-pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let pack = _mm512_packs_epi16(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, pack, i8x64::ZERO))
@@ -6780,10 +6796,11 @@ pub const fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m1
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
-        let max = simd_splat(i32::from(u16::MAX));
-        let min = simd_splat(i32::from(u16::MIN));
+        let max = simd_splat(u16::MAX as i32);
+        let min = simd_splat(u16::MIN as i32);
 
         let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min)
             .as_m512i()
@@ -6816,7 +6833,13 @@ pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_packus_epi32(
+    src: __m512i,
+    k: __mmask32,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let pack = _mm512_packus_epi32(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, pack, src.as_i16x32()))
@@ -6830,7 +6853,8 @@ pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m51
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackusdw))]
-pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let pack = _mm512_packus_epi32(a, b).as_i16x32();
         transmute(simd_select_bitmask(k, pack, i16x32::ZERO))
@@ -6909,10 +6933,11 @@ pub const fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m1
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i {
     unsafe {
-        let max = simd_splat(i16::from(u8::MAX));
-        let min = simd_splat(i16::from(u8::MIN));
+        let max = simd_splat(u8::MAX as i16);
+        let min = simd_splat(u8::MIN as i16);
 
         let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min)
             .as_m512i()
@@ -6945,7 +6970,13 @@ pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_mask_packus_epi16(
+    src: __m512i,
+    k: __mmask64,
+    a: __m512i,
+    b: __m512i,
+) -> __m512i {
     unsafe {
         let pack = _mm512_packus_epi16(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, pack, src.as_i8x64()))
@@ -6959,7 +6990,8 @@ pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m51
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpackuswb))]
-pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
+pub const fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
     unsafe {
         let pack = _mm512_packus_epi16(a, b).as_i8x64();
         transmute(simd_select_bitmask(k, pack, i8x64::ZERO))
@@ -17828,7 +17860,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_packs_epi32() {
+    const fn test_mm512_packs_epi32() {
         let a = _mm512_set1_epi32(i32::MAX);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_packs_epi32(a, b);
@@ -17839,7 +17871,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_mask_packs_epi32() {
+    const fn test_mm512_mask_packs_epi32() {
         let a = _mm512_set1_epi32(i32::MAX);
         let b = _mm512_set1_epi32(1 << 16 | 1);
         let r = _mm512_mask_packs_epi32(a, 0, a, b);
@@ -17852,7 +17884,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_maskz_packs_epi32() {
+    const fn test_mm512_maskz_packs_epi32() {
         let a = _mm512_set1_epi32(i32::MAX);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_packs_epi32(0, a, b);
@@ -17911,7 +17943,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_packs_epi16() {
+    const fn test_mm512_packs_epi16() {
         let a = _mm512_set1_epi16(i16::MAX);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_packs_epi16(a, b);
@@ -17924,7 +17956,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_mask_packs_epi16() {
+    const fn test_mm512_mask_packs_epi16() {
         let a = _mm512_set1_epi16(i16::MAX);
         let b = _mm512_set1_epi16(1 << 8 | 1);
         let r = _mm512_mask_packs_epi16(a, 0, a, b);
@@ -17944,7 +17976,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_maskz_packs_epi16() {
+    const fn test_mm512_maskz_packs_epi16() {
         let a = _mm512_set1_epi16(i16::MAX);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_packs_epi16(0, a, b);
@@ -18013,7 +18045,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_packus_epi32() {
+    const fn test_mm512_packus_epi32() {
         let a = _mm512_set1_epi32(-1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_packus_epi32(a, b);
@@ -18024,7 +18056,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_mask_packus_epi32() {
+    const fn test_mm512_mask_packus_epi32() {
         let a = _mm512_set1_epi32(-1);
         let b = _mm512_set1_epi32(1 << 16 | 1);
         let r = _mm512_mask_packus_epi32(a, 0, a, b);
@@ -18037,7 +18069,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_maskz_packus_epi32() {
+    const fn test_mm512_maskz_packus_epi32() {
         let a = _mm512_set1_epi32(-1);
         let b = _mm512_set1_epi32(1);
         let r = _mm512_maskz_packus_epi32(0, a, b);
@@ -18094,7 +18126,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_packus_epi16() {
+    const fn test_mm512_packus_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_packus_epi16(a, b);
@@ -18107,7 +18139,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_mask_packus_epi16() {
+    const fn test_mm512_mask_packus_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(1 << 8 | 1);
         let r = _mm512_mask_packus_epi16(a, 0, a, b);
@@ -18127,7 +18159,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    fn test_mm512_maskz_packus_epi16() {
+    const fn test_mm512_maskz_packus_epi16() {
         let a = _mm512_set1_epi16(-1);
         let b = _mm512_set1_epi16(1);
         let r = _mm512_maskz_packus_epi16(0, a, b);

From 7a8829af33c37ea7c69a42526089e152c1b59912 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 23 Feb 2026 11:58:18 +0100
Subject: [PATCH 175/326] aarch64: cleanup of some long array literals

---
 .../core_arch/src/aarch64/neon/generated.rs   | 539 ++----------------
 .../spec/neon/aarch64.spec.yml                | 108 ++--
 2 files changed, 108 insertions(+), 539 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 41f01d445f..de64839661 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -14131,26 +14131,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlal_high_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
@@ -14165,26 +14146,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
     c: int16x8_t,
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlal_high_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
@@ -14195,13 +14157,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlal_high_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
@@ -14216,13 +14172,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
     c: int32x4_t,
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlal_high_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
@@ -14237,26 +14187,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
     c: uint16x4_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlal_high_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
@@ -14271,26 +14202,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
     c: uint16x8_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlal_high_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
@@ -14305,13 +14217,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
     c: uint32x2_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlal_high_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
@@ -14326,13 +14232,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
     c: uint32x4_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlal_high_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
@@ -14475,26 +14375,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsl_high_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
@@ -14509,26 +14390,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
     c: int16x8_t,
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlsl_high_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
@@ -14539,13 +14401,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlsl_high_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
@@ -14560,13 +14416,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
     c: int32x4_t,
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsl_high_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
@@ -14581,26 +14431,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
     c: uint16x4_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsl_high_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
@@ -14615,26 +14446,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
     c: uint16x8_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlsl_high_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
@@ -14649,13 +14461,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
     c: uint32x2_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlsl_high_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
@@ -14670,13 +14476,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
     c: uint32x4_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsl_high_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
@@ -14975,12 +14775,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"]
@@ -14992,25 +14787,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"]
@@ -15104,25 +14881,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmull_high_s16(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
@@ -15133,25 +14892,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmull_high_s16(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
@@ -15162,12 +14903,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmull_high_s32(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
@@ -15178,12 +14914,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmull_high_s32(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
@@ -15194,25 +14925,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmull_high_u16(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
@@ -15223,25 +14936,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmull_high_u16(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
@@ -15252,12 +14947,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmull_high_u32(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
@@ -15268,12 +14958,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmull_high_u32(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
@@ -15436,7 +15121,7 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t {
     static_assert!(LANE == 0);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"]
@@ -15447,7 +15132,7 @@ pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float6
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"]
@@ -15599,12 +15284,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmulx_f16(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"]
@@ -15616,12 +15296,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmulx_f16(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"]
@@ -15633,25 +15308,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmulxq_f16(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"]
@@ -15663,25 +15320,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmulxq_f16(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"]
@@ -15692,7 +15331,7 @@ pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> floa
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"]
@@ -15703,7 +15342,7 @@ pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float3
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"]
@@ -15714,12 +15353,7 @@ pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmulxq_f32(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"]
@@ -15730,12 +15364,7 @@ pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmulxq_f32(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"]
@@ -15746,7 +15375,7 @@ pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> floa
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"]
@@ -15916,7 +15545,7 @@ pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t {
     static_assert!(LANE == 0);
-    unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"]
@@ -17916,8 +17545,7 @@ pub fn vqnegd_s64(a: i64) -> i64 {
 pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int16x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlah_s16(a, b, c)
     }
 }
@@ -17931,7 +17559,7 @@ pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
     unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
         vqrdmlah_s32(a, b, c)
     }
 }
@@ -17945,8 +17573,7 @@ pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
     unsafe {
-        let c: int16x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlah_s16(a, b, c)
     }
 }
@@ -17960,7 +17587,7 @@ pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
         vqrdmlah_s32(a, b, c)
     }
 }
@@ -17974,20 +17601,7 @@ pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32
-            ]
-        );
+        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
         vqrdmlahq_s16(a, b, c)
     }
 }
@@ -18001,8 +17615,7 @@ pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
     unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlahq_s32(a, b, c)
     }
 }
@@ -18016,20 +17629,7 @@ pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
     unsafe {
-        let c: int16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32
-            ]
-        );
+        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
         vqrdmlahq_s16(a, b, c)
     }
 }
@@ -18043,8 +17643,7 @@ pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 pub fn vqrdmlahq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlahq_s32(a, b, c)
     }
 }
@@ -18190,8 +17789,7 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
 pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int16x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlsh_s16(a, b, c)
     }
 }
@@ -18205,7 +17803,7 @@ pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
     unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
         vqrdmlsh_s32(a, b, c)
     }
 }
@@ -18219,8 +17817,7 @@ pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
     unsafe {
-        let c: int16x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlsh_s16(a, b, c)
     }
 }
@@ -18234,7 +17831,7 @@ pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
         vqrdmlsh_s32(a, b, c)
     }
 }
@@ -18248,20 +17845,7 @@ pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32
-            ]
-        );
+        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
         vqrdmlshq_s16(a, b, c)
     }
 }
@@ -18275,8 +17859,7 @@ pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
     unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlshq_s32(a, b, c)
     }
 }
@@ -18290,20 +17873,7 @@ pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
     unsafe {
-        let c: int16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32
-            ]
-        );
+        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
         vqrdmlshq_s16(a, b, c)
     }
 }
@@ -18317,8 +17887,7 @@ pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 pub fn vqrdmlshq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
         vqrdmlshq_s32(a, b, c)
     }
 }
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 0ec8024fdf..8574aacee6 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5374,7 +5374,7 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32, LANE as u32]']
+      - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32; 2]']
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
       - FnCall:
@@ -5443,11 +5443,11 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32, LANE as u32]']
-      - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32, LANE as u32]']
-      - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32, LANE as u32]']
+      - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32; 2]']
+      - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32; 2]']
+      - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32; 4]']
+      - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32; 4]']
+      - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32; 2]']
     compose:
       - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]]
       - FnCall:
@@ -5473,10 +5473,10 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32; 4]']
+      - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32; 4]']
+      - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32; 8]']
+      - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32; 8]']
     compose:
       - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]]
       - FnCall:
@@ -7755,14 +7755,14 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]']
+      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]']
+      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
+      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
+      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]']
+      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]']
+      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
+      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']]
       - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}]
@@ -7839,14 +7839,14 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]']
+      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]']
+      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
+      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
+      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]']
+      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]']
+      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
+      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']]
       - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}]
@@ -11138,7 +11138,7 @@ intrinsics:
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32, LANE as u32]']]
+            - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32; 2]']]
 
   - name: "vmuld_lane_f64"
     doc: "Floating-point multiply"
@@ -11195,7 +11195,7 @@ intrinsics:
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: [simd_shuffle!, [b, b, '[LANE as u32, LANE as u32]']]
+            - FnCall: [simd_shuffle!, [b, b, '[LANE as u32; 2]']]
 
 
   # vmulq_laneq_f16
@@ -11212,8 +11212,8 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float16x4_t, float16x8_t, '_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32]"]
-      - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]"]
+      - [float16x4_t, float16x8_t, '_lane', "[LANE as u32; 4]"]
+      - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32; 8]"]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '3']]
       - FnCall:
@@ -11335,10 +11335,10 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
+      - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
+      - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
+      - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
@@ -11358,10 +11358,10 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]']
+      - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]']
+      - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]']
+      - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
@@ -11660,10 +11660,10 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32; 8]']
+      - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32; 8]']
+      - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32; 4]']
+      - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
@@ -11682,10 +11682,10 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32; 8]']
+      - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32; 8]']
+      - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32; 4]']
+      - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
@@ -11973,10 +11973,10 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
+      - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
+      - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
+      - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]]
@@ -11992,10 +11992,10 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]']
+      - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]']
+      - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]']
+      - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]]

From 792d10e70555841e092f03a01924f4c4564e6ba7 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Wed, 25 Feb 2026 04:49:15 +0530
Subject: [PATCH 176/326] Update Intel SDE version to 10.5

---
 ci/docker/x86_64-unknown-linux-gnu/Dockerfile | 2 +-
 ci/docker/x86_64-unknown-linux-gnu/cpuid.def  | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
index 2743896375..a357449d51 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
@@ -12,7 +12,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   build-essential \
   lld
 
-RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.58.0-2025-06-16-lin.tar.xz -O sde.tar.xz
+RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-10.5.0-2026-01-13-lin.tar.xz -O sde.tar.xz
 RUN mkdir intel-sde
 RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde
 ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \
diff --git a/ci/docker/x86_64-unknown-linux-gnu/cpuid.def b/ci/docker/x86_64-unknown-linux-gnu/cpuid.def
index 342f7d83a6..acf023ed0d 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/cpuid.def
+++ b/ci/docker/x86_64-unknown-linux-gnu/cpuid.def
@@ -12,7 +12,7 @@
 # CPUID_VERSION = 1.0
 #      Input      =>               Output
 # EAX      ECX    =>   EAX      EBX      ECX      EDX
-00000000 ******** => 00000024 756e6547 6c65746e 49656e69
+00000000 ******** => 00000029 756e6547 6c65746e 49656e69
 00000001 ******** => 00400f10 00100800 7ffaf3ff bfebfbff
 00000002 ******** => 76035a01 00f0b6ff 00000000 00c10000
 00000003 ******** => 00000000 00000000 00000000 00000000
@@ -48,6 +48,7 @@
 0000001e 00000001 => 000001ff 00000000 00000000 00000000
 00000024 00000000 => 00000001 00070002 00000000 00000000 #AVX10
 00000024 00000001 => 00000000 00000000 00000004 00000000
+00000029 ******** => 00000000 00000001 00000000 00000000
 80000000 ******** => 80000008 00000000 00000000 00000000
 80000001 ******** => 00000000 00000000 00000121 2c100000
 80000002 ******** => 00000000 00000000 00000000 00000000

From cf7c280c45b47e8cec3fd7afbe9f982aa0049679 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 25 Feb 2026 15:00:04 +0100
Subject: [PATCH 177/326] update to `resolver = 3`

---
 Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index 5979096439..e3963a6987 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,5 +1,5 @@
 [workspace]
-resolver = "1"
+resolver = "3"
 members = [
   "crates/*",
   "examples",

From 5c271992588aedb0f7b449a1252441be34c74826 Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Wed, 25 Feb 2026 23:56:42 +0000
Subject: [PATCH 178/326] Add missing runtime test for _mm_comige_ss and fix
 _mm_comigt_ss test

---
 crates/core_arch/src/x86/sse.rs | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 2c4439a3f3..3f7781cc7d 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2816,14 +2816,32 @@ mod tests {
         let aa = &[3.0f32, 12.0, 23.0, NAN];
         let bb = &[3.0f32, 47.5, 1.5, NAN];
 
-        let ee = &[1i32, 0, 1, 0];
+        let ee = &[0i32, 0, 1, 0];
 
         for i in 0..4 {
             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
 
-            let r = _mm_comige_ss(a, b);
+            let r = _mm_comigt_ss(a, b);
 
+            assert_eq!(
+                ee[i], r,
+                "_mm_comigt_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                a, b, r, ee[i], i
+            );
+        }
+    }
+
+    #[simd_test(enable = "sse")]
+    fn test_mm_comige_ss() {
+        let aa = &[3.0f32, 23.0, 12.0, NAN];
+        let bb = &[3.0f32, 1.5, 47.5, NAN];
+        let ee = &[1i32, 1, 0, 0];
+
+        for i in 0..4 {
+            let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+            let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+            let r = _mm_comige_ss(a, b);
             assert_eq!(
                 ee[i], r,
                 "_mm_comige_ss({:?}, {:?}) = {}, expected: {} (i={})",

From ea6a074876f2a489c2f3ed907a1943998fe8751e Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Thu, 26 Feb 2026 09:19:29 +0000
Subject: [PATCH 179/326] Remove _mm_comige_ss from skip list in x86-intel.rs

---
 crates/stdarch-verify/tests/x86-intel.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 4136463f19..2ac05e28cb 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -246,7 +246,6 @@ fn verify_all_signatures() {
                 "_xend",
                 "_xabort_code",
                 // Aliases
-                "_mm_comige_ss",
                 "_mm_cvt_ss2si",
                 "_mm_cvtt_ss2si",
                 "_mm_cvt_si2ss",

From 5d0935fea966c70500957f4f29b99c58ad3a0c49 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 26 Feb 2026 13:00:21 +0100
Subject: [PATCH 180/326] aarch64: fix UB in non-power-of-two reads and writes

---
 crates/core_arch/src/macros.rs | 29 ++++++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 5a582fe177..00e92428b3 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -237,12 +237,12 @@ macro_rules! deinterleaving_load {
     ($elem:ty, $lanes:literal, 2, $ptr:expr) => {{
         use $crate::core_arch::macros::deinterleave_mask;
         use $crate::core_arch::simd::Simd;
-        use $crate::{mem::transmute, ptr};
+        use $crate::mem::transmute;
 
         type V = Simd<$elem, $lanes>;
         type W = Simd<$elem, { $lanes * 2 }>;
 
-        let w: W = ptr::read_unaligned($ptr as *const W);
+        let w: W = $crate::ptr::read_unaligned($ptr as *const W);
 
         let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 0>());
         let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 1>());
@@ -253,12 +253,20 @@ macro_rules! deinterleaving_load {
     ($elem:ty, $lanes:literal, 3, $ptr:expr) => {{
         use $crate::core_arch::macros::deinterleave_mask;
         use $crate::core_arch::simd::Simd;
-        use $crate::{mem::transmute, ptr};
+        use $crate::mem::{MaybeUninit, transmute};
 
         type V = Simd<$elem, $lanes>;
         type W = Simd<$elem, { $lanes * 3 }>;
 
-        let w: W = ptr::read_unaligned($ptr as *const W);
+        // NOTE: repr(simd) adds padding to make the total size a power of two.
+        // Hence reading W from ptr might read out of bounds.
+        let mut mem = MaybeUninit::<W>::uninit();
+        $crate::ptr::copy_nonoverlapping(
+            $ptr.cast::<$elem>(),
+            mem.as_mut_ptr().cast::<$elem>(),
+            $lanes * 3,
+        );
+        let w = mem.assume_init();
 
         let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 0>());
         let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 1>());
@@ -270,12 +278,12 @@ macro_rules! deinterleaving_load {
     ($elem:ty, $lanes:literal, 4, $ptr:expr) => {{
         use $crate::core_arch::macros::deinterleave_mask;
         use $crate::core_arch::simd::Simd;
-        use $crate::{mem::transmute, ptr};
+        use $crate::mem::transmute;
 
         type V = Simd<$elem, $lanes>;
         type W = Simd<$elem, { $lanes * 4 }>;
 
-        let w: W = ptr::read_unaligned($ptr as *const W);
+        let w: W = $crate::ptr::read_unaligned($ptr as *const W);
 
         let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 0>());
         let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 1>());
@@ -322,8 +330,15 @@ macro_rules! interleaving_store {
             simd_shuffle!($v.2, $v.2, identity::<{ $lanes * 2 }>());
 
         type W = Simd<$elem, { $lanes * 3 }>;
+
+        // NOTE: repr(simd) adds padding to make the total size a power of two.
+        // Hence writing W to ptr might write out of bounds.
         let w: W = simd_shuffle!(v0v1, v2v2, interleave_mask::<{ $lanes * 3 }, $lanes, 3>());
-        $crate::ptr::write_unaligned($ptr as *mut W, w);
+        $crate::ptr::copy_nonoverlapping(
+            (&w as *const W).cast::<$elem>(),
+            $ptr.cast::<$elem>(),
+            $lanes * 3,
+        );
     }};
 
     // N = 4

From de85b1c6fe86fcf8626d390d3efe25ab462077e2 Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Thu, 26 Feb 2026 00:42:04 +0000
Subject: [PATCH 181/326] Add missing runtime tests for alias intrinsics:
 _mm_cvt_ss2si, _mm_cvtt_ss2si, _mm_cvt_si2ss, _mm_set_ps1

---
 crates/core_arch/src/x86/sse.rs | 71 +++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 3f7781cc7d..0ec842f9fc 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3013,6 +3013,22 @@ mod tests {
         }
     }
 
+    #[simd_test(enable = "sse")]
+    fn test_mm_cvt_ss2si() {
+        let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
+        let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
+        for i in 0..inputs.len() {
+            let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
+            let e = result[i];
+            let r = _mm_cvt_ss2si(x);
+            assert_eq!(
+                e, r,
+                "TestCase #{} _mm_cvt_ss2si({:?}) = {}, expected: {}",
+                i, x, r, e
+            );
+        }
+    }
+
     #[simd_test(enable = "sse")]
     fn test_mm_cvttss_si32() {
         let inputs = &[
@@ -3038,6 +3054,31 @@ mod tests {
         }
     }
 
+    #[simd_test(enable = "sse")]
+    fn test_mm_cvtt_ss2si() {
+        let inputs = &[
+            (42.0f32, 42i32),
+            (-31.4, -31),
+            (-33.5, -33),
+            (-34.5, -34),
+            (10.999, 10),
+            (-5.99, -5),
+            (4.0e10, i32::MIN),
+            (4.0e-10, 0),
+            (NAN, i32::MIN),
+            (2147483500.1, 2147483520),
+        ];
+        for (i, &(xi, e)) in inputs.iter().enumerate() {
+            let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+            let r = _mm_cvtt_ss2si(x);
+            assert_eq!(
+                e, r,
+                "TestCase #{} _mm_cvtt_ss2si({:?}) = {}, expected: {}",
+                i, x, r, e
+            );
+        }
+    }
+
     #[simd_test(enable = "sse")]
     const fn test_mm_cvtsi32_ss() {
         let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
@@ -3059,6 +3100,27 @@ mod tests {
         assert_eq_m128(e, r);
     }
 
+    #[simd_test(enable = "sse")]
+    fn test_mm_cvt_si2ss() {
+        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+
+        let r = _mm_cvt_si2ss(a, 4555);
+        let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvt_si2ss(a, 322223333);
+        let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvt_si2ss(a, -432);
+        let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+
+        let r = _mm_cvt_si2ss(a, -322223333);
+        let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0);
+        assert_eq_m128(e, r);
+    }
+
     #[simd_test(enable = "sse")]
     const fn test_mm_cvtss_f32() {
         let a = _mm_setr_ps(312.0134, 5.0, 6.0, 7.0);
@@ -3085,6 +3147,15 @@ mod tests {
         assert_eq!(get_m128(r2, 3), 4.25);
     }
 
+    #[simd_test(enable = "sse")]
+    const fn test_mm_set_ps1() {
+        let r = _mm_set_ps1(black_box(4.25));
+        assert_eq!(get_m128(r, 0), 4.25);
+        assert_eq!(get_m128(r, 1), 4.25);
+        assert_eq!(get_m128(r, 2), 4.25);
+        assert_eq!(get_m128(r, 3), 4.25);
+    }
+
     #[simd_test(enable = "sse")]
     const fn test_mm_set_ps() {
         let r = _mm_set_ps(

From b397dacf633e07d925d6646042cbf54622608936 Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Thu, 26 Feb 2026 16:18:30 +0000
Subject: [PATCH 182/326] Refactor alias tests using meta function pattern and
 add missing tests for _mm_undefined_ps, _mm_prefetch, _mm_load_ps1,
 _mm_store_ps1

---
 crates/core_arch/src/x86/sse.rs          | 216 ++++++++++-------------
 crates/stdarch-verify/tests/x86-intel.rs |   7 +-
 2 files changed, 94 insertions(+), 129 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 0ec842f9fc..4e9a3a3cb1 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2997,40 +2997,28 @@ mod tests {
         }
     }
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvtss_si32() {
+    fn test_mm_cvtss_si32_impl(f: fn(__m128) -> i32) {
         let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
         let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
         for i in 0..inputs.len() {
-            let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
+            let x = unsafe { _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0) };
             let e = result[i];
-            let r = _mm_cvtss_si32(x);
-            assert_eq!(
-                e, r,
-                "TestCase #{} _mm_cvtss_si32({:?}) = {}, expected: {}",
-                i, x, r, e
-            );
+            let r = f(x);
+            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
         }
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_cvt_ss2si() {
-        let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
-        let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
-        for i in 0..inputs.len() {
-            let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
-            let e = result[i];
-            let r = _mm_cvt_ss2si(x);
-            assert_eq!(
-                e, r,
-                "TestCase #{} _mm_cvt_ss2si({:?}) = {}, expected: {}",
-                i, x, r, e
-            );
-        }
+    fn test_mm_cvtss_si32() {
+        test_mm_cvtss_si32_impl(_mm_cvtss_si32);
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_cvttss_si32() {
+    fn test_mm_cvt_ss2si() {
+        test_mm_cvtss_si32_impl(_mm_cvt_ss2si);
+    }
+
+    fn test_cvttss_si32_impl(f: fn(__m128) -> i32) {
         let inputs = &[
             (42.0f32, 42i32),
             (-31.4, -31),
@@ -3044,81 +3032,48 @@ mod tests {
             (2147483500.1, 2147483520),
         ];
         for (i, &(xi, e)) in inputs.iter().enumerate() {
-            let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
-            let r = _mm_cvttss_si32(x);
-            assert_eq!(
-                e, r,
-                "TestCase #{} _mm_cvttss_si32({:?}) = {}, expected: {}",
-                i, x, r, e
-            );
+            let x = unsafe { _mm_setr_ps(xi, 1.0, 3.0, 4.0) };
+            let r = f(x);
+            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
         }
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_cvtt_ss2si() {
-        let inputs = &[
-            (42.0f32, 42i32),
-            (-31.4, -31),
-            (-33.5, -33),
-            (-34.5, -34),
-            (10.999, 10),
-            (-5.99, -5),
-            (4.0e10, i32::MIN),
-            (4.0e-10, 0),
-            (NAN, i32::MIN),
-            (2147483500.1, 2147483520),
-        ];
-        for (i, &(xi, e)) in inputs.iter().enumerate() {
-            let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
-            let r = _mm_cvtt_ss2si(x);
-            assert_eq!(
-                e, r,
-                "TestCase #{} _mm_cvtt_ss2si({:?}) = {}, expected: {}",
-                i, x, r, e
-            );
-        }
+    fn test_mm_cvttss_si32() {
+        test_cvttss_si32_impl(_mm_cvttss_si32);
     }
 
     #[simd_test(enable = "sse")]
-    const fn test_mm_cvtsi32_ss() {
-        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+    fn test_mm_cvtt_ss2si() {
+        test_cvttss_si32_impl(_mm_cvtt_ss2si)
+    }
 
-        let r = _mm_cvtsi32_ss(a, 4555);
-        let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
+    fn test_mm_cvtsi32_ss_impl(f: fn(__m128, i32) -> __m128) {
+        unsafe {
+            let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-        let r = _mm_cvtsi32_ss(a, 322223333);
-        let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
+            let r = f(a, 4555);
+            assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r);
 
-        let r = _mm_cvtsi32_ss(a, -432);
-        let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
+            let r = f(a, 322223333);
+            assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r);
 
-        let r = _mm_cvtsi32_ss(a, -322223333);
-        let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
+            let r = f(a, -432);
+            assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r);
+
+            let r = f(a, -322223333);
+            assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r);
+        }
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_cvt_si2ss() {
-        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
-
-        let r = _mm_cvt_si2ss(a, 4555);
-        let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
-
-        let r = _mm_cvt_si2ss(a, 322223333);
-        let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
-
-        let r = _mm_cvt_si2ss(a, -432);
-        let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
+    fn test_mm_cvtsi32_ss() {
+        test_mm_cvtsi32_ss_impl(_mm_cvtsi32_ss);
+    }
 
-        let r = _mm_cvt_si2ss(a, -322223333);
-        let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0);
-        assert_eq_m128(e, r);
+    #[simd_test(enable = "sse")]
+    fn test_mm_cvt_si2ss() {
+        test_mm_cvtsi32_ss_impl(_mm_cvt_si2ss);
     }
 
     #[simd_test(enable = "sse")]
@@ -3133,27 +3088,25 @@ mod tests {
         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
     }
 
+    fn test_mm_set1_ps_impl(f: fn(f32) -> __m128) {
+        unsafe {
+            let r = f(black_box(4.25));
+            assert_eq!(get_m128(r, 0), 4.25);
+            assert_eq!(get_m128(r, 1), 4.25);
+            assert_eq!(get_m128(r, 2), 4.25);
+            assert_eq!(get_m128(r, 3), 4.25);
+        }
+    }
+
     #[simd_test(enable = "sse")]
-    const fn test_mm_set1_ps() {
-        let r1 = _mm_set1_ps(black_box(4.25));
-        let r2 = _mm_set_ps1(black_box(4.25));
-        assert_eq!(get_m128(r1, 0), 4.25);
-        assert_eq!(get_m128(r1, 1), 4.25);
-        assert_eq!(get_m128(r1, 2), 4.25);
-        assert_eq!(get_m128(r1, 3), 4.25);
-        assert_eq!(get_m128(r2, 0), 4.25);
-        assert_eq!(get_m128(r2, 1), 4.25);
-        assert_eq!(get_m128(r2, 2), 4.25);
-        assert_eq!(get_m128(r2, 3), 4.25);
+    fn test_mm_set1_ps() {
+        test_mm_set1_ps_impl(_mm_set1_ps);
+        test_mm_set1_ps_impl(_mm_set_ps1);
     }
 
     #[simd_test(enable = "sse")]
-    const fn test_mm_set_ps1() {
-        let r = _mm_set_ps1(black_box(4.25));
-        assert_eq!(get_m128(r, 0), 4.25);
-        assert_eq!(get_m128(r, 1), 4.25);
-        assert_eq!(get_m128(r, 2), 4.25);
-        assert_eq!(get_m128(r, 3), 4.25);
+    fn test_mm_set_ps1() {
+        test_mm_set1_ps_impl(_mm_set_ps1);
     }
 
     #[simd_test(enable = "sse")]
@@ -3242,11 +3195,20 @@ mod tests {
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
-    #[simd_test(enable = "sse")]
-    const fn test_mm_load1_ps() {
+    fn test_mm_load1_ps_impl(f: unsafe fn(*const f32) -> __m128) {
         let a = 42.0f32;
-        let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) };
-        assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
+        let r = unsafe { f(ptr::addr_of!(a)) };
+        unsafe { assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)) };
+    }
+
+    #[simd_test(enable = "sse")]
+    fn test_mm_load1_ps() {
+        test_mm_load1_ps_impl(_mm_load1_ps);
+    }
+
+    #[simd_test(enable = "sse")]
+    fn test_mm_load_ps1() {
+        test_mm_load1_ps_impl(_mm_load_ps1);
     }
 
     #[simd_test(enable = "sse")]
@@ -3298,34 +3260,24 @@ mod tests {
         assert_eq!(vals[2], 0.0);
     }
 
-    #[simd_test(enable = "sse")]
-    const fn test_mm_store1_ps() {
+    fn test_mm_store1_ps_impl(f: unsafe fn(*mut f32, __m128)) {
         let mut vals = Memory { data: [0.0f32; 4] };
-        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-
-        // guaranteed to be aligned to 16 bytes
+        let a = unsafe { _mm_setr_ps(1.0, 2.0, 3.0, 4.0) };
         let p = vals.data.as_mut_ptr();
-
         unsafe {
-            _mm_store1_ps(p, *black_box(&a));
+            f(p, *black_box(&a));
         }
-
         assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const fn test_mm_store_ps() {
-        let mut vals = Memory { data: [0.0f32; 4] };
-        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-
-        // guaranteed to be aligned to 16 bytes
-        let p = vals.data.as_mut_ptr();
-
-        unsafe {
-            _mm_store_ps(p, *black_box(&a));
-        }
+    fn test_mm_store1_ps() {
+        test_mm_store1_ps_impl(_mm_store1_ps);
+    }
 
-        assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
+    #[simd_test(enable = "sse")]
+    fn test_mm_store_ps1() {
+        test_mm_store1_ps_impl(_mm_store_ps1);
     }
 
     #[simd_test(enable = "sse")]
@@ -3364,6 +3316,24 @@ mod tests {
         assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]);
     }
 
+    #[simd_test(enable = "sse")]
+    fn test_mm_undefined_ps() {
+        // _mm_undefined_ps returns a vector with indeterminate elements,
+        // so we can only verify it doesn't crash.
+        let _r = _mm_undefined_ps();
+    }
+
+    #[simd_test(enable = "sse")]
+    fn test_mm_prefetch() {
+        // Prefetch only affects cache behavior, not program correctness,
+        // so we can only verify it doesn't crash for each hint strategy.
+        let data = 42.0f32;
+        _mm_prefetch::<_MM_HINT_T0>(ptr::addr_of!(data) as *const i8);
+        _mm_prefetch::<_MM_HINT_T1>(ptr::addr_of!(data) as *const i8);
+        _mm_prefetch::<_MM_HINT_T2>(ptr::addr_of!(data) as *const i8);
+        _mm_prefetch::<_MM_HINT_NTA>(ptr::addr_of!(data) as *const i8);
+    }
+
     #[simd_test(enable = "sse")]
     const fn test_mm_move_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 2ac05e28cb..85f718038e 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -209,12 +209,9 @@ fn verify_all_signatures() {
                 "_rdseed16_step",
                 "_rdseed32_step",
                 "_rdseed64_step",
-                // Prefetch
-                "_mm_prefetch",
                 // CMPXCHG
                 "cmpxchg16b",
-                // Undefined
-                "_mm_undefined_ps",
+                // Undefined,
                 "_mm_undefined_pd",
                 "_mm_undefined_si128",
                 "_mm_undefined_ph",
@@ -250,8 +247,6 @@ fn verify_all_signatures() {
                 "_mm_cvtt_ss2si",
                 "_mm_cvt_si2ss",
                 "_mm_set_ps1",
-                "_mm_load_ps1",
-                "_mm_store_ps1",
                 "_mm_bslli_si128",
                 "_mm_bsrli_si128",
                 "_bextr2_u32",

From b5b01c0ff183fa2698c5d01f8fb507e69e95b140 Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Thu, 26 Feb 2026 16:27:41 +0000
Subject: [PATCH 183/326] Restore deleted test_mm_store_ps

---
 crates/core_arch/src/x86/sse.rs | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 4e9a3a3cb1..6a857f22b0 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3275,6 +3275,21 @@ mod tests {
         test_mm_store1_ps_impl(_mm_store1_ps);
     }
 
+    #[simd_test(enable = "sse")]
+    const fn test_mm_store_ps() {
+        let mut vals = Memory { data: [0.0f32; 4] };
+        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+
+        // guaranteed to be aligned to 16 bytes
+        let p = vals.data.as_mut_ptr();
+
+        unsafe {
+            _mm_store_ps(p, *black_box(&a));
+        }
+
+        assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
+    }
+
     #[simd_test(enable = "sse")]
     fn test_mm_store_ps1() {
         test_mm_store1_ps_impl(_mm_store_ps1);

From 1a3e7983ab4ee2ca3ccce09409dfc9ce3f000928 Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Fri, 27 Feb 2026 18:28:23 +0000
Subject: [PATCH 184/326] Remove redundant tests for _mm_prefetch and
 _mm_undefined_ps

Already verified by assert_instr; no output to assert at runtime.
---
 crates/core_arch/src/x86/sse.rs          | 18 ------------------
 crates/stdarch-verify/tests/x86-intel.rs |  3 +++
 2 files changed, 3 insertions(+), 18 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 6a857f22b0..95666b5c3d 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3331,24 +3331,6 @@ mod tests {
         assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]);
     }
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_undefined_ps() {
-        // _mm_undefined_ps returns a vector with indeterminate elements,
-        // so we can only verify it doesn't crash.
-        let _r = _mm_undefined_ps();
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_prefetch() {
-        // Prefetch only affects cache behavior, not program correctness,
-        // so we can only verify it doesn't crash for each hint strategy.
-        let data = 42.0f32;
-        _mm_prefetch::<_MM_HINT_T0>(ptr::addr_of!(data) as *const i8);
-        _mm_prefetch::<_MM_HINT_T1>(ptr::addr_of!(data) as *const i8);
-        _mm_prefetch::<_MM_HINT_T2>(ptr::addr_of!(data) as *const i8);
-        _mm_prefetch::<_MM_HINT_NTA>(ptr::addr_of!(data) as *const i8);
-    }
-
     #[simd_test(enable = "sse")]
     const fn test_mm_move_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 85f718038e..0ee32c826b 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -211,7 +211,10 @@ fn verify_all_signatures() {
                 "_rdseed64_step",
                 // CMPXCHG
                 "cmpxchg16b",
+                //PREFETCH
+                "_mm_prefetch",
                 // Undefined,
+                "_mm_undefined_ps",
                 "_mm_undefined_pd",
                 "_mm_undefined_si128",
                 "_mm_undefined_ph",

From 3ad23c9b71f40da84595797a7130773d63880786 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 2 Mar 2026 00:32:24 +0530
Subject: [PATCH 185/326] Fix LLVM intrinsic signatures for AVX-VNNI

---
 crates/core_arch/src/x86/avx512vnni.rs | 160 ++++++++++++-------------
 1 file changed, 80 insertions(+), 80 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512vnni.rs b/crates/core_arch/src/x86/avx512vnni.rs
index 49b790b151..8cd8764f24 100644
--- a/crates/core_arch/src/x86/avx512vnni.rs
+++ b/crates/core_arch/src/x86/avx512vnni.rs
@@ -12,7 +12,7 @@ use stdarch_test::assert_instr;
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssd))]
 pub fn _mm512_dpwssd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) }
+    unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i16x32(), b.as_i16x32())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -51,7 +51,7 @@ pub fn _mm512_maskz_dpwssd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssd))]
 pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst.
@@ -62,7 +62,7 @@ pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssd))]
 pub fn _mm256_dpwssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -101,7 +101,7 @@ pub fn _mm256_maskz_dpwssd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssd))]
 pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst.
@@ -112,7 +112,7 @@ pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssd))]
 pub fn _mm_dpwssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -151,7 +151,7 @@ pub fn _mm_maskz_dpwssd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i)
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssds))]
 pub fn _mm512_dpwssds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) }
+    unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i16x32(), b.as_i16x32())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -190,7 +190,7 @@ pub fn _mm512_maskz_dpwssds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssds))]
 pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst.
@@ -201,7 +201,7 @@ pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssds))]
 pub fn _mm256_dpwssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -240,7 +240,7 @@ pub fn _mm256_maskz_dpwssds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssds))]
 pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst.
@@ -251,7 +251,7 @@ pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpwssds))]
 pub fn _mm_dpwssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -290,7 +290,7 @@ pub fn _mm_maskz_dpwssds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusd))]
 pub fn _mm512_dpbusd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) }
+    unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_u8x64(), b.as_i8x64())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -329,7 +329,7 @@ pub fn _mm512_maskz_dpbusd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusd))]
 pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst.
@@ -340,7 +340,7 @@ pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusd))]
 pub fn _mm256_dpbusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -379,7 +379,7 @@ pub fn _mm256_maskz_dpbusd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusd))]
 pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst.
@@ -390,7 +390,7 @@ pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusd))]
 pub fn _mm_dpbusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -429,7 +429,7 @@ pub fn _mm_maskz_dpbusd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i)
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusds))]
 pub fn _mm512_dpbusds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i {
-    unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) }
+    unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_u8x64(), b.as_i8x64())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -468,7 +468,7 @@ pub fn _mm512_maskz_dpbusds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusds))]
 pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst.
@@ -479,7 +479,7 @@ pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusds))]
 pub fn _mm256_dpbusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -518,7 +518,7 @@ pub fn _mm256_maskz_dpbusds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusds))]
 pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst.
@@ -529,7 +529,7 @@ pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpdpbusds))]
 pub fn _mm_dpbusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -570,7 +570,7 @@ pub fn _mm_maskz_dpbusds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i
 #[cfg_attr(test, assert_instr(vpdpbssd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i8x16(), b.as_i8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit
@@ -583,7 +583,7 @@ pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpbssd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i8x32(), b.as_i8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit
@@ -596,7 +596,7 @@ pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpbssds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i8x16(), b.as_i8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit
@@ -609,7 +609,7 @@ pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpbssds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i8x32(), b.as_i8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit
@@ -622,7 +622,7 @@ pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpbsud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i8x16(), b.as_u8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit
@@ -635,7 +635,7 @@ pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpbsud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i8x32(), b.as_u8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit
@@ -648,7 +648,7 @@ pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpbsuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i8x16(), b.as_u8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit
@@ -661,7 +661,7 @@ pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpbsuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i8x32(), b.as_u8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit
@@ -674,7 +674,7 @@ pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpbuud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_u8x16(), b.as_u8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit
@@ -687,7 +687,7 @@ pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpbuud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_u8x32(), b.as_u8x32())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit
@@ -700,7 +700,7 @@ pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpbuuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_u8x16(), b.as_u8x16())) }
 }
 
 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit
@@ -713,7 +713,7 @@ pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpbuuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_u8x32(), b.as_u8x32())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit
@@ -726,7 +726,7 @@ pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpwsud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i16x8(), b.as_u16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit
@@ -739,7 +739,7 @@ pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpwsud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i16x16(), b.as_u16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit
@@ -752,7 +752,7 @@ pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpwsuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i16x8(), b.as_u16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit
@@ -765,7 +765,7 @@ pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpwsuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i16x16(), b.as_u16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit
@@ -778,7 +778,7 @@ pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpwusd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_u16x8(), b.as_i16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit
@@ -791,7 +791,7 @@ pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpwusd))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_u16x16(), b.as_i16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit
@@ -804,7 +804,7 @@ pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpwusds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_u16x8(), b.as_i16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit
@@ -817,7 +817,7 @@ pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpwusds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_u16x16(), b.as_i16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit
@@ -830,7 +830,7 @@ pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpwuud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_u16x8(), b.as_u16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit
@@ -843,7 +843,7 @@ pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpwuud))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_u16x16(), b.as_u16x16())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit
@@ -856,7 +856,7 @@ pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
 #[cfg_attr(test, assert_instr(vpdpwuuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
-    unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
+    unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_u16x8(), b.as_u16x8())) }
 }
 
 /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit
@@ -869,98 +869,98 @@ pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
 #[cfg_attr(test, assert_instr(vpdpwuuds))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_dpwuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
-    unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
+    unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_u16x16(), b.as_u16x16())) }
 }
 
 #[allow(improper_ctypes)]
 unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.vpdpwssd.512"]
-    fn vpdpwssd(src: i32x16, a: i32x16, b: i32x16) -> i32x16;
+    fn vpdpwssd(src: i32x16, a: i16x32, b: i16x32) -> i32x16;
     #[link_name = "llvm.x86.avx512.vpdpwssd.256"]
-    fn vpdpwssd256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwssd256(src: i32x8, a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx512.vpdpwssd.128"]
-    fn vpdpwssd128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwssd128(src: i32x4, a: i16x8, b: i16x8) -> i32x4;
 
     #[link_name = "llvm.x86.avx512.vpdpwssds.512"]
-    fn vpdpwssds(src: i32x16, a: i32x16, b: i32x16) -> i32x16;
+    fn vpdpwssds(src: i32x16, a: i16x32, b: i16x32) -> i32x16;
     #[link_name = "llvm.x86.avx512.vpdpwssds.256"]
-    fn vpdpwssds256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwssds256(src: i32x8, a: i16x16, b: i16x16) -> i32x8;
     #[link_name = "llvm.x86.avx512.vpdpwssds.128"]
-    fn vpdpwssds128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwssds128(src: i32x4, a: i16x8, b: i16x8) -> i32x4;
 
     #[link_name = "llvm.x86.avx512.vpdpbusd.512"]
-    fn vpdpbusd(src: i32x16, a: i32x16, b: i32x16) -> i32x16;
+    fn vpdpbusd(src: i32x16, a: u8x64, b: i8x64) -> i32x16;
     #[link_name = "llvm.x86.avx512.vpdpbusd.256"]
-    fn vpdpbusd256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbusd256(src: i32x8, a: u8x32, b: i8x32) -> i32x8;
     #[link_name = "llvm.x86.avx512.vpdpbusd.128"]
-    fn vpdpbusd128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbusd128(src: i32x4, a: u8x16, b: i8x16) -> i32x4;
 
     #[link_name = "llvm.x86.avx512.vpdpbusds.512"]
-    fn vpdpbusds(src: i32x16, a: i32x16, b: i32x16) -> i32x16;
+    fn vpdpbusds(src: i32x16, a: u8x64, b: i8x64) -> i32x16;
     #[link_name = "llvm.x86.avx512.vpdpbusds.256"]
-    fn vpdpbusds256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbusds256(src: i32x8, a: u8x32, b: i8x32) -> i32x8;
     #[link_name = "llvm.x86.avx512.vpdpbusds.128"]
-    fn vpdpbusds128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbusds128(src: i32x4, a: u8x16, b: i8x16) -> i32x4;
 
     #[link_name = "llvm.x86.avx2.vpdpbssd.128"]
-    fn vpdpbssd_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbssd_128(src: i32x4, a: i8x16, b: i8x16) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpbssd.256"]
-    fn vpdpbssd_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbssd_256(src: i32x8, a: i8x32, b: i8x32) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpbssds.128"]
-    fn vpdpbssds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbssds_128(src: i32x4, a: i8x16, b: i8x16) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpbssds.256"]
-    fn vpdpbssds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbssds_256(src: i32x8, a: i8x32, b: i8x32) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpbsud.128"]
-    fn vpdpbsud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbsud_128(src: i32x4, a: i8x16, b: u8x16) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpbsud.256"]
-    fn vpdpbsud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbsud_256(src: i32x8, a: i8x32, b: u8x32) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpbsuds.128"]
-    fn vpdpbsuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbsuds_128(src: i32x4, a: i8x16, b: u8x16) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpbsuds.256"]
-    fn vpdpbsuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbsuds_256(src: i32x8, a: i8x32, b: u8x32) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpbuud.128"]
-    fn vpdpbuud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbuud_128(src: i32x4, a: u8x16, b: u8x16) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpbuud.256"]
-    fn vpdpbuud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbuud_256(src: i32x8, a: u8x32, b: u8x32) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpbuuds.128"]
-    fn vpdpbuuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpbuuds_128(src: i32x4, a: u8x16, b: u8x16) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpbuuds.256"]
-    fn vpdpbuuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpbuuds_256(src: i32x8, a: u8x32, b: u8x32) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpwsud.128"]
-    fn vpdpwsud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwsud_128(src: i32x4, a: i16x8, b: u16x8) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpwsud.256"]
-    fn vpdpwsud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwsud_256(src: i32x8, a: i16x16, b: u16x16) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpwsuds.128"]
-    fn vpdpwsuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwsuds_128(src: i32x4, a: i16x8, b: u16x8) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpwsuds.256"]
-    fn vpdpwsuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwsuds_256(src: i32x8, a: i16x16, b: u16x16) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpwusd.128"]
-    fn vpdpwusd_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwusd_128(src: i32x4, a: u16x8, b: i16x8) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpwusd.256"]
-    fn vpdpwusd_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwusd_256(src: i32x8, a: u16x16, b: i16x16) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpwusds.128"]
-    fn vpdpwusds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwusds_128(src: i32x4, a: u16x8, b: i16x8) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpwusds.256"]
-    fn vpdpwusds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwusds_256(src: i32x8, a: u16x16, b: i16x16) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpwuud.128"]
-    fn vpdpwuud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwuud_128(src: i32x4, a: u16x8, b: u16x8) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpwuud.256"]
-    fn vpdpwuud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwuud_256(src: i32x8, a: u16x16, b: u16x16) -> i32x8;
 
     #[link_name = "llvm.x86.avx2.vpdpwuuds.128"]
-    fn vpdpwuuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4;
+    fn vpdpwuuds_128(src: i32x4, a: u16x8, b: u16x8) -> i32x4;
     #[link_name = "llvm.x86.avx2.vpdpwuuds.256"]
-    fn vpdpwuuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8;
+    fn vpdpwuuds_256(src: i32x8, a: u16x16, b: u16x16) -> i32x8;
 }
 
 #[cfg(test)]

From 86e982f871a37b5f8a9a712876e7d37b349e214a Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 5 Mar 2026 00:43:31 +0530
Subject: [PATCH 186/326] Correct stability attribute for avx512bw intrinsics

---
 crates/core_arch/src/x86/avx512bw.rs | 30 ++++++++++++++--------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs
index b41f8576cf..659d6c3be8 100644
--- a/crates/core_arch/src/x86/avx512bw.rs
+++ b/crates/core_arch/src/x86/avx512bw.rs
@@ -11753,7 +11753,7 @@ pub const fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
         simd_cast::<_, i8x32>(simd_imax(
@@ -11771,7 +11771,7 @@ pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
     unsafe {
         simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), src.as_i8x32()).as_m256i()
@@ -11785,7 +11785,7 @@ pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
     unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), i8x32::ZERO).as_m256i() }
 }
@@ -11797,7 +11797,7 @@ pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
     unsafe {
         simd_cast::<_, i8x16>(simd_imax(
@@ -11815,7 +11815,7 @@ pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
     unsafe {
         simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), src.as_i8x16()).as_m128i()
@@ -11829,7 +11829,7 @@ pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
     unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), i8x16::ZERO).as_m128i() }
 }
@@ -11874,7 +11874,7 @@ pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
     unsafe {
         simd_cast::<_, u8x32>(simd_imin(a.as_u16x32(), u16x32::splat(u8::MAX as _))).as_m256i()
@@ -11888,7 +11888,7 @@ pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
     unsafe {
         simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), src.as_u8x32()).as_m256i()
@@ -11902,7 +11902,7 @@ pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i)
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
     unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), u8x32::ZERO).as_m256i() }
 }
@@ -11914,7 +11914,7 @@ pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
     unsafe {
         simd_cast::<_, u8x16>(simd_imin(a.as_u16x16(), u16x16::splat(u8::MAX as _))).as_m128i()
@@ -11928,7 +11928,7 @@ pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
     unsafe {
         simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), src.as_u8x16()).as_m128i()
@@ -11942,7 +11942,7 @@ pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i)
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovuswb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
     unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), u8x16::ZERO).as_m128i() }
 }
@@ -12678,7 +12678,7 @@ pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a:
 #[target_feature(enable = "avx512bw")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
     let result = _mm512_cvtepi16_epi8(a).as_i8x32();
     let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO);
@@ -12692,7 +12692,7 @@ pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mma
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
     let result = _mm256_cvtepi16_epi8(a).as_i8x16();
     let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO);
@@ -12706,7 +12706,7 @@ pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mma
 #[target_feature(enable = "avx512bw,avx512vl")]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpmovwb))]
-#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
     let result: i8x8 = simd_shuffle!(
         _mm_cvtepi16_epi8(a).as_i8x16(),

From 78891f7d23e7091e63d1ce9597805d7534fff416 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 2 Mar 2026 00:27:37 +0530
Subject: [PATCH 187/326] Add immediate AMX intrinsics

---
 crates/core_arch/src/x86_64/amx.rs | 181 +++++++++++++++++++++++++++++
 1 file changed, 181 insertions(+)

diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index 4e20e014cf..03bbe3e449 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -398,6 +398,22 @@ pub unsafe fn _tile_cvtrowd2ps<const TILE: i32>(row: u32) -> __m512 {
     tcvtrowd2ps(TILE as i8, row).as_m512()
 }
 
+/// Moves a row from a tile register to a zmm register, converting the packed 32-bit signed integer
+/// elements to packed single-precision (32-bit) floating-point elements.
+#[inline]
+#[rustc_legacy_const_generics(0, 1)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowd2ps, TILE = 0, ROW = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowd2psi<const TILE: i32, const ROW: i32>() -> __m512 {
+    static_assert_uimm_bits!(TILE, 3);
+    static_assert_uimm_bits!(ROW, 6);
+    tcvtrowd2psi(TILE as i8, ROW as u32).as_m512()
+}
+
 /// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
 /// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting
 /// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector.
@@ -414,6 +430,23 @@ pub unsafe fn _tile_cvtrowps2phh<const TILE: i32>(row: u32) -> __m512h {
     tcvtrowps2phh(TILE as i8, row).as_m512h()
 }
 
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0, 1)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2phh, TILE = 0, ROW = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2phhi<const TILE: i32, const ROW: i32>() -> __m512h {
+    static_assert_uimm_bits!(TILE, 3);
+    static_assert_uimm_bits!(ROW, 6);
+    tcvtrowps2phhi(TILE as i8, ROW as u32).as_m512h()
+}
+
 /// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
 /// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting
 /// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector.
@@ -430,6 +463,23 @@ pub unsafe fn _tile_cvtrowps2phl<const TILE: i32>(row: u32) -> __m512h {
     tcvtrowps2phl(TILE as i8, row).as_m512h()
 }
 
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0, 1)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2phl, TILE = 0, ROW = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2phli<const TILE: i32, const ROW: i32>() -> __m512h {
+    static_assert_uimm_bits!(TILE, 3);
+    static_assert_uimm_bits!(ROW, 6);
+    tcvtrowps2phli(TILE as i8, ROW as u32).as_m512h()
+}
+
 /// Moves one row of tile data into a zmm vector register
 #[inline]
 #[rustc_legacy_const_generics(0)]
@@ -444,6 +494,21 @@ pub unsafe fn _tile_movrow<const TILE: i32>(row: u32) -> __m512i {
     tilemovrow(TILE as i8, row).as_m512i()
 }
 
+/// Moves one row of tile data into a zmm vector register
+#[inline]
+#[rustc_legacy_const_generics(0, 1)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tilemovrow, TILE = 0, ROW = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_movrowi<const TILE: i32, const ROW: i32>() -> __m512i {
+    static_assert_uimm_bits!(TILE, 3);
+    static_assert_uimm_bits!(ROW, 6);
+    tilemovrowi(TILE as i8, ROW as u32).as_m512i()
+}
+
 #[allow(improper_ctypes)]
 unsafe extern "C" {
     #[link_name = "llvm.x86.ldtilecfg"]
@@ -492,12 +557,20 @@ unsafe extern "C" {
     fn tmmultf32ps(dst: i8, a: i8, b: i8);
     #[link_name = "llvm.x86.tcvtrowd2ps"]
     fn tcvtrowd2ps(tile: i8, row: u32) -> f32x16;
+    #[link_name = "llvm.x86.tcvtrowd2psi"]
+    fn tcvtrowd2psi(tile: i8, row: u32) -> f32x16;
     #[link_name = "llvm.x86.tcvtrowps2phh"]
     fn tcvtrowps2phh(tile: i8, row: u32) -> f16x32;
+    #[link_name = "llvm.x86.tcvtrowps2phhi"]
+    fn tcvtrowps2phhi(tile: i8, row: u32) -> f16x32;
     #[link_name = "llvm.x86.tcvtrowps2phl"]
     fn tcvtrowps2phl(tile: i8, row: u32) -> f16x32;
+    #[link_name = "llvm.x86.tcvtrowps2phli"]
+    fn tcvtrowps2phli(tile: i8, row: u32) -> f16x32;
     #[link_name = "llvm.x86.tilemovrow"]
     fn tilemovrow(tile: i8, row: u32) -> i32x16;
+    #[link_name = "llvm.x86.tilemovrowi"]
+    fn tilemovrowi(tile: i8, row: u32) -> i32x16;
 }
 
 #[cfg(test)]
@@ -1032,6 +1105,50 @@ mod tests {
         }
     }
 
+    macro_rules! wrap_imm4 {
+        ($name:ident :: <$TILE:literal>, $row:expr) => {
+            match $row {
+                0 => $name::<$TILE, 0>(),
+                1 => $name::<$TILE, 1>(),
+                2 => $name::<$TILE, 2>(),
+                3 => $name::<$TILE, 3>(),
+                4 => $name::<$TILE, 4>(),
+                5 => $name::<$TILE, 5>(),
+                6 => $name::<$TILE, 6>(),
+                7 => $name::<$TILE, 7>(),
+                8 => $name::<$TILE, 8>(),
+                9 => $name::<$TILE, 9>(),
+                10 => $name::<$TILE, 10>(),
+                11 => $name::<$TILE, 11>(),
+                12 => $name::<$TILE, 12>(),
+                13 => $name::<$TILE, 13>(),
+                14 => $name::<$TILE, 14>(),
+                15 => $name::<$TILE, 15>(),
+                _ => panic!("row index out of range"),
+            }
+        };
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_movrowi() {
+        unsafe {
+            _init_amx();
+            let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+
+            for i in 0..16 {
+                let row = wrap_imm4!(_tile_movrowi::<0>, i);
+                assert_eq!(*row.as_u8x64().as_array(), [i as _; _]);
+            }
+        }
+    }
+
     #[simd_test(enable = "amx-avx512,avx10.2")]
     fn test_tile_cvtrowd2ps() {
         unsafe {
@@ -1051,6 +1168,26 @@ mod tests {
         }
     }
 
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowd2psi() {
+        unsafe {
+            _init_amx();
+            let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+
+            for i in 0..16 {
+                let row = wrap_imm4!(_tile_cvtrowd2psi::<0>, i);
+                assert_eq!(*row.as_f32x16().as_array(), [i as _; _]);
+            }
+        }
+    }
+
     #[simd_test(enable = "amx-avx512,avx10.2")]
     fn test_tile_cvtrowps2phh() {
         unsafe {
@@ -1073,6 +1210,28 @@ mod tests {
         }
     }
 
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2phhi() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = wrap_imm4!(_tile_cvtrowps2phhi::<0>, i);
+                assert_eq!(
+                    *row.as_f16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ })
+                );
+            }
+        }
+    }
+
     #[simd_test(enable = "amx-avx512,avx10.2")]
     fn test_tile_cvtrowps2phl() {
         unsafe {
@@ -1095,6 +1254,28 @@ mod tests {
         }
     }
 
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2phli() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = wrap_imm4!(_tile_cvtrowps2phli::<0>, i);
+                assert_eq!(
+                    *row.as_f16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 })
+                );
+            }
+        }
+    }
+
     #[simd_test(enable = "amx-tf32")]
     fn test_tile_mmultf32ps() {
         unsafe {

From 429e0731a05a33295b14b7e9b1dc70e353b535f3 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 5 Mar 2026 11:32:59 +0530
Subject: [PATCH 188/326] Add movrs intrinsics

---
 crates/core_arch/src/lib.rs              |  3 +-
 crates/core_arch/src/x86/mod.rs          |  4 +
 crates/core_arch/src/x86/movrs.rs        | 23 ++++++
 crates/core_arch/src/x86_64/mod.rs       |  4 +
 crates/core_arch/src/x86_64/movrs.rs     | 94 ++++++++++++++++++++++++
 crates/stdarch-verify/tests/x86-intel.rs |  3 +-
 6 files changed, 129 insertions(+), 2 deletions(-)
 create mode 100644 crates/core_arch/src/x86/movrs.rs
 create mode 100644 crates/core_arch/src/x86_64/movrs.rs

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 8a1bead7c4..9255994e5e 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -39,7 +39,8 @@
     const_trait_impl,
     const_cmp,
     const_eval_select,
-    maybe_uninit_as_bytes
+    maybe_uninit_as_bytes,
+    movrs_target_feature
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]
diff --git a/crates/core_arch/src/x86/mod.rs b/crates/core_arch/src/x86/mod.rs
index 9396507f08..68a963f65b 100644
--- a/crates/core_arch/src/x86/mod.rs
+++ b/crates/core_arch/src/x86/mod.rs
@@ -774,3 +774,7 @@ pub use self::avx512fp16::*;
 mod kl;
 #[stable(feature = "keylocker_x86", since = "1.89.0")]
 pub use self::kl::*;
+
+mod movrs;
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub use self::movrs::*;
diff --git a/crates/core_arch/src/x86/movrs.rs b/crates/core_arch/src/x86/movrs.rs
new file mode 100644
index 0000000000..d5f4d146c4
--- /dev/null
+++ b/crates/core_arch/src/x86/movrs.rs
@@ -0,0 +1,23 @@
+//! Read-shared move intrinsics
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.x86.prefetchrs"]
+    fn prefetchrs(p: *const u8);
+}
+
+/// Prefetches the cache line that contains address `p`, with an indication that the source memory
+/// location is likely to become read-shared by multiple processors, i.e., read in the future by at
+/// least one other processor before it is written, assuming it is ever written in the future.
+///
+/// Note: this intrinsic is safe to use even though it takes a raw pointer argument. In general, this
+/// cannot change the behavior of the program, including not trapping on invalid pointers.
+#[inline]
+#[target_feature(enable = "movrs")]
+#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(prefetchrst2))]
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub fn _m_prefetchrs(p: *const u8) {
+    unsafe { prefetchrs(p) }
+}
diff --git a/crates/core_arch/src/x86_64/mod.rs b/crates/core_arch/src/x86_64/mod.rs
index 9caab44e46..46384176e0 100644
--- a/crates/core_arch/src/x86_64/mod.rs
+++ b/crates/core_arch/src/x86_64/mod.rs
@@ -81,3 +81,7 @@ pub use self::avx512fp16::*;
 mod amx;
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
 pub use self::amx::*;
+
+mod movrs;
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub use self::movrs::*;
diff --git a/crates/core_arch/src/x86_64/movrs.rs b/crates/core_arch/src/x86_64/movrs.rs
new file mode 100644
index 0000000000..fc669bbb1c
--- /dev/null
+++ b/crates/core_arch/src/x86_64/movrs.rs
@@ -0,0 +1,94 @@
+//! Read-shared Move instructions
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.x86.movrsqi"]
+    fn movrsqi(src: *const i8) -> i8;
+    #[link_name = "llvm.x86.movrshi"]
+    fn movrshi(src: *const i16) -> i16;
+    #[link_name = "llvm.x86.movrssi"]
+    fn movrssi(src: *const i32) -> i32;
+    #[link_name = "llvm.x86.movrsdi"]
+    fn movrsdi(src: *const i64) -> i64;
+}
+
+/// Moves a byte from the source to the destination, with an indication that the source memory
+/// location is likely to become read-shared by multiple processors, i.e., read in the future by at
+/// least one other processor before it is written, assuming it is ever written in the future.
+#[inline]
+#[target_feature(enable = "movrs")]
+#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))]
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub unsafe fn _movrs_i8(src: *const i8) -> i8 {
+    movrsqi(src)
+}
+
+/// Moves a 16-bit word from the source to the destination, with an indication that the source memory
+/// location is likely to become read-shared by multiple processors, i.e., read in the future by at
+/// least one other processor before it is written, assuming it is ever written in the future.
+#[inline]
+#[target_feature(enable = "movrs")]
+#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))]
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub unsafe fn _movrs_i16(src: *const i16) -> i16 {
+    movrshi(src)
+}
+
+/// Moves a 32-bit doubleword from the source to the destination, with an indication that the source
+/// memory location is likely to become read-shared by multiple processors, i.e., read in the future
+/// by at least one other processor before it is written, assuming it is ever written in the future.
+#[inline]
+#[target_feature(enable = "movrs")]
+#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))]
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub unsafe fn _movrs_i32(src: *const i32) -> i32 {
+    movrssi(src)
+}
+
+/// Moves a 64-bit quadword from the source to the destination, with an indication that the source
+/// memory location is likely to become read-shared by multiple processors, i.e., read in the future
+/// by at least one other processor before it is written, assuming it is ever written in the future.
+#[inline]
+#[target_feature(enable = "movrs")]
+#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))]
+#[unstable(feature = "movrs_target_feature", issue = "137976")]
+pub unsafe fn _movrs_i64(src: *const i64) -> i64 {
+    movrsdi(src)
+}
+
+#[cfg(test)]
+mod tests {
+    use stdarch_test::simd_test;
+
+    use super::*;
+
+    #[simd_test(enable = "movrs")]
+    fn test_movrs_i8() {
+        let x: i8 = 42;
+        let y = unsafe { _movrs_i8(&x) };
+        assert_eq!(x, y);
+    }
+
+    #[simd_test(enable = "movrs")]
+    fn test_movrs_i16() {
+        let x: i16 = 42;
+        let y = unsafe { _movrs_i16(&x) };
+        assert_eq!(x, y);
+    }
+
+    #[simd_test(enable = "movrs")]
+    fn test_movrs_i32() {
+        let x: i32 = 42;
+        let y = unsafe { _movrs_i32(&x) };
+        assert_eq!(x, y);
+    }
+
+    #[simd_test(enable = "movrs")]
+    fn test_movrs_i64() {
+        let x: i64 = 42;
+        let y = unsafe { _movrs_i64(&x) };
+        assert_eq!(x, y);
+    }
+}
diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 2ac05e28cb..7fc47be42e 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -211,6 +211,7 @@ fn verify_all_signatures() {
                 "_rdseed64_step",
                 // Prefetch
                 "_mm_prefetch",
+                "_m_prefetchrs",
                 // CMPXCHG
                 "cmpxchg16b",
                 // Undefined
@@ -305,7 +306,7 @@ fn verify_all_signatures() {
             }
 
             // FIXME: these have not been added to Intrinsics Guide yet
-            if ["amx-avx512", "amx-fp8", "amx-movrs", "amx-tf32"]
+            if ["amx-avx512", "amx-fp8", "amx-movrs", "amx-tf32", "movrs"]
                 .iter()
                 .any(|f| feature.contains(f))
             {

From 3d9eaafc317db477f274e48861ec244d837df181 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Fri, 6 Mar 2026 13:15:28 +0100
Subject: [PATCH 189/326] gate use of `wasm_target_feature` on wasm target arch

---
 examples/hex.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/examples/hex.rs b/examples/hex.rs
index 621f55bc09..21827b375a 100644
--- a/examples/hex.rs
+++ b/examples/hex.rs
@@ -13,7 +13,6 @@
 //! and you should see `746573740a` get printed out.
 
 #![allow(internal_features)]
-#![feature(wasm_target_feature)]
 #![cfg_attr(test, feature(test))]
 #![cfg_attr(
     any(target_arch = "x86", target_arch = "x86_64"),

From 6ff8b9b94ee7c6935fb8598a61d8a6d81b094bda Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Fri, 6 Mar 2026 21:26:59 +0100
Subject: [PATCH 190/326] add ACLE random number generation intrinsics

---
 crates/core_arch/src/aarch64/mod.rs  |  4 ++
 crates/core_arch/src/aarch64/rand.rs | 69 ++++++++++++++++++++++++++++
 crates/stdarch-verify/tests/arm.rs   |  1 +
 3 files changed, 74 insertions(+)
 create mode 100644 crates/core_arch/src/aarch64/rand.rs

diff --git a/crates/core_arch/src/aarch64/mod.rs b/crates/core_arch/src/aarch64/mod.rs
index b48bdac57e..d7295659c3 100644
--- a/crates/core_arch/src/aarch64/mod.rs
+++ b/crates/core_arch/src/aarch64/mod.rs
@@ -17,6 +17,10 @@ mod mte;
 #[unstable(feature = "stdarch_aarch64_mte", issue = "129010")]
 pub use self::mte::*;
 
+mod rand;
+#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")]
+pub use self::rand::*;
+
 mod neon;
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub use self::neon::*;
diff --git a/crates/core_arch/src/aarch64/rand.rs b/crates/core_arch/src/aarch64/rand.rs
new file mode 100644
index 0000000000..5492fd0144
--- /dev/null
+++ b/crates/core_arch/src/aarch64/rand.rs
@@ -0,0 +1,69 @@
+//! AArch64 Random Number intrinsics
+//!
+//! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#random-number-generation-intrinsics)
+
+unsafe extern "unadjusted" {
+    #[cfg_attr(
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        link_name = "llvm.aarch64.rndr"
+    )]
+    fn rndr_() -> Tuple;
+
+    #[cfg_attr(
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        link_name = "llvm.aarch64.rndrrs"
+    )]
+    fn rndrrs_() -> Tuple;
+}
+
+#[repr(C)]
+struct Tuple {
+    bits: u64,
+    status: bool,
+}
+
+/// Stores a 64-bit random number into the object pointed to by the argument and returns
+/// zero. If the implementation could not generate a random number within a reasonable
+/// period of time the object pointed to by the input is set to zero and a non-zero value
+/// is returned.
+#[inline]
+#[target_feature(enable = "rand")]
+#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")]
+pub unsafe fn __rndr(value: *mut u64) -> i32 {
+    let Tuple { bits, status } = rndr_();
+    unsafe { *value = bits };
+    status as i32
+}
+
+/// Reseeds the random number generator. After that stores a 64-bit random number into
+/// the object pointed to by the argument and returns zero. If the implementation could
+/// not generate a random number within a reasonable period of time the object pointed
+/// to by the input is set to zero and a non-zero value is returned.
+#[inline]
+#[target_feature(enable = "rand")]
+#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")]
+pub unsafe fn __rndrrs(value: *mut u64) -> i32 {
+    let Tuple { bits, status } = rndrrs_();
+    unsafe { *value = bits };
+    status as i32
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+    use stdarch_test::assert_instr;
+
+    #[cfg_attr(test, assert_instr(mrs))]
+    #[allow(dead_code)]
+    #[target_feature(enable = "rand")]
+    unsafe fn test_rndr(value: &mut u64) -> i32 {
+        __rndr(value)
+    }
+
+    #[cfg_attr(test, assert_instr(mrs))]
+    #[allow(dead_code)]
+    #[target_feature(enable = "rand")]
+    unsafe fn test_rndrrs(value: &mut u64) -> i32 {
+        __rndrrs(value)
+    }
+}
diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs
index 86897908e0..3ef9ce2a38 100644
--- a/crates/stdarch-verify/tests/arm.rs
+++ b/crates/stdarch-verify/tests/arm.rs
@@ -445,6 +445,7 @@ fn verify_all_signatures() {
                     && !rust.file.ends_with("v7.rs\"")
                     && !rust.file.ends_with("v8.rs\"")
                     && !rust.file.ends_with("mte.rs\"")
+                    && !rust.file.ends_with("rand.rs\"")
                     && !rust.file.ends_with("ex.rs\"")
                     && !skip_intrinsic_verify.contains(&rust.name)
                 {

From 2fdb5a652c61a5c256c4439688559ea5bc5ff102 Mon Sep 17 00:00:00 2001
From: Josh Stone <jistone@redhat.com>
Date: Mon, 2 Mar 2026 15:00:53 -0800
Subject: [PATCH 191/326] Replace version placeholders with 1.95.0

(cherry picked from commit bad24ccbeceb787d2ad62847196315576a0d4fc7)
---
 crates/core_arch/src/aarch64/neon/generated.rs    | 2 +-
 crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index de64839661..490f04020e 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -49,7 +49,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 #[inline(always)]
 #[target_feature(enable = "jsconv")]
 #[cfg_attr(test, assert_instr(fjcvtzs))]
-#[stable(feature = "stdarch_aarch64_jscvt", since = "CURRENT_RUSTC_VERSION")]
+#[stable(feature = "stdarch_aarch64_jscvt", since = "1.95.0")]
 pub fn __jcvt(a: f64) -> i32 {
     unsafe extern "unadjusted" {
         #[cfg_attr(
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 8574aacee6..4df899a202 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -64,7 +64,7 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut
   FnCall: [unstable, ['feature = "stdarch_neon_feat_lut"', 'issue = "138050"']]
 
 aarch64-stable-jscvt: &aarch64-stable-jscvt
-  FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']]
+  FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "1.95.0"']]
 
 # #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3

From 98f93f47ce7c94a79e5b79ee6899806dbb5f6158 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 9 Mar 2026 04:42:45 +0000
Subject: [PATCH 192/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to eda4fc7733ee89e484d7120cafbd80dcb2fce66e.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index b22c6c3869..db9492636f 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-139651428df86cf88443295542c12ea617cbb587
+eda4fc7733ee89e484d7120cafbd80dcb2fce66e

From ff2cbd13cc80c5c539c5727595ad7a7a9930e0ec Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Tue, 10 Mar 2026 12:19:33 +0100
Subject: [PATCH 193/326] Revert "Merge pull request #1871 from
 folkertdev/aarch64-float-min-max"

This reverts commit 6a8a764262df5e65c06bc5d9180046a636a53ce9, reversing
changes made to a37563b5f8cec0c873864b786c33d00386189916.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 360 ++++++++++++++++--
 .../src/arm_shared/neon/generated.rs          |  80 +++-
 .../spec/neon/aarch64.spec.yml                |  85 ++++-
 .../spec/neon/arm_shared.spec.yml             |  32 +-
 4 files changed, 491 insertions(+), 66 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index de64839661..c4968a68c4 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -13532,7 +13532,14 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
 pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
-    unsafe { simd_fmax(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.v1f64"
+        )]
+        fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
+    }
+    unsafe { _vmaxnm_f64(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"]
@@ -13541,7 +13548,14 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
 pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
-    unsafe { simd_fmax(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.v2f64"
+        )]
+        fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
+    }
+    unsafe { _vmaxnmq_f64(a, b) }
 }
 #[doc = "Floating-point Maximum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"]
@@ -13551,7 +13565,14 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnm))]
 pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
-    f16::max(a, b)
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.f16"
+        )]
+        fn _vmaxnmh_f16(a: f16, b: f16) -> f16;
+    }
+    unsafe { _vmaxnmh_f16(a, b) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"]
@@ -13561,7 +13582,14 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
 pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnmv.f16.v4f16"
+        )]
+        fn _vmaxnmv_f16(a: float16x4_t) -> f16;
+    }
+    unsafe { _vmaxnmv_f16(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"]
@@ -13571,7 +13599,14 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
 pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnmv.f16.v8f16"
+        )]
+        fn _vmaxnmvq_f16(a: float16x8_t) -> f16;
+    }
+    unsafe { _vmaxnmvq_f16(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"]
@@ -13580,7 +13615,14 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32"
+        )]
+        fn _vmaxnmv_f32(a: float32x2_t) -> f32;
+    }
+    unsafe { _vmaxnmv_f32(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"]
@@ -13589,7 +13631,14 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64"
+        )]
+        fn _vmaxnmvq_f64(a: float64x2_t) -> f64;
+    }
+    unsafe { _vmaxnmvq_f64(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"]
@@ -13598,7 +13647,14 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
 pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32"
+        )]
+        fn _vmaxnmvq_f32(a: float32x4_t) -> f32;
+    }
+    unsafe { _vmaxnmvq_f32(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"]
@@ -13689,7 +13745,14 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxv_s8(a: int8x8_t) -> i8 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.smaxv.i8.v8i8"
+        )]
+        fn _vmaxv_s8(a: int8x8_t) -> i8;
+    }
+    unsafe { _vmaxv_s8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
@@ -13698,7 +13761,14 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.smaxv.i8.v16i8"
+        )]
+        fn _vmaxvq_s8(a: int8x16_t) -> i8;
+    }
+    unsafe { _vmaxvq_s8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
@@ -13707,7 +13777,14 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxv_s16(a: int16x4_t) -> i16 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.smaxv.i16.v4i16"
+        )]
+        fn _vmaxv_s16(a: int16x4_t) -> i16;
+    }
+    unsafe { _vmaxv_s16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
@@ -13716,7 +13793,14 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.smaxv.i16.v8i16"
+        )]
+        fn _vmaxvq_s16(a: int16x8_t) -> i16;
+    }
+    unsafe { _vmaxvq_s16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
@@ -13725,7 +13809,14 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
 pub fn vmaxv_s32(a: int32x2_t) -> i32 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.smaxv.i32.v2i32"
+        )]
+        fn _vmaxv_s32(a: int32x2_t) -> i32;
+    }
+    unsafe { _vmaxv_s32(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
@@ -13734,7 +13825,14 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.smaxv.i32.v4i32"
+        )]
+        fn _vmaxvq_s32(a: int32x4_t) -> i32;
+    }
+    unsafe { _vmaxvq_s32(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
@@ -13743,7 +13841,14 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.umaxv.i8.v8i8"
+        )]
+        fn _vmaxv_u8(a: uint8x8_t) -> u8;
+    }
+    unsafe { _vmaxv_u8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
@@ -13752,7 +13857,14 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.umaxv.i8.v16i8"
+        )]
+        fn _vmaxvq_u8(a: uint8x16_t) -> u8;
+    }
+    unsafe { _vmaxvq_u8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
@@ -13761,7 +13873,14 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.umaxv.i16.v4i16"
+        )]
+        fn _vmaxv_u16(a: uint16x4_t) -> u16;
+    }
+    unsafe { _vmaxv_u16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
@@ -13770,7 +13889,14 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.umaxv.i16.v8i16"
+        )]
+        fn _vmaxvq_u16(a: uint16x8_t) -> u16;
+    }
+    unsafe { _vmaxvq_u16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
@@ -13779,7 +13905,14 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
 pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.umaxv.i32.v2i32"
+        )]
+        fn _vmaxv_u32(a: uint32x2_t) -> u32;
+    }
+    unsafe { _vmaxv_u32(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
@@ -13788,7 +13921,14 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
-    unsafe { simd_reduce_max(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.umaxv.i32.v4i32"
+        )]
+        fn _vmaxvq_u32(a: uint32x4_t) -> u32;
+    }
+    unsafe { _vmaxvq_u32(a) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
@@ -13846,7 +13986,14 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
 pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
-    unsafe { simd_fmin(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.v1f64"
+        )]
+        fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
+    }
+    unsafe { _vminnm_f64(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"]
@@ -13855,7 +14002,14 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
 pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
-    unsafe { simd_fmin(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.v2f64"
+        )]
+        fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
+    }
+    unsafe { _vminnmq_f64(a, b) }
 }
 #[doc = "Floating-point Minimum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"]
@@ -13865,7 +14019,14 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnm))]
 pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
-    f16::min(a, b)
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.f16"
+        )]
+        fn _vminnmh_f16(a: f16, b: f16) -> f16;
+    }
+    unsafe { _vminnmh_f16(a, b) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"]
@@ -13875,7 +14036,14 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnmv))]
 pub fn vminnmv_f16(a: float16x4_t) -> f16 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnmv.f16.v4f16"
+        )]
+        fn _vminnmv_f16(a: float16x4_t) -> f16;
+    }
+    unsafe { _vminnmv_f16(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"]
@@ -13885,7 +14053,14 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fminnmv))]
 pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnmv.f16.v8f16"
+        )]
+        fn _vminnmvq_f16(a: float16x8_t) -> f16;
+    }
+    unsafe { _vminnmvq_f16(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"]
@@ -13894,7 +14069,14 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vminnmv_f32(a: float32x2_t) -> f32 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32"
+        )]
+        fn _vminnmv_f32(a: float32x2_t) -> f32;
+    }
+    unsafe { _vminnmv_f32(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"]
@@ -13903,7 +14085,14 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 {
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64"
+        )]
+        fn _vminnmvq_f64(a: float64x2_t) -> f64;
+    }
+    unsafe { _vminnmvq_f64(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"]
@@ -13912,7 +14101,14 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
 #[cfg_attr(test, assert_instr(fminnmv))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vminnmvq_f32(a: float32x4_t) -> f32 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32"
+        )]
+        fn _vminnmvq_f32(a: float32x4_t) -> f32;
+    }
+    unsafe { _vminnmvq_f32(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"]
@@ -14003,7 +14199,14 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminv_s8(a: int8x8_t) -> i8 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.sminv.i8.v8i8"
+        )]
+        fn _vminv_s8(a: int8x8_t) -> i8;
+    }
+    unsafe { _vminv_s8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
@@ -14012,7 +14215,14 @@ pub fn vminv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s8(a: int8x16_t) -> i8 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.sminv.i8.v16i8"
+        )]
+        fn _vminvq_s8(a: int8x16_t) -> i8;
+    }
+    unsafe { _vminvq_s8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
@@ -14021,7 +14231,14 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminv_s16(a: int16x4_t) -> i16 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.sminv.i16.v4i16"
+        )]
+        fn _vminv_s16(a: int16x4_t) -> i16;
+    }
+    unsafe { _vminv_s16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
@@ -14030,7 +14247,14 @@ pub fn vminv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s16(a: int16x8_t) -> i16 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.sminv.i16.v8i16"
+        )]
+        fn _vminvq_s16(a: int16x8_t) -> i16;
+    }
+    unsafe { _vminvq_s16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
@@ -14039,7 +14263,14 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
 pub fn vminv_s32(a: int32x2_t) -> i32 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.sminv.i32.v2i32"
+        )]
+        fn _vminv_s32(a: int32x2_t) -> i32;
+    }
+    unsafe { _vminv_s32(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
@@ -14048,7 +14279,14 @@ pub fn vminv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s32(a: int32x4_t) -> i32 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.sminv.i32.v4i32"
+        )]
+        fn _vminvq_s32(a: int32x4_t) -> i32;
+    }
+    unsafe { _vminvq_s32(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
@@ -14057,7 +14295,14 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminv_u8(a: uint8x8_t) -> u8 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.uminv.i8.v8i8"
+        )]
+        fn _vminv_u8(a: uint8x8_t) -> u8;
+    }
+    unsafe { _vminv_u8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
@@ -14066,7 +14311,14 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u8(a: uint8x16_t) -> u8 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.uminv.i8.v16i8"
+        )]
+        fn _vminvq_u8(a: uint8x16_t) -> u8;
+    }
+    unsafe { _vminvq_u8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
@@ -14075,7 +14327,14 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminv_u16(a: uint16x4_t) -> u16 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.uminv.i16.v4i16"
+        )]
+        fn _vminv_u16(a: uint16x4_t) -> u16;
+    }
+    unsafe { _vminv_u16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
@@ -14084,7 +14343,14 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u16(a: uint16x8_t) -> u16 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.uminv.i16.v8i16"
+        )]
+        fn _vminvq_u16(a: uint16x8_t) -> u16;
+    }
+    unsafe { _vminvq_u16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
@@ -14093,7 +14359,14 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
 pub fn vminv_u32(a: uint32x2_t) -> u32 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.uminv.i32.v2i32"
+        )]
+        fn _vminv_u32(a: uint32x2_t) -> u32;
+    }
+    unsafe { _vminv_u32(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
@@ -14102,7 +14375,14 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u32(a: uint32x4_t) -> u32 {
-    unsafe { simd_reduce_min(a) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.uminv.i32.v4i32"
+        )]
+        fn _vminvq_u32(a: uint32x4_t) -> u32;
+    }
+    unsafe { _vminvq_u32(a) }
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index a7c33917a8..4a846e2877 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -25891,7 +25891,15 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
-    unsafe { simd_fmax(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.v4f16"
+        )]
+        fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
+    }
+    unsafe { _vmaxnm_f16(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
@@ -25913,7 +25921,15 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
-    unsafe { simd_fmax(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.v8f16"
+        )]
+        fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    }
+    unsafe { _vmaxnmq_f16(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
@@ -25934,7 +25950,15 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
-    unsafe { simd_fmax(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.v2f32"
+        )]
+        fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
+    }
+    unsafe { _vmaxnm_f32(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
@@ -25955,7 +25979,15 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
-    unsafe { simd_fmax(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fmaxnm.v4f32"
+        )]
+        fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+    }
+    unsafe { _vmaxnmq_f32(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
@@ -26383,7 +26415,15 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
-    unsafe { simd_fmin(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.v4f16"
+        )]
+        fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
+    }
+    unsafe { _vminnm_f16(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
@@ -26405,7 +26445,15 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
-    unsafe { simd_fmin(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.v8f16"
+        )]
+        fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    }
+    unsafe { _vminnmq_f16(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
@@ -26426,7 +26474,15 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
-    unsafe { simd_fmin(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.v2f32"
+        )]
+        fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
+    }
+    unsafe { _vminnm_f32(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
@@ -26447,7 +26503,15 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
-    unsafe { simd_fmin(a, b) }
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")]
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fminnm.v4f32"
+        )]
+        fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+    }
+    unsafe { _vminnmq_f32(a, b) }
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 8574aacee6..2b4282e803 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -6625,6 +6625,7 @@ intrinsics:
               arch: aarch64,arm64ec
 
 
+
   - name: "vmaxnm{neon_type.no}"
     doc: Floating-point Maximum Number (vector)
     arguments: ["a: {neon_type}", "b: {neon_type}"]
@@ -6636,7 +6637,11 @@ intrinsics:
       - float64x1_t
       - float64x2_t
     compose:
-      - FnCall: [simd_fmax, [a, b]]
+      - LLVMLink:
+          name: "fmaxnm.{neon_type}"
+          links:
+            - link: "llvm.aarch64.neon.fmaxnm.{neon_type}"
+              arch: aarch64,arm64ec
 
 
   - name: "vmaxnmh_{type}"
@@ -6652,7 +6657,11 @@ intrinsics:
     types:
       - f16
     compose:
-      - FnCall: ["f16::max", [a, b]]
+      - LLVMLink:
+          name: "vmaxh.{neon_type}"
+          links:
+            - link: "llvm.aarch64.neon.fmaxnm.{type}"
+              arch: aarch64,arm64ec
 
 
   - name: "vminnmh_{type}"
@@ -6668,7 +6677,11 @@ intrinsics:
     types:
       - f16
     compose:
-      - FnCall: ["f16::min", [a, b]]
+      - LLVMLink:
+          name: "vminh.{neon_type}"
+          links:
+            - link: "llvm.aarch64.neon.fminnm.{type}"
+              arch: aarch64,arm64ec
 
 
   - name: "vmaxnmv{neon_type[0].no}"
@@ -6682,7 +6695,11 @@ intrinsics:
       - [float32x2_t, f32]
       - [float64x2_t, f64]
     compose:
-      - FnCall: [simd_reduce_max, [a]]
+      - LLVMLink:
+          name: "fmaxnmv.{neon_type[0]}"
+          links:
+            - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vmaxnmv{neon_type[0].no}"
     doc: Floating-point maximum number across vector
@@ -6694,7 +6711,11 @@ intrinsics:
     types:
       - [float32x4_t, f32]
     compose:
-      - FnCall: [simd_reduce_max, [a]]
+      - LLVMLink:
+          name: "fmaxnmv.{neon_type[0]}"
+          links:
+            - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
 
   - name: "vmaxnmv{neon_type[0].no}"
@@ -6711,7 +6732,11 @@ intrinsics:
       - [float16x4_t, f16]
       - [float16x8_t, f16]
     compose:
-      - FnCall: [simd_reduce_max, [a]]
+      - LLVMLink:
+          name: "fmaxnmv.{neon_type[0]}"
+          links:
+            - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
 
   - name: "vminnmv{neon_type[0].no}"
@@ -6728,7 +6753,11 @@ intrinsics:
       - [float16x4_t, f16]
       - [float16x8_t, f16]
     compose:
-      - FnCall: [simd_reduce_min, [a]]
+      - LLVMLink:
+          name: "fminnmv.{neon_type[0]}"
+          links:
+            - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
 
   - name: "vmaxv{neon_type[0].no}"
@@ -6837,7 +6866,11 @@ intrinsics:
       - float64x1_t
       - float64x2_t
     compose:
-      - FnCall: [simd_fmin, [a, b]]
+      - LLVMLink:
+          name: "fminnm.{neon_type}"
+          links:
+            - link: "llvm.aarch64.neon.fminnm.{neon_type}"
+              arch: aarch64,arm64ec
 
   - name: "vminnmv{neon_type[0].no}"
     doc: "Floating-point minimum number across vector"
@@ -6851,7 +6884,11 @@ intrinsics:
       - [float32x2_t, "f32"]
       - [float64x2_t, "f64"]
     compose:
-      - FnCall: [simd_reduce_min, [a]]
+      - LLVMLink:
+          name: "vminnmv.{neon_type[0]}"
+          links:
+            - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vminnmv{neon_type[0].no}"
     doc: "Floating-point minimum number across vector"
@@ -6864,7 +6901,11 @@ intrinsics:
     types:
       - [float32x4_t, "f32"]
     compose:
-      - FnCall: [simd_reduce_min, [a]]
+      - LLVMLink:
+          name: "vminnmv.{neon_type[0]}"
+          links:
+            - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vmovl_high{neon_type[0].noq}"
     doc: Vector move
@@ -13372,7 +13413,11 @@ intrinsics:
       - [int16x8_t, i16, 'smaxv']
       - [int32x4_t, i32, 'smaxv']
     compose:
-      - FnCall: [simd_reduce_max, [a]]
+      - LLVMLink:
+          name: "vmaxv{neon_type[0].no}"
+          links:
+            - link: "llvm.aarch64.neon.smaxv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
@@ -13390,7 +13435,11 @@ intrinsics:
       - [uint16x8_t, u16, 'umaxv']
       - [uint32x4_t, u32, 'umaxv']
     compose:
-      - FnCall: [simd_reduce_max, [a]]
+      - LLVMLink:
+          name: "vmaxv{neon_type[0].no}"
+          links:
+            - link: "llvm.aarch64.neon.umaxv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
@@ -13427,7 +13476,11 @@ intrinsics:
       - [int16x8_t, i16, 'sminv']
       - [int32x4_t, i32, 'sminv']
     compose:
-      - FnCall: [simd_reduce_min, [a]]
+      - LLVMLink:
+          name: "vminv{neon_type[0].no}"
+          links:
+            - link: "llvm.aarch64.neon.sminv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vminv{neon_type[0].no}"
     doc: "Horizontal vector min."
@@ -13445,7 +13498,11 @@ intrinsics:
       - [uint16x8_t, u16, 'uminv']
       - [uint32x4_t, u32, 'uminv']
     compose:
-      - FnCall: [simd_reduce_min, [a]]
+      - LLVMLink:
+          name: "vminv{neon_type[0].no}"
+          links:
+            - link: "llvm.aarch64.neon.uminv.{type[1]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
 
   - name: "vminv{neon_type[0].no}"
     doc: "Horizontal vector min."
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 5104ae607c..56b2252c9e 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -7324,7 +7324,13 @@ intrinsics:
       - float32x2_t
       - float32x4_t
     compose:
-      - FnCall: [simd_fmax, [a, b]]
+      - LLVMLink:
+          name: "fmaxnm.{neon_type}"
+          links:
+            - link: "llvm.arm.neon.vmaxnm.{neon_type}"
+              arch: arm
+            - link: "llvm.aarch64.neon.fmaxnm.{neon_type}"
+              arch: aarch64,arm64ec
 
 
   - name: "vmaxnm{neon_type.no}"
@@ -7344,7 +7350,13 @@ intrinsics:
       - float16x4_t
       - float16x8_t
     compose:
-      - FnCall: [simd_fmax, [a, b]]
+      - LLVMLink:
+          name: "fmaxnm.{neon_type}"
+          links:
+            - link: "llvm.arm.neon.vmaxnm.{neon_type}"
+              arch: arm
+            - link: "llvm.aarch64.neon.fmaxnm.{neon_type}"
+              arch: aarch64,arm64ec
 
 
   - name: "vminnm{neon_type.no}"
@@ -7364,7 +7376,13 @@ intrinsics:
       - float16x4_t
       - float16x8_t
     compose:
-      - FnCall: [simd_fmin, [a, b]]
+      - LLVMLink:
+          name: "fminnm.{neon_type}"
+          links:
+            - link: "llvm.arm.neon.vminnm.{neon_type}"
+              arch: arm
+            - link: "llvm.aarch64.neon.fminnm.{neon_type}"
+              arch: aarch64,arm64ec
 
 
   - name: "vmin{neon_type.no}"
@@ -7477,7 +7495,13 @@ intrinsics:
       - float32x2_t
       - float32x4_t
     compose:
-      - FnCall: [simd_fmin, [a, b]]
+      - LLVMLink:
+          name: "fminnm.{neon_type}"
+          links:
+            - link: "llvm.arm.neon.vminnm.{neon_type}"
+              arch: arm
+            - link: "llvm.aarch64.neon.fminnm.{neon_type}"
+              arch: aarch64,arm64ec
 
   - name: "vpadd{neon_type.no}"
     doc: Floating-point add pairwise

From 6a716c419f1df08252cb2bc85dadfb1ea4fb0c35 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 10 Mar 2026 13:03:00 +0100
Subject: [PATCH 194/326] aarch64: use `simd_reduce_{min, max}` on integers

---
 .../core_arch/src/aarch64/neon/generated.rs   | 216 ++----------------
 .../spec/neon/aarch64.spec.yml                |  24 +-
 2 files changed, 28 insertions(+), 212 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index c4968a68c4..479a909a40 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -13745,14 +13745,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxv_s8(a: int8x8_t) -> i8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i8.v8i8"
-        )]
-        fn _vmaxv_s8(a: int8x8_t) -> i8;
-    }
-    unsafe { _vmaxv_s8(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
@@ -13761,14 +13754,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i8.v16i8"
-        )]
-        fn _vmaxvq_s8(a: int8x16_t) -> i8;
-    }
-    unsafe { _vmaxvq_s8(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
@@ -13777,14 +13763,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxv_s16(a: int16x4_t) -> i16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i16.v4i16"
-        )]
-        fn _vmaxv_s16(a: int16x4_t) -> i16;
-    }
-    unsafe { _vmaxv_s16(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
@@ -13793,14 +13772,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i16.v8i16"
-        )]
-        fn _vmaxvq_s16(a: int16x8_t) -> i16;
-    }
-    unsafe { _vmaxvq_s16(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
@@ -13809,14 +13781,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
 pub fn vmaxv_s32(a: int32x2_t) -> i32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i32.v2i32"
-        )]
-        fn _vmaxv_s32(a: int32x2_t) -> i32;
-    }
-    unsafe { _vmaxv_s32(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
@@ -13825,14 +13790,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i32.v4i32"
-        )]
-        fn _vmaxvq_s32(a: int32x4_t) -> i32;
-    }
-    unsafe { _vmaxvq_s32(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
@@ -13841,14 +13799,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i8.v8i8"
-        )]
-        fn _vmaxv_u8(a: uint8x8_t) -> u8;
-    }
-    unsafe { _vmaxv_u8(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
@@ -13857,14 +13808,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i8.v16i8"
-        )]
-        fn _vmaxvq_u8(a: uint8x16_t) -> u8;
-    }
-    unsafe { _vmaxvq_u8(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
@@ -13873,14 +13817,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i16.v4i16"
-        )]
-        fn _vmaxv_u16(a: uint16x4_t) -> u16;
-    }
-    unsafe { _vmaxv_u16(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
@@ -13889,14 +13826,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i16.v8i16"
-        )]
-        fn _vmaxvq_u16(a: uint16x8_t) -> u16;
-    }
-    unsafe { _vmaxvq_u16(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
@@ -13905,14 +13835,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
 pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i32.v2i32"
-        )]
-        fn _vmaxv_u32(a: uint32x2_t) -> u32;
-    }
-    unsafe { _vmaxv_u32(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
@@ -13921,14 +13844,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i32.v4i32"
-        )]
-        fn _vmaxvq_u32(a: uint32x4_t) -> u32;
-    }
-    unsafe { _vmaxvq_u32(a) }
+    unsafe { simd_reduce_max(a) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
@@ -14199,14 +14115,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminv_s8(a: int8x8_t) -> i8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i8.v8i8"
-        )]
-        fn _vminv_s8(a: int8x8_t) -> i8;
-    }
-    unsafe { _vminv_s8(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
@@ -14215,14 +14124,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s8(a: int8x16_t) -> i8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i8.v16i8"
-        )]
-        fn _vminvq_s8(a: int8x16_t) -> i8;
-    }
-    unsafe { _vminvq_s8(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
@@ -14231,14 +14133,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminv_s16(a: int16x4_t) -> i16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i16.v4i16"
-        )]
-        fn _vminv_s16(a: int16x4_t) -> i16;
-    }
-    unsafe { _vminv_s16(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
@@ -14247,14 +14142,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s16(a: int16x8_t) -> i16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i16.v8i16"
-        )]
-        fn _vminvq_s16(a: int16x8_t) -> i16;
-    }
-    unsafe { _vminvq_s16(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
@@ -14263,14 +14151,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
 pub fn vminv_s32(a: int32x2_t) -> i32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i32.v2i32"
-        )]
-        fn _vminv_s32(a: int32x2_t) -> i32;
-    }
-    unsafe { _vminv_s32(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
@@ -14279,14 +14160,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s32(a: int32x4_t) -> i32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i32.v4i32"
-        )]
-        fn _vminvq_s32(a: int32x4_t) -> i32;
-    }
-    unsafe { _vminvq_s32(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
@@ -14295,14 +14169,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminv_u8(a: uint8x8_t) -> u8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i8.v8i8"
-        )]
-        fn _vminv_u8(a: uint8x8_t) -> u8;
-    }
-    unsafe { _vminv_u8(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
@@ -14311,14 +14178,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u8(a: uint8x16_t) -> u8 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i8.v16i8"
-        )]
-        fn _vminvq_u8(a: uint8x16_t) -> u8;
-    }
-    unsafe { _vminvq_u8(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
@@ -14327,14 +14187,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminv_u16(a: uint16x4_t) -> u16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i16.v4i16"
-        )]
-        fn _vminv_u16(a: uint16x4_t) -> u16;
-    }
-    unsafe { _vminv_u16(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
@@ -14343,14 +14196,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u16(a: uint16x8_t) -> u16 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i16.v8i16"
-        )]
-        fn _vminvq_u16(a: uint16x8_t) -> u16;
-    }
-    unsafe { _vminvq_u16(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
@@ -14359,14 +14205,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
 pub fn vminv_u32(a: uint32x2_t) -> u32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i32.v2i32"
-        )]
-        fn _vminv_u32(a: uint32x2_t) -> u32;
-    }
-    unsafe { _vminv_u32(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
@@ -14375,14 +14214,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u32(a: uint32x4_t) -> u32 {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i32.v4i32"
-        )]
-        fn _vminvq_u32(a: uint32x4_t) -> u32;
-    }
-    unsafe { _vminvq_u32(a) }
+    unsafe { simd_reduce_min(a) }
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 2b4282e803..f6f3e029f2 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -13413,11 +13413,7 @@ intrinsics:
       - [int16x8_t, i16, 'smaxv']
       - [int32x4_t, i32, 'smaxv']
     compose:
-      - LLVMLink:
-          name: "vmaxv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.smaxv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
+      - FnCall: [simd_reduce_max, [a]]
 
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
@@ -13435,11 +13431,7 @@ intrinsics:
       - [uint16x8_t, u16, 'umaxv']
       - [uint32x4_t, u32, 'umaxv']
     compose:
-      - LLVMLink:
-          name: "vmaxv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.umaxv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
+      - FnCall: [simd_reduce_max, [a]]
 
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
@@ -13476,11 +13468,7 @@ intrinsics:
       - [int16x8_t, i16, 'sminv']
       - [int32x4_t, i32, 'sminv']
     compose:
-      - LLVMLink:
-          name: "vminv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.sminv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
+      - FnCall: [simd_reduce_min, [a]]
 
   - name: "vminv{neon_type[0].no}"
     doc: "Horizontal vector min."
@@ -13498,11 +13486,7 @@ intrinsics:
       - [uint16x8_t, u16, 'uminv']
       - [uint32x4_t, u32, 'uminv']
     compose:
-      - LLVMLink:
-          name: "vminv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.uminv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
+      - FnCall: [simd_reduce_min, [a]]
 
   - name: "vminv{neon_type[0].no}"
     doc: "Horizontal vector min."

From 6efd06e975e7dea1f5b7e1f1db5aba51237feaca Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Tue, 10 Mar 2026 17:42:37 +0100
Subject: [PATCH 195/326] s390x: use llvm.s390 intrinsics instead of
 simd_fmin/fmax

---
 crates/core_arch/src/s390x/vector.rs | 37 +++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 346cd674df..2f31eb48f8 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -335,6 +335,11 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vcfn"] fn vcfn(a: vector_signed_short, immarg: i32) -> vector_signed_short;
     #[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short;
     #[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short;
+
+    #[link_name = "llvm.s390.vfmaxsb"] fn vfmaxsb(a: vector_float, b: vector_float, mode: i32) -> vector_float;
+    #[link_name = "llvm.s390.vfmaxdb"] fn vfmaxdb(a: vector_double, b: vector_double, mode: i32) -> vector_double;
+    #[link_name = "llvm.s390.vfminsb"] fn vfminsb(a: vector_float, b: vector_float, mode: i32) -> vector_float;
+    #[link_name = "llvm.s390.vfmindb"] fn vfmindb(a: vector_double, b: vector_double, mode: i32) -> vector_double;
 }
 
 #[repr(simd)]
@@ -780,8 +785,20 @@ mod sealed {
         impl_max!(vec_vmxslg, vector_unsigned_long_long, vmxlg);
     }
 
-    test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [simd_fmax, "vector-enhancements-1" vfmaxsb ] }
-    test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [simd_fmax, "vector-enhancements-1" vfmaxdb] }
+    #[inline]
+    #[target_feature(enable = "vector")]
+    unsafe fn vfmaxsb_m0(a: vector_float, b: vector_float) -> vector_float {
+        // clang uses mode 0 for `vec_max`, so we do the same.
+        vfmaxsb(a, b, const { 0 })
+    }
+    #[inline]
+    #[target_feature(enable = "vector")]
+    unsafe fn vfmaxdb_m0(a: vector_double, b: vector_double) -> vector_double {
+        vfmaxdb(a, b, const { 0 })
+    }
+
+    test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [vfmaxsb_m0, "vector-enhancements-1" vfmaxsb ] }
+    test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [vfmaxdb_m0, "vector-enhancements-1" vfmaxdb] }
 
     impl_vec_trait!([VectorMax vec_max] vec_vfmaxsb (vector_float, vector_float) -> vector_float);
     impl_vec_trait!([VectorMax vec_max] vec_vfmaxdb (vector_double, vector_double) -> vector_double);
@@ -827,8 +844,20 @@ mod sealed {
         impl_min!(vec_vmnslg, vector_unsigned_long_long, vmnlg);
     }
 
-    test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [simd_fmin, "vector-enhancements-1" vfminsb]  }
-    test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [simd_fmin, "vector-enhancements-1" vfmindb]  }
+    #[inline]
+    #[target_feature(enable = "vector")]
+    unsafe fn vfminsb_m0(a: vector_float, b: vector_float) -> vector_float {
+        // clang uses mode 0 for `vec_min`, so we do the same.
+        vfminsb(a, b, const { 0 })
+    }
+    #[inline]
+    #[target_feature(enable = "vector")]
+    unsafe fn vfmindb_m0(a: vector_double, b: vector_double) -> vector_double {
+        vfmindb(a, b, const { 0 })
+    }
+
+    test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [vfminsb_m0, "vector-enhancements-1" vfminsb]  }
+    test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [vfmindb_m0, "vector-enhancements-1" vfmindb]  }
 
     impl_vec_trait!([VectorMin vec_min] vec_vfminsb (vector_float, vector_float) -> vector_float);
     impl_vec_trait!([VectorMin vec_min] vec_vfmindb (vector_double, vector_double) -> vector_double);

From bfc3662a29ace7a6e18d2705ad7fb138a1976473 Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Tue, 10 Mar 2026 23:26:51 +0100
Subject: [PATCH 196/326] add f32 min/max tests

---
 crates/core_arch/src/s390x/vector.rs | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 2f31eb48f8..33921eca5f 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -7506,6 +7506,19 @@ mod tests {
         [0, !0, !0, !0]
     }
 
+    // f32 is the tricky case for max/min as that needs a fallback on z13
+    test_vec_2! { test_vec_max, vec_max, f32x4, f32x4 -> f32x4,
+        [1.0,   f32::NAN, f32::INFINITY, 2.0],
+        [-10.0, -10.0,    5.0,           f32::NAN],
+        [1.0,   -10.0,    f32::INFINITY, 2.0]
+    }
+
+    test_vec_2! { test_vec_min, vec_min, f32x4, f32x4 -> f32x4,
+        [1.0,   f32::NAN, f32::INFINITY, 2.0],
+        [-10.0, -10.0,    5.0,           f32::NAN],
+        [-10.0, -10.0,    5.0,           2.0]
+    }
+
     #[simd_test(enable = "vector")]
     fn test_vec_meadd() {
         let a = vector_unsigned_short([1, 0, 2, 0, 3, 0, 4, 0]);

From 454668b30b8acb355cf4052de711092f7cfb4c8c Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Wed, 11 Mar 2026 08:52:03 +0100
Subject: [PATCH 197/326] go back to portable LLVM intrinsic to avoid fallback
 trouble

---
 crates/core_arch/src/s390x/vector.rs | 49 ++++++++++------------------
 1 file changed, 17 insertions(+), 32 deletions(-)

diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 33921eca5f..31b9dc5eac 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -336,10 +336,19 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short;
     #[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short;
 
-    #[link_name = "llvm.s390.vfmaxsb"] fn vfmaxsb(a: vector_float, b: vector_float, mode: i32) -> vector_float;
-    #[link_name = "llvm.s390.vfmaxdb"] fn vfmaxdb(a: vector_double, b: vector_double, mode: i32) -> vector_double;
-    #[link_name = "llvm.s390.vfminsb"] fn vfminsb(a: vector_float, b: vector_float, mode: i32) -> vector_float;
-    #[link_name = "llvm.s390.vfmindb"] fn vfmindb(a: vector_double, b: vector_double, mode: i32) -> vector_double;
+    // These are the intrinsics we'd like to use (with mode 0). However, they require
+    // "vector-enhancements-1" and don't have a fallback, whereas `vec_min`/`vec_max` should be
+    // available with just "vector". Therefore, we cannot use them.
+    // #[link_name = "llvm.s390.vfmaxsb"] fn vfmaxsb(a: vector_float, b: vector_float, mode: i32) -> vector_float;
+    // #[link_name = "llvm.s390.vfmaxdb"] fn vfmaxdb(a: vector_double, b: vector_double, mode: i32) -> vector_double;
+    // #[link_name = "llvm.s390.vfminsb"] fn vfminsb(a: vector_float, b: vector_float, mode: i32) -> vector_float;
+    // #[link_name = "llvm.s390.vfmindb"] fn vfmindb(a: vector_double, b: vector_double, mode: i32) -> vector_double;
+    // Instead, we use "portable" LLVM intrinsics -- even though those have the wrong semantics
+    // (https://github.com/rust-lang/stdarch/issues/2060), they usually do the right thing.
+    #[link_name = "llvm.minnum.v4f32"] fn minnum_v4f32(a: vector_float, b: vector_float) -> vector_float;
+    #[link_name = "llvm.minnum.v2f64"] fn minnum_v2f64(a: vector_double, b: vector_double) -> vector_double;
+    #[link_name = "llvm.maxnum.v4f32"] fn maxnum_v4f32(a: vector_float, b: vector_float) -> vector_float;
+    #[link_name = "llvm.maxnum.v2f64"] fn maxnum_v2f64(a: vector_double, b: vector_double) -> vector_double;
 }
 
 #[repr(simd)]
@@ -785,20 +794,8 @@ mod sealed {
         impl_max!(vec_vmxslg, vector_unsigned_long_long, vmxlg);
     }
 
-    #[inline]
-    #[target_feature(enable = "vector")]
-    unsafe fn vfmaxsb_m0(a: vector_float, b: vector_float) -> vector_float {
-        // clang uses mode 0 for `vec_max`, so we do the same.
-        vfmaxsb(a, b, const { 0 })
-    }
-    #[inline]
-    #[target_feature(enable = "vector")]
-    unsafe fn vfmaxdb_m0(a: vector_double, b: vector_double) -> vector_double {
-        vfmaxdb(a, b, const { 0 })
-    }
-
-    test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [vfmaxsb_m0, "vector-enhancements-1" vfmaxsb ] }
-    test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [vfmaxdb_m0, "vector-enhancements-1" vfmaxdb] }
+    test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [maxnum_v4f32, "vector-enhancements-1" vfmaxsb] }
+    test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [maxnum_v2f64, "vector-enhancements-1" vfmaxdb] }
 
     impl_vec_trait!([VectorMax vec_max] vec_vfmaxsb (vector_float, vector_float) -> vector_float);
     impl_vec_trait!([VectorMax vec_max] vec_vfmaxdb (vector_double, vector_double) -> vector_double);
@@ -844,20 +841,8 @@ mod sealed {
         impl_min!(vec_vmnslg, vector_unsigned_long_long, vmnlg);
     }
 
-    #[inline]
-    #[target_feature(enable = "vector")]
-    unsafe fn vfminsb_m0(a: vector_float, b: vector_float) -> vector_float {
-        // clang uses mode 0 for `vec_min`, so we do the same.
-        vfminsb(a, b, const { 0 })
-    }
-    #[inline]
-    #[target_feature(enable = "vector")]
-    unsafe fn vfmindb_m0(a: vector_double, b: vector_double) -> vector_double {
-        vfmindb(a, b, const { 0 })
-    }
-
-    test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [vfminsb_m0, "vector-enhancements-1" vfminsb]  }
-    test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [vfmindb_m0, "vector-enhancements-1" vfmindb]  }
+    test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [minnum_v4f32, "vector-enhancements-1" vfminsb] }
+    test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [minnum_v2f64, "vector-enhancements-1" vfmindb] }
 
     impl_vec_trait!([VectorMin vec_min] vec_vfminsb (vector_float, vector_float) -> vector_float);
     impl_vec_trait!([VectorMin vec_min] vec_vfmindb (vector_double, vector_double) -> vector_double);

From 44c14dfb56cb790c2483dd29a6057860641c2ea7 Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Wed, 11 Mar 2026 18:31:49 +0100
Subject: [PATCH 198/326] s390x: add f64 tests for vec_min

---
 crates/core_arch/src/s390x/vector.rs | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 31b9dc5eac..376c912c04 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -7491,19 +7491,30 @@ mod tests {
         [0, !0, !0, !0]
     }
 
-    // f32 is the tricky case for max/min as that needs a fallback on z13
-    test_vec_2! { test_vec_max, vec_max, f32x4, f32x4 -> f32x4,
+    test_vec_2! { test_vec_max_f32, vec_max, f32x4, f32x4 -> f32x4,
         [1.0,   f32::NAN, f32::INFINITY, 2.0],
         [-10.0, -10.0,    5.0,           f32::NAN],
         [1.0,   -10.0,    f32::INFINITY, 2.0]
     }
 
-    test_vec_2! { test_vec_min, vec_min, f32x4, f32x4 -> f32x4,
+    test_vec_2! { test_vec_min_f32, vec_min, f32x4, f32x4 -> f32x4,
         [1.0,   f32::NAN, f32::INFINITY, 2.0],
         [-10.0, -10.0,    5.0,           f32::NAN],
         [-10.0, -10.0,    5.0,           2.0]
     }
 
+    test_vec_2! { test_vec_max_f64, vec_max, f64x2, f64x2 -> f64x2,
+        [f64::NAN, 2.0],
+        [-10.0,    f64::NAN],
+        [-10.0,    2.0]
+    }
+
+    test_vec_2! { test_vec_min_f64, vec_min, f64x2, f64x2 -> f64x2,
+        [f64::NAN, 2.0],
+        [-10.0,    f64::NAN],
+        [-10.0,    2.0]
+    }
+
     #[simd_test(enable = "vector")]
     fn test_vec_meadd() {
         let a = vector_unsigned_short([1, 0, 2, 0, 3, 0, 4, 0]);

From 44f40691ddf205368ef5809cd7d41da1486e428e Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 12 Mar 2026 10:37:52 +0100
Subject: [PATCH 199/326] remove `cfg_attr` on `aarch64`/`arm64ec` in the
 aarch64 module

---
 crates/core_arch/src/aarch64/mte.rs  | 30 ++++++----------------------
 crates/core_arch/src/aarch64/rand.rs | 10 ++--------
 2 files changed, 8 insertions(+), 32 deletions(-)

diff --git a/crates/core_arch/src/aarch64/mte.rs b/crates/core_arch/src/aarch64/mte.rs
index c400f774bc..1b05eb3498 100644
--- a/crates/core_arch/src/aarch64/mte.rs
+++ b/crates/core_arch/src/aarch64/mte.rs
@@ -3,35 +3,17 @@
 //! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#markdown-toc-mte-intrinsics)
 
 unsafe extern "unadjusted" {
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.irg"
-    )]
+    #[link_name = "llvm.aarch64.irg"]
     fn irg_(ptr: *const (), exclude: i64) -> *const ();
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.gmi"
-    )]
+    #[link_name = "llvm.aarch64.gmi"]
     fn gmi_(ptr: *const (), exclude: i64) -> i64;
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.ldg"
-    )]
+    #[link_name = "llvm.aarch64.ldg"]
     fn ldg_(ptr: *const (), tag_ptr: *const ()) -> *const ();
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.stg"
-    )]
+    #[link_name = "llvm.aarch64.stg"]
     fn stg_(tagged_ptr: *const (), addr_to_tag: *const ());
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.addg"
-    )]
+    #[link_name = "llvm.aarch64.addg"]
     fn addg_(ptr: *const (), value: i64) -> *const ();
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.subp"
-    )]
+    #[link_name = "llvm.aarch64.subp"]
     fn subp_(ptr_a: *const (), ptr_b: *const ()) -> i64;
 }
 
diff --git a/crates/core_arch/src/aarch64/rand.rs b/crates/core_arch/src/aarch64/rand.rs
index 5492fd0144..17b616f4ec 100644
--- a/crates/core_arch/src/aarch64/rand.rs
+++ b/crates/core_arch/src/aarch64/rand.rs
@@ -3,16 +3,10 @@
 //! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#random-number-generation-intrinsics)
 
 unsafe extern "unadjusted" {
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.rndr"
-    )]
+    #[link_name = "llvm.aarch64.rndr"]
     fn rndr_() -> Tuple;
 
-    #[cfg_attr(
-        any(target_arch = "aarch64", target_arch = "arm64ec"),
-        link_name = "llvm.aarch64.rndrrs"
-    )]
+    #[link_name = "llvm.aarch64.rndrrs"]
     fn rndrrs_() -> Tuple;
 }
 

From b7a5d2ded4d71efd351f2531a2da70021711362f Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Thu, 12 Mar 2026 13:01:57 +0000
Subject: [PATCH 200/326] Refactor alias tests using macros instead of meta
 functions

---
 crates/core_arch/src/x86/sse.rs | 192 ++++++++++++++------------------
 1 file changed, 84 insertions(+), 108 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 95666b5c3d..93b2816869 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2997,84 +2997,73 @@ mod tests {
         }
     }
 
-    fn test_mm_cvtss_si32_impl(f: fn(__m128) -> i32) {
-        let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
-        let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
-        for i in 0..inputs.len() {
-            let x = unsafe { _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0) };
-            let e = result[i];
-            let r = f(x);
-            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
+    macro_rules! test_mm_cvtss_si32 {
+    ($($test_name:ident : $alias:ident),*) => {$(
+        #[simd_test(enable = "sse")]
+        unsafe fn $test_name() {
+            let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
+            let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
+            for i in 0..inputs.len() {
+                let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
+                let e = result[i];
+                let r = $alias(x);
+                assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
+                }
+            }
+        )*}
+    }
+
+    test_mm_cvtss_si32!(test_mm_cvtss_si32: _mm_cvtss_si32, test_mm_cvt_ss2si: _mm_cvt_ss2si);
+
+    macro_rules! test_cvttss_si32 {
+    ($($test_name:ident : $alias:ident),*) => {$(
+        #[simd_test(enable = "sse")]
+        unsafe fn $test_name() {
+            let inputs = &[
+                (42.0f32, 42i32),
+                (-31.4, -31),
+                (-33.5, -33),
+                (-34.5, -34),
+                (10.999, 10),
+                (-5.99, -5),
+                (4.0e10, i32::MIN),
+                (4.0e-10, 0),
+                (NAN, i32::MIN),
+                (2147483500.1, 2147483520),
+            ];
+            for (i, &(xi, e)) in inputs.iter().enumerate() {
+                let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+                let r = $alias(x);
+                assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
+            }
         }
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvtss_si32() {
-        test_mm_cvtss_si32_impl(_mm_cvtss_si32);
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvt_ss2si() {
-        test_mm_cvtss_si32_impl(_mm_cvt_ss2si);
-    }
-
-    fn test_cvttss_si32_impl(f: fn(__m128) -> i32) {
-        let inputs = &[
-            (42.0f32, 42i32),
-            (-31.4, -31),
-            (-33.5, -33),
-            (-34.5, -34),
-            (10.999, 10),
-            (-5.99, -5),
-            (4.0e10, i32::MIN),
-            (4.0e-10, 0),
-            (NAN, i32::MIN),
-            (2147483500.1, 2147483520),
-        ];
-        for (i, &(xi, e)) in inputs.iter().enumerate() {
-            let x = unsafe { _mm_setr_ps(xi, 1.0, 3.0, 4.0) };
-            let r = f(x);
-            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
-        }
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvttss_si32() {
-        test_cvttss_si32_impl(_mm_cvttss_si32);
-    }
+    )*}
+}
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvtt_ss2si() {
-        test_cvttss_si32_impl(_mm_cvtt_ss2si)
-    }
+test_cvttss_si32!(test_cvttss_si32: _mm_cvttss_si32, test_mm_cvtt_ss2si: _mm_cvtt_ss2si);
 
-    fn test_mm_cvtsi32_ss_impl(f: fn(__m128, i32) -> __m128) {
-        unsafe {
+macro_rules! test_mm_cvtsi32_ss {
+    ($($test_name:ident : $alias:ident),*) => {$(
+        #[simd_test(enable = "sse")]
+        unsafe fn $test_name() {
             let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-            let r = f(a, 4555);
+            let r = $alias(a, 4555);
             assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r);
 
-            let r = f(a, 322223333);
+            let r = $alias(a, 322223333);
             assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r);
 
-            let r = f(a, -432);
+            let r = $alias(a, -432);
             assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r);
 
-            let r = f(a, -322223333);
+            let r = $alias(a, -322223333);
             assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r);
         }
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvtsi32_ss() {
-        test_mm_cvtsi32_ss_impl(_mm_cvtsi32_ss);
-    }
+    )*}
+}
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_cvt_si2ss() {
-        test_mm_cvtsi32_ss_impl(_mm_cvt_si2ss);
-    }
+test_mm_cvtsi32_ss!(test_mm_cvtsi32_ss: _mm_cvtsi32_ss, test_mm_cvt_si2ss: _mm_cvt_si2ss);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_cvtss_f32() {
@@ -3088,26 +3077,20 @@ mod tests {
         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
     }
 
-    fn test_mm_set1_ps_impl(f: fn(f32) -> __m128) {
-        unsafe {
-            let r = f(black_box(4.25));
+macro_rules! test_mm_set1_ps {
+    ($($test_name:ident : $alias:ident),*) => {$(
+        #[simd_test(enable = "sse")]
+        unsafe fn $test_name() {
+            let r = $alias(black_box(4.25));
             assert_eq!(get_m128(r, 0), 4.25);
             assert_eq!(get_m128(r, 1), 4.25);
             assert_eq!(get_m128(r, 2), 4.25);
             assert_eq!(get_m128(r, 3), 4.25);
         }
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_set1_ps() {
-        test_mm_set1_ps_impl(_mm_set1_ps);
-        test_mm_set1_ps_impl(_mm_set_ps1);
-    }
+    )*}
+}
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_set_ps1() {
-        test_mm_set1_ps_impl(_mm_set_ps1);
-    }
+test_mm_set1_ps!(test_mm_set1_ps: _mm_set1_ps, test_mm_set_ps1: _mm_set_ps1);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_set_ps() {
@@ -3195,21 +3178,18 @@ mod tests {
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
-    fn test_mm_load1_ps_impl(f: unsafe fn(*const f32) -> __m128) {
-        let a = 42.0f32;
-        let r = unsafe { f(ptr::addr_of!(a)) };
-        unsafe { assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)) };
-    }
-
-    #[simd_test(enable = "sse")]
-    fn test_mm_load1_ps() {
-        test_mm_load1_ps_impl(_mm_load1_ps);
-    }
+  macro_rules! test_mm_load1_ps {
+    ($($test_name:ident : $alias:ident),*) => {$(
+        #[simd_test(enable = "sse")]
+        unsafe fn $test_name() {
+            let a = 42.0f32;
+            let r = $alias(ptr::addr_of!(a));
+            assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
+        }
+    )*}
+}
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_load_ps1() {
-        test_mm_load1_ps_impl(_mm_load_ps1);
-    }
+test_mm_load1_ps!(test_mm_load1_ps: _mm_load1_ps, test_mm_load_ps1: _mm_load_ps1);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_load_ps() {
@@ -3260,20 +3240,20 @@ mod tests {
         assert_eq!(vals[2], 0.0);
     }
 
-    fn test_mm_store1_ps_impl(f: unsafe fn(*mut f32, __m128)) {
-        let mut vals = Memory { data: [0.0f32; 4] };
-        let a = unsafe { _mm_setr_ps(1.0, 2.0, 3.0, 4.0) };
-        let p = vals.data.as_mut_ptr();
-        unsafe {
-            f(p, *black_box(&a));
+macro_rules! test_mm_store1_ps {
+    ($($test_name:ident : $alias:ident),*) => {$(
+        #[simd_test(enable = "sse")]
+        unsafe fn $test_name() {
+            let mut vals = Memory { data: [0.0f32; 4] };
+            let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+            let p = vals.data.as_mut_ptr();
+            $alias(p, *black_box(&a));
+            assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
         }
-        assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
-    }
+    )*}
+}
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_store1_ps() {
-        test_mm_store1_ps_impl(_mm_store1_ps);
-    }
+test_mm_store1_ps!(test_mm_store1_ps: _mm_store1_ps, test_mm_store_ps1: _mm_store_ps1);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_store_ps() {
@@ -3290,10 +3270,6 @@ mod tests {
         assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
     }
 
-    #[simd_test(enable = "sse")]
-    fn test_mm_store_ps1() {
-        test_mm_store1_ps_impl(_mm_store_ps1);
-    }
 
     #[simd_test(enable = "sse")]
     const fn test_mm_storer_ps() {

From a4d7d29e5718f8e159d31b76663fd474c063143d Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Thu, 12 Mar 2026 13:16:36 +0000
Subject: [PATCH 201/326] Fix formatting

---
 crates/core_arch/src/x86/sse.rs | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 93b2816869..e12087da23 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3040,9 +3040,9 @@ mod tests {
     )*}
 }
 
-test_cvttss_si32!(test_cvttss_si32: _mm_cvttss_si32, test_mm_cvtt_ss2si: _mm_cvtt_ss2si);
+    test_cvttss_si32!(test_cvttss_si32: _mm_cvttss_si32, test_mm_cvtt_ss2si: _mm_cvtt_ss2si);
 
-macro_rules! test_mm_cvtsi32_ss {
+    macro_rules! test_mm_cvtsi32_ss {
     ($($test_name:ident : $alias:ident),*) => {$(
         #[simd_test(enable = "sse")]
         unsafe fn $test_name() {
@@ -3063,7 +3063,7 @@ macro_rules! test_mm_cvtsi32_ss {
     )*}
 }
 
-test_mm_cvtsi32_ss!(test_mm_cvtsi32_ss: _mm_cvtsi32_ss, test_mm_cvt_si2ss: _mm_cvt_si2ss);
+    test_mm_cvtsi32_ss!(test_mm_cvtsi32_ss: _mm_cvtsi32_ss, test_mm_cvt_si2ss: _mm_cvt_si2ss);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_cvtss_f32() {
@@ -3077,7 +3077,7 @@ test_mm_cvtsi32_ss!(test_mm_cvtsi32_ss: _mm_cvtsi32_ss, test_mm_cvt_si2ss: _mm_c
         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
     }
 
-macro_rules! test_mm_set1_ps {
+    macro_rules! test_mm_set1_ps {
     ($($test_name:ident : $alias:ident),*) => {$(
         #[simd_test(enable = "sse")]
         unsafe fn $test_name() {
@@ -3090,7 +3090,7 @@ macro_rules! test_mm_set1_ps {
     )*}
 }
 
-test_mm_set1_ps!(test_mm_set1_ps: _mm_set1_ps, test_mm_set_ps1: _mm_set_ps1);
+    test_mm_set1_ps!(test_mm_set1_ps: _mm_set1_ps, test_mm_set_ps1: _mm_set_ps1);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_set_ps() {
@@ -3178,7 +3178,7 @@ test_mm_set1_ps!(test_mm_set1_ps: _mm_set1_ps, test_mm_set_ps1: _mm_set_ps1);
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
-  macro_rules! test_mm_load1_ps {
+    macro_rules! test_mm_load1_ps {
     ($($test_name:ident : $alias:ident),*) => {$(
         #[simd_test(enable = "sse")]
         unsafe fn $test_name() {
@@ -3189,7 +3189,7 @@ test_mm_set1_ps!(test_mm_set1_ps: _mm_set1_ps, test_mm_set_ps1: _mm_set_ps1);
     )*}
 }
 
-test_mm_load1_ps!(test_mm_load1_ps: _mm_load1_ps, test_mm_load_ps1: _mm_load_ps1);
+    test_mm_load1_ps!(test_mm_load1_ps: _mm_load1_ps, test_mm_load_ps1: _mm_load_ps1);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_load_ps() {
@@ -3240,7 +3240,7 @@ test_mm_load1_ps!(test_mm_load1_ps: _mm_load1_ps, test_mm_load_ps1: _mm_load_ps1
         assert_eq!(vals[2], 0.0);
     }
 
-macro_rules! test_mm_store1_ps {
+    macro_rules! test_mm_store1_ps {
     ($($test_name:ident : $alias:ident),*) => {$(
         #[simd_test(enable = "sse")]
         unsafe fn $test_name() {
@@ -3253,7 +3253,7 @@ macro_rules! test_mm_store1_ps {
     )*}
 }
 
-test_mm_store1_ps!(test_mm_store1_ps: _mm_store1_ps, test_mm_store_ps1: _mm_store_ps1);
+    test_mm_store1_ps!(test_mm_store1_ps: _mm_store1_ps, test_mm_store_ps1: _mm_store_ps1);
 
     #[simd_test(enable = "sse")]
     const fn test_mm_store_ps() {
@@ -3270,7 +3270,6 @@ test_mm_store1_ps!(test_mm_store1_ps: _mm_store1_ps, test_mm_store_ps1: _mm_stor
         assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
     }
 
-
     #[simd_test(enable = "sse")]
     const fn test_mm_storer_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };

From 2e84c7586ef5475d0533aead935b43870220c772 Mon Sep 17 00:00:00 2001
From: anonymous <you@example.com>
Date: Thu, 12 Mar 2026 16:05:20 -0700
Subject: [PATCH 202/326] ci: update to actions/checkout@v6

ci is showing a lot of warnings (72) right now. apparently
actions/checkout@v4 uses Node.js 20, and all github actions are
scheduled to be force opted-in to Node.js 24 on 2026-06-02.
I don't anticipate bumping the checkout action to v6 / Node.js 24
to cause any issues (Node.js 24 drops support for ARM32 and macOS
versions <= 13.4, but this shouldn't matter because we use Docker
to test in those environments, not github runners natively) but if
it does cause issues it's probably better to find out now rather
than by surprise 3 months from now... :)
---
 .github/workflows/main.yml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 0ec355aa3c..3749ed1f6a 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -8,7 +8,7 @@ jobs:
     name: Check Style
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: Install Rust
       run: rustup update nightly --no-self-update && rustup default nightly
     - run: ci/style.sh
@@ -18,7 +18,7 @@ jobs:
     needs: [style]
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: Install Rust
       run: rustup update nightly --no-self-update && rustup default nightly
     - run: ci/dox.sh
@@ -30,7 +30,7 @@ jobs:
     needs: [style]
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: Install Rust
       run: rustup update nightly --no-self-update && rustup default nightly
     - run: cargo test --manifest-path crates/stdarch-verify/Cargo.toml
@@ -216,7 +216,7 @@ jobs:
           build_std: true
 
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: Install Rust
       run: |
         rustup update nightly --no-self-update
@@ -285,7 +285,7 @@ jobs:
             build_std: true
 
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: Install Rust
       run: |
         rustup update nightly --no-self-update
@@ -310,7 +310,7 @@ jobs:
     name: Check stdarch-gen-{arm, loongarch, hexagon} output
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: Install Rust
       run: rustup update nightly && rustup default nightly && rustup component add rustfmt
     - name: Check arm spec

From d6ffea0306966691ddcab4b232085e09bb76eb58 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 12 Mar 2026 12:32:35 +0100
Subject: [PATCH 203/326] inline `assert_instr` tests

---
 crates/core_arch/src/aarch64/mte.rs  | 16 ++++++++++------
 crates/core_arch/src/aarch64/rand.rs | 25 +++++--------------------
 2 files changed, 15 insertions(+), 26 deletions(-)

diff --git a/crates/core_arch/src/aarch64/mte.rs b/crates/core_arch/src/aarch64/mte.rs
index 1b05eb3498..a5031a45c1 100644
--- a/crates/core_arch/src/aarch64/mte.rs
+++ b/crates/core_arch/src/aarch64/mte.rs
@@ -109,42 +109,46 @@ mod test {
     use super::*;
     use stdarch_test::assert_instr;
 
-    #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(irg))] // FIXME: MSVC  `dumpbin` doesn't support MTE
+    // Instruction tests are separate because the functions use generics.
+    //
+    // FIXME: As of 2026 MSVC  `dumpbin` doesn't support MTE.
+
+    #[cfg_attr(not(target_env = "msvc"), assert_instr(irg))]
     #[allow(dead_code)]
     #[target_feature(enable = "mte")]
     unsafe fn test_arm_mte_create_random_tag(src: *const (), mask: u64) -> *const () {
         __arm_mte_create_random_tag(src, mask)
     }
 
-    #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(addg))]
+    #[cfg_attr(not(target_env = "msvc"), assert_instr(addg))]
     #[allow(dead_code)]
     #[target_feature(enable = "mte")]
     unsafe fn test_arm_mte_increment_tag(src: *const ()) -> *const () {
         __arm_mte_increment_tag::<1, _>(src)
     }
 
-    #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(gmi))]
+    #[cfg_attr(not(target_env = "msvc"), assert_instr(gmi))]
     #[allow(dead_code)]
     #[target_feature(enable = "mte")]
     unsafe fn test_arm_mte_exclude_tag(src: *const (), excluded: u64) -> u64 {
         __arm_mte_exclude_tag(src, excluded)
     }
 
-    #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stg))]
+    #[cfg_attr(not(target_env = "msvc"), assert_instr(stg))]
     #[allow(dead_code)]
     #[target_feature(enable = "mte")]
     unsafe fn test_arm_mte_set_tag(src: *const ()) {
         __arm_mte_set_tag(src)
     }
 
-    #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldg))]
+    #[cfg_attr(not(target_env = "msvc"), assert_instr(ldg))]
     #[allow(dead_code)]
     #[target_feature(enable = "mte")]
     unsafe fn test_arm_mte_get_tag(src: *const ()) -> *const () {
         __arm_mte_get_tag(src)
     }
 
-    #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(subp))]
+    #[cfg_attr(not(target_env = "msvc"), assert_instr(subp))]
     #[allow(dead_code)]
     #[target_feature(enable = "mte")]
     unsafe fn test_arm_mte_ptrdiff(a: *const (), b: *const ()) -> i64 {
diff --git a/crates/core_arch/src/aarch64/rand.rs b/crates/core_arch/src/aarch64/rand.rs
index 17b616f4ec..3f52cf2ce8 100644
--- a/crates/core_arch/src/aarch64/rand.rs
+++ b/crates/core_arch/src/aarch64/rand.rs
@@ -2,6 +2,9 @@
 //!
 //! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#random-number-generation-intrinsics)
 
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
 unsafe extern "unadjusted" {
     #[link_name = "llvm.aarch64.rndr"]
     fn rndr_() -> Tuple;
@@ -22,6 +25,7 @@ struct Tuple {
 /// is returned.
 #[inline]
 #[target_feature(enable = "rand")]
+#[cfg_attr(test, assert_instr(mrs))]
 #[unstable(feature = "stdarch_aarch64_rand", issue = "153514")]
 pub unsafe fn __rndr(value: *mut u64) -> i32 {
     let Tuple { bits, status } = rndr_();
@@ -35,29 +39,10 @@ pub unsafe fn __rndr(value: *mut u64) -> i32 {
 /// to by the input is set to zero and a non-zero value is returned.
 #[inline]
 #[target_feature(enable = "rand")]
+#[cfg_attr(test, assert_instr(mrs))]
 #[unstable(feature = "stdarch_aarch64_rand", issue = "153514")]
 pub unsafe fn __rndrrs(value: *mut u64) -> i32 {
     let Tuple { bits, status } = rndrrs_();
     unsafe { *value = bits };
     status as i32
 }
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use stdarch_test::assert_instr;
-
-    #[cfg_attr(test, assert_instr(mrs))]
-    #[allow(dead_code)]
-    #[target_feature(enable = "rand")]
-    unsafe fn test_rndr(value: &mut u64) -> i32 {
-        __rndr(value)
-    }
-
-    #[cfg_attr(test, assert_instr(mrs))]
-    #[allow(dead_code)]
-    #[target_feature(enable = "rand")]
-    unsafe fn test_rndrrs(value: &mut u64) -> i32 {
-        __rndrrs(value)
-    }
-}

From 7420bd76405fe6e767aff541c99a3e0e3efeea6a Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Sun, 15 Mar 2026 22:11:26 +0000
Subject: [PATCH 204/326] remove usages of to-be-deprecated numeric constants

---
 crates/core_arch/src/mips/msa.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/crates/core_arch/src/mips/msa.rs b/crates/core_arch/src/mips/msa.rs
index 563e121a7b..6246433da5 100644
--- a/crates/core_arch/src/mips/msa.rs
+++ b/crates/core_arch/src/mips/msa.rs
@@ -9187,7 +9187,6 @@ mod tests {
         core_arch::{mips::msa::*, simd::*},
         mem,
     };
-    use std::{f32, f64};
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "msa")]

From 8c4d55cc87894cb740c09923ac14eb9234d37339 Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Tue, 17 Mar 2026 22:16:33 +0000
Subject: [PATCH 205/326] Use macros for test body deduplication in SSE alias
 tests

---
 crates/core_arch/src/x86/sse.rs | 210 ++++++++++++++++++--------------
 1 file changed, 120 insertions(+), 90 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index e12087da23..fbce52fc29 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2997,73 +2997,88 @@ mod tests {
         }
     }
 
-    macro_rules! test_mm_cvtss_si32 {
-    ($($test_name:ident : $alias:ident),*) => {$(
-        #[simd_test(enable = "sse")]
-        unsafe fn $test_name() {
-            let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
-            let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
-            for i in 0..inputs.len() {
-                let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
-                let e = result[i];
-                let r = $alias(x);
-                assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
-                }
+    macro_rules! test_mm_cvtss_si32_impl {
+    ($alias:ident) => {
+        let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
+        let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
+        for i in 0..inputs.len() {
+            let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
+            let e = result[i];
+            let r = $alias(x);
+            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
             }
-        )*}
-    }
-
-    test_mm_cvtss_si32!(test_mm_cvtss_si32: _mm_cvtss_si32, test_mm_cvt_ss2si: _mm_cvt_ss2si);
-
-    macro_rules! test_cvttss_si32 {
-    ($($test_name:ident : $alias:ident),*) => {$(
-        #[simd_test(enable = "sse")]
-        unsafe fn $test_name() {
-            let inputs = &[
-                (42.0f32, 42i32),
-                (-31.4, -31),
-                (-33.5, -33),
-                (-34.5, -34),
-                (10.999, 10),
-                (-5.99, -5),
-                (4.0e10, i32::MIN),
-                (4.0e-10, 0),
-                (NAN, i32::MIN),
-                (2147483500.1, 2147483520),
-            ];
-            for (i, &(xi, e)) in inputs.iter().enumerate() {
-                let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
-                let r = $alias(x);
-                assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
+        }
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_cvtss_si32() {
+        test_mm_cvtss_si32_impl!(_mm_cvtss_si32);
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_cvt_ss2si() {
+        test_mm_cvtss_si32_impl!(_mm_cvt_ss2si);
+    }
+
+    macro_rules! test_cvttss_si32_impl {
+    ($alias:ident) => {
+        let inputs = &[
+            (42.0f32, 42i32),
+            (-31.4, -31),
+            (-33.5, -33),
+            (-34.5, -34),
+            (10.999, 10),
+            (-5.99, -5),
+            (4.0e10, i32::MIN),
+            (4.0e-10, 0),
+            (NAN, i32::MIN),
+            (2147483500.1, 2147483520),
+        ];
+        for (i, &(xi, e)) in inputs.iter().enumerate() {
+            let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+            let r = $alias(x);
+            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
             }
         }
-    )*}
-}
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_cvttss_si32() {
+        test_cvttss_si32_impl!(_mm_cvttss_si32);
+    }
 
-    test_cvttss_si32!(test_cvttss_si32: _mm_cvttss_si32, test_mm_cvtt_ss2si: _mm_cvtt_ss2si);
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_cvtt_ss2si() {
+        test_cvttss_si32_impl!(_mm_cvtt_ss2si);
+    }
 
-    macro_rules! test_mm_cvtsi32_ss {
-    ($($test_name:ident : $alias:ident),*) => {$(
-        #[simd_test(enable = "sse")]
-        unsafe fn $test_name() {
-            let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+    macro_rules! test_mm_cvtsi32_ss_impl {
+    ($alias:ident) => {
+        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-            let r = $alias(a, 4555);
-            assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r);
+        let r = $alias(a, 4555);
+        assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r);
 
-            let r = $alias(a, 322223333);
-            assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r);
+        let r = $alias(a, 322223333);
+        assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r);
 
-            let r = $alias(a, -432);
-            assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r);
+        let r = $alias(a, -432);
+        assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r);
 
-            let r = $alias(a, -322223333);
-            assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r);
+        let r = $alias(a, -322223333);
+        assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r);
         }
-    )*}
-}
+    }
 
-    test_mm_cvtsi32_ss!(test_mm_cvtsi32_ss: _mm_cvtsi32_ss, test_mm_cvt_si2ss: _mm_cvt_si2ss);
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_cvtsi32_ss() {
+        test_mm_cvtsi32_ss_impl!(_mm_cvtsi32_ss);
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_cvt_si2ss() {
+        test_mm_cvtsi32_ss_impl!(_mm_cvt_si2ss);
+    }
 
     #[simd_test(enable = "sse")]
     const fn test_mm_cvtss_f32() {
@@ -3077,20 +3092,25 @@ mod tests {
         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
     }
 
-    macro_rules! test_mm_set1_ps {
-    ($($test_name:ident : $alias:ident),*) => {$(
-        #[simd_test(enable = "sse")]
-        unsafe fn $test_name() {
-            let r = $alias(black_box(4.25));
-            assert_eq!(get_m128(r, 0), 4.25);
-            assert_eq!(get_m128(r, 1), 4.25);
-            assert_eq!(get_m128(r, 2), 4.25);
-            assert_eq!(get_m128(r, 3), 4.25);
+    macro_rules! test_mm_set1_ps_impl {
+    ($alias:ident) => {
+        let r = $alias(black_box(4.25));
+        assert_eq!(get_m128(r, 0), 4.25);
+        assert_eq!(get_m128(r, 1), 4.25);
+        assert_eq!(get_m128(r, 2), 4.25);
+        assert_eq!(get_m128(r, 3), 4.25);
         }
-    )*}
-}
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_set1_ps() {
+        test_mm_set1_ps_impl!(_mm_set1_ps);
+    }
 
-    test_mm_set1_ps!(test_mm_set1_ps: _mm_set1_ps, test_mm_set_ps1: _mm_set_ps1);
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_set_ps1() {
+        test_mm_set1_ps_impl!(_mm_set_ps1);
+    }
 
     #[simd_test(enable = "sse")]
     const fn test_mm_set_ps() {
@@ -3178,18 +3198,23 @@ mod tests {
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
-    macro_rules! test_mm_load1_ps {
-    ($($test_name:ident : $alias:ident),*) => {$(
-        #[simd_test(enable = "sse")]
-        unsafe fn $test_name() {
-            let a = 42.0f32;
-            let r = $alias(ptr::addr_of!(a));
-            assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
+    macro_rules! test_mm_load1_ps_impl {
+    ($alias:ident) => {
+        let a = 42.0f32;
+        let r = $alias(ptr::addr_of!(a));
+        assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
         }
-    )*}
-}
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_load1_ps() {
+        test_mm_load1_ps_impl!(_mm_load1_ps);
+    }
 
-    test_mm_load1_ps!(test_mm_load1_ps: _mm_load1_ps, test_mm_load_ps1: _mm_load_ps1);
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_load_ps1() {
+        test_mm_load1_ps_impl!(_mm_load_ps1);
+    }
 
     #[simd_test(enable = "sse")]
     const fn test_mm_load_ps() {
@@ -3240,20 +3265,25 @@ mod tests {
         assert_eq!(vals[2], 0.0);
     }
 
-    macro_rules! test_mm_store1_ps {
-    ($($test_name:ident : $alias:ident),*) => {$(
-        #[simd_test(enable = "sse")]
-        unsafe fn $test_name() {
-            let mut vals = Memory { data: [0.0f32; 4] };
-            let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-            let p = vals.data.as_mut_ptr();
-            $alias(p, *black_box(&a));
-            assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
+    macro_rules! test_mm_store1_ps_impl {
+    ($alias:ident) => {
+        let mut vals = Memory { data: [0.0f32; 4] };
+        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+        let p = vals.data.as_mut_ptr();
+        $alias(p, *black_box(&a));
+        assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
         }
-    )*}
-}
+    }
+
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_store1_ps() {
+        test_mm_store1_ps_impl!(_mm_store1_ps);
+    }
 
-    test_mm_store1_ps!(test_mm_store1_ps: _mm_store1_ps, test_mm_store_ps1: _mm_store_ps1);
+    #[simd_test(enable = "sse")]
+    unsafe fn test_mm_store_ps1() {
+        test_mm_store1_ps_impl!(_mm_store_ps1);
+    }
 
     #[simd_test(enable = "sse")]
     const fn test_mm_store_ps() {

From 66cc054d50a2c49c11ac1f678b242940cfaa747c Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Tue, 17 Mar 2026 22:18:40 +0000
Subject: [PATCH 206/326] Fix formatting

---
 crates/core_arch/src/x86/sse.rs | 114 ++++++++++++++++----------------
 1 file changed, 57 insertions(+), 57 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index fbce52fc29..11fb3a865b 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -2998,16 +2998,16 @@ mod tests {
     }
 
     macro_rules! test_mm_cvtss_si32_impl {
-    ($alias:ident) => {
-        let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
-        let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
-        for i in 0..inputs.len() {
-            let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
-            let e = result[i];
-            let r = $alias(x);
-            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
+        ($alias:ident) => {
+            let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
+            let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
+            for i in 0..inputs.len() {
+                let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
+                let e = result[i];
+                let r = $alias(x);
+                assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
             }
-        }
+        };
     }
 
     #[simd_test(enable = "sse")]
@@ -3021,25 +3021,25 @@ mod tests {
     }
 
     macro_rules! test_cvttss_si32_impl {
-    ($alias:ident) => {
-        let inputs = &[
-            (42.0f32, 42i32),
-            (-31.4, -31),
-            (-33.5, -33),
-            (-34.5, -34),
-            (10.999, 10),
-            (-5.99, -5),
-            (4.0e10, i32::MIN),
-            (4.0e-10, 0),
-            (NAN, i32::MIN),
-            (2147483500.1, 2147483520),
-        ];
-        for (i, &(xi, e)) in inputs.iter().enumerate() {
-            let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
-            let r = $alias(x);
-            assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
+        ($alias:ident) => {
+            let inputs = &[
+                (42.0f32, 42i32),
+                (-31.4, -31),
+                (-33.5, -33),
+                (-34.5, -34),
+                (10.999, 10),
+                (-5.99, -5),
+                (4.0e10, i32::MIN),
+                (4.0e-10, 0),
+                (NAN, i32::MIN),
+                (2147483500.1, 2147483520),
+            ];
+            for (i, &(xi, e)) in inputs.iter().enumerate() {
+                let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+                let r = $alias(x);
+                assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e);
             }
-        }
+        };
     }
 
     #[simd_test(enable = "sse")]
@@ -3053,21 +3053,21 @@ mod tests {
     }
 
     macro_rules! test_mm_cvtsi32_ss_impl {
-    ($alias:ident) => {
-        let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+        ($alias:ident) => {
+            let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-        let r = $alias(a, 4555);
-        assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r);
+            let r = $alias(a, 4555);
+            assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r);
 
-        let r = $alias(a, 322223333);
-        assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r);
+            let r = $alias(a, 322223333);
+            assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r);
 
-        let r = $alias(a, -432);
-        assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r);
+            let r = $alias(a, -432);
+            assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r);
 
-        let r = $alias(a, -322223333);
-        assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r);
-        }
+            let r = $alias(a, -322223333);
+            assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r);
+        };
     }
 
     #[simd_test(enable = "sse")]
@@ -3093,13 +3093,13 @@ mod tests {
     }
 
     macro_rules! test_mm_set1_ps_impl {
-    ($alias:ident) => {
-        let r = $alias(black_box(4.25));
-        assert_eq!(get_m128(r, 0), 4.25);
-        assert_eq!(get_m128(r, 1), 4.25);
-        assert_eq!(get_m128(r, 2), 4.25);
-        assert_eq!(get_m128(r, 3), 4.25);
-        }
+        ($alias:ident) => {
+            let r = $alias(black_box(4.25));
+            assert_eq!(get_m128(r, 0), 4.25);
+            assert_eq!(get_m128(r, 1), 4.25);
+            assert_eq!(get_m128(r, 2), 4.25);
+            assert_eq!(get_m128(r, 3), 4.25);
+        };
     }
 
     #[simd_test(enable = "sse")]
@@ -3199,11 +3199,11 @@ mod tests {
     }
 
     macro_rules! test_mm_load1_ps_impl {
-    ($alias:ident) => {
-        let a = 42.0f32;
-        let r = $alias(ptr::addr_of!(a));
-        assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
-        }
+        ($alias:ident) => {
+            let a = 42.0f32;
+            let r = $alias(ptr::addr_of!(a));
+            assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
+        };
     }
 
     #[simd_test(enable = "sse")]
@@ -3266,13 +3266,13 @@ mod tests {
     }
 
     macro_rules! test_mm_store1_ps_impl {
-    ($alias:ident) => {
-        let mut vals = Memory { data: [0.0f32; 4] };
-        let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-        let p = vals.data.as_mut_ptr();
-        $alias(p, *black_box(&a));
-        assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
-        }
+        ($alias:ident) => {
+            let mut vals = Memory { data: [0.0f32; 4] };
+            let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+            let p = vals.data.as_mut_ptr();
+            $alias(p, *black_box(&a));
+            assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
+        };
     }
 
     #[simd_test(enable = "sse")]

From e700d17c83e5c7e2b376899cf7412339d408198d Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Wed, 18 Mar 2026 15:04:47 +0100
Subject: [PATCH 207/326] simd_fmin/fmax: make semantics and name consistent
 with scalar intrinsics

---
 crates/core_arch/src/nvptx/packed.rs |  4 ++--
 crates/core_arch/src/x86/sse.rs      | 14 +++++++-------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/crates/core_arch/src/nvptx/packed.rs b/crates/core_arch/src/nvptx/packed.rs
index 856aeea4b6..1c7e81268f 100644
--- a/crates/core_arch/src/nvptx/packed.rs
+++ b/crates/core_arch/src/nvptx/packed.rs
@@ -99,7 +99,7 @@ pub unsafe fn f16x2_neg(a: f16x2) -> f16x2 {
 #[cfg_attr(test, assert_instr(min.f16x2))]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
 pub unsafe fn f16x2_min(a: f16x2, b: f16x2) -> f16x2 {
-    simd_fmin(a, b)
+    simd_minimum_number_nsz(a, b)
 }
 
 /// Find the minimum of two values, NaNs pass through.
@@ -123,7 +123,7 @@ pub unsafe fn f16x2_min_nan(a: f16x2, b: f16x2) -> f16x2 {
 #[cfg_attr(test, assert_instr(max.f16x2))]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
 pub unsafe fn f16x2_max(a: f16x2, b: f16x2) -> f16x2 {
-    simd_fmax(a, b)
+    simd_maximum_number_nsz(a, b)
 }
 
 /// Find the maximum of two values, NaNs pass through.
diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 3f7781cc7d..9183eabd53 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -208,7 +208,7 @@ pub fn _mm_min_ss(a: __m128, b: __m128) -> __m128 {
 #[cfg_attr(test, assert_instr(minps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_min_ps(a: __m128, b: __m128) -> __m128 {
-    // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmin`.
+    // See the `test_mm_min_ps` test why this can't be implemented using `simd_minimum_number_nsz`.
     unsafe { minps(a, b) }
 }
 
@@ -234,7 +234,7 @@ pub fn _mm_max_ss(a: __m128, b: __m128) -> __m128 {
 #[cfg_attr(test, assert_instr(maxps))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_max_ps(a: __m128, b: __m128) -> __m128 {
-    // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmax`.
+    // See the `test_mm_min_ps` test why this can't be implemented using `simd_maximum_number_nsz`.
     unsafe { maxps(a, b) }
 }
 
@@ -2227,11 +2227,11 @@ mod tests {
         let r = _mm_min_ps(a, b);
         assert_eq_m128(r, _mm_setr_ps(-100.0, 5.0, 0.0, -10.0));
 
-        // `_mm_min_ps` can **not** be implemented using the `simd_min` rust intrinsic. `simd_min`
-        // is lowered by the llvm codegen backend to `llvm.minnum.v*` llvm intrinsic. This intrinsic
-        // doesn't specify how -0.0 is handled. Unfortunately it happens to behave different from
-        // the `minps` x86 instruction on x86. The `llvm.minnum.v*` llvm intrinsic equals
-        // `r1` to `a` and `r2` to `b`.
+        // `_mm_min_ps` can **not** be implemented using the `simd_minimum_number_nsz` rust
+        // intrinsic. That intrinsic is lowered by the llvm codegen backend to `llvm.minimumnum.v*`
+        // llvm intrinsic with the `nsz` attribute. The `nsz` attribute means -0.0 is handled
+        // non-deterministically. The `minps` x86 instruction however has a deterministic semantics
+        // for signed zeros.
         let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0);
         let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0);
         let r1 = _mm_min_ps(a, b).as_f32x4().to_bits();

From 4a7416d5b639365ea4c52e27369af904f1f4d166 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Thu, 19 Mar 2026 20:39:38 +0800
Subject: [PATCH 208/326] Mark the LoongArch intrinsics as inline(always)

---
 crates/core_arch/src/loongarch32/mod.rs       |    8 +-
 .../src/loongarch64/lasx/generated.rs         | 1516 ++++++++---------
 .../src/loongarch64/lsx/generated.rs          | 1440 ++++++++--------
 crates/core_arch/src/loongarch64/mod.rs       |   26 +-
 crates/core_arch/src/loongarch_shared/mod.rs  |   50 +-
 crates/stdarch-gen-loongarch/src/main.rs      |    4 +-
 6 files changed, 1522 insertions(+), 1522 deletions(-)

diff --git a/crates/core_arch/src/loongarch32/mod.rs b/crates/core_arch/src/loongarch32/mod.rs
index 4e3f3d2718..6cc1116113 100644
--- a/crates/core_arch/src/loongarch32/mod.rs
+++ b/crates/core_arch/src/loongarch32/mod.rs
@@ -15,7 +15,7 @@ unsafe extern "unadjusted" {
 }
 
 /// Generates the cache operation instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn cacop<const IMM5: i32, const IMM_S12: i32>(b: i32) {
     static_assert_uimm_bits!(IMM5, 5);
@@ -24,7 +24,7 @@ pub unsafe fn cacop<const IMM5: i32, const IMM_S12: i32>(b: i32) {
 }
 
 /// Reads the CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -32,7 +32,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
 }
 
 /// Writes the CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -40,7 +40,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
 }
 
 /// Exchanges the CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
     static_assert_uimm_bits!(IMM14, 14);
diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index 1d9d4e8248..d2e1a87fde 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -1529,35 +1529,35 @@ unsafe extern "unadjusted" {
     fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64;
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsll_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsll_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsll_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsll_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsll_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsll_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsll_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsll_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1566,7 +1566,7 @@ pub fn lasx_xvslli_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslli_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1575,7 +1575,7 @@ pub fn lasx_xvslli_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslli_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1584,7 +1584,7 @@ pub fn lasx_xvslli_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslli_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1593,35 +1593,35 @@ pub fn lasx_xvslli_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslli_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsra_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsra_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsra_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsra_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsra_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsra_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsra_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsra_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1630,7 +1630,7 @@ pub fn lasx_xvsrai_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrai_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1639,7 +1639,7 @@ pub fn lasx_xvsrai_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrai_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1648,7 +1648,7 @@ pub fn lasx_xvsrai_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrai_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1657,35 +1657,35 @@ pub fn lasx_xvsrai_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrai_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1694,7 +1694,7 @@ pub fn lasx_xvsrari_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1703,7 +1703,7 @@ pub fn lasx_xvsrari_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1712,7 +1712,7 @@ pub fn lasx_xvsrari_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1721,35 +1721,35 @@ pub fn lasx_xvsrari_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrl_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrl_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrl_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrl_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrl_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrl_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrl_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrl_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1758,7 +1758,7 @@ pub fn lasx_xvsrli_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrli_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1767,7 +1767,7 @@ pub fn lasx_xvsrli_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrli_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1776,7 +1776,7 @@ pub fn lasx_xvsrli_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrli_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1785,35 +1785,35 @@ pub fn lasx_xvsrli_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrli_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1822,7 +1822,7 @@ pub fn lasx_xvsrlri_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1831,7 +1831,7 @@ pub fn lasx_xvsrlri_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1840,7 +1840,7 @@ pub fn lasx_xvsrlri_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1849,35 +1849,35 @@ pub fn lasx_xvsrlri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1886,7 +1886,7 @@ pub fn lasx_xvbitclri_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1895,7 +1895,7 @@ pub fn lasx_xvbitclri_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1904,7 +1904,7 @@ pub fn lasx_xvbitclri_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1913,35 +1913,35 @@ pub fn lasx_xvbitclri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1950,7 +1950,7 @@ pub fn lasx_xvbitseti_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1959,7 +1959,7 @@ pub fn lasx_xvbitseti_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1968,7 +1968,7 @@ pub fn lasx_xvbitseti_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1977,35 +1977,35 @@ pub fn lasx_xvbitseti_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2014,7 +2014,7 @@ pub fn lasx_xvbitrevi_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2023,7 +2023,7 @@ pub fn lasx_xvbitrevi_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2032,7 +2032,7 @@ pub fn lasx_xvbitrevi_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2041,35 +2041,35 @@ pub fn lasx_xvbitrevi_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadd_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadd_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadd_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadd_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadd_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadd_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadd_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2078,7 +2078,7 @@ pub fn lasx_xvaddi_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddi_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2087,7 +2087,7 @@ pub fn lasx_xvaddi_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddi_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2096,7 +2096,7 @@ pub fn lasx_xvaddi_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddi_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2105,35 +2105,35 @@ pub fn lasx_xvaddi_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddi_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsub_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsub_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsub_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsub_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsub_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsub_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsub_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsub_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2142,7 +2142,7 @@ pub fn lasx_xvsubi_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2151,7 +2151,7 @@ pub fn lasx_xvsubi_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2160,7 +2160,7 @@ pub fn lasx_xvsubi_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2169,35 +2169,35 @@ pub fn lasx_xvsubi_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2206,7 +2206,7 @@ pub fn lasx_xvmaxi_b<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2215,7 +2215,7 @@ pub fn lasx_xvmaxi_h<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2224,7 +2224,7 @@ pub fn lasx_xvmaxi_w<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2233,35 +2233,35 @@ pub fn lasx_xvmaxi_d<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmax_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmax_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2270,7 +2270,7 @@ pub fn lasx_xvmaxi_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2279,7 +2279,7 @@ pub fn lasx_xvmaxi_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2288,7 +2288,7 @@ pub fn lasx_xvmaxi_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2297,35 +2297,35 @@ pub fn lasx_xvmaxi_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaxi_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2334,7 +2334,7 @@ pub fn lasx_xvmini_b<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2343,7 +2343,7 @@ pub fn lasx_xvmini_h<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2352,7 +2352,7 @@ pub fn lasx_xvmini_w<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2361,35 +2361,35 @@ pub fn lasx_xvmini_d<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmin_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmin_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2398,7 +2398,7 @@ pub fn lasx_xvmini_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2407,7 +2407,7 @@ pub fn lasx_xvmini_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2416,7 +2416,7 @@ pub fn lasx_xvmini_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2425,35 +2425,35 @@ pub fn lasx_xvmini_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmini_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvseq_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseq_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvseq_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseq_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvseq_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseq_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvseq_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2462,7 +2462,7 @@ pub fn lasx_xvseqi_b<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseqi_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2471,7 +2471,7 @@ pub fn lasx_xvseqi_h<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseqi_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2480,7 +2480,7 @@ pub fn lasx_xvseqi_w<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseqi_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2489,35 +2489,35 @@ pub fn lasx_xvseqi_d<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvseqi_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2526,7 +2526,7 @@ pub fn lasx_xvslti_b<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2535,7 +2535,7 @@ pub fn lasx_xvslti_h<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2544,7 +2544,7 @@ pub fn lasx_xvslti_w<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2553,35 +2553,35 @@ pub fn lasx_xvslti_d<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvslt_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslt_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2590,7 +2590,7 @@ pub fn lasx_xvslti_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2599,7 +2599,7 @@ pub fn lasx_xvslti_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2608,7 +2608,7 @@ pub fn lasx_xvslti_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2617,35 +2617,35 @@ pub fn lasx_xvslti_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslti_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2654,7 +2654,7 @@ pub fn lasx_xvslei_b<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2663,7 +2663,7 @@ pub fn lasx_xvslei_h<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2672,7 +2672,7 @@ pub fn lasx_xvslei_w<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2681,35 +2681,35 @@ pub fn lasx_xvslei_d<const IMM_S5: i32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsle_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsle_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2718,7 +2718,7 @@ pub fn lasx_xvslei_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2727,7 +2727,7 @@ pub fn lasx_xvslei_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2736,7 +2736,7 @@ pub fn lasx_xvslei_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2745,7 +2745,7 @@ pub fn lasx_xvslei_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvslei_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2754,7 +2754,7 @@ pub fn lasx_xvsat_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2763,7 +2763,7 @@ pub fn lasx_xvsat_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2772,7 +2772,7 @@ pub fn lasx_xvsat_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2781,7 +2781,7 @@ pub fn lasx_xvsat_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2790,7 +2790,7 @@ pub fn lasx_xvsat_bu<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2799,7 +2799,7 @@ pub fn lasx_xvsat_hu<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2808,7 +2808,7 @@ pub fn lasx_xvsat_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2817,595 +2817,595 @@ pub fn lasx_xvsat_du<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmul_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmul_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmul_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmul_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmul_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmul_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmul_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmul_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmadd_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmadd_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmadd_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmadd_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmsub_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmsub_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmsub_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmsub_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvdiv_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvdiv_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmod_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmod_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3414,7 +3414,7 @@ pub fn lasx_xvrepl128vei_b<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_b(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3423,7 +3423,7 @@ pub fn lasx_xvrepl128vei_h<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_h(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3432,7 +3432,7 @@ pub fn lasx_xvrepl128vei_w<const IMM2: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_w(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3441,210 +3441,210 @@ pub fn lasx_xvrepl128vei_d<const IMM1: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_d(transmute(a), IMM1)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvand_v(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvand_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3653,14 +3653,14 @@ pub fn lasx_xvandi_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvor_v(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvor_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3669,14 +3669,14 @@ pub fn lasx_xvori_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvnor_v(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvnor_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3685,14 +3685,14 @@ pub fn lasx_xvnori_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvxor_v(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvxor_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3701,14 +3701,14 @@ pub fn lasx_xvxori_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3717,7 +3717,7 @@ pub fn lasx_xvbitseli_b<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3726,7 +3726,7 @@ pub fn lasx_xvshuf4i_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3735,7 +3735,7 @@ pub fn lasx_xvshuf4i_h<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3744,497 +3744,497 @@ pub fn lasx_xvshuf4i_w<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplgr2vr_b(a: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplgr2vr_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplgr2vr_h(a: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplgr2vr_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplgr2vr_w(a: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplgr2vr_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplgr2vr_d(a: i64) -> m256i {
     unsafe { transmute(__lasx_xvreplgr2vr_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpcnt_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpcnt_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpcnt_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpcnt_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpcnt_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpcnt_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpcnt_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpcnt_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclz_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclz_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclz_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclz_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfadd_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfadd_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfadd_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfsub_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfsub_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfsub_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfsub_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmul_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmul_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmul_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmul_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfdiv_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfdiv_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfdiv_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfdiv_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvt_h_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcvt_h_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvt_s_d(a: m256d, b: m256d) -> m256 {
     unsafe { transmute(__lasx_xvfcvt_s_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmin_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmin_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmin_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmin_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmina_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmina_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmina_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmina_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmax_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmax_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmax_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmax_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmaxa_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmaxa_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmaxa_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmaxa_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfclass_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvfclass_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfclass_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfclass_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfsqrt_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfsqrt_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfsqrt_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfsqrt_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecip_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrecip_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecip_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrecip_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecipe_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrecipe_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecipe_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrecipe_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrte_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrsqrte_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrte_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrsqrte_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrint_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrint_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrint_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrint_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrt_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrsqrt_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrt_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrsqrt_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvflogb_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvflogb_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvflogb_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvflogb_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvth_s_h(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvfcvth_s_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvth_d_s(a: m256) -> m256d {
     unsafe { transmute(__lasx_xvfcvth_d_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvtl_s_h(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvfcvtl_s_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvtl_d_s(a: m256) -> m256d {
     unsafe { transmute(__lasx_xvfcvtl_d_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftint_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftint_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_wu_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftint_wu_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_lu_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftint_lu_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_wu_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_wu_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_lu_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_lu_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_s_w(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvffint_s_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_d_l(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffint_d_l(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_s_wu(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvffint_s_wu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_d_lu(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffint_d_lu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_b(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_h(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_w(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_d(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4243,98 +4243,98 @@ pub fn lasx_xvpermi_w<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvandn_v(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvandn_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvneg_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvneg_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvneg_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvneg_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvneg_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvneg_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvneg_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvneg_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4343,7 +4343,7 @@ pub fn lasx_xvsllwil_h_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_h_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4352,7 +4352,7 @@ pub fn lasx_xvsllwil_w_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_w_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4361,7 +4361,7 @@ pub fn lasx_xvsllwil_d_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_d_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4370,7 +4370,7 @@ pub fn lasx_xvsllwil_hu_bu<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_hu_bu(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4379,7 +4379,7 @@ pub fn lasx_xvsllwil_wu_hu<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_wu_hu(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4388,217 +4388,217 @@ pub fn lasx_xvsllwil_du_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_du_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsran_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsran_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsran_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrarn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrarn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrarn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrln_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrln_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrln_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlrn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlrn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlrn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4607,7 +4607,7 @@ pub fn lasx_xvfrstpi_b<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstpi_b(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4616,21 +4616,21 @@ pub fn lasx_xvfrstpi_h<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstpi_h(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrstp_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrstp_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4639,7 +4639,7 @@ pub fn lasx_xvshuf4i_d<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4648,7 +4648,7 @@ pub fn lasx_xvbsrl_v<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbsrl_v(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4657,7 +4657,7 @@ pub fn lasx_xvbsll_v<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbsll_v(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4666,7 +4666,7 @@ pub fn lasx_xvextrins_b<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4675,7 +4675,7 @@ pub fn lasx_xvextrins_h<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_h(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4684,7 +4684,7 @@ pub fn lasx_xvextrins_w<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4693,343 +4693,343 @@ pub fn lasx_xvextrins_d<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmadd_s(a: m256, b: m256, c: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmadd_d(a: m256d, b: m256d, c: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmsub_s(a: m256, b: m256, c: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmsub_d(a: m256d, b: m256d, c: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfnmadd_s(a: m256, b: m256, c: m256) -> m256 {
     unsafe { transmute(__lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfnmadd_d(a: m256d, b: m256d, c: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfnmsub_s(a: m256, b: m256, c: m256) -> m256 {
     unsafe { transmute(__lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfnmsub_d(a: m256d, b: m256d, c: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrne_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrne_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrne_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrne_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrp_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrp_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrp_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrp_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrm_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrm_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrm_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrm_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftint_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_s_l(a: m256i, b: m256i) -> m256 {
     unsafe { transmute(__lasx_xvffint_s_l(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrp_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrp_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrm_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrm_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrne_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrne_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftinth_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftinth_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintl_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintl_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffinth_d_w(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffinth_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffintl_d_w(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffintl_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrzh_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrzh_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrzl_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrzl_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrph_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrph_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrpl_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrpl_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrmh_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrmh_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrml_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrml_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrneh_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrneh_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrnel_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrnel_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrne_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrne_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrne_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrne_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrz_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrz_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrz_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrp_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrp_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrp_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrp_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrm_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrm_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrm_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrm_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5038,7 +5038,7 @@ pub unsafe fn lasx_xvld<const IMM_S12: i32>(mem_addr: *const i8) -> m256i {
     transmute(__lasx_xvld(mem_addr, IMM_S12))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5047,7 +5047,7 @@ pub unsafe fn lasx_xvst<const IMM_S12: i32>(a: m256i, mem_addr: *mut i8) {
     transmute(__lasx_xvst(transmute(a), mem_addr, IMM_S12))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5057,7 +5057,7 @@ pub unsafe fn lasx_xvstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m256i, mem_a
     transmute(__lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5067,7 +5067,7 @@ pub unsafe fn lasx_xvstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m256i, mem_a
     transmute(__lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5077,7 +5077,7 @@ pub unsafe fn lasx_xvstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m256i, mem_a
     transmute(__lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5087,7 +5087,7 @@ pub unsafe fn lasx_xvstelm_d<const IMM_S8: i32, const IMM1: u32>(a: m256i, mem_a
     transmute(__lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5096,7 +5096,7 @@ pub fn lasx_xvinsve0_w<const IMM3: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvinsve0_w(transmute(a), transmute(b), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5105,7 +5105,7 @@ pub fn lasx_xvinsve0_d<const IMM2: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvinsve0_d(transmute(a), transmute(b), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5114,7 +5114,7 @@ pub fn lasx_xvpickve_w<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickve_w(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5123,56 +5123,56 @@ pub fn lasx_xvpickve_d<const IMM2: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickve_d(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvorn_v(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvorn_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5181,28 +5181,28 @@ pub fn lasx_xvldi<const IMM_S13: i32>() -> m256i {
     unsafe { transmute(__lasx_xvldi(IMM_S13)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lasx_xvldx(mem_addr: *const i8, b: i64) -> m256i {
     transmute(__lasx_xvldx(mem_addr, transmute(b)))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lasx_xvstx(a: m256i, mem_addr: *mut i8, b: i64) {
     transmute(__lasx_xvstx(transmute(a), mem_addr, transmute(b)))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvextl_qu_du(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextl_qu_du(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5211,7 +5211,7 @@ pub fn lasx_xvinsgr2vr_w<const IMM3: u32>(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvinsgr2vr_w(transmute(a), transmute(b), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5220,126 +5220,126 @@ pub fn lasx_xvinsgr2vr_d<const IMM2: u32>(a: m256i, b: i64) -> m256i {
     unsafe { transmute(__lasx_xvinsgr2vr_d(transmute(a), transmute(b), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_q(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_q(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_h_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_h_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_w_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_w_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_d_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_w_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_w_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_d_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_d_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_d_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_d_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_hu_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_hu_bu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_wu_hu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_wu_hu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_du_wu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_du_wu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_wu_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_wu_bu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_du_hu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_du_hu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_du_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_du_bu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5348,7 +5348,7 @@ pub fn lasx_xvpermi_q<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_q(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5357,14 +5357,14 @@ pub fn lasx_xvpermi_d<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_d(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvperm_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvperm_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5373,7 +5373,7 @@ pub unsafe fn lasx_xvldrepl_b<const IMM_S12: i32>(mem_addr: *const i8) -> m256i
     transmute(__lasx_xvldrepl_b(mem_addr, IMM_S12))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5382,7 +5382,7 @@ pub unsafe fn lasx_xvldrepl_h<const IMM_S11: i32>(mem_addr: *const i8) -> m256i
     transmute(__lasx_xvldrepl_h(mem_addr, IMM_S11))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5391,7 +5391,7 @@ pub unsafe fn lasx_xvldrepl_w<const IMM_S10: i32>(mem_addr: *const i8) -> m256i
     transmute(__lasx_xvldrepl_w(mem_addr, IMM_S10))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5400,7 +5400,7 @@ pub unsafe fn lasx_xvldrepl_d<const IMM_S9: i32>(mem_addr: *const i8) -> m256i {
     transmute(__lasx_xvldrepl_d(mem_addr, IMM_S9))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5409,7 +5409,7 @@ pub fn lasx_xvpickve2gr_w<const IMM3: u32>(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xvpickve2gr_w(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5418,7 +5418,7 @@ pub fn lasx_xvpickve2gr_wu<const IMM3: u32>(a: m256i) -> u32 {
     unsafe { transmute(__lasx_xvpickve2gr_wu(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5427,7 +5427,7 @@ pub fn lasx_xvpickve2gr_d<const IMM2: u32>(a: m256i) -> i64 {
     unsafe { transmute(__lasx_xvpickve2gr_d(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5436,763 +5436,763 @@ pub fn lasx_xvpickve2gr_du<const IMM2: u32>(a: m256i) -> u64 {
     unsafe { transmute(__lasx_xvpickve2gr_du(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_qu_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_qu_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_q_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_d_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_w_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_h_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_q_du(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_d_wu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_w_hu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_h_bu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_q_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_d_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_w_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_h_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_q_du(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_d_wu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_w_hu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_h_bu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_q_du_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_d_wu_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_w_hu_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_q_du_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_d_wu_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_w_hu_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadd_q(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadd_q(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsub_q(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsub_q(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskgez_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskgez_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmsknz_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmsknz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_h_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_h_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_w_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_w_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_d_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_q_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_q_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_hu_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_hu_bu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_wu_hu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_wu_hu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_du_wu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_du_wu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_qu_du(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_qu_du(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6201,7 +6201,7 @@ pub fn lasx_xvrotri_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6210,7 +6210,7 @@ pub fn lasx_xvrotri_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6219,7 +6219,7 @@ pub fn lasx_xvrotri_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6228,14 +6228,14 @@ pub fn lasx_xvrotri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvextl_q_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextl_q_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6244,7 +6244,7 @@ pub fn lasx_xvsrlni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6253,7 +6253,7 @@ pub fn lasx_xvsrlni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6262,7 +6262,7 @@ pub fn lasx_xvsrlni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6271,7 +6271,7 @@ pub fn lasx_xvsrlni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6280,7 +6280,7 @@ pub fn lasx_xvsrlrni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6289,7 +6289,7 @@ pub fn lasx_xvsrlrni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6298,7 +6298,7 @@ pub fn lasx_xvsrlrni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6307,7 +6307,7 @@ pub fn lasx_xvsrlrni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6316,7 +6316,7 @@ pub fn lasx_xvssrlni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6325,7 +6325,7 @@ pub fn lasx_xvssrlni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6334,7 +6334,7 @@ pub fn lasx_xvssrlni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6343,7 +6343,7 @@ pub fn lasx_xvssrlni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6352,7 +6352,7 @@ pub fn lasx_xvssrlni_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6361,7 +6361,7 @@ pub fn lasx_xvssrlni_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6370,7 +6370,7 @@ pub fn lasx_xvssrlni_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6379,7 +6379,7 @@ pub fn lasx_xvssrlni_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6388,7 +6388,7 @@ pub fn lasx_xvssrlrni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6397,7 +6397,7 @@ pub fn lasx_xvssrlrni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6406,7 +6406,7 @@ pub fn lasx_xvssrlrni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6415,7 +6415,7 @@ pub fn lasx_xvssrlrni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6424,7 +6424,7 @@ pub fn lasx_xvssrlrni_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6433,7 +6433,7 @@ pub fn lasx_xvssrlrni_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6442,7 +6442,7 @@ pub fn lasx_xvssrlrni_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6451,7 +6451,7 @@ pub fn lasx_xvssrlrni_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6460,7 +6460,7 @@ pub fn lasx_xvsrani_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6469,7 +6469,7 @@ pub fn lasx_xvsrani_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6478,7 +6478,7 @@ pub fn lasx_xvsrani_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6487,7 +6487,7 @@ pub fn lasx_xvsrani_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6496,7 +6496,7 @@ pub fn lasx_xvsrarni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6505,7 +6505,7 @@ pub fn lasx_xvsrarni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6514,7 +6514,7 @@ pub fn lasx_xvsrarni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6523,7 +6523,7 @@ pub fn lasx_xvsrarni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6532,7 +6532,7 @@ pub fn lasx_xvssrani_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6541,7 +6541,7 @@ pub fn lasx_xvssrani_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6550,7 +6550,7 @@ pub fn lasx_xvssrani_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6559,7 +6559,7 @@ pub fn lasx_xvssrani_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6568,7 +6568,7 @@ pub fn lasx_xvssrani_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6577,7 +6577,7 @@ pub fn lasx_xvssrani_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6586,7 +6586,7 @@ pub fn lasx_xvssrani_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6595,7 +6595,7 @@ pub fn lasx_xvssrani_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6604,7 +6604,7 @@ pub fn lasx_xvssrarni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6613,7 +6613,7 @@ pub fn lasx_xvssrarni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6622,7 +6622,7 @@ pub fn lasx_xvssrarni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6631,7 +6631,7 @@ pub fn lasx_xvssrarni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6640,7 +6640,7 @@ pub fn lasx_xvssrarni_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6649,7 +6649,7 @@ pub fn lasx_xvssrarni_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6658,7 +6658,7 @@ pub fn lasx_xvssrarni_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6667,385 +6667,385 @@ pub fn lasx_xvssrarni_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_b(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_d(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_h(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_v(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_v(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_w(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_b(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_d(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_h(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_v(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_v(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_w(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_caf_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_caf_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_caf_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_caf_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_ceq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_ceq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_ceq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_ceq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cle_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cle_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cle_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cle_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_clt_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_clt_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_clt_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_clt_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cne_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cne_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cne_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cne_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cor_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cor_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cor_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cor_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cueq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cueq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cule_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cule_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cule_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cule_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cult_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cult_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cult_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cult_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cun_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cun_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cune_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cune_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cune_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cune_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cun_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cun_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_saf_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_saf_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_saf_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_saf_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_seq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_seq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_seq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_seq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sle_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sle_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sle_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sle_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_slt_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_slt_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_slt_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_slt_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sne_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sne_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sne_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sne_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sor_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sor_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sor_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sor_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sueq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sueq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sule_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sule_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sule_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sule_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sult_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sult_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sult_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sult_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sun_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sun_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sune_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sune_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sune_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sune_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sun_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sun_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7054,7 +7054,7 @@ pub fn lasx_xvpickve_d_f<const IMM2: u32>(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvpickve_d_f(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7063,7 +7063,7 @@ pub fn lasx_xvpickve_w_f<const IMM3: u32>(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvpickve_w_f(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7072,7 +7072,7 @@ pub fn lasx_xvrepli_b<const IMM_S10: i32>() -> m256i {
     unsafe { transmute(__lasx_xvrepli_b(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7081,7 +7081,7 @@ pub fn lasx_xvrepli_d<const IMM_S10: i32>() -> m256i {
     unsafe { transmute(__lasx_xvrepli_d(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7090,7 +7090,7 @@ pub fn lasx_xvrepli_h<const IMM_S10: i32>() -> m256i {
     unsafe { transmute(__lasx_xvrepli_h(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7099,126 +7099,126 @@ pub fn lasx_xvrepli_w<const IMM_S10: i32>() -> m256i {
     unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_cast_128_s(a: m128) -> m256 {
     unsafe { transmute(__lasx_cast_128_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_cast_128_d(a: m128d) -> m256d {
     unsafe { transmute(__lasx_cast_128_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_cast_128(a: m128i) -> m256i {
     unsafe { transmute(__lasx_cast_128(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 {
     unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d {
     unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i {
     unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_lo_s(a: m256) -> m128 {
     unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_hi_s(a: m256) -> m128 {
     unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_lo_d(a: m256d) -> m128d {
     unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_hi_d(a: m256d) -> m128d {
     unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_lo(a: m256i) -> m128i {
     unsafe { transmute(__lasx_extract_128_lo(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_hi(a: m256i) -> m128i {
     unsafe { transmute(__lasx_extract_128_hi(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 {
     unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 {
     unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d {
     unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d {
     unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i {
     unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i {
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 25efaadb42..679c82079c 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -1453,35 +1453,35 @@ unsafe extern "unadjusted" {
     fn __lsx_vrepli_w(a: i32) -> __v4i32;
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsll_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsll_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsll_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsll_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsll_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsll_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsll_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsll_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1490,7 +1490,7 @@ pub fn lsx_vslli_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslli_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1499,7 +1499,7 @@ pub fn lsx_vslli_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslli_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1508,7 +1508,7 @@ pub fn lsx_vslli_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslli_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1517,35 +1517,35 @@ pub fn lsx_vslli_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslli_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsra_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsra_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsra_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsra_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsra_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsra_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsra_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsra_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1554,7 +1554,7 @@ pub fn lsx_vsrai_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrai_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1563,7 +1563,7 @@ pub fn lsx_vsrai_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrai_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1572,7 +1572,7 @@ pub fn lsx_vsrai_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrai_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1581,35 +1581,35 @@ pub fn lsx_vsrai_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrai_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1618,7 +1618,7 @@ pub fn lsx_vsrari_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1627,7 +1627,7 @@ pub fn lsx_vsrari_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1636,7 +1636,7 @@ pub fn lsx_vsrari_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1645,35 +1645,35 @@ pub fn lsx_vsrari_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrl_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrl_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrl_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrl_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrl_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrl_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrl_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrl_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1682,7 +1682,7 @@ pub fn lsx_vsrli_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrli_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1691,7 +1691,7 @@ pub fn lsx_vsrli_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrli_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1700,7 +1700,7 @@ pub fn lsx_vsrli_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrli_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1709,35 +1709,35 @@ pub fn lsx_vsrli_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrli_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1746,7 +1746,7 @@ pub fn lsx_vsrlri_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1755,7 +1755,7 @@ pub fn lsx_vsrlri_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1764,7 +1764,7 @@ pub fn lsx_vsrlri_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1773,35 +1773,35 @@ pub fn lsx_vsrlri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1810,7 +1810,7 @@ pub fn lsx_vbitclri_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1819,7 +1819,7 @@ pub fn lsx_vbitclri_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1828,7 +1828,7 @@ pub fn lsx_vbitclri_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1837,35 +1837,35 @@ pub fn lsx_vbitclri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1874,7 +1874,7 @@ pub fn lsx_vbitseti_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1883,7 +1883,7 @@ pub fn lsx_vbitseti_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1892,7 +1892,7 @@ pub fn lsx_vbitseti_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1901,35 +1901,35 @@ pub fn lsx_vbitseti_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1938,7 +1938,7 @@ pub fn lsx_vbitrevi_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1947,7 +1947,7 @@ pub fn lsx_vbitrevi_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1956,7 +1956,7 @@ pub fn lsx_vbitrevi_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1965,35 +1965,35 @@ pub fn lsx_vbitrevi_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadd_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadd_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadd_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadd_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadd_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadd_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadd_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2002,7 +2002,7 @@ pub fn lsx_vaddi_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddi_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2011,7 +2011,7 @@ pub fn lsx_vaddi_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddi_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2020,7 +2020,7 @@ pub fn lsx_vaddi_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddi_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2029,35 +2029,35 @@ pub fn lsx_vaddi_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddi_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsub_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsub_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsub_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsub_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsub_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsub_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsub_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsub_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2066,7 +2066,7 @@ pub fn lsx_vsubi_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2075,7 +2075,7 @@ pub fn lsx_vsubi_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2084,7 +2084,7 @@ pub fn lsx_vsubi_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2093,35 +2093,35 @@ pub fn lsx_vsubi_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2130,7 +2130,7 @@ pub fn lsx_vmaxi_b<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2139,7 +2139,7 @@ pub fn lsx_vmaxi_h<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2148,7 +2148,7 @@ pub fn lsx_vmaxi_w<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2157,35 +2157,35 @@ pub fn lsx_vmaxi_d<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmax_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmax_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2194,7 +2194,7 @@ pub fn lsx_vmaxi_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2203,7 +2203,7 @@ pub fn lsx_vmaxi_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2212,7 +2212,7 @@ pub fn lsx_vmaxi_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2221,35 +2221,35 @@ pub fn lsx_vmaxi_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaxi_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2258,7 +2258,7 @@ pub fn lsx_vmini_b<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2267,7 +2267,7 @@ pub fn lsx_vmini_h<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2276,7 +2276,7 @@ pub fn lsx_vmini_w<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2285,35 +2285,35 @@ pub fn lsx_vmini_d<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmin_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmin_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2322,7 +2322,7 @@ pub fn lsx_vmini_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2331,7 +2331,7 @@ pub fn lsx_vmini_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2340,7 +2340,7 @@ pub fn lsx_vmini_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2349,35 +2349,35 @@ pub fn lsx_vmini_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmini_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vseq_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vseq_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vseq_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vseq_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vseq_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vseq_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vseq_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vseq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2386,7 +2386,7 @@ pub fn lsx_vseqi_b<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vseqi_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2395,7 +2395,7 @@ pub fn lsx_vseqi_h<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vseqi_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2404,7 +2404,7 @@ pub fn lsx_vseqi_w<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vseqi_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2413,7 +2413,7 @@ pub fn lsx_vseqi_d<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vseqi_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2422,35 +2422,35 @@ pub fn lsx_vslti_b<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2459,7 +2459,7 @@ pub fn lsx_vslti_h<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2468,7 +2468,7 @@ pub fn lsx_vslti_w<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2477,35 +2477,35 @@ pub fn lsx_vslti_d<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vslt_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vslt_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2514,7 +2514,7 @@ pub fn lsx_vslti_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2523,7 +2523,7 @@ pub fn lsx_vslti_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2532,7 +2532,7 @@ pub fn lsx_vslti_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2541,35 +2541,35 @@ pub fn lsx_vslti_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslti_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2578,7 +2578,7 @@ pub fn lsx_vslei_b<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_b(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2587,7 +2587,7 @@ pub fn lsx_vslei_h<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_h(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2596,7 +2596,7 @@ pub fn lsx_vslei_w<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_w(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2605,35 +2605,35 @@ pub fn lsx_vslei_d<const IMM_S5: i32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_d(transmute(a), IMM_S5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsle_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsle_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2642,7 +2642,7 @@ pub fn lsx_vslei_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_bu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2651,7 +2651,7 @@ pub fn lsx_vslei_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_hu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2660,7 +2660,7 @@ pub fn lsx_vslei_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2669,7 +2669,7 @@ pub fn lsx_vslei_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vslei_du(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2678,7 +2678,7 @@ pub fn lsx_vsat_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2687,7 +2687,7 @@ pub fn lsx_vsat_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2696,7 +2696,7 @@ pub fn lsx_vsat_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2705,7 +2705,7 @@ pub fn lsx_vsat_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2714,7 +2714,7 @@ pub fn lsx_vsat_bu<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2723,7 +2723,7 @@ pub fn lsx_vsat_hu<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2732,7 +2732,7 @@ pub fn lsx_vsat_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2741,623 +2741,623 @@ pub fn lsx_vsat_du<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmul_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmul_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmul_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmul_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmul_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmul_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmul_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmul_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmadd_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmadd_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmadd_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmadd_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmsub_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmsub_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmsub_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmsub_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vdiv_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vdiv_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmod_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmod_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3366,7 +3366,7 @@ pub fn lsx_vreplvei_b<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3375,7 +3375,7 @@ pub fn lsx_vreplvei_h<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3384,7 +3384,7 @@ pub fn lsx_vreplvei_w<const IMM2: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_w(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3393,203 +3393,203 @@ pub fn lsx_vreplvei_d<const IMM1: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vand_v(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vand_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3598,14 +3598,14 @@ pub fn lsx_vandi_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vor_v(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vor_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3614,14 +3614,14 @@ pub fn lsx_vori_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vnor_v(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vnor_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3630,14 +3630,14 @@ pub fn lsx_vnori_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vxor_v(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vxor_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3646,14 +3646,14 @@ pub fn lsx_vxori_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3662,7 +3662,7 @@ pub fn lsx_vbitseli_b<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3671,7 +3671,7 @@ pub fn lsx_vshuf4i_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3680,7 +3680,7 @@ pub fn lsx_vshuf4i_h<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3689,119 +3689,119 @@ pub fn lsx_vshuf4i_w<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplgr2vr_b(a: i32) -> m128i {
     unsafe { transmute(__lsx_vreplgr2vr_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplgr2vr_h(a: i32) -> m128i {
     unsafe { transmute(__lsx_vreplgr2vr_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplgr2vr_w(a: i32) -> m128i {
     unsafe { transmute(__lsx_vreplgr2vr_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplgr2vr_d(a: i64) -> m128i {
     unsafe { transmute(__lsx_vreplgr2vr_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpcnt_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vpcnt_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpcnt_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vpcnt_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpcnt_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vpcnt_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpcnt_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vpcnt_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclz_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclz_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclz_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclz_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3810,7 +3810,7 @@ pub fn lsx_vpickve2gr_b<const IMM4: u32>(a: m128i) -> i32 {
     unsafe { transmute(__lsx_vpickve2gr_b(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3819,7 +3819,7 @@ pub fn lsx_vpickve2gr_h<const IMM3: u32>(a: m128i) -> i32 {
     unsafe { transmute(__lsx_vpickve2gr_h(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3828,7 +3828,7 @@ pub fn lsx_vpickve2gr_w<const IMM2: u32>(a: m128i) -> i32 {
     unsafe { transmute(__lsx_vpickve2gr_w(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3837,7 +3837,7 @@ pub fn lsx_vpickve2gr_d<const IMM1: u32>(a: m128i) -> i64 {
     unsafe { transmute(__lsx_vpickve2gr_d(transmute(a), IMM1)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3846,7 +3846,7 @@ pub fn lsx_vpickve2gr_bu<const IMM4: u32>(a: m128i) -> u32 {
     unsafe { transmute(__lsx_vpickve2gr_bu(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3855,7 +3855,7 @@ pub fn lsx_vpickve2gr_hu<const IMM3: u32>(a: m128i) -> u32 {
     unsafe { transmute(__lsx_vpickve2gr_hu(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3864,7 +3864,7 @@ pub fn lsx_vpickve2gr_wu<const IMM2: u32>(a: m128i) -> u32 {
     unsafe { transmute(__lsx_vpickve2gr_wu(transmute(a), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3873,7 +3873,7 @@ pub fn lsx_vpickve2gr_du<const IMM1: u32>(a: m128i) -> u64 {
     unsafe { transmute(__lsx_vpickve2gr_du(transmute(a), IMM1)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3882,7 +3882,7 @@ pub fn lsx_vinsgr2vr_b<const IMM4: u32>(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vinsgr2vr_b(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3891,7 +3891,7 @@ pub fn lsx_vinsgr2vr_h<const IMM3: u32>(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vinsgr2vr_h(transmute(a), transmute(b), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3900,7 +3900,7 @@ pub fn lsx_vinsgr2vr_w<const IMM2: u32>(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vinsgr2vr_w(transmute(a), transmute(b), IMM2)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3909,448 +3909,448 @@ pub fn lsx_vinsgr2vr_d<const IMM1: u32>(a: m128i, b: i64) -> m128i {
     unsafe { transmute(__lsx_vinsgr2vr_d(transmute(a), transmute(b), IMM1)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfadd_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfadd_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfadd_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfsub_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfsub_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfsub_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfsub_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmul_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmul_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmul_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmul_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfdiv_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfdiv_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfdiv_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfdiv_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvt_h_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcvt_h_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvt_s_d(a: m128d, b: m128d) -> m128 {
     unsafe { transmute(__lsx_vfcvt_s_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmin_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmin_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmin_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmin_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmina_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmina_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmina_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmina_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmax_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmax_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmax_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmax_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmaxa_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmaxa_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmaxa_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmaxa_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfclass_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vfclass_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfclass_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vfclass_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfsqrt_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfsqrt_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfsqrt_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfsqrt_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecip_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrecip_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecip_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrecip_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecipe_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrecipe_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecipe_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrecipe_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrte_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrsqrte_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrte_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrsqrte_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrint_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrint_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrint_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrint_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrt_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrsqrt_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrt_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrsqrt_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vflogb_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vflogb_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vflogb_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vflogb_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvth_s_h(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vfcvth_s_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvth_d_s(a: m128) -> m128d {
     unsafe { transmute(__lsx_vfcvth_d_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvtl_s_h(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vfcvtl_s_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvtl_d_s(a: m128) -> m128d {
     unsafe { transmute(__lsx_vfcvtl_d_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftint_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftint_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_wu_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftint_wu_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_lu_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftint_lu_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrz_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrz_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_wu_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrz_wu_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_lu_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrz_lu_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_s_w(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vffint_s_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_d_l(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffint_d_l(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_s_wu(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vffint_s_wu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_d_lu(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vandn_v(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vandn_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vneg_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vneg_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vneg_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vneg_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vneg_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vneg_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vneg_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vneg_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4359,7 +4359,7 @@ pub fn lsx_vsllwil_h_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_h_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4368,7 +4368,7 @@ pub fn lsx_vsllwil_w_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_w_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4377,7 +4377,7 @@ pub fn lsx_vsllwil_d_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_d_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4386,7 +4386,7 @@ pub fn lsx_vsllwil_hu_bu<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_hu_bu(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4395,7 +4395,7 @@ pub fn lsx_vsllwil_wu_hu<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_wu_hu(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4404,217 +4404,217 @@ pub fn lsx_vsllwil_du_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_du_wu(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsran_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsran_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsran_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrarn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrarn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrarn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrln_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrln_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrln_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlrn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlrn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlrn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4623,7 +4623,7 @@ pub fn lsx_vfrstpi_b<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstpi_b(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4632,21 +4632,21 @@ pub fn lsx_vfrstpi_h<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstpi_h(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrstp_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstp_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrstp_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4655,7 +4655,7 @@ pub fn lsx_vshuf4i_d<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4664,7 +4664,7 @@ pub fn lsx_vbsrl_v<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbsrl_v(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4673,7 +4673,7 @@ pub fn lsx_vbsll_v<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbsll_v(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4682,7 +4682,7 @@ pub fn lsx_vextrins_b<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4691,7 +4691,7 @@ pub fn lsx_vextrins_h<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_h(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4700,7 +4700,7 @@ pub fn lsx_vextrins_w<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4709,343 +4709,343 @@ pub fn lsx_vextrins_d<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmadd_s(a: m128, b: m128, c: m128) -> m128 {
     unsafe { transmute(__lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmadd_d(a: m128d, b: m128d, c: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmsub_s(a: m128, b: m128, c: m128) -> m128 {
     unsafe { transmute(__lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmsub_d(a: m128d, b: m128d, c: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfnmadd_s(a: m128, b: m128, c: m128) -> m128 {
     unsafe { transmute(__lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfnmadd_d(a: m128d, b: m128d, c: m128d) -> m128d {
     unsafe { transmute(__lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfnmsub_s(a: m128, b: m128, c: m128) -> m128 {
     unsafe { transmute(__lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfnmsub_d(a: m128d, b: m128d, c: m128d) -> m128d {
     unsafe { transmute(__lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrne_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrne_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrne_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrne_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrp_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrp_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrp_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrp_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrm_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrm_w_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrm_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrm_l_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftint_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_s_l(a: m128i, b: m128i) -> m128 {
     unsafe { transmute(__lsx_vffint_s_l(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrz_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrp_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrp_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrm_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrm_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrne_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrne_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintl_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintl_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftinth_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftinth_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffinth_d_w(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffinth_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffintl_d_w(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffintl_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrzl_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrzl_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrzh_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrzh_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrpl_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrpl_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrph_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrph_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrml_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrml_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrmh_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrmh_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrnel_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrnel_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrneh_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrneh_l_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrne_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrne_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrne_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrne_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrz_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrz_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrz_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrp_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrp_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrp_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrp_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrm_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrm_s(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrm_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrm_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5055,7 +5055,7 @@ pub unsafe fn lsx_vstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m128i, mem_add
     transmute(__lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5065,7 +5065,7 @@ pub unsafe fn lsx_vstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m128i, mem_add
     transmute(__lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5075,7 +5075,7 @@ pub unsafe fn lsx_vstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m128i, mem_add
     transmute(__lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5085,693 +5085,693 @@ pub unsafe fn lsx_vstelm_d<const IMM_S8: i32, const IMM1: u32>(a: m128i, mem_add
     transmute(__lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_qu_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_qu_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_d_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_w_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_h_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_d_wu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_w_hu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_h_bu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_d_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_w_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_h_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_d_wu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_w_hu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_h_bu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_d_wu_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_w_hu_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_h_bu_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_d_wu_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_w_hu_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_h_bu_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_q_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_q_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_q_du(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_q_du(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_b(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadd_q(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadd_q(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsub_q(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsub_q(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5780,7 +5780,7 @@ pub unsafe fn lsx_vldrepl_b<const IMM_S12: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_b(mem_addr, IMM_S12))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5789,7 +5789,7 @@ pub unsafe fn lsx_vldrepl_h<const IMM_S11: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_h(mem_addr, IMM_S11))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5798,7 +5798,7 @@ pub unsafe fn lsx_vldrepl_w<const IMM_S10: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_w(mem_addr, IMM_S10))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5807,77 +5807,77 @@ pub unsafe fn lsx_vldrepl_d<const IMM_S9: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_d(mem_addr, IMM_S9))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskgez_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskgez_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmsknz_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmsknz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_h_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_h_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_w_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_w_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_d_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_d_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_q_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_q_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_hu_bu(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_hu_bu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_wu_hu(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_wu_hu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_du_wu(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_du_wu(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_qu_du(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_qu_du(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5886,7 +5886,7 @@ pub fn lsx_vrotri_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_b(transmute(a), IMM3)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5895,7 +5895,7 @@ pub fn lsx_vrotri_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_h(transmute(a), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5904,7 +5904,7 @@ pub fn lsx_vrotri_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_w(transmute(a), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5913,14 +5913,14 @@ pub fn lsx_vrotri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vextl_q_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vextl_q_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5929,7 +5929,7 @@ pub fn lsx_vsrlni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5938,7 +5938,7 @@ pub fn lsx_vsrlni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5947,7 +5947,7 @@ pub fn lsx_vsrlni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5956,7 +5956,7 @@ pub fn lsx_vsrlni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5965,7 +5965,7 @@ pub fn lsx_vsrlrni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5974,7 +5974,7 @@ pub fn lsx_vsrlrni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5983,7 +5983,7 @@ pub fn lsx_vsrlrni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5992,7 +5992,7 @@ pub fn lsx_vsrlrni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6001,7 +6001,7 @@ pub fn lsx_vssrlni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6010,7 +6010,7 @@ pub fn lsx_vssrlni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6019,7 +6019,7 @@ pub fn lsx_vssrlni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6028,7 +6028,7 @@ pub fn lsx_vssrlni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6037,7 +6037,7 @@ pub fn lsx_vssrlni_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6046,7 +6046,7 @@ pub fn lsx_vssrlni_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6055,7 +6055,7 @@ pub fn lsx_vssrlni_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6064,7 +6064,7 @@ pub fn lsx_vssrlni_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6073,7 +6073,7 @@ pub fn lsx_vssrlrni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6082,7 +6082,7 @@ pub fn lsx_vssrlrni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6091,7 +6091,7 @@ pub fn lsx_vssrlrni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6100,7 +6100,7 @@ pub fn lsx_vssrlrni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6109,7 +6109,7 @@ pub fn lsx_vssrlrni_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6118,7 +6118,7 @@ pub fn lsx_vssrlrni_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6127,7 +6127,7 @@ pub fn lsx_vssrlrni_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6136,7 +6136,7 @@ pub fn lsx_vssrlrni_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6145,7 +6145,7 @@ pub fn lsx_vsrani_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6154,7 +6154,7 @@ pub fn lsx_vsrani_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6163,7 +6163,7 @@ pub fn lsx_vsrani_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6172,7 +6172,7 @@ pub fn lsx_vsrani_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6181,7 +6181,7 @@ pub fn lsx_vsrarni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6190,7 +6190,7 @@ pub fn lsx_vsrarni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6199,7 +6199,7 @@ pub fn lsx_vsrarni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6208,7 +6208,7 @@ pub fn lsx_vsrarni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6217,7 +6217,7 @@ pub fn lsx_vssrani_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6226,7 +6226,7 @@ pub fn lsx_vssrani_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6235,7 +6235,7 @@ pub fn lsx_vssrani_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6244,7 +6244,7 @@ pub fn lsx_vssrani_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6253,7 +6253,7 @@ pub fn lsx_vssrani_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6262,7 +6262,7 @@ pub fn lsx_vssrani_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6271,7 +6271,7 @@ pub fn lsx_vssrani_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6280,7 +6280,7 @@ pub fn lsx_vssrani_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6289,7 +6289,7 @@ pub fn lsx_vssrarni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6298,7 +6298,7 @@ pub fn lsx_vssrarni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6307,7 +6307,7 @@ pub fn lsx_vssrarni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6316,7 +6316,7 @@ pub fn lsx_vssrarni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6325,7 +6325,7 @@ pub fn lsx_vssrarni_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6334,7 +6334,7 @@ pub fn lsx_vssrarni_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6343,7 +6343,7 @@ pub fn lsx_vssrarni_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6352,7 +6352,7 @@ pub fn lsx_vssrarni_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6361,7 +6361,7 @@ pub fn lsx_vpermi_w<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpermi_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6370,7 +6370,7 @@ pub unsafe fn lsx_vld<const IMM_S12: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vld(mem_addr, IMM_S12))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6379,56 +6379,56 @@ pub unsafe fn lsx_vst<const IMM_S12: i32>(a: m128i, mem_addr: *mut i8) {
     transmute(__lsx_vst(transmute(a), mem_addr, IMM_S12))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vorn_v(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vorn_v(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6437,413 +6437,413 @@ pub fn lsx_vldi<const IMM_S13: i32>() -> m128i {
     unsafe { transmute(__lsx_vldi(IMM_S13)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lsx_vldx(mem_addr: *const i8, b: i64) -> m128i {
     transmute(__lsx_vldx(mem_addr, transmute(b)))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lsx_vstx(a: m128i, mem_addr: *mut i8, b: i64) {
     transmute(__lsx_vstx(transmute(a), mem_addr, transmute(b)))
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vextl_qu_du(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vextl_qu_du(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_b(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_d(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_h(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_v(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_v(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_w(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_b(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_b(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_d(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_d(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_h(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_h(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_v(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_v(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_w(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_w(transmute(a))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_caf_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_caf_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_caf_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_caf_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_ceq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_ceq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_ceq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_ceq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cle_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cle_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cle_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cle_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_clt_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_clt_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_clt_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_clt_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cne_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cne_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cne_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cne_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cor_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cor_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cor_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cor_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cueq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cueq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cule_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cule_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cule_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cule_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cult_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cult_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cult_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cult_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cun_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cun_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cune_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cune_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cune_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cune_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cun_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cun_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_saf_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_saf_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_saf_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_saf_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_seq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_seq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_seq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_seq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sle_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sle_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sle_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sle_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_slt_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_slt_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_slt_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_slt_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sne_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sne_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sne_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sne_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sor_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sor_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sor_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sor_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sueq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sueq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sule_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sule_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sule_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sule_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sult_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sult_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sult_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sult_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sun_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sun_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sune_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sune_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sune_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sune_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sun_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sun_s(transmute(a), transmute(b))) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6852,7 +6852,7 @@ pub fn lsx_vrepli_b<const IMM_S10: i32>() -> m128i {
     unsafe { transmute(__lsx_vrepli_b(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6861,7 +6861,7 @@ pub fn lsx_vrepli_d<const IMM_S10: i32>() -> m128i {
     unsafe { transmute(__lsx_vrepli_d(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6870,7 +6870,7 @@ pub fn lsx_vrepli_h<const IMM_S10: i32>() -> m128i {
     unsafe { transmute(__lsx_vrepli_h(IMM_S10)) }
 }
 
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/mod.rs b/crates/core_arch/src/loongarch64/mod.rs
index ab968aff20..41c21aac2a 100644
--- a/crates/core_arch/src/loongarch64/mod.rs
+++ b/crates/core_arch/src/loongarch64/mod.rs
@@ -11,7 +11,7 @@ pub use self::lsx::*;
 use crate::arch::asm;
 
 /// Reads the 64-bit stable counter value and the counter ID
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn rdtime_d() -> (i64, isize) {
     let (val, tid): (i64, isize);
@@ -48,21 +48,21 @@ unsafe extern "unadjusted" {
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crc_w_d_w(a: i64, b: i32) -> i32 {
     unsafe { __crc_w_d_w(a, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crcc_w_d_w(a: i64, b: i32) -> i32 {
     unsafe { __crcc_w_d_w(a, b) }
 }
 
 /// Generates the cache operation instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn cacop<const IMM5: i64, const IMM_S12: i64>(b: i64) {
     static_assert_uimm_bits!(IMM5, 5);
@@ -71,7 +71,7 @@ pub unsafe fn cacop<const IMM5: i64, const IMM_S12: i64>(b: i64) {
 }
 
 /// Reads the CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -79,7 +79,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
 }
 
 /// Writes the CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -87,7 +87,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
 }
 
 /// Exchanges the CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -95,35 +95,35 @@ pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {
 }
 
 /// Reads the 64-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrrd_d(a: i32) -> i64 {
     __iocsrrd_d(a)
 }
 
 /// Writes the 64-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrwr_d(a: i64, b: i32) {
     __iocsrwr_d(a, b)
 }
 
 /// Generates the less-than-or-equal asseration instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn asrtle(a: i64, b: i64) {
     __asrtle(a, b);
 }
 
 /// Generates the greater-than asseration instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn asrtgt(a: i64, b: i64) {
     __asrtgt(a, b);
 }
 
 /// Loads the page table directory entry
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lddir<const IMM8: i64>(a: i64) -> i64 {
@@ -132,7 +132,7 @@ pub unsafe fn lddir<const IMM8: i64>(a: i64) -> i64 {
 }
 
 /// Loads the page table entry
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn ldpte<const IMM8: i64>(a: i64) {
diff --git a/crates/core_arch/src/loongarch_shared/mod.rs b/crates/core_arch/src/loongarch_shared/mod.rs
index 8991fe8576..b2a67fb609 100644
--- a/crates/core_arch/src/loongarch_shared/mod.rs
+++ b/crates/core_arch/src/loongarch_shared/mod.rs
@@ -3,7 +3,7 @@
 use crate::arch::asm;
 
 /// Reads the lower 32-bit stable counter value and the counter ID
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn rdtimel_w() -> (i32, isize) {
     let (val, tid): (i32, isize);
@@ -12,7 +12,7 @@ pub fn rdtimel_w() -> (i32, isize) {
 }
 
 /// Reads the upper 32-bit stable counter value and the counter ID
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn rdtimeh_w() -> (i32, isize) {
     let (val, tid): (i32, isize);
@@ -71,49 +71,49 @@ unsafe extern "unadjusted" {
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crc_w_b_w(a: i32, b: i32) -> i32 {
     unsafe { __crc_w_b_w(a, b) }
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crc_w_h_w(a: i32, b: i32) -> i32 {
     unsafe { __crc_w_h_w(a, b) }
 }
 
 /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crc_w_w_w(a: i32, b: i32) -> i32 {
     unsafe { __crc_w_w_w(a, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crcc_w_b_w(a: i32, b: i32) -> i32 {
     unsafe { __crcc_w_b_w(a, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crcc_w_h_w(a: i32, b: i32) -> i32 {
     unsafe { __crcc_w_h_w(a, b) }
 }
 
 /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
     unsafe { __crcc_w_w_w(a, b) }
 }
 
 /// Generates the memory barrier instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn dbar<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -121,7 +121,7 @@ pub fn dbar<const IMM15: i32>() {
 }
 
 /// Generates the instruction-fetch barrier instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn ibar<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -129,7 +129,7 @@ pub fn ibar<const IMM15: i32>() {
 }
 
 /// Moves data from a GPR to the FCSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn movgr2fcsr<const IMM2: i32>(a: i32) {
     static_assert_uimm_bits!(IMM2, 2);
@@ -137,7 +137,7 @@ pub unsafe fn movgr2fcsr<const IMM2: i32>(a: i32) {
 }
 
 /// Moves data from a FCSR to the GPR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn movfcsr2gr<const IMM2: i32>() -> i32 {
     static_assert_uimm_bits!(IMM2, 2);
@@ -145,49 +145,49 @@ pub fn movfcsr2gr<const IMM2: i32>() -> i32 {
 }
 
 /// Reads the 8-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrrd_b(a: i32) -> i32 {
     __iocsrrd_b(a)
 }
 
 /// Reads the 16-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrrd_h(a: i32) -> i32 {
     __iocsrrd_h(a)
 }
 
 /// Reads the 32-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrrd_w(a: i32) -> i32 {
     __iocsrrd_w(a)
 }
 
 /// Writes the 8-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrwr_b(a: i32, b: i32) {
     __iocsrwr_b(a, b)
 }
 
 /// Writes the 16-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrwr_h(a: i32, b: i32) {
     __iocsrwr_h(a, b)
 }
 
 /// Writes the 32-bit IO-CSR
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn iocsrwr_w(a: i32, b: i32) {
     __iocsrwr_w(a, b)
 }
 
 /// Generates the breakpoint instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn brk<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -195,14 +195,14 @@ pub unsafe fn brk<const IMM15: i32>() {
 }
 
 /// Reads the CPU configuration register
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn cpucfg(a: i32) -> i32 {
     unsafe { __cpucfg(a) }
 }
 
 /// Generates the syscall instruction
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn syscall<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -210,7 +210,7 @@ pub unsafe fn syscall<const IMM15: i32>() {
 }
 
 /// Calculate the approximate single-precision result of 1.0 divided
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frecipe_s(a: f32) -> f32 {
@@ -218,7 +218,7 @@ pub fn frecipe_s(a: f32) -> f32 {
 }
 
 /// Calculate the approximate double-precision result of 1.0 divided
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frecipe_d(a: f64) -> f64 {
@@ -226,7 +226,7 @@ pub fn frecipe_d(a: f64) -> f64 {
 }
 
 /// Calculate the approximate single-precision result of dividing 1.0 by the square root
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frsqrte_s(a: f32) -> f32 {
@@ -234,7 +234,7 @@ pub fn frsqrte_s(a: f32) -> f32 {
 }
 
 /// Calculate the approximate double-precision result of dividing 1.0 by the square root
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frsqrte_d(a: f64) -> f64 {
diff --git a/crates/stdarch-gen-loongarch/src/main.rs b/crates/stdarch-gen-loongarch/src/main.rs
index 10b87c70e9..fdc9b2b6bc 100644
--- a/crates/stdarch-gen-loongarch/src/main.rs
+++ b/crates/stdarch-gen-loongarch/src/main.rs
@@ -597,7 +597,7 @@ fn gen_bind_body(
     let function = if !rustc_legacy_const_generics.is_empty() {
         format!(
             r#"
-#[inline]{target_feature}
+#[inline(always)]{target_feature}
 #[{rustc_legacy_const_generics}]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 {fn_decl}{{
@@ -609,7 +609,7 @@ fn gen_bind_body(
     } else {
         format!(
             r#"
-#[inline]{target_feature}
+#[inline(always)]{target_feature}
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 {fn_decl}{{
     {call_params}

From 7e32fbc0a37258f6f28d154b973a0629b950dd5a Mon Sep 17 00:00:00 2001
From: Jynn Nelson <jynn.nelson@ferrous-systems.com>
Date: Thu, 19 Mar 2026 13:43:40 +0100
Subject: [PATCH 209/326] Add more docs on how to run the generator

- Note that working directory matters
- Note that stdarch-gen-arm uses nightly
- Fix missing directory. Without this, it would print to stdout in one
  giant merged file.
---
 crates/stdarch-gen-arm/README.md | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/crates/stdarch-gen-arm/README.md b/crates/stdarch-gen-arm/README.md
index 4da14bcbb6..64f1183f1d 100644
--- a/crates/stdarch-gen-arm/README.md
+++ b/crates/stdarch-gen-arm/README.md
@@ -1,11 +1,11 @@
 # stdarch-gen-arm generator guide
 ## Running the generator
-- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec`
-```
-$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
-    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s
-     Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec`
-```
+
+Run: `cargo +nightly run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec crates/core_arch/src`
+
+NOTE: If you are running this from rust-lang/rust, you must be in the `library/stdarch`
+working directory.
+
 ## Input/Output
 ### Input files (intrinsic YAML definitions)
  - `crates/stdarch-gen-arm/spec/<feature>/*.spec.yml`

From 4289c08406a0d594bce51ec7f5d2927cb4132f7e Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Sun, 22 Mar 2026 19:50:07 +0000
Subject: [PATCH 210/326] Use const fn and remove unsafe from alias test
 wrappers

---
 crates/core_arch/src/x86/sse.rs | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 11fb3a865b..4d052186bc 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3011,12 +3011,12 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtss_si32() {
+    fn test_mm_cvtss_si32() {
         test_mm_cvtss_si32_impl!(_mm_cvtss_si32);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvt_ss2si() {
+    fn test_mm_cvt_ss2si() {
         test_mm_cvtss_si32_impl!(_mm_cvt_ss2si);
     }
 
@@ -3043,12 +3043,12 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvttss_si32() {
+    fn test_mm_cvttss_si32() {
         test_cvttss_si32_impl!(_mm_cvttss_si32);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtt_ss2si() {
+    fn test_mm_cvtt_ss2si() {
         test_cvttss_si32_impl!(_mm_cvtt_ss2si);
     }
 
@@ -3071,12 +3071,12 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvtsi32_ss() {
+    fn test_mm_cvtsi32_ss() {
         test_mm_cvtsi32_ss_impl!(_mm_cvtsi32_ss);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cvt_si2ss() {
+    fn test_mm_cvt_si2ss() {
         test_mm_cvtsi32_ss_impl!(_mm_cvt_si2ss);
     }
 
@@ -3103,12 +3103,12 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_set1_ps() {
+    const fn test_mm_set1_ps() {
         test_mm_set1_ps_impl!(_mm_set1_ps);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_set_ps1() {
+    const fn test_mm_set_ps1() {
         test_mm_set1_ps_impl!(_mm_set_ps1);
     }
 
@@ -3201,18 +3201,18 @@ mod tests {
     macro_rules! test_mm_load1_ps_impl {
         ($alias:ident) => {
             let a = 42.0f32;
-            let r = $alias(ptr::addr_of!(a));
+            let r = unsafe { $alias(ptr::addr_of!(a)) };
             assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
         };
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_load1_ps() {
+    fn test_mm_load1_ps() {
         test_mm_load1_ps_impl!(_mm_load1_ps);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_load_ps1() {
+    fn test_mm_load_ps1() {
         test_mm_load1_ps_impl!(_mm_load_ps1);
     }
 
@@ -3270,18 +3270,18 @@ mod tests {
             let mut vals = Memory { data: [0.0f32; 4] };
             let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
             let p = vals.data.as_mut_ptr();
-            $alias(p, *black_box(&a));
+            unsafe { $alias(p, *black_box(&a)) };
             assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
         };
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_store1_ps() {
+    fn test_mm_store1_ps() {
         test_mm_store1_ps_impl!(_mm_store1_ps);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_store_ps1() {
+    fn test_mm_store_ps1() {
         test_mm_store1_ps_impl!(_mm_store_ps1);
     }
 

From c2ec4acc7a6632473044c923394ab35400bd9ee2 Mon Sep 17 00:00:00 2001
From: Flakebi <flakebi@t-online.de>
Date: Tue, 24 Mar 2026 10:58:31 +0100
Subject: [PATCH 211/326] Document convergent limitation on intrinsics

---
 .../src/amdgpu/intrinsic_is_convergent.md     |  6 ++
 crates/core_arch/src/amdgpu/mod.rs            | 72 +++++++++++++++++++
 crates/core_arch/src/nvptx/mod.rs             |  2 +
 3 files changed, 80 insertions(+)
 create mode 100644 crates/core_arch/src/amdgpu/intrinsic_is_convergent.md

diff --git a/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md b/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md
new file mode 100644
index 0000000000..1bc8899d33
--- /dev/null
+++ b/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md
@@ -0,0 +1,6 @@
+This intrinsic does not behave like a normal function call; it is a "[convergent]" operation and as such has non-standard control-flow effects which need special treatment by the language.
+Rust currently does not properly support convergent operations.
+This operation is hence provided on a best-effort basis.
+Using it may result in incorrect code under some circumstances.
+
+[convergent]: https://llvm.org/docs/ConvergentOperations.html
diff --git a/crates/core_arch/src/amdgpu/mod.rs b/crates/core_arch/src/amdgpu/mod.rs
index 40274e4d79..374f582696 100644
--- a/crates/core_arch/src/amdgpu/mod.rs
+++ b/crates/core_arch/src/amdgpu/mod.rs
@@ -244,6 +244,8 @@ pub fn wavefrontsize() -> u32 {
 /// Synchronize all wavefronts in a workgroup.
 ///
 /// Each wavefronts in a workgroup waits at the barrier until all wavefronts in the workgroup arrive at a barrier.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn s_barrier() {
@@ -253,6 +255,8 @@ pub fn s_barrier() {
 /// Signal a specific barrier type.
 ///
 /// Only for non-named barriers.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn s_barrier_signal<const BARRIER_TYPE: i32>() {
@@ -265,6 +269,8 @@ pub unsafe fn s_barrier_signal<const BARRIER_TYPE: i32>() {
 /// Provides access to the s_barrier_signal_first instruction;
 /// additionally ensures that the result value is valid even when
 /// the intrinsic is used from a wavefront that is not running in a workgroup.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn s_barrier_signal_isfirst<const BARRIER_TYPE: i32>() -> bool {
@@ -274,6 +280,8 @@ pub unsafe fn s_barrier_signal_isfirst<const BARRIER_TYPE: i32>() -> bool {
 /// Wait for a specific barrier type.
 ///
 /// Only for non-named barriers.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn s_barrier_wait<const BARRIER_TYPE: i16>() {
@@ -283,6 +291,8 @@ pub unsafe fn s_barrier_wait<const BARRIER_TYPE: i16>() {
 /// Get the state of a specific barrier type.
 ///
 /// The `barrier_type` argument must be uniform, otherwise behavior is undefined.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn s_get_barrier_state<const BARRIER_TYPE: i32>() -> u32 {
@@ -292,6 +302,8 @@ pub unsafe fn s_get_barrier_state<const BARRIER_TYPE: i32>() -> u32 {
 /// A barrier for only the threads within the current wavefront.
 ///
 /// Does not result in an instruction but restricts the compiler.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_barrier() {
@@ -315,6 +327,8 @@ pub fn wave_barrier() {
 /// - 0x0100: All DS read instructions may be scheduled across `sched_barrier`.
 /// - 0x0200: All DS write instructions may be scheduled across `sched_barrier`.
 /// - 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across `sched_barrier`.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn sched_barrier<const MASK: u32>() {
@@ -345,6 +359,8 @@ pub unsafe fn sched_barrier<const MASK: u32>() {
 /// // 5 MFMA
 /// sched_group_barrier::<8, 5, 0>()
 /// ```
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn sched_group_barrier<const MASK: u32, const SIZE: u32, const SYNC_ID: u32>() {
@@ -366,6 +382,8 @@ pub fn s_sleep<const COUNT: u32>() {
 /// Stop execution of the kernel.
 ///
 /// This usually signals an error state.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn s_sethalt<const VALUE: u32>() -> ! {
@@ -407,6 +425,8 @@ pub fn mbcnt_hi(value: u32, init: u32) -> u32 {
 
 /// Returns a bitfield (`u32` or `u64`) containing the result of its i1 argument
 /// in all active lanes, and zero in all inactive lanes.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn ballot(b: bool) -> u64 {
@@ -419,6 +439,8 @@ pub fn ballot(b: bool) -> u64 {
 /// While [`ballot`] converts a `bool` to a mask, `inverse_ballot` converts a mask back to a `bool`.
 /// This means `inverse_ballot(ballot(b)) == b`.
 /// The inverse of `ballot(inverse_ballot(value)) ~= value` is not always true as inactive lanes are set to zero by `ballot`.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn inverse_ballot(value: u64) -> bool {
@@ -433,6 +455,8 @@ pub fn inverse_ballot(value: u64) -> bool {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_umin<const STRATEGY: u32>(value: u32) -> u32 {
@@ -447,6 +471,8 @@ pub fn wave_reduce_umin<const STRATEGY: u32>(value: u32) -> u32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_min<const STRATEGY: u32>(value: i32) -> i32 {
@@ -462,6 +488,8 @@ pub fn wave_reduce_min<const STRATEGY: u32>(value: i32) -> i32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_umax<const STRATEGY: u32>(value: u32) -> u32 {
@@ -476,6 +504,8 @@ pub fn wave_reduce_umax<const STRATEGY: u32>(value: u32) -> u32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_max<const STRATEGY: u32>(value: i32) -> i32 {
@@ -491,6 +521,8 @@ pub fn wave_reduce_max<const STRATEGY: u32>(value: i32) -> i32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_add<const STRATEGY: u32>(value: u32) -> u32 {
@@ -506,6 +538,8 @@ pub fn wave_reduce_add<const STRATEGY: u32>(value: u32) -> u32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_and<const STRATEGY: u32>(value: u32) -> u32 {
@@ -520,6 +554,8 @@ pub fn wave_reduce_and<const STRATEGY: u32>(value: u32) -> u32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_or<const STRATEGY: u32>(value: u32) -> u32 {
@@ -534,6 +570,8 @@ pub fn wave_reduce_or<const STRATEGY: u32>(value: u32) -> u32 {
 /// - 2: DPP
 ///
 /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn wave_reduce_xor<const STRATEGY: u32>(value: u32) -> u32 {
@@ -544,12 +582,16 @@ pub fn wave_reduce_xor<const STRATEGY: u32>(value: u32) -> u32 {
 // The following intrinsics can have multiple sizes
 
 /// Get `value` from the first active lane in the wavefront.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn readfirstlane_u32(value: u32) -> u32 {
     llvm_readfirstlane_u32(value)
 }
 /// Get `value` from the first active lane in the wavefront.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn readfirstlane_u64(value: u64) -> u64 {
@@ -559,6 +601,8 @@ pub fn readfirstlane_u64(value: u64) -> u64 {
 ///
 /// The lane argument must be uniform across the currently active threads
 /// of the current wavefront. Otherwise, the result is undefined.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 {
@@ -568,6 +612,8 @@ pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 {
 ///
 /// The lane argument must be uniform across the currently active threads
 /// of the current wavefront. Otherwise, the result is undefined.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 {
@@ -582,6 +628,8 @@ pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 {
 ///
 /// `value` is the value returned by `lane`.
 /// `default` is the value returned by all lanes other than `lane`.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 {
@@ -596,6 +644,8 @@ pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 {
 ///
 /// `value` is the value returned by `lane`.
 /// `default` is the value returned by all lanes other than `lane`.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 {
@@ -605,6 +655,8 @@ pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 {
 /// Stop execution of the wavefront.
 ///
 /// This usually signals the end of a successful execution.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub fn endpgm() -> ! {
@@ -621,6 +673,8 @@ pub fn endpgm() -> ! {
 /// v_mov_b32 <dest> <old>
 /// v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
 /// ```
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn update_dpp<
@@ -651,6 +705,8 @@ pub fn s_memrealtime() -> u64 {
 ///
 /// Reading from inactive lanes returns `0`.
 /// In case multiple values get written to the same `lane`, the value from the source lane with the higher index is taken.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 {
@@ -661,6 +717,8 @@ pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 {
 /// Returns the `value` given to `ds_permute` by lane `lane`.
 ///
 /// Reading from inactive lanes returns `0`.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn ds_bpermute(lane: u32, value: u32) -> u32 {
@@ -680,6 +738,8 @@ pub unsafe fn perm(src0: u32, src1: u32, selector: u32) -> u32 {
 ///
 /// The third and fourth inputs must be uniform across the current wavefront.
 /// These are combined into a single 64-bit value representing lane selects used to swizzle within each row.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlane16_u32<const FI: bool, const BOUND_CONTROL: bool>(
@@ -696,6 +756,8 @@ pub unsafe fn permlane16_u32<const FI: bool, const BOUND_CONTROL: bool>(
 ///
 /// The third and fourth inputs must be uniform across the current wavefront.
 /// These are combined into a single 64-bit value representing lane selects used to swizzle within each row.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlanex16_u32<const FI: bool, const BOUND_CONTROL: bool>(
@@ -718,6 +780,8 @@ pub fn s_get_waveid_in_workgroup() -> u32 {
 /// Swap `value` between upper and lower 32 lanes in a wavefront.
 ///
 /// Does nothing for wave32.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlane64_u32(value: u32) -> u32 {
@@ -728,6 +792,8 @@ pub unsafe fn permlane64_u32(value: u32) -> u32 {
 /// Performs arbitrary gather-style operation within a row (16 contiguous lanes) of the second input operand.
 ///
 /// In contrast to [`permlane16_u32`], allows each lane to specify its own gather lane.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlane16_var<const FI: bool, const BOUND_CONTROL: bool>(
@@ -742,6 +808,8 @@ pub unsafe fn permlane16_var<const FI: bool, const BOUND_CONTROL: bool>(
 /// Performs arbitrary gather-style operation across two rows (16 contiguous lanes) of the second input operand.
 ///
 /// In contrast to [`permlanex16_u32`], allows each lane to specify its own gather lane.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlanex16_var<const FI: bool, const BOUND_CONTROL: bool>(
@@ -766,6 +834,8 @@ pub fn wave_id() -> u32 {
 /// Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes).
 /// Returns a pair for the swapped registers.
 /// The first element of the return corresponds to the swapped element of the first argument.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlane16_swap<const FI: bool, const BOUND_CONTROL: bool>(
@@ -782,6 +852,8 @@ pub unsafe fn permlane16_swap<const FI: bool, const BOUND_CONTROL: bool>(
 /// Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes).
 /// Returns a pair for the swapped registers.
 /// The first element of the return corresponds to the swapped element of the first argument.
+///
+#[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]
 pub unsafe fn permlane32_swap<const FI: bool, const BOUND_CONTROL: bool>(
diff --git a/crates/core_arch/src/nvptx/mod.rs b/crates/core_arch/src/nvptx/mod.rs
index 5471ef8198..b63a5d01a7 100644
--- a/crates/core_arch/src/nvptx/mod.rs
+++ b/crates/core_arch/src/nvptx/mod.rs
@@ -49,6 +49,8 @@ unsafe extern "C" {
 }
 
 /// Synchronizes all threads in the block.
+///
+#[doc = include_str!("../amdgpu/intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
 pub unsafe fn _syncthreads() -> () {

From eec5cd937ea06cca7d0a387ae62f78304b8486ea Mon Sep 17 00:00:00 2001
From: ArunTamil21 <aruntamiln@gmail.com>
Date: Tue, 24 Mar 2026 12:23:05 +0000
Subject: [PATCH 212/326] Mark alias test wrappers as const fn where supported
 and clean up skip list

---
 crates/core_arch/src/x86/sse.rs          | 10 +++++-----
 crates/stdarch-verify/tests/x86-intel.rs |  1 -
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs
index 4d052186bc..c6531e839a 100644
--- a/crates/core_arch/src/x86/sse.rs
+++ b/crates/core_arch/src/x86/sse.rs
@@ -3071,7 +3071,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_cvtsi32_ss() {
+    const fn test_mm_cvtsi32_ss() {
         test_mm_cvtsi32_ss_impl!(_mm_cvtsi32_ss);
     }
 
@@ -3207,12 +3207,12 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_load1_ps() {
+    const fn test_mm_load1_ps() {
         test_mm_load1_ps_impl!(_mm_load1_ps);
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_load_ps1() {
+    const fn test_mm_load_ps1() {
         test_mm_load1_ps_impl!(_mm_load_ps1);
     }
 
@@ -3276,12 +3276,12 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_store1_ps() {
+    const fn test_mm_store1_ps() {
         test_mm_store1_ps_impl!(_mm_store1_ps);
     }
 
     #[simd_test(enable = "sse")]
-    fn test_mm_store_ps1() {
+    const fn test_mm_store_ps1() {
         test_mm_store1_ps_impl!(_mm_store_ps1);
     }
 
diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 754be9dc39..024a873de1 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -250,7 +250,6 @@ fn verify_all_signatures() {
                 "_mm_cvt_ss2si",
                 "_mm_cvtt_ss2si",
                 "_mm_cvt_si2ss",
-                "_mm_set_ps1",
                 "_mm_bslli_si128",
                 "_mm_bsrli_si128",
                 "_bextr2_u32",

From e984a3c4dbed96dc4ca27e1462e9fa3fde0f39c3 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Tue, 31 Mar 2026 15:48:28 +0000
Subject: [PATCH 213/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to e4fdb554ad2c0270473181438e338c42b5b30b0c.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index db9492636f..a8efb5c477 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-eda4fc7733ee89e484d7120cafbd80dcb2fce66e
+e4fdb554ad2c0270473181438e338c42b5b30b0c

From 43b791258dcec44d9a61315d490cadd30730691a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jakub=20Ber=C3=A1nek?= <berykubik@gmail.com>
Date: Wed, 1 Apr 2026 11:05:53 +0200
Subject: [PATCH 214/326] Fix rustc-pull CI workflow

---
 .github/workflows/rustc-pull.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/rustc-pull.yml b/.github/workflows/rustc-pull.yml
index ee0c498878..d2feb1add6 100644
--- a/.github/workflows/rustc-pull.yml
+++ b/.github/workflows/rustc-pull.yml
@@ -13,6 +13,7 @@ jobs:
     uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main
     with:
       github-app-id: ${{ vars.APP_CLIENT_ID }}
+      pr-author: "workflows-stdarch[bot]"
       # https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782
       zulip-stream-id: 208962
       zulip-bot-email:  "stdarch-ci-bot@rust-lang.zulipchat.com"

From cb3ceeb6156d9fac76c5b62414d4e344b5bca777 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 6 Apr 2026 19:13:30 +0200
Subject: [PATCH 215/326] disable hexagon tests for now

---
 .github/workflows/main.yml | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 3749ed1f6a..966ba0ba9e 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -96,8 +96,9 @@ jobs:
           os: ubuntu-latest
         - tuple: loongarch64-unknown-linux-gnu
           os: ubuntu-latest
-        - tuple: hexagon-unknown-linux-musl
-          os: ubuntu-latest
+        # hexagon doesn't build at the moment due to a libc issue.
+        # - tuple: hexagon-unknown-linux-musl
+        #   os: ubuntu-latest
         - tuple: wasm32-wasip1
           os: ubuntu-latest
 
@@ -209,11 +210,12 @@ jobs:
             tuple: amdgcn-amd-amdhsa
             os: ubuntu-latest
           norun: true
-        - target:
-            tuple: hexagon-unknown-linux-musl
-            os: ubuntu-latest
-          norun: true
-          build_std: true
+        # hexagon doesn't build at the moment due to a libc issue.
+        # - target:
+        #     tuple: hexagon-unknown-linux-musl
+        #     os: ubuntu-latest
+        #   norun: true
+        #   build_std: true
 
     steps:
     - uses: actions/checkout@v6

From 6db0299623d615ca08d62f643d5b363f8c1fee84 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 19 Mar 2026 15:08:04 +0100
Subject: [PATCH 216/326] check that store/load rountrip initializes all bytes

---
 crates/core_arch/src/aarch64/neon/mod.rs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 2fbd2255aa..29a278b80d 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -1022,8 +1022,12 @@ mod tests {
         ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => {
             let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty);
             let a: $vec_ty = transmute(vals);
-            let mut tmp = [0 as $elem_ty; $len];
+            let mut tmp = core::mem::MaybeUninit::<[$elem_ty; $len]>::uninit();
             $store(tmp.as_mut_ptr().cast(), a);
+
+            // With Miri this will check that all elements were initialized.
+            let tmp = tmp.assume_init();
+
             let r: $vec_ty = $load(tmp.as_ptr().cast());
             let out: [$elem_ty; $len] = transmute(r);
             assert_eq!(out, vals);

From b05c08693a18f69f76e44c6bbe5ee338cbc57107 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 19 Mar 2026 15:38:10 +0100
Subject: [PATCH 217/326] support roundtrip of `vst3q`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 18 +----
 .../src/arm_shared/neon/generated.rs          | 72 +++----------------
 .../spec/neon/aarch64.spec.yml                | 13 +---
 .../spec/neon/arm_shared.spec.yml             | 29 +++-----
 4 files changed, 22 insertions(+), 110 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 74af500166..34303b706c 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12127,14 +12127,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v2f64.p0"
-        )]
-        fn _vld3q_f64(ptr: *const float64x2_t) -> float64x2x3_t;
-    }
-    _vld3q_f64(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f64, 2, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
@@ -12145,14 +12138,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld3.v2i64.p0"
-        )]
-        fn _vld3q_s64(ptr: *const int64x2_t) -> int64x2x3_t;
-    }
-    _vld3q_s64(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i64, 2, 3, a)
 }
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 4a846e2877..cf4d10162e 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -67158,14 +67158,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v2f32.p0"
-        )]
-        fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8);
-    }
-    _vst3_f32(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
@@ -67177,14 +67170,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v4f32.p0"
-        )]
-        fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8);
-    }
-    _vst3q_f32(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
@@ -67196,14 +67182,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v8i8.p0"
-        )]
-        fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
-    }
-    _vst3_s8(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
@@ -67215,14 +67194,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v16i8.p0"
-        )]
-        fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
-    }
-    _vst3q_s8(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
@@ -67234,14 +67206,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v4i16.p0"
-        )]
-        fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8);
-    }
-    _vst3_s16(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
@@ -67253,14 +67218,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v8i16.p0"
-        )]
-        fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8);
-    }
-    _vst3q_s16(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
@@ -67272,14 +67230,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v2i32.p0"
-        )]
-        fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8);
-    }
-    _vst3_s32(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
@@ -67291,14 +67242,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
 pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.st3.v4i32.p0"
-        )]
-        fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8);
-    }
-    _vst3q_s32(b.0, b.1, b.2, a as _)
+    crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b)
 }
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index e88860717b..dfcdfb59a5 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -4031,17 +4031,10 @@ intrinsics:
       unsafe: [neon]
     assert_instr: [ld3]
     types:
-      - ['*const i64', int64x2x3_t, '*const int64x2_t', i64]
-      - ['*const f64', float64x2x3_t, '*const float64x2_t', f64]
+      - ['*const i64', int64x2x3_t, i64, "2"]
+      - ['*const f64', float64x2x3_t, f64, "2"]
     compose:
-      - LLVMLink:
-          name: 'vld3{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[2]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']]
+      - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true]
 
   - name: "vld3{neon_type[1].nox}"
     doc: Load multiple 3-element structures to three registers
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 56b2252c9e..f6ef7f17d7 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -5642,27 +5642,16 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [i8, int8x8x3_t, int8x8_t]
-      - [i16, int16x4x3_t, int16x4_t]
-      - [i32, int32x2x3_t, int32x2_t]
-      - [i8, int8x16x3_t, int8x16_t]
-      - [i16, int16x8x3_t, int16x8_t]
-      - [i32, int32x4x3_t, int32x4_t]
-      - [f32, float32x2x3_t, float32x2_t]
-      - [f32, float32x4x3_t, float32x4_t]
+      - [i8, int8x8x3_t, "8"]
+      - [i16, int16x4x3_t, "4"]
+      - [i32, int32x2x3_t, "2"]
+      - [i8, int8x16x3_t, "16"]
+      - [i16, int16x8x3_t, "8"]
+      - [i32, int32x4x3_t, "4"]
+      - [f32, float32x2x3_t, "2"]
+      - [f32, float32x4x3_t, "4"]
     compose:
-      - LLVMLink:
-          name: 'vst3.{neon_type[1]}'
-          arguments:
-            - 'a: {type[2]}'
-            - 'b: {type[2]}'
-            - 'c: {type[2]}'
-            - 'ptr: *mut i8'
-          links:
-            - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']]
-
+      - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true]
 
   - name: "vst3{neon_type[1].nox}"
     doc: "Store multiple 3-element structures from three registers"

From d3034edff2f3e1039c780729da526edb6ae37385 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Thu, 19 Mar 2026 15:46:27 +0100
Subject: [PATCH 218/326] run `test_vld3q` tests with miri on CI

---
 .github/workflows/main.yml | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 966ba0ba9e..5520bc9b97 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -272,7 +272,7 @@ jobs:
   intrinsic-test:
     needs: [style]
     name: Intrinsic Test
-    runs-on: ubuntu-latest 
+    runs-on: ubuntu-latest
     strategy:
       matrix:
         target:
@@ -332,11 +332,30 @@ jobs:
         cargo run -p stdarch-gen-hexagon --release
         git diff --exit-code
 
+  # Run some tests with Miri. Most stdarch functions use platform-specific intrinsics
+  # that Miri does not support. Also Miri is reltively slow.
+  #
+  # Below we run some tests where Miri might catch UB, for instance on intrinsics that read from
+  # or write to pointers.
+  miri:
+    needs: [style]
+    name: Run some tests with miri
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v6
+    - name: Install Rust
+      run: rustup update nightly && rustup default nightly && rustup component add miri
+    - name: Aarch64 load/store roundtrip
+      env:
+        TARGET: "aarch64-unknown-linux-gnu"
+      run: cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- test_vld3q
+
   conclusion:
     needs:
       - docs
       - verify
       - test
+      - miri
       - intrinsic-test
       - check-stdarch-gen
     runs-on: ubuntu-latest

From 27b22afba9c6fa2b355d4f72ba6f62fe8a055102 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 31 Mar 2026 23:11:51 +0200
Subject: [PATCH 219/326] run some aarch64 tests with miri on CI

---
 .github/workflows/main.yml | 7 +++++--
 aarch64-miri-tests.txt     | 3 +++
 2 files changed, 8 insertions(+), 2 deletions(-)
 create mode 100644 aarch64-miri-tests.txt

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 5520bc9b97..1f598f6e20 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -345,10 +345,13 @@ jobs:
     - uses: actions/checkout@v6
     - name: Install Rust
       run: rustup update nightly && rustup default nightly && rustup component add miri
-    - name: Aarch64 load/store roundtrip
+    - name: Run miri tests
       env:
         TARGET: "aarch64-unknown-linux-gnu"
-      run: cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- test_vld3q
+      run: |
+        # read filters and join them with a space.
+        FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ')
+        cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- $FILTERS
 
   conclusion:
     needs:
diff --git a/aarch64-miri-tests.txt b/aarch64-miri-tests.txt
new file mode 100644
index 0000000000..2c66cc5eea
--- /dev/null
+++ b/aarch64-miri-tests.txt
@@ -0,0 +1,3 @@
+test_vld3q
+neon::load_tests
+neon::store_tests

From 5f27e9e6e8464aff2820e4ee0c94fb6a8339a9c5 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Tue, 31 Mar 2026 09:40:38 +0800
Subject: [PATCH 220/326] loongarch: Remove unnecessary `transmute` calls

This commit removes unnecessary `transmute` calls to resolve clippy
warnings.
---
 crates/core_arch/src/loongarch64/lasx/generated.rs | 12 ++++++------
 crates/core_arch/src/loongarch64/lsx/generated.rs  | 12 ++++++------
 crates/stdarch-gen-loongarch/src/main.rs           |  6 +++---
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index d2e1a87fde..5559c6ad4d 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -5044,7 +5044,7 @@ pub unsafe fn lasx_xvld<const IMM_S12: i32>(mem_addr: *const i8) -> m256i {
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lasx_xvst<const IMM_S12: i32>(a: m256i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S12, 12);
-    transmute(__lasx_xvst(transmute(a), mem_addr, IMM_S12))
+    __lasx_xvst(transmute(a), mem_addr, IMM_S12)
 }
 
 #[inline(always)]
@@ -5054,7 +5054,7 @@ pub unsafe fn lasx_xvst<const IMM_S12: i32>(a: m256i, mem_addr: *mut i8) {
 pub unsafe fn lasx_xvstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m256i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM4, 4);
-    transmute(__lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4))
+    __lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)
 }
 
 #[inline(always)]
@@ -5064,7 +5064,7 @@ pub unsafe fn lasx_xvstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m256i, mem_a
 pub unsafe fn lasx_xvstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m256i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM3, 3);
-    transmute(__lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3))
+    __lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)
 }
 
 #[inline(always)]
@@ -5074,7 +5074,7 @@ pub unsafe fn lasx_xvstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m256i, mem_a
 pub unsafe fn lasx_xvstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m256i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM2, 2);
-    transmute(__lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2))
+    __lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)
 }
 
 #[inline(always)]
@@ -5084,7 +5084,7 @@ pub unsafe fn lasx_xvstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m256i, mem_a
 pub unsafe fn lasx_xvstelm_d<const IMM_S8: i32, const IMM1: u32>(a: m256i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM1, 1);
-    transmute(__lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1))
+    __lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)
 }
 
 #[inline(always)]
@@ -5192,7 +5192,7 @@ pub unsafe fn lasx_xvldx(mem_addr: *const i8, b: i64) -> m256i {
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lasx_xvstx(a: m256i, mem_addr: *mut i8, b: i64) {
-    transmute(__lasx_xvstx(transmute(a), mem_addr, transmute(b)))
+    __lasx_xvstx(transmute(a), mem_addr, transmute(b))
 }
 
 #[inline(always)]
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 679c82079c..faa8859eba 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -5052,7 +5052,7 @@ pub fn lsx_vfrintrm_d(a: m128d) -> m128d {
 pub unsafe fn lsx_vstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m128i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM4, 4);
-    transmute(__lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4))
+    __lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)
 }
 
 #[inline(always)]
@@ -5062,7 +5062,7 @@ pub unsafe fn lsx_vstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m128i, mem_add
 pub unsafe fn lsx_vstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m128i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM3, 3);
-    transmute(__lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3))
+    __lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)
 }
 
 #[inline(always)]
@@ -5072,7 +5072,7 @@ pub unsafe fn lsx_vstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m128i, mem_add
 pub unsafe fn lsx_vstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m128i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM2, 2);
-    transmute(__lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2))
+    __lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)
 }
 
 #[inline(always)]
@@ -5082,7 +5082,7 @@ pub unsafe fn lsx_vstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m128i, mem_add
 pub unsafe fn lsx_vstelm_d<const IMM_S8: i32, const IMM1: u32>(a: m128i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S8, 8);
     static_assert_uimm_bits!(IMM1, 1);
-    transmute(__lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1))
+    __lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)
 }
 
 #[inline(always)]
@@ -6376,7 +6376,7 @@ pub unsafe fn lsx_vld<const IMM_S12: i32>(mem_addr: *const i8) -> m128i {
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lsx_vst<const IMM_S12: i32>(a: m128i, mem_addr: *mut i8) {
     static_assert_simm_bits!(IMM_S12, 12);
-    transmute(__lsx_vst(transmute(a), mem_addr, IMM_S12))
+    __lsx_vst(transmute(a), mem_addr, IMM_S12)
 }
 
 #[inline(always)]
@@ -6455,7 +6455,7 @@ pub unsafe fn lsx_vldx(mem_addr: *const i8, b: i64) -> m128i {
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lsx_vstx(a: m128i, mem_addr: *mut i8, b: i64) {
-    transmute(__lsx_vstx(transmute(a), mem_addr, transmute(b)))
+    __lsx_vstx(transmute(a), mem_addr, transmute(b))
 }
 
 #[inline(always)]
diff --git a/crates/stdarch-gen-loongarch/src/main.rs b/crates/stdarch-gen-loongarch/src/main.rs
index fdc9b2b6bc..fe767fc309 100644
--- a/crates/stdarch-gen-loongarch/src/main.rs
+++ b/crates/stdarch-gen-loongarch/src/main.rs
@@ -571,21 +571,21 @@ fn gen_bind_body(
     } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "SI" {
         call_params = match asm_fmts[2].as_str() {
             "si12" => format!(
-                "static_assert_simm_bits!(IMM_S12, 12);\n    {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S12)){unsafe_end}"
+                "static_assert_simm_bits!(IMM_S12, 12);\n    {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S12){unsafe_end}"
             ),
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         };
     } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "DI" {
         call_params = match asm_fmts[2].as_str() {
             "rk" => format!(
-                "{unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, transmute(b))){unsafe_end}"
+                "{unsafe_start}__{current_name}(transmute(a), mem_addr, transmute(b)){unsafe_end}"
             ),
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         };
     } else if para_num == 4 {
         call_params = match (asm_fmts[2].as_str(), current_name.chars().last().unwrap()) {
             ("si8", t) => format!(
-                "static_assert_simm_bits!(IMM_S8, 8);\n    static_assert_uimm_bits!(IMM{0}, {0});\n    {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0})){unsafe_end}",
+                "static_assert_simm_bits!(IMM_S8, 8);\n    static_assert_uimm_bits!(IMM{0}, {0});\n    {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0}){unsafe_end}",
                 type_to_imm(t)
             ),
             (_, _) => panic!(

From f7266e8711e709cf3e368cccb5192cfb84c62f89 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 8 Apr 2026 10:44:44 +0200
Subject: [PATCH 221/326] make `vld4q` portable

---
 aarch64-miri-tests.txt                         |  3 ++-
 crates/core_arch/src/aarch64/neon/generated.rs | 18 ++----------------
 .../stdarch-gen-arm/spec/neon/aarch64.spec.yml | 14 ++++----------
 3 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/aarch64-miri-tests.txt b/aarch64-miri-tests.txt
index 2c66cc5eea..2c0dbb8297 100644
--- a/aarch64-miri-tests.txt
+++ b/aarch64-miri-tests.txt
@@ -1,3 +1,4 @@
-test_vld3q
+test_vld3
+test_vld4
 neon::load_tests
 neon::store_tests
diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 34303b706c..c9ce7a69a6 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12521,14 +12521,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v2f64.p0"
-        )]
-        fn _vld4q_f64(ptr: *const float64x2_t) -> float64x2x4_t;
-    }
-    _vld4q_f64(a as _)
+    crate::core_arch::macros::deinterleaving_load!(f64, 2, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
@@ -12539,14 +12532,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.ld4.v2i64.p0"
-        )]
-        fn _vld4q_s64(ptr: *const int64x2_t) -> int64x2x4_t;
-    }
-    _vld4q_s64(a as _)
+    crate::core_arch::macros::deinterleaving_load!(i64, 2, 4, a)
 }
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index dfcdfb59a5..a769d35264 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -4167,17 +4167,11 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ['*const f64', float64x2x4_t, f64, '*const float64x2_t']
-      - ['*const i64', int64x2x4_t, i64, '*const int64x2_t']
+      - ['*const f64', float64x2x4_t, f64, "2"]
+      - ['*const i64', int64x2x4_t, i64, "2"]
     compose:
-      - LLVMLink:
-          name: 'vld4{neon_type[1].nox}'
-          arguments:
-            - 'ptr: {type[3]}'
-          links:
-            - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0'
-              arch: aarch64,arm64ec
-      - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']]
+      - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true]
+
 
   - name: "vld4{neon_type[1].nox}"
     doc: Load multiple 4-element structures to four registers

From 34808ce2ab10d2cc76b2628a60faef4abc866cba Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Wed, 8 Apr 2026 09:52:49 -0700
Subject: [PATCH 222/326] hexagon: Preserve original Q6 naming case for HVX
 intrinsics

---
 crates/core_arch/src/hexagon/v128.rs   | 965 +++++++++++++------------
 crates/core_arch/src/hexagon/v64.rs    | 965 +++++++++++++------------
 crates/stdarch-gen-hexagon/src/main.rs |  23 +-
 examples/gaussian.rs                   |  54 +-
 4 files changed, 1020 insertions(+), 987 deletions(-)

diff --git a/crates/core_arch/src/hexagon/v128.rs b/crates/core_arch/src/hexagon/v128.rs
index ef7ff4205c..1026338293 100644
--- a/crates/core_arch/src/hexagon/v128.rs
+++ b/crates/core_arch/src/hexagon/v128.rs
@@ -15,6 +15,18 @@
 //!
 //! To use this module, compile with `-C target-feature=+hvx-length128b`.
 //!
+//! ## Naming Convention
+//!
+//! Function names preserve the original Q6 naming case because the convention
+//! uses case to distinguish register types:
+//! - `W` (uppercase) = vector pair (`HvxVectorPair`)
+//! - `V` (uppercase) = vector (`HvxVector`)
+//! - `Q` (uppercase) = predicate (`HvxVectorPred`)
+//! - `R` = scalar register (`i32`)
+//!
+//! For example, `Q6_W_vcombine_VV` operates on a vector pair while
+//! `Q6_V_hi_W` extracts a vector from a pair.
+//!
 //! ## Architecture Versions
 //!
 //! Different intrinsics require different HVX architecture versions. Use the
@@ -31,6 +43,7 @@
 //! Each version includes all features from previous versions.
 
 #![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
@@ -1034,7 +1047,7 @@ unsafe extern "unadjusted" {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(extractw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 {
+pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 {
     extractw(vu, rs)
 }
 
@@ -1046,7 +1059,7 @@ pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(hi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector {
+pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector {
     hi(vss)
 }
 
@@ -1058,7 +1071,7 @@ pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lo))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector {
+pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector {
     lo(vss)
 }
 
@@ -1070,7 +1083,7 @@ pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lvsplatw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector {
     lvsplatw(rt)
 }
 
@@ -1082,7 +1095,7 @@ pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffh(vu, vv)
 }
 
@@ -1094,7 +1107,7 @@ pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffub(vu, vv)
 }
 
@@ -1106,7 +1119,7 @@ pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffuh(vu, vv)
 }
 
@@ -1118,7 +1131,7 @@ pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffw(vu, vv)
 }
 
@@ -1130,7 +1143,7 @@ pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector {
     vabsh(vu)
 }
 
@@ -1142,7 +1155,7 @@ pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector {
     vabsh_sat(vu)
 }
 
@@ -1154,7 +1167,7 @@ pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector {
     vabsw(vu)
 }
 
@@ -1166,7 +1179,7 @@ pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector {
     vabsw_sat(vu)
 }
 
@@ -1178,7 +1191,7 @@ pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddb(vu, vv)
 }
 
@@ -1190,7 +1203,7 @@ pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddb_dv(vuu, vvv)
 }
 
@@ -1202,7 +1215,7 @@ pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddh(vu, vv)
 }
 
@@ -1214,7 +1227,7 @@ pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddh_dv(vuu, vvv)
 }
 
@@ -1226,7 +1239,7 @@ pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddhsat(vu, vv)
 }
 
@@ -1238,7 +1251,7 @@ pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddhsat_dv(vuu, vvv)
 }
 
@@ -1250,7 +1263,7 @@ pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vaddhw(vu, vv)
 }
 
@@ -1262,7 +1275,7 @@ pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vaddubh(vu, vv)
 }
 
@@ -1274,7 +1287,7 @@ pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddubsat(vu, vv)
 }
 
@@ -1286,7 +1299,7 @@ pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddubsat_dv(vuu, vvv)
 }
 
@@ -1298,7 +1311,7 @@ pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadduhsat(vu, vv)
 }
 
@@ -1310,7 +1323,7 @@ pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vadduhsat_dv(vuu, vvv)
 }
 
@@ -1322,7 +1335,7 @@ pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vadduhw(vu, vv)
 }
 
@@ -1334,7 +1347,7 @@ pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_add(vu, vv)
 }
 
@@ -1346,7 +1359,7 @@ pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddw_dv(vuu, vvv)
 }
 
@@ -1358,7 +1371,7 @@ pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddwsat(vu, vv)
 }
 
@@ -1370,7 +1383,7 @@ pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddwsat_dv(vuu, vvv)
 }
 
@@ -1382,7 +1395,7 @@ pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     valignb(vu, vv, rt)
 }
 
@@ -1394,7 +1407,7 @@ pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
     valignbi(vu, vv, iu3)
 }
 
@@ -1406,7 +1419,7 @@ pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vand))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_and(vu, vv)
 }
 
@@ -1418,7 +1431,7 @@ pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector {
     vaslh(vu, rt)
 }
 
@@ -1430,7 +1443,7 @@ pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaslhv(vu, vv)
 }
 
@@ -1442,7 +1455,7 @@ pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector {
     vaslw(vu, rt)
 }
 
@@ -1454,7 +1467,7 @@ pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vaslw_acc(vx, vu, rt)
 }
 
@@ -1466,7 +1479,7 @@ pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaslwv(vu, vv)
 }
 
@@ -1478,7 +1491,7 @@ pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector {
     vasrh(vu, rt)
 }
 
@@ -1490,7 +1503,7 @@ pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhbrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhbrndsat(vu, vv, rt)
 }
 
@@ -1502,7 +1515,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhubrndsat(vu, vv, rt)
 }
 
@@ -1514,7 +1527,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhubsat(vu, vv, rt)
 }
 
@@ -1526,7 +1539,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vasrhv(vu, vv)
 }
 
@@ -1538,7 +1551,7 @@ pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector {
     vasrw(vu, rt)
 }
 
@@ -1550,7 +1563,7 @@ pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vasrw_acc(vx, vu, rt)
 }
 
@@ -1562,7 +1575,7 @@ pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwh(vu, vv, rt)
 }
 
@@ -1574,7 +1587,7 @@ pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwhrndsat(vu, vv, rt)
 }
 
@@ -1586,7 +1599,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwhsat(vu, vv, rt)
 }
 
@@ -1598,7 +1611,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwuhsat(vu, vv, rt)
 }
 
@@ -1610,7 +1623,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vasrwv(vu, vv)
 }
 
@@ -1622,7 +1635,7 @@ pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassign))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector {
     vassign(vu)
 }
 
@@ -1634,7 +1647,7 @@ pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassignp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair {
     vassignp(vuu)
 }
 
@@ -1646,7 +1659,7 @@ pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgh(vu, vv)
 }
 
@@ -1658,7 +1671,7 @@ pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavghrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavghrnd(vu, vv)
 }
 
@@ -1670,7 +1683,7 @@ pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgub(vu, vv)
 }
 
@@ -1682,7 +1695,7 @@ pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgubrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgubrnd(vu, vv)
 }
 
@@ -1694,7 +1707,7 @@ pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguh(vu, vv)
 }
 
@@ -1706,7 +1719,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguhrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguhrnd(vu, vv)
 }
 
@@ -1718,7 +1731,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgw(vu, vv)
 }
 
@@ -1730,7 +1743,7 @@ pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgwrnd(vu, vv)
 }
 
@@ -1742,7 +1755,7 @@ pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector {
     vcl0h(vu)
 }
 
@@ -1754,7 +1767,7 @@ pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector {
     vcl0w(vu)
 }
 
@@ -1766,7 +1779,7 @@ pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcombine))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vcombine(vu, vv)
 }
 
@@ -1778,7 +1791,7 @@ pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vzero() -> HvxVector {
+pub unsafe fn Q6_V_vzero() -> HvxVector {
     vd0()
 }
 
@@ -1790,7 +1803,7 @@ pub unsafe fn q6_v_vzero() -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector {
     vdealb(vu)
 }
 
@@ -1802,7 +1815,7 @@ pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb4w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdealb4w(vu, vv)
 }
 
@@ -1814,7 +1827,7 @@ pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector {
     vdealh(vu)
 }
 
@@ -1826,7 +1839,7 @@ pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vdealvdd(vu, vv, rt)
 }
 
@@ -1838,7 +1851,7 @@ pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdelta(vu, vv)
 }
 
@@ -1850,7 +1863,7 @@ pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpybus(vu, rt)
 }
 
@@ -1862,7 +1875,7 @@ pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpybus_acc(vx, vu, rt)
 }
 
@@ -1874,7 +1887,7 @@ pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vdmpybus_dv(vuu, rt)
 }
 
@@ -1886,7 +1899,7 @@ pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vdmpyacc_whwubrb(
+pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -1902,7 +1915,7 @@ pub unsafe fn q6_wh_vdmpyacc_whwubrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhb(vu, rt)
 }
 
@@ -1914,7 +1927,7 @@ pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhb_acc(vx, vu, rt)
 }
 
@@ -1926,7 +1939,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vdmpyhb_dv(vuu, rt)
 }
 
@@ -1938,7 +1951,7 @@ pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vdmpyacc_wwwhrb(
+pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -1954,7 +1967,7 @@ pub unsafe fn q6_ww_vdmpyacc_wwwhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhisat(vuu, rt)
 }
 
@@ -1966,7 +1979,7 @@ pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhisat_acc(vx, vuu, rt)
 }
 
@@ -1978,7 +1991,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsat(vu, rt)
 }
 
@@ -1990,7 +2003,7 @@ pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsat_acc(vx, vu, rt)
 }
 
@@ -2002,7 +2015,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhsuisat(vuu, rt)
 }
 
@@ -2014,7 +2027,7 @@ pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhsuisat_acc(vx, vuu, rt)
 }
 
@@ -2026,7 +2039,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt:
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsusat(vu, rt)
 }
 
@@ -2038,7 +2051,7 @@ pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsusat_acc(vx, vu, rt)
 }
 
@@ -2050,7 +2063,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpyhvsat(vu, vv)
 }
 
@@ -2062,7 +2075,7 @@ pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpyhvsat_acc(vx, vu, vv)
 }
 
@@ -2074,7 +2087,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vdsaduh(vuu, rt)
 }
 
@@ -2086,7 +2099,7 @@ pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh(
+pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -2102,7 +2115,7 @@ pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vinsertwr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector {
     vinsertwr(vx, rt)
 }
 
@@ -2114,7 +2127,7 @@ pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vlalignb(vu, vv, rt)
 }
 
@@ -2126,7 +2139,7 @@ pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
     vlalignbi(vu, vv, iu3)
 }
 
@@ -2138,7 +2151,7 @@ pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector {
     vlsrh(vu, rt)
 }
 
@@ -2150,7 +2163,7 @@ pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vlsrhv(vu, vv)
 }
 
@@ -2162,7 +2175,7 @@ pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector {
     vlsrw(vu, rt)
 }
 
@@ -2174,7 +2187,7 @@ pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vlsrwv(vu, vv)
 }
 
@@ -2186,7 +2199,7 @@ pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vlutvvb(vu, vv, rt)
 }
 
@@ -2198,7 +2211,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32or_vbvbvbr(
+pub unsafe fn Q6_Vb_vlut32or_VbVbVbR(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -2215,7 +2228,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbr(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vlutvwh(vu, vv, rt)
 }
 
@@ -2227,7 +2240,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16or_whvbvhr(
+pub unsafe fn Q6_Wh_vlut16or_WhVbVhR(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2244,7 +2257,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhr(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxh(vu, vv)
 }
 
@@ -2256,7 +2269,7 @@ pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxub(vu, vv)
 }
 
@@ -2268,7 +2281,7 @@ pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxuh(vu, vv)
 }
 
@@ -2280,7 +2293,7 @@ pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxw(vu, vv)
 }
 
@@ -2292,7 +2305,7 @@ pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminh(vu, vv)
 }
 
@@ -2304,7 +2317,7 @@ pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminub(vu, vv)
 }
 
@@ -2316,7 +2329,7 @@ pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminuh(vu, vv)
 }
 
@@ -2328,7 +2341,7 @@ pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminw(vu, vv)
 }
 
@@ -2340,7 +2353,7 @@ pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpabus(vuu, rt)
 }
 
@@ -2352,7 +2365,7 @@ pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpaacc_whwubrb(
+pub unsafe fn Q6_Wh_vmpaacc_WhWubRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -2368,7 +2381,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vmpabusv(vuu, vvv)
 }
 
@@ -2380,7 +2393,7 @@ pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabuuv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vmpabuuv(vuu, vvv)
 }
 
@@ -2392,7 +2405,7 @@ pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpahb(vuu, rt)
 }
 
@@ -2404,7 +2417,7 @@ pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpaacc_wwwhrb(
+pub unsafe fn Q6_Ww_vmpaacc_WwWhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -2420,7 +2433,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpybus(vu, rt)
 }
 
@@ -2432,7 +2445,7 @@ pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpybus_acc(vxx, vu, rt)
 }
 
@@ -2444,7 +2457,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpybusv(vu, vv)
 }
 
@@ -2456,7 +2469,7 @@ pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpyacc_whvubvb(
+pub unsafe fn Q6_Wh_vmpyacc_WhVubVb(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2472,7 +2485,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubvb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpybv(vu, vv)
 }
 
@@ -2484,7 +2497,7 @@ pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpyacc_whvbvb(
+pub unsafe fn Q6_Wh_vmpyacc_WhVbVb(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2500,7 +2513,7 @@ pub unsafe fn q6_wh_vmpyacc_whvbvb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyewuh(vu, vv)
 }
 
@@ -2512,7 +2525,7 @@ pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyh(vu, rt)
 }
 
@@ -2524,7 +2537,7 @@ pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat(
+pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat(
     vxx: HvxVectorPair,
     vu: HvxVector,
     rt: i32,
@@ -2540,7 +2553,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyhsrs(vu, rt)
 }
 
@@ -2552,7 +2565,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhss))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyhss(vu, rt)
 }
 
@@ -2564,7 +2577,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyhus(vu, vv)
 }
 
@@ -2576,7 +2589,7 @@ pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhvuh(
+pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2592,7 +2605,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvuh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyhv(vu, vv)
 }
 
@@ -2604,7 +2617,7 @@ pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhvh(
+pub unsafe fn Q6_Ww_vmpyacc_WwVhVh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2620,7 +2633,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhvsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyhvsrs(vu, vv)
 }
 
@@ -2632,7 +2645,7 @@ pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyieoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyieoh(vu, vv)
 }
 
@@ -2644,7 +2657,7 @@ pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiewh_acc(vx, vu, vv)
 }
 
@@ -2656,7 +2669,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiewuh(vu, vv)
 }
 
@@ -2668,7 +2681,7 @@ pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiewuh_acc(vx, vu, vv)
 }
 
@@ -2680,7 +2693,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyih(vu, vv)
 }
 
@@ -2692,7 +2705,7 @@ pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyih_acc(vx, vu, vv)
 }
 
@@ -2704,7 +2717,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyihb(vu, rt)
 }
 
@@ -2716,7 +2729,7 @@ pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyihb_acc(vx, vu, rt)
 }
 
@@ -2728,7 +2741,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiowh(vu, vv)
 }
 
@@ -2740,7 +2753,7 @@ pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwb(vu, rt)
 }
 
@@ -2752,7 +2765,7 @@ pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwb_acc(vx, vu, rt)
 }
 
@@ -2764,7 +2777,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwh(vu, rt)
 }
 
@@ -2776,7 +2789,7 @@ pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwh_acc(vx, vu, rt)
 }
 
@@ -2788,7 +2801,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyowh(vu, vv)
 }
 
@@ -2800,7 +2813,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyowh_rnd(vu, vv)
 }
 
@@ -2812,7 +2825,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift(
+pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -2828,7 +2841,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift(
+pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -2844,7 +2857,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyub(vu, rt)
 }
 
@@ -2856,7 +2869,7 @@ pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpyacc_wuhvubrub(
+pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub(
     vxx: HvxVectorPair,
     vu: HvxVector,
     rt: i32,
@@ -2872,7 +2885,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubrub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyubv(vu, vv)
 }
 
@@ -2884,7 +2897,7 @@ pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpyacc_wuhvubvub(
+pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2900,7 +2913,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubvub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyuh(vu, rt)
 }
 
@@ -2912,7 +2925,7 @@ pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh(
+pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     rt: i32,
@@ -2928,7 +2941,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyuhv(vu, vv)
 }
 
@@ -2940,7 +2953,7 @@ pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh(
+pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2956,7 +2969,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgh(vu, vv)
 }
 
@@ -2968,7 +2981,7 @@ pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgub(vu, vv)
 }
 
@@ -2980,7 +2993,7 @@ pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgw(vu, vv)
 }
 
@@ -2992,7 +3005,7 @@ pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector {
     vnormamth(vu)
 }
 
@@ -3004,7 +3017,7 @@ pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamtw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector {
     vnormamtw(vu)
 }
 
@@ -3016,7 +3029,7 @@ pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnot))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector {
     vnot(vu)
 }
 
@@ -3028,7 +3041,7 @@ pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_or(vu, vv)
 }
 
@@ -3040,7 +3053,7 @@ pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackeb(vu, vv)
 }
 
@@ -3052,7 +3065,7 @@ pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackeh(vu, vv)
 }
 
@@ -3064,7 +3077,7 @@ pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackhb_sat(vu, vv)
 }
 
@@ -3076,7 +3089,7 @@ pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhub_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackhub_sat(vu, vv)
 }
 
@@ -3088,7 +3101,7 @@ pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackob(vu, vv)
 }
 
@@ -3100,7 +3113,7 @@ pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackoh(vu, vv)
 }
 
@@ -3112,7 +3125,7 @@ pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackwh_sat(vu, vv)
 }
 
@@ -3124,7 +3137,7 @@ pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwuh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackwuh_sat(vu, vv)
 }
 
@@ -3136,7 +3149,7 @@ pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpopcounth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector {
     vpopcounth(vu)
 }
 
@@ -3148,7 +3161,7 @@ pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrdelta(vu, vv)
 }
 
@@ -3160,7 +3173,7 @@ pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
     vrmpybus(vu, rt)
 }
 
@@ -3172,7 +3185,7 @@ pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vrmpybus_acc(vx, vu, rt)
 }
 
@@ -3184,7 +3197,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
     vrmpybusi(vuu, rt, iu1)
 }
 
@@ -3196,7 +3209,7 @@ pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vrmpyacc_wwwubrbi(
+pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3213,7 +3226,7 @@ pub unsafe fn q6_ww_vrmpyacc_wwwubrbi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybusv(vu, vv)
 }
 
@@ -3225,7 +3238,7 @@ pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybusv_acc(vx, vu, vv)
 }
 
@@ -3237,7 +3250,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybv(vu, vv)
 }
 
@@ -3249,7 +3262,7 @@ pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybv_acc(vx, vu, vv)
 }
 
@@ -3261,7 +3274,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector {
     vrmpyub(vu, rt)
 }
 
@@ -3273,7 +3286,7 @@ pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vrmpyub_acc(vx, vu, rt)
 }
 
@@ -3285,7 +3298,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
     vrmpyubi(vuu, rt, iu1)
 }
 
@@ -3297,7 +3310,7 @@ pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi(
+pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3314,7 +3327,7 @@ pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpyubv(vu, vv)
 }
 
@@ -3326,7 +3339,7 @@ pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpyubv_acc(vx, vu, vv)
 }
 
@@ -3338,7 +3351,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vror))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector {
     vror(vu, rt)
 }
 
@@ -3350,7 +3363,7 @@ pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundhb(vu, vv)
 }
 
@@ -3362,7 +3375,7 @@ pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundhub(vu, vv)
 }
 
@@ -3374,7 +3387,7 @@ pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundwh(vu, vv)
 }
 
@@ -3386,7 +3399,7 @@ pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundwuh(vu, vv)
 }
 
@@ -3398,7 +3411,7 @@ pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
     vrsadubi(vuu, rt, iu1)
 }
 
@@ -3410,7 +3423,7 @@ pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi(
+pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3427,7 +3440,7 @@ pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsathub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsathub(vu, vv)
 }
 
@@ -3439,7 +3452,7 @@ pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsatwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsatwh(vu, vv)
 }
 
@@ -3451,7 +3464,7 @@ pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair {
     vsb(vu)
 }
 
@@ -3463,7 +3476,7 @@ pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair {
     vsh(vu)
 }
 
@@ -3475,7 +3488,7 @@ pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshufeh(vu, vv)
 }
 
@@ -3487,7 +3500,7 @@ pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector {
     vshuffb(vu)
 }
 
@@ -3499,7 +3512,7 @@ pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshuffeb(vu, vv)
 }
 
@@ -3511,7 +3524,7 @@ pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector {
     vshuffh(vu)
 }
 
@@ -3523,7 +3536,7 @@ pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshuffob(vu, vv)
 }
 
@@ -3535,7 +3548,7 @@ pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vshuffvdd(vu, vv, rt)
 }
 
@@ -3547,7 +3560,7 @@ pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vshufoeb(vu, vv)
 }
 
@@ -3559,7 +3572,7 @@ pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vshufoeh(vu, vv)
 }
 
@@ -3571,7 +3584,7 @@ pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshufoh(vu, vv)
 }
 
@@ -3583,7 +3596,7 @@ pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubb(vu, vv)
 }
 
@@ -3595,7 +3608,7 @@ pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubb_dv(vuu, vvv)
 }
 
@@ -3607,7 +3620,7 @@ pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubh(vu, vv)
 }
 
@@ -3619,7 +3632,7 @@ pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubh_dv(vuu, vvv)
 }
 
@@ -3631,7 +3644,7 @@ pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubhsat(vu, vv)
 }
 
@@ -3643,7 +3656,7 @@ pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubhsat_dv(vuu, vvv)
 }
 
@@ -3655,7 +3668,7 @@ pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsubhw(vu, vv)
 }
 
@@ -3667,7 +3680,7 @@ pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsububh(vu, vv)
 }
 
@@ -3679,7 +3692,7 @@ pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsububsat(vu, vv)
 }
 
@@ -3691,7 +3704,7 @@ pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsububsat_dv(vuu, vvv)
 }
 
@@ -3703,7 +3716,7 @@ pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubuhsat(vu, vv)
 }
 
@@ -3715,7 +3728,7 @@ pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubuhsat_dv(vuu, vvv)
 }
 
@@ -3727,7 +3740,7 @@ pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsubuhw(vu, vv)
 }
 
@@ -3739,7 +3752,7 @@ pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_sub(vu, vv)
 }
 
@@ -3751,7 +3764,7 @@ pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubw_dv(vuu, vvv)
 }
 
@@ -3763,7 +3776,7 @@ pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubwsat(vu, vv)
 }
 
@@ -3775,7 +3788,7 @@ pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubwsat_dv(vuu, vvv)
 }
 
@@ -3787,7 +3800,7 @@ pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vtmpyb(vuu, rt)
 }
 
@@ -3799,7 +3812,7 @@ pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpyacc_whwbrb(
+pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3815,7 +3828,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwbrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vtmpybus(vuu, rt)
 }
 
@@ -3827,7 +3840,7 @@ pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpyacc_whwubrb(
+pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3843,7 +3856,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwubrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vtmpyhb(vuu, rt)
 }
 
@@ -3855,7 +3868,7 @@ pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vtmpyacc_wwwhrb(
+pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3871,7 +3884,7 @@ pub unsafe fn q6_ww_vtmpyacc_wwwhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair {
     vunpackb(vu)
 }
 
@@ -3883,7 +3896,7 @@ pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair {
     vunpackh(vu)
 }
 
@@ -3895,7 +3908,7 @@ pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
     vunpackob(vxx, vu)
 }
 
@@ -3907,7 +3920,7 @@ pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
     vunpackoh(vxx, vu)
 }
 
@@ -3919,7 +3932,7 @@ pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair {
     vunpackub(vu)
 }
 
@@ -3931,7 +3944,7 @@ pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair {
     vunpackuh(vu)
 }
 
@@ -3943,7 +3956,7 @@ pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vxor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_xor(vu, vv)
 }
 
@@ -3955,7 +3968,7 @@ pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair {
     vzb(vu)
 }
 
@@ -3967,7 +3980,7 @@ pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair {
     vzh(vu)
 }
 
@@ -3979,7 +3992,7 @@ pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplatb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector {
     lvsplatb(rt)
 }
 
@@ -3991,7 +4004,7 @@ pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplath))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector {
     lvsplath(rt)
 }
 
@@ -4003,7 +4016,7 @@ pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddbsat(vu, vv)
 }
 
@@ -4015,7 +4028,7 @@ pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddbsat_dv(vuu, vvv)
 }
 
@@ -4027,7 +4040,7 @@ pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddclbh(vu, vv)
 }
 
@@ -4039,7 +4052,7 @@ pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddclbw(vu, vv)
 }
 
@@ -4051,7 +4064,7 @@ pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vaddacc_wwvhvh(
+pub unsafe fn Q6_Ww_vaddacc_WwVhVh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4067,7 +4080,7 @@ pub unsafe fn q6_ww_vaddacc_wwvhvh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddubh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vaddacc_whvubvub(
+pub unsafe fn Q6_Wh_vaddacc_WhVubVub(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4083,7 +4096,7 @@ pub unsafe fn q6_wh_vaddacc_whvubvub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddububb_sat(vu, vv)
 }
 
@@ -4095,7 +4108,7 @@ pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vaddacc_wwvuhvuh(
+pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4111,7 +4124,7 @@ pub unsafe fn q6_ww_vaddacc_wwvuhvuh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadduwsat(vu, vv)
 }
 
@@ -4123,7 +4136,7 @@ pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vadduwsat_dv(vuu, vvv)
 }
 
@@ -4135,7 +4148,7 @@ pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrhbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhbsat(vu, vv, rt)
 }
 
@@ -4147,7 +4160,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasruwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruwuhrndsat(vu, vv, rt)
 }
 
@@ -4159,7 +4172,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwuhrndsat(vu, vv, rt)
 }
 
@@ -4171,7 +4184,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlsrb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector {
     vlsrb(vu, rt)
 }
 
@@ -4183,7 +4196,7 @@ pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vlutvvb_nm(vu, vv, rt)
 }
 
@@ -4195,7 +4208,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32or_vbvbvbi(
+pub unsafe fn Q6_Vb_vlut32or_VbVbVbI(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -4212,7 +4225,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
     vlutvvbi(vu, vv, iu3)
 }
 
@@ -4224,7 +4237,7 @@ pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vlutvwh_nm(vu, vv, rt)
 }
 
@@ -4236,7 +4249,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16or_whvbvhi(
+pub unsafe fn Q6_Wh_vlut16or_WhVbVhI(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4253,7 +4266,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwhi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
     vlutvwhi(vu, vv, iu3)
 }
 
@@ -4265,7 +4278,7 @@ pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmaxb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxb(vu, vv)
 }
 
@@ -4277,7 +4290,7 @@ pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vminb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminb(vu, vv)
 }
 
@@ -4289,7 +4302,7 @@ pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpauhb(vuu, rt)
 }
 
@@ -4301,7 +4314,7 @@ pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpaacc_wwwuhrb(
+pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -4317,7 +4330,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwuhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyewuh_64))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyewuh_64(vu, vv)
 }
 
@@ -4329,7 +4342,7 @@ pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwub(vu, rt)
 }
 
@@ -4341,7 +4354,7 @@ pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwub_acc(vx, vu, rt)
 }
 
@@ -4353,7 +4366,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vmpyoacc_wvwvh(
+pub unsafe fn Q6_W_vmpyoacc_WVwVh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4369,7 +4382,7 @@ pub unsafe fn q6_w_vmpyoacc_wvwvh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrounduhub(vu, vv)
 }
 
@@ -4381,7 +4394,7 @@ pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrounduwuh(vu, vv)
 }
 
@@ -4393,7 +4406,7 @@ pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsatuwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsatuwuh(vu, vv)
 }
 
@@ -4405,7 +4418,7 @@ pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubbsat(vu, vv)
 }
 
@@ -4417,7 +4430,7 @@ pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubbsat_dv(vuu, vvv)
 }
 
@@ -4429,7 +4442,7 @@ pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubububb_sat(vu, vv)
 }
 
@@ -4441,7 +4454,7 @@ pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubuwsat(vu, vv)
 }
 
@@ -4453,7 +4466,7 @@ pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubuwsat_dv(vuu, vvv)
 }
 
@@ -4465,7 +4478,7 @@ pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector {
     vabsb(vu)
 }
 
@@ -4477,7 +4490,7 @@ pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector {
     vabsb_sat(vu)
 }
 
@@ -4489,7 +4502,7 @@ pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vaslh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vaslh_acc(vx, vu, rt)
 }
 
@@ -4501,7 +4514,7 @@ pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasrh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vasrh_acc(vx, vu, rt)
 }
 
@@ -4513,7 +4526,7 @@ pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruhubrndsat(vu, vv, rt)
 }
 
@@ -4525,7 +4538,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruhubsat(vu, vv, rt)
 }
 
@@ -4537,7 +4550,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruwuhsat(vu, vv, rt)
 }
 
@@ -4549,7 +4562,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgb(vu, vv)
 }
 
@@ -4561,7 +4574,7 @@ pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgbrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgbrnd(vu, vv)
 }
 
@@ -4573,7 +4586,7 @@ pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguw(vu, vv)
 }
 
@@ -4585,7 +4598,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguwrnd(vu, vv)
 }
 
@@ -4597,7 +4610,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vdd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vzero() -> HvxVectorPair {
+pub unsafe fn Q6_W_vzero() -> HvxVectorPair {
     vdd0()
 }
 
@@ -4609,7 +4622,7 @@ pub unsafe fn q6_w_vzero() -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
     vgathermh(rs, rt, mu, vv)
 }
 
@@ -4621,7 +4634,7 @@ pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
+pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
     vgathermhw(rs, rt, mu, vvv)
 }
 
@@ -4633,7 +4646,7 @@ pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
     vgathermw(rs, rt, mu, vv)
 }
 
@@ -4645,7 +4658,7 @@ pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpabuu(vuu, rt)
 }
 
@@ -4657,7 +4670,7 @@ pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpaacc_whwubrub(
+pub unsafe fn Q6_Wh_vmpaacc_WhWubRub(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -4673,7 +4686,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyh_acc(vxx, vu, rt)
 }
 
@@ -4685,7 +4698,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyuhe(vu, rt)
 }
 
@@ -4697,7 +4710,7 @@ pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyuhe_acc(vx, vu, rt)
 }
 
@@ -4709,7 +4722,7 @@ pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vnavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgb(vu, vv)
 }
 
@@ -4721,7 +4734,7 @@ pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermh(rt, mu, vv, vw)
 }
 
@@ -4733,7 +4746,7 @@ pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermh_add(rt, mu, vv, vw)
 }
 
@@ -4745,7 +4758,7 @@ pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
     vscattermhw(rt, mu, vvv, vw)
 }
 
@@ -4757,7 +4770,7 @@ pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
     vscattermhw_add(rt, mu, vvv, vw)
 }
 
@@ -4769,7 +4782,7 @@ pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermw(rt, mu, vv, vw)
 }
 
@@ -4781,7 +4794,7 @@ pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermw_add(rt, mu, vv, vw)
 }
 
@@ -4793,7 +4806,7 @@ pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vasr_into))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vasrinto_wwvwvw(
+pub unsafe fn Q6_Ww_vasrinto_WwVwVw(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4809,7 +4822,7 @@ pub unsafe fn q6_ww_vasrinto_wwvwvw(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vrotr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrotr(vu, vv)
 }
 
@@ -4821,7 +4834,7 @@ pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vsatdw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsatdw(vu, vv)
 }
 
@@ -4833,7 +4846,7 @@ pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpy_wubwbi_h(
+pub unsafe fn Q6_Ww_v6mpy_WubWbI_h(
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
     iu2: i32,
@@ -4849,7 +4862,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_h(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h(
+pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
@@ -4866,7 +4879,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpy_wubwbi_v(
+pub unsafe fn Q6_Ww_v6mpy_WubWbI_v(
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
     iu2: i32,
@@ -4882,7 +4895,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_v(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v(
+pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
@@ -4899,7 +4912,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector {
     vabs_hf(vu)
 }
 
@@ -4911,7 +4924,7 @@ pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector {
     vabs_sf(vu)
 }
 
@@ -4923,7 +4936,7 @@ pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_hf(vu, vv)
 }
 
@@ -4935,7 +4948,7 @@ pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_hf_hf(vu, vv)
 }
 
@@ -4947,7 +4960,7 @@ pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf16(vu, vv)
 }
 
@@ -4959,7 +4972,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf16_mix(vu, vv)
 }
 
@@ -4971,7 +4984,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf32(vu, vv)
 }
 
@@ -4983,7 +4996,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf32_mix(vu, vv)
 }
 
@@ -4995,7 +5008,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_sf(vu, vv)
 }
 
@@ -5007,7 +5020,7 @@ pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vadd_sf_hf(vu, vv)
 }
 
@@ -5019,7 +5032,7 @@ pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_sf_sf(vu, vv)
 }
 
@@ -5031,7 +5044,7 @@ pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vassign_fp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector {
     vassign_fp(vu)
 }
 
@@ -5043,7 +5056,7 @@ pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector {
     vconv_hf_qf16(vu)
 }
 
@@ -5055,7 +5068,7 @@ pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector {
+pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector {
     vconv_hf_qf32(vuu)
 }
 
@@ -5067,7 +5080,7 @@ pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_sf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector {
     vconv_sf_qf32(vu)
 }
 
@@ -5079,7 +5092,7 @@ pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_b_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vcvt_b_hf(vu, vv)
 }
 
@@ -5091,7 +5104,7 @@ pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
     vcvt_h_hf(vu)
 }
 
@@ -5103,7 +5116,7 @@ pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair {
     vcvt_hf_b(vu)
 }
 
@@ -5115,7 +5128,7 @@ pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector {
     vcvt_hf_h(vu)
 }
 
@@ -5127,7 +5140,7 @@ pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vcvt_hf_sf(vu, vv)
 }
 
@@ -5139,7 +5152,7 @@ pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair {
     vcvt_hf_ub(vu)
 }
 
@@ -5151,7 +5164,7 @@ pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_uh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector {
     vcvt_hf_uh(vu)
 }
 
@@ -5163,7 +5176,7 @@ pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair {
     vcvt_sf_hf(vu)
 }
 
@@ -5175,7 +5188,7 @@ pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_ub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vcvt_ub_hf(vu, vv)
 }
 
@@ -5187,7 +5200,7 @@ pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_uh_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
     vcvt_uh_hf(vu)
 }
 
@@ -5199,7 +5212,7 @@ pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpy_sf_hf(vu, vv)
 }
 
@@ -5211,7 +5224,7 @@ pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpy_sf_hf_acc(vx, vu, vv)
 }
 
@@ -5223,7 +5236,7 @@ pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmax_hf(vu, vv)
 }
 
@@ -5235,7 +5248,7 @@ pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmax_sf(vu, vv)
 }
 
@@ -5247,7 +5260,7 @@ pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmin_hf(vu, vv)
 }
 
@@ -5259,7 +5272,7 @@ pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmin_sf(vu, vv)
 }
 
@@ -5271,7 +5284,7 @@ pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector {
     vfneg_hf(vu)
 }
 
@@ -5283,7 +5296,7 @@ pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector {
     vfneg_sf(vu)
 }
 
@@ -5295,7 +5308,7 @@ pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmax_hf(vu, vv)
 }
 
@@ -5307,7 +5320,7 @@ pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmax_sf(vu, vv)
 }
 
@@ -5319,7 +5332,7 @@ pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmin_hf(vu, vv)
 }
 
@@ -5331,7 +5344,7 @@ pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmin_sf(vu, vv)
 }
 
@@ -5343,7 +5356,7 @@ pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_hf_hf(vu, vv)
 }
 
@@ -5355,7 +5368,7 @@ pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_hf_hf_acc(vx, vu, vv)
 }
 
@@ -5367,7 +5380,7 @@ pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf16(vu, vv)
 }
 
@@ -5379,7 +5392,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf16_hf(vu, vv)
 }
 
@@ -5391,7 +5404,7 @@ pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf16_mix_hf(vu, vv)
 }
 
@@ -5403,7 +5416,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf32(vu, vv)
 }
 
@@ -5415,7 +5428,7 @@ pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_qf32_hf(vu, vv)
 }
 
@@ -5427,7 +5440,7 @@ pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_qf32_mix_hf(vu, vv)
 }
 
@@ -5439,7 +5452,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_qf32_qf16(vu, vv)
 }
 
@@ -5451,7 +5464,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf32_sf(vu, vv)
 }
 
@@ -5463,7 +5476,7 @@ pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_sf_hf(vu, vv)
 }
 
@@ -5475,7 +5488,7 @@ pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf(
+pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -5491,7 +5504,7 @@ pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_sf_sf(vu, vv)
 }
 
@@ -5503,7 +5516,7 @@ pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_hf(vu, vv)
 }
 
@@ -5515,7 +5528,7 @@ pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_hf_hf(vu, vv)
 }
 
@@ -5527,7 +5540,7 @@ pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf16(vu, vv)
 }
 
@@ -5539,7 +5552,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf16_mix(vu, vv)
 }
 
@@ -5551,7 +5564,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf32(vu, vv)
 }
 
@@ -5563,7 +5576,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf32_mix(vu, vv)
 }
 
@@ -5575,7 +5588,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_sf(vu, vv)
 }
 
@@ -5587,7 +5600,7 @@ pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsub_sf_hf(vu, vv)
 }
 
@@ -5599,7 +5612,7 @@ pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_sf_sf(vu, vv)
 }
 
@@ -5611,7 +5624,7 @@ pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvuhubrndsat(vuu, vv)
 }
 
@@ -5623,7 +5636,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvuhubsat(vuu, vv)
 }
 
@@ -5635,7 +5648,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvwuhrndsat(vuu, vv)
 }
 
@@ -5647,7 +5660,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvwuhsat(vuu, vv)
 }
 
@@ -5659,7 +5672,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vmpyuhvs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyuhvs(vu, vv)
 }
 
@@ -5671,7 +5684,7 @@ pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector {
     vconv_h_hf(vu)
 }
 
@@ -5683,7 +5696,7 @@ pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector {
     vconv_hf_h(vu)
 }
 
@@ -5695,7 +5708,7 @@ pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_sf_w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector {
     vconv_sf_w(vu)
 }
 
@@ -5707,7 +5720,7 @@ pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_w_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector {
     vconv_w_sf(vu)
 }
 
@@ -5719,7 +5732,7 @@ pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(get_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
     get_qfext(vu, rt)
 }
 
@@ -5731,7 +5744,7 @@ pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(set_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
     set_qfext(vu, rt)
 }
 
@@ -5743,7 +5756,7 @@ pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vabs_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector {
     vabs_f8(vu)
 }
 
@@ -5755,7 +5768,7 @@ pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair {
     vcvt2_hf_b(vu)
 }
 
@@ -5767,7 +5780,7 @@ pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair {
     vcvt2_hf_ub(vu)
 }
 
@@ -5779,7 +5792,7 @@ pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair {
     vcvt_hf_f8(vu)
 }
 
@@ -5791,7 +5804,7 @@ pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmax_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmax_f8(vu, vv)
 }
 
@@ -5803,7 +5816,7 @@ pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmin_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmin_f8(vu, vv)
 }
 
@@ -5815,7 +5828,7 @@ pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfneg_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector {
     vfneg_f8(vu)
 }
 
@@ -5827,7 +5840,7 @@ pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_and(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5845,7 +5858,7 @@ pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_and_n(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5863,7 +5876,7 @@ pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_not(vandvrt(
             core::mem::transmute::<HvxVectorPred, HvxVector>(qs),
@@ -5881,7 +5894,7 @@ pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_or(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5899,7 +5912,7 @@ pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_or_n(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5917,7 +5930,7 @@ pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2(rt), -1))
 }
 
@@ -5929,7 +5942,7 @@ pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_xor(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5947,7 +5960,7 @@ pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_nqpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -5963,7 +5976,7 @@ pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_nt_nqpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -5979,7 +5992,7 @@ pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_nt_qpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -5995,7 +6008,7 @@ pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_qpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -6011,7 +6024,7 @@ pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector)
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddbnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6027,7 +6040,7 @@ pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddbq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6043,7 +6056,7 @@ pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddhnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6059,7 +6072,7 @@ pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddhq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6075,7 +6088,7 @@ pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddwnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6091,7 +6104,7 @@ pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddwq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6107,7 +6120,7 @@ pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
 }
 
@@ -6119,7 +6132,7 @@ pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandvrt_acc(vx, core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
 }
 
@@ -6131,7 +6144,7 @@ pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vu, rt))
 }
 
@@ -6143,7 +6156,7 @@ pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt_acc(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qx),
         vu,
@@ -6159,7 +6172,7 @@ pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqb(vu, vv), -1))
 }
 
@@ -6171,7 +6184,7 @@ pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqand_qvbvb(
+pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6194,7 +6207,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqor_qvbvb(
+pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6217,7 +6230,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqxacc_qvbvb(
+pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6240,7 +6253,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqh(vu, vv), -1))
 }
 
@@ -6252,7 +6265,7 @@ pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqand_qvhvh(
+pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6275,7 +6288,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqor_qvhvh(
+pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6298,7 +6311,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqxacc_qvhvh(
+pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6321,7 +6334,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqw(vu, vv), -1))
 }
 
@@ -6333,7 +6346,7 @@ pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqand_qvwvw(
+pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6356,7 +6369,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqor_qvwvw(
+pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6379,7 +6392,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqxacc_qvwvw(
+pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6402,7 +6415,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtb(vu, vv), -1))
 }
 
@@ -6414,7 +6427,7 @@ pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvbvb(
+pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6437,7 +6450,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvbvb(
+pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6460,7 +6473,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvbvb(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6483,7 +6496,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgth(vu, vv), -1))
 }
 
@@ -6495,7 +6508,7 @@ pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvhvh(
+pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6518,7 +6531,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvhvh(
+pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6541,7 +6554,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvhvh(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6564,7 +6577,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtub(vu, vv), -1))
 }
 
@@ -6576,7 +6589,7 @@ pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvubvub(
+pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6599,7 +6612,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvubvub(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvubvub(
+pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6622,7 +6635,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvubvub(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvubvub(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6645,7 +6658,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvubvub(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuh(vu, vv), -1))
 }
 
@@ -6657,7 +6670,7 @@ pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvuhvuh(
+pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6680,7 +6693,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuhvuh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvuhvuh(
+pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6703,7 +6716,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuhvuh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6726,7 +6739,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuw(vu, vv), -1))
 }
 
@@ -6738,7 +6751,7 @@ pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvuwvuw(
+pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6761,7 +6774,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuwvuw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvuwvuw(
+pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6784,7 +6797,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuwvuw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6807,7 +6820,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtw(vu, vv), -1))
 }
 
@@ -6819,7 +6832,7 @@ pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvwvw(
+pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6842,7 +6855,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvwvw(
+pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6865,7 +6878,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvwvw(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6888,7 +6901,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmux(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
         vu,
@@ -6904,7 +6917,7 @@ pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubbnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6920,7 +6933,7 @@ pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubbq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6936,7 +6949,7 @@ pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubhnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6952,7 +6965,7 @@ pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubhq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6968,7 +6981,7 @@ pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubwnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6984,7 +6997,7 @@ pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubwq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -7000,7 +7013,7 @@ pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vswap(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
         vu,
@@ -7016,7 +7029,7 @@ pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2v2(rt), -1))
 }
 
@@ -7028,7 +7041,7 @@ pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         shuffeqh(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -7046,7 +7059,7 @@ pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         shuffeqw(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -7064,7 +7077,7 @@ pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandnqrt(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
         rt,
@@ -7079,7 +7092,7 @@ pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandnqrt_acc(
         vx,
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
@@ -7095,7 +7108,7 @@ pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
     vandvnqv(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vu,
@@ -7110,7 +7123,7 @@ pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
     vandvqv(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vu,
@@ -7125,7 +7138,7 @@ pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_aqrmvh(
+pub unsafe fn Q6_vgather_AQRMVh(
     rs: *mut HvxVector,
     qs: HvxVectorPred,
     rt: i32,
@@ -7149,7 +7162,7 @@ pub unsafe fn q6_vgather_aqrmvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_aqrmww(
+pub unsafe fn Q6_vgather_AQRMWw(
     rs: *mut HvxVector,
     qs: HvxVectorPred,
     rt: i32,
@@ -7173,7 +7186,7 @@ pub unsafe fn q6_vgather_aqrmww(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_aqrmvw(
+pub unsafe fn Q6_vgather_AQRMVw(
     rs: *mut HvxVector,
     qs: HvxVectorPred,
     rt: i32,
@@ -7197,7 +7210,7 @@ pub unsafe fn q6_vgather_aqrmvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
     vprefixqb(vandvrt(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
         -1,
@@ -7212,7 +7225,7 @@ pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
     vprefixqh(vandvrt(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
         -1,
@@ -7227,7 +7240,7 @@ pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
     vprefixqw(vandvrt(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
         -1,
@@ -7242,7 +7255,7 @@ pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_qrmvhv(
+pub unsafe fn Q6_vscatter_QRMVhV(
     qs: HvxVectorPred,
     rt: i32,
     mu: i32,
@@ -7266,7 +7279,7 @@ pub unsafe fn q6_vscatter_qrmvhv(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_qrmwwv(
+pub unsafe fn Q6_vscatter_QRMWwV(
     qs: HvxVectorPred,
     rt: i32,
     mu: i32,
@@ -7290,7 +7303,7 @@ pub unsafe fn q6_vscatter_qrmwwv(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_qrmvwv(
+pub unsafe fn Q6_vscatter_QRMVwV(
     qs: HvxVectorPred,
     rt: i32,
     mu: i32,
@@ -7314,7 +7327,7 @@ pub unsafe fn q6_vscatter_qrmvwv(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vwvwq_carry_sat(
+pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
     vu: HvxVector,
     vv: HvxVector,
     qs: HvxVectorPred,
@@ -7334,7 +7347,7 @@ pub unsafe fn q6_vw_vadd_vwvwq_carry_sat(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgthf(vu, vv), -1))
 }
 
@@ -7346,7 +7359,7 @@ pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvhfvhf(
+pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7369,7 +7382,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhfvhf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvhfvhf(
+pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7392,7 +7405,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhfvhf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7415,7 +7428,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtsf(vu, vv), -1))
 }
 
@@ -7427,7 +7440,7 @@ pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvsfvsf(
+pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7450,7 +7463,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvsfvsf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvsfvsf(
+pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7473,7 +7486,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvsfvsf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
diff --git a/crates/core_arch/src/hexagon/v64.rs b/crates/core_arch/src/hexagon/v64.rs
index 023a8711d2..517a807db4 100644
--- a/crates/core_arch/src/hexagon/v64.rs
+++ b/crates/core_arch/src/hexagon/v64.rs
@@ -15,6 +15,18 @@
 //!
 //! To use this module, compile with `-C target-feature=+hvx-length64b`.
 //!
+//! ## Naming Convention
+//!
+//! Function names preserve the original Q6 naming case because the convention
+//! uses case to distinguish register types:
+//! - `W` (uppercase) = vector pair (`HvxVectorPair`)
+//! - `V` (uppercase) = vector (`HvxVector`)
+//! - `Q` (uppercase) = predicate (`HvxVectorPred`)
+//! - `R` = scalar register (`i32`)
+//!
+//! For example, `Q6_W_vcombine_VV` operates on a vector pair while
+//! `Q6_V_hi_W` extracts a vector from a pair.
+//!
 //! ## Architecture Versions
 //!
 //! Different intrinsics require different HVX architecture versions. Use the
@@ -31,6 +43,7 @@
 //! Each version includes all features from previous versions.
 
 #![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
@@ -1034,7 +1047,7 @@ unsafe extern "unadjusted" {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(extractw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 {
+pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 {
     extractw(vu, rs)
 }
 
@@ -1046,7 +1059,7 @@ pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(hi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector {
+pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector {
     hi(vss)
 }
 
@@ -1058,7 +1071,7 @@ pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lo))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector {
+pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector {
     lo(vss)
 }
 
@@ -1070,7 +1083,7 @@ pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lvsplatw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector {
     lvsplatw(rt)
 }
 
@@ -1082,7 +1095,7 @@ pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffh(vu, vv)
 }
 
@@ -1094,7 +1107,7 @@ pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffub(vu, vv)
 }
 
@@ -1106,7 +1119,7 @@ pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffuh(vu, vv)
 }
 
@@ -1118,7 +1131,7 @@ pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vabsdiffw(vu, vv)
 }
 
@@ -1130,7 +1143,7 @@ pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector {
     vabsh(vu)
 }
 
@@ -1142,7 +1155,7 @@ pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector {
     vabsh_sat(vu)
 }
 
@@ -1154,7 +1167,7 @@ pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector {
     vabsw(vu)
 }
 
@@ -1166,7 +1179,7 @@ pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector {
     vabsw_sat(vu)
 }
 
@@ -1178,7 +1191,7 @@ pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddb(vu, vv)
 }
 
@@ -1190,7 +1203,7 @@ pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddb_dv(vuu, vvv)
 }
 
@@ -1202,7 +1215,7 @@ pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddh(vu, vv)
 }
 
@@ -1214,7 +1227,7 @@ pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddh_dv(vuu, vvv)
 }
 
@@ -1226,7 +1239,7 @@ pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddhsat(vu, vv)
 }
 
@@ -1238,7 +1251,7 @@ pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddhsat_dv(vuu, vvv)
 }
 
@@ -1250,7 +1263,7 @@ pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vaddhw(vu, vv)
 }
 
@@ -1262,7 +1275,7 @@ pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vaddubh(vu, vv)
 }
 
@@ -1274,7 +1287,7 @@ pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddubsat(vu, vv)
 }
 
@@ -1286,7 +1299,7 @@ pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddubsat_dv(vuu, vvv)
 }
 
@@ -1298,7 +1311,7 @@ pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadduhsat(vu, vv)
 }
 
@@ -1310,7 +1323,7 @@ pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vadduhsat_dv(vuu, vvv)
 }
 
@@ -1322,7 +1335,7 @@ pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vadduhw(vu, vv)
 }
 
@@ -1334,7 +1347,7 @@ pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_add(vu, vv)
 }
 
@@ -1346,7 +1359,7 @@ pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddw_dv(vuu, vvv)
 }
 
@@ -1358,7 +1371,7 @@ pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddwsat(vu, vv)
 }
 
@@ -1370,7 +1383,7 @@ pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddwsat_dv(vuu, vvv)
 }
 
@@ -1382,7 +1395,7 @@ pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     valignb(vu, vv, rt)
 }
 
@@ -1394,7 +1407,7 @@ pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
     valignbi(vu, vv, iu3)
 }
 
@@ -1406,7 +1419,7 @@ pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vand))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_and(vu, vv)
 }
 
@@ -1418,7 +1431,7 @@ pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector {
     vaslh(vu, rt)
 }
 
@@ -1430,7 +1443,7 @@ pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaslhv(vu, vv)
 }
 
@@ -1442,7 +1455,7 @@ pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector {
     vaslw(vu, rt)
 }
 
@@ -1454,7 +1467,7 @@ pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vaslw_acc(vx, vu, rt)
 }
 
@@ -1466,7 +1479,7 @@ pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaslwv(vu, vv)
 }
 
@@ -1478,7 +1491,7 @@ pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector {
     vasrh(vu, rt)
 }
 
@@ -1490,7 +1503,7 @@ pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhbrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhbrndsat(vu, vv, rt)
 }
 
@@ -1502,7 +1515,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhubrndsat(vu, vv, rt)
 }
 
@@ -1514,7 +1527,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhubsat(vu, vv, rt)
 }
 
@@ -1526,7 +1539,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vasrhv(vu, vv)
 }
 
@@ -1538,7 +1551,7 @@ pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector {
     vasrw(vu, rt)
 }
 
@@ -1550,7 +1563,7 @@ pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vasrw_acc(vx, vu, rt)
 }
 
@@ -1562,7 +1575,7 @@ pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwh(vu, vv, rt)
 }
 
@@ -1574,7 +1587,7 @@ pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwhrndsat(vu, vv, rt)
 }
 
@@ -1586,7 +1599,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwhsat(vu, vv, rt)
 }
 
@@ -1598,7 +1611,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwuhsat(vu, vv, rt)
 }
 
@@ -1610,7 +1623,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vasrwv(vu, vv)
 }
 
@@ -1622,7 +1635,7 @@ pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassign))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector {
     vassign(vu)
 }
 
@@ -1634,7 +1647,7 @@ pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassignp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair {
     vassignp(vuu)
 }
 
@@ -1646,7 +1659,7 @@ pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgh(vu, vv)
 }
 
@@ -1658,7 +1671,7 @@ pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavghrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavghrnd(vu, vv)
 }
 
@@ -1670,7 +1683,7 @@ pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgub(vu, vv)
 }
 
@@ -1682,7 +1695,7 @@ pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgubrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgubrnd(vu, vv)
 }
 
@@ -1694,7 +1707,7 @@ pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguh(vu, vv)
 }
 
@@ -1706,7 +1719,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguhrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguhrnd(vu, vv)
 }
 
@@ -1718,7 +1731,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgw(vu, vv)
 }
 
@@ -1730,7 +1743,7 @@ pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgwrnd(vu, vv)
 }
 
@@ -1742,7 +1755,7 @@ pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector {
     vcl0h(vu)
 }
 
@@ -1754,7 +1767,7 @@ pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector {
     vcl0w(vu)
 }
 
@@ -1766,7 +1779,7 @@ pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcombine))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vcombine(vu, vv)
 }
 
@@ -1778,7 +1791,7 @@ pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vzero() -> HvxVector {
+pub unsafe fn Q6_V_vzero() -> HvxVector {
     vd0()
 }
 
@@ -1790,7 +1803,7 @@ pub unsafe fn q6_v_vzero() -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector {
     vdealb(vu)
 }
 
@@ -1802,7 +1815,7 @@ pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb4w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdealb4w(vu, vv)
 }
 
@@ -1814,7 +1827,7 @@ pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector {
     vdealh(vu)
 }
 
@@ -1826,7 +1839,7 @@ pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vdealvdd(vu, vv, rt)
 }
 
@@ -1838,7 +1851,7 @@ pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdelta(vu, vv)
 }
 
@@ -1850,7 +1863,7 @@ pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpybus(vu, rt)
 }
 
@@ -1862,7 +1875,7 @@ pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpybus_acc(vx, vu, rt)
 }
 
@@ -1874,7 +1887,7 @@ pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vdmpybus_dv(vuu, rt)
 }
 
@@ -1886,7 +1899,7 @@ pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vdmpyacc_whwubrb(
+pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -1902,7 +1915,7 @@ pub unsafe fn q6_wh_vdmpyacc_whwubrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhb(vu, rt)
 }
 
@@ -1914,7 +1927,7 @@ pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhb_acc(vx, vu, rt)
 }
 
@@ -1926,7 +1939,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vdmpyhb_dv(vuu, rt)
 }
 
@@ -1938,7 +1951,7 @@ pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vdmpyacc_wwwhrb(
+pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -1954,7 +1967,7 @@ pub unsafe fn q6_ww_vdmpyacc_wwwhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhisat(vuu, rt)
 }
 
@@ -1966,7 +1979,7 @@ pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhisat_acc(vx, vuu, rt)
 }
 
@@ -1978,7 +1991,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsat(vu, rt)
 }
 
@@ -1990,7 +2003,7 @@ pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsat_acc(vx, vu, rt)
 }
 
@@ -2002,7 +2015,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhsuisat(vuu, rt)
 }
 
@@ -2014,7 +2027,7 @@ pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector {
     vdmpyhsuisat_acc(vx, vuu, rt)
 }
 
@@ -2026,7 +2039,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt:
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsusat(vu, rt)
 }
 
@@ -2038,7 +2051,7 @@ pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vdmpyhsusat_acc(vx, vu, rt)
 }
 
@@ -2050,7 +2063,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpyhvsat(vu, vv)
 }
 
@@ -2062,7 +2075,7 @@ pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpyhvsat_acc(vx, vu, vv)
 }
 
@@ -2074,7 +2087,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vdsaduh(vuu, rt)
 }
 
@@ -2086,7 +2099,7 @@ pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh(
+pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -2102,7 +2115,7 @@ pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vinsertwr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector {
     vinsertwr(vx, rt)
 }
 
@@ -2114,7 +2127,7 @@ pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vlalignb(vu, vv, rt)
 }
 
@@ -2126,7 +2139,7 @@ pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
     vlalignbi(vu, vv, iu3)
 }
 
@@ -2138,7 +2151,7 @@ pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector {
     vlsrh(vu, rt)
 }
 
@@ -2150,7 +2163,7 @@ pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vlsrhv(vu, vv)
 }
 
@@ -2162,7 +2175,7 @@ pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector {
     vlsrw(vu, rt)
 }
 
@@ -2174,7 +2187,7 @@ pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vlsrwv(vu, vv)
 }
 
@@ -2186,7 +2199,7 @@ pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vlutvvb(vu, vv, rt)
 }
 
@@ -2198,7 +2211,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32or_vbvbvbr(
+pub unsafe fn Q6_Vb_vlut32or_VbVbVbR(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -2215,7 +2228,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbr(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vlutvwh(vu, vv, rt)
 }
 
@@ -2227,7 +2240,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16or_whvbvhr(
+pub unsafe fn Q6_Wh_vlut16or_WhVbVhR(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2244,7 +2257,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhr(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxh(vu, vv)
 }
 
@@ -2256,7 +2269,7 @@ pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxub(vu, vv)
 }
 
@@ -2268,7 +2281,7 @@ pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxuh(vu, vv)
 }
 
@@ -2280,7 +2293,7 @@ pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxw(vu, vv)
 }
 
@@ -2292,7 +2305,7 @@ pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminh(vu, vv)
 }
 
@@ -2304,7 +2317,7 @@ pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminub(vu, vv)
 }
 
@@ -2316,7 +2329,7 @@ pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminuh(vu, vv)
 }
 
@@ -2328,7 +2341,7 @@ pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminw(vu, vv)
 }
 
@@ -2340,7 +2353,7 @@ pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpabus(vuu, rt)
 }
 
@@ -2352,7 +2365,7 @@ pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpaacc_whwubrb(
+pub unsafe fn Q6_Wh_vmpaacc_WhWubRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -2368,7 +2381,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vmpabusv(vuu, vvv)
 }
 
@@ -2380,7 +2393,7 @@ pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabuuv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vmpabuuv(vuu, vvv)
 }
 
@@ -2392,7 +2405,7 @@ pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpahb(vuu, rt)
 }
 
@@ -2404,7 +2417,7 @@ pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpaacc_wwwhrb(
+pub unsafe fn Q6_Ww_vmpaacc_WwWhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -2420,7 +2433,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpybus(vu, rt)
 }
 
@@ -2432,7 +2445,7 @@ pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpybus_acc(vxx, vu, rt)
 }
 
@@ -2444,7 +2457,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpybusv(vu, vv)
 }
 
@@ -2456,7 +2469,7 @@ pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpyacc_whvubvb(
+pub unsafe fn Q6_Wh_vmpyacc_WhVubVb(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2472,7 +2485,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubvb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpybv(vu, vv)
 }
 
@@ -2484,7 +2497,7 @@ pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpyacc_whvbvb(
+pub unsafe fn Q6_Wh_vmpyacc_WhVbVb(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2500,7 +2513,7 @@ pub unsafe fn q6_wh_vmpyacc_whvbvb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyewuh(vu, vv)
 }
 
@@ -2512,7 +2525,7 @@ pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyh(vu, rt)
 }
 
@@ -2524,7 +2537,7 @@ pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat(
+pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat(
     vxx: HvxVectorPair,
     vu: HvxVector,
     rt: i32,
@@ -2540,7 +2553,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyhsrs(vu, rt)
 }
 
@@ -2552,7 +2565,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhss))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyhss(vu, rt)
 }
 
@@ -2564,7 +2577,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyhus(vu, vv)
 }
 
@@ -2576,7 +2589,7 @@ pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhvuh(
+pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2592,7 +2605,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvuh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyhv(vu, vv)
 }
 
@@ -2604,7 +2617,7 @@ pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhvh(
+pub unsafe fn Q6_Ww_vmpyacc_WwVhVh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2620,7 +2633,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhvsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyhvsrs(vu, vv)
 }
 
@@ -2632,7 +2645,7 @@ pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyieoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyieoh(vu, vv)
 }
 
@@ -2644,7 +2657,7 @@ pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiewh_acc(vx, vu, vv)
 }
 
@@ -2656,7 +2669,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiewuh(vu, vv)
 }
 
@@ -2668,7 +2681,7 @@ pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiewuh_acc(vx, vu, vv)
 }
 
@@ -2680,7 +2693,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyih(vu, vv)
 }
 
@@ -2692,7 +2705,7 @@ pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyih_acc(vx, vu, vv)
 }
 
@@ -2704,7 +2717,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyihb(vu, rt)
 }
 
@@ -2716,7 +2729,7 @@ pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyihb_acc(vx, vu, rt)
 }
 
@@ -2728,7 +2741,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyiowh(vu, vv)
 }
 
@@ -2740,7 +2753,7 @@ pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwb(vu, rt)
 }
 
@@ -2752,7 +2765,7 @@ pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwb_acc(vx, vu, rt)
 }
 
@@ -2764,7 +2777,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwh(vu, rt)
 }
 
@@ -2776,7 +2789,7 @@ pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwh_acc(vx, vu, rt)
 }
 
@@ -2788,7 +2801,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyowh(vu, vv)
 }
 
@@ -2800,7 +2813,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyowh_rnd(vu, vv)
 }
 
@@ -2812,7 +2825,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift(
+pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -2828,7 +2841,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift(
+pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -2844,7 +2857,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyub(vu, rt)
 }
 
@@ -2856,7 +2869,7 @@ pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpyacc_wuhvubrub(
+pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub(
     vxx: HvxVectorPair,
     vu: HvxVector,
     rt: i32,
@@ -2872,7 +2885,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubrub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyubv(vu, vv)
 }
 
@@ -2884,7 +2897,7 @@ pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vmpyacc_wuhvubvub(
+pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2900,7 +2913,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubvub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyuh(vu, rt)
 }
 
@@ -2912,7 +2925,7 @@ pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh(
+pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     rt: i32,
@@ -2928,7 +2941,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyuhv(vu, vv)
 }
 
@@ -2940,7 +2953,7 @@ pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh(
+pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -2956,7 +2969,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgh(vu, vv)
 }
 
@@ -2968,7 +2981,7 @@ pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgub(vu, vv)
 }
 
@@ -2980,7 +2993,7 @@ pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgw(vu, vv)
 }
 
@@ -2992,7 +3005,7 @@ pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector {
     vnormamth(vu)
 }
 
@@ -3004,7 +3017,7 @@ pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamtw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector {
     vnormamtw(vu)
 }
 
@@ -3016,7 +3029,7 @@ pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnot))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector {
     vnot(vu)
 }
 
@@ -3028,7 +3041,7 @@ pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_or(vu, vv)
 }
 
@@ -3040,7 +3053,7 @@ pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackeb(vu, vv)
 }
 
@@ -3052,7 +3065,7 @@ pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackeh(vu, vv)
 }
 
@@ -3064,7 +3077,7 @@ pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackhb_sat(vu, vv)
 }
 
@@ -3076,7 +3089,7 @@ pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhub_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackhub_sat(vu, vv)
 }
 
@@ -3088,7 +3101,7 @@ pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackob(vu, vv)
 }
 
@@ -3100,7 +3113,7 @@ pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackoh(vu, vv)
 }
 
@@ -3112,7 +3125,7 @@ pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackwh_sat(vu, vv)
 }
 
@@ -3124,7 +3137,7 @@ pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwuh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vpackwuh_sat(vu, vv)
 }
 
@@ -3136,7 +3149,7 @@ pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpopcounth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector {
     vpopcounth(vu)
 }
 
@@ -3148,7 +3161,7 @@ pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrdelta(vu, vv)
 }
 
@@ -3160,7 +3173,7 @@ pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
     vrmpybus(vu, rt)
 }
 
@@ -3172,7 +3185,7 @@ pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vrmpybus_acc(vx, vu, rt)
 }
 
@@ -3184,7 +3197,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
     vrmpybusi(vuu, rt, iu1)
 }
 
@@ -3196,7 +3209,7 @@ pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vrmpyacc_wwwubrbi(
+pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3213,7 +3226,7 @@ pub unsafe fn q6_ww_vrmpyacc_wwwubrbi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybusv(vu, vv)
 }
 
@@ -3225,7 +3238,7 @@ pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybusv_acc(vx, vu, vv)
 }
 
@@ -3237,7 +3250,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybv(vu, vv)
 }
 
@@ -3249,7 +3262,7 @@ pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpybv_acc(vx, vu, vv)
 }
 
@@ -3261,7 +3274,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector {
     vrmpyub(vu, rt)
 }
 
@@ -3273,7 +3286,7 @@ pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vrmpyub_acc(vx, vu, rt)
 }
 
@@ -3285,7 +3298,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
     vrmpyubi(vuu, rt, iu1)
 }
 
@@ -3297,7 +3310,7 @@ pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi(
+pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3314,7 +3327,7 @@ pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpyubv(vu, vv)
 }
 
@@ -3326,7 +3339,7 @@ pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrmpyubv_acc(vx, vu, vv)
 }
 
@@ -3338,7 +3351,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vror))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector {
     vror(vu, rt)
 }
 
@@ -3350,7 +3363,7 @@ pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundhb(vu, vv)
 }
 
@@ -3362,7 +3375,7 @@ pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundhub(vu, vv)
 }
 
@@ -3374,7 +3387,7 @@ pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundwh(vu, vv)
 }
 
@@ -3386,7 +3399,7 @@ pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vroundwuh(vu, vv)
 }
 
@@ -3398,7 +3411,7 @@ pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair {
     vrsadubi(vuu, rt, iu1)
 }
 
@@ -3410,7 +3423,7 @@ pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi(
+pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3427,7 +3440,7 @@ pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsathub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsathub(vu, vv)
 }
 
@@ -3439,7 +3452,7 @@ pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsatwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsatwh(vu, vv)
 }
 
@@ -3451,7 +3464,7 @@ pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair {
     vsb(vu)
 }
 
@@ -3463,7 +3476,7 @@ pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair {
     vsh(vu)
 }
 
@@ -3475,7 +3488,7 @@ pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshufeh(vu, vv)
 }
 
@@ -3487,7 +3500,7 @@ pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector {
     vshuffb(vu)
 }
 
@@ -3499,7 +3512,7 @@ pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshuffeb(vu, vv)
 }
 
@@ -3511,7 +3524,7 @@ pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector {
     vshuffh(vu)
 }
 
@@ -3523,7 +3536,7 @@ pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshuffob(vu, vv)
 }
 
@@ -3535,7 +3548,7 @@ pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vshuffvdd(vu, vv, rt)
 }
 
@@ -3547,7 +3560,7 @@ pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vshufoeb(vu, vv)
 }
 
@@ -3559,7 +3572,7 @@ pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vshufoeh(vu, vv)
 }
 
@@ -3571,7 +3584,7 @@ pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vshufoh(vu, vv)
 }
 
@@ -3583,7 +3596,7 @@ pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubb(vu, vv)
 }
 
@@ -3595,7 +3608,7 @@ pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubb_dv(vuu, vvv)
 }
 
@@ -3607,7 +3620,7 @@ pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubh(vu, vv)
 }
 
@@ -3619,7 +3632,7 @@ pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubh_dv(vuu, vvv)
 }
 
@@ -3631,7 +3644,7 @@ pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubhsat(vu, vv)
 }
 
@@ -3643,7 +3656,7 @@ pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubhsat_dv(vuu, vvv)
 }
 
@@ -3655,7 +3668,7 @@ pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsubhw(vu, vv)
 }
 
@@ -3667,7 +3680,7 @@ pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsububh(vu, vv)
 }
 
@@ -3679,7 +3692,7 @@ pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsububsat(vu, vv)
 }
 
@@ -3691,7 +3704,7 @@ pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsububsat_dv(vuu, vvv)
 }
 
@@ -3703,7 +3716,7 @@ pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubuhsat(vu, vv)
 }
 
@@ -3715,7 +3728,7 @@ pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubuhsat_dv(vuu, vvv)
 }
 
@@ -3727,7 +3740,7 @@ pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsubuhw(vu, vv)
 }
 
@@ -3739,7 +3752,7 @@ pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_sub(vu, vv)
 }
 
@@ -3751,7 +3764,7 @@ pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubw_dv(vuu, vvv)
 }
 
@@ -3763,7 +3776,7 @@ pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubwsat(vu, vv)
 }
 
@@ -3775,7 +3788,7 @@ pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubwsat_dv(vuu, vvv)
 }
 
@@ -3787,7 +3800,7 @@ pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vtmpyb(vuu, rt)
 }
 
@@ -3799,7 +3812,7 @@ pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpyacc_whwbrb(
+pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3815,7 +3828,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwbrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vtmpybus(vuu, rt)
 }
 
@@ -3827,7 +3840,7 @@ pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vtmpyacc_whwubrb(
+pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3843,7 +3856,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwubrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vtmpyhb(vuu, rt)
 }
 
@@ -3855,7 +3868,7 @@ pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vtmpyacc_wwwhrb(
+pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -3871,7 +3884,7 @@ pub unsafe fn q6_ww_vtmpyacc_wwwhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair {
     vunpackb(vu)
 }
 
@@ -3883,7 +3896,7 @@ pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair {
     vunpackh(vu)
 }
 
@@ -3895,7 +3908,7 @@ pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
     vunpackob(vxx, vu)
 }
 
@@ -3907,7 +3920,7 @@ pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair {
     vunpackoh(vxx, vu)
 }
 
@@ -3919,7 +3932,7 @@ pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair {
     vunpackub(vu)
 }
 
@@ -3931,7 +3944,7 @@ pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair {
     vunpackuh(vu)
 }
 
@@ -3943,7 +3956,7 @@ pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vxor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     simd_xor(vu, vv)
 }
 
@@ -3955,7 +3968,7 @@ pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair {
     vzb(vu)
 }
 
@@ -3967,7 +3980,7 @@ pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair {
     vzh(vu)
 }
 
@@ -3979,7 +3992,7 @@ pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplatb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector {
     lvsplatb(rt)
 }
 
@@ -3991,7 +4004,7 @@ pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplath))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector {
     lvsplath(rt)
 }
 
@@ -4003,7 +4016,7 @@ pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddbsat(vu, vv)
 }
 
@@ -4015,7 +4028,7 @@ pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vaddbsat_dv(vuu, vvv)
 }
 
@@ -4027,7 +4040,7 @@ pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddclbh(vu, vv)
 }
 
@@ -4039,7 +4052,7 @@ pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddclbw(vu, vv)
 }
 
@@ -4051,7 +4064,7 @@ pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vaddacc_wwvhvh(
+pub unsafe fn Q6_Ww_vaddacc_WwVhVh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4067,7 +4080,7 @@ pub unsafe fn q6_ww_vaddacc_wwvhvh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddubh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vaddacc_whvubvub(
+pub unsafe fn Q6_Wh_vaddacc_WhVubVub(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4083,7 +4096,7 @@ pub unsafe fn q6_wh_vaddacc_whvubvub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vaddububb_sat(vu, vv)
 }
 
@@ -4095,7 +4108,7 @@ pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vaddacc_wwvuhvuh(
+pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4111,7 +4124,7 @@ pub unsafe fn q6_ww_vaddacc_wwvuhvuh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadduwsat(vu, vv)
 }
 
@@ -4123,7 +4136,7 @@ pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vadduwsat_dv(vuu, vvv)
 }
 
@@ -4135,7 +4148,7 @@ pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrhbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrhbsat(vu, vv, rt)
 }
 
@@ -4147,7 +4160,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasruwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruwuhrndsat(vu, vv, rt)
 }
 
@@ -4159,7 +4172,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasrwuhrndsat(vu, vv, rt)
 }
 
@@ -4171,7 +4184,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlsrb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector {
     vlsrb(vu, rt)
 }
 
@@ -4183,7 +4196,7 @@ pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vlutvvb_nm(vu, vv, rt)
 }
 
@@ -4195,7 +4208,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32or_vbvbvbi(
+pub unsafe fn Q6_Vb_vlut32or_VbVbVbI(
     vx: HvxVector,
     vu: HvxVector,
     vv: HvxVector,
@@ -4212,7 +4225,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
+pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector {
     vlutvvbi(vu, vv, iu3)
 }
 
@@ -4224,7 +4237,7 @@ pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair {
     vlutvwh_nm(vu, vv, rt)
 }
 
@@ -4236,7 +4249,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16or_whvbvhi(
+pub unsafe fn Q6_Wh_vlut16or_WhVbVhI(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4253,7 +4266,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhi(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwhi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair {
     vlutvwhi(vu, vv, iu3)
 }
 
@@ -4265,7 +4278,7 @@ pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmaxb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmaxb(vu, vv)
 }
 
@@ -4277,7 +4290,7 @@ pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vminb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vminb(vu, vv)
 }
 
@@ -4289,7 +4302,7 @@ pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpauhb(vuu, rt)
 }
 
@@ -4301,7 +4314,7 @@ pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpaacc_wwwuhrb(
+pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -4317,7 +4330,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwuhrb(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyewuh_64))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpyewuh_64(vu, vv)
 }
 
@@ -4329,7 +4342,7 @@ pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwub(vu, rt)
 }
 
@@ -4341,7 +4354,7 @@ pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyiwub_acc(vx, vu, rt)
 }
 
@@ -4353,7 +4366,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vmpyoacc_wvwvh(
+pub unsafe fn Q6_W_vmpyoacc_WVwVh(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4369,7 +4382,7 @@ pub unsafe fn q6_w_vmpyoacc_wvwvh(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrounduhub(vu, vv)
 }
 
@@ -4381,7 +4394,7 @@ pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrounduwuh(vu, vv)
 }
 
@@ -4393,7 +4406,7 @@ pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsatuwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsatuwuh(vu, vv)
 }
 
@@ -4405,7 +4418,7 @@ pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubbsat(vu, vv)
 }
 
@@ -4417,7 +4430,7 @@ pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubbsat_dv(vuu, vvv)
 }
 
@@ -4429,7 +4442,7 @@ pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubububb_sat(vu, vv)
 }
 
@@ -4441,7 +4454,7 @@ pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsubuwsat(vu, vv)
 }
 
@@ -4453,7 +4466,7 @@ pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
+pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair {
     vsubuwsat_dv(vuu, vvv)
 }
 
@@ -4465,7 +4478,7 @@ pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector {
     vabsb(vu)
 }
 
@@ -4477,7 +4490,7 @@ pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector {
     vabsb_sat(vu)
 }
 
@@ -4489,7 +4502,7 @@ pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vaslh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vaslh_acc(vx, vu, rt)
 }
 
@@ -4501,7 +4514,7 @@ pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasrh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vasrh_acc(vx, vu, rt)
 }
 
@@ -4513,7 +4526,7 @@ pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruhubrndsat(vu, vv, rt)
 }
 
@@ -4525,7 +4538,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruhubsat(vu, vv, rt)
 }
 
@@ -4537,7 +4550,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector {
     vasruwuhsat(vu, vv, rt)
 }
 
@@ -4549,7 +4562,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgb(vu, vv)
 }
 
@@ -4561,7 +4574,7 @@ pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgbrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavgbrnd(vu, vv)
 }
 
@@ -4573,7 +4586,7 @@ pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguw(vu, vv)
 }
 
@@ -4585,7 +4598,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vavguwrnd(vu, vv)
 }
 
@@ -4597,7 +4610,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vdd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vzero() -> HvxVectorPair {
+pub unsafe fn Q6_W_vzero() -> HvxVectorPair {
     vdd0()
 }
 
@@ -4609,7 +4622,7 @@ pub unsafe fn q6_w_vzero() -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
     vgathermh(rs, rt, mu, vv)
 }
 
@@ -4621,7 +4634,7 @@ pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
+pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) {
     vgathermhw(rs, rt, mu, vvv)
 }
 
@@ -4633,7 +4646,7 @@ pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
+pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) {
     vgathermw(rs, rt, mu, vv)
 }
 
@@ -4645,7 +4658,7 @@ pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
     vmpabuu(vuu, rt)
 }
 
@@ -4657,7 +4670,7 @@ pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wh_vmpaacc_whwubrub(
+pub unsafe fn Q6_Wh_vmpaacc_WhWubRub(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     rt: i32,
@@ -4673,7 +4686,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrub(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
+pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair {
     vmpyh_acc(vxx, vu, rt)
 }
 
@@ -4685,7 +4698,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector {
     vmpyuhe(vu, rt)
 }
 
@@ -4697,7 +4710,7 @@ pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector {
     vmpyuhe_acc(vx, vu, rt)
 }
 
@@ -4709,7 +4722,7 @@ pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vnavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vnavgb(vu, vv)
 }
 
@@ -4721,7 +4734,7 @@ pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermh(rt, mu, vv, vw)
 }
 
@@ -4733,7 +4746,7 @@ pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermh_add(rt, mu, vv, vw)
 }
 
@@ -4745,7 +4758,7 @@ pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
     vscattermhw(rt, mu, vvv, vw)
 }
 
@@ -4757,7 +4770,7 @@ pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
+pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) {
     vscattermhw_add(rt, mu, vvv, vw)
 }
 
@@ -4769,7 +4782,7 @@ pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermw(rt, mu, vv, vw)
 }
 
@@ -4781,7 +4794,7 @@ pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
+pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) {
     vscattermw_add(rt, mu, vv, vw)
 }
 
@@ -4793,7 +4806,7 @@ pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vasr_into))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_vasrinto_wwvwvw(
+pub unsafe fn Q6_Ww_vasrinto_WwVwVw(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -4809,7 +4822,7 @@ pub unsafe fn q6_ww_vasrinto_wwvwvw(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vrotr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vrotr(vu, vv)
 }
 
@@ -4821,7 +4834,7 @@ pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vsatdw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsatdw(vu, vv)
 }
 
@@ -4833,7 +4846,7 @@ pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpy_wubwbi_h(
+pub unsafe fn Q6_Ww_v6mpy_WubWbI_h(
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
     iu2: i32,
@@ -4849,7 +4862,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_h(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h(
+pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
@@ -4866,7 +4879,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpy_wubwbi_v(
+pub unsafe fn Q6_Ww_v6mpy_WubWbI_v(
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
     iu2: i32,
@@ -4882,7 +4895,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_v(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v(
+pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v(
     vxx: HvxVectorPair,
     vuu: HvxVectorPair,
     vvv: HvxVectorPair,
@@ -4899,7 +4912,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector {
     vabs_hf(vu)
 }
 
@@ -4911,7 +4924,7 @@ pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector {
     vabs_sf(vu)
 }
 
@@ -4923,7 +4936,7 @@ pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_hf(vu, vv)
 }
 
@@ -4935,7 +4948,7 @@ pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_hf_hf(vu, vv)
 }
 
@@ -4947,7 +4960,7 @@ pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf16(vu, vv)
 }
 
@@ -4959,7 +4972,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf16_mix(vu, vv)
 }
 
@@ -4971,7 +4984,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf32(vu, vv)
 }
 
@@ -4983,7 +4996,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_qf32_mix(vu, vv)
 }
 
@@ -4995,7 +5008,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_sf(vu, vv)
 }
 
@@ -5007,7 +5020,7 @@ pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vadd_sf_hf(vu, vv)
 }
 
@@ -5019,7 +5032,7 @@ pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vadd_sf_sf(vu, vv)
 }
 
@@ -5031,7 +5044,7 @@ pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vassign_fp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector {
     vassign_fp(vu)
 }
 
@@ -5043,7 +5056,7 @@ pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector {
     vconv_hf_qf16(vu)
 }
 
@@ -5055,7 +5068,7 @@ pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector {
+pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector {
     vconv_hf_qf32(vuu)
 }
 
@@ -5067,7 +5080,7 @@ pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_sf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector {
     vconv_sf_qf32(vu)
 }
 
@@ -5079,7 +5092,7 @@ pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_b_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vcvt_b_hf(vu, vv)
 }
 
@@ -5091,7 +5104,7 @@ pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
     vcvt_h_hf(vu)
 }
 
@@ -5103,7 +5116,7 @@ pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair {
     vcvt_hf_b(vu)
 }
 
@@ -5115,7 +5128,7 @@ pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector {
     vcvt_hf_h(vu)
 }
 
@@ -5127,7 +5140,7 @@ pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vcvt_hf_sf(vu, vv)
 }
 
@@ -5139,7 +5152,7 @@ pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair {
     vcvt_hf_ub(vu)
 }
 
@@ -5151,7 +5164,7 @@ pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_uh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector {
     vcvt_hf_uh(vu)
 }
 
@@ -5163,7 +5176,7 @@ pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair {
     vcvt_sf_hf(vu)
 }
 
@@ -5175,7 +5188,7 @@ pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_ub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vcvt_ub_hf(vu, vv)
 }
 
@@ -5187,7 +5200,7 @@ pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_uh_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
     vcvt_uh_hf(vu)
 }
 
@@ -5199,7 +5212,7 @@ pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpy_sf_hf(vu, vv)
 }
 
@@ -5211,7 +5224,7 @@ pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vdmpy_sf_hf_acc(vx, vu, vv)
 }
 
@@ -5223,7 +5236,7 @@ pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmax_hf(vu, vv)
 }
 
@@ -5235,7 +5248,7 @@ pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmax_sf(vu, vv)
 }
 
@@ -5247,7 +5260,7 @@ pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmin_hf(vu, vv)
 }
 
@@ -5259,7 +5272,7 @@ pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmin_sf(vu, vv)
 }
 
@@ -5271,7 +5284,7 @@ pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector {
     vfneg_hf(vu)
 }
 
@@ -5283,7 +5296,7 @@ pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector {
     vfneg_sf(vu)
 }
 
@@ -5295,7 +5308,7 @@ pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmax_hf(vu, vv)
 }
 
@@ -5307,7 +5320,7 @@ pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmax_sf(vu, vv)
 }
 
@@ -5319,7 +5332,7 @@ pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmin_hf(vu, vv)
 }
 
@@ -5331,7 +5344,7 @@ pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmin_sf(vu, vv)
 }
 
@@ -5343,7 +5356,7 @@ pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_hf_hf(vu, vv)
 }
 
@@ -5355,7 +5368,7 @@ pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_hf_hf_acc(vx, vu, vv)
 }
 
@@ -5367,7 +5380,7 @@ pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVect
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf16(vu, vv)
 }
 
@@ -5379,7 +5392,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf16_hf(vu, vv)
 }
 
@@ -5391,7 +5404,7 @@ pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf16_mix_hf(vu, vv)
 }
 
@@ -5403,7 +5416,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf32(vu, vv)
 }
 
@@ -5415,7 +5428,7 @@ pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_qf32_hf(vu, vv)
 }
 
@@ -5427,7 +5440,7 @@ pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_qf32_mix_hf(vu, vv)
 }
 
@@ -5439,7 +5452,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_qf32_qf16(vu, vv)
 }
 
@@ -5451,7 +5464,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_qf32_sf(vu, vv)
 }
 
@@ -5463,7 +5476,7 @@ pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vmpy_sf_hf(vu, vv)
 }
 
@@ -5475,7 +5488,7 @@ pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf(
+pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf(
     vxx: HvxVectorPair,
     vu: HvxVector,
     vv: HvxVector,
@@ -5491,7 +5504,7 @@ pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf(
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpy_sf_sf(vu, vv)
 }
 
@@ -5503,7 +5516,7 @@ pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_hf(vu, vv)
 }
 
@@ -5515,7 +5528,7 @@ pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_hf_hf(vu, vv)
 }
 
@@ -5527,7 +5540,7 @@ pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf16(vu, vv)
 }
 
@@ -5539,7 +5552,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf16_mix(vu, vv)
 }
 
@@ -5551,7 +5564,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf32(vu, vv)
 }
 
@@ -5563,7 +5576,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_qf32_mix(vu, vv)
 }
 
@@ -5575,7 +5588,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_sf(vu, vv)
 }
 
@@ -5587,7 +5600,7 @@ pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vsub_sf_hf(vu, vv)
 }
 
@@ -5599,7 +5612,7 @@ pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vsub_sf_sf(vu, vv)
 }
 
@@ -5611,7 +5624,7 @@ pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvuhubrndsat(vuu, vv)
 }
 
@@ -5623,7 +5636,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvuhubsat(vuu, vv)
 }
 
@@ -5635,7 +5648,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvwuhrndsat(vuu, vv)
 }
 
@@ -5647,7 +5660,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector {
     vasrvwuhsat(vuu, vv)
 }
 
@@ -5659,7 +5672,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vmpyuhvs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmpyuhvs(vu, vv)
 }
 
@@ -5671,7 +5684,7 @@ pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector {
     vconv_h_hf(vu)
 }
 
@@ -5683,7 +5696,7 @@ pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector {
     vconv_hf_h(vu)
 }
 
@@ -5695,7 +5708,7 @@ pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_sf_w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector {
     vconv_sf_w(vu)
 }
 
@@ -5707,7 +5720,7 @@ pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_w_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector {
     vconv_w_sf(vu)
 }
 
@@ -5719,7 +5732,7 @@ pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(get_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
     get_qfext(vu, rt)
 }
 
@@ -5731,7 +5744,7 @@ pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(set_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
     set_qfext(vu, rt)
 }
 
@@ -5743,7 +5756,7 @@ pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vabs_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector {
     vabs_f8(vu)
 }
 
@@ -5755,7 +5768,7 @@ pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair {
     vcvt2_hf_b(vu)
 }
 
@@ -5767,7 +5780,7 @@ pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair {
     vcvt2_hf_ub(vu)
 }
 
@@ -5779,7 +5792,7 @@ pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair {
     vcvt_hf_f8(vu)
 }
 
@@ -5791,7 +5804,7 @@ pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmax_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmax_f8(vu, vv)
 }
 
@@ -5803,7 +5816,7 @@ pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmin_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
     vfmin_f8(vu, vv)
 }
 
@@ -5815,7 +5828,7 @@ pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector {
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfneg_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector {
     vfneg_f8(vu)
 }
 
@@ -5827,7 +5840,7 @@ pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_and(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5845,7 +5858,7 @@ pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_and_n(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5863,7 +5876,7 @@ pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_not(vandvrt(
             core::mem::transmute::<HvxVectorPred, HvxVector>(qs),
@@ -5881,7 +5894,7 @@ pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_or(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5899,7 +5912,7 @@ pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_or_n(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5917,7 +5930,7 @@ pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2(rt), -1))
 }
 
@@ -5929,7 +5942,7 @@ pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         pred_xor(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -5947,7 +5960,7 @@ pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_nqpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -5963,7 +5976,7 @@ pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_nt_nqpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -5979,7 +5992,7 @@ pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_nt_qpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -5995,7 +6008,7 @@ pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
+pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
     vS32b_qpred_ai(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         rt,
@@ -6011,7 +6024,7 @@ pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector)
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddbnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6027,7 +6040,7 @@ pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddbq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6043,7 +6056,7 @@ pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddhnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6059,7 +6072,7 @@ pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddhq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6075,7 +6088,7 @@ pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddwnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6091,7 +6104,7 @@ pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vaddwq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6107,7 +6120,7 @@ pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
 }
 
@@ -6119,7 +6132,7 @@ pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandvrt_acc(vx, core::mem::transmute::<HvxVectorPred, HvxVector>(qu), rt)
 }
 
@@ -6131,7 +6144,7 @@ pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vu, rt))
 }
 
@@ -6143,7 +6156,7 @@ pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt_acc(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qx),
         vu,
@@ -6159,7 +6172,7 @@ pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqb(vu, vv), -1))
 }
 
@@ -6171,7 +6184,7 @@ pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqand_qvbvb(
+pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6194,7 +6207,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqor_qvbvb(
+pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6217,7 +6230,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqxacc_qvbvb(
+pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6240,7 +6253,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqh(vu, vv), -1))
 }
 
@@ -6252,7 +6265,7 @@ pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqand_qvhvh(
+pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6275,7 +6288,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqor_qvhvh(
+pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6298,7 +6311,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqxacc_qvhvh(
+pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6321,7 +6334,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(veqw(vu, vv), -1))
 }
 
@@ -6333,7 +6346,7 @@ pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqand_qvwvw(
+pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6356,7 +6369,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqor_qvwvw(
+pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6379,7 +6392,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_eqxacc_qvwvw(
+pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6402,7 +6415,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtb(vu, vv), -1))
 }
 
@@ -6414,7 +6427,7 @@ pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvbvb(
+pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6437,7 +6450,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvbvb(
+pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6460,7 +6473,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvbvb(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6483,7 +6496,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvbvb(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgth(vu, vv), -1))
 }
 
@@ -6495,7 +6508,7 @@ pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvhvh(
+pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6518,7 +6531,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvhvh(
+pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6541,7 +6554,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvhvh(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6564,7 +6577,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtub(vu, vv), -1))
 }
 
@@ -6576,7 +6589,7 @@ pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvubvub(
+pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6599,7 +6612,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvubvub(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvubvub(
+pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6622,7 +6635,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvubvub(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvubvub(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6645,7 +6658,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvubvub(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuh(vu, vv), -1))
 }
 
@@ -6657,7 +6670,7 @@ pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvuhvuh(
+pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6680,7 +6693,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuhvuh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvuhvuh(
+pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6703,7 +6716,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuhvuh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6726,7 +6739,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtuw(vu, vv), -1))
 }
 
@@ -6738,7 +6751,7 @@ pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvuwvuw(
+pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6761,7 +6774,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuwvuw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvuwvuw(
+pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6784,7 +6797,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuwvuw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6807,7 +6820,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtw(vu, vv), -1))
 }
 
@@ -6819,7 +6832,7 @@ pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvwvw(
+pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6842,7 +6855,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvwvw(
+pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6865,7 +6878,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvwvw(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -6888,7 +6901,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvwvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
     vmux(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
         vu,
@@ -6904,7 +6917,7 @@ pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubbnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6920,7 +6933,7 @@ pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubbq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6936,7 +6949,7 @@ pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubhnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6952,7 +6965,7 @@ pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubhq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6968,7 +6981,7 @@ pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubwnq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -6984,7 +6997,7 @@ pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
     vsubwq(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vx,
@@ -7000,7 +7013,7 @@ pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
+pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
     vswap(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qt), -1),
         vu,
@@ -7016,7 +7029,7 @@ pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(pred_scalar2v2(rt), -1))
 }
 
@@ -7028,7 +7041,7 @@ pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         shuffeqh(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -7046,7 +7059,7 @@ pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
+pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(
         shuffeqw(
             vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qs), -1),
@@ -7064,7 +7077,7 @@ pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandnqrt(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
         rt,
@@ -7079,7 +7092,7 @@ pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
+pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
     vandnqrt_acc(
         vx,
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qu), -1),
@@ -7095,7 +7108,7 @@ pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
     vandvnqv(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vu,
@@ -7110,7 +7123,7 @@ pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
+pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
     vandvqv(
         vandvrt(core::mem::transmute::<HvxVectorPred, HvxVector>(qv), -1),
         vu,
@@ -7125,7 +7138,7 @@ pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_aqrmvh(
+pub unsafe fn Q6_vgather_AQRMVh(
     rs: *mut HvxVector,
     qs: HvxVectorPred,
     rt: i32,
@@ -7149,7 +7162,7 @@ pub unsafe fn q6_vgather_aqrmvh(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_aqrmww(
+pub unsafe fn Q6_vgather_AQRMWw(
     rs: *mut HvxVector,
     qs: HvxVectorPred,
     rt: i32,
@@ -7173,7 +7186,7 @@ pub unsafe fn q6_vgather_aqrmww(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vgather_aqrmvw(
+pub unsafe fn Q6_vgather_AQRMVw(
     rs: *mut HvxVector,
     qs: HvxVectorPred,
     rt: i32,
@@ -7197,7 +7210,7 @@ pub unsafe fn q6_vgather_aqrmvw(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
     vprefixqb(vandvrt(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
         -1,
@@ -7212,7 +7225,7 @@ pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
     vprefixqh(vandvrt(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
         -1,
@@ -7227,7 +7240,7 @@ pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
+pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
     vprefixqw(vandvrt(
         core::mem::transmute::<HvxVectorPred, HvxVector>(qv),
         -1,
@@ -7242,7 +7255,7 @@ pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector {
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_qrmvhv(
+pub unsafe fn Q6_vscatter_QRMVhV(
     qs: HvxVectorPred,
     rt: i32,
     mu: i32,
@@ -7266,7 +7279,7 @@ pub unsafe fn q6_vscatter_qrmvhv(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_qrmwwv(
+pub unsafe fn Q6_vscatter_QRMWwV(
     qs: HvxVectorPred,
     rt: i32,
     mu: i32,
@@ -7290,7 +7303,7 @@ pub unsafe fn q6_vscatter_qrmwwv(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vscatter_qrmvwv(
+pub unsafe fn Q6_vscatter_QRMVwV(
     qs: HvxVectorPred,
     rt: i32,
     mu: i32,
@@ -7314,7 +7327,7 @@ pub unsafe fn q6_vscatter_qrmvwv(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_vw_vadd_vwvwq_carry_sat(
+pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
     vu: HvxVector,
     vv: HvxVector,
     qs: HvxVectorPred,
@@ -7334,7 +7347,7 @@ pub unsafe fn q6_vw_vadd_vwvwq_carry_sat(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgthf(vu, vv), -1))
 }
 
@@ -7346,7 +7359,7 @@ pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvhfvhf(
+pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7369,7 +7382,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhfvhf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvhfvhf(
+pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7392,7 +7405,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhfvhf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7415,7 +7428,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
+pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
     core::mem::transmute::<HvxVector, HvxVectorPred>(vandqrt(vgtsf(vu, vv), -1))
 }
 
@@ -7427,7 +7440,7 @@ pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtand_qvsfvsf(
+pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7450,7 +7463,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvsfvsf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtor_qvsfvsf(
+pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
@@ -7473,7 +7486,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvsfvsf(
 #[inline(always)]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
-pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf(
+pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf(
     qx: HvxVectorPred,
     vu: HvxVector,
     vv: HvxVector,
diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 3cfbabfe0a..79837e2224 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -515,12 +515,6 @@ fn parse_header(content: &str) -> Vec<IntrinsicInfo> {
     intrinsics
 }
 
-/// Convert Q6 name to Rust function name (lowercase with underscores)
-fn q6_to_rust_name(q6_name: &str) -> String {
-    // Q6_V_hi_W -> q6_v_hi_w
-    q6_name.to_lowercase()
-}
-
 /// Generate the module documentation
 fn generate_module_doc(mode: VectorMode) -> String {
     format!(
@@ -541,6 +535,18 @@ fn generate_module_doc(mode: VectorMode) -> String {
 //!
 //! To use this module, compile with `-C target-feature=+{target_feature}`.
 //!
+//! ## Naming Convention
+//!
+//! Function names preserve the original Q6 naming case because the convention
+//! uses case to distinguish register types:
+//! - `W` (uppercase) = vector pair (`HvxVectorPair`)
+//! - `V` (uppercase) = vector (`HvxVector`)
+//! - `Q` (uppercase) = predicate (`HvxVectorPred`)
+//! - `R` = scalar register (`i32`)
+//!
+//! For example, `Q6_W_vcombine_VV` operates on a vector pair while
+//! `Q6_V_hi_W` extracts a vector from a pair.
+//!
 //! ## Architecture Versions
 //!
 //! Different intrinsics require different HVX architecture versions. Use the
@@ -577,6 +583,7 @@ fn generate_types(mode: VectorMode) -> String {
     format!(
         r#"
 #![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
@@ -1433,7 +1440,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String {
 
     // Generate simple intrinsics
     for info in intrinsics.iter().filter(|i| !i.is_compound) {
-        let rust_name = q6_to_rust_name(&info.q6_name);
+        let rust_name = &info.q6_name;
 
         // Generate doc comment
         output.push_str(&format!("/// `{}`\n", info.asm_syntax));
@@ -1505,7 +1512,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String {
     let overrides = get_compound_overrides();
     for info in intrinsics.iter().filter(|i| i.is_compound) {
         if let Some(ref compound_expr) = info.compound_expr {
-            let rust_name = q6_to_rust_name(&info.q6_name);
+            let rust_name = &info.q6_name;
 
             // Get the primary instruction for assert_instr
             let _primary_instr = get_compound_primary_instr(compound_expr)
diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index dea16f797a..a310c24def 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -95,30 +95,30 @@ mod hvx {
             let below = *inp2.add(i);
 
             // Widen above + below to 16-bit using HvxVectorPair
-            // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair
-            let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below);
+            // Q6_Wh_vadd_VubVub: adds two u8 vectors, producing u16 results in a pair
+            let above_plus_below: HvxVectorPair = Q6_Wh_vadd_VubVub(above, below);
 
             // Widen center * 2 (add center to itself)
-            let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center);
+            let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(center, center);
 
             // Add them: (above + below) + (center * 2) = above + 2*center + below
-            let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2);
+            let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(above_plus_below, center_x2);
 
             // Extract high and low vectors from the pair (each contains u16 values)
-            let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16
-            let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16
+            let sum_lo = Q6_V_lo_W(sum); // Lower 64 elements as i16
+            let sum_hi = Q6_V_hi_W(sum); // Upper 64 elements as i16
 
             // Arithmetic right shift by 2 (divide by 4) with rounding
             // Add 2 for rounding before shift: (sum + 2) >> 2
-            let two = q6_vh_vsplat_r(2);
-            let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
-            let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
-            let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
-            let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
+            let two = Q6_Vh_vsplat_R(2);
+            let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two);
+            let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two);
+            let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two);
+            let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two);
 
             // Pack back to u8 with saturation: takes hi and lo halfword vectors,
             // saturates to u8, and interleaves them back to original order
-            let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
+            let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo);
 
             *outp.add(i) = result;
         }
@@ -142,44 +142,44 @@ mod hvx {
         let outp = dst as *mut HvxVector;
 
         let n_chunks = width / VLEN;
-        let mut prev = q6_v_vzero();
+        let mut prev = Q6_V_vzero();
 
         for i in 0..n_chunks {
             let curr = *inp.add(i);
             let next = if i + 1 < n_chunks {
                 *inp.add(i + 1)
             } else {
-                q6_v_vzero()
+                Q6_V_vzero()
             };
 
             // Left neighbor (x-1): shift curr right by 1 byte, filling from prev
-            let left = q6_v_vlalign_vvr(curr, prev, 1);
+            let left = Q6_V_vlalign_VVR(curr, prev, 1);
 
             // Right neighbor (x+1): shift curr left by 1 byte, filling from next
-            let right = q6_v_valign_vvr(next, curr, 1);
+            let right = Q6_V_valign_VVR(next, curr, 1);
 
             // Widen left + right to 16-bit
-            let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right);
+            let left_plus_right: HvxVectorPair = Q6_Wh_vadd_VubVub(left, right);
 
             // Widen center * 2
-            let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr);
+            let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(curr, curr);
 
             // Add: left + 2*center + right
-            let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2);
+            let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(left_plus_right, center_x2);
 
             // Extract high and low vectors
-            let sum_lo = q6_v_lo_w(sum);
-            let sum_hi = q6_v_hi_w(sum);
+            let sum_lo = Q6_V_lo_W(sum);
+            let sum_hi = Q6_V_hi_W(sum);
 
             // Arithmetic right shift by 2 with rounding
-            let two = q6_vh_vsplat_r(2);
-            let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two);
-            let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two);
-            let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two);
-            let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two);
+            let two = Q6_Vh_vsplat_R(2);
+            let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two);
+            let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two);
+            let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two);
+            let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two);
 
             // Pack back to u8 with saturation
-            let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo);
+            let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo);
 
             *outp.add(i) = result;
 

From d13f8876dde5c7b879da4851ba6928224574d944 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Fri, 10 Apr 2026 20:12:46 +0200
Subject: [PATCH 223/326] Do not use `SimdM::new` and remove `simd_m_ty!`

---
 crates/core_arch/src/powerpc/altivec.rs |  24 ++---
 crates/core_arch/src/powerpc/vsx.rs     |  12 +--
 crates/core_arch/src/s390x/vector.rs    |   8 +-
 crates/core_arch/src/simd.rs            | 138 ++++--------------------
 4 files changed, 45 insertions(+), 137 deletions(-)

diff --git a/crates/core_arch/src/powerpc/altivec.rs b/crates/core_arch/src/powerpc/altivec.rs
index f68121ad31..78ec39f91f 100644
--- a/crates/core_arch/src/powerpc/altivec.rs
+++ b/crates/core_arch/src/powerpc/altivec.rs
@@ -4700,10 +4700,10 @@ mod tests {
         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
             #[simd_test(enable = "altivec")]
             fn $name() {
-                let a: s_t_l!($ty) = $ty::new($($a),+).into();
-                let b: s_t_l!($ty) = $ty::new($($b),+).into();
+                let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into();
+                let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into();
 
-                let d = $ty_out::new($($d),+);
+                let d = $ty_out::from_array([$($d),+]);
                 let r = $ty_out::from(unsafe { $fn(a, b) });
                 assert_eq!(d, r);
             }
@@ -4711,8 +4711,8 @@ mod tests {
          { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
             #[simd_test(enable = "altivec")]
             fn $name() {
-                let a: s_t_l!($ty) = $ty::new($($a),+).into();
-                let b: s_t_l!($ty) = $ty::new($($b),+).into();
+                let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into();
+                let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into();
 
                 let r = $ty_out::from(unsafe { $fn(a, b) });
                 assert_eq!($d, r);
@@ -4728,7 +4728,7 @@ mod tests {
 
                 let d = vector_float::from(f32x4::new($($d),+));
                 let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) });
-                let e = m32x4::new(true, true, true, true);
+                let e = m32x4::splat(true);
                 assert_eq!(e, r);
             }
         };
@@ -6212,10 +6212,10 @@ mod tests {
          [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "altivec")]
             fn $name() {
-                let a = $longtype::from($shorttype::new($($a),+));
-                let b = $longtype::from($shorttype::new($($b),+));
-                let c = vector_unsigned_char::from(u8x16::new($($c),+));
-                let d = $shorttype::new($($d),+);
+                let a = $longtype::from($shorttype::from_array([$($a),+]));
+                let b = $longtype::from($shorttype::from_array([$($b),+]));
+                let c = vector_unsigned_char::from(u8x16::from_array([$($c),+]));
+                let d = $shorttype::from_array([$($d),+]);
 
                 let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
                 assert_eq!(d, r);
@@ -6664,7 +6664,7 @@ mod tests {
         let check = |a, b| {
             let r =
                 m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
-            let e = m32x4::new(true, true, true, true);
+            let e = m32x4::splat(true);
             assert_eq!(e, r);
         };
 
@@ -6720,7 +6720,7 @@ mod tests {
             let r =
                 m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
             println!("{:?} {:?}", a, b);
-            let e = m32x4::new(true, true, true, true);
+            let e = m32x4::splat(true);
             assert_eq!(e, r);
         };
 
diff --git a/crates/core_arch/src/powerpc/vsx.rs b/crates/core_arch/src/powerpc/vsx.rs
index 0aac236173..4a7b561a20 100644
--- a/crates/core_arch/src/powerpc/vsx.rs
+++ b/crates/core_arch/src/powerpc/vsx.rs
@@ -238,14 +238,14 @@ mod tests {
         {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "vsx")]
             fn $name() {
-                let a = $longtype::from($shorttype::new($($a),+, $($b),+));
-                let b = $longtype::from($shorttype::new($($c),+, $($d),+));
+                let a = $longtype::from($shorttype::from_array([$($a),+, $($b),+]));
+                let b = $longtype::from($shorttype::from_array([$($c),+, $($d),+]));
 
                 unsafe {
-                    assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b)));
-                    assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b)));
-                    assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b)));
-                    assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b)));
+                    assert_eq!($shorttype::from_array([$($a),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 0>(a, b)));
+                    assert_eq!($shorttype::from_array([$($b),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 1>(a, b)));
+                    assert_eq!($shorttype::from_array([$($a),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 2>(a, b)));
+                    assert_eq!($shorttype::from_array([$($b),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 3>(a, b)));
                 }
             }
         }
diff --git a/crates/core_arch/src/s390x/vector.rs b/crates/core_arch/src/s390x/vector.rs
index 376c912c04..fc5af1b14d 100644
--- a/crates/core_arch/src/s390x/vector.rs
+++ b/crates/core_arch/src/s390x/vector.rs
@@ -6463,10 +6463,10 @@ mod tests {
          [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
             #[simd_test(enable = "vector")]
             fn $name() {
-                let a = $longtype::from($shorttype::new($($a),+));
-                let b = $longtype::from($shorttype::new($($b),+));
-                let c = vector_unsigned_char::from(u8x16::new($($c),+));
-                let d = $shorttype::new($($d),+);
+                let a = $longtype::from($shorttype::from_array([$($a),+]));
+                let b = $longtype::from($shorttype::from_array([$($b),+]));
+                let c = vector_unsigned_char::from(u8x16::from_array([$($c),+]));
+                let d = $shorttype::from_array([$($d),+]);
 
                 let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
                 assert_eq!(d, r);
diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index 313c474792..28716072f0 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -20,6 +20,8 @@ pub(crate) const unsafe fn simd_imin<T: Copy>(a: T, b: T) -> T {
 pub(crate) unsafe trait SimdElement:
     Copy + const PartialEq + crate::fmt::Debug
 {
+    // SAFETY: all bits patterns of types implementing this trait must be valid
+    const ZERO: Self = unsafe { crate::mem::zeroed() };
 }
 
 unsafe impl SimdElement for u8 {}
@@ -42,8 +44,7 @@ pub(crate) struct Simd<T: SimdElement, const N: usize>([T; N]);
 
 impl<T: SimdElement, const N: usize> Simd<T, N> {
     /// A value of this type where all elements are zeroed out.
-    // SAFETY: `T` implements `SimdElement`, so it is zeroable.
-    pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() };
+    pub(crate) const ZERO: Self = Self::splat(T::ZERO);
 
     #[inline(always)]
     pub(crate) const fn from_array(elements: [T; N]) -> Self {
@@ -163,7 +164,6 @@ impl<T: SimdElement, const N: usize> SimdM<T, N> {
     #[inline(always)]
     const fn bool_to_internal(x: bool) -> T {
         // SAFETY: `T` implements `SimdElement`, so all bit patterns are valid.
-        let zeros = const { unsafe { crate::mem::zeroed::<T>() } };
         let ones = const {
             // Ideally, this would be `transmute([0xFFu8; size_of::<T>()])`, but
             // `size_of::<T>()` is not allowed to use a generic parameter there.
@@ -175,13 +175,24 @@ impl<T: SimdElement, const N: usize> SimdM<T, N> {
             }
             unsafe { r.assume_init() }
         };
-        [zeros, ones][x as usize]
+        [T::ZERO, ones][x as usize]
+    }
+
+    #[inline]
+    pub(crate) const fn from_array(elements: [bool; N]) -> Self {
+        let mut internal = [T::ZERO; N];
+        let mut i = 0;
+        while i < N {
+            internal[i] = Self::bool_to_internal(elements[i]);
+            i += 1;
+        }
+        Self(internal)
     }
 
     #[inline]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
     pub(crate) const fn splat(value: bool) -> Self {
-        unsafe { crate::intrinsics::simd::simd_splat(value) }
+        unsafe { crate::intrinsics::simd::simd_splat(Self::bool_to_internal(value)) }
     }
 
     #[inline]
@@ -218,19 +229,6 @@ impl<T: SimdElement, const N: usize> crate::fmt::Debug for SimdM<T, N> {
     }
 }
 
-macro_rules! simd_m_ty {
-    ($id:ident [$elem_type:ident ; $len:literal]: $($param_name:ident),*) => {
-        pub(crate) type $id  = SimdM<$elem_type, $len>;
-
-        impl $id {
-            #[inline(always)]
-            pub(crate) const fn new($($param_name: bool),*) -> Self {
-                Self([$(Self::bool_to_internal($param_name)),*])
-            }
-        }
-    }
-}
-
 // 16-bit wide types:
 
 simd_ty!(u8x2[u8;2]: x0, x1);
@@ -363,38 +361,10 @@ simd_ty!(
 simd_ty!(f32x4[f32;4]: x0, x1, x2, x3);
 simd_ty!(f64x2[f64;2]: x0, x1);
 
-simd_m_ty!(
-    m8x16[i8;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_m_ty!(
-    m16x8[i16;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_m_ty!(m32x4[i32;4]: x0, x1, x2, x3);
-simd_m_ty!(m64x2[i64;2]: x0, x1);
+pub(crate) type m8x16 = SimdM<i8, 16>;
+pub(crate) type m16x8 = SimdM<i16, 8>;
+pub(crate) type m32x4 = SimdM<i32, 4>;
+pub(crate) type m64x2 = SimdM<i64, 2>;
 
 // 256-bit wide types:
 
@@ -564,71 +534,9 @@ simd_ty!(
 );
 simd_ty!(f64x4[f64;4]: x0, x1, x2, x3);
 
-simd_m_ty!(
-    m8x32[i8;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
-simd_m_ty!(
-    m16x16[i16;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_m_ty!(
-    m32x8[i32;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
+pub(crate) type m8x32 = SimdM<i8, 32>;
+pub(crate) type m16x16 = SimdM<i16, 16>;
+pub(crate) type m32x8 = SimdM<i32, 8>;
 
 // 512-bit wide types:
 

From 784a3bdf898382b19c3f03b997b32326bbb8477c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Fri, 10 Apr 2026 20:42:25 +0200
Subject: [PATCH 224/326] Do not use a macro to define `Simd::new`

---
 crates/core_arch/src/simd.rs        | 914 +++++-----------------------
 crates/core_arch/src/x86/avx512f.rs |   4 +-
 2 files changed, 153 insertions(+), 765 deletions(-)

diff --git a/crates/core_arch/src/simd.rs b/crates/core_arch/src/simd.rs
index 28716072f0..2c6829b465 100644
--- a/crates/core_arch/src/simd.rs
+++ b/crates/core_arch/src/simd.rs
@@ -101,6 +101,103 @@ impl<T: SimdElement, const N: usize> crate::fmt::Debug for Simd<T, N> {
     }
 }
 
+impl<T: SimdElement> Simd<T, 1> {
+    #[inline]
+    pub(crate) const fn new(x0: T) -> Self {
+        Self([x0])
+    }
+}
+
+impl<T: SimdElement> Simd<T, 2> {
+    #[inline]
+    pub(crate) const fn new(x0: T, x1: T) -> Self {
+        Self([x0, x1])
+    }
+}
+
+impl<T: SimdElement> Simd<T, 4> {
+    #[inline]
+    pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T) -> Self {
+        Self([x0, x1, x2, x3])
+    }
+}
+
+impl<T: SimdElement> Simd<T, 8> {
+    #[inline]
+    pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T, x4: T, x5: T, x6: T, x7: T) -> Self {
+        Self([x0, x1, x2, x3, x4, x5, x6, x7])
+    }
+}
+
+impl<T: SimdElement> Simd<T, 16> {
+    #[inline]
+    pub(crate) const fn new(
+        x0: T,
+        x1: T,
+        x2: T,
+        x3: T,
+        x4: T,
+        x5: T,
+        x6: T,
+        x7: T,
+        x8: T,
+        x9: T,
+        x10: T,
+        x11: T,
+        x12: T,
+        x13: T,
+        x14: T,
+        x15: T,
+    ) -> Self {
+        Self([
+            x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        ])
+    }
+}
+
+impl<T: SimdElement> Simd<T, 32> {
+    #[inline]
+    pub(crate) const fn new(
+        x0: T,
+        x1: T,
+        x2: T,
+        x3: T,
+        x4: T,
+        x5: T,
+        x6: T,
+        x7: T,
+        x8: T,
+        x9: T,
+        x10: T,
+        x11: T,
+        x12: T,
+        x13: T,
+        x14: T,
+        x15: T,
+        x16: T,
+        x17: T,
+        x18: T,
+        x19: T,
+        x20: T,
+        x21: T,
+        x22: T,
+        x23: T,
+        x24: T,
+        x25: T,
+        x26: T,
+        x27: T,
+        x28: T,
+        x29: T,
+        x30: T,
+        x31: T,
+    ) -> Self {
+        Self([
+            x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18,
+            x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31,
+        ])
+    }
+}
+
 impl<const N: usize> Simd<f16, N> {
     #[inline]
     pub(crate) const fn to_bits(self) -> Simd<u16, N> {
@@ -143,19 +240,6 @@ impl<const N: usize> Simd<f64, N> {
     }
 }
 
-macro_rules! simd_ty {
-    ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => {
-        pub(crate) type $id = Simd<$elem_type, $len>;
-
-        impl $id {
-            #[inline(always)]
-            pub(crate) const fn new($($param_name: $elem_type),*) -> Self {
-                Self([$($param_name),*])
-            }
-        }
-    }
-}
-
 #[repr(simd)]
 #[derive(Copy)]
 pub(crate) struct SimdM<T: SimdElement, const N: usize>([T; N]);
@@ -231,135 +315,48 @@ impl<T: SimdElement, const N: usize> crate::fmt::Debug for SimdM<T, N> {
 
 // 16-bit wide types:
 
-simd_ty!(u8x2[u8;2]: x0, x1);
-simd_ty!(i8x2[i8;2]: x0, x1);
+pub(crate) type u8x2 = Simd<u8, 2>;
+pub(crate) type i8x2 = Simd<i8, 2>;
 
 // 32-bit wide types:
 
-simd_ty!(u8x4[u8;4]: x0, x1, x2, x3);
-simd_ty!(u16x2[u16;2]: x0, x1);
+pub(crate) type u8x4 = Simd<u8, 4>;
+pub(crate) type u16x2 = Simd<u16, 2>;
 
-simd_ty!(i8x4[i8;4]: x0, x1, x2, x3);
-simd_ty!(i16x2[i16;2]: x0, x1);
+pub(crate) type i8x4 = Simd<i8, 4>;
+pub(crate) type i16x2 = Simd<i16, 2>;
 
 // 64-bit wide types:
 
-simd_ty!(
-    u8x8[u8;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(u16x4[u16;4]: x0, x1, x2, x3);
-simd_ty!(u32x2[u32;2]: x0, x1);
-simd_ty!(u64x1[u64;1]: x1);
+pub(crate) type u8x8 = Simd<u8, 8>;
+pub(crate) type u16x4 = Simd<u16, 4>;
+pub(crate) type u32x2 = Simd<u32, 2>;
+pub(crate) type u64x1 = Simd<u64, 1>;
 
-simd_ty!(
-    i8x8[i8;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(i16x4[i16;4]: x0, x1, x2, x3);
-simd_ty!(i32x2[i32;2]: x0, x1);
-simd_ty!(i64x1[i64;1]: x1);
+pub(crate) type i8x8 = Simd<i8, 8>;
+pub(crate) type i16x4 = Simd<i16, 4>;
+pub(crate) type i32x2 = Simd<i32, 2>;
+pub(crate) type i64x1 = Simd<i64, 1>;
 
-simd_ty!(f32x2[f32;2]: x0, x1);
-simd_ty!(f64x1[f64;1]: x1);
+pub(crate) type f16x4 = Simd<f16, 4>;
+pub(crate) type f32x2 = Simd<f32, 2>;
+pub(crate) type f64x1 = Simd<f64, 1>;
 
 // 128-bit wide types:
 
-simd_ty!(
-    u8x16[u8;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_ty!(
-    u16x8[u16;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(u32x4[u32;4]: x0, x1, x2, x3);
-simd_ty!(u64x2[u64;2]: x0, x1);
-
-simd_ty!(
-    i8x16[i8;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_ty!(
-    i16x8[i16;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(i32x4[i32;4]: x0, x1, x2, x3);
-simd_ty!(i64x2[i64;2]: x0, x1);
+pub(crate) type u8x16 = Simd<u8, 16>;
+pub(crate) type u16x8 = Simd<u16, 8>;
+pub(crate) type u32x4 = Simd<u32, 4>;
+pub(crate) type u64x2 = Simd<u64, 2>;
 
-simd_ty!(f16x4[f16;4]: x0, x1, x2, x3);
+pub(crate) type i8x16 = Simd<i8, 16>;
+pub(crate) type i16x8 = Simd<i16, 8>;
+pub(crate) type i32x4 = Simd<i32, 4>;
+pub(crate) type i64x2 = Simd<i64, 2>;
 
-simd_ty!(
-    f16x8[f16;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(f32x4[f32;4]: x0, x1, x2, x3);
-simd_ty!(f64x2[f64;2]: x0, x1);
+pub(crate) type f16x8 = Simd<f16, 8>;
+pub(crate) type f32x4 = Simd<f32, 4>;
+pub(crate) type f64x2 = Simd<f64, 2>;
 
 pub(crate) type m8x16 = SimdM<i8, 16>;
 pub(crate) type m16x8 = SimdM<i16, 8>;
@@ -368,171 +365,19 @@ pub(crate) type m64x2 = SimdM<i64, 2>;
 
 // 256-bit wide types:
 
-simd_ty!(
-    u8x32[u8;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
-simd_ty!(
-    u16x16[u16;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_ty!(
-    u32x8[u32;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(u64x4[u64;4]: x0, x1, x2, x3);
+pub(crate) type u8x32 = Simd<u8, 32>;
+pub(crate) type u16x16 = Simd<u16, 16>;
+pub(crate) type u32x8 = Simd<u32, 8>;
+pub(crate) type u64x4 = Simd<u64, 4>;
 
-simd_ty!(
-    i8x32[i8;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
-simd_ty!(
-    i16x16[i16;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_ty!(
-    i32x8[i32;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(i64x4[i64;4]: x0, x1, x2, x3);
+pub(crate) type i8x32 = Simd<i8, 32>;
+pub(crate) type i16x16 = Simd<i16, 16>;
+pub(crate) type i32x8 = Simd<i32, 8>;
+pub(crate) type i64x4 = Simd<i64, 4>;
 
-simd_ty!(
-    f16x16[f16;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-simd_ty!(
-    f32x8[f32;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-simd_ty!(f64x4[f64;4]: x0, x1, x2, x3);
+pub(crate) type f16x16 = Simd<f16, 16>;
+pub(crate) type f32x8 = Simd<f32, 8>;
+pub(crate) type f64x4 = Simd<f64, 4>;
 
 pub(crate) type m8x32 = SimdM<i8, 32>;
 pub(crate) type m16x16 = SimdM<i16, 16>;
@@ -540,483 +385,26 @@ pub(crate) type m32x8 = SimdM<i32, 8>;
 
 // 512-bit wide types:
 
-simd_ty!(
-    i8x64[i8;64]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31,
-    x32,
-    x33,
-    x34,
-    x35,
-    x36,
-    x37,
-    x38,
-    x39,
-    x40,
-    x41,
-    x42,
-    x43,
-    x44,
-    x45,
-    x46,
-    x47,
-    x48,
-    x49,
-    x50,
-    x51,
-    x52,
-    x53,
-    x54,
-    x55,
-    x56,
-    x57,
-    x58,
-    x59,
-    x60,
-    x61,
-    x62,
-    x63
-);
-
-simd_ty!(
-    u8x64[u8;64]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31,
-    x32,
-    x33,
-    x34,
-    x35,
-    x36,
-    x37,
-    x38,
-    x39,
-    x40,
-    x41,
-    x42,
-    x43,
-    x44,
-    x45,
-    x46,
-    x47,
-    x48,
-    x49,
-    x50,
-    x51,
-    x52,
-    x53,
-    x54,
-    x55,
-    x56,
-    x57,
-    x58,
-    x59,
-    x60,
-    x61,
-    x62,
-    x63
-);
-
-simd_ty!(
-    i16x32[i16;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
-
-simd_ty!(
-    u16x32[u16;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
+pub(crate) type u8x64 = Simd<u8, 64>;
+pub(crate) type u16x32 = Simd<u16, 32>;
+pub(crate) type u32x16 = Simd<u32, 16>;
+pub(crate) type u64x8 = Simd<u64, 8>;
 
-simd_ty!(
-    i32x16[i32;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
+pub(crate) type i8x64 = Simd<i8, 64>;
+pub(crate) type i16x32 = Simd<i16, 32>;
+pub(crate) type i32x16 = Simd<i32, 16>;
+pub(crate) type i64x8 = Simd<i64, 8>;
 
-simd_ty!(
-    u32x16[u32;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
+pub(crate) type f16x32 = Simd<f16, 32>;
+pub(crate) type f32x16 = Simd<f32, 16>;
+pub(crate) type f64x8 = Simd<f64, 8>;
 
-simd_ty!(
-    f16x32[f16;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
-simd_ty!(
-    f32x16[f32;16]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15
-);
-
-simd_ty!(
-    i64x8[i64;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
-
-simd_ty!(
-    u64x8[u64;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
+// 1024-bit wide types:
 
-simd_ty!(
-    f64x8[f64;8]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7
-);
+pub(crate) type u16x64 = Simd<u16, 64>;
+pub(crate) type u32x32 = Simd<u32, 32>;
 
-// 1024-bit wide types:
-simd_ty!(
-    u16x64[u16;64]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31,
-    x32,
-    x33,
-    x34,
-    x35,
-    x36,
-    x37,
-    x38,
-    x39,
-    x40,
-    x41,
-    x42,
-    x43,
-    x44,
-    x45,
-    x46,
-    x47,
-    x48,
-    x49,
-    x50,
-    x51,
-    x52,
-    x53,
-    x54,
-    x55,
-    x56,
-    x57,
-    x58,
-    x59,
-    x60,
-    x61,
-    x62,
-    x63
-);
-simd_ty!(
-    i32x32[i32;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
-simd_ty!(
-    u32x32[u32;32]:
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    x8,
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    x16,
-    x17,
-    x18,
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    x29,
-    x30,
-    x31
-);
+pub(crate) type i32x32 = Simd<i32, 32>;
 
 /// Used to continue `Debug`ging SIMD types as `MySimd(1, 2, 3, 4)`, as they
 /// were before moving to array-based simd.
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 3730496e1e..0c725402a9 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -16807,12 +16807,12 @@ pub const fn _mm512_set_epi8(
     e0: i8,
 ) -> __m512i {
     unsafe {
-        let r = i8x64::new(
+        let r = i8x64::from_array([
             e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18,
             e19, e20, e21, e22, e23, e24, e25, e26, e27, e28, e29, e30, e31, e32, e33, e34, e35,
             e36, e37, e38, e39, e40, e41, e42, e43, e44, e45, e46, e47, e48, e49, e50, e51, e52,
             e53, e54, e55, e56, e57, e58, e59, e60, e61, e62, e63,
-        );
+        ]);
         transmute(r)
     }
 }

From ab813384a3eb6e1bb27244c486af909532968811 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Thu, 9 Apr 2026 20:02:25 +0800
Subject: [PATCH 225/326] loongarch: Avoid constant folding in tests to ensure
 SIMD coverage

Use `black_box` on SIMD intrinsic inputs to prevent the compiler from
constant folding SIMD operations, ensuring the corresponding SIMD
instructions are actually emitted and covered by tests.
---
 .../core_arch/src/loongarch64/lasx/tests.rs   | 4181 ++++++++++++++---
 crates/core_arch/src/loongarch64/lsx/tests.rs | 3848 ++++++++++++---
 crates/stdarch-gen-loongarch/src/main.rs      |   29 +-
 3 files changed, 6536 insertions(+), 1522 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/tests.rs b/crates/core_arch/src/loongarch64/lasx/tests.rs
index 319ce7cf98..bd22d25771 100644
--- a/crates/core_arch/src/loongarch64/lasx/tests.rs
+++ b/crates/core_arch/src/loongarch64/lasx/tests.rs
@@ -5,6 +5,7 @@ use crate::{
     core_arch::{loongarch64::*, simd::*},
     mem::transmute,
 };
+use std::hint::black_box;
 use stdarch_test::simd_test;
 
 #[simd_test(enable = "lasx")]
@@ -24,7 +25,13 @@ unsafe fn test_lasx_xvsll_b() {
         2882304449461665880,
     );
 
-    assert_eq!(r, transmute(lasx_xvsll_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsll_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -44,7 +51,13 @@ unsafe fn test_lasx_xvsll_h() {
         7061899947028838480,
     );
 
-    assert_eq!(r, transmute(lasx_xvsll_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsll_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -76,7 +89,13 @@ unsafe fn test_lasx_xvsll_w() {
         3598939055443673088,
     );
 
-    assert_eq!(r, transmute(lasx_xvsll_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsll_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -100,7 +119,13 @@ unsafe fn test_lasx_xvsll_d() {
         -289787284616642560,
     );
 
-    assert_eq!(r, transmute(lasx_xvsll_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsll_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -116,7 +141,7 @@ unsafe fn test_lasx_xvslli_b() {
         5775955139904200724,
     );
 
-    assert_eq!(r, transmute(lasx_xvslli_b::<2>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslli_b::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -132,7 +157,7 @@ unsafe fn test_lasx_xvslli_h() {
         -9223160928474759168,
     );
 
-    assert_eq!(r, transmute(lasx_xvslli_h::<14>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslli_h::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -154,7 +179,7 @@ unsafe fn test_lasx_xvslli_w() {
         -1585267064908546048,
     );
 
-    assert_eq!(r, transmute(lasx_xvslli_w::<24>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslli_w::<24>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -172,7 +197,7 @@ unsafe fn test_lasx_xvslli_d() {
         -2305843009213693952,
     );
 
-    assert_eq!(r, transmute(lasx_xvslli_d::<61>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslli_d::<61>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -192,7 +217,13 @@ unsafe fn test_lasx_xvsra_b() {
         -505532365968836077,
     );
 
-    assert_eq!(r, transmute(lasx_xvsra_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsra_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -212,7 +243,13 @@ unsafe fn test_lasx_xvsra_h() {
         8725659825471543,
     );
 
-    assert_eq!(r, transmute(lasx_xvsra_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsra_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -244,7 +281,13 @@ unsafe fn test_lasx_xvsra_w() {
         -36696200575105,
     );
 
-    assert_eq!(r, transmute(lasx_xvsra_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsra_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -263,7 +306,13 @@ unsafe fn test_lasx_xvsra_d() {
     );
     let r = i64x4::new(1, -129761412875, -1, 8464978396185);
 
-    assert_eq!(r, transmute(lasx_xvsra_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsra_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -279,7 +328,7 @@ unsafe fn test_lasx_xvsrai_b() {
         -218421283493247239,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrai_b::<4>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrai_b::<4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -290,7 +339,7 @@ unsafe fn test_lasx_xvsrai_h() {
     );
     let r = i64x4::new(-281474976710658, 8589803520, -4295098367, 562941363552256);
 
-    assert_eq!(r, transmute(lasx_xvsrai_h::<14>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrai_h::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -307,7 +356,7 @@ unsafe fn test_lasx_xvsrai_w() {
     );
     let r = i64x4::new(68719476730, -16, 17179869169, -25769803773);
 
-    assert_eq!(r, transmute(lasx_xvsrai_w::<27>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrai_w::<27>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -320,7 +369,7 @@ unsafe fn test_lasx_xvsrai_d() {
     );
     let r = i64x4::new(-2, 2, -6, -8);
 
-    assert_eq!(r, transmute(lasx_xvsrai_d::<60>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrai_d::<60>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -340,7 +389,13 @@ unsafe fn test_lasx_xvsrar_b() {
         302862676776648704,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrar_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrar_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -360,7 +415,13 @@ unsafe fn test_lasx_xvsrar_h() {
         -2251658079567874,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrar_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrar_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -392,7 +453,13 @@ unsafe fn test_lasx_xvsrar_w() {
         -1668156707832192,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrar_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrar_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -411,7 +478,13 @@ unsafe fn test_lasx_xvsrar_d() {
     );
     let r = i64x4::new(19951225, 505, -1907248091287715676, 362);
 
-    assert_eq!(r, transmute(lasx_xvsrar_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrar_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -427,7 +500,7 @@ unsafe fn test_lasx_xvsrari_b() {
         790117907428411639,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrari_b::<3>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrari_b::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -443,7 +516,7 @@ unsafe fn test_lasx_xvsrari_h() {
         -24488623625338826,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrari_h::<8>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrari_h::<8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -460,7 +533,7 @@ unsafe fn test_lasx_xvsrari_w() {
     );
     let r = i64x4::new(-1, 4294967294, -2, -1);
 
-    assert_eq!(r, transmute(lasx_xvsrari_w::<29>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrari_w::<29>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -473,7 +546,7 @@ unsafe fn test_lasx_xvsrari_d() {
     );
     let r = i64x4::new(-3228, 4782, -4328, -2120);
 
-    assert_eq!(r, transmute(lasx_xvsrari_d::<50>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrari_d::<50>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -493,7 +566,13 @@ unsafe fn test_lasx_xvsrl_b() {
         3996105849293766692,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrl_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrl_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -513,7 +592,13 @@ unsafe fn test_lasx_xvsrl_h() {
         12385032119328029,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrl_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrl_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -540,7 +625,13 @@ unsafe fn test_lasx_xvsrl_w() {
     );
     let r = i64x4::new(3152506611213, 910538585043, 150899, 25769803779);
 
-    assert_eq!(r, transmute(lasx_xvsrl_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrl_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -559,7 +650,13 @@ unsafe fn test_lasx_xvsrl_d() {
     );
     let r = i64x4::new(22, 8215, 774027732, 338970735904462);
 
-    assert_eq!(r, transmute(lasx_xvsrl_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrl_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -575,7 +672,7 @@ unsafe fn test_lasx_xvsrli_b() {
         3694315145030590091,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrli_b::<0>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrli_b::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -586,7 +683,7 @@ unsafe fn test_lasx_xvsrli_h() {
     );
     let r = i64x4::new(7036883009470493, 73014771737, 38655688722, 3096241924866048);
 
-    assert_eq!(r, transmute(lasx_xvsrli_h::<11>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrli_h::<11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -608,7 +705,7 @@ unsafe fn test_lasx_xvsrli_w() {
         11669426172998,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrli_w::<17>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrli_w::<17>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -621,7 +718,7 @@ unsafe fn test_lasx_xvsrli_d() {
     );
     let r = i64x4::new(16617962184, 1898365962, 5054169972, 27969530398);
 
-    assert_eq!(r, transmute(lasx_xvsrli_d::<29>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrli_d::<29>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -641,7 +738,13 @@ unsafe fn test_lasx_xvsrlr_b() {
         150872911094481483,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrlr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -661,7 +764,13 @@ unsafe fn test_lasx_xvsrlr_h() {
         565118914199555,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrlr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -693,7 +802,13 @@ unsafe fn test_lasx_xvsrlr_w() {
         7085854838990307330,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrlr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -712,7 +827,13 @@ unsafe fn test_lasx_xvsrlr_d() {
     );
     let r = i64x4::new(1801, 481878, 1923591164085, 6280495597);
 
-    assert_eq!(r, transmute(lasx_xvsrlr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -728,7 +849,7 @@ unsafe fn test_lasx_xvsrlri_b() {
         2893318883870770962,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -744,7 +865,7 @@ unsafe fn test_lasx_xvsrlri_h() {
         32932658182619167,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -761,7 +882,7 @@ unsafe fn test_lasx_xvsrlri_w() {
     );
     let r = i64x4::new(8589934592, 8589934594, 4294967296, 8589934593);
 
-    assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -779,7 +900,7 @@ unsafe fn test_lasx_xvsrlri_d() {
         197693428197319479,
     );
 
-    assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -799,7 +920,13 @@ unsafe fn test_lasx_xvbitclr_b() {
         2031321085346416701,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitclr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -819,7 +946,13 @@ unsafe fn test_lasx_xvbitclr_h() {
         -8417099780160452424,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitclr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -839,7 +972,13 @@ unsafe fn test_lasx_xvbitclr_w() {
         436221668492520778,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitclr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -863,7 +1002,13 @@ unsafe fn test_lasx_xvbitclr_d() {
         3668272799860684125,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitclr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -879,7 +1024,7 @@ unsafe fn test_lasx_xvbitclri_b() {
         3065582154070828979,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -895,7 +1040,7 @@ unsafe fn test_lasx_xvbitclri_h() {
         7727381349517352021,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -911,7 +1056,10 @@ unsafe fn test_lasx_xvbitclri_w() {
         -5611395396043530126,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclri_w::<30>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitclri_w::<30>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -929,7 +1077,10 @@ unsafe fn test_lasx_xvbitclri_d() {
         -63139220754952887,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitclri_d::<46>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitclri_d::<46>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -949,7 +1100,13 @@ unsafe fn test_lasx_xvbitset_b() {
         -7702318388235109826,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitset_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitset_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -969,7 +1126,13 @@ unsafe fn test_lasx_xvbitset_h() {
         1674099372676878223,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitset_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitset_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -989,7 +1152,13 @@ unsafe fn test_lasx_xvbitset_w() {
         -4953617511697867204,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitset_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitset_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1013,7 +1182,13 @@ unsafe fn test_lasx_xvbitset_d() {
         8641001130845153939,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitset_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitset_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1029,7 +1204,7 @@ unsafe fn test_lasx_xvbitseti_b() {
         -3539275497407339017,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1045,7 +1220,10 @@ unsafe fn test_lasx_xvbitseti_h() {
         -1050847327214912781,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitseti_h::<13>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitseti_h::<13>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1061,7 +1239,10 @@ unsafe fn test_lasx_xvbitseti_w() {
         -1933536090599238411,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitseti_w::<29>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitseti_w::<29>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1079,7 +1260,10 @@ unsafe fn test_lasx_xvbitseti_d() {
         7640056937583456779,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitseti_d::<17>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitseti_d::<17>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1099,7 +1283,13 @@ unsafe fn test_lasx_xvbitrev_b() {
         8353346322052154032,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrev_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrev_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1119,7 +1309,13 @@ unsafe fn test_lasx_xvbitrev_h() {
         1161012008856358603,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrev_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrev_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1139,7 +1335,13 @@ unsafe fn test_lasx_xvbitrev_w() {
         2239715596821320928,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrev_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrev_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1163,7 +1365,13 @@ unsafe fn test_lasx_xvbitrev_d() {
         -7824300689033275105,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrev_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrev_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1179,7 +1387,7 @@ unsafe fn test_lasx_xvbitrevi_b() {
         -468434338938596352,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1195,7 +1403,10 @@ unsafe fn test_lasx_xvbitrevi_h() {
         4180481285432101679,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrevi_h::<11>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrevi_h::<11>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1211,7 +1422,10 @@ unsafe fn test_lasx_xvbitrevi_w() {
         -7201777846932221130,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrevi_w::<30>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrevi_w::<30>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1229,7 +1443,10 @@ unsafe fn test_lasx_xvbitrevi_d() {
         -1340750007927221124,
     );
 
-    assert_eq!(r, transmute(lasx_xvbitrevi_d::<25>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvbitrevi_d::<25>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1249,7 +1466,13 @@ unsafe fn test_lasx_xvadd_b() {
         39834845715162790,
     );
 
-    assert_eq!(r, transmute(lasx_xvadd_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1269,7 +1492,13 @@ unsafe fn test_lasx_xvadd_h() {
         3485514723534807729,
     );
 
-    assert_eq!(r, transmute(lasx_xvadd_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1301,7 +1530,13 @@ unsafe fn test_lasx_xvadd_w() {
         449408456544649458,
     );
 
-    assert_eq!(r, transmute(lasx_xvadd_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1325,7 +1560,13 @@ unsafe fn test_lasx_xvadd_d() {
         -3333036084724254699,
     );
 
-    assert_eq!(r, transmute(lasx_xvadd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1341,7 +1582,7 @@ unsafe fn test_lasx_xvaddi_bu() {
         1765491911008659808,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1357,7 +1598,7 @@ unsafe fn test_lasx_xvaddi_hu() {
         4257614802810591100,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1379,7 +1620,7 @@ unsafe fn test_lasx_xvaddi_wu() {
         8831113348648816385,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1397,7 +1638,7 @@ unsafe fn test_lasx_xvaddi_du() {
         -4546559236496052074,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddi_du::<24>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvaddi_du::<24>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1417,7 +1658,13 @@ unsafe fn test_lasx_xvsub_b() {
         -7947080804470620196,
     );
 
-    assert_eq!(r, transmute(lasx_xvsub_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsub_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1437,7 +1684,13 @@ unsafe fn test_lasx_xvsub_h() {
         -2694318201466204009,
     );
 
-    assert_eq!(r, transmute(lasx_xvsub_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsub_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1469,7 +1722,13 @@ unsafe fn test_lasx_xvsub_w() {
         -4928352995773315889,
     );
 
-    assert_eq!(r, transmute(lasx_xvsub_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsub_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1493,7 +1752,13 @@ unsafe fn test_lasx_xvsub_d() {
         -1297126209654251318,
     );
 
-    assert_eq!(r, transmute(lasx_xvsub_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1509,7 +1774,7 @@ unsafe fn test_lasx_xvsubi_bu() {
         6185872108420092159,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1525,7 +1790,7 @@ unsafe fn test_lasx_xvsubi_hu() {
         1522443898558080492,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1547,7 +1812,7 @@ unsafe fn test_lasx_xvsubi_wu() {
         1285045436848317605,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1565,7 +1830,7 @@ unsafe fn test_lasx_xvsubi_du() {
         4145748346670499010,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubi_du::<12>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsubi_du::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1585,7 +1850,13 @@ unsafe fn test_lasx_xvmax_b() {
         8535488153625188193,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1605,7 +1876,13 @@ unsafe fn test_lasx_xvmax_h() {
         -4332902052436023459,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1637,7 +1914,13 @@ unsafe fn test_lasx_xvmax_w() {
         6702174376295843649,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1661,7 +1944,13 @@ unsafe fn test_lasx_xvmax_d() {
         -880822478913123851,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1677,7 +1966,7 @@ unsafe fn test_lasx_xvmaxi_b() {
         5914634738497113077,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1693,7 +1982,7 @@ unsafe fn test_lasx_xvmaxi_h() {
         4406209242478280693,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1715,7 +2004,7 @@ unsafe fn test_lasx_xvmaxi_w() {
         22981864337,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1733,7 +2022,7 @@ unsafe fn test_lasx_xvmaxi_d() {
         2429249725865673045,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1753,7 +2042,13 @@ unsafe fn test_lasx_xvmax_bu() {
         4233495576175936231,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1773,7 +2068,13 @@ unsafe fn test_lasx_xvmax_hu() {
         -1573457187787184228,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1793,7 +2094,13 @@ unsafe fn test_lasx_xvmax_wu() {
         -7315994376096540525,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1817,7 +2124,13 @@ unsafe fn test_lasx_xvmax_du() {
         5141420152487342561,
     );
 
-    assert_eq!(r, transmute(lasx_xvmax_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmax_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1833,7 +2146,7 @@ unsafe fn test_lasx_xvmaxi_bu() {
         -8478920119441971628,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1849,7 +2162,7 @@ unsafe fn test_lasx_xvmaxi_hu() {
         2580949584734723198,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1865,7 +2178,7 @@ unsafe fn test_lasx_xvmaxi_wu() {
         6328395255824707620,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1883,7 +2196,7 @@ unsafe fn test_lasx_xvmaxi_du() {
         3280369825537805033,
     );
 
-    assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -1903,7 +2216,13 @@ unsafe fn test_lasx_xvmin_b() {
         -433018640497265418,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1923,7 +2242,13 @@ unsafe fn test_lasx_xvmin_h() {
         -1753422264687927210,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1949,7 +2274,13 @@ unsafe fn test_lasx_xvmin_w() {
         -710046880263550629,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1973,7 +2304,13 @@ unsafe fn test_lasx_xvmin_d() {
         -3792381296290037631,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -1989,7 +2326,7 @@ unsafe fn test_lasx_xvmini_b() {
         -1088282380739546975,
     );
 
-    assert_eq!(r, transmute(lasx_xvmini_b::<-16>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_b::<-16>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2005,7 +2342,7 @@ unsafe fn test_lasx_xvmini_h() {
         2439077560844296,
     );
 
-    assert_eq!(r, transmute(lasx_xvmini_h::<8>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_h::<8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2027,7 +2364,7 @@ unsafe fn test_lasx_xvmini_w() {
         -3162971646443594334,
     );
 
-    assert_eq!(r, transmute(lasx_xvmini_w::<-16>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_w::<-16>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2040,7 +2377,7 @@ unsafe fn test_lasx_xvmini_d() {
     );
     let r = i64x4::new(-8, -8, -8, -8);
 
-    assert_eq!(r, transmute(lasx_xvmini_d::<-8>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_d::<-8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2060,7 +2397,13 @@ unsafe fn test_lasx_xvmin_bu() {
         481055128827070653,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2080,7 +2423,13 @@ unsafe fn test_lasx_xvmin_hu() {
         4690886800975071114,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2100,7 +2449,13 @@ unsafe fn test_lasx_xvmin_wu() {
         841320412252129092,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2124,7 +2479,13 @@ unsafe fn test_lasx_xvmin_du() {
         168959420679376173,
     );
 
-    assert_eq!(r, transmute(lasx_xvmin_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmin_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2140,7 +2501,7 @@ unsafe fn test_lasx_xvmini_bu() {
         1803156197610166553,
     );
 
-    assert_eq!(r, transmute(lasx_xvmini_bu::<25>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_bu::<25>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2156,7 +2517,7 @@ unsafe fn test_lasx_xvmini_hu() {
         7881419608817692,
     );
 
-    assert_eq!(r, transmute(lasx_xvmini_hu::<28>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_hu::<28>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2167,7 +2528,7 @@ unsafe fn test_lasx_xvmini_wu() {
     );
     let r = i64x4::new(94489280534, 94489280534, 94489280534, 94489280534);
 
-    assert_eq!(r, transmute(lasx_xvmini_wu::<22>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_wu::<22>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2180,7 +2541,7 @@ unsafe fn test_lasx_xvmini_du() {
     );
     let r = i64x4::new(18, 18, 18, 18);
 
-    assert_eq!(r, transmute(lasx_xvmini_du::<18>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmini_du::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2195,7 +2556,13 @@ unsafe fn test_lasx_xvseq_b() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseq_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvseq_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2210,7 +2577,13 @@ unsafe fn test_lasx_xvseq_h() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseq_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvseq_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2237,7 +2610,13 @@ unsafe fn test_lasx_xvseq_w() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseq_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvseq_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2256,7 +2635,13 @@ unsafe fn test_lasx_xvseq_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvseq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2267,7 +2652,7 @@ unsafe fn test_lasx_xvseqi_b() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2278,7 +2663,7 @@ unsafe fn test_lasx_xvseqi_h() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2295,7 +2680,7 @@ unsafe fn test_lasx_xvseqi_w() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2308,7 +2693,7 @@ unsafe fn test_lasx_xvseqi_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2328,7 +2713,13 @@ unsafe fn test_lasx_xvslt_b() {
         71776119077994495,
     );
 
-    assert_eq!(r, transmute(lasx_xvslt_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2348,7 +2739,13 @@ unsafe fn test_lasx_xvslt_h() {
         -281470681743361,
     );
 
-    assert_eq!(r, transmute(lasx_xvslt_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2375,7 +2772,13 @@ unsafe fn test_lasx_xvslt_w() {
     );
     let r = i64x4::new(4294967295, 0, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvslt_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2394,7 +2797,13 @@ unsafe fn test_lasx_xvslt_d() {
     );
     let r = i64x4::new(0, 0, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvslt_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2410,7 +2819,7 @@ unsafe fn test_lasx_xvslti_b() {
         71777218556067840,
     );
 
-    assert_eq!(r, transmute(lasx_xvslti_b::<-16>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_b::<-16>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2421,7 +2830,7 @@ unsafe fn test_lasx_xvslti_h() {
     );
     let r = i64x4::new(4294967295, -1, -281470681743361, 65535);
 
-    assert_eq!(r, transmute(lasx_xvslti_h::<-4>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_h::<-4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2438,7 +2847,7 @@ unsafe fn test_lasx_xvslti_w() {
     );
     let r = i64x4::new(-1, 0, -4294967296, -1);
 
-    assert_eq!(r, transmute(lasx_xvslti_w::<-4>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_w::<-4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2451,7 +2860,7 @@ unsafe fn test_lasx_xvslti_d() {
     );
     let r = i64x4::new(-1, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslti_d::<1>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_d::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2466,7 +2875,13 @@ unsafe fn test_lasx_xvslt_bu() {
     );
     let r = i64x4::new(-1095216660481, 280375465083135, -1099494915841, 16711680);
 
-    assert_eq!(r, transmute(lasx_xvslt_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2481,7 +2896,13 @@ unsafe fn test_lasx_xvslt_hu() {
     );
     let r = i64x4::new(-281470681808896, 4294901760, -65536, 281470681808895);
 
-    assert_eq!(r, transmute(lasx_xvslt_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2496,7 +2917,13 @@ unsafe fn test_lasx_xvslt_wu() {
     );
     let r = i64x4::new(-1, -1, -4294967296, -1);
 
-    assert_eq!(r, transmute(lasx_xvslt_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2515,7 +2942,13 @@ unsafe fn test_lasx_xvslt_du() {
     );
     let r = i64x4::new(-1, -1, 0, -1);
 
-    assert_eq!(r, transmute(lasx_xvslt_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvslt_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2526,7 +2959,7 @@ unsafe fn test_lasx_xvslti_bu() {
     );
     let r = i64x4::new(16711680, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslti_bu::<7>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_bu::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2537,7 +2970,7 @@ unsafe fn test_lasx_xvslti_hu() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslti_hu::<13>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_hu::<13>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2548,7 +2981,7 @@ unsafe fn test_lasx_xvslti_wu() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslti_wu::<8>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_wu::<8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2561,7 +2994,7 @@ unsafe fn test_lasx_xvslti_du() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslti_du::<2>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslti_du::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2581,7 +3014,13 @@ unsafe fn test_lasx_xvsle_b() {
         1095216726015,
     );
 
-    assert_eq!(r, transmute(lasx_xvsle_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2596,7 +3035,13 @@ unsafe fn test_lasx_xvsle_h() {
     );
     let r = i64x4::new(-1, 4294901760, 4294901760, -281470681743361);
 
-    assert_eq!(r, transmute(lasx_xvsle_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2623,7 +3068,13 @@ unsafe fn test_lasx_xvsle_w() {
     );
     let r = i64x4::new(-4294967296, 0, -1, -4294967296);
 
-    assert_eq!(r, transmute(lasx_xvsle_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2642,7 +3093,13 @@ unsafe fn test_lasx_xvsle_d() {
     );
     let r = i64x4::new(-1, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvsle_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2658,7 +3115,7 @@ unsafe fn test_lasx_xvslei_b() {
         280375465148415,
     );
 
-    assert_eq!(r, transmute(lasx_xvslei_b::<-14>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_b::<-14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2669,7 +3126,7 @@ unsafe fn test_lasx_xvslei_h() {
     );
     let r = i64x4::new(-65536, -4294901761, 281474976710655, -65536);
 
-    assert_eq!(r, transmute(lasx_xvslei_h::<-15>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_h::<-15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2680,7 +3137,7 @@ unsafe fn test_lasx_xvslei_w() {
     );
     let r = i64x4::new(-4294967296, 0, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvslei_w::<-3>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_w::<-3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2693,7 +3150,7 @@ unsafe fn test_lasx_xvslei_d() {
     );
     let r = i64x4::new(-1, 0, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvslei_d::<6>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_d::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2713,7 +3170,13 @@ unsafe fn test_lasx_xvsle_bu() {
         281474976710655,
     );
 
-    assert_eq!(r, transmute(lasx_xvsle_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2728,7 +3191,13 @@ unsafe fn test_lasx_xvsle_hu() {
     );
     let r = i64x4::new(281474976645120, -4294967296, 281470681808895, 0);
 
-    assert_eq!(r, transmute(lasx_xvsle_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2743,7 +3212,13 @@ unsafe fn test_lasx_xvsle_wu() {
     );
     let r = i64x4::new(-4294967296, -1, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvsle_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2762,7 +3237,13 @@ unsafe fn test_lasx_xvsle_du() {
     );
     let r = i64x4::new(0, -1, 0, -1);
 
-    assert_eq!(r, transmute(lasx_xvsle_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsle_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2773,7 +3254,7 @@ unsafe fn test_lasx_xvslei_bu() {
     );
     let r = i64x4::new(72056494526365440, 280375465082880, 71776119077928960, 0);
 
-    assert_eq!(r, transmute(lasx_xvslei_bu::<29>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_bu::<29>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2784,7 +3265,7 @@ unsafe fn test_lasx_xvslei_hu() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslei_hu::<30>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_hu::<30>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2795,7 +3276,7 @@ unsafe fn test_lasx_xvslei_wu() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslei_wu::<31>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_wu::<31>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2808,7 +3289,7 @@ unsafe fn test_lasx_xvslei_du() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvslei_du::<5>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvslei_du::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2824,7 +3305,7 @@ unsafe fn test_lasx_xvsat_b() {
         1985954429852520914,
     );
 
-    assert_eq!(r, transmute(lasx_xvsat_b::<7>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_b::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2840,7 +3321,7 @@ unsafe fn test_lasx_xvsat_h() {
         1152903912689234618,
     );
 
-    assert_eq!(r, transmute(lasx_xvsat_h::<12>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_h::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2857,7 +3338,7 @@ unsafe fn test_lasx_xvsat_w() {
     );
     let r = i64x4::new(-34359738361, 34359738360, -30064771080, -34359738361);
 
-    assert_eq!(r, transmute(lasx_xvsat_w::<3>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_w::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2875,7 +3356,7 @@ unsafe fn test_lasx_xvsat_d() {
         6102033771404793023,
     );
 
-    assert_eq!(r, transmute(lasx_xvsat_d::<63>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_d::<63>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2891,7 +3372,7 @@ unsafe fn test_lasx_xvsat_bu() {
         2539795165049929535,
     );
 
-    assert_eq!(r, transmute(lasx_xvsat_bu::<5>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_bu::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2907,7 +3388,7 @@ unsafe fn test_lasx_xvsat_hu() {
         1970354902204423,
     );
 
-    assert_eq!(r, transmute(lasx_xvsat_hu::<2>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_hu::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2918,7 +3399,7 @@ unsafe fn test_lasx_xvsat_wu() {
     );
     let r = i64x4::new(270582939711, 270582939711, 270582939711, 270582939711);
 
-    assert_eq!(r, transmute(lasx_xvsat_wu::<5>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_wu::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2931,7 +3412,7 @@ unsafe fn test_lasx_xvsat_du() {
     );
     let r = i64x4::new(8796093022207, 8796093022207, 8796093022207, 8796093022207);
 
-    assert_eq!(r, transmute(lasx_xvsat_du::<42>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvsat_du::<42>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -2951,7 +3432,13 @@ unsafe fn test_lasx_xvadda_b() {
         -6512388827583513148,
     );
 
-    assert_eq!(r, transmute(lasx_xvadda_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadda_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2971,7 +3458,13 @@ unsafe fn test_lasx_xvadda_h() {
         4288196905584441792,
     );
 
-    assert_eq!(r, transmute(lasx_xvadda_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadda_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -2997,7 +3490,13 @@ unsafe fn test_lasx_xvadda_w() {
         7114837115730115925,
     );
 
-    assert_eq!(r, transmute(lasx_xvadda_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadda_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3021,7 +3520,13 @@ unsafe fn test_lasx_xvadda_d() {
         -3532969990801796507,
     );
 
-    assert_eq!(r, transmute(lasx_xvadda_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadda_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3041,7 +3546,13 @@ unsafe fn test_lasx_xvsadd_b() {
         3530119333939728429,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3061,7 +3572,13 @@ unsafe fn test_lasx_xvsadd_h() {
         -5137195089227040637,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3093,7 +3610,13 @@ unsafe fn test_lasx_xvsadd_w() {
         6493388403303310332,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3117,7 +3640,13 @@ unsafe fn test_lasx_xvsadd_d() {
         -1670245304326307655,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3137,7 +3666,13 @@ unsafe fn test_lasx_xvsadd_bu() {
         -380207497217,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3157,7 +3692,13 @@ unsafe fn test_lasx_xvsadd_hu() {
         -2766274561,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3177,7 +3718,13 @@ unsafe fn test_lasx_xvsadd_wu() {
         9110967605937569791,
     );
 
-    assert_eq!(r, transmute(lasx_xvsadd_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3196,7 +3743,13 @@ unsafe fn test_lasx_xvsadd_du() {
     );
     let r = i64x4::new(-1, -7683287700352967836, -3264735658191843562, -1);
 
-    assert_eq!(r, transmute(lasx_xvsadd_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsadd_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3216,7 +3769,13 @@ unsafe fn test_lasx_xvavg_b() {
         -2451086284962613015,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3236,7 +3795,13 @@ unsafe fn test_lasx_xvavg_h() {
         -6082277202109387491,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3268,7 +3833,13 @@ unsafe fn test_lasx_xvavg_w() {
         -97541447405991454,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3292,7 +3863,13 @@ unsafe fn test_lasx_xvavg_d() {
         743619511763122382,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3312,7 +3889,13 @@ unsafe fn test_lasx_xvavg_bu() {
         5794025379951354001,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3332,7 +3915,13 @@ unsafe fn test_lasx_xvavg_hu() {
         -3939723307751543404,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3351,7 +3940,13 @@ unsafe fn test_lasx_xvavg_wu() {
         6180173283312674740,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3375,7 +3970,13 @@ unsafe fn test_lasx_xvavg_du() {
         -9048945872629561085,
     );
 
-    assert_eq!(r, transmute(lasx_xvavg_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavg_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3395,7 +3996,13 @@ unsafe fn test_lasx_xvavgr_b() {
         -1577916506278329386,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3415,7 +4022,13 @@ unsafe fn test_lasx_xvavgr_h() {
         1044782302812228671,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3447,7 +4060,13 @@ unsafe fn test_lasx_xvavgr_w() {
         4983380877656540978,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3471,7 +4090,13 @@ unsafe fn test_lasx_xvavgr_d() {
         229317404291257478,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3491,7 +4116,13 @@ unsafe fn test_lasx_xvavgr_bu() {
         8511681618342279077,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3511,7 +4142,13 @@ unsafe fn test_lasx_xvavgr_hu() {
         -4835281559523879916,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3531,7 +4168,13 @@ unsafe fn test_lasx_xvavgr_wu() {
         2489338192049926342,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3555,7 +4198,13 @@ unsafe fn test_lasx_xvavgr_du() {
         6414723233875186966,
     );
 
-    assert_eq!(r, transmute(lasx_xvavgr_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvavgr_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3575,7 +4224,13 @@ unsafe fn test_lasx_xvssub_b() {
         -4561472970538678093,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3595,7 +4250,13 @@ unsafe fn test_lasx_xvssub_h() {
         8048307602867637285,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3627,7 +4288,13 @@ unsafe fn test_lasx_xvssub_w() {
         4655436811119524629,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3651,7 +4318,13 @@ unsafe fn test_lasx_xvssub_d() {
         -9223372036854775808,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3671,7 +4344,13 @@ unsafe fn test_lasx_xvssub_bu() {
         864691185841012929,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3691,7 +4370,13 @@ unsafe fn test_lasx_xvssub_hu() {
         188750927758467,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3711,7 +4396,13 @@ unsafe fn test_lasx_xvssub_wu() {
         3974517532346153551,
     );
 
-    assert_eq!(r, transmute(lasx_xvssub_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3730,7 +4421,13 @@ unsafe fn test_lasx_xvssub_du() {
     );
     let r = i64x4::new(1075384133325788465, 0, 8236940487074099359, 0);
 
-    assert_eq!(r, transmute(lasx_xvssub_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssub_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3750,7 +4447,13 @@ unsafe fn test_lasx_xvabsd_b() {
         4109603046844106624,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3770,7 +4473,13 @@ unsafe fn test_lasx_xvabsd_h() {
         5513891007581016946,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3802,7 +4511,13 @@ unsafe fn test_lasx_xvabsd_w() {
         -7014776540975538355,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3826,7 +4541,13 @@ unsafe fn test_lasx_xvabsd_d() {
         4722306005291245989,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3846,7 +4567,13 @@ unsafe fn test_lasx_xvabsd_bu() {
         1887319547440621943,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3866,7 +4593,13 @@ unsafe fn test_lasx_xvabsd_hu() {
         1864011964690965056,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3886,7 +4619,13 @@ unsafe fn test_lasx_xvabsd_wu() {
         1525979489064328670,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3910,7 +4649,13 @@ unsafe fn test_lasx_xvabsd_du() {
         2127486190004927946,
     );
 
-    assert_eq!(r, transmute(lasx_xvabsd_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvabsd_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3930,7 +4675,13 @@ unsafe fn test_lasx_xvmul_b() {
         -9159357540886189840,
     );
 
-    assert_eq!(r, transmute(lasx_xvmul_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmul_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3950,7 +4701,13 @@ unsafe fn test_lasx_xvmul_h() {
         -7534790044979024262,
     );
 
-    assert_eq!(r, transmute(lasx_xvmul_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmul_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -3982,7 +4739,13 @@ unsafe fn test_lasx_xvmul_w() {
         1142495638330554240,
     );
 
-    assert_eq!(r, transmute(lasx_xvmul_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmul_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4006,7 +4769,13 @@ unsafe fn test_lasx_xvmul_d() {
         -3668010491661410128,
     );
 
-    assert_eq!(r, transmute(lasx_xvmul_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmul_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4032,7 +4801,11 @@ unsafe fn test_lasx_xvmadd_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmadd_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmadd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4059,7 +4832,11 @@ unsafe fn test_lasx_xvmadd_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmadd_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmadd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4104,7 +4881,11 @@ unsafe fn test_lasx_xvmadd_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmadd_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmadd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4137,7 +4918,11 @@ unsafe fn test_lasx_xvmadd_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmadd_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4164,7 +4949,11 @@ unsafe fn test_lasx_xvmsub_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmsub_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmsub_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4191,7 +4980,11 @@ unsafe fn test_lasx_xvmsub_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmsub_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmsub_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4236,7 +5029,11 @@ unsafe fn test_lasx_xvmsub_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmsub_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmsub_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4269,7 +5066,11 @@ unsafe fn test_lasx_xvmsub_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmsub_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4285,7 +5086,13 @@ unsafe fn test_lasx_xvdiv_b() {
     );
     let r = i64x4::new(67174400, 843334041468931, 16515072, 1090921824000);
 
-    assert_eq!(r, transmute(lasx_xvdiv_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4305,7 +5112,13 @@ unsafe fn test_lasx_xvdiv_h() {
         -281470681939967,
     );
 
-    assert_eq!(r, transmute(lasx_xvdiv_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4332,7 +5145,13 @@ unsafe fn test_lasx_xvdiv_w() {
     );
     let r = i64x4::new(-25769803778, 4294967295, 34359738365, 1);
 
-    assert_eq!(r, transmute(lasx_xvdiv_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4351,7 +5170,13 @@ unsafe fn test_lasx_xvdiv_d() {
     );
     let r = i64x4::new(-3, 0, -3, 0);
 
-    assert_eq!(r, transmute(lasx_xvdiv_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4371,7 +5196,13 @@ unsafe fn test_lasx_xvdiv_bu() {
         144118486677848127,
     );
 
-    assert_eq!(r, transmute(lasx_xvdiv_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4386,7 +5217,13 @@ unsafe fn test_lasx_xvdiv_hu() {
     );
     let r = i64x4::new(4295098372, 38654705665, 281474976776212, 283467841601537);
 
-    assert_eq!(r, transmute(lasx_xvdiv_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4401,7 +5238,13 @@ unsafe fn test_lasx_xvdiv_wu() {
     );
     let r = i64x4::new(0, 1, 46, 4294967299);
 
-    assert_eq!(r, transmute(lasx_xvdiv_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4420,7 +5263,13 @@ unsafe fn test_lasx_xvdiv_du() {
     );
     let r = i64x4::new(0, 0, 1, 6);
 
-    assert_eq!(r, transmute(lasx_xvdiv_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvdiv_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4440,7 +5289,13 @@ unsafe fn test_lasx_xvhaddw_h_b() {
         -18859072538017839,
     );
 
-    assert_eq!(r, transmute(lasx_xvhaddw_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4460,7 +5315,13 @@ unsafe fn test_lasx_xvhaddw_w_h() {
         -36597416302335,
     );
 
-    assert_eq!(r, transmute(lasx_xvhaddw_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4487,7 +5348,13 @@ unsafe fn test_lasx_xvhaddw_d_w() {
     );
     let r = i64x4::new(1043954543, 64421064, -1003667433, -119821715);
 
-    assert_eq!(r, transmute(lasx_xvhaddw_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4507,7 +5374,13 @@ unsafe fn test_lasx_xvhaddw_hu_bu() {
         56014362196705476,
     );
 
-    assert_eq!(r, transmute(lasx_xvhaddw_hu_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_hu_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4527,7 +5400,13 @@ unsafe fn test_lasx_xvhaddw_wu_hu() {
         392255068231306,
     );
 
-    assert_eq!(r, transmute(lasx_xvhaddw_wu_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_wu_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4542,7 +5421,13 @@ unsafe fn test_lasx_xvhaddw_du_wu() {
     );
     let r = i64x4::new(2983569336, 4514288382, 2479696956, 1680431840);
 
-    assert_eq!(r, transmute(lasx_xvhaddw_du_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_du_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4562,7 +5447,13 @@ unsafe fn test_lasx_xvhsubw_h_b() {
         -21955597927907350,
     );
 
-    assert_eq!(r, transmute(lasx_xvhsubw_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4582,7 +5473,13 @@ unsafe fn test_lasx_xvhsubw_w_h() {
         -108800111503156,
     );
 
-    assert_eq!(r, transmute(lasx_xvhsubw_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4603,7 +5500,13 @@ unsafe fn test_lasx_xvhsubw_d_w() {
     );
     let r = i64x4::new(2748898148, -45146293, 958916832, 1285325893);
 
-    assert_eq!(r, transmute(lasx_xvhsubw_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4623,7 +5526,13 @@ unsafe fn test_lasx_xvhsubw_hu_bu() {
         9289103727198239,
     );
 
-    assert_eq!(r, transmute(lasx_xvhsubw_hu_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_hu_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4643,7 +5552,13 @@ unsafe fn test_lasx_xvhsubw_wu_hu() {
         32018981198856,
     );
 
-    assert_eq!(r, transmute(lasx_xvhsubw_wu_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_wu_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4658,7 +5573,13 @@ unsafe fn test_lasx_xvhsubw_du_wu() {
     );
     let r = i64x4::new(-1056733131, -2613149992, 384615677, -1588276541);
 
-    assert_eq!(r, transmute(lasx_xvhsubw_du_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_du_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4678,7 +5599,13 @@ unsafe fn test_lasx_xvmod_b() {
         -48385121157714142,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4698,7 +5625,13 @@ unsafe fn test_lasx_xvmod_h() {
         -194216204870745003,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4723,8 +5656,14 @@ unsafe fn test_lasx_xvmod_w() {
         -1953977774316925897,
         807808928635455307,
     );
-
-    assert_eq!(r, transmute(lasx_xvmod_w(transmute(a), transmute(b))));
+
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4748,7 +5687,13 @@ unsafe fn test_lasx_xvmod_d() {
         -3048989907394276239,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4768,7 +5713,13 @@ unsafe fn test_lasx_xvmod_bu() {
         5417620637589803790,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4788,7 +5739,13 @@ unsafe fn test_lasx_xvmod_hu() {
         129490854556368167,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4808,7 +5765,13 @@ unsafe fn test_lasx_xvmod_wu() {
         480682694340619302,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4832,7 +5795,13 @@ unsafe fn test_lasx_xvmod_du() {
         150087784552479859,
     );
 
-    assert_eq!(r, transmute(lasx_xvmod_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmod_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4848,7 +5817,10 @@ unsafe fn test_lasx_xvrepl128vei_b() {
         8970181431921507452,
     );
 
-    assert_eq!(r, transmute(lasx_xvrepl128vei_b::<8>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrepl128vei_b::<8>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4864,7 +5836,10 @@ unsafe fn test_lasx_xvrepl128vei_h() {
         -3904680457625679409,
     );
 
-    assert_eq!(r, transmute(lasx_xvrepl128vei_h::<3>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrepl128vei_h::<3>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4886,7 +5861,10 @@ unsafe fn test_lasx_xvrepl128vei_w() {
         -1327396365108239351,
     );
 
-    assert_eq!(r, transmute(lasx_xvrepl128vei_w::<1>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrepl128vei_w::<1>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4904,7 +5882,10 @@ unsafe fn test_lasx_xvrepl128vei_d() {
         4427502889722976813,
     );
 
-    assert_eq!(r, transmute(lasx_xvrepl128vei_d::<0>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrepl128vei_d::<0>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4924,7 +5905,13 @@ unsafe fn test_lasx_xvpickev_b() {
         4502896606534087725,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickev_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickev_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4944,7 +5931,13 @@ unsafe fn test_lasx_xvpickev_h() {
         -2117051360895385090,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickev_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickev_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -4976,7 +5969,13 @@ unsafe fn test_lasx_xvpickev_w() {
         -4454806063744691677,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickev_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickev_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5000,7 +5999,13 @@ unsafe fn test_lasx_xvpickev_d() {
         1952973857169882715,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickev_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickev_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5020,7 +6025,13 @@ unsafe fn test_lasx_xvpickod_b() {
         4092165317489988560,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickod_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickod_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5040,7 +6051,13 @@ unsafe fn test_lasx_xvpickod_h() {
         5912677724127371711,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickod_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickod_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5072,7 +6089,13 @@ unsafe fn test_lasx_xvpickod_w() {
         14200989743342145,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickod_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickod_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5096,7 +6119,13 @@ unsafe fn test_lasx_xvpickod_d() {
         3923084493864153244,
     );
 
-    assert_eq!(r, transmute(lasx_xvpickod_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickod_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5116,7 +6145,13 @@ unsafe fn test_lasx_xvilvh_b() {
         6070396101995813657,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvh_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvh_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5136,7 +6171,13 @@ unsafe fn test_lasx_xvilvh_h() {
         6944594579025051980,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvh_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvh_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5168,7 +6209,13 @@ unsafe fn test_lasx_xvilvh_w() {
         2557948893958412086,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvh_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvh_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5192,7 +6239,13 @@ unsafe fn test_lasx_xvilvh_d() {
         -1576924492614617443,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvh_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvh_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5212,7 +6265,13 @@ unsafe fn test_lasx_xvilvl_b() {
         -1661662459983806644,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvl_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvl_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5232,7 +6291,13 @@ unsafe fn test_lasx_xvilvl_h() {
         -894657396213105965,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvl_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvl_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5264,7 +6329,13 @@ unsafe fn test_lasx_xvilvl_w() {
         6940426927105417163,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvl_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvl_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5288,7 +6359,13 @@ unsafe fn test_lasx_xvilvl_d() {
         -2688716944239585727,
     );
 
-    assert_eq!(r, transmute(lasx_xvilvl_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvilvl_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5308,7 +6385,13 @@ unsafe fn test_lasx_xvpackev_b() {
         -9004682544879989266,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackev_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackev_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5328,7 +6411,13 @@ unsafe fn test_lasx_xvpackev_h() {
         -5280992525495869891,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackev_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackev_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5360,7 +6449,13 @@ unsafe fn test_lasx_xvpackev_w() {
         338692385926626324,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackev_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackev_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5384,7 +6479,13 @@ unsafe fn test_lasx_xvpackev_d() {
         -3601691172781761847,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackev_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackev_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5404,7 +6505,13 @@ unsafe fn test_lasx_xvpackod_b() {
         3700670962761760653,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackod_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackod_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5424,7 +6531,13 @@ unsafe fn test_lasx_xvpackod_h() {
         -5523279134117035742,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackod_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackod_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5456,7 +6569,13 @@ unsafe fn test_lasx_xvpackod_w() {
         -7292079267755798519,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackod_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackod_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5480,7 +6599,13 @@ unsafe fn test_lasx_xvpackod_d() {
         -8628096693516187272,
     );
 
-    assert_eq!(r, transmute(lasx_xvpackod_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpackod_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5506,7 +6631,11 @@ unsafe fn test_lasx_xvshuf_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvshuf_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvshuf_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5530,7 +6659,11 @@ unsafe fn test_lasx_xvshuf_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvshuf_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvshuf_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5566,7 +6699,11 @@ unsafe fn test_lasx_xvshuf_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvshuf_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvshuf_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5594,7 +6731,11 @@ unsafe fn test_lasx_xvshuf_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvshuf_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvshuf_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5615,7 +6756,13 @@ unsafe fn test_lasx_xvand_v() {
         -7998109804568426495,
     );
 
-    assert_eq!(r, transmute(lasx_xvand_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvand_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5631,7 +6778,7 @@ unsafe fn test_lasx_xvandi_b() {
         793492300495455493,
     );
 
-    assert_eq!(r, transmute(lasx_xvandi_b::<47>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvandi_b::<47>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5651,7 +6798,13 @@ unsafe fn test_lasx_xvor_v() {
         -198266276987019378,
     );
 
-    assert_eq!(r, transmute(lasx_xvor_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvor_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5667,7 +6820,7 @@ unsafe fn test_lasx_xvori_b() {
         8466485259632311926,
     );
 
-    assert_eq!(r, transmute(lasx_xvori_b::<116>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvori_b::<116>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5687,7 +6840,13 @@ unsafe fn test_lasx_xvnor_v() {
         -8601510250130767824,
     );
 
-    assert_eq!(r, transmute(lasx_xvnor_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvnor_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5703,7 +6862,7 @@ unsafe fn test_lasx_xvnori_b() {
         6053994920729270286,
     );
 
-    assert_eq!(r, transmute(lasx_xvnori_b::<161>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvnori_b::<161>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5723,7 +6882,13 @@ unsafe fn test_lasx_xvxor_v() {
         4786489823605581252,
     );
 
-    assert_eq!(r, transmute(lasx_xvxor_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvxor_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5739,7 +6904,7 @@ unsafe fn test_lasx_xvxori_b() {
         1979210996964535887,
     );
 
-    assert_eq!(r, transmute(lasx_xvxori_b::<179>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvxori_b::<179>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5765,7 +6930,11 @@ unsafe fn test_lasx_xvbitsel_v() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvbitsel_v(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5788,7 +6957,10 @@ unsafe fn test_lasx_xvbitseli_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvbitseli_b::<156>(transmute(a), transmute(b)))
+        transmute(lasx_xvbitseli_b::<156>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5805,7 +6977,10 @@ unsafe fn test_lasx_xvshuf4i_b() {
         1357573681433480718,
     );
 
-    assert_eq!(r, transmute(lasx_xvshuf4i_b::<117>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvshuf4i_b::<117>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5821,7 +6996,10 @@ unsafe fn test_lasx_xvshuf4i_h() {
         4406041774853078309,
     );
 
-    assert_eq!(r, transmute(lasx_xvshuf4i_h::<125>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvshuf4i_h::<125>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5843,7 +7021,7 @@ unsafe fn test_lasx_xvshuf4i_w() {
         -206225345846487261,
     );
 
-    assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5855,7 +7033,7 @@ unsafe fn test_lasx_xvreplgr2vr_b() {
         8463800222054970741,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplgr2vr_b(-139770763)));
+    assert_eq!(r, transmute(lasx_xvreplgr2vr_b(black_box(-139770763))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5867,7 +7045,7 @@ unsafe fn test_lasx_xvreplgr2vr_h() {
         -1100020993973555013,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplgr2vr_h(-111546181)));
+    assert_eq!(r, transmute(lasx_xvreplgr2vr_h(black_box(-111546181))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5879,7 +7057,7 @@ unsafe fn test_lasx_xvreplgr2vr_w() {
         -8112237653938959659,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplgr2vr_w(-1888777515)));
+    assert_eq!(r, transmute(lasx_xvreplgr2vr_w(black_box(-1888777515))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5891,7 +7069,10 @@ unsafe fn test_lasx_xvreplgr2vr_d() {
         -1472556476011894783,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplgr2vr_d(-1472556476011894783)));
+    assert_eq!(
+        r,
+        transmute(lasx_xvreplgr2vr_d(black_box(-1472556476011894783)))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -5907,7 +7088,7 @@ unsafe fn test_lasx_xvpcnt_b() {
         288795538114413315,
     );
 
-    assert_eq!(r, transmute(lasx_xvpcnt_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpcnt_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5923,7 +7104,7 @@ unsafe fn test_lasx_xvpcnt_h() {
         2251829878980617,
     );
 
-    assert_eq!(r, transmute(lasx_xvpcnt_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpcnt_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5940,7 +7121,7 @@ unsafe fn test_lasx_xvpcnt_w() {
     );
     let r = i64x4::new(77309411341, 60129542155, 73014444046, 55834574863);
 
-    assert_eq!(r, transmute(lasx_xvpcnt_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpcnt_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5953,7 +7134,7 @@ unsafe fn test_lasx_xvpcnt_d() {
     );
     let r = i64x4::new(33, 31, 29, 33);
 
-    assert_eq!(r, transmute(lasx_xvpcnt_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpcnt_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5964,7 +7145,7 @@ unsafe fn test_lasx_xvclo_b() {
     );
     let r = i64x4::new(2207613190657, 8589934592, 1103806726660, 3298568503554);
 
-    assert_eq!(r, transmute(lasx_xvclo_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclo_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5980,7 +7161,7 @@ unsafe fn test_lasx_xvclo_h() {
         281479271677953,
     );
 
-    assert_eq!(r, transmute(lasx_xvclo_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclo_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -5997,7 +7178,7 @@ unsafe fn test_lasx_xvclo_w() {
     );
     let r = i64x4::new(4294967299, 1, 1, 8589934593);
 
-    assert_eq!(r, transmute(lasx_xvclo_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclo_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6010,7 +7191,7 @@ unsafe fn test_lasx_xvclo_d() {
     );
     let r = i64x4::new(2, 0, 1, 0);
 
-    assert_eq!(r, transmute(lasx_xvclo_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclo_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6021,7 +7202,7 @@ unsafe fn test_lasx_xvclz_b() {
     );
     let r = i64x4::new(65538, 72621643502977024, 216173885920575744, 3302846693380);
 
-    assert_eq!(r, transmute(lasx_xvclz_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6037,7 +7218,7 @@ unsafe fn test_lasx_xvclz_h() {
         17179934721,
     );
 
-    assert_eq!(r, transmute(lasx_xvclz_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6054,7 +7235,7 @@ unsafe fn test_lasx_xvclz_w() {
     );
     let r = i64x4::new(8589934592, 0, 3, 4294967296);
 
-    assert_eq!(r, transmute(lasx_xvclz_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6067,7 +7248,7 @@ unsafe fn test_lasx_xvclz_d() {
     );
     let r = i64x4::new(0, 0, 0, 1);
 
-    assert_eq!(r, transmute(lasx_xvclz_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvclz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6087,7 +7268,13 @@ unsafe fn test_lasx_xvfadd_s() {
         4545553165339792015,
     );
 
-    assert_eq!(r, transmute(lasx_xvfadd_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfadd_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6111,7 +7298,13 @@ unsafe fn test_lasx_xvfadd_d() {
         4607242424158867483,
     );
 
-    assert_eq!(r, transmute(lasx_xvfadd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6131,7 +7324,13 @@ unsafe fn test_lasx_xvfsub_s() {
         -4716328899074058446,
     );
 
-    assert_eq!(r, transmute(lasx_xvfsub_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfsub_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6155,7 +7354,13 @@ unsafe fn test_lasx_xvfsub_d() {
         4602885236169716939,
     );
 
-    assert_eq!(r, transmute(lasx_xvfsub_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6175,7 +7380,13 @@ unsafe fn test_lasx_xvfmul_s() {
         4412217640780718091,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmul_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmul_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6199,7 +7410,13 @@ unsafe fn test_lasx_xvfmul_d() {
         4604645288864682176,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmul_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmul_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6219,7 +7436,13 @@ unsafe fn test_lasx_xvfdiv_s() {
         4544549637634302505,
     );
 
-    assert_eq!(r, transmute(lasx_xvfdiv_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfdiv_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6243,7 +7466,13 @@ unsafe fn test_lasx_xvfdiv_d() {
         4608170208670026319,
     );
 
-    assert_eq!(r, transmute(lasx_xvfdiv_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfdiv_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6263,7 +7492,13 @@ unsafe fn test_lasx_xvfcvt_h_s() {
         4182498428240214789,
     );
 
-    assert_eq!(r, transmute(lasx_xvfcvt_h_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcvt_h_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6287,7 +7522,13 @@ unsafe fn test_lasx_xvfcvt_s_d() {
         4509540616169896248,
     );
 
-    assert_eq!(r, transmute(lasx_xvfcvt_s_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcvt_s_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6307,7 +7548,13 @@ unsafe fn test_lasx_xvfmin_s() {
         4470137692837414470,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmin_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmin_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6331,7 +7578,13 @@ unsafe fn test_lasx_xvfmin_d() {
         4596668800324369880,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmin_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmin_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6351,7 +7604,13 @@ unsafe fn test_lasx_xvfmina_s() {
         4561809912873379512,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmina_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmina_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6375,7 +7634,13 @@ unsafe fn test_lasx_xvfmina_d() {
         4597161583916257152,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmina_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmina_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6395,7 +7660,13 @@ unsafe fn test_lasx_xvfmax_s() {
         4574742780979947531,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmax_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmax_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6419,7 +7690,13 @@ unsafe fn test_lasx_xvfmax_d() {
         4602928137069840177,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmax_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmax_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6439,7 +7716,13 @@ unsafe fn test_lasx_xvfmaxa_s() {
         4527767521076114844,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmaxa_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmaxa_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6463,7 +7746,13 @@ unsafe fn test_lasx_xvfmaxa_d() {
         4596362093665607644,
     );
 
-    assert_eq!(r, transmute(lasx_xvfmaxa_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfmaxa_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -6474,7 +7763,7 @@ unsafe fn test_lasx_xvfclass_s() {
     );
     let r = i64x4::new(549755814016, 549755814016, 549755814016, 549755814016);
 
-    assert_eq!(r, transmute(lasx_xvfclass_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfclass_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6487,7 +7776,7 @@ unsafe fn test_lasx_xvfclass_d() {
     );
     let r = i64x4::new(128, 128, 128, 128);
 
-    assert_eq!(r, transmute(lasx_xvfclass_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfclass_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6503,7 +7792,7 @@ unsafe fn test_lasx_xvfsqrt_s() {
         4566109703441416989,
     );
 
-    assert_eq!(r, transmute(lasx_xvfsqrt_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfsqrt_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6521,7 +7810,7 @@ unsafe fn test_lasx_xvfsqrt_d() {
         4601138545884238765,
     );
 
-    assert_eq!(r, transmute(lasx_xvfsqrt_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfsqrt_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6537,7 +7826,7 @@ unsafe fn test_lasx_xvfrecip_s() {
         4585242601638738136,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrecip_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrecip_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6555,7 +7844,7 @@ unsafe fn test_lasx_xvfrecip_d() {
         4611482062367896141,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrecip_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrecip_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx,frecipe")]
@@ -6571,7 +7860,7 @@ unsafe fn test_lasx_xvfrecipe_s() {
         4728509413412007938,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrecipe_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrecipe_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx,frecipe")]
@@ -6589,7 +7878,7 @@ unsafe fn test_lasx_xvfrecipe_d() {
         4611499011256352768,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrecipe_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrecipe_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx,frecipe")]
@@ -6605,7 +7894,7 @@ unsafe fn test_lasx_xvfrsqrte_s() {
         4612427253546066334,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrsqrte_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrsqrte_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx,frecipe")]
@@ -6623,7 +7912,7 @@ unsafe fn test_lasx_xvfrsqrte_d() {
         4612346183891812352,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrsqrte_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrsqrte_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6634,7 +7923,7 @@ unsafe fn test_lasx_xvfrint_s() {
     );
     let r = i64x4::new(0, 4575657222473777152, 1065353216, 4575657222473777152);
 
-    assert_eq!(r, transmute(lasx_xvfrint_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrint_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6652,7 +7941,7 @@ unsafe fn test_lasx_xvfrint_d() {
         0,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrint_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrint_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6668,7 +7957,7 @@ unsafe fn test_lasx_xvfrsqrt_s() {
         4651901116840286347,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrsqrt_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrsqrt_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6686,7 +7975,7 @@ unsafe fn test_lasx_xvfrsqrt_d() {
         4612495411087822923,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrsqrt_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrsqrt_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6702,7 +7991,7 @@ unsafe fn test_lasx_xvflogb_s() {
         -4575657218195587072,
     );
 
-    assert_eq!(r, transmute(lasx_xvflogb_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvflogb_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6720,7 +8009,7 @@ unsafe fn test_lasx_xvflogb_d() {
         -4616189618054758400,
     );
 
-    assert_eq!(r, transmute(lasx_xvflogb_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvflogb_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6736,7 +8025,7 @@ unsafe fn test_lasx_xvfcvth_s_h() {
         4931511963987271680,
     );
 
-    assert_eq!(r, transmute(lasx_xvfcvth_s_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfcvth_s_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6752,7 +8041,7 @@ unsafe fn test_lasx_xvfcvth_d_s() {
         4605684912954015744,
     );
 
-    assert_eq!(r, transmute(lasx_xvfcvth_d_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfcvth_d_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6768,7 +8057,7 @@ unsafe fn test_lasx_xvfcvtl_s_h() {
         4719033540912152576,
     );
 
-    assert_eq!(r, transmute(lasx_xvfcvtl_s_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfcvtl_s_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6784,7 +8073,7 @@ unsafe fn test_lasx_xvfcvtl_d_s() {
         4598772185639682048,
     );
 
-    assert_eq!(r, transmute(lasx_xvfcvtl_d_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfcvtl_d_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6795,7 +8084,7 @@ unsafe fn test_lasx_xvftint_w_s() {
     );
     let r = i64x4::new(0, 0, 1, 0);
 
-    assert_eq!(r, transmute(lasx_xvftint_w_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftint_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6808,7 +8097,7 @@ unsafe fn test_lasx_xvftint_l_d() {
     );
     let r = i64x4::new(0, 0, 1, 1);
 
-    assert_eq!(r, transmute(lasx_xvftint_l_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftint_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6819,7 +8108,7 @@ unsafe fn test_lasx_xvftint_wu_s() {
     );
     let r = i64x4::new(1, 4294967297, 1, 4294967297);
 
-    assert_eq!(r, transmute(lasx_xvftint_wu_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftint_wu_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6832,7 +8121,7 @@ unsafe fn test_lasx_xvftint_lu_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftint_lu_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftint_lu_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6843,7 +8132,7 @@ unsafe fn test_lasx_xvftintrz_w_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrz_w_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrz_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6856,7 +8145,7 @@ unsafe fn test_lasx_xvftintrz_l_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrz_l_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrz_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6867,7 +8156,7 @@ unsafe fn test_lasx_xvftintrz_wu_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrz_wu_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrz_wu_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6880,7 +8169,7 @@ unsafe fn test_lasx_xvftintrz_lu_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrz_lu_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrz_lu_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6902,7 +8191,7 @@ unsafe fn test_lasx_xvffint_s_w() {
         5669248528000103797,
     );
 
-    assert_eq!(r, transmute(lasx_xvffint_s_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvffint_s_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6920,7 +8209,7 @@ unsafe fn test_lasx_xvffint_d_l() {
         -4362160337941248997,
     );
 
-    assert_eq!(r, transmute(lasx_xvffint_d_l(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvffint_d_l(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6936,7 +8225,7 @@ unsafe fn test_lasx_xvffint_s_wu() {
         5723492283472660471,
     );
 
-    assert_eq!(r, transmute(lasx_xvffint_s_wu(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvffint_s_wu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6954,7 +8243,7 @@ unsafe fn test_lasx_xvffint_d_lu() {
         4892265567869239358,
     );
 
-    assert_eq!(r, transmute(lasx_xvffint_d_lu(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvffint_d_lu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6970,7 +8259,7 @@ unsafe fn test_lasx_xvreplve_b() {
         -5280832617179597130,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve_b(transmute(a), 5)));
+    assert_eq!(r, transmute(lasx_xvreplve_b(black_box(transmute(a)), 5)));
 }
 
 #[simd_test(enable = "lasx")]
@@ -6986,7 +8275,7 @@ unsafe fn test_lasx_xvreplve_h() {
         -8907411554322709406,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve_h(transmute(a), -5)));
+    assert_eq!(r, transmute(lasx_xvreplve_h(black_box(transmute(a)), -5)));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7008,7 +8297,7 @@ unsafe fn test_lasx_xvreplve_w() {
         -2569718735257041300,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve_w(transmute(a), 1)));
+    assert_eq!(r, transmute(lasx_xvreplve_w(black_box(transmute(a)), 1)));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7026,7 +8315,7 @@ unsafe fn test_lasx_xvreplve_d() {
         -7945890434069746992,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve_d(transmute(a), -6)));
+    assert_eq!(r, transmute(lasx_xvreplve_d(black_box(transmute(a)), -6)));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7060,7 +8349,10 @@ unsafe fn test_lasx_xvpermi_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvpermi_w::<217>(transmute(a), transmute(b)))
+        transmute(lasx_xvpermi_w::<217>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -7081,7 +8373,13 @@ unsafe fn test_lasx_xvandn_v() {
         5350223724150917,
     );
 
-    assert_eq!(r, transmute(lasx_xvandn_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvandn_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7097,7 +8395,7 @@ unsafe fn test_lasx_xvneg_b() {
         -5388239603749330053,
     );
 
-    assert_eq!(r, transmute(lasx_xvneg_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvneg_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7113,7 +8411,7 @@ unsafe fn test_lasx_xvneg_h() {
         5510114370614593991,
     );
 
-    assert_eq!(r, transmute(lasx_xvneg_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvneg_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7135,7 +8433,7 @@ unsafe fn test_lasx_xvneg_w() {
         -6240794077010148150,
     );
 
-    assert_eq!(r, transmute(lasx_xvneg_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvneg_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7153,7 +8451,7 @@ unsafe fn test_lasx_xvneg_d() {
         -906750919774206543,
     );
 
-    assert_eq!(r, transmute(lasx_xvneg_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvneg_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -7173,7 +8471,13 @@ unsafe fn test_lasx_xvmuh_b() {
         131228860074087168,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7193,7 +8497,13 @@ unsafe fn test_lasx_xvmuh_h() {
         -14890625691814142,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7225,7 +8535,13 @@ unsafe fn test_lasx_xvmuh_w() {
         15710306989437773,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7249,7 +8565,13 @@ unsafe fn test_lasx_xvmuh_d() {
         273863514955286020,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7268,8 +8590,14 @@ unsafe fn test_lasx_xvmuh_bu() {
         4579080056940291892,
         442221464076014683,
     );
-
-    assert_eq!(r, transmute(lasx_xvmuh_bu(transmute(a), transmute(b))));
+
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7289,7 +8617,13 @@ unsafe fn test_lasx_xvmuh_hu() {
         108786773599653576,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7309,7 +8643,13 @@ unsafe fn test_lasx_xvmuh_wu() {
         3278999485098399815,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7333,7 +8673,13 @@ unsafe fn test_lasx_xvmuh_du() {
         1569823798457591419,
     );
 
-    assert_eq!(r, transmute(lasx_xvmuh_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmuh_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7349,7 +8695,10 @@ unsafe fn test_lasx_xvsllwil_h_b() {
         283732621893107440,
     );
 
-    assert_eq!(r, transmute(lasx_xvsllwil_h_b::<4>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsllwil_h_b::<4>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7365,7 +8714,10 @@ unsafe fn test_lasx_xvsllwil_w_h() {
         -19087521822982144,
     );
 
-    assert_eq!(r, transmute(lasx_xvsllwil_w_h::<11>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsllwil_w_h::<11>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7387,7 +8739,10 @@ unsafe fn test_lasx_xvsllwil_d_w() {
         -21769464725504,
     );
 
-    assert_eq!(r, transmute(lasx_xvsllwil_d_w::<14>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsllwil_d_w::<14>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7403,7 +8758,10 @@ unsafe fn test_lasx_xvsllwil_hu_bu() {
         180156217344131904,
     );
 
-    assert_eq!(r, transmute(lasx_xvsllwil_hu_bu::<5>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsllwil_hu_bu::<5>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7419,7 +8777,10 @@ unsafe fn test_lasx_xvsllwil_wu_hu() {
         3493526673607606272,
     );
 
-    assert_eq!(r, transmute(lasx_xvsllwil_wu_hu::<14>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsllwil_wu_hu::<14>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7435,7 +8796,10 @@ unsafe fn test_lasx_xvsllwil_du_wu() {
         147522340803051520,
     );
 
-    assert_eq!(r, transmute(lasx_xvsllwil_du_wu::<28>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsllwil_du_wu::<28>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7450,7 +8814,13 @@ unsafe fn test_lasx_xvsran_b_h() {
     );
     let r = i64x4::new(-5107013816536599300, 0, -576745268203292981, 0);
 
-    assert_eq!(r, transmute(lasx_xvsran_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsran_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7477,7 +8847,13 @@ unsafe fn test_lasx_xvsran_h_w() {
     );
     let r = i64x4::new(-7492863874014043255, 0, -5145548381371170633, 0);
 
-    assert_eq!(r, transmute(lasx_xvsran_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsran_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7496,7 +8872,13 @@ unsafe fn test_lasx_xvsran_w_d() {
     );
     let r = i64x4::new(58054624080, 0, 1863787881113495402, 0);
 
-    assert_eq!(r, transmute(lasx_xvsran_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsran_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7511,7 +8893,13 @@ unsafe fn test_lasx_xvssran_b_h() {
     );
     let r = i64x4::new(179865806513864501, 0, -9222296776751415043, 0);
 
-    assert_eq!(r, transmute(lasx_xvssran_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssran_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7538,7 +8926,13 @@ unsafe fn test_lasx_xvssran_h_w() {
     );
     let r = i64x4::new(281015415144451, 0, 281472829161978, 0);
 
-    assert_eq!(r, transmute(lasx_xvssran_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssran_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7557,7 +8951,13 @@ unsafe fn test_lasx_xvssran_w_d() {
     );
     let r = i64x4::new(-109363692856335914, 0, -713658208354305, 0);
 
-    assert_eq!(r, transmute(lasx_xvssran_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssran_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7572,7 +8972,13 @@ unsafe fn test_lasx_xvssran_bu_h() {
     );
     let r = i64x4::new(144116287595479055, 0, 71776131929997312, 0);
 
-    assert_eq!(r, transmute(lasx_xvssran_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssran_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7587,7 +8993,13 @@ unsafe fn test_lasx_xvssran_hu_w() {
     );
     let r = i64x4::new(254837589540863, 0, 281470681765343, 0);
 
-    assert_eq!(r, transmute(lasx_xvssran_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssran_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7606,7 +9018,13 @@ unsafe fn test_lasx_xvssran_wu_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvssran_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssran_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7621,7 +9039,13 @@ unsafe fn test_lasx_xvsrarn_b_h() {
     );
     let r = i64x4::new(-7204067930850651184, 0, -5909457163402939758, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrarn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrarn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7648,7 +9072,13 @@ unsafe fn test_lasx_xvsrarn_h_w() {
     );
     let r = i64x4::new(4021320339558432771, 0, -5499970420202995712, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrarn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrarn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7667,7 +9097,13 @@ unsafe fn test_lasx_xvsrarn_w_d() {
     );
     let r = i64x4::new(-69752906595470, 0, -7240468610764767136, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrarn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrarn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7682,7 +9118,13 @@ unsafe fn test_lasx_xvssrarn_b_h() {
     );
     let r = i64x4::new(142413695971000447, 0, -141179869986524, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrarn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrarn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7709,7 +9151,13 @@ unsafe fn test_lasx_xvssrarn_h_w() {
     );
     let r = i64x4::new(-10414028872220672, 0, 9223104806137135104, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrarn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrarn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7728,7 +9176,13 @@ unsafe fn test_lasx_xvssrarn_w_d() {
     );
     let r = i64x4::new(2147483648, 0, 326062786704572415, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrarn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrarn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7743,7 +9197,13 @@ unsafe fn test_lasx_xvssrarn_bu_h() {
     );
     let r = i64x4::new(4286578689, 0, 8163878114427135, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrarn_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrarn_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7758,7 +9218,13 @@ unsafe fn test_lasx_xvssrarn_hu_w() {
     );
     let r = i64x4::new(-281474976710656, 0, 2199023255552, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrarn_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrarn_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7777,7 +9243,13 @@ unsafe fn test_lasx_xvssrarn_wu_d() {
     );
     let r = i64x4::new(-3539373509, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrarn_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrarn_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7792,7 +9264,13 @@ unsafe fn test_lasx_xvsrln_b_h() {
     );
     let r = i64x4::new(776589499955319005, 0, 285495199351976, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrln_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrln_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7819,7 +9297,13 @@ unsafe fn test_lasx_xvsrln_h_w() {
     );
     let r = i64x4::new(-6090306652816735409, 0, -1175228277373752196, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrln_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrln_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7838,7 +9322,13 @@ unsafe fn test_lasx_xvsrln_w_d() {
     );
     let r = i64x4::new(262796920316080678, 0, 1866060245111069, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrln_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrln_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7853,7 +9343,13 @@ unsafe fn test_lasx_xvssrln_bu_h() {
     );
     let r = i64x4::new(-996419305685, 0, -71773920038018305, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrln_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrln_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7867,7 +9363,13 @@ unsafe fn test_lasx_xvssrln_hu_w() {
     );
     let r = i64x4::new(2319476961249468, 0, 208855326080470286, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrln_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrln_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7886,7 +9388,13 @@ unsafe fn test_lasx_xvssrln_wu_d() {
     );
     let r = i64x4::new(-1, 0, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrln_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrln_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7901,7 +9409,13 @@ unsafe fn test_lasx_xvsrlrn_b_h() {
     );
     let r = i64x4::new(-6693460433276960310, 0, -6122543899663285619, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrlrn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlrn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7928,7 +9442,13 @@ unsafe fn test_lasx_xvsrlrn_h_w() {
     );
     let r = i64x4::new(390723813551243448, 0, 6015496732136052023, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrlrn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlrn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7947,7 +9467,13 @@ unsafe fn test_lasx_xvsrlrn_w_d() {
     );
     let r = i64x4::new(4295025675, 0, -3281590872273059757, 0);
 
-    assert_eq!(r, transmute(lasx_xvsrlrn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsrlrn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7962,7 +9488,13 @@ unsafe fn test_lasx_xvssrlrn_bu_h() {
     );
     let r = i64x4::new(-258385232527491, 0, 4034951496335359804, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrlrn_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrlrn_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7977,7 +9509,13 @@ unsafe fn test_lasx_xvssrlrn_hu_w() {
     );
     let r = i64x4::new(-3854303052, 0, -4029743103, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrlrn_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrlrn_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -7996,7 +9534,13 @@ unsafe fn test_lasx_xvssrlrn_wu_d() {
     );
     let r = i64x4::new(-3223981555, 0, 35952127557763071, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrlrn_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrlrn_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8018,7 +9562,10 @@ unsafe fn test_lasx_xvfrstpi_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfrstpi_b::<24>(transmute(a), transmute(b)))
+        transmute(lasx_xvfrstpi_b::<24>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8041,7 +9588,10 @@ unsafe fn test_lasx_xvfrstpi_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfrstpi_h::<10>(transmute(a), transmute(b)))
+        transmute(lasx_xvfrstpi_h::<10>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8068,7 +9618,11 @@ unsafe fn test_lasx_xvfrstp_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfrstp_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8095,7 +9649,11 @@ unsafe fn test_lasx_xvfrstp_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfrstp_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8122,7 +9680,10 @@ unsafe fn test_lasx_xvshuf4i_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvshuf4i_d::<115>(transmute(a), transmute(b)))
+        transmute(lasx_xvshuf4i_d::<115>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8139,7 +9700,7 @@ unsafe fn test_lasx_xvbsrl_v() {
         8842437361645499941,
     );
 
-    assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8155,7 +9716,7 @@ unsafe fn test_lasx_xvbsll_v() {
         5030360181484275352,
     );
 
-    assert_eq!(r, transmute(lasx_xvbsll_v::<0>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvbsll_v::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8177,7 +9738,10 @@ unsafe fn test_lasx_xvextrins_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvextrins_b::<69>(transmute(a), transmute(b)))
+        transmute(lasx_xvextrins_b::<69>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8200,7 +9764,10 @@ unsafe fn test_lasx_xvextrins_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvextrins_h::<190>(transmute(a), transmute(b)))
+        transmute(lasx_xvextrins_h::<190>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8235,7 +9802,10 @@ unsafe fn test_lasx_xvextrins_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvextrins_w::<133>(transmute(a), transmute(b)))
+        transmute(lasx_xvextrins_w::<133>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8262,7 +9832,10 @@ unsafe fn test_lasx_xvextrins_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvextrins_d::<210>(transmute(a), transmute(b)))
+        transmute(lasx_xvextrins_d::<210>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8274,7 +9847,7 @@ unsafe fn test_lasx_xvmskltz_b() {
     );
     let r = i64x4::new(5684, 0, 36244, 0);
 
-    assert_eq!(r, transmute(lasx_xvmskltz_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmskltz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8285,7 +9858,7 @@ unsafe fn test_lasx_xvmskltz_h() {
     );
     let r = i64x4::new(225, 0, 96, 0);
 
-    assert_eq!(r, transmute(lasx_xvmskltz_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmskltz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8302,7 +9875,7 @@ unsafe fn test_lasx_xvmskltz_w() {
     );
     let r = i64x4::new(13, 0, 10, 0);
 
-    assert_eq!(r, transmute(lasx_xvmskltz_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmskltz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8315,7 +9888,7 @@ unsafe fn test_lasx_xvmskltz_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvmskltz_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmskltz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8335,7 +9908,13 @@ unsafe fn test_lasx_xvsigncov_b() {
         -6215157037026399088,
     );
 
-    assert_eq!(r, transmute(lasx_xvsigncov_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsigncov_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8355,7 +9934,13 @@ unsafe fn test_lasx_xvsigncov_h() {
         2866604565619890601,
     );
 
-    assert_eq!(r, transmute(lasx_xvsigncov_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsigncov_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8387,7 +9972,13 @@ unsafe fn test_lasx_xvsigncov_w() {
         -180354238538399451,
     );
 
-    assert_eq!(r, transmute(lasx_xvsigncov_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsigncov_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8411,7 +10002,13 @@ unsafe fn test_lasx_xvsigncov_d() {
         293290471183495768,
     );
 
-    assert_eq!(r, transmute(lasx_xvsigncov_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsigncov_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8437,7 +10034,11 @@ unsafe fn test_lasx_xvfmadd_s() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfmadd_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8470,7 +10071,11 @@ unsafe fn test_lasx_xvfmadd_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfmadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8497,7 +10102,11 @@ unsafe fn test_lasx_xvfmsub_s() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfmsub_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8530,7 +10139,11 @@ unsafe fn test_lasx_xvfmsub_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfmsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8557,7 +10170,11 @@ unsafe fn test_lasx_xvfnmadd_s() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfnmadd_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8590,7 +10207,11 @@ unsafe fn test_lasx_xvfnmadd_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfnmadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8617,7 +10238,11 @@ unsafe fn test_lasx_xvfnmsub_s() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfnmsub_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8650,7 +10275,11 @@ unsafe fn test_lasx_xvfnmsub_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvfnmsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -8662,7 +10291,7 @@ unsafe fn test_lasx_xvftintrne_w_s() {
     );
     let r = i64x4::new(1, 0, 1, 4294967297);
 
-    assert_eq!(r, transmute(lasx_xvftintrne_w_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrne_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8675,7 +10304,7 @@ unsafe fn test_lasx_xvftintrne_l_d() {
     );
     let r = i64x4::new(0, 1, 1, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrne_l_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrne_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8686,7 +10315,7 @@ unsafe fn test_lasx_xvftintrp_w_s() {
     );
     let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297);
 
-    assert_eq!(r, transmute(lasx_xvftintrp_w_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrp_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8699,7 +10328,7 @@ unsafe fn test_lasx_xvftintrp_l_d() {
     );
     let r = i64x4::new(1, 1, 1, 1);
 
-    assert_eq!(r, transmute(lasx_xvftintrp_l_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrp_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8710,7 +10339,7 @@ unsafe fn test_lasx_xvftintrm_w_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrm_w_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrm_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8723,7 +10352,7 @@ unsafe fn test_lasx_xvftintrm_l_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrm_l_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrm_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8742,7 +10371,13 @@ unsafe fn test_lasx_xvftint_w_d() {
     );
     let r = i64x4::new(0, 0, 4294967297, 4294967296);
 
-    assert_eq!(r, transmute(lasx_xvftint_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvftint_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8766,7 +10401,13 @@ unsafe fn test_lasx_xvffint_s_l() {
         -2383622820954443903,
     );
 
-    assert_eq!(r, transmute(lasx_xvffint_s_l(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvffint_s_l(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8785,7 +10426,13 @@ unsafe fn test_lasx_xvftintrz_w_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrz_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvftintrz_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8804,7 +10451,13 @@ unsafe fn test_lasx_xvftintrp_w_d() {
     );
     let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297);
 
-    assert_eq!(r, transmute(lasx_xvftintrp_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvftintrp_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8823,7 +10476,13 @@ unsafe fn test_lasx_xvftintrm_w_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrm_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvftintrm_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -8844,7 +10503,10 @@ unsafe fn test_lasx_xvftintrne_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvftintrne_w_d(transmute(a), transmute(b)))
+        transmute(lasx_xvftintrne_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -8856,7 +10518,7 @@ unsafe fn test_lasx_xvftinth_l_s() {
     );
     let r = i64x4::new(0, 1, 0, 1);
 
-    assert_eq!(r, transmute(lasx_xvftinth_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftinth_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8867,7 +10529,7 @@ unsafe fn test_lasx_xvftintl_l_s() {
     );
     let r = i64x4::new(0, 0, 0, 1);
 
-    assert_eq!(r, transmute(lasx_xvftintl_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintl_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8889,7 +10551,7 @@ unsafe fn test_lasx_xvffinth_d_w() {
         -4485741486683455488,
     );
 
-    assert_eq!(r, transmute(lasx_xvffinth_d_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvffinth_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8911,7 +10573,7 @@ unsafe fn test_lasx_xvffintl_d_w() {
         -4489746915386195968,
     );
 
-    assert_eq!(r, transmute(lasx_xvffintl_d_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvffintl_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8922,7 +10584,7 @@ unsafe fn test_lasx_xvftintrzh_l_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrzh_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrzh_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8933,7 +10595,7 @@ unsafe fn test_lasx_xvftintrzl_l_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrzl_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrzl_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8944,7 +10606,7 @@ unsafe fn test_lasx_xvftintrph_l_s() {
     );
     let r = i64x4::new(1, 1, 1, 1);
 
-    assert_eq!(r, transmute(lasx_xvftintrph_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrph_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8955,7 +10617,7 @@ unsafe fn test_lasx_xvftintrpl_l_s() {
     );
     let r = i64x4::new(1, 1, 1, 1);
 
-    assert_eq!(r, transmute(lasx_xvftintrpl_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrpl_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8966,7 +10628,7 @@ unsafe fn test_lasx_xvftintrmh_l_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrmh_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrmh_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8977,7 +10639,7 @@ unsafe fn test_lasx_xvftintrml_l_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrml_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrml_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8988,7 +10650,7 @@ unsafe fn test_lasx_xvftintrneh_l_s() {
     );
     let r = i64x4::new(1, 0, 0, 1);
 
-    assert_eq!(r, transmute(lasx_xvftintrneh_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrneh_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -8999,7 +10661,7 @@ unsafe fn test_lasx_xvftintrnel_l_s() {
     );
     let r = i64x4::new(0, 1, 1, 0);
 
-    assert_eq!(r, transmute(lasx_xvftintrnel_l_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvftintrnel_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9015,7 +10677,7 @@ unsafe fn test_lasx_xvfrintrne_s() {
         1065353216,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrintrne_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrne_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9028,7 +10690,7 @@ unsafe fn test_lasx_xvfrintrne_d() {
     );
     let r = i64x4::new(0, 0, 4607182418800017408, 0);
 
-    assert_eq!(r, transmute(lasx_xvfrintrne_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrne_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9039,7 +10701,7 @@ unsafe fn test_lasx_xvfrintrz_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfrintrz_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrz_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9052,7 +10714,7 @@ unsafe fn test_lasx_xvfrintrz_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfrintrz_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9068,7 +10730,7 @@ unsafe fn test_lasx_xvfrintrp_s() {
         4575657222473777152,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrintrp_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrp_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9086,7 +10748,7 @@ unsafe fn test_lasx_xvfrintrp_d() {
         4607182418800017408,
     );
 
-    assert_eq!(r, transmute(lasx_xvfrintrp_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrp_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9097,7 +10759,7 @@ unsafe fn test_lasx_xvfrintrm_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfrintrm_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrm_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9110,7 +10772,7 @@ unsafe fn test_lasx_xvfrintrm_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfrintrm_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvfrintrm_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9146,7 +10808,7 @@ unsafe fn test_lasx_xvst() {
         -1239470096778490055,
     );
 
-    lasx_xvst::<0>(transmute(a), o.as_mut_ptr());
+    lasx_xvst::<0>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -9167,7 +10829,7 @@ unsafe fn test_lasx_xvstelm_b() {
         -1243134694581333281,
     );
 
-    lasx_xvstelm_b::<0, 9>(transmute(a), o.as_mut_ptr());
+    lasx_xvstelm_b::<0, 9>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -9188,7 +10850,7 @@ unsafe fn test_lasx_xvstelm_h() {
         4649151313692342074,
     );
 
-    lasx_xvstelm_h::<0, 6>(transmute(a), o.as_mut_ptr());
+    lasx_xvstelm_h::<0, 6>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -9215,7 +10877,7 @@ unsafe fn test_lasx_xvstelm_w() {
         5471549130760739388,
     );
 
-    lasx_xvstelm_w::<0, 3>(transmute(a), o.as_mut_ptr());
+    lasx_xvstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -9238,7 +10900,7 @@ unsafe fn test_lasx_xvstelm_d() {
         -4006899083251152793,
     );
 
-    lasx_xvstelm_d::<0, 0>(transmute(a), o.as_mut_ptr());
+    lasx_xvstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -9273,7 +10935,10 @@ unsafe fn test_lasx_xvinsve0_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvinsve0_w::<5>(transmute(a), transmute(b)))
+        transmute(lasx_xvinsve0_w::<5>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -9300,7 +10965,10 @@ unsafe fn test_lasx_xvinsve0_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvinsve0_d::<3>(transmute(a), transmute(b)))
+        transmute(lasx_xvinsve0_d::<3>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -9318,7 +10986,7 @@ unsafe fn test_lasx_xvpickve_w() {
     );
     let r = i64x4::new(1138467779, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvpickve_w::<2>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpickve_w::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9331,7 +10999,7 @@ unsafe fn test_lasx_xvpickve_d() {
     );
     let r = i64x4::new(8402618222187512066, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvpickve_d::<0>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpickve_d::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9346,7 +11014,13 @@ unsafe fn test_lasx_xvssrlrn_b_h() {
     );
     let r = i64x4::new(3463408299017240959, 0, 35748968851799935, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrlrn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrlrn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9373,7 +11047,13 @@ unsafe fn test_lasx_xvssrlrn_h_w() {
     );
     let r = i64x4::new(422210317549567, 0, 11259106657337343, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrlrn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrlrn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9392,7 +11072,13 @@ unsafe fn test_lasx_xvssrlrn_w_d() {
     );
     let r = i64x4::new(33428474336875, 0, 9223372034707292159, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrlrn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrlrn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9407,7 +11093,13 @@ unsafe fn test_lasx_xvssrln_b_h() {
     );
     let r = i64x4::new(657383790217428863, 0, 941881790371430152, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrln_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrln_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9434,7 +11126,13 @@ unsafe fn test_lasx_xvssrln_h_w() {
     );
     let r = i64x4::new(9223103287866884105, 0, 1696871892814295669, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrln_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrln_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9453,7 +11151,13 @@ unsafe fn test_lasx_xvssrln_w_d() {
     );
     let r = i64x4::new(3937140138060021759, 0, 9223372034707292159, 0);
 
-    assert_eq!(r, transmute(lasx_xvssrln_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvssrln_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9473,7 +11177,13 @@ unsafe fn test_lasx_xvorn_v() {
         -126121887133672977,
     );
 
-    assert_eq!(r, transmute(lasx_xvorn_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvorn_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9521,7 +11231,7 @@ unsafe fn test_lasx_xvstx() {
         -4162173646616256791,
     );
 
-    lasx_xvstx(transmute(a), o.as_mut_ptr(), 0);
+    lasx_xvstx(black_box(transmute(a)), o.as_mut_ptr(), 0);
     assert_eq!(r, transmute(o));
 }
 
@@ -9535,7 +11245,7 @@ unsafe fn test_lasx_xvextl_qu_du() {
     );
     let r = i64x4::new(-5083351180651141737, 0, 4121325568380818738, 0);
 
-    assert_eq!(r, transmute(lasx_xvextl_qu_du(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvextl_qu_du(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9559,7 +11269,7 @@ unsafe fn test_lasx_xvinsgr2vr_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvinsgr2vr_w::<4>(transmute(a), -596457645))
+        transmute(lasx_xvinsgr2vr_w::<4>(black_box(transmute(a)), -596457645))
     );
 }
 
@@ -9580,7 +11290,7 @@ unsafe fn test_lasx_xvinsgr2vr_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvinsgr2vr_d::<3>(transmute(a), -1262509914))
+        transmute(lasx_xvinsgr2vr_d::<3>(black_box(transmute(a)), -1262509914))
     );
 }
 
@@ -9597,7 +11307,7 @@ unsafe fn test_lasx_xvreplve0_b() {
         3472328296227680304,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve0_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvreplve0_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9613,7 +11323,7 @@ unsafe fn test_lasx_xvreplve0_h() {
         115969459958317468,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve0_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvreplve0_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9635,7 +11345,7 @@ unsafe fn test_lasx_xvreplve0_w() {
         5341799334363128369,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve0_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvreplve0_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9653,7 +11363,7 @@ unsafe fn test_lasx_xvreplve0_d() {
         -7669512117913941619,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve0_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvreplve0_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9669,7 +11379,7 @@ unsafe fn test_lasx_xvreplve0_q() {
         -7451765666000961269,
     );
 
-    assert_eq!(r, transmute(lasx_xvreplve0_q(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvreplve0_q(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9685,7 +11395,7 @@ unsafe fn test_lasx_vext2xv_h_b() {
         24207148650070059,
     );
 
-    assert_eq!(r, transmute(lasx_vext2xv_h_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_h_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9701,7 +11411,7 @@ unsafe fn test_lasx_vext2xv_w_h() {
         -34359738358622,
     );
 
-    assert_eq!(r, transmute(lasx_vext2xv_w_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_w_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9718,7 +11428,7 @@ unsafe fn test_lasx_vext2xv_d_w() {
     );
     let r = i64x4::new(-585251458, -2113345963, -1846838006, -474453663);
 
-    assert_eq!(r, transmute(lasx_vext2xv_d_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9729,7 +11439,7 @@ unsafe fn test_lasx_vext2xv_w_b() {
     );
     let r = i64x4::new(-240518168540, -528280977282, 30064770965, -489626271740);
 
-    assert_eq!(r, transmute(lasx_vext2xv_w_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_w_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9740,7 +11450,7 @@ unsafe fn test_lasx_vext2xv_d_h() {
     );
     let r = i64x4::new(28568, -25911, 12053, -2728);
 
-    assert_eq!(r, transmute(lasx_vext2xv_d_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_d_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9751,7 +11461,7 @@ unsafe fn test_lasx_vext2xv_d_b() {
     );
     let r = i64x4::new(18, 112, -36, -67);
 
-    assert_eq!(r, transmute(lasx_vext2xv_d_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_d_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9767,7 +11477,7 @@ unsafe fn test_lasx_vext2xv_hu_bu() {
         16888898041348298,
     );
 
-    assert_eq!(r, transmute(lasx_vext2xv_hu_bu(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_hu_bu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9783,7 +11493,7 @@ unsafe fn test_lasx_vext2xv_wu_hu() {
         225172250484459,
     );
 
-    assert_eq!(r, transmute(lasx_vext2xv_wu_hu(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_wu_hu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9800,7 +11510,7 @@ unsafe fn test_lasx_vext2xv_du_wu() {
     );
     let r = i64x4::new(4027501046, 3358638690, 2495633600, 1035808674);
 
-    assert_eq!(r, transmute(lasx_vext2xv_du_wu(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_du_wu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9811,7 +11521,7 @@ unsafe fn test_lasx_vext2xv_wu_bu() {
     );
     let r = i64x4::new(987842478134, 481036337184, 266287972487, 979252543649);
 
-    assert_eq!(r, transmute(lasx_vext2xv_wu_bu(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_wu_bu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9822,7 +11532,7 @@ unsafe fn test_lasx_vext2xv_du_hu() {
     );
     let r = i64x4::new(61301, 41410, 35355, 19598);
 
-    assert_eq!(r, transmute(lasx_vext2xv_du_hu(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_du_hu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9833,7 +11543,7 @@ unsafe fn test_lasx_vext2xv_du_bu() {
     );
     let r = i64x4::new(69, 25, 36, 204);
 
-    assert_eq!(r, transmute(lasx_vext2xv_du_bu(transmute(a))));
+    assert_eq!(r, transmute(lasx_vext2xv_du_bu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9855,7 +11565,10 @@ unsafe fn test_lasx_xvpermi_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvpermi_q::<49>(transmute(a), transmute(b)))
+        transmute(lasx_xvpermi_q::<49>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -9874,7 +11587,7 @@ unsafe fn test_lasx_xvpermi_d() {
         1609032298240495217,
     );
 
-    assert_eq!(r, transmute(lasx_xvpermi_d::<137>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvpermi_d::<137>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -9900,7 +11613,13 @@ unsafe fn test_lasx_xvperm_w() {
         -3042141963630030871,
     );
 
-    assert_eq!(r, transmute(lasx_xvperm_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvperm_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9981,7 +11700,10 @@ unsafe fn test_lasx_xvpickve2gr_w() {
     );
     let r: i32 = 1367768596;
 
-    assert_eq!(r, transmute(lasx_xvpickve2gr_w::<4>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickve2gr_w::<4>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -9998,7 +11720,10 @@ unsafe fn test_lasx_xvpickve2gr_wu() {
     );
     let r: u32 = 3194994707;
 
-    assert_eq!(r, transmute(lasx_xvpickve2gr_wu::<7>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickve2gr_wu::<7>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10011,7 +11736,10 @@ unsafe fn test_lasx_xvpickve2gr_d() {
     );
     let r: i64 = 6739870851682505277;
 
-    assert_eq!(r, transmute(lasx_xvpickve2gr_d::<2>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickve2gr_d::<2>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10022,9 +11750,12 @@ unsafe fn test_lasx_xvpickve2gr_du() {
         -4272175049937479582,
         -8920910898336101981,
     );
-    let r: u64 = 9525833175373449635;
-
-    assert_eq!(r, transmute(lasx_xvpickve2gr_du::<3>(transmute(a))));
+    let r: u64 = 9525833175373449635;
+
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickve2gr_du::<3>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10043,7 +11774,13 @@ unsafe fn test_lasx_xvaddwev_q_d() {
     );
     let r = i64x4::new(-7472750192138786681, -1, -7758725841623301722, -1);
 
-    assert_eq!(r, transmute(lasx_xvaddwev_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10070,7 +11807,13 @@ unsafe fn test_lasx_xvaddwev_d_w() {
     );
     let r = i64x4::new(614980351, -1946929141, -3309402607, -619077207);
 
-    assert_eq!(r, transmute(lasx_xvaddwev_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10090,7 +11833,13 @@ unsafe fn test_lasx_xvaddwev_w_h() {
         -232787227420502,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwev_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10110,7 +11859,13 @@ unsafe fn test_lasx_xvaddwev_h_b() {
         -10414449598922739,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwev_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10129,7 +11884,13 @@ unsafe fn test_lasx_xvaddwev_q_du() {
     );
     let r = i64x4::new(4866121314102936184, 1, 898239984703082844, 1);
 
-    assert_eq!(r, transmute(lasx_xvaddwev_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10144,7 +11905,13 @@ unsafe fn test_lasx_xvaddwev_d_wu() {
     );
     let r = i64x4::new(4001409528, 3398767892, 6021892971, 4349349069);
 
-    assert_eq!(r, transmute(lasx_xvaddwev_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10164,7 +11931,13 @@ unsafe fn test_lasx_xvaddwev_w_hu() {
         376479653317006,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwev_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10184,7 +11957,13 @@ unsafe fn test_lasx_xvaddwev_h_bu() {
         68962872563859917,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwev_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10203,7 +11982,13 @@ unsafe fn test_lasx_xvsubwev_q_d() {
     );
     let r = i64x4::new(8183582659207736591, -1, 5496584216395980167, -1);
 
-    assert_eq!(r, transmute(lasx_xvsubwev_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10230,7 +12015,13 @@ unsafe fn test_lasx_xvsubwev_d_w() {
     );
     let r = i64x4::new(-1945765730, 1700549847, -1218066002, -827282692);
 
-    assert_eq!(r, transmute(lasx_xvsubwev_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10250,7 +12041,13 @@ unsafe fn test_lasx_xvsubwev_w_h() {
         217514323726817,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwev_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10270,7 +12067,13 @@ unsafe fn test_lasx_xvsubwev_h_b() {
         -5910188531122352,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwev_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10289,7 +12092,13 @@ unsafe fn test_lasx_xvsubwev_q_du() {
     );
     let r = i64x4::new(-7180841769120666233, -1, -3901807980557405007, -1);
 
-    assert_eq!(r, transmute(lasx_xvsubwev_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10304,7 +12113,13 @@ unsafe fn test_lasx_xvsubwev_d_wu() {
     );
     let r = i64x4::new(-2531041484, -1085343469, -1900376905, 1600829569);
 
-    assert_eq!(r, transmute(lasx_xvsubwev_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10324,7 +12139,13 @@ unsafe fn test_lasx_xvsubwev_w_hu() {
         -117029268872947,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwev_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10344,7 +12165,13 @@ unsafe fn test_lasx_xvsubwev_h_bu() {
         -7035942402260810,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwev_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10368,7 +12195,13 @@ unsafe fn test_lasx_xvmulwev_q_d() {
         -2723954123981949807,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10400,7 +12233,13 @@ unsafe fn test_lasx_xvmulwev_d_w() {
         904288373202150940,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10420,7 +12259,13 @@ unsafe fn test_lasx_xvmulwev_w_h() {
         -218736636965849761,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10440,7 +12285,13 @@ unsafe fn test_lasx_xvmulwev_h_b() {
         -532018857412992924,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10464,7 +12315,13 @@ unsafe fn test_lasx_xvmulwev_q_du() {
         1973424773030267173,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10484,7 +12341,13 @@ unsafe fn test_lasx_xvmulwev_d_wu() {
         312983850752328844,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10504,7 +12367,13 @@ unsafe fn test_lasx_xvmulwev_w_hu() {
         -4803214827614038190,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10524,7 +12393,13 @@ unsafe fn test_lasx_xvmulwev_h_bu() {
         4458585836433706972,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwev_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10543,7 +12418,13 @@ unsafe fn test_lasx_xvaddwod_q_d() {
     );
     let r = i64x4::new(-3813723879058076957, 0, 200103109406722390, 0);
 
-    assert_eq!(r, transmute(lasx_xvaddwod_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10570,7 +12451,13 @@ unsafe fn test_lasx_xvaddwod_d_w() {
     );
     let r = i64x4::new(3142724184, -2585235328, -785720463, 926940003);
 
-    assert_eq!(r, transmute(lasx_xvaddwod_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10590,7 +12477,13 @@ unsafe fn test_lasx_xvaddwod_w_h() {
         -148498494282599,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwod_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10610,7 +12503,13 @@ unsafe fn test_lasx_xvaddwod_h_b() {
         -9570449863999416,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwod_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10629,7 +12528,13 @@ unsafe fn test_lasx_xvaddwod_q_du() {
     );
     let r = i64x4::new(751645223963476143, 1, -1275901335613508018, 0);
 
-    assert_eq!(r, transmute(lasx_xvaddwod_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10644,7 +12549,13 @@ unsafe fn test_lasx_xvaddwod_d_wu() {
     );
     let r = i64x4::new(4757884041, 1673456593, 2162927615, 5143136401);
 
-    assert_eq!(r, transmute(lasx_xvaddwod_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10664,7 +12575,13 @@ unsafe fn test_lasx_xvaddwod_w_hu() {
         248416613500221,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwod_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10684,7 +12601,13 @@ unsafe fn test_lasx_xvaddwod_h_bu() {
         83880238860075230,
     );
 
-    assert_eq!(r, transmute(lasx_xvaddwod_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvaddwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10703,7 +12626,13 @@ unsafe fn test_lasx_xvsubwod_q_d() {
     );
     let r = i64x4::new(1764856097736252489, 0, 7683656878360999333, -1);
 
-    assert_eq!(r, transmute(lasx_xvsubwod_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10730,7 +12659,13 @@ unsafe fn test_lasx_xvsubwod_d_w() {
     );
     let r = i64x4::new(-959924898, 7572903, 2106559810, 3976421257);
 
-    assert_eq!(r, transmute(lasx_xvsubwod_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10750,7 +12685,13 @@ unsafe fn test_lasx_xvsubwod_w_h() {
         -17665200524651,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwod_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10770,7 +12711,13 @@ unsafe fn test_lasx_xvsubwod_h_b() {
         -3939721971105776,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwod_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10789,7 +12736,13 @@ unsafe fn test_lasx_xvsubwod_q_du() {
     );
     let r = i64x4::new(-6069526046627127478, -1, -1804068722113556285, -1);
 
-    assert_eq!(r, transmute(lasx_xvsubwod_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10804,7 +12757,13 @@ unsafe fn test_lasx_xvsubwod_d_wu() {
     );
     let r = i64x4::new(762157671, -772219478, -1655146846, -1402401592);
 
-    assert_eq!(r, transmute(lasx_xvsubwod_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10824,7 +12783,13 @@ unsafe fn test_lasx_xvsubwod_w_hu() {
         164866614644743,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwod_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10844,7 +12809,13 @@ unsafe fn test_lasx_xvsubwod_h_bu() {
         -280740536975491,
     );
 
-    assert_eq!(r, transmute(lasx_xvsubwod_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsubwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10868,7 +12839,13 @@ unsafe fn test_lasx_xvmulwod_q_d() {
         -113061080830775254,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10900,7 +12877,13 @@ unsafe fn test_lasx_xvmulwod_d_w() {
         -1334126209007208500,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10920,7 +12903,13 @@ unsafe fn test_lasx_xvmulwod_w_h() {
         337273560374881751,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10940,7 +12929,13 @@ unsafe fn test_lasx_xvmulwod_h_b() {
         -797714991416606612,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10964,7 +12959,13 @@ unsafe fn test_lasx_xvmulwod_q_du() {
         -6864651532066967840,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -10984,7 +12985,13 @@ unsafe fn test_lasx_xvmulwod_d_wu() {
         170736982952013264,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11004,7 +13011,13 @@ unsafe fn test_lasx_xvmulwod_w_hu() {
         648970298882764352,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11024,7 +13037,13 @@ unsafe fn test_lasx_xvmulwod_h_bu() {
         861263883582730760,
     );
 
-    assert_eq!(r, transmute(lasx_xvmulwod_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvmulwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11047,7 +13066,10 @@ unsafe fn test_lasx_xvaddwev_d_wu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwev_d_wu_w(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwev_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11070,7 +13092,10 @@ unsafe fn test_lasx_xvaddwev_w_hu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwev_w_hu_h(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwev_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11093,7 +13118,10 @@ unsafe fn test_lasx_xvaddwev_h_bu_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwev_h_bu_b(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwev_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11122,7 +13150,10 @@ unsafe fn test_lasx_xvmulwev_d_wu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwev_d_wu_w(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwev_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11145,7 +13176,10 @@ unsafe fn test_lasx_xvmulwev_w_hu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwev_w_hu_h(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwev_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11168,7 +13202,10 @@ unsafe fn test_lasx_xvmulwev_h_bu_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwev_h_bu_b(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwev_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11192,7 +13229,10 @@ unsafe fn test_lasx_xvaddwod_d_wu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwod_d_wu_w(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwod_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11215,7 +13255,10 @@ unsafe fn test_lasx_xvaddwod_w_hu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwod_w_hu_h(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwod_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11238,7 +13281,10 @@ unsafe fn test_lasx_xvaddwod_h_bu_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwod_h_bu_b(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwod_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11267,7 +13313,10 @@ unsafe fn test_lasx_xvmulwod_d_wu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwod_d_wu_w(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwod_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11290,7 +13339,10 @@ unsafe fn test_lasx_xvmulwod_w_hu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwod_w_hu_h(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwod_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11313,7 +13365,10 @@ unsafe fn test_lasx_xvmulwod_h_bu_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwod_h_bu_b(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwod_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -11333,7 +13388,13 @@ unsafe fn test_lasx_xvhaddw_q_d() {
     );
     let r = i64x4::new(7070440900316630840, -1, 4582440905924999074, 0);
 
-    assert_eq!(r, transmute(lasx_xvhaddw_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11352,7 +13413,13 @@ unsafe fn test_lasx_xvhaddw_qu_du() {
     );
     let r = i64x4::new(-6342973196760799579, 0, -6232960347008472572, 1);
 
-    assert_eq!(r, transmute(lasx_xvhaddw_qu_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhaddw_qu_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11371,7 +13438,13 @@ unsafe fn test_lasx_xvhsubw_q_d() {
     );
     let r = i64x4::new(5317548498597883842, 0, 6155348192460751216, -1);
 
-    assert_eq!(r, transmute(lasx_xvhsubw_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11390,7 +13463,13 @@ unsafe fn test_lasx_xvhsubw_qu_du() {
     );
     let r = i64x4::new(11053881530518619, 0, -1215853579082277290, -1);
 
-    assert_eq!(r, transmute(lasx_xvhsubw_qu_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvhsubw_qu_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -11422,7 +13501,11 @@ unsafe fn test_lasx_xvmaddwev_q_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11463,7 +13546,11 @@ unsafe fn test_lasx_xvmaddwev_d_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11496,7 +13583,11 @@ unsafe fn test_lasx_xvmaddwev_w_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11523,7 +13614,11 @@ unsafe fn test_lasx_xvmaddwev_h_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11557,9 +13652,9 @@ unsafe fn test_lasx_xvmaddwev_q_du() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_q_du(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11590,9 +13685,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_d_wu(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11621,9 +13716,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_w_hu(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11652,9 +13747,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_h_bu(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11688,7 +13783,11 @@ unsafe fn test_lasx_xvmaddwod_q_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11729,7 +13828,11 @@ unsafe fn test_lasx_xvmaddwod_d_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11762,7 +13865,11 @@ unsafe fn test_lasx_xvmaddwod_w_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11789,7 +13896,11 @@ unsafe fn test_lasx_xvmaddwod_h_b() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lasx_xvmaddwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -11823,9 +13934,9 @@ unsafe fn test_lasx_xvmaddwod_q_du() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_q_du(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11856,9 +13967,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_d_wu(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11887,9 +13998,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_w_hu(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11918,9 +14029,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_h_bu(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11955,9 +14066,9 @@ unsafe fn test_lasx_xvmaddwev_q_du_d() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_q_du_d(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -11994,9 +14105,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu_w() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_d_wu_w(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12031,9 +14142,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu_h() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_w_hu_h(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12062,9 +14173,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu_b() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwev_h_bu_b(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12099,9 +14210,9 @@ unsafe fn test_lasx_xvmaddwod_q_du_d() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_q_du_d(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12138,9 +14249,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu_w() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_d_wu_w(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12169,9 +14280,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu_h() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_w_hu_h(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12200,9 +14311,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu_b() {
     assert_eq!(
         r,
         transmute(lasx_xvmaddwod_h_bu_b(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -12224,7 +14335,13 @@ unsafe fn test_lasx_xvrotr_b() {
         5842271601646106402,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrotr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -12244,7 +14361,13 @@ unsafe fn test_lasx_xvrotr_h() {
         8109266518466894464,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrotr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -12264,7 +14387,13 @@ unsafe fn test_lasx_xvrotr_w() {
         8567937817891640092,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrotr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -12288,7 +14417,13 @@ unsafe fn test_lasx_xvrotr_d() {
         4254025119287920211,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvrotr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -12312,7 +14447,13 @@ unsafe fn test_lasx_xvadd_q() {
         1706530784161666452,
     );
 
-    assert_eq!(r, transmute(lasx_xvadd_q(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvadd_q(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -12336,7 +14477,13 @@ unsafe fn test_lasx_xvsub_q() {
         1242748497994781383,
     );
 
-    assert_eq!(r, transmute(lasx_xvsub_q(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvsub_q(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -12357,7 +14504,10 @@ unsafe fn test_lasx_xvaddwev_q_du_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwev_q_du_d(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwev_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12379,7 +14529,10 @@ unsafe fn test_lasx_xvaddwod_q_du_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvaddwod_q_du_d(transmute(a), transmute(b)))
+        transmute(lasx_xvaddwod_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12406,7 +14559,10 @@ unsafe fn test_lasx_xvmulwev_q_du_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwev_q_du_d(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwev_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12433,7 +14589,10 @@ unsafe fn test_lasx_xvmulwod_q_du_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvmulwod_q_du_d(transmute(a), transmute(b)))
+        transmute(lasx_xvmulwod_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12445,7 +14604,7 @@ unsafe fn test_lasx_xvmskgez_b() {
     );
     let r = i64x4::new(13289, 0, 4927, 0);
 
-    assert_eq!(r, transmute(lasx_xvmskgez_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmskgez_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12456,7 +14615,7 @@ unsafe fn test_lasx_xvmsknz_b() {
     );
     let r = i64x4::new(65535, 0, 65535, 0);
 
-    assert_eq!(r, transmute(lasx_xvmsknz_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvmsknz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12472,7 +14631,7 @@ unsafe fn test_lasx_xvexth_h_b() {
         -1689051729887256,
     );
 
-    assert_eq!(r, transmute(lasx_xvexth_h_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_h_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12488,7 +14647,7 @@ unsafe fn test_lasx_xvexth_w_h() {
         -117171002791439,
     );
 
-    assert_eq!(r, transmute(lasx_xvexth_w_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_w_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12505,7 +14664,7 @@ unsafe fn test_lasx_xvexth_d_w() {
     );
     let r = i64x4::new(78514216, -1063299454, -1487536177, 1875317589);
 
-    assert_eq!(r, transmute(lasx_xvexth_d_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12518,7 +14677,7 @@ unsafe fn test_lasx_xvexth_q_d() {
     );
     let r = i64x4::new(5196480214883180720, 0, 7776492634988202392, 0);
 
-    assert_eq!(r, transmute(lasx_xvexth_q_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_q_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12534,7 +14693,7 @@ unsafe fn test_lasx_xvexth_hu_bu() {
         11259067788754993,
     );
 
-    assert_eq!(r, transmute(lasx_xvexth_hu_bu(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_hu_bu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12550,7 +14709,7 @@ unsafe fn test_lasx_xvexth_wu_hu() {
         211376815493177,
     );
 
-    assert_eq!(r, transmute(lasx_xvexth_wu_hu(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_wu_hu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12561,7 +14720,7 @@ unsafe fn test_lasx_xvexth_du_wu() {
     );
     let r = i64x4::new(3486710391, 717721410, 1954296323, 1406265475);
 
-    assert_eq!(r, transmute(lasx_xvexth_du_wu(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_du_wu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12574,7 +14733,7 @@ unsafe fn test_lasx_xvexth_qu_du() {
     );
     let r = i64x4::new(6305760528044738869, 0, 3857202168052068182, 0);
 
-    assert_eq!(r, transmute(lasx_xvexth_qu_du(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvexth_qu_du(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12590,7 +14749,7 @@ unsafe fn test_lasx_xvrotri_b() {
         -3500418816657076903,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotri_b::<4>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvrotri_b::<4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12606,7 +14765,7 @@ unsafe fn test_lasx_xvrotri_h() {
         4779464405959485451,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotri_h::<15>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvrotri_h::<15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12628,7 +14787,7 @@ unsafe fn test_lasx_xvrotri_w() {
         -1679179889808014898,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotri_w::<11>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvrotri_w::<11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12646,7 +14805,7 @@ unsafe fn test_lasx_xvrotri_d() {
         -7958311692822812825,
     );
 
-    assert_eq!(r, transmute(lasx_xvrotri_d::<16>(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvrotri_d::<16>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12659,7 +14818,7 @@ unsafe fn test_lasx_xvextl_q_d() {
     );
     let r = i64x4::new(-4167783494125842132, -1, 7476993593286219399, 0);
 
-    assert_eq!(r, transmute(lasx_xvextl_q_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xvextl_q_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -12681,7 +14840,10 @@ unsafe fn test_lasx_xvsrlni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlni_b_h::<4>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlni_b_h::<4>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12704,7 +14866,10 @@ unsafe fn test_lasx_xvsrlni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlni_h_w::<16>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlni_h_w::<16>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12739,7 +14904,10 @@ unsafe fn test_lasx_xvsrlni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlni_w_d::<26>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlni_w_d::<26>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12761,7 +14929,10 @@ unsafe fn test_lasx_xvsrlni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlni_d_q::<102>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlni_d_q::<102>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12784,7 +14955,10 @@ unsafe fn test_lasx_xvsrlrni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlrni_b_h::<8>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlrni_b_h::<8>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12807,7 +14981,10 @@ unsafe fn test_lasx_xvsrlrni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlrni_h_w::<5>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlrni_h_w::<5>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12842,7 +15019,10 @@ unsafe fn test_lasx_xvsrlrni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlrni_w_d::<43>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlrni_w_d::<43>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12864,7 +15044,10 @@ unsafe fn test_lasx_xvsrlrni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrlrni_d_q::<126>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrlrni_d_q::<126>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12887,7 +15070,10 @@ unsafe fn test_lasx_xvssrlni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_b_h::<4>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_b_h::<4>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12905,7 +15091,10 @@ unsafe fn test_lasx_xvssrlni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_h_w::<31>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_h_w::<31>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12940,7 +15129,10 @@ unsafe fn test_lasx_xvssrlni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_w_d::<14>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_w_d::<14>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12967,7 +15159,10 @@ unsafe fn test_lasx_xvssrlni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_d_q::<35>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_d_q::<35>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -12990,7 +15185,10 @@ unsafe fn test_lasx_xvssrlni_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_bu_h::<11>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_bu_h::<11>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13008,7 +15206,10 @@ unsafe fn test_lasx_xvssrlni_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_hu_w::<31>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_hu_w::<31>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13032,7 +15233,10 @@ unsafe fn test_lasx_xvssrlni_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_wu_d::<24>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_wu_d::<24>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13054,7 +15258,10 @@ unsafe fn test_lasx_xvssrlni_du_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlni_du_q::<109>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlni_du_q::<109>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13077,7 +15284,10 @@ unsafe fn test_lasx_xvssrlrni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_b_h::<7>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_b_h::<7>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13100,7 +15310,10 @@ unsafe fn test_lasx_xvssrlrni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_h_w::<11>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_h_w::<11>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13135,7 +15348,10 @@ unsafe fn test_lasx_xvssrlrni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_w_d::<27>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_w_d::<27>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13157,7 +15373,10 @@ unsafe fn test_lasx_xvssrlrni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_d_q::<94>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_d_q::<94>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13175,7 +15394,10 @@ unsafe fn test_lasx_xvssrlrni_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_bu_h::<4>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_bu_h::<4>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13198,7 +15420,10 @@ unsafe fn test_lasx_xvssrlrni_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_hu_w::<16>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_hu_w::<16>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13227,7 +15452,10 @@ unsafe fn test_lasx_xvssrlrni_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_wu_d::<50>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_wu_d::<50>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13249,7 +15477,10 @@ unsafe fn test_lasx_xvssrlrni_du_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrlrni_du_q::<53>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrlrni_du_q::<53>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13272,7 +15503,10 @@ unsafe fn test_lasx_xvsrani_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrani_b_h::<8>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrani_b_h::<8>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13295,7 +15529,10 @@ unsafe fn test_lasx_xvsrani_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrani_h_w::<0>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrani_h_w::<0>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13330,7 +15567,10 @@ unsafe fn test_lasx_xvsrani_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrani_w_d::<28>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrani_w_d::<28>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13357,7 +15597,10 @@ unsafe fn test_lasx_xvsrani_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrani_d_q::<66>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrani_d_q::<66>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13380,7 +15623,10 @@ unsafe fn test_lasx_xvsrarni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrarni_b_h::<4>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrarni_b_h::<4>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13403,7 +15649,10 @@ unsafe fn test_lasx_xvsrarni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrarni_h_w::<9>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrarni_h_w::<9>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13427,7 +15676,10 @@ unsafe fn test_lasx_xvsrarni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrarni_w_d::<63>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrarni_w_d::<63>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13449,7 +15701,10 @@ unsafe fn test_lasx_xvsrarni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvsrarni_d_q::<102>(transmute(a), transmute(b)))
+        transmute(lasx_xvsrarni_d_q::<102>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13472,7 +15727,10 @@ unsafe fn test_lasx_xvssrani_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_b_h::<5>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_b_h::<5>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13495,7 +15753,10 @@ unsafe fn test_lasx_xvssrani_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_h_w::<0>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_h_w::<0>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13530,7 +15791,10 @@ unsafe fn test_lasx_xvssrani_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_w_d::<45>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_w_d::<45>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13557,7 +15821,10 @@ unsafe fn test_lasx_xvssrani_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_d_q::<73>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_d_q::<73>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13575,7 +15842,10 @@ unsafe fn test_lasx_xvssrani_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_bu_h::<12>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_bu_h::<12>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13593,7 +15863,10 @@ unsafe fn test_lasx_xvssrani_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_hu_w::<9>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_hu_w::<9>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13617,7 +15890,10 @@ unsafe fn test_lasx_xvssrani_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_wu_d::<42>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_wu_d::<42>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13639,7 +15915,10 @@ unsafe fn test_lasx_xvssrani_du_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrani_du_q::<115>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrani_du_q::<115>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13662,7 +15941,10 @@ unsafe fn test_lasx_xvssrarni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_b_h::<6>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_b_h::<6>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13685,7 +15967,10 @@ unsafe fn test_lasx_xvssrarni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_h_w::<25>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_h_w::<25>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13715,7 +16000,10 @@ unsafe fn test_lasx_xvssrarni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_w_d::<61>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_w_d::<61>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13737,7 +16025,10 @@ unsafe fn test_lasx_xvssrarni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_d_q::<123>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_d_q::<123>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13760,7 +16051,10 @@ unsafe fn test_lasx_xvssrarni_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_bu_h::<10>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_bu_h::<10>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13778,7 +16072,10 @@ unsafe fn test_lasx_xvssrarni_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_hu_w::<30>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_hu_w::<30>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13802,7 +16099,10 @@ unsafe fn test_lasx_xvssrarni_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_wu_d::<61>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_wu_d::<61>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13824,7 +16124,10 @@ unsafe fn test_lasx_xvssrarni_du_q() {
 
     assert_eq!(
         r,
-        transmute(lasx_xvssrarni_du_q::<15>(transmute(a), transmute(b)))
+        transmute(lasx_xvssrarni_du_q::<15>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -13836,7 +16139,7 @@ unsafe fn test_lasx_xbnz_b() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lasx_xbnz_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbnz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13849,7 +16152,7 @@ unsafe fn test_lasx_xbnz_d() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lasx_xbnz_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbnz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13860,7 +16163,7 @@ unsafe fn test_lasx_xbnz_h() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lasx_xbnz_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbnz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13871,7 +16174,7 @@ unsafe fn test_lasx_xbnz_v() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lasx_xbnz_v(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbnz_v(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13882,7 +16185,7 @@ unsafe fn test_lasx_xbnz_w() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lasx_xbnz_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbnz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13893,7 +16196,7 @@ unsafe fn test_lasx_xbz_b() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lasx_xbz_b(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13906,7 +16209,7 @@ unsafe fn test_lasx_xbz_d() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lasx_xbz_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13917,7 +16220,7 @@ unsafe fn test_lasx_xbz_h() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lasx_xbz_h(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13928,7 +16231,7 @@ unsafe fn test_lasx_xbz_v() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lasx_xbz_v(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbz_v(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13939,7 +16242,7 @@ unsafe fn test_lasx_xbz_w() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lasx_xbz_w(transmute(a))));
+    assert_eq!(r, transmute(lasx_xbz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -13958,7 +16261,13 @@ unsafe fn test_lasx_xvfcmp_caf_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_caf_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_caf_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -13973,7 +16282,13 @@ unsafe fn test_lasx_xvfcmp_caf_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_caf_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_caf_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -13992,7 +16307,13 @@ unsafe fn test_lasx_xvfcmp_ceq_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_ceq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_ceq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14007,7 +16328,13 @@ unsafe fn test_lasx_xvfcmp_ceq_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_ceq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_ceq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14026,7 +16353,13 @@ unsafe fn test_lasx_xvfcmp_cle_d() {
     );
     let r = i64x4::new(-1, -1, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cle_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cle_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14041,7 +16374,13 @@ unsafe fn test_lasx_xvfcmp_cle_s() {
     );
     let r = i64x4::new(0, -1, -1, -4294967296);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cle_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cle_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14060,7 +16399,13 @@ unsafe fn test_lasx_xvfcmp_clt_d() {
     );
     let r = i64x4::new(0, -1, 0, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_clt_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_clt_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14075,7 +16420,13 @@ unsafe fn test_lasx_xvfcmp_clt_s() {
     );
     let r = i64x4::new(-1, 4294967295, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_clt_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_clt_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14094,7 +16445,13 @@ unsafe fn test_lasx_xvfcmp_cne_d() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cne_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cne_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14109,7 +16466,13 @@ unsafe fn test_lasx_xvfcmp_cne_s() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cne_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cne_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14128,7 +16491,13 @@ unsafe fn test_lasx_xvfcmp_cor_d() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cor_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cor_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14143,7 +16512,13 @@ unsafe fn test_lasx_xvfcmp_cor_s() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cor_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cor_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14162,7 +16537,13 @@ unsafe fn test_lasx_xvfcmp_cueq_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cueq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cueq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14177,7 +16558,13 @@ unsafe fn test_lasx_xvfcmp_cueq_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cueq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cueq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14196,7 +16583,13 @@ unsafe fn test_lasx_xvfcmp_cule_d() {
     );
     let r = i64x4::new(0, -1, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cule_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cule_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14211,7 +16604,13 @@ unsafe fn test_lasx_xvfcmp_cule_s() {
     );
     let r = i64x4::new(-4294967296, 4294967295, 4294967295, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cule_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cule_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14230,7 +16629,13 @@ unsafe fn test_lasx_xvfcmp_cult_d() {
     );
     let r = i64x4::new(0, -1, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cult_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cult_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14245,7 +16650,13 @@ unsafe fn test_lasx_xvfcmp_cult_s() {
     );
     let r = i64x4::new(-1, 0, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cult_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cult_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14264,7 +16675,13 @@ unsafe fn test_lasx_xvfcmp_cun_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cun_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cun_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14283,7 +16700,13 @@ unsafe fn test_lasx_xvfcmp_cune_d() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cune_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cune_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14298,7 +16721,13 @@ unsafe fn test_lasx_xvfcmp_cune_s() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cune_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cune_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14313,7 +16742,13 @@ unsafe fn test_lasx_xvfcmp_cun_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_cun_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_cun_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14332,7 +16767,13 @@ unsafe fn test_lasx_xvfcmp_saf_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_saf_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_saf_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14347,7 +16788,13 @@ unsafe fn test_lasx_xvfcmp_saf_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_saf_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_saf_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14366,7 +16813,13 @@ unsafe fn test_lasx_xvfcmp_seq_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_seq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_seq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14381,7 +16834,13 @@ unsafe fn test_lasx_xvfcmp_seq_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_seq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_seq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14400,7 +16859,13 @@ unsafe fn test_lasx_xvfcmp_sle_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sle_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sle_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14415,7 +16880,13 @@ unsafe fn test_lasx_xvfcmp_sle_s() {
     );
     let r = i64x4::new(0, 4294967295, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sle_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sle_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14434,7 +16905,13 @@ unsafe fn test_lasx_xvfcmp_slt_d() {
     );
     let r = i64x4::new(0, -1, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_slt_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_slt_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14449,7 +16926,13 @@ unsafe fn test_lasx_xvfcmp_slt_s() {
     );
     let r = i64x4::new(0, -4294967296, 4294967295, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_slt_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_slt_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14468,7 +16951,13 @@ unsafe fn test_lasx_xvfcmp_sne_d() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sne_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sne_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14483,7 +16972,13 @@ unsafe fn test_lasx_xvfcmp_sne_s() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sne_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sne_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14502,7 +16997,13 @@ unsafe fn test_lasx_xvfcmp_sor_d() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sor_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sor_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14517,7 +17018,13 @@ unsafe fn test_lasx_xvfcmp_sor_s() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sor_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sor_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14536,7 +17043,13 @@ unsafe fn test_lasx_xvfcmp_sueq_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sueq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sueq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14551,7 +17064,13 @@ unsafe fn test_lasx_xvfcmp_sueq_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sueq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sueq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14570,7 +17089,13 @@ unsafe fn test_lasx_xvfcmp_sule_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sule_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sule_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14585,7 +17110,13 @@ unsafe fn test_lasx_xvfcmp_sule_s() {
     );
     let r = i64x4::new(0, 4294967295, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sule_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sule_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14604,7 +17135,13 @@ unsafe fn test_lasx_xvfcmp_sult_d() {
     );
     let r = i64x4::new(0, -1, 0, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sult_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sult_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14619,7 +17156,13 @@ unsafe fn test_lasx_xvfcmp_sult_s() {
     );
     let r = i64x4::new(-1, 4294967295, -1, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sult_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sult_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14638,7 +17181,13 @@ unsafe fn test_lasx_xvfcmp_sun_d() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sun_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sun_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14657,7 +17206,13 @@ unsafe fn test_lasx_xvfcmp_sune_d() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sune_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sune_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14672,7 +17227,13 @@ unsafe fn test_lasx_xvfcmp_sune_s() {
     );
     let r = i64x4::new(-1, -1, -1, -1);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sune_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sune_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14687,7 +17248,13 @@ unsafe fn test_lasx_xvfcmp_sun_s() {
     );
     let r = i64x4::new(0, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvfcmp_sun_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvfcmp_sun_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14700,7 +17267,10 @@ unsafe fn test_lasx_xvpickve_d_f() {
     );
     let r = i64x4::new(4605596490350167974, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvpickve_d_f::<1>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickve_d_f::<1>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14711,7 +17281,10 @@ unsafe fn test_lasx_xvpickve_w_f() {
     );
     let r = i64x4::new(1040565756, 0, 0, 0);
 
-    assert_eq!(r, transmute(lasx_xvpickve_w_f::<1>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lasx_xvpickve_w_f::<1>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14764,7 +17337,7 @@ unsafe fn test_lasx_cast_128_s() {
 
     assert_eq!(
         r.as_array()[0..2],
-        transmute::<_, i64x4>(lasx_cast_128_s(transmute(a))).as_array()[0..2]
+        transmute::<_, i64x4>(lasx_cast_128_s(black_box(transmute(a)))).as_array()[0..2]
     );
 }
 
@@ -14780,7 +17353,7 @@ unsafe fn test_lasx_cast_128_d() {
 
     assert_eq!(
         r.as_array()[0..2],
-        transmute::<_, i64x4>(lasx_cast_128_d(transmute(a))).as_array()[0..2]
+        transmute::<_, i64x4>(lasx_cast_128_d(black_box(transmute(a)))).as_array()[0..2]
     );
 }
 
@@ -14796,7 +17369,7 @@ unsafe fn test_lasx_cast_128() {
 
     assert_eq!(
         r.as_array()[0..2],
-        transmute::<_, i64x4>(lasx_cast_128(transmute(a))).as_array()[0..2]
+        transmute::<_, i64x4>(lasx_cast_128(black_box(transmute(a)))).as_array()[0..2]
     );
 }
 
@@ -14811,7 +17384,13 @@ unsafe fn test_lasx_concat_128_s() {
         4410275898954698048,
     );
 
-    assert_eq!(r, transmute(lasx_concat_128_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_concat_128_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14825,7 +17404,13 @@ unsafe fn test_lasx_concat_128_d() {
         4600308396523102002,
     );
 
-    assert_eq!(r, transmute(lasx_concat_128_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_concat_128_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14839,7 +17424,13 @@ unsafe fn test_lasx_concat_128() {
         7751541408133090748,
     );
 
-    assert_eq!(r, transmute(lasx_concat_128(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_concat_128(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -14850,7 +17441,7 @@ unsafe fn test_lasx_extract_128_lo_s() {
     );
     let r = i64x2::new(4524431379435545192, 4532741359493293580);
 
-    assert_eq!(r, transmute(lasx_extract_128_lo_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_extract_128_lo_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -14861,7 +17452,7 @@ unsafe fn test_lasx_extract_128_hi_s() {
     );
     let r = i64x2::new(4572785117706267614, 4549394373627784333);
 
-    assert_eq!(r, transmute(lasx_extract_128_hi_s(transmute(a))));
+    assert_eq!(r, transmute(lasx_extract_128_hi_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -14874,7 +17465,7 @@ unsafe fn test_lasx_extract_128_lo_d() {
     );
     let r = i64x2::new(4606487981487128637, 4592443779247846248);
 
-    assert_eq!(r, transmute(lasx_extract_128_lo_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_extract_128_lo_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -14887,7 +17478,7 @@ unsafe fn test_lasx_extract_128_hi_d() {
     );
     let r = i64x2::new(4603881047625519227, 4604218419306666352);
 
-    assert_eq!(r, transmute(lasx_extract_128_hi_d(transmute(a))));
+    assert_eq!(r, transmute(lasx_extract_128_hi_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -14900,7 +17491,7 @@ unsafe fn test_lasx_extract_128_lo() {
     );
     let r = i64x2::new(1690990426210778543, -1056924033489771427);
 
-    assert_eq!(r, transmute(lasx_extract_128_lo(transmute(a))));
+    assert_eq!(r, transmute(lasx_extract_128_lo(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -14913,7 +17504,7 @@ unsafe fn test_lasx_extract_128_hi() {
     );
     let r = i64x2::new(-1903780563362068813, -7449796170151383489);
 
-    assert_eq!(r, transmute(lasx_extract_128_hi(transmute(a))));
+    assert_eq!(r, transmute(lasx_extract_128_hi(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lasx")]
@@ -14932,7 +17523,10 @@ unsafe fn test_lasx_insert_128_lo_s() {
 
     assert_eq!(
         r,
-        transmute(lasx_insert_128_lo_s(transmute(a), transmute(b)))
+        transmute(lasx_insert_128_lo_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -14952,7 +17546,10 @@ unsafe fn test_lasx_insert_128_hi_s() {
 
     assert_eq!(
         r,
-        transmute(lasx_insert_128_hi_s(transmute(a), transmute(b)))
+        transmute(lasx_insert_128_hi_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -14974,7 +17571,10 @@ unsafe fn test_lasx_insert_128_lo_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_insert_128_lo_d(transmute(a), transmute(b)))
+        transmute(lasx_insert_128_lo_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -14996,7 +17596,10 @@ unsafe fn test_lasx_insert_128_hi_d() {
 
     assert_eq!(
         r,
-        transmute(lasx_insert_128_hi_d(transmute(a), transmute(b)))
+        transmute(lasx_insert_128_hi_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -15016,7 +17619,13 @@ unsafe fn test_lasx_insert_128_lo() {
         -4396186135186039276,
     );
 
-    assert_eq!(r, transmute(lasx_insert_128_lo(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_insert_128_lo(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lasx")]
@@ -15035,5 +17644,11 @@ unsafe fn test_lasx_insert_128_hi() {
         -7502655081590988207,
     );
 
-    assert_eq!(r, transmute(lasx_insert_128_hi(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lasx_insert_128_hi(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
diff --git a/crates/core_arch/src/loongarch64/lsx/tests.rs b/crates/core_arch/src/loongarch64/lsx/tests.rs
index 5670bd4378..748e2b597a 100644
--- a/crates/core_arch/src/loongarch64/lsx/tests.rs
+++ b/crates/core_arch/src/loongarch64/lsx/tests.rs
@@ -5,6 +5,7 @@ use crate::{
     core_arch::{loongarch64::*, simd::*},
     mem::transmute,
 };
+use std::hint::black_box;
 use stdarch_test::simd_test;
 
 #[simd_test(enable = "lsx")]
@@ -17,7 +18,10 @@ unsafe fn test_lsx_vsll_b() {
     );
     let r = i64x2::new(70990221811840, -3257029622096690968);
 
-    assert_eq!(r, transmute(lsx_vsll_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsll_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -26,7 +30,10 @@ unsafe fn test_lsx_vsll_h() {
     let b = i16x8::new(-10317, -20778, -9962, -8975, 25298, 12929, -13803, -18669);
     let r = i64x2::new(-5063658964307128392, -3539825456407336052);
 
-    assert_eq!(r, transmute(lsx_vsll_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsll_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -35,7 +42,10 @@ unsafe fn test_lsx_vsll_w() {
     let b = i32x4::new(82237029, -819106294, -96895338, -456101700);
     let r = i64x2::new(-7163824029380778240, 2305843009528266752);
 
-    assert_eq!(r, transmute(lsx_vsll_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsll_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -44,7 +54,10 @@ unsafe fn test_lsx_vsll_d() {
     let b = i64x2::new(8592669249977019309, -1379694176202045825);
     let r = i64x2::new(1790743801833193472, 0);
 
-    assert_eq!(r, transmute(lsx_vsll_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsll_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -54,7 +67,7 @@ unsafe fn test_lsx_vslli_b() {
     );
     let r = i64x2::new(-2780807324588213414, -3708578564830607166);
 
-    assert_eq!(r, transmute(lsx_vslli_b::<0>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslli_b::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -62,7 +75,7 @@ unsafe fn test_lsx_vslli_h() {
     let a = i16x8::new(18469, -14840, 23655, -3474, 7467, 2798, -15418, 26847);
     let r = i64x2::new(-7241759886206301888, 4017476402818337472);
 
-    assert_eq!(r, transmute(lsx_vslli_h::<6>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslli_h::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -70,7 +83,7 @@ unsafe fn test_lsx_vslli_w() {
     let a = i32x4::new(20701902, -1777432355, 6349179, 1747667894);
     let r = i64x2::new(4189319625752393728, -5967594959501136896);
 
-    assert_eq!(r, transmute(lsx_vslli_w::<10>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslli_w::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -78,7 +91,7 @@ unsafe fn test_lsx_vslli_d() {
     let a = i64x2::new(-5896889635782282086, -8807609320972692839);
     let r = i64x2::new(-4233027607937510592, -5142337165482896608);
 
-    assert_eq!(r, transmute(lsx_vslli_d::<5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslli_d::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -91,7 +104,10 @@ unsafe fn test_lsx_vsra_b() {
     );
     let r = i64x2::new(-1080315035391229440, 720022881735668484);
 
-    assert_eq!(r, transmute(lsx_vsra_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsra_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -100,7 +116,10 @@ unsafe fn test_lsx_vsra_h() {
     let b = i16x8::new(14017, 3796, 23987, -27244, -13363, 21333, -10262, 23633);
     let r = i64x2::new(164116464290576704, -1935703552267190275);
 
-    assert_eq!(r, transmute(lsx_vsra_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsra_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -109,7 +128,10 @@ unsafe fn test_lsx_vsra_w() {
     let b = i32x4::new(-670772992, 2044335288, -1224858031, 520588790);
     let r = i64x2::new(-210763200496, 1619202657181);
 
-    assert_eq!(r, transmute(lsx_vsra_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsra_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -118,7 +140,10 @@ unsafe fn test_lsx_vsra_d() {
     let b = i64x2::new(4251079558060308329, 4657697142994416829);
     let r = i64x2::new(-623956, 3);
 
-    assert_eq!(r, transmute(lsx_vsra_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsra_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -128,7 +153,7 @@ unsafe fn test_lsx_vsrai_b() {
     );
     let r = i64x2::new(-2018743940785760257, -2093355901512246518);
 
-    assert_eq!(r, transmute(lsx_vsrai_b::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrai_b::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -136,7 +161,7 @@ unsafe fn test_lsx_vsrai_h() {
     let a = i16x8::new(-22502, -7299, 19084, -21578, -28082, 20851, 23456, 15524);
     let r = i64x2::new(-1688828385492998, 844446405361657);
 
-    assert_eq!(r, transmute(lsx_vsrai_h::<12>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrai_h::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -144,7 +169,7 @@ unsafe fn test_lsx_vsrai_w() {
     let a = i32x4::new(743537539, 1831641900, -1639033567, -984629971);
     let r = i64x2::new(30008936499988, -16131897170029);
 
-    assert_eq!(r, transmute(lsx_vsrai_w::<18>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrai_w::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -152,7 +177,7 @@ unsafe fn test_lsx_vsrai_d() {
     let a = i64x2::new(-8375997486414293750, 1714581574012370587);
     let r = i64x2::new(-476121, 97462);
 
-    assert_eq!(r, transmute(lsx_vsrai_d::<44>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrai_d::<44>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -165,7 +190,13 @@ unsafe fn test_lsx_vsrar_b() {
     );
     let r = i64x2::new(139917463134404866, 143840305941130491);
 
-    assert_eq!(r, transmute(lsx_vsrar_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrar_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -174,7 +205,13 @@ unsafe fn test_lsx_vsrar_h() {
     let b = i16x8::new(-26450, 2176, 31587, 2222, 13726, 30172, 1067, -14273);
     let r = i64x2::new(-287115463426050, 42950131714);
 
-    assert_eq!(r, transmute(lsx_vsrar_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrar_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -183,7 +220,13 @@ unsafe fn test_lsx_vsrar_w() {
     let b = i32x4::new(-1532076758, 940127488, 1781366421, 1497262222);
     let r = i64x2::new(7179867468326627830, 560544771735247);
 
-    assert_eq!(r, transmute(lsx_vsrar_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrar_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -192,7 +235,13 @@ unsafe fn test_lsx_vsrar_d() {
     let b = i64x2::new(3571440266112779495, -725943254065719378);
     let r = i64x2::new(-890187, -17811);
 
-    assert_eq!(r, transmute(lsx_vsrar_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrar_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -202,7 +251,7 @@ unsafe fn test_lsx_vsrari_b() {
     );
     let r = i64x2::new(867219992078845182, -503291487652282122);
 
-    assert_eq!(r, transmute(lsx_vsrari_b::<3>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrari_b::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -210,7 +259,7 @@ unsafe fn test_lsx_vsrari_h() {
     let a = i16x8::new(29939, -1699, 12357, 30805, -30883, 31936, 15701, -11818);
     let r = i64x2::new(4222154715365391, -1688815499411471);
 
-    assert_eq!(r, transmute(lsx_vsrari_h::<11>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrari_h::<11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -218,7 +267,7 @@ unsafe fn test_lsx_vsrari_w() {
     let a = i32x4::new(588196178, -1058764534, 1325397591, 1169671026);
     let r = i64x2::new(-4294967295, 4294967297);
 
-    assert_eq!(r, transmute(lsx_vsrari_w::<30>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrari_w::<30>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -226,7 +275,7 @@ unsafe fn test_lsx_vsrari_d() {
     let a = i64x2::new(-2795326946470057100, 6746045132217841338);
     let r = i64x2::new(-174707934154378569, 421627820763615084);
 
-    assert_eq!(r, transmute(lsx_vsrari_d::<4>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrari_d::<4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -239,7 +288,10 @@ unsafe fn test_lsx_vsrl_b() {
     );
     let r = i64x2::new(1300161376517358116, 72917012339034650);
 
-    assert_eq!(r, transmute(lsx_vsrl_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrl_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -248,7 +300,10 @@ unsafe fn test_lsx_vsrl_h() {
     let b = i16x8::new(16605, -13577, -26644, -17739, 11000, -29283, -15971, 20169);
     let r = i64x2::new(468374382728249347, 20829178341621860);
 
-    assert_eq!(r, transmute(lsx_vsrl_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrl_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -257,7 +312,10 @@ unsafe fn test_lsx_vsrl_w() {
     let b = i32x4::new(1777885221, -1725401090, 1849724045, -1051851102);
     let r = i64x2::new(12953227061, 1599606693325790121);
 
-    assert_eq!(r, transmute(lsx_vsrl_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrl_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -266,7 +324,10 @@ unsafe fn test_lsx_vsrl_d() {
     let b = i64x2::new(-7903128394835365398, 7601347629202818185);
     let r = i64x2::new(649044, 1572171616025062);
 
-    assert_eq!(r, transmute(lsx_vsrl_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrl_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -276,7 +337,7 @@ unsafe fn test_lsx_vsrli_b() {
     );
     let r = i64x2::new(1952909805632365845, 3971107439766933248);
 
-    assert_eq!(r, transmute(lsx_vsrli_b::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrli_b::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -284,7 +345,7 @@ unsafe fn test_lsx_vsrli_h() {
     let a = i16x8::new(29545, 354, 27695, 20915, -32766, -24491, 10641, 20310);
     let r = i64x2::new(11259230996660281, 10977609996304448);
 
-    assert_eq!(r, transmute(lsx_vsrli_h::<9>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrli_h::<9>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -292,7 +353,7 @@ unsafe fn test_lsx_vsrli_w() {
     let a = i32x4::new(627703601, 922874410, -234412645, -1216101872);
     let r = i64x2::new(3870813506329215, 12913695352717769);
 
-    assert_eq!(r, transmute(lsx_vsrli_w::<10>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrli_w::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -300,7 +361,7 @@ unsafe fn test_lsx_vsrli_d() {
     let a = i64x2::new(1407685950714554203, -6076144426076800688);
     let r = i64x2::new(9, 85);
 
-    assert_eq!(r, transmute(lsx_vsrli_d::<57>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrli_d::<57>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -313,7 +374,13 @@ unsafe fn test_lsx_vsrlr_b() {
     );
     let r = i64x2::new(3317746744565237249, 144420860932066826);
 
-    assert_eq!(r, transmute(lsx_vsrlr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -322,7 +389,13 @@ unsafe fn test_lsx_vsrlr_h() {
     let b = i16x8::new(19500, -26403, -1282, 12290, -18989, 25105, -24347, 6707);
     let r = i64x2::new(1991716935204929539, 311033695131730530);
 
-    assert_eq!(r, transmute(lsx_vsrlr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -331,7 +404,13 @@ unsafe fn test_lsx_vsrlr_w() {
     let b = i32x4::new(1830015593, -1452673200, 962662328, -252736055);
     let r = i64x2::new(7864089021084, 20473000998469780);
 
-    assert_eq!(r, transmute(lsx_vsrlr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -340,7 +419,13 @@ unsafe fn test_lsx_vsrlr_d() {
     let b = i64x2::new(-1543621369665313706, 8544381131364512650);
     let r = i64x2::new(1428972826343, 4256393046182047);
 
-    assert_eq!(r, transmute(lsx_vsrlr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -350,7 +435,7 @@ unsafe fn test_lsx_vsrlri_b() {
     );
     let r = i64x2::new(93866580842851436, 1896906350202744602);
 
-    assert_eq!(r, transmute(lsx_vsrlri_b::<1>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrlri_b::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -358,7 +443,7 @@ unsafe fn test_lsx_vsrlri_h() {
     let a = i16x8::new(-18045, 1968, 22966, 3692, 2010, -17108, 3373, -30706);
     let r = i64x2::new(1039304252363684227, -8642956144778934310);
 
-    assert_eq!(r, transmute(lsx_vsrlri_h::<0>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrlri_h::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -366,7 +451,7 @@ unsafe fn test_lsx_vsrlri_w() {
     let a = i32x4::new(1306456564, -1401620667, -839707416, -1634862919);
     let r = i64x2::new(1553353645217275455, 1428132662790218397);
 
-    assert_eq!(r, transmute(lsx_vsrlri_w::<3>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrlri_w::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -374,7 +459,7 @@ unsafe fn test_lsx_vsrlri_d() {
     let a = i64x2::new(-3683179565838693027, 6160461828074490983);
     let r = i64x2::new(205, 85);
 
-    assert_eq!(r, transmute(lsx_vsrlri_d::<56>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsrlri_d::<56>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -387,7 +472,13 @@ unsafe fn test_lsx_vbitclr_b() {
     );
     let r = i64x2::new(-7325372782311046420, -5316383129963115396);
 
-    assert_eq!(r, transmute(lsx_vbitclr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitclr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -396,7 +487,13 @@ unsafe fn test_lsx_vbitclr_h() {
     let b = u16x8::new(26587, 57597, 34751, 38678, 23919, 45729, 62569, 5978);
     let r = i64x2::new(-5495443997997256700, -3317648531059028099);
 
-    assert_eq!(r, transmute(lsx_vbitclr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitclr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -405,7 +502,13 @@ unsafe fn test_lsx_vbitclr_w() {
     let b = u32x4::new(1968231094, 2827365864, 4097273355, 4016923215);
     let r = i64x2::new(-7626667807832507452, 546969093373761021);
 
-    assert_eq!(r, transmute(lsx_vbitclr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitclr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -414,7 +517,13 @@ unsafe fn test_lsx_vbitclr_d() {
     let b = u64x2::new(5723204188033770667, 2981956604140378920);
     let r = i64x2::new(-1242851545812588193, -5509634528458855560);
 
-    assert_eq!(r, transmute(lsx_vbitclr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitclr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -424,7 +533,7 @@ unsafe fn test_lsx_vbitclri_b() {
     );
     let r = i64x2::new(7503621968728299154, -6865556469255070542);
 
-    assert_eq!(r, transmute(lsx_vbitclri_b::<0>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitclri_b::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -432,7 +541,7 @@ unsafe fn test_lsx_vbitclri_h() {
     let a = u16x8::new(17366, 58985, 22108, 45942, 27326, 19605, 9632, 32322);
     let r = i64x2::new(-5515130134779575338, 8809640793386347198);
 
-    assert_eq!(r, transmute(lsx_vbitclri_h::<10>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitclri_h::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -440,7 +549,7 @@ unsafe fn test_lsx_vbitclri_w() {
     let a = u32x4::new(718858183, 3771164920, 1842485081, 896350597);
     let r = i64x2::new(-2249714073768237625, 3849796501707560281);
 
-    assert_eq!(r, transmute(lsx_vbitclri_w::<9>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitclri_w::<9>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -448,7 +557,7 @@ unsafe fn test_lsx_vbitclri_d() {
     let a = u64x2::new(10838658690401820648, 3833745076866321369);
     let r = i64x2::new(-7608085933063544856, 3833744527110507481);
 
-    assert_eq!(r, transmute(lsx_vbitclri_d::<39>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitclri_d::<39>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -461,7 +570,13 @@ unsafe fn test_lsx_vbitset_b() {
     );
     let r = i64x2::new(-7941579666116909337, -8620998056061183460);
 
-    assert_eq!(r, transmute(lsx_vbitset_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitset_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -470,7 +585,13 @@ unsafe fn test_lsx_vbitset_h() {
     let b = u16x8::new(64512, 23847, 57770, 47705, 8024, 31966, 14493, 50266);
     let r = i64x2::new(8218739538452480967, 9190693790629616954);
 
-    assert_eq!(r, transmute(lsx_vbitset_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitset_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -479,7 +600,13 @@ unsafe fn test_lsx_vbitset_w() {
     let b = u32x4::new(3259082048, 1303228302, 1429001720, 209615081);
     let r = i64x2::new(5472281065241838073, -4235320193476931022);
 
-    assert_eq!(r, transmute(lsx_vbitset_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitset_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -488,7 +615,13 @@ unsafe fn test_lsx_vbitset_d() {
     let b = u64x2::new(12687331714071910183, 1753585392879336372);
     let r = i64x2::new(8117422612773760492, 5031452210401715131);
 
-    assert_eq!(r, transmute(lsx_vbitset_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitset_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -498,7 +631,7 @@ unsafe fn test_lsx_vbitseti_b() {
     );
     let r = i64x2::new(6185254145054243811, 5860546440891134157);
 
-    assert_eq!(r, transmute(lsx_vbitseti_b::<6>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitseti_b::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -506,7 +639,7 @@ unsafe fn test_lsx_vbitseti_h() {
     let a = u16x8::new(15222, 59961, 52253, 2908, 61562, 41309, 63627, 4191);
     let r = i64x2::new(819316619673811830, 1179934905985921146);
 
-    assert_eq!(r, transmute(lsx_vbitseti_h::<1>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitseti_h::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -514,7 +647,7 @@ unsafe fn test_lsx_vbitseti_w() {
     let a = u32x4::new(3788412756, 1863556832, 1913138259, 1199998627);
     let r = i64x2::new(8012922850722617172, 5162962059379878995);
 
-    assert_eq!(r, transmute(lsx_vbitseti_w::<21>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitseti_w::<21>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -522,7 +655,7 @@ unsafe fn test_lsx_vbitseti_d() {
     let a = u64x2::new(10744510173660993785, 16946223211744108759);
     let r = i64x2::new(-7702233900048557831, -1500520861831225129);
 
-    assert_eq!(r, transmute(lsx_vbitseti_d::<27>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitseti_d::<27>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -535,7 +668,13 @@ unsafe fn test_lsx_vbitrev_b() {
     );
     let r = i64x2::new(7553563628828981794, -3550669970358088907);
 
-    assert_eq!(r, transmute(lsx_vbitrev_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitrev_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -544,7 +683,13 @@ unsafe fn test_lsx_vbitrev_h() {
     let b = u16x8::new(21347, 23131, 57157, 13786, 34463, 33445, 23964, 48087);
     let r = i64x2::new(-2253077037977362312, -1686202867067838120);
 
-    assert_eq!(r, transmute(lsx_vbitrev_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitrev_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -553,7 +698,13 @@ unsafe fn test_lsx_vbitrev_w() {
     let b = u32x4::new(3330530584, 4153020036, 822570638, 2652744506);
     let r = i64x2::new(4583672484591007782, 3195058299616182309);
 
-    assert_eq!(r, transmute(lsx_vbitrev_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitrev_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -562,7 +713,13 @@ unsafe fn test_lsx_vbitrev_d() {
     let b = u64x2::new(10942298949673565895, 12884740754463765660);
     let r = i64x2::new(-2430080033105247697, -384636561250515393);
 
-    assert_eq!(r, transmute(lsx_vbitrev_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vbitrev_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -572,7 +729,7 @@ unsafe fn test_lsx_vbitrevi_b() {
     );
     let r = i64x2::new(8727320563398842300, 7658903196653594166);
 
-    assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -580,7 +737,7 @@ unsafe fn test_lsx_vbitrevi_h() {
     let a = u16x8::new(15083, 24599, 61212, 12408, 48399, 59833, 45416, 58826);
     let r = i64x2::new(8104420064785562347, -6500117680329458417);
 
-    assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -588,7 +745,7 @@ unsafe fn test_lsx_vbitrevi_w() {
     let a = u32x4::new(1200613355, 1418062686, 3847355950, 3312937419);
     let r = i64x2::new(6099540060505368555, -4226793400815190482);
 
-    assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -596,7 +753,7 @@ unsafe fn test_lsx_vbitrevi_d() {
     let a = u64x2::new(295858379748270823, 1326723086853575042);
     let r = i64x2::new(295858379748254439, 1326723086853591426);
 
-    assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -609,7 +766,10 @@ unsafe fn test_lsx_vadd_b() {
     );
     let r = i64x2::new(5228548393274527852, 1107461330348121713);
 
-    assert_eq!(r, transmute(lsx_vadd_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadd_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -618,7 +778,10 @@ unsafe fn test_lsx_vadd_h() {
     let b = i16x8::new(-25040, 15453, -28080, -31322, -24429, -12453, -18073, 27019);
     let r = i64x2::new(1938006946753467667, 3264410328302682781);
 
-    assert_eq!(r, transmute(lsx_vadd_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadd_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -627,7 +790,10 @@ unsafe fn test_lsx_vadd_w() {
     let b = i32x4::new(-1169804484, 389773725, -731843701, -1825112934);
     let r = i64x2::new(-2841313158179161935, -1386205072290870384);
 
-    assert_eq!(r, transmute(lsx_vadd_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadd_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -636,7 +802,10 @@ unsafe fn test_lsx_vadd_d() {
     let b = i64x2::new(7093939531558864473, 4047047970310912233);
     let r = i64x2::new(-204689461315224217, -5456447511965942904);
 
-    assert_eq!(r, transmute(lsx_vadd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadd_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -646,7 +815,7 @@ unsafe fn test_lsx_vaddi_bu() {
     );
     let r = i64x2::new(-7790681010872578420, 298548864442153210);
 
-    assert_eq!(r, transmute(lsx_vaddi_bu::<10>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vaddi_bu::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -654,7 +823,7 @@ unsafe fn test_lsx_vaddi_hu() {
     let a = i16x8::new(-16986, -28417, 11657, 16608, -30167, 18602, 8897, -854);
     let r = i64x2::new(4681541984598867390, -233585914045887935);
 
-    assert_eq!(r, transmute(lsx_vaddi_hu::<24>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vaddi_hu::<24>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -662,7 +831,7 @@ unsafe fn test_lsx_vaddi_wu() {
     let a = i32x4::new(1142343549, 56714754, -180143297, 408668191);
     let r = i64x2::new(243588023362963327, 1755216527965240129);
 
-    assert_eq!(r, transmute(lsx_vaddi_wu::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vaddi_wu::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -670,7 +839,7 @@ unsafe fn test_lsx_vaddi_du() {
     let a = i64x2::new(4516502893749962130, 9158051921593642947);
     let r = i64x2::new(4516502893749962139, 9158051921593642956);
 
-    assert_eq!(r, transmute(lsx_vaddi_du::<9>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vaddi_du::<9>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -683,7 +852,10 @@ unsafe fn test_lsx_vsub_b() {
     );
     let r = i64x2::new(-4051929421319416371, 8737463450488952169);
 
-    assert_eq!(r, transmute(lsx_vsub_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsub_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -692,7 +864,10 @@ unsafe fn test_lsx_vsub_h() {
     let b = i16x8::new(15368, 16207, 9677, 21447, -29583, -22036, 1845, 15671);
     let r = i64x2::new(-913983189443969573, 2742472381424198215);
 
-    assert_eq!(r, transmute(lsx_vsub_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsub_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -701,7 +876,10 @@ unsafe fn test_lsx_vsub_w() {
     let b = i32x4::new(617176389, -1376778690, 1463940361, 620446698);
     let r = i64x2::new(-7247543435452521192, -8067077040042720878);
 
-    assert_eq!(r, transmute(lsx_vsub_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsub_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -710,7 +888,10 @@ unsafe fn test_lsx_vsub_d() {
     let b = i64x2::new(1314101702815749241, 7673634401554993450);
     let r = i64x2::new(5925090640479842026, 5645651807574135757);
 
-    assert_eq!(r, transmute(lsx_vsub_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsub_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -720,7 +901,7 @@ unsafe fn test_lsx_vsubi_bu() {
     );
     let r = i64x2::new(-8192169673836457574, 4758493248402185941);
 
-    assert_eq!(r, transmute(lsx_vsubi_bu::<19>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsubi_bu::<19>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -728,7 +909,7 @@ unsafe fn test_lsx_vsubi_hu() {
     let a = i16x8::new(13272, -26858, -235, 16054, 29698, 1377, 4604, -3878);
     let r = i64x2::new(4514576075959186376, -1096043853912116238);
 
-    assert_eq!(r, transmute(lsx_vsubi_hu::<16>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsubi_hu::<16>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -736,7 +917,7 @@ unsafe fn test_lsx_vsubi_wu() {
     let a = i32x4::new(1277091145, -2076591216, -1523555105, -945754023);
     let r = i64x2::new(-8918891362898748088, -4061982600368986914);
 
-    assert_eq!(r, transmute(lsx_vsubi_wu::<1>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsubi_wu::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -744,7 +925,7 @@ unsafe fn test_lsx_vsubi_du() {
     let a = i64x2::new(-8248876128472283209, -2119651236628000925);
     let r = i64x2::new(-8248876128472283234, -2119651236628000950);
 
-    assert_eq!(r, transmute(lsx_vsubi_du::<25>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsubi_du::<25>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -757,7 +938,10 @@ unsafe fn test_lsx_vmax_b() {
     );
     let r = i64x2::new(1260734548147228113, 7591133008682590587);
 
-    assert_eq!(r, transmute(lsx_vmax_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -766,7 +950,10 @@ unsafe fn test_lsx_vmax_h() {
     let b = i16x8::new(25637, -11569, -23103, 6983, -17125, 5183, -709, 5986);
     let r = i64x2::new(1965654441534120997, 1684966995419662474);
 
-    assert_eq!(r, transmute(lsx_vmax_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -775,7 +962,10 @@ unsafe fn test_lsx_vmax_w() {
     let b = i32x4::new(643859790, -389733899, -1309288060, 1934346522);
     let r = i64x2::new(-1673894349703707314, 8307955054730158361);
 
-    assert_eq!(r, transmute(lsx_vmax_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -784,7 +974,10 @@ unsafe fn test_lsx_vmax_d() {
     let b = i64x2::new(-6137495199657896371, 2160025776787809810);
     let r = i64x2::new(-990960773872867733, 6406870358170165030);
 
-    assert_eq!(r, transmute(lsx_vmax_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -794,7 +987,7 @@ unsafe fn test_lsx_vmaxi_b() {
     );
     let r = i64x2::new(5908253215318699518, 1728939149412407162);
 
-    assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -802,7 +995,7 @@ unsafe fn test_lsx_vmaxi_h() {
     let a = i16x8::new(-14059, 19536, 15816, 28251, 23079, -10486, -11781, 25565);
     let r = i64x2::new(7952017497535807498, 7195907822558272039);
 
-    assert_eq!(r, transmute(lsx_vmaxi_h::<10>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_h::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -810,7 +1003,7 @@ unsafe fn test_lsx_vmaxi_w() {
     let a = i32x4::new(-1136628686, -168033999, -2082324641, -1789957469);
     let r = i64x2::new(55834574861, 55834574861);
 
-    assert_eq!(r, transmute(lsx_vmaxi_w::<13>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_w::<13>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -818,7 +1011,7 @@ unsafe fn test_lsx_vmaxi_d() {
     let a = i64x2::new(-490958606840895025, -602287987736508723);
     let r = i64x2::new(-5, -5);
 
-    assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -831,7 +1024,13 @@ unsafe fn test_lsx_vmax_bu() {
     );
     let r = i64x2::new(-5712542810735052010, 4588590651995571688);
 
-    assert_eq!(r, transmute(lsx_vmax_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -840,7 +1039,13 @@ unsafe fn test_lsx_vmax_hu() {
     let b = u16x8::new(61508, 27224, 11696, 15294, 30725, 4809, 55995, 24012);
     let r = i64x2::new(6366821095949791300, 6759017637785204741);
 
-    assert_eq!(r, transmute(lsx_vmax_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -849,7 +1054,13 @@ unsafe fn test_lsx_vmax_wu() {
     let b = u32x4::new(2856502284, 546582019, 3814541188, 2370198139);
     let r = i64x2::new(2347551899043152908, -8266820577849948284);
 
-    assert_eq!(r, transmute(lsx_vmax_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -858,7 +1069,13 @@ unsafe fn test_lsx_vmax_du() {
     let b = u64x2::new(15559502733477870114, 3537017767853389449);
     let r = i64x2::new(-1341110034690820781, -6520089917898609068);
 
-    assert_eq!(r, transmute(lsx_vmax_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmax_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -868,7 +1085,7 @@ unsafe fn test_lsx_vmaxi_bu() {
     );
     let r = i64x2::new(-1045930669804428840, -8076220938123067729);
 
-    assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -876,7 +1093,7 @@ unsafe fn test_lsx_vmaxi_hu() {
     let a = u16x8::new(56394, 18974, 59, 64239, 15178, 38205, 20044, 21066);
     let r = i64x2::new(-365072790147113910, 5929637950214978378);
 
-    assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -884,7 +1101,7 @@ unsafe fn test_lsx_vmaxi_wu() {
     let a = u32x4::new(2234002286, 3837532269, 3218694441, 2956128392);
     let r = i64x2::new(-1964668478775874706, -5750269304073789143);
 
-    assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -892,7 +1109,7 @@ unsafe fn test_lsx_vmaxi_du() {
     let a = u64x2::new(3145066433415682744, 697260191203805367);
     let r = i64x2::new(3145066433415682744, 697260191203805367);
 
-    assert_eq!(r, transmute(lsx_vmaxi_du::<15>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmaxi_du::<15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -905,7 +1122,10 @@ unsafe fn test_lsx_vmin_b() {
     );
     let r = i64x2::new(1870285769536668398, -8941449826914199819);
 
-    assert_eq!(r, transmute(lsx_vmin_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -914,7 +1134,10 @@ unsafe fn test_lsx_vmin_h() {
     let b = i16x8::new(-5519, 15267, -28304, -5842, 32145, 6582, -9646, -24918);
     let r = i64x2::new(-1644216902720689551, -7013553423522578637);
 
-    assert_eq!(r, transmute(lsx_vmin_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -923,7 +1146,10 @@ unsafe fn test_lsx_vmin_w() {
     let b = i32x4::new(-425011290, -2104111279, 175390640, 571448257);
     let r = i64x2::new(-9037089126579775578, 2454351575346593712);
 
-    assert_eq!(r, transmute(lsx_vmin_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -932,7 +1158,10 @@ unsafe fn test_lsx_vmin_d() {
     let b = i64x2::new(7269804448576860985, -2384075780126369706);
     let r = i64x2::new(5262417572890363865, -2384075780126369706);
 
-    assert_eq!(r, transmute(lsx_vmin_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -942,7 +1171,7 @@ unsafe fn test_lsx_vmini_b() {
     );
     let r = i64x2::new(-1187557278141451540, -940475489144045070);
 
-    assert_eq!(r, transmute(lsx_vmini_b::<-14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_b::<-14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -950,7 +1179,7 @@ unsafe fn test_lsx_vmini_h() {
     let a = i16x8::new(26119, -26421, -26720, 11534, 11181, -13024, -9525, -1565);
     let r = i64x2::new(-677708916064259, -440267769697468419);
 
-    assert_eq!(r, transmute(lsx_vmini_h::<-3>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_h::<-3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -958,7 +1187,7 @@ unsafe fn test_lsx_vmini_w() {
     let a = i32x4::new(1937226480, -56354461, -210581139, 118641668);
     let r = i64x2::new(-242040566978707451, 25559222637);
 
-    assert_eq!(r, transmute(lsx_vmini_w::<5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_w::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -966,7 +1195,7 @@ unsafe fn test_lsx_vmini_d() {
     let a = i64x2::new(-6839357499730806877, 2982085289136510651);
     let r = i64x2::new(-6839357499730806877, 11);
 
-    assert_eq!(r, transmute(lsx_vmini_d::<11>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_d::<11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -979,7 +1208,13 @@ unsafe fn test_lsx_vmin_bu() {
     );
     let r = i64x2::new(3617816997909406996, 4784078933357220137);
 
-    assert_eq!(r, transmute(lsx_vmin_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -988,7 +1223,13 @@ unsafe fn test_lsx_vmin_hu() {
     let b = u16x8::new(30424, 14541, 7654, 46014, 42452, 14971, 14903, 13871);
     let r = i64x2::new(-5494921620712753448, 3904403410832303572);
 
-    assert_eq!(r, transmute(lsx_vmin_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -997,7 +1238,13 @@ unsafe fn test_lsx_vmin_wu() {
     let b = u32x4::new(1456829356, 2264966310, 1587887390, 645429404);
     let r = i64x2::new(-8718787844260924500, 2772098183187911585);
 
-    assert_eq!(r, transmute(lsx_vmin_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1006,7 +1253,13 @@ unsafe fn test_lsx_vmin_du() {
     let b = u64x2::new(15079551366517035256, 13891052596545854864);
     let r = i64x2::new(6641707046382446478, 5750385968612732680);
 
-    assert_eq!(r, transmute(lsx_vmin_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmin_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1016,7 +1269,7 @@ unsafe fn test_lsx_vmini_bu() {
     );
     let r = i64x2::new(361700864190383365, 361700864190317829);
 
-    assert_eq!(r, transmute(lsx_vmini_bu::<5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_bu::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1024,7 +1277,7 @@ unsafe fn test_lsx_vmini_hu() {
     let a = u16x8::new(51791, 41830, 16737, 31634, 36341, 58491, 48701, 8690);
     let r = i64x2::new(5066626891382802, 5066626891382802);
 
-    assert_eq!(r, transmute(lsx_vmini_hu::<18>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_hu::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1032,7 +1285,7 @@ unsafe fn test_lsx_vmini_wu() {
     let a = u32x4::new(1158888991, 2639721369, 556001789, 2902942998);
     let r = i64x2::new(77309411346, 77309411346);
 
-    assert_eq!(r, transmute(lsx_vmini_wu::<18>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_wu::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1040,7 +1293,7 @@ unsafe fn test_lsx_vmini_du() {
     let a = u64x2::new(17903595768445663391, 13119300660970895532);
     let r = i64x2::new(13, 13);
 
-    assert_eq!(r, transmute(lsx_vmini_du::<13>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmini_du::<13>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1053,7 +1306,10 @@ unsafe fn test_lsx_vseq_b() {
     );
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseq_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vseq_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1062,7 +1318,10 @@ unsafe fn test_lsx_vseq_h() {
     let b = i16x8::new(-7387, -24074, 15709, -4629, 30465, -9504, -21403, -30287);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseq_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vseq_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1071,7 +1330,10 @@ unsafe fn test_lsx_vseq_w() {
     let b = i32x4::new(-493722413, -522973881, -1254416384, -884207273);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseq_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vseq_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1080,7 +1342,10 @@ unsafe fn test_lsx_vseq_d() {
     let b = i64x2::new(3023654898382436999, 1783520577741396523);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vseq_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1090,7 +1355,7 @@ unsafe fn test_lsx_vseqi_b() {
     );
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseqi_b::<12>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vseqi_b::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1098,7 +1363,7 @@ unsafe fn test_lsx_vseqi_h() {
     let a = i16x8::new(-3205, 25452, 20774, 22065, -8424, 16590, -15971, -14154);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseqi_h::<-1>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vseqi_h::<-1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1106,7 +1371,7 @@ unsafe fn test_lsx_vseqi_w() {
     let a = i32x4::new(199798215, -798304779, -1812193878, -1830438161);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseqi_w::<11>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vseqi_w::<11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1114,7 +1379,7 @@ unsafe fn test_lsx_vseqi_d() {
     let a = i64x2::new(-7376858177879278972, 1947027764115386661);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vseqi_d::<3>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vseqi_d::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1124,7 +1389,7 @@ unsafe fn test_lsx_vslti_b() {
     );
     let r = i64x2::new(-1099511627776, 1095216660480);
 
-    assert_eq!(r, transmute(lsx_vslti_b::<-4>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_b::<-4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1137,7 +1402,10 @@ unsafe fn test_lsx_vslt_b() {
     );
     let r = i64x2::new(-72056494526365441, -280375465148416);
 
-    assert_eq!(r, transmute(lsx_vslt_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1146,7 +1414,10 @@ unsafe fn test_lsx_vslt_h() {
     let b = i16x8::new(-10624, 12762, 31216, 13253, 2299, -12591, -8652, -22348);
     let r = i64x2::new(-4294967296, 65535);
 
-    assert_eq!(r, transmute(lsx_vslt_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1155,7 +1426,10 @@ unsafe fn test_lsx_vslt_w() {
     let b = i32x4::new(-1849021639, -756143028, 54274044, 646446450);
     let r = i64x2::new(-4294967296, -1);
 
-    assert_eq!(r, transmute(lsx_vslt_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1164,7 +1438,10 @@ unsafe fn test_lsx_vslt_d() {
     let b = i64x2::new(1481173131774551907, 270656941607020532);
     let r = i64x2::new(-1, 0);
 
-    assert_eq!(r, transmute(lsx_vslt_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1172,7 +1449,7 @@ unsafe fn test_lsx_vslti_h() {
     let a = i16x8::new(-8902, 5527, 17224, -27356, 4424, 28839, 29975, 18805);
     let r = i64x2::new(-281474976645121, 0);
 
-    assert_eq!(r, transmute(lsx_vslti_h::<14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_h::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1180,7 +1457,7 @@ unsafe fn test_lsx_vslti_w() {
     let a = i32x4::new(995282502, -1964668207, -996118772, 1812234755);
     let r = i64x2::new(-4294967296, 4294967295);
 
-    assert_eq!(r, transmute(lsx_vslti_w::<14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_w::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1188,7 +1465,7 @@ unsafe fn test_lsx_vslti_d() {
     let a = i64x2::new(1441753618400573134, 3878439049744730841);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslti_d::<14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_d::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1201,7 +1478,13 @@ unsafe fn test_lsx_vslt_bu() {
     );
     let r = i64x2::new(-281474959998721, -72057589742960896);
 
-    assert_eq!(r, transmute(lsx_vslt_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1210,7 +1493,13 @@ unsafe fn test_lsx_vslt_hu() {
     let b = u16x8::new(513, 13075, 20319, 44422, 12609, 18638, 20227, 21354);
     let r = i64x2::new(281474976645120, -281474976645121);
 
-    assert_eq!(r, transmute(lsx_vslt_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1219,7 +1508,13 @@ unsafe fn test_lsx_vslt_wu() {
     let b = u32x4::new(1402243125, 1129899238, 2591537060, 4152171743);
     let r = i64x2::new(4294967295, -1);
 
-    assert_eq!(r, transmute(lsx_vslt_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1228,7 +1523,13 @@ unsafe fn test_lsx_vslt_du() {
     let b = u64x2::new(835355141719377733, 10472626544222695938);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslt_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vslt_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1238,7 +1539,7 @@ unsafe fn test_lsx_vslti_bu() {
     );
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslti_bu::<7>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_bu::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1246,7 +1547,7 @@ unsafe fn test_lsx_vslti_hu() {
     let a = u16x8::new(60550, 12178, 30950, 44771, 25514, 35987, 55940, 21614);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslti_hu::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_hu::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1254,7 +1555,7 @@ unsafe fn test_lsx_vslti_wu() {
     let a = u32x4::new(912580668, 18660032, 3405726641, 4033549497);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslti_wu::<8>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_wu::<8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1262,7 +1563,7 @@ unsafe fn test_lsx_vslti_du() {
     let a = u64x2::new(17196150830761730262, 5893061291971214149);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslti_du::<14>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslti_du::<14>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1275,7 +1576,10 @@ unsafe fn test_lsx_vsle_b() {
     );
     let r = i64x2::new(281470681808895, 280375465148415);
 
-    assert_eq!(r, transmute(lsx_vsle_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1284,7 +1588,10 @@ unsafe fn test_lsx_vsle_h() {
     let b = i16x8::new(-30602, -9535, 10944, 3343, -1093, 6600, -19453, -4561);
     let r = i64x2::new(281470681743360, -281470681808896);
 
-    assert_eq!(r, transmute(lsx_vsle_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1293,7 +1600,10 @@ unsafe fn test_lsx_vsle_w() {
     let b = i32x4::new(-1810853975, 2021418524, 215198844, 1124361386);
     let r = i64x2::new(-4294967296, -4294967296);
 
-    assert_eq!(r, transmute(lsx_vsle_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1302,7 +1612,10 @@ unsafe fn test_lsx_vsle_d() {
     let b = i64x2::new(71694374951002423, -4307912969104303925);
     let r = i64x2::new(-1, 0);
 
-    assert_eq!(r, transmute(lsx_vsle_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1312,7 +1625,7 @@ unsafe fn test_lsx_vslei_b() {
     );
     let r = i64x2::new(72056494526365440, 280375465082880);
 
-    assert_eq!(r, transmute(lsx_vslei_b::<3>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_b::<3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1320,7 +1633,7 @@ unsafe fn test_lsx_vslei_h() {
     let a = i16x8::new(31276, -16628, -30006, -20587, 2104, -30062, 18261, -6449);
     let r = i64x2::new(-65536, -281470681808896);
 
-    assert_eq!(r, transmute(lsx_vslei_h::<-3>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_h::<-3>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1328,7 +1641,7 @@ unsafe fn test_lsx_vslei_w() {
     let a = i32x4::new(-1890390435, 1289536678, 1490122113, 2120063492);
     let r = i64x2::new(4294967295, 0);
 
-    assert_eq!(r, transmute(lsx_vslei_w::<-16>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_w::<-16>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1336,7 +1649,7 @@ unsafe fn test_lsx_vslei_d() {
     let a = i64x2::new(-123539898448811963, 8007480165241051883);
     let r = i64x2::new(-1, 0);
 
-    assert_eq!(r, transmute(lsx_vslei_d::<8>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_d::<8>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1349,7 +1662,13 @@ unsafe fn test_lsx_vsle_bu() {
     );
     let r = i64x2::new(1095216660480, 72057594021150720);
 
-    assert_eq!(r, transmute(lsx_vsle_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1358,7 +1677,13 @@ unsafe fn test_lsx_vsle_hu() {
     let b = u16x8::new(50529, 35111, 24746, 62465, 21587, 30574, 11054, 11653);
     let r = i64x2::new(-4294967296, 281474976710655);
 
-    assert_eq!(r, transmute(lsx_vsle_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1367,7 +1692,13 @@ unsafe fn test_lsx_vsle_wu() {
     let b = u32x4::new(1321018603, 1091195011, 3525236625, 4061062671);
     let r = i64x2::new(0, -1);
 
-    assert_eq!(r, transmute(lsx_vsle_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1376,7 +1707,13 @@ unsafe fn test_lsx_vsle_du() {
     let b = u64x2::new(16044633718831874991, 3531311371811276914);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vsle_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsle_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1386,7 +1723,7 @@ unsafe fn test_lsx_vslei_bu() {
     );
     let r = i64x2::new(71776119061217280, 280375465082880);
 
-    assert_eq!(r, transmute(lsx_vslei_bu::<18>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_bu::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1394,7 +1731,7 @@ unsafe fn test_lsx_vslei_hu() {
     let a = u16x8::new(1430, 10053, 35528, 28458, 2394, 22098, 40236, 20853);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslei_hu::<10>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_hu::<10>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1402,7 +1739,7 @@ unsafe fn test_lsx_vslei_wu() {
     let a = u32x4::new(3289026584, 3653636092, 2919866047, 2895662832);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslei_wu::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_wu::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1410,7 +1747,7 @@ unsafe fn test_lsx_vslei_du() {
     let a = u64x2::new(17462377852989253439, 17741928456729041079);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vslei_du::<12>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vslei_du::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1420,7 +1757,7 @@ unsafe fn test_lsx_vsat_b() {
     );
     let r = i64x2::new(-2964542792447819074, 3186937137643144200);
 
-    assert_eq!(r, transmute(lsx_vsat_b::<7>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_b::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1428,7 +1765,7 @@ unsafe fn test_lsx_vsat_h() {
     let a = i16x8::new(-22234, -8008, -23350, 13768, 26313, -27447, -3569, 6025);
     let r = i64x2::new(576451960371214336, 576451960371152895);
 
-    assert_eq!(r, transmute(lsx_vsat_h::<11>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_h::<11>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1436,7 +1773,7 @@ unsafe fn test_lsx_vsat_w() {
     let a = i32x4::new(-84179653, 874415975, 1823119516, 1667850968);
     let r = i64x2::new(137438953440, 133143986207);
 
-    assert_eq!(r, transmute(lsx_vsat_w::<5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_w::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1444,7 +1781,7 @@ unsafe fn test_lsx_vsat_d() {
     let a = i64x2::new(6859869867233872152, 2514172105675226457);
     let r = i64x2::new(262143, 262143);
 
-    assert_eq!(r, transmute(lsx_vsat_d::<18>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_d::<18>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1454,7 +1791,7 @@ unsafe fn test_lsx_vsat_bu() {
     );
     let r = i64x2::new(2125538672170008439, 6577605268441825038);
 
-    assert_eq!(r, transmute(lsx_vsat_bu::<6>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_bu::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1462,7 +1799,7 @@ unsafe fn test_lsx_vsat_hu() {
     let a = u16x8::new(36681, 34219, 6160, 8687, 4544, 20195, 35034, 916);
     let r = i64x2::new(287953294993589247, 257835472485549055);
 
-    assert_eq!(r, transmute(lsx_vsat_hu::<9>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_hu::<9>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1470,7 +1807,7 @@ unsafe fn test_lsx_vsat_wu() {
     let a = u32x4::new(1758000759, 4138051566, 2705324001, 3927640324);
     let r = i64x2::new(70364449226751, 70364449226751);
 
-    assert_eq!(r, transmute(lsx_vsat_wu::<13>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_wu::<13>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1478,7 +1815,7 @@ unsafe fn test_lsx_vsat_du() {
     let a = u64x2::new(1953136817312581670, 2606878300382729363);
     let r = i64x2::new(9007199254740991, 9007199254740991);
 
-    assert_eq!(r, transmute(lsx_vsat_du::<52>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsat_du::<52>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -1491,7 +1828,13 @@ unsafe fn test_lsx_vadda_b() {
     );
     let r = i64x2::new(8248499858970022011, 8535863472581999270);
 
-    assert_eq!(r, transmute(lsx_vadda_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadda_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1500,7 +1843,13 @@ unsafe fn test_lsx_vadda_h() {
     let b = i16x8::new(-21543, 21720, 14529, -19143, -28953, 13450, 8037, 29413);
     let r = i64x2::new(-8646732423142600033, 8924050915627474398);
 
-    assert_eq!(r, transmute(lsx_vadda_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadda_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1509,7 +1858,13 @@ unsafe fn test_lsx_vadda_w() {
     let b = i32x4::new(287041349, 249467792, 312776520, 1314435078);
     let r = i64x2::new(8345875378983299469, 6092442344252138029);
 
-    assert_eq!(r, transmute(lsx_vadda_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadda_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1518,7 +1873,13 @@ unsafe fn test_lsx_vadda_d() {
     let b = i64x2::new(-4324432602362661920, 6402427893748093984);
     let r = i64x2::new(6071741662385212188, -5328622052402301597);
 
-    assert_eq!(r, transmute(lsx_vadda_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadda_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1531,7 +1892,13 @@ unsafe fn test_lsx_vsadd_b() {
     );
     let r = i64x2::new(-3422653801050278697, 1909270979770548186);
 
-    assert_eq!(r, transmute(lsx_vsadd_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1540,7 +1907,13 @@ unsafe fn test_lsx_vsadd_h() {
     let b = i16x8::new(26970, 17131, 15547, -7614, -8479, 22338, 3567, -22299);
     let r = i64x2::new(6720170624686097630, -304244782337649222);
 
-    assert_eq!(r, transmute(lsx_vsadd_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1549,7 +1922,13 @@ unsafe fn test_lsx_vsadd_w() {
     let b = i32x4::new(-1026388582, 222487110, 501504960, -1863994162);
     let r = i64x2::new(-6565289918505943040, -6915373914453178024);
 
-    assert_eq!(r, transmute(lsx_vsadd_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1558,7 +1937,13 @@ unsafe fn test_lsx_vsadd_d() {
     let b = i64x2::new(-6599608819082608284, -5088169537193133686);
     let r = i64x2::new(-8567396806692999839, -9223372036854775808);
 
-    assert_eq!(r, transmute(lsx_vsadd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1571,7 +1956,13 @@ unsafe fn test_lsx_vsadd_bu() {
     );
     let r = i64x2::new(-5404438145481572386, -7318352348905473);
 
-    assert_eq!(r, transmute(lsx_vsadd_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1580,7 +1971,13 @@ unsafe fn test_lsx_vsadd_hu() {
     let b = u16x8::new(31219, 59227, 25607, 62798, 18845, 3238, 19902, 24978);
     let r = i64x2::new(-8740258447361, -136834913009665);
 
-    assert_eq!(r, transmute(lsx_vsadd_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1589,7 +1986,13 @@ unsafe fn test_lsx_vsadd_wu() {
     let b = u32x4::new(3676524021, 3894343575, 904432536, 1616820031);
     let r = i64x2::new(-1, -7583652642497232897);
 
-    assert_eq!(r, transmute(lsx_vsadd_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1598,7 +2001,13 @@ unsafe fn test_lsx_vsadd_du() {
     let b = u64x2::new(11054638512585704882, 3549000132135395099);
     let r = i64x2::new(-3651327027786652925, -623479558932885349);
 
-    assert_eq!(r, transmute(lsx_vsadd_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsadd_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1611,7 +2020,10 @@ unsafe fn test_lsx_vavg_b() {
     );
     let r = i64x2::new(-152206416164856247, 4369276355735447089);
 
-    assert_eq!(r, transmute(lsx_vavg_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1620,7 +2032,10 @@ unsafe fn test_lsx_vavg_h() {
     let b = i16x8::new(-3088, -25854, -32552, -8417, 7808, -12495, 22032, -5168);
     let r = i64x2::new(696836182083297626, -4337760619710117321);
 
-    assert_eq!(r, transmute(lsx_vavg_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1629,7 +2044,10 @@ unsafe fn test_lsx_vavg_w() {
     let b = i32x4::new(-324844828, -1580060766, -1909832882, 328273785);
     let r = i64x2::new(475428188150908257, 4521676108535152711);
 
-    assert_eq!(r, transmute(lsx_vavg_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1638,7 +2056,10 @@ unsafe fn test_lsx_vavg_d() {
     let b = i64x2::new(3169904420607189220, 5159962511251707672);
     let r = i64x2::new(2328313764472338215, 5669256157716045974);
 
-    assert_eq!(r, transmute(lsx_vavg_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1651,7 +2072,13 @@ unsafe fn test_lsx_vavg_bu() {
     );
     let r = i64x2::new(-5663745084945885565, 2801126043194071837);
 
-    assert_eq!(r, transmute(lsx_vavg_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1660,7 +2087,13 @@ unsafe fn test_lsx_vavg_hu() {
     let b = u16x8::new(44835, 36733, 12115, 42874, 4819, 12201, 27397, 25394);
     let r = i64x2::new(-4196978047981735086, -6439149718662907396);
 
-    assert_eq!(r, transmute(lsx_vavg_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1669,7 +2102,13 @@ unsafe fn test_lsx_vavg_wu() {
     let b = u32x4::new(160886383, 26081142, 459122380, 2523086630);
     let r = i64x2::new(123816739188229069, -5586965600173345916);
 
-    assert_eq!(r, transmute(lsx_vavg_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1678,7 +2117,13 @@ unsafe fn test_lsx_vavg_du() {
     let b = u64x2::new(9749063966076740681, 5963120178993456389);
     let r = i64x2::new(-7770235857859936532, 7939635441364553211);
 
-    assert_eq!(r, transmute(lsx_vavg_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavg_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1691,7 +2136,13 @@ unsafe fn test_lsx_vavgr_b() {
     );
     let r = i64x2::new(1883712581662731545, -1226681417271426582);
 
-    assert_eq!(r, transmute(lsx_vavgr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1700,7 +2151,13 @@ unsafe fn test_lsx_vavgr_h() {
     let b = i16x8::new(-9758, -8332, 20577, 31066, 31120, 14788, -22323, 16722);
     let r = i64x2::new(3801916629507170613, 3994084079587580569);
 
-    assert_eq!(r, transmute(lsx_vavgr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1709,7 +2166,13 @@ unsafe fn test_lsx_vavgr_w() {
     let b = i32x4::new(1278058715, -155858446, -195547847, -750518746);
     let r = i64x2::new(4040594005688324125, -5795079921582298726);
 
-    assert_eq!(r, transmute(lsx_vavgr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1718,7 +2181,13 @@ unsafe fn test_lsx_vavgr_d() {
     let b = i64x2::new(8758126674980055299, -7441643514470614533);
     let r = i64x2::new(3399991646978312393, -1904131665097658207);
 
-    assert_eq!(r, transmute(lsx_vavgr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1731,7 +2200,13 @@ unsafe fn test_lsx_vavgr_bu() {
     );
     let r = i64x2::new(9122444831751176042, 6010164553039771699);
 
-    assert_eq!(r, transmute(lsx_vavgr_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1740,7 +2215,13 @@ unsafe fn test_lsx_vavgr_hu() {
     let b = u16x8::new(26111, 34713, 61420, 23702, 29204, 9543, 62786, 7043);
     let r = i64x2::new(7022187818705851223, 4754859411904311722);
 
-    assert_eq!(r, transmute(lsx_vavgr_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1749,7 +2230,13 @@ unsafe fn test_lsx_vavgr_wu() {
     let b = u32x4::new(1930150361, 3668628165, 2983921396, 2410913126);
     let r = i64x2::new(-5401180487351753235, 8140240017388800980);
 
-    assert_eq!(r, transmute(lsx_vavgr_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1758,7 +2245,13 @@ unsafe fn test_lsx_vavgr_du() {
     let b = u64x2::new(8650759135311802962, 11380630663742852932);
     let r = i64x2::new(6046550632940509412, 8095423581736830430);
 
-    assert_eq!(r, transmute(lsx_vavgr_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vavgr_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1771,7 +2264,13 @@ unsafe fn test_lsx_vssub_b() {
     );
     let r = i64x2::new(628822736562549631, -9187601072510296593);
 
-    assert_eq!(r, transmute(lsx_vssub_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1780,7 +2279,13 @@ unsafe fn test_lsx_vssub_h() {
     let b = i16x8::new(-26027, 6118, -13204, 25080, 12458, 8441, 24701, 11617);
     let r = i64x2::new(-9223231300041015297, 1942699741282756937);
 
-    assert_eq!(r, transmute(lsx_vssub_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1789,7 +2294,13 @@ unsafe fn test_lsx_vssub_w() {
     let b = i32x4::new(-1808829767, 2144666490, 146236682, 1180114488);
     let r = i64x2::new(-9223372035405031217, -177933965588659662);
 
-    assert_eq!(r, transmute(lsx_vssub_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1798,7 +2309,13 @@ unsafe fn test_lsx_vssub_d() {
     let b = i64x2::new(-2293337525465880409, 5736255249834646932);
     let r = i64x2::new(2921430482628531027, -4208815595153969049);
 
-    assert_eq!(r, transmute(lsx_vssub_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1811,7 +2328,13 @@ unsafe fn test_lsx_vssub_bu() {
     );
     let r = i64x2::new(1441151919413273782, 87960930222283);
 
-    assert_eq!(r, transmute(lsx_vssub_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1820,7 +2343,13 @@ unsafe fn test_lsx_vssub_hu() {
     let b = u16x8::new(50468, 33060, 15257, 59071, 59343, 21993, 42978, 20097);
     let r = i64x2::new(902801202201243247, -7922957643493867520);
 
-    assert_eq!(r, transmute(lsx_vssub_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1829,7 +2358,13 @@ unsafe fn test_lsx_vssub_wu() {
     let b = u32x4::new(31483972, 3489479082, 152079374, 1875131600);
     let r = i64x2::new(66202020638834260, 1378022115978010238);
 
-    assert_eq!(r, transmute(lsx_vssub_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1838,7 +2373,13 @@ unsafe fn test_lsx_vssub_du() {
     let b = u64x2::new(6460869225596371206, 16765308520486969885);
     let r = i64x2::new(8426906920692365065, 0);
 
-    assert_eq!(r, transmute(lsx_vssub_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssub_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1851,7 +2392,13 @@ unsafe fn test_lsx_vabsd_b() {
     );
     let r = i64x2::new(4230359294854509733, 2116586434120326452);
 
-    assert_eq!(r, transmute(lsx_vabsd_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1860,7 +2407,13 @@ unsafe fn test_lsx_vabsd_h() {
     let b = i16x8::new(9346, 27961, 21592, 10762, -6831, 17219, 14968, -1750);
     let r = i64x2::new(4018377481144584593, 2994052849949411737);
 
-    assert_eq!(r, transmute(lsx_vabsd_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1869,7 +2422,13 @@ unsafe fn test_lsx_vabsd_w() {
     let b = i32x4::new(-638463360, -1154268425, 818053243, -1766966029);
     let r = i64x2::new(4346218292750542585, 1613133471209364690);
 
-    assert_eq!(r, transmute(lsx_vabsd_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1878,7 +2437,13 @@ unsafe fn test_lsx_vabsd_d() {
     let b = i64x2::new(-8533946706796471089, 1165272962517390961);
     let r = i64x2::new(7188249046367538699, 8146605509049538382);
 
-    assert_eq!(r, transmute(lsx_vabsd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1891,7 +2456,13 @@ unsafe fn test_lsx_vabsd_bu() {
     );
     let r = i64x2::new(2316568964225934796, 5350198762417854927);
 
-    assert_eq!(r, transmute(lsx_vabsd_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1900,7 +2471,13 @@ unsafe fn test_lsx_vabsd_hu() {
     let b = u16x8::new(42102, 40052, 6807, 16289, 29686, 38061, 42843, 26642);
     let r = i64x2::new(-6889746235852116468, 1175584127230950722);
 
-    assert_eq!(r, transmute(lsx_vabsd_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1909,7 +2486,13 @@ unsafe fn test_lsx_vabsd_wu() {
     let b = u32x4::new(3008439409, 976530727, 1726048801, 4235308512);
     let r = i64x2::new(-5056055741505581388, 103751774096297765);
 
-    assert_eq!(r, transmute(lsx_vabsd_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1918,7 +2501,13 @@ unsafe fn test_lsx_vabsd_du() {
     let b = u64x2::new(305704565845198935, 18327726360649467511);
     let r = i64x2::new(-4540227154002526968, -1590034053554043722);
 
-    assert_eq!(r, transmute(lsx_vabsd_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vabsd_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1931,7 +2520,10 @@ unsafe fn test_lsx_vmul_b() {
     );
     let r = i64x2::new(-836412611799730432, -7959044669412588992);
 
-    assert_eq!(r, transmute(lsx_vmul_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmul_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1940,7 +2532,10 @@ unsafe fn test_lsx_vmul_h() {
     let b = i16x8::new(-18582, -25667, 17674, 8424, -17121, -21798, 28934, -353);
     let r = i64x2::new(-7419436171490628650, 3947512047518358605);
 
-    assert_eq!(r, transmute(lsx_vmul_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmul_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1949,7 +2544,10 @@ unsafe fn test_lsx_vmul_w() {
     let b = i32x4::new(1754730718, 782084571, 894216679, -1895747372);
     let r = i64x2::new(6602438528086061106, 4680306660704041039);
 
-    assert_eq!(r, transmute(lsx_vmul_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmul_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1958,7 +2556,10 @@ unsafe fn test_lsx_vmul_d() {
     let b = i64x2::new(8096709215426138432, -5454415917204378153);
     let r = i64x2::new(-1062747544199352000, -649255846668983579);
 
-    assert_eq!(r, transmute(lsx_vmul_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmul_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -1976,7 +2577,11 @@ unsafe fn test_lsx_vmadd_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmadd_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmadd_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -1989,7 +2594,11 @@ unsafe fn test_lsx_vmadd_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmadd_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmadd_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2002,7 +2611,11 @@ unsafe fn test_lsx_vmadd_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmadd_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmadd_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2015,7 +2628,11 @@ unsafe fn test_lsx_vmadd_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmadd_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2034,7 +2651,11 @@ unsafe fn test_lsx_vmsub_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmsub_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmsub_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2047,7 +2668,11 @@ unsafe fn test_lsx_vmsub_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmsub_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmsub_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2060,7 +2685,11 @@ unsafe fn test_lsx_vmsub_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmsub_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmsub_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2073,7 +2702,11 @@ unsafe fn test_lsx_vmsub_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmsub_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2087,7 +2720,10 @@ unsafe fn test_lsx_vdiv_b() {
     );
     let r = i64x2::new(720575944674246657, 281475060530176);
 
-    assert_eq!(r, transmute(lsx_vdiv_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2096,7 +2732,10 @@ unsafe fn test_lsx_vdiv_h() {
     let b = i16x8::new(-11221, 24673, 19931, 3799, -3251, -21373, -13758, -31286);
     let r = i64x2::new(-1125904201744385, 281470681743353);
 
-    assert_eq!(r, transmute(lsx_vdiv_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2105,7 +2744,10 @@ unsafe fn test_lsx_vdiv_w() {
     let b = i32x4::new(-775731190, 1887886939, 1001718213, 1135075421);
     let r = i64x2::new(4294967295, 4294967297);
 
-    assert_eq!(r, transmute(lsx_vdiv_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2114,7 +2756,10 @@ unsafe fn test_lsx_vdiv_d() {
     let b = i64x2::new(-9175012156877545557, -6390704898809702209);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vdiv_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2127,7 +2772,13 @@ unsafe fn test_lsx_vdiv_bu() {
     );
     let r = i64x2::new(261, 72058702139687425);
 
-    assert_eq!(r, transmute(lsx_vdiv_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2136,7 +2787,13 @@ unsafe fn test_lsx_vdiv_hu() {
     let b = u16x8::new(25282, 44917, 13706, 63351, 58837, 46710, 29092, 57823);
     let r = i64x2::new(4294967297, 0);
 
-    assert_eq!(r, transmute(lsx_vdiv_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2145,7 +2802,13 @@ unsafe fn test_lsx_vdiv_wu() {
     let b = u32x4::new(1130189258, 1211056894, 2357258312, 3855913706);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vdiv_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2154,7 +2817,13 @@ unsafe fn test_lsx_vdiv_du() {
     let b = u64x2::new(14945948123666054968, 10864054932328247404);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vdiv_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vdiv_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2167,7 +2836,13 @@ unsafe fn test_lsx_vhaddw_h_b() {
     );
     let r = i64x2::new(13791943145684950, -562821104926904);
 
-    assert_eq!(r, transmute(lsx_vhaddw_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2178,7 +2853,13 @@ unsafe fn test_lsx_vhaddw_w_h() {
     );
     let r = i64x2::new(56307021213062, 183021441324639);
 
-    assert_eq!(r, transmute(lsx_vhaddw_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2187,7 +2868,13 @@ unsafe fn test_lsx_vhaddw_d_w() {
     let b = i32x4::new(-1119468785, -1334232049, -1752131604, -2016112631);
     let r = i64x2::new(-2502031305, -1217615295);
 
-    assert_eq!(r, transmute(lsx_vhaddw_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2200,7 +2887,13 @@ unsafe fn test_lsx_vhaddw_hu_bu() {
     );
     let r = i64x2::new(45601115212087520, 21110838012870921);
 
-    assert_eq!(r, transmute(lsx_vhaddw_hu_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_hu_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2209,7 +2902,13 @@ unsafe fn test_lsx_vhaddw_wu_hu() {
     let b = u16x8::new(40369, 53005, 64424, 35720, 9231, 19965, 20662, 8208);
     let r = i64x2::new(411432097222434, 312888367535410);
 
-    assert_eq!(r, transmute(lsx_vhaddw_wu_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_wu_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2218,7 +2917,13 @@ unsafe fn test_lsx_vhaddw_du_wu() {
     let b = u32x4::new(728838120, 1267673009, 2659634151, 2264611356);
     let r = i64x2::new(4172122985, 4839922613);
 
-    assert_eq!(r, transmute(lsx_vhaddw_du_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_du_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2231,7 +2936,13 @@ unsafe fn test_lsx_vhsubw_h_b() {
     );
     let r = i64x2::new(-4503363402989617, -31243430355664844);
 
-    assert_eq!(r, transmute(lsx_vhsubw_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2240,7 +2951,13 @@ unsafe fn test_lsx_vhsubw_w_h() {
     let b = i16x8::new(-14204, -13312, 8240, -4455, -6362, -4711, -30790, -15773);
     let r = i64x2::new(70059506530916, 60275571046613);
 
-    assert_eq!(r, transmute(lsx_vhsubw_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2249,7 +2966,13 @@ unsafe fn test_lsx_vhsubw_d_w() {
     let b = i32x4::new(-1671723008, 870456702, 264823818, 13322401);
     let r = i64x2::new(-201438605, 449141316);
 
-    assert_eq!(r, transmute(lsx_vhsubw_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2262,7 +2985,13 @@ unsafe fn test_lsx_vhsubw_hu_bu() {
     );
     let r = i64x2::new(-62206416523952172, 42783380429340790);
 
-    assert_eq!(r, transmute(lsx_vhsubw_hu_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_hu_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2271,7 +3000,13 @@ unsafe fn test_lsx_vhsubw_wu_hu() {
     let b = u16x8::new(5212, 32159, 36502, 59290, 7604, 229, 35511, 47443);
     let r = i64x2::new(24696062008394, -147484881944276);
 
-    assert_eq!(r, transmute(lsx_vhsubw_wu_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_wu_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2280,7 +3015,13 @@ unsafe fn test_lsx_vhsubw_du_wu() {
     let b = u32x4::new(1383087137, 2403951939, 360532131, 3513614550);
     let r = i64x2::new(-601935499, 31776736);
 
-    assert_eq!(r, transmute(lsx_vhsubw_du_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_du_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2293,7 +3034,10 @@ unsafe fn test_lsx_vmod_b() {
     );
     let r = i64x2::new(2804691417388804007, -2461515231199824166);
 
-    assert_eq!(r, transmute(lsx_vmod_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2302,7 +3046,10 @@ unsafe fn test_lsx_vmod_h() {
     let b = i16x8::new(1550, 9221, -12080, 14553, -24847, 28286, 1074, 192);
     let r = i64x2::new(3930282117007147005, -10982007906888970);
 
-    assert_eq!(r, transmute(lsx_vmod_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2311,7 +3058,10 @@ unsafe fn test_lsx_vmod_w() {
     let b = i32x4::new(344507881, 1692387020, -1397506903, -1257953510);
     let r = i64x2::new(-5027973877095011085, 2553570821342119010);
 
-    assert_eq!(r, transmute(lsx_vmod_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2320,7 +3070,10 @@ unsafe fn test_lsx_vmod_d() {
     let b = i64x2::new(4636642606889723746, -259899475747531088);
     let r = i64x2::new(-1381676014874400835, -257849503742906530);
 
-    assert_eq!(r, transmute(lsx_vmod_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2333,7 +3086,13 @@ unsafe fn test_lsx_vmod_bu() {
     );
     let r = i64x2::new(7287961163701724026, 4745974892933063220);
 
-    assert_eq!(r, transmute(lsx_vmod_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2342,7 +3101,13 @@ unsafe fn test_lsx_vmod_hu() {
     let b = u16x8::new(15317, 24954, 61354, 3720, 21471, 6193, 8193, 35745);
     let r = i64x2::new(315403234587388856, 7101062794264266609);
 
-    assert_eq!(r, transmute(lsx_vmod_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2351,7 +3116,13 @@ unsafe fn test_lsx_vmod_wu() {
     let b = u32x4::new(49228057, 2249712923, 358897384, 1782599598);
     let r = i64x2::new(1070413902953059662, 3340025749258890964);
 
-    assert_eq!(r, transmute(lsx_vmod_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2360,7 +3131,13 @@ unsafe fn test_lsx_vmod_du() {
     let b = u64x2::new(16850073055169051895, 16069565262862467484);
     let r = i64x2::new(7747010922784437137, 20234676239478699);
 
-    assert_eq!(r, transmute(lsx_vmod_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmod_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2370,7 +3147,7 @@ unsafe fn test_lsx_vreplve_b() {
     );
     let r = i64x2::new(-2893606913523066921, -2893606913523066921);
 
-    assert_eq!(r, transmute(lsx_vreplve_b(transmute(a), -8)));
+    assert_eq!(r, transmute(lsx_vreplve_b(black_box(transmute(a)), -8)));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2378,7 +3155,7 @@ unsafe fn test_lsx_vreplve_h() {
     let a = i16x8::new(-29429, -23495, 8705, -7614, -25353, 11887, -25989, -12818);
     let r = i64x2::new(-3607719825936298514, -3607719825936298514);
 
-    assert_eq!(r, transmute(lsx_vreplve_h(transmute(a), 7)));
+    assert_eq!(r, transmute(lsx_vreplve_h(black_box(transmute(a)), 7)));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2386,7 +3163,7 @@ unsafe fn test_lsx_vreplve_w() {
     let a = i32x4::new(1584940676, 95787593, -1655264847, 682404402);
     let r = i64x2::new(411404579393346121, 411404579393346121);
 
-    assert_eq!(r, transmute(lsx_vreplve_w(transmute(a), -3)));
+    assert_eq!(r, transmute(lsx_vreplve_w(black_box(transmute(a)), -3)));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2394,7 +3171,7 @@ unsafe fn test_lsx_vreplve_d() {
     let a = i64x2::new(7614424214598615675, -7096892795239148002);
     let r = i64x2::new(7614424214598615675, 7614424214598615675);
 
-    assert_eq!(r, transmute(lsx_vreplve_d(transmute(a), 0)));
+    assert_eq!(r, transmute(lsx_vreplve_d(black_box(transmute(a)), 0)));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2404,7 +3181,7 @@ unsafe fn test_lsx_vreplvei_b() {
     );
     let r = i64x2::new(-2097865012304223518, -2097865012304223518);
 
-    assert_eq!(r, transmute(lsx_vreplvei_b::<5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vreplvei_b::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2412,7 +3189,7 @@ unsafe fn test_lsx_vreplvei_h() {
     let a = i16x8::new(-15455, -4410, 5029, 25863, -23170, 26570, 27423, -834);
     let r = i64x2::new(7719006069021698847, 7719006069021698847);
 
-    assert_eq!(r, transmute(lsx_vreplvei_h::<6>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vreplvei_h::<6>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2420,7 +3197,7 @@ unsafe fn test_lsx_vreplvei_w() {
     let a = i32x4::new(1843143434, 491125746, -328585251, -1996512058);
     let r = i64x2::new(7916240772710277898, 7916240772710277898);
 
-    assert_eq!(r, transmute(lsx_vreplvei_w::<0>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vreplvei_w::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2428,7 +3205,7 @@ unsafe fn test_lsx_vreplvei_d() {
     let a = i64x2::new(4333963848299154309, -8310246545782080694);
     let r = i64x2::new(-8310246545782080694, -8310246545782080694);
 
-    assert_eq!(r, transmute(lsx_vreplvei_d::<1>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vreplvei_d::<1>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2441,7 +3218,13 @@ unsafe fn test_lsx_vpickev_b() {
     );
     let r = i64x2::new(3921750152141124833, -933322373843017127);
 
-    assert_eq!(r, transmute(lsx_vpickev_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickev_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2450,7 +3233,13 @@ unsafe fn test_lsx_vpickev_h() {
     let b = i16x8::new(-5248, -1786, -21768, 23214, -4223, 23538, -24936, -32316);
     let r = i64x2::new(-7018596679058658432, 139073165196191894);
 
-    assert_eq!(r, transmute(lsx_vpickev_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickev_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2459,7 +3248,13 @@ unsafe fn test_lsx_vpickev_w() {
     let b = i32x4::new(-1187277846, -787064901, -980229113, 1746235326);
     let r = i64x2::new(-4210051979814398998, -769258006856513132);
 
-    assert_eq!(r, transmute(lsx_vpickev_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickev_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2468,7 +3263,13 @@ unsafe fn test_lsx_vpickev_d() {
     let b = i64x2::new(6574352346370076190, -3979792156310826694);
     let r = i64x2::new(6574352346370076190, 1789073368466131160);
 
-    assert_eq!(r, transmute(lsx_vpickev_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickev_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2481,7 +3282,13 @@ unsafe fn test_lsx_vpickod_b() {
     );
     let r = i64x2::new(8220640377280882872, -6083110277645985532);
 
-    assert_eq!(r, transmute(lsx_vpickod_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickod_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2490,7 +3297,13 @@ unsafe fn test_lsx_vpickod_h() {
     let b = i16x8::new(12047, 25024, -10709, -28077, 24357, 19934, 10289, 28546);
     let r = i64x2::new(8035070303515402688, 6167254016163165900);
 
-    assert_eq!(r, transmute(lsx_vpickod_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickod_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2499,7 +3312,13 @@ unsafe fn test_lsx_vpickod_w() {
     let b = i32x4::new(-99240403, 314407358, 543396756, 1976776696);
     let r = i64x2::new(8490191261129341374, -7045044594236590438);
 
-    assert_eq!(r, transmute(lsx_vpickod_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickod_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2508,7 +3327,13 @@ unsafe fn test_lsx_vpickod_d() {
     let b = i64x2::new(-4197243771252175958, -543692393753629390);
     let r = i64x2::new(-543692393753629390, -7578696032343374601);
 
-    assert_eq!(r, transmute(lsx_vpickod_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickod_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2521,7 +3346,13 @@ unsafe fn test_lsx_vilvh_b() {
     );
     let r = i64x2::new(1211180715666052671, -2634368371891034045);
 
-    assert_eq!(r, transmute(lsx_vilvh_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvh_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2530,7 +3361,13 @@ unsafe fn test_lsx_vilvh_h() {
     let b = i16x8::new(23768, -31845, 28689, 14757, 9499, 7795, -13573, -10011);
     let r = i64x2::new(-4714953853167983333, 4564918175499275003);
 
-    assert_eq!(r, transmute(lsx_vilvh_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvh_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2539,7 +3376,13 @@ unsafe fn test_lsx_vilvh_w() {
     let b = i32x4::new(-737076987, 38515006, 602108871, -63099569);
     let r = i64x2::new(-5365723764939852857, -1200522227779556017);
 
-    assert_eq!(r, transmute(lsx_vilvh_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvh_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2548,7 +3391,13 @@ unsafe fn test_lsx_vilvh_d() {
     let b = i64x2::new(-2160658667838026389, 1449429407527660400);
     let r = i64x2::new(1449429407527660400, 5375050218784453679);
 
-    assert_eq!(r, transmute(lsx_vilvh_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvh_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2561,7 +3410,13 @@ unsafe fn test_lsx_vilvl_b() {
     );
     let r = i64x2::new(6945744258789947856, 8515979671552484861);
 
-    assert_eq!(r, transmute(lsx_vilvl_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvl_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2570,7 +3425,13 @@ unsafe fn test_lsx_vilvl_h() {
     let b = i16x8::new(11601, 6788, 3174, -4208, -25999, -25660, -4591, 7133);
     let r = i64x2::new(-6560589601043632815, -2260825085889541018);
 
-    assert_eq!(r, transmute(lsx_vilvl_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvl_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2579,7 +3440,13 @@ unsafe fn test_lsx_vilvl_w() {
     let b = i32x4::new(486029703, 1245981961, 112180197, 1939621508);
     let r = i64x2::new(-4282490222245561977, 7435326725564935433);
 
-    assert_eq!(r, transmute(lsx_vilvl_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvl_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2588,7 +3455,13 @@ unsafe fn test_lsx_vilvl_d() {
     let b = i64x2::new(3142531875873363679, 736682102982019415);
     let r = i64x2::new(3142531875873363679, 7063413230460842607);
 
-    assert_eq!(r, transmute(lsx_vilvl_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vilvl_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2601,7 +3474,13 @@ unsafe fn test_lsx_vpackev_b() {
     );
     let r = i64x2::new(-1928363389519380677, -1882898104368665381);
 
-    assert_eq!(r, transmute(lsx_vpackev_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackev_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2610,7 +3489,13 @@ unsafe fn test_lsx_vpackev_h() {
     let b = i16x8::new(-9444, 5210, -14402, 17972, 16606, 2450, 5123, 14727);
     let r = i64x2::new(7533052947329899292, 1461440082551914718);
 
-    assert_eq!(r, transmute(lsx_vpackev_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackev_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2619,7 +3504,13 @@ unsafe fn test_lsx_vpackev_w() {
     let b = i32x4::new(-872903277, 1255047449, -2110158279, 682925573);
     let r = i64x2::new(5636997704425442707, -8345976908349339079);
 
-    assert_eq!(r, transmute(lsx_vpackev_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackev_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2628,7 +3519,13 @@ unsafe fn test_lsx_vpackev_d() {
     let b = i64x2::new(-9119315954224042738, -4563700463464702181);
     let r = i64x2::new(-9119315954224042738, 7118943335298607169);
 
-    assert_eq!(r, transmute(lsx_vpackev_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackev_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2641,7 +3538,13 @@ unsafe fn test_lsx_vpackod_b() {
     );
     let r = i64x2::new(4389351353151377653, -4315624792288929032);
 
-    assert_eq!(r, transmute(lsx_vpackod_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackod_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2650,7 +3553,13 @@ unsafe fn test_lsx_vpackod_h() {
     let b = i16x8::new(-23247, 17928, -13353, -20146, 5696, 22071, -10728, -30262);
     let r = i64x2::new(-4433598883325590008, -9178747487946648009);
 
-    assert_eq!(r, transmute(lsx_vpackod_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackod_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2659,7 +3568,13 @@ unsafe fn test_lsx_vpackod_w() {
     let b = i32x4::new(445270781, 793617340, -1461557030, -22199234);
     let r = i64x2::new(51238874735551420, 6731566319615689790);
 
-    assert_eq!(r, transmute(lsx_vpackod_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackod_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2668,7 +3583,13 @@ unsafe fn test_lsx_vpackod_d() {
     let b = i64x2::new(9039771682296134623, -6404442538060227683);
     let r = i64x2::new(-6404442538060227683, -4670773907187480618);
 
-    assert_eq!(r, transmute(lsx_vpackod_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpackod_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2680,7 +3601,11 @@ unsafe fn test_lsx_vshuf_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vshuf_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vshuf_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2693,7 +3618,11 @@ unsafe fn test_lsx_vshuf_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vshuf_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vshuf_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2706,7 +3635,11 @@ unsafe fn test_lsx_vshuf_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vshuf_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vshuf_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2720,7 +3653,10 @@ unsafe fn test_lsx_vand_v() {
     );
     let r = i64x2::new(244105884219744360, -9223116804091473582);
 
-    assert_eq!(r, transmute(lsx_vand_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vand_v(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2730,7 +3666,7 @@ unsafe fn test_lsx_vandi_b() {
     );
     let r = i64x2::new(-8135737750142058361, -7666517314596397435);
 
-    assert_eq!(r, transmute(lsx_vandi_b::<159>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vandi_b::<159>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2743,7 +3679,10 @@ unsafe fn test_lsx_vor_v() {
     );
     let r = i64x2::new(-2351582766212852737, -4924766118269159990);
 
-    assert_eq!(r, transmute(lsx_vor_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vor_v(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2753,7 +3692,7 @@ unsafe fn test_lsx_vori_b() {
     );
     let r = i64x2::new(-589140355308650538, -3179554720060804109);
 
-    assert_eq!(r, transmute(lsx_vori_b::<210>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vori_b::<210>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2766,7 +3705,10 @@ unsafe fn test_lsx_vnor_v() {
     );
     let r = i64x2::new(3036560889408918025, 7823034030269427744);
 
-    assert_eq!(r, transmute(lsx_vnor_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vnor_v(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2776,7 +3718,7 @@ unsafe fn test_lsx_vnori_b() {
     );
     let r = i64x2::new(5227628601268782144, 596802560304890884);
 
-    assert_eq!(r, transmute(lsx_vnori_b::<51>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vnori_b::<51>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2789,7 +3731,10 @@ unsafe fn test_lsx_vxor_v() {
     );
     let r = i64x2::new(8732028225622312747, 6858262329367852470);
 
-    assert_eq!(r, transmute(lsx_vxor_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vxor_v(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2799,7 +3744,7 @@ unsafe fn test_lsx_vxori_b() {
     );
     let r = i64x2::new(3478586993001400570, 4687744515358339026);
 
-    assert_eq!(r, transmute(lsx_vxori_b::<225>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vxori_b::<225>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2817,7 +3762,11 @@ unsafe fn test_lsx_vbitsel_v() {
 
     assert_eq!(
         r,
-        transmute(lsx_vbitsel_v(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vbitsel_v(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -2833,7 +3782,10 @@ unsafe fn test_lsx_vbitseli_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vbitseli_b::<65>(transmute(a), transmute(b)))
+        transmute(lsx_vbitseli_b::<65>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -2844,7 +3796,7 @@ unsafe fn test_lsx_vshuf4i_b() {
     );
     let r = i64x2::new(3937170420478429898, -3347145886530736916);
 
-    assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2852,7 +3804,7 @@ unsafe fn test_lsx_vshuf4i_h() {
     let a = i16x8::new(27707, -1094, -15784, -28387, 31634, -12323, -30387, -11480);
     let r = i64x2::new(-7989953385787032646, -3231104182470389795);
 
-    assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2860,35 +3812,38 @@ unsafe fn test_lsx_vshuf4i_w() {
     let a = i32x4::new(768986805, -1036149600, -1196682940, -214444511);
     let r = i64x2::new(3302773179299516085, -5139714087882845884);
 
-    assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
 unsafe fn test_lsx_vreplgr2vr_b() {
     let r = i64x2::new(795741901218843403, 795741901218843403);
 
-    assert_eq!(r, transmute(lsx_vreplgr2vr_b(970839819)));
+    assert_eq!(r, transmute(lsx_vreplgr2vr_b(black_box(970839819))));
 }
 
 #[simd_test(enable = "lsx")]
 unsafe fn test_lsx_vreplgr2vr_h() {
     let r = i64x2::new(-6504141532176800324, -6504141532176800324);
 
-    assert_eq!(r, transmute(lsx_vreplgr2vr_h(93693372)));
+    assert_eq!(r, transmute(lsx_vreplgr2vr_h(black_box(93693372))));
 }
 
 #[simd_test(enable = "lsx")]
 unsafe fn test_lsx_vreplgr2vr_w() {
     let r = i64x2::new(-6737078705572473188, -6737078705572473188);
 
-    assert_eq!(r, transmute(lsx_vreplgr2vr_w(-1568598372)));
+    assert_eq!(r, transmute(lsx_vreplgr2vr_w(black_box(-1568598372))));
 }
 
 #[simd_test(enable = "lsx")]
 unsafe fn test_lsx_vreplgr2vr_d() {
     let r = i64x2::new(5000134708087557572, 5000134708087557572);
 
-    assert_eq!(r, transmute(lsx_vreplgr2vr_d(5000134708087557572)));
+    assert_eq!(
+        r,
+        transmute(lsx_vreplgr2vr_d(black_box(5000134708087557572)))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -2898,7 +3853,7 @@ unsafe fn test_lsx_vpcnt_b() {
     );
     let r = i64x2::new(217867142450840068, 145528077781566722);
 
-    assert_eq!(r, transmute(lsx_vpcnt_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpcnt_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2906,7 +3861,7 @@ unsafe fn test_lsx_vpcnt_h() {
     let a = i16x8::new(-512, 10388, -21267, -27094, 1085, -26444, -29360, -11576);
     let r = i64x2::new(1970367786975239, 1970350607237126);
 
-    assert_eq!(r, transmute(lsx_vpcnt_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpcnt_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2914,7 +3869,7 @@ unsafe fn test_lsx_vpcnt_w() {
     let a = i32x4::new(1399276601, -2094725994, -100739325, -1239551533);
     let r = i64x2::new(47244640271, 81604378645);
 
-    assert_eq!(r, transmute(lsx_vpcnt_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpcnt_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2922,7 +3877,7 @@ unsafe fn test_lsx_vpcnt_d() {
     let a = i64x2::new(-4470823169399930539, 3184270543884128372);
     let r = i64x2::new(29, 25);
 
-    assert_eq!(r, transmute(lsx_vpcnt_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpcnt_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2932,7 +3887,7 @@ unsafe fn test_lsx_vclo_b() {
     );
     let r = i64x2::new(72057594071547904, 3311470116864);
 
-    assert_eq!(r, transmute(lsx_vclo_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclo_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2940,7 +3895,7 @@ unsafe fn test_lsx_vclo_h() {
     let a = i16x8::new(-5432, 27872, -9150, 27393, 25236, 1028, -21312, -25189);
     let r = i64x2::new(8589934595, 281479271677952);
 
-    assert_eq!(r, transmute(lsx_vclo_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclo_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2948,7 +3903,7 @@ unsafe fn test_lsx_vclo_w() {
     let a = i32x4::new(1214322611, -1755838761, -1222326743, -1511364419);
     let r = i64x2::new(4294967296, 4294967297);
 
-    assert_eq!(r, transmute(lsx_vclo_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclo_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2956,7 +3911,7 @@ unsafe fn test_lsx_vclo_d() {
     let a = i64x2::new(-249299854527467825, -459308653408461862);
     let r = i64x2::new(6, 5);
 
-    assert_eq!(r, transmute(lsx_vclo_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclo_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2966,7 +3921,7 @@ unsafe fn test_lsx_vclz_b() {
     );
     let r = i64x2::new(144116287587483648, 72903118479688195);
 
-    assert_eq!(r, transmute(lsx_vclz_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2974,7 +3929,7 @@ unsafe fn test_lsx_vclz_h() {
     let a = i16x8::new(1222, 32426, 3164, -10763, 10189, -4197, -21841, -28676);
     let r = i64x2::new(17179934725, 2);
 
-    assert_eq!(r, transmute(lsx_vclz_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2982,7 +3937,7 @@ unsafe fn test_lsx_vclz_w() {
     let a = i32x4::new(-490443689, -1039971379, -217310592, -1921086575);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vclz_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -2990,7 +3945,7 @@ unsafe fn test_lsx_vclz_d() {
     let a = i64x2::new(4630351532137644314, -6587611980764816064);
     let r = i64x2::new(1, 0);
 
-    assert_eq!(r, transmute(lsx_vclz_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vclz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3000,7 +3955,10 @@ unsafe fn test_lsx_vpickve2gr_b() {
     );
     let r: i32 = 51;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_b::<15>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickve2gr_b::<15>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3008,7 +3966,7 @@ unsafe fn test_lsx_vpickve2gr_h() {
     let a = i16x8::new(-12924, 31013, 18171, 20404, 21226, 14128, -6255, 26521);
     let r: i32 = 21226;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3016,7 +3974,7 @@ unsafe fn test_lsx_vpickve2gr_w() {
     let a = i32x4::new(-1559379275, 2065542381, -1882161334, 1502157419);
     let r: i32 = -1882161334;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3024,7 +3982,7 @@ unsafe fn test_lsx_vpickve2gr_d() {
     let a = i64x2::new(-6941380853339482104, 8405634758774935528);
     let r: i64 = -6941380853339482104;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3034,7 +3992,10 @@ unsafe fn test_lsx_vpickve2gr_bu() {
     );
     let r: u32 = 199;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_bu::<8>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickve2gr_bu::<8>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3042,7 +4003,10 @@ unsafe fn test_lsx_vpickve2gr_hu() {
     let a = i16x8::new(25003, 5139, -12977, 7550, -12177, 19294, -2216, 12693);
     let r: u32 = 25003;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_hu::<0>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickve2gr_hu::<0>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3050,7 +4014,10 @@ unsafe fn test_lsx_vpickve2gr_wu() {
     let a = i32x4::new(-295894883, 551663550, -710853968, 82692774);
     let r: u32 = 3999072413;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_wu::<0>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickve2gr_wu::<0>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3058,7 +4025,10 @@ unsafe fn test_lsx_vpickve2gr_du() {
     let a = i64x2::new(748282319555413922, -1352335765832355666);
     let r: u64 = 748282319555413922;
 
-    assert_eq!(r, transmute(lsx_vpickve2gr_du::<0>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vpickve2gr_du::<0>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3070,7 +4040,7 @@ unsafe fn test_lsx_vinsgr2vr_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vinsgr2vr_b::<14>(transmute(a), 1333652061))
+        transmute(lsx_vinsgr2vr_b::<14>(black_box(transmute(a)), 1333652061))
     );
 }
 
@@ -3079,7 +4049,10 @@ unsafe fn test_lsx_vinsgr2vr_h() {
     let a = i16x8::new(-20591, 7819, 25287, -11296, 4604, 28833, -1306, 6418);
     let r = i64x2::new(-3179432729573085295, 1806782266980897276);
 
-    assert_eq!(r, transmute(lsx_vinsgr2vr_h::<5>(transmute(a), -987420193)));
+    assert_eq!(
+        r,
+        transmute(lsx_vinsgr2vr_h::<5>(black_box(transmute(a)), -987420193))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3087,7 +4060,10 @@ unsafe fn test_lsx_vinsgr2vr_w() {
     let a = i32x4::new(1608179655, 886830932, -621638499, 2021214690);
     let r = i64x2::new(3808909851629379527, 8681050995079237782);
 
-    assert_eq!(r, transmute(lsx_vinsgr2vr_w::<2>(transmute(a), -960507754)));
+    assert_eq!(
+        r,
+        transmute(lsx_vinsgr2vr_w::<2>(black_box(transmute(a)), -960507754))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3095,7 +4071,10 @@ unsafe fn test_lsx_vinsgr2vr_d() {
     let a = i64x2::new(-6562091001143116290, -2425423285843953307);
     let r = i64x2::new(-6562091001143116290, -233659266);
 
-    assert_eq!(r, transmute(lsx_vinsgr2vr_d::<1>(transmute(a), -233659266)));
+    assert_eq!(
+        r,
+        transmute(lsx_vinsgr2vr_d::<1>(black_box(transmute(a)), -233659266))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3104,7 +4083,13 @@ unsafe fn test_lsx_vfadd_s() {
     let b = u32x4::new(1050272808, 1054022924, 1064036136, 1063113730);
     let r = i64x2::new(4588396142719948771, 4567018621615066847);
 
-    assert_eq!(r, transmute(lsx_vfadd_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfadd_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3113,7 +4098,13 @@ unsafe fn test_lsx_vfadd_d() {
     let b = u64x2::new(4605819027271079334, 4601207158507578498);
     let r = i64x2::new(4608685566198055604, 4608371493448991663);
 
-    assert_eq!(r, transmute(lsx_vfadd_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3122,7 +4113,13 @@ unsafe fn test_lsx_vfsub_s() {
     let b = u32x4::new(1063475462, 1045836432, 1065150677, 1042376676);
     let r = i64x2::new(4532926601401089072, 4475386505810184670);
 
-    assert_eq!(r, transmute(lsx_vfsub_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfsub_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3131,7 +4128,13 @@ unsafe fn test_lsx_vfsub_d() {
     let b = u64x2::new(4605973926398825814, 4600156145303017004);
     let r = i64x2::new(-4622342180736116526, 4603750919602422881);
 
-    assert_eq!(r, transmute(lsx_vfsub_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3140,7 +4143,13 @@ unsafe fn test_lsx_vfmul_s() {
     let b = u32x4::new(1065241951, 1044285812, 1050678216, 1009264512);
     let r = i64x2::new(4471727895898079441, 4289440988347233543);
 
-    assert_eq!(r, transmute(lsx_vfmul_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmul_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3149,7 +4158,13 @@ unsafe fn test_lsx_vfmul_d() {
     let b = u64x2::new(4605208047666947899, 4599634375243914522);
     let r = i64x2::new(4591550625791030606, 4595475933048682142);
 
-    assert_eq!(r, transmute(lsx_vfmul_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmul_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3158,7 +4173,13 @@ unsafe fn test_lsx_vfdiv_s() {
     let b = u32x4::new(1055538538, 1042248668, 1061233585, 1063649172);
     let r = i64x2::new(4613180427594946541, 4523223175100126088);
 
-    assert_eq!(r, transmute(lsx_vfdiv_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfdiv_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3167,7 +4188,13 @@ unsafe fn test_lsx_vfdiv_d() {
     let b = u64x2::new(4606326032528596062, 4601783079746725386);
     let r = i64x2::new(4592460108638699314, 4612120084672695832);
 
-    assert_eq!(r, transmute(lsx_vfdiv_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfdiv_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3176,7 +4203,13 @@ unsafe fn test_lsx_vfcvt_h_s() {
     let b = u32x4::new(1049501482, 1043939972, 1042291392, 1041250232);
     let r = i64x2::new(3495410141992989809, 3873441386606634666);
 
-    assert_eq!(r, transmute(lsx_vfcvt_h_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcvt_h_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3185,7 +4218,13 @@ unsafe fn test_lsx_vfcvt_s_d() {
     let b = u64x2::new(4600251021237488420, 4593890179408150924);
     let r = i64x2::new(4469319308295208818, 4496796258465732597);
 
-    assert_eq!(r, transmute(lsx_vfcvt_s_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcvt_s_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3194,7 +4233,13 @@ unsafe fn test_lsx_vfmin_s() {
     let b = u32x4::new(1060093085, 1026130528, 1057322097, 1057646773);
     let r = i64x2::new(4407197060203522560, 4542558301798153756);
 
-    assert_eq!(r, transmute(lsx_vfmin_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmin_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3203,7 +4248,13 @@ unsafe fn test_lsx_vfmin_d() {
     let b = u64x2::new(4584808359801648672, 4602712060570539582);
     let r = i64x2::new(4584808359801648672, 4602712060570539582);
 
-    assert_eq!(r, transmute(lsx_vfmin_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmin_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3212,7 +4263,13 @@ unsafe fn test_lsx_vfmina_s() {
     let b = u32x4::new(1049119234, 1058336224, 1057046116, 1029386720);
     let r = i64x2::new(4519411155382848002, 4421182298393539560);
 
-    assert_eq!(r, transmute(lsx_vfmina_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmina_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3221,7 +4278,13 @@ unsafe fn test_lsx_vfmina_d() {
     let b = u64x2::new(4599088744110071826, 4598732503789588496);
     let r = i64x2::new(4599088744110071826, 4598732503789588496);
 
-    assert_eq!(r, transmute(lsx_vfmina_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmina_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3230,7 +4293,13 @@ unsafe fn test_lsx_vfmax_s() {
     let b = u32x4::new(1042175760, 1040826492, 1059132266, 1050815434);
     let r = i64x2::new(4557520760982391874, 4573984521684325226);
 
-    assert_eq!(r, transmute(lsx_vfmax_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmax_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3239,7 +4308,13 @@ unsafe fn test_lsx_vfmax_d() {
     let b = u64x2::new(4593616624275112016, 4605244843740986156);
     let r = i64x2::new(4606275407710467505, 4605244843740986156);
 
-    assert_eq!(r, transmute(lsx_vfmax_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmax_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3248,7 +4323,13 @@ unsafe fn test_lsx_vfmaxa_s() {
     let b = u32x4::new(1064739422, 1055122552, 1049654310, 1057411362);
     let r = i64x2::new(4531716855176798814, 4541547219258471462);
 
-    assert_eq!(r, transmute(lsx_vfmaxa_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmaxa_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3257,7 +4338,13 @@ unsafe fn test_lsx_vfmaxa_d() {
     let b = u64x2::new(4603647289310579471, 4603999027307573908);
     let r = i64x2::new(4603647289310579471, 4606304546706191737);
 
-    assert_eq!(r, transmute(lsx_vfmaxa_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfmaxa_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3265,7 +4352,7 @@ unsafe fn test_lsx_vfclass_s() {
     let a = u32x4::new(1059786314, 1058231666, 1061513647, 1038650488);
     let r = i64x2::new(549755814016, 549755814016);
 
-    assert_eq!(r, transmute(lsx_vfclass_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfclass_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3273,7 +4360,7 @@ unsafe fn test_lsx_vfclass_d() {
     let a = u64x2::new(4601724705608768104, 4601126152607382566);
     let r = i64x2::new(128, 128);
 
-    assert_eq!(r, transmute(lsx_vfclass_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfclass_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3281,7 +4368,7 @@ unsafe fn test_lsx_vfsqrt_s() {
     let a = u32x4::new(1055398716, 1050305974, 995168768, 1064901995);
     let r = i64x2::new(4543169501430832482, 4574681629207255333);
 
-    assert_eq!(r, transmute(lsx_vfsqrt_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfsqrt_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3289,7 +4376,7 @@ unsafe fn test_lsx_vfsqrt_d() {
     let a = u64x2::new(4605784293613801157, 4602267946351406890);
     let r = i64x2::new(4606453893731357485, 4604397310232711799);
 
-    assert_eq!(r, transmute(lsx_vfsqrt_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfsqrt_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3297,7 +4384,7 @@ unsafe fn test_lsx_vfrecip_s() {
     let a = u32x4::new(1003452672, 1050811504, 1044295808, 1064402913);
     let r = i64x2::new(4632552602764963931, 4577820515916044016);
 
-    assert_eq!(r, transmute(lsx_vfrecip_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrecip_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3305,7 +4392,7 @@ unsafe fn test_lsx_vfrecip_d() {
     let a = u64x2::new(4598634931235673106, 4598630619264835010);
     let r = i64x2::new(4615355353482170689, 4615362460048142095);
 
-    assert_eq!(r, transmute(lsx_vfrecip_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrecip_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx,frecipe")]
@@ -3313,7 +4400,7 @@ unsafe fn test_lsx_vfrecipe_s() {
     let a = u32x4::new(1057583779, 1062308847, 1060089100, 1048454688);
     let r = i64x2::new(4583644530211711115, 4647978179615164140);
 
-    assert_eq!(r, transmute(lsx_vfrecipe_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrecipe_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx,frecipe")]
@@ -3321,7 +4408,7 @@ unsafe fn test_lsx_vfrecipe_d() {
     let a = u64x2::new(4605515926442181274, 4605369703273365674);
     let r = i64x2::new(4608204937770303488, 4608317161507651584);
 
-    assert_eq!(r, transmute(lsx_vfrecipe_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrecipe_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx,frecipe")]
@@ -3329,7 +4416,7 @@ unsafe fn test_lsx_vfrsqrte_s() {
     let a = u32x4::new(1064377488, 1055815904, 1056897740, 1064016656);
     let r = i64x2::new(4592421282989204764, 4577184195020153336);
 
-    assert_eq!(r, transmute(lsx_vfrsqrte_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrsqrte_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx,frecipe")]
@@ -3337,7 +4424,7 @@ unsafe fn test_lsx_vfrsqrte_d() {
     let a = u64x2::new(4602766865443628663, 4605323203937791867);
     let r = i64x2::new(4608986772678901760, 4607734355383549952);
 
-    assert_eq!(r, transmute(lsx_vfrsqrte_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrsqrte_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3345,7 +4432,7 @@ unsafe fn test_lsx_vfrint_s() {
     let a = u32x4::new(1062138521, 1056849108, 1034089720, 1038314384);
     let r = i64x2::new(1065353216, 0);
 
-    assert_eq!(r, transmute(lsx_vfrint_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrint_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3353,7 +4440,7 @@ unsafe fn test_lsx_vfrint_d() {
     let a = u64x2::new(4598620052333442366, 4603262362368837514);
     let r = i64x2::new(0, 4607182418800017408);
 
-    assert_eq!(r, transmute(lsx_vfrint_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrint_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3361,7 +4448,7 @@ unsafe fn test_lsx_vfrsqrt_s() {
     let a = u32x4::new(1058614029, 1050504950, 1013814976, 1062355001);
     let r = i64x2::new(4604601921912011494, 4579384257679777264);
 
-    assert_eq!(r, transmute(lsx_vfrsqrt_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrsqrt_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3369,7 +4456,7 @@ unsafe fn test_lsx_vfrsqrt_d() {
     let a = u64x2::new(4602924191185043139, 4606088351077917251);
     let r = i64x2::new(4608881149202581394, 4607483676176768181);
 
-    assert_eq!(r, transmute(lsx_vfrsqrt_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrsqrt_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3377,7 +4464,7 @@ unsafe fn test_lsx_vflogb_s() {
     let a = u32x4::new(1053488512, 1061429282, 1064965594, 1061326585);
     let r = i64x2::new(-4647714812225126400, -4647714812233515008);
 
-    assert_eq!(r, transmute(lsx_vflogb_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vflogb_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3385,7 +4472,7 @@ unsafe fn test_lsx_vflogb_d() {
     let a = u64x2::new(4589481276789128632, 4599408395082246526);
     let r = i64x2::new(-4607182418800017408, -4611686018427387904);
 
-    assert_eq!(r, transmute(lsx_vflogb_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vflogb_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3393,7 +4480,7 @@ unsafe fn test_lsx_vfcvth_s_h() {
     let a = i16x8::new(29550, -13884, 689, -1546, 24006, -19112, -12769, 1779);
     let r = i64x2::new(-4707668984349540352, 4097818267320836096);
 
-    assert_eq!(r, transmute(lsx_vfcvth_s_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfcvth_s_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3401,7 +4488,7 @@ unsafe fn test_lsx_vfcvth_d_s() {
     let a = u32x4::new(1051543000, 1042275304, 1038283216, 1063876621);
     let r = i64x2::new(4592649323212177408, 4606389677895712768);
 
-    assert_eq!(r, transmute(lsx_vfcvth_d_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfcvth_d_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3409,7 +4496,7 @@ unsafe fn test_lsx_vfcvtl_s_h() {
     let a = i16x8::new(-21951, -13772, -17190, 9566, -19227, 9682, 13427, -30861);
     let r = i64x2::new(-4519784435355738112, 4371798972740354048);
 
-    assert_eq!(r, transmute(lsx_vfcvtl_s_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfcvtl_s_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3417,7 +4504,7 @@ unsafe fn test_lsx_vfcvtl_d_s() {
     let a = u32x4::new(1059809930, 1051084496, 1062618346, 1058273673);
     let r = i64x2::new(4604206389789720576, 4599521958080544768);
 
-    assert_eq!(r, transmute(lsx_vfcvtl_d_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfcvtl_d_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3425,7 +4512,7 @@ unsafe fn test_lsx_vftint_w_s() {
     let a = u32x4::new(1064738153, 1040181800, 1064331056, 1050732566);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftint_w_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftint_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3433,7 +4520,7 @@ unsafe fn test_lsx_vftint_l_d() {
     let a = u64x2::new(4602244632405616462, 4606437548563176328);
     let r = i64x2::new(0, 1);
 
-    assert_eq!(r, transmute(lsx_vftint_l_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftint_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3441,7 +4528,7 @@ unsafe fn test_lsx_vftint_wu_s() {
     let a = u32x4::new(1051598962, 1051261298, 1059326008, 1057784192);
     let r = i64x2::new(0, 4294967297);
 
-    assert_eq!(r, transmute(lsx_vftint_wu_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftint_wu_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3449,7 +4536,7 @@ unsafe fn test_lsx_vftint_lu_d() {
     let a = u64x2::new(4605561240422589260, 4595241299507769712);
     let r = i64x2::new(1, 0);
 
-    assert_eq!(r, transmute(lsx_vftint_lu_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftint_lu_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3457,7 +4544,7 @@ unsafe fn test_lsx_vftintrz_w_s() {
     let a = u32x4::new(1027659872, 1064207676, 1058472873, 1055740014);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrz_w_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrz_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3465,7 +4552,7 @@ unsafe fn test_lsx_vftintrz_l_d() {
     let a = u64x2::new(4605051539601556532, 4605129242354661923);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrz_l_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrz_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3473,7 +4560,7 @@ unsafe fn test_lsx_vftintrz_wu_s() {
     let a = u32x4::new(1060876751, 1053710034, 1057340881, 1055555596);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrz_wu_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrz_wu_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3481,7 +4568,7 @@ unsafe fn test_lsx_vftintrz_lu_d() {
     let a = u64x2::new(4598711097624940956, 4598268778109474002);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrz_lu_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrz_lu_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3489,7 +4576,7 @@ unsafe fn test_lsx_vffint_s_w() {
     let a = i32x4::new(81337967, 1396520141, 2124859806, 1655115736);
     let r = i64x2::new(5667351778062705614, 5676028806041521555);
 
-    assert_eq!(r, transmute(lsx_vffint_s_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vffint_s_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3497,7 +4584,7 @@ unsafe fn test_lsx_vffint_d_l() {
     let a = i64x2::new(-1543454772280682525, -7672333112582708041);
     let r = i64x2::new(-4344448119835677720, -4333977527979901593);
 
-    assert_eq!(r, transmute(lsx_vffint_d_l(transmute(a))));
+    assert_eq!(r, transmute(lsx_vffint_d_l(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3505,7 +4592,7 @@ unsafe fn test_lsx_vffint_s_wu() {
     let a = u32x4::new(2224947834, 194720725, 2248289069, 1131100007);
     let r = i64x2::new(5564675890493038082, 5658445755393114667);
 
-    assert_eq!(r, transmute(lsx_vffint_s_wu(transmute(a))));
+    assert_eq!(r, transmute(lsx_vffint_s_wu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3513,7 +4600,7 @@ unsafe fn test_lsx_vffint_d_lu() {
     let a = u64x2::new(11793247389644223387, 1356636411353166515);
     let r = i64x2::new(4892164017273962878, 4878194157796724979);
 
-    assert_eq!(r, transmute(lsx_vffint_d_lu(transmute(a))));
+    assert_eq!(r, transmute(lsx_vffint_d_lu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3526,7 +4613,13 @@ unsafe fn test_lsx_vandn_v() {
     );
     let r = i64x2::new(184648152262214664, 2315143230533931624);
 
-    assert_eq!(r, transmute(lsx_vandn_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vandn_v(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3536,7 +4629,7 @@ unsafe fn test_lsx_vneg_b() {
     );
     let r = i64x2::new(-6195839201974406282, 3566844512212398771);
 
-    assert_eq!(r, transmute(lsx_vneg_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vneg_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3544,7 +4637,7 @@ unsafe fn test_lsx_vneg_h() {
     let a = i16x8::new(-6540, 25893, -2534, 29805, -28719, -16331, -20168, 14650);
     let r = i64x2::new(-8389350794815923828, -4123521786840387537);
 
-    assert_eq!(r, transmute(lsx_vneg_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vneg_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3552,7 +4645,7 @@ unsafe fn test_lsx_vneg_w() {
     let a = i32x4::new(-927815384, -898911982, 716171852, -2025175544);
     let r = i64x2::new(3860797565600356056, 8698062733717804468);
 
-    assert_eq!(r, transmute(lsx_vneg_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vneg_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3560,7 +4653,7 @@ unsafe fn test_lsx_vneg_d() {
     let a = i64x2::new(4241851098775470984, 2487122929432859927);
     let r = i64x2::new(-4241851098775470984, -2487122929432859927);
 
-    assert_eq!(r, transmute(lsx_vneg_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vneg_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3573,7 +4666,10 @@ unsafe fn test_lsx_vmuh_b() {
     );
     let r = i64x2::new(931993372669836524, 2017024359980467698);
 
-    assert_eq!(r, transmute(lsx_vmuh_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_b(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3582,7 +4678,10 @@ unsafe fn test_lsx_vmuh_h() {
     let b = i16x8::new(-446, -16863, 19467, -13578, -9673, -26572, -7864, 9855);
     let r = i64x2::new(-1422322400225984462, -842721997477184351);
 
-    assert_eq!(r, transmute(lsx_vmuh_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_h(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3591,7 +4690,10 @@ unsafe fn test_lsx_vmuh_w() {
     let b = i32x4::new(-1684820454, 449222301, 1106076122, 431017950);
     let r = i64x2::new(-950505610786872114, 420439596918869732);
 
-    assert_eq!(r, transmute(lsx_vmuh_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_w(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3600,7 +4702,10 @@ unsafe fn test_lsx_vmuh_d() {
     let b = i64x2::new(-1208434038665242614, -6078343251861677818);
     let r = i64x2::new(-121343209662433286, 284995587689374477);
 
-    assert_eq!(r, transmute(lsx_vmuh_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_d(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3613,7 +4718,13 @@ unsafe fn test_lsx_vmuh_bu() {
     );
     let r = i64x2::new(8725461799780227590, -3369022092985820632);
 
-    assert_eq!(r, transmute(lsx_vmuh_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3622,7 +4733,13 @@ unsafe fn test_lsx_vmuh_hu() {
     let b = u16x8::new(14769, 6489, 58866, 5997, 46648, 26325, 42186, 26942);
     let r = i64x2::new(1572068217944938757, 4366267597274655896);
 
-    assert_eq!(r, transmute(lsx_vmuh_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3631,7 +4748,13 @@ unsafe fn test_lsx_vmuh_wu() {
     let b = u32x4::new(1981234883, 1290836259, 1284878577, 702668871);
     let r = i64x2::new(4011887256539048298, 960560772888018584);
 
-    assert_eq!(r, transmute(lsx_vmuh_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3640,7 +4763,13 @@ unsafe fn test_lsx_vmuh_du() {
     let b = u64x2::new(14805542397189366587, 10025341254588295994);
     let r = i64x2::new(-9132083796568587258, 2493261783600858707);
 
-    assert_eq!(r, transmute(lsx_vmuh_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmuh_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3650,7 +4779,7 @@ unsafe fn test_lsx_vsllwil_h_b() {
     );
     let r = i64x2::new(-990777899147527584, 126109727303143360);
 
-    assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3658,7 +4787,7 @@ unsafe fn test_lsx_vsllwil_w_h() {
     let a = i16x8::new(25135, -4241, 25399, -32451, 5597, -16847, 3192, -14694);
     let r = i64x2::new(-9326057613926912, -71360503652913664);
 
-    assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3666,7 +4795,7 @@ unsafe fn test_lsx_vsllwil_d_w() {
     let a = i32x4::new(1472328927, -2106442262, 379100488, -607174188);
     let r = i64x2::new(6030659284992, -8627987505152);
 
-    assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -3676,7 +4805,10 @@ unsafe fn test_lsx_vsllwil_hu_bu() {
     );
     let r = i64x2::new(6953679870551405312, 6809531147446388736);
 
-    assert_eq!(r, transmute(lsx_vsllwil_hu_bu::<7>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsllwil_hu_bu::<7>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3684,7 +4816,10 @@ unsafe fn test_lsx_vsllwil_wu_hu() {
     let a = u16x8::new(370, 47410, 29611, 6206, 10390, 34658, 65264, 5264);
     let r = i64x2::new(52127846272954880, 6823569169558272);
 
-    assert_eq!(r, transmute(lsx_vsllwil_wu_hu::<8>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsllwil_wu_hu::<8>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3692,7 +4827,10 @@ unsafe fn test_lsx_vsllwil_du_wu() {
     let a = u32x4::new(3249798491, 4098547305, 1101510259, 3478509641);
     let r = i64x2::new(13630642809995264, 17190553355550720);
 
-    assert_eq!(r, transmute(lsx_vsllwil_du_wu::<22>(transmute(a))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsllwil_du_wu::<22>(black_box(transmute(a))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3701,7 +4839,13 @@ unsafe fn test_lsx_vsran_b_h() {
     let b = i16x8::new(-12507, -16997, -17826, 5682, -298, -28572, -8117, -13478);
     let r = i64x2::new(-864943573596831881, 0);
 
-    assert_eq!(r, transmute(lsx_vsran_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsran_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3710,7 +4854,13 @@ unsafe fn test_lsx_vsran_h_w() {
     let b = i32x4::new(-52337348, -677553123, -58200260, -1473338606);
     let r = i64x2::new(1267763303694925820, 0);
 
-    assert_eq!(r, transmute(lsx_vsran_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsran_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3719,7 +4869,13 @@ unsafe fn test_lsx_vsran_w_d() {
     let b = i64x2::new(-8585295495893484131, -2657141976436452013);
     let r = i64x2::new(-5882350952887806270, 0);
 
-    assert_eq!(r, transmute(lsx_vsran_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsran_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3728,7 +4884,13 @@ unsafe fn test_lsx_vssran_b_h() {
     let b = i16x8::new(9459, 15241, 22170, 28027, 5348, 14784, 22613, -9469);
     let r = i64x2::new(9187483431610086528, 0);
 
-    assert_eq!(r, transmute(lsx_vssran_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssran_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3737,7 +4899,13 @@ unsafe fn test_lsx_vssran_h_w() {
     let b = i32x4::new(2070726003, -944816867, -160621862, -1222036466);
     let r = i64x2::new(-5219109151313101350, 0);
 
-    assert_eq!(r, transmute(lsx_vssran_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssran_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3746,7 +4914,13 @@ unsafe fn test_lsx_vssran_w_d() {
     let b = i64x2::new(-7078666005882550400, -2564990402652718339);
     let r = i64x2::new(-15032385536, 0);
 
-    assert_eq!(r, transmute(lsx_vssran_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssran_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3755,7 +4929,13 @@ unsafe fn test_lsx_vssran_bu_h() {
     let b = u16x8::new(2372, 26267, 4722, 47876, 44857, 55242, 45998, 51450);
     let r = i64x2::new(47227865344, 0);
 
-    assert_eq!(r, transmute(lsx_vssran_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssran_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3764,7 +4944,13 @@ unsafe fn test_lsx_vssran_hu_w() {
     let b = u32x4::new(2085279153, 2679576985, 2935643238, 3797496208);
     let r = i64x2::new(281470684234479, 0);
 
-    assert_eq!(r, transmute(lsx_vssran_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssran_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3773,7 +4959,13 @@ unsafe fn test_lsx_vssran_wu_d() {
     let b = u64x2::new(3904652404244024971, 4230656884168675704);
     let r = i64x2::new(536870912000, 0);
 
-    assert_eq!(r, transmute(lsx_vssran_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssran_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3782,7 +4974,13 @@ unsafe fn test_lsx_vsrarn_b_h() {
     let b = i16x8::new(-19071, -903, 11542, -25909, 24111, 14882, -27192, -8283);
     let r = i64x2::new(7076043428318610384, 0);
 
-    assert_eq!(r, transmute(lsx_vsrarn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrarn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3791,7 +4989,13 @@ unsafe fn test_lsx_vsrarn_h_w() {
     let b = i32x4::new(-1571698573, 1467958613, -1857488008, 424713310);
     let r = i64x2::new(498163119212, 0);
 
-    assert_eq!(r, transmute(lsx_vsrarn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrarn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3800,7 +5004,13 @@ unsafe fn test_lsx_vsrarn_w_d() {
     let b = i64x2::new(-8645668865455529235, -3129277582817496880);
     let r = i64x2::new(-8628090759335017621, 0);
 
-    assert_eq!(r, transmute(lsx_vsrarn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrarn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3809,7 +5019,13 @@ unsafe fn test_lsx_vssrarn_b_h() {
     let b = i16x8::new(24298, 2343, 24641, 20910, 3142, -1171, 25850, 15932);
     let r = i64x2::new(-148338468081139694, 0);
 
-    assert_eq!(r, transmute(lsx_vssrarn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrarn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3818,7 +5034,13 @@ unsafe fn test_lsx_vssrarn_h_w() {
     let b = i32x4::new(1911424854, -931292983, -1710824608, -1179580317);
     let r = i64x2::new(-9223231301513904204, 0);
 
-    assert_eq!(r, transmute(lsx_vssrarn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrarn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3827,7 +5049,13 @@ unsafe fn test_lsx_vssrarn_w_d() {
     let b = i64x2::new(2843689038926761304, -6830262024912907383);
     let r = i64x2::new(-9223372034707292161, 0);
 
-    assert_eq!(r, transmute(lsx_vssrarn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrarn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3836,7 +5064,13 @@ unsafe fn test_lsx_vssrarn_bu_h() {
     let b = u16x8::new(60210, 40155, 14296, 25577, 1550, 1674, 5330, 10645);
     let r = i64x2::new(10999415373897, 0);
 
-    assert_eq!(r, transmute(lsx_vssrarn_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrarn_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3845,7 +5079,13 @@ unsafe fn test_lsx_vssrarn_hu_w() {
     let b = u32x4::new(3570029841, 3229468238, 1070101998, 3159433736);
     let r = i64x2::new(281474976645120, 0);
 
-    assert_eq!(r, transmute(lsx_vssrarn_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrarn_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3854,7 +5094,13 @@ unsafe fn test_lsx_vssrarn_wu_d() {
     let b = u64x2::new(1112771813772164907, 646071836375127186);
     let r = i64x2::new(963446, 0);
 
-    assert_eq!(r, transmute(lsx_vssrarn_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrarn_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3863,7 +5109,13 @@ unsafe fn test_lsx_vsrln_b_h() {
     let b = i16x8::new(-11667, 13077, -23656, 5150, -23771, -31329, 20729, 15169);
     let r = i64x2::new(23363148983015937, 0);
 
-    assert_eq!(r, transmute(lsx_vsrln_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrln_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3872,7 +5124,13 @@ unsafe fn test_lsx_vsrln_h_w() {
     let b = i32x4::new(1775989751, -1602688801, -801213995, -1801759515);
     let r = i64x2::new(-7033214568759295968, 0);
 
-    assert_eq!(r, transmute(lsx_vsrln_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrln_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3881,7 +5139,13 @@ unsafe fn test_lsx_vsrln_w_d() {
     let b = i64x2::new(-1428152872702150626, 3907864416256094744);
     let r = i64x2::new(-8718771486483115547, 0);
 
-    assert_eq!(r, transmute(lsx_vsrln_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrln_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3890,7 +5154,13 @@ unsafe fn test_lsx_vssrln_bu_h() {
     let b = u16x8::new(41072, 41125, 44619, 49581, 20733, 905, 47558, 7801);
     let r = i64x2::new(8862857593125412863, 0);
 
-    assert_eq!(r, transmute(lsx_vssrln_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrln_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3899,7 +5169,13 @@ unsafe fn test_lsx_vssrln_hu_w() {
     let b = u32x4::new(1325069171, 1380839173, 3495604120, 2839043866);
     let r = i64x2::new(16889194387279379, 0);
 
-    assert_eq!(r, transmute(lsx_vssrln_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrln_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3908,7 +5184,13 @@ unsafe fn test_lsx_vssrln_wu_d() {
     let b = u64x2::new(3908262745817581251, 17131627096934512209);
     let r = i64x2::new(-1, 0);
 
-    assert_eq!(r, transmute(lsx_vssrln_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrln_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3917,7 +5199,13 @@ unsafe fn test_lsx_vsrlrn_b_h() {
     let b = i16x8::new(22830, -27866, -24616, -9547, 11336, 320, 19908, 7056);
     let r = i64x2::new(-4888418841542521598, 0);
 
-    assert_eq!(r, transmute(lsx_vsrlrn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlrn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3926,7 +5214,13 @@ unsafe fn test_lsx_vsrlrn_h_w() {
     let b = i32x4::new(1387862348, 119424523, 185407104, 1890720739);
     let r = i64x2::new(2222313691660711041, 0);
 
-    assert_eq!(r, transmute(lsx_vsrlrn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlrn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3935,7 +5229,13 @@ unsafe fn test_lsx_vsrlrn_w_d() {
     let b = i64x2::new(-8550351213501194562, 7071641301481388656);
     let r = i64x2::new(182866822561795, 0);
 
-    assert_eq!(r, transmute(lsx_vsrlrn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsrlrn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3944,7 +5244,13 @@ unsafe fn test_lsx_vssrlrn_bu_h() {
     let b = u16x8::new(51122, 39148, 45511, 57479, 62603, 43668, 5537, 61004);
     let r = i64x2::new(432344477600776959, 0);
 
-    assert_eq!(r, transmute(lsx_vssrlrn_bu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrlrn_bu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3953,7 +5259,13 @@ unsafe fn test_lsx_vssrlrn_hu_w() {
     let b = u32x4::new(1618795892, 3678356443, 862445734, 2115250342);
     let r = i64x2::new(-4293983341, 0);
 
-    assert_eq!(r, transmute(lsx_vssrlrn_hu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrlrn_hu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3962,7 +5274,13 @@ unsafe fn test_lsx_vssrlrn_wu_d() {
     let b = u64x2::new(13406765083608623828, 7214649593148131096);
     let r = i64x2::new(-1, 0);
 
-    assert_eq!(r, transmute(lsx_vssrlrn_wu_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrlrn_wu_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -3977,7 +5295,10 @@ unsafe fn test_lsx_vfrstpi_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfrstpi_b::<28>(transmute(a), transmute(b)))
+        transmute(lsx_vfrstpi_b::<28>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -3987,7 +5308,13 @@ unsafe fn test_lsx_vfrstpi_h() {
     let b = i16x8::new(9590, -8044, 15088, 4172, 1721, 27581, -19895, -25679);
     let r = i64x2::new(-4160352588467724069, 5959935604366651239);
 
-    assert_eq!(r, transmute(lsx_vfrstpi_h::<1>(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfrstpi_h::<1>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4005,7 +5332,11 @@ unsafe fn test_lsx_vfrstp_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfrstp_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfrstp_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4018,7 +5349,11 @@ unsafe fn test_lsx_vfrstp_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfrstp_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfrstp_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4030,7 +5365,10 @@ unsafe fn test_lsx_vshuf4i_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vshuf4i_d::<153>(transmute(a), transmute(b)))
+        transmute(lsx_vshuf4i_d::<153>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -4041,7 +5379,7 @@ unsafe fn test_lsx_vbsrl_v() {
     );
     let r = i64x2::new(4570595419764160432, 56);
 
-    assert_eq!(r, transmute(lsx_vbsrl_v::<7>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbsrl_v::<7>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4051,7 +5389,7 @@ unsafe fn test_lsx_vbsll_v() {
     );
     let r = i64x2::new(0, -1801439850948198400);
 
-    assert_eq!(r, transmute(lsx_vbsll_v::<15>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vbsll_v::<15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4066,7 +5404,10 @@ unsafe fn test_lsx_vextrins_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vextrins_b::<21>(transmute(a), transmute(b)))
+        transmute(lsx_vextrins_b::<21>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -4078,7 +5419,10 @@ unsafe fn test_lsx_vextrins_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vextrins_h::<33>(transmute(a), transmute(b)))
+        transmute(lsx_vextrins_h::<33>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -4090,7 +5434,10 @@ unsafe fn test_lsx_vextrins_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vextrins_w::<57>(transmute(a), transmute(b)))
+        transmute(lsx_vextrins_w::<57>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -4102,7 +5449,10 @@ unsafe fn test_lsx_vextrins_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vextrins_d::<62>(transmute(a), transmute(b)))
+        transmute(lsx_vextrins_d::<62>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -4113,7 +5463,7 @@ unsafe fn test_lsx_vmskltz_b() {
     );
     let r = i64x2::new(40038, 0);
 
-    assert_eq!(r, transmute(lsx_vmskltz_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmskltz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4121,7 +5471,7 @@ unsafe fn test_lsx_vmskltz_h() {
     let a = i16x8::new(16730, 29121, -23447, -8647, -22303, 21817, 30964, -27069);
     let r = i64x2::new(156, 0);
 
-    assert_eq!(r, transmute(lsx_vmskltz_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmskltz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4129,7 +5479,7 @@ unsafe fn test_lsx_vmskltz_w() {
     let a = i32x4::new(-657282776, -1247210048, 162595942, 949871015);
     let r = i64x2::new(3, 0);
 
-    assert_eq!(r, transmute(lsx_vmskltz_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmskltz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4137,7 +5487,7 @@ unsafe fn test_lsx_vmskltz_d() {
     let a = i64x2::new(7728638770319849738, 4250984610820351699);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vmskltz_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmskltz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4150,7 +5500,13 @@ unsafe fn test_lsx_vsigncov_b() {
     );
     let r = i64x2::new(-9074694153930972472, 1986788453588057010);
 
-    assert_eq!(r, transmute(lsx_vsigncov_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsigncov_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4159,7 +5515,13 @@ unsafe fn test_lsx_vsigncov_h() {
     let b = i16x8::new(27367, 4727, -2962, 14937, 26207, -19075, -26630, 10708);
     let r = i64x2::new(-4204122973533661927, -3013866947575178847);
 
-    assert_eq!(r, transmute(lsx_vsigncov_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsigncov_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4168,7 +5530,13 @@ unsafe fn test_lsx_vsigncov_w() {
     let b = i32x4::new(-1719915889, 290419288, 202835952, -1715336967);
     let r = i64x2::new(-1247341342367689359, -7367316170792699888);
 
-    assert_eq!(r, transmute(lsx_vsigncov_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsigncov_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4177,7 +5545,13 @@ unsafe fn test_lsx_vsigncov_d() {
     let b = i64x2::new(-7146260093067324952, -4263419240070336957);
     let r = i64x2::new(-7146260093067324952, 4263419240070336957);
 
-    assert_eq!(r, transmute(lsx_vsigncov_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsigncov_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4189,7 +5563,11 @@ unsafe fn test_lsx_vfmadd_s() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfmadd_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfmadd_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4202,7 +5580,11 @@ unsafe fn test_lsx_vfmadd_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfmadd_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfmadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4215,7 +5597,11 @@ unsafe fn test_lsx_vfmsub_s() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfmsub_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfmsub_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4228,7 +5614,11 @@ unsafe fn test_lsx_vfmsub_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfmsub_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfmsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4241,7 +5631,11 @@ unsafe fn test_lsx_vfnmadd_s() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfnmadd_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4254,7 +5648,11 @@ unsafe fn test_lsx_vfnmadd_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfnmadd_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4267,7 +5665,11 @@ unsafe fn test_lsx_vfnmsub_s() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfnmsub_s(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4280,7 +5682,11 @@ unsafe fn test_lsx_vfnmsub_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vfnmsub_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -4289,7 +5695,7 @@ unsafe fn test_lsx_vftintrne_w_s() {
     let a = u32x4::new(1031214064, 1059673230, 1042813024, 1053602874);
     let r = i64x2::new(4294967296, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrne_w_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrne_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4297,7 +5703,7 @@ unsafe fn test_lsx_vftintrne_l_d() {
     let a = u64x2::new(4606989588359571497, 4604713245380178790);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftintrne_l_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrne_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4305,7 +5711,7 @@ unsafe fn test_lsx_vftintrp_w_s() {
     let a = u32x4::new(1061716225, 1050491008, 1064711040, 1065018777);
     let r = i64x2::new(4294967297, 4294967297);
 
-    assert_eq!(r, transmute(lsx_vftintrp_w_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrp_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4313,7 +5719,7 @@ unsafe fn test_lsx_vftintrp_l_d() {
     let a = u64x2::new(4587516915944025472, 4601504548481216392);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftintrp_l_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrp_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4321,7 +5727,7 @@ unsafe fn test_lsx_vftintrm_w_s() {
     let a = u32x4::new(1045772456, 1065200707, 1061587478, 1035467272);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrm_w_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrm_w_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4329,7 +5735,7 @@ unsafe fn test_lsx_vftintrm_l_d() {
     let a = u64x2::new(4597123259408216804, 4594399417822716772);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrm_l_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrm_l_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4338,7 +5744,13 @@ unsafe fn test_lsx_vftint_w_d() {
     let b = u64x2::new(4606905060326467647, 4606985586417166381);
     let r = i64x2::new(4294967297, 0);
 
-    assert_eq!(r, transmute(lsx_vftint_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vftint_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4347,7 +5759,13 @@ unsafe fn test_lsx_vffint_s_l() {
     let b = i64x2::new(5814449889729512723, -111756032377486319);
     let r = i64x2::new(-2610252963668467161, 6669016150524087533);
 
-    assert_eq!(r, transmute(lsx_vffint_s_l(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vffint_s_l(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4356,7 +5774,13 @@ unsafe fn test_lsx_vftintrz_w_d() {
     let b = u64x2::new(4599106720144900270, 4600531579473237336);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrz_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vftintrz_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4365,7 +5789,13 @@ unsafe fn test_lsx_vftintrp_w_d() {
     let b = u64x2::new(4606104970322966899, 4595679410565085836);
     let r = i64x2::new(4294967297, 4294967297);
 
-    assert_eq!(r, transmute(lsx_vftintrp_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vftintrp_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4374,7 +5804,13 @@ unsafe fn test_lsx_vftintrm_w_d() {
     let b = u64x2::new(4606733822200032543, 4589510164179968984);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrm_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vftintrm_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4383,7 +5819,13 @@ unsafe fn test_lsx_vftintrne_w_d() {
     let b = u64x2::new(4599197176714081204, 4605745859931721980);
     let r = i64x2::new(4294967296, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrne_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vftintrne_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4391,7 +5833,7 @@ unsafe fn test_lsx_vftintl_l_s() {
     let a = u32x4::new(1058856635, 1060563398, 1061422616, 1056124918);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftintl_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintl_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4399,7 +5841,7 @@ unsafe fn test_lsx_vftinth_l_s() {
     let a = u32x4::new(1045383680, 1040752748, 1061879518, 1054801708);
     let r = i64x2::new(1, 0);
 
-    assert_eq!(r, transmute(lsx_vftinth_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftinth_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4407,7 +5849,7 @@ unsafe fn test_lsx_vffinth_d_w() {
     let a = i32x4::new(517100418, -188510766, 949226647, -87467194);
     let r = i64x2::new(4741245898611228672, -4497729803343888384);
 
-    assert_eq!(r, transmute(lsx_vffinth_d_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vffinth_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4415,7 +5857,7 @@ unsafe fn test_lsx_vffintl_d_w() {
     let a = i32x4::new(1273684401, -2137528906, -2109294912, -1646387998);
     let r = i64x2::new(4743129027571613696, -4476619782820462592);
 
-    assert_eq!(r, transmute(lsx_vffintl_d_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vffintl_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4423,7 +5865,7 @@ unsafe fn test_lsx_vftintrzl_l_s() {
     let a = u32x4::new(1031186688, 987838976, 1034565688, 1061017371);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrzl_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrzl_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4431,7 +5873,7 @@ unsafe fn test_lsx_vftintrzh_l_s() {
     let a = u32x4::new(1049433828, 1048953580, 1060964637, 1059899586);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrzh_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrzh_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4439,7 +5881,7 @@ unsafe fn test_lsx_vftintrpl_l_s() {
     let a = u32x4::new(1061834803, 1064858941, 1060475110, 1063896216);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftintrpl_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrpl_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4447,7 +5889,7 @@ unsafe fn test_lsx_vftintrph_l_s() {
     let a = u32x4::new(1059691939, 1065187151, 1059017027, 1061117394);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftintrph_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrph_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4455,7 +5897,7 @@ unsafe fn test_lsx_vftintrml_l_s() {
     let a = u32x4::new(1062985651, 1065211455, 1056421466, 1057373572);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrml_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrml_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4463,7 +5905,7 @@ unsafe fn test_lsx_vftintrmh_l_s() {
     let a = u32x4::new(1050224290, 1063763666, 1057677270, 1063622234);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrmh_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrmh_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4471,7 +5913,7 @@ unsafe fn test_lsx_vftintrnel_l_s() {
     let a = u32x4::new(1060174609, 1050974638, 1047193308, 1062040876);
     let r = i64x2::new(1, 0);
 
-    assert_eq!(r, transmute(lsx_vftintrnel_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrnel_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4479,7 +5921,7 @@ unsafe fn test_lsx_vftintrneh_l_s() {
     let a = u32x4::new(1055675382, 1036879184, 1064176794, 1063791852);
     let r = i64x2::new(1, 1);
 
-    assert_eq!(r, transmute(lsx_vftintrneh_l_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vftintrneh_l_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4487,7 +5929,7 @@ unsafe fn test_lsx_vfrintrne_s() {
     let a = u32x4::new(1054667842, 1061395025, 1062986478, 1062529334);
     let r = i64x2::new(4575657221408423936, 4575657222473777152);
 
-    assert_eq!(r, transmute(lsx_vfrintrne_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrne_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4495,7 +5937,7 @@ unsafe fn test_lsx_vfrintrne_d() {
     let a = u64x2::new(4603260356641870565, 4601614335120512898);
     let r = i64x2::new(4607182418800017408, 0);
 
-    assert_eq!(r, transmute(lsx_vfrintrne_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrne_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4503,7 +5945,7 @@ unsafe fn test_lsx_vfrintrz_s() {
     let a = u32x4::new(1063039577, 1033416832, 1052369306, 1057885024);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfrintrz_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrz_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4511,7 +5953,7 @@ unsafe fn test_lsx_vfrintrz_d() {
     let a = u64x2::new(4601515428088814484, 4604735152905786794);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfrintrz_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4519,7 +5961,7 @@ unsafe fn test_lsx_vfrintrp_s() {
     let a = u32x4::new(1061968959, 1056597596, 1064869916, 1058742360);
     let r = i64x2::new(4575657222473777152, 4575657222473777152);
 
-    assert_eq!(r, transmute(lsx_vfrintrp_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrp_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4527,7 +5969,7 @@ unsafe fn test_lsx_vfrintrp_d() {
     let a = u64x2::new(4603531792479663401, 4587997630530425392);
     let r = i64x2::new(4607182418800017408, 4607182418800017408);
 
-    assert_eq!(r, transmute(lsx_vfrintrp_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrp_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4535,7 +5977,7 @@ unsafe fn test_lsx_vfrintrm_s() {
     let a = u32x4::new(1058024441, 1044087184, 1059777964, 1050835426);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfrintrm_s(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrm_s(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4543,7 +5985,7 @@ unsafe fn test_lsx_vfrintrm_d() {
     let a = u64x2::new(4589388034824743512, 4606800774570289382);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfrintrm_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vfrintrm_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -4556,7 +5998,7 @@ unsafe fn test_lsx_vstelm_b() {
     ];
     let r = i64x2::new(2624488095427530938, -2742340989646681128);
 
-    lsx_vstelm_b::<0, 0>(transmute(a), o.as_mut_ptr());
+    lsx_vstelm_b::<0, 0>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -4568,7 +6010,7 @@ unsafe fn test_lsx_vstelm_h() {
     ];
     let r = i64x2::new(-5777879910580360821, -8010388107109560809);
 
-    lsx_vstelm_h::<0, 1>(transmute(a), o.as_mut_ptr());
+    lsx_vstelm_h::<0, 1>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -4580,7 +6022,7 @@ unsafe fn test_lsx_vstelm_w() {
     ];
     let r = i64x2::new(-7107014201697162202, -4954294907532227136);
 
-    lsx_vstelm_w::<0, 3>(transmute(a), o.as_mut_ptr());
+    lsx_vstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -4592,7 +6034,7 @@ unsafe fn test_lsx_vstelm_d() {
     ];
     let r = i64x2::new(2628828971609511929, -1577551211298588582);
 
-    lsx_vstelm_d::<0, 0>(transmute(a), o.as_mut_ptr());
+    lsx_vstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -4602,7 +6044,13 @@ unsafe fn test_lsx_vaddwev_d_w() {
     let b = i32x4::new(-2105551735, -1478351177, 1027048582, -607110700);
     let r = i64x2::new(-3995454036, 2115628395);
 
-    assert_eq!(r, transmute(lsx_vaddwev_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4611,7 +6059,13 @@ unsafe fn test_lsx_vaddwev_w_h() {
     let b = i16x8::new(-17479, -32614, 24343, 25426, -14077, -12419, 10115, 23013);
     let r = i64x2::new(57531086920254, -11304353922851);
 
-    assert_eq!(r, transmute(lsx_vaddwev_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4624,7 +6078,13 @@ unsafe fn test_lsx_vaddwev_h_b() {
     );
     let r = i64x2::new(-6191796646052051, 32369798417022969);
 
-    assert_eq!(r, transmute(lsx_vaddwev_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4633,7 +6093,13 @@ unsafe fn test_lsx_vaddwod_d_w() {
     let b = i32x4::new(420515981, 473447119, 1471756335, 1044924117);
     let r = i64x2::new(126219465, 3020814787);
 
-    assert_eq!(r, transmute(lsx_vaddwod_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4642,7 +6108,13 @@ unsafe fn test_lsx_vaddwod_w_h() {
     let b = i16x8::new(-26581, -22301, 18214, -3616, -24489, 12150, -10765, -24232);
     let r = i64x2::new(-151719719748481, -112154480997307);
 
-    assert_eq!(r, transmute(lsx_vaddwod_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4655,7 +6127,13 @@ unsafe fn test_lsx_vaddwod_h_b() {
     );
     let r = i64x2::new(-18014780768845678, 14636475441676413);
 
-    assert_eq!(r, transmute(lsx_vaddwod_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4664,7 +6142,13 @@ unsafe fn test_lsx_vaddwev_d_wu() {
     let b = u32x4::new(1482213353, 1001198416, 3345983326, 2244256337);
     let r = i64x2::new(4022160583, 4539965521);
 
-    assert_eq!(r, transmute(lsx_vaddwev_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4673,7 +6157,13 @@ unsafe fn test_lsx_vaddwev_w_hu() {
     let b = u16x8::new(28483, 24704, 9817, 62062, 47674, 8032, 29897, 62737);
     let r = i64x2::new(176725019407839, 226649719257774);
 
-    assert_eq!(r, transmute(lsx_vaddwev_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4686,7 +6176,13 @@ unsafe fn test_lsx_vaddwev_h_bu() {
     );
     let r = i64x2::new(85006057160704351, 47850943627526421);
 
-    assert_eq!(r, transmute(lsx_vaddwev_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4695,7 +6191,13 @@ unsafe fn test_lsx_vaddwod_d_wu() {
     let b = u32x4::new(2782520439, 2496077290, 2678772394, 196273109);
     let r = i64x2::new(4147231270, 2289089430);
 
-    assert_eq!(r, transmute(lsx_vaddwod_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4704,7 +6206,13 @@ unsafe fn test_lsx_vaddwod_w_hu() {
     let b = u16x8::new(20353, 34039, 21222, 4948, 58293, 4766, 51360, 37497);
     let r = i64x2::new(82519206727777, 206875689791292);
 
-    assert_eq!(r, transmute(lsx_vaddwod_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4717,7 +6225,13 @@ unsafe fn test_lsx_vaddwod_h_bu() {
     );
     let r = i64x2::new(73466429242409013, 32932877227196635);
 
-    assert_eq!(r, transmute(lsx_vaddwod_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4726,7 +6240,13 @@ unsafe fn test_lsx_vaddwev_d_wu_w() {
     let b = i32x4::new(-1308530150, 1427930358, 1723198474, 1987356336);
     let r = i64x2::new(2478528121, 3014708115);
 
-    assert_eq!(r, transmute(lsx_vaddwev_d_wu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4735,7 +6255,13 @@ unsafe fn test_lsx_vaddwev_w_hu_h() {
     let b = i16x8::new(-11621, -6593, 7431, -1189, -12361, -15174, 16182, -32434);
     let r = i64x2::new(64158221463769, 194716637325930);
 
-    assert_eq!(r, transmute(lsx_vaddwev_w_hu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4748,7 +6274,13 @@ unsafe fn test_lsx_vaddwev_h_bu_b() {
     );
     let r = i64x2::new(71776235037065355, -7880749580746636);
 
-    assert_eq!(r, transmute(lsx_vaddwev_h_bu_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4757,7 +6289,13 @@ unsafe fn test_lsx_vaddwod_d_wu_w() {
     let b = i32x4::new(-1646368557, 586112311, 376247963, 1048800083);
     let r = i64x2::new(3497092601, 3306080422);
 
-    assert_eq!(r, transmute(lsx_vaddwod_d_wu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4766,7 +6304,13 @@ unsafe fn test_lsx_vaddwod_w_hu_h() {
     let b = i16x8::new(31700, 22725, 14068, -14860, -28839, -14513, -1195, 27082);
     let r = i64x2::new(-10273561712908, 369560461022726);
 
-    assert_eq!(r, transmute(lsx_vaddwod_w_hu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4779,7 +6323,13 @@ unsafe fn test_lsx_vaddwod_h_bu_b() {
     );
     let r = i64x2::new(49259327819481212, 19140654913421439);
 
-    assert_eq!(r, transmute(lsx_vaddwod_h_bu_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4788,7 +6338,13 @@ unsafe fn test_lsx_vsubwev_d_w() {
     let b = i32x4::new(-2090701374, 629564229, -1170676885, 1069800209);
     let r = i64x2::new(4070621277, 63900397);
 
-    assert_eq!(r, transmute(lsx_vsubwev_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4797,7 +6353,13 @@ unsafe fn test_lsx_vsubwev_w_h() {
     let b = i16x8::new(-23957, 9416, -29569, -13210, 5333, 8420, 18648, -24201);
     let r = i64x2::new(228187317494294, -105188044063209);
 
-    assert_eq!(r, transmute(lsx_vsubwev_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4810,7 +6372,13 @@ unsafe fn test_lsx_vsubwev_h_b() {
     );
     let r = i64x2::new(-41939247539617653, -14355228098887689);
 
-    assert_eq!(r, transmute(lsx_vsubwev_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4819,7 +6387,13 @@ unsafe fn test_lsx_vsubwod_d_w() {
     let b = i32x4::new(1436617964, -45524609, 502994793, -2039550077);
     let r = i64x2::new(-1037882987, 3497647797);
 
-    assert_eq!(r, transmute(lsx_vsubwod_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4828,7 +6402,13 @@ unsafe fn test_lsx_vsubwod_w_h() {
     let b = i16x8::new(-1276, 12669, 24115, 19617, -26739, 1910, -757, 23994);
     let r = i64x2::new(-158286724709540, -182411556002309);
 
-    assert_eq!(r, transmute(lsx_vsubwod_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4841,7 +6421,13 @@ unsafe fn test_lsx_vsubwod_h_b() {
     );
     let r = i64x2::new(23925540523802608, 562958549909362);
 
-    assert_eq!(r, transmute(lsx_vsubwod_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4850,7 +6436,13 @@ unsafe fn test_lsx_vsubwev_d_wu() {
     let b = u32x4::new(1691253880, 1939268473, 1629937431, 2921768539);
     let r = i64x2::new(974418830, 1402878171);
 
-    assert_eq!(r, transmute(lsx_vsubwev_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4859,7 +6451,13 @@ unsafe fn test_lsx_vsubwev_w_hu() {
     let b = u16x8::new(15957, 42770, 43138, 30319, 50823, 18089, 64120, 18054);
     let r = i64x2::new(-41807211666923, -194858371266981);
 
-    assert_eq!(r, transmute(lsx_vsubwev_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4872,7 +6470,13 @@ unsafe fn test_lsx_vsubwev_h_bu() {
     );
     let r = i64x2::new(-1407181617889293, 47851128289689387);
 
-    assert_eq!(r, transmute(lsx_vsubwev_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4881,7 +6485,13 @@ unsafe fn test_lsx_vsubwod_d_wu() {
     let b = u32x4::new(103354715, 19070238, 1662532733, 3761231766);
     let r = i64x2::new(3487028338, -1512426824);
 
-    assert_eq!(r, transmute(lsx_vsubwod_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4890,7 +6500,13 @@ unsafe fn test_lsx_vsubwod_w_hu() {
     let b = u16x8::new(21739, 45406, 21733, 63910, 6659, 16020, 1211, 637);
     let r = i64x2::new(-93999654264447, 232211701825972);
 
-    assert_eq!(r, transmute(lsx_vsubwod_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4903,7 +6519,13 @@ unsafe fn test_lsx_vsubwod_h_bu() {
     );
     let r = i64x2::new(-14355150803107815, 14636020195655765);
 
-    assert_eq!(r, transmute(lsx_vsubwod_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4912,7 +6534,13 @@ unsafe fn test_lsx_vaddwev_q_d() {
     let b = i64x2::new(6738886902337351868, -5985538541381931477);
     let r = i64x2::new(5606769623790009521, 0);
 
-    assert_eq!(r, transmute(lsx_vaddwev_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4921,7 +6549,13 @@ unsafe fn test_lsx_vaddwod_q_d() {
     let b = i64x2::new(-1244049724346527963, -3275029038845457041);
     let r = i64x2::new(-4417812606654001824, -1);
 
-    assert_eq!(r, transmute(lsx_vaddwod_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4930,7 +6564,13 @@ unsafe fn test_lsx_vaddwev_q_du() {
     let b = u64x2::new(6745766838534849346, 15041258018068294402);
     let r = i64x2::new(5074243625310689089, 1);
 
-    assert_eq!(r, transmute(lsx_vaddwev_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4939,7 +6579,13 @@ unsafe fn test_lsx_vaddwod_q_du() {
     let b = u64x2::new(13496765248439164553, 4640846570780442359);
     let r = i64x2::new(-2107214925415534967, 0);
 
-    assert_eq!(r, transmute(lsx_vaddwod_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4948,7 +6594,13 @@ unsafe fn test_lsx_vsubwev_q_d() {
     let b = i64x2::new(8029026411722387723, -2105201823388787841);
     let r = i64x2::new(480269655671735476, 0);
 
-    assert_eq!(r, transmute(lsx_vsubwev_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4957,7 +6609,13 @@ unsafe fn test_lsx_vsubwod_q_d() {
     let b = i64x2::new(5758437127240728961, 2933507971643343184);
     let r = i64x2::new(-8752278892998837291, -1);
 
-    assert_eq!(r, transmute(lsx_vsubwod_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4966,7 +6624,13 @@ unsafe fn test_lsx_vsubwev_q_du() {
     let b = u64x2::new(1574118313456291324, 7787456577305510529);
     let r = i64x2::new(-4672772323591679948, 0);
 
-    assert_eq!(r, transmute(lsx_vsubwev_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4975,7 +6639,13 @@ unsafe fn test_lsx_vsubwod_q_du() {
     let b = u64x2::new(5627376085113520030, 12775637764770549815);
     let r = i64x2::new(6257163948134922640, -1);
 
-    assert_eq!(r, transmute(lsx_vsubwod_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsubwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4984,7 +6654,13 @@ unsafe fn test_lsx_vaddwev_q_du_d() {
     let b = i64x2::new(-1159499132550683978, -4257322329662100669);
     let r = i64x2::new(-8502520416635627524, 0);
 
-    assert_eq!(r, transmute(lsx_vaddwev_q_du_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwev_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -4993,7 +6669,13 @@ unsafe fn test_lsx_vaddwod_q_du_d() {
     let b = i64x2::new(-3902573037873546881, 160140233311333524);
     let r = i64x2::new(286209858134078253, 0);
 
-    assert_eq!(r, transmute(lsx_vaddwod_q_du_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vaddwod_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5002,7 +6684,13 @@ unsafe fn test_lsx_vmulwev_d_w() {
     let b = i32x4::new(8741677, -276509855, -1214560052, -1338519080);
     let r = i64x2::new(11251431313755612, -2205748716678689436);
 
-    assert_eq!(r, transmute(lsx_vmulwev_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5011,7 +6699,13 @@ unsafe fn test_lsx_vmulwev_w_h() {
     let b = i16x8::new(30661, -20472, 1422, -16868, 4256, 9713, -27765, -7287);
     let r = i64x2::new(-178740441125036345, 469367082934888736);
 
-    assert_eq!(r, transmute(lsx_vmulwev_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5024,7 +6718,13 @@ unsafe fn test_lsx_vmulwev_h_b() {
     );
     let r = i64x2::new(38855607073696482, 823864071118590255);
 
-    assert_eq!(r, transmute(lsx_vmulwev_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5033,7 +6733,13 @@ unsafe fn test_lsx_vmulwod_d_w() {
     let b = i32x4::new(63312847, -1377579771, -2054819244, -1416520586);
     let r = i64x2::new(1549708311038418702, 2478205834807109862);
 
-    assert_eq!(r, transmute(lsx_vmulwod_d_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5042,7 +6748,13 @@ unsafe fn test_lsx_vmulwod_w_h() {
     let b = i16x8::new(23748, 11912, 4946, -23048, 22372, 24702, -24875, -27771);
     let r = i64x2::new(3222038736804363232, 360450672278114574);
 
-    assert_eq!(r, transmute(lsx_vmulwod_w_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5055,7 +6767,13 @@ unsafe fn test_lsx_vmulwod_h_b() {
     );
     let r = i64x2::new(-351280556043402912, 951366355207905332);
 
-    assert_eq!(r, transmute(lsx_vmulwod_h_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5064,7 +6782,13 @@ unsafe fn test_lsx_vmulwev_d_wu() {
     let b = u32x4::new(1769900227, 2256955703, 2342391995, 2407560006);
     let r = i64x2::new(3651844205567962921, 7772247680216328210);
 
-    assert_eq!(r, transmute(lsx_vmulwev_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5073,7 +6797,13 @@ unsafe fn test_lsx_vmulwev_w_hu() {
     let b = u16x8::new(20499, 45056, 20580, 12771, 53914, 60742, 45402, 40547);
     let r = i64x2::new(4070644332601545987, 8033224333626513014);
 
-    assert_eq!(r, transmute(lsx_vmulwev_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5086,7 +6816,13 @@ unsafe fn test_lsx_vmulwev_h_bu() {
     );
     let r = i64x2::new(271910110892810861, 1947809607093856504);
 
-    assert_eq!(r, transmute(lsx_vmulwev_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5095,7 +6831,13 @@ unsafe fn test_lsx_vmulwod_d_wu() {
     let b = u32x4::new(3750239707, 1422851626, 1277923597, 1377279439);
     let r = i64x2::new(2821622727533716246, 3005960862740149995);
 
-    assert_eq!(r, transmute(lsx_vmulwod_d_wu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5104,7 +6846,13 @@ unsafe fn test_lsx_vmulwod_w_hu() {
     let b = u16x8::new(38950, 5357, 36233, 17707, 61077, 61518, 5789, 13317);
     let r = i64x2::new(2460325445475503463, 3109522059894091248);
 
-    assert_eq!(r, transmute(lsx_vmulwod_w_hu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5117,7 +6865,13 @@ unsafe fn test_lsx_vmulwod_h_bu() {
     );
     let r = i64x2::new(7364114643151226902, 6612146073643521312);
 
-    assert_eq!(r, transmute(lsx_vmulwod_h_bu(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5126,7 +6880,13 @@ unsafe fn test_lsx_vmulwev_d_wu_w() {
     let b = i32x4::new(1254729285, 1938836163, -1902169358, -257980375);
     let r = i64x2::new(2295762833698990875, -6669027432954818262);
 
-    assert_eq!(r, transmute(lsx_vmulwev_d_wu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5135,7 +6895,13 @@ unsafe fn test_lsx_vmulwev_w_hu_h() {
     let b = i16x8::new(-30477, -10049, 16428, -30668, 21000, 24834, -3219, -9555);
     let r = i64x2::new(3369342936690107644, -701630285043265176);
 
-    assert_eq!(r, transmute(lsx_vmulwev_w_hu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5148,7 +6914,13 @@ unsafe fn test_lsx_vmulwev_h_bu_b() {
     );
     let r = i64x2::new(-1134643098233554544, -1885853116779133038);
 
-    assert_eq!(r, transmute(lsx_vmulwev_h_bu_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5157,7 +6929,13 @@ unsafe fn test_lsx_vmulwod_d_wu_w() {
     let b = i32x4::new(1204047391, -1970001586, 608763444, -2082771896);
     let r = i64x2::new(-5967343163181744876, -3673352984882804288);
 
-    assert_eq!(r, transmute(lsx_vmulwod_d_wu_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_d_wu_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5166,7 +6944,13 @@ unsafe fn test_lsx_vmulwod_w_hu_h() {
     let b = i16x8::new(-3735, -12972, -4920, 7170, 11577, 9785, 4896, -537);
     let r = i64x2::new(1024392868267999948, -48053790042385565);
 
-    assert_eq!(r, transmute(lsx_vmulwod_w_hu_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_w_hu_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5179,7 +6963,13 @@ unsafe fn test_lsx_vmulwod_h_bu_b() {
     );
     let r = i64x2::new(1905300476090387090, -3940634277386171400);
 
-    assert_eq!(r, transmute(lsx_vmulwod_h_bu_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_h_bu_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5188,7 +6978,13 @@ unsafe fn test_lsx_vmulwev_q_d() {
     let b = i64x2::new(7023560313675997328, 4368639658790376608);
     let r = i64x2::new(-1409563343912029488, -2779799970834089134);
 
-    assert_eq!(r, transmute(lsx_vmulwev_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5197,7 +6993,13 @@ unsafe fn test_lsx_vmulwod_q_d() {
     let b = i64x2::new(1734538850547798281, 6505001633960390309);
     let r = i64x2::new(655114704133495137, -1013080750363369114);
 
-    assert_eq!(r, transmute(lsx_vmulwod_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5206,7 +7008,13 @@ unsafe fn test_lsx_vmulwev_q_du() {
     let b = u64x2::new(15048173707940873365, 13594773395779002998);
     let r = i64x2::new(-4049323972691826149, 6179334620527225413);
 
-    assert_eq!(r, transmute(lsx_vmulwev_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5215,7 +7023,13 @@ unsafe fn test_lsx_vmulwod_q_du() {
     let b = u64x2::new(16172423495582959833, 11676106279348566952);
     let r = i64x2::new(-66293137947075128, 3694303051148166412);
 
-    assert_eq!(r, transmute(lsx_vmulwod_q_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5224,7 +7038,13 @@ unsafe fn test_lsx_vmulwev_q_du_d() {
     let b = i64x2::new(-7071166739782294817, 8496829998090419991);
     let r = i64x2::new(5234431817964974175, -5931105679667820544);
 
-    assert_eq!(r, transmute(lsx_vmulwev_q_du_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwev_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5233,7 +7053,13 @@ unsafe fn test_lsx_vmulwod_q_du_d() {
     let b = i64x2::new(-9085162554263782091, -3351642387065053502);
     let r = i64x2::new(-3119502026085414102, -1153233394465180223);
 
-    assert_eq!(r, transmute(lsx_vmulwod_q_du_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vmulwod_q_du_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5242,7 +7068,13 @@ unsafe fn test_lsx_vhaddw_q_d() {
     let b = i64x2::new(9222966760421493517, -8347454331188625422);
     let r = i64x2::new(6438946365641244151, 0);
 
-    assert_eq!(r, transmute(lsx_vhaddw_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5251,7 +7083,13 @@ unsafe fn test_lsx_vhaddw_qu_du() {
     let b = u64x2::new(2141387370256045519, 12417156199252644485);
     let r = i64x2::new(5083013417816990364, 0);
 
-    assert_eq!(r, transmute(lsx_vhaddw_qu_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhaddw_qu_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5260,7 +7098,13 @@ unsafe fn test_lsx_vhsubw_q_d() {
     let b = i64x2::new(-3245503809142406078, 8660213762027125085);
     let r = i64x2::new(817818278178354941, 0);
 
-    assert_eq!(r, transmute(lsx_vhsubw_q_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5269,7 +7113,13 @@ unsafe fn test_lsx_vhsubw_qu_du() {
     let b = u64x2::new(3098179646743711521, 11374525358855478565);
     let r = i64x2::new(-8990580109137044958, 0);
 
-    assert_eq!(r, transmute(lsx_vhsubw_qu_du(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vhsubw_qu_du(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5281,7 +7131,11 @@ unsafe fn test_lsx_vmaddwev_d_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5294,7 +7148,11 @@ unsafe fn test_lsx_vmaddwev_w_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5311,7 +7169,11 @@ unsafe fn test_lsx_vmaddwev_h_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5324,7 +7186,11 @@ unsafe fn test_lsx_vmaddwev_d_wu() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5337,7 +7203,11 @@ unsafe fn test_lsx_vmaddwev_w_hu() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5354,7 +7224,11 @@ unsafe fn test_lsx_vmaddwev_h_bu() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5367,7 +7241,11 @@ unsafe fn test_lsx_vmaddwod_d_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_d_w(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5380,7 +7258,11 @@ unsafe fn test_lsx_vmaddwod_w_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_w_h(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5397,7 +7279,11 @@ unsafe fn test_lsx_vmaddwod_h_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_h_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5410,7 +7296,11 @@ unsafe fn test_lsx_vmaddwod_d_wu() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_d_wu(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5423,7 +7313,11 @@ unsafe fn test_lsx_vmaddwod_w_hu() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_w_hu(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5440,7 +7334,11 @@ unsafe fn test_lsx_vmaddwod_h_bu() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_h_bu(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5454,9 +7352,9 @@ unsafe fn test_lsx_vmaddwev_d_wu_w() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwev_d_wu_w(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5471,9 +7369,9 @@ unsafe fn test_lsx_vmaddwev_w_hu_h() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwev_w_hu_h(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5492,9 +7390,9 @@ unsafe fn test_lsx_vmaddwev_h_bu_b() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwev_h_bu_b(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5509,9 +7407,9 @@ unsafe fn test_lsx_vmaddwod_d_wu_w() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwod_d_wu_w(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5526,9 +7424,9 @@ unsafe fn test_lsx_vmaddwod_w_hu_h() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwod_w_hu_h(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5547,9 +7445,9 @@ unsafe fn test_lsx_vmaddwod_h_bu_b() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwod_h_bu_b(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5563,7 +7461,11 @@ unsafe fn test_lsx_vmaddwev_q_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5576,7 +7478,11 @@ unsafe fn test_lsx_vmaddwod_q_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_q_d(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5589,7 +7495,11 @@ unsafe fn test_lsx_vmaddwev_q_du() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwev_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5602,7 +7512,11 @@ unsafe fn test_lsx_vmaddwod_q_du() {
 
     assert_eq!(
         r,
-        transmute(lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vmaddwod_q_du(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -5616,9 +7530,9 @@ unsafe fn test_lsx_vmaddwev_q_du_d() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwev_q_du_d(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5633,9 +7547,9 @@ unsafe fn test_lsx_vmaddwod_q_du_d() {
     assert_eq!(
         r,
         transmute(lsx_vmaddwod_q_du_d(
-            transmute(a),
-            transmute(b),
-            transmute(c)
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
         ))
     );
 }
@@ -5650,7 +7564,13 @@ unsafe fn test_lsx_vrotr_b() {
     );
     let r = i64x2::new(2841128540244802403, -8694309599374351908);
 
-    assert_eq!(r, transmute(lsx_vrotr_b(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vrotr_b(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5659,7 +7579,13 @@ unsafe fn test_lsx_vrotr_h() {
     let b = i16x8::new(-6485, 1418, 8263, -29872, -6491, 3930, -20621, 32531);
     let r = i64x2::new(2742461657407651598, 3308267577913279393);
 
-    assert_eq!(r, transmute(lsx_vrotr_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vrotr_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5668,7 +7594,13 @@ unsafe fn test_lsx_vrotr_w() {
     let b = i32x4::new(1956224189, -1858012941, -1889446514, -2130978943);
     let r = i64x2::new(6458469860191573231, -8548346292466177157);
 
-    assert_eq!(r, transmute(lsx_vrotr_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vrotr_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5677,7 +7609,13 @@ unsafe fn test_lsx_vrotr_d() {
     let b = i64x2::new(4553458262651691654, -5062393334123159235);
     let r = i64x2::new(-3594618648537251961, 7897385285240526033);
 
-    assert_eq!(r, transmute(lsx_vrotr_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vrotr_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5686,7 +7624,10 @@ unsafe fn test_lsx_vadd_q() {
     let b = i64x2::new(114135477458514099, 3481307531297359399);
     let r = i64x2::new(2537705118259771652, 4159381110985057604);
 
-    assert_eq!(r, transmute(lsx_vadd_q(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vadd_q(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5695,7 +7636,10 @@ unsafe fn test_lsx_vsub_q() {
     let b = i64x2::new(-8526086848853095438, -1323481969747305966);
     let r = i64x2::new(-2027679534337857341, -1789445478164204527);
 
-    assert_eq!(r, transmute(lsx_vsub_q(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vsub_q(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -5745,7 +7689,7 @@ unsafe fn test_lsx_vmskgez_b() {
     );
     let r = i64x2::new(24930, 0);
 
-    assert_eq!(r, transmute(lsx_vmskgez_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmskgez_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5755,7 +7699,7 @@ unsafe fn test_lsx_vmsknz_b() {
     );
     let r = i64x2::new(65535, 0);
 
-    assert_eq!(r, transmute(lsx_vmsknz_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vmsknz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5765,7 +7709,7 @@ unsafe fn test_lsx_vexth_h_b() {
     );
     let r = i64x2::new(-3377613816397739, 32088276197572514);
 
-    assert_eq!(r, transmute(lsx_vexth_h_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_h_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5773,7 +7717,7 @@ unsafe fn test_lsx_vexth_w_h() {
     let a = i16x8::new(14576, -26514, 14165, -15781, 10106, 1864, 23348, 30478);
     let r = i64x2::new(8005819049850, 130902013270836);
 
-    assert_eq!(r, transmute(lsx_vexth_w_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_w_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5781,7 +7725,7 @@ unsafe fn test_lsx_vexth_d_w() {
     let a = i32x4::new(863783254, 799653326, -1122161877, -652869192);
     let r = i64x2::new(-1122161877, -652869192);
 
-    assert_eq!(r, transmute(lsx_vexth_d_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_d_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5789,7 +7733,7 @@ unsafe fn test_lsx_vexth_q_d() {
     let a = i64x2::new(2924262436748867523, 1959694872821330818);
     let r = i64x2::new(1959694872821330818, 0);
 
-    assert_eq!(r, transmute(lsx_vexth_q_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_q_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5799,7 +7743,7 @@ unsafe fn test_lsx_vexth_hu_bu() {
     );
     let r = i64x2::new(61080980486815914, 60235902725652628);
 
-    assert_eq!(r, transmute(lsx_vexth_hu_bu(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_hu_bu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5807,7 +7751,7 @@ unsafe fn test_lsx_vexth_wu_hu() {
     let a = u16x8::new(58875, 18924, 17611, 30197, 33869, 53931, 4693, 53025);
     let r = i64x2::new(231631881274445, 227740640875093);
 
-    assert_eq!(r, transmute(lsx_vexth_wu_hu(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_wu_hu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5815,7 +7759,7 @@ unsafe fn test_lsx_vexth_du_wu() {
     let a = u32x4::new(3499742961, 2840979237, 2082263829, 1096292547);
     let r = i64x2::new(2082263829, 1096292547);
 
-    assert_eq!(r, transmute(lsx_vexth_du_wu(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_du_wu(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5823,7 +7767,7 @@ unsafe fn test_lsx_vexth_qu_du() {
     let a = u64x2::new(14170556367894986991, 14238702840099699193);
     let r = i64x2::new(-4208041233609852423, 0);
 
-    assert_eq!(r, transmute(lsx_vexth_qu_du(transmute(a))));
+    assert_eq!(r, transmute(lsx_vexth_qu_du(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5833,7 +7777,7 @@ unsafe fn test_lsx_vrotri_b() {
     );
     let r = i64x2::new(-2919654548887155519, -96080239582005205);
 
-    assert_eq!(r, transmute(lsx_vrotri_b::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vrotri_b::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5841,7 +7785,7 @@ unsafe fn test_lsx_vrotri_h() {
     let a = i16x8::new(-14120, -16812, -19570, -990, 24476, -7640, 20329, 8879);
     let r = i64x2::new(-556925602567188047, 4998607264501841720);
 
-    assert_eq!(r, transmute(lsx_vrotri_h::<15>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vrotri_h::<15>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5849,7 +7793,7 @@ unsafe fn test_lsx_vrotri_w() {
     let a = i32x4::new(-1760224525, -1644621284, 1835781046, -1487934110);
     let r = i64x2::new(2845787365010917052, -6209343103231659283);
 
-    assert_eq!(r, transmute(lsx_vrotri_w::<2>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vrotri_w::<2>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5857,7 +7801,7 @@ unsafe fn test_lsx_vrotri_d() {
     let a = i64x2::new(8884634342417174882, 244175985366916345);
     let r = i64x2::new(-3963790888197019724, 4020656082573561910);
 
-    assert_eq!(r, transmute(lsx_vrotri_d::<52>(transmute(a))));
+    assert_eq!(r, transmute(lsx_vrotri_d::<52>(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5865,7 +7809,7 @@ unsafe fn test_lsx_vextl_q_d() {
     let a = i64x2::new(-5110246490938885255, 377414780188285171);
     let r = i64x2::new(-5110246490938885255, -1);
 
-    assert_eq!(r, transmute(lsx_vextl_q_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_vextl_q_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -5880,7 +7824,10 @@ unsafe fn test_lsx_vsrlni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlni_b_h::<14>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlni_b_h::<14>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5892,7 +7839,10 @@ unsafe fn test_lsx_vsrlni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlni_h_w::<26>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlni_h_w::<26>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5904,7 +7854,10 @@ unsafe fn test_lsx_vsrlni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlni_w_d::<18>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlni_w_d::<18>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5916,7 +7869,10 @@ unsafe fn test_lsx_vsrlni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlni_d_q::<74>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlni_d_q::<74>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5932,7 +7888,10 @@ unsafe fn test_lsx_vsrlrni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlrni_b_h::<6>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlrni_b_h::<6>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5944,7 +7903,10 @@ unsafe fn test_lsx_vsrlrni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlrni_h_w::<6>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlrni_h_w::<6>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5956,7 +7918,10 @@ unsafe fn test_lsx_vsrlrni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlrni_w_d::<52>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlrni_w_d::<52>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5968,7 +7933,10 @@ unsafe fn test_lsx_vsrlrni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrlrni_d_q::<101>(transmute(a), transmute(b)))
+        transmute(lsx_vsrlrni_d_q::<101>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5984,7 +7952,10 @@ unsafe fn test_lsx_vssrlni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_b_h::<13>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_b_h::<13>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -5996,7 +7967,10 @@ unsafe fn test_lsx_vssrlni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_h_w::<23>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_h_w::<23>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6008,7 +7982,10 @@ unsafe fn test_lsx_vssrlni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_w_d::<12>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_w_d::<12>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6020,7 +7997,10 @@ unsafe fn test_lsx_vssrlni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_d_q::<88>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_d_q::<88>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6036,7 +8016,10 @@ unsafe fn test_lsx_vssrlni_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_bu_h::<13>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_bu_h::<13>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6048,7 +8031,10 @@ unsafe fn test_lsx_vssrlni_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_hu_w::<9>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_hu_w::<9>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6060,7 +8046,10 @@ unsafe fn test_lsx_vssrlni_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_wu_d::<59>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_wu_d::<59>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6072,7 +8061,10 @@ unsafe fn test_lsx_vssrlni_du_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlni_du_q::<6>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlni_du_q::<6>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6088,7 +8080,10 @@ unsafe fn test_lsx_vssrlrni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_b_h::<0>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_b_h::<0>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6100,7 +8095,10 @@ unsafe fn test_lsx_vssrlrni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_h_w::<28>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_h_w::<28>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6112,7 +8110,10 @@ unsafe fn test_lsx_vssrlrni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_w_d::<1>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_w_d::<1>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6124,7 +8125,10 @@ unsafe fn test_lsx_vssrlrni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_d_q::<60>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_d_q::<60>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6140,7 +8144,10 @@ unsafe fn test_lsx_vssrlrni_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_bu_h::<13>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_bu_h::<13>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6152,7 +8159,10 @@ unsafe fn test_lsx_vssrlrni_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_hu_w::<25>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_hu_w::<25>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6164,7 +8174,10 @@ unsafe fn test_lsx_vssrlrni_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_wu_d::<36>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_wu_d::<36>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6176,7 +8189,10 @@ unsafe fn test_lsx_vssrlrni_du_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrlrni_du_q::<38>(transmute(a), transmute(b)))
+        transmute(lsx_vssrlrni_du_q::<38>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6192,7 +8208,10 @@ unsafe fn test_lsx_vsrani_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrani_b_h::<5>(transmute(a), transmute(b)))
+        transmute(lsx_vsrani_b_h::<5>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6204,7 +8223,10 @@ unsafe fn test_lsx_vsrani_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrani_h_w::<4>(transmute(a), transmute(b)))
+        transmute(lsx_vsrani_h_w::<4>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6216,7 +8238,10 @@ unsafe fn test_lsx_vsrani_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrani_w_d::<24>(transmute(a), transmute(b)))
+        transmute(lsx_vsrani_w_d::<24>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6228,7 +8253,10 @@ unsafe fn test_lsx_vsrani_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrani_d_q::<81>(transmute(a), transmute(b)))
+        transmute(lsx_vsrani_d_q::<81>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6244,7 +8272,10 @@ unsafe fn test_lsx_vsrarni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrarni_b_h::<3>(transmute(a), transmute(b)))
+        transmute(lsx_vsrarni_b_h::<3>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6256,7 +8287,10 @@ unsafe fn test_lsx_vsrarni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrarni_h_w::<15>(transmute(a), transmute(b)))
+        transmute(lsx_vsrarni_h_w::<15>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6268,7 +8302,10 @@ unsafe fn test_lsx_vsrarni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrarni_w_d::<59>(transmute(a), transmute(b)))
+        transmute(lsx_vsrarni_w_d::<59>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6280,7 +8317,10 @@ unsafe fn test_lsx_vsrarni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vsrarni_d_q::<0>(transmute(a), transmute(b)))
+        transmute(lsx_vsrarni_d_q::<0>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6296,7 +8336,10 @@ unsafe fn test_lsx_vssrani_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_b_h::<0>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_b_h::<0>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6308,7 +8351,10 @@ unsafe fn test_lsx_vssrani_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_h_w::<28>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_h_w::<28>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6320,7 +8366,10 @@ unsafe fn test_lsx_vssrani_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_w_d::<49>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_w_d::<49>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6332,7 +8381,10 @@ unsafe fn test_lsx_vssrani_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_d_q::<80>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_d_q::<80>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6348,7 +8400,10 @@ unsafe fn test_lsx_vssrani_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_bu_h::<14>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_bu_h::<14>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6360,7 +8415,10 @@ unsafe fn test_lsx_vssrani_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_hu_w::<23>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_hu_w::<23>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6372,7 +8430,10 @@ unsafe fn test_lsx_vssrani_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_wu_d::<13>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_wu_d::<13>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6384,7 +8445,10 @@ unsafe fn test_lsx_vssrani_du_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrani_du_q::<33>(transmute(a), transmute(b)))
+        transmute(lsx_vssrani_du_q::<33>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6400,7 +8464,10 @@ unsafe fn test_lsx_vssrarni_b_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_b_h::<2>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_b_h::<2>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6412,7 +8479,10 @@ unsafe fn test_lsx_vssrarni_h_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_h_w::<29>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_h_w::<29>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6424,7 +8494,10 @@ unsafe fn test_lsx_vssrarni_w_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_w_d::<18>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_w_d::<18>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6436,7 +8509,10 @@ unsafe fn test_lsx_vssrarni_d_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_d_q::<70>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_d_q::<70>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6452,7 +8528,10 @@ unsafe fn test_lsx_vssrarni_bu_h() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_bu_h::<14>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_bu_h::<14>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6464,7 +8543,10 @@ unsafe fn test_lsx_vssrarni_hu_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_hu_w::<13>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_hu_w::<13>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6476,7 +8558,10 @@ unsafe fn test_lsx_vssrarni_wu_d() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_wu_d::<15>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_wu_d::<15>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6488,7 +8573,10 @@ unsafe fn test_lsx_vssrarni_du_q() {
 
     assert_eq!(
         r,
-        transmute(lsx_vssrarni_du_q::<126>(transmute(a), transmute(b)))
+        transmute(lsx_vssrarni_du_q::<126>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6500,7 +8588,10 @@ unsafe fn test_lsx_vpermi_w() {
 
     assert_eq!(
         r,
-        transmute(lsx_vpermi_w::<158>(transmute(a), transmute(b)))
+        transmute(lsx_vpermi_w::<158>(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
     );
 }
 
@@ -6524,7 +8615,7 @@ unsafe fn test_lsx_vst() {
     ];
     let r = i64x2::new(4153633675232462821, -2083384694265299697);
 
-    lsx_vst::<0>(transmute(a), o.as_mut_ptr());
+    lsx_vst::<0>(black_box(transmute(a)), o.as_mut_ptr());
     assert_eq!(r, transmute(o));
 }
 
@@ -6534,7 +8625,13 @@ unsafe fn test_lsx_vssrlrn_b_h() {
     let b = i16x8::new(17437, 9775, -20467, -31838, 5913, 4238, -7458, 2822);
     let r = i64x2::new(5981906731171643399, 0);
 
-    assert_eq!(r, transmute(lsx_vssrlrn_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrlrn_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6543,7 +8640,13 @@ unsafe fn test_lsx_vssrlrn_h_w() {
     let b = i32x4::new(-2116426818, 1641049288, 712377342, -1572394121);
     let r = i64x2::new(31243728857268226, 0);
 
-    assert_eq!(r, transmute(lsx_vssrlrn_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrlrn_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6552,7 +8655,13 @@ unsafe fn test_lsx_vssrlrn_w_d() {
     let b = i64x2::new(-3890929847852895653, -7819301294522132056);
     let r = i64x2::new(66519777023098879, 0);
 
-    assert_eq!(r, transmute(lsx_vssrlrn_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrlrn_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6561,7 +8670,13 @@ unsafe fn test_lsx_vssrln_b_h() {
     let b = i16x8::new(-14062, -29610, -24609, -8884, -1818, 32133, 29934, -6498);
     let r = i64x2::new(140183437672319, 0);
 
-    assert_eq!(r, transmute(lsx_vssrln_b_h(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrln_b_h(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6570,7 +8685,13 @@ unsafe fn test_lsx_vssrln_h_w() {
     let b = i32x4::new(-1437891045, 1546371535, -1800954476, -1892390372);
     let r = i64x2::new(2820489990832156, 0);
 
-    assert_eq!(r, transmute(lsx_vssrln_h_w(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrln_h_w(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6579,7 +8700,13 @@ unsafe fn test_lsx_vssrln_w_d() {
     let b = i64x2::new(2034490755997557661, -3470252066162700534);
     let r = i64x2::new(9223372034707292159, 0);
 
-    assert_eq!(r, transmute(lsx_vssrln_w_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vssrln_w_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6592,7 +8719,10 @@ unsafe fn test_lsx_vorn_v() {
     );
     let r = i64x2::new(-883973744907789059, -2901520201165080862);
 
-    assert_eq!(r, transmute(lsx_vorn_v(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vorn_v(black_box(transmute(a)), black_box(transmute(b))))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6615,7 +8745,11 @@ unsafe fn test_lsx_vshuf_b() {
 
     assert_eq!(
         r,
-        transmute(lsx_vshuf_b(transmute(a), transmute(b), transmute(c)))
+        transmute(lsx_vshuf_b(
+            black_box(transmute(a)),
+            black_box(transmute(b)),
+            black_box(transmute(c))
+        ))
     );
 }
 
@@ -6639,7 +8773,7 @@ unsafe fn test_lsx_vstx() {
     ];
     let r = i64x2::new(-1493444417618012559, 7191635320606490850);
 
-    lsx_vstx(transmute(a), o.as_mut_ptr(), 0);
+    lsx_vstx(black_box(transmute(a)), o.as_mut_ptr(), 0);
     assert_eq!(r, transmute(o));
 }
 
@@ -6648,7 +8782,7 @@ unsafe fn test_lsx_vextl_qu_du() {
     let a = u64x2::new(14708598110732796778, 2132245682694336458);
     let r = i64x2::new(-3738145962976754838, 0);
 
-    assert_eq!(r, transmute(lsx_vextl_qu_du(transmute(a))));
+    assert_eq!(r, transmute(lsx_vextl_qu_du(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6658,7 +8792,7 @@ unsafe fn test_lsx_bnz_b() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lsx_bnz_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_bnz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6666,7 +8800,7 @@ unsafe fn test_lsx_bnz_d() {
     let a = u64x2::new(2935166648440262530, 9853932033129373129);
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lsx_bnz_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_bnz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6674,7 +8808,7 @@ unsafe fn test_lsx_bnz_h() {
     let a = u16x8::new(55695, 60003, 59560, 35123, 25693, 41352, 61626, 42007);
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lsx_bnz_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_bnz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6684,7 +8818,7 @@ unsafe fn test_lsx_bnz_v() {
     );
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lsx_bnz_v(transmute(a))));
+    assert_eq!(r, transmute(lsx_bnz_v(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6692,7 +8826,7 @@ unsafe fn test_lsx_bnz_w() {
     let a = u32x4::new(1172712391, 4211490091, 1954893853, 1606462106);
     let r: i32 = 1;
 
-    assert_eq!(r, transmute(lsx_bnz_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_bnz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6702,7 +8836,7 @@ unsafe fn test_lsx_bz_b() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lsx_bz_b(transmute(a))));
+    assert_eq!(r, transmute(lsx_bz_b(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6710,7 +8844,7 @@ unsafe fn test_lsx_bz_d() {
     let a = u64x2::new(6051854163594201075, 9957257179760945130);
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lsx_bz_d(transmute(a))));
+    assert_eq!(r, transmute(lsx_bz_d(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6718,7 +8852,7 @@ unsafe fn test_lsx_bz_h() {
     let a = u16x8::new(19470, 29377, 53886, 60432, 20799, 41755, 54479, 52192);
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lsx_bz_h(transmute(a))));
+    assert_eq!(r, transmute(lsx_bz_h(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6728,7 +8862,7 @@ unsafe fn test_lsx_bz_v() {
     );
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lsx_bz_v(transmute(a))));
+    assert_eq!(r, transmute(lsx_bz_v(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6736,7 +8870,7 @@ unsafe fn test_lsx_bz_w() {
     let a = u32x4::new(840335855, 1404686204, 628335401, 1171808080);
     let r: i32 = 0;
 
-    assert_eq!(r, transmute(lsx_bz_w(transmute(a))));
+    assert_eq!(r, transmute(lsx_bz_w(black_box(transmute(a)))));
 }
 
 #[simd_test(enable = "lsx")]
@@ -6745,7 +8879,13 @@ unsafe fn test_lsx_vfcmp_caf_d() {
     let b = u64x2::new(4594845432849836188, 4605165420863530034);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_caf_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_caf_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6754,7 +8894,13 @@ unsafe fn test_lsx_vfcmp_caf_s() {
     let b = u32x4::new(1058412800, 1058762495, 1028487696, 1027290752);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_caf_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_caf_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6763,7 +8909,13 @@ unsafe fn test_lsx_vfcmp_ceq_d() {
     let b = u64x2::new(4605937250150464526, 4596769502461699132);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_ceq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_ceq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6772,7 +8924,13 @@ unsafe fn test_lsx_vfcmp_ceq_s() {
     let b = u32x4::new(1057471620, 1064008655, 1062698831, 1064822930);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_ceq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_ceq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6781,7 +8939,13 @@ unsafe fn test_lsx_vfcmp_cle_d() {
     let b = u64x2::new(4596931282408842596, 4592481315209481584);
     let r = i64x2::new(-1, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cle_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cle_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6790,7 +8954,13 @@ unsafe fn test_lsx_vfcmp_cle_s() {
     let b = u32x4::new(1021993344, 1043028808, 1064182329, 1054794412);
     let r = i64x2::new(-4294967296, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cle_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cle_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6799,7 +8969,13 @@ unsafe fn test_lsx_vfcmp_clt_d() {
     let b = u64x2::new(4603056125735978454, 4595932368389116476);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_clt_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_clt_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6808,7 +8984,13 @@ unsafe fn test_lsx_vfcmp_clt_s() {
     let b = u32x4::new(1040327468, 1040072248, 1063314103, 1061361061);
     let r = i64x2::new(0, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_clt_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_clt_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6817,7 +8999,13 @@ unsafe fn test_lsx_vfcmp_cne_d() {
     let b = u64x2::new(4602354759349431170, 4598595124838935466);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cne_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cne_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6826,7 +9014,13 @@ unsafe fn test_lsx_vfcmp_cne_s() {
     let b = u32x4::new(1063262940, 1058010357, 1052721962, 1061295988);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cne_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cne_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6835,7 +9029,13 @@ unsafe fn test_lsx_vfcmp_cor_d() {
     let b = u64x2::new(4606863361114437050, 4600753700959452152);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cor_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cor_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6844,7 +9044,13 @@ unsafe fn test_lsx_vfcmp_cor_s() {
     let b = u32x4::new(1053615382, 1065255138, 1051565294, 1041776832);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cor_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cor_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6853,7 +9059,13 @@ unsafe fn test_lsx_vfcmp_cueq_d() {
     let b = u64x2::new(4603317345052528721, 4586734343919602352);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cueq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cueq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6862,7 +9074,13 @@ unsafe fn test_lsx_vfcmp_cueq_s() {
     let b = u32x4::new(1057082822, 1059761998, 1052599998, 1054369118);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cueq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cueq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6871,7 +9089,13 @@ unsafe fn test_lsx_vfcmp_cule_d() {
     let b = u64x2::new(4604253448175093958, 4599648167588382448);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cule_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cule_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6880,7 +9104,13 @@ unsafe fn test_lsx_vfcmp_cule_s() {
     let b = u32x4::new(1051100696, 1062219104, 1064568294, 1032521352);
     let r = i64x2::new(-4294967296, 4294967295);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cule_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cule_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6889,7 +9119,13 @@ unsafe fn test_lsx_vfcmp_cult_d() {
     let b = u64x2::new(4602944708025910986, 4606429728449082215);
     let r = i64x2::new(0, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cult_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cult_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6898,7 +9134,13 @@ unsafe fn test_lsx_vfcmp_cult_s() {
     let b = u32x4::new(1030808384, 1044268840, 1050761328, 1037308928);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cult_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cult_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6907,7 +9149,13 @@ unsafe fn test_lsx_vfcmp_cun_d() {
     let b = u64x2::new(4599145506416791474, 4602762942707610466);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cun_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cun_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6916,7 +9164,13 @@ unsafe fn test_lsx_vfcmp_cune_d() {
     let b = u64x2::new(4602895209237804084, 4598685577984089858);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cune_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cune_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6925,7 +9179,13 @@ unsafe fn test_lsx_vfcmp_cune_s() {
     let b = u32x4::new(1049955876, 1032474200, 1023410112, 1050347912);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cune_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cune_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6934,7 +9194,13 @@ unsafe fn test_lsx_vfcmp_cun_s() {
     let b = u32x4::new(1053288920, 1059911123, 1058695573, 1062913175);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_cun_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_cun_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6943,7 +9209,13 @@ unsafe fn test_lsx_vfcmp_saf_d() {
     let b = u64x2::new(4589118818065931376, 4603302333347826011);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_saf_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_saf_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6952,7 +9224,13 @@ unsafe fn test_lsx_vfcmp_saf_s() {
     let b = u32x4::new(1044756936, 1054667546, 1059141760, 1062203553);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_saf_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_saf_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6961,7 +9239,13 @@ unsafe fn test_lsx_vfcmp_seq_d() {
     let b = u64x2::new(4594167956310606988, 4596272126122589228);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_seq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_seq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6970,7 +9254,13 @@ unsafe fn test_lsx_vfcmp_seq_s() {
     let b = u32x4::new(1057231588, 1051495460, 1057998997, 1049117328);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_seq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_seq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6979,7 +9269,13 @@ unsafe fn test_lsx_vfcmp_sle_d() {
     let b = u64x2::new(4603919005855163252, 4594682846653946884);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sle_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sle_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6988,7 +9284,13 @@ unsafe fn test_lsx_vfcmp_sle_s() {
     let b = u32x4::new(1045989468, 1052518900, 1046184640, 1032417352);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sle_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sle_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -6997,7 +9299,13 @@ unsafe fn test_lsx_vfcmp_slt_d() {
     let b = u64x2::new(4600564867142526828, 4585131890265864544);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_slt_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_slt_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7006,7 +9314,13 @@ unsafe fn test_lsx_vfcmp_slt_s() {
     let b = u32x4::new(1063435026, 1062439603, 1060665555, 1059252630);
     let r = i64x2::new(-1, -4294967296);
 
-    assert_eq!(r, transmute(lsx_vfcmp_slt_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_slt_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7015,7 +9329,13 @@ unsafe fn test_lsx_vfcmp_sne_d() {
     let b = u64x2::new(4606789952952688555, 4605380358192261377);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sne_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sne_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7024,7 +9344,13 @@ unsafe fn test_lsx_vfcmp_sne_s() {
     let b = u32x4::new(1055803760, 1063372602, 1062608900, 1054634370);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sne_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sne_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7033,7 +9359,13 @@ unsafe fn test_lsx_vfcmp_sor_d() {
     let b = u64x2::new(4606380175568635560, 4602092067387067462);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sor_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sor_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7042,7 +9374,13 @@ unsafe fn test_lsx_vfcmp_sor_s() {
     let b = u32x4::new(1064534350, 1035771168, 1059142426, 1034677600);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sor_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sor_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7051,7 +9389,13 @@ unsafe fn test_lsx_vfcmp_sueq_d() {
     let b = u64x2::new(4602917609947054533, 4605983209212177197);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sueq_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sueq_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7060,7 +9404,13 @@ unsafe fn test_lsx_vfcmp_sueq_s() {
     let b = u32x4::new(1064871165, 1059796257, 1055456352, 1058662692);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sueq_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sueq_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7069,7 +9419,13 @@ unsafe fn test_lsx_vfcmp_sule_d() {
     let b = u64x2::new(4594044173266256632, 4601549551994738386);
     let r = i64x2::new(0, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sule_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sule_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7078,7 +9434,13 @@ unsafe fn test_lsx_vfcmp_sule_s() {
     let b = u32x4::new(1061061244, 1051874412, 1041025316, 1056018690);
     let r = i64x2::new(4294967295, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sule_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sule_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7087,7 +9449,13 @@ unsafe fn test_lsx_vfcmp_sult_d() {
     let b = u64x2::new(4603848042095479627, 4605032971316970060);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sult_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sult_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7096,7 +9464,13 @@ unsafe fn test_lsx_vfcmp_sult_s() {
     let b = u32x4::new(1053631630, 1064026599, 1058029398, 1041182304);
     let r = i64x2::new(-4294967296, 4294967295);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sult_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sult_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7105,7 +9479,13 @@ unsafe fn test_lsx_vfcmp_sun_d() {
     let b = u64x2::new(4560681020073292800, 4604624347352815433);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sun_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sun_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7114,7 +9494,13 @@ unsafe fn test_lsx_vfcmp_sune_d() {
     let b = u64x2::new(4593947987798339484, 4603656097008761637);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sune_d(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sune_d(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7123,7 +9509,13 @@ unsafe fn test_lsx_vfcmp_sune_s() {
     let b = u32x4::new(1049327168, 1034635272, 1042258196, 1062844003);
     let r = i64x2::new(-1, -1);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sune_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sune_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
@@ -7132,7 +9524,13 @@ unsafe fn test_lsx_vfcmp_sun_s() {
     let b = u32x4::new(1057442863, 1064573466, 1058086753, 1015993248);
     let r = i64x2::new(0, 0);
 
-    assert_eq!(r, transmute(lsx_vfcmp_sun_s(transmute(a), transmute(b))));
+    assert_eq!(
+        r,
+        transmute(lsx_vfcmp_sun_s(
+            black_box(transmute(a)),
+            black_box(transmute(b))
+        ))
+    );
 }
 
 #[simd_test(enable = "lsx")]
diff --git a/crates/stdarch-gen-loongarch/src/main.rs b/crates/stdarch-gen-loongarch/src/main.rs
index fe767fc309..3a946a12d6 100644
--- a/crates/stdarch-gen-loongarch/src/main.rs
+++ b/crates/stdarch-gen-loongarch/src/main.rs
@@ -847,6 +847,7 @@ union v4df
     out.push_str("    printf(\"    core_arch::{loongarch64::*, simd::*},\\n\");\n");
     out.push_str("    printf(\"    mem::transmute,\\n\");\n");
     out.push_str("    printf(\"};\\n\");\n");
+    out.push_str("    printf(\"use std::hint::black_box;\\n\");\n");
     out.push_str("    printf(\"use stdarch_test::simd_test;\\n\");\n");
     out.push_str(&call_function_str);
     out.push_str("    return 0;\n");
@@ -1323,10 +1324,10 @@ fn gen_test_body(
             _ => "unsupported parameter number".to_string(),
         };
         let mut as_params = match para_num {
-            1 => "(transmute(a))".to_string(),
-            2 => "(transmute(a), transmute(b))".to_string(),
-            3 => "(transmute(a), transmute(b), transmute(c))".to_string(),
-            4 => "(transmute(a), transmute(b), transmute(c), transmute(d))".to_string(),
+            1 => "(black_box(transmute(a)))".to_string(),
+            2 => "(black_box(transmute(a)), black_box(transmute(b)))".to_string(),
+            3 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)))".to_string(),
+            4 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)), black_box(transmute(d)))".to_string(),
             _ => panic!("unsupported parameter number"),
         };
         let mut as_args = String::new();
@@ -1356,9 +1357,9 @@ fn gen_test_body(
         {
             fn_params = "(a)".to_string();
             if in_t[0] == "SI" {
-                as_params = "(%d)".to_string();
+                as_params = "(black_box(%d))".to_string();
             } else {
-                as_params = "(%ld)".to_string();
+                as_params = "(black_box(%ld))".to_string();
             }
             as_args = ", a".to_string();
         } else if para_num == 2 && (in_t[1] == "UQI" || in_t[1] == "USI") {
@@ -1370,7 +1371,7 @@ fn gen_test_body(
                 );
                 let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::<u8>().unwrap());
                 fn_params = format!("(a.v, {val})");
-                as_params = format!("::<{val}>(transmute(a))");
+                as_params = format!("::<{val}>(black_box(transmute(a)))");
             } else {
                 panic!("unsupported assembly format: {}", asm_fmts[2]);
             }
@@ -1383,13 +1384,13 @@ fn gen_test_body(
                 );
                 let val = rand_i32(asm_fmts[2].get(2..).unwrap().parse::<u8>().unwrap());
                 fn_params = format!("(a.v, {val})");
-                as_params = format!("::<{val}>(transmute(a))");
+                as_params = format!("::<{val}>(black_box(transmute(a)))");
             } else {
                 panic!("unsupported assembly format: {}", asm_fmts[2]);
             }
         } else if para_num == 2 && in_t[1] == "SI" && asm_fmts[2].starts_with("rk") {
             fn_params = "(a.v, b)".to_string();
-            as_params = "(transmute(a), %d)".to_string();
+            as_params = "(black_box(transmute(a)), %d)".to_string();
             as_args = ", b".to_string();
         } else if para_num == 2 && in_t[0] == "CVPOINTER" && in_t[1] == "SI" {
             if asm_fmts[2].starts_with("si") {
@@ -1441,7 +1442,7 @@ fn gen_test_body(
                 let ival = rand_i32(32);
                 let uval = rand_u32(asm_fmts[2].get(2..).unwrap().parse::<u8>().unwrap());
                 fn_params = format!("(a.v, {ival}, {uval})");
-                as_params = format!("::<{uval}>(transmute(a), {ival})");
+                as_params = format!("::<{uval}>(black_box(transmute(a)), {ival})");
             } else {
                 panic!("unsupported assembly format: {}", asm_fmts[2]);
             }
@@ -1456,7 +1457,7 @@ fn gen_test_body(
                 );
                 let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::<u8>().unwrap());
                 fn_params = format!("(a.v, b.v, {val})");
-                as_params = format!("::<{val}>(transmute(a), transmute(b))");
+                as_params = format!("::<{val}>(black_box(transmute(a)), black_box(transmute(b)))");
             } else {
                 panic!("unsupported assembly format: {}", asm_fmts[2]);
             }
@@ -1478,7 +1479,7 @@ fn gen_test_body(
                     type_to_ct(in_t[1])
                 );
                 fn_params = "(a.v, b, 0)".to_string();
-                as_params = "::<0>(transmute(a), o.as_mut_ptr())".to_string();
+                as_params = "::<0>(black_box(transmute(a)), o.as_mut_ptr())".to_string();
             } else {
                 panic!("unsupported assembly format: {}", asm_fmts[2]);
             }
@@ -1500,7 +1501,7 @@ fn gen_test_body(
                     type_to_ct(in_t[1])
                 );
                 fn_params = "(a.v, b, 0)".to_string();
-                as_params = "(transmute(a), o.as_mut_ptr(), 0)".to_string();
+                as_params = "(black_box(transmute(a)), o.as_mut_ptr(), 0)".to_string();
             } else {
                 panic!("unsupported assembly format: {}", asm_fmts[2]);
             }
@@ -1524,7 +1525,7 @@ fn gen_test_body(
                     );
                     let val = rand_u32(type_to_imm(t).try_into().unwrap());
                     fn_params = format!("(a.v, b, 0, {val})");
-                    as_params = format!("::<0, {val}>(transmute(a), o.as_mut_ptr())");
+                    as_params = format!("::<0, {val}>(black_box(transmute(a)), o.as_mut_ptr())");
                 }
                 (_, _) => panic!(
                     "unsupported assembly format: {} for {}",

From cffa88e090828010598a8cdaeb5c164ff2f0f86d Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 13 Apr 2026 00:06:34 +0530
Subject: [PATCH 226/326] Update SDE to v10.8.0

---
 ci/docker/x86_64-unknown-linux-gnu/Dockerfile | 2 +-
 ci/docker/x86_64-unknown-linux-gnu/cpuid.def  | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
index a357449d51..17c6d25215 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
@@ -12,7 +12,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   build-essential \
   lld
 
-RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-10.5.0-2026-01-13-lin.tar.xz -O sde.tar.xz
+RUN wget http://ci-mirrors.rust-lang.org/sde-external-10.8.0-2026-03-15-lin.tar.xz -O sde.tar.xz
 RUN mkdir intel-sde
 RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde
 ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \
diff --git a/ci/docker/x86_64-unknown-linux-gnu/cpuid.def b/ci/docker/x86_64-unknown-linux-gnu/cpuid.def
index acf023ed0d..3bd657873e 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/cpuid.def
+++ b/ci/docker/x86_64-unknown-linux-gnu/cpuid.def
@@ -1,4 +1,4 @@
-# Copyright (C) 2017-2025 Intel Corporation.
+# Copyright (C) 2017-2026 Intel Corporation.
 # 
 # This software and the related documents are Intel copyrighted materials, and your
 # use of them is governed by the express license under which they were provided to
@@ -23,8 +23,9 @@
 00000004 00000004 => 00000000 00000000 00000000 00000000
 00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT
 00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power
-00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features
+00000007 00000000 => 00000002 f3bfbfbf bac05ffe 03d54130 #Extended Features
 00000007 00000001 => 98ee00bf 00000002 00000020 1d29cd3e
+00000007 00000002 => 00000000 00000000 00000000 00000010
 00000008 ******** => 00000000 00000000 00000000 00000000
 00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache
 0000000a ******** => 07300403 00000000 00000000 00000603

From 3489955b133ffb6f3b4c00a4a7b4bd22fa31319e Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 2 Mar 2026 11:03:13 +0000
Subject: [PATCH 227/326] stdarch-verify: re-add runtime test check

This was accidentally removed in 713444d.
---
 crates/stdarch-verify/tests/arm.rs | 4706 ++++++++++++++++++++++++++--
 1 file changed, 4482 insertions(+), 224 deletions(-)

diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs
index 3ef9ce2a38..c5744de3f6 100644
--- a/crates/stdarch-verify/tests/arm.rs
+++ b/crates/stdarch-verify/tests/arm.rs
@@ -183,230 +183,20 @@ fn verify_all_signatures() {
     let mut all_valid = true;
     for rust in FUNCTIONS {
         if !rust.has_test {
-            let skip = [
-                "vaddq_s64",
-                "vaddq_u64",
-                "vrsqrte_f32",
-                "vtbl1_s8",
-                "vtbl1_u8",
-                "vtbl1_p8",
-                "vtbl2_s8",
-                "vtbl2_u8",
-                "vtbl2_p8",
-                "vtbl3_s8",
-                "vtbl3_u8",
-                "vtbl3_p8",
-                "vtbl4_s8",
-                "vtbl4_u8",
-                "vtbl4_p8",
-                "vtbx1_s8",
-                "vtbx1_u8",
-                "vtbx1_p8",
-                "vtbx2_s8",
-                "vtbx2_u8",
-                "vtbx2_p8",
-                "vtbx3_s8",
-                "vtbx3_u8",
-                "vtbx3_p8",
-                "vtbx4_s8",
-                "vtbx4_u8",
-                "vtbx4_p8",
-                "udf",
-                "_clz_u8",
-                "_clz_u16",
-                "_clz_u32",
-                "_rbit_u32",
-                "_rev_u16",
-                "_rev_u32",
-                "__breakpoint",
-                "vpminq_f32",
-                "vpminq_f64",
-                "vpmaxq_f32",
-                "vpmaxq_f64",
-                "vcombine_s8",
-                "vcombine_s16",
-                "vcombine_s32",
-                "vcombine_s64",
-                "vcombine_u8",
-                "vcombine_u16",
-                "vcombine_u32",
-                "vcombine_u64",
-                "vcombine_p64",
-                "vcombine_f32",
-                "vcombine_p8",
-                "vcombine_p16",
-                "vcombine_f64",
-                "vtbl1_s8",
-                "vtbl1_u8",
-                "vtbl1_p8",
-                "vtbl2_s8",
-                "vtbl2_u8",
-                "vtbl2_p8",
-                "vtbl3_s8",
-                "vtbl3_u8",
-                "vtbl3_p8",
-                "vtbl4_s8",
-                "vtbl4_u8",
-                "vtbl4_p8",
-                "vtbx1_s8",
-                "vtbx1_u8",
-                "vtbx1_p8",
-                "vtbx2_s8",
-                "vtbx2_u8",
-                "vtbx2_p8",
-                "vtbx3_s8",
-                "vtbx3_u8",
-                "vtbx3_p8",
-                "vtbx4_s8",
-                "vtbx4_u8",
-                "vtbx4_p8",
-                "vqtbl1_s8",
-                "vqtbl1q_s8",
-                "vqtbl1_u8",
-                "vqtbl1q_u8",
-                "vqtbl1_p8",
-                "vqtbl1q_p8",
-                "vqtbx1_s8",
-                "vqtbx1q_s8",
-                "vqtbx1_u8",
-                "vqtbx1q_u8",
-                "vqtbx1_p8",
-                "vqtbx1q_p8",
-                "vqtbl2_s8",
-                "vqtbl2q_s8",
-                "vqtbl2_u8",
-                "vqtbl2q_u8",
-                "vqtbl2_p8",
-                "vqtbl2q_p8",
-                "vqtbx2_s8",
-                "vqtbx2q_s8",
-                "vqtbx2_u8",
-                "vqtbx2q_u8",
-                "vqtbx2_p8",
-                "vqtbx2q_p8",
-                "vqtbl3_s8",
-                "vqtbl3q_s8",
-                "vqtbl3_u8",
-                "vqtbl3q_u8",
-                "vqtbl3_p8",
-                "vqtbl3q_p8",
-                "vqtbx3_s8",
-                "vqtbx3q_s8",
-                "vqtbx3_u8",
-                "vqtbx3q_u8",
-                "vqtbx3_p8",
-                "vqtbx3q_p8",
-                "vqtbl4_s8",
-                "vqtbl4q_s8",
-                "vqtbl4_u8",
-                "vqtbl4q_u8",
-                "vqtbl4_p8",
-                "vqtbl4q_p8",
-                "vqtbx4_s8",
-                "vqtbx4q_s8",
-                "vqtbx4_u8",
-                "vqtbx4q_u8",
-                "vqtbx4_p8",
-                "vqtbx4q_p8",
-                "brk",
-                "_rev_u64",
-                "_clz_u64",
-                "_rbit_u64",
-                "_cls_u32",
-                "_cls_u64",
-                "_prefetch",
-                "vsli_n_s8",
-                "vsliq_n_s8",
-                "vsli_n_s16",
-                "vsliq_n_s16",
-                "vsli_n_s32",
-                "vsliq_n_s32",
-                "vsli_n_s64",
-                "vsliq_n_s64",
-                "vsli_n_u8",
-                "vsliq_n_u8",
-                "vsli_n_u16",
-                "vsliq_n_u16",
-                "vsli_n_u32",
-                "vsliq_n_u32",
-                "vsli_n_u64",
-                "vsliq_n_u64",
-                "vsli_n_p8",
-                "vsliq_n_p8",
-                "vsli_n_p16",
-                "vsliq_n_p16",
-                "vsli_n_p64",
-                "vsliq_n_p64",
-                "vsri_n_s8",
-                "vsriq_n_s8",
-                "vsri_n_s16",
-                "vsriq_n_s16",
-                "vsri_n_s32",
-                "vsriq_n_s32",
-                "vsri_n_s64",
-                "vsriq_n_s64",
-                "vsri_n_u8",
-                "vsriq_n_u8",
-                "vsri_n_u16",
-                "vsriq_n_u16",
-                "vsri_n_u32",
-                "vsriq_n_u32",
-                "vsri_n_u64",
-                "vsriq_n_u64",
-                "vsri_n_p8",
-                "vsriq_n_p8",
-                "vsri_n_p16",
-                "vsriq_n_p16",
-                "vsri_n_p64",
-                "vsriq_n_p64",
-                "__smulbb",
-                "__smultb",
-                "__smulbt",
-                "__smultt",
-                "__smulwb",
-                "__smulwt",
-                "__qadd",
-                "__qsub",
-                "__qdbl",
-                "__smlabb",
-                "__smlabt",
-                "__smlatb",
-                "__smlatt",
-                "__smlawb",
-                "__smlawt",
-                "__qadd8",
-                "__qsub8",
-                "__qsub16",
-                "__qadd16",
-                "__qasx",
-                "__qsax",
-                "__sadd16",
-                "__sadd8",
-                "__smlad",
-                "__smlsd",
-                "__sasx",
-                "__sel",
-                "__shadd8",
-                "__shadd16",
-                "__shsub8",
-                "__usub8",
-                "__ssub8",
-                "__shsub16",
-                "__smuad",
-                "__smuadx",
-                "__smusd",
-                "__smusdx",
-                "__usad8",
-                "__usada8",
-                "__ldrex",
-                "__strex",
-                "__ldrexb",
-                "__strexb",
-                "__ldrexh",
-                "__strexh",
-                "__clrex",
-                "__dbg",
-            ];
+            if !SKIP_RUNTIME_TESTS.contains(&rust.name) {
+                println!(
+                    "missing run-time test named `test_{}` for `{}`",
+                    {
+                        let mut id = rust.name;
+                        while id.starts_with('_') {
+                            id = &id[1..];
+                        }
+                        id
+                    },
+                    rust.name
+                );
+                all_valid = false;
+            }
         }
 
         // Skip some intrinsics that aren't NEON and are located in different
@@ -743,3 +533,4471 @@ fn parse_ty_base(s: &str) -> &'static Type {
         _ => panic!("failed to parse json type {s:?}"),
     }
 }
+
+// FIXME(arm-maintainers): With the advent of the `intrinsic-test` tool, new tests of this kind
+// are no longer being added and just adding to this list indefinitely isn't the best solution for
+// dealing with that.
+static SKIP_RUNTIME_TESTS: &'static [&'static str] = &[
+    "vaddq_s64",
+    "vaddq_u64",
+    "vrsqrte_f32",
+    "vtbl1_s8",
+    "vtbl1_u8",
+    "vtbl1_p8",
+    "vtbl2_s8",
+    "vtbl2_u8",
+    "vtbl2_p8",
+    "vtbl3_s8",
+    "vtbl3_u8",
+    "vtbl3_p8",
+    "vtbl4_s8",
+    "vtbl4_u8",
+    "vtbl4_p8",
+    "vtbx1_s8",
+    "vtbx1_u8",
+    "vtbx1_p8",
+    "vtbx2_s8",
+    "vtbx2_u8",
+    "vtbx2_p8",
+    "vtbx3_s8",
+    "vtbx3_u8",
+    "vtbx3_p8",
+    "vtbx4_s8",
+    "vtbx4_u8",
+    "vtbx4_p8",
+    "udf",
+    "_clz_u8",
+    "_clz_u16",
+    "_clz_u32",
+    "_rbit_u32",
+    "_rev_u16",
+    "_rev_u32",
+    "__breakpoint",
+    "vpminq_f32",
+    "vpminq_f64",
+    "vpmaxq_f32",
+    "vpmaxq_f64",
+    "vcombine_s8",
+    "vcombine_s16",
+    "vcombine_s32",
+    "vcombine_s64",
+    "vcombine_u8",
+    "vcombine_u16",
+    "vcombine_u32",
+    "vcombine_u64",
+    "vcombine_p64",
+    "vcombine_f32",
+    "vcombine_p8",
+    "vcombine_p16",
+    "vcombine_f64",
+    "vtbl1_s8",
+    "vtbl1_u8",
+    "vtbl1_p8",
+    "vtbl2_s8",
+    "vtbl2_u8",
+    "vtbl2_p8",
+    "vtbl3_s8",
+    "vtbl3_u8",
+    "vtbl3_p8",
+    "vtbl4_s8",
+    "vtbl4_u8",
+    "vtbl4_p8",
+    "vtbx1_s8",
+    "vtbx1_u8",
+    "vtbx1_p8",
+    "vtbx2_s8",
+    "vtbx2_u8",
+    "vtbx2_p8",
+    "vtbx3_s8",
+    "vtbx3_u8",
+    "vtbx3_p8",
+    "vtbx4_s8",
+    "vtbx4_u8",
+    "vtbx4_p8",
+    "vqtbl1_s8",
+    "vqtbl1q_s8",
+    "vqtbl1_u8",
+    "vqtbl1q_u8",
+    "vqtbl1_p8",
+    "vqtbl1q_p8",
+    "vqtbx1_s8",
+    "vqtbx1q_s8",
+    "vqtbx1_u8",
+    "vqtbx1q_u8",
+    "vqtbx1_p8",
+    "vqtbx1q_p8",
+    "vqtbl2_s8",
+    "vqtbl2q_s8",
+    "vqtbl2_u8",
+    "vqtbl2q_u8",
+    "vqtbl2_p8",
+    "vqtbl2q_p8",
+    "vqtbx2_s8",
+    "vqtbx2q_s8",
+    "vqtbx2_u8",
+    "vqtbx2q_u8",
+    "vqtbx2_p8",
+    "vqtbx2q_p8",
+    "vqtbl3_s8",
+    "vqtbl3q_s8",
+    "vqtbl3_u8",
+    "vqtbl3q_u8",
+    "vqtbl3_p8",
+    "vqtbl3q_p8",
+    "vqtbx3_s8",
+    "vqtbx3q_s8",
+    "vqtbx3_u8",
+    "vqtbx3q_u8",
+    "vqtbx3_p8",
+    "vqtbx3q_p8",
+    "vqtbl4_s8",
+    "vqtbl4q_s8",
+    "vqtbl4_u8",
+    "vqtbl4q_u8",
+    "vqtbl4_p8",
+    "vqtbl4q_p8",
+    "vqtbx4_s8",
+    "vqtbx4q_s8",
+    "vqtbx4_u8",
+    "vqtbx4q_u8",
+    "vqtbx4_p8",
+    "vqtbx4q_p8",
+    "brk",
+    "_rev_u64",
+    "_clz_u64",
+    "_rbit_u64",
+    "_cls_u32",
+    "_cls_u64",
+    "_prefetch",
+    "vsli_n_s8",
+    "vsliq_n_s8",
+    "vsli_n_s16",
+    "vsliq_n_s16",
+    "vsli_n_s32",
+    "vsliq_n_s32",
+    "vsli_n_s64",
+    "vsliq_n_s64",
+    "vsli_n_u8",
+    "vsliq_n_u8",
+    "vsli_n_u16",
+    "vsliq_n_u16",
+    "vsli_n_u32",
+    "vsliq_n_u32",
+    "vsli_n_u64",
+    "vsliq_n_u64",
+    "vsli_n_p8",
+    "vsliq_n_p8",
+    "vsli_n_p16",
+    "vsliq_n_p16",
+    "vsli_n_p64",
+    "vsliq_n_p64",
+    "vsri_n_s8",
+    "vsriq_n_s8",
+    "vsri_n_s16",
+    "vsriq_n_s16",
+    "vsri_n_s32",
+    "vsriq_n_s32",
+    "vsri_n_s64",
+    "vsriq_n_s64",
+    "vsri_n_u8",
+    "vsriq_n_u8",
+    "vsri_n_u16",
+    "vsriq_n_u16",
+    "vsri_n_u32",
+    "vsriq_n_u32",
+    "vsri_n_u64",
+    "vsriq_n_u64",
+    "vsri_n_p8",
+    "vsriq_n_p8",
+    "vsri_n_p16",
+    "vsriq_n_p16",
+    "vsri_n_p64",
+    "vsriq_n_p64",
+    "__smulbb",
+    "__smultb",
+    "__smulbt",
+    "__smultt",
+    "__smulwb",
+    "__smulwt",
+    "__qadd",
+    "__qsub",
+    "__qdbl",
+    "__smlabb",
+    "__smlabt",
+    "__smlatb",
+    "__smlatt",
+    "__smlawb",
+    "__smlawt",
+    "__qadd8",
+    "__qsub8",
+    "__qsub16",
+    "__qadd16",
+    "__qasx",
+    "__qsax",
+    "__sadd16",
+    "__sadd8",
+    "__smlad",
+    "__smlsd",
+    "__sasx",
+    "__sel",
+    "__shadd8",
+    "__shadd16",
+    "__shsub8",
+    "__usub8",
+    "__ssub8",
+    "__shsub16",
+    "__smuad",
+    "__smuadx",
+    "__smusd",
+    "__smusdx",
+    "__usad8",
+    "__usada8",
+    "__ldrex",
+    "__strex",
+    "__ldrexb",
+    "__strexb",
+    "__ldrexh",
+    "__strexh",
+    "__clrex",
+    "__dbg",
+    "__crc32cd",
+    "__crc32d",
+    "__jcvt",
+    "vabal_high_s8",
+    "vabal_high_s16",
+    "vabal_high_s32",
+    "vabal_high_u8",
+    "vabal_high_u16",
+    "vabal_high_u32",
+    "vabd_f64",
+    "vabdq_f64",
+    "vabdd_f64",
+    "vabds_f32",
+    "vabdh_f16",
+    "vabdl_high_s16",
+    "vabdl_high_s32",
+    "vabdl_high_s8",
+    "vabdl_high_u8",
+    "vabdl_high_u16",
+    "vabdl_high_u32",
+    "vabs_f64",
+    "vabsq_f64",
+    "vabs_s64",
+    "vabsq_s64",
+    "vabsd_s64",
+    "vaddlv_s16",
+    "vaddlvq_s16",
+    "vaddlvq_s32",
+    "vaddlv_s32",
+    "vaddlv_s8",
+    "vaddlvq_s8",
+    "vaddlv_u16",
+    "vaddlvq_u16",
+    "vaddlvq_u32",
+    "vaddlv_u32",
+    "vaddlv_u8",
+    "vaddlvq_u8",
+    "vaddv_f32",
+    "vaddvq_f32",
+    "vaddvq_f64",
+    "vaddv_s32",
+    "vaddv_s8",
+    "vaddvq_s8",
+    "vaddv_s16",
+    "vaddvq_s16",
+    "vaddvq_s32",
+    "vaddv_u32",
+    "vaddv_u8",
+    "vaddvq_u8",
+    "vaddv_u16",
+    "vaddvq_u16",
+    "vaddvq_u32",
+    "vaddvq_s64",
+    "vaddvq_u64",
+    "vamax_f16",
+    "vamaxq_f16",
+    "vamax_f32",
+    "vamaxq_f32",
+    "vamaxq_f64",
+    "vamin_f16",
+    "vaminq_f16",
+    "vamin_f32",
+    "vaminq_f32",
+    "vaminq_f64",
+    "vbcaxq_s8",
+    "vbcaxq_s16",
+    "vbcaxq_s32",
+    "vbcaxq_s64",
+    "vbcaxq_u8",
+    "vbcaxq_u16",
+    "vbcaxq_u32",
+    "vbcaxq_u64",
+    "vcadd_rot270_f16",
+    "vcaddq_rot270_f16",
+    "vcadd_rot270_f32",
+    "vcaddq_rot270_f32",
+    "vcaddq_rot270_f64",
+    "vcadd_rot90_f16",
+    "vcaddq_rot90_f16",
+    "vcadd_rot90_f32",
+    "vcaddq_rot90_f32",
+    "vcaddq_rot90_f64",
+    "vcage_f64",
+    "vcageq_f64",
+    "vcaged_f64",
+    "vcages_f32",
+    "vcageh_f16",
+    "vcagt_f64",
+    "vcagtq_f64",
+    "vcagtd_f64",
+    "vcagts_f32",
+    "vcagth_f16",
+    "vcale_f64",
+    "vcaleq_f64",
+    "vcaled_f64",
+    "vcales_f32",
+    "vcaleh_f16",
+    "vcalt_f64",
+    "vcaltq_f64",
+    "vcaltd_f64",
+    "vcalts_f32",
+    "vcalth_f16",
+    "vceq_f64",
+    "vceqq_f64",
+    "vceq_s64",
+    "vceqq_s64",
+    "vceq_u64",
+    "vceqq_u64",
+    "vceq_p64",
+    "vceqq_p64",
+    "vceqd_f64",
+    "vceqs_f32",
+    "vceqd_s64",
+    "vceqd_u64",
+    "vceqh_f16",
+    "vceqz_f16",
+    "vceqzq_f16",
+    "vceqz_f32",
+    "vceqzq_f32",
+    "vceqz_f64",
+    "vceqzq_f64",
+    "vceqz_s8",
+    "vceqzq_s8",
+    "vceqz_s16",
+    "vceqzq_s16",
+    "vceqz_s32",
+    "vceqzq_s32",
+    "vceqz_s64",
+    "vceqzq_s64",
+    "vceqz_p8",
+    "vceqzq_p8",
+    "vceqz_p64",
+    "vceqzq_p64",
+    "vceqz_u8",
+    "vceqzq_u8",
+    "vceqz_u16",
+    "vceqzq_u16",
+    "vceqz_u32",
+    "vceqzq_u32",
+    "vceqz_u64",
+    "vceqzq_u64",
+    "vceqzd_s64",
+    "vceqzd_u64",
+    "vceqzh_f16",
+    "vceqzs_f32",
+    "vceqzd_f64",
+    "vcge_f64",
+    "vcgeq_f64",
+    "vcge_s64",
+    "vcgeq_s64",
+    "vcge_u64",
+    "vcgeq_u64",
+    "vcged_f64",
+    "vcges_f32",
+    "vcged_s64",
+    "vcged_u64",
+    "vcgeh_f16",
+    "vcgez_f32",
+    "vcgezq_f32",
+    "vcgez_f64",
+    "vcgezq_f64",
+    "vcgez_s8",
+    "vcgezq_s8",
+    "vcgez_s16",
+    "vcgezq_s16",
+    "vcgez_s32",
+    "vcgezq_s32",
+    "vcgez_s64",
+    "vcgezq_s64",
+    "vcgezd_f64",
+    "vcgezs_f32",
+    "vcgezd_s64",
+    "vcgezh_f16",
+    "vcgt_f64",
+    "vcgtq_f64",
+    "vcgt_s64",
+    "vcgtq_s64",
+    "vcgt_u64",
+    "vcgtq_u64",
+    "vcgtd_f64",
+    "vcgts_f32",
+    "vcgtd_s64",
+    "vcgtd_u64",
+    "vcgth_f16",
+    "vcgtz_f32",
+    "vcgtzq_f32",
+    "vcgtz_f64",
+    "vcgtzq_f64",
+    "vcgtz_s8",
+    "vcgtzq_s8",
+    "vcgtz_s16",
+    "vcgtzq_s16",
+    "vcgtz_s32",
+    "vcgtzq_s32",
+    "vcgtz_s64",
+    "vcgtzq_s64",
+    "vcgtzd_f64",
+    "vcgtzs_f32",
+    "vcgtzd_s64",
+    "vcgtzh_f16",
+    "vcle_f64",
+    "vcleq_f64",
+    "vcle_s64",
+    "vcleq_s64",
+    "vcle_u64",
+    "vcleq_u64",
+    "vcled_f64",
+    "vcles_f32",
+    "vcled_u64",
+    "vcled_s64",
+    "vcleh_f16",
+    "vclez_f32",
+    "vclezq_f32",
+    "vclez_f64",
+    "vclezq_f64",
+    "vclez_s8",
+    "vclezq_s8",
+    "vclez_s16",
+    "vclezq_s16",
+    "vclez_s32",
+    "vclezq_s32",
+    "vclez_s64",
+    "vclezq_s64",
+    "vclezd_f64",
+    "vclezs_f32",
+    "vclezd_s64",
+    "vclezh_f16",
+    "vclt_f64",
+    "vcltq_f64",
+    "vclt_s64",
+    "vcltq_s64",
+    "vclt_u64",
+    "vcltq_u64",
+    "vcltd_u64",
+    "vcltd_s64",
+    "vclth_f16",
+    "vclts_f32",
+    "vcltd_f64",
+    "vcltz_f32",
+    "vcltzq_f32",
+    "vcltz_f64",
+    "vcltzq_f64",
+    "vcltz_s8",
+    "vcltzq_s8",
+    "vcltz_s16",
+    "vcltzq_s16",
+    "vcltz_s32",
+    "vcltzq_s32",
+    "vcltz_s64",
+    "vcltzq_s64",
+    "vcltzd_f64",
+    "vcltzs_f32",
+    "vcltzd_s64",
+    "vcltzh_f16",
+    "vcmla_f16",
+    "vcmlaq_f16",
+    "vcmla_f32",
+    "vcmlaq_f32",
+    "vcmlaq_f64",
+    "vcmla_lane_f16",
+    "vcmlaq_lane_f16",
+    "vcmla_lane_f32",
+    "vcmlaq_lane_f32",
+    "vcmla_laneq_f16",
+    "vcmlaq_laneq_f16",
+    "vcmla_laneq_f32",
+    "vcmlaq_laneq_f32",
+    "vcmla_rot180_f16",
+    "vcmlaq_rot180_f16",
+    "vcmla_rot180_f32",
+    "vcmlaq_rot180_f32",
+    "vcmlaq_rot180_f64",
+    "vcmla_rot180_lane_f16",
+    "vcmlaq_rot180_lane_f16",
+    "vcmla_rot180_lane_f32",
+    "vcmlaq_rot180_lane_f32",
+    "vcmla_rot180_laneq_f16",
+    "vcmlaq_rot180_laneq_f16",
+    "vcmla_rot180_laneq_f32",
+    "vcmlaq_rot180_laneq_f32",
+    "vcmla_rot270_f16",
+    "vcmlaq_rot270_f16",
+    "vcmla_rot270_f32",
+    "vcmlaq_rot270_f32",
+    "vcmlaq_rot270_f64",
+    "vcmla_rot270_lane_f16",
+    "vcmlaq_rot270_lane_f16",
+    "vcmla_rot270_lane_f32",
+    "vcmlaq_rot270_lane_f32",
+    "vcmla_rot270_laneq_f16",
+    "vcmlaq_rot270_laneq_f16",
+    "vcmla_rot270_laneq_f32",
+    "vcmlaq_rot270_laneq_f32",
+    "vcmla_rot90_f16",
+    "vcmlaq_rot90_f16",
+    "vcmla_rot90_f32",
+    "vcmlaq_rot90_f32",
+    "vcmlaq_rot90_f64",
+    "vcmla_rot90_lane_f16",
+    "vcmlaq_rot90_lane_f16",
+    "vcmla_rot90_lane_f32",
+    "vcmlaq_rot90_lane_f32",
+    "vcmla_rot90_laneq_f16",
+    "vcmlaq_rot90_laneq_f16",
+    "vcmla_rot90_laneq_f32",
+    "vcmlaq_rot90_laneq_f32",
+    "vcopy_lane_f32",
+    "vcopy_lane_s8",
+    "vcopy_lane_s16",
+    "vcopy_lane_s32",
+    "vcopy_lane_u8",
+    "vcopy_lane_u16",
+    "vcopy_lane_u32",
+    "vcopy_lane_p8",
+    "vcopy_lane_p16",
+    "vcopy_laneq_f32",
+    "vcopy_laneq_s8",
+    "vcopy_laneq_s16",
+    "vcopy_laneq_s32",
+    "vcopy_laneq_u8",
+    "vcopy_laneq_u16",
+    "vcopy_laneq_u32",
+    "vcopy_laneq_p8",
+    "vcopy_laneq_p16",
+    "vcopyq_lane_f32",
+    "vcopyq_lane_f64",
+    "vcopyq_lane_s64",
+    "vcopyq_lane_u64",
+    "vcopyq_lane_p64",
+    "vcopyq_lane_s8",
+    "vcopyq_lane_s16",
+    "vcopyq_lane_s32",
+    "vcopyq_lane_u8",
+    "vcopyq_lane_u16",
+    "vcopyq_lane_u32",
+    "vcopyq_lane_p8",
+    "vcopyq_lane_p16",
+    "vcopyq_laneq_f32",
+    "vcopyq_laneq_f64",
+    "vcopyq_laneq_s8",
+    "vcopyq_laneq_s16",
+    "vcopyq_laneq_s32",
+    "vcopyq_laneq_s64",
+    "vcopyq_laneq_u8",
+    "vcopyq_laneq_u16",
+    "vcopyq_laneq_u32",
+    "vcopyq_laneq_u64",
+    "vcopyq_laneq_p8",
+    "vcopyq_laneq_p16",
+    "vcopyq_laneq_p64",
+    "vcreate_f64",
+    "vcvt_f32_f64",
+    "vcvt_f64_f32",
+    "vcvt_f64_s64",
+    "vcvtq_f64_s64",
+    "vcvt_f64_u64",
+    "vcvtq_f64_u64",
+    "vcvt_high_f16_f32",
+    "vcvt_high_f32_f16",
+    "vcvt_high_f32_f64",
+    "vcvt_high_f64_f32",
+    "vcvt_n_f64_s64",
+    "vcvtq_n_f64_s64",
+    "vcvt_n_f64_u64",
+    "vcvtq_n_f64_u64",
+    "vcvt_n_s64_f64",
+    "vcvtq_n_s64_f64",
+    "vcvt_n_u64_f64",
+    "vcvtq_n_u64_f64",
+    "vcvt_s64_f64",
+    "vcvtq_s64_f64",
+    "vcvt_u64_f64",
+    "vcvtq_u64_f64",
+    "vcvta_s16_f16",
+    "vcvtaq_s16_f16",
+    "vcvta_s32_f32",
+    "vcvtaq_s32_f32",
+    "vcvta_s64_f64",
+    "vcvtaq_s64_f64",
+    "vcvta_u16_f16",
+    "vcvtaq_u16_f16",
+    "vcvta_u32_f32",
+    "vcvtaq_u32_f32",
+    "vcvta_u64_f64",
+    "vcvtaq_u64_f64",
+    "vcvtah_s16_f16",
+    "vcvtah_s32_f16",
+    "vcvtah_s64_f16",
+    "vcvtah_u16_f16",
+    "vcvtah_u32_f16",
+    "vcvtah_u64_f16",
+    "vcvtas_s32_f32",
+    "vcvtad_s64_f64",
+    "vcvtas_u32_f32",
+    "vcvtad_u64_f64",
+    "vcvtd_f64_s64",
+    "vcvts_f32_s32",
+    "vcvth_f16_s16",
+    "vcvth_f16_s32",
+    "vcvth_f16_s64",
+    "vcvth_f16_u16",
+    "vcvth_f16_u32",
+    "vcvth_f16_u64",
+    "vcvth_n_f16_s16",
+    "vcvth_n_f16_s32",
+    "vcvth_n_f16_s64",
+    "vcvth_n_f16_u16",
+    "vcvth_n_f16_u32",
+    "vcvth_n_f16_u64",
+    "vcvth_n_s16_f16",
+    "vcvth_n_s32_f16",
+    "vcvth_n_s64_f16",
+    "vcvth_n_u16_f16",
+    "vcvth_n_u32_f16",
+    "vcvth_n_u64_f16",
+    "vcvth_s16_f16",
+    "vcvth_s32_f16",
+    "vcvth_s64_f16",
+    "vcvth_u16_f16",
+    "vcvth_u32_f16",
+    "vcvth_u64_f16",
+    "vcvtm_s16_f16",
+    "vcvtmq_s16_f16",
+    "vcvtm_s32_f32",
+    "vcvtmq_s32_f32",
+    "vcvtm_s64_f64",
+    "vcvtmq_s64_f64",
+    "vcvtm_u16_f16",
+    "vcvtmq_u16_f16",
+    "vcvtm_u32_f32",
+    "vcvtmq_u32_f32",
+    "vcvtm_u64_f64",
+    "vcvtmq_u64_f64",
+    "vcvtmh_s16_f16",
+    "vcvtmh_s32_f16",
+    "vcvtmh_s64_f16",
+    "vcvtmh_u16_f16",
+    "vcvtmh_u32_f16",
+    "vcvtmh_u64_f16",
+    "vcvtms_s32_f32",
+    "vcvtmd_s64_f64",
+    "vcvtms_u32_f32",
+    "vcvtmd_u64_f64",
+    "vcvtn_s16_f16",
+    "vcvtnq_s16_f16",
+    "vcvtn_s32_f32",
+    "vcvtnq_s32_f32",
+    "vcvtn_s64_f64",
+    "vcvtnq_s64_f64",
+    "vcvtn_u16_f16",
+    "vcvtnq_u16_f16",
+    "vcvtn_u32_f32",
+    "vcvtnq_u32_f32",
+    "vcvtn_u64_f64",
+    "vcvtnq_u64_f64",
+    "vcvtnh_s16_f16",
+    "vcvtnh_s32_f16",
+    "vcvtnh_s64_f16",
+    "vcvtnh_u16_f16",
+    "vcvtnh_u32_f16",
+    "vcvtnh_u64_f16",
+    "vcvtns_s32_f32",
+    "vcvtnd_s64_f64",
+    "vcvtns_u32_f32",
+    "vcvtnd_u64_f64",
+    "vcvtp_s16_f16",
+    "vcvtpq_s16_f16",
+    "vcvtp_s32_f32",
+    "vcvtpq_s32_f32",
+    "vcvtp_s64_f64",
+    "vcvtpq_s64_f64",
+    "vcvtp_u16_f16",
+    "vcvtpq_u16_f16",
+    "vcvtp_u32_f32",
+    "vcvtpq_u32_f32",
+    "vcvtp_u64_f64",
+    "vcvtpq_u64_f64",
+    "vcvtph_s16_f16",
+    "vcvtph_s32_f16",
+    "vcvtph_s64_f16",
+    "vcvtph_u16_f16",
+    "vcvtph_u32_f16",
+    "vcvtph_u64_f16",
+    "vcvtps_s32_f32",
+    "vcvtpd_s64_f64",
+    "vcvtps_u32_f32",
+    "vcvtpd_u64_f64",
+    "vcvts_f32_u32",
+    "vcvtd_f64_u64",
+    "vcvts_n_f32_s32",
+    "vcvtd_n_f64_s64",
+    "vcvts_n_f32_u32",
+    "vcvtd_n_f64_u64",
+    "vcvts_n_s32_f32",
+    "vcvtd_n_s64_f64",
+    "vcvts_n_u32_f32",
+    "vcvtd_n_u64_f64",
+    "vcvts_s32_f32",
+    "vcvtd_s64_f64",
+    "vcvts_u32_f32",
+    "vcvtd_u64_f64",
+    "vcvtx_f32_f64",
+    "vcvtx_high_f32_f64",
+    "vcvtxd_f32_f64",
+    "vdiv_f16",
+    "vdivq_f16",
+    "vdiv_f32",
+    "vdivq_f32",
+    "vdiv_f64",
+    "vdivq_f64",
+    "vdivh_f16",
+    "vdup_lane_f64",
+    "vdup_lane_p64",
+    "vdup_laneq_f64",
+    "vdup_laneq_p64",
+    "vdupb_lane_s8",
+    "vduph_laneq_s16",
+    "vdupb_lane_u8",
+    "vduph_laneq_u16",
+    "vdupb_lane_p8",
+    "vduph_laneq_p16",
+    "vdupb_laneq_s8",
+    "vdupb_laneq_u8",
+    "vdupb_laneq_p8",
+    "vdupd_lane_f64",
+    "vdupd_lane_s64",
+    "vdupd_lane_u64",
+    "vduph_lane_f16",
+    "vduph_laneq_f16",
+    "vdupq_lane_f64",
+    "vdupq_lane_p64",
+    "vdupq_laneq_f64",
+    "vdupq_laneq_p64",
+    "vdups_lane_f32",
+    "vdupd_laneq_f64",
+    "vdups_lane_s32",
+    "vdupd_laneq_s64",
+    "vdups_lane_u32",
+    "vdupd_laneq_u64",
+    "vdups_laneq_f32",
+    "vduph_lane_s16",
+    "vdups_laneq_s32",
+    "vduph_lane_u16",
+    "vdups_laneq_u32",
+    "vduph_lane_p16",
+    "veor3q_s8",
+    "veor3q_s16",
+    "veor3q_s32",
+    "veor3q_s64",
+    "veor3q_u8",
+    "veor3q_u16",
+    "veor3q_u32",
+    "veor3q_u64",
+    "vextq_f64",
+    "vextq_p64",
+    "vfma_f64",
+    "vfma_lane_f16",
+    "vfma_laneq_f16",
+    "vfmaq_lane_f16",
+    "vfmaq_laneq_f16",
+    "vfma_lane_f32",
+    "vfma_laneq_f32",
+    "vfmaq_lane_f32",
+    "vfmaq_laneq_f32",
+    "vfmaq_laneq_f64",
+    "vfma_lane_f64",
+    "vfma_laneq_f64",
+    "vfma_n_f16",
+    "vfmaq_n_f16",
+    "vfma_n_f64",
+    "vfmad_lane_f64",
+    "vfmah_f16",
+    "vfmah_lane_f16",
+    "vfmah_laneq_f16",
+    "vfmaq_f64",
+    "vfmaq_lane_f64",
+    "vfmaq_n_f64",
+    "vfmas_lane_f32",
+    "vfmas_laneq_f32",
+    "vfmad_laneq_f64",
+    "vfmlal_high_f16",
+    "vfmlalq_high_f16",
+    "vfmlal_lane_high_f16",
+    "vfmlal_laneq_high_f16",
+    "vfmlalq_lane_high_f16",
+    "vfmlalq_laneq_high_f16",
+    "vfmlal_lane_low_f16",
+    "vfmlal_laneq_low_f16",
+    "vfmlalq_lane_low_f16",
+    "vfmlalq_laneq_low_f16",
+    "vfmlal_low_f16",
+    "vfmlalq_low_f16",
+    "vfmlsl_high_f16",
+    "vfmlslq_high_f16",
+    "vfmlsl_lane_high_f16",
+    "vfmlsl_laneq_high_f16",
+    "vfmlslq_lane_high_f16",
+    "vfmlslq_laneq_high_f16",
+    "vfmlsl_lane_low_f16",
+    "vfmlsl_laneq_low_f16",
+    "vfmlslq_lane_low_f16",
+    "vfmlslq_laneq_low_f16",
+    "vfmlsl_low_f16",
+    "vfmlslq_low_f16",
+    "vfms_f64",
+    "vfms_lane_f16",
+    "vfms_laneq_f16",
+    "vfmsq_lane_f16",
+    "vfmsq_laneq_f16",
+    "vfms_lane_f32",
+    "vfms_laneq_f32",
+    "vfmsq_lane_f32",
+    "vfmsq_laneq_f32",
+    "vfmsq_laneq_f64",
+    "vfms_lane_f64",
+    "vfms_laneq_f64",
+    "vfms_n_f16",
+    "vfmsq_n_f16",
+    "vfms_n_f64",
+    "vfmsh_f16",
+    "vfmsh_lane_f16",
+    "vfmsh_laneq_f16",
+    "vfmsq_f64",
+    "vfmsq_lane_f64",
+    "vfmsq_n_f64",
+    "vfmss_lane_f32",
+    "vfmss_laneq_f32",
+    "vfmsd_lane_f64",
+    "vfmsd_laneq_f64",
+    "vld1_f16",
+    "vld1q_f16",
+    "vld1_f64_x2",
+    "vld1_f64_x3",
+    "vld1_f64_x4",
+    "vld1q_f64_x2",
+    "vld1q_f64_x3",
+    "vld1q_f64_x4",
+    "vld2_dup_f64",
+    "vld2q_dup_f64",
+    "vld2q_dup_s64",
+    "vld2_f64",
+    "vld2_lane_f64",
+    "vld2_lane_s64",
+    "vld2_lane_p64",
+    "vld2_lane_u64",
+    "vld2q_dup_p64",
+    "vld2q_dup_p64",
+    "vld2q_dup_u64",
+    "vld2q_dup_u64",
+    "vld2q_f64",
+    "vld2q_s64",
+    "vld2q_lane_f64",
+    "vld2q_lane_s8",
+    "vld2q_lane_s64",
+    "vld2q_lane_p64",
+    "vld2q_lane_u8",
+    "vld2q_lane_u64",
+    "vld2q_lane_p8",
+    "vld2q_p64",
+    "vld2q_p64",
+    "vld2q_u64",
+    "vld3_dup_f64",
+    "vld3q_dup_f64",
+    "vld3q_dup_s64",
+    "vld3_f64",
+    "vld3_lane_f64",
+    "vld3_lane_p64",
+    "vld3_lane_s64",
+    "vld3_lane_u64",
+    "vld3q_dup_p64",
+    "vld3q_dup_p64",
+    "vld3q_dup_u64",
+    "vld3q_dup_u64",
+    "vld3q_f64",
+    "vld3q_s64",
+    "vld3q_lane_f64",
+    "vld3q_lane_p64",
+    "vld3q_lane_s8",
+    "vld3q_lane_s64",
+    "vld3q_lane_u8",
+    "vld3q_lane_u64",
+    "vld3q_lane_p8",
+    "vld3q_p64",
+    "vld3q_p64",
+    "vld3q_u64",
+    "vld4_dup_f64",
+    "vld4q_dup_f64",
+    "vld4q_dup_s64",
+    "vld4_f64",
+    "vld4_lane_f64",
+    "vld4_lane_s64",
+    "vld4_lane_p64",
+    "vld4_lane_u64",
+    "vld4q_dup_p64",
+    "vld4q_dup_p64",
+    "vld4q_dup_u64",
+    "vld4q_dup_u64",
+    "vld4q_f64",
+    "vld4q_s64",
+    "vld4q_lane_f64",
+    "vld4q_lane_s8",
+    "vld4q_lane_s64",
+    "vld4q_lane_p64",
+    "vld4q_lane_u8",
+    "vld4q_lane_u64",
+    "vld4q_lane_p8",
+    "vld4q_p64",
+    "vld4q_p64",
+    "vld4q_u64",
+    "vldap1_lane_s64",
+    "vldap1q_lane_s64",
+    "vldap1q_lane_f64",
+    "vldap1_lane_u64",
+    "vldap1q_lane_u64",
+    "vldap1_lane_p64",
+    "vldap1q_lane_p64",
+    "vluti2_lane_f16",
+    "vluti2q_lane_f16",
+    "vluti2_lane_u8",
+    "vluti2q_lane_u8",
+    "vluti2_lane_u16",
+    "vluti2q_lane_u16",
+    "vluti2_lane_p8",
+    "vluti2q_lane_p8",
+    "vluti2_lane_p16",
+    "vluti2q_lane_p16",
+    "vluti2_lane_s8",
+    "vluti2q_lane_s8",
+    "vluti2_lane_s16",
+    "vluti2q_lane_s16",
+    "vluti2_laneq_f16",
+    "vluti2q_laneq_f16",
+    "vluti2_laneq_u8",
+    "vluti2q_laneq_u8",
+    "vluti2_laneq_u16",
+    "vluti2q_laneq_u16",
+    "vluti2_laneq_p8",
+    "vluti2q_laneq_p8",
+    "vluti2_laneq_p16",
+    "vluti2q_laneq_p16",
+    "vluti2_laneq_s8",
+    "vluti2q_laneq_s8",
+    "vluti2_laneq_s16",
+    "vluti2q_laneq_s16",
+    "vluti4q_lane_f16_x2",
+    "vluti4q_lane_u16_x2",
+    "vluti4q_lane_p16_x2",
+    "vluti4q_lane_s16_x2",
+    "vluti4q_lane_s8",
+    "vluti4q_lane_u8",
+    "vluti4q_lane_p8",
+    "vluti4q_laneq_f16_x2",
+    "vluti4q_laneq_u16_x2",
+    "vluti4q_laneq_p16_x2",
+    "vluti4q_laneq_s16_x2",
+    "vluti4q_laneq_s8",
+    "vluti4q_laneq_u8",
+    "vluti4q_laneq_p8",
+    "vmax_f64",
+    "vmaxq_f64",
+    "vmaxh_f16",
+    "vmaxnm_f64",
+    "vmaxnmq_f64",
+    "vmaxnmh_f16",
+    "vmaxnmv_f16",
+    "vmaxnmvq_f16",
+    "vmaxnmv_f32",
+    "vmaxnmvq_f64",
+    "vmaxnmvq_f32",
+    "vmaxv_f16",
+    "vmaxvq_f16",
+    "vmaxv_f32",
+    "vmaxvq_f32",
+    "vmaxvq_f64",
+    "vmaxv_s8",
+    "vmaxvq_s8",
+    "vmaxv_s16",
+    "vmaxvq_s16",
+    "vmaxv_s32",
+    "vmaxvq_s32",
+    "vmaxv_u8",
+    "vmaxvq_u8",
+    "vmaxv_u16",
+    "vmaxvq_u16",
+    "vmaxv_u32",
+    "vmaxvq_u32",
+    "vmin_f64",
+    "vminq_f64",
+    "vminh_f16",
+    "vminnm_f64",
+    "vminnmq_f64",
+    "vminnmh_f16",
+    "vminnmv_f16",
+    "vminnmvq_f16",
+    "vminnmv_f32",
+    "vminnmvq_f64",
+    "vminnmvq_f32",
+    "vminv_f16",
+    "vminvq_f16",
+    "vminv_f32",
+    "vminvq_f32",
+    "vminvq_f64",
+    "vminv_s8",
+    "vminvq_s8",
+    "vminv_s16",
+    "vminvq_s16",
+    "vminv_s32",
+    "vminvq_s32",
+    "vminv_u8",
+    "vminvq_u8",
+    "vminv_u16",
+    "vminvq_u16",
+    "vminv_u32",
+    "vminvq_u32",
+    "vmla_f64",
+    "vmlaq_f64",
+    "vmlal_high_lane_s16",
+    "vmlal_high_laneq_s16",
+    "vmlal_high_lane_s32",
+    "vmlal_high_laneq_s32",
+    "vmlal_high_lane_u16",
+    "vmlal_high_laneq_u16",
+    "vmlal_high_lane_u32",
+    "vmlal_high_laneq_u32",
+    "vmlal_high_n_s16",
+    "vmlal_high_n_s32",
+    "vmlal_high_n_u16",
+    "vmlal_high_n_u32",
+    "vmlal_high_s8",
+    "vmlal_high_s16",
+    "vmlal_high_s32",
+    "vmlal_high_u8",
+    "vmlal_high_u16",
+    "vmlal_high_u32",
+    "vmls_f64",
+    "vmlsq_f64",
+    "vmlsl_high_lane_s16",
+    "vmlsl_high_laneq_s16",
+    "vmlsl_high_lane_s32",
+    "vmlsl_high_laneq_s32",
+    "vmlsl_high_lane_u16",
+    "vmlsl_high_laneq_u16",
+    "vmlsl_high_lane_u32",
+    "vmlsl_high_laneq_u32",
+    "vmlsl_high_n_s16",
+    "vmlsl_high_n_s32",
+    "vmlsl_high_n_u16",
+    "vmlsl_high_n_u32",
+    "vmlsl_high_s8",
+    "vmlsl_high_s16",
+    "vmlsl_high_s32",
+    "vmlsl_high_u8",
+    "vmlsl_high_u16",
+    "vmlsl_high_u32",
+    "vmovl_high_s8",
+    "vmovl_high_s16",
+    "vmovl_high_s32",
+    "vmovl_high_u8",
+    "vmovl_high_u16",
+    "vmovl_high_u32",
+    "vmovn_high_s16",
+    "vmovn_high_s32",
+    "vmovn_high_s64",
+    "vmovn_high_u16",
+    "vmovn_high_u32",
+    "vmovn_high_u64",
+    "vmul_f64",
+    "vmulq_f64",
+    "vmul_lane_f64",
+    "vmul_laneq_f16",
+    "vmulq_laneq_f16",
+    "vmul_laneq_f64",
+    "vmul_n_f64",
+    "vmulq_n_f64",
+    "vmuld_lane_f64",
+    "vmulh_f16",
+    "vmulh_lane_f16",
+    "vmulh_laneq_f16",
+    "vmull_high_lane_s16",
+    "vmull_high_laneq_s16",
+    "vmull_high_lane_s32",
+    "vmull_high_laneq_s32",
+    "vmull_high_lane_u16",
+    "vmull_high_laneq_u16",
+    "vmull_high_lane_u32",
+    "vmull_high_laneq_u32",
+    "vmull_high_n_s16",
+    "vmull_high_n_s32",
+    "vmull_high_n_u16",
+    "vmull_high_n_u32",
+    "vmull_high_p64",
+    "vmull_high_p8",
+    "vmull_high_s8",
+    "vmull_high_s16",
+    "vmull_high_s32",
+    "vmull_high_u8",
+    "vmull_high_u16",
+    "vmull_high_u32",
+    "vmull_p64",
+    "vmulq_lane_f64",
+    "vmulq_laneq_f64",
+    "vmuls_lane_f32",
+    "vmuls_laneq_f32",
+    "vmuld_laneq_f64",
+    "vmulx_f16",
+    "vmulxq_f16",
+    "vmulx_f32",
+    "vmulxq_f32",
+    "vmulx_f64",
+    "vmulxq_f64",
+    "vmulx_lane_f16",
+    "vmulx_laneq_f16",
+    "vmulxq_lane_f16",
+    "vmulxq_laneq_f16",
+    "vmulx_lane_f32",
+    "vmulx_laneq_f32",
+    "vmulxq_lane_f32",
+    "vmulxq_laneq_f32",
+    "vmulxq_laneq_f64",
+    "vmulx_lane_f64",
+    "vmulx_laneq_f64",
+    "vmulx_n_f16",
+    "vmulxq_n_f16",
+    "vmulxd_f64",
+    "vmulxs_f32",
+    "vmulxd_lane_f64",
+    "vmulxd_laneq_f64",
+    "vmulxs_lane_f32",
+    "vmulxs_laneq_f32",
+    "vmulxh_f16",
+    "vmulxh_lane_f16",
+    "vmulxh_laneq_f16",
+    "vmulxq_lane_f64",
+    "vneg_f64",
+    "vnegq_f64",
+    "vneg_s64",
+    "vnegq_s64",
+    "vnegd_s64",
+    "vnegh_f16",
+    "vpaddd_f64",
+    "vpadds_f32",
+    "vpaddd_s64",
+    "vpaddd_u64",
+    "vpaddq_f16",
+    "vpaddq_f32",
+    "vpaddq_f64",
+    "vpaddq_s8",
+    "vpaddq_s16",
+    "vpaddq_s32",
+    "vpaddq_s64",
+    "vpaddq_u8",
+    "vpaddq_u16",
+    "vpaddq_u32",
+    "vpaddq_u64",
+    "vpmax_f16",
+    "vpmaxq_f16",
+    "vpmaxnm_f16",
+    "vpmaxnmq_f16",
+    "vpmaxnm_f32",
+    "vpmaxnmq_f32",
+    "vpmaxnmq_f64",
+    "vpmaxnmqd_f64",
+    "vpmaxnms_f32",
+    "vpmaxq_s8",
+    "vpmaxq_s16",
+    "vpmaxq_s32",
+    "vpmaxq_u8",
+    "vpmaxq_u16",
+    "vpmaxq_u32",
+    "vpmaxqd_f64",
+    "vpmaxs_f32",
+    "vpmin_f16",
+    "vpminq_f16",
+    "vpminnm_f16",
+    "vpminnmq_f16",
+    "vpminnm_f32",
+    "vpminnmq_f32",
+    "vpminnmq_f64",
+    "vpminnmqd_f64",
+    "vpminnms_f32",
+    "vpminq_s8",
+    "vpminq_s16",
+    "vpminq_s32",
+    "vpminq_u8",
+    "vpminq_u16",
+    "vpminq_u32",
+    "vpminqd_f64",
+    "vpmins_f32",
+    "vqabs_s64",
+    "vqabsq_s64",
+    "vqabsb_s8",
+    "vqabsh_s16",
+    "vqabss_s32",
+    "vqabsd_s64",
+    "vqaddb_s8",
+    "vqaddh_s16",
+    "vqaddb_u8",
+    "vqaddh_u16",
+    "vqadds_s32",
+    "vqaddd_s64",
+    "vqadds_u32",
+    "vqaddd_u64",
+    "vqdmlal_high_lane_s16",
+    "vqdmlal_high_laneq_s16",
+    "vqdmlal_high_lane_s32",
+    "vqdmlal_high_laneq_s32",
+    "vqdmlal_high_n_s16",
+    "vqdmlal_high_s16",
+    "vqdmlal_high_n_s32",
+    "vqdmlal_high_s32",
+    "vqdmlal_laneq_s16",
+    "vqdmlal_laneq_s32",
+    "vqdmlalh_lane_s16",
+    "vqdmlalh_laneq_s16",
+    "vqdmlals_lane_s32",
+    "vqdmlals_laneq_s32",
+    "vqdmlalh_s16",
+    "vqdmlals_s32",
+    "vqdmlsl_high_lane_s16",
+    "vqdmlsl_high_laneq_s16",
+    "vqdmlsl_high_lane_s32",
+    "vqdmlsl_high_laneq_s32",
+    "vqdmlsl_high_n_s16",
+    "vqdmlsl_high_s16",
+    "vqdmlsl_high_n_s32",
+    "vqdmlsl_high_s32",
+    "vqdmlsl_laneq_s16",
+    "vqdmlsl_laneq_s32",
+    "vqdmlslh_lane_s16",
+    "vqdmlslh_laneq_s16",
+    "vqdmlsls_lane_s32",
+    "vqdmlsls_laneq_s32",
+    "vqdmlslh_s16",
+    "vqdmlsls_s32",
+    "vqdmulh_lane_s16",
+    "vqdmulhq_lane_s16",
+    "vqdmulh_lane_s32",
+    "vqdmulhq_lane_s32",
+    "vqdmulhh_lane_s16",
+    "vqdmulhh_laneq_s16",
+    "vqdmulhh_s16",
+    "vqdmulhs_s32",
+    "vqdmulhs_lane_s32",
+    "vqdmulhs_laneq_s32",
+    "vqdmull_high_lane_s16",
+    "vqdmull_high_laneq_s32",
+    "vqdmull_high_lane_s32",
+    "vqdmull_high_laneq_s16",
+    "vqdmull_high_n_s16",
+    "vqdmull_high_n_s32",
+    "vqdmull_high_s16",
+    "vqdmull_high_s32",
+    "vqdmull_laneq_s16",
+    "vqdmull_laneq_s32",
+    "vqdmullh_lane_s16",
+    "vqdmulls_laneq_s32",
+    "vqdmullh_laneq_s16",
+    "vqdmullh_s16",
+    "vqdmulls_lane_s32",
+    "vqdmulls_s32",
+    "vqmovn_high_s16",
+    "vqmovn_high_s32",
+    "vqmovn_high_s64",
+    "vqmovn_high_u16",
+    "vqmovn_high_u32",
+    "vqmovn_high_u64",
+    "vqmovnd_s64",
+    "vqmovnd_u64",
+    "vqmovnh_s16",
+    "vqmovns_s32",
+    "vqmovnh_u16",
+    "vqmovns_u32",
+    "vqmovun_high_s16",
+    "vqmovun_high_s32",
+    "vqmovun_high_s64",
+    "vqmovunh_s16",
+    "vqmovuns_s32",
+    "vqmovund_s64",
+    "vqneg_s64",
+    "vqnegq_s64",
+    "vqnegb_s8",
+    "vqnegh_s16",
+    "vqnegs_s32",
+    "vqnegd_s64",
+    "vqrdmlah_lane_s16",
+    "vqrdmlah_lane_s32",
+    "vqrdmlah_laneq_s16",
+    "vqrdmlah_laneq_s32",
+    "vqrdmlahq_lane_s16",
+    "vqrdmlahq_lane_s32",
+    "vqrdmlahq_laneq_s16",
+    "vqrdmlahq_laneq_s32",
+    "vqrdmlah_s16",
+    "vqrdmlahq_s16",
+    "vqrdmlah_s32",
+    "vqrdmlahq_s32",
+    "vqrdmlahh_lane_s16",
+    "vqrdmlahh_laneq_s16",
+    "vqrdmlahs_lane_s32",
+    "vqrdmlahs_laneq_s32",
+    "vqrdmlahh_s16",
+    "vqrdmlahs_s32",
+    "vqrdmlsh_lane_s16",
+    "vqrdmlsh_lane_s32",
+    "vqrdmlsh_laneq_s16",
+    "vqrdmlsh_laneq_s32",
+    "vqrdmlshq_lane_s16",
+    "vqrdmlshq_lane_s32",
+    "vqrdmlshq_laneq_s16",
+    "vqrdmlshq_laneq_s32",
+    "vqrdmlsh_s16",
+    "vqrdmlshq_s16",
+    "vqrdmlsh_s32",
+    "vqrdmlshq_s32",
+    "vqrdmlshh_lane_s16",
+    "vqrdmlshh_laneq_s16",
+    "vqrdmlshs_lane_s32",
+    "vqrdmlshs_laneq_s32",
+    "vqrdmlshh_s16",
+    "vqrdmlshs_s32",
+    "vqrdmulhh_lane_s16",
+    "vqrdmulhh_laneq_s16",
+    "vqrdmulhs_lane_s32",
+    "vqrdmulhs_laneq_s32",
+    "vqrdmulhh_s16",
+    "vqrdmulhs_s32",
+    "vqrshlb_s8",
+    "vqrshlh_s16",
+    "vqrshlb_u8",
+    "vqrshlh_u16",
+    "vqrshld_s64",
+    "vqrshls_s32",
+    "vqrshls_u32",
+    "vqrshld_u64",
+    "vqrshrn_high_n_s16",
+    "vqrshrn_high_n_s32",
+    "vqrshrn_high_n_s64",
+    "vqrshrn_high_n_u16",
+    "vqrshrn_high_n_u32",
+    "vqrshrn_high_n_u64",
+    "vqrshrnd_n_u64",
+    "vqrshrnh_n_u16",
+    "vqrshrns_n_u32",
+    "vqrshrnh_n_s16",
+    "vqrshrns_n_s32",
+    "vqrshrnd_n_s64",
+    "vqrshrun_high_n_s16",
+    "vqrshrun_high_n_s32",
+    "vqrshrun_high_n_s64",
+    "vqrshrund_n_s64",
+    "vqrshrunh_n_s16",
+    "vqrshruns_n_s32",
+    "vqshlb_n_s8",
+    "vqshld_n_s64",
+    "vqshlh_n_s16",
+    "vqshls_n_s32",
+    "vqshlb_n_u8",
+    "vqshld_n_u64",
+    "vqshlh_n_u16",
+    "vqshls_n_u32",
+    "vqshlb_s8",
+    "vqshlh_s16",
+    "vqshls_s32",
+    "vqshlb_u8",
+    "vqshlh_u16",
+    "vqshls_u32",
+    "vqshld_s64",
+    "vqshld_u64",
+    "vqshlub_n_s8",
+    "vqshlud_n_s64",
+    "vqshluh_n_s16",
+    "vqshlus_n_s32",
+    "vqshrn_high_n_s16",
+    "vqshrn_high_n_s32",
+    "vqshrn_high_n_s64",
+    "vqshrn_high_n_u16",
+    "vqshrn_high_n_u32",
+    "vqshrn_high_n_u64",
+    "vqshrnd_n_s64",
+    "vqshrnd_n_u64",
+    "vqshrnh_n_s16",
+    "vqshrns_n_s32",
+    "vqshrnh_n_u16",
+    "vqshrns_n_u32",
+    "vqshrun_high_n_s16",
+    "vqshrun_high_n_s32",
+    "vqshrun_high_n_s64",
+    "vqshrund_n_s64",
+    "vqshrunh_n_s16",
+    "vqshruns_n_s32",
+    "vqsubb_s8",
+    "vqsubh_s16",
+    "vqsubb_u8",
+    "vqsubh_u16",
+    "vqsubs_s32",
+    "vqsubd_s64",
+    "vqsubs_u32",
+    "vqsubd_u64",
+    "vrax1q_u64",
+    "vrbit_s8",
+    "vrbitq_s8",
+    "vrbit_u8",
+    "vrbit_u8",
+    "vrbitq_u8",
+    "vrbitq_u8",
+    "vrbit_p8",
+    "vrbit_p8",
+    "vrbitq_p8",
+    "vrbitq_p8",
+    "vrecpe_f64",
+    "vrecpeq_f64",
+    "vrecped_f64",
+    "vrecpes_f32",
+    "vrecpeh_f16",
+    "vrecps_f64",
+    "vrecpsq_f64",
+    "vrecpsd_f64",
+    "vrecpss_f32",
+    "vrecpsh_f16",
+    "vrecpxd_f64",
+    "vrecpxs_f32",
+    "vrecpxh_f16",
+    "vreinterpret_f64_f16",
+    "vreinterpret_f64_f16",
+    "vreinterpretq_f64_f16",
+    "vreinterpretq_f64_f16",
+    "vreinterpret_f16_f64",
+    "vreinterpret_f16_f64",
+    "vreinterpretq_f16_f64",
+    "vreinterpretq_f16_f64",
+    "vreinterpretq_f64_p128",
+    "vreinterpretq_f64_p128",
+    "vreinterpret_f64_f32",
+    "vreinterpret_f64_f32",
+    "vreinterpret_p64_f32",
+    "vreinterpret_p64_f32",
+    "vreinterpretq_f64_f32",
+    "vreinterpretq_f64_f32",
+    "vreinterpretq_p64_f32",
+    "vreinterpretq_p64_f32",
+    "vreinterpret_f32_f64",
+    "vreinterpret_f32_f64",
+    "vreinterpret_s8_f64",
+    "vreinterpret_s8_f64",
+    "vreinterpret_s16_f64",
+    "vreinterpret_s16_f64",
+    "vreinterpret_s32_f64",
+    "vreinterpret_s32_f64",
+    "vreinterpret_s64_f64",
+    "vreinterpret_u8_f64",
+    "vreinterpret_u8_f64",
+    "vreinterpret_u16_f64",
+    "vreinterpret_u16_f64",
+    "vreinterpret_u32_f64",
+    "vreinterpret_u32_f64",
+    "vreinterpret_u64_f64",
+    "vreinterpret_p8_f64",
+    "vreinterpret_p8_f64",
+    "vreinterpret_p16_f64",
+    "vreinterpret_p16_f64",
+    "vreinterpret_p64_f64",
+    "vreinterpretq_p128_f64",
+    "vreinterpretq_p128_f64",
+    "vreinterpretq_f32_f64",
+    "vreinterpretq_f32_f64",
+    "vreinterpretq_s8_f64",
+    "vreinterpretq_s8_f64",
+    "vreinterpretq_s16_f64",
+    "vreinterpretq_s16_f64",
+    "vreinterpretq_s32_f64",
+    "vreinterpretq_s32_f64",
+    "vreinterpretq_s64_f64",
+    "vreinterpretq_s64_f64",
+    "vreinterpretq_u8_f64",
+    "vreinterpretq_u8_f64",
+    "vreinterpretq_u16_f64",
+    "vreinterpretq_u16_f64",
+    "vreinterpretq_u32_f64",
+    "vreinterpretq_u32_f64",
+    "vreinterpretq_u64_f64",
+    "vreinterpretq_u64_f64",
+    "vreinterpretq_p8_f64",
+    "vreinterpretq_p8_f64",
+    "vreinterpretq_p16_f64",
+    "vreinterpretq_p16_f64",
+    "vreinterpretq_p64_f64",
+    "vreinterpretq_p64_f64",
+    "vreinterpret_f64_s8",
+    "vreinterpret_f64_s8",
+    "vreinterpretq_f64_s8",
+    "vreinterpretq_f64_s8",
+    "vreinterpret_f64_s16",
+    "vreinterpret_f64_s16",
+    "vreinterpretq_f64_s16",
+    "vreinterpretq_f64_s16",
+    "vreinterpret_f64_s32",
+    "vreinterpret_f64_s32",
+    "vreinterpretq_f64_s32",
+    "vreinterpretq_f64_s32",
+    "vreinterpret_f64_s64",
+    "vreinterpret_p64_s64",
+    "vreinterpretq_f64_s64",
+    "vreinterpretq_f64_s64",
+    "vreinterpretq_p64_s64",
+    "vreinterpretq_p64_s64",
+    "vreinterpret_f64_u8",
+    "vreinterpret_f64_u8",
+    "vreinterpretq_f64_u8",
+    "vreinterpretq_f64_u8",
+    "vreinterpret_f64_u16",
+    "vreinterpret_f64_u16",
+    "vreinterpretq_f64_u16",
+    "vreinterpretq_f64_u16",
+    "vreinterpret_f64_u32",
+    "vreinterpret_f64_u32",
+    "vreinterpretq_f64_u32",
+    "vreinterpretq_f64_u32",
+    "vreinterpret_f64_u64",
+    "vreinterpret_p64_u64",
+    "vreinterpretq_f64_u64",
+    "vreinterpretq_f64_u64",
+    "vreinterpretq_p64_u64",
+    "vreinterpretq_p64_u64",
+    "vreinterpret_f64_p8",
+    "vreinterpret_f64_p8",
+    "vreinterpretq_f64_p8",
+    "vreinterpretq_f64_p8",
+    "vreinterpret_f64_p16",
+    "vreinterpret_f64_p16",
+    "vreinterpretq_f64_p16",
+    "vreinterpretq_f64_p16",
+    "vreinterpret_f32_p64",
+    "vreinterpret_f32_p64",
+    "vreinterpret_f64_p64",
+    "vreinterpret_s64_p64",
+    "vreinterpret_u64_p64",
+    "vreinterpretq_f32_p64",
+    "vreinterpretq_f32_p64",
+    "vreinterpretq_f64_p64",
+    "vreinterpretq_f64_p64",
+    "vreinterpretq_s64_p64",
+    "vreinterpretq_s64_p64",
+    "vreinterpretq_u64_p64",
+    "vreinterpretq_u64_p64",
+    "vrnd32x_f32",
+    "vrnd32xq_f32",
+    "vrnd32xq_f64",
+    "vrnd32x_f64",
+    "vrnd32z_f32",
+    "vrnd32zq_f32",
+    "vrnd32zq_f64",
+    "vrnd32z_f64",
+    "vrnd64x_f32",
+    "vrnd64xq_f32",
+    "vrnd64xq_f64",
+    "vrnd64x_f64",
+    "vrnd64z_f32",
+    "vrnd64zq_f32",
+    "vrnd64zq_f64",
+    "vrnd64z_f64",
+    "vrnd_f16",
+    "vrndq_f16",
+    "vrnd_f32",
+    "vrndq_f32",
+    "vrnd_f64",
+    "vrndq_f64",
+    "vrnda_f16",
+    "vrndaq_f16",
+    "vrnda_f32",
+    "vrndaq_f32",
+    "vrnda_f64",
+    "vrndaq_f64",
+    "vrndah_f16",
+    "vrndh_f16",
+    "vrndi_f16",
+    "vrndiq_f16",
+    "vrndi_f32",
+    "vrndiq_f32",
+    "vrndi_f64",
+    "vrndiq_f64",
+    "vrndih_f16",
+    "vrndm_f16",
+    "vrndmq_f16",
+    "vrndm_f32",
+    "vrndmq_f32",
+    "vrndm_f64",
+    "vrndmq_f64",
+    "vrndmh_f16",
+    "vrndn_f64",
+    "vrndnq_f64",
+    "vrndnh_f16",
+    "vrndns_f32",
+    "vrndp_f16",
+    "vrndpq_f16",
+    "vrndp_f32",
+    "vrndpq_f32",
+    "vrndp_f64",
+    "vrndpq_f64",
+    "vrndph_f16",
+    "vrndx_f16",
+    "vrndxq_f16",
+    "vrndx_f32",
+    "vrndxq_f32",
+    "vrndx_f64",
+    "vrndxq_f64",
+    "vrndxh_f16",
+    "vrshld_s64",
+    "vrshld_u64",
+    "vrshrd_n_s64",
+    "vrshrd_n_u64",
+    "vrshrn_high_n_s16",
+    "vrshrn_high_n_s32",
+    "vrshrn_high_n_s64",
+    "vrshrn_high_n_u16",
+    "vrshrn_high_n_u32",
+    "vrshrn_high_n_u64",
+    "vrsqrte_f64",
+    "vrsqrteq_f64",
+    "vrsqrted_f64",
+    "vrsqrtes_f32",
+    "vrsqrteh_f16",
+    "vrsqrts_f64",
+    "vrsqrtsq_f64",
+    "vrsqrtsd_f64",
+    "vrsqrtss_f32",
+    "vrsqrtsh_f16",
+    "vrsrad_n_s64",
+    "vrsrad_n_u64",
+    "vrsubhn_high_s16",
+    "vrsubhn_high_s32",
+    "vrsubhn_high_s64",
+    "vrsubhn_high_u16",
+    "vrsubhn_high_u32",
+    "vrsubhn_high_u64",
+    "vrsubhn_high_s16",
+    "vrsubhn_high_s32",
+    "vrsubhn_high_s64",
+    "vrsubhn_high_u16",
+    "vrsubhn_high_u32",
+    "vrsubhn_high_u64",
+    "vscale_f16",
+    "vscaleq_f16",
+    "vscale_f32",
+    "vscaleq_f32",
+    "vscaleq_f64",
+    "vset_lane_f64",
+    "vsetq_lane_f64",
+    "vsha512h2q_u64",
+    "vsha512hq_u64",
+    "vsha512su0q_u64",
+    "vsha512su1q_u64",
+    "vshld_s64",
+    "vshld_u64",
+    "vshll_high_n_s8",
+    "vshll_high_n_s16",
+    "vshll_high_n_s32",
+    "vshll_high_n_u8",
+    "vshll_high_n_u16",
+    "vshll_high_n_u32",
+    "vshrn_high_n_s16",
+    "vshrn_high_n_s32",
+    "vshrn_high_n_s64",
+    "vshrn_high_n_u16",
+    "vshrn_high_n_u32",
+    "vshrn_high_n_u64",
+    "vslid_n_s64",
+    "vslid_n_u64",
+    "vsm3partw1q_u32",
+    "vsm3partw2q_u32",
+    "vsm3ss1q_u32",
+    "vsm3tt1aq_u32",
+    "vsm3tt1bq_u32",
+    "vsm3tt2aq_u32",
+    "vsm3tt2bq_u32",
+    "vsm4ekeyq_u32",
+    "vsm4eq_u32",
+    "vsqadd_u8",
+    "vsqaddq_u8",
+    "vsqadd_u16",
+    "vsqaddq_u16",
+    "vsqadd_u32",
+    "vsqaddq_u32",
+    "vsqadd_u64",
+    "vsqaddq_u64",
+    "vsqaddb_u8",
+    "vsqaddh_u16",
+    "vsqaddd_u64",
+    "vsqadds_u32",
+    "vsqrt_f16",
+    "vsqrtq_f16",
+    "vsqrt_f32",
+    "vsqrtq_f32",
+    "vsqrt_f64",
+    "vsqrtq_f64",
+    "vsqrth_f16",
+    "vsrid_n_s64",
+    "vsrid_n_u64",
+    "vst1_f16",
+    "vst1q_f16",
+    "vst1_f64_x2",
+    "vst1q_f64_x2",
+    "vst1_f64_x3",
+    "vst1q_f64_x3",
+    "vst1_f64_x4",
+    "vst1q_f64_x4",
+    "vst1_lane_f64",
+    "vst1q_lane_f64",
+    "vst2_f64",
+    "vst2_lane_f64",
+    "vst2_lane_s64",
+    "vst2_lane_p64",
+    "vst2_lane_u64",
+    "vst2q_f64",
+    "vst2q_s64",
+    "vst2q_lane_f64",
+    "vst2q_lane_s8",
+    "vst2q_lane_s64",
+    "vst2q_lane_p64",
+    "vst2q_lane_u8",
+    "vst2q_lane_u64",
+    "vst2q_lane_p8",
+    "vst2q_p64",
+    "vst2q_u64",
+    "vst3_f64",
+    "vst3_lane_f64",
+    "vst3_lane_s64",
+    "vst3_lane_p64",
+    "vst3_lane_u64",
+    "vst3q_f64",
+    "vst3q_s64",
+    "vst3q_lane_f64",
+    "vst3q_lane_s8",
+    "vst3q_lane_s64",
+    "vst3q_lane_p64",
+    "vst3q_lane_u8",
+    "vst3q_lane_u64",
+    "vst3q_lane_p8",
+    "vst3q_p64",
+    "vst3q_u64",
+    "vst4_f64",
+    "vst4_lane_f64",
+    "vst4_lane_s64",
+    "vst4_lane_p64",
+    "vst4_lane_u64",
+    "vst4q_f64",
+    "vst4q_s64",
+    "vst4q_lane_f64",
+    "vst4q_lane_s8",
+    "vst4q_lane_s64",
+    "vst4q_lane_p64",
+    "vst4q_lane_u8",
+    "vst4q_lane_u64",
+    "vst4q_lane_p8",
+    "vst4q_p64",
+    "vst4q_u64",
+    "vstl1_lane_f64",
+    "vstl1q_lane_f64",
+    "vstl1_lane_u64",
+    "vstl1q_lane_u64",
+    "vstl1_lane_p64",
+    "vstl1q_lane_p64",
+    "vstl1_lane_s64",
+    "vstl1q_lane_s64",
+    "vsub_f64",
+    "vsubq_f64",
+    "vsubd_s64",
+    "vsubd_u64",
+    "vsubh_f16",
+    "vsubl_high_s8",
+    "vsubl_high_s16",
+    "vsubl_high_s32",
+    "vsubl_high_u8",
+    "vsubl_high_u16",
+    "vsubl_high_u32",
+    "vsubw_high_s8",
+    "vsubw_high_s16",
+    "vsubw_high_s32",
+    "vsubw_high_u8",
+    "vsubw_high_u16",
+    "vsubw_high_u32",
+    "vtrn1_f16",
+    "vtrn1q_f16",
+    "vtrn1_f32",
+    "vtrn1q_f64",
+    "vtrn1_s32",
+    "vtrn1q_s64",
+    "vtrn1_u32",
+    "vtrn1q_u64",
+    "vtrn1q_p64",
+    "vtrn1q_f32",
+    "vtrn1_s8",
+    "vtrn1q_s8",
+    "vtrn1_s16",
+    "vtrn1q_s16",
+    "vtrn1q_s32",
+    "vtrn1_u8",
+    "vtrn1q_u8",
+    "vtrn1_u16",
+    "vtrn1q_u16",
+    "vtrn1q_u32",
+    "vtrn1_p8",
+    "vtrn1q_p8",
+    "vtrn1_p16",
+    "vtrn1q_p16",
+    "vtrn2_f16",
+    "vtrn2q_f16",
+    "vtrn2_f32",
+    "vtrn2q_f64",
+    "vtrn2_s32",
+    "vtrn2q_s64",
+    "vtrn2_u32",
+    "vtrn2q_u64",
+    "vtrn2q_p64",
+    "vtrn2q_f32",
+    "vtrn2_s8",
+    "vtrn2q_s8",
+    "vtrn2_s16",
+    "vtrn2q_s16",
+    "vtrn2q_s32",
+    "vtrn2_u8",
+    "vtrn2q_u8",
+    "vtrn2_u16",
+    "vtrn2q_u16",
+    "vtrn2q_u32",
+    "vtrn2_p8",
+    "vtrn2q_p8",
+    "vtrn2_p16",
+    "vtrn2q_p16",
+    "vtst_s64",
+    "vtstq_s64",
+    "vtst_p64",
+    "vtstq_p64",
+    "vtst_u64",
+    "vtstq_u64",
+    "vtstd_s64",
+    "vtstd_u64",
+    "vuqadd_s8",
+    "vuqaddq_s8",
+    "vuqadd_s16",
+    "vuqaddq_s16",
+    "vuqadd_s32",
+    "vuqaddq_s32",
+    "vuqadd_s64",
+    "vuqaddq_s64",
+    "vuqaddb_s8",
+    "vuqaddh_s16",
+    "vuqaddd_s64",
+    "vuqadds_s32",
+    "vuzp1_f16",
+    "vuzp1q_f16",
+    "vuzp1_f32",
+    "vuzp1q_f64",
+    "vuzp1_s32",
+    "vuzp1q_s64",
+    "vuzp1_u32",
+    "vuzp1q_u64",
+    "vuzp1q_p64",
+    "vuzp1q_f32",
+    "vuzp1_s8",
+    "vuzp1q_s8",
+    "vuzp1_s16",
+    "vuzp1q_s16",
+    "vuzp1q_s32",
+    "vuzp1_u8",
+    "vuzp1q_u8",
+    "vuzp1_u16",
+    "vuzp1q_u16",
+    "vuzp1q_u32",
+    "vuzp1_p8",
+    "vuzp1q_p8",
+    "vuzp1_p16",
+    "vuzp1q_p16",
+    "vuzp2_f16",
+    "vuzp2q_f16",
+    "vuzp2_f32",
+    "vuzp2q_f64",
+    "vuzp2_s32",
+    "vuzp2q_s64",
+    "vuzp2_u32",
+    "vuzp2q_u64",
+    "vuzp2q_p64",
+    "vuzp2q_f32",
+    "vuzp2_s8",
+    "vuzp2q_s8",
+    "vuzp2_s16",
+    "vuzp2q_s16",
+    "vuzp2q_s32",
+    "vuzp2_u8",
+    "vuzp2q_u8",
+    "vuzp2_u16",
+    "vuzp2q_u16",
+    "vuzp2q_u32",
+    "vuzp2_p8",
+    "vuzp2q_p8",
+    "vuzp2_p16",
+    "vuzp2q_p16",
+    "vxarq_u64",
+    "vzip1_f16",
+    "vzip1q_f16",
+    "vzip1_f32",
+    "vzip1q_f32",
+    "vzip1q_f64",
+    "vzip1_s8",
+    "vzip1q_s8",
+    "vzip1_s16",
+    "vzip1q_s16",
+    "vzip1_s32",
+    "vzip1q_s32",
+    "vzip1q_s64",
+    "vzip1_u8",
+    "vzip1q_u8",
+    "vzip1_u16",
+    "vzip1q_u16",
+    "vzip1_u32",
+    "vzip1q_u32",
+    "vzip1q_u64",
+    "vzip1_p8",
+    "vzip1q_p8",
+    "vzip1_p16",
+    "vzip1q_p16",
+    "vzip1q_p64",
+    "vzip2_f16",
+    "vzip2q_f16",
+    "vzip2_f32",
+    "vzip2q_f32",
+    "vzip2q_f64",
+    "vzip2_s8",
+    "vzip2q_s8",
+    "vzip2_s16",
+    "vzip2q_s16",
+    "vzip2_s32",
+    "vzip2q_s32",
+    "vzip2q_s64",
+    "vzip2_u8",
+    "vzip2q_u8",
+    "vzip2_u16",
+    "vzip2q_u16",
+    "vzip2_u32",
+    "vzip2q_u32",
+    "vzip2q_u64",
+    "vzip2_p8",
+    "vzip2q_p8",
+    "vzip2_p16",
+    "vzip2q_p16",
+    "vzip2q_p64",
+    "__crc32b",
+    "__crc32cb",
+    "__crc32cd",
+    "__crc32ch",
+    "__crc32cw",
+    "__crc32d",
+    "__crc32h",
+    "__crc32w",
+    "vabal_s8",
+    "vabal_s16",
+    "vabal_s32",
+    "vabal_u8",
+    "vabal_u16",
+    "vabal_u32",
+    "vabd_f16",
+    "vabdq_f16",
+    "vabd_f32",
+    "vabdq_f32",
+    "vabd_s8",
+    "vabdq_s8",
+    "vabd_s16",
+    "vabdq_s16",
+    "vabd_s32",
+    "vabdq_s32",
+    "vabd_u8",
+    "vabdq_u8",
+    "vabd_u16",
+    "vabdq_u16",
+    "vabd_u32",
+    "vabdq_u32",
+    "vabdl_s8",
+    "vabdl_s16",
+    "vabdl_s32",
+    "vabdl_u8",
+    "vabdl_u16",
+    "vabdl_u32",
+    "vabs_f16",
+    "vabsq_f16",
+    "vabs_f32",
+    "vabsq_f32",
+    "vabs_s8",
+    "vabsq_s8",
+    "vabs_s16",
+    "vabsq_s16",
+    "vabs_s32",
+    "vabsq_s32",
+    "vabsh_f16",
+    "vadd_f16",
+    "vaddq_f16",
+    "vadd_p8",
+    "vaddq_p8",
+    "vadd_p16",
+    "vaddq_p16",
+    "vadd_p64",
+    "vaddq_p64",
+    "vaddh_f16",
+    "vaddhn_high_s16",
+    "vaddhn_high_s32",
+    "vaddhn_high_s64",
+    "vaddhn_high_u16",
+    "vaddhn_high_u32",
+    "vaddhn_high_u64",
+    "vaddhn_s16",
+    "vaddhn_s32",
+    "vaddhn_s64",
+    "vaddhn_u16",
+    "vaddhn_u32",
+    "vaddhn_u64",
+    "vaddq_p128",
+    "vaesdq_u8",
+    "vaeseq_u8",
+    "vaesimcq_u8",
+    "vaesmcq_u8",
+    "vbsl_f16",
+    "vbslq_f16",
+    "vcage_f16",
+    "vcageq_f16",
+    "vcage_f32",
+    "vcageq_f32",
+    "vcagt_f16",
+    "vcagtq_f16",
+    "vcagt_f32",
+    "vcagtq_f32",
+    "vcale_f16",
+    "vcaleq_f16",
+    "vcale_f32",
+    "vcaleq_f32",
+    "vcalt_f16",
+    "vcaltq_f16",
+    "vcalt_f32",
+    "vcaltq_f32",
+    "vceq_f16",
+    "vceqq_f16",
+    "vceq_p8",
+    "vceqq_p8",
+    "vcge_f16",
+    "vcgeq_f16",
+    "vcgez_f16",
+    "vcgezq_f16",
+    "vcgt_f16",
+    "vcgtq_f16",
+    "vcgtz_f16",
+    "vcgtzq_f16",
+    "vcle_f16",
+    "vcleq_f16",
+    "vclez_f16",
+    "vclezq_f16",
+    "vcls_s8",
+    "vclsq_s8",
+    "vcls_s16",
+    "vclsq_s16",
+    "vcls_s32",
+    "vclsq_s32",
+    "vcls_u8",
+    "vclsq_u8",
+    "vcls_u16",
+    "vclsq_u16",
+    "vcls_u32",
+    "vclsq_u32",
+    "vclt_f16",
+    "vcltq_f16",
+    "vcltz_f16",
+    "vcltzq_f16",
+    "vclz_s8",
+    "vclzq_s8",
+    "vclz_s16",
+    "vclzq_s16",
+    "vclz_s32",
+    "vclzq_s32",
+    "vclz_u16",
+    "vclz_u16",
+    "vclzq_u16",
+    "vclzq_u16",
+    "vclz_u32",
+    "vclz_u32",
+    "vclzq_u32",
+    "vclzq_u32",
+    "vclz_u8",
+    "vclz_u8",
+    "vclzq_u8",
+    "vclzq_u8",
+    "vcnt_s8",
+    "vcntq_s8",
+    "vcnt_u8",
+    "vcnt_u8",
+    "vcntq_u8",
+    "vcntq_u8",
+    "vcnt_p8",
+    "vcnt_p8",
+    "vcntq_p8",
+    "vcntq_p8",
+    "vcombine_f16",
+    "vcreate_f16",
+    "vcreate_f16",
+    "vcreate_f32",
+    "vcreate_f32",
+    "vcreate_s8",
+    "vcreate_s8",
+    "vcreate_s16",
+    "vcreate_s16",
+    "vcreate_s32",
+    "vcreate_s32",
+    "vcreate_s64",
+    "vcreate_u8",
+    "vcreate_u8",
+    "vcreate_u16",
+    "vcreate_u16",
+    "vcreate_u32",
+    "vcreate_u32",
+    "vcreate_u64",
+    "vcreate_p8",
+    "vcreate_p8",
+    "vcreate_p16",
+    "vcreate_p16",
+    "vcreate_p64",
+    "vcvt_f16_f32",
+    "vcvt_f16_s16",
+    "vcvtq_f16_s16",
+    "vcvt_f16_u16",
+    "vcvtq_f16_u16",
+    "vcvt_f32_f16",
+    "vcvt_f32_s32",
+    "vcvtq_f32_s32",
+    "vcvt_f32_u32",
+    "vcvtq_f32_u32",
+    "vcvt_n_f16_s16",
+    "vcvtq_n_f16_s16",
+    "vcvt_n_f16_u16",
+    "vcvtq_n_f16_u16",
+    "vcvt_n_f32_s32",
+    "vcvtq_n_f32_s32",
+    "vcvt_n_f32_s32",
+    "vcvtq_n_f32_s32",
+    "vcvt_n_f32_u32",
+    "vcvtq_n_f32_u32",
+    "vcvt_n_f32_u32",
+    "vcvtq_n_f32_u32",
+    "vcvt_n_s16_f16",
+    "vcvtq_n_s16_f16",
+    "vcvt_n_s32_f32",
+    "vcvtq_n_s32_f32",
+    "vcvt_n_s32_f32",
+    "vcvtq_n_s32_f32",
+    "vcvt_n_u16_f16",
+    "vcvtq_n_u16_f16",
+    "vcvt_n_u32_f32",
+    "vcvtq_n_u32_f32",
+    "vcvt_n_u32_f32",
+    "vcvtq_n_u32_f32",
+    "vcvt_s16_f16",
+    "vcvtq_s16_f16",
+    "vcvt_s32_f32",
+    "vcvtq_s32_f32",
+    "vcvt_u16_f16",
+    "vcvtq_u16_f16",
+    "vcvt_u32_f32",
+    "vcvtq_u32_f32",
+    "vdot_lane_s32",
+    "vdot_lane_s32",
+    "vdotq_lane_s32",
+    "vdotq_lane_s32",
+    "vdot_lane_u32",
+    "vdot_lane_u32",
+    "vdotq_lane_u32",
+    "vdotq_lane_u32",
+    "vdot_laneq_s32",
+    "vdot_laneq_s32",
+    "vdotq_laneq_s32",
+    "vdotq_laneq_s32",
+    "vdot_laneq_u32",
+    "vdot_laneq_u32",
+    "vdotq_laneq_u32",
+    "vdotq_laneq_u32",
+    "vdot_s32",
+    "vdotq_s32",
+    "vdot_u32",
+    "vdotq_u32",
+    "vdup_lane_f16",
+    "vdupq_lane_f16",
+    "vdup_lane_f32",
+    "vdup_lane_s32",
+    "vdup_lane_u32",
+    "vdupq_lane_f32",
+    "vdupq_lane_s32",
+    "vdupq_lane_u32",
+    "vdup_lane_p16",
+    "vdup_lane_s16",
+    "vdup_lane_u16",
+    "vdupq_lane_p16",
+    "vdupq_lane_s16",
+    "vdupq_lane_u16",
+    "vdup_lane_p8",
+    "vdup_lane_s8",
+    "vdup_lane_u8",
+    "vdupq_lane_p8",
+    "vdupq_lane_s8",
+    "vdupq_lane_u8",
+    "vdup_lane_s64",
+    "vdup_lane_u64",
+    "vdup_laneq_f16",
+    "vdupq_laneq_f16",
+    "vdup_laneq_f32",
+    "vdup_laneq_s32",
+    "vdup_laneq_u32",
+    "vdupq_laneq_f32",
+    "vdupq_laneq_s32",
+    "vdupq_laneq_u32",
+    "vdup_laneq_p16",
+    "vdup_laneq_s16",
+    "vdup_laneq_u16",
+    "vdupq_laneq_p16",
+    "vdupq_laneq_s16",
+    "vdupq_laneq_u16",
+    "vdup_laneq_p8",
+    "vdup_laneq_s8",
+    "vdup_laneq_u8",
+    "vdupq_laneq_p8",
+    "vdupq_laneq_s8",
+    "vdupq_laneq_u8",
+    "vdup_laneq_s64",
+    "vdup_laneq_u64",
+    "vdup_n_f16",
+    "vdupq_n_f16",
+    "vdupq_lane_s64",
+    "vdupq_lane_u64",
+    "vdupq_laneq_s64",
+    "vdupq_laneq_u64",
+    "vext_f16",
+    "vext_f32",
+    "vext_s32",
+    "vext_u32",
+    "vext_s8",
+    "vextq_s16",
+    "vext_u8",
+    "vextq_u16",
+    "vext_p8",
+    "vextq_p16",
+    "vextq_f16",
+    "vextq_f32",
+    "vext_s16",
+    "vextq_s32",
+    "vext_u16",
+    "vextq_u32",
+    "vext_p16",
+    "vextq_s64",
+    "vextq_u64",
+    "vextq_s8",
+    "vextq_u8",
+    "vextq_p8",
+    "vfma_f16",
+    "vfmaq_f16",
+    "vfma_f32",
+    "vfmaq_f32",
+    "vfma_n_f32",
+    "vfmaq_n_f32",
+    "vfms_f16",
+    "vfmsq_f16",
+    "vfms_f32",
+    "vfmsq_f32",
+    "vfms_n_f32",
+    "vfmsq_n_f32",
+    "vget_high_f16",
+    "vget_low_f16",
+    "vget_lane_f16",
+    "vgetq_lane_f16",
+    "vld1_dup_f16",
+    "vld1q_dup_f16",
+    "vld1_f16",
+    "vld1_f16",
+    "vld1q_f16",
+    "vld1q_f16",
+    "vld1_f16_x2",
+    "vld1_f16_x3",
+    "vld1_f16_x4",
+    "vld1q_f16_x2",
+    "vld1q_f16_x3",
+    "vld1q_f16_x4",
+    "vld1_f32_x2",
+    "vld1_f32_x3",
+    "vld1_f32_x4",
+    "vld1q_f32_x2",
+    "vld1q_f32_x3",
+    "vld1q_f32_x4",
+    "vld1_lane_f16",
+    "vld1q_lane_f16",
+    "vld1_p64_x2",
+    "vld1_p64_x3",
+    "vld1_p64_x4",
+    "vld1q_p64_x2",
+    "vld1q_p64_x3",
+    "vld1q_p64_x4",
+    "vld1_s8_x2",
+    "vld1_s8_x3",
+    "vld1_s8_x4",
+    "vld1q_s8_x2",
+    "vld1q_s8_x3",
+    "vld1q_s8_x4",
+    "vld1_s16_x2",
+    "vld1_s16_x3",
+    "vld1_s16_x4",
+    "vld1q_s16_x2",
+    "vld1q_s16_x3",
+    "vld1q_s16_x4",
+    "vld1_s32_x2",
+    "vld1_s32_x3",
+    "vld1_s32_x4",
+    "vld1q_s32_x2",
+    "vld1q_s32_x3",
+    "vld1q_s32_x4",
+    "vld1_s64_x2",
+    "vld1_s64_x3",
+    "vld1_s64_x4",
+    "vld1q_s64_x2",
+    "vld1q_s64_x3",
+    "vld1q_s64_x4",
+    "vld1_u8_x2",
+    "vld1_u8_x3",
+    "vld1_u8_x4",
+    "vld1q_u8_x2",
+    "vld1q_u8_x3",
+    "vld1q_u8_x4",
+    "vld1_u16_x2",
+    "vld1_u16_x3",
+    "vld1_u16_x4",
+    "vld1q_u16_x2",
+    "vld1q_u16_x3",
+    "vld1q_u16_x4",
+    "vld1_u32_x2",
+    "vld1_u32_x3",
+    "vld1_u32_x4",
+    "vld1q_u32_x2",
+    "vld1q_u32_x3",
+    "vld1q_u32_x4",
+    "vld1_u64_x2",
+    "vld1_u64_x3",
+    "vld1_u64_x4",
+    "vld1q_u64_x2",
+    "vld1q_u64_x3",
+    "vld1q_u64_x4",
+    "vld1_p8_x2",
+    "vld1_p8_x3",
+    "vld1_p8_x4",
+    "vld1q_p8_x2",
+    "vld1q_p8_x3",
+    "vld1q_p8_x4",
+    "vld1_p16_x2",
+    "vld1_p16_x3",
+    "vld1_p16_x4",
+    "vld1q_p16_x2",
+    "vld1q_p16_x3",
+    "vld1q_p16_x4",
+    "vld2_dup_f16",
+    "vld2q_dup_f16",
+    "vld2_dup_f16",
+    "vld2q_dup_f16",
+    "vld2_dup_f32",
+    "vld2q_dup_f32",
+    "vld2_dup_s8",
+    "vld2q_dup_s8",
+    "vld2_dup_s16",
+    "vld2q_dup_s16",
+    "vld2_dup_s32",
+    "vld2q_dup_s32",
+    "vld2_dup_f32",
+    "vld2q_dup_f32",
+    "vld2_dup_s8",
+    "vld2q_dup_s8",
+    "vld2_dup_s16",
+    "vld2q_dup_s16",
+    "vld2_dup_s32",
+    "vld2q_dup_s32",
+    "vld2_dup_p64",
+    "vld2_dup_s64",
+    "vld2_dup_s64",
+    "vld2_dup_u64",
+    "vld2_dup_u8",
+    "vld2_dup_u8",
+    "vld2q_dup_u8",
+    "vld2q_dup_u8",
+    "vld2_dup_u16",
+    "vld2_dup_u16",
+    "vld2q_dup_u16",
+    "vld2q_dup_u16",
+    "vld2_dup_u32",
+    "vld2_dup_u32",
+    "vld2q_dup_u32",
+    "vld2q_dup_u32",
+    "vld2_dup_p8",
+    "vld2_dup_p8",
+    "vld2q_dup_p8",
+    "vld2q_dup_p8",
+    "vld2_dup_p16",
+    "vld2_dup_p16",
+    "vld2q_dup_p16",
+    "vld2q_dup_p16",
+    "vld2_f16",
+    "vld2q_f16",
+    "vld2_f16",
+    "vld2q_f16",
+    "vld2_f32",
+    "vld2q_f32",
+    "vld2_s8",
+    "vld2q_s8",
+    "vld2_s16",
+    "vld2q_s16",
+    "vld2_s32",
+    "vld2q_s32",
+    "vld2_f32",
+    "vld2q_f32",
+    "vld2_s8",
+    "vld2q_s8",
+    "vld2_s16",
+    "vld2q_s16",
+    "vld2_s32",
+    "vld2q_s32",
+    "vld2_lane_f16",
+    "vld2q_lane_f16",
+    "vld2_lane_f16",
+    "vld2q_lane_f16",
+    "vld2_lane_f32",
+    "vld2q_lane_f32",
+    "vld2_lane_s8",
+    "vld2_lane_s16",
+    "vld2q_lane_s16",
+    "vld2_lane_s32",
+    "vld2q_lane_s32",
+    "vld2_lane_f32",
+    "vld2q_lane_f32",
+    "vld2q_lane_s16",
+    "vld2q_lane_s32",
+    "vld2_lane_s8",
+    "vld2_lane_s16",
+    "vld2_lane_s32",
+    "vld2_lane_u8",
+    "vld2_lane_u16",
+    "vld2q_lane_u16",
+    "vld2_lane_u32",
+    "vld2q_lane_u32",
+    "vld2_lane_p8",
+    "vld2_lane_p16",
+    "vld2q_lane_p16",
+    "vld2_p64",
+    "vld2_s64",
+    "vld2_s64",
+    "vld2_u64",
+    "vld2_u8",
+    "vld2q_u8",
+    "vld2_u16",
+    "vld2q_u16",
+    "vld2_u32",
+    "vld2q_u32",
+    "vld2_p8",
+    "vld2q_p8",
+    "vld2_p16",
+    "vld2q_p16",
+    "vld3_dup_f16",
+    "vld3q_dup_f16",
+    "vld3_dup_f16",
+    "vld3q_dup_f16",
+    "vld3_dup_f32",
+    "vld3q_dup_f32",
+    "vld3_dup_s8",
+    "vld3q_dup_s8",
+    "vld3_dup_s16",
+    "vld3q_dup_s16",
+    "vld3_dup_s32",
+    "vld3q_dup_s32",
+    "vld3_dup_s64",
+    "vld3_dup_f32",
+    "vld3q_dup_f32",
+    "vld3_dup_s8",
+    "vld3q_dup_s8",
+    "vld3_dup_s16",
+    "vld3q_dup_s16",
+    "vld3_dup_s32",
+    "vld3q_dup_s32",
+    "vld3_dup_p64",
+    "vld3_dup_s64",
+    "vld3_dup_u64",
+    "vld3_dup_u8",
+    "vld3_dup_u8",
+    "vld3q_dup_u8",
+    "vld3q_dup_u8",
+    "vld3_dup_u16",
+    "vld3_dup_u16",
+    "vld3q_dup_u16",
+    "vld3q_dup_u16",
+    "vld3_dup_u32",
+    "vld3_dup_u32",
+    "vld3q_dup_u32",
+    "vld3q_dup_u32",
+    "vld3_dup_p8",
+    "vld3_dup_p8",
+    "vld3q_dup_p8",
+    "vld3q_dup_p8",
+    "vld3_dup_p16",
+    "vld3_dup_p16",
+    "vld3q_dup_p16",
+    "vld3q_dup_p16",
+    "vld3_f16",
+    "vld3q_f16",
+    "vld3_f16",
+    "vld3q_f16",
+    "vld3_f32",
+    "vld3q_f32",
+    "vld3_s8",
+    "vld3q_s8",
+    "vld3_s16",
+    "vld3q_s16",
+    "vld3_s32",
+    "vld3q_s32",
+    "vld3_f32",
+    "vld3q_f32",
+    "vld3_s8",
+    "vld3q_s8",
+    "vld3_s16",
+    "vld3q_s16",
+    "vld3_s32",
+    "vld3q_s32",
+    "vld3_lane_f16",
+    "vld3q_lane_f16",
+    "vld3_lane_f16",
+    "vld3q_lane_f16",
+    "vld3_lane_f32",
+    "vld3q_lane_f32",
+    "vld3_lane_f32",
+    "vld3_lane_s8",
+    "vld3_lane_s16",
+    "vld3q_lane_s16",
+    "vld3_lane_s32",
+    "vld3q_lane_s32",
+    "vld3_lane_s8",
+    "vld3_lane_s16",
+    "vld3q_lane_s16",
+    "vld3_lane_s32",
+    "vld3q_lane_s32",
+    "vld3_lane_u8",
+    "vld3_lane_u16",
+    "vld3q_lane_u16",
+    "vld3_lane_u32",
+    "vld3q_lane_u32",
+    "vld3_lane_p8",
+    "vld3_lane_p16",
+    "vld3q_lane_p16",
+    "vld3_p64",
+    "vld3_s64",
+    "vld3_s64",
+    "vld3_u64",
+    "vld3_u8",
+    "vld3q_u8",
+    "vld3_u16",
+    "vld3q_u16",
+    "vld3_u32",
+    "vld3q_u32",
+    "vld3_p8",
+    "vld3q_p8",
+    "vld3_p16",
+    "vld3q_p16",
+    "vld3q_lane_f32",
+    "vld4_dup_f16",
+    "vld4q_dup_f16",
+    "vld4_dup_f16",
+    "vld4q_dup_f16",
+    "vld4_dup_f32",
+    "vld4q_dup_f32",
+    "vld4_dup_s8",
+    "vld4q_dup_s8",
+    "vld4_dup_s16",
+    "vld4q_dup_s16",
+    "vld4_dup_s32",
+    "vld4q_dup_s32",
+    "vld4_dup_f32",
+    "vld4q_dup_f32",
+    "vld4_dup_s8",
+    "vld4q_dup_s8",
+    "vld4_dup_s16",
+    "vld4q_dup_s16",
+    "vld4_dup_s32",
+    "vld4q_dup_s32",
+    "vld4_dup_s64",
+    "vld4_dup_p64",
+    "vld4_dup_s64",
+    "vld4_dup_u64",
+    "vld4_dup_u8",
+    "vld4_dup_u8",
+    "vld4q_dup_u8",
+    "vld4q_dup_u8",
+    "vld4_dup_u16",
+    "vld4_dup_u16",
+    "vld4q_dup_u16",
+    "vld4q_dup_u16",
+    "vld4_dup_u32",
+    "vld4_dup_u32",
+    "vld4q_dup_u32",
+    "vld4q_dup_u32",
+    "vld4_dup_p8",
+    "vld4_dup_p8",
+    "vld4q_dup_p8",
+    "vld4q_dup_p8",
+    "vld4_dup_p16",
+    "vld4_dup_p16",
+    "vld4q_dup_p16",
+    "vld4q_dup_p16",
+    "vld4_f16",
+    "vld4q_f16",
+    "vld4_f16",
+    "vld4q_f16",
+    "vld4_f32",
+    "vld4q_f32",
+    "vld4_s8",
+    "vld4q_s8",
+    "vld4_s16",
+    "vld4q_s16",
+    "vld4_s32",
+    "vld4q_s32",
+    "vld4_f32",
+    "vld4q_f32",
+    "vld4_s8",
+    "vld4q_s8",
+    "vld4_s16",
+    "vld4q_s16",
+    "vld4_s32",
+    "vld4q_s32",
+    "vld4_lane_f16",
+    "vld4q_lane_f16",
+    "vld4_lane_f16",
+    "vld4q_lane_f16",
+    "vld4_lane_f32",
+    "vld4q_lane_f32",
+    "vld4_lane_s8",
+    "vld4_lane_s16",
+    "vld4q_lane_s16",
+    "vld4_lane_s32",
+    "vld4q_lane_s32",
+    "vld4_lane_f32",
+    "vld4q_lane_f32",
+    "vld4_lane_s8",
+    "vld4_lane_s16",
+    "vld4q_lane_s16",
+    "vld4_lane_s32",
+    "vld4q_lane_s32",
+    "vld4_lane_u8",
+    "vld4_lane_u16",
+    "vld4q_lane_u16",
+    "vld4_lane_u32",
+    "vld4q_lane_u32",
+    "vld4_lane_p8",
+    "vld4_lane_p16",
+    "vld4q_lane_p16",
+    "vld4_p64",
+    "vld4_s64",
+    "vld4_s64",
+    "vld4_u64",
+    "vld4_u8",
+    "vld4q_u8",
+    "vld4_u16",
+    "vld4q_u16",
+    "vld4_u32",
+    "vld4q_u32",
+    "vld4_p8",
+    "vld4q_p8",
+    "vld4_p16",
+    "vld4q_p16",
+    "vmax_f16",
+    "vmaxq_f16",
+    "vmax_f32",
+    "vmaxq_f32",
+    "vmax_s8",
+    "vmaxq_s8",
+    "vmax_s16",
+    "vmaxq_s16",
+    "vmax_s32",
+    "vmaxq_s32",
+    "vmax_u8",
+    "vmaxq_u8",
+    "vmax_u16",
+    "vmaxq_u16",
+    "vmax_u32",
+    "vmaxq_u32",
+    "vmaxnm_f16",
+    "vmaxnmq_f16",
+    "vmaxnm_f32",
+    "vmaxnmq_f32",
+    "vmin_f16",
+    "vminq_f16",
+    "vmin_f32",
+    "vminq_f32",
+    "vmin_s8",
+    "vminq_s8",
+    "vmin_s16",
+    "vminq_s16",
+    "vmin_s32",
+    "vminq_s32",
+    "vmin_u8",
+    "vminq_u8",
+    "vmin_u16",
+    "vminq_u16",
+    "vmin_u32",
+    "vminq_u32",
+    "vminnm_f16",
+    "vminnmq_f16",
+    "vminnm_f32",
+    "vminnmq_f32",
+    "vmla_f32",
+    "vmlaq_f32",
+    "vmla_lane_f32",
+    "vmla_laneq_f32",
+    "vmlaq_lane_f32",
+    "vmlaq_laneq_f32",
+    "vmla_lane_s16",
+    "vmla_lane_u16",
+    "vmla_laneq_s16",
+    "vmla_laneq_u16",
+    "vmlaq_lane_s16",
+    "vmlaq_lane_u16",
+    "vmlaq_laneq_s16",
+    "vmlaq_laneq_u16",
+    "vmla_lane_s32",
+    "vmla_lane_u32",
+    "vmla_laneq_s32",
+    "vmla_laneq_u32",
+    "vmlaq_lane_s32",
+    "vmlaq_lane_u32",
+    "vmlaq_laneq_s32",
+    "vmlaq_laneq_u32",
+    "vmla_n_f32",
+    "vmlaq_n_f32",
+    "vmla_n_s16",
+    "vmlaq_n_s16",
+    "vmla_n_u16",
+    "vmlaq_n_u16",
+    "vmla_n_s32",
+    "vmlaq_n_s32",
+    "vmla_n_u32",
+    "vmlaq_n_u32",
+    "vmla_s8",
+    "vmlaq_s8",
+    "vmla_s16",
+    "vmlaq_s16",
+    "vmla_s32",
+    "vmlaq_s32",
+    "vmla_u8",
+    "vmlaq_u8",
+    "vmla_u16",
+    "vmlaq_u16",
+    "vmla_u32",
+    "vmlaq_u32",
+    "vmlal_lane_s16",
+    "vmlal_laneq_s16",
+    "vmlal_lane_s32",
+    "vmlal_laneq_s32",
+    "vmlal_lane_u16",
+    "vmlal_laneq_u16",
+    "vmlal_lane_u32",
+    "vmlal_laneq_u32",
+    "vmlal_n_s16",
+    "vmlal_n_s32",
+    "vmlal_n_u16",
+    "vmlal_n_u32",
+    "vmlal_s8",
+    "vmlal_s16",
+    "vmlal_s32",
+    "vmlal_u8",
+    "vmlal_u16",
+    "vmlal_u32",
+    "vmls_f32",
+    "vmlsq_f32",
+    "vmls_lane_f32",
+    "vmls_laneq_f32",
+    "vmlsq_lane_f32",
+    "vmlsq_laneq_f32",
+    "vmls_lane_s16",
+    "vmls_lane_u16",
+    "vmls_laneq_s16",
+    "vmls_laneq_u16",
+    "vmlsq_lane_s16",
+    "vmlsq_lane_u16",
+    "vmlsq_laneq_s16",
+    "vmlsq_laneq_u16",
+    "vmls_lane_s32",
+    "vmls_lane_u32",
+    "vmls_laneq_s32",
+    "vmls_laneq_u32",
+    "vmlsq_lane_s32",
+    "vmlsq_lane_u32",
+    "vmlsq_laneq_s32",
+    "vmlsq_laneq_u32",
+    "vmls_n_f32",
+    "vmlsq_n_f32",
+    "vmls_n_s16",
+    "vmlsq_n_s16",
+    "vmls_n_u16",
+    "vmlsq_n_u16",
+    "vmls_n_s32",
+    "vmlsq_n_s32",
+    "vmls_n_u32",
+    "vmlsq_n_u32",
+    "vmls_s8",
+    "vmlsq_s8",
+    "vmls_s16",
+    "vmlsq_s16",
+    "vmls_s32",
+    "vmlsq_s32",
+    "vmls_u8",
+    "vmlsq_u8",
+    "vmls_u16",
+    "vmlsq_u16",
+    "vmls_u32",
+    "vmlsq_u32",
+    "vmlsl_lane_s16",
+    "vmlsl_laneq_s16",
+    "vmlsl_lane_s32",
+    "vmlsl_laneq_s32",
+    "vmlsl_lane_u16",
+    "vmlsl_laneq_u16",
+    "vmlsl_lane_u32",
+    "vmlsl_laneq_u32",
+    "vmlsl_n_s16",
+    "vmlsl_n_s32",
+    "vmlsl_n_u16",
+    "vmlsl_n_u32",
+    "vmlsl_s8",
+    "vmlsl_s16",
+    "vmlsl_s32",
+    "vmlsl_u8",
+    "vmlsl_u16",
+    "vmlsl_u32",
+    "vmmlaq_s32",
+    "vmmlaq_u32",
+    "vmov_n_f16",
+    "vmovq_n_f16",
+    "vmul_f16",
+    "vmulq_f16",
+    "vmul_lane_f16",
+    "vmulq_lane_f16",
+    "vmul_lane_f32",
+    "vmul_laneq_f32",
+    "vmulq_lane_f32",
+    "vmulq_laneq_f32",
+    "vmul_lane_s16",
+    "vmulq_lane_s16",
+    "vmul_lane_s32",
+    "vmulq_lane_s32",
+    "vmul_lane_u16",
+    "vmulq_lane_u16",
+    "vmul_lane_u32",
+    "vmulq_lane_u32",
+    "vmul_laneq_s16",
+    "vmulq_laneq_s16",
+    "vmul_laneq_s32",
+    "vmulq_laneq_s32",
+    "vmul_laneq_u16",
+    "vmulq_laneq_u16",
+    "vmul_laneq_u32",
+    "vmulq_laneq_u32",
+    "vmul_n_f16",
+    "vmulq_n_f16",
+    "vmul_n_f32",
+    "vmulq_n_f32",
+    "vmul_n_s16",
+    "vmulq_n_s16",
+    "vmul_n_s32",
+    "vmulq_n_s32",
+    "vmul_n_u16",
+    "vmulq_n_u16",
+    "vmul_n_u32",
+    "vmulq_n_u32",
+    "vmul_p8",
+    "vmulq_p8",
+    "vmull_lane_s16",
+    "vmull_laneq_s16",
+    "vmull_lane_s32",
+    "vmull_laneq_s32",
+    "vmull_lane_u16",
+    "vmull_laneq_u16",
+    "vmull_lane_u32",
+    "vmull_laneq_u32",
+    "vmull_n_s16",
+    "vmull_n_s32",
+    "vmull_n_u16",
+    "vmull_n_u32",
+    "vmull_p8",
+    "vmull_s16",
+    "vmull_s32",
+    "vmull_s8",
+    "vmull_u8",
+    "vmull_u16",
+    "vmull_u32",
+    "vneg_f16",
+    "vnegq_f16",
+    "vneg_f32",
+    "vnegq_f32",
+    "vneg_s8",
+    "vnegq_s8",
+    "vneg_s16",
+    "vnegq_s16",
+    "vneg_s32",
+    "vnegq_s32",
+    "vpadal_s8",
+    "vpadalq_s8",
+    "vpadal_s16",
+    "vpadalq_s16",
+    "vpadal_s32",
+    "vpadalq_s32",
+    "vpadal_u8",
+    "vpadalq_u8",
+    "vpadal_u16",
+    "vpadalq_u16",
+    "vpadal_u32",
+    "vpadalq_u32",
+    "vpadd_f16",
+    "vpadd_f32",
+    "vpadd_s8",
+    "vpadd_s16",
+    "vpadd_s32",
+    "vpadd_u8",
+    "vpadd_u8",
+    "vpadd_u16",
+    "vpadd_u16",
+    "vpadd_u32",
+    "vpadd_u32",
+    "vpaddl_s8",
+    "vpaddlq_s8",
+    "vpaddl_s16",
+    "vpaddlq_s16",
+    "vpaddl_s32",
+    "vpaddlq_s32",
+    "vpaddl_u8",
+    "vpaddlq_u8",
+    "vpaddl_u16",
+    "vpaddlq_u16",
+    "vpaddl_u32",
+    "vpaddlq_u32",
+    "vpmax_f32",
+    "vpmax_s8",
+    "vpmax_s16",
+    "vpmax_s32",
+    "vpmax_u8",
+    "vpmax_u16",
+    "vpmax_u32",
+    "vpmin_f32",
+    "vpmin_s8",
+    "vpmin_s16",
+    "vpmin_s32",
+    "vpmin_u8",
+    "vpmin_u16",
+    "vpmin_u32",
+    "vqabs_s8",
+    "vqabsq_s8",
+    "vqabs_s16",
+    "vqabsq_s16",
+    "vqabs_s32",
+    "vqabsq_s32",
+    "vqadd_s64",
+    "vqaddq_s64",
+    "vqadd_u64",
+    "vqaddq_u64",
+    "vqdmlal_lane_s16",
+    "vqdmlal_lane_s32",
+    "vqdmlal_n_s16",
+    "vqdmlal_n_s32",
+    "vqdmlal_s16",
+    "vqdmlal_s32",
+    "vqdmlsl_lane_s16",
+    "vqdmlsl_lane_s32",
+    "vqdmlsl_n_s16",
+    "vqdmlsl_n_s32",
+    "vqdmlsl_s16",
+    "vqdmlsl_s32",
+    "vqdmulh_laneq_s16",
+    "vqdmulhq_laneq_s16",
+    "vqdmulh_laneq_s32",
+    "vqdmulhq_laneq_s32",
+    "vqdmulh_n_s16",
+    "vqdmulhq_n_s16",
+    "vqdmulh_n_s32",
+    "vqdmulhq_n_s32",
+    "vqdmulh_s16",
+    "vqdmulhq_s16",
+    "vqdmulh_s32",
+    "vqdmulhq_s32",
+    "vqdmull_lane_s16",
+    "vqdmull_lane_s32",
+    "vqdmull_n_s16",
+    "vqdmull_n_s32",
+    "vqdmull_s16",
+    "vqdmull_s32",
+    "vqmovn_s16",
+    "vqmovn_s32",
+    "vqmovn_s64",
+    "vqmovn_u16",
+    "vqmovn_u32",
+    "vqmovn_u64",
+    "vqmovun_s16",
+    "vqmovun_s32",
+    "vqmovun_s64",
+    "vqneg_s8",
+    "vqnegq_s8",
+    "vqneg_s16",
+    "vqnegq_s16",
+    "vqneg_s32",
+    "vqnegq_s32",
+    "vqrdmulh_lane_s16",
+    "vqrdmulh_lane_s32",
+    "vqrdmulh_laneq_s16",
+    "vqrdmulh_laneq_s32",
+    "vqrdmulhq_lane_s16",
+    "vqrdmulhq_lane_s32",
+    "vqrdmulhq_laneq_s16",
+    "vqrdmulhq_laneq_s32",
+    "vqrdmulh_n_s16",
+    "vqrdmulhq_n_s16",
+    "vqrdmulh_n_s32",
+    "vqrdmulhq_n_s32",
+    "vqrdmulh_s16",
+    "vqrdmulhq_s16",
+    "vqrdmulh_s32",
+    "vqrdmulhq_s32",
+    "vqrshl_s8",
+    "vqrshlq_s8",
+    "vqrshl_s16",
+    "vqrshlq_s16",
+    "vqrshl_s32",
+    "vqrshlq_s32",
+    "vqrshl_s64",
+    "vqrshlq_s64",
+    "vqrshl_u8",
+    "vqrshlq_u8",
+    "vqrshl_u16",
+    "vqrshlq_u16",
+    "vqrshl_u32",
+    "vqrshlq_u32",
+    "vqrshl_u64",
+    "vqrshlq_u64",
+    "vqrshrn_n_s16",
+    "vqrshrn_n_s32",
+    "vqrshrn_n_s64",
+    "vqrshrn_n_s16",
+    "vqrshrn_n_s32",
+    "vqrshrn_n_s64",
+    "vqrshrn_n_u16",
+    "vqrshrn_n_u32",
+    "vqrshrn_n_u64",
+    "vqrshrn_n_u16",
+    "vqrshrn_n_u32",
+    "vqrshrn_n_u64",
+    "vqrshrun_n_s16",
+    "vqrshrun_n_s32",
+    "vqrshrun_n_s64",
+    "vqrshrun_n_s16",
+    "vqrshrun_n_s32",
+    "vqrshrun_n_s64",
+    "vqshl_n_s8",
+    "vqshlq_n_s8",
+    "vqshl_n_s16",
+    "vqshlq_n_s16",
+    "vqshl_n_s32",
+    "vqshlq_n_s32",
+    "vqshl_n_s64",
+    "vqshlq_n_s64",
+    "vqshl_n_u8",
+    "vqshlq_n_u8",
+    "vqshl_n_u16",
+    "vqshlq_n_u16",
+    "vqshl_n_u32",
+    "vqshlq_n_u32",
+    "vqshl_n_u64",
+    "vqshlq_n_u64",
+    "vqshl_s8",
+    "vqshlq_s8",
+    "vqshl_s16",
+    "vqshlq_s16",
+    "vqshl_s32",
+    "vqshlq_s32",
+    "vqshl_s64",
+    "vqshlq_s64",
+    "vqshl_u8",
+    "vqshlq_u8",
+    "vqshl_u16",
+    "vqshlq_u16",
+    "vqshl_u32",
+    "vqshlq_u32",
+    "vqshl_u64",
+    "vqshlq_u64",
+    "vqshlu_n_s8",
+    "vqshluq_n_s8",
+    "vqshlu_n_s16",
+    "vqshluq_n_s16",
+    "vqshlu_n_s32",
+    "vqshluq_n_s32",
+    "vqshlu_n_s64",
+    "vqshluq_n_s64",
+    "vqshlu_n_s8",
+    "vqshluq_n_s8",
+    "vqshlu_n_s16",
+    "vqshluq_n_s16",
+    "vqshlu_n_s32",
+    "vqshluq_n_s32",
+    "vqshlu_n_s64",
+    "vqshluq_n_s64",
+    "vqshrn_n_s16",
+    "vqshrn_n_s32",
+    "vqshrn_n_s64",
+    "vqshrn_n_s16",
+    "vqshrn_n_s32",
+    "vqshrn_n_s64",
+    "vqshrn_n_u16",
+    "vqshrn_n_u32",
+    "vqshrn_n_u64",
+    "vqshrn_n_u16",
+    "vqshrn_n_u32",
+    "vqshrn_n_u64",
+    "vqshrun_n_s16",
+    "vqshrun_n_s32",
+    "vqshrun_n_s64",
+    "vqshrun_n_s16",
+    "vqshrun_n_s32",
+    "vqshrun_n_s64",
+    "vqsub_s64",
+    "vqsubq_s64",
+    "vqsub_u64",
+    "vqsubq_u64",
+    "vraddhn_high_s16",
+    "vraddhn_high_s32",
+    "vraddhn_high_s64",
+    "vraddhn_high_u16",
+    "vraddhn_high_u32",
+    "vraddhn_high_u64",
+    "vraddhn_s16",
+    "vraddhn_s32",
+    "vraddhn_s64",
+    "vraddhn_u16",
+    "vraddhn_u16",
+    "vraddhn_u32",
+    "vraddhn_u32",
+    "vraddhn_u64",
+    "vraddhn_u64",
+    "vrecpe_f16",
+    "vrecpeq_f16",
+    "vrecpe_f32",
+    "vrecpeq_f32",
+    "vrecpe_u32",
+    "vrecpeq_u32",
+    "vrecps_f16",
+    "vrecpsq_f16",
+    "vrecps_f32",
+    "vrecpsq_f32",
+    "vreinterpret_f32_f16",
+    "vreinterpret_f32_f16",
+    "vreinterpret_s8_f16",
+    "vreinterpret_s8_f16",
+    "vreinterpret_s16_f16",
+    "vreinterpret_s16_f16",
+    "vreinterpret_s32_f16",
+    "vreinterpret_s32_f16",
+    "vreinterpret_s64_f16",
+    "vreinterpret_s64_f16",
+    "vreinterpret_u8_f16",
+    "vreinterpret_u8_f16",
+    "vreinterpret_u16_f16",
+    "vreinterpret_u16_f16",
+    "vreinterpret_u32_f16",
+    "vreinterpret_u32_f16",
+    "vreinterpret_u64_f16",
+    "vreinterpret_u64_f16",
+    "vreinterpret_p8_f16",
+    "vreinterpret_p8_f16",
+    "vreinterpret_p16_f16",
+    "vreinterpret_p16_f16",
+    "vreinterpretq_f32_f16",
+    "vreinterpretq_f32_f16",
+    "vreinterpretq_s8_f16",
+    "vreinterpretq_s8_f16",
+    "vreinterpretq_s16_f16",
+    "vreinterpretq_s16_f16",
+    "vreinterpretq_s32_f16",
+    "vreinterpretq_s32_f16",
+    "vreinterpretq_s64_f16",
+    "vreinterpretq_s64_f16",
+    "vreinterpretq_u8_f16",
+    "vreinterpretq_u8_f16",
+    "vreinterpretq_u16_f16",
+    "vreinterpretq_u16_f16",
+    "vreinterpretq_u32_f16",
+    "vreinterpretq_u32_f16",
+    "vreinterpretq_u64_f16",
+    "vreinterpretq_u64_f16",
+    "vreinterpretq_p8_f16",
+    "vreinterpretq_p8_f16",
+    "vreinterpretq_p16_f16",
+    "vreinterpretq_p16_f16",
+    "vreinterpret_f16_f32",
+    "vreinterpret_f16_f32",
+    "vreinterpretq_f16_f32",
+    "vreinterpretq_f16_f32",
+    "vreinterpret_f16_s8",
+    "vreinterpret_f16_s8",
+    "vreinterpretq_f16_s8",
+    "vreinterpretq_f16_s8",
+    "vreinterpret_f16_s16",
+    "vreinterpret_f16_s16",
+    "vreinterpretq_f16_s16",
+    "vreinterpretq_f16_s16",
+    "vreinterpret_f16_s32",
+    "vreinterpret_f16_s32",
+    "vreinterpretq_f16_s32",
+    "vreinterpretq_f16_s32",
+    "vreinterpret_f16_s64",
+    "vreinterpret_f16_s64",
+    "vreinterpretq_f16_s64",
+    "vreinterpretq_f16_s64",
+    "vreinterpret_f16_u8",
+    "vreinterpret_f16_u8",
+    "vreinterpretq_f16_u8",
+    "vreinterpretq_f16_u8",
+    "vreinterpret_f16_u16",
+    "vreinterpret_f16_u16",
+    "vreinterpretq_f16_u16",
+    "vreinterpretq_f16_u16",
+    "vreinterpret_f16_u32",
+    "vreinterpret_f16_u32",
+    "vreinterpretq_f16_u32",
+    "vreinterpretq_f16_u32",
+    "vreinterpret_f16_u64",
+    "vreinterpret_f16_u64",
+    "vreinterpretq_f16_u64",
+    "vreinterpretq_f16_u64",
+    "vreinterpret_f16_p8",
+    "vreinterpret_f16_p8",
+    "vreinterpretq_f16_p8",
+    "vreinterpretq_f16_p8",
+    "vreinterpret_f16_p16",
+    "vreinterpret_f16_p16",
+    "vreinterpretq_f16_p16",
+    "vreinterpretq_f16_p16",
+    "vreinterpretq_f16_p128",
+    "vreinterpretq_f16_p128",
+    "vreinterpret_p64_f16",
+    "vreinterpret_p64_f16",
+    "vreinterpretq_p128_f16",
+    "vreinterpretq_p128_f16",
+    "vreinterpretq_p64_f16",
+    "vreinterpretq_p64_f16",
+    "vreinterpret_f16_p64",
+    "vreinterpret_f16_p64",
+    "vreinterpretq_f16_p64",
+    "vreinterpretq_f16_p64",
+    "vreinterpretq_f32_p128",
+    "vreinterpretq_f32_p128",
+    "vreinterpret_s8_f32",
+    "vreinterpret_s8_f32",
+    "vreinterpret_s16_f32",
+    "vreinterpret_s16_f32",
+    "vreinterpret_s32_f32",
+    "vreinterpret_s32_f32",
+    "vreinterpret_s64_f32",
+    "vreinterpret_s64_f32",
+    "vreinterpret_u8_f32",
+    "vreinterpret_u8_f32",
+    "vreinterpret_u16_f32",
+    "vreinterpret_u16_f32",
+    "vreinterpret_u32_f32",
+    "vreinterpret_u32_f32",
+    "vreinterpret_u64_f32",
+    "vreinterpret_u64_f32",
+    "vreinterpret_p8_f32",
+    "vreinterpret_p8_f32",
+    "vreinterpret_p16_f32",
+    "vreinterpret_p16_f32",
+    "vreinterpretq_p128_f32",
+    "vreinterpretq_p128_f32",
+    "vreinterpretq_s8_f32",
+    "vreinterpretq_s8_f32",
+    "vreinterpretq_s16_f32",
+    "vreinterpretq_s16_f32",
+    "vreinterpretq_s32_f32",
+    "vreinterpretq_s32_f32",
+    "vreinterpretq_s64_f32",
+    "vreinterpretq_s64_f32",
+    "vreinterpretq_u8_f32",
+    "vreinterpretq_u8_f32",
+    "vreinterpretq_u16_f32",
+    "vreinterpretq_u16_f32",
+    "vreinterpretq_u32_f32",
+    "vreinterpretq_u32_f32",
+    "vreinterpretq_u64_f32",
+    "vreinterpretq_u64_f32",
+    "vreinterpretq_p8_f32",
+    "vreinterpretq_p8_f32",
+    "vreinterpretq_p16_f32",
+    "vreinterpretq_p16_f32",
+    "vreinterpret_f32_s8",
+    "vreinterpret_f32_s8",
+    "vreinterpret_s16_s8",
+    "vreinterpret_s16_s8",
+    "vreinterpret_s32_s8",
+    "vreinterpret_s32_s8",
+    "vreinterpret_s64_s8",
+    "vreinterpret_s64_s8",
+    "vreinterpret_u8_s8",
+    "vreinterpret_u8_s8",
+    "vreinterpret_u16_s8",
+    "vreinterpret_u16_s8",
+    "vreinterpret_u32_s8",
+    "vreinterpret_u32_s8",
+    "vreinterpret_u64_s8",
+    "vreinterpret_u64_s8",
+    "vreinterpret_p8_s8",
+    "vreinterpret_p8_s8",
+    "vreinterpret_p16_s8",
+    "vreinterpret_p16_s8",
+    "vreinterpretq_f32_s8",
+    "vreinterpretq_f32_s8",
+    "vreinterpretq_s16_s8",
+    "vreinterpretq_s16_s8",
+    "vreinterpretq_s32_s8",
+    "vreinterpretq_s32_s8",
+    "vreinterpretq_s64_s8",
+    "vreinterpretq_s64_s8",
+    "vreinterpretq_u8_s8",
+    "vreinterpretq_u8_s8",
+    "vreinterpretq_u16_s8",
+    "vreinterpretq_u16_s8",
+    "vreinterpretq_u32_s8",
+    "vreinterpretq_u32_s8",
+    "vreinterpretq_u64_s8",
+    "vreinterpretq_u64_s8",
+    "vreinterpretq_p8_s8",
+    "vreinterpretq_p8_s8",
+    "vreinterpretq_p16_s8",
+    "vreinterpretq_p16_s8",
+    "vreinterpret_f32_s16",
+    "vreinterpret_f32_s16",
+    "vreinterpret_s8_s16",
+    "vreinterpret_s8_s16",
+    "vreinterpret_s32_s16",
+    "vreinterpret_s32_s16",
+    "vreinterpret_s64_s16",
+    "vreinterpret_s64_s16",
+    "vreinterpret_u8_s16",
+    "vreinterpret_u8_s16",
+    "vreinterpret_u16_s16",
+    "vreinterpret_u16_s16",
+    "vreinterpret_u32_s16",
+    "vreinterpret_u32_s16",
+    "vreinterpret_u64_s16",
+    "vreinterpret_u64_s16",
+    "vreinterpret_p8_s16",
+    "vreinterpret_p8_s16",
+    "vreinterpret_p16_s16",
+    "vreinterpret_p16_s16",
+    "vreinterpretq_f32_s16",
+    "vreinterpretq_f32_s16",
+    "vreinterpretq_s8_s16",
+    "vreinterpretq_s8_s16",
+    "vreinterpretq_s32_s16",
+    "vreinterpretq_s32_s16",
+    "vreinterpretq_s64_s16",
+    "vreinterpretq_s64_s16",
+    "vreinterpretq_u8_s16",
+    "vreinterpretq_u8_s16",
+    "vreinterpretq_u16_s16",
+    "vreinterpretq_u16_s16",
+    "vreinterpretq_u32_s16",
+    "vreinterpretq_u32_s16",
+    "vreinterpretq_u64_s16",
+    "vreinterpretq_u64_s16",
+    "vreinterpretq_p8_s16",
+    "vreinterpretq_p8_s16",
+    "vreinterpretq_p16_s16",
+    "vreinterpretq_p16_s16",
+    "vreinterpret_f32_s32",
+    "vreinterpret_f32_s32",
+    "vreinterpret_s8_s32",
+    "vreinterpret_s8_s32",
+    "vreinterpret_s16_s32",
+    "vreinterpret_s16_s32",
+    "vreinterpret_s64_s32",
+    "vreinterpret_s64_s32",
+    "vreinterpret_u8_s32",
+    "vreinterpret_u8_s32",
+    "vreinterpret_u16_s32",
+    "vreinterpret_u16_s32",
+    "vreinterpret_u32_s32",
+    "vreinterpret_u32_s32",
+    "vreinterpret_u64_s32",
+    "vreinterpret_u64_s32",
+    "vreinterpret_p8_s32",
+    "vreinterpret_p8_s32",
+    "vreinterpret_p16_s32",
+    "vreinterpret_p16_s32",
+    "vreinterpretq_f32_s32",
+    "vreinterpretq_f32_s32",
+    "vreinterpretq_s8_s32",
+    "vreinterpretq_s8_s32",
+    "vreinterpretq_s16_s32",
+    "vreinterpretq_s16_s32",
+    "vreinterpretq_s64_s32",
+    "vreinterpretq_s64_s32",
+    "vreinterpretq_u8_s32",
+    "vreinterpretq_u8_s32",
+    "vreinterpretq_u16_s32",
+    "vreinterpretq_u16_s32",
+    "vreinterpretq_u32_s32",
+    "vreinterpretq_u32_s32",
+    "vreinterpretq_u64_s32",
+    "vreinterpretq_u64_s32",
+    "vreinterpretq_p8_s32",
+    "vreinterpretq_p8_s32",
+    "vreinterpretq_p16_s32",
+    "vreinterpretq_p16_s32",
+    "vreinterpret_f32_s64",
+    "vreinterpret_f32_s64",
+    "vreinterpret_s8_s64",
+    "vreinterpret_s8_s64",
+    "vreinterpret_s16_s64",
+    "vreinterpret_s16_s64",
+    "vreinterpret_s32_s64",
+    "vreinterpret_s32_s64",
+    "vreinterpret_u8_s64",
+    "vreinterpret_u8_s64",
+    "vreinterpret_u16_s64",
+    "vreinterpret_u16_s64",
+    "vreinterpret_u32_s64",
+    "vreinterpret_u32_s64",
+    "vreinterpret_u64_s64",
+    "vreinterpret_p8_s64",
+    "vreinterpret_p8_s64",
+    "vreinterpret_p16_s64",
+    "vreinterpret_p16_s64",
+    "vreinterpretq_f32_s64",
+    "vreinterpretq_f32_s64",
+    "vreinterpretq_s8_s64",
+    "vreinterpretq_s8_s64",
+    "vreinterpretq_s16_s64",
+    "vreinterpretq_s16_s64",
+    "vreinterpretq_s32_s64",
+    "vreinterpretq_s32_s64",
+    "vreinterpretq_u8_s64",
+    "vreinterpretq_u8_s64",
+    "vreinterpretq_u16_s64",
+    "vreinterpretq_u16_s64",
+    "vreinterpretq_u32_s64",
+    "vreinterpretq_u32_s64",
+    "vreinterpretq_u64_s64",
+    "vreinterpretq_u64_s64",
+    "vreinterpretq_p8_s64",
+    "vreinterpretq_p8_s64",
+    "vreinterpretq_p16_s64",
+    "vreinterpretq_p16_s64",
+    "vreinterpret_f32_u8",
+    "vreinterpret_f32_u8",
+    "vreinterpret_s8_u8",
+    "vreinterpret_s8_u8",
+    "vreinterpret_s16_u8",
+    "vreinterpret_s16_u8",
+    "vreinterpret_s32_u8",
+    "vreinterpret_s32_u8",
+    "vreinterpret_s64_u8",
+    "vreinterpret_s64_u8",
+    "vreinterpret_u16_u8",
+    "vreinterpret_u16_u8",
+    "vreinterpret_u32_u8",
+    "vreinterpret_u32_u8",
+    "vreinterpret_u64_u8",
+    "vreinterpret_u64_u8",
+    "vreinterpret_p8_u8",
+    "vreinterpret_p8_u8",
+    "vreinterpret_p16_u8",
+    "vreinterpret_p16_u8",
+    "vreinterpretq_f32_u8",
+    "vreinterpretq_f32_u8",
+    "vreinterpretq_s8_u8",
+    "vreinterpretq_s8_u8",
+    "vreinterpretq_s16_u8",
+    "vreinterpretq_s16_u8",
+    "vreinterpretq_s32_u8",
+    "vreinterpretq_s32_u8",
+    "vreinterpretq_s64_u8",
+    "vreinterpretq_s64_u8",
+    "vreinterpretq_u16_u8",
+    "vreinterpretq_u16_u8",
+    "vreinterpretq_u32_u8",
+    "vreinterpretq_u32_u8",
+    "vreinterpretq_u64_u8",
+    "vreinterpretq_u64_u8",
+    "vreinterpretq_p8_u8",
+    "vreinterpretq_p8_u8",
+    "vreinterpretq_p16_u8",
+    "vreinterpretq_p16_u8",
+    "vreinterpret_f32_u16",
+    "vreinterpret_f32_u16",
+    "vreinterpret_s8_u16",
+    "vreinterpret_s8_u16",
+    "vreinterpret_s16_u16",
+    "vreinterpret_s16_u16",
+    "vreinterpret_s32_u16",
+    "vreinterpret_s32_u16",
+    "vreinterpret_s64_u16",
+    "vreinterpret_s64_u16",
+    "vreinterpret_u8_u16",
+    "vreinterpret_u8_u16",
+    "vreinterpret_u32_u16",
+    "vreinterpret_u32_u16",
+    "vreinterpret_u64_u16",
+    "vreinterpret_u64_u16",
+    "vreinterpret_p8_u16",
+    "vreinterpret_p8_u16",
+    "vreinterpret_p16_u16",
+    "vreinterpret_p16_u16",
+    "vreinterpretq_f32_u16",
+    "vreinterpretq_f32_u16",
+    "vreinterpretq_s8_u16",
+    "vreinterpretq_s8_u16",
+    "vreinterpretq_s16_u16",
+    "vreinterpretq_s16_u16",
+    "vreinterpretq_s32_u16",
+    "vreinterpretq_s32_u16",
+    "vreinterpretq_s64_u16",
+    "vreinterpretq_s64_u16",
+    "vreinterpretq_u8_u16",
+    "vreinterpretq_u8_u16",
+    "vreinterpretq_u32_u16",
+    "vreinterpretq_u32_u16",
+    "vreinterpretq_u64_u16",
+    "vreinterpretq_u64_u16",
+    "vreinterpretq_p8_u16",
+    "vreinterpretq_p8_u16",
+    "vreinterpretq_p16_u16",
+    "vreinterpretq_p16_u16",
+    "vreinterpret_f32_u32",
+    "vreinterpret_f32_u32",
+    "vreinterpret_s8_u32",
+    "vreinterpret_s8_u32",
+    "vreinterpret_s16_u32",
+    "vreinterpret_s16_u32",
+    "vreinterpret_s32_u32",
+    "vreinterpret_s32_u32",
+    "vreinterpret_s64_u32",
+    "vreinterpret_s64_u32",
+    "vreinterpret_u8_u32",
+    "vreinterpret_u8_u32",
+    "vreinterpret_u16_u32",
+    "vreinterpret_u16_u32",
+    "vreinterpret_u64_u32",
+    "vreinterpret_u64_u32",
+    "vreinterpret_p8_u32",
+    "vreinterpret_p8_u32",
+    "vreinterpret_p16_u32",
+    "vreinterpret_p16_u32",
+    "vreinterpretq_f32_u32",
+    "vreinterpretq_f32_u32",
+    "vreinterpretq_s8_u32",
+    "vreinterpretq_s8_u32",
+    "vreinterpretq_s16_u32",
+    "vreinterpretq_s16_u32",
+    "vreinterpretq_s32_u32",
+    "vreinterpretq_s32_u32",
+    "vreinterpretq_s64_u32",
+    "vreinterpretq_s64_u32",
+    "vreinterpretq_u8_u32",
+    "vreinterpretq_u8_u32",
+    "vreinterpretq_u16_u32",
+    "vreinterpretq_u16_u32",
+    "vreinterpretq_u64_u32",
+    "vreinterpretq_u64_u32",
+    "vreinterpretq_p8_u32",
+    "vreinterpretq_p8_u32",
+    "vreinterpretq_p16_u32",
+    "vreinterpretq_p16_u32",
+    "vreinterpret_f32_u64",
+    "vreinterpret_f32_u64",
+    "vreinterpret_s8_u64",
+    "vreinterpret_s8_u64",
+    "vreinterpret_s16_u64",
+    "vreinterpret_s16_u64",
+    "vreinterpret_s32_u64",
+    "vreinterpret_s32_u64",
+    "vreinterpret_s64_u64",
+    "vreinterpret_u8_u64",
+    "vreinterpret_u8_u64",
+    "vreinterpret_u16_u64",
+    "vreinterpret_u16_u64",
+    "vreinterpret_u32_u64",
+    "vreinterpret_u32_u64",
+    "vreinterpret_p8_u64",
+    "vreinterpret_p8_u64",
+    "vreinterpret_p16_u64",
+    "vreinterpret_p16_u64",
+    "vreinterpretq_f32_u64",
+    "vreinterpretq_f32_u64",
+    "vreinterpretq_s8_u64",
+    "vreinterpretq_s8_u64",
+    "vreinterpretq_s16_u64",
+    "vreinterpretq_s16_u64",
+    "vreinterpretq_s32_u64",
+    "vreinterpretq_s32_u64",
+    "vreinterpretq_s64_u64",
+    "vreinterpretq_s64_u64",
+    "vreinterpretq_u8_u64",
+    "vreinterpretq_u8_u64",
+    "vreinterpretq_u16_u64",
+    "vreinterpretq_u16_u64",
+    "vreinterpretq_u32_u64",
+    "vreinterpretq_u32_u64",
+    "vreinterpretq_p8_u64",
+    "vreinterpretq_p8_u64",
+    "vreinterpretq_p16_u64",
+    "vreinterpretq_p16_u64",
+    "vreinterpret_f32_p8",
+    "vreinterpret_f32_p8",
+    "vreinterpret_s8_p8",
+    "vreinterpret_s8_p8",
+    "vreinterpret_s16_p8",
+    "vreinterpret_s16_p8",
+    "vreinterpret_s32_p8",
+    "vreinterpret_s32_p8",
+    "vreinterpret_s64_p8",
+    "vreinterpret_s64_p8",
+    "vreinterpret_u8_p8",
+    "vreinterpret_u8_p8",
+    "vreinterpret_u16_p8",
+    "vreinterpret_u16_p8",
+    "vreinterpret_u32_p8",
+    "vreinterpret_u32_p8",
+    "vreinterpret_u64_p8",
+    "vreinterpret_u64_p8",
+    "vreinterpret_p16_p8",
+    "vreinterpret_p16_p8",
+    "vreinterpretq_f32_p8",
+    "vreinterpretq_f32_p8",
+    "vreinterpretq_s8_p8",
+    "vreinterpretq_s8_p8",
+    "vreinterpretq_s16_p8",
+    "vreinterpretq_s16_p8",
+    "vreinterpretq_s32_p8",
+    "vreinterpretq_s32_p8",
+    "vreinterpretq_s64_p8",
+    "vreinterpretq_s64_p8",
+    "vreinterpretq_u8_p8",
+    "vreinterpretq_u8_p8",
+    "vreinterpretq_u16_p8",
+    "vreinterpretq_u16_p8",
+    "vreinterpretq_u32_p8",
+    "vreinterpretq_u32_p8",
+    "vreinterpretq_u64_p8",
+    "vreinterpretq_u64_p8",
+    "vreinterpretq_p16_p8",
+    "vreinterpretq_p16_p8",
+    "vreinterpret_f32_p16",
+    "vreinterpret_f32_p16",
+    "vreinterpret_s8_p16",
+    "vreinterpret_s8_p16",
+    "vreinterpret_s16_p16",
+    "vreinterpret_s16_p16",
+    "vreinterpret_s32_p16",
+    "vreinterpret_s32_p16",
+    "vreinterpret_s64_p16",
+    "vreinterpret_s64_p16",
+    "vreinterpret_u8_p16",
+    "vreinterpret_u8_p16",
+    "vreinterpret_u16_p16",
+    "vreinterpret_u16_p16",
+    "vreinterpret_u32_p16",
+    "vreinterpret_u32_p16",
+    "vreinterpret_u64_p16",
+    "vreinterpret_u64_p16",
+    "vreinterpret_p8_p16",
+    "vreinterpret_p8_p16",
+    "vreinterpretq_f32_p16",
+    "vreinterpretq_f32_p16",
+    "vreinterpretq_s8_p16",
+    "vreinterpretq_s8_p16",
+    "vreinterpretq_s16_p16",
+    "vreinterpretq_s16_p16",
+    "vreinterpretq_s32_p16",
+    "vreinterpretq_s32_p16",
+    "vreinterpretq_s64_p16",
+    "vreinterpretq_s64_p16",
+    "vreinterpretq_u8_p16",
+    "vreinterpretq_u8_p16",
+    "vreinterpretq_u16_p16",
+    "vreinterpretq_u16_p16",
+    "vreinterpretq_u32_p16",
+    "vreinterpretq_u32_p16",
+    "vreinterpretq_u64_p16",
+    "vreinterpretq_u64_p16",
+    "vreinterpretq_p8_p16",
+    "vreinterpretq_p8_p16",
+    "vreinterpretq_s8_p128",
+    "vreinterpretq_s8_p128",
+    "vreinterpretq_s16_p128",
+    "vreinterpretq_s16_p128",
+    "vreinterpretq_s32_p128",
+    "vreinterpretq_s32_p128",
+    "vreinterpretq_s64_p128",
+    "vreinterpretq_s64_p128",
+    "vreinterpretq_u8_p128",
+    "vreinterpretq_u8_p128",
+    "vreinterpretq_u16_p128",
+    "vreinterpretq_u16_p128",
+    "vreinterpretq_u32_p128",
+    "vreinterpretq_u32_p128",
+    "vreinterpretq_u64_p128",
+    "vreinterpretq_u64_p128",
+    "vreinterpretq_p8_p128",
+    "vreinterpretq_p8_p128",
+    "vreinterpretq_p16_p128",
+    "vreinterpretq_p16_p128",
+    "vreinterpretq_p64_p128",
+    "vreinterpretq_p64_p128",
+    "vreinterpret_p64_s8",
+    "vreinterpret_p64_s8",
+    "vreinterpretq_p128_s8",
+    "vreinterpretq_p128_s8",
+    "vreinterpretq_p64_s8",
+    "vreinterpretq_p64_s8",
+    "vreinterpret_p64_s16",
+    "vreinterpret_p64_s16",
+    "vreinterpretq_p128_s16",
+    "vreinterpretq_p128_s16",
+    "vreinterpretq_p64_s16",
+    "vreinterpretq_p64_s16",
+    "vreinterpret_p64_s32",
+    "vreinterpret_p64_s32",
+    "vreinterpretq_p128_s32",
+    "vreinterpretq_p128_s32",
+    "vreinterpretq_p64_s32",
+    "vreinterpretq_p64_s32",
+    "vreinterpretq_p128_s64",
+    "vreinterpretq_p128_s64",
+    "vreinterpret_p64_u8",
+    "vreinterpret_p64_u8",
+    "vreinterpretq_p128_u8",
+    "vreinterpretq_p128_u8",
+    "vreinterpretq_p64_u8",
+    "vreinterpretq_p64_u8",
+    "vreinterpret_p64_u16",
+    "vreinterpret_p64_u16",
+    "vreinterpretq_p128_u16",
+    "vreinterpretq_p128_u16",
+    "vreinterpretq_p64_u16",
+    "vreinterpretq_p64_u16",
+    "vreinterpret_p64_u32",
+    "vreinterpret_p64_u32",
+    "vreinterpretq_p128_u32",
+    "vreinterpretq_p128_u32",
+    "vreinterpretq_p64_u32",
+    "vreinterpretq_p64_u32",
+    "vreinterpretq_p128_u64",
+    "vreinterpretq_p128_u64",
+    "vreinterpret_p64_p8",
+    "vreinterpret_p64_p8",
+    "vreinterpretq_p128_p8",
+    "vreinterpretq_p128_p8",
+    "vreinterpretq_p64_p8",
+    "vreinterpretq_p64_p8",
+    "vreinterpret_p64_p16",
+    "vreinterpret_p64_p16",
+    "vreinterpretq_p128_p16",
+    "vreinterpretq_p128_p16",
+    "vreinterpretq_p64_p16",
+    "vreinterpretq_p64_p16",
+    "vreinterpret_s8_p64",
+    "vreinterpret_s8_p64",
+    "vreinterpret_s16_p64",
+    "vreinterpret_s16_p64",
+    "vreinterpret_s32_p64",
+    "vreinterpret_s32_p64",
+    "vreinterpret_u8_p64",
+    "vreinterpret_u8_p64",
+    "vreinterpret_u16_p64",
+    "vreinterpret_u16_p64",
+    "vreinterpret_u32_p64",
+    "vreinterpret_u32_p64",
+    "vreinterpret_p8_p64",
+    "vreinterpret_p8_p64",
+    "vreinterpret_p16_p64",
+    "vreinterpret_p16_p64",
+    "vreinterpretq_p128_p64",
+    "vreinterpretq_p128_p64",
+    "vreinterpretq_s8_p64",
+    "vreinterpretq_s8_p64",
+    "vreinterpretq_s16_p64",
+    "vreinterpretq_s16_p64",
+    "vreinterpretq_s32_p64",
+    "vreinterpretq_s32_p64",
+    "vreinterpretq_u8_p64",
+    "vreinterpretq_u8_p64",
+    "vreinterpretq_u16_p64",
+    "vreinterpretq_u16_p64",
+    "vreinterpretq_u32_p64",
+    "vreinterpretq_u32_p64",
+    "vreinterpretq_p8_p64",
+    "vreinterpretq_p8_p64",
+    "vreinterpretq_p16_p64",
+    "vreinterpretq_p16_p64",
+    "vrev64_f16",
+    "vrev64q_f16",
+    "vrndn_f16",
+    "vrndnq_f16",
+    "vrndn_f32",
+    "vrndnq_f32",
+    "vrshl_s8",
+    "vrshlq_s8",
+    "vrshl_s16",
+    "vrshlq_s16",
+    "vrshl_s32",
+    "vrshlq_s32",
+    "vrshl_s64",
+    "vrshlq_s64",
+    "vrshl_u8",
+    "vrshlq_u8",
+    "vrshl_u16",
+    "vrshlq_u16",
+    "vrshl_u32",
+    "vrshlq_u32",
+    "vrshl_u64",
+    "vrshlq_u64",
+    "vrshr_n_s8",
+    "vrshrq_n_s8",
+    "vrshr_n_s16",
+    "vrshrq_n_s16",
+    "vrshr_n_s32",
+    "vrshrq_n_s32",
+    "vrshr_n_s64",
+    "vrshrq_n_s64",
+    "vrshr_n_u8",
+    "vrshrq_n_u8",
+    "vrshr_n_u16",
+    "vrshrq_n_u16",
+    "vrshr_n_u32",
+    "vrshrq_n_u32",
+    "vrshr_n_u64",
+    "vrshrq_n_u64",
+    "vrshrn_n_s16",
+    "vrshrn_n_s32",
+    "vrshrn_n_s64",
+    "vrshrn_n_s16",
+    "vrshrn_n_s32",
+    "vrshrn_n_s64",
+    "vrshrn_n_u16",
+    "vrshrn_n_u32",
+    "vrshrn_n_u64",
+    "vrsqrte_f16",
+    "vrsqrteq_f16",
+    "vrsqrteq_f32",
+    "vrsqrte_u32",
+    "vrsqrteq_u32",
+    "vrsqrts_f16",
+    "vrsqrtsq_f16",
+    "vrsqrts_f32",
+    "vrsqrtsq_f32",
+    "vrsra_n_s8",
+    "vrsraq_n_s8",
+    "vrsra_n_s16",
+    "vrsraq_n_s16",
+    "vrsra_n_s32",
+    "vrsraq_n_s32",
+    "vrsra_n_s64",
+    "vrsraq_n_s64",
+    "vrsra_n_u8",
+    "vrsraq_n_u8",
+    "vrsra_n_u16",
+    "vrsraq_n_u16",
+    "vrsra_n_u32",
+    "vrsraq_n_u32",
+    "vrsra_n_u64",
+    "vrsraq_n_u64",
+    "vrsubhn_s16",
+    "vrsubhn_s32",
+    "vrsubhn_s64",
+    "vrsubhn_u16",
+    "vrsubhn_u16",
+    "vrsubhn_u32",
+    "vrsubhn_u32",
+    "vrsubhn_u64",
+    "vrsubhn_u64",
+    "vset_lane_f16",
+    "vsetq_lane_f16",
+    "vset_lane_f32",
+    "vsetq_lane_f32",
+    "vset_lane_s8",
+    "vsetq_lane_s8",
+    "vset_lane_s16",
+    "vsetq_lane_s16",
+    "vset_lane_s32",
+    "vsetq_lane_s32",
+    "vsetq_lane_s64",
+    "vset_lane_u8",
+    "vsetq_lane_u8",
+    "vset_lane_u16",
+    "vsetq_lane_u16",
+    "vset_lane_u32",
+    "vsetq_lane_u32",
+    "vsetq_lane_u64",
+    "vset_lane_p8",
+    "vsetq_lane_p8",
+    "vset_lane_p16",
+    "vsetq_lane_p16",
+    "vset_lane_p64",
+    "vset_lane_s64",
+    "vset_lane_u64",
+    "vsetq_lane_p64",
+    "vsha1cq_u32",
+    "vsha1h_u32",
+    "vsha1mq_u32",
+    "vsha1pq_u32",
+    "vsha1su0q_u32",
+    "vsha1su1q_u32",
+    "vsha256h2q_u32",
+    "vsha256hq_u32",
+    "vsha256su0q_u32",
+    "vsha256su1q_u32",
+    "vshl_n_s8",
+    "vshlq_n_s8",
+    "vshl_n_s16",
+    "vshlq_n_s16",
+    "vshl_n_s32",
+    "vshlq_n_s32",
+    "vshl_n_s64",
+    "vshlq_n_s64",
+    "vshl_n_u8",
+    "vshlq_n_u8",
+    "vshl_n_u16",
+    "vshlq_n_u16",
+    "vshl_n_u32",
+    "vshlq_n_u32",
+    "vshl_n_u64",
+    "vshlq_n_u64",
+    "vshl_s8",
+    "vshlq_s8",
+    "vshl_s16",
+    "vshlq_s16",
+    "vshl_s32",
+    "vshlq_s32",
+    "vshl_s64",
+    "vshlq_s64",
+    "vshl_u8",
+    "vshlq_u8",
+    "vshl_u16",
+    "vshlq_u16",
+    "vshl_u32",
+    "vshlq_u32",
+    "vshl_u64",
+    "vshlq_u64",
+    "vshll_n_s16",
+    "vshll_n_s32",
+    "vshll_n_s8",
+    "vshll_n_u16",
+    "vshll_n_u32",
+    "vshll_n_u8",
+    "vshr_n_s8",
+    "vshrq_n_s8",
+    "vshr_n_s16",
+    "vshrq_n_s16",
+    "vshr_n_s32",
+    "vshrq_n_s32",
+    "vshr_n_s64",
+    "vshrq_n_s64",
+    "vshr_n_u8",
+    "vshrq_n_u8",
+    "vshr_n_u16",
+    "vshrq_n_u16",
+    "vshr_n_u32",
+    "vshrq_n_u32",
+    "vshr_n_u64",
+    "vshrq_n_u64",
+    "vshrn_n_s16",
+    "vshrn_n_s32",
+    "vshrn_n_s64",
+    "vshrn_n_u16",
+    "vshrn_n_u32",
+    "vshrn_n_u64",
+    "vsra_n_s8",
+    "vsraq_n_s8",
+    "vsra_n_s16",
+    "vsraq_n_s16",
+    "vsra_n_s32",
+    "vsraq_n_s32",
+    "vsra_n_s64",
+    "vsraq_n_s64",
+    "vsra_n_u8",
+    "vsraq_n_u8",
+    "vsra_n_u16",
+    "vsraq_n_u16",
+    "vsra_n_u32",
+    "vsraq_n_u32",
+    "vsra_n_u64",
+    "vsraq_n_u64",
+    "vst1_f16",
+    "vst1q_f16",
+    "vst1_f16_x2",
+    "vst1q_f16_x2",
+    "vst1_f16_x2",
+    "vst1q_f16_x2",
+    "vst1_f16_x3",
+    "vst1q_f16_x3",
+    "vst1_f16_x3",
+    "vst1q_f16_x3",
+    "vst1_f16_x4",
+    "vst1q_f16_x4",
+    "vst1_f16_x4",
+    "vst1q_f16_x4",
+    "vst1_f32_x2",
+    "vst1q_f32_x2",
+    "vst1_f32_x2",
+    "vst1q_f32_x2",
+    "vst1_f32_x3",
+    "vst1q_f32_x3",
+    "vst1_f32_x4",
+    "vst1q_f32_x4",
+    "vst1_f32_x4",
+    "vst1q_f32_x4",
+    "vst1_lane_f16",
+    "vst1q_lane_f16",
+    "vst1_lane_f32",
+    "vst1q_lane_f32",
+    "vst1_lane_s8",
+    "vst1q_lane_s8",
+    "vst1_lane_s16",
+    "vst1q_lane_s16",
+    "vst1_lane_s32",
+    "vst1q_lane_s32",
+    "vst1q_lane_s64",
+    "vst1_lane_u8",
+    "vst1q_lane_u8",
+    "vst1_lane_u16",
+    "vst1q_lane_u16",
+    "vst1_lane_u32",
+    "vst1q_lane_u32",
+    "vst1q_lane_u64",
+    "vst1_lane_p8",
+    "vst1q_lane_p8",
+    "vst1_lane_p16",
+    "vst1q_lane_p16",
+    "vst1_lane_p64",
+    "vst1_lane_s64",
+    "vst1_lane_u64",
+    "vst1_p64_x2",
+    "vst1_p64_x3",
+    "vst1_p64_x4",
+    "vst1q_p64_x2",
+    "vst1q_p64_x3",
+    "vst1q_p64_x4",
+    "vst1_s8_x2",
+    "vst1q_s8_x2",
+    "vst1_s16_x2",
+    "vst1q_s16_x2",
+    "vst1_s32_x2",
+    "vst1q_s32_x2",
+    "vst1_s64_x2",
+    "vst1q_s64_x2",
+    "vst1_s8_x2",
+    "vst1q_s8_x2",
+    "vst1_s16_x2",
+    "vst1q_s16_x2",
+    "vst1_s32_x2",
+    "vst1q_s32_x2",
+    "vst1_s64_x2",
+    "vst1q_s64_x2",
+    "vst1_s8_x3",
+    "vst1q_s8_x3",
+    "vst1_s16_x3",
+    "vst1q_s16_x3",
+    "vst1_s32_x3",
+    "vst1q_s32_x3",
+    "vst1_s64_x3",
+    "vst1q_s64_x3",
+    "vst1_s8_x3",
+    "vst1q_s8_x3",
+    "vst1_s16_x3",
+    "vst1q_s16_x3",
+    "vst1_s32_x3",
+    "vst1q_s32_x3",
+    "vst1_s64_x3",
+    "vst1q_s64_x3",
+    "vst1_s8_x4",
+    "vst1q_s8_x4",
+    "vst1_s16_x4",
+    "vst1q_s16_x4",
+    "vst1_s32_x4",
+    "vst1q_s32_x4",
+    "vst1_s64_x4",
+    "vst1q_s64_x4",
+    "vst1_s8_x4",
+    "vst1q_s8_x4",
+    "vst1_s16_x4",
+    "vst1q_s16_x4",
+    "vst1_s32_x4",
+    "vst1q_s32_x4",
+    "vst1_s64_x4",
+    "vst1q_s64_x4",
+    "vst1_u8_x2",
+    "vst1_u8_x3",
+    "vst1_u8_x4",
+    "vst1q_u8_x2",
+    "vst1q_u8_x3",
+    "vst1q_u8_x4",
+    "vst1_u16_x2",
+    "vst1_u16_x3",
+    "vst1_u16_x4",
+    "vst1q_u16_x2",
+    "vst1q_u16_x3",
+    "vst1q_u16_x4",
+    "vst1_u32_x2",
+    "vst1_u32_x3",
+    "vst1_u32_x4",
+    "vst1q_u32_x2",
+    "vst1q_u32_x3",
+    "vst1q_u32_x4",
+    "vst1_u64_x2",
+    "vst1_u64_x3",
+    "vst1_u64_x4",
+    "vst1q_u64_x2",
+    "vst1q_u64_x3",
+    "vst1q_u64_x4",
+    "vst1_p8_x2",
+    "vst1_p8_x3",
+    "vst1_p8_x4",
+    "vst1q_p8_x2",
+    "vst1q_p8_x3",
+    "vst1q_p8_x4",
+    "vst1_p16_x2",
+    "vst1_p16_x3",
+    "vst1_p16_x4",
+    "vst1q_p16_x2",
+    "vst1q_p16_x3",
+    "vst1q_p16_x4",
+    "vst1q_lane_p64",
+    "vst2_f16",
+    "vst2q_f16",
+    "vst2_f16",
+    "vst2q_f16",
+    "vst2_f32",
+    "vst2q_f32",
+    "vst2_s8",
+    "vst2q_s8",
+    "vst2_s16",
+    "vst2q_s16",
+    "vst2_s32",
+    "vst2q_s32",
+    "vst2_f32",
+    "vst2q_f32",
+    "vst2_s8",
+    "vst2q_s8",
+    "vst2_s16",
+    "vst2q_s16",
+    "vst2_s32",
+    "vst2q_s32",
+    "vst2_lane_f16",
+    "vst2q_lane_f16",
+    "vst2_lane_f16",
+    "vst2q_lane_f16",
+    "vst2_lane_f32",
+    "vst2q_lane_f32",
+    "vst2_lane_s8",
+    "vst2_lane_s16",
+    "vst2q_lane_s16",
+    "vst2_lane_s32",
+    "vst2q_lane_s32",
+    "vst2_lane_f32",
+    "vst2q_lane_f32",
+    "vst2_lane_s8",
+    "vst2_lane_s16",
+    "vst2q_lane_s16",
+    "vst2_lane_s32",
+    "vst2q_lane_s32",
+    "vst2_lane_u8",
+    "vst2_lane_u16",
+    "vst2q_lane_u16",
+    "vst2_lane_u32",
+    "vst2q_lane_u32",
+    "vst2_lane_p8",
+    "vst2_lane_p16",
+    "vst2q_lane_p16",
+    "vst2_p64",
+    "vst2_s64",
+    "vst2_s64",
+    "vst2_u64",
+    "vst2_u8",
+    "vst2q_u8",
+    "vst2_u16",
+    "vst2q_u16",
+    "vst2_u32",
+    "vst2q_u32",
+    "vst2_p8",
+    "vst2q_p8",
+    "vst2_p16",
+    "vst2q_p16",
+    "vst3_f16",
+    "vst3q_f16",
+    "vst3_f16",
+    "vst3q_f16",
+    "vst3_f32",
+    "vst3q_f32",
+    "vst3_s8",
+    "vst3q_s8",
+    "vst3_s16",
+    "vst3q_s16",
+    "vst3_s32",
+    "vst3q_s32",
+    "vst3_f32",
+    "vst3q_f32",
+    "vst3_s8",
+    "vst3q_s8",
+    "vst3_s16",
+    "vst3q_s16",
+    "vst3_s32",
+    "vst3q_s32",
+    "vst3_lane_f16",
+    "vst3q_lane_f16",
+    "vst3_lane_f16",
+    "vst3q_lane_f16",
+    "vst3_lane_f32",
+    "vst3q_lane_f32",
+    "vst3_lane_s8",
+    "vst3_lane_s16",
+    "vst3q_lane_s16",
+    "vst3_lane_s32",
+    "vst3q_lane_s32",
+    "vst3_lane_f32",
+    "vst3q_lane_f32",
+    "vst3_lane_s8",
+    "vst3_lane_s16",
+    "vst3q_lane_s16",
+    "vst3_lane_s32",
+    "vst3q_lane_s32",
+    "vst3_lane_u8",
+    "vst3_lane_u16",
+    "vst3q_lane_u16",
+    "vst3_lane_u32",
+    "vst3q_lane_u32",
+    "vst3_lane_p8",
+    "vst3_lane_p16",
+    "vst3q_lane_p16",
+    "vst3_p64",
+    "vst3_s64",
+    "vst3_s64",
+    "vst3_u64",
+    "vst3_u8",
+    "vst3q_u8",
+    "vst3_u16",
+    "vst3q_u16",
+    "vst3_u32",
+    "vst3q_u32",
+    "vst3_p8",
+    "vst3q_p8",
+    "vst3_p16",
+    "vst3q_p16",
+    "vst4_f16",
+    "vst4q_f16",
+    "vst4_f16",
+    "vst4q_f16",
+    "vst4_f32",
+    "vst4q_f32",
+    "vst4_s8",
+    "vst4q_s8",
+    "vst4_s16",
+    "vst4q_s16",
+    "vst4_s32",
+    "vst4q_s32",
+    "vst4_f32",
+    "vst4q_f32",
+    "vst4_s8",
+    "vst4q_s8",
+    "vst4_s16",
+    "vst4q_s16",
+    "vst4_s32",
+    "vst4q_s32",
+    "vst4_lane_f16",
+    "vst4q_lane_f16",
+    "vst4_lane_f16",
+    "vst4q_lane_f16",
+    "vst4_lane_f32",
+    "vst4q_lane_f32",
+    "vst4_lane_s8",
+    "vst4_lane_s16",
+    "vst4q_lane_s16",
+    "vst4_lane_s32",
+    "vst4q_lane_s32",
+    "vst4_lane_f32",
+    "vst4q_lane_f32",
+    "vst4_lane_s8",
+    "vst4_lane_s16",
+    "vst4q_lane_s16",
+    "vst4_lane_s32",
+    "vst4q_lane_s32",
+    "vst4_lane_u8",
+    "vst4_lane_u16",
+    "vst4q_lane_u16",
+    "vst4_lane_u32",
+    "vst4q_lane_u32",
+    "vst4_lane_p8",
+    "vst4_lane_p16",
+    "vst4q_lane_p16",
+    "vst4_p64",
+    "vst4_s64",
+    "vst4_s64",
+    "vst4_u64",
+    "vst4_u8",
+    "vst4q_u8",
+    "vst4_u16",
+    "vst4q_u16",
+    "vst4_u32",
+    "vst4q_u32",
+    "vst4_p8",
+    "vst4q_p8",
+    "vst4_p16",
+    "vst4q_p16",
+    "vsub_f16",
+    "vsubq_f16",
+    "vsub_s64",
+    "vsubq_s64",
+    "vsub_u64",
+    "vsubq_u64",
+    "vsubhn_high_s16",
+    "vsubhn_high_s32",
+    "vsubhn_high_s64",
+    "vsubhn_high_u16",
+    "vsubhn_high_u32",
+    "vsubhn_high_u64",
+    "vsubhn_s16",
+    "vsubhn_s32",
+    "vsubhn_s64",
+    "vsubhn_u16",
+    "vsubhn_u32",
+    "vsubhn_u64",
+    "vsubl_s8",
+    "vsubl_s16",
+    "vsubl_s32",
+    "vsubl_u8",
+    "vsubl_u16",
+    "vsubl_u32",
+    "vsubw_s8",
+    "vsubw_s16",
+    "vsubw_s32",
+    "vsubw_u8",
+    "vsubw_u16",
+    "vsubw_u32",
+    "vsudot_lane_s32",
+    "vsudot_lane_s32",
+    "vsudotq_lane_s32",
+    "vsudotq_lane_s32",
+    "vsudot_laneq_s32",
+    "vsudotq_laneq_s32",
+    "vtrn_f16",
+    "vtrnq_f16",
+    "vtrn_f32",
+    "vtrn_s32",
+    "vtrn_u32",
+    "vtrnq_f32",
+    "vtrn_s8",
+    "vtrnq_s8",
+    "vtrn_s16",
+    "vtrnq_s16",
+    "vtrnq_s32",
+    "vtrn_u8",
+    "vtrnq_u8",
+    "vtrn_u16",
+    "vtrnq_u16",
+    "vtrnq_u32",
+    "vtrn_p8",
+    "vtrnq_p8",
+    "vtrn_p16",
+    "vtrnq_p16",
+    "vtst_s8",
+    "vtstq_s8",
+    "vtst_s16",
+    "vtstq_s16",
+    "vtst_s32",
+    "vtstq_s32",
+    "vtst_p8",
+    "vtstq_p8",
+    "vtst_p16",
+    "vtstq_p16",
+    "vtst_u8",
+    "vtstq_u8",
+    "vtst_u16",
+    "vtstq_u16",
+    "vtst_u32",
+    "vtstq_u32",
+    "vusdot_lane_s32",
+    "vusdot_lane_s32",
+    "vusdotq_lane_s32",
+    "vusdotq_lane_s32",
+    "vusdot_laneq_s32",
+    "vusdot_laneq_s32",
+    "vusdotq_laneq_s32",
+    "vusdotq_laneq_s32",
+    "vusdot_s32",
+    "vusdotq_s32",
+    "vusmmlaq_s32",
+    "vuzp_f16",
+    "vuzpq_f16",
+    "vuzp_f32",
+    "vuzp_s32",
+    "vuzp_u32",
+    "vuzpq_f32",
+    "vuzp_s8",
+    "vuzpq_s8",
+    "vuzp_s16",
+    "vuzpq_s16",
+    "vuzpq_s32",
+    "vuzp_u8",
+    "vuzpq_u8",
+    "vuzp_u16",
+    "vuzpq_u16",
+    "vuzpq_u32",
+    "vuzp_p8",
+    "vuzpq_p8",
+    "vuzp_p16",
+    "vuzpq_p16",
+    "vzip_f16",
+    "vzipq_f16",
+    "vzip_f32",
+    "vzip_s32",
+    "vzip_u32",
+    "vzip_s8",
+    "vzip_s16",
+    "vzip_u8",
+    "vzip_u16",
+    "vzip_p8",
+    "vzip_p16",
+    "vzipq_f32",
+    "vzipq_s8",
+    "vzipq_s16",
+    "vzipq_s32",
+    "vzipq_u8",
+    "vzipq_u16",
+    "vzipq_u32",
+    "vzipq_p8",
+    "vzipq_p16",
+    "__rndr",
+    "__rndrrs",
+];

From d3455edde4817dcf0265d356ab1652c2c5168459 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 15:53:53 +0000
Subject: [PATCH 228/326] gen-arm: add `generate_load_store_tests`

Instead of generating load/store tests based on the input filename -
which no longer works given the expected input file structure of
`stdarch-gen-arm` - add a simple global context option that SVE specs can
set.
---
 crates/stdarch-gen-arm/src/context.rs | 4 ++++
 crates/stdarch-gen-arm/src/main.rs    | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/crates/stdarch-gen-arm/src/context.rs b/crates/stdarch-gen-arm/src/context.rs
index 9b8eb8e8b9..4d02a82b89 100644
--- a/crates/stdarch-gen-arm/src/context.rs
+++ b/crates/stdarch-gen-arm/src/context.rs
@@ -43,6 +43,10 @@ pub struct GlobalContext {
     /// Should all LLVM wrappers convert their arguments to a signed type
     #[serde(default)]
     pub auto_llvm_sign_conversion: bool,
+
+    /// Should SVE load/store tests be generated?
+    #[serde(default)]
+    pub generate_load_store_tests: bool,
 }
 
 /// Context of an intrinsic group
diff --git a/crates/stdarch-gen-arm/src/main.rs b/crates/stdarch-gen-arm/src/main.rs
index e14e278248..b7e2aa416f 100644
--- a/crates/stdarch-gen-arm/src/main.rs
+++ b/crates/stdarch-gen-arm/src/main.rs
@@ -54,7 +54,7 @@ fn main() -> Result<(), String> {
                     vv.into_iter().flatten().collect_vec()
                 })?;
 
-            if filepath.ends_with("sve.spec.yml") || filepath.ends_with("sve2.spec.yml") {
+            if input.ctx.generate_load_store_tests {
                 let loads = intrinsics.iter()
                     .filter_map(|i| {
                         if matches!(i.test, Test::Load(..)) {

From 3a51a2c047bbc2d4a41ce12e82334718315ff67a Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Sat, 28 Feb 2026 18:00:16 +0000
Subject: [PATCH 229/326] gen-arm: remove `SvUndef`

The `SvUndef` expression is no longer necessary as a
`core::intrinsics::scalable::sve_undef` intrinsic has been introduced
to produce an undefined SVE vector, used by `svundef*` intrinsics. Other
intrinsics that used `SvUndef` now use the `svundef*` intrinsics.
---
 crates/stdarch-gen-arm/README.md         |  3 ---
 crates/stdarch-gen-arm/src/expression.rs | 12 ++----------
 2 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/crates/stdarch-gen-arm/README.md b/crates/stdarch-gen-arm/README.md
index 64f1183f1d..970721681c 100644
--- a/crates/stdarch-gen-arm/README.md
+++ b/crates/stdarch-gen-arm/README.md
@@ -205,9 +205,6 @@ MatchKind:
 - `Array`
     - An array of expressions
     - Usage: `Array: [<expression>, ...]`
-- `SvUndef`
-    - Returns the LLVM `undef` symbol
-    - Usage: `SvUndef`
 - `Multiply`
     - Simply `*`
     - Usage: `Multiply: [<expression>, <expression>]`
diff --git a/crates/stdarch-gen-arm/src/expression.rs b/crates/stdarch-gen-arm/src/expression.rs
index bf48f0dab7..0b6ffef9d8 100644
--- a/crates/stdarch-gen-arm/src/expression.rs
+++ b/crates/stdarch-gen-arm/src/expression.rs
@@ -143,8 +143,6 @@ pub enum Expression {
     LLVMLink(LLVMLink),
     /// Casts the given expression to the specified (unchecked) type
     CastAs(Box<Expression>, String),
-    /// Returns the LLVM `undef` symbol
-    SvUndef,
     /// Multiplication
     Multiply(Box<Expression>, Box<Expression>),
     /// Xor
@@ -295,7 +293,7 @@ impl Expression {
     ///  - An unnecessary `unsafe` is a warning, made into an error by the CI's `-D warnings`.
     ///
     /// This **panics** if it encounters an expression that shouldn't appear in a safe function at
-    /// all (such as `SvUndef`).
+    /// all.
     pub fn requires_unsafe_wrapper(&self, ctx_fn: &str) -> bool {
         match self {
             // The call will need to be unsafe, but the declaration does not.
@@ -347,9 +345,6 @@ impl Expression {
             },
             // We only use macros to check const generics (using static assertions).
             Self::MacroCall(_name, _args) => false,
-            // Materialising uninitialised values is always unsafe, and we avoid it in safe
-            // functions.
-            Self::SvUndef => panic!("Refusing to wrap unsafe SvUndef in safe function '{ctx_fn}'."),
             // Variants that aren't tokenised. We shouldn't encounter these here.
             Self::MatchKind(..) => {
                 unimplemented!("The unsafety of {self:?} cannot be determined in '{ctx_fn}'.")
@@ -390,9 +385,7 @@ impl FromStr for Expression {
         static MACRO_RE: LazyLock<Regex> =
             LazyLock::new(|| Regex::new(r"^(?P<name>[\w\d_]+)!\((?P<ex>.*?)\);?$").unwrap());
 
-        if s == "SvUndef" {
-            Ok(Expression::SvUndef)
-        } else if MACRO_RE.is_match(s) {
+        if MACRO_RE.is_match(s) {
             let c = MACRO_RE.captures(s).unwrap();
             let ex = c["ex"].to_string();
             let _: TokenStream = ex
@@ -533,7 +526,6 @@ impl ToTokens for Expression {
                 let ty: TokenStream = ty.parse().expect("invalid syntax");
                 tokens.append_all(quote! { #ex as #ty })
             }
-            Self::SvUndef => tokens.append_all(quote! { simd_reinterpret(()) }),
             Self::Multiply(lhs, rhs) => tokens.append_all(quote! { #lhs * #rhs }),
             Self::Xor(lhs, rhs) => tokens.append_all(quote! { #lhs ^ #rhs }),
             Self::Type(ty) => ty.to_tokens(tokens),

From a2f1fd44078420f1cb4fed361a0824f5a4294901 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 15:53:53 +0000
Subject: [PATCH 230/326] gen-arm: s/simd_reinterpret/transmute_unchecked

`simd_reinterpret` was expected to be used when it was added as
`transmute_unchecked` requires `Sized`, but scalable vectors are now
`Sized` so `transmute_unchecked` can be used and `simd_reinterpret` was
not added in rust-lang/rust#143924.
---
 crates/stdarch-gen-arm/src/typekinds.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/stdarch-gen-arm/src/typekinds.rs b/crates/stdarch-gen-arm/src/typekinds.rs
index bd47ff2bd1..c3aa22294d 100644
--- a/crates/stdarch-gen-arm/src/typekinds.rs
+++ b/crates/stdarch-gen-arm/src/typekinds.rs
@@ -289,9 +289,9 @@ impl TypeKind {
                     (
                         BaseType::Sized(Float | Int | UInt, _),
                         BaseType::Sized(Float | Int | UInt, _),
-                    ) => Some(FnCall::new_expression(
+                    ) => Some(FnCall::new_unsafe_expression(
                         // Conversions between float and (u)int, or where the lane size changes.
-                        "simd_reinterpret".parse().unwrap(),
+                        "transmute_unchecked".parse().unwrap(),
                         vec![expr.into()],
                     )),
                     _ => None,

From 6fae36bd37fdb1910996d911e32abc15a43beb66 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 15:53:53 +0000
Subject: [PATCH 231/326] gen-arm: `auto-llvm-sign-conversion` not for `into`

Matching the current behaviour for arguments, `auto_llvm_sign_conversion`
should only be required for `as_unsigned` conversions, not `into`
conversions.
---
 crates/stdarch-gen-arm/src/intrinsic.rs | 33 ++++++++++++-------------
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index ce427d54b3..e20ab6779c 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -647,27 +647,26 @@ impl LLVMLink {
             })
             .try_collect()?;
 
-        let return_type_conversion = if !ctx.global.auto_llvm_sign_conversion {
-            None
-        } else {
-            self.signature
-                .as_ref()
-                .and_then(|sig| sig.return_type.as_ref())
-                .and_then(|ty| {
-                    if let Some(Sized(Bool, bitsize)) = ty.base_type() {
-                        (*bitsize != 8).then_some(Bool)
-                    } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() {
-                        Some(UInt)
-                    } else {
-                        None
-                    }
-                })
-        };
+        let return_type_conversion = self
+            .signature
+            .as_ref()
+            .and_then(|sig| sig.return_type.as_ref())
+            .and_then(|ty| {
+                if let Some(Sized(Bool, bitsize)) = ty.base_type() {
+                    (*bitsize != 8).then_some(Bool)
+                } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() {
+                    Some(UInt)
+                } else {
+                    None
+                }
+            });
 
         let fn_call = Expression::FnCall(fn_call);
         match return_type_conversion {
             Some(Bool) => Ok(convert("into", fn_call)),
-            Some(UInt) => Ok(convert("as_unsigned", fn_call)),
+            Some(UInt) if ctx.global.auto_llvm_sign_conversion => {
+                Ok(convert("as_unsigned", fn_call))
+            }
             _ => Ok(fn_call),
         }
     }

From ccf650718e6d060de4071a18d4c9aaa7d47b21bc Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 15:53:53 +0000
Subject: [PATCH 232/326] core_arch: add `static_assert_range`

This is a convenience macro used by the generated SVE intrinsics.

Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
Co-authored-by: Adam Gemmell <adam.gemmell@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
---
 crates/core_arch/src/macros.rs        | 16 ++++++++++++++++
 crates/stdarch-gen-arm/src/context.rs |  4 ++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 00e92428b3..83039bc65a 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -14,6 +14,22 @@ macro_rules! static_assert {
     };
 }
 
+#[allow(unused_macros)]
+macro_rules! static_assert_range {
+    ($imm:ident, $min:literal..=$max:literal) => {
+        static_assert!(
+            $min <= $imm && $imm <= $max,
+            concat!(
+                stringify!($imm),
+                " is not in range ",
+                stringify!($min),
+                "-",
+                stringify!($max),
+            )
+        )
+    };
+}
+
 #[allow(unused_macros)]
 macro_rules! static_assert_uimm_bits {
     ($imm:ident, $bits:expr) => {
diff --git a/crates/stdarch-gen-arm/src/context.rs b/crates/stdarch-gen-arm/src/context.rs
index 4d02a82b89..85342a1804 100644
--- a/crates/stdarch-gen-arm/src/context.rs
+++ b/crates/stdarch-gen-arm/src/context.rs
@@ -222,7 +222,7 @@ impl LocalContext {
             } => Ok(Expression::MacroCall(
                 "static_assert_range".to_string(),
                 format!(
-                    "{variable}, {min}, {max}",
+                    "{variable}, {min}..={max}",
                     min = range.start(),
                     max = range.end()
                 ),
@@ -250,7 +250,7 @@ impl LocalContext {
                             |bitsize| Ok(higher_limit / bitsize - 1))?;
                     Ok(Expression::MacroCall(
                         "static_assert_range".to_string(),
-                        format!("{variable}, 0, {max}"),
+                        format!("{variable}, 0..={max}"),
                     ))
                 } else {
                     Err(format!(

From 8b544efc563448824bf53cd8f72aa02b82b02cfc Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 15:53:53 +0000
Subject: [PATCH 233/326] core_arch: sve types

Add the SVE types (without any of the generated intrinsics) and empty
modules where the generated intrinsics will be. Enables the
`adt_const_params` crate feature that the generated intrinsics will use.

Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
Co-authored-by: Adam Gemmell <adam.gemmell@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
---
 crates/core_arch/src/aarch64/mod.rs           |   8 +
 crates/core_arch/src/aarch64/sve/generated.rs |   1 +
 crates/core_arch/src/aarch64/sve/mod.rs       | 379 ++++++++++++++++++
 .../core_arch/src/aarch64/sve2/generated.rs   |   1 +
 crates/core_arch/src/aarch64/sve2/mod.rs      |  17 +
 crates/core_arch/src/lib.rs                   |   3 +-
 6 files changed, 408 insertions(+), 1 deletion(-)
 create mode 100644 crates/core_arch/src/aarch64/sve/generated.rs
 create mode 100644 crates/core_arch/src/aarch64/sve/mod.rs
 create mode 100644 crates/core_arch/src/aarch64/sve2/generated.rs
 create mode 100644 crates/core_arch/src/aarch64/sve2/mod.rs

diff --git a/crates/core_arch/src/aarch64/mod.rs b/crates/core_arch/src/aarch64/mod.rs
index d7295659c3..9376e04b3b 100644
--- a/crates/core_arch/src/aarch64/mod.rs
+++ b/crates/core_arch/src/aarch64/mod.rs
@@ -25,6 +25,14 @@ mod neon;
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub use self::neon::*;
 
+mod sve;
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub use self::sve::*;
+
+mod sve2;
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub use self::sve2::*;
+
 mod prefetch;
 #[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
 pub use self::prefetch::*;
diff --git a/crates/core_arch/src/aarch64/sve/generated.rs b/crates/core_arch/src/aarch64/sve/generated.rs
new file mode 100644
index 0000000000..8b13789179
--- /dev/null
+++ b/crates/core_arch/src/aarch64/sve/generated.rs
@@ -0,0 +1 @@
+
diff --git a/crates/core_arch/src/aarch64/sve/mod.rs b/crates/core_arch/src/aarch64/sve/mod.rs
new file mode 100644
index 0000000000..a3f70ab61c
--- /dev/null
+++ b/crates/core_arch/src/aarch64/sve/mod.rs
@@ -0,0 +1,379 @@
+//! SVE intrinsics
+
+#![allow(non_camel_case_types)]
+
+// `generated.rs` has a `super::*` and this import is for that
+use crate::intrinsics::{simd::*, *};
+
+#[rustfmt::skip]
+mod generated;
+#[rustfmt::skip]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub use self::generated::*;
+
+use crate::{marker::ConstParamTy, mem::transmute};
+
+pub(super) trait AsUnsigned {
+    type Unsigned;
+    unsafe fn as_unsigned(self) -> Self::Unsigned;
+}
+
+pub(super) trait AsSigned {
+    type Signed;
+    unsafe fn as_signed(self) -> Self::Signed;
+}
+
+/// Same as `Into` but with into being unsafe so that it can have the required `target_feature`
+pub(super) trait SveInto<T>: Sized {
+    unsafe fn sve_into(self) -> T;
+}
+
+macro_rules! impl_sve_type {
+    ($(($v:vis, $elem_type:ty, $name:ident, $elt:literal))*) => ($(
+        #[doc = concat!("Scalable vector of type ", stringify!($elem_type))]
+        #[derive(Clone, Copy, Debug)]
+        #[rustc_scalable_vector($elt)]
+        #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+        $v struct $name($elem_type);
+    )*)
+}
+
+macro_rules! impl_sve_tuple_type {
+    ($(($v:vis, $vec_type:ty, $elt:tt, $name:ident))*) => ($(
+        impl_sve_tuple_type!(@ ($v, $vec_type, $elt, $name));
+    )*);
+    (@ ($v:vis, $vec_type:ty, 2, $name:ident)) => (
+        #[doc = concat!("Two-element tuple of scalable vectors of type ", stringify!($vec_type))]
+        #[derive(Clone, Copy, Debug)]
+        #[rustc_scalable_vector]
+        #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+        $v struct $name($vec_type, $vec_type);
+    );
+    (@ ($v:vis, $vec_type:ty, 3, $name:ident)) => (
+        #[doc = concat!("Three-element tuple of scalable vectors of type ", stringify!($vec_type))]
+        #[derive(Clone, Copy, Debug)]
+        #[rustc_scalable_vector]
+        #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+        $v struct $name($vec_type, $vec_type, $vec_type);
+    );
+    (@ ($v:vis, $vec_type:ty, 4, $name:ident)) => (
+        #[doc = concat!("Four-element tuple of scalable vectors of type ", stringify!($vec_type))]
+        #[derive(Clone, Copy, Debug)]
+        #[rustc_scalable_vector]
+        #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+        $v struct $name($vec_type, $vec_type, $vec_type, $vec_type);
+    );
+}
+
+macro_rules! impl_sign_conversions_sv {
+    ($(($signed:ty, $unsigned:ty))*) => ($(
+        impl AsUnsigned for $signed {
+            type Unsigned = $unsigned;
+
+            #[inline]
+            #[target_feature(enable = "sve")]
+            unsafe fn as_unsigned(self) -> $unsigned {
+                transmute_unchecked(self)
+            }
+        }
+
+        impl AsSigned for $unsigned {
+            type Signed = $signed;
+
+            #[inline]
+            #[target_feature(enable = "sve")]
+            unsafe fn as_signed(self) -> $signed {
+                transmute_unchecked(self)
+            }
+        }
+    )*)
+}
+
+macro_rules! impl_sign_conversions {
+    ($(($signed:ty, $unsigned:ty))*) => ($(
+        impl AsUnsigned for $signed {
+            type Unsigned = $unsigned;
+
+            #[inline]
+            #[target_feature(enable = "sve")]
+            unsafe fn as_unsigned(self) -> $unsigned {
+                transmute(self)
+            }
+        }
+
+        impl AsSigned for $unsigned {
+            type Signed = $signed;
+
+            #[inline]
+            #[target_feature(enable = "sve")]
+            unsafe fn as_signed(self) -> $signed {
+                transmute(self)
+            }
+        }
+    )*)
+}
+
+/// LLVM requires the predicate lane count to be the same as the lane count
+/// it's working with. However the ACLE only defines one bool type and the
+/// instruction set doesn't have this distinction. As a result we have to
+/// create these internal types so we can match the LLVM signature. Each of
+/// these internal types can be converted to the public `svbool_t` type and
+/// the `svbool_t` type can be converted into these.
+macro_rules! impl_internal_sve_predicate {
+    ($(($name:ident, $elt:literal))*) => ($(
+        impl_sve_type! {
+            (pub(super), bool, $name, $elt)
+        }
+
+        impl SveInto<svbool_t> for $name {
+            #[inline]
+            #[target_feature(enable = "sve")]
+            unsafe fn sve_into(self) -> svbool_t {
+                #[allow(improper_ctypes)]
+                unsafe extern "C" {
+                    #[cfg_attr(
+                        target_arch = "aarch64",
+                        link_name = concat!("llvm.aarch64.sve.convert.to.svbool.nxv", $elt, "i1")
+                    )]
+                    fn convert_to_svbool(b: $name) -> svbool_t;
+                }
+                unsafe { convert_to_svbool(self) }
+            }
+        }
+
+        #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+        impl SveInto<$name> for svbool_t {
+            #[inline]
+            #[target_feature(enable = "sve")]
+            unsafe fn sve_into(self) -> $name {
+                #[allow(improper_ctypes)]
+                unsafe extern "C" {
+                    #[cfg_attr(
+                        target_arch = "aarch64",
+                        link_name = concat!("llvm.aarch64.sve.convert.from.svbool.nxv", $elt, "i1")
+                    )]
+                    fn convert_from_svbool(b: svbool_t) -> $name;
+                }
+                unsafe { convert_from_svbool(self) }
+            }
+        }
+    )*)
+}
+
+impl_sve_type! {
+    (pub, bool, svbool_t, 16)
+
+    (pub, i8, svint8_t, 16)
+    (pub, u8, svuint8_t, 16)
+
+    (pub, i16, svint16_t, 8)
+    (pub, u16, svuint16_t, 8)
+    (pub, f32, svfloat32_t, 4)
+    (pub, i32, svint32_t, 4)
+    (pub, u32, svuint32_t, 4)
+    (pub, f64, svfloat64_t, 2)
+    (pub, i64, svint64_t, 2)
+    (pub, u64, svuint64_t, 2)
+
+    // Internal types:
+    (pub(super), i8, nxv2i8, 2)
+    (pub(super), i8, nxv4i8, 4)
+    (pub(super), i8, nxv8i8, 8)
+
+    (pub(super), i16, nxv2i16, 2)
+    (pub(super), i16, nxv4i16, 4)
+
+    (pub(super), i32, nxv2i32, 2)
+
+    (pub(super), u8, nxv2u8, 2)
+    (pub(super), u8, nxv4u8, 4)
+    (pub(super), u8, nxv8u8, 8)
+
+    (pub(super), u16, nxv2u16, 2)
+    (pub(super), u16, nxv4u16, 4)
+
+    (pub(super), u32, nxv2u32, 2)
+}
+
+impl_sve_tuple_type! {
+    (pub, svint8_t, 2, svint8x2_t)
+    (pub, svuint8_t, 2, svuint8x2_t)
+    (pub, svint16_t, 2, svint16x2_t)
+    (pub, svuint16_t, 2, svuint16x2_t)
+    (pub, svfloat32_t, 2, svfloat32x2_t)
+    (pub, svint32_t, 2, svint32x2_t)
+    (pub, svuint32_t, 2, svuint32x2_t)
+    (pub, svfloat64_t, 2, svfloat64x2_t)
+    (pub, svint64_t, 2, svint64x2_t)
+    (pub, svuint64_t, 2, svuint64x2_t)
+
+    (pub, svint8_t, 3, svint8x3_t)
+    (pub, svuint8_t, 3, svuint8x3_t)
+    (pub, svint16_t, 3, svint16x3_t)
+    (pub, svuint16_t, 3, svuint16x3_t)
+    (pub, svfloat32_t, 3, svfloat32x3_t)
+    (pub, svint32_t, 3, svint32x3_t)
+    (pub, svuint32_t, 3, svuint32x3_t)
+    (pub, svfloat64_t, 3, svfloat64x3_t)
+    (pub, svint64_t, 3, svint64x3_t)
+    (pub, svuint64_t, 3, svuint64x3_t)
+
+    (pub, svint8_t, 4, svint8x4_t)
+    (pub, svuint8_t, 4, svuint8x4_t)
+    (pub, svint16_t, 4, svint16x4_t)
+    (pub, svuint16_t, 4, svuint16x4_t)
+    (pub, svfloat32_t, 4, svfloat32x4_t)
+    (pub, svint32_t, 4, svint32x4_t)
+    (pub, svuint32_t, 4, svuint32x4_t)
+    (pub, svfloat64_t, 4, svfloat64x4_t)
+    (pub, svint64_t, 4, svint64x4_t)
+    (pub, svuint64_t, 4, svuint64x4_t)
+}
+
+impl_sign_conversions! {
+    (i8, u8)
+    (i16, u16)
+    (i32, u32)
+    (i64, u64)
+    (*const i8, *const u8)
+    (*const i16, *const u16)
+    (*const i32, *const u32)
+    (*const i64, *const u64)
+    (*mut i8, *mut u8)
+    (*mut i16, *mut u16)
+    (*mut i32, *mut u32)
+    (*mut i64, *mut u64)
+}
+
+impl_sign_conversions_sv! {
+    (svint8_t, svuint8_t)
+    (svint16_t, svuint16_t)
+    (svint32_t, svuint32_t)
+    (svint64_t, svuint64_t)
+
+    (svint8x2_t, svuint8x2_t)
+    (svint16x2_t, svuint16x2_t)
+    (svint32x2_t, svuint32x2_t)
+    (svint64x2_t, svuint64x2_t)
+
+    (svint8x3_t, svuint8x3_t)
+    (svint16x3_t, svuint16x3_t)
+    (svint32x3_t, svuint32x3_t)
+    (svint64x3_t, svuint64x3_t)
+
+    (svint8x4_t, svuint8x4_t)
+    (svint16x4_t, svuint16x4_t)
+    (svint32x4_t, svuint32x4_t)
+    (svint64x4_t, svuint64x4_t)
+
+    // Internal types:
+    (nxv2i8, nxv2u8)
+    (nxv4i8, nxv4u8)
+    (nxv8i8, nxv8u8)
+
+    (nxv2i16, nxv2u16)
+    (nxv4i16, nxv4u16)
+
+    (nxv2i32, nxv2u32)
+}
+
+impl_internal_sve_predicate! {
+    (svbool2_t, 2)
+    (svbool4_t, 4)
+    (svbool8_t, 8)
+}
+
+/// Patterns returned by a `PTRUE`
+#[repr(i32)]
+#[allow(non_camel_case_types)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)]
+#[non_exhaustive]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub enum svpattern {
+    /// Activate the largest power-of-two number of elements that is less than the vector length
+    SV_POW2 = 0,
+    /// Activate the first element
+    SV_VL1 = 1,
+    /// Activate the first two elements
+    SV_VL2 = 2,
+    /// Activate the first three elements
+    SV_VL3 = 3,
+    /// Activate the first four elements
+    SV_VL4 = 4,
+    /// Activate the first five elements
+    SV_VL5 = 5,
+    /// Activate the first six elements
+    SV_VL6 = 6,
+    /// Activate the first seven elements
+    SV_VL7 = 7,
+    /// Activate the first eight elements
+    SV_VL8 = 8,
+    /// Activate the first sixteen elements
+    SV_VL16 = 9,
+    /// Activate the first thirty-two elements
+    SV_VL32 = 10,
+    /// Activate the first sixty-four elements
+    SV_VL64 = 11,
+    /// Activate the first one-hundred-and-twenty-eight elements
+    SV_VL128 = 12,
+    /// Activate the first two-hundred-and-fifty-six elements
+    SV_VL256 = 13,
+    /// Activate the largest multiple-of-four number of elements that is less than the vector length
+    SV_MUL4 = 29,
+    /// Activate the largest multiple-of-three number of elements that is less than the vector
+    /// length
+    SV_MUL3 = 30,
+    /// Activate all elements
+    SV_ALL = 31,
+}
+
+/// Addressing mode for prefetch intrinsics - allows the specification of the expected access
+/// kind (read or write), the cache level to load the data, the data retention policy
+/// (temporal or streaming)
+#[repr(i32)]
+#[allow(non_camel_case_types)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)]
+#[non_exhaustive]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub enum svprfop {
+    /// Temporal fetch of the addressed location for reading to the L1 cache (i.e. allocate in
+    /// cache normally)
+    SV_PLDL1KEEP = 0,
+    /// Streaming fetch of the addressed location for reading to the L1 cache (i.e. memory only
+    /// used once)
+    SV_PLDL1STRM = 1,
+    /// Temporal fetch of the addressed location for reading to the L2 cache (i.e. allocate in
+    /// cache normally)
+    SV_PLDL2KEEP = 2,
+    /// Streaming fetch of the addressed location for reading to the L2 cache (i.e. memory only
+    /// used once)
+    SV_PLDL2STRM = 3,
+    /// Temporal fetch of the addressed location for reading to the L3 cache (i.e. allocate in
+    /// cache normally)
+    SV_PLDL3KEEP = 4,
+    /// Streaming fetch of the addressed location for reading to the L3 cache (i.e. memory only
+    /// used once)
+    SV_PLDL3STRM = 5,
+    /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. allocate in
+    /// cache normally)
+    SV_PSTL1KEEP = 8,
+    /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. memory only
+    /// used once)
+    SV_PSTL1STRM = 9,
+    /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. allocate in
+    /// cache normally)
+    SV_PSTL2KEEP = 10,
+    /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. memory only
+    /// used once)
+    SV_PSTL2STRM = 11,
+    /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. allocate in
+    /// cache normally)
+    SV_PSTL3KEEP = 12,
+    /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. memory only
+    /// used once)
+    SV_PSTL3STRM = 13,
+}
+
+#[cfg(test)]
+#[path = "ld_st_tests_aarch64.rs"]
+mod ld_st_tests;
diff --git a/crates/core_arch/src/aarch64/sve2/generated.rs b/crates/core_arch/src/aarch64/sve2/generated.rs
new file mode 100644
index 0000000000..8b13789179
--- /dev/null
+++ b/crates/core_arch/src/aarch64/sve2/generated.rs
@@ -0,0 +1 @@
+
diff --git a/crates/core_arch/src/aarch64/sve2/mod.rs b/crates/core_arch/src/aarch64/sve2/mod.rs
new file mode 100644
index 0000000000..acf9070214
--- /dev/null
+++ b/crates/core_arch/src/aarch64/sve2/mod.rs
@@ -0,0 +1,17 @@
+//! SVE2 intrinsics
+
+#![allow(non_camel_case_types)]
+
+// `generated.rs` has a `super::*` and this import is for that
+use super::sve::*;
+use crate::intrinsics::*;
+
+#[rustfmt::skip]
+mod generated;
+#[rustfmt::skip]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub use self::generated::*;
+
+#[cfg(test)]
+#[path = "ld_st_tests_aarch64.rs"]
+mod ld_st_tests;
diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 9255994e5e..f2f19eba26 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -40,7 +40,8 @@
     const_cmp,
     const_eval_select,
     maybe_uninit_as_bytes,
-    movrs_target_feature
+    movrs_target_feature,
+    min_adt_const_params
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]

From f6adf6f891bded1c447231d6a930775dc041531c Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Fri, 16 Jan 2026 12:30:36 +0000
Subject: [PATCH 234/326] gen-arm: use `sve_into` instead of `into`

`Into::into` can't be used here because the implementations can't have
the required target feature, so `SveInto` needs to be introduced and
written by the generator
---
 crates/stdarch-gen-arm/src/intrinsic.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index e20ab6779c..18a638a039 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -630,7 +630,7 @@ impl LLVMLink {
 
                     match (scope, kind.base_type()) {
                         (Argument, Some(Sized(Bool, bitsize))) if *bitsize != 8 => {
-                            Ok(convert("into", arg))
+                            Ok(convert("sve_into", arg))
                         }
                         (Argument, Some(Sized(UInt, _) | Unsized(UInt))) => {
                             if ctx.global.auto_llvm_sign_conversion {
@@ -663,7 +663,7 @@ impl LLVMLink {
 
         let fn_call = Expression::FnCall(fn_call);
         match return_type_conversion {
-            Some(Bool) => Ok(convert("into", fn_call)),
+            Some(Bool) => Ok(convert("sve_into", fn_call)),
             Some(UInt) if ctx.global.auto_llvm_sign_conversion => {
                 Ok(convert("as_unsigned", fn_call))
             }

From 5d9c7cceece00919281182b6d90642167247be26 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Wed, 4 Mar 2026 14:16:40 +0000
Subject: [PATCH 235/326] gen-arm: correct renamed `from_exposed_addr` link

`core::ptr::from_exposed_addr` was renamed to
`core::ptr::with_exposed_provenance` and so this link needs updated.
---
 crates/stdarch-gen-arm/src/intrinsic.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index 18a638a039..5d38d45ca6 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -871,8 +871,8 @@ impl fmt::Display for UnsafetyComment {
             Self::NoProvenance(arg) => write!(
                 f,
                 "Addresses passed in `{arg}` lack provenance, so this is similar to using a \
-                `usize as ptr` cast (or [`core::ptr::from_exposed_addr`]) on each lane before \
-                using it."
+                `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane \
+                before  using it."
             ),
             Self::UnpredictableOnFault => write!(
                 f,

From 552a505e59c8fe84b348fba7f983e7ea42a5f099 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 15:53:53 +0000
Subject: [PATCH 236/326] gen-arm: add sve intrinsic definitions

Thousands of lines of SVE intrinsic definitions..

Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
Co-authored-by: Adam Gemmell <adam.gemmell@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
---
 .../stdarch-gen-arm/spec/sve/aarch64.spec.yml | 5199 +++++++++++++++++
 .../spec/sve2/aarch64.spec.yml                | 3196 ++++++++++
 2 files changed, 8395 insertions(+)
 create mode 100644 crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
 create mode 100644 crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml

diff --git a/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
new file mode 100644
index 0000000000..1fad8bb371
--- /dev/null
+++ b/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
@@ -0,0 +1,5199 @@
+arch_cfgs:
+  - arch_name: aarch64
+    target_feature: [sve]
+    llvm_prefix: llvm.aarch64.sve
+
+uses_neon_types: true
+auto_llvm_sign_conversion: true
+generate_load_store_tests: true
+
+# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]`
+sve-unstable: &sve-unstable
+  FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']]
+
+intrinsics:
+  - name: svacge[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Absolute compare greater than or equal to
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64]
+    assert_instr: [facge]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "facge.{sve_type}" }
+
+  - name: svacgt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Absolute compare greater than
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64]
+    assert_instr: [facgt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "facgt.{sve_type}" }
+
+  - name: svacle[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Absolute compare less than or equal to
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64]
+    assert_instr: [facge]
+    n_variant_op: op2
+    compose:
+      - FnCall: ["svacge_{type}", [$pg, $op2, $op1]]
+
+  - name: svaclt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Absolute compare less than
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64]
+    assert_instr: [facgt]
+    n_variant_op: op2
+    compose:
+      - FnCall: ["svacgt_{type}", [$pg, $op2, $op1]]
+
+  - name: svcadd[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Complex add with rotate
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }]
+    assert_instr: [[fcadd, "IMM_ROTATION = 90"]]
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink:
+          name: fcadd.{sve_type}
+          arguments:
+            - "pg: {predicate}"
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $IMM_ROTATION]]
+
+  - name: svcmla[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Complex multiply-add with rotate
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }]
+    assert_instr: [[fcmla, "IMM_ROTATION = 90"]]
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink:
+          name: fcmla.{sve_type}
+          arguments:
+            - "pg: {predicate}"
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $op3, $IMM_ROTATION]]
+
+  - name: svcmla_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Complex multiply-add with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32]
+    static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"]
+    constraints:
+      - variable: IMM_INDEX
+        range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] }
+      - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }
+    assert_instr: [[fcmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: fcmla.lane.x.{sve_type}
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "imm_index: i32"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]]
+
+  - name: svadd[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Add
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind.f}add"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}add.{sve_type}" }
+
+  - name: svqsub[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating subtract
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.su}qsub"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qsub.x.{sve_type}" }
+
+  - name: svcnt[_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Count nonzero bits
+    arguments:
+      ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [f32, u32]
+      - [f64, u64]
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+      - [u8, u8]
+      - [u16, u16]
+      - [u32, u32]
+      - [u64, u64]
+    zeroing_method: { drop: inactive }
+    assert_instr: [cnt]
+    compose:
+      - LLVMLink: { name: "cnt.{sve_type[0]}" }
+
+  - name: svcls[_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Count leading sign bits
+    arguments:
+      ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[i8, u8], [i16, u16], [i32, u32], [i64, u64]]
+    zeroing_method: { drop: inactive }
+    assert_instr: [cls]
+    compose:
+      - LLVMLink: { name: "cls.{sve_type[0]}" }
+
+  - name: svclz[_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Count leading zero bits
+    arguments:
+      ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+      - [u8, u8]
+      - [u16, u16]
+      - [u32, u32]
+      - [u64, u64]
+    zeroing_method: { drop: inactive }
+    assert_instr: [clz]
+    compose:
+      - LLVMLink: { name: "clz.{sve_type[0]}" }
+
+  - name: svext{size_literal[1]}[_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    substitutions:
+      sign_or_zero:
+        match_kind: "{type[0]}"
+        default: Sign
+        unsigned: Zero
+      kind_literal: { match_kind: "{type[0]}", default: s, unsigned: u }
+    doc: "{sign_or_zero}-extend the low {size[1]} bits"
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {predicate[0]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    zeroing_method: { drop: inactive }
+    assert_instr: ["{type_kind[0].su}xt{size_literal[1]}"]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}xt{size_literal[1]}.{sve_type[0]}"
+
+  - name: svsqrt[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Square root
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { drop: inactive }
+    assert_instr: [fsqrt]
+    compose:
+      - LLVMLink: { name: "fsqrt.{sve_type}" }
+
+  - name: svcmpeq[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare equal to
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [{ float: fcmeq, default: cmpeq }]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}cmpeq.{sve_type}" }
+
+  - name: svcmpeq_wide[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Compare equal to
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{predicate[0]}"
+    types:
+      - [[i8, i16, i32], i64]
+    assert_instr: [cmpeq]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "cmpeq.wide.{sve_type[0]}" }
+
+  - name: svcmpge[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare greater than or equal to
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }]
+    n_variant_op: op2
+    compose:
+      - MatchKind:
+          - "{type}"
+          - default:
+              LLVMLink: { name: "{type_kind.f}cmpge.{sve_type}" }
+            unsigned:
+              LLVMLink: { name: "cmphs.{sve_type}" }
+
+  - name: svcmpge_wide[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Compare greater than or equal to
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{predicate[0]}"
+    n_variant_op: op2
+    types:
+      - [[i8, i16, i32], i64]
+      - [[u8, u16, u32], u64]
+    assert_instr: [{ default: cmpge, unsigned: cmphs }]
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default:
+              LLVMLink: { name: "cmpge.wide.{sve_type[0]}" }
+            unsigned:
+              LLVMLink: { name: "cmphs.wide.{sve_type[0]}" }
+
+  - name: svcmpgt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare greater than
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }]
+    n_variant_op: op2
+    compose:
+      - MatchKind:
+          - "{type}"
+          - default:
+              LLVMLink: { name: "{type_kind.f}cmpgt.{sve_type}" }
+            unsigned:
+              LLVMLink: { name: "cmphi.{sve_type}" }
+
+  - name: svcmpgt_wide[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Compare greater than
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{predicate[0]}"
+    types:
+      - [[i8, i16, i32], i64]
+      - [[u8, u16, u32], u64]
+    assert_instr: [{ default: cmpgt, unsigned: cmphi }]
+    n_variant_op: op2
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default:
+              LLVMLink: { name: "cmpgt.wide.{sve_type[0]}" }
+            unsigned:
+              LLVMLink: { name: "cmphi.wide.{sve_type[0]}" }
+
+  - name: svcmple[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare less than or equal to
+    arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "svbool_t"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }]
+    n_variant_op: op2
+    compose:
+      - FnCall: ["svcmpge_{type}", [$pg, $op2, $op1]]
+
+  - name: svcmple_wide[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Compare less than or equal to
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{predicate[0]}"
+    types:
+      - [[i8, i16, i32], i64]
+      - [[u8, u16, u32], u64]
+    assert_instr: [{ default: cmple, unsigned: cmpls }]
+    n_variant_op: op2
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default:
+              LLVMLink: { name: "cmple.wide.{sve_type[0]}" }
+            unsigned:
+              LLVMLink: { name: "cmpls.wide.{sve_type[0]}" }
+
+  - name: svcmplt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare less than
+    arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "svbool_t"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }]
+    n_variant_op: op2
+    compose:
+      - FnCall: ["svcmpgt_{type}", [$pg, $op2, $op1]]
+
+  - name: svcmplt_wide[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Compare less than
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{predicate[0]}"
+    types:
+      - [[i8, i16, i32], i64]
+      - [[u8, u16, u32], u64]
+    assert_instr: [{ default: cmplt, unsigned: cmplo }]
+    n_variant_op: op2
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default:
+              LLVMLink: { name: "cmplt.wide.{sve_type[0]}" }
+            unsigned:
+              LLVMLink: { name: "cmplo.wide.{sve_type[0]}" }
+
+  - name: svcmpne[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare not equal to
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [{ float: fcmne, default: cmpne }]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}cmpne.{sve_type}" }
+
+  - name: svcmpne_wide[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Compare not equal to
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{predicate[0]}"
+    types: [[[i8, i16, i32], i64]]
+    assert_instr: [cmpne]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "cmpne.wide.{sve_type[0]}" }
+
+  - name: svcmpuo[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Compare unordered with
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [f32, f64]
+    assert_instr: [fcmuo]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "fcmpuo.{sve_type}" }
+
+  - name: svcnt{size_literal}
+    attr: [*sve-unstable]
+    doc: Count the number of {size}-bit elements in a vector
+    arguments: []
+    return_type: u64
+    types: [i8, i16, i32, i64]
+    assert_instr:
+      - default: { byte: rdvl, halfword: cnth, default: cntw, doubleword: cntd }
+    compose:
+      - FnCall: ["svcnt{size_literal}_pat", [], ["{{ svpattern::SV_ALL }}"]]
+
+  - name: svcnt{size_literal}_pat
+    attr: [*sve-unstable]
+    doc: Count the number of {size}-bit elements in a vector
+    arguments: []
+    static_defs: ["const PATTERN: svpattern"]
+    return_type: u64
+    assert_instr:
+      - [rdvl, "PATTERN = {{ svpattern::SV_ALL }}"]
+      - ["cnt{size_literal}", "PATTERN = {{ svpattern::SV_MUL4 }}"]
+    types: [i8]
+    compose:
+      - LLVMLink:
+          name: cnt{size_literal}
+          arguments: ["pattern: svpattern"]
+      - FnCall: ["{llvm_link}", [$PATTERN]]
+
+  - name: svcnt{size_literal}_pat
+    attr: [*sve-unstable]
+    doc: Count the number of {size}-bit elements in a vector
+    arguments: []
+    static_defs: ["const PATTERN: svpattern"]
+    return_type: u64
+    assert_instr: [["cnt{size_literal}", "PATTERN = {{ svpattern::SV_ALL }}"]]
+    types: [i16, i32, i64]
+    compose:
+      - LLVMLink:
+          name: cnt{size_literal}
+          arguments: ["pattern: svpattern"]
+      - FnCall: ["{llvm_link}", [$PATTERN]]
+
+  - name: svlen[_{type}]
+    attr: [*sve-unstable]
+    doc: Count the number of elements in a full vector
+    arguments: ["_op: {sve_type}"]
+    return_type: "u64"
+    types: [i8, u8, i16, u16, i32, u32, f32, i64, u64, f64]
+    assert_instr: [{ default: { default: "cnt{size_literal}", byte: rdvl } }]
+    compose:
+      - FnCall: ["svcnt{size_literal}", []]
+
+  - name: svdup[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a scalar value
+    arguments: ["op: {type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [mov]
+    compose:
+      - LLVMLink: { name: "dup.x.{sve_type}" }
+
+  - name: svdup[_n]_{type}{_mxz}
+    attr: [*sve-unstable]
+    doc: Broadcast a scalar value
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { drop: inactive }
+    assert_instr: [mov]
+    compose:
+      - LLVMLink: { name: "dup.{sve_type}" }
+
+  - name: svdup[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a scalar value
+    arguments: ["op: bool"]
+    return_type: "{predicate}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [sbfx, whilelo]
+    compose:
+      - LLVMLink: { name: "dup.x.{sve_type}" }
+
+  - name: svdup_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Broadcast a scalar value
+    arguments: ["data: {sve_type[0]}", "index: {type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [f32, u32]
+      - [f64, u64]
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+      - [u8, u8]
+      - [u16, u16]
+      - [u32, u32]
+      - [u64, u64]
+    assert_instr: [tbl]
+    compose:
+      - FnCall:
+          - svtbl_{type[0]}
+          - - $data
+            - FnCall: ["svdup_n_{type[1]}", [$index]]
+
+  - name: svdupq_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    arguments: ["data: {sve_type}", "index: u64"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [tbl]
+    compose:
+      - LLVMLink: { name: "dupq.lane.{sve_type}" }
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    arguments:
+      - "x0: {type}"
+      - "x1: {type}"
+      - "x2: {type}"
+      - "x3: {type}"
+      - "x4: {type}"
+      - "x5: {type}"
+      - "x6: {type}"
+      - "x7: {type}"
+      - "x8: {type}"
+      - "x9: {type}"
+      - "x10: {type}"
+      - "x11: {type}"
+      - "x12: {type}"
+      - "x13: {type}"
+      - "x14: {type}"
+      - "x15: {type}"
+    return_type: "{sve_type}"
+    types: [i8, u8]
+    assert_instr: []
+    compose:
+      - LLVMLink:
+          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
+      - Let:
+          - op
+          - FnCall:
+              - "{llvm_link}"
+              - - FnCall: ["svundef_{type}", [], [], true]
+                - FnCall:
+                    - "crate::mem::transmute"
+                    - - - $x0
+                        - $x1
+                        - $x2
+                        - $x3
+                        - $x4
+                        - $x5
+                        - $x6
+                        - $x7
+                        - $x8
+                        - $x9
+                        - $x10
+                        - $x11
+                        - $x12
+                        - $x13
+                        - $x14
+                        - $x15
+                - 0
+      - FnCall: ["svdupq_lane_{type}", [$op, 0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    types: [b8]
+    arguments:
+      - "x0: bool"
+      - "x1: bool"
+      - "x2: bool"
+      - "x3: bool"
+      - "x4: bool"
+      - "x5: bool"
+      - "x6: bool"
+      - "x7: bool"
+      - "x8: bool"
+      - "x9: bool"
+      - "x10: bool"
+      - "x11: bool"
+      - "x12: bool"
+      - "x13: bool"
+      - "x14: bool"
+      - "x15: bool"
+    return_type: "svbool_t"
+    assert_instr: []
+    compose:
+      - Let:
+          - op1
+          - FnCall:
+              - svdupq_n_s8
+              - - CastAs: [$x0, i8]
+                - CastAs: [$x1, i8]
+                - CastAs: [$x2, i8]
+                - CastAs: [$x3, i8]
+                - CastAs: [$x4, i8]
+                - CastAs: [$x5, i8]
+                - CastAs: [$x6, i8]
+                - CastAs: [$x7, i8]
+                - CastAs: [$x8, i8]
+                - CastAs: [$x9, i8]
+                - CastAs: [$x10, i8]
+                - CastAs: [$x11, i8]
+                - CastAs: [$x12, i8]
+                - CastAs: [$x13, i8]
+                - CastAs: [$x14, i8]
+                - CastAs: [$x15, i8]
+      - FnCall:
+          - svcmpne_wide_s8
+          - - FnCall: [svptrue_b8, []]
+            - $op1
+            - FnCall: [svdup_n_s64, [0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    arguments:
+      - "x0: {type}"
+      - "x1: {type}"
+      - "x2: {type}"
+      - "x3: {type}"
+      - "x4: {type}"
+      - "x5: {type}"
+      - "x6: {type}"
+      - "x7: {type}"
+    return_type: "{sve_type}"
+    types: [i16, u16]
+    assert_instr: []
+    compose:
+      - LLVMLink:
+          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
+      - Let:
+          - op
+          - FnCall:
+              - "{llvm_link}"
+              - - FnCall: ["svundef_{type}", [], [], true]
+                - FnCall:
+                    - "crate::mem::transmute"
+                    - - [$x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7]
+                - 0
+      - FnCall: ["svdupq_lane_{type}", [$op, 0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    types: [b16]
+    arguments:
+      - "x0: bool"
+      - "x1: bool"
+      - "x2: bool"
+      - "x3: bool"
+      - "x4: bool"
+      - "x5: bool"
+      - "x6: bool"
+      - "x7: bool"
+    return_type: svbool_t
+    assert_instr: []
+    compose:
+      - Let:
+          - op1
+          - FnCall:
+              - svdupq_n_s16
+              - - CastAs: [$x0, i16]
+                - CastAs: [$x1, i16]
+                - CastAs: [$x2, i16]
+                - CastAs: [$x3, i16]
+                - CastAs: [$x4, i16]
+                - CastAs: [$x5, i16]
+                - CastAs: [$x6, i16]
+                - CastAs: [$x7, i16]
+      - FnCall:
+          - svcmpne_wide_s16
+          - - FnCall: [svptrue_b16, []]
+            - $op1
+            - FnCall: [svdup_n_s64, [0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    arguments: ["x0: {type}", "x1: {type}", "x2: {type}", "x3: {type}"]
+    return_type: "{sve_type}"
+    types: [f32, i32, u32]
+    assert_instr: []
+    compose:
+      - LLVMLink:
+          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
+      - Let:
+          - op
+          - FnCall:
+              - "{llvm_link}"
+              - - FnCall: ["svundef_{type}", [], [], true]
+                - FnCall: ["crate::mem::transmute", [[$x0, $x1, $x2, $x3]]]
+                - 0
+      - FnCall: ["svdupq_lane_{type}", [$op, 0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    types: [b32]
+    arguments: ["x0: bool", "x1: bool", "x2: bool", "x3: bool"]
+    return_type: "svbool_t"
+    assert_instr: []
+    compose:
+      - Let:
+          - op1
+          - FnCall:
+              - svdupq_n_s32
+              - - CastAs: [$x0, i32]
+                - CastAs: [$x1, i32]
+                - CastAs: [$x2, i32]
+                - CastAs: [$x3, i32]
+      - FnCall:
+          - svcmpne_wide_s32
+          - - FnCall: [svptrue_b32, []]
+            - $op1
+            - FnCall: [svdup_n_s64, [0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    arguments: ["x0: {type}", "x1: {type}"]
+    return_type: "{sve_type}"
+    types: [f64, i64, u64]
+    assert_instr: []
+    compose:
+      - LLVMLink:
+          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
+      - Let:
+          - op
+          - FnCall:
+              - "{llvm_link}"
+              - - FnCall: ["svundef_{type}", [], [], true]
+                - FnCall: ["crate::mem::transmute", [[$x0, $x1]]]
+                - 0
+      - FnCall: ["svdupq_lane_{type}", [$op, 0]]
+
+  - name: svdupq[_n]_{type}
+    attr: [*sve-unstable]
+    doc: Broadcast a quadword of scalars
+    types: [b64]
+    arguments: ["x0: bool", "x1: bool"]
+    return_type: "svbool_t"
+    assert_instr: []
+    compose:
+      - Let:
+          - op1
+          - FnCall: [svdupq_n_s64, [CastAs: [$x0, i64], CastAs: [$x1, i64]]]
+      - FnCall:
+          - svcmpne_s64
+          - - FnCall: [svptrue_b64, []]
+            - $op1
+            - FnCall: [svdup_n_s64, [0]]
+
+  - name: svcreate2[_{type}]
+    attr: [*sve-unstable]
+    doc: Create a tuple of two vectors
+    arguments: ["x0: {sve_type}", "x1: {sve_type}"]
+    return_type: "{sve_type_x2}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create2", [$x0, $x1], [], true]
+
+  - name: svcreate3[_{type}]
+    attr: [*sve-unstable]
+    doc: Create a tuple of three vectors
+    arguments: ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}"]
+    return_type: "{sve_type_x3}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create3", [$x0, $x1, $x2], [], true]
+
+  - name: svcreate4[_{type}]
+    attr: [*sve-unstable]
+    doc: Create a tuple of four vectors
+    arguments:
+      ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}", "x3: {sve_type}"]
+    return_type: "{sve_type_x4}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create4", [$x0, $x1, $x2, $x3], [], true]
+
+  - name: svundef_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized vector
+    arguments: []
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["svdup_n_{type}", ["0"]]
+
+  - name: svundef_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized vector
+    arguments: []
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: []
+    compose:
+      - FnCall: ["svdup_n_{type}", ["0{type}"]]
+
+  - name: svundef2_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized tuple of two vectors
+    arguments: []
+    return_type: "{sve_type_x2}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall:
+        - "svcreate2_{type}"
+        - - FnCall: ["svdup_n_{type}", ["0"]]
+          - FnCall: ["svdup_n_{type}", ["0"]]
+
+  - name: svundef2_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized tuple of two vectors
+    arguments: []
+    return_type: "{sve_type_x2}"
+    types: [f32, f64]
+    assert_instr: []
+    compose:
+      - FnCall:
+        - "svcreate2_{type}"
+        - - FnCall: ["svdup_n_{type}", ["0{type}"]]
+          - FnCall: ["svdup_n_{type}", ["0{type}"]]
+
+  - name: svundef3_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized tuple of three vectors
+    arguments: []
+    return_type: "{sve_type_x3}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall:
+        - "svcreate3_{type}"
+        - - FnCall: ["svdup_n_{type}", ["0"]]
+          - FnCall: ["svdup_n_{type}", ["0"]]
+          - FnCall: ["svdup_n_{type}", ["0"]]
+
+  - name: svundef3_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized tuple of three vectors
+    arguments: []
+    return_type: "{sve_type_x3}"
+    types: [f32, f64]
+    assert_instr: []
+    compose:
+      - FnCall:
+        - "svcreate3_{type}"
+        - - FnCall: ["svdup_n_{type}", ["0{type}"]]
+          - FnCall: ["svdup_n_{type}", ["0{type}"]]
+          - FnCall: ["svdup_n_{type}", ["0{type}"]]
+
+  - name: svundef4_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized tuple of four vectors
+    arguments: []
+    return_type: "{sve_type_x4}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall:
+        - "svcreate4_{type}"
+        - - FnCall: ["svdup_n_{type}", ["0"]]
+          - FnCall: ["svdup_n_{type}", ["0"]]
+          - FnCall: ["svdup_n_{type}", ["0"]]
+          - FnCall: ["svdup_n_{type}", ["0"]]
+
+  - name: svundef4_{type}
+    attr: [*sve-unstable]
+    safety:
+      unsafe: [uninitialized]
+    doc: Create an uninitialized tuple of four vectors
+    arguments: []
+    return_type: "{sve_type_x4}"
+    types: [f32, f64]
+    assert_instr: []
+    compose:
+      - FnCall:
+        - "svcreate4_{type}"
+        - - FnCall: ["svdup_n_{type}", ["0{type}"]]
+          - FnCall: ["svdup_n_{type}", ["0{type}"]]
+          - FnCall: ["svdup_n_{type}", ["0{type}"]]
+          - FnCall: ["svdup_n_{type}", ["0{type}"]]
+
+  - name: svindex_{type}
+    attr: [*sve-unstable]
+    doc: Create linear series
+    arguments: ["base: {type}", "step: {type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [index]
+    compose:
+      - LLVMLink: { name: "index.{sve_type}" }
+
+  - name: svget2[_{type}]
+    attr: [*sve-unstable]
+    doc: Extract one vector from a tuple of two vectors
+    arguments: ["tuple: {sve_type_x2}"]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, range: [0, 1] }]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true]
+
+  - name: svget3[_{type}]
+    attr: [*sve-unstable]
+    doc: Extract one vector from a tuple of three vectors
+    arguments: ["tuple: {sve_type_x3}"]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, range: [0, 2] }]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true]
+
+  - name: svget4[_{type}]
+    attr: [*sve-unstable]
+    doc: Extract one vector from a tuple of four vectors
+    arguments: ["tuple: {sve_type_x4}"]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, range: [0, 3] }]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true]
+
+  - name: svset2[_{type}]
+    attr: [*sve-unstable]
+    doc: Change one vector in a tuple of two vectors
+    arguments: ["tuple: {sve_type_x2}", "x: {sve_type}"]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, range: [0, 1] }]
+    return_type: "{sve_type_x2}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true]
+
+  - name: svset3[_{type}]
+    attr: [*sve-unstable]
+    doc: Change one vector in a tuple of three vectors
+    arguments: ["tuple: {sve_type_x3}", "x: {sve_type}"]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, range: [0, 2] }]
+    return_type: "{sve_type_x3}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true]
+
+  - name: svset4[_{type}]
+    attr: [*sve-unstable]
+    doc: Change one vector in a tuple of four vectors
+    arguments: ["tuple: {sve_type_x4}", "x: {sve_type}"]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, range: [0, 3] }]
+    return_type: "{sve_type_x4}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: []
+    compose:
+      - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true]
+
+  - name: svzip1[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave elements from low halves of two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [zip1]
+    compose:
+      - LLVMLink: { name: "zip1.{sve_type}" }
+
+  - name: svzip1_{type}
+    attr: [*sve-unstable]
+    doc: Interleave elements from low halves of two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [zip1]
+    compose:
+      - LLVMLink: { name: "zip1.{sve_type}" }
+
+  - name: svzip1q[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave quadwords from low halves of two inputs
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [zip1]
+    compose:
+      - LLVMLink: { name: "zip1q.{sve_type}" }
+
+  - name: svzip2[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave elements from high halves of two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [zip2]
+    compose:
+      - LLVMLink: { name: "zip2.{sve_type}" }
+
+  - name: svzip2_{type}
+    attr: [*sve-unstable]
+    doc: Interleave elements from high halves of two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [zip2]
+    compose:
+      - LLVMLink: { name: "zip2.{sve_type}" }
+
+  - name: svzip2q[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave quadwords from high halves of two inputs
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [zip2]
+    compose:
+      - LLVMLink: { name: "zip2q.{sve_type}" }
+
+  - name: svuzp1[_{type}]
+    attr: [*sve-unstable]
+    doc: Concatenate even elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [uzp1]
+    compose:
+      - LLVMLink: { name: "uzp1.{sve_type}" }
+
+  - name: svuzp1_{type}
+    attr: [*sve-unstable]
+    doc: Concatenate even elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [uzp1]
+    compose:
+      - LLVMLink: { name: "uzp1.{sve_type}" }
+
+  - name: svuzp1q[_{type}]
+    attr: [*sve-unstable]
+    doc: Concatenate even quadwords from two inputs
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [uzp1]
+    compose:
+      - LLVMLink: { name: "uzp1q.{sve_type}" }
+
+  - name: svuzp2[_{type}]
+    attr: [*sve-unstable]
+    doc: Concatenate odd elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [uzp2]
+    compose:
+      - LLVMLink: { name: "uzp2.{sve_type}" }
+
+  - name: svuzp2_{type}
+    attr: [*sve-unstable]
+    doc: Concatenate odd elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [uzp2]
+    compose:
+      - LLVMLink: { name: "uzp2.{sve_type}" }
+
+  - name: svuzp2q[_{type}]
+    attr: [*sve-unstable]
+    doc: Concatenate odd quadwords from two inputs
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [uzp2]
+    compose:
+      - LLVMLink: { name: "uzp2q.{sve_type}" }
+
+  - name: svtrn1[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave even elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [trn1]
+    compose:
+      - LLVMLink: { name: "trn1.{sve_type}" }
+
+  - name: svtrn1_{type}
+    attr: [*sve-unstable]
+    doc: Interleave even elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [trn1]
+    compose:
+      - LLVMLink: { name: "trn1.{sve_type}" }
+
+  - name: svtrn1q[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave even quadwords from two inputs
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [trn1]
+    compose:
+      - LLVMLink: { name: "trn1q.{sve_type}" }
+
+  - name: svtrn2[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave odd elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [trn2]
+    compose:
+      - LLVMLink: { name: "trn2.{sve_type}" }
+
+  - name: svtrn2_{type}
+    attr: [*sve-unstable]
+    doc: Interleave odd elements from two inputs
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [trn2]
+    compose:
+      - LLVMLink: { name: "trn2.{sve_type}" }
+
+  - name: svtrn2q[_{type}]
+    attr: [*sve-unstable]
+    doc: Interleave odd quadwords from two inputs
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [trn2]
+    compose:
+      - LLVMLink: { name: "trn2q.{sve_type}" }
+
+  - name: svrev[_{type}]
+    attr: [*sve-unstable]
+    doc: Reverse all elements
+    arguments: ["op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [rev]
+    compose:
+      - LLVMLink: { name: "rev.{sve_type}" }
+
+  - name: svrev_{type}
+    attr: [*sve-unstable]
+    doc: Reverse all elements
+    arguments: ["op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [rev]
+    compose:
+      - LLVMLink: { name: "rev.{sve_type}" }
+
+  - name: svrevb[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reverse bytes within elements
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i16, i32, i64, u16, u32, u64]
+    zeroing_method: { drop: "inactive" }
+    assert_instr: [revb]
+    compose:
+      - LLVMLink: { name: "revb.{sve_type}" }
+
+  - name: svrevh[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reverse halfwords within elements
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i32, i64, u32, u64]
+    zeroing_method: { drop: "inactive" }
+    assert_instr: [revh]
+    compose:
+      - LLVMLink: { name: "revh.{sve_type}" }
+
+  - name: svrevw[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reverse words within elements
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i64, u64]
+    zeroing_method: { drop: "inactive" }
+    assert_instr: [revw]
+    compose:
+      - LLVMLink: { name: "revw.{sve_type}" }
+
+  - name: svrbit[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reverse bits
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { drop: "inactive" }
+    assert_instr: [rbit]
+    compose:
+      - LLVMLink: { name: "rbit.{sve_type}" }
+
+  - name: svext[_{type}]
+    attr: [*sve-unstable]
+    doc: Extract vector from pair of vectors
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, sve_max_elems_type: "{type}" }]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [[ext, "IMM3 = 1"]]
+    compose:
+      - LLVMLink:
+          name: ext.{sve_type}
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]]
+
+  - name: svsplice[_{type}]
+    attr: [*sve-unstable]
+    doc: Splice two vectors under predicate control
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [splice]
+    compose:
+      - LLVMLink: { name: "splice.{sve_type}" }
+
+  - name: svinsr[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Insert scalar in shifted vector
+    arguments: ["op1: {sve_type}", "op2: {type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [insr]
+    compose:
+      - LLVMLink: { name: "insr.{sve_type}" }
+
+  - name: svld1[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ld1.{sve_type}" }
+
+  - name: svld1_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svld1_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld1_gather_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["ld1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}"
+            doubleword:
+              LLVMLink:
+                name: "ld1.gather.index.{sve_type[1]}"
+
+  - name: svld1_gather_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["ld1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1]}"
+            doubleword:
+              LLVMLink:
+                name: "ld1.gather.{sve_type[1]}"
+
+  - name: svld1_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ld1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ld1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}"
+
+  - name: svld1_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ld1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svld1_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svld1_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ld1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svld1_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]]
+
+  - name: svld1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [i32, u32], i16]
+      - [[i64, u64], [i64, u64], [i16, i32]]
+    assert_instr: ["ld1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ld1.gather.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $indices]]
+
+  - name: svld1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [u32, i32], u16]
+      - [[i64, u64], [u64, i64], [u16, u32]]
+    assert_instr: ["ld1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ld1.gather.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $indices]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svld1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [i32, u32], [i8, i16]]
+      - [[i64, u64], [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ld1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ld1.gather.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]]
+
+  - name: svld1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [u32, i32], [u8, u16]]
+      - [[i64, u64], [u64, i64], [u8, u16, u32]]
+    assert_instr: ["ld1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ld1.gather.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ld1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]]
+
+  - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [u32, i32], [u8, u16]]
+      - [u64, [u64, i64], [u8, u16, u32]]
+    assert_instr: ["ld1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ld1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [u8, u16]]
+      - [u64, [i64, u64], [u8, u16, u32]]
+    assert_instr: ["ld1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], i16]
+      - [u64, [i64, u64], [i16, i32]]
+    assert_instr: ["ld1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+
+  - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], u16]
+      - [u64, [i64, u64], [u16, u32]]
+    assert_instr: ["ld1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+
+  - name: svldnt1[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ldnt1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ldnt1.{sve_type}" }
+
+  - name: svldnt1_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ldnt1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svldnt1_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld1s{size_literal[1]}_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    assert_instr: ["ld1s{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ld1.{sve_type[0] as {type[1]}}"
+          arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+          return_type: "{sve_type[0] as {type[1]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base]]
+
+  - name: svld1u{size_literal[1]}_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], u8]
+      - [[i32, i64, u32, u64], u16]
+      - [[i64, u64], u32]
+    assert_instr: ["ld1{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ld1.{sve_type[0] as {type[1]}}"
+          arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+          return_type: "{sve_type[0] as {type[1]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base]]
+          - [Type: "{sve_type[0] as {type[1]}}", _]
+
+  - name: svld1s{size_literal[1]}_vnum_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and sign-extend
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    assert_instr: ["ld1s{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svld1s{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld1u{size_literal[1]}_vnum_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and zero-extend
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], u8]
+      - [[i32, i64, u32, u64], u16]
+      - [[i64, u64], u32]
+    assert_instr: ["ld1{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svld1u{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld2[_{type}]
+    attr: [*sve-unstable]
+    doc: Load two-element tuples into two vectors
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type_x2}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld2{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ld2.sret.{sve_type}" }
+
+  - name: svld2_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Load two-element tuples into two vectors
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type_x2}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld2{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svld2_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld3[_{type}]
+    attr: [*sve-unstable]
+    doc: Load three-element tuples into three vectors
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type_x3}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld3{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ld3.sret.{sve_type}" }
+
+  - name: svld3_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Load three-element tuples into three vectors
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type_x3}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld3{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svld3_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld4[_{type}]
+    attr: [*sve-unstable]
+    doc: Load four-element tuples into four vectors
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type_x4}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld4{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ld4.sret.{sve_type}" }
+
+  - name: svld4_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Load four-element tuples into four vectors
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type_x4}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld4{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svld4_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svld1rq[_{type}]
+    attr: [*sve-unstable]
+    doc: Load and replicate 128 bits of data
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld1rq{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ld1rq.{sve_type}" }
+
+  - name: svld1ro[_{type}]
+    attr: [*sve-unstable]
+    doc: Load and replicate 256 bits of data
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    target_features: [f64mm]
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ld1ro{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ld1ro.{sve_type}" }
+
+  - name: svldnf1[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load, non-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_non_faulting
+        - dereference: predicated_non_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ldnf1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ldnf1.{sve_type}" }
+
+  - name: svldnf1_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load, non-faulting
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated_non_faulting
+        - dereference: predicated_non_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ldnf1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svldnf1_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svldnf1s{size_literal[1]}_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and sign-extend, non-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_non_faulting
+        - dereference: predicated_non_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    assert_instr: ["ldnf1s{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ldnf1.{sve_type[0] as {type[1]}}"
+          arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+          return_type: "{sve_type[0] as {type[1]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base]]
+
+  - name: svldnf1u{size_literal[1]}_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and zero-extend, non-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_non_faulting
+        - dereference: predicated_non_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], u8]
+      - [[i32, i64, u32, u64], u16]
+      - [[i64, u64], u32]
+    assert_instr: ["ldnf1{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ldnf1.{sve_type[0] as {type[1]}}"
+          arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+          return_type: "{sve_type[0] as {type[1]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base]]
+          - [Type: "{sve_type[0] as {type[1]}}", _]
+
+  - name: svldnf1s{size_literal[1]}_vnum_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and sign-extend, non-faulting
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated_non_faulting
+        - dereference: predicated_non_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    assert_instr: ["ldnf1s{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldnf1s{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svldnf1u{size_literal[1]}_vnum_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and zero-extend, non-faulting
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated_non_faulting
+        - dereference: predicated_non_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], u8]
+      - [[i32, i64, u32, u64], u16]
+      - [[i64, u64], u32]
+    assert_instr: ["ldnf1{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldnf1u{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svldff1[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate}", "base: *{type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ldff1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink: { name: "ldff1.{sve_type}" }
+
+  - name: svldff1_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["ldff1{size_literal}"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svldff1_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svldff1s{size_literal[1]}_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and sign-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    assert_instr: ["ldff1s{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ldff1.{sve_type[0] as {type[1]}}"
+          arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+          return_type: "{sve_type[0] as {type[1]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base]]
+
+  - name: svldff1u{size_literal[1]}_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], u8]
+      - [[i32, i64, u32, u64], u16]
+      - [[i64, u64], u32]
+    assert_instr: ["ldff1{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ldff1.{sve_type[0] as {type[1]}}"
+          arguments: ["pg: {predicate[0]}", "base: *{type[1]}"]
+          return_type: "{sve_type[0] as {type[1]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base]]
+          - [Type: "{sve_type[0] as {type[1]}}", _]
+
+  - name: svldff1s{size_literal[1]}_vnum_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and sign-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], i8]
+      - [[i32, i64, u32, u64], i16]
+      - [[i64, u64], i32]
+    assert_instr: ["ldff1s{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldff1s{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svldff1u{size_literal[1]}_vnum_{type[0]}
+    attr: [*sve-unstable]
+    doc: Load {size[1]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i16, i32, i64, u16, u32, u64], u8]
+      - [[i32, i64, u32, u64], u16]
+      - [[i64, u64], u32]
+    assert_instr: ["ldff1{size_literal[1]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldff1u{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+
+  - name: svldff1_gather_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["ldff1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}"
+            doubleword:
+              LLVMLink:
+                name: "ldff1.gather.index.{sve_type[1]}"
+
+  - name: svldff1_gather_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["ldff1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1]}"
+            doubleword:
+              LLVMLink:
+                name: "ldff1.gather.{sve_type[1]}"
+
+  - name: svldff1_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ldff1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ldff1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}"
+
+  - name: svldff1_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ldff1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldff1_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svldff1_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ldff1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldff1_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]]
+
+  - name: svldff1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [i32, u32], i16]
+      - [[i64, u64], [i64, u64], [i16, i32]]
+    assert_instr: ["ldff1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ldff1.gather.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $indices]]
+
+  - name: svldff1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [u32, i32], u16]
+      - [[i64, u64], [u64, i64], [u16, u32]]
+    assert_instr: ["ldff1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ldff1.gather.index.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $indices]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svldff1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [i32, u32], [i8, i16]]
+      - [[i64, u64], [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ldff1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ldff1.gather.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]]
+
+  - name: svldff1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i32, u32], [u32, i32], [u8, u16]]
+      - [[i64, u64], [u64, i64], [u8, u16, u32]]
+    assert_instr: ["ldff1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ldff1.gather.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ldff1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]]
+
+  - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [u32, i32], [u8, u16]]
+      - [u64, [u64, i64], [u8, u16, u32]]
+    assert_instr: ["ldff1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - crate::intrinsics::simd::simd_cast
+          - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    doc: Load {size[2]}-bit data and sign-extend, first-faulting
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ldff1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [u8, u16]]
+      - [u64, [i64, u64], [u8, u16, u32]]
+    assert_instr: ["ldff1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], i16]
+      - [u64, [i64, u64], [i16, i32]]
+    assert_instr: ["ldff1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+
+  - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, first-faulting
+    safety:
+      unsafe:
+        - pointer_offset: predicated_first_faulting
+        - dereference: predicated_first_faulting
+        - unpredictable_on_fault
+        - no_provenance: bases
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], u16]
+      - [u64, [i64, u64], [u16, u32]]
+    assert_instr: ["ldff1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+
+  - name: svrdffr_z
+    attr: [*sve-unstable]
+    doc: Read FFR, returning predicate of succesfully loaded elements
+    arguments: ["pg: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [rdffr]
+    compose:
+      - LLVMLink: { name: "rdffr.z" }
+
+  - name: svrdffr
+    attr: [*sve-unstable]
+    doc: Read FFR, returning predicate of succesfully loaded elements
+    arguments: []
+    return_type: svbool_t
+    assert_instr: [rdffr]
+    compose:
+      - FnCall: [svrdffr_z, [FnCall: [svptrue_b8, []]]]
+
+  - name: svsetffr
+    attr: [*sve-unstable]
+    doc: Initialize the first-fault register to all-true
+    arguments: []
+    assert_instr: [setffr]
+    compose:
+      - LLVMLink: { name: "setffr" }
+
+  - name: svwrffr
+    attr: [*sve-unstable]
+    doc: Write to the first-fault register
+    arguments: ["op: svbool_t"]
+    assert_instr: [wrffr]
+    compose:
+      - LLVMLink: { name: "wrffr" }
+
+  - name: svqinc{size_literal[1]}[_n_{type[0]}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type[1]}"
+        default: word
+        byte: byte
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating increment by number of {textual_size} elements
+    arguments: ["op: {type[0]}"]
+    static_defs: ["const IMM_FACTOR: i32"]
+    return_type: "{type[0]}"
+    types:
+      - [[i32, i64, u32, u64], [i8, i16, i32, i64]]
+    assert_instr:
+      - ["{type_kind[0].su}qinc{size_literal[1]}", "IMM_FACTOR = 1"]
+    compose:
+      - FnCall:
+          - "svqinc{size_literal[1]}_pat_n_{type[0]}"
+          - [$op]
+          - ["{{svpattern::SV_ALL}}", $IMM_FACTOR]
+
+  - name: svqinc{size_literal[1]}_pat[_n_{type[0]}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type[1]}"
+        default: word
+        byte: byte
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating increment by number of {textual_size} elements
+    arguments: ["op: {type[0]}"]
+    static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"]
+    constraints: [{ variable: IMM_FACTOR, range: [1, 16] }]
+    return_type: "{type[0]}"
+    types:
+      - [[i32, i64, u32, u64], [i8, i16, i32, i64]]
+    assert_instr:
+      - - "{type_kind[0].su}qinc{size_literal[1]}"
+        - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1"
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}qinc{size_literal[1]}.n{size[0]}"
+          arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"]
+          return_type: "{type[0]}"
+      - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]]
+
+  - name: svqinc{size_literal}[_{type}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type}"
+        default: word
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating increment by number of {textual_size} elements
+    arguments: ["op: {sve_type}"]
+    static_defs: ["const IMM_FACTOR: i32"]
+    return_type: "{sve_type}"
+    types: [i16, u16, i32, u32, i64, u64]
+    assert_instr: [["{type_kind.su}qinc{size_literal}", "IMM_FACTOR = 1"]]
+    compose:
+      - FnCall:
+          - "svqinc{size_literal}_pat_{type}"
+          - [$op]
+          - ["{{svpattern::SV_ALL}}", $IMM_FACTOR]
+
+  - name: svqinc{size_literal}_pat[_{type}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type}"
+        default: word
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating increment by number of {textual_size} elements
+    arguments: ["op: {sve_type}"]
+    static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"]
+    constraints: [{ variable: IMM_FACTOR, range: [1, 16] }]
+    return_type: "{sve_type}"
+    types: [i16, u16, i32, u32, i64, u64]
+    assert_instr:
+      - - "{type_kind.su}qinc{size_literal}"
+        - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1"
+    compose:
+      - LLVMLink:
+          name: "{type_kind.su}qinc{size_literal}.{sve_type}"
+          arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"]
+          return_type: "{sve_type}"
+      - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]]
+
+  - name: svqdec{size_literal[1]}[_n_{type[0]}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type[1]}"
+        default: word
+        byte: byte
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating decrement by number of {textual_size} elements
+    arguments: ["op: {type[0]}"]
+    static_defs: ["const IMM_FACTOR: i32"]
+    return_type: "{type[0]}"
+    types:
+      - [[i32, i64, u32, u64], [i8, i16, i32, i64]]
+    assert_instr:
+      - ["{type_kind[0].su}qdec{size_literal[1]}", "IMM_FACTOR = 1"]
+    compose:
+      - FnCall:
+          - "svqdec{size_literal[1]}_pat_n_{type[0]}"
+          - [$op]
+          - ["{{svpattern::SV_ALL}}", $IMM_FACTOR]
+
+  - name: svqdec{size_literal[1]}_pat[_n_{type[0]}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type[1]}"
+        default: word
+        byte: byte
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating decrement by number of {textual_size} elements
+    arguments: ["op: {type[0]}"]
+    static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"]
+    constraints: [{ variable: IMM_FACTOR, range: [1, 16] }]
+    return_type: "{type[0]}"
+    types:
+      - [[i32, i64, u32, u64], [i8, i16, i32, i64]]
+    assert_instr:
+      - - "{type_kind[0].su}qdec{size_literal[1]}"
+        - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1"
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}qdec{size_literal[1]}.n{size[0]}"
+          arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"]
+          return_type: "{type[0]}"
+      - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]]
+
+  - name: svqdec{size_literal}[_{type}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type}"
+        default: word
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating decrement by number of {textual_size} elements
+    arguments: ["op: {sve_type}"]
+    static_defs: ["const IMM_FACTOR: i32"]
+    return_type: "{sve_type}"
+    types: [i16, u16, i32, u32, i64, u64]
+    assert_instr: [["{type_kind.su}qdec{size_literal}", "IMM_FACTOR = 1"]]
+    compose:
+      - FnCall:
+          - "svqdec{size_literal}_pat_{type}"
+          - [$op]
+          - ["{{svpattern::SV_ALL}}", $IMM_FACTOR]
+
+  - name: svqdec{size_literal}_pat[_{type}]
+    attr: [*sve-unstable]
+    substitutions:
+      textual_size:
+        match_size: "{type}"
+        default: word
+        halfword: halfword
+        doubleword: doubleword
+    doc: Saturating decrement by number of {textual_size} elements
+    arguments: ["op: {sve_type}"]
+    static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"]
+    constraints: [{ variable: IMM_FACTOR, range: [1, 16] }]
+    return_type: "{sve_type}"
+    types: [i16, u16, i32, u32, i64, u64]
+    assert_instr:
+      - - "{type_kind.su}qdec{size_literal}"
+        - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1"
+    compose:
+      - LLVMLink:
+          name: "{type_kind.su}qdec{size_literal}.{sve_type}"
+          arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"]
+          return_type: "{sve_type}"
+      - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]]
+
+  - name: svst1[_{type}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st1{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - LLVMLink:
+          name: "st1.{sve_type}"
+          arguments:
+            - "data: {sve_type}"
+            - "pg: {predicate}"
+            - "ptr: *mut {type}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $base]]
+
+  - name: svst1_scatter_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[1]}"
+      - "indices: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [[i32, u32], [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["st1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1]}"
+                arguments:
+                  - "data: {sve_type[1]}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[1]}"
+                  - "indices: {sve_type[0]}"
+            doubleword:
+              LLVMLink:
+                name: "st1.scatter.index.{sve_type[1]}"
+                arguments:
+                  - "data: {sve_type[1]}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[1]}"
+                  - "indices: {sve_type[0]}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]]
+
+  - name: svst1_scatter_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[1]}"
+      - "offsets: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [[i32, u32], [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["st1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1]}"
+                arguments:
+                  - "data: {sve_type[1]}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[1]}"
+                  - "offsets: {sve_type[0]}"
+            doubleword:
+              LLVMLink:
+                name: "st1.scatter.{sve_type[1]}"
+                arguments:
+                  - "data: {sve_type[1]}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[1]}"
+                  - "offsets: {sve_type[0]}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]]
+
+  - name: svst1_scatter[_{type[0]}base]_offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "offset: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["st1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - LLVMLink:
+          arguments:
+            - "data: {sve_type[1]}"
+            - "pg: {predicate[0]}"
+            - "bases: {sve_type[0]}"
+            - "offset: i64"
+          name: "st1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]]
+
+  - name: svst1_scatter[_{type[0]}base_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments:
+      ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"]
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["st1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - FnCall:
+          - "svst1_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+            - $data
+
+  - name: svst1_scatter[_{type[0]}base]_index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "index: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["st1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - FnCall:
+          - "svst1_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]]
+            - $data
+
+  - name: svst1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[2]}"
+      - "indices: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [[i32, u32], i32, i16]
+      - [[i32, u32], u32, u16]
+      - [[i64, u64], i64, [i16, i32]]
+      - [[i64, u64], u64, [u16, u32]]
+    assert_instr: ["st1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}"
+                arguments:
+                  - "data: {sve_type[1] as {type[2]}}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[2]}"
+                  - "indices: {sve_type[0]}"
+            doubleword:
+              LLVMLink:
+                name: "st1.scatter.index.{sve_type[1] as {type[2]}}"
+                arguments:
+                  - "data: {sve_type[1] as {type[2]}}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[2]}"
+                  - "indices: {sve_type[0]}"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices]
+
+  - name: svst1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[2]}"
+      - "offsets: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [[i32, u32], i32, [i8, i16]]
+      - [[i32, u32], u32, [u8, u16]]
+      - [[i64, u64], i64, [i8, i16, i32]]
+      - [[i64, u64], u64, [u8, u16, u32]]
+    assert_instr: ["st1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}"
+                arguments:
+                  - "data: {sve_type[1] as {type[2]}}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[2]}"
+                  - "offsets: {sve_type[0]}"
+            doubleword:
+              LLVMLink:
+                name: "st1.scatter.{sve_type[1] as {type[2]}}"
+                arguments:
+                  - "data: {sve_type[1] as {type[2]}}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[2]}"
+                  - "offsets: {sve_type[0]}"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets]
+
+  - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "offset: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["st1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - LLVMLink:
+          name: "st1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          arguments:
+            - "data: {sve_type[1] as {type[2]}}"
+            - "pg: {predicate[0]}"
+            - "bases: {sve_type[0]}"
+            - "offset: i64"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset]
+
+  - name: svst1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments:
+      ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"]
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["st1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - FnCall:
+          - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+            - $data
+
+  - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "index: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [i32, u32], i16]
+      - [u64, [i64, u64], [i16, i32]]
+    assert_instr: ["st1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - FnCall:
+          - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+            - $data
+
+  - name: svstnt1[_{type}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["stnt1{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - LLVMLink:
+          name: "stnt1.{sve_type}"
+          arguments:
+            - "data: {sve_type}"
+            - "pg: {predicate}"
+            - "ptr: *mut {type}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $base]]
+
+  - name: svstnt1_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["stnt1{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - FnCall:
+          - "svstnt1_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+            - $data
+
+  - name: svst1{size_literal[1]}[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[1]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate[0]}", "base: *mut {type[1]}", "data: {sve_type[0]}"]
+    types:
+      - [[i16, i32, i64], i8]
+      - [[u16, u32, u64], u8]
+      - [[i32, i64], i16]
+      - [[u32, u64], u16]
+      - [i64, i32]
+      - [u64, u32]
+    assert_instr: ["st1{size_literal[1]}"]
+    test: { store: 1 }
+    compose:
+      - LLVMLink:
+          name: "st1.{sve_type[0] as {type[1]}}"
+          arguments:
+            - "data: {sve_type[0] as {type[1]}}"
+            - "pg: {predicate[0]}"
+            - "ptr: *mut {type[1]}"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base]
+
+  - name: svst1{size_literal[1]}_vnum[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[1]} bits and store
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[1]}"
+      - "vnum: i64"
+      - "data: {sve_type[0]}"
+    types:
+      - [[i16, i32, i64], i8]
+      - [[u16, u32, u64], u8]
+      - [[i32, i64], i16]
+      - [[u32, u64], u16]
+      - [i64, i32]
+      - [u64, u32]
+    assert_instr: ["st1{size_literal[1]}"]
+    test: { store: 1 }
+    compose:
+      - FnCall:
+          - "svst1{size_literal[1]}_{type[0]}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs:
+                          [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+            - $data
+
+  - name: svst1_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st1{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - FnCall:
+          - "svst1_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+            - $data
+
+  - name: svst2[_{type}]
+    attr: [*sve-unstable]
+    doc: Store two vectors into two-element tuples
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x2}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st2{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - LLVMLink:
+          name: "st2.{sve_type}"
+          arguments:
+            - "data0: {sve_type}"
+            - "data1: {sve_type}"
+            - "pg: {predicate}"
+            - "ptr: *mut {type}"
+      - FnCall:
+          - "{llvm_link}"
+          - - FnCall: ["svget2_{type}", ["$data"], [0]]
+            - FnCall: ["svget2_{type}", ["$data"], [1]]
+            - "$pg"
+            - "$base"
+
+  - name: svst2_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Store two vectors into two-element tuples
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate}"
+      - "base: *mut {type}"
+      - "vnum: i64"
+      - "data: {sve_type_x2}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st2{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - FnCall:
+          - "svst2_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+            - $data
+
+  - name: svst3[_{type}]
+    attr: [*sve-unstable]
+    doc: Store three vectors into three-element tuples
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x3}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st3{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - LLVMLink:
+          name: "st3.{sve_type}"
+          arguments:
+            - "data0: {sve_type}"
+            - "data1: {sve_type}"
+            - "data2: {sve_type}"
+            - "pg: {predicate}"
+            - "ptr: *mut {type}"
+      - FnCall:
+          - "{llvm_link}"
+          - - FnCall: ["svget3_{type}", ["$data"], [0]]
+            - FnCall: ["svget3_{type}", ["$data"], [1]]
+            - FnCall: ["svget3_{type}", ["$data"], [2]]
+            - "$pg"
+            - "$base"
+
+  - name: svst3_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Store three vectors into three-element tuples
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate}"
+      - "base: *mut {type}"
+      - "vnum: i64"
+      - "data: {sve_type_x3}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st3{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - FnCall:
+          - "svst3_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+            - $data
+
+  - name: svst4[_{type}]
+    attr: [*sve-unstable]
+    doc: Store four vectors into four-element tuples
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+    arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x4}"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st4{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - LLVMLink:
+          name: "st4.{sve_type}"
+          arguments:
+            - "data0: {sve_type}"
+            - "data1: {sve_type}"
+            - "data2: {sve_type}"
+            - "data3: {sve_type}"
+            - "pg: {predicate}"
+            - "ptr: *mut {type}"
+      - FnCall:
+          - "{llvm_link}"
+          - - FnCall: ["svget4_{type}", ["$data"], [0]]
+            - FnCall: ["svget4_{type}", ["$data"], [1]]
+            - FnCall: ["svget4_{type}", ["$data"], [2]]
+            - FnCall: ["svget4_{type}", ["$data"], [3]]
+            - "$pg"
+            - "$base"
+
+  - name: svst4_vnum[_{type}]
+    attr: [*sve-unstable]
+    doc: Store four vectors into four-element tuples
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+        - dereference: predicated
+    arguments:
+      - "pg: {predicate}"
+      - "base: *mut {type}"
+      - "vnum: i64"
+      - "data: {sve_type_x4}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["st4{size_literal}"]
+    test: { store: 0 }
+    compose:
+      - FnCall:
+          - "svst4_{type}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+            - $data
+
+  - name: svtbl[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Table lookup in single-vector table
+    arguments: ["data: {sve_type[0]}", "indices: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    assert_instr: [tbl]
+    types:
+      - [f32, u32]
+      - [f64, u64]
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+      - [u8, u8]
+      - [u16, u16]
+      - [u32, u32]
+      - [u64, u64]
+    compose:
+      - LLVMLink: { name: "tbl.{sve_type[0]}" }
+
+  - name: svwhilele_{type[1]}[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: While incrementing scalar is less than or equal to
+    arguments: ["op1: {type[0]}", "op2: {type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]]
+    assert_instr: [{ default: whilele, unsigned: whilels }]
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default: { LLVMLink: { name: "whilele.{sve_type[1]}.{type[0]}" } }
+            unsigned: { LLVMLink: { name: "whilels.{sve_type[1]}.{type[0]}" } }
+
+  - name: svwhilelt_{type[1]}[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: While incrementing scalar is less than
+    arguments: ["op1: {type[0]}", "op2: {type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]]
+    assert_instr: [{ default: whilelt, unsigned: whilelo }]
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default: { LLVMLink: { name: "whilelt.{sve_type[1]}.{type[0]}" } }
+            unsigned: { LLVMLink: { name: "whilelo.{sve_type[1]}.{type[0]}" } }
+
+  - name: svmax[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Maximum
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind}max"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}max.{sve_type}" }
+
+  - name: svmaxnm[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Maximum number
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    assert_instr: [fmaxnm]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}maxnm.{sve_type}" }
+
+  - name: svpfalse[_b]
+    attr: [*sve-unstable]
+    doc: Set all predicate elements to false
+    arguments: []
+    return_type: "svbool_t"
+    assert_instr: [pfalse]
+    compose:
+      - FnCall:
+          - "svdupq_n_b8"
+          - - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+            - false
+
+  - name: svptrue_pat_{type}
+    attr: [*sve-unstable]
+    doc: Set predicate elements to true
+    arguments: []
+    static_defs: ["const PATTERN: svpattern"]
+    return_type: "{predicate}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [[ptrue, "PATTERN = {{svpattern::SV_ALL}}"]]
+    compose:
+      - LLVMLink:
+          name: ptrue.{sve_type}
+          arguments: ["pattern: svpattern"]
+      - FnCall: ["{llvm_link}", [$PATTERN]]
+
+  - name: svptrue_{type}
+    attr: [*sve-unstable]
+    doc: Set predicate elements to true
+    arguments: []
+    return_type: "svbool_t"
+    types: [b8, b16, b32, b64]
+    assert_instr: [ptrue]
+    compose:
+      - FnCall: ["svptrue_pat_{type}", [], ["{{svpattern::SV_ALL}}"]]
+
+  - name: svptest_any
+    attr: [*sve-unstable]
+    doc: Test whether any active element is true
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: "bool"
+    assert_instr: [ptest]
+    compose:
+      - LLVMLink: { name: "ptest.any.nxv16i1" }
+
+  - name: svptest_first
+    attr: [*sve-unstable]
+    doc: Test whether first active element is true
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: "bool"
+    assert_instr: [ptest]
+    compose:
+      - LLVMLink: { name: "ptest.first.nxv16i1" }
+
+  - name: svptest_last
+    attr: [*sve-unstable]
+    doc: Test whether last active element is true
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: "bool"
+    assert_instr: [ptest]
+    compose:
+      - LLVMLink: { name: "ptest.last.nxv16i1" }
+
+  - name: svpfirst[_b]
+    attr: [*sve-unstable]
+    doc: Set the first active predicate element to true
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [pfirst]
+    compose:
+      - LLVMLink: { name: "pfirst.nxv16i1" }
+
+  - name: svpnext_{type}
+    attr: [*sve-unstable]
+    doc: Find next active predicate
+    arguments: ["pg: {predicate}", "op: {predicate}"]
+    return_type: "{predicate}"
+    types: [b8, b16, b32, b64]
+    assert_instr: [pnext]
+    compose:
+      - LLVMLink: { name: "pnext.{sve_type}" }
+
+  - name: svbrkn[_b]_z
+    attr: [*sve-unstable]
+    doc: Propagate break to next partition
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brkn]
+    compose:
+      - LLVMLink: { name: "brkn.z.nxv16i1" }
+
+  - name: svbrkb[_b]_z
+    attr: [*sve-unstable]
+    doc: Break before first true condition
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brkb]
+    compose:
+      - LLVMLink: { name: "brkb.z.nxv16i1" }
+
+  - name: svbrkb[_b]_m
+    attr: [*sve-unstable]
+    doc: Break before first true condition
+    arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brkb]
+    compose:
+      - LLVMLink: { name: "brkb.nxv16i1" }
+
+  - name: svbrkpb[_b]_z
+    attr: [*sve-unstable]
+    doc: Break before first true condition, propagating from previous partition
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brkpb]
+    compose:
+      - LLVMLink: { name: "brkpb.z.nxv16i1" }
+
+  - name: svbrka[_b]_z
+    attr: [*sve-unstable]
+    doc: Break after first true condition
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brka]
+    compose:
+      - LLVMLink: { name: "brka.z.nxv16i1" }
+
+  - name: svbrka[_b]_m
+    attr: [*sve-unstable]
+    doc: Break after first true condition
+    arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brka]
+    compose:
+      - LLVMLink: { name: "brka.nxv16i1" }
+
+  - name: svbrkpa[_b]_z
+    attr: [*sve-unstable]
+    doc: Break after first true condition, propagating from previous partition
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [brkpa]
+    compose:
+      - LLVMLink: { name: "brkpa.z.nxv16i1" }
+
+  - name: svsel[_b]
+    attr: [*sve-unstable]
+    doc: Conditionally select elements
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: "svbool_t"
+    assert_instr: [sel]
+    compose:
+      - FnCall: ["simd_select", [$pg, $op1, $op2]]
+
+  - name: svsel[_{type}]
+    attr: [*sve-unstable]
+    doc: Conditionally select elements
+    arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [sel]
+    compose:
+      - FnCall:
+          - "simd_select"
+          - - MatchSize:
+                - "{type}"
+                - { default: { MethodCall: [$pg, sve_into, []] }, byte: $pg }
+            - $op1
+            - $op2
+          - - MatchSize:
+                - "{type}"
+                - byte: svbool_t
+                  halfword: svbool8_t
+                  default: svbool4_t
+                  doubleword: svbool2_t
+            - _
+
+  - name: svsub[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Subtract
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64]
+    assert_instr: ["{type_kind.f}sub"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}sub.{sve_type}" }
+
+  - name: svsubr[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Subtract reversed
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64]
+    assert_instr: ["{type_kind.f}subr"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}subr.{sve_type}" }
+
+  - name: svcntp_{predicate}
+    attr: [*sve-unstable]
+    doc: Count set predicate bits
+    arguments: ["pg: {predicate}", "op: {predicate}"]
+    types: [b8, b16, b32, b64]
+    return_type: u64
+    assert_instr: [cntp]
+    compose:
+      - LLVMLink: { name: "cntp.{predicate}" }
+
+  - name: svcompact[_{type}]
+    attr: [*sve-unstable]
+    doc: Shuffle active elements of vector to the right and fill with zero
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i32, i64, u32, u64]
+    assert_instr: [compact]
+    compose:
+      - LLVMLink: { name: "compact.{sve_type}" }
+
+  - name: svlasta[_{type}]
+    attr: [*sve-unstable]
+    doc: Extract element after last
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [lasta]
+    compose:
+      - LLVMLink: { name: "lasta.{sve_type}" }
+
+  - name: svclasta[_{type}]
+    attr: [*sve-unstable]
+    doc: Conditionally extract element after last
+    arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [clasta]
+    compose:
+      - LLVMLink: { name: "clasta.{sve_type}" }
+
+  - name: svclasta[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Conditionally extract element after last
+    arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [clasta]
+    compose:
+      - LLVMLink: { name: "clasta.n.{sve_type}" }
+
+  - name: svlastb[_{type}]
+    attr: [*sve-unstable]
+    doc: Extract last element
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [lastb]
+    compose:
+      - LLVMLink: { name: "lastb.{sve_type}" }
+
+  - name: svclastb[_{type}]
+    attr: [*sve-unstable]
+    doc: Conditionally extract last element
+    arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [clastb]
+    compose:
+      - LLVMLink: { name: "clastb.{sve_type}" }
+
+  - name: svclastb[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Conditionally extract last element
+    arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [clastb]
+    compose:
+      - LLVMLink: { name: "clastb.n.{sve_type}" }
+
+  - name: svqdecp[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating decrement by active element count
+    arguments: ["op: {sve_type}", "pg: {predicate}"]
+    return_type: "{sve_type}"
+    types: [i16, i32, i64, u16, u32, u64]
+    assert_instr: ["{type_kind.su}qdecp"]
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qdecp.{sve_type}" }
+
+  - name: svqdecp[_n_{type[0]}]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Saturating decrement by active element count
+    arguments: ["op: {type[0]}", "pg: {sve_type[1]}"]
+    return_type: "{type[0]}"
+    types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]]
+    assert_instr: ["{type_kind[0].su}qdecp"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}qdecp.n{size[0]}.{sve_type[1]}" }
+
+  - name: svqincp[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating increment by active element count
+    arguments: ["op: {sve_type}", "pg: {predicate}"]
+    return_type: "{sve_type}"
+    types: [i16, i32, i64, u16, u32, u64]
+    assert_instr: ["{type_kind.su}qincp"]
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qincp.{sve_type}" }
+
+  - name: svqincp[_n_{type[0]}]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Saturating increment by active element count
+    arguments: ["op: {type[0]}", "pg: {sve_type[1]}"]
+    return_type: "{type[0]}"
+    types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]]
+    assert_instr: ["{type_kind[0].su}qincp"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}qincp.n{size[0]}.{sve_type[1]}" }
+
+  - name: svtmad[_{type}]
+    attr: [*sve-unstable]
+    doc: Trigonometric multiply-add coefficient
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, range: [0, 7] }]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [[ftmad, "IMM3 = 0"]]
+    compose:
+      - LLVMLink:
+          name: "ftmad.x.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall:
+          - "{llvm_link}"
+          - [op1, op2, IMM3]
+
+  - name: svtsmul[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Trigonometric starting value
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [f32, u32]
+      - [f64, u64]
+    assert_instr: [ftsmul]
+    compose:
+      - LLVMLink:
+          name: "ftsmul.x.{sve_type[0]}"
+
+  - name: svtssel[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Trigonometric select coefficient
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [f32, u32]
+      - [f64, u64]
+    assert_instr: [ftssel]
+    compose:
+      - LLVMLink:
+          name: "ftssel.x.{sve_type[0]}"
+
+  - name: svprf{size_literal}
+    attr: [*sve-unstable]
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+    substitutions:
+      textual_size:
+        match_size: "{type}"
+        default: words
+        byte: bytes
+        halfword: halfwords
+        doubleword: doublewords
+    doc: Prefetch {textual_size}
+    arguments: ["pg: {predicate}", "base: *T"]
+    static_defs: ["const OP: svprfop", T]
+    types: [b8, b16, b32, b64]
+    assert_instr:
+      - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"]
+    test: { load: 0 }
+    compose:
+      - LLVMLink:
+          name: "prf.{sve_type}"
+          arguments:
+            ["pg: {predicate}", "base: *crate::ffi::c_void", "op: svprfop"]
+      - FnCall:
+          - "{llvm_link}"
+          - - $pg
+            - CastAs: [$base, "*const crate::ffi::c_void"]
+            - $OP
+
+  - name: svprf{size_literal}_vnum
+    attr: [*sve-unstable]
+    safety:
+      unsafe:
+        - pointer_offset_vnum: predicated
+    substitutions:
+      textual_size:
+        match_size: "{type}"
+        default: words
+        byte: bytes
+        halfword: halfwords
+        doubleword: doublewords
+    doc: Prefetch {textual_size}
+    arguments: ["pg: {predicate}", "base: *T", "vnum: i64"]
+    static_defs: ["const OP: svprfop", T]
+    types: [b8, b16, b32, b64]
+    assert_instr:
+      - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"]
+    test: { load: 0 }
+    compose:
+      - FnCall:
+          - "svprf{size_literal}"
+          - - $pg
+            - MethodCall:
+                - $base
+                - offset
+                - - Multiply:
+                      - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize]
+                      - CastAs: [$vnum, isize]
+          - - $OP
+            - _
+
+  - name: svprf{size_literal[1]}_gather_[{type[0]}]{index_or_offset}
+    attr: [*sve-unstable]
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+    substitutions:
+      index_or_offset:
+        { match_size: "{type[1]}", default: "index", byte: "offset" }
+      indices_or_offsets:
+        { match_size: "{type[1]}", default: "indices", byte: "offsets" }
+      textual_size:
+        match_size: "{type[1]}"
+        default: words
+        byte: bytes
+        halfword: halfwords
+        doubleword: doublewords
+    doc: Prefetch {textual_size}
+    types:
+      - [[i32, u32, i64, u64], [i8, i16, i32, i64]]
+    arguments:
+      ["pg: {predicate[0]}", "base: *T", "{indices_or_offsets}: {sve_type[0]}"]
+    static_defs: ["const OP: svprfop", T]
+    assert_instr:
+      [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"]]
+    test: { load: 0 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "prf{size_literal[1]}.gather.{type_kind[0].su}xtw.index.{sve_type[0]}"
+                arguments:
+                  - "pg: {predicate[0]}"
+                  - "base: *crate::ffi::c_void"
+                  - "{indices_or_offsets}: {sve_type[0]}"
+                  - "op: svprfop"
+            doubleword:
+              LLVMLink:
+                name: "prf{size_literal[1]}.gather.index.{sve_type[0]}"
+                arguments:
+                  - "pg: {predicate[0]}"
+                  - "base: *crate::ffi::c_void"
+                  - "{indices_or_offsets}: {sve_type[0]}"
+                  - "op: svprfop"
+      - FnCall:
+          - "{llvm_link}"
+          - - $pg
+            - CastAs: [$base, "*const crate::ffi::c_void"]
+            - "${indices_or_offsets}"
+            - $OP
+
+  - name: svprf{size_literal[1]}_gather[_{type[0]}base]
+    attr: [*sve-unstable]
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - no_provenance: bases
+    substitutions:
+      textual_size:
+        match_size: "{type[1]}"
+        default: words
+        byte: bytes
+        halfword: halfwords
+        doubleword: doublewords
+    doc: Prefetch {textual_size}
+    types:
+      - [[u32, u64], [i8, i16, i32, i64]]
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    static_defs: ["const OP: svprfop"]
+    assert_instr: [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}"]]
+    test: { load: 0 }
+    compose:
+      - LLVMLink:
+          name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}"
+          arguments:
+            - "pg: {predicate[0]}"
+            - "bases: {sve_type[0]}"
+            - "index: i64"
+            - "op: svprfop"
+      - FnCall: ["{llvm_link}", [$pg, $bases, 0, $OP]]
+
+  - name: svprf{size_literal[1]}_gather[_{type[0]}base]_{index_or_offset}
+    attr: [*sve-unstable]
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - no_provenance: bases
+    substitutions:
+      index_or_offset:
+        { match_size: "{type[1]}", default: "index", byte: "offset" }
+      textual_size:
+        match_size: "{type[1]}"
+        default: words
+        byte: bytes
+        halfword: halfwords
+        doubleword: doublewords
+    doc: Prefetch {textual_size}
+    types:
+      - [[u32, u64], [i8, i16, i32, i64]]
+    arguments:
+      ["pg: {predicate[0]}", "bases: {sve_type[0]}", "{index_or_offset}: i64"]
+    static_defs: ["const OP: svprfop"]
+    assert_instr: [["prfb", "OP = {{svprfop::SV_PLDL1KEEP}}"]]
+    test: { load: 0 }
+    compose:
+      - LLVMLink:
+          name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}"
+          arguments:
+            - "pg: {predicate[0]}"
+            - "bases: {sve_type[0]}"
+            - "{index_or_offset}: i64"
+            - "op: svprfop"
+      - FnCall:
+          - "{llvm_link}"
+          - - $pg
+            - $bases
+            - MatchSize:
+                - "{type[1]}"
+                - byte: $offset
+                  halfword: { MethodCall: [$index, unchecked_shl, [1]] }
+                  default: { MethodCall: [$index, unchecked_shl, [2]] }
+                  doubleword: { MethodCall: [$index, unchecked_shl, [3]] }
+            - $OP
+
+  - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Floating-point convert
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[f32, f64], [i32, u32, i64, u64]]
+    zeroing_method: { drop: inactive }
+    substitutions:
+      convert_from: { match_kind: "{type[1]}", default: s, unsigned: u }
+    assert_instr: ["{convert_from}cvtf"]
+    compose:
+      - LLVMLink:
+          name: "{convert_from}cvtf.{type[0]}{type[1]}"
+
+  - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Floating-point convert
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i32, u32, i64, u64], [f32, f64]]
+    zeroing_method: { drop: inactive }
+    substitutions:
+      convert_to: { match_kind: "{type[0]}", default: s, unsigned: u }
+    assert_instr: ["fcvtz{convert_to}"]
+    compose:
+      - LLVMLink: { name: "fcvtz{convert_to}.{type[0]}{type[1]}" }
+
+  - name: svcvt_{type[0]}[_{type[1]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Floating-point convert
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f32, f64], [f64, f32]]
+    zeroing_method: { drop: inactive }
+    assert_instr: [fcvt]
+    compose:
+      - LLVMLink: { name: "fcvt.{type[0]}{type[1]}" }
+
+  - name: svreinterpret_{type[0]}[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Reinterpret vector contents
+    arguments: ["op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    assert_instr: []
+    types:
+      - - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+        - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    compose:
+      - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true]
+
+  - name: svrinta[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round to nearest, ties away from zero
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frinta]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frinta.{sve_type}" }
+
+  - name: svrinti[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round using current rounding mode (inexact)
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frinti]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frinti.{sve_type}" }
+
+  - name: svrintm[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round towards -∞
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frintm]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frintm.{sve_type}" }
+
+  - name: svrintn[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round to nearest, ties to even
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frintn]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frintn.{sve_type}" }
+
+  - name: svrintp[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round towards +∞
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frintp]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frintp.{sve_type}" }
+
+  - name: svrintx[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round using current rounding mode (exact)
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frintx]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frintx.{sve_type}" }
+
+  - name: svrintz[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Round towards zero
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frintz]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frintz.{sve_type}" }
+
+  - name: svabd[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Absolute difference
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f64, f32, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind}abd"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind}abd.{sve_type}" }
+
+  - name: svabs[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Absolute value
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64]
+    assert_instr: ["{type_kind.f}abs"]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "{type_kind.f}abs.{sve_type}" }
+
+  - name: svand[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Bitwise AND
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [and]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op2
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink: { name: "and.{sve_type}" }
+
+  - name: svandv[_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise AND reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    assert_instr: [andv]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    compose:
+      - LLVMLink: { name: "andv.{sve_type}" }
+
+  - name: svand[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise AND
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [and]
+    compose:
+      - LLVMLink: { name: "and.z.nvx16i1" }
+
+  - name: svmov[_b]_z
+    attr: [*sve-unstable]
+    doc: Move
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [mov]
+    compose:
+      - FnCall: ["svand_b_z", [$pg, $op, $op]]
+
+  - name: svbic[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Bitwise clear
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [bic]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op2
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink: { name: "bic.{sve_type}" }
+
+  - name: svbic[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise clear
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [bic]
+    compose:
+      - LLVMLink: { name: "bic.z.nvx16i1" }
+
+  - name: sveor[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Bitwise exclusive OR
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [eor]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op2
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink: { name: "eor.{sve_type}" }
+
+  - name: sveorv[_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise exclusive OR reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    assert_instr: [eorv]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    compose:
+      - LLVMLink: { name: "eorv.{sve_type}" }
+
+  - name: sveor[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise exclusive OR
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [eor]
+    compose:
+      - LLVMLink: { name: "eor.z.nvx16i1" }
+
+  - name: svnot[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Bitwise invert
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [not]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "not.{sve_type}" }
+
+  - name: svnot[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise invert
+    arguments: ["pg: svbool_t", "op: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [not]
+    compose:
+      - FnCall: ["sveor_b_z", [$pg, $op, $pg]]
+
+  - name: svcnot[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Logically invert boolean condition
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [cnot]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "cnot.{sve_type}" }
+
+  - name: svnand[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise NAND
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [nand]
+    compose:
+      - LLVMLink: { name: "nand.z.nxv16i1" }
+
+  - name: svnor[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise NOR
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [nor]
+    compose:
+      - LLVMLink: { name: "nor.z.nxv16i1" }
+
+  - name: svorr[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Bitwise inclusive OR
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [orr]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op2
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink: { name: "orr.{sve_type}" }
+
+  - name: svorv[_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise inclusive OR reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    assert_instr: [orv]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    compose:
+      - LLVMLink: { name: "orv.{sve_type}" }
+
+  - name: svorr[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise inclusive OR
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [orr]
+    compose:
+      - LLVMLink: { name: "orr.z.nvx16i1" }
+
+  - name: svorn[_b]_z
+    attr: [*sve-unstable]
+    doc: Bitwise inclusive OR, inverting second argument
+    arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"]
+    return_type: svbool_t
+    assert_instr: [orn]
+    compose:
+      - LLVMLink: { name: "orn.z.nvx16i1" }
+
+  - name: svlsl[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Logical shift left
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i8, u8], u8]
+      - [[i16, u16], u16]
+      - [[i32, u32], u32]
+      - [[i64, u64], u64]
+    assert_instr: [lsl]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "lsl.{sve_type[0]}" }
+
+  - name: svlsl_wide[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Logical shift left
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i8, i16, i32, u8, u16, u32], u64]
+    assert_instr: [lsl]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "lsl.wide.{sve_type[0]}" }
+
+  - name: svasr[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Arithmetic shift right
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+    assert_instr: [asr]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "asr.{sve_type[0]}" }
+
+  - name: svasr_wide[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Arithmetic shift right
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i8, i16, i32], u64]
+    assert_instr: [asr]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "asr.wide.{sve_type[0]}" }
+
+  - name: svasrd[_n_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Arithmetic shift right for divide by immediate
+    arguments: ["pg: {predicate}", "op1: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size}"] }]
+    types: [i8, i16, i32, i64]
+    assert_instr: [[asrd, "IMM2 = 1"]]
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink:
+          name: "asrd.{sve_type}"
+          arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]]
+
+  - name: svlsr[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Logical shift right
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8, u16, u32, u64]
+    assert_instr: [lsr]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "lsr.{sve_type}" }
+
+  - name: svlsr_wide[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Logical shift right
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[u8, u16, u32], u64]
+    assert_instr: [lsr]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "lsr.wide.{sve_type[0]}" }
+
+  - name: svadda[_{type}]
+    attr: [*sve-unstable]
+    doc: Add reduction (strictly-ordered)
+    arguments: ["pg: {predicate}", "initial: {type}", "op: {sve_type}"]
+    return_type: "{type}"
+    assert_instr: [fadda]
+    types: [f32, f64]
+    compose:
+      - LLVMLink: { name: "fadda.{sve_type}" }
+
+  - name: svaddv[_{type}]
+    attr: [*sve-unstable]
+    doc: Add reduction
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i64, u64]
+    assert_instr: [{ float: faddv, default: uaddv }]
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}addv.{sve_type}" }
+
+  - name: svaddv[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add reduction
+    arguments: ["pg: {predicate[0]}", "op: {sve_type[0]}"]
+    return_type: "{type[1]}"
+    types:
+      - [[i8, i16, i32], i64]
+      - [[u8, u16, u32], u64]
+    assert_instr: ["{type_kind[0].su}addv"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}addv.{sve_type[0]}" }
+
+  - name: svmaxv[_{type}]
+    attr: [*sve-unstable]
+    doc: Maximum reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.fsu}maxv"]
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}maxv.{sve_type}" }
+
+  - name: svmaxnmv[_{type}]
+    attr: [*sve-unstable]
+    doc: Maximum number reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64]
+    assert_instr: [fmaxnmv]
+    compose:
+      - LLVMLink: { name: "fmaxnmv.{sve_type}" }
+
+  - name: svminv[_{type}]
+    attr: [*sve-unstable]
+    doc: Minimum reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.fsu}minv"]
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}minv.{sve_type}" }
+
+  - name: svminnmv[_{type}]
+    attr: [*sve-unstable]
+    doc: Minimum number reduction to scalar
+    arguments: ["pg: {predicate}", "op: {sve_type}"]
+    return_type: "{type}"
+    types: [f32, f64]
+    assert_instr: [fminnmv]
+    compose:
+      - LLVMLink: { name: "fminnmv.{sve_type}" }
+
+  - name: svmul[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: ["{type_kind.f}mul"]
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.f}mul.{sve_type}" }
+
+  - name: svmulh[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply, returning high-half
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: ["{type_kind.su}mulh"]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}mulh.{sve_type}" }
+
+  - name: svmulx[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply extended (∞×0=2)
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: ["fmulx"]
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "fmulx.{sve_type}" }
+
+  - name: svrecpe[_{type}]
+    attr: [*sve-unstable]
+    doc: Reciprocal estimate
+    arguments: ["op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frecpe]
+    compose:
+      - LLVMLink: { name: "frecpe.x.{sve_type}" }
+
+  - name: svrecps[_{type}]
+    attr: [*sve-unstable]
+    doc: Reciprocal step
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frecps]
+    compose:
+      - LLVMLink: { name: "frecps.x.{sve_type}" }
+
+  - name: svrecpx[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reciprocal exponent
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frecpx]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "frecpx.x.{sve_type}" }
+
+  - name: svrsqrte[_{type}]
+    attr: [*sve-unstable]
+    doc: Reciprocal square root estimate
+    arguments: ["op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frsqrte]
+    compose:
+      - LLVMLink: { name: "frsqrte.x.{sve_type}" }
+
+  - name: svrsqrts[_{type}]
+    attr: [*sve-unstable]
+    doc: Reciprocal square root step
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: [frsqrts]
+    compose:
+      - LLVMLink: { name: "frsqrts.x.{sve_type}" }
+
+  - name: svmad[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply-add, multiplicand first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: ["{type_kind.f}mad"]
+    compose:
+      - LLVMLink: { name: "{type_kind.f}mad.{sve_type}" }
+
+  - name: svmla[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply-add, addend first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: ["{type_kind.f}mla"]
+    compose:
+      - LLVMLink: { name: "{type_kind.f}mla.{sve_type}" }
+
+  - name: svmla_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Multiply-add, addend first
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    types: [f32, f64]
+    assert_instr: [[fmla, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "fmla.lane.{sve_type}"
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmls[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply-subtract, minuend first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: ["{type_kind.f}mls"]
+    compose:
+      - LLVMLink: { name: "{type_kind.f}mls.{sve_type}" }
+
+  - name: svmls_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Multiply-subtract, minuend first
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    types: [f32, f64]
+    assert_instr: [[fmls, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "fmls.lane.{sve_type}"
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmsb[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Multiply-subtract, multiplicand first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: ["{type_kind.f}msb"]
+    compose:
+      - LLVMLink: { name: "{type_kind.f}msb.{sve_type}" }
+
+  - name: svnmad[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Negated multiply-add, multiplicand first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: [fnmad]
+    compose:
+      - LLVMLink: { name: "fnmad.{sve_type}" }
+
+  - name: svnmla[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Negated multiply-add, addend first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: [fnmla]
+    compose:
+      - LLVMLink: { name: "fnmla.{sve_type}" }
+
+  - name: svnmls[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Negated multiply-subtract, minuend first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: [fnmls]
+    compose:
+      - LLVMLink: { name: "fnmls.{sve_type}" }
+
+  - name: svnmsb[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Negated multiply-subtract, multiplicand first
+    arguments:
+      - "pg: {predicate}"
+      - "op1: {sve_type}"
+      - "op2: {sve_type}"
+      - "op3: {sve_type}"
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    n_variant_op: op3
+    assert_instr: [fnmsb]
+    compose:
+      - LLVMLink: { name: "fnmsb.{sve_type}" }
+
+  - name: svneg[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Negate
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64]
+    assert_instr: ["{type_kind.f}neg"]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "{type_kind.f}neg.{sve_type}" }
+
+  - name: svqadd[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating add
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.su}qadd"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qadd.x.{sve_type}" }
+
+  - name: svadr{size_literal[2]}[_{type[0]}base]_[{type[1]}]{index_or_offset}
+    attr: [*sve-unstable]
+    substitutions:
+      index_or_offset: { match_size: "{type[2]}", default: index, byte: offset }
+      indices_or_offsets:
+        { match_size: "{type[2]}", default: indices, byte: offsets }
+    doc: Compute vector addresses for {size[2]}-bit data
+    arguments: ["bases: {sve_type[0]}", "{indices_or_offsets}: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [u32, [i32, u32], [i8, i16, i32, i64]]
+      - [u64, [i64, u64], [i8, i16, i32, i64]]
+    assert_instr: [adr]
+    compose:
+      - LLVMLink: { name: "adr{size_literal[2]}.{sve_type[0]}" }
+
+  - name: svdot[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Dot product
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i32, i8]
+      - [i64, i16]
+      - [u32, u8]
+      - [u64, u16]
+    assert_instr: ["{type_kind[0].su}dot"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}dot.{sve_type[0]}" }
+
+  - name: svdot_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Dot product
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }]
+    types:
+      - [i32, i8]
+      - [i64, i16]
+      - [u32, u8]
+      - [u64, u16]
+    assert_instr: [["{type_kind[0].su}dot", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}dot.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "imm_index: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svusdot[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Dot product (unsigned × signed)
+    target_features: [i8mm]
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i32, u8, i8]]
+    assert_instr: [usdot]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "usdot.{sve_type[0]}" }
+
+  - name: svusdot_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Dot product (unsigned × signed)
+    target_features: [i8mm]
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }]
+    types: [[i32, u8, i8]]
+    assert_instr: [[usdot, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "usdot.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[2]}"
+            - "imm_index: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svsudot[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Dot product (signed × unsigned)
+    target_features: [i8mm]
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i32, i8, u8]]
+    assert_instr: [usdot]
+    n_variant_op: op3
+    compose:
+      - FnCall: ["svusdot_{type[0]}", [$op1, $op3, $op2]]
+
+  - name: svsudot_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Dot product (signed × unsigned)
+    target_features: [i8mm]
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }]
+    types: [[i32, i8, u8]]
+    assert_instr: [[sudot, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sudot.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[2]}"
+            - "imm_index: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svdiv[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Divide
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i32, i64, u32, u64]
+    assert_instr: ["{type_kind.fsu}div"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}div.{sve_type}" }
+
+  - name: svdivr[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Divide reversed
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i32, i64, u32, u64]
+    assert_instr: ["{type_kind.fsu}divr"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}divr.{sve_type}" }
+
+  - name: svexpa[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Floating-point exponential accelerator
+    arguments: ["op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f32, u32], [f64, u64]]
+    assert_instr: [fexpa]
+    compose:
+      - LLVMLink: { name: "fexpa.x.{sve_type[0]} " }
+
+  - name: svscale[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Adjust exponent
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f32, i32], [f64, i64]]
+    assert_instr: [fscale]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "fscale.{sve_type[0]}" }
+
+  - name: svmmla[_{type}]
+    attr: [*sve-unstable]
+    doc: Matrix multiply-accumulate
+    target_features: [f32mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32]
+    assert_instr: [fmmla]
+    compose:
+      - LLVMLink: { name: "fmmla.{sve_type}" }
+
+  - name: svmmla[_{type}]
+    attr: [*sve-unstable]
+    doc: Matrix multiply-accumulate
+    target_features: [f64mm]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f64]
+    assert_instr: [fmmla]
+    compose:
+      - LLVMLink: { name: "fmmla.{sve_type}" }
+
+  - name: svmmla[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Matrix multiply-accumulate
+    target_features: [i8mm]
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i32, i8], [u32, u8]]
+    assert_instr: ["{type_kind[0].su}mmla"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mmla.{sve_type[0]}" }
+
+  - name: svusmmla[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Matrix multiply-accumulate (unsigned × signed)
+    target_features: [i8mm]
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i32, u8, i8]]
+    assert_instr: [usmmla]
+    compose:
+      - LLVMLink: { name: "usmmla.{sve_type[0]}" }
+
+  - name: svmin[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Minimum
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind.fsu}min"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}min.{sve_type}" }
+
+  - name: svminnm[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Minimum number
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    zeroing_method: { select: op1 }
+    assert_instr: [fminnm]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "fminnm.{sve_type}" }
diff --git a/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml
new file mode 100644
index 0000000000..6365bea21b
--- /dev/null
+++ b/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml
@@ -0,0 +1,3196 @@
+arch_cfgs:
+  - arch_name: aarch64
+    target_feature: [sve, sve2]
+    llvm_prefix: llvm.aarch64.sve
+
+auto_llvm_sign_conversion: true
+generate_load_store_tests: true
+
+# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]`
+sve-unstable: &sve-unstable
+  FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']]
+
+intrinsics:
+  - name: svbext[{_n}_{type}]
+    attr: [*sve-unstable]
+    target_features: [sve2-bitperm]
+    doc: Gather lower bits from positions selected by bitmask
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8, u16, u32, u64]
+    assert_instr: [bext]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "bext.x.{sve_type}" }
+
+  - name: svbgrp[{_n}_{type}]
+    attr: [*sve-unstable]
+    target_features: [sve2-bitperm]
+    doc: Group bits to right or left as selected by bitmask
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8, u16, u32, u64]
+    assert_instr: [bgrp]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "bgrp.x.{sve_type}" }
+
+  - name: svbdep[{_n}_{type}]
+    attr: [*sve-unstable]
+    target_features: [sve2-bitperm]
+    doc: Scatter lower bits into positions selected by bitmask
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8, u16, u32, u64]
+    assert_instr: [bdep]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "bdep.x.{sve_type}" }
+
+  - name: svhistcnt[_{type[0]}]_z
+    attr: [*sve-unstable]
+    doc: Count matching elements
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[i32, u32], [i64, u64], [u32, u32], [u64, u64]]
+    assert_instr: [histcnt]
+    compose:
+      - LLVMLink: { name: "histcnt.{sve_type[0]}" }
+
+  - name: svhistseg[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Count matching elements in 128-bit segments
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[i8, u8], [u8, u8]]
+    assert_instr: [histseg]
+    compose:
+      - LLVMLink: { name: "histseg.{sve_type[0]}" }
+
+  - name: svmatch[_{type}]
+    attr: [*sve-unstable]
+    doc: Detect any matching elements
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [i8, i16, u8, u16]
+    assert_instr: [match]
+    compose:
+      - LLVMLink: { name: "match.{sve_type}" }
+
+  - name: svnmatch[_{type}]
+    attr: [*sve-unstable]
+    doc: Detect no matching elements
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{predicate}"
+    types: [i8, i16, u8, u16]
+    assert_instr: [nmatch]
+    compose:
+      - LLVMLink: { name: "nmatch.{sve_type}" }
+
+  - name: svhadd[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Halving add
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind.su}hadd"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}hadd.{sve_type}" }
+
+  - name: svrhadd[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Rounding halving add
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind.su}rhadd"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}rhadd.{sve_type}" }
+
+  - name: svaddhnb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add narrow high part (bottom)
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    return_type: "{sve_type[1]}"
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    assert_instr: [addhnb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "addhnb.{sve_type[0]}" }
+
+  - name: svaddhnt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add narrow high part (top)
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    return_type: "{sve_type[1]}"
+    arguments:
+      ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    assert_instr: [addhnt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "addhnt.{sve_type[0]}" }
+
+  - name: svraddhnb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Rounding add narrow high part (bottom)
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    return_type: "{sve_type[1]}"
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    assert_instr: [raddhnb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "raddhnb.{sve_type[0]}" }
+
+  - name: svraddhnt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Rounding add narrow high part (top)
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    return_type: "{sve_type[1]}"
+    arguments:
+      ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    assert_instr: [raddhnt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "raddhnt.{sve_type[0]}" }
+
+  - name: svcadd[_{type}]
+    attr: [*sve-unstable]
+    doc: Complex add with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }]
+    assert_instr: [[cadd, "IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: cadd.x.{sve_type}
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_ROTATION]]
+
+  - name: svcdot[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Complex dot product
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i32, i8], [i64, i16]]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }]
+    assert_instr: [[cdot, "IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: cdot.{sve_type[0]}
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]]
+
+  - name: svcdot_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Complex dot product
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i32, i8], [i64, i16]]
+    static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"]
+    constraints:
+      - { variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }
+      - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }
+    assert_instr: [[cdot, "IMM_INDEX = 0, IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: cdot.lane.{sve_type[0]}
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "imm_index: i32"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]]
+
+  - name: svcmla[_{type}]
+    attr: [*sve-unstable]
+    doc: Complex multiply-add with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }]
+    assert_instr: [[cmla, "IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: cmla.x.{sve_type}
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]]
+
+  - name: svcmla_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Complex multiply-add with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i16, i32, u16, u32]
+    static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"]
+    constraints:
+      - variable: IMM_INDEX
+        range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] }
+      - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }
+    assert_instr: [[cmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: cmla.lane.x.{sve_type}
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "imm_index: i32"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]]
+
+  - name: svqrdcmlah[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling complex multiply-add high with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }]
+    assert_instr: [[sqrdcmlah, "IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: sqrdcmlah.x.{sve_type}
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]]
+
+  - name: svqrdcmlah_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling complex multiply-add high with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i16, i32]
+    static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"]
+    constraints:
+      - variable: IMM_INDEX
+        range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] }
+      - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }
+    assert_instr: [[sqrdcmlah, "IMM_INDEX = 0, IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: sqrdcmlah.lane.x.{sve_type}
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "imm_index: i32"
+            - "imm_rotation: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]]
+
+  - name: svqcadd[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating complex add with rotate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    static_defs: ["const IMM_ROTATION: i32"]
+    constraints: [{ variable: "IMM_ROTATION", any_values: [90, 270] }]
+    assert_instr: [[sqcadd, "IMM_ROTATION = 90"]]
+    compose:
+      - LLVMLink:
+          name: "sqcadd.x.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"]
+      - FnCall: ["{llvm_link}", ["$op1", "$op2", "$IMM_ROTATION"]]
+
+  - name: svsublb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}sublb"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}sublb.{sve_type[0]}"
+
+  - name: svsublbt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract long (bottom - top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+    assert_instr: [ssublbt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink:
+          name: "ssublbt.{sve_type[0]}"
+
+  - name: svsublt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}sublt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}sublt.{sve_type[0]}" }
+
+  - name: svsubltb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract long (top - bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+    assert_instr: [ssubltb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink:
+          name: "ssubltb.{sve_type[0]}"
+
+  - name: svsubwb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract wide (bottom)
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}subwb"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}subwb.{sve_type[0]}" }
+
+  - name: svsubwt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract wide (top)
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}subwt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}subwt.{sve_type[0]}" }
+
+  - name: svrsubhnb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Rounding subtract narrow high part (bottom)
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [rsubhnb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "rsubhnb.{sve_type[0]}" }
+
+  - name: svrsubhnt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Rounding subtract narrow high part (top)
+    arguments:
+      ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [rsubhnt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "rsubhnt.{sve_type[0]}" }
+
+  - name: svsubhnb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract narrow high part (bottom)
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [subhnb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "subhnb.{sve_type[0]}" }
+
+  - name: svsubhnt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Subtract narrow high part (top)
+    arguments:
+      ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [subhnt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "subhnt.{sve_type[0]}" }
+
+  - name: svsbclb[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Subtract with borrow long (bottom)
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32, u64]
+    assert_instr: [sbclb]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sbclb.{sve_type}" }
+
+  - name: svsbclt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Subtract with borrow long (top)
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32, u64]
+    assert_instr: [sbclt]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sbclt.{sve_type}" }
+
+  - name: svqsub[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating subtract
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind.su}qsub"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qsub.{sve_type}" }
+
+  - name: svqsubr[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating subtract reversed
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    zeroing_method: { select: op1 }
+    assert_instr: ["{type_kind.su}qsubr"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qsubr.{sve_type}" }
+
+  - name: svhsub[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Halving subtract
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.su}hsub"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}hsub.{sve_type}" }
+
+  - name: svhsubr[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Halving subtract reversed
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.su}hsub"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}hsubr.{sve_type}" }
+
+  - name: svwhilege_{sve_type[1]}[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: While decrementing scalar is greater than or equal to
+    arguments: ["op1: {type[0]}", "op2: {type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]]
+    assert_instr: [{ default: whilege, unsigned: whilehs }]
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default: { LLVMLink: { name: "whilege.{sve_type[1]}.{type[0]}" } }
+            unsigned: { LLVMLink: { name: "whilehs.{sve_type[1]}.{type[0]}" } }
+
+  - name: svwhilegt_{sve_type[1]}[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: While decrementing scalar is greater than
+    arguments: ["op1: {type[0]}", "op2: {type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]]
+    assert_instr: [{ default: whilegt, unsigned: whilehi }]
+    compose:
+      - MatchKind:
+          - "{type[0]}"
+          - default: { LLVMLink: { name: "whilegt.{sve_type[1]}.{type[0]}" } }
+            unsigned: { LLVMLink: { name: "whilehi.{sve_type[1]}.{type[0]}" } }
+
+  - name: svwhilerw_{size}ptr
+    attr: [*sve-unstable]
+    safety:
+      unsafe: []
+    visibility: private
+    static_defs: [T]
+    substitutions:
+      size_alt:
+        match_size: "{type}"
+        byte: b
+        halfword: h
+        default: s
+        doubleword: d
+    arguments: ["op1: *T", "op2: *T"]
+    return_type: "{predicate}"
+    types: [i8, i16, i32, i64]
+    assert_instr: []
+    compose:
+      - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]]
+      - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]]
+      - LLVMLink:
+          name: "whilerw.{size_alt}.{predicate}.p0"
+          arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"]
+
+  - name: svwhilerw[_{type}]
+    attr: [*sve-unstable]
+    doc: While free of read-after-write conflicts
+    # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't
+    # seem to be documented, so we conservatively keep this unsafe for now.
+    safety:
+      unsafe:
+      - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints
+        must be met for at least the base pointers, `op1` and `op2`."
+    arguments: ["op1: *{type}", "op2: *{type}"]
+    return_type: "svbool_t"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [whilerw]
+    compose:
+      - FnCall:
+          - "svwhilerw_{size}ptr"
+          - - $op1
+            - $op2
+          - - Type: "{type}"
+
+  - name: svwhilewr_{size}ptr
+    attr: [*sve-unstable]
+    safety:
+      unsafe: []
+    visibility: private
+    static_defs: [T]
+    substitutions:
+      size_alt:
+        match_size: "{type}"
+        byte: b
+        halfword: h
+        default: s
+        doubleword: d
+    arguments: ["op1: *T", "op2: *T"]
+    return_type: "{predicate}"
+    types: [i8, i16, i32, i64]
+    assert_instr: []
+    compose:
+      - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]]
+      - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]]
+      - LLVMLink:
+          name: "whilewr.{size_alt}.{predicate}.p0"
+          arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"]
+
+  - name: svwhilewr[_{type}]
+    attr: [*sve-unstable]
+    doc: While free of write-after-read conflicts
+    # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't
+    # seem to be documented, so we conservatively keep this unsafe for now.
+    safety:
+      unsafe:
+      - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints
+        must be met for at least the base pointers, `op1` and `op2`."
+    arguments: ["op1: *{type}", "op2: *{type}"]
+    return_type: "svbool_t"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [whilewr]
+    compose:
+      - FnCall:
+          - "svwhilewr_{size}ptr"
+          - - $op1
+            - $op2
+          - - Type: "{type}"
+
+  - name: svtbl2[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Table lookup in two-vector table
+    arguments: ["data: {sve_type_x2[0]}", "indices: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [f32, u32]
+      - [f64, u64]
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+      - [u8, u8]
+      - [u16, u16]
+      - [u32, u32]
+      - [u64, u64]
+    assert_instr: [tbl]
+    compose:
+      - LLVMLink:
+          name: "tbl2.{sve_type[0]}"
+          arguments:
+            - "data0: {sve_type[0]}"
+            - "data1: {sve_type[0]}"
+            - "indices: {sve_type[1]}"
+      - FnCall:
+          - "{llvm_link}"
+          - - FnCall: ["svget2_{type[0]}", ["$data"], [0]]
+            - FnCall: ["svget2_{type[0]}", ["$data"], [1]]
+            - $indices
+
+  - name: svtbx[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Table lookup in single-vector table (merging)
+    arguments:
+      - "fallback: {sve_type[0]}"
+      - "data: {sve_type[0]}"
+      - "indices: {sve_type[1]}"
+    return_type: "{sve_type[0]}"
+    types:
+      - [f32, u32]
+      - [f64, u64]
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+      - [u8, u8]
+      - [u16, u16]
+      - [u32, u32]
+      - [u64, u64]
+    assert_instr: [tbx]
+    compose:
+      - LLVMLink: { name: "tbx.{sve_type[0]}" }
+
+  - name: svcvtlt_{type[0]}[_{type[1]}]_m
+    attr: [*sve-unstable]
+    doc: Up convert long (top)
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f64, f32]]
+    assert_instr: [fcvtlt]
+    compose:
+      - LLVMLink: { name: "fcvtlt.{type[0]}{type[1]}" }
+
+  - name: svcvtlt_{type[0]}[_{type[1]}]_x
+    attr: [*sve-unstable]
+    doc: Up convert long (top)
+    arguments: ["pg: svbool_t", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f64, f32]]
+    assert_instr: [fcvtlt]
+    compose:
+      - FnCall:
+        - "svcvtlt_{type[0]}_{type[1]}_m"
+        - - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true]
+          - $pg
+          - $op
+
+  - name: svcvtnt_{type[0]}[_{type[1]}]{_mx}
+    attr: [*sve-unstable]
+    doc: Down convert and narrow (top)
+    arguments:
+      ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f32, f64]]
+    assert_instr: [fcvtnt]
+    compose:
+      - LLVMLink: { name: "fcvtnt.{type[0]}{type[1]}" }
+
+  - name: svcvtx_{type[0]}[_{type[1]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Down convert, rounding to odd
+    arguments:
+      ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f32, f64]]
+    zeroing_method: { drop: inactive }
+    assert_instr: [fcvtx]
+    compose:
+      - LLVMLink: { name: "fcvtx.{type[0]}{type[1]}" }
+
+  - name: svcvtxnt_{type[0]}[_{type[1]}]{_mx}
+    attr: [*sve-unstable]
+    doc: Down convert, rounding to odd (top)
+    arguments:
+      ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[f32, f64]]
+    assert_instr: [fcvtxnt]
+    compose:
+      - LLVMLink: { name: "fcvtxnt.{type[0]}{type[1]}" }
+
+  - name: svldnt1_gather_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["ldnt1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink: { name: "ldnt1.gather.index.{sve_type[1]}" }
+
+  - name: svldnt1_gather_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["ldnt1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink: { name: "ldnt1.gather.uxtw.{sve_type[1]}" }
+            doubleword:
+              LLVMLink: { name: "ldnt1.gather.{sve_type[1]}" }
+
+  - name: svldnt1_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ldnt1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - LLVMLink:
+          name: "ldnt1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}"
+
+  - name: svldnt1_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ldnt1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldnt1_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svldnt1_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Unextended load, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["ldnt1{size_literal[0]}"]
+    test: { load: 1 }
+    compose:
+      - FnCall:
+          - "svldnt1_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]]
+
+  - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i64, u64], [i64, u64], [i16, i32]]
+    assert_instr: ["ldnt1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base, $indices]]
+
+  - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [[i64, u64], [u64, i64], [u16, u32]]
+    assert_instr: ["ldnt1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base, $indices]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [[i64, u64], [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ldnt1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ldnt1.gather.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]]
+
+  - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [u32, i32], [u8, u16]]
+      - [[i64, u64], [u64, i64], [u8, u16, u32]]
+    assert_instr: ["ldnt1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+            doubleword:
+              LLVMLink:
+                name: "ldnt1.gather.{sve_type[1] as {type[2]}}"
+                return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ldnt1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]]
+
+  - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [u32, i32], [u8, u16]]
+      - [u64, [u64, i64], [u8, u16, u32]]
+    assert_instr: ["ldnt1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - LLVMLink:
+          name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          return_type: "{sve_type[1] as {type[2]}}"
+      - FnCall:
+          - "crate::intrinsics::simd::simd_cast"
+          - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]]
+          - - Type: "{sve_type[1] as {type[2]}}"
+            - _
+
+  - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["ldnt1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [u8, u16]]
+      - [u64, [i64, u64], [u8, u16, u32]]
+    assert_instr: ["ldnt1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+
+  - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and sign-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], u16]
+      - [u64, [i64, u64], [u16, u32]]
+    assert_instr: ["ldnt1s{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+
+  - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]}
+    attr: [*sve-unstable]
+    doc: Load {size[2]}-bit data and zero-extend, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [u32, [i32, u32], u16]
+      - [u64, [i64, u64], [u16, u32]]
+    assert_instr: ["ldnt1{size_literal[2]}"]
+    test: { load: 2 }
+    compose:
+      - FnCall:
+          - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+
+  - name: svstnt1_scatter_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[1]}"
+      - "indices: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["stnt1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - LLVMLink:
+          name: "stnt1.scatter.index.{sve_type[1]}"
+          arguments:
+            - "data: {sve_type[1]}"
+            - "pg: {predicate[0]}"
+            - "base: *mut {type[1]}"
+            - "indices: {sve_type[0]}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]]
+
+  - name: svstnt1_scatter_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[1]}"
+      - "offsets: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [[i64, u64], [f64, i64, u64]]
+    assert_instr: ["stnt1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "stnt1.scatter.uxtw.{sve_type[1]}"
+                arguments:
+                  - "data: {sve_type[1]}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[1]}"
+                  - "offsets: {sve_type[0]}"
+            doubleword:
+              LLVMLink:
+                name: "stnt1.scatter.{sve_type[1]}"
+                arguments:
+                  - "data: {sve_type[1]}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[1]}"
+                  - "offsets: {sve_type[0]}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]]
+
+  - name: svstnt1_scatter[_{type[0]}base]_offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "offset: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["stnt1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - LLVMLink:
+          arguments:
+            - "data: {sve_type[1]}"
+            - "pg: {predicate[0]}"
+            - "bases: {sve_type[0]}"
+            - "offset: i64"
+          name: "stnt1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}"
+      - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]]
+
+  - name: svstnt1_scatter[_{type[0]}base_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"]
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["stnt1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - FnCall:
+          - "svstnt1_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+            - $data
+
+  - name: svstnt1_scatter[_{type[0]}base]_index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Non-truncating store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "index: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [f32, i32, u32]]
+      - [u64, [f64, i64, u64]]
+    assert_instr: ["stnt1{size_literal[0]}"]
+    test: { store: 1 }
+    compose:
+      - FnCall:
+          - "svstnt1_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]]
+            - $data
+
+  - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[2]}"
+      - "indices: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [[i64, u64], i64, [i16, i32]]
+      - [[i64, u64], u64, [u16, u32]]
+    assert_instr: ["stnt1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - LLVMLink:
+          name: "stnt1.scatter.index.{sve_type[1] as {type[2]}}"
+          arguments:
+            - "data: {sve_type[1] as {type[2]}}"
+            - "pg: {predicate[0]}"
+            - "base: *mut {type[2]}"
+            - "indices: {sve_type[0]}"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices]
+
+  - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "base: *mut {type[2]}"
+      - "offsets: {sve_type[0]}"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, i32, [i8, i16]]
+      - [u32, u32, [u8, u16]]
+      - [[i64, u64], i64, [i8, i16, i32]]
+      - [[i64, u64], u64, [u8, u16, u32]]
+    assert_instr: ["stnt1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - MatchSize:
+          - "{type[0]}"
+          - default:
+              LLVMLink:
+                name: "stnt1.scatter.uxtw.{sve_type[1] as {type[2]}}"
+                arguments:
+                  - "data: {sve_type[1] as {type[2]}}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[2]}"
+                  - "offsets: {sve_type[0]}"
+            doubleword:
+              LLVMLink:
+                name: "stnt1.scatter.{sve_type[1] as {type[2]}}"
+                arguments:
+                  - "data: {sve_type[1] as {type[2]}}"
+                  - "pg: {predicate[0]}"
+                  - "base: *mut {type[2]}"
+                  - "offsets: {sve_type[0]}"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets]
+
+  - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "offset: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["stnt1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - LLVMLink:
+          name: "stnt1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}"
+          arguments:
+            - "data: {sve_type[1] as {type[2]}}"
+            - "pg: {predicate[0]}"
+            - "bases: {sve_type[0]}"
+            - "offset: i64"
+      - FnCall:
+          - "{llvm_link}"
+          - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset]
+
+  - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments:
+      ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"]
+    types:
+      - [u32, [i32, u32], [i8, i16]]
+      - [u64, [i64, u64], [i8, i16, i32]]
+    assert_instr: ["stnt1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - FnCall:
+          - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - 0
+            - $data
+
+  - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}]
+    attr: [*sve-unstable]
+    doc: Truncate to {size[2]} bits and store, non-temporal
+    safety:
+      unsafe:
+        - pointer_offset: predicated
+        - dereference: predicated
+        - no_provenance: bases
+        - non_temporal
+    arguments:
+      - "pg: {predicate[0]}"
+      - "bases: {sve_type[0]}"
+      - "index: i64"
+      - "data: {sve_type[1]}"
+    types:
+      - [u32, [i32, u32], i16]
+      - [u64, [i64, u64], [i16, i32]]
+    assert_instr: ["stnt1{size_literal[2]}"]
+    test: { store: 2 }
+    compose:
+      - FnCall:
+          - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}"
+          - - $pg
+            - $bases
+            - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]]
+            - $data
+
+  - name: svaba[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Absolute difference and accumulate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind}aba"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind}aba.{sve_type}" }
+
+  - name: svqabs[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating absolute value
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    assert_instr: [sqabs]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "sqabs.{sve_type}" }
+
+  - name: svabdlb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Absolute difference long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}abdlb"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}abdlb.{sve_type[0]}" }
+
+  - name: svabdlt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Absolute difference long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}abdlt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}abdlt.{sve_type[0]}" }
+
+  - name: svabalb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Absolute difference long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}abalb"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}abalb.{sve_type[0]}" }
+
+  - name: svabalt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Absolute difference long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}abalt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}abalt.{sve_type[0]}" }
+
+  - name: svbcax[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise clear and exclusive OR
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [bcax]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "bcax.{sve_type}" }
+
+  - name: sveorbt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Interleaving exclusive OR (bottom, top)
+    arguments: ["odd: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [eorbt]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "eorbt.{sve_type}" }
+
+  - name: sveortb[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Interleaving exclusive OR (top, bottom)
+    arguments: ["even: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [eortb]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "eortb.{sve_type}" }
+
+  - name: sveor3[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise exclusive OR of three vectors
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [eor3]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "eor3.{sve_type}" }
+
+  - name: svbsl[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise select
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [bsl]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "bsl.{sve_type}" }
+
+  - name: svbsl1n[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise select with first input inverted
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [bsl1n]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "bsl1n.{sve_type}" }
+
+  - name: svbsl2n[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise select with second input inverted
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [bsl2n]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "bsl2n.{sve_type}" }
+
+  - name: svnbsl[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise select
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [nbsl]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "nbsl.{sve_type}" }
+
+  - name: svxar[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise exclusive OR and rotate right
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, range: ["1", "{size}"] }]
+    assert_instr: [[xar, "IMM3 = 1"]]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    compose:
+      - LLVMLink:
+          name: "xar.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]]
+
+  - name: svrax1[_{type}]
+    attr: [*sve-unstable]
+    doc: Bitwise rotate left by 1 and exclusive OR
+    target_features: [sve2-sha3]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    assert_instr: [rax1]
+    types: [i64, u64]
+    compose:
+      - LLVMLink: { name: "rax1" }
+
+  - name: svshllb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Shift left long (bottom)
+    arguments: ["op1: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [["{type_kind[0].su}shllb", "IMM2 = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}shllb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[1]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svshllt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Shift left long (top)
+    arguments: ["op1: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [["{type_kind[0].su}shllt", "IMM2 = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}shllt.{sve_type[0]}"
+          arguments: ["op1: {sve_type[1]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svrshl[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Rounding shift left
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i8, u8], i8]
+      - [[i16, u16], i16]
+      - [[i32, u32], i32]
+      - [[i64, u64], i64]
+    assert_instr: ["{type_kind[0].su}rshl"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}rshl.{sve_type[0]}" }
+
+  - name: svqrshl[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating rounding shift left
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i8, u8], i8]
+      - [[i16, u16], i16]
+      - [[i32, u32], i32]
+      - [[i64, u64], i64]
+    assert_instr: ["{type_kind[0].su}qrshl"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}qrshl.{sve_type[0]}" }
+
+  - name: svqshl[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating shift left
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [[i8, u8], i8]
+      - [[i16, u16], i16]
+      - [[i32, u32], i32]
+      - [[i64, u64], i64]
+    assert_instr: ["{type_kind[0].su}qshl"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}qshl.{sve_type[0]}" }
+
+  - name: svqshlu[_n_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating shift left unsigned
+    arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }]
+    types:
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+    assert_instr: [[sqshlu, "IMM2 = 0"]]
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink:
+          name: "sqshlu.{sve_type[0]}"
+          arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]]
+
+  - name: svsli[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Shift left and insert
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, range: ["0", "{size_minus_one}"] }]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [[sli, "IMM3 = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sli.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]]
+
+  - name: svrshr[_n_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Rounding shift right
+    arguments: ["pg: {predicate}", "op1: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size}"] }]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [["{type_kind.su}rshr", "IMM2 = 1"]]
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink:
+          name: "{type_kind.su}rshr.{sve_type}"
+          arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]]
+
+  - name: svrsra[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Rounding shift right and accumulate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, range: ["1", "{size}"] }]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [["{type_kind.su}rsra", "IMM3 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind.su}rsra.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]]
+
+  - name: svrshrnb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Rounding shift right narrow (bottom)
+    arguments: ["op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [[rshrnb, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "rshrnb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svrshrnt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Rounding shift right narrow (top)
+    arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [[rshrnt, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "rshrnt.{sve_type[0]}"
+          arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]]
+
+  - name: svqrshrnb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding shift right narrow (bottom)
+    arguments: ["op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [["{type_kind[0].su}qrshrnb", "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}qrshrnb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svqrshrnt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding shift right narrow (top)
+    arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [["{type_kind[0].su}qrshrnt", "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}qrshrnt.{sve_type[0]}"
+          arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]]
+
+  - name: svqrshrunb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding shift right unsigned narrow (bottom)
+    arguments: ["op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, u8]
+      - [i32, u16]
+      - [i64, u32]
+    assert_instr: [[sqrshrunb, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "sqrshrunb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svqrshrunt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding shift right unsigned narrow (top)
+    arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, u8]
+      - [i32, u16]
+      - [i64, u32]
+    assert_instr: [[sqrshrunt, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "sqrshrunt.{sve_type[0]}"
+          arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]]
+
+  - name: svqshrnb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating shift right narrow (bottom)
+    arguments: ["op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [["{type_kind[0].su}qshrnb", "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}qshrnb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svqshrnt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating shift right narrow (top)
+    arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [["{type_kind[0].su}qshrnt", "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}qshrnt.{sve_type[0]}"
+          arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]]
+
+  - name: svqshrunb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating shift right unsigned narrow (bottom)
+    arguments: ["op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, u8]
+      - [i32, u16]
+      - [i64, u32]
+    assert_instr: [[sqshrunb, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "sqshrunb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svqshrunt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating shift right unsigned narrow (top)
+    arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, u8]
+      - [i32, u16]
+      - [i64, u32]
+    assert_instr: [[sqshrunt, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "sqshrunt.{sve_type[0]}"
+          arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]]
+
+  - name: svsra[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Shift right and accumulate
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, range: ["1", "{size}"] }]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [["{type_kind.su}sra", "IMM3 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind.su}sra.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]]
+
+  - name: svsri[_n_{type}]
+    attr: [*sve-unstable]
+    doc: Shift right and insert
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM3: i32"]
+    constraints: [{ variable: IMM3, range: ["1", "{size}"] }]
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: [[sri, "IMM3 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "sri.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]]
+
+  - name: svshrnb[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Shift right narrow (bottom)
+    arguments: ["op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [[shrnb, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "shrnb.{sve_type[0]}"
+          arguments: ["op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $IMM2]]
+
+  - name: svshrnt[_n_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Shift right narrow (top)
+    arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    static_defs: ["const IMM2: i32"]
+    constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }]
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: [[shrnt, "IMM2 = 1"]]
+    compose:
+      - LLVMLink:
+          name: "shrnt.{sve_type[0]}"
+          arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"]
+      - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]]
+
+  - name: svqxtnb[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating extract narrow (bottom)
+    arguments: ["op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}qxtnb"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}qxtnb.{sve_type[0]}" }
+
+  - name: svqxtnt[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating extract narrow (top)
+    arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}qxtnt"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}qxtnt.{sve_type[0]}" }
+
+  - name: svqxtunb[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating extract unsigned narrow (bottom)
+    arguments: ["op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, u8]
+      - [i32, u16]
+      - [i64, u32]
+    assert_instr: [sqxtunb]
+    compose:
+      - LLVMLink: { name: "sqxtunb.{sve_type[0]}" }
+
+  - name: svqxtunt[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating extract unsigned narrow (top)
+    arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types:
+      - [i16, u8]
+      - [i32, u16]
+      - [i64, u32]
+    assert_instr: [sqxtunt]
+    compose:
+      - LLVMLink: { name: "sqxtunt.{sve_type[0]}" }
+
+  - name: svmovlb[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Move long (bottom)
+    arguments: ["op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}shllb"]
+    compose:
+      - FnCall: ["svshllb_n_{type[0]}", [$op], [0]]
+
+  - name: svmovlt[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Move long (top)
+    arguments: ["op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}shllt"]
+    compose:
+      - FnCall: ["svshllt_n_{type[0]}", [$op], [0]]
+
+  - name: svunpkhi[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Unpack and extend high half
+    arguments: ["op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}unpkhi"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}unpkhi.{sve_type[0]}" }
+
+  - name: svunpkhi[_b]
+    attr: [*sve-unstable]
+    doc: Unpack and extend high half
+    arguments: ["op: svbool_t"]
+    return_type: "svbool8_t"
+    assert_instr: [punpkhi]
+    compose:
+      - LLVMLink: { name: "punpkhi.nxv16i1" }
+
+  - name: svunpklo[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Unpack and extend low half
+    arguments: ["op: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}unpklo"]
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}unpklo.{sve_type[0]}" }
+
+  - name: svunpklo[_b]
+    attr: [*sve-unstable]
+    doc: Unpack and extend low half
+    arguments: ["op: svbool_t"]
+    return_type: "svbool8_t"
+    assert_instr: [punpklo]
+    compose:
+      - LLVMLink: { name: "punpklo.nxv16i1" }
+
+  - name: svaddp[_{type}]{_mx}
+    attr: [*sve-unstable]
+    doc: Add pairwise
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.f}addp"]
+    compose:
+      - LLVMLink: { name: "{type_kind.f}addp.{sve_type}" }
+
+  - name: svadalp[_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Add and accumulate long pairwise
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}adalp"]
+    zeroing_method: { select: op1 }
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}adalp.{sve_type[0]}" }
+
+  - name: svmaxp[_{type}]{_mx}
+    attr: [*sve-unstable]
+    doc: Maximum pairwise
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.fsu}maxp"]
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}maxp.{sve_type}" }
+
+  - name: svmaxnmp[_{type}]{_mx}
+    attr: [*sve-unstable]
+    doc: Maximum number pairwise
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: ["fmaxnmp"]
+    compose:
+      - LLVMLink: { name: "fmaxnmp.{sve_type}" }
+
+  - name: svminp[_{type}]{_mx}
+    attr: [*sve-unstable]
+    doc: Minimum pairwise
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.fsu}minp"]
+    compose:
+      - LLVMLink: { name: "{type_kind.fsu}minp.{sve_type}" }
+
+  - name: svminnmp[_{type}]{_mx}
+    attr: [*sve-unstable]
+    doc: Minimum number pairwise
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [f32, f64]
+    assert_instr: ["fminnmp"]
+    compose:
+      - LLVMLink: { name: "fminnmp.{sve_type}" }
+
+  - name: svmul_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Multiply
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    assert_instr: [["{type_kind.f}mul", "IMM_INDEX = 0"]]
+    types: [f32, f64, i16, i32, i64, u16, u32, u64]
+    compose:
+      - LLVMLink:
+          name: "{type_kind.f}mul.lane.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]]
+
+  - name: svqdmulh[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    assert_instr: [sqdmulh]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "sqdmulh.{sve_type}" }
+
+  - name: svqdmulh_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    assert_instr: [["sqdmulh", "IMM_INDEX = 0"]]
+    types: [i16, i32, i64]
+    compose:
+      - LLVMLink:
+          name: "sqdmulh.lane.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]]
+
+  - name: svqrdmulh[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling multiply high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    assert_instr: [sqrdmulh]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "sqrdmulh.{sve_type}" }
+
+  - name: svqrdmulh_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling multiply high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    assert_instr: [["sqrdmulh", "IMM_INDEX = 0"]]
+    types: [i16, i32, i64]
+    compose:
+      - LLVMLink:
+          name: "sqrdmulh.lane.{sve_type}"
+          arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]]
+
+  - name: svqdmullb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: [sqdmullb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "sqdmullb.{sve_type[0]}" }
+
+  - name: svqdmullb_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    assert_instr: [["sqdmullb", "IMM_INDEX = 0"]]
+    types: [[i32, i16], [i64, i32]]
+    compose:
+      - LLVMLink:
+          name: "sqdmullb.lane.{sve_type[0]}"
+          arguments:
+            ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]]
+
+  - name: svqdmullt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: [sqdmullt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "sqdmullt.{sve_type[0]}" }
+
+  - name: svqdmullt_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    assert_instr: [["sqdmullt", "IMM_INDEX = 0"]]
+    types: [[i32, i16], [i64, i32]]
+    compose:
+      - LLVMLink:
+          name: "sqdmullt.lane.{sve_type[0]}"
+          arguments:
+            ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]]
+
+  - name: svmullb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}mullb"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mullb.{sve_type[0]}" }
+
+  - name: svmullb_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i32, i16]
+      - [i64, i32]
+      - [u32, u16]
+      - [u64, u32]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    assert_instr: [["{type_kind[0].su}mullb", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}mullb.lane.{sve_type[0]}"
+          arguments:
+            ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]]
+
+  - name: svmullt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}mullt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mullt.{sve_type[0]}" }
+
+  - name: svmullt_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i32, i16]
+      - [i64, i32]
+      - [u32, u16]
+      - [u64, u32]
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    assert_instr: [["{type_kind[0].su}mullt", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}mullt.lane.{sve_type[0]}"
+          arguments:
+            ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"]
+      - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]]
+
+  - name: svrecpe[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reciprocal estimate
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32]
+    assert_instr: [urecpe]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "urecpe.{sve_type}" }
+
+  - name: svrsqrte[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Reciprocal square root estimate
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32]
+    assert_instr: [ursqrte]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "ursqrte.{sve_type}" }
+
+  - name: svmla_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Multiply-add, addend first
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    types: [i16, i32, i64, u16, u32, u64]
+    assert_instr: [[mla, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "mla.lane.{sve_type}"
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmls_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Multiply-subtract, minuend first
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    types: [i16, i32, i64, u16, u32, u64]
+    assert_instr: [[mls, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "mls.lane.{sve_type}"
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmlalb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-add long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    assert_instr: ["{type_kind[0].su}mlalb"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mlalb.{sve_type[0]}" }
+
+  - name: svmlalb_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-add long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]]
+    assert_instr: [["{type_kind[0].su}mlalb", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}mlalb.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmlalt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-add long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    assert_instr: ["{type_kind[0].su}mlalt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mlalt.{sve_type[0]}" }
+
+  - name: svmlalt_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-add long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]]
+    assert_instr: [["{type_kind[0].su}mlalt", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}mlalt.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmlslb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-subtract long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    assert_instr: ["{type_kind[0].su}mlslb"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mlslb.{sve_type[0]}" }
+
+  - name: svmlslb_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-subtract long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]]
+    assert_instr: [["{type_kind[0].su}mlslb", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}mlslb.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svmlslt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-subtract long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]]
+    assert_instr: ["{type_kind[0].su}mlslt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}mlslt.{sve_type[0]}" }
+
+  - name: svmlslt_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Multiply-subtract long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]]
+    assert_instr: [["{type_kind[0].su}mlslt", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "{type_kind[0].su}mlslt.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqrdmlah[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling multiply-add high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    assert_instr: [sqrdmlah]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqrdmlah.{sve_type}" }
+
+  - name: svqrdmlah_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling multiply-add high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    types: [i16, i32, i64]
+    assert_instr: [[sqrdmlah, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sqrdmlah.lane.{sve_type}"
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqrdmlsh[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling multiply-subtract high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    assert_instr: [sqrdmlsh]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqrdmlsh.{sve_type}" }
+
+  - name: svqrdmlsh_lane[_{type}]
+    attr: [*sve-unstable]
+    doc: Saturating rounding doubling multiply-subtract high
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }]
+    types: [i16, i32, i64]
+    assert_instr: [[sqrdmlsh, "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sqrdmlsh.lane.{sve_type}"
+          arguments:
+            - "op1: {sve_type}"
+            - "op2: {sve_type}"
+            - "op3: {sve_type}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqdmlalb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-add long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: ["sqdmlalb"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqdmlalb.{sve_type[0]}" }
+
+  - name: svqdmlalb_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-add long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32]]
+    assert_instr: [["sqdmlalb", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sqdmlalb.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqdmlalbt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-add long (bottom × top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: ["sqdmlalbt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqdmlalbt.{sve_type[0]}" }
+
+  - name: svqdmlalt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-add long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: ["sqdmlalt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqdmlalt.{sve_type[0]}" }
+
+  - name: svqdmlalt_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-add long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32]]
+    assert_instr: [["sqdmlalt", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sqdmlalt.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqdmlslb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-subtract long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: ["sqdmlslb"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqdmlslb.{sve_type[0]}" }
+
+  - name: svqdmlslb_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-subtract long (bottom)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32]]
+    assert_instr: [["sqdmlslb", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sqdmlslb.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqdmlslbt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-subtract long (bottom × top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: ["sqdmlslbt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqdmlslbt.{sve_type[0]}" }
+
+  - name: svqdmlslt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-subtract long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[i16, i8], [i32, i16], [i64, i32]]
+    assert_instr: ["sqdmlslt"]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "sqdmlslt.{sve_type[0]}" }
+
+  - name: svqdmlslt_lane[_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Saturating doubling multiply-subtract long (top)
+    arguments:
+      ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    static_defs: ["const IMM_INDEX: i32"]
+    constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
+    types: [[i32, i16], [i64, i32]]
+    assert_instr: [["sqdmlslt", "IMM_INDEX = 0"]]
+    compose:
+      - LLVMLink:
+          name: "sqdmlslt.lane.{sve_type[0]}"
+          arguments:
+            - "op1: {sve_type[0]}"
+            - "op2: {sve_type[1]}"
+            - "op3: {sve_type[1]}"
+            - "IMM_INDEX: i32"
+      - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]]
+
+  - name: svqneg[_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating negate
+    arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64]
+    assert_instr: [sqneg]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "sqneg.{sve_type}" }
+
+  - name: svadclb[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Add with carry long (bottom)
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32, u64]
+    assert_instr: [adclb]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "adclb.{sve_type}" }
+
+  - name: svadclt[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Add with carry long (top)
+    arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32, u64]
+    assert_instr: [adclt]
+    n_variant_op: op3
+    compose:
+      - LLVMLink: { name: "adclt.{sve_type}" }
+
+  - name: svqadd[{_n}_{type}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating add
+    arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [i8, i16, i32, i64, u8, u16, u32, u64]
+    assert_instr: ["{type_kind.su}qadd"]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind.su}qadd.{sve_type}" }
+
+  - name: svsqadd[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating add with signed addend
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [u8, i8]
+      - [u16, i16]
+      - [u32, i32]
+      - [u64, i64]
+    assert_instr: [usqadd]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "usqadd.{sve_type[0]}" }
+
+  - name: svuqadd[{_n}_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Saturating add with unsigned addend
+    arguments:
+      ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i8, u8]
+      - [i16, u16]
+      - [i32, u32]
+      - [i64, u64]
+    assert_instr: [suqadd]
+    zeroing_method: { select: op1 }
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "suqadd.{sve_type[0]}" }
+
+  - name: svaddlb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add long (bottom)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}addlb"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}addlb.{sve_type[0]}" }
+
+  - name: svaddlbt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add long (bottom + top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+    assert_instr: ["{type_kind[0].su}addlbt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}addlbt.{sve_type[0]}" }
+
+  - name: svaddlt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add long (top)
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}addlt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}addlt.{sve_type[0]}" }
+
+  - name: svaddwb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add wide (bottom)
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}addwb"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}addwb.{sve_type[0]}" }
+
+  - name: svaddwt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Add wide (top)
+    arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types:
+      - [i16, i8]
+      - [i32, i16]
+      - [i64, i32]
+      - [u16, u8]
+      - [u32, u16]
+      - [u64, u32]
+    assert_instr: ["{type_kind[0].su}addwt"]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "{type_kind[0].su}addwt.{sve_type[0]}" }
+
+  - name: svlogb[_{type[0]}]{_mxz}
+    attr: [*sve-unstable]
+    doc: Base 2 logarithm as integer
+    arguments:
+      ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"]
+    return_type: "{sve_type[1]}"
+    types: [[f32, i32], [f64, i64]]
+    assert_instr: [flogb]
+    zeroing_method: { drop: inactive }
+    compose:
+      - LLVMLink: { name: "flogb.{sve_type[0]}" }
+
+  - name: svpmul[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Polynomial multiply
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8]
+    assert_instr: [pmul]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "pmul.{sve_type}" }
+
+  - name: svpmullb_pair[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Polynomial multiply long (bottom)
+    target_features: [sve2-aes]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8, u32, u64]
+    assert_instr: [pmullb]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "pmullb.pair.{sve_type}" }
+
+  - name: svpmullb[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Polynomial multiply long (bottom)
+    target_features: [sve2-aes]
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[u16, u8], [u64, u32]]
+    assert_instr: [pmullb]
+    n_variant_op: op2
+    compose:
+      - FnCall:
+          - "crate::intrinsics::transmute_unchecked"
+          - [FnCall: ["svpmullb_pair_{type[1]}", [$op1, $op2]]]
+          - []
+          - true
+
+  - name: svpmullt_pair[{_n}_{type}]
+    attr: [*sve-unstable]
+    doc: Polynomial multiply long (top)
+    target_features: [sve2-aes]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8, u32, u64]
+    assert_instr: [pmullt]
+    n_variant_op: op2
+    compose:
+      - LLVMLink: { name: "pmullt.pair.{sve_type}" }
+
+  - name: svpmullt[{_n}_{type[0]}]
+    attr: [*sve-unstable]
+    doc: Polynomial multiply long (top)
+    target_features: [sve2-aes]
+    arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
+    return_type: "{sve_type[0]}"
+    types: [[u16, u8], [u64, u32]]
+    assert_instr: [pmullt]
+    n_variant_op: op2
+    compose:
+      - FnCall:
+          - "crate::intrinsics::transmute_unchecked"
+          - [FnCall: ["svpmullt_pair_{type[1]}", [$op1, $op2]]]
+          - []
+          - true
+
+  - name: svaesd[_{type}]
+    attr: [*sve-unstable]
+    doc: AES single round decryption
+    target_features: [sve2-aes]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8]
+    assert_instr: [aesd]
+    compose:
+      - LLVMLink: { name: "aesd" }
+
+  - name: svaese[_{type}]
+    attr: [*sve-unstable]
+    doc: AES single round encryption
+    target_features: [sve2-aes]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8]
+    assert_instr: [aese]
+    compose:
+      - LLVMLink: { name: "aese" }
+
+  - name: svaesmc[_{type}]
+    attr: [*sve-unstable]
+    doc: AES mix columns
+    target_features: [sve2-aes]
+    arguments: ["op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8]
+    assert_instr: [aesmc]
+    compose:
+      - LLVMLink: { name: "aesmc" }
+
+  - name: svaesimc[_{type}]
+    attr: [*sve-unstable]
+    doc: AES inverse mix columns
+    target_features: [sve2-aes]
+    arguments: ["op: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u8]
+    assert_instr: [aesimc]
+    compose:
+      - LLVMLink: { name: "aesimc" }
+
+  - name: svsm4e[_{type}]
+    attr: [*sve-unstable]
+    doc: SM4 encryption and decryption
+    target_features: [sve2-sm4]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32]
+    assert_instr: [sm4e]
+    compose:
+      - LLVMLink: { name: "sm4e" }
+
+  - name: svsm4ekey[_{type}]
+    attr: [*sve-unstable]
+    doc: SM4 key updates
+    target_features: [sve2-sm4]
+    arguments: ["op1: {sve_type}", "op2: {sve_type}"]
+    return_type: "{sve_type}"
+    types: [u32]
+    assert_instr: [sm4ekey]
+    compose:
+      - LLVMLink: { name: "sm4ekey" }

From e215315df0696f19d16d98cd03dd38494f0f779a Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 15 Jan 2026 16:29:25 +0000
Subject: [PATCH 237/326] core_arch: generated sve intrinsics

Following from previous commit, this commit only contains generated code
from the SVE intrinsic specifications

Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
Co-authored-by: Adam Gemmell <adam.gemmell@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
---
 crates/core_arch/src/aarch64/sve/generated.rs | 44957 ++++++++++++++++
 .../src/aarch64/sve/ld_st_tests_aarch64.rs    |  9345 ++++
 .../core_arch/src/aarch64/sve2/generated.rs   | 23856 ++++++++
 .../src/aarch64/sve2/ld_st_tests_aarch64.rs   |  2482 +
 4 files changed, 80640 insertions(+)
 create mode 100644 crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
 create mode 100644 crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs

diff --git a/crates/core_arch/src/aarch64/sve/generated.rs b/crates/core_arch/src/aarch64/sve/generated.rs
index 8b13789179..6edfc8e159 100644
--- a/crates/core_arch/src/aarch64/sve/generated.rs
+++ b/crates/core_arch/src/aarch64/sve/generated.rs
@@ -1 +1,44958 @@
+// This code is automatically generated. DO NOT MODIFY.
+//
+// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file:
+//
+// ```
+// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
+// ```
+#![allow(improper_ctypes)]
 
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+use super::*;
+use crate::core_arch::arch::aarch64::*;
+
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv4f32")]
+        fn _svabd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svabd_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svabd_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svabd_f32_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svabd_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svabd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svabd_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv2f64")]
+        fn _svabd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svabd_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svabd_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svabd_f64_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svabd_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svabd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabd))]
+pub fn svabd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svabd_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv16i8")]
+        fn _svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svabd_s8_m(pg, op1, op2) }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svabd_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svabd_s8_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svabd_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svabd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svabd_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv8i16")]
+        fn _svabd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svabd_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svabd_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svabd_s16_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svabd_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svabd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svabd_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv4i32")]
+        fn _svabd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svabd_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svabd_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svabd_s32_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svabd_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svabd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svabd_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv2i64")]
+        fn _svabd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svabd_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svabd_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svabd_s64_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svabd_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svabd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabd))]
+pub fn svabd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svabd_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv16i8")]
+        fn _svabd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svabd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svabd_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svabd_u8_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svabd_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svabd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svabd_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv8i16")]
+        fn _svabd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svabd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svabd_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svabd_u16_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svabd_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svabd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svabd_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv4i32")]
+        fn _svabd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svabd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svabd_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svabd_u32_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svabd_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svabd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svabd_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv2i64")]
+        fn _svabd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svabd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svabd_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svabd_u64_m(pg, op1, op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svabd_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svabd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Absolute difference"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabd))]
+pub fn svabd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svabd_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabs))]
+pub fn svabs_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv4f32")]
+        fn _svabs_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svabs_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabs))]
+pub fn svabs_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svabs_f32_m(op, pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabs))]
+pub fn svabs_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svabs_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabs))]
+pub fn svabs_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv2f64")]
+        fn _svabs_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svabs_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabs))]
+pub fn svabs_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svabs_f64_m(op, pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fabs))]
+pub fn svabs_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svabs_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv16i8")]
+        fn _svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svabs_s8_m(inactive, pg, op) }
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svabs_s8_m(op, pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svabs_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv8i16")]
+        fn _svabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svabs_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svabs_s16_m(op, pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svabs_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv4i32")]
+        fn _svabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svabs_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svabs_s32_m(op, pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svabs_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv2i64")]
+        fn _svabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svabs_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svabs_s64_m(op, pg, op)
+}
+#[doc = "Absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(abs))]
+pub fn svabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svabs_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Absolute compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv4f32")]
+        fn _svacge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svacge_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Absolute compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svacge_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv2f64")]
+        fn _svacge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svacge_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Absolute compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svacge_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Absolute compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svacgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv4f32")]
+        fn _svacgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svacgt_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Absolute compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svacgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svacgt_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svacgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv2f64")]
+        fn _svacgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svacgt_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Absolute compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svacgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svacgt_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Absolute compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacle_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    svacge_f32(pg, op2, op1)
+}
+#[doc = "Absolute compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacle_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svacle_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacle_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    svacge_f64(pg, op2, op1)
+}
+#[doc = "Absolute compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facge))]
+pub fn svacle_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svacle_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Absolute compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svaclt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    svacgt_f32(pg, op2, op1)
+}
+#[doc = "Absolute compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svaclt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svaclt_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Absolute compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svaclt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    svacgt_f64(pg, op2, op1)
+}
+#[doc = "Absolute compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(facgt))]
+pub fn svaclt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svaclt_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv4f32")]
+        fn _svadd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svadd_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svadd_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svadd_f32_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svadd_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svadd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svadd_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv2f64")]
+        fn _svadd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svadd_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svadd_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svadd_f64_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svadd_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svadd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadd))]
+pub fn svadd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svadd_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv16i8")]
+        fn _svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svadd_s8_m(pg, op1, op2) }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svadd_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svadd_s8_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svadd_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svadd_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv8i16")]
+        fn _svadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svadd_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svadd_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svadd_s16_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svadd_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svadd_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv4i32")]
+        fn _svadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadd_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svadd_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svadd_s32_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svadd_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svadd_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv2i64")]
+        fn _svadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadd_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svadd_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svadd_s64_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svadd_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svadd_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svadd_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svadd_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svadd_u8_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svadd_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svadd_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svadd_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svadd_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svadd_u16_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svadd_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svadd_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svadd_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svadd_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svadd_u32_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svadd_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svadd_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svadd_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svadd_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svadd_u64_m(pg, op1, op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svadd_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(add))]
+pub fn svadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svadd_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Add reduction (strictly-ordered)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadda))]
+pub fn svadda_f32(pg: svbool_t, initial: f32, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv4f32")]
+        fn _svadda_f32(pg: svbool4_t, initial: f32, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svadda_f32(pg.sve_into(), initial, op) }
+}
+#[doc = "Add reduction (strictly-ordered)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fadda))]
+pub fn svadda_f64(pg: svbool_t, initial: f64, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv2f64")]
+        fn _svadda_f64(pg: svbool2_t, initial: f64, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svadda_f64(pg.sve_into(), initial, op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(faddv))]
+pub fn svaddv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv4f32")]
+        fn _svaddv_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svaddv_f32(pg.sve_into(), op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(faddv))]
+pub fn svaddv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv2f64")]
+        fn _svaddv_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svaddv_f64(pg.sve_into(), op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddv))]
+pub fn svaddv_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv2i64")]
+        fn _svaddv_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svaddv_s64(pg.sve_into(), op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddv))]
+pub fn svaddv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv2i64")]
+        fn _svaddv_u64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svaddv_u64(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddv))]
+pub fn svaddv_s8(pg: svbool_t, op: svint8_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv16i8")]
+        fn _svaddv_s8(pg: svbool_t, op: svint8_t) -> i64;
+    }
+    unsafe { _svaddv_s8(pg, op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddv))]
+pub fn svaddv_s16(pg: svbool_t, op: svint16_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv8i16")]
+        fn _svaddv_s16(pg: svbool8_t, op: svint16_t) -> i64;
+    }
+    unsafe { _svaddv_s16(pg.sve_into(), op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddv))]
+pub fn svaddv_s32(pg: svbool_t, op: svint32_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv4i32")]
+        fn _svaddv_s32(pg: svbool4_t, op: svint32_t) -> i64;
+    }
+    unsafe { _svaddv_s32(pg.sve_into(), op) }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddv))]
+pub fn svaddv_u8(pg: svbool_t, op: svuint8_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv16i8")]
+        fn _svaddv_u8(pg: svbool_t, op: svint8_t) -> i64;
+    }
+    unsafe { _svaddv_u8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddv))]
+pub fn svaddv_u16(pg: svbool_t, op: svuint16_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv8i16")]
+        fn _svaddv_u16(pg: svbool8_t, op: svint16_t) -> i64;
+    }
+    unsafe { _svaddv_u16(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Add reduction"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddv))]
+pub fn svaddv_u32(pg: svbool_t, op: svuint32_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv4i32")]
+        fn _svaddv_u32(pg: svbool4_t, op: svint32_t) -> i64;
+    }
+    unsafe { _svaddv_u32(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 8-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[s32]offset)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrb_u32base_s32offset(bases: svuint32_t, offsets: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv4i32")]
+        fn _svadrb_u32base_s32offset(bases: svint32_t, offsets: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadrb_u32base_s32offset(bases.as_signed(), offsets).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 16-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[s32]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrh_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv4i32")]
+        fn _svadrh_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadrh_u32base_s32index(bases.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 32-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[s32]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrw_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv4i32")]
+        fn _svadrw_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadrw_u32base_s32index(bases.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 64-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[s32]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrd_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv4i32")]
+        fn _svadrd_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadrd_u32base_s32index(bases.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 8-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[u32]offset)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrb_u32base_u32offset(bases: svuint32_t, offsets: svuint32_t) -> svuint32_t {
+    unsafe { svadrb_u32base_s32offset(bases, offsets.as_signed()) }
+}
+#[doc = "Compute vector addresses for 16-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[u32]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrh_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t {
+    unsafe { svadrh_u32base_s32index(bases, indices.as_signed()) }
+}
+#[doc = "Compute vector addresses for 32-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[u32]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrw_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t {
+    unsafe { svadrw_u32base_s32index(bases, indices.as_signed()) }
+}
+#[doc = "Compute vector addresses for 64-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[u32]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrd_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t {
+    unsafe { svadrd_u32base_s32index(bases, indices.as_signed()) }
+}
+#[doc = "Compute vector addresses for 8-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[s64]offset)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrb_u64base_s64offset(bases: svuint64_t, offsets: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv2i64")]
+        fn _svadrb_u64base_s64offset(bases: svint64_t, offsets: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadrb_u64base_s64offset(bases.as_signed(), offsets).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 16-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[s64]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrh_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv2i64")]
+        fn _svadrh_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadrh_u64base_s64index(bases.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 32-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[s64]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrw_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv2i64")]
+        fn _svadrw_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadrw_u64base_s64index(bases.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 64-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[s64]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrd_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv2i64")]
+        fn _svadrd_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadrd_u64base_s64index(bases.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Compute vector addresses for 8-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[u64]offset)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrb_u64base_u64offset(bases: svuint64_t, offsets: svuint64_t) -> svuint64_t {
+    unsafe { svadrb_u64base_s64offset(bases, offsets.as_signed()) }
+}
+#[doc = "Compute vector addresses for 16-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[u64]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrh_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t {
+    unsafe { svadrh_u64base_s64index(bases, indices.as_signed()) }
+}
+#[doc = "Compute vector addresses for 32-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[u64]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrw_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t {
+    unsafe { svadrw_u64base_s64index(bases, indices.as_signed()) }
+}
+#[doc = "Compute vector addresses for 64-bit data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[u64]index)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adr))]
+pub fn svadrd_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t {
+    unsafe { svadrd_u64base_s64index(bases, indices.as_signed()) }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.z.nvx16i1")]
+        fn _svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svand_b_z(pg, op1, op2) }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv16i8")]
+        fn _svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svand_s8_m(pg, op1, op2) }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svand_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svand_s8_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svand_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svand_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svand_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv8i16")]
+        fn _svand_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svand_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svand_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svand_s16_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svand_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svand_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svand_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv4i32")]
+        fn _svand_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svand_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svand_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svand_s32_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svand_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svand_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svand_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv2i64")]
+        fn _svand_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svand_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svand_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svand_s64_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svand_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svand_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svand_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svand_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svand_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svand_u8_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svand_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svand_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svand_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svand_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svand_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svand_u16_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svand_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svand_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svand_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svand_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svand_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svand_u32_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svand_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svand_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svand_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svand_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svand_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svand_u64_m(pg, op1, op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svand_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svand_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Bitwise AND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(and))]
+pub fn svand_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svand_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv16i8")]
+        fn _svandv_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svandv_s8(pg, op) }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv8i16")]
+        fn _svandv_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svandv_s16(pg.sve_into(), op) }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv4i32")]
+        fn _svandv_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svandv_s32(pg.sve_into(), op) }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv2i64")]
+        fn _svandv_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svandv_s64(pg.sve_into(), op) }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe { svandv_s8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe { svandv_s16(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe { svandv_s32(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise AND reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(andv))]
+pub fn svandv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe { svandv_s64(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv16i8")]
+        fn _svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svasr_s8_m(pg, op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svasr_s8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    svasr_s8_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svasr_s8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    svasr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svasr_s8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv8i16")]
+        fn _svasr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svasr_s16_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svasr_s16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    svasr_s16_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svasr_s16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    svasr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svasr_s16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv4i32")]
+        fn _svasr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svasr_s32_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svasr_s32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    svasr_s32_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svasr_s32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    svasr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svasr_s32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv2i64")]
+        fn _svasr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svasr_s64_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svasr_s64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    svasr_s64_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svasr_s64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    svasr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svasr_s64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.asr.wide.nxv16i8"
+        )]
+        fn _svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t;
+    }
+    unsafe { _svasr_wide_s8_m(pg, op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
+    svasr_wide_s8_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t {
+    svasr_wide_s8_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
+    svasr_wide_s8_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t {
+    svasr_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
+    svasr_wide_s8_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.asr.wide.nxv8i16"
+        )]
+        fn _svasr_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t;
+    }
+    unsafe { _svasr_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
+    svasr_wide_s16_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t {
+    svasr_wide_s16_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
+    svasr_wide_s16_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t {
+    svasr_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
+    svasr_wide_s16_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.asr.wide.nxv4i32"
+        )]
+        fn _svasr_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svasr_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
+    svasr_wide_s32_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t {
+    svasr_wide_s32_m(pg, op1, op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
+    svasr_wide_s32_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t {
+    svasr_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Arithmetic shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asr))]
+pub fn svasr_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
+    svasr_wide_s32_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s8_m<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv16i8")]
+        fn _svasrd_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svasrd_n_s8_m(pg, op1, IMM2) }
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s8_x<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
+    svasrd_n_s8_m::<IMM2>(pg, op1)
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s8_z<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
+    svasrd_n_s8_m::<IMM2>(pg, svsel_s8(pg, op1, svdup_n_s8(0)))
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s16_m<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv8i16")]
+        fn _svasrd_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svasrd_n_s16_m(pg.sve_into(), op1, IMM2) }
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s16_x<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_t {
+    svasrd_n_s16_m::<IMM2>(pg, op1)
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s16_z<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_t {
+    svasrd_n_s16_m::<IMM2>(pg, svsel_s16(pg, op1, svdup_n_s16(0)))
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s32_m<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv4i32")]
+        fn _svasrd_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svasrd_n_s32_m(pg.sve_into(), op1, IMM2) }
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s32_x<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_t {
+    svasrd_n_s32_m::<IMM2>(pg, op1)
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s32_z<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_t {
+    svasrd_n_s32_m::<IMM2>(pg, svsel_s32(pg, op1, svdup_n_s32(0)))
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s64_m<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_t {
+    static_assert_range!(IMM2, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv2i64")]
+        fn _svasrd_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svasrd_n_s64_m(pg.sve_into(), op1, IMM2) }
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s64_x<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_t {
+    svasrd_n_s64_m::<IMM2>(pg, op1)
+}
+#[doc = "Arithmetic shift right for divide by immediate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
+pub fn svasrd_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_t {
+    svasrd_n_s64_m::<IMM2>(pg, svsel_s64(pg, op1, svdup_n_s64(0)))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.z.nvx16i1")]
+        fn _svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbic_b_z(pg, op1, op2) }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv16i8")]
+        fn _svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbic_s8_m(pg, op1, op2) }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svbic_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svbic_s8_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svbic_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svbic_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svbic_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv8i16")]
+        fn _svbic_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbic_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svbic_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svbic_s16_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svbic_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svbic_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svbic_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv4i32")]
+        fn _svbic_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbic_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svbic_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svbic_s32_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svbic_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svbic_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svbic_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv2i64")]
+        fn _svbic_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbic_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svbic_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svbic_s64_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svbic_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svbic_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svbic_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svbic_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svbic_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svbic_u8_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svbic_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svbic_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svbic_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svbic_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svbic_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svbic_u16_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svbic_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svbic_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svbic_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svbic_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svbic_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svbic_u32_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svbic_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svbic_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svbic_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svbic_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svbic_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svbic_u64_m(pg, op1, op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svbic_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svbic_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Bitwise clear"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bic))]
+pub fn svbic_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svbic_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Break after first true condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brka))]
+pub fn svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.nxv16i1")]
+        fn _svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrka_b_m(inactive, pg, op) }
+}
+#[doc = "Break after first true condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brka))]
+pub fn svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.z.nxv16i1")]
+        fn _svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrka_b_z(pg, op) }
+}
+#[doc = "Break before first true condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brkb))]
+pub fn svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.nxv16i1")]
+        fn _svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrkb_b_m(inactive, pg, op) }
+}
+#[doc = "Break before first true condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brkb))]
+pub fn svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.z.nxv16i1")]
+        fn _svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrkb_b_z(pg, op) }
+}
+#[doc = "Propagate break to next partition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkn[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brkn))]
+pub fn svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkn.z.nxv16i1")]
+        fn _svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrkn_b_z(pg, op1, op2) }
+}
+#[doc = "Break after first true condition, propagating from previous partition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpa[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brkpa))]
+pub fn svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.brkpa.z.nxv16i1"
+        )]
+        fn _svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrkpa_b_z(pg, op1, op2) }
+}
+#[doc = "Break before first true condition, propagating from previous partition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpb[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(brkpb))]
+pub fn svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.brkpb.z.nxv16i1"
+        )]
+        fn _svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svbrkpb_b_z(pg, op1, op2) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
+pub fn svcadd_f32_m<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+) -> svfloat32_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv4f32")]
+        fn _svcadd_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            imm_rotation: i32,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svcadd_f32_m(pg.sve_into(), op1, op2, IMM_ROTATION) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
+pub fn svcadd_f32_x<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+) -> svfloat32_t {
+    svcadd_f32_m::<IMM_ROTATION>(pg, op1, op2)
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
+pub fn svcadd_f32_z<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+) -> svfloat32_t {
+    svcadd_f32_m::<IMM_ROTATION>(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
+pub fn svcadd_f64_m<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+) -> svfloat64_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv2f64")]
+        fn _svcadd_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            imm_rotation: i32,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svcadd_f64_m(pg.sve_into(), op1, op2, IMM_ROTATION) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
+pub fn svcadd_f64_x<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+) -> svfloat64_t {
+    svcadd_f64_m::<IMM_ROTATION>(pg, op1, op2)
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
+pub fn svcadd_f64_z<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+) -> svfloat64_t {
+    svcadd_f64_m::<IMM_ROTATION>(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4f32")]
+        fn _svclasta_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svclasta_f32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2f64")]
+        fn _svclasta_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svclasta_f64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv16i8")]
+        fn _svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t;
+    }
+    unsafe { _svclasta_s8(pg, fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv8i16")]
+        fn _svclasta_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t;
+    }
+    unsafe { _svclasta_s16(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4i32")]
+        fn _svclasta_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t;
+    }
+    unsafe { _svclasta_s32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2i64")]
+        fn _svclasta_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t;
+    }
+    unsafe { _svclasta_s64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t {
+    unsafe { svclasta_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t {
+    unsafe { svclasta_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t {
+    unsafe { svclasta_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t {
+    unsafe { svclasta_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clasta.n.nxv4f32"
+        )]
+        fn _svclasta_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32;
+    }
+    unsafe { _svclasta_n_f32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clasta.n.nxv2f64"
+        )]
+        fn _svclasta_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64;
+    }
+    unsafe { _svclasta_n_f64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clasta.n.nxv16i8"
+        )]
+        fn _svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8;
+    }
+    unsafe { _svclasta_n_s8(pg, fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clasta.n.nxv8i16"
+        )]
+        fn _svclasta_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16;
+    }
+    unsafe { _svclasta_n_s16(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clasta.n.nxv4i32"
+        )]
+        fn _svclasta_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32;
+    }
+    unsafe { _svclasta_n_s32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clasta.n.nxv2i64"
+        )]
+        fn _svclasta_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64;
+    }
+    unsafe { _svclasta_n_s64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 {
+    unsafe { svclasta_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 {
+    unsafe { svclasta_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 {
+    unsafe { svclasta_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clasta))]
+pub fn svclasta_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 {
+    unsafe { svclasta_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4f32")]
+        fn _svclastb_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svclastb_f32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2f64")]
+        fn _svclastb_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svclastb_f64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv16i8")]
+        fn _svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t;
+    }
+    unsafe { _svclastb_s8(pg, fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv8i16")]
+        fn _svclastb_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t;
+    }
+    unsafe { _svclastb_s16(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4i32")]
+        fn _svclastb_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t;
+    }
+    unsafe { _svclastb_s32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2i64")]
+        fn _svclastb_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t;
+    }
+    unsafe { _svclastb_s64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t {
+    unsafe { svclastb_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t {
+    unsafe { svclastb_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t {
+    unsafe { svclastb_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t {
+    unsafe { svclastb_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clastb.n.nxv4f32"
+        )]
+        fn _svclastb_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32;
+    }
+    unsafe { _svclastb_n_f32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clastb.n.nxv2f64"
+        )]
+        fn _svclastb_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64;
+    }
+    unsafe { _svclastb_n_f64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clastb.n.nxv16i8"
+        )]
+        fn _svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8;
+    }
+    unsafe { _svclastb_n_s8(pg, fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clastb.n.nxv8i16"
+        )]
+        fn _svclastb_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16;
+    }
+    unsafe { _svclastb_n_s16(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clastb.n.nxv4i32"
+        )]
+        fn _svclastb_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32;
+    }
+    unsafe { _svclastb_n_s32(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.clastb.n.nxv2i64"
+        )]
+        fn _svclastb_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64;
+    }
+    unsafe { _svclastb_n_s64(pg.sve_into(), fallback, data) }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 {
+    unsafe { svclastb_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 {
+    unsafe { svclastb_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 {
+    unsafe { svclastb_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Conditionally extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clastb))]
+pub fn svclastb_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 {
+    unsafe { svclastb_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv16i8")]
+        fn _svcls_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svcls_s8_m(inactive.as_signed(), pg, op).as_unsigned() }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t {
+    unsafe { svcls_s8_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t {
+    svcls_s8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv8i16")]
+        fn _svcls_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svcls_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t {
+    unsafe { svcls_s16_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t {
+    svcls_s16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv4i32")]
+        fn _svcls_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svcls_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t {
+    unsafe { svcls_s32_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t {
+    svcls_s32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv2i64")]
+        fn _svcls_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svcls_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t {
+    unsafe { svcls_s64_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading sign bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cls))]
+pub fn svcls_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t {
+    svcls_s64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv16i8")]
+        fn _svclz_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svclz_s8_m(inactive.as_signed(), pg, op).as_unsigned() }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t {
+    unsafe { svclz_s8_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t {
+    svclz_s8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv8i16")]
+        fn _svclz_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svclz_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t {
+    unsafe { svclz_s16_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t {
+    svclz_s16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv4i32")]
+        fn _svclz_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svclz_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t {
+    unsafe { svclz_s32_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t {
+    svclz_s32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv2i64")]
+        fn _svclz_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svclz_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t {
+    unsafe { svclz_s64_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t {
+    svclz_s64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    unsafe { svclz_s8_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svclz_u8_m(op, pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svclz_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe { svclz_s16_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svclz_u16_m(op, pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svclz_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svclz_s32_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svclz_u32_m(op, pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svclz_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svclz_s64_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svclz_u64_m(op, pg, op)
+}
+#[doc = "Count leading zero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(clz))]
+pub fn svclz_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svclz_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
+pub fn svcmla_f32_m<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv4f32")]
+        fn _svcmla_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+            imm_rotation: i32,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svcmla_f32_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
+pub fn svcmla_f32_x<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svcmla_f32_m::<IMM_ROTATION>(pg, op1, op2, op3)
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
+pub fn svcmla_f32_z<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svcmla_f32_m::<IMM_ROTATION>(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
+pub fn svcmla_f64_m<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv2f64")]
+        fn _svcmla_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+            imm_rotation: i32,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svcmla_f64_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
+pub fn svcmla_f64_x<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svcmla_f64_m::<IMM_ROTATION>(pg, op1, op2, op3)
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
+pub fn svcmla_f64_z<const IMM_ROTATION: i32>(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svcmla_f64_m::<IMM_ROTATION>(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcmla_lane_f32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fcmla.lane.x.nxv4f32"
+        )]
+        fn _svcmla_lane_f32(
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svcmla_lane_f32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmeq))]
+pub fn svcmpeq_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv4f32")]
+        fn _svcmpeq_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpeq_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmeq))]
+pub fn svcmpeq_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmpeq_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmeq))]
+pub fn svcmpeq_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv2f64")]
+        fn _svcmpeq_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpeq_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmeq))]
+pub fn svcmpeq_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmpeq_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv16i8")]
+        fn _svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svcmpeq_s8(pg, op1, op2) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
+    svcmpeq_s8(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv8i16")]
+        fn _svcmpeq_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svcmpeq_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
+    svcmpeq_s16(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv4i32")]
+        fn _svcmpeq_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpeq_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
+    svcmpeq_s32(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv2i64")]
+        fn _svcmpeq_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpeq_s64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
+    svcmpeq_s64(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    unsafe { svcmpeq_s8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
+    svcmpeq_u8(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    unsafe { svcmpeq_s16(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
+    svcmpeq_u16(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
+    unsafe { svcmpeq_s32(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
+    svcmpeq_u32(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
+    unsafe { svcmpeq_s64(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
+    svcmpeq_u64(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpeq.wide.nxv16i8"
+        )]
+        fn _svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmpeq_wide_s8(pg, op1, op2) }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
+    svcmpeq_wide_s8(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpeq.wide.nxv8i16"
+        )]
+        fn _svcmpeq_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmpeq_wide_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
+    svcmpeq_wide_s16(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpeq.wide.nxv4i32"
+        )]
+        fn _svcmpeq_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmpeq_wide_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpeq))]
+pub fn svcmpeq_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
+    svcmpeq_wide_s32(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmpge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv4f32")]
+        fn _svcmpge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpge_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmpge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmpge_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmpge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv2f64")]
+        fn _svcmpge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpge_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmpge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmpge_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv16i8")]
+        fn _svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svcmpge_s8(pg, op1, op2) }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
+    svcmpge_s8(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv8i16")]
+        fn _svcmpge_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svcmpge_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
+    svcmpge_s16(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv4i32")]
+        fn _svcmpge_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpge_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
+    svcmpge_s32(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv2i64")]
+        fn _svcmpge_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpge_s64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
+    svcmpge_s64(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv16i8")]
+        fn _svcmpge_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svcmpge_u8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
+    svcmpge_u8(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv8i16")]
+        fn _svcmpge_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svcmpge_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
+    svcmpge_u16(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv4i32")]
+        fn _svcmpge_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpge_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
+    svcmpge_u32(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv2i64")]
+        fn _svcmpge_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpge_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
+    svcmpge_u64(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpge.wide.nxv16i8"
+        )]
+        fn _svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmpge_wide_s8(pg, op1, op2) }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
+    svcmpge_wide_s8(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpge.wide.nxv8i16"
+        )]
+        fn _svcmpge_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmpge_wide_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
+    svcmpge_wide_s16(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpge.wide.nxv4i32"
+        )]
+        fn _svcmpge_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmpge_wide_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmpge_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
+    svcmpge_wide_s32(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmphs.wide.nxv16i8"
+        )]
+        fn _svcmpge_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmpge_wide_u8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
+    svcmpge_wide_u8(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmphs.wide.nxv8i16"
+        )]
+        fn _svcmpge_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmpge_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
+    svcmpge_wide_u16(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmphs.wide.nxv4i32"
+        )]
+        fn _svcmpge_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmpge_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmpge_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
+    svcmpge_wide_u32(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmpgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv4f32")]
+        fn _svcmpgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpgt_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmpgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmpgt_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmpgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv2f64")]
+        fn _svcmpgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpgt_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmpgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmpgt_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv16i8")]
+        fn _svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svcmpgt_s8(pg, op1, op2) }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
+    svcmpgt_s8(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv8i16")]
+        fn _svcmpgt_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svcmpgt_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
+    svcmpgt_s16(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv4i32")]
+        fn _svcmpgt_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpgt_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
+    svcmpgt_s32(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv2i64")]
+        fn _svcmpgt_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpgt_s64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
+    svcmpgt_s64(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv16i8")]
+        fn _svcmpgt_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svcmpgt_u8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
+    svcmpgt_u8(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv8i16")]
+        fn _svcmpgt_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svcmpgt_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
+    svcmpgt_u16(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv4i32")]
+        fn _svcmpgt_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpgt_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
+    svcmpgt_u32(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv2i64")]
+        fn _svcmpgt_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpgt_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
+    svcmpgt_u64(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpgt.wide.nxv16i8"
+        )]
+        fn _svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmpgt_wide_s8(pg, op1, op2) }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
+    svcmpgt_wide_s8(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpgt.wide.nxv8i16"
+        )]
+        fn _svcmpgt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmpgt_wide_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
+    svcmpgt_wide_s16(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpgt.wide.nxv4i32"
+        )]
+        fn _svcmpgt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmpgt_wide_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmpgt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
+    svcmpgt_wide_s32(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmphi.wide.nxv16i8"
+        )]
+        fn _svcmpgt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmpgt_wide_u8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
+    svcmpgt_wide_u8(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmphi.wide.nxv8i16"
+        )]
+        fn _svcmpgt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmpgt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
+    svcmpgt_wide_u16(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmphi.wide.nxv4i32"
+        )]
+        fn _svcmpgt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmpgt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmpgt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
+    svcmpgt_wide_u32(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmple_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    svcmpge_f32(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmple_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmple_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmple_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    svcmpge_f64(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmge))]
+pub fn svcmple_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmple_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    svcmpge_s8(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
+    svcmple_s8(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    svcmpge_s16(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
+    svcmple_s16(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
+    svcmpge_s32(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
+    svcmple_s32(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
+    svcmpge_s64(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpge))]
+pub fn svcmple_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
+    svcmple_s64(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    svcmpge_u8(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
+    svcmple_u8(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    svcmpge_u16(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
+    svcmple_u16(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
+    svcmpge_u32(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
+    svcmple_u32(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
+    svcmpge_u64(pg, op2, op1)
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphs))]
+pub fn svcmple_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
+    svcmple_u64(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmple))]
+pub fn svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmple.wide.nxv16i8"
+        )]
+        fn _svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmple_wide_s8(pg, op1, op2) }
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmple))]
+pub fn svcmple_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
+    svcmple_wide_s8(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmple))]
+pub fn svcmple_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmple.wide.nxv8i16"
+        )]
+        fn _svcmple_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmple_wide_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmple))]
+pub fn svcmple_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
+    svcmple_wide_s16(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmple))]
+pub fn svcmple_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmple.wide.nxv4i32"
+        )]
+        fn _svcmple_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmple_wide_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmple))]
+pub fn svcmple_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
+    svcmple_wide_s32(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpls))]
+pub fn svcmple_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpls.wide.nxv16i8"
+        )]
+        fn _svcmple_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmple_wide_u8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpls))]
+pub fn svcmple_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
+    svcmple_wide_u8(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpls))]
+pub fn svcmple_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpls.wide.nxv8i16"
+        )]
+        fn _svcmple_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmple_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpls))]
+pub fn svcmple_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
+    svcmple_wide_u16(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpls))]
+pub fn svcmple_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpls.wide.nxv4i32"
+        )]
+        fn _svcmple_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmple_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpls))]
+pub fn svcmple_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
+    svcmple_wide_u32(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmplt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    svcmpgt_f32(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmplt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmplt_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmplt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    svcmpgt_f64(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmgt))]
+pub fn svcmplt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmplt_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    svcmpgt_s8(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
+    svcmplt_s8(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    svcmpgt_s16(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
+    svcmplt_s16(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
+    svcmpgt_s32(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
+    svcmplt_s32(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
+    svcmpgt_s64(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpgt))]
+pub fn svcmplt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
+    svcmplt_s64(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    svcmpgt_u8(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
+    svcmplt_u8(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    svcmpgt_u16(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
+    svcmplt_u16(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
+    svcmpgt_u32(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
+    svcmplt_u32(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
+    svcmpgt_u64(pg, op2, op1)
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmphi))]
+pub fn svcmplt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
+    svcmplt_u64(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplt))]
+pub fn svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmplt.wide.nxv16i8"
+        )]
+        fn _svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmplt_wide_s8(pg, op1, op2) }
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplt))]
+pub fn svcmplt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
+    svcmplt_wide_s8(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplt))]
+pub fn svcmplt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmplt.wide.nxv8i16"
+        )]
+        fn _svcmplt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmplt_wide_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplt))]
+pub fn svcmplt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
+    svcmplt_wide_s16(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplt))]
+pub fn svcmplt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmplt.wide.nxv4i32"
+        )]
+        fn _svcmplt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmplt_wide_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplt))]
+pub fn svcmplt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
+    svcmplt_wide_s32(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplo))]
+pub fn svcmplt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmplo.wide.nxv16i8"
+        )]
+        fn _svcmplt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmplt_wide_u8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplo))]
+pub fn svcmplt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
+    svcmplt_wide_u8(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplo))]
+pub fn svcmplt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmplo.wide.nxv8i16"
+        )]
+        fn _svcmplt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmplt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplo))]
+pub fn svcmplt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
+    svcmplt_wide_u16(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplo))]
+pub fn svcmplt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmplo.wide.nxv4i32"
+        )]
+        fn _svcmplt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmplt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Compare less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmplo))]
+pub fn svcmplt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
+    svcmplt_wide_u32(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmne))]
+pub fn svcmpne_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv4f32")]
+        fn _svcmpne_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpne_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmne))]
+pub fn svcmpne_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmpne_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmne))]
+pub fn svcmpne_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv2f64")]
+        fn _svcmpne_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpne_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmne))]
+pub fn svcmpne_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmpne_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv16i8")]
+        fn _svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svcmpne_s8(pg, op1, op2) }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
+    svcmpne_s8(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv8i16")]
+        fn _svcmpne_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svcmpne_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
+    svcmpne_s16(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv4i32")]
+        fn _svcmpne_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpne_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
+    svcmpne_s32(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv2i64")]
+        fn _svcmpne_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpne_s64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
+    svcmpne_s64(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    unsafe { svcmpne_s8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
+    svcmpne_u8(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    unsafe { svcmpne_s16(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
+    svcmpne_u16(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
+    unsafe { svcmpne_s32(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
+    svcmpne_u32(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
+    unsafe { svcmpne_s64(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
+    svcmpne_u64(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpne.wide.nxv16i8"
+        )]
+        fn _svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t;
+    }
+    unsafe { _svcmpne_wide_s8(pg, op1, op2) }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
+    svcmpne_wide_s8(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpne.wide.nxv8i16"
+        )]
+        fn _svcmpne_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t;
+    }
+    unsafe { _svcmpne_wide_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
+    svcmpne_wide_s16(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmpne.wide.nxv4i32"
+        )]
+        fn _svcmpne_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t;
+    }
+    unsafe { _svcmpne_wide_s32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare not equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmpne))]
+pub fn svcmpne_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
+    svcmpne_wide_s32(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Compare unordered with"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmuo))]
+pub fn svcmpuo_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv4f32")]
+        fn _svcmpuo_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t;
+    }
+    unsafe { _svcmpuo_f32(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare unordered with"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmuo))]
+pub fn svcmpuo_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
+    svcmpuo_f32(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Compare unordered with"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmuo))]
+pub fn svcmpuo_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv2f64")]
+        fn _svcmpuo_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t;
+    }
+    unsafe { _svcmpuo_f64(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Compare unordered with"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcmuo))]
+pub fn svcmpuo_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
+    svcmpuo_f64(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv16i8")]
+        fn _svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svcnot_s8_m(inactive, pg, op) }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svcnot_s8_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svcnot_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv8i16")]
+        fn _svcnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svcnot_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svcnot_s16_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svcnot_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv4i32")]
+        fn _svcnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svcnot_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svcnot_s32_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svcnot_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv2i64")]
+        fn _svcnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svcnot_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svcnot_s64_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svcnot_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    unsafe { svcnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svcnot_u8_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svcnot_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe { svcnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svcnot_u16_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svcnot_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svcnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svcnot_u32_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svcnot_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svcnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svcnot_u64_m(op, pg, op)
+}
+#[doc = "Logically invert boolean condition"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnot))]
+pub fn svcnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svcnot_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4f32")]
+        fn _svcnt_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
+    }
+    unsafe { _svcnt_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    unsafe { svcnt_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    svcnt_f32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2f64")]
+        fn _svcnt_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
+    }
+    unsafe { _svcnt_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    unsafe { svcnt_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    svcnt_f64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv16i8")]
+        fn _svcnt_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svcnt_s8_m(inactive.as_signed(), pg, op).as_unsigned() }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t {
+    unsafe { svcnt_s8_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t {
+    svcnt_s8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv8i16")]
+        fn _svcnt_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svcnt_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t {
+    unsafe { svcnt_s16_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t {
+    svcnt_s16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4i32")]
+        fn _svcnt_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svcnt_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t {
+    unsafe { svcnt_s32_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t {
+    svcnt_s32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2i64")]
+        fn _svcnt_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svcnt_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t {
+    unsafe { svcnt_s64_m(op.as_unsigned(), pg, op) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t {
+    svcnt_s64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    unsafe { svcnt_s8_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svcnt_u8_m(op, pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svcnt_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe { svcnt_s16_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svcnt_u16_m(op, pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svcnt_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svcnt_s32_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svcnt_u32_m(op, pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svcnt_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svcnt_s64_m(inactive, pg, op.as_signed()) }
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svcnt_u64_m(op, pg, op)
+}
+#[doc = "Count nonzero bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnt))]
+pub fn svcnt_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svcnt_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Count the number of 8-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rdvl))]
+pub fn svcntb() -> u64 {
+    svcntb_pat::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Count the number of 16-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnth))]
+pub fn svcnth() -> u64 {
+    svcnth_pat::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Count the number of 32-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntw))]
+pub fn svcntw() -> u64 {
+    svcntw_pat::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Count the number of 64-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntd))]
+pub fn svcntd() -> u64 {
+    svcntd_pat::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Count the number of 8-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb_pat)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (rdvl , PATTERN = { svpattern :: SV_ALL }))]
+# [cfg_attr (test , assert_instr (cntb , PATTERN = { svpattern :: SV_MUL4 }))]
+pub fn svcntb_pat<const PATTERN: svpattern>() -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntb")]
+        fn _svcntb_pat(pattern: svpattern) -> i64;
+    }
+    unsafe { _svcntb_pat(PATTERN).as_unsigned() }
+}
+#[doc = "Count the number of 16-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth_pat)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (cnth , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svcnth_pat<const PATTERN: svpattern>() -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnth")]
+        fn _svcnth_pat(pattern: svpattern) -> i64;
+    }
+    unsafe { _svcnth_pat(PATTERN).as_unsigned() }
+}
+#[doc = "Count the number of 32-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw_pat)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (cntw , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svcntw_pat<const PATTERN: svpattern>() -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntw")]
+        fn _svcntw_pat(pattern: svpattern) -> i64;
+    }
+    unsafe { _svcntw_pat(PATTERN).as_unsigned() }
+}
+#[doc = "Count the number of 64-bit elements in a vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd_pat)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (cntd , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svcntd_pat<const PATTERN: svpattern>() -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntd")]
+        fn _svcntd_pat(pattern: svpattern) -> i64;
+    }
+    unsafe { _svcntd_pat(PATTERN).as_unsigned() }
+}
+#[doc = "Count set predicate bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntp))]
+pub fn svcntp_b8(pg: svbool_t, op: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv16i1")]
+        fn _svcntp_b8(pg: svbool_t, op: svbool_t) -> i64;
+    }
+    unsafe { _svcntp_b8(pg, op).as_unsigned() }
+}
+#[doc = "Count set predicate bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntp))]
+pub fn svcntp_b16(pg: svbool_t, op: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv8i1")]
+        fn _svcntp_b16(pg: svbool8_t, op: svbool8_t) -> i64;
+    }
+    unsafe { _svcntp_b16(pg.sve_into(), op.sve_into()).as_unsigned() }
+}
+#[doc = "Count set predicate bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntp))]
+pub fn svcntp_b32(pg: svbool_t, op: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv4i1")]
+        fn _svcntp_b32(pg: svbool4_t, op: svbool4_t) -> i64;
+    }
+    unsafe { _svcntp_b32(pg.sve_into(), op.sve_into()).as_unsigned() }
+}
+#[doc = "Count set predicate bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntp))]
+pub fn svcntp_b64(pg: svbool_t, op: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv2i1")]
+        fn _svcntp_b64(pg: svbool2_t, op: svbool2_t) -> i64;
+    }
+    unsafe { _svcntp_b64(pg.sve_into(), op.sve_into()).as_unsigned() }
+}
+#[doc = "Shuffle active elements of vector to the right and fill with zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(compact))]
+pub fn svcompact_f32(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.compact.nxv4f32"
+        )]
+        fn _svcompact_f32(pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svcompact_f32(pg.sve_into(), op) }
+}
+#[doc = "Shuffle active elements of vector to the right and fill with zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(compact))]
+pub fn svcompact_f64(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.compact.nxv2f64"
+        )]
+        fn _svcompact_f64(pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svcompact_f64(pg.sve_into(), op) }
+}
+#[doc = "Shuffle active elements of vector to the right and fill with zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(compact))]
+pub fn svcompact_s32(pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.compact.nxv4i32"
+        )]
+        fn _svcompact_s32(pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svcompact_s32(pg.sve_into(), op) }
+}
+#[doc = "Shuffle active elements of vector to the right and fill with zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(compact))]
+pub fn svcompact_s64(pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.compact.nxv2i64"
+        )]
+        fn _svcompact_s64(pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svcompact_s64(pg.sve_into(), op) }
+}
+#[doc = "Shuffle active elements of vector to the right and fill with zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(compact))]
+pub fn svcompact_u32(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svcompact_s32(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Shuffle active elements of vector to the right and fill with zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(compact))]
+pub fn svcompact_u64(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svcompact_s64(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_f32(x0: svfloat32_t, x1: svfloat32_t) -> svfloat32x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_f64(x0: svfloat64_t, x1: svfloat64_t) -> svfloat64x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_s8(x0: svint8_t, x1: svint8_t) -> svint8x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_s16(x0: svint16_t, x1: svint16_t) -> svint16x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_s32(x0: svint32_t, x1: svint32_t) -> svint32x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_s64(x0: svint64_t, x1: svint64_t) -> svint64x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_u8(x0: svuint8_t, x1: svuint8_t) -> svuint8x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_u16(x0: svuint16_t, x1: svuint16_t) -> svuint16x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_u32(x0: svuint32_t, x1: svuint32_t) -> svuint32x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate2_u64(x0: svuint64_t, x1: svuint64_t) -> svuint64x2_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_f32(x0: svfloat32_t, x1: svfloat32_t, x2: svfloat32_t) -> svfloat32x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_f64(x0: svfloat64_t, x1: svfloat64_t, x2: svfloat64_t) -> svfloat64x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t) -> svint8x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t) -> svint16x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t) -> svint32x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t) -> svint64x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t) -> svuint8x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_u16(x0: svuint16_t, x1: svuint16_t, x2: svuint16_t) -> svuint16x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_u32(x0: svuint32_t, x1: svuint32_t, x2: svuint32_t) -> svuint32x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate3_u64(x0: svuint64_t, x1: svuint64_t, x2: svuint64_t) -> svuint64x3_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_f32(
+    x0: svfloat32_t,
+    x1: svfloat32_t,
+    x2: svfloat32_t,
+    x3: svfloat32_t,
+) -> svfloat32x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_f64(
+    x0: svfloat64_t,
+    x1: svfloat64_t,
+    x2: svfloat64_t,
+    x3: svfloat64_t,
+) -> svfloat64x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t, x3: svint8_t) -> svint8x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t, x3: svint16_t) -> svint16x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t, x3: svint32_t) -> svint32x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t, x3: svint64_t) -> svint64x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t, x3: svuint8_t) -> svuint8x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_u16(
+    x0: svuint16_t,
+    x1: svuint16_t,
+    x2: svuint16_t,
+    x3: svuint16_t,
+) -> svuint16x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_u32(
+    x0: svuint32_t,
+    x1: svuint32_t,
+    x2: svuint32_t,
+    x3: svuint32_t,
+) -> svuint32x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Create a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svcreate4_u64(
+    x0: svuint64_t,
+    x1: svuint64_t,
+    x2: svuint64_t,
+    x3: svuint64_t,
+) -> svuint64x4_t {
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvt))]
+pub fn svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f32f64")]
+        fn _svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvt))]
+pub fn svcvt_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    unsafe { svcvt_f32_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvt))]
+pub fn svcvt_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    svcvt_f32_f64_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvt))]
+pub fn svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f64f32")]
+        fn _svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) -> svfloat64_t;
+    }
+    unsafe { _svcvt_f64_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvt))]
+pub fn svcvt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
+    unsafe { svcvt_f64_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvt))]
+pub fn svcvt_f64_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
+    svcvt_f64_f32_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool_t, op: svint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i32")]
+        fn _svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s32_x(pg: svbool_t, op: svint32_t) -> svfloat32_t {
+    unsafe { svcvt_f32_s32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s32_z(pg: svbool_t, op: svint32_t) -> svfloat32_t {
+    svcvt_f32_s32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i64")]
+        fn _svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t {
+    unsafe { svcvt_f32_s64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t {
+    svcvt_f32_s64_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i32")]
+        fn _svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_u32_m(inactive, pg.sve_into(), op.as_signed()) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+    unsafe { svcvt_f32_u32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
+    svcvt_f32_u32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool_t, op: svuint64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i64")]
+        fn _svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvt_f32_u64_m(inactive, pg.sve_into(), op.as_signed()) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat32_t {
+    unsafe { svcvt_f32_u64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f32_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat32_t {
+    svcvt_f32_u64_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool_t, op: svint32_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i32")]
+        fn _svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t;
+    }
+    unsafe { _svcvt_f64_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f64_s32_x(pg: svbool_t, op: svint32_t) -> svfloat64_t {
+    unsafe { svcvt_f64_s32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f64_s32_z(pg: svbool_t, op: svint32_t) -> svfloat64_t {
+    svcvt_f64_s32_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i64")]
+        fn _svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svcvt_f64_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t {
+    unsafe { svcvt_f64_s64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(scvtf))]
+pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t {
+    svcvt_f64_s64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool_t, op: svuint32_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i32")]
+        fn _svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t;
+    }
+    unsafe { _svcvt_f64_u32_m(inactive, pg.sve_into(), op.as_signed()) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f64_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat64_t {
+    unsafe { svcvt_f64_u32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f64_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat64_t {
+    svcvt_f64_u32_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i64")]
+        fn _svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svcvt_f64_u64_m(inactive, pg.sve_into(), op.as_signed()) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
+    unsafe { svcvt_f64_u64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ucvtf))]
+pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
+    svcvt_f64_u64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f32")]
+        fn _svcvt_s32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
+    }
+    unsafe { _svcvt_s32_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    unsafe { svcvt_s32_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    svcvt_s32_f32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f64")]
+        fn _svcvt_s32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t;
+    }
+    unsafe { _svcvt_s32_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t {
+    unsafe { svcvt_s32_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t {
+    svcvt_s32_f64_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f32")]
+        fn _svcvt_s64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t;
+    }
+    unsafe { _svcvt_s64_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t {
+    unsafe { svcvt_s64_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t {
+    svcvt_s64_f32_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f64")]
+        fn _svcvt_s64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
+    }
+    unsafe { _svcvt_s64_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    unsafe { svcvt_s64_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzs))]
+pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    svcvt_s64_f64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f32")]
+        fn _svcvt_u32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
+    }
+    unsafe { _svcvt_u32_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    unsafe { svcvt_u32_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
+    svcvt_u32_f32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f64_m(inactive: svuint32_t, pg: svbool_t, op: svfloat64_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f64")]
+        fn _svcvt_u32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t;
+    }
+    unsafe { _svcvt_u32_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint32_t {
+    unsafe { svcvt_u32_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u32_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint32_t {
+    svcvt_u32_f64_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f32_m(inactive: svuint64_t, pg: svbool_t, op: svfloat32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f32")]
+        fn _svcvt_u64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t;
+    }
+    unsafe { _svcvt_u64_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint64_t {
+    unsafe { svcvt_u64_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint64_t {
+    svcvt_u64_f32_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f64")]
+        fn _svcvt_u64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
+    }
+    unsafe { _svcvt_u64_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    unsafe { svcvt_u64_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Floating-point convert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtzu))]
+pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
+    svcvt_u64_f64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv4f32")]
+        fn _svdiv_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svdiv_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svdiv_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svdiv_f32_m(pg, op1, op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svdiv_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svdiv_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svdiv_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv2f64")]
+        fn _svdiv_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svdiv_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svdiv_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svdiv_f64_m(pg, op1, op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svdiv_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svdiv_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdiv))]
+pub fn svdiv_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svdiv_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv4i32")]
+        fn _svdiv_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svdiv_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svdiv_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svdiv_s32_m(pg, op1, op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svdiv_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svdiv_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svdiv_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv2i64")]
+        fn _svdiv_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svdiv_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svdiv_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svdiv_s64_m(pg, op1, op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svdiv_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svdiv_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdiv))]
+pub fn svdiv_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svdiv_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv4i32")]
+        fn _svdiv_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svdiv_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svdiv_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svdiv_u32_m(pg, op1, op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svdiv_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svdiv_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svdiv_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv2i64")]
+        fn _svdiv_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svdiv_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svdiv_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svdiv_u64_m(pg, op1, op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svdiv_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svdiv_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Divide"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udiv))]
+pub fn svdiv_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svdiv_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv4f32")]
+        fn _svdivr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svdivr_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svdivr_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svdivr_f32_m(pg, op1, op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svdivr_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svdivr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svdivr_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv2f64")]
+        fn _svdivr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svdivr_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svdivr_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svdivr_f64_m(pg, op1, op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svdivr_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svdivr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fdivr))]
+pub fn svdivr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svdivr_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv4i32")]
+        fn _svdivr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svdivr_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svdivr_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svdivr_s32_m(pg, op1, op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svdivr_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svdivr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svdivr_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv2i64")]
+        fn _svdivr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svdivr_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svdivr_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svdivr_s64_m(pg, op1, op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svdivr_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svdivr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdivr))]
+pub fn svdivr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svdivr_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv4i32")]
+        fn _svdivr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svdivr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svdivr_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svdivr_u32_m(pg, op1, op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svdivr_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svdivr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svdivr_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv2i64")]
+        fn _svdivr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svdivr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svdivr_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svdivr_u64_m(pg, op1, op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svdivr_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svdivr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Divide reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udivr))]
+pub fn svdivr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svdivr_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))]
+pub fn svdot_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint8_t,
+    op3: svint8_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sdot.lane.nxv4i32"
+        )]
+        fn _svdot_lane_s32(
+            op1: svint32_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_index: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svdot_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))]
+pub fn svdot_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sdot.lane.nxv2i64"
+        )]
+        fn _svdot_lane_s64(
+            op1: svint64_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_index: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svdot_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))]
+pub fn svdot_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint8_t,
+    op3: svuint8_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.udot.lane.nxv4i32"
+        )]
+        fn _svdot_lane_u32(
+            op1: svint32_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_index: i32,
+        ) -> svint32_t;
+    }
+    unsafe {
+        _svdot_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned()
+    }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))]
+pub fn svdot_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.udot.lane.nxv2i64"
+        )]
+        fn _svdot_lane_u64(
+            op1: svint64_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_index: i32,
+        ) -> svint64_t;
+    }
+    unsafe {
+        _svdot_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned()
+    }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdot))]
+pub fn svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv4i32")]
+        fn _svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t;
+    }
+    unsafe { _svdot_s32(op1, op2, op3) }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdot))]
+pub fn svdot_n_s32(op1: svint32_t, op2: svint8_t, op3: i8) -> svint32_t {
+    svdot_s32(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdot))]
+pub fn svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv2i64")]
+        fn _svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t;
+    }
+    unsafe { _svdot_s64(op1, op2, op3) }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sdot))]
+pub fn svdot_n_s64(op1: svint64_t, op2: svint16_t, op3: i16) -> svint64_t {
+    svdot_s64(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udot))]
+pub fn svdot_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv4i32")]
+        fn _svdot_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t;
+    }
+    unsafe { _svdot_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udot))]
+pub fn svdot_n_u32(op1: svuint32_t, op2: svuint8_t, op3: u8) -> svuint32_t {
+    svdot_u32(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udot))]
+pub fn svdot_u64(op1: svuint64_t, op2: svuint16_t, op3: svuint16_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv2i64")]
+        fn _svdot_u64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t;
+    }
+    unsafe { _svdot_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(udot))]
+pub fn svdot_n_u64(op1: svuint64_t, op2: svuint16_t, op3: u16) -> svuint64_t {
+    svdot_u64(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_f32(data: svfloat32_t, index: u32) -> svfloat32_t {
+    svtbl_f32(data, svdup_n_u32(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t {
+    svtbl_f64(data, svdup_n_u64(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_s8(data: svint8_t, index: u8) -> svint8_t {
+    svtbl_s8(data, svdup_n_u8(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_s16(data: svint16_t, index: u16) -> svint16_t {
+    svtbl_s16(data, svdup_n_u16(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_s32(data: svint32_t, index: u32) -> svint32_t {
+    svtbl_s32(data, svdup_n_u32(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_s64(data: svint64_t, index: u64) -> svint64_t {
+    svtbl_s64(data, svdup_n_u64(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_u8(data: svuint8_t, index: u8) -> svuint8_t {
+    svtbl_u8(data, svdup_n_u8(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_u16(data: svuint16_t, index: u16) -> svuint16_t {
+    svtbl_u16(data, svdup_n_u16(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_u32(data: svuint32_t, index: u32) -> svuint32_t {
+    svtbl_u32(data, svdup_n_u32(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdup_lane_u64(data: svuint64_t, index: u64) -> svuint64_t {
+    svtbl_u64(data, svdup_n_u64(index))
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbfx))]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svdup_n_b8(op: bool) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i1")]
+        fn _svdup_n_b8(op: bool) -> svbool_t;
+    }
+    unsafe { _svdup_n_b8(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbfx))]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svdup_n_b16(op: bool) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i1")]
+        fn _svdup_n_b16(op: bool) -> svbool8_t;
+    }
+    unsafe { _svdup_n_b16(op).sve_into() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbfx))]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svdup_n_b32(op: bool) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i1")]
+        fn _svdup_n_b32(op: bool) -> svbool4_t;
+    }
+    unsafe { _svdup_n_b32(op).sve_into() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbfx))]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svdup_n_b64(op: bool) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i1")]
+        fn _svdup_n_b64(op: bool) -> svbool2_t;
+    }
+    unsafe { _svdup_n_b64(op).sve_into() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f32(op: f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4f32")]
+        fn _svdup_n_f32(op: f32) -> svfloat32_t;
+    }
+    unsafe { _svdup_n_f32(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f64(op: f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2f64")]
+        fn _svdup_n_f64(op: f64) -> svfloat64_t;
+    }
+    unsafe { _svdup_n_f64(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s8(op: i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i8")]
+        fn _svdup_n_s8(op: i8) -> svint8_t;
+    }
+    unsafe { _svdup_n_s8(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s16(op: i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i16")]
+        fn _svdup_n_s16(op: i16) -> svint16_t;
+    }
+    unsafe { _svdup_n_s16(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s32(op: i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i32")]
+        fn _svdup_n_s32(op: i32) -> svint32_t;
+    }
+    unsafe { _svdup_n_s32(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s64(op: i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i64")]
+        fn _svdup_n_s64(op: i64) -> svint64_t;
+    }
+    unsafe { _svdup_n_s64(op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u8(op: u8) -> svuint8_t {
+    unsafe { svdup_n_s8(op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u16(op: u16) -> svuint16_t {
+    unsafe { svdup_n_s16(op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u32(op: u32) -> svuint32_t {
+    unsafe { svdup_n_s32(op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u64(op: u64) -> svuint64_t {
+    unsafe { svdup_n_s64(op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f32_m(inactive: svfloat32_t, pg: svbool_t, op: f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4f32")]
+        fn _svdup_n_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: f32) -> svfloat32_t;
+    }
+    unsafe { _svdup_n_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f32_x(pg: svbool_t, op: f32) -> svfloat32_t {
+    svdup_n_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f32_z(pg: svbool_t, op: f32) -> svfloat32_t {
+    svdup_n_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f64_m(inactive: svfloat64_t, pg: svbool_t, op: f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2f64")]
+        fn _svdup_n_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: f64) -> svfloat64_t;
+    }
+    unsafe { _svdup_n_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f64_x(pg: svbool_t, op: f64) -> svfloat64_t {
+    svdup_n_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_f64_z(pg: svbool_t, op: f64) -> svfloat64_t {
+    svdup_n_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv16i8")]
+        fn _svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t;
+    }
+    unsafe { _svdup_n_s8_m(inactive, pg, op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s8_x(pg: svbool_t, op: i8) -> svint8_t {
+    svdup_n_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s8_z(pg: svbool_t, op: i8) -> svint8_t {
+    svdup_n_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s16_m(inactive: svint16_t, pg: svbool_t, op: i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv8i16")]
+        fn _svdup_n_s16_m(inactive: svint16_t, pg: svbool8_t, op: i16) -> svint16_t;
+    }
+    unsafe { _svdup_n_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s16_x(pg: svbool_t, op: i16) -> svint16_t {
+    svdup_n_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s16_z(pg: svbool_t, op: i16) -> svint16_t {
+    svdup_n_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s32_m(inactive: svint32_t, pg: svbool_t, op: i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4i32")]
+        fn _svdup_n_s32_m(inactive: svint32_t, pg: svbool4_t, op: i32) -> svint32_t;
+    }
+    unsafe { _svdup_n_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s32_x(pg: svbool_t, op: i32) -> svint32_t {
+    svdup_n_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s32_z(pg: svbool_t, op: i32) -> svint32_t {
+    svdup_n_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s64_m(inactive: svint64_t, pg: svbool_t, op: i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2i64")]
+        fn _svdup_n_s64_m(inactive: svint64_t, pg: svbool2_t, op: i64) -> svint64_t;
+    }
+    unsafe { _svdup_n_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s64_x(pg: svbool_t, op: i64) -> svint64_t {
+    svdup_n_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_s64_z(pg: svbool_t, op: i64) -> svint64_t {
+    svdup_n_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u8_m(inactive: svuint8_t, pg: svbool_t, op: u8) -> svuint8_t {
+    unsafe { svdup_n_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u8_x(pg: svbool_t, op: u8) -> svuint8_t {
+    svdup_n_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u8_z(pg: svbool_t, op: u8) -> svuint8_t {
+    svdup_n_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u16_m(inactive: svuint16_t, pg: svbool_t, op: u16) -> svuint16_t {
+    unsafe { svdup_n_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u16_x(pg: svbool_t, op: u16) -> svuint16_t {
+    svdup_n_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u16_z(pg: svbool_t, op: u16) -> svuint16_t {
+    svdup_n_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u32_m(inactive: svuint32_t, pg: svbool_t, op: u32) -> svuint32_t {
+    unsafe { svdup_n_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u32_x(pg: svbool_t, op: u32) -> svuint32_t {
+    svdup_n_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u32_z(pg: svbool_t, op: u32) -> svuint32_t {
+    svdup_n_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u64_m(inactive: svuint64_t, pg: svbool_t, op: u64) -> svuint64_t {
+    unsafe { svdup_n_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u64_x(pg: svbool_t, op: u64) -> svuint64_t {
+    svdup_n_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Broadcast a scalar value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svdup_n_u64_z(pg: svbool_t, op: u64) -> svuint64_t {
+    svdup_n_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_f32(data: svfloat32_t, index: u64) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.dupq.lane.nxv4f32"
+        )]
+        fn _svdupq_lane_f32(data: svfloat32_t, index: i64) -> svfloat32_t;
+    }
+    unsafe { _svdupq_lane_f32(data, index.as_signed()) }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.dupq.lane.nxv2f64"
+        )]
+        fn _svdupq_lane_f64(data: svfloat64_t, index: i64) -> svfloat64_t;
+    }
+    unsafe { _svdupq_lane_f64(data, index.as_signed()) }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_s8(data: svint8_t, index: u64) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.dupq.lane.nxv16i8"
+        )]
+        fn _svdupq_lane_s8(data: svint8_t, index: i64) -> svint8_t;
+    }
+    unsafe { _svdupq_lane_s8(data, index.as_signed()) }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_s16(data: svint16_t, index: u64) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.dupq.lane.nxv8i16"
+        )]
+        fn _svdupq_lane_s16(data: svint16_t, index: i64) -> svint16_t;
+    }
+    unsafe { _svdupq_lane_s16(data, index.as_signed()) }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_s32(data: svint32_t, index: u64) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.dupq.lane.nxv4i32"
+        )]
+        fn _svdupq_lane_s32(data: svint32_t, index: i64) -> svint32_t;
+    }
+    unsafe { _svdupq_lane_s32(data, index.as_signed()) }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_s64(data: svint64_t, index: u64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.dupq.lane.nxv2i64"
+        )]
+        fn _svdupq_lane_s64(data: svint64_t, index: i64) -> svint64_t;
+    }
+    unsafe { _svdupq_lane_s64(data, index.as_signed()) }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_u8(data: svuint8_t, index: u64) -> svuint8_t {
+    unsafe { svdupq_lane_s8(data.as_signed(), index).as_unsigned() }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_u16(data: svuint16_t, index: u64) -> svuint16_t {
+    unsafe { svdupq_lane_s16(data.as_signed(), index).as_unsigned() }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_u32(data: svuint32_t, index: u64) -> svuint32_t {
+    unsafe { svdupq_lane_s32(data.as_signed(), index).as_unsigned() }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svdupq_lane_u64(data: svuint64_t, index: u64) -> svuint64_t {
+    unsafe { svdupq_lane_s64(data.as_signed(), index).as_unsigned() }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_b16(
+    x0: bool,
+    x1: bool,
+    x2: bool,
+    x3: bool,
+    x4: bool,
+    x5: bool,
+    x6: bool,
+    x7: bool,
+) -> svbool_t {
+    let op1 = svdupq_n_s16(
+        x0 as i16, x1 as i16, x2 as i16, x3 as i16, x4 as i16, x5 as i16, x6 as i16, x7 as i16,
+    );
+    svcmpne_wide_s16(svptrue_b16(), op1, svdup_n_s64(0))
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_b32(x0: bool, x1: bool, x2: bool, x3: bool) -> svbool_t {
+    let op1 = svdupq_n_s32(x0 as i32, x1 as i32, x2 as i32, x3 as i32);
+    svcmpne_wide_s32(svptrue_b32(), op1, svdup_n_s64(0))
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_b64(x0: bool, x1: bool) -> svbool_t {
+    let op1 = svdupq_n_s64(x0 as i64, x1 as i64);
+    svcmpne_s64(svptrue_b64(), op1, svdup_n_s64(0))
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_b8(
+    x0: bool,
+    x1: bool,
+    x2: bool,
+    x3: bool,
+    x4: bool,
+    x5: bool,
+    x6: bool,
+    x7: bool,
+    x8: bool,
+    x9: bool,
+    x10: bool,
+    x11: bool,
+    x12: bool,
+    x13: bool,
+    x14: bool,
+    x15: bool,
+) -> svbool_t {
+    let op1 = svdupq_n_s8(
+        x0 as i8, x1 as i8, x2 as i8, x3 as i8, x4 as i8, x5 as i8, x6 as i8, x7 as i8, x8 as i8,
+        x9 as i8, x10 as i8, x11 as i8, x12 as i8, x13 as i8, x14 as i8, x15 as i8,
+    );
+    svcmpne_wide_s8(svptrue_b8(), op1, svdup_n_s64(0))
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.experimental.vector.insert.nxv4f32.v4f32"
+        )]
+        fn _svdupq_n_f32(op0: svfloat32_t, op1: float32x4_t, idx: i64) -> svfloat32_t;
+    }
+    unsafe {
+        let op = _svdupq_n_f32(svundef_f32(), crate::mem::transmute([x0, x1, x2, x3]), 0);
+        svdupq_lane_f32(op, 0)
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.experimental.vector.insert.nxv4i32.v4i32"
+        )]
+        fn _svdupq_n_s32(op0: svint32_t, op1: int32x4_t, idx: i64) -> svint32_t;
+    }
+    unsafe {
+        let op = _svdupq_n_s32(svundef_s32(), crate::mem::transmute([x0, x1, x2, x3]), 0);
+        svdupq_lane_s32(op, 0)
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t {
+    unsafe {
+        svdupq_n_s32(
+            x0.as_signed(),
+            x1.as_signed(),
+            x2.as_signed(),
+            x3.as_signed(),
+        )
+        .as_unsigned()
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.experimental.vector.insert.nxv2f64.v2f64"
+        )]
+        fn _svdupq_n_f64(op0: svfloat64_t, op1: float64x2_t, idx: i64) -> svfloat64_t;
+    }
+    unsafe {
+        let op = _svdupq_n_f64(svundef_f64(), crate::mem::transmute([x0, x1]), 0);
+        svdupq_lane_f64(op, 0)
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.experimental.vector.insert.nxv2i64.v2i64"
+        )]
+        fn _svdupq_n_s64(op0: svint64_t, op1: int64x2_t, idx: i64) -> svint64_t;
+    }
+    unsafe {
+        let op = _svdupq_n_s64(svundef_s64(), crate::mem::transmute([x0, x1]), 0);
+        svdupq_lane_s64(op, 0)
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t {
+    unsafe { svdupq_n_s64(x0.as_signed(), x1.as_signed()).as_unsigned() }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_s16(
+    x0: i16,
+    x1: i16,
+    x2: i16,
+    x3: i16,
+    x4: i16,
+    x5: i16,
+    x6: i16,
+    x7: i16,
+) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.experimental.vector.insert.nxv8i16.v8i16"
+        )]
+        fn _svdupq_n_s16(op0: svint16_t, op1: int16x8_t, idx: i64) -> svint16_t;
+    }
+    unsafe {
+        let op = _svdupq_n_s16(
+            svundef_s16(),
+            crate::mem::transmute([x0, x1, x2, x3, x4, x5, x6, x7]),
+            0,
+        );
+        svdupq_lane_s16(op, 0)
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_u16(
+    x0: u16,
+    x1: u16,
+    x2: u16,
+    x3: u16,
+    x4: u16,
+    x5: u16,
+    x6: u16,
+    x7: u16,
+) -> svuint16_t {
+    unsafe {
+        svdupq_n_s16(
+            x0.as_signed(),
+            x1.as_signed(),
+            x2.as_signed(),
+            x3.as_signed(),
+            x4.as_signed(),
+            x5.as_signed(),
+            x6.as_signed(),
+            x7.as_signed(),
+        )
+        .as_unsigned()
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_s8(
+    x0: i8,
+    x1: i8,
+    x2: i8,
+    x3: i8,
+    x4: i8,
+    x5: i8,
+    x6: i8,
+    x7: i8,
+    x8: i8,
+    x9: i8,
+    x10: i8,
+    x11: i8,
+    x12: i8,
+    x13: i8,
+    x14: i8,
+    x15: i8,
+) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.experimental.vector.insert.nxv16i8.v16i8"
+        )]
+        fn _svdupq_n_s8(op0: svint8_t, op1: int8x16_t, idx: i64) -> svint8_t;
+    }
+    unsafe {
+        let op = _svdupq_n_s8(
+            svundef_s8(),
+            crate::mem::transmute([
+                x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+            ]),
+            0,
+        );
+        svdupq_lane_s8(op, 0)
+    }
+}
+#[doc = "Broadcast a quadword of scalars"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svdupq_n_u8(
+    x0: u8,
+    x1: u8,
+    x2: u8,
+    x3: u8,
+    x4: u8,
+    x5: u8,
+    x6: u8,
+    x7: u8,
+    x8: u8,
+    x9: u8,
+    x10: u8,
+    x11: u8,
+    x12: u8,
+    x13: u8,
+    x14: u8,
+    x15: u8,
+) -> svuint8_t {
+    unsafe {
+        svdupq_n_s8(
+            x0.as_signed(),
+            x1.as_signed(),
+            x2.as_signed(),
+            x3.as_signed(),
+            x4.as_signed(),
+            x5.as_signed(),
+            x6.as_signed(),
+            x7.as_signed(),
+            x8.as_signed(),
+            x9.as_signed(),
+            x10.as_signed(),
+            x11.as_signed(),
+            x12.as_signed(),
+            x13.as_signed(),
+            x14.as_signed(),
+            x15.as_signed(),
+        )
+        .as_unsigned()
+    }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nvx16i1")]
+        fn _sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _sveor_b_z(pg, op1, op2) }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv16i8")]
+        fn _sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _sveor_s8_m(pg, op1, op2) }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    sveor_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    sveor_s8_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    sveor_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    sveor_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    sveor_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv8i16")]
+        fn _sveor_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _sveor_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    sveor_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    sveor_s16_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    sveor_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    sveor_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    sveor_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv4i32")]
+        fn _sveor_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _sveor_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    sveor_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    sveor_s32_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    sveor_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    sveor_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    sveor_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv2i64")]
+        fn _sveor_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _sveor_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    sveor_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    sveor_s64_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    sveor_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    sveor_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    sveor_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { sveor_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    sveor_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    sveor_u8_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    sveor_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    sveor_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    sveor_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { sveor_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    sveor_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    sveor_u16_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    sveor_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    sveor_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    sveor_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { sveor_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    sveor_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    sveor_u32_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    sveor_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    sveor_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    sveor_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { sveor_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    sveor_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    sveor_u64_m(pg, op1, op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    sveor_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    sveor_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Bitwise exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor))]
+pub fn sveor_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    sveor_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv16i8")]
+        fn _sveorv_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _sveorv_s8(pg, op) }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv8i16")]
+        fn _sveorv_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _sveorv_s16(pg.sve_into(), op) }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv4i32")]
+        fn _sveorv_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _sveorv_s32(pg.sve_into(), op) }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv2i64")]
+        fn _sveorv_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _sveorv_s64(pg.sve_into(), op) }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe { sveorv_s8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe { sveorv_s16(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe { sveorv_s32(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorv))]
+pub fn sveorv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe { sveorv_s64(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Floating-point exponential accelerator"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fexpa))]
+pub fn svexpa_f32(op: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fexpa.x.nxv4f32 "
+        )]
+        fn _svexpa_f32(op: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svexpa_f32(op.as_signed()) }
+}
+#[doc = "Floating-point exponential accelerator"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fexpa))]
+pub fn svexpa_f64(op: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fexpa.x.nxv2f64 "
+        )]
+        fn _svexpa_f64(op: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svexpa_f64(op.as_signed()) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_f32<const IMM3: i32>(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    static_assert_range!(IMM3, 0..=63);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4f32")]
+        fn _svext_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t;
+    }
+    unsafe { _svext_f32(op1, op2, IMM3) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_f64<const IMM3: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    static_assert_range!(IMM3, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2f64")]
+        fn _svext_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t;
+    }
+    unsafe { _svext_f64(op1, op2, IMM3) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert_range!(IMM3, 0..=255);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv16i8")]
+        fn _svext_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svext_s8(op1, op2, IMM3) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM3, 0..=127);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv8i16")]
+        fn _svext_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svext_s16(op1, op2, IMM3) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM3, 0..=63);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4i32")]
+        fn _svext_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svext_s32(op1, op2, IMM3) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM3, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2i64")]
+        fn _svext_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svext_s64(op1, op2, IMM3) }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM3, 0..=255);
+    unsafe { svext_s8::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM3, 0..=127);
+    unsafe { svext_s16::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM3, 0..=63);
+    unsafe { svext_s32::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Extract vector from pair of vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
+pub fn svext_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM3, 0..=31);
+    unsafe { svext_s64::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv8i16")]
+        fn _svextb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svextb_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svextb_s16_m(op, pg, op)
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svextb_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv4i32")]
+        fn _svextb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svextb_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svextb_s32_m(op, pg, op)
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svextb_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Sign-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxth))]
+pub fn svexth_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv4i32")]
+        fn _svexth_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svexth_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Sign-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxth))]
+pub fn svexth_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svexth_s32_m(op, pg, op)
+}
+#[doc = "Sign-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxth))]
+pub fn svexth_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svexth_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv2i64")]
+        fn _svextb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svextb_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svextb_s64_m(op, pg, op)
+}
+#[doc = "Sign-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtb))]
+pub fn svextb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svextb_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Sign-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxth))]
+pub fn svexth_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv2i64")]
+        fn _svexth_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svexth_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Sign-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxth))]
+pub fn svexth_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svexth_s64_m(op, pg, op)
+}
+#[doc = "Sign-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxth))]
+pub fn svexth_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svexth_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Sign-extend the low 32 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtw))]
+pub fn svextw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtw.nxv2i64")]
+        fn _svextw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svextw_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Sign-extend the low 32 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtw))]
+pub fn svextw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svextw_s64_m(op, pg, op)
+}
+#[doc = "Sign-extend the low 32 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sxtw))]
+pub fn svextw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svextw_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv8i16")]
+        fn _svextb_u16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svextb_u16_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svextb_u16_m(op, pg, op)
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svextb_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv4i32")]
+        fn _svextb_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svextb_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svextb_u32_m(op, pg, op)
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svextb_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Zero-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxth))]
+pub fn svexth_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv4i32")]
+        fn _svexth_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svexth_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Zero-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxth))]
+pub fn svexth_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svexth_u32_m(op, pg, op)
+}
+#[doc = "Zero-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxth))]
+pub fn svexth_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svexth_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv2i64")]
+        fn _svextb_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svextb_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svextb_u64_m(op, pg, op)
+}
+#[doc = "Zero-extend the low 8 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtb))]
+pub fn svextb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svextb_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Zero-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxth))]
+pub fn svexth_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv2i64")]
+        fn _svexth_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svexth_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Zero-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxth))]
+pub fn svexth_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svexth_u64_m(op, pg, op)
+}
+#[doc = "Zero-extend the low 16 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxth))]
+pub fn svexth_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svexth_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Zero-extend the low 32 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtw))]
+pub fn svextw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtw.nxv2i64")]
+        fn _svextw_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svextw_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Zero-extend the low 32 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtw))]
+pub fn svextw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svextw_u64_m(op, pg, op)
+}
+#[doc = "Zero-extend the low 32 bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uxtw))]
+pub fn svextw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svextw_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_f32<const IMM_INDEX: i32>(tuple: svfloat32x2_t) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_f64<const IMM_INDEX: i32>(tuple: svfloat64x2_t) -> svfloat64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_s8<const IMM_INDEX: i32>(tuple: svint8x2_t) -> svint8_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_s16<const IMM_INDEX: i32>(tuple: svint16x2_t) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_s32<const IMM_INDEX: i32>(tuple: svint32x2_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_s64<const IMM_INDEX: i32>(tuple: svint64x2_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_u8<const IMM_INDEX: i32>(tuple: svuint8x2_t) -> svuint8_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_u16<const IMM_INDEX: i32>(tuple: svuint16x2_t) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_u32<const IMM_INDEX: i32>(tuple: svuint32x2_t) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget2_u64<const IMM_INDEX: i32>(tuple: svuint64x2_t) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_f32<const IMM_INDEX: i32>(tuple: svfloat32x3_t) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_f64<const IMM_INDEX: i32>(tuple: svfloat64x3_t) -> svfloat64_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_s8<const IMM_INDEX: i32>(tuple: svint8x3_t) -> svint8_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_s16<const IMM_INDEX: i32>(tuple: svint16x3_t) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_s32<const IMM_INDEX: i32>(tuple: svint32x3_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_s64<const IMM_INDEX: i32>(tuple: svint64x3_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_u8<const IMM_INDEX: i32>(tuple: svuint8x3_t) -> svuint8_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_u16<const IMM_INDEX: i32>(tuple: svuint16x3_t) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_u32<const IMM_INDEX: i32>(tuple: svuint32x3_t) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget3_u64<const IMM_INDEX: i32>(tuple: svuint64x3_t) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_f32<const IMM_INDEX: i32>(tuple: svfloat32x4_t) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_f64<const IMM_INDEX: i32>(tuple: svfloat64x4_t) -> svfloat64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_s8<const IMM_INDEX: i32>(tuple: svint8x4_t) -> svint8_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_s16<const IMM_INDEX: i32>(tuple: svint16x4_t) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_s32<const IMM_INDEX: i32>(tuple: svint32x4_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_s64<const IMM_INDEX: i32>(tuple: svint64x4_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_u8<const IMM_INDEX: i32>(tuple: svuint8x4_t) -> svuint8_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_u16<const IMM_INDEX: i32>(tuple: svuint16x4_t) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_u32<const IMM_INDEX: i32>(tuple: svuint32x4_t) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Extract one vector from a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svget4_u64<const IMM_INDEX: i32>(tuple: svuint64x4_t) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_s8(base: i8, step: i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv16i8")]
+        fn _svindex_s8(base: i8, step: i8) -> svint8_t;
+    }
+    unsafe { _svindex_s8(base, step) }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_s16(base: i16, step: i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv8i16")]
+        fn _svindex_s16(base: i16, step: i16) -> svint16_t;
+    }
+    unsafe { _svindex_s16(base, step) }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_s32(base: i32, step: i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv4i32")]
+        fn _svindex_s32(base: i32, step: i32) -> svint32_t;
+    }
+    unsafe { _svindex_s32(base, step) }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_s64(base: i64, step: i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv2i64")]
+        fn _svindex_s64(base: i64, step: i64) -> svint64_t;
+    }
+    unsafe { _svindex_s64(base, step) }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_u8(base: u8, step: u8) -> svuint8_t {
+    unsafe { svindex_s8(base.as_signed(), step.as_signed()).as_unsigned() }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_u16(base: u16, step: u16) -> svuint16_t {
+    unsafe { svindex_s16(base.as_signed(), step.as_signed()).as_unsigned() }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_u32(base: u32, step: u32) -> svuint32_t {
+    unsafe { svindex_s32(base.as_signed(), step.as_signed()).as_unsigned() }
+}
+#[doc = "Create linear series"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(index))]
+pub fn svindex_u64(base: u64, step: u64) -> svuint64_t {
+    unsafe { svindex_s64(base.as_signed(), step.as_signed()).as_unsigned() }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4f32")]
+        fn _svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t;
+    }
+    unsafe { _svinsr_n_f32(op1, op2) }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2f64")]
+        fn _svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t;
+    }
+    unsafe { _svinsr_n_f64(op1, op2) }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv16i8")]
+        fn _svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t;
+    }
+    unsafe { _svinsr_n_s8(op1, op2) }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv8i16")]
+        fn _svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t;
+    }
+    unsafe { _svinsr_n_s16(op1, op2) }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4i32")]
+        fn _svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t;
+    }
+    unsafe { _svinsr_n_s32(op1, op2) }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2i64")]
+        fn _svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t;
+    }
+    unsafe { _svinsr_n_s64(op1, op2) }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    unsafe { svinsr_n_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
+    unsafe { svinsr_n_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    unsafe { svinsr_n_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Insert scalar in shifted vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(insr))]
+pub fn svinsr_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    unsafe { svinsr_n_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4f32")]
+        fn _svlasta_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svlasta_f32(pg.sve_into(), op) }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2f64")]
+        fn _svlasta_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svlasta_f64(pg.sve_into(), op) }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv16i8")]
+        fn _svlasta_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svlasta_s8(pg, op) }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv8i16")]
+        fn _svlasta_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svlasta_s16(pg.sve_into(), op) }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4i32")]
+        fn _svlasta_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svlasta_s32(pg.sve_into(), op) }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2i64")]
+        fn _svlasta_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svlasta_s64(pg.sve_into(), op) }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe { svlasta_s8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe { svlasta_s16(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe { svlasta_s32(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract element after last"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lasta))]
+pub fn svlasta_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe { svlasta_s64(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4f32")]
+        fn _svlastb_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svlastb_f32(pg.sve_into(), op) }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2f64")]
+        fn _svlastb_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svlastb_f64(pg.sve_into(), op) }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv16i8")]
+        fn _svlastb_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svlastb_s8(pg, op) }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv8i16")]
+        fn _svlastb_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svlastb_s16(pg.sve_into(), op) }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4i32")]
+        fn _svlastb_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svlastb_s32(pg.sve_into(), op) }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2i64")]
+        fn _svlastb_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svlastb_s64(pg.sve_into(), op) }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe { svlastb_s8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe { svlastb_s16(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe { svlastb_s32(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Extract last element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lastb))]
+pub fn svlastb_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe { svlastb_s64(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4f32")]
+        fn _svld1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t;
+    }
+    _svld1_f32(pg.sve_into(), base)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2f64")]
+        fn _svld1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t;
+    }
+    _svld1_f64(pg.sve_into(), base)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv16i8")]
+        fn _svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t;
+    }
+    _svld1_s8(pg, base)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i16")]
+        fn _svld1_s16(pg: svbool8_t, base: *const i16) -> svint16_t;
+    }
+    _svld1_s16(pg.sve_into(), base)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i32")]
+        fn _svld1_s32(pg: svbool4_t, base: *const i32) -> svint32_t;
+    }
+    _svld1_s32(pg.sve_into(), base)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i64")]
+        fn _svld1_s64(pg: svbool2_t, base: *const i64) -> svint64_t;
+    }
+    _svld1_s64(pg.sve_into(), base)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
+    svld1_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
+    svld1_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
+    svld1_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
+    svld1_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_s32index_f32(
+    pg: svbool_t,
+    base: *const f32,
+    indices: svint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4f32"
+        )]
+        fn _svld1_gather_s32index_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            indices: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svld1_gather_s32index_f32(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_s32index_s32(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32"
+        )]
+        fn _svld1_gather_s32index_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            indices: svint32_t,
+        ) -> svint32_t;
+    }
+    _svld1_gather_s32index_s32(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_s32index_u32(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint32_t,
+) -> svuint32_t {
+    svld1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_s64index_f64(
+    pg: svbool_t,
+    base: *const f64,
+    indices: svint64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2f64"
+        )]
+        fn _svld1_gather_s64index_f64(
+            pg: svbool2_t,
+            base: *const f64,
+            indices: svint64_t,
+        ) -> svfloat64_t;
+    }
+    _svld1_gather_s64index_f64(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i64,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i64"
+        )]
+        fn _svld1_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i64,
+            indices: svint64_t,
+        ) -> svint64_t;
+    }
+    _svld1_gather_s64index_s64(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u64,
+    indices: svint64_t,
+) -> svuint64_t {
+    svld1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32index_f32(
+    pg: svbool_t,
+    base: *const f32,
+    indices: svuint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4f32"
+        )]
+        fn _svld1_gather_u32index_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            indices: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svld1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32index_s32(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32"
+        )]
+        fn _svld1_gather_u32index_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            indices: svint32_t,
+        ) -> svint32_t;
+    }
+    _svld1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32index_u32(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint32_t,
+) -> svuint32_t {
+    svld1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64index_f64(
+    pg: svbool_t,
+    base: *const f64,
+    indices: svuint64_t,
+) -> svfloat64_t {
+    svld1_gather_s64index_f64(pg, base, indices.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i64,
+    indices: svuint64_t,
+) -> svint64_t {
+    svld1_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u64,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svld1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_s32offset_f32(
+    pg: svbool_t,
+    base: *const f32,
+    offsets: svint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32"
+        )]
+        fn _svld1_gather_s32offset_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            offsets: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svld1_gather_s32offset_f32(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32"
+        )]
+        fn _svld1_gather_s32offset_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            offsets: svint32_t,
+        ) -> svint32_t;
+    }
+    _svld1_gather_s32offset_s32(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint32_t,
+) -> svuint32_t {
+    svld1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_s64offset_f64(
+    pg: svbool_t,
+    base: *const f64,
+    offsets: svint64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2f64"
+        )]
+        fn _svld1_gather_s64offset_f64(
+            pg: svbool2_t,
+            base: *const f64,
+            offsets: svint64_t,
+        ) -> svfloat64_t;
+    }
+    _svld1_gather_s64offset_f64(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i64,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i64"
+        )]
+        fn _svld1_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i64,
+            offsets: svint64_t,
+        ) -> svint64_t;
+    }
+    _svld1_gather_s64offset_s64(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u64,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svld1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32offset_f32(
+    pg: svbool_t,
+    base: *const f32,
+    offsets: svuint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32"
+        )]
+        fn _svld1_gather_u32offset_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            offsets: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svld1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32"
+        )]
+        fn _svld1_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            offsets: svint32_t,
+        ) -> svint32_t;
+    }
+    _svld1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svld1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64offset_f64(
+    pg: svbool_t,
+    base: *const f64,
+    offsets: svuint64_t,
+) -> svfloat64_t {
+    svld1_gather_s64offset_f64(pg, base, offsets.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i64,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u64,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t {
+    svld1_gather_u32base_offset_f32(pg, bases, 0)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svld1_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svld1_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t {
+    svld1_gather_u64base_offset_f64(pg, bases, 0)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_index_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svfloat32_t {
+    svld1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svld1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svld1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_index_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svfloat64_t {
+    svld1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svld1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svld1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_offset_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32"
+        )]
+        fn _svld1_gather_u32base_offset_f32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> svfloat32_t;
+    }
+    _svld1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32"
+        )]
+        fn _svld1_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> svint32_t;
+    }
+    _svld1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svld1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_offset_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64"
+        )]
+        fn _svld1_gather_u64base_offset_f64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> svfloat64_t;
+    }
+    _svld1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64"
+        )]
+        fn _svld1_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> svint64_t;
+    }
+    _svld1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svld1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t {
+    svld1_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t {
+    svld1_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t {
+    svld1_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t {
+    svld1_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t {
+    svld1_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t {
+    svld1_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t {
+    svld1_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t {
+    svld1_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t {
+    svld1_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1d))]
+pub unsafe fn svld1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t {
+    svld1_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1row))]
+pub unsafe fn svld1ro_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4f32")]
+        fn _svld1ro_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t;
+    }
+    _svld1ro_f32(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rod))]
+pub unsafe fn svld1ro_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2f64")]
+        fn _svld1ro_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t;
+    }
+    _svld1ro_f64(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rob))]
+pub unsafe fn svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv16i8")]
+        fn _svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t;
+    }
+    _svld1ro_s8(pg, base)
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1roh))]
+pub unsafe fn svld1ro_s16(pg: svbool_t, base: *const i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv8i16")]
+        fn _svld1ro_s16(pg: svbool8_t, base: *const i16) -> svint16_t;
+    }
+    _svld1ro_s16(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1row))]
+pub unsafe fn svld1ro_s32(pg: svbool_t, base: *const i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4i32")]
+        fn _svld1ro_s32(pg: svbool4_t, base: *const i32) -> svint32_t;
+    }
+    _svld1ro_s32(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rod))]
+pub unsafe fn svld1ro_s64(pg: svbool_t, base: *const i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2i64")]
+        fn _svld1ro_s64(pg: svbool2_t, base: *const i64) -> svint64_t;
+    }
+    _svld1ro_s64(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rob))]
+pub unsafe fn svld1ro_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
+    svld1ro_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1roh))]
+pub unsafe fn svld1ro_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
+    svld1ro_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1row))]
+pub unsafe fn svld1ro_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
+    svld1ro_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 256 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rod))]
+pub unsafe fn svld1ro_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
+    svld1ro_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqw))]
+pub unsafe fn svld1rq_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4f32")]
+        fn _svld1rq_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t;
+    }
+    _svld1rq_f32(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqd))]
+pub unsafe fn svld1rq_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2f64")]
+        fn _svld1rq_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t;
+    }
+    _svld1rq_f64(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqb))]
+pub unsafe fn svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv16i8")]
+        fn _svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t;
+    }
+    _svld1rq_s8(pg, base)
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqh))]
+pub unsafe fn svld1rq_s16(pg: svbool_t, base: *const i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv8i16")]
+        fn _svld1rq_s16(pg: svbool8_t, base: *const i16) -> svint16_t;
+    }
+    _svld1rq_s16(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqw))]
+pub unsafe fn svld1rq_s32(pg: svbool_t, base: *const i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4i32")]
+        fn _svld1rq_s32(pg: svbool4_t, base: *const i32) -> svint32_t;
+    }
+    _svld1rq_s32(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqd))]
+pub unsafe fn svld1rq_s64(pg: svbool_t, base: *const i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2i64")]
+        fn _svld1rq_s64(pg: svbool2_t, base: *const i64) -> svint64_t;
+    }
+    _svld1rq_s64(pg.sve_into(), base)
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqb))]
+pub unsafe fn svld1rq_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
+    svld1rq_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqh))]
+pub unsafe fn svld1rq_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
+    svld1rq_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqw))]
+pub unsafe fn svld1rq_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
+    svld1rq_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load and replicate 128 bits of data"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1rqd))]
+pub unsafe fn svld1rq_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
+    svld1rq_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8"
+        )]
+        fn _svld1sb_gather_s32offset_s32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_gather_s32offset_s32(pg.sve_into(), base, offsets))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16"
+        )]
+        fn _svld1sh_gather_s32offset_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32offset_s32(pg.sve_into(), base, offsets))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint32_t,
+) -> svuint32_t {
+    svld1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint32_t,
+) -> svuint32_t {
+    svld1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8"
+        )]
+        fn _svld1sb_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i8,
+            offsets: svint64_t,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_gather_s64offset_s64(pg.sve_into(), base, offsets))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16"
+        )]
+        fn _svld1sh_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i16,
+            offsets: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64offset_s64(pg.sve_into(), base, offsets))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32"
+        )]
+        fn _svld1sw_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i32,
+            offsets: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64offset_s64(pg.sve_into(), base, offsets))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svld1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svld1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svld1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8"
+        )]
+        fn _svld1sb_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16"
+        )]
+        fn _svld1sh_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svld1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svld1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svld1sb_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32base_offset_s32(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svld1sh_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32base_offset_s32(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svld1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svld1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svld1sb_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svld1sh_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svld1sw_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sw_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svld1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svld1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svld1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svld1sb_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svld1sh_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svld1sb_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svld1sh_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1sb_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1sh_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1sw_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1sb_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1sh_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1sw_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")]
+        fn _svld1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_s16(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")]
+        fn _svld1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_s32(pg.sve_into(), base))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")]
+        fn _svld1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_s32(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")]
+        fn _svld1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sb_s64(pg.sve_into(), base))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")]
+        fn _svld1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_s64(pg.sve_into(), base))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")]
+        fn _svld1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sw_s64(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t {
+    svld1sb_s16(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t {
+    svld1sb_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t {
+    svld1sh_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t {
+    svld1sb_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t {
+    svld1sh_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t {
+    svld1sw_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t {
+    svld1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t {
+    svld1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t {
+    svld1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t {
+    svld1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t {
+    svld1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t {
+    svld1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t {
+    svld1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t {
+    svld1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t {
+    svld1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sb))]
+pub unsafe fn svld1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t {
+    svld1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t {
+    svld1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t {
+    svld1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s32index_s32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16"
+        )]
+        fn _svld1sh_gather_s32index_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32index_s32(pg.sve_into(), base, indices))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s32index_u32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint32_t,
+) -> svuint32_t {
+    svld1sh_gather_s32index_s32(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16"
+        )]
+        fn _svld1sh_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i16,
+            indices: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64index_s64(pg.sve_into(), base, indices))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32"
+        )]
+        fn _svld1sw_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i32,
+            indices: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64index_s64(pg.sve_into(), base, indices))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint64_t,
+) -> svuint64_t {
+    svld1sh_gather_s64index_s64(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint64_t,
+) -> svuint64_t {
+    svld1sw_gather_s64index_s64(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32index_s32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16"
+        )]
+        fn _svld1sh_gather_u32index_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32index_s32(
+        pg.sve_into(),
+        base,
+        indices.as_signed(),
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32index_u32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint32_t,
+) -> svuint32_t {
+    svld1sh_gather_u32index_s32(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint64_t,
+) -> svint64_t {
+    svld1sh_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint64_t,
+) -> svint64_t {
+    svld1sw_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svld1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svld1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svld1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svld1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svld1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svld1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 16-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sh))]
+pub unsafe fn svld1sh_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svld1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and sign-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1sw))]
+pub unsafe fn svld1sw_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svld1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint32_t,
+) -> svint32_t {
+    svld1ub_gather_s32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint32_t,
+) -> svint32_t {
+    svld1uh_gather_s32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8"
+        )]
+        fn _svld1ub_gather_s32offset_u32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svld1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16"
+        )]
+        fn _svld1uh_gather_s32offset_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svld1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint64_t,
+) -> svint64_t {
+    svld1ub_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint64_t,
+) -> svint64_t {
+    svld1uh_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint64_t,
+) -> svint64_t {
+    svld1uw_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8"
+        )]
+        fn _svld1ub_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i8,
+            offsets: svint64_t,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svld1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16"
+        )]
+        fn _svld1uh_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i16,
+            offsets: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svld1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32"
+        )]
+        fn _svld1uw_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i32,
+            offsets: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svld1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint32_t,
+) -> svint32_t {
+    svld1ub_gather_u32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint32_t,
+) -> svint32_t {
+    svld1uh_gather_u32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8"
+        )]
+        fn _svld1ub_gather_u32offset_u32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svld1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16"
+        )]
+        fn _svld1uh_gather_u32offset_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svld1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    svld1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    svld1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svld1ub_gather_u32base_offset_u32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svld1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svld1uh_gather_u32base_offset_u32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svld1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svld1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svld1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svld1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svld1ub_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svld1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svld1uh_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svld1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svld1uw_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svld1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svld1ub_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svld1uh_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svld1ub_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svld1uh_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1ub_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1uh_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svld1uw_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1ub_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1uh_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svld1uw_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")]
+        fn _svld1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv8u8, _>(
+        _svld1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")]
+        fn _svld1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svld1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")]
+        fn _svld1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svld1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")]
+        fn _svld1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svld1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")]
+        fn _svld1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svld1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")]
+        fn _svld1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svld1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t {
+    svld1ub_s16(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t {
+    svld1ub_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t {
+    svld1uh_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t {
+    svld1ub_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t {
+    svld1uh_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t {
+    svld1uw_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t {
+    svld1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t {
+    svld1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t {
+    svld1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t {
+    svld1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t {
+    svld1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t {
+    svld1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t {
+    svld1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t {
+    svld1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t {
+    svld1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1b))]
+pub unsafe fn svld1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t {
+    svld1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t {
+    svld1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t {
+    svld1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s32index_s32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint32_t,
+) -> svint32_t {
+    svld1uh_gather_s32index_u32(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s32index_u32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16"
+        )]
+        fn _svld1uh_gather_s32index_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svld1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint64_t,
+) -> svint64_t {
+    svld1uh_gather_s64index_u64(pg, base, indices).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint64_t,
+) -> svint64_t {
+    svld1uw_gather_s64index_u64(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16"
+        )]
+        fn _svld1uh_gather_s64index_u64(
+            pg: svbool2_t,
+            base: *const i16,
+            indices: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svld1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32"
+        )]
+        fn _svld1uw_gather_s64index_u64(
+            pg: svbool2_t,
+            base: *const i32,
+            indices: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svld1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32index_s32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint32_t,
+) -> svint32_t {
+    svld1uh_gather_u32index_u32(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32index_u32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16"
+        )]
+        fn _svld1uh_gather_u32index_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svld1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint64_t,
+) -> svint64_t {
+    svld1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint64_t,
+) -> svint64_t {
+    svld1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svld1uh_gather_s64index_u64(pg, base, indices.as_signed())
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svld1uw_gather_s64index_u64(pg, base, indices.as_signed())
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svld1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svld1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svld1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svld1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 16-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1h))]
+pub unsafe fn svld1uh_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svld1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and zero-extend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld1w))]
+pub unsafe fn svld1uw_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svld1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2w))]
+pub unsafe fn svld2_f32(pg: svbool_t, base: *const f32) -> svfloat32x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld2.sret.nxv4f32"
+        )]
+        fn _svld2_f32(pg: svbool4_t, base: *const f32) -> svfloat32x2_t;
+    }
+    _svld2_f32(pg.sve_into(), base)
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2d))]
+pub unsafe fn svld2_f64(pg: svbool_t, base: *const f64) -> svfloat64x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld2.sret.nxv2f64"
+        )]
+        fn _svld2_f64(pg: svbool2_t, base: *const f64) -> svfloat64x2_t;
+    }
+    _svld2_f64(pg.sve_into(), base)
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2b))]
+pub unsafe fn svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld2.sret.nxv16i8"
+        )]
+        fn _svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t;
+    }
+    _svld2_s8(pg, base)
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2h))]
+pub unsafe fn svld2_s16(pg: svbool_t, base: *const i16) -> svint16x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld2.sret.nxv8i16"
+        )]
+        fn _svld2_s16(pg: svbool8_t, base: *const i16) -> svint16x2_t;
+    }
+    _svld2_s16(pg.sve_into(), base)
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2w))]
+pub unsafe fn svld2_s32(pg: svbool_t, base: *const i32) -> svint32x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld2.sret.nxv4i32"
+        )]
+        fn _svld2_s32(pg: svbool4_t, base: *const i32) -> svint32x2_t;
+    }
+    _svld2_s32(pg.sve_into(), base)
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2d))]
+pub unsafe fn svld2_s64(pg: svbool_t, base: *const i64) -> svint64x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld2.sret.nxv2i64"
+        )]
+        fn _svld2_s64(pg: svbool2_t, base: *const i64) -> svint64x2_t;
+    }
+    _svld2_s64(pg.sve_into(), base)
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2b))]
+pub unsafe fn svld2_u8(pg: svbool_t, base: *const u8) -> svuint8x2_t {
+    svld2_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2h))]
+pub unsafe fn svld2_u16(pg: svbool_t, base: *const u16) -> svuint16x2_t {
+    svld2_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2w))]
+pub unsafe fn svld2_u32(pg: svbool_t, base: *const u32) -> svuint32x2_t {
+    svld2_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2d))]
+pub unsafe fn svld2_u64(pg: svbool_t, base: *const u64) -> svuint64x2_t {
+    svld2_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2w))]
+pub unsafe fn svld2_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x2_t {
+    svld2_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2d))]
+pub unsafe fn svld2_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x2_t {
+    svld2_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2b))]
+pub unsafe fn svld2_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x2_t {
+    svld2_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2h))]
+pub unsafe fn svld2_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x2_t {
+    svld2_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2w))]
+pub unsafe fn svld2_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x2_t {
+    svld2_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2d))]
+pub unsafe fn svld2_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x2_t {
+    svld2_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2b))]
+pub unsafe fn svld2_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x2_t {
+    svld2_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2h))]
+pub unsafe fn svld2_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x2_t {
+    svld2_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2w))]
+pub unsafe fn svld2_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x2_t {
+    svld2_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load two-element tuples into two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld2d))]
+pub unsafe fn svld2_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x2_t {
+    svld2_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3w))]
+pub unsafe fn svld3_f32(pg: svbool_t, base: *const f32) -> svfloat32x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld3.sret.nxv4f32"
+        )]
+        fn _svld3_f32(pg: svbool4_t, base: *const f32) -> svfloat32x3_t;
+    }
+    _svld3_f32(pg.sve_into(), base)
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3d))]
+pub unsafe fn svld3_f64(pg: svbool_t, base: *const f64) -> svfloat64x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld3.sret.nxv2f64"
+        )]
+        fn _svld3_f64(pg: svbool2_t, base: *const f64) -> svfloat64x3_t;
+    }
+    _svld3_f64(pg.sve_into(), base)
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3b))]
+pub unsafe fn svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld3.sret.nxv16i8"
+        )]
+        fn _svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t;
+    }
+    _svld3_s8(pg, base)
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3h))]
+pub unsafe fn svld3_s16(pg: svbool_t, base: *const i16) -> svint16x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld3.sret.nxv8i16"
+        )]
+        fn _svld3_s16(pg: svbool8_t, base: *const i16) -> svint16x3_t;
+    }
+    _svld3_s16(pg.sve_into(), base)
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3w))]
+pub unsafe fn svld3_s32(pg: svbool_t, base: *const i32) -> svint32x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld3.sret.nxv4i32"
+        )]
+        fn _svld3_s32(pg: svbool4_t, base: *const i32) -> svint32x3_t;
+    }
+    _svld3_s32(pg.sve_into(), base)
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3d))]
+pub unsafe fn svld3_s64(pg: svbool_t, base: *const i64) -> svint64x3_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld3.sret.nxv2i64"
+        )]
+        fn _svld3_s64(pg: svbool2_t, base: *const i64) -> svint64x3_t;
+    }
+    _svld3_s64(pg.sve_into(), base)
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3b))]
+pub unsafe fn svld3_u8(pg: svbool_t, base: *const u8) -> svuint8x3_t {
+    svld3_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3h))]
+pub unsafe fn svld3_u16(pg: svbool_t, base: *const u16) -> svuint16x3_t {
+    svld3_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3w))]
+pub unsafe fn svld3_u32(pg: svbool_t, base: *const u32) -> svuint32x3_t {
+    svld3_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3d))]
+pub unsafe fn svld3_u64(pg: svbool_t, base: *const u64) -> svuint64x3_t {
+    svld3_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3w))]
+pub unsafe fn svld3_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x3_t {
+    svld3_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3d))]
+pub unsafe fn svld3_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x3_t {
+    svld3_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3b))]
+pub unsafe fn svld3_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x3_t {
+    svld3_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3h))]
+pub unsafe fn svld3_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x3_t {
+    svld3_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3w))]
+pub unsafe fn svld3_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x3_t {
+    svld3_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3d))]
+pub unsafe fn svld3_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x3_t {
+    svld3_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3b))]
+pub unsafe fn svld3_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x3_t {
+    svld3_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3h))]
+pub unsafe fn svld3_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x3_t {
+    svld3_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3w))]
+pub unsafe fn svld3_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x3_t {
+    svld3_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load three-element tuples into three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld3d))]
+pub unsafe fn svld3_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x3_t {
+    svld3_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4w))]
+pub unsafe fn svld4_f32(pg: svbool_t, base: *const f32) -> svfloat32x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld4.sret.nxv4f32"
+        )]
+        fn _svld4_f32(pg: svbool4_t, base: *const f32) -> svfloat32x4_t;
+    }
+    _svld4_f32(pg.sve_into(), base)
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4d))]
+pub unsafe fn svld4_f64(pg: svbool_t, base: *const f64) -> svfloat64x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld4.sret.nxv2f64"
+        )]
+        fn _svld4_f64(pg: svbool2_t, base: *const f64) -> svfloat64x4_t;
+    }
+    _svld4_f64(pg.sve_into(), base)
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4b))]
+pub unsafe fn svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld4.sret.nxv16i8"
+        )]
+        fn _svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t;
+    }
+    _svld4_s8(pg, base)
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4h))]
+pub unsafe fn svld4_s16(pg: svbool_t, base: *const i16) -> svint16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld4.sret.nxv8i16"
+        )]
+        fn _svld4_s16(pg: svbool8_t, base: *const i16) -> svint16x4_t;
+    }
+    _svld4_s16(pg.sve_into(), base)
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4w))]
+pub unsafe fn svld4_s32(pg: svbool_t, base: *const i32) -> svint32x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld4.sret.nxv4i32"
+        )]
+        fn _svld4_s32(pg: svbool4_t, base: *const i32) -> svint32x4_t;
+    }
+    _svld4_s32(pg.sve_into(), base)
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4d))]
+pub unsafe fn svld4_s64(pg: svbool_t, base: *const i64) -> svint64x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ld4.sret.nxv2i64"
+        )]
+        fn _svld4_s64(pg: svbool2_t, base: *const i64) -> svint64x4_t;
+    }
+    _svld4_s64(pg.sve_into(), base)
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4b))]
+pub unsafe fn svld4_u8(pg: svbool_t, base: *const u8) -> svuint8x4_t {
+    svld4_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4h))]
+pub unsafe fn svld4_u16(pg: svbool_t, base: *const u16) -> svuint16x4_t {
+    svld4_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4w))]
+pub unsafe fn svld4_u32(pg: svbool_t, base: *const u32) -> svuint32x4_t {
+    svld4_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4d))]
+pub unsafe fn svld4_u64(pg: svbool_t, base: *const u64) -> svuint64x4_t {
+    svld4_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4w))]
+pub unsafe fn svld4_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x4_t {
+    svld4_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4d))]
+pub unsafe fn svld4_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x4_t {
+    svld4_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4b))]
+pub unsafe fn svld4_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x4_t {
+    svld4_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4h))]
+pub unsafe fn svld4_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x4_t {
+    svld4_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4w))]
+pub unsafe fn svld4_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x4_t {
+    svld4_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4d))]
+pub unsafe fn svld4_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x4_t {
+    svld4_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4b))]
+pub unsafe fn svld4_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x4_t {
+    svld4_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4h))]
+pub unsafe fn svld4_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x4_t {
+    svld4_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4w))]
+pub unsafe fn svld4_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x4_t {
+    svld4_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load four-element tuples into four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ld4d))]
+pub unsafe fn svld4_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x4_t {
+    svld4_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4f32")]
+        fn _svldff1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t;
+    }
+    _svldff1_f32(pg.sve_into(), base)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2f64")]
+        fn _svldff1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t;
+    }
+    _svldff1_f64(pg.sve_into(), base)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv16i8")]
+        fn _svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t;
+    }
+    _svldff1_s8(pg, base)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i16")]
+        fn _svldff1_s16(pg: svbool8_t, base: *const i16) -> svint16_t;
+    }
+    _svldff1_s16(pg.sve_into(), base)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i32")]
+        fn _svldff1_s32(pg: svbool4_t, base: *const i32) -> svint32_t;
+    }
+    _svldff1_s32(pg.sve_into(), base)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i64")]
+        fn _svldff1_s64(pg: svbool2_t, base: *const i64) -> svint64_t;
+    }
+    _svldff1_s64(pg.sve_into(), base)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
+    svldff1_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
+    svldff1_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
+    svldff1_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
+    svldff1_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_s32index_f32(
+    pg: svbool_t,
+    base: *const f32,
+    indices: svint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32"
+        )]
+        fn _svldff1_gather_s32index_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            indices: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svldff1_gather_s32index_f32(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_s32index_s32(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32"
+        )]
+        fn _svldff1_gather_s32index_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            indices: svint32_t,
+        ) -> svint32_t;
+    }
+    _svldff1_gather_s32index_s32(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_s32index_u32(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint32_t,
+) -> svuint32_t {
+    svldff1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_s64index_f64(
+    pg: svbool_t,
+    base: *const f64,
+    indices: svint64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2f64"
+        )]
+        fn _svldff1_gather_s64index_f64(
+            pg: svbool2_t,
+            base: *const f64,
+            indices: svint64_t,
+        ) -> svfloat64_t;
+    }
+    _svldff1_gather_s64index_f64(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i64,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i64"
+        )]
+        fn _svldff1_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i64,
+            indices: svint64_t,
+        ) -> svint64_t;
+    }
+    _svldff1_gather_s64index_s64(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u64,
+    indices: svint64_t,
+) -> svuint64_t {
+    svldff1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32index_f32(
+    pg: svbool_t,
+    base: *const f32,
+    indices: svuint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32"
+        )]
+        fn _svldff1_gather_u32index_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            indices: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svldff1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32index_s32(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32"
+        )]
+        fn _svldff1_gather_u32index_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            indices: svint32_t,
+        ) -> svint32_t;
+    }
+    _svldff1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32index_u32(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint32_t,
+) -> svuint32_t {
+    svldff1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64index_f64(
+    pg: svbool_t,
+    base: *const f64,
+    indices: svuint64_t,
+) -> svfloat64_t {
+    svldff1_gather_s64index_f64(pg, base, indices.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i64,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldff1_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u64,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldff1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_s32offset_f32(
+    pg: svbool_t,
+    base: *const f32,
+    offsets: svint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4f32"
+        )]
+        fn _svldff1_gather_s32offset_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            offsets: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svldff1_gather_s32offset_f32(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i32"
+        )]
+        fn _svldff1_gather_s32offset_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            offsets: svint32_t,
+        ) -> svint32_t;
+    }
+    _svldff1_gather_s32offset_s32(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint32_t,
+) -> svuint32_t {
+    svldff1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_s64offset_f64(
+    pg: svbool_t,
+    base: *const f64,
+    offsets: svint64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2f64"
+        )]
+        fn _svldff1_gather_s64offset_f64(
+            pg: svbool2_t,
+            base: *const f64,
+            offsets: svint64_t,
+        ) -> svfloat64_t;
+    }
+    _svldff1_gather_s64offset_f64(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i64,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i64"
+        )]
+        fn _svldff1_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i64,
+            offsets: svint64_t,
+        ) -> svint64_t;
+    }
+    _svldff1_gather_s64offset_s64(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u64,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32offset_f32(
+    pg: svbool_t,
+    base: *const f32,
+    offsets: svuint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4f32"
+        )]
+        fn _svldff1_gather_u32offset_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            offsets: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svldff1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i32"
+        )]
+        fn _svldff1_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            offsets: svint32_t,
+        ) -> svint32_t;
+    }
+    _svldff1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svldff1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64offset_f64(
+    pg: svbool_t,
+    base: *const f64,
+    offsets: svuint64_t,
+) -> svfloat64_t {
+    svldff1_gather_s64offset_f64(pg, base, offsets.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i64,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u64,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t {
+    svldff1_gather_u32base_offset_f32(pg, bases, 0)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldff1_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldff1_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t {
+    svldff1_gather_u64base_offset_f64(pg, bases, 0)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_index_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svfloat32_t {
+    svldff1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svldff1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svldff1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_index_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svfloat64_t {
+    svldff1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldff1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldff1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_offset_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32"
+        )]
+        fn _svldff1_gather_u32base_offset_f32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> svfloat32_t;
+    }
+    _svldff1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32"
+        )]
+        fn _svldff1_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> svint32_t;
+    }
+    _svldff1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svldff1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_offset_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64"
+        )]
+        fn _svldff1_gather_u64base_offset_f64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> svfloat64_t;
+    }
+    _svldff1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64"
+        )]
+        fn _svldff1_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> svint64_t;
+    }
+    _svldff1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldff1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t {
+    svldff1_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t {
+    svldff1_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t {
+    svldff1_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t {
+    svldff1_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t {
+    svldff1_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t {
+    svldff1_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t {
+    svldff1_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t {
+    svldff1_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t {
+    svldff1_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1d))]
+pub unsafe fn svldff1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t {
+    svldff1_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8"
+        )]
+        fn _svldff1sb_gather_s32offset_s32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16"
+        )]
+        fn _svldff1sh_gather_s32offset_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint32_t,
+) -> svuint32_t {
+    svldff1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint32_t,
+) -> svuint32_t {
+    svldff1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8"
+        )]
+        fn _svldff1sb_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i8,
+            offsets: svint64_t,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s64offset_s64(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16"
+        )]
+        fn _svldff1sh_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i16,
+            offsets: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64offset_s64(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32"
+        )]
+        fn _svldff1sw_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i32,
+            offsets: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64offset_s64(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldff1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldff1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldff1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8"
+        )]
+        fn _svldff1sb_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16"
+        )]
+        fn _svldff1sh_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svldff1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svldff1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svldff1sb_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32base_offset_s32(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svldff1sh_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32base_offset_s32(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svldff1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svldff1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svldff1sb_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svldff1sh_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svldff1sw_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sw_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldff1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldff1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldff1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldff1sb_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldff1sh_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldff1sb_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldff1sh_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1sb_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1sh_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1sw_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1sb_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1sh_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1sw_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")]
+        fn _svldff1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_s16(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")]
+        fn _svldff1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_s32(pg.sve_into(), base))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")]
+        fn _svldff1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_s32(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")]
+        fn _svldff1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sb_s64(pg.sve_into(), base))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")]
+        fn _svldff1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_s64(pg.sve_into(), base))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")]
+        fn _svldff1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sw_s64(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t {
+    svldff1sb_s16(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t {
+    svldff1sb_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t {
+    svldff1sh_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t {
+    svldff1sb_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t {
+    svldff1sh_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t {
+    svldff1sw_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t {
+    svldff1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t {
+    svldff1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t {
+    svldff1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t {
+    svldff1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t {
+    svldff1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t {
+    svldff1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t {
+    svldff1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t {
+    svldff1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t {
+    svldff1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sb))]
+pub unsafe fn svldff1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t {
+    svldff1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t {
+    svldff1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t {
+    svldff1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s32index_s32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16"
+        )]
+        fn _svldff1sh_gather_s32index_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32index_s32(pg.sve_into(), base, indices))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s32index_u32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint32_t,
+) -> svuint32_t {
+    svldff1sh_gather_s32index_s32(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16"
+        )]
+        fn _svldff1sh_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i16,
+            indices: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64index_s64(pg.sve_into(), base, indices))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32"
+        )]
+        fn _svldff1sw_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i32,
+            indices: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64index_s64(pg.sve_into(), base, indices))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint64_t,
+) -> svuint64_t {
+    svldff1sh_gather_s64index_s64(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint64_t,
+) -> svuint64_t {
+    svldff1sw_gather_s64index_s64(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32index_s32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16"
+        )]
+        fn _svldff1sh_gather_u32index_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32index_s32(
+        pg.sve_into(),
+        base,
+        indices.as_signed(),
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32index_u32(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint32_t,
+) -> svuint32_t {
+    svldff1sh_gather_u32index_s32(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldff1sh_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldff1sw_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svldff1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svldff1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldff1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldff1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 16-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sh))]
+pub unsafe fn svldff1sh_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldff1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and sign-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1sw))]
+pub unsafe fn svldff1sw_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldff1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint32_t,
+) -> svint32_t {
+    svldff1ub_gather_s32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s32offset_s32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint32_t,
+) -> svint32_t {
+    svldff1uh_gather_s32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8"
+        )]
+        fn _svldff1ub_gather_s32offset_u32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldff1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s32offset_u32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16"
+        )]
+        fn _svldff1uh_gather_s32offset_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldff1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint64_t,
+) -> svint64_t {
+    svldff1ub_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint64_t,
+) -> svint64_t {
+    svldff1uh_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint64_t,
+) -> svint64_t {
+    svldff1uw_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8"
+        )]
+        fn _svldff1ub_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i8,
+            offsets: svint64_t,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svldff1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16"
+        )]
+        fn _svldff1uh_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i16,
+            offsets: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldff1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32"
+        )]
+        fn _svldff1uw_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i32,
+            offsets: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldff1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint32_t,
+) -> svint32_t {
+    svldff1ub_gather_u32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint32_t,
+) -> svint32_t {
+    svldff1uh_gather_u32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8"
+        )]
+        fn _svldff1ub_gather_u32offset_u32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldff1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16"
+        )]
+        fn _svldff1uh_gather_u32offset_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldff1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    svldff1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    svldff1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svldff1ub_gather_u32base_offset_u32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldff1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svldff1uh_gather_u32base_offset_u32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldff1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svldff1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svldff1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svldff1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svldff1ub_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svldff1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svldff1uh_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldff1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svldff1uw_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldff1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldff1ub_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldff1uh_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldff1ub_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldff1uh_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1ub_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1uh_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldff1uw_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1ub_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1uh_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldff1uw_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")]
+        fn _svldff1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv8u8, _>(
+        _svldff1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")]
+        fn _svldff1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldff1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")]
+        fn _svldff1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldff1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")]
+        fn _svldff1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svldff1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")]
+        fn _svldff1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldff1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")]
+        fn _svldff1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldff1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t {
+    svldff1ub_s16(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t {
+    svldff1ub_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t {
+    svldff1uh_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t {
+    svldff1ub_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t {
+    svldff1uh_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t {
+    svldff1uw_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t {
+    svldff1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t {
+    svldff1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t {
+    svldff1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t {
+    svldff1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t {
+    svldff1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t {
+    svldff1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t {
+    svldff1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t {
+    svldff1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t {
+    svldff1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1b))]
+pub unsafe fn svldff1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t {
+    svldff1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t {
+    svldff1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t {
+    svldff1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s32index_s32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint32_t,
+) -> svint32_t {
+    svldff1uh_gather_s32index_u32(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s32index_u32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16"
+        )]
+        fn _svldff1uh_gather_s32index_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldff1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint64_t,
+) -> svint64_t {
+    svldff1uh_gather_s64index_u64(pg, base, indices).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint64_t,
+) -> svint64_t {
+    svldff1uw_gather_s64index_u64(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16"
+        )]
+        fn _svldff1uh_gather_s64index_u64(
+            pg: svbool2_t,
+            base: *const i16,
+            indices: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldff1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32"
+        )]
+        fn _svldff1uw_gather_s64index_u64(
+            pg: svbool2_t,
+            base: *const i32,
+            indices: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldff1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32index_s32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint32_t,
+) -> svint32_t {
+    svldff1uh_gather_u32index_u32(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32index_u32(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16"
+        )]
+        fn _svldff1uh_gather_u32index_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            indices: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldff1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldff1uh_gather_s64index_u64(pg, base, indices.as_signed())
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldff1uw_gather_s64index_u64(pg, base, indices.as_signed())
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svldff1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svldff1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldff1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldff1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 16-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1h))]
+pub unsafe fn svldff1uh_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldff1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and zero-extend, first-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldff1w))]
+pub unsafe fn svldff1uw_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldff1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4f32")]
+        fn _svldnf1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t;
+    }
+    _svldnf1_f32(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1d))]
+pub unsafe fn svldnf1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2f64")]
+        fn _svldnf1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t;
+    }
+    _svldnf1_f64(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv16i8")]
+        fn _svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t;
+    }
+    _svldnf1_s8(pg, base)
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i16")]
+        fn _svldnf1_s16(pg: svbool8_t, base: *const i16) -> svint16_t;
+    }
+    _svldnf1_s16(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i32")]
+        fn _svldnf1_s32(pg: svbool4_t, base: *const i32) -> svint32_t;
+    }
+    _svldnf1_s32(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1d))]
+pub unsafe fn svldnf1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i64")]
+        fn _svldnf1_s64(pg: svbool2_t, base: *const i64) -> svint64_t;
+    }
+    _svldnf1_s64(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
+    svldnf1_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
+    svldnf1_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
+    svldnf1_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1d))]
+pub unsafe fn svldnf1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
+    svldnf1_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t {
+    svldnf1_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1d))]
+pub unsafe fn svldnf1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t {
+    svldnf1_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t {
+    svldnf1_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t {
+    svldnf1_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t {
+    svldnf1_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1d))]
+pub unsafe fn svldnf1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t {
+    svldnf1_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t {
+    svldnf1_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t {
+    svldnf1_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t {
+    svldnf1_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1d))]
+pub unsafe fn svldnf1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t {
+    svldnf1_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")]
+        fn _svldnf1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnf1sb_s16(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")]
+        fn _svldnf1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnf1sb_s32(pg.sve_into(), base))
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")]
+        fn _svldnf1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnf1sh_s32(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")]
+        fn _svldnf1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnf1sb_s64(pg.sve_into(), base))
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")]
+        fn _svldnf1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnf1sh_s64(pg.sve_into(), base))
+}
+#[doc = "Load 32-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sw))]
+pub unsafe fn svldnf1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")]
+        fn _svldnf1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnf1sw_s64(pg.sve_into(), base))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t {
+    svldnf1sb_s16(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t {
+    svldnf1sb_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t {
+    svldnf1sh_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t {
+    svldnf1sb_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t {
+    svldnf1sh_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sw))]
+pub unsafe fn svldnf1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t {
+    svldnf1sw_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t {
+    svldnf1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t {
+    svldnf1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t {
+    svldnf1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t {
+    svldnf1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t {
+    svldnf1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sw))]
+pub unsafe fn svldnf1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t {
+    svldnf1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t {
+    svldnf1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t {
+    svldnf1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t {
+    svldnf1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sb))]
+pub unsafe fn svldnf1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t {
+    svldnf1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sh))]
+pub unsafe fn svldnf1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t {
+    svldnf1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and sign-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1sw))]
+pub unsafe fn svldnf1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t {
+    svldnf1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")]
+        fn _svldnf1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv8u8, _>(
+        _svldnf1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")]
+        fn _svldnf1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldnf1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")]
+        fn _svldnf1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldnf1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")]
+        fn _svldnf1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svldnf1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")]
+        fn _svldnf1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldnf1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")]
+        fn _svldnf1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldnf1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t {
+    svldnf1ub_s16(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t {
+    svldnf1ub_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t {
+    svldnf1uh_s32(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t {
+    svldnf1ub_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t {
+    svldnf1uh_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 32-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t {
+    svldnf1uw_s64(pg, base).as_unsigned()
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t {
+    svldnf1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t {
+    svldnf1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t {
+    svldnf1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t {
+    svldnf1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t {
+    svldnf1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t {
+    svldnf1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t {
+    svldnf1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t {
+    svldnf1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t {
+    svldnf1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Load 8-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1b))]
+pub unsafe fn svldnf1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t {
+    svldnf1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 16-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1h))]
+pub unsafe fn svldnf1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t {
+    svldnf1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Load 32-bit data and zero-extend, non-faulting"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
+#[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnf1w))]
+pub unsafe fn svldnf1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t {
+    svldnf1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4f32")]
+        fn _svldnt1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t;
+    }
+    _svldnt1_f32(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2f64")]
+        fn _svldnt1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t;
+    }
+    _svldnt1_f64(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv16i8")]
+        fn _svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t;
+    }
+    _svldnt1_s8(pg, base)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv8i16")]
+        fn _svldnt1_s16(pg: svbool8_t, base: *const i16) -> svint16_t;
+    }
+    _svldnt1_s16(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4i32")]
+        fn _svldnt1_s32(pg: svbool4_t, base: *const i32) -> svint32_t;
+    }
+    _svldnt1_s32(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2i64")]
+        fn _svldnt1_s64(pg: svbool2_t, base: *const i64) -> svint64_t;
+    }
+    _svldnt1_s64(pg.sve_into(), base)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
+    svldnt1_s8(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
+    svldnt1_s16(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
+    svldnt1_s32(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
+    svldnt1_s64(pg, base.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t {
+    svldnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t {
+    svldnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t {
+    svldnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t {
+    svldnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t {
+    svldnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t {
+    svldnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t {
+    svldnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t {
+    svldnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t {
+    svldnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t {
+    svldnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntw))]
+pub fn svlen_f32(_op: svfloat32_t) -> u64 {
+    svcntw()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntd))]
+pub fn svlen_f64(_op: svfloat64_t) -> u64 {
+    svcntd()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rdvl))]
+pub fn svlen_s8(_op: svint8_t) -> u64 {
+    svcntb()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnth))]
+pub fn svlen_s16(_op: svint16_t) -> u64 {
+    svcnth()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntw))]
+pub fn svlen_s32(_op: svint32_t) -> u64 {
+    svcntw()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntd))]
+pub fn svlen_s64(_op: svint64_t) -> u64 {
+    svcntd()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rdvl))]
+pub fn svlen_u8(_op: svuint8_t) -> u64 {
+    svcntb()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cnth))]
+pub fn svlen_u16(_op: svuint16_t) -> u64 {
+    svcnth()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntw))]
+pub fn svlen_u32(_op: svuint32_t) -> u64 {
+    svcntw()
+}
+#[doc = "Count the number of elements in a full vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cntd))]
+pub fn svlen_u64(_op: svuint64_t) -> u64 {
+    svcntd()
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv16i8")]
+        fn _svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svlsl_s8_m(pg, op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svlsl_s8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    svlsl_s8_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svlsl_s8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    svlsl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svlsl_s8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv8i16")]
+        fn _svlsl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svlsl_s16_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svlsl_s16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    svlsl_s16_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svlsl_s16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    svlsl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svlsl_s16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv4i32")]
+        fn _svlsl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svlsl_s32_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svlsl_s32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    svlsl_s32_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svlsl_s32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    svlsl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svlsl_s32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv2i64")]
+        fn _svlsl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svlsl_s64_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svlsl_s64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    svlsl_s64_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svlsl_s64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    svlsl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svlsl_s64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svlsl_s8_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svlsl_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svlsl_u8_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svlsl_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svlsl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svlsl_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svlsl_s16_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svlsl_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svlsl_u16_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svlsl_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svlsl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svlsl_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svlsl_s32_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svlsl_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svlsl_u32_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svlsl_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svlsl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svlsl_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svlsl_s64_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svlsl_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svlsl_u64_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svlsl_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svlsl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svlsl_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.lsl.wide.nxv16i8"
+        )]
+        fn _svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t;
+    }
+    unsafe { _svlsl_wide_s8_m(pg, op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
+    svlsl_wide_s8_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t {
+    svlsl_wide_s8_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
+    svlsl_wide_s8_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t {
+    svlsl_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
+    svlsl_wide_s8_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.lsl.wide.nxv8i16"
+        )]
+        fn _svlsl_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t;
+    }
+    unsafe { _svlsl_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
+    svlsl_wide_s16_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t {
+    svlsl_wide_s16_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
+    svlsl_wide_s16_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t {
+    svlsl_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
+    svlsl_wide_s16_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.lsl.wide.nxv4i32"
+        )]
+        fn _svlsl_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svlsl_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
+    svlsl_wide_s32_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t {
+    svlsl_wide_s32_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
+    svlsl_wide_s32_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t {
+    svlsl_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
+    svlsl_wide_s32_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t {
+    unsafe { svlsl_wide_s8_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
+    svlsl_wide_u8_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t {
+    svlsl_wide_u8_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
+    svlsl_wide_u8_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t {
+    svlsl_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
+    svlsl_wide_u8_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t {
+    unsafe { svlsl_wide_s16_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t {
+    svlsl_wide_u16_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t {
+    svlsl_wide_u16_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t {
+    svlsl_wide_u16_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t {
+    svlsl_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t {
+    svlsl_wide_u16_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svlsl_wide_s32_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t {
+    svlsl_wide_u32_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t {
+    svlsl_wide_u32_m(pg, op1, op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t {
+    svlsl_wide_u32_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t {
+    svlsl_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Logical shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsl))]
+pub fn svlsl_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t {
+    svlsl_wide_u32_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv16i8")]
+        fn _svlsr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svlsr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svlsr_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svlsr_u8_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svlsr_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svlsr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svlsr_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv8i16")]
+        fn _svlsr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svlsr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svlsr_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svlsr_u16_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svlsr_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svlsr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svlsr_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv4i32")]
+        fn _svlsr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svlsr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svlsr_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svlsr_u32_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svlsr_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svlsr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svlsr_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv2i64")]
+        fn _svlsr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svlsr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svlsr_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svlsr_u64_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svlsr_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svlsr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svlsr_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.lsr.wide.nxv16i8"
+        )]
+        fn _svlsr_wide_u8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t;
+    }
+    unsafe { _svlsr_wide_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
+    svlsr_wide_u8_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t {
+    svlsr_wide_u8_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
+    svlsr_wide_u8_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t {
+    svlsr_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
+    svlsr_wide_u8_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.lsr.wide.nxv8i16"
+        )]
+        fn _svlsr_wide_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t;
+    }
+    unsafe { _svlsr_wide_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t {
+    svlsr_wide_u16_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t {
+    svlsr_wide_u16_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t {
+    svlsr_wide_u16_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t {
+    svlsr_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t {
+    svlsr_wide_u16_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.lsr.wide.nxv4i32"
+        )]
+        fn _svlsr_wide_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svlsr_wide_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t {
+    svlsr_wide_u32_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t {
+    svlsr_wide_u32_m(pg, op1, op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t {
+    svlsr_wide_u32_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t {
+    svlsr_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Logical shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(lsr))]
+pub fn svlsr_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t {
+    svlsr_wide_u32_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv4f32")]
+        fn _svmad_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svmad_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmad_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmad_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmad_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmad_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv2f64")]
+        fn _svmad_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svmad_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmad_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmad_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmad_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmad))]
+pub fn svmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmad_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv16i8")]
+        fn _svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmad_s8_m(pg, op1, op2, op3) }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmad_s8_m(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmad_s8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmad_s8_x(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmad_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmad_s8_z(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv8i16")]
+        fn _svmad_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
+            -> svint16_t;
+    }
+    unsafe { _svmad_s16_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmad_s16_m(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmad_s16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmad_s16_x(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmad_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmad_s16_z(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv4i32")]
+        fn _svmad_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
+            -> svint32_t;
+    }
+    unsafe { _svmad_s32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmad_s32_m(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmad_s32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmad_s32_x(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmad_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmad_s32_z(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv2i64")]
+        fn _svmad_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
+            -> svint64_t;
+    }
+    unsafe { _svmad_s64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmad_s64_m(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmad_s64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmad_s64_x(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmad_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmad_s64_z(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svmad_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmad_u8_m(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmad_u8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmad_u8_x(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmad_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmad_u8_z(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svmad_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmad_u16_m(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmad_u16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmad_u16_x(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmad_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmad_u16_z(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svmad_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmad_u32_m(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmad_u32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmad_u32_x(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmad_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmad_u32_z(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svmad_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmad_u64_m(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmad_u64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmad_u64_x(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmad_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3)
+}
+#[doc = "Multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mad))]
+pub fn svmad_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmad_u64_z(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv4f32")]
+        fn _svmax_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmax_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmax_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmax_f32_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmax_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmax_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmax_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv2f64")]
+        fn _svmax_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmax_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmax_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmax_f64_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmax_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmax_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmax))]
+pub fn svmax_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmax_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv16i8")]
+        fn _svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmax_s8_m(pg, op1, op2) }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmax_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmax_s8_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmax_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmax_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmax_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv8i16")]
+        fn _svmax_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmax_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmax_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmax_s16_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmax_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmax_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmax_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv4i32")]
+        fn _svmax_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmax_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmax_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmax_s32_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmax_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmax_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmax_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv2i64")]
+        fn _svmax_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmax_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmax_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmax_s64_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmax_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmax_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smax))]
+pub fn svmax_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmax_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv16i8")]
+        fn _svmax_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmax_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmax_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmax_u8_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmax_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmax_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmax_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv8i16")]
+        fn _svmax_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmax_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmax_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmax_u16_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmax_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmax_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmax_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv4i32")]
+        fn _svmax_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmax_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmax_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmax_u32_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmax_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmax_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmax_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv2i64")]
+        fn _svmax_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmax_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmax_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmax_u64_m(pg, op1, op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmax_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmax_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umax))]
+pub fn svmax_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmax_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv4f32")]
+        fn _svmaxnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmaxnm_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmaxnm_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmaxnm_f32_m(pg, op1, op2)
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmaxnm_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmaxnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmaxnm_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv2f64")]
+        fn _svmaxnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmaxnm_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmaxnm_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmaxnm_f64_m(pg, op1, op2)
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmaxnm_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmaxnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Maximum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnm))]
+pub fn svmaxnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmaxnm_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Maximum number reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnmv))]
+pub fn svmaxnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmaxnmv.nxv4f32"
+        )]
+        fn _svmaxnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svmaxnmv_f32(pg.sve_into(), op) }
+}
+#[doc = "Maximum number reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnmv))]
+pub fn svmaxnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmaxnmv.nxv2f64"
+        )]
+        fn _svmaxnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svmaxnmv_f64(pg.sve_into(), op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxv))]
+pub fn svmaxv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv4f32")]
+        fn _svmaxv_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svmaxv_f32(pg.sve_into(), op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxv))]
+pub fn svmaxv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv2f64")]
+        fn _svmaxv_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svmaxv_f64(pg.sve_into(), op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxv))]
+pub fn svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv16i8")]
+        fn _svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svmaxv_s8(pg, op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxv))]
+pub fn svmaxv_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv8i16")]
+        fn _svmaxv_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svmaxv_s16(pg.sve_into(), op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxv))]
+pub fn svmaxv_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv4i32")]
+        fn _svmaxv_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svmaxv_s32(pg.sve_into(), op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxv))]
+pub fn svmaxv_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv2i64")]
+        fn _svmaxv_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svmaxv_s64(pg.sve_into(), op) }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxv))]
+pub fn svmaxv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv16i8")]
+        fn _svmaxv_u8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svmaxv_u8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxv))]
+pub fn svmaxv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv8i16")]
+        fn _svmaxv_u16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svmaxv_u16(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxv))]
+pub fn svmaxv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv4i32")]
+        fn _svmaxv_u32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svmaxv_u32(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxv))]
+pub fn svmaxv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv2i64")]
+        fn _svmaxv_u64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svmaxv_u64(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv4f32")]
+        fn _svmin_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmin_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmin_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmin_f32_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmin_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmin_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmin_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv2f64")]
+        fn _svmin_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmin_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmin_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmin_f64_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmin_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmin_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmin))]
+pub fn svmin_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmin_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv16i8")]
+        fn _svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmin_s8_m(pg, op1, op2) }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmin_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmin_s8_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmin_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmin_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmin_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv8i16")]
+        fn _svmin_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmin_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmin_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmin_s16_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmin_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmin_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmin_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv4i32")]
+        fn _svmin_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmin_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmin_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmin_s32_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmin_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmin_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmin_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv2i64")]
+        fn _svmin_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmin_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmin_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmin_s64_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmin_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmin_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smin))]
+pub fn svmin_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmin_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv16i8")]
+        fn _svmin_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmin_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmin_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmin_u8_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmin_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmin_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmin_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv8i16")]
+        fn _svmin_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmin_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmin_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmin_u16_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmin_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmin_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmin_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv4i32")]
+        fn _svmin_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmin_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmin_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmin_u32_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmin_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmin_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmin_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv2i64")]
+        fn _svmin_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmin_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmin_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmin_u64_m(pg, op1, op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmin_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmin_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umin))]
+pub fn svmin_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmin_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv4f32")]
+        fn _svminnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svminnm_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svminnm_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svminnm_f32_m(pg, op1, op2)
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svminnm_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svminnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svminnm_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv2f64")]
+        fn _svminnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svminnm_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svminnm_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svminnm_f64_m(pg, op1, op2)
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svminnm_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svminnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Minimum number"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnm))]
+pub fn svminnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svminnm_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Minimum number reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnmv))]
+pub fn svminnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fminnmv.nxv4f32"
+        )]
+        fn _svminnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svminnmv_f32(pg.sve_into(), op) }
+}
+#[doc = "Minimum number reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnmv))]
+pub fn svminnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fminnmv.nxv2f64"
+        )]
+        fn _svminnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svminnmv_f64(pg.sve_into(), op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminv))]
+pub fn svminv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv4f32")]
+        fn _svminv_f32(pg: svbool4_t, op: svfloat32_t) -> f32;
+    }
+    unsafe { _svminv_f32(pg.sve_into(), op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminv))]
+pub fn svminv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv2f64")]
+        fn _svminv_f64(pg: svbool2_t, op: svfloat64_t) -> f64;
+    }
+    unsafe { _svminv_f64(pg.sve_into(), op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminv))]
+pub fn svminv_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv16i8")]
+        fn _svminv_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svminv_s8(pg, op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminv))]
+pub fn svminv_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv8i16")]
+        fn _svminv_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svminv_s16(pg.sve_into(), op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminv))]
+pub fn svminv_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv4i32")]
+        fn _svminv_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svminv_s32(pg.sve_into(), op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminv))]
+pub fn svminv_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv2i64")]
+        fn _svminv_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svminv_s64(pg.sve_into(), op) }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminv))]
+pub fn svminv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv16i8")]
+        fn _svminv_u8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svminv_u8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminv))]
+pub fn svminv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv8i16")]
+        fn _svminv_u16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svminv_u16(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminv))]
+pub fn svminv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv4i32")]
+        fn _svminv_u32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svminv_u32(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminv))]
+pub fn svminv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv2i64")]
+        fn _svminv_u64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svminv_u64(pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv4f32")]
+        fn _svmla_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svmla_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmla_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmla_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmla_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmla_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv2f64")]
+        fn _svmla_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svmla_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmla_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmla_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmla_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla))]
+pub fn svmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmla_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv16i8")]
+        fn _svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmla_s8_m(pg, op1, op2, op3) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmla_s8_m(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmla_s8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmla_s8_x(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmla_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmla_s8_z(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv8i16")]
+        fn _svmla_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
+            -> svint16_t;
+    }
+    unsafe { _svmla_s16_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmla_s16_m(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmla_s16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmla_s16_x(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmla_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmla_s16_z(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv4i32")]
+        fn _svmla_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
+            -> svint32_t;
+    }
+    unsafe { _svmla_s32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmla_s32_m(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmla_s32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmla_s32_x(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmla_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmla_s32_z(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv2i64")]
+        fn _svmla_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
+            -> svint64_t;
+    }
+    unsafe { _svmla_s64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmla_s64_m(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmla_s64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmla_s64_x(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmla_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmla_s64_z(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svmla_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmla_u8_m(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmla_u8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmla_u8_x(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmla_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmla_u8_z(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svmla_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmla_u16_m(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmla_u16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmla_u16_x(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmla_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmla_u16_z(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svmla_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmla_u32_m(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmla_u32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmla_u32_x(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmla_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmla_u32_z(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svmla_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmla_u64_m(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmla_u64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmla_u64_x(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmla_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla))]
+pub fn svmla_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmla_u64_z(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))]
+pub fn svmla_lane_f32<const IMM_INDEX: i32>(
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmla.lane.nxv4f32"
+        )]
+        fn _svmla_lane_f32(
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+            IMM_INDEX: i32,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svmla_lane_f32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))]
+pub fn svmla_lane_f64<const IMM_INDEX: i32>(
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmla.lane.nxv2f64"
+        )]
+        fn _svmla_lane_f64(
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+            IMM_INDEX: i32,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svmla_lane_f64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv4f32")]
+        fn _svmls_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svmls_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmls_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmls_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmls_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmls_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv2f64")]
+        fn _svmls_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svmls_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmls_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmls_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmls_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls))]
+pub fn svmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmls_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv16i8")]
+        fn _svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmls_s8_m(pg, op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmls_s8_m(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmls_s8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmls_s8_x(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmls_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmls_s8_z(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv8i16")]
+        fn _svmls_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
+            -> svint16_t;
+    }
+    unsafe { _svmls_s16_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmls_s16_m(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmls_s16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmls_s16_x(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmls_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmls_s16_z(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv4i32")]
+        fn _svmls_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
+            -> svint32_t;
+    }
+    unsafe { _svmls_s32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmls_s32_m(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmls_s32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmls_s32_x(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmls_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmls_s32_z(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv2i64")]
+        fn _svmls_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
+            -> svint64_t;
+    }
+    unsafe { _svmls_s64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmls_s64_m(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmls_s64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmls_s64_x(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmls_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmls_s64_z(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svmls_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmls_u8_m(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmls_u8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmls_u8_x(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmls_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmls_u8_z(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svmls_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmls_u16_m(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmls_u16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmls_u16_x(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmls_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmls_u16_z(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svmls_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmls_u32_m(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmls_u32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmls_u32_x(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmls_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmls_u32_z(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svmls_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmls_u64_m(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmls_u64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmls_u64_x(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmls_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls))]
+pub fn svmls_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmls_u64_z(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))]
+pub fn svmls_lane_f32<const IMM_INDEX: i32>(
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmls.lane.nxv4f32"
+        )]
+        fn _svmls_lane_f32(
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+            IMM_INDEX: i32,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svmls_lane_f32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))]
+pub fn svmls_lane_f64<const IMM_INDEX: i32>(
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmls.lane.nxv2f64"
+        )]
+        fn _svmls_lane_f64(
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+            IMM_INDEX: i32,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svmls_lane_f64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Matrix multiply-accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f32mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmmla))]
+pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv4f32")]
+        fn _svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmmla_f32(op1, op2, op3) }
+}
+#[doc = "Matrix multiply-accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmmla))]
+pub fn svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv2f64")]
+        fn _svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmmla_f64(op1, op2, op3) }
+}
+#[doc = "Matrix multiply-accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smmla))]
+pub fn svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smmla.nxv4i32")]
+        fn _svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t;
+    }
+    unsafe { _svmmla_s32(op1, op2, op3) }
+}
+#[doc = "Matrix multiply-accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ummla))]
+pub fn svmmla_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ummla.nxv4i32")]
+        fn _svmmla_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t;
+    }
+    unsafe { _svmmla_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Move"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmov[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn svmov_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
+    svand_b_z(pg, op, op)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv4f32")]
+        fn _svmsb_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svmsb_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmsb_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmsb_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmsb_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svmsb_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv2f64")]
+        fn _svmsb_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svmsb_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmsb_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmsb_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmsb_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmsb))]
+pub fn svmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svmsb_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv16i8")]
+        fn _svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmsb_s8_m(pg, op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmsb_s8_m(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmsb_s8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmsb_s8_x(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    svmsb_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svmsb_s8_z(pg, op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv8i16")]
+        fn _svmsb_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
+            -> svint16_t;
+    }
+    unsafe { _svmsb_s16_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmsb_s16_m(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmsb_s16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmsb_s16_x(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    svmsb_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svmsb_s16_z(pg, op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv4i32")]
+        fn _svmsb_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
+            -> svint32_t;
+    }
+    unsafe { _svmsb_s32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmsb_s32_m(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmsb_s32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmsb_s32_x(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    svmsb_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svmsb_s32_z(pg, op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv2i64")]
+        fn _svmsb_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
+            -> svint64_t;
+    }
+    unsafe { _svmsb_s64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmsb_s64_m(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmsb_s64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmsb_s64_x(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    svmsb_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svmsb_s64_z(pg, op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svmsb_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmsb_u8_m(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmsb_u8_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmsb_u8_x(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    svmsb_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svmsb_u8_z(pg, op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svmsb_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmsb_u16_m(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmsb_u16_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmsb_u16_x(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    svmsb_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svmsb_u16_z(pg, op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svmsb_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmsb_u32_m(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmsb_u32_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmsb_u32_x(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    svmsb_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svmsb_u32_z(pg, op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svmsb_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmsb_u64_m(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmsb_u64_m(pg, op1, op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmsb_u64_x(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    svmsb_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3)
+}
+#[doc = "Multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(msb))]
+pub fn svmsb_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svmsb_u64_z(pg, op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv4f32")]
+        fn _svmul_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmul_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmul_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmul_f32_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmul_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmul_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmul_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv2f64")]
+        fn _svmul_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmul_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmul_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmul_f64_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmul_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmul_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul))]
+pub fn svmul_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmul_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv16i8")]
+        fn _svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmul_s8_m(pg, op1, op2) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmul_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmul_s8_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmul_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmul_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmul_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv8i16")]
+        fn _svmul_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmul_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmul_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmul_s16_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmul_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmul_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmul_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv4i32")]
+        fn _svmul_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmul_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmul_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmul_s32_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmul_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmul_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmul_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv2i64")]
+        fn _svmul_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmul_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmul_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmul_s64_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmul_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmul_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmul_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svmul_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmul_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmul_u8_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmul_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmul_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmul_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svmul_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmul_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmul_u16_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmul_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmul_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmul_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svmul_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmul_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmul_u32_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmul_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmul_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmul_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svmul_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmul_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmul_u64_m(pg, op1, op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmul_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmul_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul))]
+pub fn svmul_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmul_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv16i8")]
+        fn _svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmulh_s8_m(pg, op1, op2) }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmulh_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmulh_s8_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmulh_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmulh_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svmulh_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv8i16")]
+        fn _svmulh_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmulh_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmulh_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmulh_s16_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmulh_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmulh_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svmulh_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv4i32")]
+        fn _svmulh_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmulh_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmulh_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmulh_s32_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmulh_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmulh_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svmulh_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv2i64")]
+        fn _svmulh_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmulh_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmulh_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmulh_s64_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmulh_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmulh_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smulh))]
+pub fn svmulh_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svmulh_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv16i8")]
+        fn _svmulh_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmulh_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmulh_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmulh_u8_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmulh_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmulh_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svmulh_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv8i16")]
+        fn _svmulh_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmulh_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmulh_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmulh_u16_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmulh_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmulh_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svmulh_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv4i32")]
+        fn _svmulh_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmulh_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmulh_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmulh_u32_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmulh_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmulh_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svmulh_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv2i64")]
+        fn _svmulh_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmulh_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmulh_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmulh_u64_m(pg, op1, op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmulh_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmulh_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Multiply, returning high-half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umulh))]
+pub fn svmulh_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svmulh_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv4f32")]
+        fn _svmulx_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmulx_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmulx_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmulx_f32_m(pg, op1, op2)
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmulx_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmulx_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svmulx_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv2f64")]
+        fn _svmulx_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmulx_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmulx_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmulx_f64_m(pg, op1, op2)
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmulx_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmulx_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Multiply extended (∞×0=2)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmulx))]
+pub fn svmulx_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svmulx_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Bitwise NAND"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnand[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nand))]
+pub fn svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nand.z.nxv16i1")]
+        fn _svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svnand_b_z(pg, op1, op2) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fneg))]
+pub fn svneg_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv4f32")]
+        fn _svneg_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svneg_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fneg))]
+pub fn svneg_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svneg_f32_m(op, pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fneg))]
+pub fn svneg_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svneg_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fneg))]
+pub fn svneg_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv2f64")]
+        fn _svneg_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svneg_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fneg))]
+pub fn svneg_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svneg_f64_m(op, pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fneg))]
+pub fn svneg_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svneg_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv16i8")]
+        fn _svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svneg_s8_m(inactive, pg, op) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svneg_s8_m(op, pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svneg_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv8i16")]
+        fn _svneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svneg_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svneg_s16_m(op, pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svneg_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv4i32")]
+        fn _svneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svneg_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svneg_s32_m(op, pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svneg_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv2i64")]
+        fn _svneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svneg_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svneg_s64_m(op, pg, op)
+}
+#[doc = "Negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(neg))]
+pub fn svneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svneg_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv4f32")]
+        fn _svnmad_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svnmad_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmad_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmad_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmad_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmad_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv2f64")]
+        fn _svnmad_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svnmad_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmad_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmad_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmad_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-add, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmad))]
+pub fn svnmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmad_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv4f32")]
+        fn _svnmla_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svnmla_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmla_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmla_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmla_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmla_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv2f64")]
+        fn _svnmla_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svnmla_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmla_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmla_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmla_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmla))]
+pub fn svnmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmla_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv4f32")]
+        fn _svnmls_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svnmls_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmls_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmls_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmls_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmls_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv2f64")]
+        fn _svnmls_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svnmls_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmls_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmls_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmls_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmls))]
+pub fn svnmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmls_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_f32_m(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv4f32")]
+        fn _svnmsb_f32_m(
+            pg: svbool4_t,
+            op1: svfloat32_t,
+            op2: svfloat32_t,
+            op3: svfloat32_t,
+        ) -> svfloat32_t;
+    }
+    unsafe { _svnmsb_f32_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmsb_f32_m(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_f32_x(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmsb_f32_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmsb_f32_x(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_f32_z(
+    pg: svbool_t,
+    op1: svfloat32_t,
+    op2: svfloat32_t,
+    op3: svfloat32_t,
+) -> svfloat32_t {
+    svnmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t {
+    svnmsb_f32_z(pg, op1, op2, svdup_n_f32(op3))
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_f64_m(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv2f64")]
+        fn _svnmsb_f64_m(
+            pg: svbool2_t,
+            op1: svfloat64_t,
+            op2: svfloat64_t,
+            op3: svfloat64_t,
+        ) -> svfloat64_t;
+    }
+    unsafe { _svnmsb_f64_m(pg.sve_into(), op1, op2, op3) }
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmsb_f64_m(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_f64_x(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmsb_f64_m(pg, op1, op2, op3)
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmsb_f64_x(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_f64_z(
+    pg: svbool_t,
+    op1: svfloat64_t,
+    op2: svfloat64_t,
+    op3: svfloat64_t,
+) -> svfloat64_t {
+    svnmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3)
+}
+#[doc = "Negated multiply-subtract, multiplicand first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fnmsb))]
+pub fn svnmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t {
+    svnmsb_f64_z(pg, op1, op2, svdup_n_f64(op3))
+}
+#[doc = "Bitwise NOR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnor[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nor))]
+pub fn svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nor.z.nxv16i1")]
+        fn _svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svnor_b_z(pg, op1, op2) }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
+    sveor_b_z(pg, op, pg)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv16i8")]
+        fn _svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svnot_s8_m(inactive, pg, op) }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svnot_s8_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svnot_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv8i16")]
+        fn _svnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svnot_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svnot_s16_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svnot_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv4i32")]
+        fn _svnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svnot_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svnot_s32_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svnot_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv2i64")]
+        fn _svnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svnot_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svnot_s64_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svnot_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    unsafe { svnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svnot_u8_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svnot_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe { svnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svnot_u16_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svnot_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svnot_u32_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svnot_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svnot_u64_m(op, pg, op)
+}
+#[doc = "Bitwise invert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(not))]
+pub fn svnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svnot_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Bitwise inclusive OR, inverting second argument"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorn[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orn))]
+pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orn.z.nvx16i1")]
+        fn _svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svorn_b_z(pg, op1, op2) }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_b]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.z.nvx16i1")]
+        fn _svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svorr_b_z(pg, op1, op2) }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv16i8")]
+        fn _svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svorr_s8_m(pg, op1, op2) }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svorr_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svorr_s8_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svorr_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svorr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svorr_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv8i16")]
+        fn _svorr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svorr_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svorr_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svorr_s16_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svorr_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svorr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svorr_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv4i32")]
+        fn _svorr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svorr_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svorr_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svorr_s32_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svorr_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svorr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svorr_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv2i64")]
+        fn _svorr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svorr_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svorr_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svorr_s64_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svorr_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svorr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svorr_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svorr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svorr_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svorr_u8_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svorr_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svorr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svorr_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svorr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svorr_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svorr_u16_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svorr_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svorr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svorr_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svorr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svorr_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svorr_u32_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svorr_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svorr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svorr_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svorr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svorr_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svorr_u64_m(pg, op1, op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svorr_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svorr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Bitwise inclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orr))]
+pub fn svorr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svorr_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_s8(pg: svbool_t, op: svint8_t) -> i8 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv16i8")]
+        fn _svorv_s8(pg: svbool_t, op: svint8_t) -> i8;
+    }
+    unsafe { _svorv_s8(pg, op) }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_s16(pg: svbool_t, op: svint16_t) -> i16 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv8i16")]
+        fn _svorv_s16(pg: svbool8_t, op: svint16_t) -> i16;
+    }
+    unsafe { _svorv_s16(pg.sve_into(), op) }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_s32(pg: svbool_t, op: svint32_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv4i32")]
+        fn _svorv_s32(pg: svbool4_t, op: svint32_t) -> i32;
+    }
+    unsafe { _svorv_s32(pg.sve_into(), op) }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_s64(pg: svbool_t, op: svint64_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv2i64")]
+        fn _svorv_s64(pg: svbool2_t, op: svint64_t) -> i64;
+    }
+    unsafe { _svorv_s64(pg.sve_into(), op) }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
+    unsafe { svorv_s8(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
+    unsafe { svorv_s16(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
+    unsafe { svorv_s32(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise inclusive OR reduction to scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(orv))]
+pub fn svorv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
+    unsafe { svorv_s64(pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Set all predicate elements to false"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfalse[_b])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pfalse))]
+pub fn svpfalse_b() -> svbool_t {
+    svdupq_n_b8(
+        false, false, false, false, false, false, false, false, false, false, false, false, false,
+        false, false, false,
+    )
+}
+#[doc = "Set the first active predicate element to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfirst[_b])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pfirst))]
+pub fn svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pfirst.nxv16i1")]
+        fn _svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svpfirst_b(pg, op) }
+}
+#[doc = "Find next active predicate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pnext))]
+pub fn svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv16i1")]
+        fn _svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svpnext_b8(pg, op) }
+}
+#[doc = "Find next active predicate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pnext))]
+pub fn svpnext_b16(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv8i1")]
+        fn _svpnext_b16(pg: svbool8_t, op: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svpnext_b16(pg.sve_into(), op.sve_into()).sve_into() }
+}
+#[doc = "Find next active predicate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pnext))]
+pub fn svpnext_b32(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv4i1")]
+        fn _svpnext_b32(pg: svbool4_t, op: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svpnext_b32(pg.sve_into(), op.sve_into()).sve_into() }
+}
+#[doc = "Find next active predicate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pnext))]
+pub fn svpnext_b64(pg: svbool_t, op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv2i1")]
+        fn _svpnext_b64(pg: svbool2_t, op: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svpnext_b64(pg.sve_into(), op.sve_into()).sve_into() }
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfb<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv16i1")]
+        fn _svprfb(pg: svbool_t, base: *const crate::ffi::c_void, op: svprfop);
+    }
+    _svprfb(pg, base as *const crate::ffi::c_void, OP)
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfh<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv8i1")]
+        fn _svprfh(pg: svbool8_t, base: *const crate::ffi::c_void, op: svprfop);
+    }
+    _svprfh(pg.sve_into(), base as *const crate::ffi::c_void, OP)
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfw<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv4i1")]
+        fn _svprfw(pg: svbool4_t, base: *const crate::ffi::c_void, op: svprfop);
+    }
+    _svprfw(pg.sve_into(), base as *const crate::ffi::c_void, OP)
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfd<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv2i1")]
+        fn _svprfd(pg: svbool2_t, base: *const crate::ffi::c_void, op: svprfop);
+    }
+    _svprfd(pg.sve_into(), base as *const crate::ffi::c_void, OP)
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s32]offset)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfb_gather_s32offset<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    offsets: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.sxtw.index.nxv4i32"
+        )]
+        fn _svprfb_gather_s32offset(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            offsets: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfb_gather_s32offset(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        offsets,
+        OP,
+    )
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s32]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfh_gather_s32index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.sxtw.index.nxv4i32"
+        )]
+        fn _svprfh_gather_s32index(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            indices: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfh_gather_s32index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices,
+        OP,
+    )
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s32]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfw_gather_s32index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.sxtw.index.nxv4i32"
+        )]
+        fn _svprfw_gather_s32index(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            indices: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfw_gather_s32index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices,
+        OP,
+    )
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s32]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfd_gather_s32index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.sxtw.index.nxv4i32"
+        )]
+        fn _svprfd_gather_s32index(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            indices: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfd_gather_s32index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices,
+        OP,
+    )
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s64]offset)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfb_gather_s64offset<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    offsets: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.index.nxv2i64"
+        )]
+        fn _svprfb_gather_s64offset(
+            pg: svbool2_t,
+            base: *const crate::ffi::c_void,
+            offsets: svint64_t,
+            op: svprfop,
+        );
+    }
+    _svprfb_gather_s64offset(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        offsets,
+        OP,
+    )
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s64]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfh_gather_s64index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.index.nxv2i64"
+        )]
+        fn _svprfh_gather_s64index(
+            pg: svbool2_t,
+            base: *const crate::ffi::c_void,
+            indices: svint64_t,
+            op: svprfop,
+        );
+    }
+    _svprfh_gather_s64index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices,
+        OP,
+    )
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s64]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfw_gather_s64index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.index.nxv2i64"
+        )]
+        fn _svprfw_gather_s64index(
+            pg: svbool2_t,
+            base: *const crate::ffi::c_void,
+            indices: svint64_t,
+            op: svprfop,
+        );
+    }
+    _svprfw_gather_s64index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices,
+        OP,
+    )
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s64]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfd_gather_s64index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.index.nxv2i64"
+        )]
+        fn _svprfd_gather_s64index(
+            pg: svbool2_t,
+            base: *const crate::ffi::c_void,
+            indices: svint64_t,
+            op: svprfop,
+        );
+    }
+    _svprfd_gather_s64index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices,
+        OP,
+    )
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u32]offset)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfb_gather_u32offset<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    offsets: svuint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.uxtw.index.nxv4i32"
+        )]
+        fn _svprfb_gather_u32offset(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            offsets: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfb_gather_u32offset(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        offsets.as_signed(),
+        OP,
+    )
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u32]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfh_gather_u32index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svuint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.uxtw.index.nxv4i32"
+        )]
+        fn _svprfh_gather_u32index(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            indices: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfh_gather_u32index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices.as_signed(),
+        OP,
+    )
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u32]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfw_gather_u32index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svuint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.uxtw.index.nxv4i32"
+        )]
+        fn _svprfw_gather_u32index(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            indices: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfw_gather_u32index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices.as_signed(),
+        OP,
+    )
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u32]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfd_gather_u32index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svuint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.uxtw.index.nxv4i32"
+        )]
+        fn _svprfd_gather_u32index(
+            pg: svbool4_t,
+            base: *const crate::ffi::c_void,
+            indices: svint32_t,
+            op: svprfop,
+        );
+    }
+    _svprfd_gather_u32index(
+        pg.sve_into(),
+        base as *const crate::ffi::c_void,
+        indices.as_signed(),
+        OP,
+    )
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u64]offset)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfb_gather_u64offset<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    offsets: svuint64_t,
+) {
+    svprfb_gather_s64offset::<OP, T>(pg, base, offsets.as_signed())
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u64]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfh_gather_u64index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svuint64_t,
+) {
+    svprfh_gather_s64index::<OP, T>(pg, base, indices.as_signed())
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u64]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfw_gather_u64index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svuint64_t,
+) {
+    svprfw_gather_s64index::<OP, T>(pg, base, indices.as_signed())
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u64]index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfd_gather_u64index<const OP: svprfop, T>(
+    pg: svbool_t,
+    base: *const T,
+    indices: svuint64_t,
+) {
+    svprfd_gather_s64index::<OP, T>(pg, base, indices.as_signed())
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfb_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svuint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfb_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfb_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfh_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svuint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfh_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfh_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfw_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svuint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfw_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfw_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfd_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svuint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfd_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfd_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfb_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svuint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfb_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfb_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfh_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svuint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfh_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfh_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfw_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svuint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfw_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfw_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfd_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svuint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfd_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfd_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP)
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base]_offset)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfb_gather_u32base_offset<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfb_gather_u32base_offset(pg: svbool4_t, bases: svint32_t, offset: i64, op: svprfop);
+    }
+    _svprfb_gather_u32base_offset(pg.sve_into(), bases.as_signed(), offset, OP)
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base]_index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfh_gather_u32base_index<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfh_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfh_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP)
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base]_index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfw_gather_u32base_index<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfw_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfw_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP)
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base]_index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfd_gather_u32base_index<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32"
+        )]
+        fn _svprfd_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop);
+    }
+    _svprfd_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP)
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base]_offset)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfb_gather_u64base_offset<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfb_gather_u64base_offset(pg: svbool2_t, bases: svint64_t, offset: i64, op: svprfop);
+    }
+    _svprfb_gather_u64base_offset(pg.sve_into(), bases.as_signed(), offset, OP)
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base]_index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfh_gather_u64base_index<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfh_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfh_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP)
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base]_index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfw_gather_u64base_index<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfw_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfw_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP)
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base]_index)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
+pub unsafe fn svprfd_gather_u64base_index<const OP: svprfop>(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64"
+        )]
+        fn _svprfd_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop);
+    }
+    _svprfd_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP)
+}
+#[doc = "Prefetch bytes"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_vnum)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfb_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vnum: i64) {
+    svprfb::<OP, _>(pg, base.offset(svcntb() as isize * vnum as isize))
+}
+#[doc = "Prefetch halfwords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_vnum)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfh_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vnum: i64) {
+    svprfh::<OP, _>(pg, base.offset(svcnth() as isize * vnum as isize))
+}
+#[doc = "Prefetch words"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_vnum)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfw_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vnum: i64) {
+    svprfw::<OP, _>(pg, base.offset(svcntw() as isize * vnum as isize))
+}
+#[doc = "Prefetch doublewords"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_vnum)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
+pub unsafe fn svprfd_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vnum: i64) {
+    svprfd::<OP, _>(pg, base.offset(svcntd() as isize * vnum as isize))
+}
+#[doc = "Test whether any active element is true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_any)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptest))]
+pub fn svptest_any(pg: svbool_t, op: svbool_t) -> bool {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ptest.any.nxv16i1"
+        )]
+        fn _svptest_any(pg: svbool_t, op: svbool_t) -> bool;
+    }
+    unsafe { _svptest_any(pg, op) }
+}
+#[doc = "Test whether first active element is true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_first)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptest))]
+pub fn svptest_first(pg: svbool_t, op: svbool_t) -> bool {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ptest.first.nxv16i1"
+        )]
+        fn _svptest_first(pg: svbool_t, op: svbool_t) -> bool;
+    }
+    unsafe { _svptest_first(pg, op) }
+}
+#[doc = "Test whether last active element is true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_last)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptest))]
+pub fn svptest_last(pg: svbool_t, op: svbool_t) -> bool {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ptest.last.nxv16i1"
+        )]
+        fn _svptest_last(pg: svbool_t, op: svbool_t) -> bool;
+    }
+    unsafe { _svptest_last(pg, op) }
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptrue))]
+pub fn svptrue_b8() -> svbool_t {
+    svptrue_pat_b8::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptrue))]
+pub fn svptrue_b16() -> svbool_t {
+    svptrue_pat_b16::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptrue))]
+pub fn svptrue_b32() -> svbool_t {
+    svptrue_pat_b32::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ptrue))]
+pub fn svptrue_b64() -> svbool_t {
+    svptrue_pat_b64::<{ svpattern::SV_ALL }>()
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svptrue_pat_b8<const PATTERN: svpattern>() -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv16i1")]
+        fn _svptrue_pat_b8(pattern: svpattern) -> svbool_t;
+    }
+    unsafe { _svptrue_pat_b8(PATTERN) }
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svptrue_pat_b16<const PATTERN: svpattern>() -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv8i1")]
+        fn _svptrue_pat_b16(pattern: svpattern) -> svbool8_t;
+    }
+    unsafe { _svptrue_pat_b16(PATTERN).sve_into() }
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svptrue_pat_b32<const PATTERN: svpattern>() -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv4i1")]
+        fn _svptrue_pat_b32(pattern: svpattern) -> svbool4_t;
+    }
+    unsafe { _svptrue_pat_b32(PATTERN).sve_into() }
+}
+#[doc = "Set predicate elements to true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
+pub fn svptrue_pat_b64<const PATTERN: svpattern>() -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv2i1")]
+        fn _svptrue_pat_b64(pattern: svpattern) -> svbool2_t;
+    }
+    unsafe { _svptrue_pat_b64(PATTERN).sve_into() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqadd.x.nxv16i8"
+        )]
+        fn _svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqadd_s8(op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
+    svqadd_s8(op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqadd.x.nxv8i16"
+        )]
+        fn _svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqadd_s16(op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
+    svqadd_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqadd.x.nxv4i32"
+        )]
+        fn _svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqadd_s32(op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
+    svqadd_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqadd.x.nxv2i64"
+        )]
+        fn _svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqadd_s64(op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
+    svqadd_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqadd.x.nxv16i8"
+        )]
+        fn _svqadd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqadd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqadd_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqadd.x.nxv8i16"
+        )]
+        fn _svqadd_u16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqadd_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqadd_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqadd.x.nxv4i32"
+        )]
+        fn _svqadd_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqadd_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqadd_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqadd.x.nxv2i64"
+        )]
+        fn _svqadd_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqadd_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqadd_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))]
+pub fn svqdecb_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqdecb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))]
+pub fn svqdech_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqdech_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))]
+pub fn svqdecw_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqdecw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))]
+pub fn svqdecd_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqdecd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))]
+pub fn svqdecb_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqdecb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))]
+pub fn svqdech_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqdech_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))]
+pub fn svqdecw_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqdecw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))]
+pub fn svqdecd_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqdecd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))]
+pub fn svqdecb_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqdecb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))]
+pub fn svqdech_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqdech_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))]
+pub fn svqdecw_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqdecw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))]
+pub fn svqdecd_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqdecd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))]
+pub fn svqdecb_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqdecb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))]
+pub fn svqdech_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqdech_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))]
+pub fn svqdecw_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqdecw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))]
+pub fn svqdecd_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqdecd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecb_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n32")]
+        fn _svqdecb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdecb_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdech_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n32")]
+        fn _svqdech_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdech_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecw_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n32")]
+        fn _svqdecw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdecw_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecd_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n32")]
+        fn _svqdecd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdecd_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecb_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n64")]
+        fn _svqdecb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdecb_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdech_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n64")]
+        fn _svqdech_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdech_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecw_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n64")]
+        fn _svqdecw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdecw_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecd_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n64")]
+        fn _svqdecd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdecd_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecb_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n32")]
+        fn _svqdecb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdecb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdech_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n32")]
+        fn _svqdech_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdech_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecw_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n32")]
+        fn _svqdecw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdecw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecd_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n32")]
+        fn _svqdecd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqdecd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecb_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n64")]
+        fn _svqdecb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdecb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdech_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n64")]
+        fn _svqdech_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdech_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecw_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n64")]
+        fn _svqdecw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdecw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecd_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n64")]
+        fn _svqdecd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqdecd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdech_pat_s16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.nxv8i16")]
+        fn _svqdech_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t;
+    }
+    unsafe { _svqdech_pat_s16(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecw_pat_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.nxv4i32")]
+        fn _svqdecw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t;
+    }
+    unsafe { _svqdecw_pat_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecd_pat_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svint64_t,
+) -> svint64_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.nxv2i64")]
+        fn _svqdecd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t;
+    }
+    unsafe { _svqdecd_pat_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdech_pat_u16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svuint16_t,
+) -> svuint16_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.nxv8i16")]
+        fn _svqdech_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t;
+    }
+    unsafe { _svqdech_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecw_pat_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svuint32_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.nxv4i32")]
+        fn _svqdecw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t;
+    }
+    unsafe { _svqdecw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqdecd_pat_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svuint64_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.nxv2i64")]
+        fn _svqdecd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t;
+    }
+    unsafe { _svqdecd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))]
+pub fn svqdech_s16<const IMM_FACTOR: i32>(op: svint16_t) -> svint16_t {
+    svqdech_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))]
+pub fn svqdecw_s32<const IMM_FACTOR: i32>(op: svint32_t) -> svint32_t {
+    svqdecw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))]
+pub fn svqdecd_s64<const IMM_FACTOR: i32>(op: svint64_t) -> svint64_t {
+    svqdecd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))]
+pub fn svqdech_u16<const IMM_FACTOR: i32>(op: svuint16_t) -> svuint16_t {
+    svqdech_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))]
+pub fn svqdecw_u32<const IMM_FACTOR: i32>(op: svuint32_t) -> svuint32_t {
+    svqdecw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))]
+pub fn svqdecd_u64<const IMM_FACTOR: i32>(op: svuint64_t) -> svuint64_t {
+    svqdecd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n32.nxv16i1"
+        )]
+        fn _svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32;
+    }
+    unsafe { _svqdecp_n_s32_b8(op, pg) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s32_b16(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n32.nxv8i1"
+        )]
+        fn _svqdecp_n_s32_b16(op: i32, pg: svbool8_t) -> i32;
+    }
+    unsafe { _svqdecp_n_s32_b16(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s32_b32(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n32.nxv4i1"
+        )]
+        fn _svqdecp_n_s32_b32(op: i32, pg: svbool4_t) -> i32;
+    }
+    unsafe { _svqdecp_n_s32_b32(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s32_b64(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n32.nxv2i1"
+        )]
+        fn _svqdecp_n_s32_b64(op: i32, pg: svbool2_t) -> i32;
+    }
+    unsafe { _svqdecp_n_s32_b64(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n64.nxv16i1"
+        )]
+        fn _svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64;
+    }
+    unsafe { _svqdecp_n_s64_b8(op, pg) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s64_b16(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n64.nxv8i1"
+        )]
+        fn _svqdecp_n_s64_b16(op: i64, pg: svbool8_t) -> i64;
+    }
+    unsafe { _svqdecp_n_s64_b16(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s64_b32(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n64.nxv4i1"
+        )]
+        fn _svqdecp_n_s64_b32(op: i64, pg: svbool4_t) -> i64;
+    }
+    unsafe { _svqdecp_n_s64_b32(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_n_s64_b64(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdecp.n64.nxv2i1"
+        )]
+        fn _svqdecp_n_s64_b64(op: i64, pg: svbool2_t) -> i64;
+    }
+    unsafe { _svqdecp_n_s64_b64(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u32_b8(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n32.nxv16i1"
+        )]
+        fn _svqdecp_n_u32_b8(op: i32, pg: svbool_t) -> i32;
+    }
+    unsafe { _svqdecp_n_u32_b8(op.as_signed(), pg).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u32_b16(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n32.nxv8i1"
+        )]
+        fn _svqdecp_n_u32_b16(op: i32, pg: svbool8_t) -> i32;
+    }
+    unsafe { _svqdecp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u32_b32(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n32.nxv4i1"
+        )]
+        fn _svqdecp_n_u32_b32(op: i32, pg: svbool4_t) -> i32;
+    }
+    unsafe { _svqdecp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u32_b64(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n32.nxv2i1"
+        )]
+        fn _svqdecp_n_u32_b64(op: i32, pg: svbool2_t) -> i32;
+    }
+    unsafe { _svqdecp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u64_b8(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n64.nxv16i1"
+        )]
+        fn _svqdecp_n_u64_b8(op: i64, pg: svbool_t) -> i64;
+    }
+    unsafe { _svqdecp_n_u64_b8(op.as_signed(), pg).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u64_b16(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n64.nxv8i1"
+        )]
+        fn _svqdecp_n_u64_b16(op: i64, pg: svbool8_t) -> i64;
+    }
+    unsafe { _svqdecp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u64_b32(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n64.nxv4i1"
+        )]
+        fn _svqdecp_n_u64_b32(op: i64, pg: svbool4_t) -> i64;
+    }
+    unsafe { _svqdecp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_n_u64_b64(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqdecp.n64.nxv2i1"
+        )]
+        fn _svqdecp_n_u64_b64(op: i64, pg: svbool2_t) -> i64;
+    }
+    unsafe { _svqdecp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_s16(op: svint16_t, pg: svbool_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv8i16")]
+        fn _svqdecp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t;
+    }
+    unsafe { _svqdecp_s16(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_s32(op: svint32_t, pg: svbool_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv4i32")]
+        fn _svqdecp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t;
+    }
+    unsafe { _svqdecp_s32(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdecp))]
+pub fn svqdecp_s64(op: svint64_t, pg: svbool_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv2i64")]
+        fn _svqdecp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t;
+    }
+    unsafe { _svqdecp_s64(op, pg.sve_into()) }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv8i16")]
+        fn _svqdecp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t;
+    }
+    unsafe { _svqdecp_u16(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv4i32")]
+        fn _svqdecp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t;
+    }
+    unsafe { _svqdecp_u32(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating decrement by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqdecp))]
+pub fn svqdecp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv2i64")]
+        fn _svqdecp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t;
+    }
+    unsafe { _svqdecp_u64(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))]
+pub fn svqincb_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqincb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))]
+pub fn svqinch_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqinch_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))]
+pub fn svqincw_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqincw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))]
+pub fn svqincd_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
+    svqincd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))]
+pub fn svqincb_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqincb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))]
+pub fn svqinch_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqinch_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))]
+pub fn svqincw_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqincw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))]
+pub fn svqincd_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
+    svqincd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))]
+pub fn svqincb_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqincb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))]
+pub fn svqinch_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqinch_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))]
+pub fn svqincw_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqincw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))]
+pub fn svqincd_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
+    svqincd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))]
+pub fn svqincb_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqincb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))]
+pub fn svqinch_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqinch_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))]
+pub fn svqincw_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqincw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))]
+pub fn svqincd_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
+    svqincd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincb_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n32")]
+        fn _svqincb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqincb_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqinch_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n32")]
+        fn _svqinch_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqinch_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincw_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n32")]
+        fn _svqincw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqincw_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincd_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i32) -> i32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n32")]
+        fn _svqincd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqincd_pat_n_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincb_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n64")]
+        fn _svqincb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqincb_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqinch_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n64")]
+        fn _svqinch_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqinch_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincw_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n64")]
+        fn _svqincw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqincw_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincd_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i64) -> i64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n64")]
+        fn _svqincd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqincd_pat_n_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincb_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n32")]
+        fn _svqincb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqincb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqinch_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n32")]
+        fn _svqinch_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqinch_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincw_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n32")]
+        fn _svqincw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqincw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincd_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u32) -> u32 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n32")]
+        fn _svqincd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32;
+    }
+    unsafe { _svqincd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of byte elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincb_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n64")]
+        fn _svqincb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqincb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqinch_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n64")]
+        fn _svqinch_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqinch_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincw_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n64")]
+        fn _svqincw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqincw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincd_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u64) -> u64 {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n64")]
+        fn _svqincd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64;
+    }
+    unsafe { _svqincd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqinch_pat_s16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.nxv8i16")]
+        fn _svqinch_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t;
+    }
+    unsafe { _svqinch_pat_s16(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincw_pat_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.nxv4i32")]
+        fn _svqincw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t;
+    }
+    unsafe { _svqincw_pat_s32(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincd_pat_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svint64_t,
+) -> svint64_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.nxv2i64")]
+        fn _svqincd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t;
+    }
+    unsafe { _svqincd_pat_s64(op, PATTERN, IMM_FACTOR) }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqinch_pat_u16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svuint16_t,
+) -> svuint16_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.nxv8i16")]
+        fn _svqinch_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t;
+    }
+    unsafe { _svqinch_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincw_pat_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svuint32_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.nxv4i32")]
+        fn _svqincw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t;
+    }
+    unsafe { _svqincw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
+pub fn svqincd_pat_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
+    op: svuint64_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_FACTOR, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.nxv2i64")]
+        fn _svqincd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t;
+    }
+    unsafe { _svqincd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() }
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))]
+pub fn svqinch_s16<const IMM_FACTOR: i32>(op: svint16_t) -> svint16_t {
+    svqinch_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))]
+pub fn svqincw_s32<const IMM_FACTOR: i32>(op: svint32_t) -> svint32_t {
+    svqincw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))]
+pub fn svqincd_s64<const IMM_FACTOR: i32>(op: svint64_t) -> svint64_t {
+    svqincd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of halfword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))]
+pub fn svqinch_u16<const IMM_FACTOR: i32>(op: svuint16_t) -> svuint16_t {
+    svqinch_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of word elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))]
+pub fn svqincw_u32<const IMM_FACTOR: i32>(op: svuint32_t) -> svuint32_t {
+    svqincw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by number of doubleword elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))]
+pub fn svqincd_u64<const IMM_FACTOR: i32>(op: svuint64_t) -> svuint64_t {
+    svqincd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op)
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n32.nxv16i1"
+        )]
+        fn _svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32;
+    }
+    unsafe { _svqincp_n_s32_b8(op, pg) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s32_b16(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n32.nxv8i1"
+        )]
+        fn _svqincp_n_s32_b16(op: i32, pg: svbool8_t) -> i32;
+    }
+    unsafe { _svqincp_n_s32_b16(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s32_b32(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n32.nxv4i1"
+        )]
+        fn _svqincp_n_s32_b32(op: i32, pg: svbool4_t) -> i32;
+    }
+    unsafe { _svqincp_n_s32_b32(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s32_b64(op: i32, pg: svbool_t) -> i32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n32.nxv2i1"
+        )]
+        fn _svqincp_n_s32_b64(op: i32, pg: svbool2_t) -> i32;
+    }
+    unsafe { _svqincp_n_s32_b64(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n64.nxv16i1"
+        )]
+        fn _svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64;
+    }
+    unsafe { _svqincp_n_s64_b8(op, pg) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s64_b16(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n64.nxv8i1"
+        )]
+        fn _svqincp_n_s64_b16(op: i64, pg: svbool8_t) -> i64;
+    }
+    unsafe { _svqincp_n_s64_b16(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s64_b32(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n64.nxv4i1"
+        )]
+        fn _svqincp_n_s64_b32(op: i64, pg: svbool4_t) -> i64;
+    }
+    unsafe { _svqincp_n_s64_b32(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_n_s64_b64(op: i64, pg: svbool_t) -> i64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqincp.n64.nxv2i1"
+        )]
+        fn _svqincp_n_s64_b64(op: i64, pg: svbool2_t) -> i64;
+    }
+    unsafe { _svqincp_n_s64_b64(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u32_b8(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n32.nxv16i1"
+        )]
+        fn _svqincp_n_u32_b8(op: i32, pg: svbool_t) -> i32;
+    }
+    unsafe { _svqincp_n_u32_b8(op.as_signed(), pg).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u32_b16(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n32.nxv8i1"
+        )]
+        fn _svqincp_n_u32_b16(op: i32, pg: svbool8_t) -> i32;
+    }
+    unsafe { _svqincp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u32_b32(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n32.nxv4i1"
+        )]
+        fn _svqincp_n_u32_b32(op: i32, pg: svbool4_t) -> i32;
+    }
+    unsafe { _svqincp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u32_b64(op: u32, pg: svbool_t) -> u32 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n32.nxv2i1"
+        )]
+        fn _svqincp_n_u32_b64(op: i32, pg: svbool2_t) -> i32;
+    }
+    unsafe { _svqincp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u64_b8(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n64.nxv16i1"
+        )]
+        fn _svqincp_n_u64_b8(op: i64, pg: svbool_t) -> i64;
+    }
+    unsafe { _svqincp_n_u64_b8(op.as_signed(), pg).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u64_b16(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n64.nxv8i1"
+        )]
+        fn _svqincp_n_u64_b16(op: i64, pg: svbool8_t) -> i64;
+    }
+    unsafe { _svqincp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u64_b32(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n64.nxv4i1"
+        )]
+        fn _svqincp_n_u64_b32(op: i64, pg: svbool4_t) -> i64;
+    }
+    unsafe { _svqincp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_n_u64_b64(op: u64, pg: svbool_t) -> u64 {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqincp.n64.nxv2i1"
+        )]
+        fn _svqincp_n_u64_b64(op: i64, pg: svbool2_t) -> i64;
+    }
+    unsafe { _svqincp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_s16(op: svint16_t, pg: svbool_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv8i16")]
+        fn _svqincp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t;
+    }
+    unsafe { _svqincp_s16(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_s32(op: svint32_t, pg: svbool_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv4i32")]
+        fn _svqincp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t;
+    }
+    unsafe { _svqincp_s32(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqincp))]
+pub fn svqincp_s64(op: svint64_t, pg: svbool_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv2i64")]
+        fn _svqincp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t;
+    }
+    unsafe { _svqincp_s64(op, pg.sve_into()) }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv8i16")]
+        fn _svqincp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t;
+    }
+    unsafe { _svqincp_u16(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv4i32")]
+        fn _svqincp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t;
+    }
+    unsafe { _svqincp_u32(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating increment by active element count"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqincp))]
+pub fn svqincp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv2i64")]
+        fn _svqincp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t;
+    }
+    unsafe { _svqincp_u64(op.as_signed(), pg.sve_into()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqsub.x.nxv16i8"
+        )]
+        fn _svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqsub_s8(op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
+    svqsub_s8(op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqsub.x.nxv8i16"
+        )]
+        fn _svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqsub_s16(op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
+    svqsub_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqsub.x.nxv4i32"
+        )]
+        fn _svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqsub_s32(op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
+    svqsub_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqsub.x.nxv2i64"
+        )]
+        fn _svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqsub_s64(op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
+    svqsub_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqsub.x.nxv16i8"
+        )]
+        fn _svqsub_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqsub_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsub_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqsub.x.nxv8i16"
+        )]
+        fn _svqsub_u16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqsub_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsub_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqsub.x.nxv4i32"
+        )]
+        fn _svqsub_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqsub_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsub_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqsub.x.nxv2i64"
+        )]
+        fn _svqsub_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqsub_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsub_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv16i8")]
+        fn _svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svrbit_s8_m(inactive, pg, op) }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svrbit_s8_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svrbit_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv8i16")]
+        fn _svrbit_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrbit_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svrbit_s16_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svrbit_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv4i32")]
+        fn _svrbit_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrbit_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svrbit_s32_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svrbit_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv2i64")]
+        fn _svrbit_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrbit_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrbit_s64_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrbit_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    unsafe { svrbit_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svrbit_u8_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
+    svrbit_u8_m(svdup_n_u8(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe { svrbit_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svrbit_u16_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svrbit_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svrbit_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrbit_u32_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrbit_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svrbit_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrbit_u64_m(op, pg, op)
+}
+#[doc = "Reverse bits"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rbit))]
+pub fn svrbit_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrbit_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Read FFR, returning predicate of succesfully loaded elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rdffr))]
+pub fn svrdffr() -> svbool_t {
+    svrdffr_z(svptrue_b8())
+}
+#[doc = "Read FFR, returning predicate of succesfully loaded elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rdffr))]
+pub fn svrdffr_z(pg: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rdffr.z")]
+        fn _svrdffr_z(pg: svbool_t) -> svbool_t;
+    }
+    unsafe { _svrdffr_z(pg) }
+}
+#[doc = "Reciprocal estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpe))]
+pub fn svrecpe_f32(op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frecpe.x.nxv4f32"
+        )]
+        fn _svrecpe_f32(op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrecpe_f32(op) }
+}
+#[doc = "Reciprocal estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpe))]
+pub fn svrecpe_f64(op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frecpe.x.nxv2f64"
+        )]
+        fn _svrecpe_f64(op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrecpe_f64(op) }
+}
+#[doc = "Reciprocal step"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecps))]
+pub fn svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frecps.x.nxv4f32"
+        )]
+        fn _svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrecps_f32(op1, op2) }
+}
+#[doc = "Reciprocal step"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecps))]
+pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frecps.x.nxv2f64"
+        )]
+        fn _svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrecps_f64(op1, op2) }
+}
+#[doc = "Reciprocal exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpx))]
+pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frecpx.x.nxv4f32"
+        )]
+        fn _svrecpx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrecpx_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reciprocal exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpx))]
+pub fn svrecpx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrecpx_f32_m(op, pg, op)
+}
+#[doc = "Reciprocal exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpx))]
+pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrecpx_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Reciprocal exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpx))]
+pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frecpx.x.nxv2f64"
+        )]
+        fn _svrecpx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrecpx_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reciprocal exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpx))]
+pub fn svrecpx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrecpx_f64_m(op, pg, op)
+}
+#[doc = "Reciprocal exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frecpx))]
+pub fn svrecpx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrecpx_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_f32(op: svfloat32_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_f64(op: svfloat64_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_s8(op: svint8_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_s16(op: svint16_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_s32(op: svint32_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_s64(op: svint64_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_u8(op: svuint8_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_u16(op: svuint16_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_u32(op: svuint32_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f32_u64(op: svuint64_t) -> svfloat32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_f32(op: svfloat32_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_f64(op: svfloat64_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_s8(op: svint8_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_s16(op: svint16_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_s32(op: svint32_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_s64(op: svint64_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_u8(op: svuint8_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_u16(op: svuint16_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_u32(op: svuint32_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_f64_u64(op: svuint64_t) -> svfloat64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_f32(op: svfloat32_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_f64(op: svfloat64_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_s8(op: svint8_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_s16(op: svint16_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_s32(op: svint32_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_s64(op: svint64_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_u8(op: svuint8_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_u16(op: svuint16_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_u32(op: svuint32_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s8_u64(op: svuint64_t) -> svint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_f32(op: svfloat32_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_f64(op: svfloat64_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_s8(op: svint8_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_s16(op: svint16_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_s32(op: svint32_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_s64(op: svint64_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_u8(op: svuint8_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_u16(op: svuint16_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_u32(op: svuint32_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s16_u64(op: svuint64_t) -> svint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_f32(op: svfloat32_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_f64(op: svfloat64_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_s8(op: svint8_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_s16(op: svint16_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_s32(op: svint32_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_s64(op: svint64_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_u8(op: svuint8_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_u16(op: svuint16_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_u32(op: svuint32_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s32_u64(op: svuint64_t) -> svint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_f32(op: svfloat32_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_f64(op: svfloat64_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_s8(op: svint8_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_s16(op: svint16_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_s32(op: svint32_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_s64(op: svint64_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_u8(op: svuint8_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_u16(op: svuint16_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_u32(op: svuint32_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_s64_u64(op: svuint64_t) -> svint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_f32(op: svfloat32_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_f64(op: svfloat64_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_s8(op: svint8_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_s16(op: svint16_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_s32(op: svint32_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_s64(op: svint64_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_u8(op: svuint8_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_u16(op: svuint16_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_u32(op: svuint32_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u8_u64(op: svuint64_t) -> svuint8_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_f32(op: svfloat32_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_f64(op: svfloat64_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_s8(op: svint8_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_s16(op: svint16_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_s32(op: svint32_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_s64(op: svint64_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_u8(op: svuint8_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_u16(op: svuint16_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_u32(op: svuint32_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u16_u64(op: svuint64_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_f32(op: svfloat32_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_f64(op: svfloat64_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_s8(op: svint8_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_s16(op: svint16_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_s32(op: svint32_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_s64(op: svint64_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_u8(op: svuint8_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_u16(op: svuint16_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_u32(op: svuint32_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u32_u64(op: svuint64_t) -> svuint32_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_f32(op: svfloat32_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_f64(op: svfloat64_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_s8(op: svint8_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_s16(op: svint16_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_s32(op: svint32_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_s64(op: svint64_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_u8(op: svuint8_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_u16(op: svuint16_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_u32(op: svuint32_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reinterpret vector contents"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_b8(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv16i1")]
+        fn _svrev_b8(op: svbool_t) -> svbool_t;
+    }
+    unsafe { _svrev_b8(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_b16(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv8i1")]
+        fn _svrev_b16(op: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svrev_b16(op.sve_into()).sve_into() }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_b32(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4i1")]
+        fn _svrev_b32(op: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svrev_b32(op.sve_into()).sve_into() }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_b64(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2i1")]
+        fn _svrev_b64(op: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svrev_b64(op.sve_into()).sve_into() }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4f32")]
+        fn _svrev_f32(op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrev_f32(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2f64")]
+        fn _svrev_f64(op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrev_f64(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_s8(op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv16i8")]
+        fn _svrev_s8(op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svrev_s8(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_s16(op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv8i16")]
+        fn _svrev_s16(op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrev_s16(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_s32(op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4i32")]
+        fn _svrev_s32(op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrev_s32(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_s64(op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2i64")]
+        fn _svrev_s64(op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrev_s64(op) }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_u8(op: svuint8_t) -> svuint8_t {
+    unsafe { svrev_s8(op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_u16(op: svuint16_t) -> svuint16_t {
+    unsafe { svrev_s16(op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_u32(op: svuint32_t) -> svuint32_t {
+    unsafe { svrev_s32(op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse all elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rev))]
+pub fn svrev_u64(op: svuint64_t) -> svuint64_t {
+    unsafe { svrev_s64(op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv8i16")]
+        fn _svrevb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrevb_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svrevb_s16_m(op, pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svrevb_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv4i32")]
+        fn _svrevb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrevb_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svrevb_s32_m(op, pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svrevb_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv2i64")]
+        fn _svrevb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrevb_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrevb_s64_m(op, pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrevb_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    unsafe { svrevb_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svrevb_u16_m(op, pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
+    svrevb_u16_m(svdup_n_u16(0), pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svrevb_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrevb_u32_m(op, pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrevb_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svrevb_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrevb_u64_m(op, pg, op)
+}
+#[doc = "Reverse bytes within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revb))]
+pub fn svrevb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrevb_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv4i32")]
+        fn _svrevh_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrevh_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svrevh_s32_m(op, pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svrevh_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv2i64")]
+        fn _svrevh_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrevh_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrevh_s64_m(op, pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrevh_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe { svrevh_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrevh_u32_m(op, pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrevh_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svrevh_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrevh_u64_m(op, pg, op)
+}
+#[doc = "Reverse halfwords within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revh))]
+pub fn svrevh_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrevh_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Reverse words within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revw))]
+pub fn svrevw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revw.nxv2i64")]
+        fn _svrevw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrevw_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Reverse words within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revw))]
+pub fn svrevw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrevw_s64_m(op, pg, op)
+}
+#[doc = "Reverse words within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revw))]
+pub fn svrevw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svrevw_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Reverse words within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revw))]
+pub fn svrevw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    unsafe { svrevw_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() }
+}
+#[doc = "Reverse words within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revw))]
+pub fn svrevw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrevw_u64_m(op, pg, op)
+}
+#[doc = "Reverse words within elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(revw))]
+pub fn svrevw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
+    svrevw_u64_m(svdup_n_u64(0), pg, op)
+}
+#[doc = "Round to nearest, ties away from zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinta))]
+pub fn svrinta_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv4f32")]
+        fn _svrinta_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrinta_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round to nearest, ties away from zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinta))]
+pub fn svrinta_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrinta_f32_m(op, pg, op)
+}
+#[doc = "Round to nearest, ties away from zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinta))]
+pub fn svrinta_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrinta_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round to nearest, ties away from zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinta))]
+pub fn svrinta_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv2f64")]
+        fn _svrinta_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrinta_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round to nearest, ties away from zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinta))]
+pub fn svrinta_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrinta_f64_m(op, pg, op)
+}
+#[doc = "Round to nearest, ties away from zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinta))]
+pub fn svrinta_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrinta_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Round using current rounding mode (inexact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinti))]
+pub fn svrinti_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv4f32")]
+        fn _svrinti_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrinti_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round using current rounding mode (inexact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinti))]
+pub fn svrinti_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrinti_f32_m(op, pg, op)
+}
+#[doc = "Round using current rounding mode (inexact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinti))]
+pub fn svrinti_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrinti_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round using current rounding mode (inexact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinti))]
+pub fn svrinti_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv2f64")]
+        fn _svrinti_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrinti_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round using current rounding mode (inexact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinti))]
+pub fn svrinti_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrinti_f64_m(op, pg, op)
+}
+#[doc = "Round using current rounding mode (inexact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frinti))]
+pub fn svrinti_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrinti_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Round towards -∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintm))]
+pub fn svrintm_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv4f32")]
+        fn _svrintm_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrintm_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round towards -∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintm))]
+pub fn svrintm_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintm_f32_m(op, pg, op)
+}
+#[doc = "Round towards -∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintm))]
+pub fn svrintm_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintm_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round towards -∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintm))]
+pub fn svrintm_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv2f64")]
+        fn _svrintm_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrintm_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round towards -∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintm))]
+pub fn svrintm_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintm_f64_m(op, pg, op)
+}
+#[doc = "Round towards -∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintm))]
+pub fn svrintm_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintm_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Round to nearest, ties to even"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintn))]
+pub fn svrintn_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv4f32")]
+        fn _svrintn_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrintn_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round to nearest, ties to even"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintn))]
+pub fn svrintn_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintn_f32_m(op, pg, op)
+}
+#[doc = "Round to nearest, ties to even"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintn))]
+pub fn svrintn_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintn_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round to nearest, ties to even"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintn))]
+pub fn svrintn_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv2f64")]
+        fn _svrintn_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrintn_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round to nearest, ties to even"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintn))]
+pub fn svrintn_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintn_f64_m(op, pg, op)
+}
+#[doc = "Round to nearest, ties to even"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintn))]
+pub fn svrintn_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintn_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Round towards +∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintp))]
+pub fn svrintp_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv4f32")]
+        fn _svrintp_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrintp_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round towards +∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintp))]
+pub fn svrintp_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintp_f32_m(op, pg, op)
+}
+#[doc = "Round towards +∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintp))]
+pub fn svrintp_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintp_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round towards +∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintp))]
+pub fn svrintp_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv2f64")]
+        fn _svrintp_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrintp_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round towards +∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintp))]
+pub fn svrintp_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintp_f64_m(op, pg, op)
+}
+#[doc = "Round towards +∞"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintp))]
+pub fn svrintp_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintp_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Round using current rounding mode (exact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintx))]
+pub fn svrintx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv4f32")]
+        fn _svrintx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrintx_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round using current rounding mode (exact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintx))]
+pub fn svrintx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintx_f32_m(op, pg, op)
+}
+#[doc = "Round using current rounding mode (exact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintx))]
+pub fn svrintx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintx_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round using current rounding mode (exact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintx))]
+pub fn svrintx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv2f64")]
+        fn _svrintx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrintx_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round using current rounding mode (exact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintx))]
+pub fn svrintx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintx_f64_m(op, pg, op)
+}
+#[doc = "Round using current rounding mode (exact)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintx))]
+pub fn svrintx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintx_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Round towards zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintz))]
+pub fn svrintz_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv4f32")]
+        fn _svrintz_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrintz_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round towards zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintz))]
+pub fn svrintz_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintz_f32_m(op, pg, op)
+}
+#[doc = "Round towards zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintz))]
+pub fn svrintz_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svrintz_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Round towards zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintz))]
+pub fn svrintz_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv2f64")]
+        fn _svrintz_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrintz_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Round towards zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintz))]
+pub fn svrintz_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintz_f64_m(op, pg, op)
+}
+#[doc = "Round towards zero"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frintz))]
+pub fn svrintz_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svrintz_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Reciprocal square root estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frsqrte))]
+pub fn svrsqrte_f32(op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frsqrte.x.nxv4f32"
+        )]
+        fn _svrsqrte_f32(op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrsqrte_f32(op) }
+}
+#[doc = "Reciprocal square root estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frsqrte))]
+pub fn svrsqrte_f64(op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frsqrte.x.nxv2f64"
+        )]
+        fn _svrsqrte_f64(op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrsqrte_f64(op) }
+}
+#[doc = "Reciprocal square root step"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frsqrts))]
+pub fn svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frsqrts.x.nxv4f32"
+        )]
+        fn _svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svrsqrts_f32(op1, op2) }
+}
+#[doc = "Reciprocal square root step"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(frsqrts))]
+pub fn svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.frsqrts.x.nxv2f64"
+        )]
+        fn _svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svrsqrts_f64(op1, op2) }
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv4f32")]
+        fn _svscale_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svscale_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t {
+    svscale_f32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t {
+    svscale_f32_m(pg, op1, op2)
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t {
+    svscale_f32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t {
+    svscale_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t {
+    svscale_f32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv2f64")]
+        fn _svscale_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svscale_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t {
+    svscale_f64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t {
+    svscale_f64_m(pg, op1, op2)
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t {
+    svscale_f64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t {
+    svscale_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn svscale_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t {
+    svscale_f64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_b])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_b(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe { simd_select(pg, op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe { simd_select::<svbool4_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe { simd_select::<svbool2_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe { simd_select::<svbool_t, _>(pg, op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe { simd_select::<svbool8_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe { simd_select::<svbool4_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe { simd_select::<svbool2_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { simd_select::<svbool_t, _>(pg, op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { simd_select::<svbool8_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { simd_select::<svbool4_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Conditionally select elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sel))]
+pub fn svsel_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { simd_select::<svbool2_t, _>(pg.sve_into(), op1, op2) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_f32<const IMM_INDEX: i32>(tuple: svfloat32x2_t, x: svfloat32_t) -> svfloat32x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_f64<const IMM_INDEX: i32>(tuple: svfloat64x2_t, x: svfloat64_t) -> svfloat64x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_s8<const IMM_INDEX: i32>(tuple: svint8x2_t, x: svint8_t) -> svint8x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_s16<const IMM_INDEX: i32>(tuple: svint16x2_t, x: svint16_t) -> svint16x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_s32<const IMM_INDEX: i32>(tuple: svint32x2_t, x: svint32_t) -> svint32x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_s64<const IMM_INDEX: i32>(tuple: svint64x2_t, x: svint64_t) -> svint64x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_u8<const IMM_INDEX: i32>(tuple: svuint8x2_t, x: svuint8_t) -> svuint8x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_u16<const IMM_INDEX: i32>(tuple: svuint16x2_t, x: svuint16_t) -> svuint16x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_u32<const IMM_INDEX: i32>(tuple: svuint32x2_t, x: svuint32_t) -> svuint32x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset2_u64<const IMM_INDEX: i32>(tuple: svuint64x2_t, x: svuint64_t) -> svuint64x2_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_f32<const IMM_INDEX: i32>(tuple: svfloat32x3_t, x: svfloat32_t) -> svfloat32x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_f64<const IMM_INDEX: i32>(tuple: svfloat64x3_t, x: svfloat64_t) -> svfloat64x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_s8<const IMM_INDEX: i32>(tuple: svint8x3_t, x: svint8_t) -> svint8x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_s16<const IMM_INDEX: i32>(tuple: svint16x3_t, x: svint16_t) -> svint16x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_s32<const IMM_INDEX: i32>(tuple: svint32x3_t, x: svint32_t) -> svint32x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_s64<const IMM_INDEX: i32>(tuple: svint64x3_t, x: svint64_t) -> svint64x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_u8<const IMM_INDEX: i32>(tuple: svuint8x3_t, x: svuint8_t) -> svuint8x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_u16<const IMM_INDEX: i32>(tuple: svuint16x3_t, x: svuint16_t) -> svuint16x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_u32<const IMM_INDEX: i32>(tuple: svuint32x3_t, x: svuint32_t) -> svuint32x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset3_u64<const IMM_INDEX: i32>(tuple: svuint64x3_t, x: svuint64_t) -> svuint64x3_t {
+    static_assert_range!(IMM_INDEX, 0..=2);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_f32<const IMM_INDEX: i32>(tuple: svfloat32x4_t, x: svfloat32_t) -> svfloat32x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_f64<const IMM_INDEX: i32>(tuple: svfloat64x4_t, x: svfloat64_t) -> svfloat64x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_s8<const IMM_INDEX: i32>(tuple: svint8x4_t, x: svint8_t) -> svint8x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_s16<const IMM_INDEX: i32>(tuple: svint16x4_t, x: svint16_t) -> svint16x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_s32<const IMM_INDEX: i32>(tuple: svint32x4_t, x: svint32_t) -> svint32x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_s64<const IMM_INDEX: i32>(tuple: svint64x4_t, x: svint64_t) -> svint64x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_u8<const IMM_INDEX: i32>(tuple: svuint8x4_t, x: svuint8_t) -> svuint8x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_u16<const IMM_INDEX: i32>(tuple: svuint16x4_t, x: svuint16_t) -> svuint16x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_u32<const IMM_INDEX: i32>(tuple: svuint32x4_t, x: svuint32_t) -> svuint32x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Change one vector in a tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub fn svset4_u64<const IMM_INDEX: i32>(tuple: svuint64x4_t, x: svuint64_t) -> svuint64x4_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) }
+}
+#[doc = "Initialize the first-fault register to all-true"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsetffr)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(setffr))]
+pub fn svsetffr() {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.setffr")]
+        fn _svsetffr();
+    }
+    unsafe { _svsetffr() }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4f32")]
+        fn _svsplice_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svsplice_f32(pg.sve_into(), op1, op2) }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2f64")]
+        fn _svsplice_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svsplice_f64(pg.sve_into(), op1, op2) }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv16i8")]
+        fn _svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svsplice_s8(pg, op1, op2) }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv8i16")]
+        fn _svsplice_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svsplice_s16(pg.sve_into(), op1, op2) }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4i32")]
+        fn _svsplice_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsplice_s32(pg.sve_into(), op1, op2) }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2i64")]
+        fn _svsplice_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svsplice_s64(pg.sve_into(), op1, op2) }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svsplice_s8(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svsplice_s16(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svsplice_s32(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Splice two vectors under predicate control"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(splice))]
+pub fn svsplice_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svsplice_s64(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Square root"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsqrt))]
+pub fn svsqrt_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv4f32")]
+        fn _svsqrt_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svsqrt_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Square root"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsqrt))]
+pub fn svsqrt_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svsqrt_f32_m(op, pg, op)
+}
+#[doc = "Square root"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsqrt))]
+pub fn svsqrt_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
+    svsqrt_f32_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Square root"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsqrt))]
+pub fn svsqrt_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv2f64")]
+        fn _svsqrt_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svsqrt_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Square root"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsqrt))]
+pub fn svsqrt_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svsqrt_f64_m(op, pg, op)
+}
+#[doc = "Square root"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsqrt))]
+pub fn svsqrt_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
+    svsqrt_f64_m(svdup_n_f64(0.0), pg, op)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4f32")]
+        fn _svst1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32);
+    }
+    _svst1_f32(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2f64")]
+        fn _svst1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64);
+    }
+    _svst1_f64(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv16i8")]
+        fn _svst1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8);
+    }
+    _svst1_s8(data, pg, base)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i16")]
+        fn _svst1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16);
+    }
+    _svst1_s16(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i32")]
+        fn _svst1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32);
+    }
+    _svst1_s32(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i64")]
+        fn _svst1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64);
+    }
+    _svst1_s64(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) {
+    svst1_s8(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) {
+    svst1_s16(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) {
+    svst1_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) {
+    svst1_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_s32index_f32(
+    pg: svbool_t,
+    base: *mut f32,
+    indices: svint32_t,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32"
+        )]
+        fn _svst1_scatter_s32index_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            base: *mut f32,
+            indices: svint32_t,
+        );
+    }
+    _svst1_scatter_s32index_f32(data, pg.sve_into(), base, indices)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_s32index_s32(
+    pg: svbool_t,
+    base: *mut i32,
+    indices: svint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32"
+        )]
+        fn _svst1_scatter_s32index_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            base: *mut i32,
+            indices: svint32_t,
+        );
+    }
+    _svst1_scatter_s32index_s32(data, pg.sve_into(), base, indices)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_s32index_u32(
+    pg: svbool_t,
+    base: *mut u32,
+    indices: svint32_t,
+    data: svuint32_t,
+) {
+    svst1_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_s64index_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    indices: svint64_t,
+    data: svfloat64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2f64"
+        )]
+        fn _svst1_scatter_s64index_f64(
+            data: svfloat64_t,
+            pg: svbool2_t,
+            base: *mut f64,
+            indices: svint64_t,
+        );
+    }
+    _svst1_scatter_s64index_f64(data, pg.sve_into(), base, indices)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_s64index_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    indices: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i64"
+        )]
+        fn _svst1_scatter_s64index_s64(
+            data: svint64_t,
+            pg: svbool2_t,
+            base: *mut i64,
+            indices: svint64_t,
+        );
+    }
+    _svst1_scatter_s64index_s64(data, pg.sve_into(), base, indices)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_s64index_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    indices: svint64_t,
+    data: svuint64_t,
+) {
+    svst1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32index_f32(
+    pg: svbool_t,
+    base: *mut f32,
+    indices: svuint32_t,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32"
+        )]
+        fn _svst1_scatter_u32index_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            base: *mut f32,
+            indices: svint32_t,
+        );
+    }
+    _svst1_scatter_u32index_f32(data, pg.sve_into(), base, indices.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32index_s32(
+    pg: svbool_t,
+    base: *mut i32,
+    indices: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32"
+        )]
+        fn _svst1_scatter_u32index_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            base: *mut i32,
+            indices: svint32_t,
+        );
+    }
+    _svst1_scatter_u32index_s32(data, pg.sve_into(), base, indices.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32index_u32(
+    pg: svbool_t,
+    base: *mut u32,
+    indices: svuint32_t,
+    data: svuint32_t,
+) {
+    svst1_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64index_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    indices: svuint64_t,
+    data: svfloat64_t,
+) {
+    svst1_scatter_s64index_f64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64index_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    indices: svuint64_t,
+    data: svint64_t,
+) {
+    svst1_scatter_s64index_s64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64index_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    indices: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_s32offset_f32(
+    pg: svbool_t,
+    base: *mut f32,
+    offsets: svint32_t,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4f32"
+        )]
+        fn _svst1_scatter_s32offset_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            base: *mut f32,
+            offsets: svint32_t,
+        );
+    }
+    _svst1_scatter_s32offset_f32(data, pg.sve_into(), base, offsets)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_s32offset_s32(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32"
+        )]
+        fn _svst1_scatter_s32offset_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            base: *mut i32,
+            offsets: svint32_t,
+        );
+    }
+    _svst1_scatter_s32offset_s32(data, pg.sve_into(), base, offsets)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_s32offset_u32(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svint32_t,
+    data: svuint32_t,
+) {
+    svst1_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_s64offset_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    offsets: svint64_t,
+    data: svfloat64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.nxv2f64"
+        )]
+        fn _svst1_scatter_s64offset_f64(
+            data: svfloat64_t,
+            pg: svbool2_t,
+            base: *mut f64,
+            offsets: svint64_t,
+        );
+    }
+    _svst1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.nxv2i64"
+        )]
+        fn _svst1_scatter_s64offset_s64(
+            data: svint64_t,
+            pg: svbool2_t,
+            base: *mut i64,
+            offsets: svint64_t,
+        );
+    }
+    _svst1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32offset_f32(
+    pg: svbool_t,
+    base: *mut f32,
+    offsets: svuint32_t,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4f32"
+        )]
+        fn _svst1_scatter_u32offset_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            base: *mut f32,
+            offsets: svint32_t,
+        );
+    }
+    _svst1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32offset_s32(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32"
+        )]
+        fn _svst1_scatter_u32offset_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            base: *mut i32,
+            offsets: svint32_t,
+        );
+    }
+    _svst1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32offset_u32(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svuint32_t,
+    data: svuint32_t,
+) {
+    svst1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64offset_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    offsets: svuint64_t,
+    data: svfloat64_t,
+) {
+    svst1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svst1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) {
+    svst1_scatter_u32base_offset_f32(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) {
+    svst1_scatter_u32base_offset_s32(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) {
+    svst1_scatter_u32base_offset_u32(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) {
+    svst1_scatter_u64base_offset_f64(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svst1_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svst1_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_index_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svfloat32_t,
+) {
+    svst1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svint32_t,
+) {
+    svst1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svuint32_t,
+) {
+    svst1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_index_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svfloat64_t,
+) {
+    svst1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svint64_t,
+) {
+    svst1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svuint64_t,
+) {
+    svst1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_offset_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4f32.nxv4i32"
+        )]
+        fn _svst1_scatter_u32base_offset_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svst1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32"
+        )]
+        fn _svst1_scatter_u32base_offset_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svst1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_scatter_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svuint32_t,
+) {
+    svst1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_offset_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svfloat64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2f64.nxv2i64"
+        )]
+        fn _svst1_scatter_u64base_offset_f64(
+            data: svfloat64_t,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svst1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64"
+        )]
+        fn _svst1_scatter_u64base_offset_s64(
+            data: svint64_t,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svst1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svst1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) {
+    svst1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) {
+    svst1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) {
+    svst1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) {
+    svst1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) {
+    svst1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) {
+    svst1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) {
+    svst1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) {
+    svst1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) {
+    svst1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1d))]
+pub unsafe fn svst1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) {
+    svst1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_s16(pg: svbool_t, base: *mut i8, data: svint16_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i8")]
+        fn _svst1b_s16(data: nxv8i8, pg: svbool8_t, ptr: *mut i8);
+    }
+    _svst1b_s16(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_s32(pg: svbool_t, base: *mut i8, data: svint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i8")]
+        fn _svst1b_s32(data: nxv4i8, pg: svbool4_t, ptr: *mut i8);
+    }
+    _svst1b_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_s32(pg: svbool_t, base: *mut i16, data: svint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i16")]
+        fn _svst1h_s32(data: nxv4i16, pg: svbool4_t, ptr: *mut i16);
+    }
+    _svst1h_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_s64(pg: svbool_t, base: *mut i8, data: svint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i8")]
+        fn _svst1b_s64(data: nxv2i8, pg: svbool2_t, ptr: *mut i8);
+    }
+    _svst1b_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_s64(pg: svbool_t, base: *mut i16, data: svint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i16")]
+        fn _svst1h_s64(data: nxv2i16, pg: svbool2_t, ptr: *mut i16);
+    }
+    _svst1h_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_s64(pg: svbool_t, base: *mut i32, data: svint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i32")]
+        fn _svst1w_s64(data: nxv2i32, pg: svbool2_t, ptr: *mut i32);
+    }
+    _svst1w_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_u16(pg: svbool_t, base: *mut u8, data: svuint16_t) {
+    svst1b_s16(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_u32(pg: svbool_t, base: *mut u8, data: svuint32_t) {
+    svst1b_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_u32(pg: svbool_t, base: *mut u16, data: svuint32_t) {
+    svst1h_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_u64(pg: svbool_t, base: *mut u8, data: svuint64_t) {
+    svst1b_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_u64(pg: svbool_t, base: *mut u16, data: svuint64_t) {
+    svst1h_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_u64(pg: svbool_t, base: *mut u32, data: svuint64_t) {
+    svst1w_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_s32offset_s32(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8"
+        )]
+        fn _svst1b_scatter_s32offset_s32(
+            data: nxv4i8,
+            pg: svbool4_t,
+            base: *mut i8,
+            offsets: svint32_t,
+        );
+    }
+    _svst1b_scatter_s32offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s32offset_s32(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16"
+        )]
+        fn _svst1h_scatter_s32offset_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            base: *mut i16,
+            offsets: svint32_t,
+        );
+    }
+    _svst1h_scatter_s32offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_s32offset_u32(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svint32_t,
+    data: svuint32_t,
+) {
+    svst1b_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s32offset_u32(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svint32_t,
+    data: svuint32_t,
+) {
+    svst1h_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.nxv2i8"
+        )]
+        fn _svst1b_scatter_s64offset_s64(
+            data: nxv2i8,
+            pg: svbool2_t,
+            base: *mut i8,
+            offsets: svint64_t,
+        );
+    }
+    _svst1b_scatter_s64offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.nxv2i16"
+        )]
+        fn _svst1h_scatter_s64offset_s64(
+            data: nxv2i16,
+            pg: svbool2_t,
+            base: *mut i16,
+            offsets: svint64_t,
+        );
+    }
+    _svst1h_scatter_s64offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.nxv2i32"
+        )]
+        fn _svst1w_scatter_s64offset_s64(
+            data: nxv2i32,
+            pg: svbool2_t,
+            base: *mut i32,
+            offsets: svint64_t,
+        );
+    }
+    _svst1w_scatter_s64offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u32offset_s32(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8"
+        )]
+        fn _svst1b_scatter_u32offset_s32(
+            data: nxv4i8,
+            pg: svbool4_t,
+            base: *mut i8,
+            offsets: svint32_t,
+        );
+    }
+    _svst1b_scatter_u32offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32offset_s32(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i16"
+        )]
+        fn _svst1h_scatter_u32offset_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            base: *mut i16,
+            offsets: svint32_t,
+        );
+    }
+    _svst1h_scatter_u32offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u32offset_u32(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svuint32_t,
+    data: svuint32_t,
+) {
+    svst1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32offset_u32(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svuint32_t,
+    data: svuint32_t,
+) {
+    svst1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svst1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svst1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svst1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svst1b_scatter_u32base_offset_s32(
+            data: nxv4i8,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svst1b_scatter_u32base_offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svst1h_scatter_u32base_offset_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svst1h_scatter_u32base_offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svuint32_t,
+) {
+    svst1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svuint32_t,
+) {
+    svst1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svst1b_scatter_u64base_offset_s64(
+            data: nxv2i8,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svst1b_scatter_u64base_offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svst1h_scatter_u64base_offset_s64(
+            data: nxv2i16,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svst1h_scatter_u64base_offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svst1w_scatter_u64base_offset_s64(
+            data: nxv2i32,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svst1w_scatter_u64base_offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svst1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svst1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svst1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) {
+    svst1b_scatter_u32base_offset_s32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) {
+    svst1h_scatter_u32base_offset_s32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) {
+    svst1b_scatter_u32base_offset_u32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) {
+    svst1h_scatter_u32base_offset_u32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svst1b_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svst1h_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svst1w_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svst1b_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svst1h_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svst1w_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_vnum_s16(pg: svbool_t, base: *mut i8, vnum: i64, data: svint16_t) {
+    svst1b_s16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_vnum_s32(pg: svbool_t, base: *mut i8, vnum: i64, data: svint32_t) {
+    svst1b_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_vnum_s32(pg: svbool_t, base: *mut i16, vnum: i64, data: svint32_t) {
+    svst1h_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_vnum_s64(pg: svbool_t, base: *mut i8, vnum: i64, data: svint64_t) {
+    svst1b_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_vnum_s64(pg: svbool_t, base: *mut i16, vnum: i64, data: svint64_t) {
+    svst1h_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_vnum_s64(pg: svbool_t, base: *mut i32, vnum: i64, data: svint64_t) {
+    svst1w_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_vnum_u16(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint16_t) {
+    svst1b_u16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_vnum_u32(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint32_t) {
+    svst1b_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_vnum_u32(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint32_t) {
+    svst1h_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 8 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1b))]
+pub unsafe fn svst1b_vnum_u64(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint64_t) {
+    svst1b_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_vnum_u64(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint64_t) {
+    svst1h_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_vnum_u64(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint64_t) {
+    svst1w_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s32index_s32(
+    pg: svbool_t,
+    base: *mut i16,
+    indices: svint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16"
+        )]
+        fn _svst1h_scatter_s32index_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            base: *mut i16,
+            indices: svint32_t,
+        );
+    }
+    _svst1h_scatter_s32index_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        indices,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s32index_u32(
+    pg: svbool_t,
+    base: *mut u16,
+    indices: svint32_t,
+    data: svuint32_t,
+) {
+    svst1h_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s64index_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    indices: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i16"
+        )]
+        fn _svst1h_scatter_s64index_s64(
+            data: nxv2i16,
+            pg: svbool2_t,
+            base: *mut i16,
+            indices: svint64_t,
+        );
+    }
+    _svst1h_scatter_s64index_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        indices,
+    )
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_s64index_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    indices: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i32"
+        )]
+        fn _svst1w_scatter_s64index_s64(
+            data: nxv2i32,
+            pg: svbool2_t,
+            base: *mut i32,
+            indices: svint64_t,
+        );
+    }
+    _svst1w_scatter_s64index_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        indices,
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_s64index_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    indices: svint64_t,
+    data: svuint64_t,
+) {
+    svst1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_s64index_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    indices: svint64_t,
+    data: svuint64_t,
+) {
+    svst1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32index_s32(
+    pg: svbool_t,
+    base: *mut i16,
+    indices: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16"
+        )]
+        fn _svst1h_scatter_u32index_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            base: *mut i16,
+            indices: svint32_t,
+        );
+    }
+    _svst1h_scatter_u32index_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        indices.as_signed(),
+    )
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32index_u32(
+    pg: svbool_t,
+    base: *mut u16,
+    indices: svuint32_t,
+    data: svuint32_t,
+) {
+    svst1h_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64index_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    indices: svuint64_t,
+    data: svint64_t,
+) {
+    svst1h_scatter_s64index_s64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64index_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    indices: svuint64_t,
+    data: svint64_t,
+) {
+    svst1w_scatter_s64index_s64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64index_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    indices: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64index_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    indices: svuint64_t,
+    data: svuint64_t,
+) {
+    svst1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svint32_t,
+) {
+    svst1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svuint32_t,
+) {
+    svst1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svint64_t,
+) {
+    svst1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svint64_t,
+) {
+    svst1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Truncate to 16 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1h))]
+pub unsafe fn svst1h_scatter_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svuint64_t,
+) {
+    svst1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 32 bits and store"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st1w))]
+pub unsafe fn svst1w_scatter_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svuint64_t,
+) {
+    svst1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2w))]
+pub unsafe fn svst2_f32(pg: svbool_t, base: *mut f32, data: svfloat32x2_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4f32")]
+        fn _svst2_f32(data0: svfloat32_t, data1: svfloat32_t, pg: svbool4_t, ptr: *mut f32);
+    }
+    _svst2_f32(
+        svget2_f32::<0>(data),
+        svget2_f32::<1>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2d))]
+pub unsafe fn svst2_f64(pg: svbool_t, base: *mut f64, data: svfloat64x2_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2f64")]
+        fn _svst2_f64(data0: svfloat64_t, data1: svfloat64_t, pg: svbool2_t, ptr: *mut f64);
+    }
+    _svst2_f64(
+        svget2_f64::<0>(data),
+        svget2_f64::<1>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2b))]
+pub unsafe fn svst2_s8(pg: svbool_t, base: *mut i8, data: svint8x2_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv16i8")]
+        fn _svst2_s8(data0: svint8_t, data1: svint8_t, pg: svbool_t, ptr: *mut i8);
+    }
+    _svst2_s8(svget2_s8::<0>(data), svget2_s8::<1>(data), pg, base)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2h))]
+pub unsafe fn svst2_s16(pg: svbool_t, base: *mut i16, data: svint16x2_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv8i16")]
+        fn _svst2_s16(data0: svint16_t, data1: svint16_t, pg: svbool8_t, ptr: *mut i16);
+    }
+    _svst2_s16(
+        svget2_s16::<0>(data),
+        svget2_s16::<1>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2w))]
+pub unsafe fn svst2_s32(pg: svbool_t, base: *mut i32, data: svint32x2_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4i32")]
+        fn _svst2_s32(data0: svint32_t, data1: svint32_t, pg: svbool4_t, ptr: *mut i32);
+    }
+    _svst2_s32(
+        svget2_s32::<0>(data),
+        svget2_s32::<1>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2d))]
+pub unsafe fn svst2_s64(pg: svbool_t, base: *mut i64, data: svint64x2_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2i64")]
+        fn _svst2_s64(data0: svint64_t, data1: svint64_t, pg: svbool2_t, ptr: *mut i64);
+    }
+    _svst2_s64(
+        svget2_s64::<0>(data),
+        svget2_s64::<1>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2b))]
+pub unsafe fn svst2_u8(pg: svbool_t, base: *mut u8, data: svuint8x2_t) {
+    svst2_s8(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2h))]
+pub unsafe fn svst2_u16(pg: svbool_t, base: *mut u16, data: svuint16x2_t) {
+    svst2_s16(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2w))]
+pub unsafe fn svst2_u32(pg: svbool_t, base: *mut u32, data: svuint32x2_t) {
+    svst2_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2d))]
+pub unsafe fn svst2_u64(pg: svbool_t, base: *mut u64, data: svuint64x2_t) {
+    svst2_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2w))]
+pub unsafe fn svst2_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x2_t) {
+    svst2_f32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2d))]
+pub unsafe fn svst2_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x2_t) {
+    svst2_f64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2b))]
+pub unsafe fn svst2_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x2_t) {
+    svst2_s8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2h))]
+pub unsafe fn svst2_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x2_t) {
+    svst2_s16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2w))]
+pub unsafe fn svst2_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x2_t) {
+    svst2_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2d))]
+pub unsafe fn svst2_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x2_t) {
+    svst2_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2b))]
+pub unsafe fn svst2_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x2_t) {
+    svst2_u8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2h))]
+pub unsafe fn svst2_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x2_t) {
+    svst2_u16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2w))]
+pub unsafe fn svst2_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x2_t) {
+    svst2_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store two vectors into two-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st2d))]
+pub unsafe fn svst2_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x2_t) {
+    svst2_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3w))]
+pub unsafe fn svst3_f32(pg: svbool_t, base: *mut f32, data: svfloat32x3_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4f32")]
+        fn _svst3_f32(
+            data0: svfloat32_t,
+            data1: svfloat32_t,
+            data2: svfloat32_t,
+            pg: svbool4_t,
+            ptr: *mut f32,
+        );
+    }
+    _svst3_f32(
+        svget3_f32::<0>(data),
+        svget3_f32::<1>(data),
+        svget3_f32::<2>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3d))]
+pub unsafe fn svst3_f64(pg: svbool_t, base: *mut f64, data: svfloat64x3_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2f64")]
+        fn _svst3_f64(
+            data0: svfloat64_t,
+            data1: svfloat64_t,
+            data2: svfloat64_t,
+            pg: svbool2_t,
+            ptr: *mut f64,
+        );
+    }
+    _svst3_f64(
+        svget3_f64::<0>(data),
+        svget3_f64::<1>(data),
+        svget3_f64::<2>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3b))]
+pub unsafe fn svst3_s8(pg: svbool_t, base: *mut i8, data: svint8x3_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv16i8")]
+        fn _svst3_s8(data0: svint8_t, data1: svint8_t, data2: svint8_t, pg: svbool_t, ptr: *mut i8);
+    }
+    _svst3_s8(
+        svget3_s8::<0>(data),
+        svget3_s8::<1>(data),
+        svget3_s8::<2>(data),
+        pg,
+        base,
+    )
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3h))]
+pub unsafe fn svst3_s16(pg: svbool_t, base: *mut i16, data: svint16x3_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv8i16")]
+        fn _svst3_s16(
+            data0: svint16_t,
+            data1: svint16_t,
+            data2: svint16_t,
+            pg: svbool8_t,
+            ptr: *mut i16,
+        );
+    }
+    _svst3_s16(
+        svget3_s16::<0>(data),
+        svget3_s16::<1>(data),
+        svget3_s16::<2>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3w))]
+pub unsafe fn svst3_s32(pg: svbool_t, base: *mut i32, data: svint32x3_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4i32")]
+        fn _svst3_s32(
+            data0: svint32_t,
+            data1: svint32_t,
+            data2: svint32_t,
+            pg: svbool4_t,
+            ptr: *mut i32,
+        );
+    }
+    _svst3_s32(
+        svget3_s32::<0>(data),
+        svget3_s32::<1>(data),
+        svget3_s32::<2>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3d))]
+pub unsafe fn svst3_s64(pg: svbool_t, base: *mut i64, data: svint64x3_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2i64")]
+        fn _svst3_s64(
+            data0: svint64_t,
+            data1: svint64_t,
+            data2: svint64_t,
+            pg: svbool2_t,
+            ptr: *mut i64,
+        );
+    }
+    _svst3_s64(
+        svget3_s64::<0>(data),
+        svget3_s64::<1>(data),
+        svget3_s64::<2>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3b))]
+pub unsafe fn svst3_u8(pg: svbool_t, base: *mut u8, data: svuint8x3_t) {
+    svst3_s8(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3h))]
+pub unsafe fn svst3_u16(pg: svbool_t, base: *mut u16, data: svuint16x3_t) {
+    svst3_s16(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3w))]
+pub unsafe fn svst3_u32(pg: svbool_t, base: *mut u32, data: svuint32x3_t) {
+    svst3_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3d))]
+pub unsafe fn svst3_u64(pg: svbool_t, base: *mut u64, data: svuint64x3_t) {
+    svst3_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3w))]
+pub unsafe fn svst3_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x3_t) {
+    svst3_f32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3d))]
+pub unsafe fn svst3_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x3_t) {
+    svst3_f64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3b))]
+pub unsafe fn svst3_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x3_t) {
+    svst3_s8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3h))]
+pub unsafe fn svst3_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x3_t) {
+    svst3_s16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3w))]
+pub unsafe fn svst3_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x3_t) {
+    svst3_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3d))]
+pub unsafe fn svst3_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x3_t) {
+    svst3_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3b))]
+pub unsafe fn svst3_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x3_t) {
+    svst3_u8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3h))]
+pub unsafe fn svst3_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x3_t) {
+    svst3_u16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3w))]
+pub unsafe fn svst3_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x3_t) {
+    svst3_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store three vectors into three-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st3d))]
+pub unsafe fn svst3_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x3_t) {
+    svst3_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4w))]
+pub unsafe fn svst4_f32(pg: svbool_t, base: *mut f32, data: svfloat32x4_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4f32")]
+        fn _svst4_f32(
+            data0: svfloat32_t,
+            data1: svfloat32_t,
+            data2: svfloat32_t,
+            data3: svfloat32_t,
+            pg: svbool4_t,
+            ptr: *mut f32,
+        );
+    }
+    _svst4_f32(
+        svget4_f32::<0>(data),
+        svget4_f32::<1>(data),
+        svget4_f32::<2>(data),
+        svget4_f32::<3>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4d))]
+pub unsafe fn svst4_f64(pg: svbool_t, base: *mut f64, data: svfloat64x4_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2f64")]
+        fn _svst4_f64(
+            data0: svfloat64_t,
+            data1: svfloat64_t,
+            data2: svfloat64_t,
+            data3: svfloat64_t,
+            pg: svbool2_t,
+            ptr: *mut f64,
+        );
+    }
+    _svst4_f64(
+        svget4_f64::<0>(data),
+        svget4_f64::<1>(data),
+        svget4_f64::<2>(data),
+        svget4_f64::<3>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4b))]
+pub unsafe fn svst4_s8(pg: svbool_t, base: *mut i8, data: svint8x4_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv16i8")]
+        fn _svst4_s8(
+            data0: svint8_t,
+            data1: svint8_t,
+            data2: svint8_t,
+            data3: svint8_t,
+            pg: svbool_t,
+            ptr: *mut i8,
+        );
+    }
+    _svst4_s8(
+        svget4_s8::<0>(data),
+        svget4_s8::<1>(data),
+        svget4_s8::<2>(data),
+        svget4_s8::<3>(data),
+        pg,
+        base,
+    )
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4h))]
+pub unsafe fn svst4_s16(pg: svbool_t, base: *mut i16, data: svint16x4_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv8i16")]
+        fn _svst4_s16(
+            data0: svint16_t,
+            data1: svint16_t,
+            data2: svint16_t,
+            data3: svint16_t,
+            pg: svbool8_t,
+            ptr: *mut i16,
+        );
+    }
+    _svst4_s16(
+        svget4_s16::<0>(data),
+        svget4_s16::<1>(data),
+        svget4_s16::<2>(data),
+        svget4_s16::<3>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4w))]
+pub unsafe fn svst4_s32(pg: svbool_t, base: *mut i32, data: svint32x4_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4i32")]
+        fn _svst4_s32(
+            data0: svint32_t,
+            data1: svint32_t,
+            data2: svint32_t,
+            data3: svint32_t,
+            pg: svbool4_t,
+            ptr: *mut i32,
+        );
+    }
+    _svst4_s32(
+        svget4_s32::<0>(data),
+        svget4_s32::<1>(data),
+        svget4_s32::<2>(data),
+        svget4_s32::<3>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4d))]
+pub unsafe fn svst4_s64(pg: svbool_t, base: *mut i64, data: svint64x4_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2i64")]
+        fn _svst4_s64(
+            data0: svint64_t,
+            data1: svint64_t,
+            data2: svint64_t,
+            data3: svint64_t,
+            pg: svbool2_t,
+            ptr: *mut i64,
+        );
+    }
+    _svst4_s64(
+        svget4_s64::<0>(data),
+        svget4_s64::<1>(data),
+        svget4_s64::<2>(data),
+        svget4_s64::<3>(data),
+        pg.sve_into(),
+        base,
+    )
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4b))]
+pub unsafe fn svst4_u8(pg: svbool_t, base: *mut u8, data: svuint8x4_t) {
+    svst4_s8(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4h))]
+pub unsafe fn svst4_u16(pg: svbool_t, base: *mut u16, data: svuint16x4_t) {
+    svst4_s16(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4w))]
+pub unsafe fn svst4_u32(pg: svbool_t, base: *mut u32, data: svuint32x4_t) {
+    svst4_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4d))]
+pub unsafe fn svst4_u64(pg: svbool_t, base: *mut u64, data: svuint64x4_t) {
+    svst4_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4w))]
+pub unsafe fn svst4_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x4_t) {
+    svst4_f32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4d))]
+pub unsafe fn svst4_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x4_t) {
+    svst4_f64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4b))]
+pub unsafe fn svst4_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x4_t) {
+    svst4_s8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4h))]
+pub unsafe fn svst4_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x4_t) {
+    svst4_s16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4w))]
+pub unsafe fn svst4_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x4_t) {
+    svst4_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4d))]
+pub unsafe fn svst4_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x4_t) {
+    svst4_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4b))]
+pub unsafe fn svst4_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x4_t) {
+    svst4_u8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4h))]
+pub unsafe fn svst4_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x4_t) {
+    svst4_u16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4w))]
+pub unsafe fn svst4_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x4_t) {
+    svst4_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Store four vectors into four-element tuples"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(st4d))]
+pub unsafe fn svst4_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x4_t) {
+    svst4_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4f32")]
+        fn _svstnt1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32);
+    }
+    _svstnt1_f32(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2f64")]
+        fn _svstnt1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64);
+    }
+    _svstnt1_f64(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv16i8")]
+        fn _svstnt1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8);
+    }
+    _svstnt1_s8(data, pg, base)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv8i16")]
+        fn _svstnt1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16);
+    }
+    _svstnt1_s16(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4i32")]
+        fn _svstnt1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32);
+    }
+    _svstnt1_s32(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2i64")]
+        fn _svstnt1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64);
+    }
+    _svstnt1_s64(data, pg.sve_into(), base)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) {
+    svstnt1_s8(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) {
+    svstnt1_s16(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) {
+    svstnt1_s32(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) {
+    svstnt1_s64(pg, base.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) {
+    svstnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) {
+    svstnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) {
+    svstnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) {
+    svstnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) {
+    svstnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) {
+    svstnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) {
+    svstnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) {
+    svstnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) {
+    svstnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) {
+    svstnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv4f32")]
+        fn _svsub_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svsub_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svsub_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svsub_f32_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svsub_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svsub_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svsub_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv2f64")]
+        fn _svsub_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svsub_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svsub_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svsub_f64_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svsub_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svsub_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsub))]
+pub fn svsub_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svsub_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv16i8")]
+        fn _svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svsub_s8_m(pg, op1, op2) }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svsub_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svsub_s8_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svsub_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svsub_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv8i16")]
+        fn _svsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svsub_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svsub_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svsub_s16_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svsub_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svsub_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv4i32")]
+        fn _svsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsub_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svsub_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svsub_s32_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svsub_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svsub_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv2i64")]
+        fn _svsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svsub_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svsub_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svsub_s64_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svsub_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svsub_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svsub_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svsub_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svsub_u8_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svsub_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svsub_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svsub_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svsub_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svsub_u16_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svsub_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svsub_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svsub_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svsub_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svsub_u32_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svsub_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svsub_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svsub_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svsub_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svsub_u64_m(pg, op1, op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svsub_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sub))]
+pub fn svsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svsub_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv4f32")]
+        fn _svsubr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svsubr_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svsubr_f32_m(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svsubr_f32_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svsubr_f32_x(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svsubr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
+    svsubr_f32_z(pg, op1, svdup_n_f32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv2f64")]
+        fn _svsubr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svsubr_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svsubr_f64_m(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svsubr_f64_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svsubr_f64_x(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svsubr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fsubr))]
+pub fn svsubr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
+    svsubr_f64_z(pg, op1, svdup_n_f64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv16i8")]
+        fn _svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svsubr_s8_m(pg, op1, op2) }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svsubr_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svsubr_s8_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svsubr_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svsubr_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv8i16")]
+        fn _svsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svsubr_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svsubr_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svsubr_s16_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svsubr_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svsubr_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv4i32")]
+        fn _svsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsubr_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svsubr_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svsubr_s32_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svsubr_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svsubr_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv2i64")]
+        fn _svsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svsubr_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svsubr_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svsubr_s64_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svsubr_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svsubr_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svsubr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svsubr_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svsubr_u8_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svsubr_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svsubr_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svsubr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svsubr_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svsubr_u16_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svsubr_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svsubr_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svsubr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svsubr_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svsubr_u32_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svsubr_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svsubr_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svsubr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svsubr_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svsubr_u64_m(pg, op1, op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svsubr_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subr))]
+pub fn svsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svsubr_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Dot product (signed × unsigned)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sudot, IMM_INDEX = 0))]
+pub fn svsudot_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint8_t,
+    op3: svuint8_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sudot.lane.nxv4i32"
+        )]
+        fn _svsudot_lane_s32(
+            op1: svint32_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_index: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svsudot_lane_s32(op1, op2, op3.as_signed(), IMM_INDEX) }
+}
+#[doc = "Dot product (signed × unsigned)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usdot))]
+pub fn svsudot_s32(op1: svint32_t, op2: svint8_t, op3: svuint8_t) -> svint32_t {
+    svusdot_s32(op1, op3, op2)
+}
+#[doc = "Dot product (signed × unsigned)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usdot))]
+pub fn svsudot_n_s32(op1: svint32_t, op2: svint8_t, op3: u8) -> svint32_t {
+    svsudot_s32(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_f32(data: svfloat32_t, indices: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4f32")]
+        fn _svtbl_f32(data: svfloat32_t, indices: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svtbl_f32(data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_f64(data: svfloat64_t, indices: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2f64")]
+        fn _svtbl_f64(data: svfloat64_t, indices: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svtbl_f64(data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_s8(data: svint8_t, indices: svuint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv16i8")]
+        fn _svtbl_s8(data: svint8_t, indices: svint8_t) -> svint8_t;
+    }
+    unsafe { _svtbl_s8(data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_s16(data: svint16_t, indices: svuint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv8i16")]
+        fn _svtbl_s16(data: svint16_t, indices: svint16_t) -> svint16_t;
+    }
+    unsafe { _svtbl_s16(data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_s32(data: svint32_t, indices: svuint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4i32")]
+        fn _svtbl_s32(data: svint32_t, indices: svint32_t) -> svint32_t;
+    }
+    unsafe { _svtbl_s32(data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_s64(data: svint64_t, indices: svuint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2i64")]
+        fn _svtbl_s64(data: svint64_t, indices: svint64_t) -> svint64_t;
+    }
+    unsafe { _svtbl_s64(data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_u8(data: svuint8_t, indices: svuint8_t) -> svuint8_t {
+    unsafe { svtbl_s8(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_u16(data: svuint16_t, indices: svuint16_t) -> svuint16_t {
+    unsafe { svtbl_s16(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_u32(data: svuint32_t, indices: svuint32_t) -> svuint32_t {
+    unsafe { svtbl_s32(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl_u64(data: svuint64_t, indices: svuint64_t) -> svuint64_t {
+    unsafe { svtbl_s64(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Trigonometric multiply-add coefficient"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))]
+pub fn svtmad_f32<const IMM3: i32>(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    static_assert_range!(IMM3, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ftmad.x.nxv4f32"
+        )]
+        fn _svtmad_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t;
+    }
+    unsafe { _svtmad_f32(op1, op2, IMM3) }
+}
+#[doc = "Trigonometric multiply-add coefficient"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))]
+pub fn svtmad_f64<const IMM3: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    static_assert_range!(IMM3, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ftmad.x.nxv2f64"
+        )]
+        fn _svtmad_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t;
+    }
+    unsafe { _svtmad_f64(op1, op2, IMM3) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")]
+        fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svtrn1_b8(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i1")]
+        fn _svtrn1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i1")]
+        fn _svtrn1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i1")]
+        fn _svtrn1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4f32")]
+        fn _svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svtrn1_f32(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2f64")]
+        fn _svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svtrn1_f64(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i8")]
+        fn _svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svtrn1_s8(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i16")]
+        fn _svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svtrn1_s16(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i32")]
+        fn _svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svtrn1_s32(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i64")]
+        fn _svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svtrn1_s64(op1, op2) }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svtrn1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svtrn1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svtrn1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svtrn1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4f32")]
+        fn _svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svtrn1q_f32(op1, op2) }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2f64")]
+        fn _svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svtrn1q_f64(op1, op2) }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv16i8")]
+        fn _svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svtrn1q_s8(op1, op2) }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv8i16")]
+        fn _svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svtrn1q_s16(op1, op2) }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4i32")]
+        fn _svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svtrn1q_s32(op1, op2) }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2i64")]
+        fn _svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svtrn1q_s64(op1, op2) }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svtrn1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svtrn1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svtrn1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svtrn1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")]
+        fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svtrn2_b8(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i1")]
+        fn _svtrn2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i1")]
+        fn _svtrn2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i1")]
+        fn _svtrn2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4f32")]
+        fn _svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svtrn2_f32(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2f64")]
+        fn _svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svtrn2_f64(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i8")]
+        fn _svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svtrn2_s8(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i16")]
+        fn _svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svtrn2_s16(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i32")]
+        fn _svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svtrn2_s32(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i64")]
+        fn _svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svtrn2_s64(op1, op2) }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svtrn2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svtrn2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svtrn2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svtrn2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4f32")]
+        fn _svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svtrn2q_f32(op1, op2) }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2f64")]
+        fn _svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svtrn2q_f64(op1, op2) }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv16i8")]
+        fn _svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svtrn2q_s8(op1, op2) }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv8i16")]
+        fn _svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svtrn2q_s16(op1, op2) }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4i32")]
+        fn _svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svtrn2q_s32(op1, op2) }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2i64")]
+        fn _svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svtrn2q_s64(op1, op2) }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svtrn2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svtrn2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svtrn2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svtrn2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Trigonometric starting value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ftsmul))]
+pub fn svtsmul_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ftsmul.x.nxv4f32"
+        )]
+        fn _svtsmul_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svtsmul_f32(op1, op2.as_signed()) }
+}
+#[doc = "Trigonometric starting value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ftsmul))]
+pub fn svtsmul_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ftsmul.x.nxv2f64"
+        )]
+        fn _svtsmul_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svtsmul_f64(op1, op2.as_signed()) }
+}
+#[doc = "Trigonometric select coefficient"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ftssel))]
+pub fn svtssel_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ftssel.x.nxv4f32"
+        )]
+        fn _svtssel_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svtssel_f32(op1, op2.as_signed()) }
+}
+#[doc = "Trigonometric select coefficient"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ftssel))]
+pub fn svtssel_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ftssel.x.nxv2f64"
+        )]
+        fn _svtssel_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svtssel_f64(op1, op2.as_signed()) }
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_f32() -> svfloat32x2_t {
+    svcreate2_f32(svdup_n_f32(0f32), svdup_n_f32(0f32))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_f64() -> svfloat64x2_t {
+    svcreate2_f64(svdup_n_f64(0f64), svdup_n_f64(0f64))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_s8() -> svint8x2_t {
+    svcreate2_s8(svdup_n_s8(0), svdup_n_s8(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_s16() -> svint16x2_t {
+    svcreate2_s16(svdup_n_s16(0), svdup_n_s16(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_s32() -> svint32x2_t {
+    svcreate2_s32(svdup_n_s32(0), svdup_n_s32(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_s64() -> svint64x2_t {
+    svcreate2_s64(svdup_n_s64(0), svdup_n_s64(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_u8() -> svuint8x2_t {
+    svcreate2_u8(svdup_n_u8(0), svdup_n_u8(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_u16() -> svuint16x2_t {
+    svcreate2_u16(svdup_n_u16(0), svdup_n_u16(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_u32() -> svuint32x2_t {
+    svcreate2_u32(svdup_n_u32(0), svdup_n_u32(0))
+}
+#[doc = "Create an uninitialized tuple of two vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef2_u64() -> svuint64x2_t {
+    svcreate2_u64(svdup_n_u64(0), svdup_n_u64(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_f32() -> svfloat32x3_t {
+    svcreate3_f32(svdup_n_f32(0f32), svdup_n_f32(0f32), svdup_n_f32(0f32))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_f64() -> svfloat64x3_t {
+    svcreate3_f64(svdup_n_f64(0f64), svdup_n_f64(0f64), svdup_n_f64(0f64))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_s8() -> svint8x3_t {
+    svcreate3_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_s16() -> svint16x3_t {
+    svcreate3_s16(svdup_n_s16(0), svdup_n_s16(0), svdup_n_s16(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_s32() -> svint32x3_t {
+    svcreate3_s32(svdup_n_s32(0), svdup_n_s32(0), svdup_n_s32(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_s64() -> svint64x3_t {
+    svcreate3_s64(svdup_n_s64(0), svdup_n_s64(0), svdup_n_s64(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_u8() -> svuint8x3_t {
+    svcreate3_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_u16() -> svuint16x3_t {
+    svcreate3_u16(svdup_n_u16(0), svdup_n_u16(0), svdup_n_u16(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_u32() -> svuint32x3_t {
+    svcreate3_u32(svdup_n_u32(0), svdup_n_u32(0), svdup_n_u32(0))
+}
+#[doc = "Create an uninitialized tuple of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef3_u64() -> svuint64x3_t {
+    svcreate3_u64(svdup_n_u64(0), svdup_n_u64(0), svdup_n_u64(0))
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_f32() -> svfloat32x4_t {
+    svcreate4_f32(
+        svdup_n_f32(0f32),
+        svdup_n_f32(0f32),
+        svdup_n_f32(0f32),
+        svdup_n_f32(0f32),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_f64() -> svfloat64x4_t {
+    svcreate4_f64(
+        svdup_n_f64(0f64),
+        svdup_n_f64(0f64),
+        svdup_n_f64(0f64),
+        svdup_n_f64(0f64),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_s8() -> svint8x4_t {
+    svcreate4_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0))
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_s16() -> svint16x4_t {
+    svcreate4_s16(
+        svdup_n_s16(0),
+        svdup_n_s16(0),
+        svdup_n_s16(0),
+        svdup_n_s16(0),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_s32() -> svint32x4_t {
+    svcreate4_s32(
+        svdup_n_s32(0),
+        svdup_n_s32(0),
+        svdup_n_s32(0),
+        svdup_n_s32(0),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_s64() -> svint64x4_t {
+    svcreate4_s64(
+        svdup_n_s64(0),
+        svdup_n_s64(0),
+        svdup_n_s64(0),
+        svdup_n_s64(0),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_u8() -> svuint8x4_t {
+    svcreate4_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0))
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_u16() -> svuint16x4_t {
+    svcreate4_u16(
+        svdup_n_u16(0),
+        svdup_n_u16(0),
+        svdup_n_u16(0),
+        svdup_n_u16(0),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_u32() -> svuint32x4_t {
+    svcreate4_u32(
+        svdup_n_u32(0),
+        svdup_n_u32(0),
+        svdup_n_u32(0),
+        svdup_n_u32(0),
+    )
+}
+#[doc = "Create an uninitialized tuple of four vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef4_u64() -> svuint64x4_t {
+    svcreate4_u64(
+        svdup_n_u64(0),
+        svdup_n_u64(0),
+        svdup_n_u64(0),
+        svdup_n_u64(0),
+    )
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_f32() -> svfloat32_t {
+    svdup_n_f32(0f32)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_f64() -> svfloat64_t {
+    svdup_n_f64(0f64)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_s8() -> svint8_t {
+    svdup_n_s8(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_s16() -> svint16_t {
+    svdup_n_s16(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_s32() -> svint32_t {
+    svdup_n_s32(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_s64() -> svint64_t {
+    svdup_n_s64(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_u8() -> svuint8_t {
+    svdup_n_u8(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_u16() -> svuint16_t {
+    svdup_n_u16(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_u32() -> svuint32_t {
+    svdup_n_u32(0)
+}
+#[doc = "Create an uninitialized vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+pub unsafe fn svundef_u64() -> svuint64_t {
+    svdup_n_u64(0)
+}
+#[doc = "Dot product (unsigned × signed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usdot, IMM_INDEX = 0))]
+pub fn svusdot_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svuint8_t,
+    op3: svint8_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.usdot.lane.nxv4i32"
+        )]
+        fn _svusdot_lane_s32(
+            op1: svint32_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_index: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svusdot_lane_s32(op1, op2.as_signed(), op3, IMM_INDEX) }
+}
+#[doc = "Dot product (unsigned × signed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usdot))]
+pub fn svusdot_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usdot.nxv4i32")]
+        fn _svusdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t;
+    }
+    unsafe { _svusdot_s32(op1, op2.as_signed(), op3) }
+}
+#[doc = "Dot product (unsigned × signed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usdot))]
+pub fn svusdot_n_s32(op1: svint32_t, op2: svuint8_t, op3: i8) -> svint32_t {
+    svusdot_s32(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Matrix multiply-accumulate (unsigned × signed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusmmla[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,i8mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usmmla))]
+pub fn svusmmla_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usmmla.nxv4i32")]
+        fn _svusmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t;
+    }
+    unsafe { _svusmmla_s32(op1, op2.as_signed(), op3) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i1")]
+        fn _svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svuzp1_b8(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i1")]
+        fn _svuzp1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svuzp1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i1")]
+        fn _svuzp1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svuzp1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i1")]
+        fn _svuzp1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svuzp1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4f32")]
+        fn _svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svuzp1_f32(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2f64")]
+        fn _svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svuzp1_f64(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i8")]
+        fn _svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svuzp1_s8(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i16")]
+        fn _svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svuzp1_s16(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i32")]
+        fn _svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svuzp1_s32(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i64")]
+        fn _svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svuzp1_s64(op1, op2) }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svuzp1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svuzp1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svuzp1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svuzp1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4f32")]
+        fn _svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svuzp1q_f32(op1, op2) }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2f64")]
+        fn _svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svuzp1q_f64(op1, op2) }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv16i8")]
+        fn _svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svuzp1q_s8(op1, op2) }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv8i16")]
+        fn _svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svuzp1q_s16(op1, op2) }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4i32")]
+        fn _svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svuzp1q_s32(op1, op2) }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2i64")]
+        fn _svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svuzp1q_s64(op1, op2) }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svuzp1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svuzp1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svuzp1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate even quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp1))]
+pub fn svuzp1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svuzp1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i1")]
+        fn _svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svuzp2_b8(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i1")]
+        fn _svuzp2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svuzp2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i1")]
+        fn _svuzp2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svuzp2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i1")]
+        fn _svuzp2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svuzp2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4f32")]
+        fn _svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svuzp2_f32(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2f64")]
+        fn _svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svuzp2_f64(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i8")]
+        fn _svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svuzp2_s8(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i16")]
+        fn _svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svuzp2_s16(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i32")]
+        fn _svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svuzp2_s32(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i64")]
+        fn _svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svuzp2_s64(op1, op2) }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svuzp2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svuzp2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svuzp2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svuzp2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4f32")]
+        fn _svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svuzp2q_f32(op1, op2) }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2f64")]
+        fn _svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svuzp2q_f64(op1, op2) }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv16i8")]
+        fn _svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svuzp2q_s8(op1, op2) }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv8i16")]
+        fn _svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svuzp2q_s16(op1, op2) }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4i32")]
+        fn _svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svuzp2q_s32(op1, op2) }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2i64")]
+        fn _svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svuzp2q_s64(op1, op2) }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svuzp2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svuzp2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svuzp2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Concatenate odd quadwords from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uzp2))]
+pub fn svuzp2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svuzp2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv16i1.i32"
+        )]
+        fn _svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilele_b8_s32(op1, op2) }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b16_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv8i1.i32"
+        )]
+        fn _svwhilele_b16_s32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilele_b16_s32(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b32_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv4i1.i32"
+        )]
+        fn _svwhilele_b32_s32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilele_b32_s32(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b64_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv2i1.i32"
+        )]
+        fn _svwhilele_b64_s32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilele_b64_s32(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv16i1.i64"
+        )]
+        fn _svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilele_b8_s64(op1, op2) }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b16_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv8i1.i64"
+        )]
+        fn _svwhilele_b16_s64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilele_b16_s64(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b32_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv4i1.i64"
+        )]
+        fn _svwhilele_b32_s64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilele_b32_s64(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilele))]
+pub fn svwhilele_b64_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilele.nxv2i1.i64"
+        )]
+        fn _svwhilele_b64_s64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilele_b64_s64(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b8_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv16i1.i32"
+        )]
+        fn _svwhilele_b8_u32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilele_b8_u32(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b16_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv8i1.i32"
+        )]
+        fn _svwhilele_b16_u32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilele_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b32_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv4i1.i32"
+        )]
+        fn _svwhilele_b32_u32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilele_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b64_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv2i1.i32"
+        )]
+        fn _svwhilele_b64_u32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilele_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b8_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv16i1.i64"
+        )]
+        fn _svwhilele_b8_u64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilele_b8_u64(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b16_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv8i1.i64"
+        )]
+        fn _svwhilele_b16_u64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilele_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b32_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv4i1.i64"
+        )]
+        fn _svwhilele_b32_u64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilele_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilels))]
+pub fn svwhilele_b64_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilels.nxv2i1.i64"
+        )]
+        fn _svwhilele_b64_u64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilele_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i32"
+        )]
+        fn _svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilelt_b8_s32(op1, op2) }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i32"
+        )]
+        fn _svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilelt_b16_s32(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i32"
+        )]
+        fn _svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilelt_b32_s32(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i32"
+        )]
+        fn _svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilelt_b64_s32(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i64"
+        )]
+        fn _svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilelt_b8_s64(op1, op2) }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i64"
+        )]
+        fn _svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilelt_b16_s64(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i64"
+        )]
+        fn _svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilelt_b32_s64(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelt))]
+pub fn svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i64"
+        )]
+        fn _svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilelt_b64_s64(op1, op2).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b8_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i32"
+        )]
+        fn _svwhilelt_b8_u32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilelt_b8_u32(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b16_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i32"
+        )]
+        fn _svwhilelt_b16_u32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilelt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b32_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i32"
+        )]
+        fn _svwhilelt_b32_u32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilelt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b64_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i32"
+        )]
+        fn _svwhilelt_b64_u32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilelt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b8_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i64"
+        )]
+        fn _svwhilelt_b8_u64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilelt_b8_u64(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b16_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i64"
+        )]
+        fn _svwhilelt_b16_u64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilelt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b32_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i64"
+        )]
+        fn _svwhilelt_b32_u64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilelt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While incrementing scalar is less than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilelo))]
+pub fn svwhilelt_b64_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i64"
+        )]
+        fn _svwhilelt_b64_u64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilelt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "Write to the first-fault register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwrffr)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(wrffr))]
+pub fn svwrffr(op: svbool_t) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.wrffr")]
+        fn _svwrffr(op: svbool_t);
+    }
+    unsafe { _svwrffr(op) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i1")]
+        fn _svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svzip1_b8(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i1")]
+        fn _svzip1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svzip1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i1")]
+        fn _svzip1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svzip1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i1")]
+        fn _svzip1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svzip1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4f32")]
+        fn _svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svzip1_f32(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2f64")]
+        fn _svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svzip1_f64(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i8")]
+        fn _svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svzip1_s8(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i16")]
+        fn _svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svzip1_s16(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i32")]
+        fn _svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svzip1_s32(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i64")]
+        fn _svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svzip1_s64(op1, op2) }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svzip1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svzip1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svzip1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svzip1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4f32")]
+        fn _svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svzip1q_f32(op1, op2) }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2f64")]
+        fn _svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svzip1q_f64(op1, op2) }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv16i8")]
+        fn _svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svzip1q_s8(op1, op2) }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv8i16")]
+        fn _svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svzip1q_s16(op1, op2) }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4i32")]
+        fn _svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svzip1q_s32(op1, op2) }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2i64")]
+        fn _svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svzip1q_s64(op1, op2) }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svzip1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svzip1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svzip1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from low halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip1))]
+pub fn svzip1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svzip1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b8)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i1")]
+        fn _svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svzip2_b8(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b16)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i1")]
+        fn _svzip2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+    }
+    unsafe { _svzip2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b32)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i1")]
+        fn _svzip2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+    }
+    unsafe { _svzip2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b64)"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i1")]
+        fn _svzip2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+    }
+    unsafe { _svzip2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4f32")]
+        fn _svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svzip2_f32(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2f64")]
+        fn _svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svzip2_f64(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i8")]
+        fn _svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svzip2_s8(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i16")]
+        fn _svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svzip2_s16(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i32")]
+        fn _svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svzip2_s32(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i64")]
+        fn _svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svzip2_s64(op1, op2) }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svzip2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svzip2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svzip2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave elements from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svzip2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4f32")]
+        fn _svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svzip2q_f32(op1, op2) }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2f64")]
+        fn _svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svzip2q_f64(op1, op2) }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv16i8")]
+        fn _svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svzip2q_s8(op1, op2) }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv8i16")]
+        fn _svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svzip2q_s16(op1, op2) }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4i32")]
+        fn _svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svzip2q_s32(op1, op2) }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2i64")]
+        fn _svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svzip2q_s64(op1, op2) }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svzip2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svzip2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svzip2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleave quadwords from high halves of two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,f64mm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(zip2))]
+pub fn svzip2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svzip2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
diff --git a/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs b/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
new file mode 100644
index 0000000000..973b7e9fa3
--- /dev/null
+++ b/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
@@ -0,0 +1,9345 @@
+// This code is automatically generated. DO NOT MODIFY.
+//
+// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate
+// this file:
+//
+// ```
+// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
+// ```
+#![allow(unused)]
+use super::*;
+use std::boxed::Box;
+use std::convert::{TryFrom, TryInto};
+use std::sync::LazyLock;
+use std::vec::Vec;
+use stdarch_test::simd_test;
+static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as f32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("f32 data incorrectly initialised")
+});
+static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| {
+    (0..32 * 5)
+        .map(|i| i as f64)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("f64 data incorrectly initialised")
+});
+static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| {
+    (0..256 * 5)
+        .map(|i| ((i + 128) % 256 - 128) as i8)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i8 data incorrectly initialised")
+});
+static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| {
+    (0..128 * 5)
+        .map(|i| i as i16)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i16 data incorrectly initialised")
+});
+static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as i32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i32 data incorrectly initialised")
+});
+static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| {
+    (0..32 * 5)
+        .map(|i| i as i64)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i64 data incorrectly initialised")
+});
+static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| {
+    (0..256 * 5)
+        .map(|i| i as u8)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u8 data incorrectly initialised")
+});
+static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| {
+    (0..128 * 5)
+        .map(|i| i as u16)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u16 data incorrectly initialised")
+});
+static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as u32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u32 data incorrectly initialised")
+});
+static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| {
+    (0..32 * 5)
+        .map(|i| i as u64)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u64 data incorrectly initialised")
+});
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_f32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b64(), defined));
+    let cmp = svcmpne_f64(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b8(), defined));
+    let cmp = svcmpne_s8(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b16(), defined));
+    let cmp = svcmpne_s16(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_s32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b64(), defined));
+    let cmp = svcmpne_s64(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b8(), defined));
+    let cmp = svcmpne_u8(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b16(), defined));
+    let cmp = svcmpne_u16(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_u32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b64(), defined));
+    let cmp = svcmpne_u64(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_f32_with_svst1_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    svst1_f32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_f32(svptrue_b32(), storage.as_ptr() as *const f32);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_f64_with_svst1_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    svst1_f64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_f64(svptrue_b64(), storage.as_ptr() as *const f64);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_s8_with_svst1_s8() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_s8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1_s8(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_s16_with_svst1_s16() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_s16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1_s16(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_s32_with_svst1_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_s32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_s32(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_s64_with_svst1_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_s64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_s64(svptrue_b64(), storage.as_ptr() as *const i64);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_u8_with_svst1_u8() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_u8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1_u8(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_u16_with_svst1_u16() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_u16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1_u16(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_u32_with_svst1_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_u32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_u32(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_u64_with_svst1_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1_u64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_u64(svptrue_b64(), storage.as_ptr() as *const u64);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s32index_f32_with_svst1_scatter_s32index_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let indices = svindex_s32(0, 1);
+    svst1_scatter_s32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s32index_s32_with_svst1_scatter_s32index_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s32(0, 1);
+    svst1_scatter_s32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s32index_u32_with_svst1_scatter_s32index_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s32(0, 1);
+    svst1_scatter_s32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s64index_f64_with_svst1_scatter_s64index_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let indices = svindex_s64(0, 1);
+    svst1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s64index_s64_with_svst1_scatter_s64index_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s64index_u64_with_svst1_scatter_s64index_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32index_f32_with_svst1_scatter_u32index_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let indices = svindex_u32(0, 1);
+    svst1_scatter_u32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32index_s32_with_svst1_scatter_u32index_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u32(0, 1);
+    svst1_scatter_u32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32index_u32_with_svst1_scatter_u32index_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u32(0, 1);
+    svst1_scatter_u32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64index_f64_with_svst1_scatter_u64index_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let indices = svindex_u64(0, 1);
+    svst1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64index_s64_with_svst1_scatter_u64index_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64index_u64_with_svst1_scatter_u64index_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s32offset_f32_with_svst1_scatter_s32offset_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
+    svst1_scatter_s32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s32offset_s32_with_svst1_scatter_s32offset_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
+    svst1_scatter_s32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s32offset_u32_with_svst1_scatter_s32offset_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
+    svst1_scatter_s32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s64offset_f64_with_svst1_scatter_s64offset_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svst1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s64offset_s64_with_svst1_scatter_s64offset_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svst1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_s64offset_u64_with_svst1_scatter_s64offset_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svst1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32offset_f32_with_svst1_scatter_u32offset_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32offset_s32_with_svst1_scatter_u32offset_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32offset_u32_with_svst1_scatter_u32offset_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64offset_f64_with_svst1_scatter_u64offset_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svst1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64offset_s64_with_svst1_scatter_u64offset_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svst1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64offset_u64_with_svst1_scatter_u64offset_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svst1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_f64_with_svst1_scatter_u64base_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_f64(svptrue_b64(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_f64(svptrue_b64(), bases);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_s64_with_svst1_scatter_u64base_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_s64(svptrue_b64(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_s64(svptrue_b64(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_u64_with_svst1_scatter_u64base_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_u64(svptrue_b64(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_u64(svptrue_b64(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32base_index_f32_with_svst1_scatter_u32base_index_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32base_index_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32base_index_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32base_index_s32_with_svst1_scatter_u32base_index_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32base_index_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32base_index_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32base_index_u32_with_svst1_scatter_u32base_index_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32base_index_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32base_index_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_index_f64_with_svst1_scatter_u64base_index_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_index_s64_with_svst1_scatter_u64base_index_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_index_u64_with_svst1_scatter_u64base_index_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32base_offset_f32_with_svst1_scatter_u32base_offset_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32base_offset_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32base_offset_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32base_offset_s32_with_svst1_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32base_offset_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32base_offset_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u32base_offset_u32_with_svst1_scatter_u32base_offset_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svst1_scatter_u32base_offset_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u32base_offset_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_offset_f64_with_svst1_scatter_u64base_offset_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_offset_s64_with_svst1_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_gather_u64base_offset_u64_with_svst1_scatter_u64base_offset_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svst1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_f32_with_svst1_vnum_f32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+    svst1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_f64_with_svst1_vnum_f64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+    svst1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_s8_with_svst1_vnum_s8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s8(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_s16_with_svst1_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_s32_with_svst1_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_s64_with_svst1_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_u8_with_svst1_vnum_u8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u8(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_u16_with_svst1_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_u32_with_svst1_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1_vnum_u64_with_svst1_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_f32() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_f32 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_f32(svptrue_b32(), F32_DATA.as_ptr());
+    assert_vector_matches_f32(
+        loaded,
+        svtrn1q_f32(
+            svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32),
+            svdupq_n_f32(4usize as f32, 5usize as f32, 6usize as f32, 7usize as f32),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_f64() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_f64 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_f64(svptrue_b64(), F64_DATA.as_ptr());
+    assert_vector_matches_f64(
+        loaded,
+        svtrn1q_f64(
+            svdupq_n_f64(0usize as f64, 1usize as f64),
+            svdupq_n_f64(2usize as f64, 3usize as f64),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_s8() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_s8 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_s8(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i8(
+        loaded,
+        svtrn1q_s8(
+            svdupq_n_s8(
+                0usize as i8,
+                1usize as i8,
+                2usize as i8,
+                3usize as i8,
+                4usize as i8,
+                5usize as i8,
+                6usize as i8,
+                7usize as i8,
+                8usize as i8,
+                9usize as i8,
+                10usize as i8,
+                11usize as i8,
+                12usize as i8,
+                13usize as i8,
+                14usize as i8,
+                15usize as i8,
+            ),
+            svdupq_n_s8(
+                16usize as i8,
+                17usize as i8,
+                18usize as i8,
+                19usize as i8,
+                20usize as i8,
+                21usize as i8,
+                22usize as i8,
+                23usize as i8,
+                24usize as i8,
+                25usize as i8,
+                26usize as i8,
+                27usize as i8,
+                28usize as i8,
+                29usize as i8,
+                30usize as i8,
+                31usize as i8,
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_s16() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_s16 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_s16(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svtrn1q_s16(
+            svdupq_n_s16(
+                0usize as i16,
+                1usize as i16,
+                2usize as i16,
+                3usize as i16,
+                4usize as i16,
+                5usize as i16,
+                6usize as i16,
+                7usize as i16,
+            ),
+            svdupq_n_s16(
+                8usize as i16,
+                9usize as i16,
+                10usize as i16,
+                11usize as i16,
+                12usize as i16,
+                13usize as i16,
+                14usize as i16,
+                15usize as i16,
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_s32() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_s32 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_s32(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svtrn1q_s32(
+            svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32),
+            svdupq_n_s32(4usize as i32, 5usize as i32, 6usize as i32, 7usize as i32),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_s64() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_s64 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_s64(svptrue_b64(), I64_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svtrn1q_s64(
+            svdupq_n_s64(0usize as i64, 1usize as i64),
+            svdupq_n_s64(2usize as i64, 3usize as i64),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_u8() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_u8 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_u8(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u8(
+        loaded,
+        svtrn1q_u8(
+            svdupq_n_u8(
+                0usize as u8,
+                1usize as u8,
+                2usize as u8,
+                3usize as u8,
+                4usize as u8,
+                5usize as u8,
+                6usize as u8,
+                7usize as u8,
+                8usize as u8,
+                9usize as u8,
+                10usize as u8,
+                11usize as u8,
+                12usize as u8,
+                13usize as u8,
+                14usize as u8,
+                15usize as u8,
+            ),
+            svdupq_n_u8(
+                16usize as u8,
+                17usize as u8,
+                18usize as u8,
+                19usize as u8,
+                20usize as u8,
+                21usize as u8,
+                22usize as u8,
+                23usize as u8,
+                24usize as u8,
+                25usize as u8,
+                26usize as u8,
+                27usize as u8,
+                28usize as u8,
+                29usize as u8,
+                30usize as u8,
+                31usize as u8,
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_u16() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_u16 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_u16(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svtrn1q_u16(
+            svdupq_n_u16(
+                0usize as u16,
+                1usize as u16,
+                2usize as u16,
+                3usize as u16,
+                4usize as u16,
+                5usize as u16,
+                6usize as u16,
+                7usize as u16,
+            ),
+            svdupq_n_u16(
+                8usize as u16,
+                9usize as u16,
+                10usize as u16,
+                11usize as u16,
+                12usize as u16,
+                13usize as u16,
+                14usize as u16,
+                15usize as u16,
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_u32() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_u32 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_u32(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svtrn1q_u32(
+            svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32),
+            svdupq_n_u32(4usize as u32, 5usize as u32, 6usize as u32, 7usize as u32),
+        ),
+    );
+}
+#[simd_test(enable = "sve,f64mm")]
+unsafe fn test_svld1ro_u64() {
+    if svcntb() < 32 {
+        println!("Skipping test_svld1ro_u64 due to SVE vector length");
+        return;
+    }
+    svsetffr();
+    let loaded = svld1ro_u64(svptrue_b64(), U64_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svtrn1q_u64(
+            svdupq_n_u64(0usize as u64, 1usize as u64),
+            svdupq_n_u64(2usize as u64, 3usize as u64),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_f32() {
+    svsetffr();
+    let loaded = svld1rq_f32(svptrue_b32(), F32_DATA.as_ptr());
+    assert_vector_matches_f32(
+        loaded,
+        svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_f64() {
+    svsetffr();
+    let loaded = svld1rq_f64(svptrue_b64(), F64_DATA.as_ptr());
+    assert_vector_matches_f64(loaded, svdupq_n_f64(0usize as f64, 1usize as f64));
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_s8() {
+    svsetffr();
+    let loaded = svld1rq_s8(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i8(
+        loaded,
+        svdupq_n_s8(
+            0usize as i8,
+            1usize as i8,
+            2usize as i8,
+            3usize as i8,
+            4usize as i8,
+            5usize as i8,
+            6usize as i8,
+            7usize as i8,
+            8usize as i8,
+            9usize as i8,
+            10usize as i8,
+            11usize as i8,
+            12usize as i8,
+            13usize as i8,
+            14usize as i8,
+            15usize as i8,
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_s16() {
+    svsetffr();
+    let loaded = svld1rq_s16(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svdupq_n_s16(
+            0usize as i16,
+            1usize as i16,
+            2usize as i16,
+            3usize as i16,
+            4usize as i16,
+            5usize as i16,
+            6usize as i16,
+            7usize as i16,
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_s32() {
+    svsetffr();
+    let loaded = svld1rq_s32(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_s64() {
+    svsetffr();
+    let loaded = svld1rq_s64(svptrue_b64(), I64_DATA.as_ptr());
+    assert_vector_matches_i64(loaded, svdupq_n_s64(0usize as i64, 1usize as i64));
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_u8() {
+    svsetffr();
+    let loaded = svld1rq_u8(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u8(
+        loaded,
+        svdupq_n_u8(
+            0usize as u8,
+            1usize as u8,
+            2usize as u8,
+            3usize as u8,
+            4usize as u8,
+            5usize as u8,
+            6usize as u8,
+            7usize as u8,
+            8usize as u8,
+            9usize as u8,
+            10usize as u8,
+            11usize as u8,
+            12usize as u8,
+            13usize as u8,
+            14usize as u8,
+            15usize as u8,
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_u16() {
+    svsetffr();
+    let loaded = svld1rq_u16(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svdupq_n_u16(
+            0usize as u16,
+            1usize as u16,
+            2usize as u16,
+            3usize as u16,
+            4usize as u16,
+            5usize as u16,
+            6usize as u16,
+            7usize as u16,
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_u32() {
+    svsetffr();
+    let loaded = svld1rq_u32(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1rq_u64() {
+    svsetffr();
+    let loaded = svld1rq_u64(svptrue_b64(), U64_DATA.as_ptr());
+    assert_vector_matches_u64(loaded, svdupq_n_u64(0usize as u64, 1usize as u64));
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u64base_s64_with_svst1b_scatter_u64base_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_s64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u64base_s64(svptrue_b8(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_s64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u64base_s64(svptrue_b16(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_s64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_gather_u64base_s64(svptrue_b32(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_gather_u64base_u64_with_svst1b_scatter_u64base_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_u64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_gather_u64base_u64(svptrue_b8(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_u64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u64base_u64(svptrue_b16(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_u64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_gather_u64base_u64(svptrue_b32(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_s16_with_svst1b_s16() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_s16(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_s32_with_svst1b_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_s32(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_s32_with_svst1h_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_s32(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_s64_with_svst1b_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_s64(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_s64_with_svst1h_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_s64(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_s64_with_svst1w_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_s64(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_u16_with_svst1b_u16() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_u16(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_u32_with_svst1b_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_u32(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_u32_with_svst1h_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1sh_u32(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_u64_with_svst1b_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_u64(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_u64_with_svst1h_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1sh_u64(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_u64_with_svst1w_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1sw_u64(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_vnum_s16_with_svst1b_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_vnum_s16(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_vnum_s32_with_svst1b_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_vnum_s32(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_vnum_s32_with_svst1h_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_vnum_s64_with_svst1b_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1sb_vnum_s64(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_vnum_s64_with_svst1h_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_vnum_s64_with_svst1w_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_vnum_u16_with_svst1b_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_vnum_u16(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_vnum_u32_with_svst1b_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_vnum_u32(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_vnum_u32_with_svst1h_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1sh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sb_vnum_u64_with_svst1b_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1sb_vnum_u64(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_vnum_u64_with_svst1h_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1sh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_vnum_u64_with_svst1w_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1sw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s32(0, 1);
+    svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s32(0, 1);
+    svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u32(0, 1);
+    svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u32(0, 1);
+    svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1sw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svst1b_scatter_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u64base_s64_with_svst1b_scatter_u64base_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_s64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u64base_s64(svptrue_b8(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_s64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u64base_s64(svptrue_b16(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_s64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_gather_u64base_s64(svptrue_b32(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_gather_u64base_u64_with_svst1b_scatter_u64base_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svst1b_scatter_u64base_u64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_gather_u64base_u64(svptrue_b8(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_u64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u64base_u64(svptrue_b16(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_u64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_gather_u64base_u64(svptrue_b32(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_s16_with_svst1b_s16() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_s16(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_s32_with_svst1b_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_s32(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_s32_with_svst1h_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_s32(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_s64_with_svst1b_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_s64(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_s64_with_svst1h_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_s64(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_s64_with_svst1w_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_s64(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_u16_with_svst1b_u16() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_u16(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_u32_with_svst1b_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_u32(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_u32_with_svst1h_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1uh_u32(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_u64_with_svst1b_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_u64(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_u64_with_svst1h_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1uh_u64(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_u64_with_svst1w_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1uw_u64(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_vnum_s16_with_svst1b_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_vnum_s16(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_vnum_s32_with_svst1b_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_vnum_s32(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_vnum_s32_with_svst1h_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_vnum_s64_with_svst1b_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld1ub_vnum_s64(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_vnum_s64_with_svst1h_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_vnum_s64_with_svst1w_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_vnum_u16_with_svst1b_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_vnum_u16(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_vnum_u32_with_svst1b_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_vnum_u32(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_vnum_u32_with_svst1h_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1uh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1ub_vnum_u64_with_svst1b_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld1ub_vnum_u64(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_vnum_u64_with_svst1h_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld1uh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_vnum_u64_with_svst1w_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld1uw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s32(0, 1);
+    svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s32(0, 1);
+    svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u32(0, 1);
+    svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u32(0, 1);
+    svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svld1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svld1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svst1h_scatter_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld1uw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_f32_with_svst2_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcreate2_f32(
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+    );
+    svst2_f32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld2_f32(svptrue_b32(), storage.as_ptr() as *const f32);
+    assert_vector_matches_f32(
+        svget2_f32::<{ 0usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget2_f32::<{ 1usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_f64_with_svst2_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcreate2_f64(
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+    );
+    svst2_f64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld2_f64(svptrue_b64(), storage.as_ptr() as *const f64);
+    assert_vector_matches_f64(
+        svget2_f64::<{ 0usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget2_f64::<{ 1usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_s8_with_svst2_s8() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svcreate2_s8(
+        svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_s8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld2_s8(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i8(
+        svget2_s8::<{ 0usize as i32 }>(loaded),
+        svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i8(
+        svget2_s8::<{ 1usize as i32 }>(loaded),
+        svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_s16_with_svst2_s16() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svcreate2_s16(
+        svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_s16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld2_s16(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i16(
+        svget2_s16::<{ 0usize as i32 }>(loaded),
+        svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i16(
+        svget2_s16::<{ 1usize as i32 }>(loaded),
+        svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_s32_with_svst2_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svcreate2_s32(
+        svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_s32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld2_s32(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_i32(
+        svget2_s32::<{ 0usize as i32 }>(loaded),
+        svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i32(
+        svget2_s32::<{ 1usize as i32 }>(loaded),
+        svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_s64_with_svst2_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svcreate2_s64(
+        svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_s64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld2_s64(svptrue_b64(), storage.as_ptr() as *const i64);
+    assert_vector_matches_i64(
+        svget2_s64::<{ 0usize as i32 }>(loaded),
+        svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i64(
+        svget2_s64::<{ 1usize as i32 }>(loaded),
+        svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_u8_with_svst2_u8() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svcreate2_u8(
+        svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_u8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld2_u8(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u8(
+        svget2_u8::<{ 0usize as i32 }>(loaded),
+        svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u8(
+        svget2_u8::<{ 1usize as i32 }>(loaded),
+        svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_u16_with_svst2_u16() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svcreate2_u16(
+        svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_u16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld2_u16(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u16(
+        svget2_u16::<{ 0usize as i32 }>(loaded),
+        svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u16(
+        svget2_u16::<{ 1usize as i32 }>(loaded),
+        svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_u32_with_svst2_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svcreate2_u32(
+        svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_u32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld2_u32(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_u32(
+        svget2_u32::<{ 0usize as i32 }>(loaded),
+        svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u32(
+        svget2_u32::<{ 1usize as i32 }>(loaded),
+        svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_u64_with_svst2_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svcreate2_u64(
+        svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+        svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    svst2_u64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld2_u64(svptrue_b64(), storage.as_ptr() as *const u64);
+    assert_vector_matches_u64(
+        svget2_u64::<{ 0usize as i32 }>(loaded),
+        svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u64(
+        svget2_u64::<{ 1usize as i32 }>(loaded),
+        svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_f32_with_svst2_vnum_f32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as f32; 320usize];
+    let data = svcreate2_f32(
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 1usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    svst2_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1);
+    assert_vector_matches_f32(
+        svget2_f32::<{ 0usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget2_f32::<{ 1usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 1usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_f64_with_svst2_vnum_f64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as f64; 160usize];
+    let data = svcreate2_f64(
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 1usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    svst2_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1);
+    assert_vector_matches_f64(
+        svget2_f64::<{ 0usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget2_f64::<{ 1usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 1usize).try_into().unwrap(),
+                2usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_s8_with_svst2_vnum_s8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svcreate2_s8(
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_s8(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i8(
+        svget2_s8::<{ 0usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i8(
+        svget2_s8::<{ 1usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_s16_with_svst2_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svcreate2_s16(
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_s16(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i16(
+        svget2_s16::<{ 0usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i16(
+        svget2_s16::<{ 1usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_s32_with_svst2_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svcreate2_s32(
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_s32(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_i32(
+        svget2_s32::<{ 0usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i32(
+        svget2_s32::<{ 1usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_s64_with_svst2_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i64; 160usize];
+    let data = svcreate2_s64(
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_s64(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1);
+    assert_vector_matches_i64(
+        svget2_s64::<{ 0usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i64(
+        svget2_s64::<{ 1usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_u8_with_svst2_vnum_u8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svcreate2_u8(
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_u8(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u8(
+        svget2_u8::<{ 0usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u8(
+        svget2_u8::<{ 1usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_u16_with_svst2_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svcreate2_u16(
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_u16(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u16(
+        svget2_u16::<{ 0usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u16(
+        svget2_u16::<{ 1usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_u32_with_svst2_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svcreate2_u32(
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_u32(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_u32(
+        svget2_u32::<{ 0usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u32(
+        svget2_u32::<{ 1usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld2_vnum_u64_with_svst2_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u64; 160usize];
+    let data = svcreate2_u64(
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+        svindex_u64(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    svst2_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld2_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1);
+    assert_vector_matches_u64(
+        svget2_u64::<{ 0usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u64(
+        svget2_u64::<{ 1usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 1usize).try_into().unwrap(),
+            2usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_f32_with_svst3_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcreate3_f32(
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+    svst3_f32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld3_f32(svptrue_b32(), storage.as_ptr() as *const f32);
+    assert_vector_matches_f32(
+        svget3_f32::<{ 0usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget3_f32::<{ 1usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget3_f32::<{ 2usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_f64_with_svst3_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcreate3_f64(
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+    svst3_f64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld3_f64(svptrue_b64(), storage.as_ptr() as *const f64);
+    assert_vector_matches_f64(
+        svget3_f64::<{ 0usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget3_f64::<{ 1usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget3_f64::<{ 2usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_s8_with_svst3_s8() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svcreate3_s8(
+        svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_s8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld3_s8(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i8(
+        svget3_s8::<{ 0usize as i32 }>(loaded),
+        svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i8(
+        svget3_s8::<{ 1usize as i32 }>(loaded),
+        svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i8(
+        svget3_s8::<{ 2usize as i32 }>(loaded),
+        svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_s16_with_svst3_s16() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svcreate3_s16(
+        svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_s16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld3_s16(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i16(
+        svget3_s16::<{ 0usize as i32 }>(loaded),
+        svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i16(
+        svget3_s16::<{ 1usize as i32 }>(loaded),
+        svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i16(
+        svget3_s16::<{ 2usize as i32 }>(loaded),
+        svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_s32_with_svst3_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svcreate3_s32(
+        svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_s32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld3_s32(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_i32(
+        svget3_s32::<{ 0usize as i32 }>(loaded),
+        svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i32(
+        svget3_s32::<{ 1usize as i32 }>(loaded),
+        svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i32(
+        svget3_s32::<{ 2usize as i32 }>(loaded),
+        svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_s64_with_svst3_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svcreate3_s64(
+        svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_s64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld3_s64(svptrue_b64(), storage.as_ptr() as *const i64);
+    assert_vector_matches_i64(
+        svget3_s64::<{ 0usize as i32 }>(loaded),
+        svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i64(
+        svget3_s64::<{ 1usize as i32 }>(loaded),
+        svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i64(
+        svget3_s64::<{ 2usize as i32 }>(loaded),
+        svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_u8_with_svst3_u8() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svcreate3_u8(
+        svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_u8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld3_u8(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u8(
+        svget3_u8::<{ 0usize as i32 }>(loaded),
+        svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u8(
+        svget3_u8::<{ 1usize as i32 }>(loaded),
+        svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u8(
+        svget3_u8::<{ 2usize as i32 }>(loaded),
+        svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_u16_with_svst3_u16() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svcreate3_u16(
+        svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_u16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld3_u16(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u16(
+        svget3_u16::<{ 0usize as i32 }>(loaded),
+        svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u16(
+        svget3_u16::<{ 1usize as i32 }>(loaded),
+        svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u16(
+        svget3_u16::<{ 2usize as i32 }>(loaded),
+        svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_u32_with_svst3_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svcreate3_u32(
+        svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_u32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld3_u32(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_u32(
+        svget3_u32::<{ 0usize as i32 }>(loaded),
+        svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u32(
+        svget3_u32::<{ 1usize as i32 }>(loaded),
+        svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u32(
+        svget3_u32::<{ 2usize as i32 }>(loaded),
+        svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_u64_with_svst3_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svcreate3_u64(
+        svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+        svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    svst3_u64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld3_u64(svptrue_b64(), storage.as_ptr() as *const u64);
+    assert_vector_matches_u64(
+        svget3_u64::<{ 0usize as i32 }>(loaded),
+        svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u64(
+        svget3_u64::<{ 1usize as i32 }>(loaded),
+        svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u64(
+        svget3_u64::<{ 2usize as i32 }>(loaded),
+        svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_f32_with_svst3_vnum_f32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as f32; 320usize];
+    let data = svcreate3_f32(
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 1usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 2usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    svst3_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1);
+    assert_vector_matches_f32(
+        svget3_f32::<{ 0usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget3_f32::<{ 1usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 1usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget3_f32::<{ 2usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 2usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_f64_with_svst3_vnum_f64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as f64; 160usize];
+    let data = svcreate3_f64(
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 1usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 2usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    svst3_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1);
+    assert_vector_matches_f64(
+        svget3_f64::<{ 0usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget3_f64::<{ 1usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 1usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget3_f64::<{ 2usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 2usize).try_into().unwrap(),
+                3usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_s8_with_svst3_vnum_s8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svcreate3_s8(
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s8(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s8(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i8(
+        svget3_s8::<{ 0usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i8(
+        svget3_s8::<{ 1usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i8(
+        svget3_s8::<{ 2usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_s16_with_svst3_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svcreate3_s16(
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s16(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s16(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i16(
+        svget3_s16::<{ 0usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i16(
+        svget3_s16::<{ 1usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i16(
+        svget3_s16::<{ 2usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_s32_with_svst3_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svcreate3_s32(
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s32(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s32(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_i32(
+        svget3_s32::<{ 0usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i32(
+        svget3_s32::<{ 1usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i32(
+        svget3_s32::<{ 2usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_s64_with_svst3_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i64; 160usize];
+    let data = svcreate3_s64(
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s64(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_s64(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1);
+    assert_vector_matches_i64(
+        svget3_s64::<{ 0usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i64(
+        svget3_s64::<{ 1usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i64(
+        svget3_s64::<{ 2usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_u8_with_svst3_vnum_u8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svcreate3_u8(
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u8(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u8(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u8(
+        svget3_u8::<{ 0usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u8(
+        svget3_u8::<{ 1usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u8(
+        svget3_u8::<{ 2usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_u16_with_svst3_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svcreate3_u16(
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u16(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u16(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u16(
+        svget3_u16::<{ 0usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u16(
+        svget3_u16::<{ 1usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u16(
+        svget3_u16::<{ 2usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_u32_with_svst3_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svcreate3_u32(
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u32(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u32(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_u32(
+        svget3_u32::<{ 0usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u32(
+        svget3_u32::<{ 1usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u32(
+        svget3_u32::<{ 2usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld3_vnum_u64_with_svst3_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u64; 160usize];
+    let data = svcreate3_u64(
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u64(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+        svindex_u64(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    svst3_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld3_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1);
+    assert_vector_matches_u64(
+        svget3_u64::<{ 0usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u64(
+        svget3_u64::<{ 1usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 1usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u64(
+        svget3_u64::<{ 2usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 2usize).try_into().unwrap(),
+            3usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_f32_with_svst4_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcreate4_f32(
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    svst4_f32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld4_f32(svptrue_b32(), storage.as_ptr() as *const f32);
+    assert_vector_matches_f32(
+        svget4_f32::<{ 0usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget4_f32::<{ 1usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget4_f32::<{ 2usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget4_f32::<{ 3usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_f64_with_svst4_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcreate4_f64(
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    svst4_f64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld4_f64(svptrue_b64(), storage.as_ptr() as *const f64);
+    assert_vector_matches_f64(
+        svget4_f64::<{ 0usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget4_f64::<{ 1usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget4_f64::<{ 2usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget4_f64::<{ 3usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_s8_with_svst4_s8() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svcreate4_s8(
+        svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_s8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld4_s8(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i8(
+        svget4_s8::<{ 0usize as i32 }>(loaded),
+        svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i8(
+        svget4_s8::<{ 1usize as i32 }>(loaded),
+        svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i8(
+        svget4_s8::<{ 2usize as i32 }>(loaded),
+        svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i8(
+        svget4_s8::<{ 3usize as i32 }>(loaded),
+        svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_s16_with_svst4_s16() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svcreate4_s16(
+        svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_s16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld4_s16(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i16(
+        svget4_s16::<{ 0usize as i32 }>(loaded),
+        svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i16(
+        svget4_s16::<{ 1usize as i32 }>(loaded),
+        svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i16(
+        svget4_s16::<{ 2usize as i32 }>(loaded),
+        svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i16(
+        svget4_s16::<{ 3usize as i32 }>(loaded),
+        svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_s32_with_svst4_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svcreate4_s32(
+        svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_s32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld4_s32(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_i32(
+        svget4_s32::<{ 0usize as i32 }>(loaded),
+        svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i32(
+        svget4_s32::<{ 1usize as i32 }>(loaded),
+        svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i32(
+        svget4_s32::<{ 2usize as i32 }>(loaded),
+        svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i32(
+        svget4_s32::<{ 3usize as i32 }>(loaded),
+        svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_s64_with_svst4_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svcreate4_s64(
+        svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_s64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld4_s64(svptrue_b64(), storage.as_ptr() as *const i64);
+    assert_vector_matches_i64(
+        svget4_s64::<{ 0usize as i32 }>(loaded),
+        svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i64(
+        svget4_s64::<{ 1usize as i32 }>(loaded),
+        svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i64(
+        svget4_s64::<{ 2usize as i32 }>(loaded),
+        svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_i64(
+        svget4_s64::<{ 3usize as i32 }>(loaded),
+        svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_u8_with_svst4_u8() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svcreate4_u8(
+        svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_u8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld4_u8(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u8(
+        svget4_u8::<{ 0usize as i32 }>(loaded),
+        svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u8(
+        svget4_u8::<{ 1usize as i32 }>(loaded),
+        svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u8(
+        svget4_u8::<{ 2usize as i32 }>(loaded),
+        svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u8(
+        svget4_u8::<{ 3usize as i32 }>(loaded),
+        svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_u16_with_svst4_u16() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svcreate4_u16(
+        svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_u16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld4_u16(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u16(
+        svget4_u16::<{ 0usize as i32 }>(loaded),
+        svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u16(
+        svget4_u16::<{ 1usize as i32 }>(loaded),
+        svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u16(
+        svget4_u16::<{ 2usize as i32 }>(loaded),
+        svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u16(
+        svget4_u16::<{ 3usize as i32 }>(loaded),
+        svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_u32_with_svst4_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svcreate4_u32(
+        svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_u32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld4_u32(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_u32(
+        svget4_u32::<{ 0usize as i32 }>(loaded),
+        svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u32(
+        svget4_u32::<{ 1usize as i32 }>(loaded),
+        svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u32(
+        svget4_u32::<{ 2usize as i32 }>(loaded),
+        svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u32(
+        svget4_u32::<{ 3usize as i32 }>(loaded),
+        svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_u64_with_svst4_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svcreate4_u64(
+        svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+        svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    svst4_u64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld4_u64(svptrue_b64(), storage.as_ptr() as *const u64);
+    assert_vector_matches_u64(
+        svget4_u64::<{ 0usize as i32 }>(loaded),
+        svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u64(
+        svget4_u64::<{ 1usize as i32 }>(loaded),
+        svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u64(
+        svget4_u64::<{ 2usize as i32 }>(loaded),
+        svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+    assert_vector_matches_u64(
+        svget4_u64::<{ 3usize as i32 }>(loaded),
+        svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_f32_with_svst4_vnum_f32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as f32; 320usize];
+    let data = svcreate4_f32(
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 1usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 2usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 3usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    svst4_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1);
+    assert_vector_matches_f32(
+        svget4_f32::<{ 0usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget4_f32::<{ 1usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 1usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget4_f32::<{ 2usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 2usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f32(
+        svget4_f32::<{ 3usize as i32 }>(loaded),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 3usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_f64_with_svst4_vnum_f64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as f64; 160usize];
+    let data = svcreate4_f64(
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 1usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 2usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 3usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    svst4_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1);
+    assert_vector_matches_f64(
+        svget4_f64::<{ 0usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget4_f64::<{ 1usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 1usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget4_f64::<{ 2usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 2usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+    assert_vector_matches_f64(
+        svget4_f64::<{ 3usize as i32 }>(loaded),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 3usize).try_into().unwrap(),
+                4usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_s8_with_svst4_vnum_s8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svcreate4_s8(
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s8(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s8(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s8(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i8(
+        svget4_s8::<{ 0usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i8(
+        svget4_s8::<{ 1usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i8(
+        svget4_s8::<{ 2usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i8(
+        svget4_s8::<{ 3usize as i32 }>(loaded),
+        svindex_s8(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_s16_with_svst4_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svcreate4_s16(
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s16(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s16(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s16(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i16(
+        svget4_s16::<{ 0usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i16(
+        svget4_s16::<{ 1usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i16(
+        svget4_s16::<{ 2usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i16(
+        svget4_s16::<{ 3usize as i32 }>(loaded),
+        svindex_s16(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_s32_with_svst4_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svcreate4_s32(
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s32(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s32(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s32(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_i32(
+        svget4_s32::<{ 0usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i32(
+        svget4_s32::<{ 1usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i32(
+        svget4_s32::<{ 2usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i32(
+        svget4_s32::<{ 3usize as i32 }>(loaded),
+        svindex_s32(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_s64_with_svst4_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i64; 160usize];
+    let data = svcreate4_s64(
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s64(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s64(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_s64(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1);
+    assert_vector_matches_i64(
+        svget4_s64::<{ 0usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i64(
+        svget4_s64::<{ 1usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i64(
+        svget4_s64::<{ 2usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_i64(
+        svget4_s64::<{ 3usize as i32 }>(loaded),
+        svindex_s64(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_u8_with_svst4_vnum_u8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svcreate4_u8(
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u8(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u8(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u8(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u8(
+        svget4_u8::<{ 0usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u8(
+        svget4_u8::<{ 1usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u8(
+        svget4_u8::<{ 2usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u8(
+        svget4_u8::<{ 3usize as i32 }>(loaded),
+        svindex_u8(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_u16_with_svst4_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svcreate4_u16(
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u16(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u16(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u16(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u16(
+        svget4_u16::<{ 0usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u16(
+        svget4_u16::<{ 1usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u16(
+        svget4_u16::<{ 2usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u16(
+        svget4_u16::<{ 3usize as i32 }>(loaded),
+        svindex_u16(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_u32_with_svst4_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svcreate4_u32(
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u32(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u32(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u32(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_u32(
+        svget4_u32::<{ 0usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u32(
+        svget4_u32::<{ 1usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u32(
+        svget4_u32::<{ 2usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u32(
+        svget4_u32::<{ 3usize as i32 }>(loaded),
+        svindex_u32(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svld4_vnum_u64_with_svst4_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u64; 160usize];
+    let data = svcreate4_u64(
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u64(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u64(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+        svindex_u64(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    svst4_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svld4_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1);
+    assert_vector_matches_u64(
+        svget4_u64::<{ 0usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u64(
+        svget4_u64::<{ 1usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 1usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u64(
+        svget4_u64::<{ 2usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 2usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+    assert_vector_matches_u64(
+        svget4_u64::<{ 3usize as i32 }>(loaded),
+        svindex_u64(
+            (len + 3usize).try_into().unwrap(),
+            4usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_f32() {
+    svsetffr();
+    let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr());
+    let loaded = svldff1_f32(svptrue_b32(), F32_DATA.as_ptr());
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_f64() {
+    svsetffr();
+    let _ = svld1_f64(svptrue_b64(), F64_DATA.as_ptr());
+    let loaded = svldff1_f64(svptrue_b64(), F64_DATA.as_ptr());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_s8() {
+    svsetffr();
+    let _ = svld1_s8(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1_s8(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_s16() {
+    svsetffr();
+    let _ = svld1_s16(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1_s16(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_s32() {
+    svsetffr();
+    let _ = svld1_s32(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldff1_s32(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_s64() {
+    svsetffr();
+    let _ = svld1_s64(svptrue_b64(), I64_DATA.as_ptr());
+    let loaded = svldff1_s64(svptrue_b64(), I64_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_u8() {
+    svsetffr();
+    let _ = svld1_u8(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1_u8(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_u16() {
+    svsetffr();
+    let _ = svld1_u16(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldff1_u16(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_u32() {
+    svsetffr();
+    let _ = svld1_u32(svptrue_b32(), U32_DATA.as_ptr());
+    let loaded = svldff1_u32(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_u64() {
+    svsetffr();
+    let _ = svld1_u64(svptrue_b64(), U64_DATA.as_ptr());
+    let loaded = svldff1_u64(svptrue_b64(), U64_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_f32() {
+    svsetffr();
+    let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_f64() {
+    svsetffr();
+    let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s8() {
+    svsetffr();
+    let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntb() as usize;
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s16() {
+    svsetffr();
+    let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s32() {
+    svsetffr();
+    let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s64() {
+    svsetffr();
+    let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u8() {
+    svsetffr();
+    let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntb() as usize;
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u16() {
+    svsetffr();
+    let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u32() {
+    svsetffr();
+    let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u64() {
+    svsetffr();
+    let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_s16() {
+    svsetffr();
+    let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_s32() {
+    svsetffr();
+    let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_s32() {
+    svsetffr();
+    let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_s64() {
+    svsetffr();
+    let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_s64() {
+    svsetffr();
+    let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_s64() {
+    svsetffr();
+    let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldff1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_u16() {
+    svsetffr();
+    let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_u32() {
+    svsetffr();
+    let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_u32() {
+    svsetffr();
+    let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_u64() {
+    svsetffr();
+    let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_u64() {
+    svsetffr();
+    let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_u64() {
+    svsetffr();
+    let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldff1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_s16() {
+    svsetffr();
+    let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_s32() {
+    svsetffr();
+    let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_s32() {
+    svsetffr();
+    let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_s64() {
+    svsetffr();
+    let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_s64() {
+    svsetffr();
+    let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_vnum_s64() {
+    svsetffr();
+    let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldff1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_u16() {
+    svsetffr();
+    let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_u32() {
+    svsetffr();
+    let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_u32() {
+    svsetffr();
+    let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_u64() {
+    svsetffr();
+    let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_u64() {
+    svsetffr();
+    let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_vnum_u64() {
+    svsetffr();
+    let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldff1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_s16() {
+    svsetffr();
+    let _ = svld1ub_s16(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1ub_s16(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_s32() {
+    svsetffr();
+    let _ = svld1ub_s32(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1ub_s32(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_s32() {
+    svsetffr();
+    let _ = svld1uh_s32(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldff1uh_s32(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_s64() {
+    svsetffr();
+    let _ = svld1ub_s64(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1ub_s64(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_s64() {
+    svsetffr();
+    let _ = svld1uh_s64(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldff1uh_s64(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_s64() {
+    svsetffr();
+    let _ = svld1uw_s64(svptrue_b32(), U32_DATA.as_ptr());
+    let loaded = svldff1uw_s64(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_u16() {
+    svsetffr();
+    let _ = svld1ub_u16(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1ub_u16(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_u32() {
+    svsetffr();
+    let _ = svld1ub_u32(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1ub_u32(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_u32() {
+    svsetffr();
+    let _ = svld1uh_u32(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldff1uh_u32(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_u64() {
+    svsetffr();
+    let _ = svld1ub_u64(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldff1ub_u64(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_u64() {
+    svsetffr();
+    let _ = svld1uh_u64(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldff1uh_u64(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_u64() {
+    svsetffr();
+    let _ = svld1uw_u64(svptrue_b32(), U32_DATA.as_ptr());
+    let loaded = svldff1uw_u64(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_vnum_s16() {
+    svsetffr();
+    let _ = svld1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_vnum_s32() {
+    svsetffr();
+    let _ = svld1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_vnum_s32() {
+    svsetffr();
+    let _ = svld1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldff1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_vnum_s64() {
+    svsetffr();
+    let _ = svld1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_vnum_s64() {
+    svsetffr();
+    let _ = svld1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldff1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_vnum_s64() {
+    svsetffr();
+    let _ = svld1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldff1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_vnum_u16() {
+    svsetffr();
+    let _ = svld1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_vnum_u32() {
+    svsetffr();
+    let _ = svld1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_vnum_u32() {
+    svsetffr();
+    let _ = svld1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldff1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_vnum_u64() {
+    svsetffr();
+    let _ = svld1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_vnum_u64() {
+    svsetffr();
+    let _ = svld1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldff1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_vnum_u64() {
+    svsetffr();
+    let _ = svld1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldff1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_f32() {
+    svsetffr();
+    let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr());
+    let loaded = svldnf1_f32(svptrue_b32(), F32_DATA.as_ptr());
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_f64() {
+    svsetffr();
+    let _ = svld1_f64(svptrue_b64(), F64_DATA.as_ptr());
+    let loaded = svldnf1_f64(svptrue_b64(), F64_DATA.as_ptr());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_s8() {
+    svsetffr();
+    let _ = svld1_s8(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1_s8(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_s16() {
+    svsetffr();
+    let _ = svld1_s16(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldnf1_s16(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_s32() {
+    svsetffr();
+    let _ = svld1_s32(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldnf1_s32(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_s64() {
+    svsetffr();
+    let _ = svld1_s64(svptrue_b64(), I64_DATA.as_ptr());
+    let loaded = svldnf1_s64(svptrue_b64(), I64_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_u8() {
+    svsetffr();
+    let _ = svld1_u8(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1_u8(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_u16() {
+    svsetffr();
+    let _ = svld1_u16(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldnf1_u16(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_u32() {
+    svsetffr();
+    let _ = svld1_u32(svptrue_b32(), U32_DATA.as_ptr());
+    let loaded = svldnf1_u32(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_u64() {
+    svsetffr();
+    let _ = svld1_u64(svptrue_b64(), U64_DATA.as_ptr());
+    let loaded = svldnf1_u64(svptrue_b64(), U64_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_f32() {
+    svsetffr();
+    let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_f64() {
+    svsetffr();
+    let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_s8() {
+    svsetffr();
+    let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntb() as usize;
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_s16() {
+    svsetffr();
+    let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_s32() {
+    svsetffr();
+    let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_s64() {
+    svsetffr();
+    let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_u8() {
+    svsetffr();
+    let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntb() as usize;
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_u16() {
+    svsetffr();
+    let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_u32() {
+    svsetffr();
+    let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1_vnum_u64() {
+    svsetffr();
+    let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
+    let loaded = svldnf1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_s16() {
+    svsetffr();
+    let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_s32() {
+    svsetffr();
+    let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_s32() {
+    svsetffr();
+    let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldnf1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_s64() {
+    svsetffr();
+    let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_s64() {
+    svsetffr();
+    let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldnf1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sw_s64() {
+    svsetffr();
+    let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldnf1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_u16() {
+    svsetffr();
+    let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_u32() {
+    svsetffr();
+    let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_u32() {
+    svsetffr();
+    let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldnf1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_u64() {
+    svsetffr();
+    let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldnf1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_u64() {
+    svsetffr();
+    let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldnf1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sw_u64() {
+    svsetffr();
+    let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldnf1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_vnum_s16() {
+    svsetffr();
+    let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_vnum_s32() {
+    svsetffr();
+    let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_vnum_s32() {
+    svsetffr();
+    let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldnf1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_vnum_s64() {
+    svsetffr();
+    let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_vnum_s64() {
+    svsetffr();
+    let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldnf1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sw_vnum_s64() {
+    svsetffr();
+    let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldnf1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_vnum_u16() {
+    svsetffr();
+    let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_vnum_u32() {
+    svsetffr();
+    let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_vnum_u32() {
+    svsetffr();
+    let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldnf1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sb_vnum_u64() {
+    svsetffr();
+    let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldnf1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sh_vnum_u64() {
+    svsetffr();
+    let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldnf1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1sw_vnum_u64() {
+    svsetffr();
+    let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldnf1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_s16() {
+    svsetffr();
+    let _ = svld1ub_s16(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1ub_s16(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_s32() {
+    svsetffr();
+    let _ = svld1ub_s32(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1ub_s32(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_s32() {
+    svsetffr();
+    let _ = svld1uh_s32(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldnf1uh_s32(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_s64() {
+    svsetffr();
+    let _ = svld1ub_s64(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1ub_s64(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_s64() {
+    svsetffr();
+    let _ = svld1uh_s64(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldnf1uh_s64(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uw_s64() {
+    svsetffr();
+    let _ = svld1uw_s64(svptrue_b32(), U32_DATA.as_ptr());
+    let loaded = svldnf1uw_s64(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_u16() {
+    svsetffr();
+    let _ = svld1ub_u16(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1ub_u16(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_u32() {
+    svsetffr();
+    let _ = svld1ub_u32(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1ub_u32(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_u32() {
+    svsetffr();
+    let _ = svld1uh_u32(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldnf1uh_u32(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_u64() {
+    svsetffr();
+    let _ = svld1ub_u64(svptrue_b8(), U8_DATA.as_ptr());
+    let loaded = svldnf1ub_u64(svptrue_b8(), U8_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_u64() {
+    svsetffr();
+    let _ = svld1uh_u64(svptrue_b16(), U16_DATA.as_ptr());
+    let loaded = svldnf1uh_u64(svptrue_b16(), U16_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uw_u64() {
+    svsetffr();
+    let _ = svld1uw_u64(svptrue_b32(), U32_DATA.as_ptr());
+    let loaded = svldnf1uw_u64(svptrue_b32(), U32_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_vnum_s16() {
+    svsetffr();
+    let _ = svld1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_vnum_s32() {
+    svsetffr();
+    let _ = svld1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_vnum_s32() {
+    svsetffr();
+    let _ = svld1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldnf1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_vnum_s64() {
+    svsetffr();
+    let _ = svld1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_vnum_s64() {
+    svsetffr();
+    let _ = svld1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldnf1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uw_vnum_s64() {
+    svsetffr();
+    let _ = svld1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldnf1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_vnum_u16() {
+    svsetffr();
+    let _ = svld1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_vnum_u32() {
+    svsetffr();
+    let _ = svld1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_vnum_u32() {
+    svsetffr();
+    let _ = svld1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldnf1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1ub_vnum_u64() {
+    svsetffr();
+    let _ = svld1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldnf1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uh_vnum_u64() {
+    svsetffr();
+    let _ = svld1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldnf1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnf1uw_vnum_u64() {
+    svsetffr();
+    let _ = svld1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldnf1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_f32_with_svstnt1_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    svstnt1_f32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svldnt1_f32(svptrue_b32(), storage.as_ptr() as *const f32);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_f64_with_svstnt1_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    svstnt1_f64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svldnt1_f64(svptrue_b64(), storage.as_ptr() as *const f64);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_s8_with_svstnt1_s8() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_s8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1_s8(svptrue_b8(), storage.as_ptr() as *const i8);
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_s16_with_svstnt1_s16() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_s16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1_s16(svptrue_b16(), storage.as_ptr() as *const i16);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_s32_with_svstnt1_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_s32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1_s32(svptrue_b32(), storage.as_ptr() as *const i32);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_s64_with_svstnt1_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_s64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svldnt1_s64(svptrue_b64(), storage.as_ptr() as *const i64);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_u8_with_svstnt1_u8() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_u8(svptrue_b8(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svldnt1_u8(svptrue_b8(), storage.as_ptr() as *const u8);
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_u16_with_svstnt1_u16() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_u16(svptrue_b16(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svldnt1_u16(svptrue_b16(), storage.as_ptr() as *const u16);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_u32_with_svstnt1_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_u32(svptrue_b32(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svldnt1_u32(svptrue_b32(), storage.as_ptr() as *const u32);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_u64_with_svstnt1_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    svstnt1_u64(svptrue_b64(), storage.as_mut_ptr(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svldnt1_u64(svptrue_b64(), storage.as_ptr() as *const u64);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_f32_with_svstnt1_vnum_f32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+    svstnt1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_f64_with_svstnt1_vnum_f64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+    svstnt1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_s8_with_svstnt1_vnum_s8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s8(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1);
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_s16_with_svstnt1_vnum_s16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1);
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_s32_with_svstnt1_vnum_s32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_s64_with_svstnt1_vnum_s64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_u8_with_svstnt1_vnum_u8() {
+    let len = svcntb() as usize;
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u8(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1);
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_u16_with_svstnt1_vnum_u16() {
+    let len = svcnth() as usize;
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u16(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1);
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_u32_with_svstnt1_vnum_u32() {
+    let len = svcntw() as usize;
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldnt1_vnum_u64_with_svstnt1_vnum_u64() {
+    let len = svcntd() as usize;
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64(
+        (len + 0usize).try_into().unwrap(),
+        1usize.try_into().unwrap(),
+    );
+    svstnt1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svldnt1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb() {
+    svsetffr();
+    let loaded = svprfb::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), I64_DATA.as_ptr());
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh() {
+    svsetffr();
+    let loaded = svprfh::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), I64_DATA.as_ptr());
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw() {
+    svsetffr();
+    let loaded = svprfw::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), I64_DATA.as_ptr());
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd() {
+    svsetffr();
+    let loaded = svprfd::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), I64_DATA.as_ptr());
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_s32offset() {
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfb_gather_s32offset::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        offsets,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_s32index() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let loaded = svprfh_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_s32index() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let loaded = svprfw_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_s32index() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let loaded = svprfd_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_s64offset() {
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfb_gather_s64offset::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        offsets,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_s64index() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let loaded = svprfh_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_s64index() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let loaded = svprfw_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_s64index() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let loaded = svprfd_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_u32offset() {
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfb_gather_u32offset::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        offsets,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_u32index() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let loaded = svprfh_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_u32index() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let loaded = svprfw_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_u32index() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let loaded = svprfd_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b32(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_u64offset() {
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfb_gather_u64offset::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        offsets,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_u64index() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let loaded = svprfh_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_u64index() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let loaded = svprfw_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_u64index() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let loaded = svprfd_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>(
+        svptrue_b64(),
+        I64_DATA.as_ptr(),
+        indices,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_u64base() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfb_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_u64base() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfh_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_u64base() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfw_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_u64base() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfd_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_u32base_offset() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfb_gather_u32base_offset::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_u32base_index() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfh_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_u32base_index() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfw_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_u32base_index() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let loaded = svprfd_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_gather_u64base_offset() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfb_gather_u64base_offset::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b64(),
+        bases,
+        8u32.try_into().unwrap(),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_gather_u64base_index() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfh_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b64(),
+        bases,
+        1.try_into().unwrap(),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_gather_u64base_index() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfw_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b64(),
+        bases,
+        1.try_into().unwrap(),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_gather_u64base_index() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let loaded = svprfd_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>(
+        svptrue_b64(),
+        bases,
+        1.try_into().unwrap(),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfb_vnum() {
+    svsetffr();
+    let loaded = svprfb_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), I64_DATA.as_ptr(), 1);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfh_vnum() {
+    svsetffr();
+    let loaded = svprfh_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), I64_DATA.as_ptr(), 1);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfw_vnum() {
+    svsetffr();
+    let loaded = svprfw_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), I64_DATA.as_ptr(), 1);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svprfd_vnum() {
+    svsetffr();
+    let loaded = svprfd_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), I64_DATA.as_ptr(), 1);
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_ffr() {
+    svsetffr();
+    let ffr = svrdffr();
+    assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0));
+    let pred = svdupq_n_b8(
+        true, false, true, false, true, false, true, false, true, false, true, false, true, false,
+        true, false,
+    );
+    svwrffr(pred);
+    let ffr = svrdffr_z(svptrue_b8());
+    assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1));
+}
diff --git a/crates/core_arch/src/aarch64/sve2/generated.rs b/crates/core_arch/src/aarch64/sve2/generated.rs
index 8b13789179..79be8a8889 100644
--- a/crates/core_arch/src/aarch64/sve2/generated.rs
+++ b/crates/core_arch/src/aarch64/sve2/generated.rs
@@ -1 +1,23857 @@
+// This code is automatically generated. DO NOT MODIFY.
+//
+// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file:
+//
+// ```
+// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
+// ```
+#![allow(improper_ctypes)]
 
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+use super::*;
+
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv16i8")]
+        fn _svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaba_s8(op1, op2, op3) }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svaba_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv8i16")]
+        fn _svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svaba_s16(op1, op2, op3) }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svaba_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv4i32")]
+        fn _svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svaba_s32(op1, op2, op3) }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svaba_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv2i64")]
+        fn _svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svaba_s64(op1, op2, op3) }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saba))]
+pub fn svaba_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svaba_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv16i8")]
+        fn _svaba_u8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaba_u8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svaba_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv8i16")]
+        fn _svaba_u16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svaba_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svaba_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv4i32")]
+        fn _svaba_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svaba_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svaba_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv2i64")]
+        fn _svaba_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svaba_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaba))]
+pub fn svaba_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svaba_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalb))]
+pub fn svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv8i16")]
+        fn _svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabalb_s16(op1, op2, op3) }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalb))]
+pub fn svabalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svabalb_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalb))]
+pub fn svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv4i32")]
+        fn _svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabalb_s32(op1, op2, op3) }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalb))]
+pub fn svabalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svabalb_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalb))]
+pub fn svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv2i64")]
+        fn _svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabalb_s64(op1, op2, op3) }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalb))]
+pub fn svabalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svabalb_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalb))]
+pub fn svabalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv8i16")]
+        fn _svabalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalb))]
+pub fn svabalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
+    svabalb_u16(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalb))]
+pub fn svabalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv4i32")]
+        fn _svabalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalb))]
+pub fn svabalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
+    svabalb_u32(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalb))]
+pub fn svabalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv2i64")]
+        fn _svabalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalb))]
+pub fn svabalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
+    svabalb_u64(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalt))]
+pub fn svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv8i16")]
+        fn _svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabalt_s16(op1, op2, op3) }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalt))]
+pub fn svabalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svabalt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalt))]
+pub fn svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv4i32")]
+        fn _svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabalt_s32(op1, op2, op3) }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalt))]
+pub fn svabalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svabalt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalt))]
+pub fn svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv2i64")]
+        fn _svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabalt_s64(op1, op2, op3) }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabalt))]
+pub fn svabalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svabalt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalt))]
+pub fn svabalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv8i16")]
+        fn _svabalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalt))]
+pub fn svabalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
+    svabalt_u16(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalt))]
+pub fn svabalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv4i32")]
+        fn _svabalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalt))]
+pub fn svabalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
+    svabalt_u32(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalt))]
+pub fn svabalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv2i64")]
+        fn _svabalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabalt))]
+pub fn svabalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
+    svabalt_u64(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlb))]
+pub fn svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv8i16")]
+        fn _svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabdlb_s16(op1, op2) }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlb))]
+pub fn svabdlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svabdlb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlb))]
+pub fn svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv4i32")]
+        fn _svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabdlb_s32(op1, op2) }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlb))]
+pub fn svabdlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svabdlb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlb))]
+pub fn svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv2i64")]
+        fn _svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabdlb_s64(op1, op2) }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlb))]
+pub fn svabdlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svabdlb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlb))]
+pub fn svabdlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv8i16")]
+        fn _svabdlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabdlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlb))]
+pub fn svabdlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svabdlb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlb))]
+pub fn svabdlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv4i32")]
+        fn _svabdlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabdlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlb))]
+pub fn svabdlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svabdlb_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlb))]
+pub fn svabdlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv2i64")]
+        fn _svabdlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabdlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlb))]
+pub fn svabdlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svabdlb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlt))]
+pub fn svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv8i16")]
+        fn _svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabdlt_s16(op1, op2) }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlt))]
+pub fn svabdlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svabdlt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlt))]
+pub fn svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv4i32")]
+        fn _svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabdlt_s32(op1, op2) }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlt))]
+pub fn svabdlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svabdlt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlt))]
+pub fn svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv2i64")]
+        fn _svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabdlt_s64(op1, op2) }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sabdlt))]
+pub fn svabdlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svabdlt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlt))]
+pub fn svabdlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv8i16")]
+        fn _svabdlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svabdlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlt))]
+pub fn svabdlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svabdlt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlt))]
+pub fn svabdlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv4i32")]
+        fn _svabdlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svabdlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlt))]
+pub fn svabdlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svabdlt_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlt))]
+pub fn svabdlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv2i64")]
+        fn _svabdlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svabdlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Absolute difference long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uabdlt))]
+pub fn svabdlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svabdlt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv8i16")]
+        fn _svadalp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svadalp_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t {
+    svadalp_s16_m(pg, op1, op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s16_z(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t {
+    svadalp_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv4i32")]
+        fn _svadalp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svadalp_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t {
+    svadalp_s32_m(pg, op1, op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s32_z(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t {
+    svadalp_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv2i64")]
+        fn _svadalp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svadalp_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t {
+    svadalp_s64_m(pg, op1, op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sadalp))]
+pub fn svadalp_s64_z(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t {
+    svadalp_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv8i16")]
+        fn _svadalp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svadalp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    svadalp_u16_m(pg, op1, op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    svadalp_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv4i32")]
+        fn _svadalp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svadalp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    svadalp_u32_m(pg, op1, op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    svadalp_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv2i64")]
+        fn _svadalp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svadalp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    svadalp_u64_m(pg, op1, op2)
+}
+#[doc = "Add and accumulate long pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uadalp))]
+pub fn svadalp_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    svadalp_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Add with carry long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclb))]
+pub fn svadclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv4i32")]
+        fn _svadclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Add with carry long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclb))]
+pub fn svadclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svadclb_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Add with carry long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclb))]
+pub fn svadclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv2i64")]
+        fn _svadclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Add with carry long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclb))]
+pub fn svadclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svadclb_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Add with carry long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclt))]
+pub fn svadclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv4i32")]
+        fn _svadclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svadclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Add with carry long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclt))]
+pub fn svadclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svadclt_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Add with carry long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclt))]
+pub fn svadclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv2i64")]
+        fn _svadclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svadclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Add with carry long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(adclt))]
+pub fn svadclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svadclt_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv8i16")]
+        fn _svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svaddhnb_s16(op1, op2) }
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
+    svaddhnb_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv4i32")]
+        fn _svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svaddhnb_s32(op1, op2) }
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
+    svaddhnb_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv2i64")]
+        fn _svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svaddhnb_s64(op1, op2) }
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
+    svaddhnb_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svaddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
+    svaddhnb_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svaddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
+    svaddhnb_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svaddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnb))]
+pub fn svaddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
+    svaddhnb_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv8i16")]
+        fn _svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svaddhnt_s16(even, op1, op2) }
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
+    svaddhnt_s16(even, op1, svdup_n_s16(op2))
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv4i32")]
+        fn _svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svaddhnt_s32(even, op1, op2) }
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
+    svaddhnt_s32(even, op1, svdup_n_s32(op2))
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv2i64")]
+        fn _svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svaddhnt_s64(even, op1, op2) }
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
+    svaddhnt_s64(even, op1, svdup_n_s64(op2))
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svaddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t {
+    svaddhnt_u16(even, op1, svdup_n_u16(op2))
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svaddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t {
+    svaddhnt_u32(even, op1, svdup_n_u32(op2))
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svaddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addhnt))]
+pub fn svaddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t {
+    svaddhnt_u64(even, op1, svdup_n_u64(op2))
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlb))]
+pub fn svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv8i16")]
+        fn _svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddlb_s16(op1, op2) }
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlb))]
+pub fn svaddlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svaddlb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlb))]
+pub fn svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv4i32")]
+        fn _svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddlb_s32(op1, op2) }
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlb))]
+pub fn svaddlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svaddlb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlb))]
+pub fn svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv2i64")]
+        fn _svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddlb_s64(op1, op2) }
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlb))]
+pub fn svaddlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svaddlb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlb))]
+pub fn svaddlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv8i16")]
+        fn _svaddlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlb))]
+pub fn svaddlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svaddlb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlb))]
+pub fn svaddlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv4i32")]
+        fn _svaddlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlb))]
+pub fn svaddlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svaddlb_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlb))]
+pub fn svaddlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv2i64")]
+        fn _svaddlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlb))]
+pub fn svaddlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svaddlb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Add long (bottom + top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlbt))]
+pub fn svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.saddlbt.nxv8i16"
+        )]
+        fn _svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddlbt_s16(op1, op2) }
+}
+#[doc = "Add long (bottom + top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlbt))]
+pub fn svaddlbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svaddlbt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Add long (bottom + top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlbt))]
+pub fn svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.saddlbt.nxv4i32"
+        )]
+        fn _svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddlbt_s32(op1, op2) }
+}
+#[doc = "Add long (bottom + top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlbt))]
+pub fn svaddlbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svaddlbt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Add long (bottom + top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlbt))]
+pub fn svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.saddlbt.nxv2i64"
+        )]
+        fn _svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddlbt_s64(op1, op2) }
+}
+#[doc = "Add long (bottom + top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlbt))]
+pub fn svaddlbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svaddlbt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlt))]
+pub fn svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv8i16")]
+        fn _svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddlt_s16(op1, op2) }
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlt))]
+pub fn svaddlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svaddlt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlt))]
+pub fn svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv4i32")]
+        fn _svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddlt_s32(op1, op2) }
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlt))]
+pub fn svaddlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svaddlt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlt))]
+pub fn svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv2i64")]
+        fn _svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddlt_s64(op1, op2) }
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddlt))]
+pub fn svaddlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svaddlt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlt))]
+pub fn svaddlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv8i16")]
+        fn _svaddlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlt))]
+pub fn svaddlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svaddlt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlt))]
+pub fn svaddlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv4i32")]
+        fn _svaddlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlt))]
+pub fn svaddlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svaddlt_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlt))]
+pub fn svaddlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv2i64")]
+        fn _svaddlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddlt))]
+pub fn svaddlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svaddlt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(faddp))]
+pub fn svaddp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv4f32")]
+        fn _svaddp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svaddp_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(faddp))]
+pub fn svaddp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svaddp_f32_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(faddp))]
+pub fn svaddp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv2f64")]
+        fn _svaddp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svaddp_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(faddp))]
+pub fn svaddp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svaddp_f64_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv16i8")]
+        fn _svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaddp_s8_m(pg, op1, op2) }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svaddp_s8_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv8i16")]
+        fn _svaddp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svaddp_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svaddp_s16_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv4i32")]
+        fn _svaddp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svaddp_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svaddp_s32_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv2i64")]
+        fn _svaddp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svaddp_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svaddp_s64_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svaddp_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svaddp_u8_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { svaddp_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svaddp_u16_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svaddp_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svaddp_u32_m(pg, op1, op2)
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svaddp_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(addp))]
+pub fn svaddp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svaddp_u64_m(pg, op1, op2)
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwb))]
+pub fn svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv8i16")]
+        fn _svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddwb_s16(op1, op2) }
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwb))]
+pub fn svaddwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
+    svaddwb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwb))]
+pub fn svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv4i32")]
+        fn _svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddwb_s32(op1, op2) }
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwb))]
+pub fn svaddwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
+    svaddwb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwb))]
+pub fn svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv2i64")]
+        fn _svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddwb_s64(op1, op2) }
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwb))]
+pub fn svaddwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
+    svaddwb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwb))]
+pub fn svaddwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv8i16")]
+        fn _svaddwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwb))]
+pub fn svaddwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
+    svaddwb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwb))]
+pub fn svaddwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv4i32")]
+        fn _svaddwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwb))]
+pub fn svaddwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
+    svaddwb_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwb))]
+pub fn svaddwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv2i64")]
+        fn _svaddwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwb))]
+pub fn svaddwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
+    svaddwb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwt))]
+pub fn svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv8i16")]
+        fn _svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddwt_s16(op1, op2) }
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwt))]
+pub fn svaddwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
+    svaddwt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwt))]
+pub fn svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv4i32")]
+        fn _svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddwt_s32(op1, op2) }
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwt))]
+pub fn svaddwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
+    svaddwt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwt))]
+pub fn svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv2i64")]
+        fn _svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddwt_s64(op1, op2) }
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(saddwt))]
+pub fn svaddwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
+    svaddwt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwt))]
+pub fn svaddwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv8i16")]
+        fn _svaddwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svaddwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwt))]
+pub fn svaddwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
+    svaddwt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwt))]
+pub fn svaddwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv4i32")]
+        fn _svaddwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svaddwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwt))]
+pub fn svaddwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
+    svaddwt_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwt))]
+pub fn svaddwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv2i64")]
+        fn _svaddwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svaddwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Add wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uaddwt))]
+pub fn svaddwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
+    svaddwt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "AES single round decryption"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesd[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(aesd))]
+pub fn svaesd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesd")]
+        fn _svaesd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaesd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "AES single round encryption"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaese[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(aese))]
+pub fn svaese_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aese")]
+        fn _svaese_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaese_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "AES inverse mix columns"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesimc[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(aesimc))]
+pub fn svaesimc_u8(op: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesimc")]
+        fn _svaesimc_u8(op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaesimc_u8(op.as_signed()).as_unsigned() }
+}
+#[doc = "AES mix columns"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesmc[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(aesmc))]
+pub fn svaesmc_u8(op: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesmc")]
+        fn _svaesmc_u8(op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svaesmc_u8(op.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv16i8")]
+        fn _svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbcax_s8(op1, op2, op3) }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svbcax_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv8i16")]
+        fn _svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbcax_s16(op1, op2, op3) }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svbcax_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv4i32")]
+        fn _svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbcax_s32(op1, op2, op3) }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svbcax_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv2i64")]
+        fn _svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbcax_s64(op1, op2, op3) }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svbcax_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svbcax_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svbcax_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svbcax_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svbcax_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svbcax_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svbcax_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svbcax_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise clear and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bcax))]
+pub fn svbcax_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svbcax_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv16i8")]
+        fn _svbdep_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbdep_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svbdep_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv8i16")]
+        fn _svbdep_u16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbdep_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
+    svbdep_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv4i32")]
+        fn _svbdep_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbdep_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svbdep_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv2i64")]
+        fn _svbdep_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbdep_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Scatter lower bits into positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bdep))]
+pub fn svbdep_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svbdep_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv16i8")]
+        fn _svbext_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbext_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svbext_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv8i16")]
+        fn _svbext_u16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbext_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
+    svbext_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv4i32")]
+        fn _svbext_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbext_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svbext_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv2i64")]
+        fn _svbext_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbext_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Gather lower bits from positions selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bext))]
+pub fn svbext_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svbext_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv16i8")]
+        fn _svbgrp_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbgrp_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svbgrp_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv8i16")]
+        fn _svbgrp_u16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbgrp_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
+    svbgrp_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv4i32")]
+        fn _svbgrp_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbgrp_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svbgrp_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv2i64")]
+        fn _svbgrp_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbgrp_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Group bits to right or left as selected by bitmask"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-bitperm")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bgrp))]
+pub fn svbgrp_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svbgrp_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv16i8")]
+        fn _svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbsl1n_s8(op1, op2, op3) }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svbsl1n_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv8i16")]
+        fn _svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbsl1n_s16(op1, op2, op3) }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svbsl1n_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv4i32")]
+        fn _svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbsl1n_s32(op1, op2, op3) }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svbsl1n_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv2i64")]
+        fn _svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbsl1n_s64(op1, op2, op3) }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svbsl1n_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svbsl1n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svbsl1n_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svbsl1n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svbsl1n_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svbsl1n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svbsl1n_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svbsl1n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with first input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl1n))]
+pub fn svbsl1n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svbsl1n_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv16i8")]
+        fn _svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbsl2n_s8(op1, op2, op3) }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svbsl2n_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv8i16")]
+        fn _svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbsl2n_s16(op1, op2, op3) }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svbsl2n_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv4i32")]
+        fn _svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbsl2n_s32(op1, op2, op3) }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svbsl2n_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv2i64")]
+        fn _svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbsl2n_s64(op1, op2, op3) }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svbsl2n_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svbsl2n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svbsl2n_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svbsl2n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svbsl2n_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svbsl2n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svbsl2n_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svbsl2n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select with second input inverted"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl2n))]
+pub fn svbsl2n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svbsl2n_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv16i8")]
+        fn _svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svbsl_s8(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svbsl_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv8i16")]
+        fn _svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svbsl_s16(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svbsl_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv4i32")]
+        fn _svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svbsl_s32(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svbsl_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv2i64")]
+        fn _svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svbsl_s64(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svbsl_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svbsl_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svbsl_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svbsl_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(bsl))]
+pub fn svbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svbsl_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_s8<const IMM_ROTATION: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv16i8")]
+        fn _svcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t;
+    }
+    unsafe { _svcadd_s8(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_s16<const IMM_ROTATION: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv8i16")]
+        fn _svcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t;
+    }
+    unsafe { _svcadd_s16(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_s32<const IMM_ROTATION: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv4i32")]
+        fn _svcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t;
+    }
+    unsafe { _svcadd_s32(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_s64<const IMM_ROTATION: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv2i64")]
+        fn _svcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t;
+    }
+    unsafe { _svcadd_s64(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_u8<const IMM_ROTATION: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe { svcadd_s8::<IMM_ROTATION>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_u16<const IMM_ROTATION: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe { svcadd_s16::<IMM_ROTATION>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_u32<const IMM_ROTATION: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe { svcadd_s32::<IMM_ROTATION>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
+pub fn svcadd_u64<const IMM_ROTATION: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe { svcadd_s64::<IMM_ROTATION>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Complex dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcdot_lane_s32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svint32_t,
+    op2: svint8_t,
+    op3: svint8_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cdot.lane.nxv4i32"
+        )]
+        fn _svcdot_lane_s32(
+            op1: svint32_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svcdot_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Complex dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcdot_lane_s64<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svint64_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cdot.lane.nxv2i64"
+        )]
+        fn _svcdot_lane_s64(
+            op1: svint64_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svcdot_lane_s64(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Complex dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))]
+pub fn svcdot_s32<const IMM_ROTATION: i32>(
+    op1: svint32_t,
+    op2: svint8_t,
+    op3: svint8_t,
+) -> svint32_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv4i32")]
+        fn _svcdot_s32(
+            op1: svint32_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_rotation: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svcdot_s32(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex dot product"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))]
+pub fn svcdot_s64<const IMM_ROTATION: i32>(
+    op1: svint64_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint64_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv2i64")]
+        fn _svcdot_s64(
+            op1: svint64_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_rotation: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svcdot_s64(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcmla_lane_s16<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmla.lane.x.nxv8i16"
+        )]
+        fn _svcmla_lane_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svcmla_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcmla_lane_s32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.cmla.lane.x.nxv4i32"
+        )]
+        fn _svcmla_lane_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svcmla_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcmla_lane_u16<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svuint16_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe {
+        svcmla_lane_s16::<IMM_INDEX, IMM_ROTATION>(
+            op1.as_signed(),
+            op2.as_signed(),
+            op3.as_signed(),
+        )
+        .as_unsigned()
+    }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svcmla_lane_u32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svuint32_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe {
+        svcmla_lane_s32::<IMM_INDEX, IMM_ROTATION>(
+            op1.as_signed(),
+            op2.as_signed(),
+            op3.as_signed(),
+        )
+        .as_unsigned()
+    }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_s8<const IMM_ROTATION: i32>(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv16i8")]
+        fn _svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t, imm_rotation: i32) -> svint8_t;
+    }
+    unsafe { _svcmla_s8(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_s16<const IMM_ROTATION: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv8i16")]
+        fn _svcmla_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_rotation: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svcmla_s16(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_s32<const IMM_ROTATION: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv4i32")]
+        fn _svcmla_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            imm_rotation: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svcmla_s32(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_s64<const IMM_ROTATION: i32>(
+    op1: svint64_t,
+    op2: svint64_t,
+    op3: svint64_t,
+) -> svint64_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv2i64")]
+        fn _svcmla_s64(
+            op1: svint64_t,
+            op2: svint64_t,
+            op3: svint64_t,
+            imm_rotation: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svcmla_s64(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_u8<const IMM_ROTATION: i32>(
+    op1: svuint8_t,
+    op2: svuint8_t,
+    op3: svuint8_t,
+) -> svuint8_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe {
+        svcmla_s8::<IMM_ROTATION>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_u16<const IMM_ROTATION: i32>(
+    op1: svuint16_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint16_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe {
+        svcmla_s16::<IMM_ROTATION>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_u32<const IMM_ROTATION: i32>(
+    op1: svuint32_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint32_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe {
+        svcmla_s32::<IMM_ROTATION>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Complex multiply-add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
+pub fn svcmla_u64<const IMM_ROTATION: i32>(
+    op1: svuint64_t,
+    op2: svuint64_t,
+    op3: svuint64_t,
+) -> svuint64_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe {
+        svcmla_s64::<IMM_ROTATION>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Up convert long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtlt))]
+pub fn svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtlt.f64f32")]
+        fn _svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t)
+            -> svfloat64_t;
+    }
+    unsafe { _svcvtlt_f64_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Up convert long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtlt))]
+pub fn svcvtlt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
+    unsafe { svcvtlt_f64_f32_m(crate::intrinsics::transmute_unchecked(op), pg, op) }
+}
+#[doc = "Down convert and narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtnt))]
+pub fn svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtnt.f32f64")]
+        fn _svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvtnt_f32_f64_m(even, pg.sve_into(), op) }
+}
+#[doc = "Down convert and narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtnt))]
+pub fn svcvtnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    svcvtnt_f32_f64_m(even, pg, op)
+}
+#[doc = "Down convert, rounding to odd"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtx))]
+pub fn svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtx.f32f64")]
+        fn _svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvtx_f32_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Down convert, rounding to odd"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtx))]
+pub fn svcvtx_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    unsafe { svcvtx_f32_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Down convert, rounding to odd"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtx))]
+pub fn svcvtx_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    svcvtx_f32_f64_m(svdup_n_f32(0.0), pg, op)
+}
+#[doc = "Down convert, rounding to odd (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtxnt))]
+pub fn svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtxnt.f32f64")]
+        fn _svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t;
+    }
+    unsafe { _svcvtxnt_f32_f64_m(even, pg.sve_into(), op) }
+}
+#[doc = "Down convert, rounding to odd (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fcvtxnt))]
+pub fn svcvtxnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
+    svcvtxnt_f32_f64_m(even, pg, op)
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv16i8")]
+        fn _sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _sveor3_s8(op1, op2, op3) }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    sveor3_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv8i16")]
+        fn _sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _sveor3_s16(op1, op2, op3) }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    sveor3_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv4i32")]
+        fn _sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _sveor3_s32(op1, op2, op3) }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    sveor3_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv2i64")]
+        fn _sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _sveor3_s64(op1, op2, op3) }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    sveor3_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { sveor3_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    sveor3_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { sveor3_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    sveor3_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { sveor3_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    sveor3_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { sveor3_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR of three vectors"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eor3))]
+pub fn sveor3_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    sveor3_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv16i8")]
+        fn _sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _sveorbt_s8(odd, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_s8(odd: svint8_t, op1: svint8_t, op2: i8) -> svint8_t {
+    sveorbt_s8(odd, op1, svdup_n_s8(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv8i16")]
+        fn _sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _sveorbt_s16(odd, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_s16(odd: svint16_t, op1: svint16_t, op2: i16) -> svint16_t {
+    sveorbt_s16(odd, op1, svdup_n_s16(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv4i32")]
+        fn _sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _sveorbt_s32(odd, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_s32(odd: svint32_t, op1: svint32_t, op2: i32) -> svint32_t {
+    sveorbt_s32(odd, op1, svdup_n_s32(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv2i64")]
+        fn _sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _sveorbt_s64(odd, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_s64(odd: svint64_t, op1: svint64_t, op2: i64) -> svint64_t {
+    sveorbt_s64(odd, op1, svdup_n_s64(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_u8(odd: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { sveorbt_s8(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_u8(odd: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    sveorbt_u8(odd, op1, svdup_n_u8(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_u16(odd: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { sveorbt_s16(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_u16(odd: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    sveorbt_u16(odd, op1, svdup_n_u16(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_u32(odd: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { sveorbt_s32(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_u32(odd: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    sveorbt_u32(odd, op1, svdup_n_u32(op2))
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_u64(odd: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { sveorbt_s64(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (bottom, top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eorbt))]
+pub fn sveorbt_n_u64(odd: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    sveorbt_u64(odd, op1, svdup_n_u64(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv16i8")]
+        fn _sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _sveortb_s8(even, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_s8(even: svint8_t, op1: svint8_t, op2: i8) -> svint8_t {
+    sveortb_s8(even, op1, svdup_n_s8(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv8i16")]
+        fn _sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _sveortb_s16(even, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_s16(even: svint16_t, op1: svint16_t, op2: i16) -> svint16_t {
+    sveortb_s16(even, op1, svdup_n_s16(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv4i32")]
+        fn _sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _sveortb_s32(even, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_s32(even: svint32_t, op1: svint32_t, op2: i32) -> svint32_t {
+    sveortb_s32(even, op1, svdup_n_s32(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv2i64")]
+        fn _sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _sveortb_s64(even, op1, op2) }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_s64(even: svint64_t, op1: svint64_t, op2: i64) -> svint64_t {
+    sveortb_s64(even, op1, svdup_n_s64(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_u8(even: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { sveortb_s8(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_u8(even: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    sveortb_u8(even, op1, svdup_n_u8(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_u16(even: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe { sveortb_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_u16(even: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    sveortb_u16(even, op1, svdup_n_u16(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_u32(even: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { sveortb_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_u32(even: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    sveortb_u32(even, op1, svdup_n_u32(op2))
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_u64(even: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { sveortb_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Interleaving exclusive OR (top, bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(eortb))]
+pub fn sveortb_n_u64(even: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    sveortb_u64(even, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv16i8")]
+        fn _svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhadd_s8_m(pg, op1, op2) }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhadd_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svhadd_s8_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhadd_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhadd_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv8i16")]
+        fn _svhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svhadd_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhadd_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svhadd_s16_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhadd_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhadd_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv4i32")]
+        fn _svhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhadd_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhadd_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svhadd_s32_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhadd_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhadd_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv2i64")]
+        fn _svhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhadd_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhadd_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svhadd_s64_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhadd_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shadd))]
+pub fn svhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhadd_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv16i8")]
+        fn _svhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhadd_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svhadd_u8_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhadd_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhadd_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv8i16")]
+        fn _svhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhadd_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svhadd_u16_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhadd_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhadd_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv4i32")]
+        fn _svhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhadd_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svhadd_u32_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhadd_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhadd_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv2i64")]
+        fn _svhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhadd_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svhadd_u64_m(pg, op1, op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhadd_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhadd))]
+pub fn svhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhadd_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Count matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(histcnt))]
+pub fn svhistcnt_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.histcnt.nxv4i32"
+        )]
+        fn _svhistcnt_s32_z(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhistcnt_s32_z(pg.sve_into(), op1, op2).as_unsigned() }
+}
+#[doc = "Count matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(histcnt))]
+pub fn svhistcnt_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.histcnt.nxv2i64"
+        )]
+        fn _svhistcnt_s64_z(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhistcnt_s64_z(pg.sve_into(), op1, op2).as_unsigned() }
+}
+#[doc = "Count matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(histcnt))]
+pub fn svhistcnt_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe { svhistcnt_s32_z(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Count matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(histcnt))]
+pub fn svhistcnt_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svhistcnt_s64_z(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Count matching elements in 128-bit segments"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(histseg))]
+pub fn svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.histseg.nxv16i8"
+        )]
+        fn _svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhistseg_s8(op1, op2).as_unsigned() }
+}
+#[doc = "Count matching elements in 128-bit segments"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(histseg))]
+pub fn svhistseg_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe { svhistseg_s8(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv16i8")]
+        fn _svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhsub_s8_m(pg, op1, op2) }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhsub_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svhsub_s8_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhsub_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svhsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhsub_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv8i16")]
+        fn _svhsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svhsub_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhsub_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svhsub_s16_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhsub_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svhsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhsub_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv4i32")]
+        fn _svhsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhsub_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhsub_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svhsub_s32_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhsub_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svhsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhsub_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv2i64")]
+        fn _svhsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhsub_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhsub_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svhsub_s64_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhsub_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svhsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhsub_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv16i8")]
+        fn _svhsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhsub_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svhsub_u8_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhsub_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svhsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhsub_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv8i16")]
+        fn _svhsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svhsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhsub_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svhsub_u16_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhsub_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svhsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhsub_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv4i32")]
+        fn _svhsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhsub_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svhsub_u32_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhsub_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svhsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhsub_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv2i64")]
+        fn _svhsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhsub_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svhsub_u64_m(pg, op1, op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhsub_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svhsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Halving subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhsub_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv16i8")]
+        fn _svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhsubr_s8_m(pg, op1, op2) }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhsubr_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svhsubr_s8_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhsubr_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svhsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svhsubr_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv8i16")]
+        fn _svhsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svhsubr_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhsubr_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svhsubr_s16_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhsubr_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svhsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svhsubr_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv4i32")]
+        fn _svhsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhsubr_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhsubr_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svhsubr_s32_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhsubr_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svhsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svhsubr_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv2i64")]
+        fn _svhsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhsubr_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhsubr_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svhsubr_s64_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhsubr_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svhsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shsub))]
+pub fn svhsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svhsubr_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv16i8")]
+        fn _svhsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svhsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhsubr_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svhsubr_u8_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhsubr_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svhsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svhsubr_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv8i16")]
+        fn _svhsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svhsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhsubr_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svhsubr_u16_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhsubr_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svhsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svhsubr_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv4i32")]
+        fn _svhsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svhsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhsubr_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svhsubr_u32_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhsubr_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svhsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svhsubr_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv2i64")]
+        fn _svhsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svhsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhsubr_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svhsubr_u64_m(pg, op1, op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhsubr_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svhsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Halving subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uhsub))]
+pub fn svhsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svhsubr_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_s64index_f64(
+    pg: svbool_t,
+    base: *const f64,
+    indices: svint64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2f64"
+        )]
+        fn _svldnt1_gather_s64index_f64(
+            pg: svbool2_t,
+            base: *const f64,
+            indices: svint64_t,
+        ) -> svfloat64_t;
+    }
+    _svldnt1_gather_s64index_f64(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i64,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i64"
+        )]
+        fn _svldnt1_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i64,
+            indices: svint64_t,
+        ) -> svint64_t;
+    }
+    _svldnt1_gather_s64index_s64(pg.sve_into(), base, indices)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u64,
+    indices: svint64_t,
+) -> svuint64_t {
+    svldnt1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64index_f64(
+    pg: svbool_t,
+    base: *const f64,
+    indices: svuint64_t,
+) -> svfloat64_t {
+    svldnt1_gather_s64index_f64(pg, base, indices.as_signed())
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i64,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldnt1_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u64,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldnt1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_s64offset_f64(
+    pg: svbool_t,
+    base: *const f64,
+    offsets: svint64_t,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2f64"
+        )]
+        fn _svldnt1_gather_s64offset_f64(
+            pg: svbool2_t,
+            base: *const f64,
+            offsets: svint64_t,
+        ) -> svfloat64_t;
+    }
+    _svldnt1_gather_s64offset_f64(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i64,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i64"
+        )]
+        fn _svldnt1_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i64,
+            offsets: svint64_t,
+        ) -> svint64_t;
+    }
+    _svldnt1_gather_s64offset_s64(pg.sve_into(), base, offsets)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u64,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32offset_f32(
+    pg: svbool_t,
+    base: *const f32,
+    offsets: svuint32_t,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4f32"
+        )]
+        fn _svldnt1_gather_u32offset_f32(
+            pg: svbool4_t,
+            base: *const f32,
+            offsets: svint32_t,
+        ) -> svfloat32_t;
+    }
+    _svldnt1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i32"
+        )]
+        fn _svldnt1_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i32,
+            offsets: svint32_t,
+        ) -> svint32_t;
+    }
+    _svldnt1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svldnt1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64offset_f64(
+    pg: svbool_t,
+    base: *const f64,
+    offsets: svuint64_t,
+) -> svfloat64_t {
+    svldnt1_gather_s64offset_f64(pg, base, offsets.as_signed())
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i64,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u64,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t {
+    svldnt1_gather_u32base_offset_f32(pg, bases, 0)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldnt1_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldnt1_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t {
+    svldnt1_gather_u64base_offset_f64(pg, bases, 0)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_index_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svfloat32_t {
+    svldnt1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svldnt1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svldnt1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_index_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svfloat64_t {
+    svldnt1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldnt1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldnt1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3))
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_f32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_offset_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32"
+        )]
+        fn _svldnt1_gather_u32base_offset_f32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> svfloat32_t;
+    }
+    _svldnt1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32"
+        )]
+        fn _svldnt1_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> svint32_t;
+    }
+    _svldnt1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svldnt1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_offset_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64"
+        )]
+        fn _svldnt1_gather_u64base_offset_f64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> svfloat64_t;
+    }
+    _svldnt1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64"
+        )]
+        fn _svldnt1_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> svint64_t;
+    }
+    _svldnt1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Unextended load, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1d))]
+pub unsafe fn svldnt1_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldnt1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8"
+        )]
+        fn _svldnt1sb_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i8,
+            offsets: svint64_t,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_s64offset_s64(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16"
+        )]
+        fn _svldnt1sh_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i16,
+            offsets: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64offset_s64(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32"
+        )]
+        fn _svldnt1sw_gather_s64offset_s64(
+            pg: svbool2_t,
+            base: *const i32,
+            offsets: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64offset_s64(
+        pg.sve_into(),
+        base,
+        offsets,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldnt1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldnt1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svint64_t,
+) -> svuint64_t {
+    svldnt1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8"
+        )]
+        fn _svldnt1sb_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint32_t,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16"
+        )]
+        fn _svldnt1sh_gather_u32offset_s32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32offset_s32(
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svldnt1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    svldnt1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i8,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i16,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const i32,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svldnt1sb_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32base_offset_s32(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svldnt1sh_gather_u32base_offset_s32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32base_offset_s32(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svldnt1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    svldnt1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svldnt1sb_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svldnt1sh_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svldnt1sw_gather_u64base_offset_s64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_u64base_offset_s64(
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    ))
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldnt1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldnt1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    svldnt1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned()
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldnt1sb_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldnt1sh_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldnt1sb_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldnt1sh_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1sb_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1sh_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1sw_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sb))]
+pub unsafe fn svldnt1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1sb_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1sh_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1sw_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16"
+        )]
+        fn _svldnt1sh_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i16,
+            indices: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64index_s64(pg.sve_into(), base, indices))
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint64_t,
+) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32"
+        )]
+        fn _svldnt1sw_gather_s64index_s64(
+            pg: svbool2_t,
+            base: *const i32,
+            indices: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64index_s64(pg.sve_into(), base, indices))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svint64_t,
+) -> svuint64_t {
+    svldnt1sh_gather_s64index_s64(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svint64_t,
+) -> svuint64_t {
+    svldnt1sw_gather_s64index_s64(pg, base, indices).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed())
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const i16,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned()
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const i32,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned()
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svldnt1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svldnt1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldnt1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldnt1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 16-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sh))]
+pub unsafe fn svldnt1sh_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldnt1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and sign-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1sw))]
+pub unsafe fn svldnt1sw_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldnt1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint64_t,
+) -> svint64_t {
+    svldnt1ub_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint64_t,
+) -> svint64_t {
+    svldnt1uh_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_s64offset_s64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint64_t,
+) -> svint64_t {
+    svldnt1uw_gather_s64offset_u64(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8"
+        )]
+        fn _svldnt1ub_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i8,
+            offsets: svint64_t,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svldnt1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16"
+        )]
+        fn _svldnt1uh_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i16,
+            offsets: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldnt1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_s64offset_u64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32"
+        )]
+        fn _svldnt1uw_gather_s64offset_u64(
+            pg: svbool2_t,
+            base: *const i32,
+            offsets: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldnt1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint32_t,
+) -> svint32_t {
+    svldnt1ub_gather_u32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32offset_s32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint32_t,
+) -> svint32_t {
+    svldnt1uh_gather_u32offset_u32(pg, base, offsets).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8"
+        )]
+        fn _svldnt1ub_gather_u32offset_u32(
+            pg: svbool4_t,
+            base: *const i8,
+            offsets: svint32_t,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldnt1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32offset_u32(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint32_t,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16"
+        )]
+        fn _svldnt1uh_gather_u32offset_u32(
+            pg: svbool4_t,
+            base: *const i16,
+            offsets: svint32_t,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldnt1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed())
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64offset_s64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint64_t,
+) -> svint64_t {
+    svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u8,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u16,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64offset_u64(
+    pg: svbool_t,
+    base: *const u32,
+    offsets: svuint64_t,
+) -> svuint64_t {
+    svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed())
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    svldnt1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svint32_t {
+    svldnt1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svldnt1ub_gather_u32base_offset_u32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u8, _>(
+        _svldnt1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svldnt1uh_gather_u32base_offset_u32(
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        ) -> nxv4i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv4u16, _>(
+        _svldnt1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svldnt1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svldnt1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svint64_t {
+    svldnt1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed()
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svldnt1ub_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i8;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u8, _>(
+        _svldnt1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svldnt1uh_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldnt1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svldnt1uw_gather_u64base_offset_u64(
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldnt1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset)
+            .as_unsigned(),
+    )
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldnt1ub_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t {
+    svldnt1uh_gather_u32base_offset_s32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldnt1ub_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t {
+    svldnt1uh_gather_u32base_offset_u32(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1ub_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1uh_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t {
+    svldnt1uw_gather_u64base_offset_s64(pg, bases, 0)
+}
+#[doc = "Load 8-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1b))]
+pub unsafe fn svldnt1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1ub_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1uh_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t {
+    svldnt1uw_gather_u64base_offset_u64(pg, bases, 0)
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint64_t,
+) -> svint64_t {
+    svldnt1uh_gather_s64index_u64(pg, base, indices).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_s64index_s64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint64_t,
+) -> svint64_t {
+    svldnt1uw_gather_s64index_u64(pg, base, indices).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16"
+        )]
+        fn _svldnt1uh_gather_s64index_u64(
+            pg: svbool2_t,
+            base: *const i16,
+            indices: svint64_t,
+        ) -> nxv2i16;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u16, _>(
+        _svldnt1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_s64index_u64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svint64_t,
+) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32"
+        )]
+        fn _svldnt1uw_gather_s64index_u64(
+            pg: svbool2_t,
+            base: *const i32,
+            indices: svint64_t,
+        ) -> nxv2i32;
+    }
+    crate::intrinsics::simd::simd_cast::<nxv2u32, _>(
+        _svldnt1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(),
+    )
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed()
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64index_s64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint64_t,
+) -> svint64_t {
+    svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed()
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u16,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed())
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64index_u64(
+    pg: svbool_t,
+    base: *const u32,
+    indices: svuint64_t,
+) -> svuint64_t {
+    svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed())
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_s32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svint32_t {
+    svldnt1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_u32)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+) -> svuint32_t {
+    svldnt1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldnt1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svint64_t {
+    svldnt1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Load 16-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1h))]
+pub unsafe fn svldnt1uh_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldnt1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1))
+}
+#[doc = "Load 32-bit data and zero-extend, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ldnt1w))]
+pub unsafe fn svldnt1uw_gather_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+) -> svuint64_t {
+    svldnt1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2))
+}
+#[doc = "Base 2 logarithm as integer"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(flogb))]
+pub fn svlogb_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv4f32")]
+        fn _svlogb_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t;
+    }
+    unsafe { _svlogb_f32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Base 2 logarithm as integer"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(flogb))]
+pub fn svlogb_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    unsafe { svlogb_f32_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Base 2 logarithm as integer"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(flogb))]
+pub fn svlogb_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t {
+    svlogb_f32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Base 2 logarithm as integer"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(flogb))]
+pub fn svlogb_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv2f64")]
+        fn _svlogb_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t;
+    }
+    unsafe { _svlogb_f64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Base 2 logarithm as integer"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(flogb))]
+pub fn svlogb_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    unsafe { svlogb_f64_m(transmute_unchecked(op), pg, op) }
+}
+#[doc = "Base 2 logarithm as integer"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(flogb))]
+pub fn svlogb_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t {
+    svlogb_f64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Detect any matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(match))]
+pub fn svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv16i8")]
+        fn _svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svmatch_s8(pg, op1, op2) }
+}
+#[doc = "Detect any matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(match))]
+pub fn svmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv8i16")]
+        fn _svmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svmatch_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Detect any matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(match))]
+pub fn svmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    unsafe { svmatch_s8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Detect any matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(match))]
+pub fn svmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    unsafe { svmatch_s16(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Maximum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnmp))]
+pub fn svmaxnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmaxnmp.nxv4f32"
+        )]
+        fn _svmaxnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmaxnmp_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnmp))]
+pub fn svmaxnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmaxnmp_f32_m(pg, op1, op2)
+}
+#[doc = "Maximum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnmp))]
+pub fn svmaxnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmaxnmp.nxv2f64"
+        )]
+        fn _svmaxnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmaxnmp_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxnmp))]
+pub fn svmaxnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmaxnmp_f64_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxp))]
+pub fn svmaxp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv4f32")]
+        fn _svmaxp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svmaxp_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxp))]
+pub fn svmaxp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svmaxp_f32_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxp))]
+pub fn svmaxp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv2f64")]
+        fn _svmaxp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svmaxp_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmaxp))]
+pub fn svmaxp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svmaxp_f64_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv16i8")]
+        fn _svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmaxp_s8_m(pg, op1, op2) }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svmaxp_s8_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv8i16")]
+        fn _svmaxp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmaxp_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svmaxp_s16_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv4i32")]
+        fn _svmaxp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmaxp_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svmaxp_s32_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv2i64")]
+        fn _svmaxp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmaxp_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smaxp))]
+pub fn svmaxp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svmaxp_s64_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv16i8")]
+        fn _svmaxp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svmaxp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svmaxp_u8_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv8i16")]
+        fn _svmaxp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svmaxp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svmaxp_u16_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv4i32")]
+        fn _svmaxp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svmaxp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svmaxp_u32_m(pg, op1, op2)
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv2i64")]
+        fn _svmaxp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svmaxp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Maximum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umaxp))]
+pub fn svmaxp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svmaxp_u64_m(pg, op1, op2)
+}
+#[doc = "Minimum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnmp))]
+pub fn svminnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fminnmp.nxv4f32"
+        )]
+        fn _svminnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svminnmp_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnmp))]
+pub fn svminnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svminnmp_f32_m(pg, op1, op2)
+}
+#[doc = "Minimum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnmp))]
+pub fn svminnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fminnmp.nxv2f64"
+        )]
+        fn _svminnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svminnmp_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum number pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminnmp))]
+pub fn svminnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svminnmp_f64_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminp))]
+pub fn svminp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv4f32")]
+        fn _svminp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
+    }
+    unsafe { _svminp_f32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminp))]
+pub fn svminp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    svminp_f32_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminp))]
+pub fn svminp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv2f64")]
+        fn _svminp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
+    }
+    unsafe { _svminp_f64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fminp))]
+pub fn svminp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    svminp_f64_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv16i8")]
+        fn _svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svminp_s8_m(pg, op1, op2) }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svminp_s8_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv8i16")]
+        fn _svminp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svminp_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svminp_s16_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv4i32")]
+        fn _svminp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svminp_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svminp_s32_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv2i64")]
+        fn _svminp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svminp_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sminp))]
+pub fn svminp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svminp_s64_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv16i8")]
+        fn _svminp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svminp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svminp_u8_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv8i16")]
+        fn _svminp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svminp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svminp_u16_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv4i32")]
+        fn _svminp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svminp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svminp_u32_m(pg, op1, op2)
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv2i64")]
+        fn _svminp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svminp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Minimum pairwise"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uminp))]
+pub fn svminp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svminp_u64_m(pg, op1, op2)
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
+pub fn svmla_lane_s16<const IMM_INDEX: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mla.lane.nxv8i16"
+        )]
+        fn _svmla_lane_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svmla_lane_s16(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
+pub fn svmla_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mla.lane.nxv4i32"
+        )]
+        fn _svmla_lane_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svmla_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
+pub fn svmla_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint64_t,
+    op3: svint64_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mla.lane.nxv2i64"
+        )]
+        fn _svmla_lane_s64(
+            op1: svint64_t,
+            op2: svint64_t,
+            op3: svint64_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svmla_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
+pub fn svmla_lane_u16<const IMM_INDEX: i32>(
+    op1: svuint16_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe {
+        svmla_lane_s16::<IMM_INDEX>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
+pub fn svmla_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe {
+        svmla_lane_s32::<IMM_INDEX>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Multiply-add, addend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
+pub fn svmla_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint64_t,
+    op3: svuint64_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe {
+        svmla_lane_s64::<IMM_INDEX>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))]
+pub fn svmlalb_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlalb.lane.nxv4i32"
+        )]
+        fn _svmlalb_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svmlalb_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))]
+pub fn svmlalb_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlalb.lane.nxv2i64"
+        )]
+        fn _svmlalb_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svmlalb_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))]
+pub fn svmlalb_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlalb.lane.nxv4i32"
+        )]
+        fn _svmlalb_lane_u32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe {
+        _svmlalb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))]
+pub fn svmlalb_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlalb.lane.nxv2i64"
+        )]
+        fn _svmlalb_lane_u64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe {
+        _svmlalb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb))]
+pub fn svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv8i16")]
+        fn _svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlalb_s16(op1, op2, op3) }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb))]
+pub fn svmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svmlalb_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb))]
+pub fn svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv4i32")]
+        fn _svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlalb_s32(op1, op2, op3) }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb))]
+pub fn svmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svmlalb_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb))]
+pub fn svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv2i64")]
+        fn _svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlalb_s64(op1, op2, op3) }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalb))]
+pub fn svmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svmlalb_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb))]
+pub fn svmlalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv8i16")]
+        fn _svmlalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb))]
+pub fn svmlalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
+    svmlalb_u16(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb))]
+pub fn svmlalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv4i32")]
+        fn _svmlalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb))]
+pub fn svmlalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
+    svmlalb_u32(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb))]
+pub fn svmlalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv2i64")]
+        fn _svmlalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalb))]
+pub fn svmlalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
+    svmlalb_u64(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))]
+pub fn svmlalt_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlalt.lane.nxv4i32"
+        )]
+        fn _svmlalt_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svmlalt_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))]
+pub fn svmlalt_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlalt.lane.nxv2i64"
+        )]
+        fn _svmlalt_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svmlalt_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))]
+pub fn svmlalt_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlalt.lane.nxv4i32"
+        )]
+        fn _svmlalt_lane_u32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe {
+        _svmlalt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))]
+pub fn svmlalt_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlalt.lane.nxv2i64"
+        )]
+        fn _svmlalt_lane_u64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe {
+        _svmlalt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt))]
+pub fn svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv8i16")]
+        fn _svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlalt_s16(op1, op2, op3) }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt))]
+pub fn svmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svmlalt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt))]
+pub fn svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv4i32")]
+        fn _svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlalt_s32(op1, op2, op3) }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt))]
+pub fn svmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svmlalt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt))]
+pub fn svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv2i64")]
+        fn _svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlalt_s64(op1, op2, op3) }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlalt))]
+pub fn svmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svmlalt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt))]
+pub fn svmlalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv8i16")]
+        fn _svmlalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt))]
+pub fn svmlalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
+    svmlalt_u16(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt))]
+pub fn svmlalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv4i32")]
+        fn _svmlalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt))]
+pub fn svmlalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
+    svmlalt_u32(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt))]
+pub fn svmlalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv2i64")]
+        fn _svmlalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlalt))]
+pub fn svmlalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
+    svmlalt_u64(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
+pub fn svmls_lane_s16<const IMM_INDEX: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mls.lane.nxv8i16"
+        )]
+        fn _svmls_lane_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svmls_lane_s16(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
+pub fn svmls_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mls.lane.nxv4i32"
+        )]
+        fn _svmls_lane_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svmls_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
+pub fn svmls_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint64_t,
+    op3: svint64_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mls.lane.nxv2i64"
+        )]
+        fn _svmls_lane_s64(
+            op1: svint64_t,
+            op2: svint64_t,
+            op3: svint64_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svmls_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
+pub fn svmls_lane_u16<const IMM_INDEX: i32>(
+    op1: svuint16_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe {
+        svmls_lane_s16::<IMM_INDEX>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
+pub fn svmls_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe {
+        svmls_lane_s32::<IMM_INDEX>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract, minuend first"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
+pub fn svmls_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint64_t,
+    op3: svuint64_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe {
+        svmls_lane_s64::<IMM_INDEX>(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))]
+pub fn svmlslb_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlslb.lane.nxv4i32"
+        )]
+        fn _svmlslb_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svmlslb_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))]
+pub fn svmlslb_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlslb.lane.nxv2i64"
+        )]
+        fn _svmlslb_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svmlslb_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))]
+pub fn svmlslb_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlslb.lane.nxv4i32"
+        )]
+        fn _svmlslb_lane_u32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe {
+        _svmlslb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))]
+pub fn svmlslb_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlslb.lane.nxv2i64"
+        )]
+        fn _svmlslb_lane_u64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe {
+        _svmlslb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb))]
+pub fn svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv8i16")]
+        fn _svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlslb_s16(op1, op2, op3) }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb))]
+pub fn svmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svmlslb_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb))]
+pub fn svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv4i32")]
+        fn _svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlslb_s32(op1, op2, op3) }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb))]
+pub fn svmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svmlslb_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb))]
+pub fn svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv2i64")]
+        fn _svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlslb_s64(op1, op2, op3) }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslb))]
+pub fn svmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svmlslb_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb))]
+pub fn svmlslb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv8i16")]
+        fn _svmlslb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlslb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb))]
+pub fn svmlslb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
+    svmlslb_u16(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb))]
+pub fn svmlslb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv4i32")]
+        fn _svmlslb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlslb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb))]
+pub fn svmlslb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
+    svmlslb_u32(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb))]
+pub fn svmlslb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv2i64")]
+        fn _svmlslb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlslb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslb))]
+pub fn svmlslb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
+    svmlslb_u64(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))]
+pub fn svmlslt_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlslt.lane.nxv4i32"
+        )]
+        fn _svmlslt_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svmlslt_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))]
+pub fn svmlslt_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smlslt.lane.nxv2i64"
+        )]
+        fn _svmlslt_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svmlslt_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))]
+pub fn svmlslt_lane_u32<const IMM_INDEX: i32>(
+    op1: svuint32_t,
+    op2: svuint16_t,
+    op3: svuint16_t,
+) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlslt.lane.nxv4i32"
+        )]
+        fn _svmlslt_lane_u32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe {
+        _svmlslt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))]
+pub fn svmlslt_lane_u64<const IMM_INDEX: i32>(
+    op1: svuint64_t,
+    op2: svuint32_t,
+    op3: svuint32_t,
+) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umlslt.lane.nxv2i64"
+        )]
+        fn _svmlslt_lane_u64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe {
+        _svmlslt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX)
+            .as_unsigned()
+    }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt))]
+pub fn svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv8i16")]
+        fn _svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlslt_s16(op1, op2, op3) }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt))]
+pub fn svmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svmlslt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt))]
+pub fn svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv4i32")]
+        fn _svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlslt_s32(op1, op2, op3) }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt))]
+pub fn svmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svmlslt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt))]
+pub fn svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv2i64")]
+        fn _svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlslt_s64(op1, op2, op3) }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smlslt))]
+pub fn svmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svmlslt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt))]
+pub fn svmlslt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv8i16")]
+        fn _svmlslt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmlslt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt))]
+pub fn svmlslt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
+    svmlslt_u16(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt))]
+pub fn svmlslt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv4i32")]
+        fn _svmlslt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmlslt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt))]
+pub fn svmlslt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
+    svmlslt_u32(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt))]
+pub fn svmlslt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv2i64")]
+        fn _svmlslt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmlslt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umlslt))]
+pub fn svmlslt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
+    svmlslt_u64(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Move long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllb))]
+pub fn svmovlb_s16(op: svint8_t) -> svint16_t {
+    svshllb_n_s16::<0>(op)
+}
+#[doc = "Move long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllb))]
+pub fn svmovlb_s32(op: svint16_t) -> svint32_t {
+    svshllb_n_s32::<0>(op)
+}
+#[doc = "Move long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllb))]
+pub fn svmovlb_s64(op: svint32_t) -> svint64_t {
+    svshllb_n_s64::<0>(op)
+}
+#[doc = "Move long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllb))]
+pub fn svmovlb_u16(op: svuint8_t) -> svuint16_t {
+    svshllb_n_u16::<0>(op)
+}
+#[doc = "Move long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllb))]
+pub fn svmovlb_u32(op: svuint16_t) -> svuint32_t {
+    svshllb_n_u32::<0>(op)
+}
+#[doc = "Move long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllb))]
+pub fn svmovlb_u64(op: svuint32_t) -> svuint64_t {
+    svshllb_n_u64::<0>(op)
+}
+#[doc = "Move long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllt))]
+pub fn svmovlt_s16(op: svint8_t) -> svint16_t {
+    svshllt_n_s16::<0>(op)
+}
+#[doc = "Move long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllt))]
+pub fn svmovlt_s32(op: svint16_t) -> svint32_t {
+    svshllt_n_s32::<0>(op)
+}
+#[doc = "Move long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllt))]
+pub fn svmovlt_s64(op: svint32_t) -> svint64_t {
+    svshllt_n_s64::<0>(op)
+}
+#[doc = "Move long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllt))]
+pub fn svmovlt_u16(op: svuint8_t) -> svuint16_t {
+    svshllt_n_u16::<0>(op)
+}
+#[doc = "Move long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllt))]
+pub fn svmovlt_u32(op: svuint16_t) -> svuint32_t {
+    svshllt_n_u32::<0>(op)
+}
+#[doc = "Move long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllt))]
+pub fn svmovlt_u64(op: svuint32_t) -> svuint64_t {
+    svshllt_n_u64::<0>(op)
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))]
+pub fn svmul_lane_f32<const IMM_INDEX: i32>(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmul.lane.nxv4f32"
+        )]
+        fn _svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t, imm_index: i32) -> svfloat32_t;
+    }
+    unsafe { _svmul_lane_f32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))]
+pub fn svmul_lane_f64<const IMM_INDEX: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.fmul.lane.nxv2f64"
+        )]
+        fn _svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t, imm_index: i32) -> svfloat64_t;
+    }
+    unsafe { _svmul_lane_f64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
+pub fn svmul_lane_s16<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mul.lane.nxv8i16"
+        )]
+        fn _svmul_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t;
+    }
+    unsafe { _svmul_lane_s16(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
+pub fn svmul_lane_s32<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mul.lane.nxv4i32"
+        )]
+        fn _svmul_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svmul_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
+pub fn svmul_lane_s64<const IMM_INDEX: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.mul.lane.nxv2i64"
+        )]
+        fn _svmul_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svmul_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
+pub fn svmul_lane_u16<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe { svmul_lane_s16::<IMM_INDEX>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
+pub fn svmul_lane_u32<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe { svmul_lane_s32::<IMM_INDEX>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
+pub fn svmul_lane_u64<const IMM_INDEX: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe { svmul_lane_s64::<IMM_INDEX>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb, IMM_INDEX = 0))]
+pub fn svmullb_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smullb.lane.nxv4i32"
+        )]
+        fn _svmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svmullb_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb, IMM_INDEX = 0))]
+pub fn svmullb_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smullb.lane.nxv2i64"
+        )]
+        fn _svmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svmullb_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb, IMM_INDEX = 0))]
+pub fn svmullb_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umullb.lane.nxv4i32"
+        )]
+        fn _svmullb_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svmullb_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb, IMM_INDEX = 0))]
+pub fn svmullb_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umullb.lane.nxv2i64"
+        )]
+        fn _svmullb_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svmullb_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb))]
+pub fn svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv8i16")]
+        fn _svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmullb_s16(op1, op2) }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb))]
+pub fn svmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svmullb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb))]
+pub fn svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv4i32")]
+        fn _svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmullb_s32(op1, op2) }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb))]
+pub fn svmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svmullb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb))]
+pub fn svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv2i64")]
+        fn _svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmullb_s64(op1, op2) }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullb))]
+pub fn svmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svmullb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb))]
+pub fn svmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv8i16")]
+        fn _svmullb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmullb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb))]
+pub fn svmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svmullb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb))]
+pub fn svmullb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv4i32")]
+        fn _svmullb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmullb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb))]
+pub fn svmullb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svmullb_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb))]
+pub fn svmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv2i64")]
+        fn _svmullb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmullb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullb))]
+pub fn svmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svmullb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt, IMM_INDEX = 0))]
+pub fn svmullt_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smullt.lane.nxv4i32"
+        )]
+        fn _svmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svmullt_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt, IMM_INDEX = 0))]
+pub fn svmullt_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.smullt.lane.nxv2i64"
+        )]
+        fn _svmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svmullt_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt, IMM_INDEX = 0))]
+pub fn svmullt_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umullt.lane.nxv4i32"
+        )]
+        fn _svmullt_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svmullt_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt, IMM_INDEX = 0))]
+pub fn svmullt_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.umullt.lane.nxv2i64"
+        )]
+        fn _svmullt_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svmullt_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt))]
+pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv8i16")]
+        fn _svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmullt_s16(op1, op2) }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt))]
+pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svmullt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt))]
+pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv4i32")]
+        fn _svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmullt_s32(op1, op2) }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt))]
+pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svmullt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt))]
+pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv2i64")]
+        fn _svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmullt_s64(op1, op2) }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(smullt))]
+pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svmullt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt))]
+pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv8i16")]
+        fn _svmullt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svmullt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt))]
+pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svmullt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt))]
+pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv4i32")]
+        fn _svmullt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svmullt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt))]
+pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svmullt_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt))]
+pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv2i64")]
+        fn _svmullt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svmullt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(umullt))]
+pub fn svmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svmullt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv16i8")]
+        fn _svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svnbsl_s8(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svnbsl_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv8i16")]
+        fn _svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svnbsl_s16(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svnbsl_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv4i32")]
+        fn _svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svnbsl_s32(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svnbsl_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv2i64")]
+        fn _svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svnbsl_s64(op1, op2, op3) }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svnbsl_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
+    unsafe { svnbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
+    svnbsl_u8(op1, op2, svdup_n_u8(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t {
+    unsafe { svnbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
+    svnbsl_u16(op1, op2, svdup_n_u16(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe { svnbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svnbsl_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe { svnbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise select"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nbsl))]
+pub fn svnbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svnbsl_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Detect no matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nmatch))]
+pub fn svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv16i8")]
+        fn _svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t;
+    }
+    unsafe { _svnmatch_s8(pg, op1, op2) }
+}
+#[doc = "Detect no matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nmatch))]
+pub fn svnmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv8i16")]
+        fn _svnmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t;
+    }
+    unsafe { _svnmatch_s16(pg.sve_into(), op1, op2).sve_into() }
+}
+#[doc = "Detect no matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nmatch))]
+pub fn svnmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
+    unsafe { svnmatch_s8(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Detect no matching elements"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(nmatch))]
+pub fn svnmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
+    unsafe { svnmatch_s16(pg, op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "Polynomial multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmul))]
+pub fn svpmul_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pmul.nxv16i8")]
+        fn _svpmul_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svpmul_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmul))]
+pub fn svpmul_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svpmul_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.pmullb.pair.nxv16i8"
+        )]
+        fn _svpmullb_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svpmullb_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svpmullb_pair_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.pmullb.pair.nxv4i32"
+        )]
+        fn _svpmullb_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svpmullb_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svpmullb_pair_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.pmullb.pair.nxv2i64"
+        )]
+        fn _svpmullb_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svpmullb_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svpmullb_pair_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u8(op1, op2)) }
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svpmullb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u32(op1, op2)) }
+}
+#[doc = "Polynomial multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullb))]
+pub fn svpmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svpmullb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.pmullt.pair.nxv16i8"
+        )]
+        fn _svpmullt_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svpmullt_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
+    svpmullt_pair_u8(op1, svdup_n_u8(op2))
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.pmullt.pair.nxv4i32"
+        )]
+        fn _svpmullt_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svpmullt_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
+    svpmullt_pair_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.pmullt.pair.nxv2i64"
+        )]
+        fn _svpmullt_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svpmullt_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
+    svpmullt_pair_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u8(op1, op2)) }
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svpmullt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u32(op1, op2)) }
+}
+#[doc = "Polynomial multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-aes")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(pmullt))]
+pub fn svpmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svpmullt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv16i8")]
+        fn _svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqabs_s8_m(inactive, pg, op) }
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svqabs_s8_m(op, pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svqabs_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv8i16")]
+        fn _svqabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqabs_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svqabs_s16_m(op, pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svqabs_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv4i32")]
+        fn _svqabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqabs_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svqabs_s32_m(op, pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svqabs_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv2i64")]
+        fn _svqabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqabs_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svqabs_s64_m(op, pg, op)
+}
+#[doc = "Saturating absolute value"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqabs))]
+pub fn svqabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svqabs_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv16i8")]
+        fn _svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqadd_s8_m(pg, op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqadd_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqadd_s8_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqadd_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqadd_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv8i16")]
+        fn _svqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqadd_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqadd_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqadd_s16_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqadd_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqadd_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv4i32")]
+        fn _svqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqadd_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqadd_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqadd_s32_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqadd_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqadd_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv2i64")]
+        fn _svqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqadd_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqadd_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqadd_s64_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqadd_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqadd))]
+pub fn svqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqadd_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv16i8")]
+        fn _svqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqadd_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svqadd_u8_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqadd_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqadd_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv8i16")]
+        fn _svqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqadd_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svqadd_u16_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqadd_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqadd_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv4i32")]
+        fn _svqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqadd_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svqadd_u32_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqadd_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqadd_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv2i64")]
+        fn _svqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqadd_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svqadd_u64_m(pg, op1, op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqadd_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Saturating add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqadd))]
+pub fn svqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqadd_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
+pub fn svqcadd_s8<const IMM_ROTATION: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqcadd.x.nxv16i8"
+        )]
+        fn _svqcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t;
+    }
+    unsafe { _svqcadd_s8(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Saturating complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
+pub fn svqcadd_s16<const IMM_ROTATION: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqcadd.x.nxv8i16"
+        )]
+        fn _svqcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t;
+    }
+    unsafe { _svqcadd_s16(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Saturating complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
+pub fn svqcadd_s32<const IMM_ROTATION: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqcadd.x.nxv4i32"
+        )]
+        fn _svqcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t;
+    }
+    unsafe { _svqcadd_s32(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Saturating complex add with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
+pub fn svqcadd_s64<const IMM_ROTATION: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqcadd.x.nxv2i64"
+        )]
+        fn _svqcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t;
+    }
+    unsafe { _svqcadd_s64(op1, op2, IMM_ROTATION) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))]
+pub fn svqdmlalb_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv4i32"
+        )]
+        fn _svqdmlalb_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqdmlalb_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))]
+pub fn svqdmlalb_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv2i64"
+        )]
+        fn _svqdmlalb_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqdmlalb_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb))]
+pub fn svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalb.nxv8i16"
+        )]
+        fn _svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmlalb_s16(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb))]
+pub fn svqdmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svqdmlalb_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb))]
+pub fn svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalb.nxv4i32"
+        )]
+        fn _svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmlalb_s32(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb))]
+pub fn svqdmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svqdmlalb_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb))]
+pub fn svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalb.nxv2i64"
+        )]
+        fn _svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmlalb_s64(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalb))]
+pub fn svqdmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svqdmlalb_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating doubling multiply-add long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalbt))]
+pub fn svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalbt.nxv8i16"
+        )]
+        fn _svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmlalbt_s16(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalbt))]
+pub fn svqdmlalbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svqdmlalbt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating doubling multiply-add long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalbt))]
+pub fn svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalbt.nxv4i32"
+        )]
+        fn _svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmlalbt_s32(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalbt))]
+pub fn svqdmlalbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svqdmlalbt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating doubling multiply-add long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalbt))]
+pub fn svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalbt.nxv2i64"
+        )]
+        fn _svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmlalbt_s64(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalbt))]
+pub fn svqdmlalbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svqdmlalbt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))]
+pub fn svqdmlalt_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv4i32"
+        )]
+        fn _svqdmlalt_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqdmlalt_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))]
+pub fn svqdmlalt_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv2i64"
+        )]
+        fn _svqdmlalt_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqdmlalt_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt))]
+pub fn svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalt.nxv8i16"
+        )]
+        fn _svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmlalt_s16(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt))]
+pub fn svqdmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svqdmlalt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt))]
+pub fn svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalt.nxv4i32"
+        )]
+        fn _svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmlalt_s32(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt))]
+pub fn svqdmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svqdmlalt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt))]
+pub fn svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlalt.nxv2i64"
+        )]
+        fn _svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmlalt_s64(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-add long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlalt))]
+pub fn svqdmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svqdmlalt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))]
+pub fn svqdmlslb_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv4i32"
+        )]
+        fn _svqdmlslb_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqdmlslb_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))]
+pub fn svqdmlslb_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv2i64"
+        )]
+        fn _svqdmlslb_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqdmlslb_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb))]
+pub fn svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslb.nxv8i16"
+        )]
+        fn _svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmlslb_s16(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb))]
+pub fn svqdmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svqdmlslb_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb))]
+pub fn svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslb.nxv4i32"
+        )]
+        fn _svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmlslb_s32(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb))]
+pub fn svqdmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svqdmlslb_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb))]
+pub fn svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslb.nxv2i64"
+        )]
+        fn _svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmlslb_s64(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslb))]
+pub fn svqdmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svqdmlslb_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslbt))]
+pub fn svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslbt.nxv8i16"
+        )]
+        fn _svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmlslbt_s16(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslbt))]
+pub fn svqdmlslbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svqdmlslbt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslbt))]
+pub fn svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslbt.nxv4i32"
+        )]
+        fn _svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmlslbt_s32(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslbt))]
+pub fn svqdmlslbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svqdmlslbt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslbt))]
+pub fn svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslbt.nxv2i64"
+        )]
+        fn _svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmlslbt_s64(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslbt))]
+pub fn svqdmlslbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svqdmlslbt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))]
+pub fn svqdmlslt_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv4i32"
+        )]
+        fn _svqdmlslt_lane_s32(
+            op1: svint32_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqdmlslt_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))]
+pub fn svqdmlslt_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv2i64"
+        )]
+        fn _svqdmlslt_lane_s64(
+            op1: svint64_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqdmlslt_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt))]
+pub fn svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslt.nxv8i16"
+        )]
+        fn _svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmlslt_s16(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt))]
+pub fn svqdmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
+    svqdmlslt_s16(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt))]
+pub fn svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslt.nxv4i32"
+        )]
+        fn _svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmlslt_s32(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt))]
+pub fn svqdmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
+    svqdmlslt_s32(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt))]
+pub fn svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmlslt.nxv2i64"
+        )]
+        fn _svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmlslt_s64(op1, op2, op3) }
+}
+#[doc = "Saturating doubling multiply-subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmlslt))]
+pub fn svqdmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
+    svqdmlslt_s64(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))]
+pub fn svqdmulh_lane_s16<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv8i16"
+        )]
+        fn _svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t;
+    }
+    unsafe { _svqdmulh_lane_s16(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))]
+pub fn svqdmulh_lane_s32<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv4i32"
+        )]
+        fn _svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svqdmulh_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))]
+pub fn svqdmulh_lane_s64<const IMM_INDEX: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv2i64"
+        )]
+        fn _svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svqdmulh_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.nxv16i8"
+        )]
+        fn _svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqdmulh_s8(op1, op2) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
+    svqdmulh_s8(op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.nxv8i16"
+        )]
+        fn _svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqdmulh_s16(op1, op2) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
+    svqdmulh_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.nxv4i32"
+        )]
+        fn _svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqdmulh_s32(op1, op2) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
+    svqdmulh_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmulh.nxv2i64"
+        )]
+        fn _svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqdmulh_s64(op1, op2) }
+}
+#[doc = "Saturating doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmulh))]
+pub fn svqdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
+    svqdmulh_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))]
+pub fn svqdmullb_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv4i32"
+        )]
+        fn _svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svqdmullb_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))]
+pub fn svqdmullb_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv2i64"
+        )]
+        fn _svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svqdmullb_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb))]
+pub fn svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullb.nxv8i16"
+        )]
+        fn _svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmullb_s16(op1, op2) }
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb))]
+pub fn svqdmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svqdmullb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb))]
+pub fn svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullb.nxv4i32"
+        )]
+        fn _svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmullb_s32(op1, op2) }
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb))]
+pub fn svqdmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svqdmullb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb))]
+pub fn svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullb.nxv2i64"
+        )]
+        fn _svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmullb_s64(op1, op2) }
+}
+#[doc = "Saturating doubling multiply long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullb))]
+pub fn svqdmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svqdmullb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))]
+pub fn svqdmullt_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv4i32"
+        )]
+        fn _svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svqdmullt_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))]
+pub fn svqdmullt_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv2i64"
+        )]
+        fn _svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svqdmullt_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt))]
+pub fn svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullt.nxv8i16"
+        )]
+        fn _svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svqdmullt_s16(op1, op2) }
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt))]
+pub fn svqdmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svqdmullt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt))]
+pub fn svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullt.nxv4i32"
+        )]
+        fn _svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svqdmullt_s32(op1, op2) }
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt))]
+pub fn svqdmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svqdmullt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt))]
+pub fn svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqdmullt.nxv2i64"
+        )]
+        fn _svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svqdmullt_s64(op1, op2) }
+}
+#[doc = "Saturating doubling multiply long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqdmullt))]
+pub fn svqdmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svqdmullt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv16i8")]
+        fn _svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqneg_s8_m(inactive, pg, op) }
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svqneg_s8_m(op, pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
+    svqneg_s8_m(svdup_n_s8(0), pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv8i16")]
+        fn _svqneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqneg_s16_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svqneg_s16_m(op, pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
+    svqneg_s16_m(svdup_n_s16(0), pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv4i32")]
+        fn _svqneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqneg_s32_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svqneg_s32_m(op, pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
+    svqneg_s32_m(svdup_n_s32(0), pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv2i64")]
+        fn _svqneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqneg_s64_m(inactive, pg.sve_into(), op) }
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svqneg_s64_m(op, pg, op)
+}
+#[doc = "Saturating negate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqneg))]
+pub fn svqneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
+    svqneg_s64_m(svdup_n_s64(0), pg, op)
+}
+#[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svqrdcmlah_lane_s16<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16"
+        )]
+        fn _svqrdcmlah_lane_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svqrdcmlah_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))]
+pub fn svqrdcmlah_lane_s32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32"
+        )]
+        fn _svqrdcmlah_lane_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            imm_index: i32,
+            imm_rotation: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqrdcmlah_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) }
+}
+#[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
+pub fn svqrdcmlah_s8<const IMM_ROTATION: i32>(
+    op1: svint8_t,
+    op2: svint8_t,
+    op3: svint8_t,
+) -> svint8_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv16i8"
+        )]
+        fn _svqrdcmlah_s8(
+            op1: svint8_t,
+            op2: svint8_t,
+            op3: svint8_t,
+            imm_rotation: i32,
+        ) -> svint8_t;
+    }
+    unsafe { _svqrdcmlah_s8(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
+pub fn svqrdcmlah_s16<const IMM_ROTATION: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv8i16"
+        )]
+        fn _svqrdcmlah_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            imm_rotation: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svqrdcmlah_s16(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
+pub fn svqrdcmlah_s32<const IMM_ROTATION: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv4i32"
+        )]
+        fn _svqrdcmlah_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            imm_rotation: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqrdcmlah_s32(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
+pub fn svqrdcmlah_s64<const IMM_ROTATION: i32>(
+    op1: svint64_t,
+    op2: svint64_t,
+    op3: svint64_t,
+) -> svint64_t {
+    static_assert!(
+        IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270
+    );
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv2i64"
+        )]
+        fn _svqrdcmlah_s64(
+            op1: svint64_t,
+            op2: svint64_t,
+            op3: svint64_t,
+            imm_rotation: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqrdcmlah_s64(op1, op2, op3, IMM_ROTATION) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))]
+pub fn svqrdmlah_lane_s16<const IMM_INDEX: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv8i16"
+        )]
+        fn _svqrdmlah_lane_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svqrdmlah_lane_s16(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))]
+pub fn svqrdmlah_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv4i32"
+        )]
+        fn _svqrdmlah_lane_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqrdmlah_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))]
+pub fn svqrdmlah_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint64_t,
+    op3: svint64_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv2i64"
+        )]
+        fn _svqrdmlah_lane_s64(
+            op1: svint64_t,
+            op2: svint64_t,
+            op3: svint64_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqrdmlah_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.nxv16i8"
+        )]
+        fn _svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqrdmlah_s8(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svqrdmlah_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.nxv8i16"
+        )]
+        fn _svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqrdmlah_s16(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svqrdmlah_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.nxv4i32"
+        )]
+        fn _svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqrdmlah_s32(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svqrdmlah_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlah.nxv2i64"
+        )]
+        fn _svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqrdmlah_s64(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-add high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlah))]
+pub fn svqrdmlah_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svqrdmlah_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))]
+pub fn svqrdmlsh_lane_s16<const IMM_INDEX: i32>(
+    op1: svint16_t,
+    op2: svint16_t,
+    op3: svint16_t,
+) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16"
+        )]
+        fn _svqrdmlsh_lane_s16(
+            op1: svint16_t,
+            op2: svint16_t,
+            op3: svint16_t,
+            IMM_INDEX: i32,
+        ) -> svint16_t;
+    }
+    unsafe { _svqrdmlsh_lane_s16(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))]
+pub fn svqrdmlsh_lane_s32<const IMM_INDEX: i32>(
+    op1: svint32_t,
+    op2: svint32_t,
+    op3: svint32_t,
+) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32"
+        )]
+        fn _svqrdmlsh_lane_s32(
+            op1: svint32_t,
+            op2: svint32_t,
+            op3: svint32_t,
+            IMM_INDEX: i32,
+        ) -> svint32_t;
+    }
+    unsafe { _svqrdmlsh_lane_s32(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))]
+pub fn svqrdmlsh_lane_s64<const IMM_INDEX: i32>(
+    op1: svint64_t,
+    op2: svint64_t,
+    op3: svint64_t,
+) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64"
+        )]
+        fn _svqrdmlsh_lane_s64(
+            op1: svint64_t,
+            op2: svint64_t,
+            op3: svint64_t,
+            IMM_INDEX: i32,
+        ) -> svint64_t;
+    }
+    unsafe { _svqrdmlsh_lane_s64(op1, op2, op3, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.nxv16i8"
+        )]
+        fn _svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqrdmlsh_s8(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
+    svqrdmlsh_s8(op1, op2, svdup_n_s8(op3))
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.nxv8i16"
+        )]
+        fn _svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqrdmlsh_s16(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
+    svqrdmlsh_s16(op1, op2, svdup_n_s16(op3))
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.nxv4i32"
+        )]
+        fn _svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqrdmlsh_s32(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
+    svqrdmlsh_s32(op1, op2, svdup_n_s32(op3))
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmlsh.nxv2i64"
+        )]
+        fn _svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqrdmlsh_s64(op1, op2, op3) }
+}
+#[doc = "Saturating rounding doubling multiply-subtract high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmlsh))]
+pub fn svqrdmlsh_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
+    svqrdmlsh_s64(op1, op2, svdup_n_s64(op3))
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))]
+pub fn svqrdmulh_lane_s16<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM_INDEX, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv8i16"
+        )]
+        fn _svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t;
+    }
+    unsafe { _svqrdmulh_lane_s16(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))]
+pub fn svqrdmulh_lane_s32<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM_INDEX, 0..=3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv4i32"
+        )]
+        fn _svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t;
+    }
+    unsafe { _svqrdmulh_lane_s32(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))]
+pub fn svqrdmulh_lane_s64<const IMM_INDEX: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM_INDEX, 0..=1);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv2i64"
+        )]
+        fn _svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t;
+    }
+    unsafe { _svqrdmulh_lane_s64(op1, op2, IMM_INDEX) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.nxv16i8"
+        )]
+        fn _svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqrdmulh_s8(op1, op2) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
+    svqrdmulh_s8(op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.nxv8i16"
+        )]
+        fn _svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqrdmulh_s16(op1, op2) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
+    svqrdmulh_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.nxv4i32"
+        )]
+        fn _svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqrdmulh_s32(op1, op2) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
+    svqrdmulh_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrdmulh.nxv2i64"
+        )]
+        fn _svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqrdmulh_s64(op1, op2) }
+}
+#[doc = "Saturating rounding doubling multiply high"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrdmulh))]
+pub fn svqrdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
+    svqrdmulh_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv16i8")]
+        fn _svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqrshl_s8_m(pg, op1, op2) }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqrshl_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqrshl_s8_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqrshl_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqrshl_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv8i16")]
+        fn _svqrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqrshl_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqrshl_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqrshl_s16_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqrshl_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqrshl_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv4i32")]
+        fn _svqrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqrshl_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqrshl_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqrshl_s32_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqrshl_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqrshl_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv2i64")]
+        fn _svqrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqrshl_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqrshl_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqrshl_s64_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqrshl_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshl))]
+pub fn svqrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqrshl_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv16i8")]
+        fn _svqrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svqrshl_u8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svqrshl_u8_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svqrshl_u8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svqrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svqrshl_u8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv8i16")]
+        fn _svqrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svqrshl_u16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svqrshl_u16_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svqrshl_u16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svqrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svqrshl_u16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv4i32")]
+        fn _svqrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svqrshl_u32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svqrshl_u32_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svqrshl_u32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svqrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svqrshl_u32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv2i64")]
+        fn _svqrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svqrshl_u64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svqrshl_u64_m(pg, op1, op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svqrshl_u64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svqrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Saturating rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshl))]
+pub fn svqrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svqrshl_u64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))]
+pub fn svqrshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrnb.nxv8i16"
+        )]
+        fn _svqrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqrshrnb_n_s16(op1, IMM2) }
+}
+#[doc = "Saturating rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))]
+pub fn svqrshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrnb.nxv4i32"
+        )]
+        fn _svqrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqrshrnb_n_s32(op1, IMM2) }
+}
+#[doc = "Saturating rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))]
+pub fn svqrshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrnb.nxv2i64"
+        )]
+        fn _svqrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqrshrnb_n_s64(op1, IMM2) }
+}
+#[doc = "Saturating rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))]
+pub fn svqrshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqrshrnb.nxv8i16"
+        )]
+        fn _svqrshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqrshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))]
+pub fn svqrshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqrshrnb.nxv4i32"
+        )]
+        fn _svqrshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqrshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))]
+pub fn svqrshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqrshrnb.nxv2i64"
+        )]
+        fn _svqrshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqrshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))]
+pub fn svqrshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrnt.nxv8i16"
+        )]
+        fn _svqrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqrshrnt_n_s16(even, op1, IMM2) }
+}
+#[doc = "Saturating rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))]
+pub fn svqrshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrnt.nxv4i32"
+        )]
+        fn _svqrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqrshrnt_n_s32(even, op1, IMM2) }
+}
+#[doc = "Saturating rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))]
+pub fn svqrshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrnt.nxv2i64"
+        )]
+        fn _svqrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqrshrnt_n_s64(even, op1, IMM2) }
+}
+#[doc = "Saturating rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))]
+pub fn svqrshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqrshrnt.nxv8i16"
+        )]
+        fn _svqrshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqrshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))]
+pub fn svqrshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqrshrnt.nxv4i32"
+        )]
+        fn _svqrshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqrshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))]
+pub fn svqrshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqrshrnt.nxv2i64"
+        )]
+        fn _svqrshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqrshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))]
+pub fn svqrshrunb_n_s16<const IMM2: i32>(op1: svint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrunb.nxv8i16"
+        )]
+        fn _svqrshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqrshrunb_n_s16(op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))]
+pub fn svqrshrunb_n_s32<const IMM2: i32>(op1: svint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrunb.nxv4i32"
+        )]
+        fn _svqrshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqrshrunb_n_s32(op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))]
+pub fn svqrshrunb_n_s64<const IMM2: i32>(op1: svint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrunb.nxv2i64"
+        )]
+        fn _svqrshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqrshrunb_n_s64(op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))]
+pub fn svqrshrunt_n_s16<const IMM2: i32>(even: svuint8_t, op1: svint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrunt.nxv8i16"
+        )]
+        fn _svqrshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqrshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))]
+pub fn svqrshrunt_n_s32<const IMM2: i32>(even: svuint16_t, op1: svint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrunt.nxv4i32"
+        )]
+        fn _svqrshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqrshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating rounding shift right unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))]
+pub fn svqrshrunt_n_s64<const IMM2: i32>(even: svuint32_t, op1: svint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqrshrunt.nxv2i64"
+        )]
+        fn _svqrshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqrshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv16i8")]
+        fn _svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqshl_s8_m(pg, op1, op2) }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqshl_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqshl_s8_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqshl_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqshl_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv8i16")]
+        fn _svqshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqshl_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqshl_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqshl_s16_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqshl_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqshl_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv4i32")]
+        fn _svqshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqshl_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqshl_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqshl_s32_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqshl_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqshl_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv2i64")]
+        fn _svqshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqshl_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqshl_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqshl_s64_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqshl_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshl))]
+pub fn svqshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqshl_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv16i8")]
+        fn _svqshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svqshl_u8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svqshl_u8_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svqshl_u8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svqshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svqshl_u8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv8i16")]
+        fn _svqshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svqshl_u16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svqshl_u16_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svqshl_u16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svqshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svqshl_u16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv4i32")]
+        fn _svqshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svqshl_u32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svqshl_u32_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svqshl_u32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svqshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svqshl_u32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv2i64")]
+        fn _svqshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svqshl_u64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svqshl_u64_m(pg, op1, op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svqshl_u64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svqshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Saturating shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshl))]
+pub fn svqshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svqshl_u64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s8_m<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svuint8_t {
+    static_assert_range!(IMM2, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv16i8")]
+        fn _svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshlu_n_s8_m(pg, op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s8_x<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svuint8_t {
+    svqshlu_n_s8_m::<IMM2>(pg, op1)
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s8_z<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svuint8_t {
+    svqshlu_n_s8_m::<IMM2>(pg, svsel_s8(pg, op1, svdup_n_s8(0)))
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s16_m<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svuint16_t {
+    static_assert_range!(IMM2, 0..=15);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv8i16")]
+        fn _svqshlu_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshlu_n_s16_m(pg.sve_into(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s16_x<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svuint16_t {
+    svqshlu_n_s16_m::<IMM2>(pg, op1)
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s16_z<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svuint16_t {
+    svqshlu_n_s16_m::<IMM2>(pg, svsel_s16(pg, op1, svdup_n_s16(0)))
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s32_m<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svuint32_t {
+    static_assert_range!(IMM2, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv4i32")]
+        fn _svqshlu_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshlu_n_s32_m(pg.sve_into(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s32_x<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svuint32_t {
+    svqshlu_n_s32_m::<IMM2>(pg, op1)
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s32_z<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svuint32_t {
+    svqshlu_n_s32_m::<IMM2>(pg, svsel_s32(pg, op1, svdup_n_s32(0)))
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s64_m<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svuint64_t {
+    static_assert_range!(IMM2, 0..=63);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv2i64")]
+        fn _svqshlu_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svqshlu_n_s64_m(pg.sve_into(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s64_x<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svuint64_t {
+    svqshlu_n_s64_m::<IMM2>(pg, op1)
+}
+#[doc = "Saturating shift left unsigned"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
+pub fn svqshlu_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svuint64_t {
+    svqshlu_n_s64_m::<IMM2>(pg, svsel_s64(pg, op1, svdup_n_s64(0)))
+}
+#[doc = "Saturating shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))]
+pub fn svqshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrnb.nxv8i16"
+        )]
+        fn _svqshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshrnb_n_s16(op1, IMM2) }
+}
+#[doc = "Saturating shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))]
+pub fn svqshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrnb.nxv4i32"
+        )]
+        fn _svqshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshrnb_n_s32(op1, IMM2) }
+}
+#[doc = "Saturating shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))]
+pub fn svqshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrnb.nxv2i64"
+        )]
+        fn _svqshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshrnb_n_s64(op1, IMM2) }
+}
+#[doc = "Saturating shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))]
+pub fn svqshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqshrnb.nxv8i16"
+        )]
+        fn _svqshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))]
+pub fn svqshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqshrnb.nxv4i32"
+        )]
+        fn _svqshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))]
+pub fn svqshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqshrnb.nxv2i64"
+        )]
+        fn _svqshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))]
+pub fn svqshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrnt.nxv8i16"
+        )]
+        fn _svqshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshrnt_n_s16(even, op1, IMM2) }
+}
+#[doc = "Saturating shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))]
+pub fn svqshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrnt.nxv4i32"
+        )]
+        fn _svqshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshrnt_n_s32(even, op1, IMM2) }
+}
+#[doc = "Saturating shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))]
+pub fn svqshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrnt.nxv2i64"
+        )]
+        fn _svqshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshrnt_n_s64(even, op1, IMM2) }
+}
+#[doc = "Saturating shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))]
+pub fn svqshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqshrnt.nxv8i16"
+        )]
+        fn _svqshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))]
+pub fn svqshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqshrnt.nxv4i32"
+        )]
+        fn _svqshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))]
+pub fn svqshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uqshrnt.nxv2i64"
+        )]
+        fn _svqshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))]
+pub fn svqshrunb_n_s16<const IMM2: i32>(op1: svint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrunb.nxv8i16"
+        )]
+        fn _svqshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshrunb_n_s16(op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))]
+pub fn svqshrunb_n_s32<const IMM2: i32>(op1: svint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrunb.nxv4i32"
+        )]
+        fn _svqshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshrunb_n_s32(op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))]
+pub fn svqshrunb_n_s64<const IMM2: i32>(op1: svint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrunb.nxv2i64"
+        )]
+        fn _svqshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshrunb_n_s64(op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))]
+pub fn svqshrunt_n_s16<const IMM2: i32>(even: svuint8_t, op1: svint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrunt.nxv8i16"
+        )]
+        fn _svqshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svqshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))]
+pub fn svqshrunt_n_s32<const IMM2: i32>(even: svuint16_t, op1: svint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrunt.nxv4i32"
+        )]
+        fn _svqshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svqshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating shift right unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))]
+pub fn svqshrunt_n_s64<const IMM2: i32>(even: svuint32_t, op1: svint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqshrunt.nxv2i64"
+        )]
+        fn _svqshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svqshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv16i8")]
+        fn _svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqsub_s8_m(pg, op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqsub_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqsub_s8_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqsub_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqsub_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv8i16")]
+        fn _svqsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqsub_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqsub_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqsub_s16_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqsub_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqsub_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv4i32")]
+        fn _svqsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqsub_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqsub_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqsub_s32_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqsub_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqsub_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv2i64")]
+        fn _svqsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqsub_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqsub_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqsub_s64_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqsub_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsub))]
+pub fn svqsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqsub_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv16i8")]
+        fn _svqsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsub_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svqsub_u8_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsub_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svqsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsub_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv8i16")]
+        fn _svqsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsub_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svqsub_u16_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsub_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svqsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsub_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv4i32")]
+        fn _svqsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsub_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svqsub_u32_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsub_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svqsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsub_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv2i64")]
+        fn _svqsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsub_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svqsub_u64_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsub_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svqsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Saturating subtract"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsub))]
+pub fn svqsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsub_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv16i8")]
+        fn _svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqsubr_s8_m(pg, op1, op2) }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqsubr_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqsubr_s8_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqsubr_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svqsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svqsubr_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv8i16")]
+        fn _svqsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqsubr_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqsubr_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqsubr_s16_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqsubr_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svqsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svqsubr_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv4i32")]
+        fn _svqsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqsubr_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqsubr_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqsubr_s32_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqsubr_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svqsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svqsubr_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv2i64")]
+        fn _svqsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqsubr_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqsubr_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqsubr_s64_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqsubr_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svqsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqsubr))]
+pub fn svqsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svqsubr_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv16i8")]
+        fn _svqsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svqsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsubr_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svqsubr_u8_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsubr_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svqsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svqsubr_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv8i16")]
+        fn _svqsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svqsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsubr_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svqsubr_u16_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsubr_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svqsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svqsubr_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv4i32")]
+        fn _svqsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svqsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsubr_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svqsubr_u32_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsubr_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svqsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svqsubr_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv2i64")]
+        fn _svqsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svqsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsubr_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svqsubr_u64_m(pg, op1, op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsubr_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svqsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Saturating subtract reversed"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqsubr))]
+pub fn svqsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svqsubr_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating extract narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtnb))]
+pub fn svqxtnb_s16(op: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv8i16")]
+        fn _svqxtnb_s16(op: svint16_t) -> svint8_t;
+    }
+    unsafe { _svqxtnb_s16(op) }
+}
+#[doc = "Saturating extract narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtnb))]
+pub fn svqxtnb_s32(op: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv4i32")]
+        fn _svqxtnb_s32(op: svint32_t) -> svint16_t;
+    }
+    unsafe { _svqxtnb_s32(op) }
+}
+#[doc = "Saturating extract narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtnb))]
+pub fn svqxtnb_s64(op: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv2i64")]
+        fn _svqxtnb_s64(op: svint64_t) -> svint32_t;
+    }
+    unsafe { _svqxtnb_s64(op) }
+}
+#[doc = "Saturating extract narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqxtnb))]
+pub fn svqxtnb_u16(op: svuint16_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv8i16")]
+        fn _svqxtnb_u16(op: svint16_t) -> svint8_t;
+    }
+    unsafe { _svqxtnb_u16(op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating extract narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqxtnb))]
+pub fn svqxtnb_u32(op: svuint32_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv4i32")]
+        fn _svqxtnb_u32(op: svint32_t) -> svint16_t;
+    }
+    unsafe { _svqxtnb_u32(op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating extract narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqxtnb))]
+pub fn svqxtnb_u64(op: svuint64_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv2i64")]
+        fn _svqxtnb_u64(op: svint64_t) -> svint32_t;
+    }
+    unsafe { _svqxtnb_u64(op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating extract narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtnt))]
+pub fn svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv8i16")]
+        fn _svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t;
+    }
+    unsafe { _svqxtnt_s16(even, op) }
+}
+#[doc = "Saturating extract narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtnt))]
+pub fn svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv4i32")]
+        fn _svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t;
+    }
+    unsafe { _svqxtnt_s32(even, op) }
+}
+#[doc = "Saturating extract narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtnt))]
+pub fn svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv2i64")]
+        fn _svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t;
+    }
+    unsafe { _svqxtnt_s64(even, op) }
+}
+#[doc = "Saturating extract narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqxtnt))]
+pub fn svqxtnt_u16(even: svuint8_t, op: svuint16_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv8i16")]
+        fn _svqxtnt_u16(even: svint8_t, op: svint16_t) -> svint8_t;
+    }
+    unsafe { _svqxtnt_u16(even.as_signed(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating extract narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqxtnt))]
+pub fn svqxtnt_u32(even: svuint16_t, op: svuint32_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv4i32")]
+        fn _svqxtnt_u32(even: svint16_t, op: svint32_t) -> svint16_t;
+    }
+    unsafe { _svqxtnt_u32(even.as_signed(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating extract narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uqxtnt))]
+pub fn svqxtnt_u64(even: svuint32_t, op: svuint64_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv2i64")]
+        fn _svqxtnt_u64(even: svint32_t, op: svint64_t) -> svint32_t;
+    }
+    unsafe { _svqxtnt_u64(even.as_signed(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating extract unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtunb))]
+pub fn svqxtunb_s16(op: svint16_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqxtunb.nxv8i16"
+        )]
+        fn _svqxtunb_s16(op: svint16_t) -> svint8_t;
+    }
+    unsafe { _svqxtunb_s16(op).as_unsigned() }
+}
+#[doc = "Saturating extract unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtunb))]
+pub fn svqxtunb_s32(op: svint32_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqxtunb.nxv4i32"
+        )]
+        fn _svqxtunb_s32(op: svint32_t) -> svint16_t;
+    }
+    unsafe { _svqxtunb_s32(op).as_unsigned() }
+}
+#[doc = "Saturating extract unsigned narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtunb))]
+pub fn svqxtunb_s64(op: svint64_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqxtunb.nxv2i64"
+        )]
+        fn _svqxtunb_s64(op: svint64_t) -> svint32_t;
+    }
+    unsafe { _svqxtunb_s64(op).as_unsigned() }
+}
+#[doc = "Saturating extract unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtunt))]
+pub fn svqxtunt_s16(even: svuint8_t, op: svint16_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqxtunt.nxv8i16"
+        )]
+        fn _svqxtunt_s16(even: svint8_t, op: svint16_t) -> svint8_t;
+    }
+    unsafe { _svqxtunt_s16(even.as_signed(), op).as_unsigned() }
+}
+#[doc = "Saturating extract unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtunt))]
+pub fn svqxtunt_s32(even: svuint16_t, op: svint32_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqxtunt.nxv4i32"
+        )]
+        fn _svqxtunt_s32(even: svint16_t, op: svint32_t) -> svint16_t;
+    }
+    unsafe { _svqxtunt_s32(even.as_signed(), op).as_unsigned() }
+}
+#[doc = "Saturating extract unsigned narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sqxtunt))]
+pub fn svqxtunt_s64(even: svuint32_t, op: svint64_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sqxtunt.nxv2i64"
+        )]
+        fn _svqxtunt_s64(even: svint32_t, op: svint64_t) -> svint32_t;
+    }
+    unsafe { _svqxtunt_s64(even.as_signed(), op).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.raddhnb.nxv8i16"
+        )]
+        fn _svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svraddhnb_s16(op1, op2) }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
+    svraddhnb_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.raddhnb.nxv4i32"
+        )]
+        fn _svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svraddhnb_s32(op1, op2) }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
+    svraddhnb_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.raddhnb.nxv2i64"
+        )]
+        fn _svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svraddhnb_s64(op1, op2) }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
+    svraddhnb_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svraddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
+    svraddhnb_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svraddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
+    svraddhnb_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svraddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnb))]
+pub fn svraddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
+    svraddhnb_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.raddhnt.nxv8i16"
+        )]
+        fn _svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svraddhnt_s16(even, op1, op2) }
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
+    svraddhnt_s16(even, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.raddhnt.nxv4i32"
+        )]
+        fn _svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svraddhnt_s32(even, op1, op2) }
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
+    svraddhnt_s32(even, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.raddhnt.nxv2i64"
+        )]
+        fn _svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svraddhnt_s64(even, op1, op2) }
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
+    svraddhnt_s64(even, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svraddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t {
+    svraddhnt_u16(even, op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svraddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t {
+    svraddhnt_u32(even, op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svraddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding add narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(raddhnt))]
+pub fn svraddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t {
+    svraddhnt_u64(even, op1, svdup_n_u64(op2))
+}
+#[doc = "Bitwise rotate left by 1 and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-sha3")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rax1))]
+pub fn svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rax1")]
+        fn _svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrax1_s64(op1, op2) }
+}
+#[doc = "Bitwise rotate left by 1 and exclusive OR"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-sha3")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rax1))]
+pub fn svrax1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe { svrax1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Reciprocal estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urecpe))]
+pub fn svrecpe_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urecpe.nxv4i32")]
+        fn _svrecpe_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrecpe_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Reciprocal estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urecpe))]
+pub fn svrecpe_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrecpe_u32_m(op, pg, op)
+}
+#[doc = "Reciprocal estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urecpe))]
+pub fn svrecpe_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrecpe_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv16i8")]
+        fn _svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svrhadd_s8_m(pg, op1, op2) }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svrhadd_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svrhadd_s8_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svrhadd_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svrhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svrhadd_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv8i16")]
+        fn _svrhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrhadd_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svrhadd_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svrhadd_s16_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svrhadd_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svrhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svrhadd_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv4i32")]
+        fn _svrhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrhadd_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svrhadd_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svrhadd_s32_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svrhadd_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svrhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svrhadd_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv2i64")]
+        fn _svrhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrhadd_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svrhadd_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svrhadd_s64_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svrhadd_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svrhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srhadd))]
+pub fn svrhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svrhadd_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv16i8")]
+        fn _svrhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svrhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svrhadd_u8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svrhadd_u8_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svrhadd_u8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    svrhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
+    svrhadd_u8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv8i16")]
+        fn _svrhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svrhadd_u16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svrhadd_u16_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svrhadd_u16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    svrhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
+    svrhadd_u16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv4i32")]
+        fn _svrhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svrhadd_u32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svrhadd_u32_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svrhadd_u32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    svrhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
+    svrhadd_u32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv2i64")]
+        fn _svrhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svrhadd_u64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svrhadd_u64_m(pg, op1, op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svrhadd_u64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    svrhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Rounding halving add"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urhadd))]
+pub fn svrhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
+    svrhadd_u64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv16i8")]
+        fn _svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svrshl_s8_m(pg, op1, op2) }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svrshl_s8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svrshl_s8_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svrshl_s8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
+    svrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
+    svrshl_s8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv8i16")]
+        fn _svrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrshl_s16_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svrshl_s16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svrshl_s16_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svrshl_s16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
+    svrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
+    svrshl_s16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv4i32")]
+        fn _svrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrshl_s32_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svrshl_s32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svrshl_s32_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svrshl_s32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
+    svrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
+    svrshl_s32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv2i64")]
+        fn _svrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrshl_s64_m(pg.sve_into(), op1, op2) }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svrshl_s64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svrshl_s64_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svrshl_s64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
+    svrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshl))]
+pub fn svrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
+    svrshl_s64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv16i8")]
+        fn _svrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svrshl_u8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svrshl_u8_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svrshl_u8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svrshl_u8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv8i16")]
+        fn _svrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svrshl_u16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svrshl_u16_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svrshl_u16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svrshl_u16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv4i32")]
+        fn _svrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svrshl_u32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svrshl_u32_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svrshl_u32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svrshl_u32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv2i64")]
+        fn _svrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svrshl_u64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svrshl_u64_m(pg, op1, op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svrshl_u64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Rounding shift left"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshl))]
+pub fn svrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svrshl_u64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s8_m<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv16i8")]
+        fn _svrshr_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svrshr_n_s8_m(pg, op1, IMM2) }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s8_x<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
+    svrshr_n_s8_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s8_z<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
+    svrshr_n_s8_m::<IMM2>(pg, svsel_s8(pg, op1, svdup_n_s8(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s16_m<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv8i16")]
+        fn _svrshr_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svrshr_n_s16_m(pg.sve_into(), op1, IMM2) }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s16_x<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_t {
+    svrshr_n_s16_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s16_z<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_t {
+    svrshr_n_s16_m::<IMM2>(pg, svsel_s16(pg, op1, svdup_n_s16(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s32_m<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv4i32")]
+        fn _svrshr_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svrshr_n_s32_m(pg.sve_into(), op1, IMM2) }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s32_x<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_t {
+    svrshr_n_s32_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s32_z<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_t {
+    svrshr_n_s32_m::<IMM2>(pg, svsel_s32(pg, op1, svdup_n_s32(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s64_m<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_t {
+    static_assert_range!(IMM2, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv2i64")]
+        fn _svrshr_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svrshr_n_s64_m(pg.sve_into(), op1, IMM2) }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s64_x<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_t {
+    svrshr_n_s64_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
+pub fn svrshr_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_t {
+    svrshr_n_s64_m::<IMM2>(pg, svsel_s64(pg, op1, svdup_n_s64(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u8_m<const IMM2: i32>(pg: svbool_t, op1: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv16i8")]
+        fn _svrshr_n_u8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svrshr_n_u8_m(pg, op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u8_x<const IMM2: i32>(pg: svbool_t, op1: svuint8_t) -> svuint8_t {
+    svrshr_n_u8_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u8_z<const IMM2: i32>(pg: svbool_t, op1: svuint8_t) -> svuint8_t {
+    svrshr_n_u8_m::<IMM2>(pg, svsel_u8(pg, op1, svdup_n_u8(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u16_m<const IMM2: i32>(pg: svbool_t, op1: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv8i16")]
+        fn _svrshr_n_u16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svrshr_n_u16_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u16_x<const IMM2: i32>(pg: svbool_t, op1: svuint16_t) -> svuint16_t {
+    svrshr_n_u16_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u16_z<const IMM2: i32>(pg: svbool_t, op1: svuint16_t) -> svuint16_t {
+    svrshr_n_u16_m::<IMM2>(pg, svsel_u16(pg, op1, svdup_n_u16(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u32_m<const IMM2: i32>(pg: svbool_t, op1: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv4i32")]
+        fn _svrshr_n_u32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svrshr_n_u32_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u32_x<const IMM2: i32>(pg: svbool_t, op1: svuint32_t) -> svuint32_t {
+    svrshr_n_u32_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u32_z<const IMM2: i32>(pg: svbool_t, op1: svuint32_t) -> svuint32_t {
+    svrshr_n_u32_m::<IMM2>(pg, svsel_u32(pg, op1, svdup_n_u32(0)))
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u64_m<const IMM2: i32>(pg: svbool_t, op1: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM2, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv2i64")]
+        fn _svrshr_n_u64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svrshr_n_u64_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u64_x<const IMM2: i32>(pg: svbool_t, op1: svuint64_t) -> svuint64_t {
+    svrshr_n_u64_m::<IMM2>(pg, op1)
+}
+#[doc = "Rounding shift right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
+pub fn svrshr_n_u64_z<const IMM2: i32>(pg: svbool_t, op1: svuint64_t) -> svuint64_t {
+    svrshr_n_u64_m::<IMM2>(pg, svsel_u64(pg, op1, svdup_n_u64(0)))
+}
+#[doc = "Rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
+pub fn svrshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv8i16")]
+        fn _svrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svrshrnb_n_s16(op1, IMM2) }
+}
+#[doc = "Rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
+pub fn svrshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv4i32")]
+        fn _svrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svrshrnb_n_s32(op1, IMM2) }
+}
+#[doc = "Rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
+pub fn svrshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv2i64")]
+        fn _svrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svrshrnb_n_s64(op1, IMM2) }
+}
+#[doc = "Rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
+pub fn svrshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe { svrshrnb_n_s16::<IMM2>(op1.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
+pub fn svrshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe { svrshrnb_n_s32::<IMM2>(op1.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
+pub fn svrshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe { svrshrnb_n_s64::<IMM2>(op1.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
+pub fn svrshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv8i16")]
+        fn _svrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svrshrnt_n_s16(even, op1, IMM2) }
+}
+#[doc = "Rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
+pub fn svrshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv4i32")]
+        fn _svrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svrshrnt_n_s32(even, op1, IMM2) }
+}
+#[doc = "Rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
+pub fn svrshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv2i64")]
+        fn _svrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svrshrnt_n_s64(even, op1, IMM2) }
+}
+#[doc = "Rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
+pub fn svrshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe { svrshrnt_n_s16::<IMM2>(even.as_signed(), op1.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
+pub fn svrshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe { svrshrnt_n_s32::<IMM2>(even.as_signed(), op1.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
+pub fn svrshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe { svrshrnt_n_s64::<IMM2>(even.as_signed(), op1.as_signed()).as_unsigned() }
+}
+#[doc = "Reciprocal square root estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursqrte))]
+pub fn svrsqrte_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ursqrte.nxv4i32"
+        )]
+        fn _svrsqrte_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t;
+    }
+    unsafe { _svrsqrte_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() }
+}
+#[doc = "Reciprocal square root estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursqrte))]
+pub fn svrsqrte_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrsqrte_u32_m(op, pg, op)
+}
+#[doc = "Reciprocal square root estimate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursqrte))]
+pub fn svrsqrte_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
+    svrsqrte_u32_m(svdup_n_u32(0), pg, op)
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
+pub fn svrsra_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv16i8")]
+        fn _svrsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svrsra_n_s8(op1, op2, IMM3) }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
+pub fn svrsra_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv8i16")]
+        fn _svrsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svrsra_n_s16(op1, op2, IMM3) }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
+pub fn svrsra_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv4i32")]
+        fn _svrsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svrsra_n_s32(op1, op2, IMM3) }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
+pub fn svrsra_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv2i64")]
+        fn _svrsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svrsra_n_s64(op1, op2, IMM3) }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
+pub fn svrsra_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv16i8")]
+        fn _svrsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svrsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
+pub fn svrsra_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv8i16")]
+        fn _svrsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svrsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
+pub fn svrsra_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv4i32")]
+        fn _svrsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svrsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Rounding shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
+pub fn svrsra_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv2i64")]
+        fn _svrsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svrsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.rsubhnb.nxv8i16"
+        )]
+        fn _svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svrsubhnb_s16(op1, op2) }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
+    svrsubhnb_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.rsubhnb.nxv4i32"
+        )]
+        fn _svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svrsubhnb_s32(op1, op2) }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
+    svrsubhnb_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.rsubhnb.nxv2i64"
+        )]
+        fn _svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svrsubhnb_s64(op1, op2) }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
+    svrsubhnb_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svrsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
+    svrsubhnb_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svrsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
+    svrsubhnb_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svrsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnb))]
+pub fn svrsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
+    svrsubhnb_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.rsubhnt.nxv8i16"
+        )]
+        fn _svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svrsubhnt_s16(even, op1, op2) }
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
+    svrsubhnt_s16(even, op1, svdup_n_s16(op2))
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.rsubhnt.nxv4i32"
+        )]
+        fn _svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svrsubhnt_s32(even, op1, op2) }
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
+    svrsubhnt_s32(even, op1, svdup_n_s32(op2))
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.rsubhnt.nxv2i64"
+        )]
+        fn _svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svrsubhnt_s64(even, op1, op2) }
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
+    svrsubhnt_s64(even, op1, svdup_n_s64(op2))
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svrsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t {
+    svrsubhnt_u16(even, op1, svdup_n_u16(op2))
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svrsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t {
+    svrsubhnt_u32(even, op1, svdup_n_u32(op2))
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svrsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Rounding subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(rsubhnt))]
+pub fn svrsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t {
+    svrsubhnt_u64(even, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract with borrow long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclb))]
+pub fn svsbclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv4i32")]
+        fn _svsbclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsbclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract with borrow long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclb))]
+pub fn svsbclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svsbclb_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Subtract with borrow long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclb))]
+pub fn svsbclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv2i64")]
+        fn _svsbclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svsbclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract with borrow long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclb))]
+pub fn svsbclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svsbclb_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Subtract with borrow long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclt))]
+pub fn svsbclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv4i32")]
+        fn _svsbclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsbclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract with borrow long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclt))]
+pub fn svsbclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
+    svsbclt_u32(op1, op2, svdup_n_u32(op3))
+}
+#[doc = "Subtract with borrow long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclt))]
+pub fn svsbclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv2i64")]
+        fn _svsbclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t;
+    }
+    unsafe { _svsbclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract with borrow long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sbclt))]
+pub fn svsbclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
+    svsbclt_u64(op1, op2, svdup_n_u64(op3))
+}
+#[doc = "Shift left long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))]
+pub fn svshllb_n_s16<const IMM2: i32>(op1: svint8_t) -> svint16_t {
+    static_assert_range!(IMM2, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv8i16")]
+        fn _svshllb_n_s16(op1: svint8_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svshllb_n_s16(op1, IMM2) }
+}
+#[doc = "Shift left long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))]
+pub fn svshllb_n_s32<const IMM2: i32>(op1: svint16_t) -> svint32_t {
+    static_assert_range!(IMM2, 0..=15);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv4i32")]
+        fn _svshllb_n_s32(op1: svint16_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svshllb_n_s32(op1, IMM2) }
+}
+#[doc = "Shift left long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))]
+pub fn svshllb_n_s64<const IMM2: i32>(op1: svint32_t) -> svint64_t {
+    static_assert_range!(IMM2, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv2i64")]
+        fn _svshllb_n_s64(op1: svint32_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svshllb_n_s64(op1, IMM2) }
+}
+#[doc = "Shift left long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))]
+pub fn svshllb_n_u16<const IMM2: i32>(op1: svuint8_t) -> svuint16_t {
+    static_assert_range!(IMM2, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv8i16")]
+        fn _svshllb_n_u16(op1: svint8_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svshllb_n_u16(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Shift left long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))]
+pub fn svshllb_n_u32<const IMM2: i32>(op1: svuint16_t) -> svuint32_t {
+    static_assert_range!(IMM2, 0..=15);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv4i32")]
+        fn _svshllb_n_u32(op1: svint16_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svshllb_n_u32(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Shift left long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))]
+pub fn svshllb_n_u64<const IMM2: i32>(op1: svuint32_t) -> svuint64_t {
+    static_assert_range!(IMM2, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv2i64")]
+        fn _svshllb_n_u64(op1: svint32_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svshllb_n_u64(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Shift left long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))]
+pub fn svshllt_n_s16<const IMM2: i32>(op1: svint8_t) -> svint16_t {
+    static_assert_range!(IMM2, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv8i16")]
+        fn _svshllt_n_s16(op1: svint8_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svshllt_n_s16(op1, IMM2) }
+}
+#[doc = "Shift left long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))]
+pub fn svshllt_n_s32<const IMM2: i32>(op1: svint16_t) -> svint32_t {
+    static_assert_range!(IMM2, 0..=15);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv4i32")]
+        fn _svshllt_n_s32(op1: svint16_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svshllt_n_s32(op1, IMM2) }
+}
+#[doc = "Shift left long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))]
+pub fn svshllt_n_s64<const IMM2: i32>(op1: svint32_t) -> svint64_t {
+    static_assert_range!(IMM2, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv2i64")]
+        fn _svshllt_n_s64(op1: svint32_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svshllt_n_s64(op1, IMM2) }
+}
+#[doc = "Shift left long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))]
+pub fn svshllt_n_u16<const IMM2: i32>(op1: svuint8_t) -> svuint16_t {
+    static_assert_range!(IMM2, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv8i16")]
+        fn _svshllt_n_u16(op1: svint8_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svshllt_n_u16(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Shift left long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))]
+pub fn svshllt_n_u32<const IMM2: i32>(op1: svuint16_t) -> svuint32_t {
+    static_assert_range!(IMM2, 0..=15);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv4i32")]
+        fn _svshllt_n_u32(op1: svint16_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svshllt_n_u32(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Shift left long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))]
+pub fn svshllt_n_u64<const IMM2: i32>(op1: svuint32_t) -> svuint64_t {
+    static_assert_range!(IMM2, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv2i64")]
+        fn _svshllt_n_u64(op1: svint32_t, imm2: i32) -> svint64_t;
+    }
+    unsafe { _svshllt_n_u64(op1.as_signed(), IMM2).as_unsigned() }
+}
+#[doc = "Shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
+pub fn svshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv8i16")]
+        fn _svshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svshrnb_n_s16(op1, IMM2) }
+}
+#[doc = "Shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
+pub fn svshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv4i32")]
+        fn _svshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svshrnb_n_s32(op1, IMM2) }
+}
+#[doc = "Shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
+pub fn svshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv2i64")]
+        fn _svshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svshrnb_n_s64(op1, IMM2) }
+}
+#[doc = "Shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
+pub fn svshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe { svshrnb_n_s16::<IMM2>(op1.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
+pub fn svshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe { svshrnb_n_s32::<IMM2>(op1.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right narrow (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
+pub fn svshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe { svshrnb_n_s64::<IMM2>(op1.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
+pub fn svshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv8i16")]
+        fn _svshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t;
+    }
+    unsafe { _svshrnt_n_s16(even, op1, IMM2) }
+}
+#[doc = "Shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
+pub fn svshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv4i32")]
+        fn _svshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t;
+    }
+    unsafe { _svshrnt_n_s32(even, op1, IMM2) }
+}
+#[doc = "Shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
+pub fn svshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv2i64")]
+        fn _svshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t;
+    }
+    unsafe { _svshrnt_n_s64(even, op1, IMM2) }
+}
+#[doc = "Shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
+pub fn svshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svuint8_t {
+    static_assert_range!(IMM2, 1..=8);
+    unsafe { svshrnt_n_s16::<IMM2>(even.as_signed(), op1.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
+pub fn svshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svuint16_t {
+    static_assert_range!(IMM2, 1..=16);
+    unsafe { svshrnt_n_s32::<IMM2>(even.as_signed(), op1.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right narrow (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
+pub fn svshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svuint32_t {
+    static_assert_range!(IMM2, 1..=32);
+    unsafe { svshrnt_n_s64::<IMM2>(even.as_signed(), op1.as_signed()).as_unsigned() }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert_range!(IMM3, 0..=7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv16i8")]
+        fn _svsli_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svsli_n_s8(op1, op2, IMM3) }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM3, 0..=15);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv8i16")]
+        fn _svsli_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svsli_n_s16(op1, op2, IMM3) }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM3, 0..=31);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv4i32")]
+        fn _svsli_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svsli_n_s32(op1, op2, IMM3) }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM3, 0..=63);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv2i64")]
+        fn _svsli_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svsli_n_s64(op1, op2, IMM3) }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM3, 0..=7);
+    unsafe { svsli_n_s8::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM3, 0..=15);
+    unsafe { svsli_n_s16::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM3, 0..=31);
+    unsafe { svsli_n_s32::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Shift left and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
+pub fn svsli_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM3, 0..=63);
+    unsafe { svsli_n_s64::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "SM4 encryption and decryption"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4e[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-sm4")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sm4e))]
+pub fn svsm4e_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4e")]
+        fn _svsm4e_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsm4e_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "SM4 key updates"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4ekey[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2,sve2-sm4")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sm4ekey))]
+pub fn svsm4ekey_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4ekey")]
+        fn _svsm4ekey_u32(op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsm4ekey_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv16i8")]
+        fn _svsqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svsqadd_u8_m(pg, op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svsqadd_u8_m(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svsqadd_u8_m(pg, op1, op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svsqadd_u8_x(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
+    svsqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
+    svsqadd_u8_z(pg, op1, svdup_n_s8(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv8i16")]
+        fn _svsqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svsqadd_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svsqadd_u16_m(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svsqadd_u16_m(pg, op1, op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svsqadd_u16_x(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t {
+    svsqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
+    svsqadd_u16_z(pg, op1, svdup_n_s16(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv4i32")]
+        fn _svsqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svsqadd_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svsqadd_u32_m(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svsqadd_u32_m(pg, op1, op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svsqadd_u32_x(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t {
+    svsqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
+    svsqadd_u32_z(pg, op1, svdup_n_s32(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv2i64")]
+        fn _svsqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svsqadd_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() }
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svsqadd_u64_m(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svsqadd_u64_m(pg, op1, op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svsqadd_u64_x(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t {
+    svsqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
+}
+#[doc = "Saturating add with signed addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usqadd))]
+pub fn svsqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
+    svsqadd_u64_z(pg, op1, svdup_n_s64(op2))
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
+pub fn svsra_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv16i8")]
+        fn _svsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svsra_n_s8(op1, op2, IMM3) }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
+pub fn svsra_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv8i16")]
+        fn _svsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svsra_n_s16(op1, op2, IMM3) }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
+pub fn svsra_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv4i32")]
+        fn _svsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svsra_n_s32(op1, op2, IMM3) }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
+pub fn svsra_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv2i64")]
+        fn _svsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svsra_n_s64(op1, op2, IMM3) }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
+pub fn svsra_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv16i8")]
+        fn _svsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
+pub fn svsra_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv8i16")]
+        fn _svsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
+pub fn svsra_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv4i32")]
+        fn _svsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Shift right and accumulate"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
+pub fn svsra_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv2i64")]
+        fn _svsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv16i8")]
+        fn _svsri_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svsri_n_s8(op1, op2, IMM3) }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv8i16")]
+        fn _svsri_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svsri_n_s16(op1, op2, IMM3) }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv4i32")]
+        fn _svsri_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svsri_n_s32(op1, op2, IMM3) }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv2i64")]
+        fn _svsri_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svsri_n_s64(op1, op2, IMM3) }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe { svsri_n_s8::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe { svsri_n_s16::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe { svsri_n_s32::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Shift right and insert"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
+pub fn svsri_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe { svsri_n_s64::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_s64index_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    indices: svint64_t,
+    data: svfloat64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2f64"
+        )]
+        fn _svstnt1_scatter_s64index_f64(
+            data: svfloat64_t,
+            pg: svbool2_t,
+            base: *mut f64,
+            indices: svint64_t,
+        );
+    }
+    _svstnt1_scatter_s64index_f64(data, pg.sve_into(), base, indices)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_s64index_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    indices: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i64"
+        )]
+        fn _svstnt1_scatter_s64index_s64(
+            data: svint64_t,
+            pg: svbool2_t,
+            base: *mut i64,
+            indices: svint64_t,
+        );
+    }
+    _svstnt1_scatter_s64index_s64(data, pg.sve_into(), base, indices)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_s64index_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    indices: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64index_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    indices: svuint64_t,
+    data: svfloat64_t,
+) {
+    svstnt1_scatter_s64index_f64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64index_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    indices: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1_scatter_s64index_s64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64index_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    indices: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_s64offset_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    offsets: svint64_t,
+    data: svfloat64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2f64"
+        )]
+        fn _svstnt1_scatter_s64offset_f64(
+            data: svfloat64_t,
+            pg: svbool2_t,
+            base: *mut f64,
+            offsets: svint64_t,
+        );
+    }
+    _svstnt1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i64"
+        )]
+        fn _svstnt1_scatter_s64offset_s64(
+            data: svint64_t,
+            pg: svbool2_t,
+            base: *mut i64,
+            offsets: svint64_t,
+        );
+    }
+    _svstnt1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32offset_f32(
+    pg: svbool_t,
+    base: *mut f32,
+    offsets: svuint32_t,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4f32"
+        )]
+        fn _svstnt1_scatter_u32offset_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            base: *mut f32,
+            offsets: svint32_t,
+        );
+    }
+    _svstnt1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32offset_s32(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32"
+        )]
+        fn _svstnt1_scatter_u32offset_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            base: *mut i32,
+            offsets: svint32_t,
+        );
+    }
+    _svstnt1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32offset_u32(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svuint32_t,
+    data: svuint32_t,
+) {
+    svstnt1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64offset_f64(
+    pg: svbool_t,
+    base: *mut f64,
+    offsets: svuint64_t,
+    data: svfloat64_t,
+) {
+    svstnt1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i64,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u64,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) {
+    svstnt1_scatter_u32base_offset_f32(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) {
+    svstnt1_scatter_u32base_offset_s32(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) {
+    svstnt1_scatter_u32base_offset_u32(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) {
+    svstnt1_scatter_u64base_offset_f64(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svstnt1_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svstnt1_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_index_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svfloat32_t,
+) {
+    svstnt1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svint32_t,
+) {
+    svstnt1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svuint32_t,
+) {
+    svstnt1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_index_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svfloat64_t,
+) {
+    svstnt1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svint64_t,
+) {
+    svstnt1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svuint64_t,
+) {
+    svstnt1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_offset_f32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svfloat32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32"
+        )]
+        fn _svstnt1_scatter_u32base_offset_f32(
+            data: svfloat32_t,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svstnt1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32"
+        )]
+        fn _svstnt1_scatter_u32base_offset_s32(
+            data: svint32_t,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svstnt1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1_scatter_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svuint32_t,
+) {
+    svstnt1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed())
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_offset_f64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svfloat64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64"
+        )]
+        fn _svstnt1_scatter_u64base_offset_f64(
+            data: svfloat64_t,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svstnt1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64"
+        )]
+        fn _svstnt1_scatter_u64base_offset_s64(
+            data: svint64_t,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svstnt1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset)
+}
+#[doc = "Non-truncating store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1d))]
+pub unsafe fn svstnt1_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svstnt1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i8"
+        )]
+        fn _svstnt1b_scatter_s64offset_s64(
+            data: nxv2i8,
+            pg: svbool2_t,
+            base: *mut i8,
+            offsets: svint64_t,
+        );
+    }
+    _svstnt1b_scatter_s64offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i16"
+        )]
+        fn _svstnt1h_scatter_s64offset_s64(
+            data: nxv2i16,
+            pg: svbool2_t,
+            base: *mut i16,
+            offsets: svint64_t,
+        );
+    }
+    _svstnt1h_scatter_s64offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_s64offset_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i32"
+        )]
+        fn _svstnt1w_scatter_s64offset_s64(
+            data: nxv2i32,
+            pg: svbool2_t,
+            base: *mut i32,
+            offsets: svint64_t,
+        );
+    }
+    _svstnt1w_scatter_s64offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets,
+    )
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_s64offset_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u32offset_s32(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8"
+        )]
+        fn _svstnt1b_scatter_u32offset_s32(
+            data: nxv4i8,
+            pg: svbool4_t,
+            base: *mut i8,
+            offsets: svint32_t,
+        );
+    }
+    _svstnt1b_scatter_u32offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    )
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32offset_s32(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svuint32_t,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16"
+        )]
+        fn _svstnt1h_scatter_u32offset_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            base: *mut i16,
+            offsets: svint32_t,
+        );
+    }
+    _svstnt1h_scatter_u32offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        offsets.as_signed(),
+    )
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u32offset_u32(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svuint32_t,
+    data: svuint32_t,
+) {
+    svstnt1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32offset_u32(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svuint32_t,
+    data: svuint32_t,
+) {
+    svstnt1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i8,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64offset_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    offsets: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data)
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u8,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64offset_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    offsets: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32"
+        )]
+        fn _svstnt1b_scatter_u32base_offset_s32(
+            data: nxv4i8,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svstnt1b_scatter_u32base_offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32base_offset_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svint32_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32"
+        )]
+        fn _svstnt1h_scatter_u32base_offset_s32(
+            data: nxv4i16,
+            pg: svbool4_t,
+            bases: svint32_t,
+            offset: i64,
+        );
+    }
+    _svstnt1h_scatter_u32base_offset_s32(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svuint32_t,
+) {
+    svstnt1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32base_offset_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    offset: i64,
+    data: svuint32_t,
+) {
+    svstnt1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64"
+        )]
+        fn _svstnt1b_scatter_u64base_offset_s64(
+            data: nxv2i8,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svstnt1b_scatter_u64base_offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64"
+        )]
+        fn _svstnt1h_scatter_u64base_offset_s64(
+            data: nxv2i16,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svstnt1h_scatter_u64base_offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64base_offset_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64"
+        )]
+        fn _svstnt1w_scatter_u64base_offset_s64(
+            data: nxv2i32,
+            pg: svbool2_t,
+            bases: svint64_t,
+            offset: i64,
+        );
+    }
+    _svstnt1w_scatter_u64base_offset_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        bases.as_signed(),
+        offset,
+    )
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svstnt1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svstnt1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64base_offset_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    offset: i64,
+    data: svuint64_t,
+) {
+    svstnt1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed())
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) {
+    svstnt1b_scatter_u32base_offset_s32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) {
+    svstnt1h_scatter_u32base_offset_s32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) {
+    svstnt1b_scatter_u32base_offset_u32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) {
+    svstnt1h_scatter_u32base_offset_u32(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svstnt1b_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svstnt1h_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) {
+    svstnt1w_scatter_u64base_offset_s64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 8 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1b))]
+pub unsafe fn svstnt1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svstnt1b_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svstnt1h_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) {
+    svstnt1w_scatter_u64base_offset_u64(pg, bases, 0, data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_s64index_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    indices: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i16"
+        )]
+        fn _svstnt1h_scatter_s64index_s64(
+            data: nxv2i16,
+            pg: svbool2_t,
+            base: *mut i16,
+            indices: svint64_t,
+        );
+    }
+    _svstnt1h_scatter_s64index_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        indices,
+    )
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_s64index_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    indices: svint64_t,
+    data: svint64_t,
+) {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i32"
+        )]
+        fn _svstnt1w_scatter_s64index_s64(
+            data: nxv2i32,
+            pg: svbool2_t,
+            base: *mut i32,
+            indices: svint64_t,
+        );
+    }
+    _svstnt1w_scatter_s64index_s64(
+        crate::intrinsics::simd::simd_cast(data),
+        pg.sve_into(),
+        base,
+        indices,
+    )
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_s64index_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    indices: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_s64index_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    indices: svint64_t,
+    data: svuint64_t,
+) {
+    svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64index_s64(
+    pg: svbool_t,
+    base: *mut i16,
+    indices: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1h_scatter_s64index_s64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64index_s64(
+    pg: svbool_t,
+    base: *mut i32,
+    indices: svuint64_t,
+    data: svint64_t,
+) {
+    svstnt1w_scatter_s64index_s64(pg, base, indices.as_signed(), data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64index_u64(
+    pg: svbool_t,
+    base: *mut u16,
+    indices: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64index_u64(
+    pg: svbool_t,
+    base: *mut u32,
+    indices: svuint64_t,
+    data: svuint64_t,
+) {
+    svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed())
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32base_index_s32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svint32_t,
+) {
+    svstnt1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u32base_index_u32(
+    pg: svbool_t,
+    bases: svuint32_t,
+    index: i64,
+    data: svuint32_t,
+) {
+    svstnt1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svint64_t,
+) {
+    svstnt1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64base_index_s64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svint64_t,
+) {
+    svstnt1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Truncate to 16 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1h))]
+pub unsafe fn svstnt1h_scatter_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svuint64_t,
+) {
+    svstnt1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data)
+}
+#[doc = "Truncate to 32 bits and store, non-temporal"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
+#[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
+#[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
+#[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(stnt1w))]
+pub unsafe fn svstnt1w_scatter_u64base_index_u64(
+    pg: svbool_t,
+    bases: svuint64_t,
+    index: i64,
+    data: svuint64_t,
+) {
+    svstnt1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data)
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv8i16")]
+        fn _svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svsubhnb_s16(op1, op2) }
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
+    svsubhnb_s16(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv4i32")]
+        fn _svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svsubhnb_s32(op1, op2) }
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
+    svsubhnb_s32(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv2i64")]
+        fn _svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svsubhnb_s64(op1, op2) }
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
+    svsubhnb_s64(op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
+    svsubhnb_u16(op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
+    svsubhnb_u32(op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract narrow high part (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnb))]
+pub fn svsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
+    svsubhnb_u64(op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv8i16")]
+        fn _svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t;
+    }
+    unsafe { _svsubhnt_s16(even, op1, op2) }
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
+    svsubhnt_s16(even, op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv4i32")]
+        fn _svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t;
+    }
+    unsafe { _svsubhnt_s32(even, op1, op2) }
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
+    svsubhnt_s32(even, op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv2i64")]
+        fn _svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t;
+    }
+    unsafe { _svsubhnt_s64(even, op1, op2) }
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
+    svsubhnt_s64(even, op1, svdup_n_s64(op2))
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
+    unsafe { svsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t {
+    svsubhnt_u16(even, op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
+    unsafe { svsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t {
+    svsubhnt_u32(even, op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
+    unsafe { svsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract narrow high part (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(subhnt))]
+pub fn svsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t {
+    svsubhnt_u64(even, op1, svdup_n_u64(op2))
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublb))]
+pub fn svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv8i16")]
+        fn _svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsublb_s16(op1, op2) }
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublb))]
+pub fn svsublb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svsublb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublb))]
+pub fn svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv4i32")]
+        fn _svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsublb_s32(op1, op2) }
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublb))]
+pub fn svsublb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svsublb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublb))]
+pub fn svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv2i64")]
+        fn _svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsublb_s64(op1, op2) }
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublb))]
+pub fn svsublb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svsublb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublb))]
+pub fn svsublb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv8i16")]
+        fn _svsublb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsublb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublb))]
+pub fn svsublb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svsublb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublb))]
+pub fn svsublb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv4i32")]
+        fn _svsublb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsublb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublb))]
+pub fn svsublb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svsublb_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublb))]
+pub fn svsublb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv2i64")]
+        fn _svsublb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsublb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract long (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublb))]
+pub fn svsublb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svsublb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract long (bottom - top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublbt))]
+pub fn svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ssublbt.nxv8i16"
+        )]
+        fn _svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsublbt_s16(op1, op2) }
+}
+#[doc = "Subtract long (bottom - top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublbt))]
+pub fn svsublbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svsublbt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract long (bottom - top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublbt))]
+pub fn svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ssublbt.nxv4i32"
+        )]
+        fn _svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsublbt_s32(op1, op2) }
+}
+#[doc = "Subtract long (bottom - top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublbt))]
+pub fn svsublbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svsublbt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract long (bottom - top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublbt))]
+pub fn svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ssublbt.nxv2i64"
+        )]
+        fn _svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsublbt_s64(op1, op2) }
+}
+#[doc = "Subtract long (bottom - top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublbt))]
+pub fn svsublbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svsublbt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublt))]
+pub fn svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv8i16")]
+        fn _svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsublt_s16(op1, op2) }
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublt))]
+pub fn svsublt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svsublt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublt))]
+pub fn svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv4i32")]
+        fn _svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsublt_s32(op1, op2) }
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublt))]
+pub fn svsublt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svsublt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublt))]
+pub fn svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv2i64")]
+        fn _svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsublt_s64(op1, op2) }
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssublt))]
+pub fn svsublt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svsublt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublt))]
+pub fn svsublt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv8i16")]
+        fn _svsublt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsublt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublt))]
+pub fn svsublt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
+    svsublt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublt))]
+pub fn svsublt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv4i32")]
+        fn _svsublt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsublt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublt))]
+pub fn svsublt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
+    svsublt_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublt))]
+pub fn svsublt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv2i64")]
+        fn _svsublt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsublt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract long (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usublt))]
+pub fn svsublt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
+    svsublt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract long (top - bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubltb))]
+pub fn svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ssubltb.nxv8i16"
+        )]
+        fn _svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsubltb_s16(op1, op2) }
+}
+#[doc = "Subtract long (top - bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubltb))]
+pub fn svsubltb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
+    svsubltb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract long (top - bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubltb))]
+pub fn svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ssubltb.nxv4i32"
+        )]
+        fn _svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsubltb_s32(op1, op2) }
+}
+#[doc = "Subtract long (top - bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubltb))]
+pub fn svsubltb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
+    svsubltb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract long (top - bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubltb))]
+pub fn svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.ssubltb.nxv2i64"
+        )]
+        fn _svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsubltb_s64(op1, op2) }
+}
+#[doc = "Subtract long (top - bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubltb))]
+pub fn svsubltb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
+    svsubltb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwb))]
+pub fn svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv8i16")]
+        fn _svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsubwb_s16(op1, op2) }
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwb))]
+pub fn svsubwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
+    svsubwb_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwb))]
+pub fn svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv4i32")]
+        fn _svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsubwb_s32(op1, op2) }
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwb))]
+pub fn svsubwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
+    svsubwb_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwb))]
+pub fn svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv2i64")]
+        fn _svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsubwb_s64(op1, op2) }
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwb))]
+pub fn svsubwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
+    svsubwb_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwb))]
+pub fn svsubwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv8i16")]
+        fn _svsubwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsubwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwb))]
+pub fn svsubwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
+    svsubwb_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwb))]
+pub fn svsubwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv4i32")]
+        fn _svsubwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsubwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwb))]
+pub fn svsubwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
+    svsubwb_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwb))]
+pub fn svsubwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv2i64")]
+        fn _svsubwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsubwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract wide (bottom)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwb))]
+pub fn svsubwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
+    svsubwb_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwt))]
+pub fn svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv8i16")]
+        fn _svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsubwt_s16(op1, op2) }
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwt))]
+pub fn svsubwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
+    svsubwt_s16(op1, svdup_n_s8(op2))
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwt))]
+pub fn svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv4i32")]
+        fn _svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsubwt_s32(op1, op2) }
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwt))]
+pub fn svsubwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
+    svsubwt_s32(op1, svdup_n_s16(op2))
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwt))]
+pub fn svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv2i64")]
+        fn _svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsubwt_s64(op1, op2) }
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(ssubwt))]
+pub fn svsubwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
+    svsubwt_s64(op1, svdup_n_s32(op2))
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwt))]
+pub fn svsubwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv8i16")]
+        fn _svsubwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t;
+    }
+    unsafe { _svsubwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwt))]
+pub fn svsubwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
+    svsubwt_u16(op1, svdup_n_u8(op2))
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwt))]
+pub fn svsubwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv4i32")]
+        fn _svsubwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t;
+    }
+    unsafe { _svsubwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwt))]
+pub fn svsubwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
+    svsubwt_u32(op1, svdup_n_u16(op2))
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwt))]
+pub fn svsubwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv2i64")]
+        fn _svsubwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t;
+    }
+    unsafe { _svsubwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Subtract wide (top)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(usubwt))]
+pub fn svsubwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
+    svsubwt_u64(op1, svdup_n_u32(op2))
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_f32(data: svfloat32x2_t, indices: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4f32")]
+        fn _svtbl2_f32(data0: svfloat32_t, data1: svfloat32_t, indices: svint32_t) -> svfloat32_t;
+    }
+    unsafe {
+        _svtbl2_f32(
+            svget2_f32::<0>(data),
+            svget2_f32::<1>(data),
+            indices.as_signed(),
+        )
+    }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_f64(data: svfloat64x2_t, indices: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2f64")]
+        fn _svtbl2_f64(data0: svfloat64_t, data1: svfloat64_t, indices: svint64_t) -> svfloat64_t;
+    }
+    unsafe {
+        _svtbl2_f64(
+            svget2_f64::<0>(data),
+            svget2_f64::<1>(data),
+            indices.as_signed(),
+        )
+    }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_s8(data: svint8x2_t, indices: svuint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv16i8")]
+        fn _svtbl2_s8(data0: svint8_t, data1: svint8_t, indices: svint8_t) -> svint8_t;
+    }
+    unsafe {
+        _svtbl2_s8(
+            svget2_s8::<0>(data),
+            svget2_s8::<1>(data),
+            indices.as_signed(),
+        )
+    }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_s16(data: svint16x2_t, indices: svuint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv8i16")]
+        fn _svtbl2_s16(data0: svint16_t, data1: svint16_t, indices: svint16_t) -> svint16_t;
+    }
+    unsafe {
+        _svtbl2_s16(
+            svget2_s16::<0>(data),
+            svget2_s16::<1>(data),
+            indices.as_signed(),
+        )
+    }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_s32(data: svint32x2_t, indices: svuint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4i32")]
+        fn _svtbl2_s32(data0: svint32_t, data1: svint32_t, indices: svint32_t) -> svint32_t;
+    }
+    unsafe {
+        _svtbl2_s32(
+            svget2_s32::<0>(data),
+            svget2_s32::<1>(data),
+            indices.as_signed(),
+        )
+    }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_s64(data: svint64x2_t, indices: svuint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2i64")]
+        fn _svtbl2_s64(data0: svint64_t, data1: svint64_t, indices: svint64_t) -> svint64_t;
+    }
+    unsafe {
+        _svtbl2_s64(
+            svget2_s64::<0>(data),
+            svget2_s64::<1>(data),
+            indices.as_signed(),
+        )
+    }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_u8(data: svuint8x2_t, indices: svuint8_t) -> svuint8_t {
+    unsafe { svtbl2_s8(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_u16(data: svuint16x2_t, indices: svuint16_t) -> svuint16_t {
+    unsafe { svtbl2_s16(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_u32(data: svuint32x2_t, indices: svuint32_t) -> svuint32_t {
+    unsafe { svtbl2_s32(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in two-vector table"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbl))]
+pub fn svtbl2_u64(data: svuint64x2_t, indices: svuint64_t) -> svuint64_t {
+    unsafe { svtbl2_s64(data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svuint32_t) -> svfloat32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4f32")]
+        fn _svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svint32_t) -> svfloat32_t;
+    }
+    unsafe { _svtbx_f32(fallback, data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svuint64_t) -> svfloat64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2f64")]
+        fn _svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svint64_t) -> svfloat64_t;
+    }
+    unsafe { _svtbx_f64(fallback, data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svuint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv16i8")]
+        fn _svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svint8_t) -> svint8_t;
+    }
+    unsafe { _svtbx_s8(fallback, data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svuint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv8i16")]
+        fn _svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svint16_t) -> svint16_t;
+    }
+    unsafe { _svtbx_s16(fallback, data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svuint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4i32")]
+        fn _svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svint32_t) -> svint32_t;
+    }
+    unsafe { _svtbx_s32(fallback, data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svuint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2i64")]
+        fn _svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svint64_t) -> svint64_t;
+    }
+    unsafe { _svtbx_s64(fallback, data, indices.as_signed()) }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_u8(fallback: svuint8_t, data: svuint8_t, indices: svuint8_t) -> svuint8_t {
+    unsafe { svtbx_s8(fallback.as_signed(), data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_u16(fallback: svuint16_t, data: svuint16_t, indices: svuint16_t) -> svuint16_t {
+    unsafe { svtbx_s16(fallback.as_signed(), data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_u32(fallback: svuint32_t, data: svuint32_t, indices: svuint32_t) -> svuint32_t {
+    unsafe { svtbx_s32(fallback.as_signed(), data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Table lookup in single-vector table (merging)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(tbx))]
+pub fn svtbx_u64(fallback: svuint64_t, data: svuint64_t, indices: svuint64_t) -> svuint64_t {
+    unsafe { svtbx_s64(fallback.as_signed(), data.as_signed(), indices).as_unsigned() }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_b])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(punpkhi))]
+pub fn svunpkhi_b(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.punpkhi.nxv16i1"
+        )]
+        fn _svunpkhi_b(op: svbool_t) -> svbool8_t;
+    }
+    unsafe { _svunpkhi_b(op).sve_into() }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sunpkhi))]
+pub fn svunpkhi_s16(op: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sunpkhi.nxv8i16"
+        )]
+        fn _svunpkhi_s16(op: svint8_t) -> svint16_t;
+    }
+    unsafe { _svunpkhi_s16(op) }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sunpkhi))]
+pub fn svunpkhi_s32(op: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sunpkhi.nxv4i32"
+        )]
+        fn _svunpkhi_s32(op: svint16_t) -> svint32_t;
+    }
+    unsafe { _svunpkhi_s32(op) }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sunpkhi))]
+pub fn svunpkhi_s64(op: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sunpkhi.nxv2i64"
+        )]
+        fn _svunpkhi_s64(op: svint32_t) -> svint64_t;
+    }
+    unsafe { _svunpkhi_s64(op) }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uunpkhi))]
+pub fn svunpkhi_u16(op: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uunpkhi.nxv8i16"
+        )]
+        fn _svunpkhi_u16(op: svint8_t) -> svint16_t;
+    }
+    unsafe { _svunpkhi_u16(op.as_signed()).as_unsigned() }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uunpkhi))]
+pub fn svunpkhi_u32(op: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uunpkhi.nxv4i32"
+        )]
+        fn _svunpkhi_u32(op: svint16_t) -> svint32_t;
+    }
+    unsafe { _svunpkhi_u32(op.as_signed()).as_unsigned() }
+}
+#[doc = "Unpack and extend high half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uunpkhi))]
+pub fn svunpkhi_u64(op: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uunpkhi.nxv2i64"
+        )]
+        fn _svunpkhi_u64(op: svint32_t) -> svint64_t;
+    }
+    unsafe { _svunpkhi_u64(op.as_signed()).as_unsigned() }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_b])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(punpklo))]
+pub fn svunpklo_b(op: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.punpklo.nxv16i1"
+        )]
+        fn _svunpklo_b(op: svbool_t) -> svbool8_t;
+    }
+    unsafe { _svunpklo_b(op).sve_into() }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sunpklo))]
+pub fn svunpklo_s16(op: svint8_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sunpklo.nxv8i16"
+        )]
+        fn _svunpklo_s16(op: svint8_t) -> svint16_t;
+    }
+    unsafe { _svunpklo_s16(op) }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sunpklo))]
+pub fn svunpklo_s32(op: svint16_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sunpklo.nxv4i32"
+        )]
+        fn _svunpklo_s32(op: svint16_t) -> svint32_t;
+    }
+    unsafe { _svunpklo_s32(op) }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(sunpklo))]
+pub fn svunpklo_s64(op: svint32_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.sunpklo.nxv2i64"
+        )]
+        fn _svunpklo_s64(op: svint32_t) -> svint64_t;
+    }
+    unsafe { _svunpklo_s64(op) }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uunpklo))]
+pub fn svunpklo_u16(op: svuint8_t) -> svuint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uunpklo.nxv8i16"
+        )]
+        fn _svunpklo_u16(op: svint8_t) -> svint16_t;
+    }
+    unsafe { _svunpklo_u16(op.as_signed()).as_unsigned() }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uunpklo))]
+pub fn svunpklo_u32(op: svuint16_t) -> svuint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uunpklo.nxv4i32"
+        )]
+        fn _svunpklo_u32(op: svint16_t) -> svint32_t;
+    }
+    unsafe { _svunpklo_u32(op.as_signed()).as_unsigned() }
+}
+#[doc = "Unpack and extend low half"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(uunpklo))]
+pub fn svunpklo_u64(op: svuint32_t) -> svuint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.uunpklo.nxv2i64"
+        )]
+        fn _svunpklo_u64(op: svint32_t) -> svint64_t;
+    }
+    unsafe { _svunpklo_u64(op.as_signed()).as_unsigned() }
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv16i8")]
+        fn _svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
+    }
+    unsafe { _svuqadd_s8_m(pg, op1, op2.as_signed()) }
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svuqadd_s8_m(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    svuqadd_s8_m(pg, op1, op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svuqadd_s8_x(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
+    svuqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
+    svuqadd_s8_z(pg, op1, svdup_n_u8(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv8i16")]
+        fn _svuqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
+    }
+    unsafe { _svuqadd_s16_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svuqadd_s16_m(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    svuqadd_s16_m(pg, op1, op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svuqadd_s16_x(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
+    svuqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
+    svuqadd_s16_z(pg, op1, svdup_n_u16(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv4i32")]
+        fn _svuqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
+    }
+    unsafe { _svuqadd_s32_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svuqadd_s32_m(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    svuqadd_s32_m(pg, op1, op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svuqadd_s32_x(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
+    svuqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
+    svuqadd_s32_z(pg, op1, svdup_n_u32(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv2i64")]
+        fn _svuqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
+    }
+    unsafe { _svuqadd_s64_m(pg.sve_into(), op1, op2.as_signed()) }
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_m)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svuqadd_s64_m(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    svuqadd_s64_m(pg, op1, op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_x)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svuqadd_s64_x(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
+    svuqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
+}
+#[doc = "Saturating add with unsigned addend"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_z)"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(suqadd))]
+pub fn svuqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
+    svuqadd_s64_z(pg, op1, svdup_n_u64(op2))
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv16i1.i32"
+        )]
+        fn _svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilege_b8_s32(op1, op2) }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b16_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv8i1.i32"
+        )]
+        fn _svwhilege_b16_s32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilege_b16_s32(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b32_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv4i1.i32"
+        )]
+        fn _svwhilege_b32_s32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilege_b32_s32(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b64_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv2i1.i32"
+        )]
+        fn _svwhilege_b64_s32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilege_b64_s32(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv16i1.i64"
+        )]
+        fn _svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilege_b8_s64(op1, op2) }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b16_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv8i1.i64"
+        )]
+        fn _svwhilege_b16_s64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilege_b16_s64(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b32_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv4i1.i64"
+        )]
+        fn _svwhilege_b32_s64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilege_b32_s64(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilege))]
+pub fn svwhilege_b64_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilege.nxv2i1.i64"
+        )]
+        fn _svwhilege_b64_s64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilege_b64_s64(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b8_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i32"
+        )]
+        fn _svwhilege_b8_u32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilege_b8_u32(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b16_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i32"
+        )]
+        fn _svwhilege_b16_u32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilege_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b32_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i32"
+        )]
+        fn _svwhilege_b32_u32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilege_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b64_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i32"
+        )]
+        fn _svwhilege_b64_u32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilege_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b8_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i64"
+        )]
+        fn _svwhilege_b8_u64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilege_b8_u64(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b16_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i64"
+        )]
+        fn _svwhilege_b16_u64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilege_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b32_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i64"
+        )]
+        fn _svwhilege_b32_u64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilege_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than or equal to"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehs))]
+pub fn svwhilege_b64_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i64"
+        )]
+        fn _svwhilege_b64_u64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilege_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i32"
+        )]
+        fn _svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilegt_b8_s32(op1, op2) }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i32"
+        )]
+        fn _svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilegt_b16_s32(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i32"
+        )]
+        fn _svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilegt_b32_s32(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i32"
+        )]
+        fn _svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilegt_b64_s32(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i64"
+        )]
+        fn _svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilegt_b8_s64(op1, op2) }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i64"
+        )]
+        fn _svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilegt_b16_s64(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i64"
+        )]
+        fn _svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilegt_b32_s64(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilegt))]
+pub fn svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i64"
+        )]
+        fn _svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilegt_b64_s64(op1, op2).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b8_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i32"
+        )]
+        fn _svwhilegt_b8_u32(op1: i32, op2: i32) -> svbool_t;
+    }
+    unsafe { _svwhilegt_b8_u32(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b16_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i32"
+        )]
+        fn _svwhilegt_b16_u32(op1: i32, op2: i32) -> svbool8_t;
+    }
+    unsafe { _svwhilegt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b32_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i32"
+        )]
+        fn _svwhilegt_b32_u32(op1: i32, op2: i32) -> svbool4_t;
+    }
+    unsafe { _svwhilegt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b64_u32(op1: u32, op2: u32) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i32"
+        )]
+        fn _svwhilegt_b64_u32(op1: i32, op2: i32) -> svbool2_t;
+    }
+    unsafe { _svwhilegt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b8_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i64"
+        )]
+        fn _svwhilegt_b8_u64(op1: i64, op2: i64) -> svbool_t;
+    }
+    unsafe { _svwhilegt_b8_u64(op1.as_signed(), op2.as_signed()) }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b16_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i64"
+        )]
+        fn _svwhilegt_b16_u64(op1: i64, op2: i64) -> svbool8_t;
+    }
+    unsafe { _svwhilegt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b32_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i64"
+        )]
+        fn _svwhilegt_b32_u64(op1: i64, op2: i64) -> svbool4_t;
+    }
+    unsafe { _svwhilegt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[doc = "While decrementing scalar is greater than"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilehi))]
+pub fn svwhilegt_b64_u64(op1: u64, op2: u64) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i64"
+        )]
+        fn _svwhilegt_b64_u64(op1: i64, op2: i64) -> svbool2_t;
+    }
+    unsafe { _svwhilegt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() }
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilerw_8ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilerw.b.nxv16i1.p0"
+        )]
+        fn _svwhilerw_8ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool_t;
+    }
+    _svwhilerw_8ptr(op1, op2)
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilerw_16ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilerw.h.nxv8i1.p0"
+        )]
+        fn _svwhilerw_16ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool8_t;
+    }
+    _svwhilerw_16ptr(op1, op2).sve_into()
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilerw_32ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilerw.s.nxv4i1.p0"
+        )]
+        fn _svwhilerw_32ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool4_t;
+    }
+    _svwhilerw_32ptr(op1, op2).sve_into()
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilerw_64ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilerw.d.nxv2i1.p0"
+        )]
+        fn _svwhilerw_64ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool2_t;
+    }
+    _svwhilerw_64ptr(op1, op2).sve_into()
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_f32(op1: *const f32, op2: *const f32) -> svbool_t {
+    svwhilerw_32ptr::<f32>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_f64(op1: *const f64, op2: *const f64) -> svbool_t {
+    svwhilerw_64ptr::<f64>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_s8(op1: *const i8, op2: *const i8) -> svbool_t {
+    svwhilerw_8ptr::<i8>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_s16(op1: *const i16, op2: *const i16) -> svbool_t {
+    svwhilerw_16ptr::<i16>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_s32(op1: *const i32, op2: *const i32) -> svbool_t {
+    svwhilerw_32ptr::<i32>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_s64(op1: *const i64, op2: *const i64) -> svbool_t {
+    svwhilerw_64ptr::<i64>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_u8(op1: *const u8, op2: *const u8) -> svbool_t {
+    svwhilerw_8ptr::<u8>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_u16(op1: *const u16, op2: *const u16) -> svbool_t {
+    svwhilerw_16ptr::<u16>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_u32(op1: *const u32, op2: *const u32) -> svbool_t {
+    svwhilerw_32ptr::<u32>(op1, op2)
+}
+#[doc = "While free of read-after-write conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilerw))]
+pub unsafe fn svwhilerw_u64(op1: *const u64, op2: *const u64) -> svbool_t {
+    svwhilerw_64ptr::<u64>(op1, op2)
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilewr_8ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilewr.b.nxv16i1.p0"
+        )]
+        fn _svwhilewr_8ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool_t;
+    }
+    _svwhilewr_8ptr(op1, op2)
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilewr_16ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilewr.h.nxv8i1.p0"
+        )]
+        fn _svwhilewr_16ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool8_t;
+    }
+    _svwhilewr_16ptr(op1, op2).sve_into()
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilewr_32ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilewr.s.nxv4i1.p0"
+        )]
+        fn _svwhilewr_32ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool4_t;
+    }
+    _svwhilewr_32ptr(op1, op2).sve_into()
+}
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+unsafe fn svwhilewr_64ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
+    let op1 = op1 as *const crate::ffi::c_void;
+    let op2 = op2 as *const crate::ffi::c_void;
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            target_arch = "aarch64",
+            link_name = "llvm.aarch64.sve.whilewr.d.nxv2i1.p0"
+        )]
+        fn _svwhilewr_64ptr(
+            op1: *const crate::ffi::c_void,
+            op2: *const crate::ffi::c_void,
+        ) -> svbool2_t;
+    }
+    _svwhilewr_64ptr(op1, op2).sve_into()
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_f32(op1: *const f32, op2: *const f32) -> svbool_t {
+    svwhilewr_32ptr::<f32>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_f64(op1: *const f64, op2: *const f64) -> svbool_t {
+    svwhilewr_64ptr::<f64>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_s8(op1: *const i8, op2: *const i8) -> svbool_t {
+    svwhilewr_8ptr::<i8>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_s16(op1: *const i16, op2: *const i16) -> svbool_t {
+    svwhilewr_16ptr::<i16>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_s32(op1: *const i32, op2: *const i32) -> svbool_t {
+    svwhilewr_32ptr::<i32>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_s64(op1: *const i64, op2: *const i64) -> svbool_t {
+    svwhilewr_64ptr::<i64>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u8])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_u8(op1: *const u8, op2: *const u8) -> svbool_t {
+    svwhilewr_8ptr::<u8>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u16])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_u16(op1: *const u16, op2: *const u16) -> svbool_t {
+    svwhilewr_16ptr::<u16>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u32])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_u32(op1: *const u32, op2: *const u32) -> svbool_t {
+    svwhilewr_32ptr::<u32>(op1, op2)
+}
+#[doc = "While free of write-after-read conflicts"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u64])"]
+#[doc = "## Safety"]
+#[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(whilewr))]
+pub unsafe fn svwhilewr_u64(op1: *const u64, op2: *const u64) -> svbool_t {
+    svwhilewr_64ptr::<u64>(op1, op2)
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv16i8")]
+        fn _svxar_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t;
+    }
+    unsafe { _svxar_n_s8(op1, op2, IMM3) }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv8i16")]
+        fn _svxar_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t;
+    }
+    unsafe { _svxar_n_s16(op1, op2, IMM3) }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv4i32")]
+        fn _svxar_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
+    }
+    unsafe { _svxar_n_s32(op1, op2, IMM3) }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv2i64")]
+        fn _svxar_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t;
+    }
+    unsafe { _svxar_n_s64(op1, op2, IMM3) }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u8])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
+    static_assert_range!(IMM3, 1..=8);
+    unsafe { svxar_n_s8::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u16])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
+    static_assert_range!(IMM3, 1..=16);
+    unsafe { svxar_n_s16::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u32])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
+    static_assert_range!(IMM3, 1..=32);
+    unsafe { svxar_n_s32::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
+#[doc = "Bitwise exclusive OR and rotate right"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u64])"]
+#[inline(always)]
+#[target_feature(enable = "sve,sve2")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
+pub fn svxar_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
+    static_assert_range!(IMM3, 1..=64);
+    unsafe { svxar_n_s64::<IMM3>(op1.as_signed(), op2.as_signed()).as_unsigned() }
+}
diff --git a/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs b/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs
new file mode 100644
index 0000000000..2ec3ad6a5d
--- /dev/null
+++ b/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs
@@ -0,0 +1,2482 @@
+// This code is automatically generated. DO NOT MODIFY.
+//
+// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate
+// this file:
+//
+// ```
+// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
+// ```
+#![allow(unused)]
+use super::*;
+use std::boxed::Box;
+use std::convert::{TryFrom, TryInto};
+use std::sync::LazyLock;
+use std::vec::Vec;
+use stdarch_test::simd_test;
+static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as f32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("f32 data incorrectly initialised")
+});
+static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| {
+    (0..32 * 5)
+        .map(|i| i as f64)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("f64 data incorrectly initialised")
+});
+static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| {
+    (0..256 * 5)
+        .map(|i| ((i + 128) % 256 - 128) as i8)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i8 data incorrectly initialised")
+});
+static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| {
+    (0..128 * 5)
+        .map(|i| i as i16)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i16 data incorrectly initialised")
+});
+static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as i32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i32 data incorrectly initialised")
+});
+static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| {
+    (0..32 * 5)
+        .map(|i| i as i64)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i64 data incorrectly initialised")
+});
+static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| {
+    (0..256 * 5)
+        .map(|i| i as u8)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u8 data incorrectly initialised")
+});
+static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| {
+    (0..128 * 5)
+        .map(|i| i as u16)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u16 data incorrectly initialised")
+});
+static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as u32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u32 data incorrectly initialised")
+});
+static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| {
+    (0..32 * 5)
+        .map(|i| i as u64)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u64 data incorrectly initialised")
+});
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_f32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b64(), defined));
+    let cmp = svcmpne_f64(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b8(), defined));
+    let cmp = svcmpne_s8(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b16(), defined));
+    let cmp = svcmpne_s16(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_s32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b64(), defined));
+    let cmp = svcmpne_s64(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b8(), defined));
+    let cmp = svcmpne_u8(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b16(), defined));
+    let cmp = svcmpne_u16(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_u32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b64(), defined));
+    let cmp = svcmpne_u64(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_s64index_f64_with_svstnt1_scatter_s64index_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let indices = svindex_s64(0, 1);
+    svstnt1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_s64index_s64_with_svstnt1_scatter_s64index_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_s64index_u64_with_svstnt1_scatter_s64index_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64index_f64_with_svstnt1_scatter_u64index_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let indices = svindex_u64(0, 1);
+    svstnt1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64index_s64_with_svstnt1_scatter_u64index_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64index_u64_with_svstnt1_scatter_u64index_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_s64offset_f64_with_svstnt1_scatter_s64offset_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svstnt1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_s64offset_s64_with_svstnt1_scatter_s64offset_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svstnt1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_s64offset_u64_with_svstnt1_scatter_s64offset_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
+    svstnt1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32offset_f32_with_svstnt1_scatter_u32offset_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets);
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32offset_s32_with_svstnt1_scatter_u32offset_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32offset_u32_with_svstnt1_scatter_u32offset_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64offset_f64_with_svstnt1_scatter_u64offset_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svstnt1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64offset_s64_with_svstnt1_scatter_u64offset_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svstnt1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64offset_u64_with_svstnt1_scatter_u64offset_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    svstnt1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_f64_with_svstnt1_scatter_u64base_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_f64(svptrue_b64(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_f64(svptrue_b64(), bases);
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_s64_with_svstnt1_scatter_u64base_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_s64(svptrue_b64(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_s64(svptrue_b64(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_u64_with_svstnt1_scatter_u64base_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_u64(svptrue_b64(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_u64(svptrue_b64(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32base_index_f32_with_svstnt1_scatter_u32base_index_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32base_index_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u32base_index_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32base_index_s32_with_svstnt1_scatter_u32base_index_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32base_index_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u32base_index_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32base_index_u32_with_svstnt1_scatter_u32base_index_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32base_index_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u32base_index_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_index_f64_with_svstnt1_scatter_u64base_index_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_index_s64_with_svstnt1_scatter_u64base_index_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_index_u64_with_svstnt1_scatter_u64base_index_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32base_offset_f32_with_svstnt1_scatter_u32base_offset_f32() {
+    let mut storage = [0 as f32; 320usize];
+    let data = svcvt_f32_s32_x(
+        svptrue_b32(),
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32base_offset_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f32 || val == i as f32);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u32base_offset_f32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32base_offset_s32_with_svstnt1_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32base_offset_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u32base_offset_s32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u32base_offset_u32_with_svstnt1_scatter_u32base_offset_u32() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svstnt1_scatter_u32base_offset_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u32base_offset_u32(
+        svptrue_b32(),
+        bases,
+        storage.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_offset_f64_with_svstnt1_scatter_u64base_offset_f64() {
+    let mut storage = [0 as f64; 160usize];
+    let data = svcvt_f64_s64_x(
+        svptrue_b64(),
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as f64 || val == i as f64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_offset_s64_with_svstnt1_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i64; 160usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i64 || val == i as i64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1_gather_u64base_offset_u64_with_svstnt1_scatter_u64base_offset_u64() {
+    let mut storage = [0 as u64; 160usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svstnt1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u64 || val == i as u64);
+    }
+    svsetffr();
+    let loaded = svldnt1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1sb_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1sb_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1sb_gather_u64base_s64(svptrue_b8(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u64base_s64(svptrue_b16(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1sw_gather_u64base_s64(svptrue_b32(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sb_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1sb_gather_u64base_u64(svptrue_b8(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u64base_u64(svptrue_b16(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1sw_gather_u64base_u64(svptrue_b32(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1sw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() {
+    let mut storage = [0 as u8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u8 || val == i as u8);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1ub_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svstnt1b_scatter_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1ub_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        storage.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1ub_gather_u64base_s64(svptrue_b8(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u64base_s64(svptrue_b16(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1uw_gather_u64base_s64(svptrue_b32(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1ub_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() {
+    let mut storage = [0 as i8; 1280usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i8 || val == i as i8);
+    }
+    svsetffr();
+    let loaded = svldnt1ub_gather_u64base_u64(svptrue_b8(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u64base_u64(svptrue_b16(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1uw_gather_u64base_u64(svptrue_b32(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_s64(0, 1);
+    svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() {
+    let mut storage = [0 as u16; 640usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u16 || val == i as u16);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() {
+    let mut storage = [0 as u32; 320usize];
+    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let indices = svindex_u64(0, 1);
+    svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as u32 || val == i as u32);
+    }
+    svsetffr();
+    let loaded =
+        svldnt1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svstnt1h_scatter_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+        data,
+    );
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        storage.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() {
+    let mut storage = [0 as i16; 640usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i16 || val == i as i16);
+    }
+    svsetffr();
+    let loaded = svldnt1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve,sve2")]
+unsafe fn test_svldnt1uw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() {
+    let mut storage = [0 as i32; 320usize];
+    let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
+    let bases = svdup_n_u64(storage.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data);
+    for (i, &val) in storage.iter().enumerate() {
+        assert!(val == 0 as i32 || val == i as i32);
+    }
+    svsetffr();
+    let loaded = svldnt1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}

From c2f8104e2b4d0fc8dd2bdbae7e9925148ffebd95 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Sat, 28 Feb 2026 21:24:33 +0000
Subject: [PATCH 238/326] intrinsics_data: add sve intrinsics

Co-authored-by: Adam Gemmell <Adam.Gemmell@arm.com>
Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
---
 intrinsics_data/arm_intrinsics.json | 270972 ++++++++++++++++++++++---
 1 file changed, 238271 insertions(+), 32701 deletions(-)

diff --git a/intrinsics_data/arm_intrinsics.json b/intrinsics_data/arm_intrinsics.json
index bce85d19a1..3a3b962a48 100644
--- a/intrinsics_data/arm_intrinsics.json
+++ b/intrinsics_data/arm_intrinsics.json
@@ -224,21 +224,25 @@
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vscale_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_s16]",
     "arguments": [
-      "float16x4_t a",
-      "int16x4_t b"
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
@@ -246,26 +250,34 @@
     ],
     "instructions": [
       [
-        "FSCALE"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vscaleq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_s32]",
     "arguments": [
-      "float16x8_t a",
-      "int16x8_t b"
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
@@ -273,26 +285,34 @@
     ],
     "instructions": [
       [
-        "FSCALE"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vscale_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_s64]",
     "arguments": [
-      "float32x2_t a",
-      "int32x2_t b"
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
@@ -300,26 +320,34 @@
     ],
     "instructions": [
       [
-        "FSCALE"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vscaleq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_s8]",
     "arguments": [
-      "float32x4_t a",
-      "int32x4_t b"
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -327,26 +355,34 @@
     ],
     "instructions": [
       [
-        "FSCALE"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vscaleq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_u16]",
     "arguments": [
-      "float64x2_t a",
-      "int64x2_t b"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
@@ -354,228 +390,244 @@
     ],
     "instructions": [
       [
-        "FSCALE"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaba_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_u32]",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.4H"
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABA"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaba_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_u64]",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.D"
       },
-      "c": {
-        "register": "Vm.2S"
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABA"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaba_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_n_u8]",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b",
-      "int8x8_t c"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.8B"
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABA"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaba_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_s16]",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t c"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.4H"
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABA"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaba_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_s32]",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t c"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.2S"
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABA"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaba_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_s64]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "uint8x8_t c"
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D"
       },
-      "c": {
-        "register": "Vm.8B"
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABA"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_high_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_s8]",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.8H"
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -583,30 +635,34 @@
     ],
     "instructions": [
       [
-        "SABAL2"
+        "SABA"
+      ],
+      [
+        "MOVPRFX",
+        "SABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_high_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_u16]",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.4S"
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -614,30 +670,34 @@
     ],
     "instructions": [
       [
-        "SABAL2"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_high_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_u32]",
     "arguments": [
-      "int16x8_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.16B"
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -645,30 +705,34 @@
     ],
     "instructions": [
       [
-        "SABAL2"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_high_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_u64]",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D"
       },
-      "c": {
-        "register": "Vm.8H"
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -676,30 +740,34 @@
     ],
     "instructions": [
       [
-        "UABAL2"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_high_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaba[_u8]",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.4S"
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -707,30 +775,34 @@
     ],
     "instructions": [
       [
-        "UABAL2"
+        "UABA"
+      ],
+      [
+        "MOVPRFX",
+        "UABA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_high_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_n_s16]",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.16B"
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -738,479 +810,524 @@
     ],
     "instructions": [
       [
-        "UABAL2"
+        "SABALB"
+      ],
+      [
+        "MOVPRFX",
+        "SABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_n_s32]",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.4H"
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABAL"
+        "SABALB"
+      ],
+      [
+        "MOVPRFX",
+        "SABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_n_s64]",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.2S"
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABAL"
+        "SABALB"
+      ],
+      [
+        "MOVPRFX",
+        "SABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_n_u16]",
     "arguments": [
-      "int16x8_t a",
-      "int8x8_t b",
-      "int8x8_t c"
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.8B"
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABAL"
+        "UABALB"
+      ],
+      [
+        "MOVPRFX",
+        "UABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_n_u32]",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t c"
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.4H"
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABAL"
+        "UABALB"
+      ],
+      [
+        "MOVPRFX",
+        "UABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_n_u64]",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t c"
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.2S"
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABAL"
+        "UABALB"
+      ],
+      [
+        "MOVPRFX",
+        "UABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabal_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_s16]",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b",
-      "uint8x8_t c"
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.8B"
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABAL"
+        "SABALB"
+      ],
+      [
+        "MOVPRFX",
+        "SABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabaq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_s32]",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.8H"
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABA"
+        "SABALB"
+      ],
+      [
+        "MOVPRFX",
+        "SABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabaq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_s64]",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.4S"
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABA"
+        "SABALB"
+      ],
+      [
+        "MOVPRFX",
+        "SABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabaq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_u16]",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.16B"
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABA"
+        "UABALB"
+      ],
+      [
+        "MOVPRFX",
+        "UABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabaq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_u32]",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.8H"
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABA"
+        "UABALB"
+      ],
+      [
+        "MOVPRFX",
+        "UABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabaq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalb[_u64]",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.4S"
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABA"
+        "UABALB"
+      ],
+      [
+        "MOVPRFX",
+        "UABALB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabaq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_n_s16]",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B"
       },
-      "c": {
-        "register": "Vm.16B"
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABA"
+        "SABALT"
+      ],
+      [
+        "MOVPRFX",
+        "SABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_n_s32]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABD"
+        "SABALT"
+      ],
+      [
+        "MOVPRFX",
+        "SABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_n_s64]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABD"
+        "SABALT"
+      ],
+      [
+        "MOVPRFX",
+        "SABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_n_u16]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -1218,200 +1335,244 @@
     ],
     "instructions": [
       [
-        "FABD"
+        "UABALT"
+      ],
+      [
+        "MOVPRFX",
+        "UABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_n_u32]",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABD"
+        "UABALT"
+      ],
+      [
+        "MOVPRFX",
+        "UABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_n_u64]",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABD"
+        "UABALT"
+      ],
+      [
+        "MOVPRFX",
+        "UABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_s16]",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABD"
+        "SABALT"
+      ],
+      [
+        "MOVPRFX",
+        "SABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_s32]",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABD"
+        "SABALT"
+      ],
+      [
+        "MOVPRFX",
+        "SABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_s64]",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABD"
+        "SABALT"
+      ],
+      [
+        "MOVPRFX",
+        "SABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabd_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_u16]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABD"
+        "UABALT"
+      ],
+      [
+        "MOVPRFX",
+        "UABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_u32]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -1419,26 +1580,34 @@
     ],
     "instructions": [
       [
-        "FABD"
+        "UABALT"
+      ],
+      [
+        "MOVPRFX",
+        "UABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdh_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabalt[_u64]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -1446,26 +1615,34 @@
     ],
     "instructions": [
       [
-        "FABD"
+        "UABALT"
+      ],
+      [
+        "MOVPRFX",
+        "UABALT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_high_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f16]_m",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -1473,26 +1650,34 @@
     ],
     "instructions": [
       [
-        "SABDL2"
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_high_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f16]_x",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -1500,26 +1685,37 @@
     ],
     "instructions": [
       [
-        "SABDL2"
+        "FABD"
+      ],
+      [
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_high_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f16]_z",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -1527,26 +1723,35 @@
     ],
     "instructions": [
       [
-        "SABDL2"
+        "MOVPRFX",
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_high_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f32]_m",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -1554,26 +1759,34 @@
     ],
     "instructions": [
       [
-        "UABDL2"
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_high_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f32]_x",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -1581,26 +1794,37 @@
     ],
     "instructions": [
       [
-        "UABDL2"
+        "FABD"
+      ],
+      [
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_high_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f32]_z",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -1608,257 +1832,326 @@
     ],
     "instructions": [
       [
-        "UABDL2"
+        "MOVPRFX",
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f64]_m",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABDL"
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f64]_x",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABDL"
+        "FABD"
+      ],
+      [
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_f64]_z",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABDL"
+        "MOVPRFX",
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f16]_m",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABDL"
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f16]_x",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABDL"
+        "FABD"
+      ],
+      [
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdl_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f16]_z",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABDL"
+        "MOVPRFX",
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f32]_m",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
         "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f32]_x",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
         "FABD"
+      ],
+      [
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f32]_z",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -1866,200 +2159,253 @@
     ],
     "instructions": [
       [
+        "MOVPRFX",
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
         "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f64]_m",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABD"
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f64]_x",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABD"
+        "FABD"
+      ],
+      [
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_f64]_z",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SABD"
+        "MOVPRFX",
+        "FABD"
+      ],
+      [
+        "MOVPRFX",
+        "FABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s16]_m",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABD"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s16]_x",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABD"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabdq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s16]_z",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UABD"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabds_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s32]_m",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -2067,71 +2413,108 @@
     ],
     "instructions": [
       [
-        "FABD"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s32]_x",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABS"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s32]_z",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABS"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s64]_m",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -2139,72 +2522,108 @@
     ],
     "instructions": [
       [
-        "FABS"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s64]_x",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ABS"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s64]_z",
     "arguments": [
-      "int32x2_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ABS"
-      ]
-    ]
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
+      ]
+    ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s8]_m",
     "arguments": [
-      "int64x1_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -2212,47 +2631,72 @@
     ],
     "instructions": [
       [
-        "ABS"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabs_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s8]_x",
     "arguments": [
-      "int8x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ABS"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_s8]_z",
     "arguments": [
-      "int64_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -2260,95 +2704,144 @@
     ],
     "instructions": [
       [
-        "ABS"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u16]_m",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABS"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u16]_x",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABS"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u16]_z",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FABS"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u32]_m",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -2356,72 +2849,108 @@
     ],
     "instructions": [
       [
-        "FABS"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u32]_x",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ABS"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u32]_z",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ABS"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u64]_m",
     "arguments": [
-      "int64x2_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -2429,108 +2958,143 @@
     ],
     "instructions": [
       [
-        "ABS"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vabsq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u64]_x",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ABS"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u64]_z",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADD"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u8]_m",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADD"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u8]_x",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -2538,345 +3102,435 @@
     ],
     "instructions": [
       [
-        "FADD"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_n_u8]_z",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s16]_m",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s16]_x",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s16]_z",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s32]_m",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s32]_x",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s32]_z",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s64]_m",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s64]_x",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s64]_z",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vadd_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s8]_m",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s8]_x",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -2884,26 +3538,37 @@
     ],
     "instructions": [
       [
-        "ADD"
+        "SABD"
+      ],
+      [
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddd_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_s8]_z",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -2911,58 +3576,70 @@
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "SABD"
+      ],
+      [
+        "MOVPRFX",
+        "SABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u16]_m",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADD"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_high_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u16]_x",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
       },
-      "r": {
-        "register": "Vd.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -2970,30 +3647,37 @@
     ],
     "instructions": [
       [
-        "ADDHN2"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_high_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u16]_z",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "r": {
-        "register": "Vd.4H"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -3001,30 +3685,35 @@
     ],
     "instructions": [
       [
-        "ADDHN2"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_high_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u32]_m",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -3032,30 +3721,34 @@
     ],
     "instructions": [
       [
-        "ADDHN2"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_high_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u32]_x",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
       },
-      "r": {
-        "register": "Vd.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -3063,30 +3756,37 @@
     ],
     "instructions": [
       [
-        "ADDHN2"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_high_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u32]_z",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -3094,30 +3794,35 @@
     ],
     "instructions": [
       [
-        "ADDHN2"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_high_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u64]_m",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.D"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -3125,200 +3830,240 @@
     ],
     "instructions": [
       [
-        "ADDHN2"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u64]_x",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDHN"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u64]_z",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDHN"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u8]_m",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDHN"
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u8]_x",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDHN"
+        "UABD"
+      ],
+      [
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabd[_u8]_z",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDHN"
+        "MOVPRFX",
+        "UABD"
+      ],
+      [
+        "MOVPRFX",
+        "UABD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddhn_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_n_s16]",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDHN"
+        "SABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_high_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_n_s32]",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -3326,26 +4071,26 @@
     ],
     "instructions": [
       [
-        "SADDL2"
+        "SABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_high_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_n_s64]",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -3353,26 +4098,26 @@
     ],
     "instructions": [
       [
-        "SADDL2"
+        "SABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_high_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_n_u16]",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -3380,26 +4125,26 @@
     ],
     "instructions": [
       [
-        "SADDL2"
+        "UABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_high_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_n_u32]",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -3407,26 +4152,26 @@
     ],
     "instructions": [
       [
-        "UADDL2"
+        "UABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_high_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_n_u64]",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -3434,26 +4179,26 @@
     ],
     "instructions": [
       [
-        "UADDL2"
+        "UABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_high_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_s16]",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -3461,196 +4206,188 @@
     ],
     "instructions": [
       [
-        "UADDL2"
+        "SABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_s32]",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDL"
+        "SABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_s64]",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDL"
+        "SABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_u16]",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDL"
+        "UABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_u32]",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDL"
+        "UABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlb[_u64]",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDL"
+        "UABDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddl_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_n_s16]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDL"
+        "SABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlv_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_n_s32]",
     "arguments": [
-      "int16x4_t a"
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -3658,22 +4395,26 @@
     ],
     "instructions": [
       [
-        "SADDLV"
+        "SABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlv_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_n_s64]",
     "arguments": [
-      "int32x2_t a"
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -3681,22 +4422,26 @@
     ],
     "instructions": [
       [
-        "SADDLP"
+        "SABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlv_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_n_u16]",
     "arguments": [
-      "int8x8_t a"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -3704,22 +4449,26 @@
     ],
     "instructions": [
       [
-        "SADDLV"
+        "UABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlv_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_n_u32]",
     "arguments": [
-      "uint16x4_t a"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -3727,22 +4476,26 @@
     ],
     "instructions": [
       [
-        "UADDLV"
+        "UABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlv_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_n_u64]",
     "arguments": [
-      "uint32x2_t a"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -3750,22 +4503,26 @@
     ],
     "instructions": [
       [
-        "UADDLP"
+        "UABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlv_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_s16]",
     "arguments": [
-      "uint8x8_t a"
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -3773,22 +4530,26 @@
     ],
     "instructions": [
       [
-        "UADDLV"
+        "SABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlvq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_s32]",
     "arguments": [
-      "int16x8_t a"
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -3796,22 +4557,26 @@
     ],
     "instructions": [
       [
-        "SADDLV"
+        "SABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlvq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_s64]",
     "arguments": [
-      "int32x4_t a"
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -3819,22 +4584,26 @@
     ],
     "instructions": [
       [
-        "SADDLV"
+        "SABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlvq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_u16]",
     "arguments": [
-      "int8x16_t a"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -3842,22 +4611,26 @@
     ],
     "instructions": [
       [
-        "SADDLV"
+        "UABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlvq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_u32]",
     "arguments": [
-      "uint16x8_t a"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -3865,22 +4638,26 @@
     ],
     "instructions": [
       [
-        "UADDLV"
+        "UABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlvq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svabdlt[_u64]",
     "arguments": [
-      "uint32x4_t a"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -3888,22 +4665,30 @@
     ],
     "instructions": [
       [
-        "UADDLV"
+        "UABDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddlvq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f16]_m",
     "arguments": [
-      "uint8x16_t a"
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -3911,83 +4696,93 @@
     ],
     "instructions": [
       [
-        "UADDLV"
+        "FABS"
+      ],
+      [
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f16]_x",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADD"
+        "FABS"
+      ],
+      [
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f16]_z",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADD"
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f32]_m",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -3995,370 +4790,406 @@
     ],
     "instructions": [
       [
-        "FADD"
+        "FABS"
+      ],
+      [
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_p128",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f32]_x",
     "arguments": [
-      "poly128_t a",
-      "poly128_t b"
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "FABS"
+      ],
+      [
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f32]_z",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b"
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f64]_m",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "FABS"
+      ],
+      [
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f64]_x",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.D|Ztied.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "FABS"
+      ],
+      [
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_f64]_z",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "FABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s16]_m",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s16]_x",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op": {
+        "register": "Zop.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s16]_z",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s32]_m",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s32]_x",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op": {
+        "register": "Zop.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s32]_z",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s64]_m",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADD"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s64]_x",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4366,22 +5197,30 @@
     ],
     "instructions": [
       [
-        "FADDP"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s64]_z",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4389,22 +5228,31 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s8]_m",
     "arguments": [
-      "int32x2_t a"
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -4412,22 +5260,30 @@
     ],
     "instructions": [
       [
-        "ADDP"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s8]_x",
     "arguments": [
-      "int8x8_t a"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -4435,22 +5291,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "ABS"
+      ],
+      [
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svabs[_s8]_z",
     "arguments": [
-      "uint16x4_t a"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -4458,22 +5322,31 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "MOVPRFX",
+        "ABS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svacge[_f16]",
     "arguments": [
-      "uint32x2_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -4481,22 +5354,30 @@
     ],
     "instructions": [
       [
-        "ADDP"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddv_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svacge[_f32]",
     "arguments": [
-      "uint8x8_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -4504,22 +5385,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svacge[_f64]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4527,23 +5416,30 @@
     ],
     "instructions": [
       [
-        "FADDP",
-        "FADDP"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svacge[_n_f16]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -4551,22 +5447,30 @@
     ],
     "instructions": [
       [
-        "FADDP"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svacge[_n_f32]",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -4574,22 +5478,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svacge[_n_f64]",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4597,22 +5509,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svacgt[_f16]",
     "arguments": [
-      "int64x2_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -4620,22 +5540,30 @@
     ],
     "instructions": [
       [
-        "ADDP"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svacgt[_f32]",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -4643,22 +5571,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svacgt[_f64]",
     "arguments": [
-      "uint16x8_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4666,22 +5602,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svacgt[_n_f16]",
     "arguments": [
-      "uint32x4_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -4689,22 +5633,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svacgt[_n_f32]",
     "arguments": [
-      "uint64x2_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -4712,22 +5664,30 @@
     ],
     "instructions": [
       [
-        "ADDP"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddvq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svacgt[_n_f64]",
     "arguments": [
-      "uint8x16_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4735,26 +5695,30 @@
     ],
     "instructions": [
       [
-        "ADDV"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_high_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svacle[_f16]",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -4762,26 +5726,30 @@
     ],
     "instructions": [
       [
-        "SADDW2"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_high_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svacle[_f32]",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -4789,26 +5757,30 @@
     ],
     "instructions": [
       [
-        "SADDW2"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_high_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svacle[_f64]",
     "arguments": [
-      "int16x8_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4816,26 +5788,30 @@
     ],
     "instructions": [
       [
-        "SADDW2"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_high_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svacle[_n_f16]",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -4843,26 +5819,30 @@
     ],
     "instructions": [
       [
-        "UADDW2"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_high_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svacle[_n_f32]",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -4870,26 +5850,30 @@
     ],
     "instructions": [
       [
-        "UADDW2"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_high_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svacle[_n_f64]",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -4897,1518 +5881,1906 @@
     ],
     "instructions": [
       [
-        "UADDW2"
+        "FACGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svaclt[_f16]",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDW"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svaclt[_f32]",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDW"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svaclt[_f64]",
     "arguments": [
-      "int16x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDW"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svaclt[_n_f16]",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDW"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svaclt[_n_f32]",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDW"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaddw_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svaclt[_n_f64]",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDW"
+        "FACGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaesdq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s16]_m",
     "arguments": [
-      "uint8x16_t data",
-      "uint8x16_t key"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "data": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "key": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AESD"
+        "SADALP"
+      ],
+      [
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaeseq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s16]_x",
     "arguments": [
-      "uint8x16_t data",
-      "uint8x16_t key"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "data": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "key": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AESE"
+        "SADALP"
+      ],
+      [
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaesimcq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s16]_z",
     "arguments": [
-      "uint8x16_t data"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "data": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AESIMC"
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vaesmcq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s32]_m",
     "arguments": [
-      "uint8x16_t data"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "data": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AESMC"
+        "SADALP"
+      ],
+      [
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s32]_x",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "SADALP"
+      ],
+      [
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s32]_z",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s64]_m",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "SADALP"
+      ],
+      [
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s64]_x",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "SADALP"
+      ],
+      [
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_s64]_z",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "MOVPRFX",
+        "SADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u16]_m",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "UADALP"
+      ],
+      [
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u16]_x",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "UADALP"
+      ],
+      [
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vand_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u16]_z",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u32]_m",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "UADALP"
+      ],
+      [
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u32]_x",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "UADALP"
+      ],
+      [
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u32]_z",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u64]_m",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "UADALP"
+      ],
+      [
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u64]_x",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "UADALP"
+      ],
+      [
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svadalp[_u64]_z",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "MOVPRFX",
+        "UADALP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclb[_n_u32]",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "ADCLB"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vandq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclb[_n_u64]",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "AND"
+        "ADCLB"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclb[_u32]",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       },
-      "b": {},
-      "c": {}
+      "op3": {
+        "register": "Zop3.S"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "ADCLB"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclb[_u64]",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       },
-      "b": {},
-      "c": {}
+      "op3": {
+        "register": "Zop3.D"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "ADCLB"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclt[_n_u32]",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b",
-      "int64x2_t c"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       },
-      "b": {},
-      "c": {}
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "ADCLT"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclt[_n_u64]",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       },
-      "b": {},
-      "c": {}
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "ADCLT"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclt[_u32]",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       },
-      "b": {},
-      "c": {}
+      "op3": {
+        "register": "Zop3.S"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "ADCLT"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svadclt[_u64]",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       },
-      "b": {},
-      "c": {}
+      "op3": {
+        "register": "Zop3.D"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "ADCLT"
+      ],
+      [
+        "MOVPRFX",
+        "ADCLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f16]_m",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
-      "uint64x2_t c"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.H"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbcaxq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f16]_x",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.H"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "BCAX"
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f16]_z",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f32]_m",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f32]_x",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f32]_z",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f64]_m",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f64]_x",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_f64]_z",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbic_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f16]_m",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f16]_x",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f16]_z",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f32]_m",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Ztied1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f32]_x",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f32]_z",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_u32",
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f64]_m",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Ztied1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f64]_x",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbicq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_f64]_z",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BIC"
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s16]_m",
     "arguments": [
-      "uint16x4_t a",
-      "float16x4_t b",
-      "float16x4_t c"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.H[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s16]_x",
     "arguments": [
-      "uint32x2_t a",
-      "float32x2_t b",
-      "float32x2_t c"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s16]_z",
     "arguments": [
-      "uint64x1_t a",
-      "float64x1_t b",
-      "float64x1_t c"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.H[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -6416,458 +7788,526 @@
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s32]_m",
     "arguments": [
-      "uint16x4_t a",
-      "poly16x4_t b",
-      "poly16x4_t c"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s32]_x",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b",
-      "poly64x1_t c"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s32]_z",
     "arguments": [
-      "uint8x8_t a",
-      "poly8x8_t b",
-      "poly8x8_t c"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s64]_m",
     "arguments": [
-      "uint16x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s64]_x",
     "arguments": [
-      "uint32x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s64]_z",
     "arguments": [
-      "uint64x1_t a",
-      "int64x1_t b",
-      "int64x1_t c"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s8]_m",
     "arguments": [
-      "uint8x8_t a",
-      "int8x8_t b",
-      "int8x8_t c"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s8]_x",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t c"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_s8]_z",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t c"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u16]_m",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b",
-      "uint64x1_t c"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.H[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbsl_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u16]_x",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "uint8x8_t c"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
       },
-      "c": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u16]_z",
     "arguments": [
-      "uint16x8_t a",
-      "float16x8_t b",
-      "float16x8_t c"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.H[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u32]_m",
     "arguments": [
-      "uint32x4_t a",
-      "float32x4_t b",
-      "float32x4_t c"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u32]_x",
     "arguments": [
-      "uint64x2_t a",
-      "float64x2_t b",
-      "float64x2_t c"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -6875,556 +8315,665 @@
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u32]_z",
     "arguments": [
-      "uint16x8_t a",
-      "poly16x8_t b",
-      "poly16x8_t c"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u64]_m",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b",
-      "poly64x2_t c"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u64]_x",
     "arguments": [
-      "uint8x16_t a",
-      "poly8x16_t b",
-      "poly8x16_t c"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u64]_z",
     "arguments": [
-      "uint16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u8]_m",
     "arguments": [
-      "uint32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u8]_x",
     "arguments": [
-      "uint64x2_t a",
-      "int64x2_t b",
-      "int64x2_t c"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_n_u8]_z",
     "arguments": [
-      "uint8x16_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B[*]"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s16]_m",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s16]_x",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s16]_z",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
-      "uint64x2_t c"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vbslq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s32]_m",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "c": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "BSL"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcadd_rot270_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s32]_x",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H "
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcadd_rot270_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s32]_z",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S "
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcadd_rot90_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s64]_m",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H "
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcadd_rot90_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s64]_x",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S "
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaddq_rot270_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s64]_z",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H "
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaddq_rot270_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s8]_m",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S "
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaddq_rot270_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s8]_x",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D "
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -7432,82 +8981,107 @@
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaddq_rot90_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_s8]_z",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H "
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaddq_rot90_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u16]_m",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S "
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaddq_rot90_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u16]_x",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D "
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -7515,83 +9089,107 @@
     ],
     "instructions": [
       [
-        "FCADD"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcage_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u16]_z",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcage_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u32]_m",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcage_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u32]_x",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -7599,26 +9197,36 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaged_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u32]_z",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -7626,26 +9234,35 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcageh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u64]_m",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -7653,83 +9270,107 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcageq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u64]_x",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcageq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u64]_z",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcageq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u8]_m",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -7737,26 +9378,34 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcages_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u8]_x",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -7764,83 +9413,103 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADD"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagt_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadd[_u8]_z",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "MOVPRFX",
+        "ADD"
+      ],
+      [
+        "MOVPRFX",
+        "ADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagt_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadda[_f16]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "float16_t initial",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "initial": {
+        "register": "Htied"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "FADDA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagt_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadda[_f32]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "float32_t initial",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "initial": {
+        "register": "Stied"
       },
-      "b": {
-        "register": "Dm"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -7848,26 +9517,30 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "FADDA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagtd_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadda[_f64]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svbool_t pg",
+      "float64_t initial",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "initial": {
+        "register": "Dtied"
       },
-      "b": {
-        "register": "Dm"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -7875,26 +9548,26 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "FADDA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagth_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_n_s16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -7902,83 +9575,80 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagtq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_n_s32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagtq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_n_s64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagtq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_n_u16]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -7986,26 +9656,26 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcagts_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_n_u32]",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -8013,83 +9683,80 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcale_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_n_u64]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcale_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_s16]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcale_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_s32]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -8097,26 +9764,26 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaled_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_s64]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
@@ -8124,26 +9791,26 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaleh_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_u16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -8151,83 +9818,84 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaleq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_u32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaleq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnb[_u64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaleq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_n_s16]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svint8_t even",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "even": {
+        "register": "Ztied.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -8235,26 +9903,30 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcales_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_n_s32]",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svint16_t even",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "even": {
+        "register": "Ztied.H"
       },
-      "b": {
-        "register": "Sm"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -8262,83 +9934,92 @@
     ],
     "instructions": [
       [
-        "FACGE"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcalt_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_n_s64]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svint32_t even",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "even": {
+        "register": "Ztied.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcalt_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_n_u16]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "even": {
+        "register": "Ztied.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcalt_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_n_u32]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "even": {
+        "register": "Ztied.H"
       },
-      "b": {
-        "register": "Dm"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -8346,26 +10027,30 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaltd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_n_u64]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "even": {
+        "register": "Ztied.S"
       },
-      "b": {
-        "register": "Dm"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
@@ -8373,26 +10058,30 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcalth_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_s16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svint8_t even",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "even": {
+        "register": "Ztied.B"
       },
-      "b": {
-        "register": "Hm"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -8400,83 +10089,92 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaltq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_s32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svint16_t even",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "even": {
+        "register": "Ztied.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaltq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_s64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svint32_t even",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "even": {
+        "register": "Ztied.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcaltq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_u16]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svuint8_t even",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "even": {
+        "register": "Ztied.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -8484,26 +10182,30 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcalts_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_u32]",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svuint16_t even",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "even": {
+        "register": "Ztied.H"
       },
-      "b": {
-        "register": "Sm"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -8511,83 +10213,84 @@
     ],
     "instructions": [
       [
-        "FACGT"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddhnt[_u64]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svuint32_t even",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "even": {
+        "register": "Ztied.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "ADDHNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_n_s16]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_n_s32]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -8595,141 +10298,134 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_n_s64]",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b"
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_n_u16]",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_n_u32]",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_n_u64]",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_s16]",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -8737,113 +10433,107 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_s32]",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_s64]",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_u16]",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_u32]",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -8851,55 +10541,53 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlb[_u64]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlbt[_n_s16]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -8907,26 +10595,26 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLBT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqd_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlbt[_n_s32]",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -8934,26 +10622,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLBT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqd_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlbt[_n_s64]",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -8961,26 +10649,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLBT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqh_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlbt[_s16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -8988,83 +10676,80 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLBT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlbt[_s32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLBT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlbt[_s64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLBT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_n_s16]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -9072,141 +10757,134 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "SADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_n_s32]",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_n_s64]",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_n_u16]",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_n_u32]",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_n_u64]",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -9214,113 +10892,107 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_s16]",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_s32]",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_s64]",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_u16]",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -9328,55 +11000,53 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_u32]",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqs_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddlt[_u64]",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -9384,46 +11054,65 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "UADDLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_f16]_m",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "FADDP"
+      ],
+      [
+        "MOVPRFX",
+        "FADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_f16]_x",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9431,22 +11120,34 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "FADDP"
+      ],
+      [
+        "MOVPRFX",
+        "FADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_f32]_m",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -9454,46 +11155,69 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "FADDP"
+      ],
+      [
+        "MOVPRFX",
+        "FADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_f32]_x",
     "arguments": [
-      "poly64x1_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "FADDP"
+      ],
+      [
+        "MOVPRFX",
+        "FADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_f64]_m",
     "arguments": [
-      "poly8x8_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9501,22 +11225,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "FADDP"
+      ],
+      [
+        "MOVPRFX",
+        "FADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_f64]_x",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9524,22 +11260,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "FADDP"
+      ],
+      [
+        "MOVPRFX",
+        "FADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s16]_m",
     "arguments": [
-      "int32x2_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9547,22 +11295,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s16]_x",
     "arguments": [
-      "int64x1_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9570,22 +11330,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s32]_m",
     "arguments": [
-      "int8x8_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -9593,22 +11365,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s32]_x",
     "arguments": [
-      "uint16x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -9616,22 +11400,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s64]_m",
     "arguments": [
-      "uint32x2_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9639,22 +11435,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s64]_x",
     "arguments": [
-      "uint64x1_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9662,22 +11470,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqz_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s8]_m",
     "arguments": [
-      "uint8x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -9685,22 +11505,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_s8]_x",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -9708,22 +11540,34 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzd_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u16]_m",
     "arguments": [
-      "int64_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9731,22 +11575,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzd_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u16]_x",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9754,22 +11610,34 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzh_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u32]_m",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -9777,46 +11645,69 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u32]_x",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u64]_m",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9824,22 +11715,34 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u64]_x",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9847,46 +11750,69 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u8]_m",
     "arguments": [
-      "poly64x2_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddp[_u8]_x",
     "arguments": [
-      "poly8x16_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -9894,22 +11820,30 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "ADDP"
+      ],
+      [
+        "MOVPRFX",
+        "ADDP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_f16]",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9917,22 +11851,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "FADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_f32]",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -9940,22 +11878,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "FADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_f64]",
     "arguments": [
-      "int64x2_t a"
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -9963,22 +11905,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "FADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_s16]",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -9986,22 +11932,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_s32]",
     "arguments": [
-      "uint16x8_t a"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -10009,22 +11959,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_s64]",
     "arguments": [
-      "uint32x4_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -10032,22 +11986,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_s8]",
     "arguments": [
-      "uint64x2_t a"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -10055,22 +12013,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "SADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_u16]",
     "arguments": [
-      "uint8x16_t a"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -10078,22 +12040,26 @@
     ],
     "instructions": [
       [
-        "CMEQ"
+        "UADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vceqzs_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_u32]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -10101,83 +12067,80 @@
     ],
     "instructions": [
       [
-        "FCMEQ"
+        "UADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_u64]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "UADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svaddv[_u8]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op": {
+        "register": "Zop.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "UADDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_n_s16]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svint16_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -10185,84 +12148,80 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "SADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_n_s32]",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svint32_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "SADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_n_s64]",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svint64_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "SADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_n_u16]",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svuint16_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -10270,113 +12229,107 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "UADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_n_u32]",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svuint32_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "UADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_n_u64]",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svuint64_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "UADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_s16]",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svint16_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "SADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_s32]",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svint32_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -10384,55 +12337,53 @@
     ],
     "instructions": [
       [
-        "CMHS"
+        "SADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcge_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_s64]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svint64_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "SADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcged_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_u16]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svuint16_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -10440,26 +12391,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "UADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcged_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_u32]",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "svuint32_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -10467,26 +12418,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "UADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcged_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwb[_u64]",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "svuint64_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -10494,26 +12445,26 @@
     ],
     "instructions": [
       [
-        "CMHS"
+        "UADDWB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeh_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_n_s16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svint16_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -10521,83 +12472,80 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "SADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_n_s32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svint32_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "SADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_n_s64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svint64_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "SADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_n_u16]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svuint16_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -10605,84 +12553,80 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "UADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_n_u32]",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svuint32_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "UADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_n_u64]",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svuint64_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "UADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_s16]",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svint16_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -10690,113 +12634,107 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "SADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_s32]",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svint32_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "SADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_s64]",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svint64_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "SADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_u16]",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svuint16_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "UADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_u32]",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svuint32_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -10804,55 +12742,53 @@
     ],
     "instructions": [
       [
-        "CMHS"
+        "UADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgeq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaddwt[_u64]",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svuint64_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "UADDWT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcges_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadrb[_u32base]_[s32]offset",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svuint32_t bases",
+      "svint32_t offsets"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "bases": {
+        "register": "Zbases.S"
       },
-      "b": {
-        "register": "Sm"
+      "offsets": {
+        "register": "Zoffsets.S"
       }
     },
     "Architectures": [
@@ -10860,46 +12796,53 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadrb[_u32base]_[u32]offset",
     "arguments": [
-      "float16x4_t a"
+      "svuint32_t bases",
+      "svuint32_t offsets"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadrb[_u64base]_[s64]offset",
     "arguments": [
-      "float32x2_t a"
+      "svuint64_t bases",
+      "svint64_t offsets"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
       }
     },
     "Architectures": [
@@ -10907,22 +12850,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadrb[_u64base]_[u64]offset",
     "arguments": [
-      "float64x1_t a"
+      "svuint64_t bases",
+      "svuint64_t offsets"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
       }
     },
     "Architectures": [
@@ -10930,22 +12877,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svadrd[_u32base]_[s32]index",
     "arguments": [
-      "int16x4_t a"
+      "svuint32_t bases",
+      "svint32_t indices"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
       }
     },
     "Architectures": [
@@ -10953,22 +12904,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svadrd[_u32base]_[u32]index",
     "arguments": [
-      "int32x2_t a"
+      "svuint32_t bases",
+      "svuint32_t indices"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
       }
     },
     "Architectures": [
@@ -10976,22 +12931,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svadrd[_u64base]_[s64]index",
     "arguments": [
-      "int64x1_t a"
+      "svuint64_t bases",
+      "svint64_t indices"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
       }
     },
     "Architectures": [
@@ -10999,22 +12958,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgez_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svadrd[_u64base]_[u64]index",
     "arguments": [
-      "int8x8_t a"
+      "svuint64_t bases",
+      "svuint64_t indices"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
       }
     },
     "Architectures": [
@@ -11022,22 +12985,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezd_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadrh[_u32base]_[s32]index",
     "arguments": [
-      "float64_t a"
+      "svuint32_t bases",
+      "svint32_t indices"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
       }
     },
     "Architectures": [
@@ -11045,22 +13012,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svadrh[_u32base]_[u32]index",
     "arguments": [
-      "int64_t a"
+      "svuint32_t bases",
+      "svuint32_t indices"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
       }
     },
     "Architectures": [
@@ -11068,22 +13039,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadrh[_u64base]_[s64]index",
     "arguments": [
-      "float16_t a"
+      "svuint64_t bases",
+      "svint64_t indices"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
       }
     },
     "Architectures": [
@@ -11091,46 +13066,53 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svadrh[_u64base]_[u64]index",
     "arguments": [
-      "float16x8_t a"
+      "svuint64_t bases",
+      "svuint64_t indices"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svadrw[_u32base]_[s32]index",
     "arguments": [
-      "float32x4_t a"
+      "svuint32_t bases",
+      "svint32_t indices"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
       }
     },
     "Architectures": [
@@ -11138,22 +13120,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svadrw[_u32base]_[u32]index",
     "arguments": [
-      "float64x2_t a"
+      "svuint32_t bases",
+      "svuint32_t indices"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
       }
     },
     "Architectures": [
@@ -11161,22 +13147,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svadrw[_u64base]_[s64]index",
     "arguments": [
-      "int16x8_t a"
+      "svuint64_t bases",
+      "svint64_t indices"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
       }
     },
     "Architectures": [
@@ -11184,22 +13174,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svadrw[_u64base]_[u64]index",
     "arguments": [
-      "int32x4_t a"
+      "svuint64_t bases",
+      "svuint64_t indices"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
       }
     },
     "Architectures": [
@@ -11207,22 +13201,26 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ADR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svaesd[_u8]",
     "arguments": [
-      "int64x2_t a"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
       }
     },
     "Architectures": [
@@ -11230,22 +13228,29 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "AESD"
+      ],
+      [
+        "AESD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svaese[_u8]",
     "arguments": [
-      "int8x16_t a"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
       }
     },
     "Architectures": [
@@ -11253,22 +13258,25 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "AESE"
+      ],
+      [
+        "AESE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgezs_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svaesimc[_u8]",
     "arguments": [
-      "float32_t a"
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op": {
+        "register": "Ztied.B"
       }
     },
     "Architectures": [
@@ -11276,83 +13284,84 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "AESIMC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svaesmc[_u8]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+      "op": {
+        "register": "Ztied.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AESMC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_b]_z",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Pop1.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s16]_m",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Ztied1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -11360,84 +13369,113 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "UXTB"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s16]_x",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s16]_z",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s32]_m",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Ztied1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -11445,113 +13483,160 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "UXTB"
+      ],
+      [
+        "UXTH"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s32]_x",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s32]_z",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "MOVPRFX",
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTH"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s64]_m",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "UXTB"
+      ],
+      [
+        "UXTH"
+      ],
+      [
+        "UXTW"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s64]_x",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -11559,55 +13644,87 @@
     ],
     "instructions": [
       [
-        "CMHI"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgt_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s64]_z",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "MOVPRFX",
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTH"
+      ],
+      [
+        "MOVPRFX",
+        "UXTW"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtd_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s8]_m",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -11615,26 +13732,34 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s8]_x",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -11642,26 +13767,39 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtd_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_s8]_z",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -11669,26 +13807,35 @@
     ],
     "instructions": [
       [
-        "CMHI"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgth_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u16]_m",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Ztied1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -11696,83 +13843,113 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "UXTB"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u16]_x",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u16]_z",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "MOVPRFX",
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u32]_m",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Ztied1.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -11780,84 +13957,120 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "UXTB"
+      ],
+      [
+        "UXTH"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u32]_x",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u32]_z",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTH"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u64]_m",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -11865,113 +14078,162 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "UXTB"
+      ],
+      [
+        "UXTH"
+      ],
+      [
+        "UXTW"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u64]_x",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u64]_z",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "MOVPRFX",
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTH"
+      ],
+      [
+        "MOVPRFX",
+        "UXTW"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u8]_m",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u8]_x",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -11979,55 +14241,75 @@
     ],
     "instructions": [
       [
-        "CMHI"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_n_u8]_z",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgts_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s16]_m",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12035,46 +14317,71 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s16]_x",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s16]_z",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12082,22 +14389,35 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s32]_m",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12105,22 +14425,34 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s32]_x",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12128,22 +14460,36 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s32]_z",
     "arguments": [
-      "int32x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12151,22 +14497,35 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s64]_m",
     "arguments": [
-      "int64x1_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -12174,22 +14533,34 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtz_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s64]_x",
     "arguments": [
-      "int8x8_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -12197,22 +14568,36 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzd_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s64]_z",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -12220,22 +14605,35 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s8]_m",
     "arguments": [
-      "int64_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -12243,22 +14641,34 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s8]_x",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -12266,46 +14676,72 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_s8]_z",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u16]_m",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12313,22 +14749,34 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u16]_x",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12336,22 +14784,36 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u16]_z",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12359,22 +14821,35 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u32]_m",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12382,22 +14857,34 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u32]_x",
     "arguments": [
-      "int64x2_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12405,22 +14892,36 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u32]_z",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12428,22 +14929,35 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcgtzs_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u64]_m",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -12451,83 +14965,107 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u64]_x",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u64]_z",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
-      ]
-    ]
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
+      ]
+    ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u8]_m",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -12535,84 +15073,103 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u8]_x",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "AND"
+      ],
+      [
+        "AND"
+      ],
+      [
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svand[_u8]_z",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "MOVPRFX",
+        "AND"
+      ],
+      [
+        "MOVPRFX",
+        "AND"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_s16]",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {
-        "register": "Dm"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12620,113 +15177,107 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_s32]",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_s64]",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {
-        "register": "Vm.4H"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_s8]",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op": {
+        "register": "Zop.B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_u16]",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {
-        "register": "Dm"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12734,55 +15285,53 @@
     ],
     "instructions": [
       [
-        "CMHS"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcle_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_u32]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcled_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_u64]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
       "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {
-        "register": "Dm"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -12790,26 +15339,26 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcled_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svandv[_u8]",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.B"
       },
-      "b": {
-        "register": "Dm"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -12817,26 +15366,30 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ANDV"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcled_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s16]_m",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Ztied1.H"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12844,26 +15397,33 @@
     ],
     "instructions": [
       [
-        "CMHS"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s16]_x",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -12871,83 +15431,114 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s16]_z",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s32]_m",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s32]_x",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -12955,84 +15546,114 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s32]_z",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s64]_m",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s64]_x",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -13040,113 +15661,155 @@
     ],
     "instructions": [
       [
-        "CMGE"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s64]_z",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s8]_m",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Ztied1.B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s8]_x",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_n_s8]_z",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -13154,55 +15817,74 @@
     ],
     "instructions": [
       [
-        "CMHS"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcleq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s16]_m",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHS"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcles_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s16]_x",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -13210,46 +15892,73 @@
     ],
     "instructions": [
       [
-        "FCMGE"
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s16]_z",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s32]_m",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -13257,22 +15966,34 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s32]_x",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -13280,22 +16001,37 @@
     ],
     "instructions": [
       [
-        "FCMLE"
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s32]_z",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -13303,22 +16039,35 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s64]_m",
     "arguments": [
-      "int32x2_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -13326,22 +16075,34 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s64]_x",
     "arguments": [
-      "int64x1_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -13349,22 +16110,37 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclez_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s64]_z",
     "arguments": [
-      "int8x8_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -13372,22 +16148,35 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezd_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s8]_m",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -13395,22 +16184,34 @@
     ],
     "instructions": [
       [
-        "FCMLE"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezd_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s8]_x",
     "arguments": [
-      "int64_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -13418,22 +16219,37 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "ASRR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr[_s8]_z",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -13441,46 +16257,69 @@
     ],
     "instructions": [
       [
-        "FCMLE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASRR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s16]_m",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLE"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s16]_x",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -13488,22 +16327,36 @@
     ],
     "instructions": [
       [
-        "FCMLE"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s16]_z",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -13511,22 +16364,35 @@
     ],
     "instructions": [
       [
-        "FCMLE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s32]_m",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -13534,22 +16400,33 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s32]_x",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -13557,22 +16434,36 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s32]_z",
     "arguments": [
-      "int64x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -13580,22 +16471,35 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s8]_m",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -13603,22 +16507,33 @@
     ],
     "instructions": [
       [
-        "CMLE"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclezs_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s8]_x",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -13626,383 +16541,517 @@
     ],
     "instructions": [
       [
-        "FCMLE"
+        "ASR"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcls_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_n_s8]_z",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcls_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s16]_m",
     "arguments": [
-      "int32x2_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcls_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s16]_x",
     "arguments": [
-      "int8x8_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcls_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s16]_z",
     "arguments": [
-      "uint16x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcls_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s32]_m",
     "arguments": [
-      "uint32x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcls_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s32]_x",
     "arguments": [
-      "uint8x8_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclsq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s32]_z",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclsq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s8]_m",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclsq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s8]_x",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASR"
+      ],
+      [
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclsq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svasr_wide[_s8]_z",
     "arguments": [
-      "uint16x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "MOVPRFX",
+        "ASR"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclsq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s16]_m",
     "arguments": [
-      "uint32x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclsq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s16]_x",
     "arguments": [
-      "uint8x16_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLS"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s16]_z",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
       },
-      "b": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s32]_m",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
       },
-      "b": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s32]_x",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
       },
-      "b": {
-        "register": "Dm"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -14010,84 +17059,104 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s32]_z",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
       },
-      "b": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s64]_m",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
       },
-      "b": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s64]_x",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
       },
-      "b": {
-        "register": "Dm"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -14095,113 +17164,140 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s64]_z",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
       },
-      "b": {
-        "register": "Vm.8B"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s8]_m",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
       },
-      "b": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s8]_x",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
       },
-      "b": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "ASRD"
+      ],
+      [
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svasrd[_n_s8]_z",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
       },
-      "b": {
-        "register": "Dm"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -14209,55 +17305,66 @@
     ],
     "instructions": [
       [
-        "CMHI"
+        "MOVPRFX",
+        "ASRD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclt_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_s16]",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_s32]",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
@@ -14265,26 +17372,34 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltd_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_s64]",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
@@ -14292,26 +17407,34 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltd_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_s8]",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -14319,26 +17442,34 @@
     ],
     "instructions": [
       [
-        "CMHI"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclth_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_u16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
@@ -14346,83 +17477,104 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_u32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_u64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_n_u8]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -14430,84 +17582,104 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_s16]",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_s32]",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_s64]",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -14515,113 +17687,139 @@
     ],
     "instructions": [
       [
-        "CMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_s8]",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMGT"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_u16]",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_u32]",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_u64]",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -14629,55 +17827,65 @@
     ],
     "instructions": [
       [
-        "CMHI"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbcax[_u8]",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMHI"
+        "BCAX"
+      ],
+      [
+        "MOVPRFX",
+        "BCAX"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclts_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_n_u16]",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Sm"
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -14685,46 +17893,53 @@
     ],
     "instructions": [
       [
-        "FCMGT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_n_u32]",
     "arguments": [
-      "float16x4_t a"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_n_u64]",
     "arguments": [
-      "float32x2_t a"
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
@@ -14732,22 +17947,26 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_n_u8]",
     "arguments": [
-      "float64x1_t a"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
@@ -14755,22 +17974,26 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_u16]",
     "arguments": [
-      "int16x4_t a"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -14778,22 +18001,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_u32]",
     "arguments": [
-      "int32x2_t a"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -14801,22 +18028,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_u64]",
     "arguments": [
-      "int64x1_t a"
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
@@ -14824,22 +18055,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltz_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbdep[_u8]",
     "arguments": [
-      "int8x8_t a"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -14847,22 +18082,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BDEP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzd_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_n_u16]",
     "arguments": [
-      "float64_t a"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -14870,22 +18109,26 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzd_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_n_u32]",
     "arguments": [
-      "int64_t a"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -14893,22 +18136,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzh_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_n_u64]",
     "arguments": [
-      "float16_t a"
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
@@ -14916,46 +18163,53 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_n_u8]",
     "arguments": [
-      "float16x8_t a"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_u16]",
     "arguments": [
-      "float32x4_t a"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -14963,22 +18217,26 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_u32]",
     "arguments": [
-      "float64x2_t a"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -14986,22 +18244,26 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_u64]",
     "arguments": [
-      "int16x8_t a"
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
@@ -15009,22 +18271,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbext[_u8]",
     "arguments": [
-      "int32x4_t a"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -15032,22 +18298,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BEXT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_n_u16]",
     "arguments": [
-      "int64x2_t a"
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
       }
     },
     "Architectures": [
@@ -15055,22 +18325,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_n_u32]",
     "arguments": [
-      "int8x16_t a"
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
       }
     },
     "Architectures": [
@@ -15078,22 +18352,26 @@
     ],
     "instructions": [
       [
-        "CMLT"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcltzs_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_n_u64]",
     "arguments": [
-      "float32_t a"
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
       }
     },
     "Architectures": [
@@ -15101,1138 +18379,1299 @@
     ],
     "instructions": [
       [
-        "FCMLT"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclz_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_n_u8]",
     "arguments": [
-      "int16x4_t a"
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclz_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_u16]",
     "arguments": [
-      "int32x2_t a"
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclz_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_u32]",
     "arguments": [
-      "int8x8_t a"
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclz_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_u64]",
     "arguments": [
-      "uint16x4_t a"
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclz_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbgrp[_u8]",
     "arguments": [
-      "uint32x2_t a"
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BGRP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclz_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_b]_z",
     "arguments": [
-      "uint8x8_t a"
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclzq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s16]_m",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclzq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s16]_x",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclzq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s16]_z",
     "arguments": [
-      "int8x16_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclzq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s32]_m",
     "arguments": [
-      "uint16x8_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclzq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s32]_x",
     "arguments": [
-      "uint32x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vclzq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s32]_z",
     "arguments": [
-      "uint8x16_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CLZ"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s64]_m",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s64]_x",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s64]_z",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.D"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s8]_m",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s8]_x",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_s8]_z",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot180_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u16]_m",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot180_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u16]_x",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot180_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u16]_z",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.H"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot180_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u32]_m",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot180_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u32]_x",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot180_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u32]_z",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot270_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u64]_m",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot270_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u64]_x",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot270_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u64]_z",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.D"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot270_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u8]_m",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot270_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u8]_x",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "AND"
+      ],
+      [
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot270_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_n_u8]_z",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot90_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s16]_m",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot90_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s16]_x",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot90_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s16]_z",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.H"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot90_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s32]_m",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot90_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s32]_x",
     "arguments": [
-      "float16x4_t r",
-      "float16x4_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmla_rot90_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s32]_z",
     "arguments": [
-      "float32x2_t r",
-      "float32x2_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s64]_m",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s64]_x",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s64]_z",
     "arguments": [
-      "float64x2_t r",
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -16240,214 +19679,233 @@
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s8]_m",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s8]_x",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_s8]_z",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u16]_m",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u16]_x",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u16]_z",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u32]_m",
     "arguments": [
-      "float64x2_t r",
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -16455,214 +19913,236 @@
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u32]_x",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u32]_z",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.S"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u64]_m",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot180_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u64]_x",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u64]_z",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.8H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u8]_m",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u8]_x",
     "arguments": [
-      "float64x2_t r",
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -16670,214 +20150,212 @@
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BIC"
+      ],
+      [
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbic[_u8]_z",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "MOVPRFX",
+        "BIC"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbrka[_b]_m",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svbool_t inactive",
+      "svbool_t pg",
+      "svbool_t op"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "inactive": {
+        "register": "Ptied.B"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op": {
+        "register": "Pop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbrka[_b]_z",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svbool_t op"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op": {
+        "register": "Pop.B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot270_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbrkb[_b]_m",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svbool_t inactive",
+      "svbool_t pg",
+      "svbool_t op"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "inactive": {
+        "register": "Ptied.B"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op": {
+        "register": "Pop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbrkb[_b]_z",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svbool_t op"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.8H"
+      "op": {
+        "register": "Pop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svbrkn[_b]_z",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Ptied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKN"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svbrkpa[_b]_z",
     "arguments": [
-      "float64x2_t r",
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "r": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -16885,368 +20363,446 @@
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKPA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svbrkpb[_b]_z",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x4_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Pop1.B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BRKPB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_lane_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_s16]",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x2_t b",
-      "const int lane"
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_laneq_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_s32]",
     "arguments": [
-      "float16x8_t r",
-      "float16x8_t a",
-      "float16x8_t b",
-      "const int lane"
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "r": {
-        "register": "Vd.8H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcmlaq_rot90_laneq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_s64]",
     "arguments": [
-      "float32x4_t r",
-      "float32x4_t a",
-      "float32x4_t b",
-      "const int lane"
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "r": {
-        "register": "Vd.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCMLA"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcnt_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_s8]",
     "arguments": [
-      "poly8x8_t a"
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CNT"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcnt_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_u16]",
     "arguments": [
-      "int8x8_t a"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CNT"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcnt_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_u32]",
     "arguments": [
-      "uint8x8_t a"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CNT"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcntq_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_u64]",
     "arguments": [
-      "poly8x16_t a"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CNT"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcntq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_n_u8]",
     "arguments": [
-      "int8x16_t a"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CNT"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcntq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_s16]",
     "arguments": [
-      "uint8x16_t a"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CNT"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_s32]",
     "arguments": [
-      "float16x4_t low",
-      "float16x4_t high"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "low": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_s64]",
     "arguments": [
-      "float32x2_t low",
-      "float32x2_t high"
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "low": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_s8]",
     "arguments": [
-      "float64x1_t low",
-      "float64x1_t high"
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.1D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "low": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -17254,366 +20810,419 @@
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_p16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_u16]",
     "arguments": [
-      "poly16x4_t low",
-      "poly16x4_t high"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "low": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_u32]",
     "arguments": [
-      "poly64x1_t low",
-      "poly64x1_t high"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.1D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "low": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_u64]",
     "arguments": [
-      "poly8x8_t low",
-      "poly8x8_t high"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "low": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl1n[_u8]",
     "arguments": [
-      "int16x4_t low",
-      "int16x4_t high"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "low": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL1N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL1N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_s16]",
     "arguments": [
-      "int32x2_t low",
-      "int32x2_t high"
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "low": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_s32]",
     "arguments": [
-      "int64x1_t low",
-      "int64x1_t high"
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.1D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "low": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_s64]",
     "arguments": [
-      "int8x8_t low",
-      "int8x8_t high"
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "low": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_s8]",
     "arguments": [
-      "uint16x4_t low",
-      "uint16x4_t high"
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.4H"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "low": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_u16]",
     "arguments": [
-      "uint32x2_t low",
-      "uint32x2_t high"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "low": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_u32]",
     "arguments": [
-      "uint64x1_t low",
-      "uint64x1_t high"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.1D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "low": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcombine_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_u64]",
     "arguments": [
-      "uint8x8_t low",
-      "uint8x8_t high"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "high": {
-        "register": "Vm.8B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "low": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP",
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_n_u8]",
     "arguments": [
-      "float32x2_t a",
-      "const int lane1",
-      "float32x2_t b",
-      "const int lane2"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -17621,36 +21230,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_s16]",
     "arguments": [
-      "float64x1_t a",
-      "const int lane1",
-      "float64x1_t b",
-      "const int lane2"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
-      },
-      "b": {
-        "register": "Vn.1D"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -17658,36 +21265,34 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_p16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_s32]",
     "arguments": [
-      "poly16x4_t a",
-      "const int lane1",
-      "poly16x4_t b",
-      "const int lane2"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -17695,74 +21300,69 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_s64]",
     "arguments": [
-      "poly64x1_t a",
-      "const int lane1",
-      "poly64x1_t b",
-      "const int lane2"
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
-      },
-      "b": {
-        "register": "Vn.1D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_s8]",
     "arguments": [
-      "poly8x8_t a",
-      "const int lane1",
-      "poly8x8_t b",
-      "const int lane2"
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -17770,36 +21370,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_u16]",
     "arguments": [
-      "int16x4_t a",
-      "const int lane1",
-      "int16x4_t b",
-      "const int lane2"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -17807,36 +21405,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_u32]",
     "arguments": [
-      "int32x2_t a",
-      "const int lane1",
-      "int32x2_t b",
-      "const int lane2"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -17844,36 +21440,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_u64]",
     "arguments": [
-      "int64x1_t a",
-      "const int lane1",
-      "int64x1_t b",
-      "const int lane2"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.1D"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -17881,36 +21475,34 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl2n[_u8]",
     "arguments": [
-      "int8x8_t a",
-      "const int lane1",
-      "int8x8_t b",
-      "const int lane2"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -17918,36 +21510,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL2N"
+      ],
+      [
+        "MOVPRFX",
+        "BSL2N"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_s16]",
     "arguments": [
-      "uint16x4_t a",
-      "const int lane1",
-      "uint16x4_t b",
-      "const int lane2"
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
@@ -17955,36 +21545,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_s32]",
     "arguments": [
-      "uint32x2_t a",
-      "const int lane1",
-      "uint32x2_t b",
-      "const int lane2"
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
@@ -17992,36 +21580,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_s64]",
     "arguments": [
-      "uint64x1_t a",
-      "const int lane1",
-      "uint64x1_t b",
-      "const int lane2"
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.1D"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
@@ -18029,36 +21615,34 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_lane_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_s8]",
     "arguments": [
-      "uint8x8_t a",
-      "const int lane1",
-      "uint8x8_t b",
-      "const int lane2"
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
@@ -18066,36 +21650,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_u16]",
     "arguments": [
-      "float32x2_t a",
-      "const int lane1",
-      "float32x4_t b",
-      "const int lane2"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.H[*]"
       }
     },
     "Architectures": [
@@ -18103,36 +21685,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_u32]",
     "arguments": [
-      "float64x1_t a",
-      "const int lane1",
-      "float64x2_t b",
-      "const int lane2"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.S[*]"
       }
     },
     "Architectures": [
@@ -18140,36 +21720,34 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_p16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_u64]",
     "arguments": [
-      "poly16x4_t a",
-      "const int lane1",
-      "poly16x8_t b",
-      "const int lane2"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.D[*]"
       }
     },
     "Architectures": [
@@ -18177,74 +21755,69 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_n_u8]",
     "arguments": [
-      "poly64x1_t a",
-      "const int lane1",
-      "poly64x2_t b",
-      "const int lane2"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.B[*]"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_s16]",
     "arguments": [
-      "poly8x8_t a",
-      "const int lane1",
-      "poly8x16_t b",
-      "const int lane2"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 15
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -18252,36 +21825,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_s32]",
     "arguments": [
-      "int16x4_t a",
-      "const int lane1",
-      "int16x8_t b",
-      "const int lane2"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -18289,36 +21860,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_s64]",
     "arguments": [
-      "int32x2_t a",
-      "const int lane1",
-      "int32x4_t b",
-      "const int lane2"
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -18326,36 +21895,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_s8]",
     "arguments": [
-      "int64x1_t a",
-      "const int lane1",
-      "int64x2_t b",
-      "const int lane2"
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -18363,36 +21930,34 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_u16]",
     "arguments": [
-      "int8x8_t a",
-      "const int lane1",
-      "int8x16_t b",
-      "const int lane2"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 15
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -18400,36 +21965,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_u32]",
     "arguments": [
-      "uint16x4_t a",
-      "const int lane1",
-      "uint16x8_t b",
-      "const int lane2"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -18437,36 +22000,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_u64]",
     "arguments": [
-      "uint32x2_t a",
-      "const int lane1",
-      "uint32x4_t b",
-      "const int lane2"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -18474,36 +22035,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svbsl[_u8]",
     "arguments": [
-      "uint64x1_t a",
-      "const int lane1",
-      "uint64x2_t b",
-      "const int lane2"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "UNUSED"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -18511,36 +22070,35 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "BSL"
+      ],
+      [
+        "MOVPRFX",
+        "BSL"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopy_laneq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f16]_m",
     "arguments": [
-      "uint8x8_t a",
-      "const int lane1",
-      "uint8x16_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 15
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -18548,36 +22106,35 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCADD"
+      ],
+      [
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f16]_x",
     "arguments": [
-      "float32x4_t a",
-      "const int lane1",
-      "float32x2_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -18585,36 +22142,35 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCADD"
+      ],
+      [
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f16]_z",
     "arguments": [
-      "float64x2_t a",
-      "const int lane1",
-      "float64x1_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.1D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -18622,36 +22178,32 @@
     ],
     "instructions": [
       [
-        "INS"
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f32]_m",
     "arguments": [
-      "poly16x8_t a",
-      "const int lane1",
-      "poly16x4_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -18659,74 +22211,71 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCADD"
+      ],
+      [
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f32]_x",
     "arguments": [
-      "poly64x2_t a",
-      "const int lane1",
-      "poly64x1_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.1D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "FCADD"
+      ],
+      [
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f32]_z",
     "arguments": [
-      "poly8x16_t a",
-      "const int lane1",
-      "poly8x8_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 15
+      "op2": {
+        "register": "Zop2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -18734,36 +22283,32 @@
     ],
     "instructions": [
       [
-        "INS"
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f64]_m",
     "arguments": [
-      "int16x8_t a",
-      "const int lane1",
-      "int16x4_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -18771,36 +22316,35 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCADD"
+      ],
+      [
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f64]_x",
     "arguments": [
-      "int32x4_t a",
-      "const int lane1",
-      "int32x2_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -18808,36 +22352,35 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCADD"
+      ],
+      [
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcadd[_f64]_z",
     "arguments": [
-      "int64x2_t a",
-      "const int lane1",
-      "int64x1_t b",
-      "const int lane2"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.1D"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -18845,36 +22388,28 @@
     ],
     "instructions": [
       [
-        "INS"
+        "MOVPRFX",
+        "FCADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_s16]",
     "arguments": [
-      "int8x16_t a",
-      "const int lane1",
-      "int8x8_t b",
-      "const int lane2"
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -18882,36 +22417,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_s32]",
     "arguments": [
-      "uint16x8_t a",
-      "const int lane1",
-      "uint16x4_t b",
-      "const int lane2"
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -18919,36 +22449,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_s64]",
     "arguments": [
-      "uint32x4_t a",
-      "const int lane1",
-      "uint32x2_t b",
-      "const int lane2"
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
@@ -18956,36 +22481,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_s8]",
     "arguments": [
-      "uint64x2_t a",
-      "const int lane1",
-      "uint64x1_t b",
-      "const int lane2"
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.1D"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 0
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -18993,36 +22513,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_lane_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_u16]",
     "arguments": [
-      "uint8x16_t a",
-      "const int lane1",
-      "uint8x8_t b",
-      "const int lane2"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.H"
       }
     },
     "Architectures": [
@@ -19030,36 +22545,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_u32]",
     "arguments": [
-      "float32x4_t a",
-      "const int lane1",
-      "float32x4_t b",
-      "const int lane2"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.S"
       }
     },
     "Architectures": [
@@ -19067,36 +22577,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_u64]",
     "arguments": [
-      "float64x2_t a",
-      "const int lane1",
-      "float64x2_t b",
-      "const int lane2"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "b": {
-        "register": "Vn.2D"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.D"
       }
     },
     "Architectures": [
@@ -19104,36 +22609,31 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_p16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcadd[_u8]",
     "arguments": [
-      "poly16x8_t a",
-      "const int lane1",
-      "poly16x8_t b",
-      "const int lane2"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.B"
       }
     },
     "Architectures": [
@@ -19141,74 +22641,71 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CADD"
+      ],
+      [
+        "MOVPRFX",
+        "CADD"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svcdot[_s32]",
     "arguments": [
-      "poly64x2_t a",
-      "const int lane1",
-      "poly64x2_t b",
-      "const int lane2"
+      "svint32_t op1",
+      "svint8_t op2",
+      "svint8_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CDOT"
+      ],
+      [
+        "MOVPRFX",
+        "CDOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_p8",
+    "SIMD_ISA": "SVE2",
+    "name": "svcdot[_s64]",
     "arguments": [
-      "poly8x16_t a",
-      "const int lane1",
-      "poly8x16_t b",
-      "const int lane2"
+      "svint64_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 15
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 15
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -19216,36 +22713,40 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CDOT"
+      ],
+      [
+        "MOVPRFX",
+        "CDOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_s16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcdot_lane[_s32]",
     "arguments": [
-      "int16x8_t a",
-      "const int lane1",
-      "int16x8_t b",
-      "const int lane2"
+      "svint32_t op1",
+      "svint8_t op2",
+      "svint8_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "op2": {
+        "register": "Zop2.B"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -19253,36 +22754,40 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CDOT"
+      ],
+      [
+        "MOVPRFX",
+        "CDOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_s32",
+    "SIMD_ISA": "SVE2",
+    "name": "svcdot_lane[_s64]",
     "arguments": [
-      "int32x4_t a",
-      "const int lane1",
-      "int32x4_t b",
-      "const int lane2"
+      "svint64_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -19290,36 +22795,34 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CDOT"
+      ],
+      [
+        "MOVPRFX",
+        "CDOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_s64",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_f16]",
     "arguments": [
-      "int64x2_t a",
-      "const int lane1",
-      "int64x2_t b",
-      "const int lane2"
+      "svfloat16_t op",
+      "svfloat16_t min",
+      "svfloat16_t max"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "max": {
+        "register": "Zreg3.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "min": {
+        "register": "Zreg2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op": {
+        "register": "Zreg1.H"
       }
     },
     "Architectures": [
@@ -19327,36 +22830,30 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_s8",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_f32]",
     "arguments": [
-      "int8x16_t a",
-      "const int lane1",
-      "int8x16_t b",
-      "const int lane2"
+      "svfloat32_t op",
+      "svfloat32_t min",
+      "svfloat32_t max"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "max": {
+        "register": "Zreg3.S"
       },
-      "b": {
-        "register": "Vn.16B"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 15
+      "min": {
+        "register": "Zreg2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 15
+      "op": {
+        "register": "Zreg1.S"
       }
     },
     "Architectures": [
@@ -19364,36 +22861,30 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_u16",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_f64]",
     "arguments": [
-      "uint16x8_t a",
-      "const int lane1",
-      "uint16x8_t b",
-      "const int lane2"
+      "svfloat64_t op",
+      "svfloat64_t min",
+      "svfloat64_t max"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
+      "max": {
+        "register": "Zreg3.D"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 7
+      "min": {
+        "register": "Zreg2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 7
+      "op": {
+        "register": "Zreg1.D"
       }
     },
     "Architectures": [
@@ -19401,36 +22892,30 @@
     ],
     "instructions": [
       [
-        "INS"
+        "FCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_u32",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_s16]",
     "arguments": [
-      "uint32x4_t a",
-      "const int lane1",
-      "uint32x4_t b",
-      "const int lane2"
+      "svint16_t op",
+      "svint16_t min",
+      "svint16_t max"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
+      "max": {
+        "register": "Zreg3.H"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 3
+      "min": {
+        "register": "Zreg2.H"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 3
+      "op": {
+        "register": "Zreg1.H"
       }
     },
     "Architectures": [
@@ -19438,36 +22923,30 @@
     ],
     "instructions": [
       [
-        "INS"
+        "SCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_u64",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_s32]",
     "arguments": [
-      "uint64x2_t a",
-      "const int lane1",
-      "uint64x2_t b",
-      "const int lane2"
+      "svint32_t op",
+      "svint32_t min",
+      "svint32_t max"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.2D"
+      "max": {
+        "register": "Zreg3.S"
       },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 1
+      "min": {
+        "register": "Zreg2.S"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 1
+      "op": {
+        "register": "Zreg1.S"
       }
     },
     "Architectures": [
@@ -19475,36 +22954,30 @@
     ],
     "instructions": [
       [
-        "INS"
+        "SCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcopyq_laneq_u8",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_s64]",
     "arguments": [
-      "uint8x16_t a",
-      "const int lane1",
-      "uint8x16_t b",
-      "const int lane2"
+      "svint64_t op",
+      "svint64_t min",
+      "svint64_t max"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
+      "max": {
+        "register": "Zreg3.D"
       },
-      "b": {
-        "register": "Vn.16B"
-      },
-      "lane1": {
-        "minimum": 0,
-        "maximum": 15
+      "min": {
+        "register": "Zreg2.D"
       },
-      "lane2": {
-        "minimum": 0,
-        "maximum": 15
+      "op": {
+        "register": "Zreg1.D"
       }
     },
     "Architectures": [
@@ -19512,72 +22985,92 @@
     ],
     "instructions": [
       [
-        "INS"
+        "SCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_s8]",
     "arguments": [
-      "uint64_t a"
+      "svint8_t op",
+      "svint8_t min",
+      "svint8_t max"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "max": {
+        "register": "Zreg3.B"
+      },
+      "min": {
+        "register": "Zreg2.B"
+      },
+      "op": {
+        "register": "Zreg1.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "SCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_u16]",
     "arguments": [
-      "uint64_t a"
+      "svuint16_t op",
+      "svuint16_t min",
+      "svuint16_t max"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "max": {
+        "register": "Zreg3.H"
+      },
+      "min": {
+        "register": "Zreg2.H"
+      },
+      "op": {
+        "register": "Zreg1.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "UCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_u32]",
     "arguments": [
-      "uint64_t a"
+      "svuint32_t op",
+      "svuint32_t min",
+      "svuint32_t max"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "max": {
+        "register": "Zreg3.S"
+      },
+      "min": {
+        "register": "Zreg2.S"
+      },
+      "op": {
+        "register": "Zreg1.S"
       }
     },
     "Architectures": [
@@ -19585,394 +23078,537 @@
     ],
     "instructions": [
       [
-        "INS"
+        "UCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_p16",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_u64]",
     "arguments": [
-      "uint64_t a"
+      "svuint64_t op",
+      "svuint64_t min",
+      "svuint64_t max"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "max": {
+        "register": "Zreg3.D"
+      },
+      "min": {
+        "register": "Zreg2.D"
+      },
+      "op": {
+        "register": "Zreg1.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "UCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_p64",
+    "SIMD_ISA": "SVE2",
+    "name": "svclamp[_u8]",
     "arguments": [
-      "uint64_t a"
+      "svuint8_t op",
+      "svuint8_t min",
+      "svuint8_t max"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "max": {
+        "register": "Zreg3.B"
+      },
+      "min": {
+        "register": "Zreg2.B"
+      },
+      "op": {
+        "register": "Zreg1.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "UCLAMP"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_f16]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "svfloat16_t fallback",
+      "svfloat16_t data"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Zfallback.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_f32]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "svfloat32_t fallback",
+      "svfloat32_t data"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Zfallback.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_f64]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "svfloat64_t fallback",
+      "svfloat64_t data"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Zfallback.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_f16]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "float16_t fallback",
+      "svfloat16_t data"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Htied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_f32]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "float32_t fallback",
+      "svfloat32_t data"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Stied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_f64]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "float64_t fallback",
+      "svfloat64_t data"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Dtied|Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_s16]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "int16_t fallback",
+      "svint16_t data"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Htied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_s32]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "int32_t fallback",
+      "svint32_t data"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Stied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcreate_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_s64]",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "int64_t fallback",
+      "svint64_t data"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Xn"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Dtied|Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f16_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_s8]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "int8_t fallback",
+      "svint8_t data"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Btied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTN"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f16_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_u16]",
     "arguments": [
-      "int16x4_t a"
+      "svbool_t pg",
+      "uint16_t fallback",
+      "svuint16_t data"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Htied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f16_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_u32]",
     "arguments": [
-      "uint16x4_t a"
+      "svbool_t pg",
+      "uint32_t fallback",
+      "svuint32_t data"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Stied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_u64]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "uint64_t fallback",
+      "svuint64_t data"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Dtied|Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTL"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f32_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_n_u8]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "uint8_t fallback",
+      "svuint8_t data"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Btied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -19980,72 +23616,103 @@
     ],
     "instructions": [
       [
-        "FCVTN"
+        "CLASTA"
+      ],
+      [
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f32_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_s16]",
     "arguments": [
-      "int32x2_t a"
+      "svbool_t pg",
+      "svint16_t fallback",
+      "svint16_t data"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Zfallback.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f32_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_s32]",
     "arguments": [
-      "uint32x2_t a"
+      "svbool_t pg",
+      "svint32_t fallback",
+      "svint32_t data"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Zfallback.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f64_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_s64]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint64_t fallback",
+      "svint64_t data"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Zfallback.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -20053,22 +23720,34 @@
     ],
     "instructions": [
       [
-        "FCVTL"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f64_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_s8]",
     "arguments": [
-      "int64x1_t a"
+      "svbool_t pg",
+      "svint8_t fallback",
+      "svint8_t data"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Zfallback.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -20076,22 +23755,34 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_f64_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_u16]",
     "arguments": [
-      "uint64x1_t a"
+      "svbool_t pg",
+      "svuint16_t fallback",
+      "svuint16_t data"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Zfallback.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -20099,26 +23790,34 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_high_f16_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_u32]",
     "arguments": [
-      "float16x4_t r",
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint32_t fallback",
+      "svuint32_t data"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "data": {
+        "register": "Zdata.S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "fallback": {
+        "register": "Zfallback.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -20126,22 +23825,34 @@
     ],
     "instructions": [
       [
-        "FCVTN2"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_high_f32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_u64]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svuint64_t fallback",
+      "svuint64_t data"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Zfallback.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -20149,26 +23860,34 @@
     ],
     "instructions": [
       [
-        "FCVTL2"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_high_f32_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclasta[_u8]",
     "arguments": [
-      "float32x2_t r",
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint8_t fallback",
+      "svuint8_t data"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "data": {
+        "register": "Zdata.B"
       },
-      "r": {
-        "register": "Vd.2S"
+      "fallback": {
+        "register": "Zfallback.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -20176,22 +23895,34 @@
     ],
     "instructions": [
       [
-        "FCVTN2"
+        "CLASTA"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_high_f64_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_f16]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svfloat16_t fallback",
+      "svfloat16_t data"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Zfallback.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -20199,145 +23930,172 @@
     ],
     "instructions": [
       [
-        "FCVTL2"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_f16_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_f32]",
     "arguments": [
-      "int16x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat32_t fallback",
+      "svfloat32_t data"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "fallback": {
+        "register": "Zfallback.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_f16_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_f64]",
     "arguments": [
-      "uint16x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat64_t fallback",
+      "svfloat64_t data"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "fallback": {
+        "register": "Zfallback.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_f32_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_f16]",
     "arguments": [
-      "int32x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "float16_t fallback",
+      "svfloat16_t data"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "fallback": {
+        "register": "Htied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_f32_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_f32]",
     "arguments": [
-      "uint32x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "float32_t fallback",
+      "svfloat32_t data"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "fallback": {
+        "register": "Stied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_f64_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_f64]",
     "arguments": [
-      "int64x1_t a",
-      "const int n"
+      "svbool_t pg",
+      "float64_t fallback",
+      "svfloat64_t data"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "fallback": {
+        "register": "Dtied|Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -20345,27 +24103,33 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_f64_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_s16]",
     "arguments": [
-      "uint64x1_t a",
-      "const int n"
+      "svbool_t pg",
+      "int16_t fallback",
+      "svint16_t data"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "fallback": {
+        "register": "Htied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -20373,86 +24137,101 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_s32]",
     "arguments": [
-      "float16x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "int32_t fallback",
+      "svint32_t data"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "fallback": {
+        "register": "Stied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_s64]",
     "arguments": [
-      "float32x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "int64_t fallback",
+      "svint64_t data"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "fallback": {
+        "register": "Dtied|Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_s8]",
     "arguments": [
-      "float64x1_t a",
-      "const int n"
+      "svbool_t pg",
+      "int8_t fallback",
+      "svint8_t data"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "fallback": {
+        "register": "Btied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -20460,86 +24239,101 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_u16]",
     "arguments": [
-      "float16x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "uint16_t fallback",
+      "svuint16_t data"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "fallback": {
+        "register": "Htied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_u32]",
     "arguments": [
-      "float32x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "uint32_t fallback",
+      "svuint32_t data"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "fallback": {
+        "register": "Stied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_n_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_u64]",
     "arguments": [
-      "float64x1_t a",
-      "const int n"
+      "svbool_t pg",
+      "uint64_t fallback",
+      "svuint64_t data"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "fallback": {
+        "register": "Dtied|Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -20547,71 +24341,102 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_n_u8]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "uint8_t fallback",
+      "svuint8_t data"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Btied|Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_s16]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint16_t fallback",
+      "svint16_t data"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Zfallback.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_s32]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svint32_t fallback",
+      "svint32_t data"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Zfallback.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -20619,71 +24444,104 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_s64]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint64_t fallback",
+      "svint64_t data"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Zfallback.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_s8]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint8_t fallback",
+      "svint8_t data"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Zfallback.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvt_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_u16]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svuint16_t fallback",
+      "svuint16_t data"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Zfallback.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -20691,70 +24549,104 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvta_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_u32]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svuint32_t fallback",
+      "svuint32_t data"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Zfallback.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvta_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_u64]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svuint64_t fallback",
+      "svuint64_t data"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Zfallback.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvta_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclastb[_u8]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svuint8_t fallback",
+      "svuint8_t data"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Zfallback.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -20762,70 +24654,96 @@
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLASTB"
+      ],
+      [
+        "MOVPRFX",
+        "CLASTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvta_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s16]_m",
     "arguments": [
-      "float16x4_t a"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvta_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s16]_x",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvta_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s16]_z",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -20833,22 +24751,31 @@
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtad_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s32]_m",
     "arguments": [
-      "float64_t a"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -20856,22 +24783,30 @@
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtad_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s32]_x",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -20879,22 +24814,30 @@
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtah_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s32]_z",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -20902,46 +24845,62 @@
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtah_s32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s64]_m",
     "arguments": [
-      "float16_t a"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtah_s64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s64]_x",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -20949,22 +24908,30 @@
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtah_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s64]_z",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -20972,46 +24939,62 @@
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtah_u32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s8]_m",
     "arguments": [
-      "float16_t a"
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtah_u64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s8]_x",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -21019,70 +25002,93 @@
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLS"
+      ],
+      [
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtaq_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcls[_s8]_z",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "MOVPRFX",
+        "CLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtaq_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s16]_m",
     "arguments": [
-      "float32x4_t a"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtaq_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s16]_x",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -21090,70 +25096,93 @@
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtaq_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s16]_z",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtaq_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s32]_m",
     "arguments": [
-      "float32x4_t a"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtaq_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s32]_x",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -21161,22 +25190,30 @@
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtas_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s32]_z",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -21184,22 +25221,31 @@
     ],
     "instructions": [
       [
-        "FCVTAS"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtas_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s64]_m",
     "arguments": [
-      "float32_t a"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21207,22 +25253,30 @@
     ],
     "instructions": [
       [
-        "FCVTAU"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_f64_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s64]_x",
     "arguments": [
-      "int64_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21230,22 +25284,30 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_f64_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s64]_z",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21253,27 +25315,31 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_n_f64_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s8]_m",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -21281,27 +25347,30 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_n_f64_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s8]_x",
     "arguments": [
-      "uint64_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.B|Ztied.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -21309,27 +25378,30 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_n_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_s8]_z",
     "arguments": [
-      "float64_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -21337,27 +25409,31 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_n_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u16]_m",
     "arguments": [
-      "float64_t a",
-      "const int n"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -21365,22 +25441,30 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u16]_x",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -21388,22 +25472,30 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtd_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u16]_z",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -21411,22 +25503,31 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_f16_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u32]_m",
     "arguments": [
-      "int16_t a"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -21434,46 +25535,61 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_f16_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u32]_x",
     "arguments": [
-      "int32_t a"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_f16_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u32]_z",
     "arguments": [
-      "int64_t a"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -21481,22 +25597,31 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_f16_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u64]_m",
     "arguments": [
-      "uint16_t a"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21504,46 +25629,61 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_f16_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u64]_x",
     "arguments": [
-      "uint32_t a"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_f16_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u64]_z",
     "arguments": [
-      "uint64_t a"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21551,27 +25691,31 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_f16_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u8]_m",
     "arguments": [
-      "int16_t a",
-      "const int n"
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -21579,56 +25723,61 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_f16_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u8]_x",
     "arguments": [
-      "int32_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.B|Ztied.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CLZ"
+      ],
+      [
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_f16_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svclz[_u8]_z",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op": {
+        "register": "Zop.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -21636,27 +25785,36 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "MOVPRFX",
+        "CLZ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_f16_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f16]_m",
     "arguments": [
-      "uint16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -21664,56 +25822,79 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_f16_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f16]_x",
     "arguments": [
-      "uint32_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_f16_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f16]_z",
     "arguments": [
-      "uint64_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -21721,27 +25902,36 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f32]_m",
     "arguments": [
-      "float16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -21749,56 +25939,79 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_s32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f32]_x",
     "arguments": [
-      "float16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_s64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f32]_z",
     "arguments": [
-      "float16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -21806,27 +26019,36 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f64]_m",
     "arguments": [
-      "float16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21834,56 +26056,79 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_u32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f64]_x",
     "arguments": [
-      "float16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_n_u64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla[_f64]_z",
     "arguments": [
-      "float16_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svfloat64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -21891,22 +26136,32 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_s16_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_s16]",
     "arguments": [
-      "float16_t a"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -21914,46 +26169,71 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_s32_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_s32]",
     "arguments": [
-      "float16_t a"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_s64_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_s64]",
     "arguments": [
-      "float16_t a"
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
@@ -21961,22 +26241,35 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_u16_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_s8]",
     "arguments": [
-      "float16_t a"
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
@@ -21984,46 +26277,71 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_u32_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_u16]",
     "arguments": [
-      "float16_t a"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvth_u64_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_u32]",
     "arguments": [
-      "float16_t a"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -22031,70 +26349,112 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtm_s16_f16",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_u64]",
     "arguments": [
-      "float16x4_t a"
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtm_s32_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla[_u8]",
     "arguments": [
-      "float32x2_t a"
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtm_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla_lane[_f16]",
     "arguments": [
-      "float64x1_t a"
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svfloat16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -22102,70 +26462,122 @@
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtm_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmla_lane[_f32]",
     "arguments": [
-      "float16x4_t a"
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svfloat32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "FCMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FCMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtm_u32_f32",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla_lane[_s16]",
     "arguments": [
-      "float32x2_t a"
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtm_u64_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla_lane[_s32]",
     "arguments": [
-      "float64x1_t a"
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -22173,22 +26585,40 @@
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmd_s64_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla_lane[_u16]",
     "arguments": [
-      "float64_t a"
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
       }
     },
     "Architectures": [
@@ -22196,22 +26626,40 @@
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmd_u64_f64",
+    "SIMD_ISA": "SVE2",
+    "name": "svcmla_lane[_u32]",
     "arguments": [
-      "float64_t a"
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
       }
     },
     "Architectures": [
@@ -22219,22 +26667,34 @@
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMLA"
+      ],
+      [
+        "MOVPRFX",
+        "CMLA"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmh_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_f16]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -22242,46 +26702,61 @@
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "FCMEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmh_s32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_f32]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "FCMEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmh_s64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_f64]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22289,22 +26764,30 @@
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "FCMEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmh_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_f16]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -22312,46 +26795,67 @@
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "FCMEQ"
+      ],
+      [
+        "FCMEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmh_u32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_f32]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "FCMEQ"
+      ],
+      [
+        "FCMEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmh_u64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_f64]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22359,70 +26863,101 @@
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "FCMEQ"
+      ],
+      [
+        "FCMEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmq_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_s16]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmq_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_s32]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmq_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_s64]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22430,70 +26965,101 @@
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmq_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_s8]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmq_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_u16]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtmq_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_u32]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -22501,22 +27067,33 @@
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtms_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_u64]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22524,22 +27101,33 @@
     ],
     "instructions": [
       [
-        "FCVTMS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtms_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_n_u8]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -22547,70 +27135,95 @@
     ],
     "instructions": [
       [
-        "FCVTMU"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtn_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_s16]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtn_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_s32]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtn_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_s64]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22618,70 +27231,92 @@
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtn_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_s8]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtn_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_u16]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtn_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_u32]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -22689,22 +27324,30 @@
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnd_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_u64]",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22712,22 +27355,30 @@
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnd_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq[_u8]",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -22735,22 +27386,30 @@
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnh_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq_wide[_n_s16]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -22758,46 +27417,67 @@
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnh_s32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq_wide[_n_s32]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnh_s64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq_wide[_n_s8]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -22805,22 +27485,33 @@
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPEQ"
+      ],
+      [
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnh_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq_wide[_s16]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -22828,46 +27519,61 @@
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnh_u32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq_wide[_s32]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnh_u64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpeq_wide[_s8]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -22875,70 +27581,92 @@
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPEQ"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnq_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_f16]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnq_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_f32]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnq_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_f64]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -22946,70 +27674,98 @@
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnq_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_f16]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "FCMGE"
+      ],
+      [
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnq_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_f32]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "FCMGE"
+      ],
+      [
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtnq_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_f64]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -23017,22 +27773,33 @@
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "FCMGE"
+      ],
+      [
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtns_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_s16]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23040,22 +27807,33 @@
     ],
     "instructions": [
       [
-        "FCVTNS"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtns_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_s32]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -23063,70 +27841,101 @@
     ],
     "instructions": [
       [
-        "FCVTNU"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtp_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_s64]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtp_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_s8]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtp_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_u16]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23134,70 +27943,101 @@
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtp_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_u32]",
     "arguments": [
-      "float16x4_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtp_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_u64]",
     "arguments": [
-      "float32x2_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtp_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_n_u8]",
     "arguments": [
-      "float64x1_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -23205,22 +28045,33 @@
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpd_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_s16]",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23228,22 +28079,30 @@
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpd_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_s32]",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -23251,22 +28110,30 @@
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtph_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_s64]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -23274,46 +28141,61 @@
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtph_s32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_s8]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtph_s64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_u16]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23321,22 +28203,30 @@
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtph_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_u32]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -23344,46 +28234,61 @@
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtph_u32_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_u64]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtph_u64_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge[_u8]",
     "arguments": [
-      "float16_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -23391,70 +28296,98 @@
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpq_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_n_s16]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpq_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_n_s32]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpq_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_n_s8]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -23462,70 +28395,101 @@
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpq_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_n_u16]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpq_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_n_u32]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtpq_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_n_u8]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -23533,22 +28497,33 @@
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPHS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtps_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_s16]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23556,22 +28531,30 @@
     ],
     "instructions": [
       [
-        "FCVTPS"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtps_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_s32]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -23579,120 +28562,154 @@
     ],
     "instructions": [
       [
-        "FCVTPU"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_f16_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_s8]",
     "arguments": [
-      "int16x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_f16_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_u16]",
     "arguments": [
-      "uint16x8_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_f32_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_u32]",
     "arguments": [
-      "int32x4_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_f32_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpge_wide[_u8]",
     "arguments": [
-      "uint32x4_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_f64_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_f16]",
     "arguments": [
-      "int64x2_t a"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23700,22 +28717,30 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_f64_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_f32]",
     "arguments": [
-      "uint64x2_t a"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -23723,145 +28748,163 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_f16_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_f64]",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_f16_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_f16]",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "FCMGT"
+      ],
+      [
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_f32_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_f32]",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SCVTF"
+        "FCMGT"
+      ],
+      [
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_f32_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_f64]",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UCVTF"
+        "FCMGT"
+      ],
+      [
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_f64_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_s16]",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23869,27 +28912,33 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_f64_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_s32]",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -23897,86 +28946,101 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_s64]",
     "arguments": [
-      "float16x8_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_s8]",
     "arguments": [
-      "float32x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_u16]",
     "arguments": [
-      "float64x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -23984,86 +29048,101 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_u32]",
     "arguments": [
-      "float16x8_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_u64]",
     "arguments": [
-      "float32x4_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_n_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_n_u8]",
     "arguments": [
-      "float64x2_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -24071,71 +29150,95 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_s16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_s16]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_s32]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_s64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_s64]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -24143,71 +29246,92 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_u16_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_s8]",
     "arguments": [
-      "float16x8_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_u16]",
     "arguments": [
-      "float32x4_t a"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtq_u64_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_u32]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24215,22 +29339,30 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_f32_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_u64]",
     "arguments": [
-      "int32_t a"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -24238,22 +29370,30 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_f32_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt[_u8]",
     "arguments": [
-      "uint32_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -24261,27 +29401,30 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_n_f32_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_n_s16]",
     "arguments": [
-      "int32_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -24289,27 +29432,33 @@
     ],
     "instructions": [
       [
-        "SCVTF"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_n_f32_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_n_s32]",
     "arguments": [
-      "uint32_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24317,27 +29466,33 @@
     ],
     "instructions": [
       [
-        "UCVTF"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_n_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_n_s8]",
     "arguments": [
-      "float32_t a",
-      "const int n"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -24345,27 +29500,33 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPGT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_n_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_n_u16]",
     "arguments": [
-      "float32_t a",
-      "const int n"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -24373,22 +29534,33 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_s32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_n_u32]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24396,22 +29568,33 @@
     ],
     "instructions": [
       [
-        "FCVTZS"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvts_u32_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_n_u8]",
     "arguments": [
-      "float32_t a"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -24419,22 +29602,33 @@
     ],
     "instructions": [
       [
-        "FCVTZU"
+        "CMPHI"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtx_f32_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_s16]",
     "arguments": [
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -24442,26 +29636,30 @@
     ],
     "instructions": [
       [
-        "FCVTXN"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtx_high_f32_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_s32]",
     "arguments": [
-      "float32x2_t r",
-      "float64x2_t a"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24469,22 +29667,30 @@
     ],
     "instructions": [
       [
-        "FCVTXN2"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vcvtxd_f32_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_s8]",
     "arguments": [
-      "float64_t a"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -24492,26 +29698,30 @@
     ],
     "instructions": [
       [
-        "FCVTXN"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdiv_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_u16]",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -24519,26 +29729,30 @@
     ],
     "instructions": [
       [
-        "FDIV"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdiv_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_u32]",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24546,26 +29760,30 @@
     ],
     "instructions": [
       [
-        "FDIV"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdiv_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpgt_wide[_u8]",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Dm"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -24573,54 +29791,61 @@
     ],
     "instructions": [
       [
-        "FDIV"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdivh_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_f16]",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Hm"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FDIV"
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdivq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_f32]",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24628,26 +29853,30 @@
     ],
     "instructions": [
       [
-        "FDIV"
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdivq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_f64]",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -24655,26 +29884,30 @@
     ],
     "instructions": [
       [
-        "FDIV"
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdivq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_f16]",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -24682,109 +29915,101 @@
     ],
     "instructions": [
       [
-        "FDIV"
+        "FCMLE"
+      ],
+      [
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdot_lane_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_f32]",
     "arguments": [
-      "int32x2_t r",
-      "int8x8_t a",
-      "int8x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SDOT"
+        "FCMLE"
+      ],
+      [
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdot_lane_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_f64]",
     "arguments": [
-      "uint32x2_t r",
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.4B"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UDOT"
+        "FCMLE"
+      ],
+      [
+        "FCMGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdot_laneq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_s16]",
     "arguments": [
-      "int32x2_t r",
-      "int8x8_t a",
-      "int8x16_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.H[*]"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -24792,35 +30017,33 @@
     ],
     "instructions": [
       [
-        "SDOT"
+        "CMPLE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdot_laneq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_s32]",
     "arguments": [
-      "uint32x2_t r",
-      "uint8x8_t a",
-      "uint8x16_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -24828,173 +30051,169 @@
     ],
     "instructions": [
       [
-        "UDOT"
+        "CMPLE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdot_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_s64]",
     "arguments": [
-      "int32x2_t r",
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SDOT"
+        "CMPLE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdot_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_s8]",
     "arguments": [
-      "uint32x2_t r",
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op2": {
+        "register": "Zop2.B[*]"
       },
-      "r": {
-        "register": "Vd.2S"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UDOT"
+        "CMPLE"
+      ],
+      [
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdotq_lane_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_u16]",
     "arguments": [
-      "int32x4_t r",
-      "int8x16_t a",
-      "int8x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.H[*]"
       },
-      "r": {
-        "register": "Vd.4S"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SDOT"
+        "CMPLS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdotq_lane_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_u32]",
     "arguments": [
-      "uint32x4_t r",
-      "uint8x16_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op2": {
+        "register": "Zop2.S[*]"
       },
-      "r": {
-        "register": "Vd.4S"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UDOT"
+        "CMPLS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdotq_laneq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_u64]",
     "arguments": [
-      "int32x4_t r",
-      "int8x16_t a",
-      "int8x16_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.D"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.D[*]"
       },
-      "r": {
-        "register": "Vd.4S"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -25002,35 +30221,33 @@
     ],
     "instructions": [
       [
-        "SDOT"
+        "CMPLS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdotq_laneq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_n_u8]",
     "arguments": [
-      "uint32x4_t r",
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.4B"
+      "op1": {
+        "register": "Zop1.B"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op2": {
+        "register": "Zop2.B[*]"
       },
-      "r": {
-        "register": "Vd.4S"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -25038,151 +30255,157 @@
     ],
     "instructions": [
       [
-        "UDOT"
+        "CMPLS"
+      ],
+      [
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdotq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_s16]",
     "arguments": [
-      "int32x4_t r",
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.H"
       },
-      "r": {
-        "register": "Vd.4S"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SDOT"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdotq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_s32]",
     "arguments": [
-      "uint32x4_t r",
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op1": {
+        "register": "Zop1.S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op2": {
+        "register": "Zop2.S"
       },
-      "r": {
-        "register": "Vd.4S"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UDOT"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_s64]",
     "arguments": [
-      "float16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_s8]",
     "arguments": [
-      "float32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPGE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_u16]",
     "arguments": [
-      "float64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -25190,356 +30413,389 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_u32]",
     "arguments": [
-      "poly16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_u64]",
     "arguments": [
-      "poly64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple[_u8]",
     "arguments": [
-      "poly8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_n_s16]",
     "arguments": [
-      "int16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLE"
+      ],
+      [
+        "CMPLE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_n_s32]",
     "arguments": [
-      "int32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLE"
+      ],
+      [
+        "CMPLE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_n_s8]",
     "arguments": [
-      "int64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLE"
+      ],
+      [
+        "CMPLE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_n_u16]",
     "arguments": [
-      "int8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLS"
+      ],
+      [
+        "CMPLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_n_u32]",
     "arguments": [
-      "uint16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLS"
+      ],
+      [
+        "CMPLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_n_u8]",
     "arguments": [
-      "uint32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLS"
+      ],
+      [
+        "CMPLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_s16]",
     "arguments": [
-      "uint64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_lane_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_s32]",
     "arguments": [
-      "uint8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_s8]",
     "arguments": [
-      "float16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -25547,27 +30803,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_u16]",
     "arguments": [
-      "float32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -25575,27 +30834,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_u32]",
     "arguments": [
-      "float64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -25603,27 +30865,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmple_wide[_u8]",
     "arguments": [
-      "poly16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -25631,27 +30896,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_f16]",
     "arguments": [
-      "poly64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -25659,27 +30927,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_f32]",
     "arguments": [
-      "poly8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -25687,27 +30958,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_f64]",
     "arguments": [
-      "int16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -25715,27 +30989,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_f16]",
     "arguments": [
-      "int32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -25743,27 +31020,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMLT"
+      ],
+      [
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_f32]",
     "arguments": [
-      "int64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -25771,27 +31054,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMLT"
+      ],
+      [
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_f64]",
     "arguments": [
-      "int8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -25799,27 +31088,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMLT"
+      ],
+      [
+        "FCMGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_s16]",
     "arguments": [
-      "uint16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -25827,27 +31122,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_s32]",
     "arguments": [
-      "uint32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -25855,27 +31156,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_s64]",
     "arguments": [
-      "uint64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -25883,27 +31190,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_laneq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_s8]",
     "arguments": [
-      "uint8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -25911,72 +31224,101 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
+      ],
+      [
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_u16]",
     "arguments": [
-      "float16_t value"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_u32]",
     "arguments": [
-      "float32_t value"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_u64]",
     "arguments": [
-      "float64_t value"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -25984,301 +31326,383 @@
     ],
     "instructions": [
       [
-        "INS"
+        "CMPLO"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_n_u8]",
     "arguments": [
-      "poly16_t value"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
+      ],
+      [
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_s16]",
     "arguments": [
-      "poly64_t value"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_s32]",
     "arguments": [
-      "poly8_t value"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_s64]",
     "arguments": [
-      "int16_t value"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_s8]",
     "arguments": [
-      "int32_t value"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPGT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_u16]",
     "arguments": [
-      "int64_t value"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_u32]",
     "arguments": [
-      "int8_t value"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_u64]",
     "arguments": [
-      "uint16_t value"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt[_u8]",
     "arguments": [
-      "uint32_t value"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_n_s16]",
     "arguments": [
-      "uint64_t value"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "INS"
+        "CMPLT"
+      ],
+      [
+        "CMPLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdup_n_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_n_s32]",
     "arguments": [
-      "uint8_t value"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
+      ],
+      [
+        "CMPLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupb_lane_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_n_s8]",
     "arguments": [
-      "poly8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "poly8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -26286,27 +31710,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
+      ],
+      [
+        "CMPLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupb_lane_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_n_u16]",
     "arguments": [
-      "int8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -26314,27 +31744,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
+      ],
+      [
+        "CMPLO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupb_lane_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_n_u32]",
     "arguments": [
-      "uint8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -26342,27 +31778,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
+      ],
+      [
+        "CMPLO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupb_laneq_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_n_u8]",
     "arguments": [
-      "poly8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "poly8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -26370,27 +31812,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
+      ],
+      [
+        "CMPLO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupb_laneq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_s16]",
     "arguments": [
-      "int8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -26398,27 +31846,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupb_laneq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_s32]",
     "arguments": [
-      "uint8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -26426,27 +31877,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupd_lane_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_s8]",
     "arguments": [
-      "float64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -26454,27 +31908,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupd_lane_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_u16]",
     "arguments": [
-      "int64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -26482,27 +31939,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupd_lane_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_u32]",
     "arguments": [
-      "uint64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -26510,27 +31970,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupd_laneq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmplt_wide[_u8]",
     "arguments": [
-      "float64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -26538,27 +32001,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPLO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupd_laneq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_f16]",
     "arguments": [
-      "int64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -26566,27 +32032,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupd_laneq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_f32]",
     "arguments": [
-      "uint64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -26594,27 +32063,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_f64]",
     "arguments": [
-      "float16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -26622,27 +32094,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_lane_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_f16]",
     "arguments": [
-      "poly16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "poly16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -26650,27 +32125,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMNE"
+      ],
+      [
+        "FCMNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_lane_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_f32]",
     "arguments": [
-      "int16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -26678,27 +32159,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMNE"
+      ],
+      [
+        "FCMNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_lane_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_f64]",
     "arguments": [
-      "uint16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -26706,27 +32193,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMNE"
+      ],
+      [
+        "FCMNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_s16]",
     "arguments": [
-      "float16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -26734,27 +32227,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_laneq_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_s32]",
     "arguments": [
-      "poly16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "poly16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -26762,27 +32261,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_laneq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_s64]",
     "arguments": [
-      "int16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -26790,27 +32295,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vduph_laneq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_s8]",
     "arguments": [
-      "uint16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -26818,87 +32329,101 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_u16]",
     "arguments": [
-      "float16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_u32]",
     "arguments": [
-      "float32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_u64]",
     "arguments": [
-      "float64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -26906,356 +32431,383 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_n_u8]",
     "arguments": [
-      "poly16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_s16]",
     "arguments": [
-      "poly64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_s32]",
     "arguments": [
-      "poly8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_s64]",
     "arguments": [
-      "int16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_s8]",
     "arguments": [
-      "int32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_u16]",
     "arguments": [
-      "int64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_u32]",
     "arguments": [
-      "int8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_u64]",
     "arguments": [
-      "uint16x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.4H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne[_u8]",
     "arguments": [
-      "uint32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne_wide[_n_s16]",
     "arguments": [
-      "uint64x1_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.1D"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_lane_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne_wide[_n_s32]",
     "arguments": [
-      "uint8x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.8B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne_wide[_n_s8]",
     "arguments": [
-      "float16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -27263,27 +32815,33 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
+      ],
+      [
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne_wide[_s16]",
     "arguments": [
-      "float32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -27291,27 +32849,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne_wide[_s32]",
     "arguments": [
-      "float64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -27319,27 +32880,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpne_wide[_s8]",
     "arguments": [
-      "poly16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint64_t op2"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.B"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -27347,27 +32911,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CMPNE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpuo[_f16]",
     "arguments": [
-      "poly64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -27375,27 +32942,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMUO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpuo[_f32]",
     "arguments": [
-      "poly8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -27403,27 +32973,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMUO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpuo[_f64]",
     "arguments": [
-      "int16x8_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -27431,27 +33004,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMUO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpuo[_n_f16]",
     "arguments": [
-      "int32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op1": {
+        "register": "Zop1.H"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -27459,27 +33035,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMUO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpuo[_n_f32]",
     "arguments": [
-      "int64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op1": {
+        "register": "Zop1.S"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -27487,27 +33066,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMUO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcmpuo[_n_f64]",
     "arguments": [
-      "int8x16_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "op1": {
+        "register": "Zop1.D"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -27515,27 +33097,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "FCMUO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s16]_m",
     "arguments": [
-      "uint16x8_t vec",
-      "const int lane"
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
       },
-      "vec": {
-        "register": "Vn.8H"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -27543,27 +33128,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s16]_x",
     "arguments": [
-      "uint32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op": {
+        "register": "Zop.H|Ztied.H"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -27571,27 +33159,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s16]_z",
     "arguments": [
-      "uint64x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op": {
+        "register": "Zop.H"
       },
-      "vec": {
-        "register": "Vn.2D"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -27599,27 +33190,31 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_laneq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s32]_m",
     "arguments": [
-      "uint8x16_t vec",
-      "const int lane"
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
       },
-      "vec": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -27627,72 +33222,93 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s32]_x",
     "arguments": [
-      "float16_t value"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s32]_z",
     "arguments": [
-      "float32_t value"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s64]_m",
     "arguments": [
-      "float64_t value"
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -27700,301 +33316,375 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s64]_x",
     "arguments": [
-      "poly16_t value"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s64]_z",
     "arguments": [
-      "poly64_t value"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s8]_m",
     "arguments": [
-      "poly8_t value"
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s8]_x",
     "arguments": [
-      "int16_t value"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_s8]_z",
     "arguments": [
-      "int32_t value"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u16]_m",
     "arguments": [
-      "int64_t value"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u16]_x",
     "arguments": [
-      "int8_t value"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u16]_z",
     "arguments": [
-      "uint16_t value"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u32]_m",
     "arguments": [
-      "uint32_t value"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u32]_x",
     "arguments": [
-      "uint64_t value"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdupq_n_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u32]_z",
     "arguments": [
-      "uint8_t value"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdups_lane_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u64]_m",
     "arguments": [
-      "float32x2_t vec",
-      "const int lane"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -28002,27 +33692,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdups_lane_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u64]_x",
     "arguments": [
-      "int32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op": {
+        "register": "Zop.D|Ztied.D"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -28030,27 +33723,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdups_lane_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u64]_z",
     "arguments": [
-      "uint32x2_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "op": {
+        "register": "Zop.D"
       },
-      "vec": {
-        "register": "Vn.2S"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -28058,27 +33754,31 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdups_laneq_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u8]_m",
     "arguments": [
-      "float32x4_t vec",
-      "const int lane"
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -28086,27 +33786,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdups_laneq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u8]_x",
     "arguments": [
-      "int32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op": {
+        "register": "Zop.B|Ztied.B"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -28114,27 +33817,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "CNOT"
+      ],
+      [
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vdups_laneq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnot[_u8]_z",
     "arguments": [
-      "uint32x4_t vec",
-      "const int lane"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "op": {
+        "register": "Zop.B"
       },
-      "vec": {
-        "register": "Vn.4S"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -28142,779 +33848,845 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MOVPRFX",
+        "CNOT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f16]_m",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.H"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f16]_x",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H|Ztied.H"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.H"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f16]_z",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b",
-      "int64x2_t c"
+      "svbool_t pg",
+      "svfloat16_t op"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.H"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f32]_m",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.S"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f32]_x",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.S|Ztied.S"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.S"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f32]_z",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "svbool_t pg",
+      "svfloat32_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.S"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f64]_m",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
-      "uint64x2_t c"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.D"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor3q_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f64]_x",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.D|Ztied.D"
       },
-      "b": {},
-      "c": {}
+      "pg": {
+        "register": "Pg.D"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "EOR3"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_f64]_z",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "svbool_t pg",
+      "svfloat64_t op"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s16]_m",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s16]_x",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s16]_z",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "svbool_t pg",
+      "svint16_t op"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s32]_m",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s32]_x",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s32]_z",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "svbool_t pg",
+      "svint32_t op"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veor_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s64]_m",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s64]_x",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.D|Ztied.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s64]_z",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "svbool_t pg",
+      "svint64_t op"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s8]_m",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_s8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s8]_x",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.B|Ztied.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_s8]_z",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "svbool_t pg",
+      "svint8_t op"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_u32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u16]_m",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_u64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u16]_x",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H|Ztied.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "veorq_u8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u16]_z",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "svbool_t pg",
+      "svuint16_t op"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "op": {
+        "register": "Zop.H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EOR"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_f16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u32]_m",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b",
-      "const int n"
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 3
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_f32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u32]_x",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b",
-      "const int n"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.S|Ztied.S"
       },
-      "b": {
-        "register": "Vm.8B"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 1
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_f64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u32]_z",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b",
-      "const int n"
+      "svbool_t pg",
+      "svuint32_t op"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "op": {
+        "register": "Zop.S"
       },
-      "b": {
-        "register": "Vm.8B"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 0
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -28922,266 +34694,197743 @@
     ],
     "instructions": [
       [
-        "EXT"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_p16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u64]_m",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b",
-      "const int n"
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 3
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_p64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u64]_x",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b",
-      "const int n"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.D|Ztied.D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 0
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_p8",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u64]_z",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b",
-      "const int n"
+      "svbool_t pg",
+      "svuint64_t op"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "svuint64_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "pg": {
+        "register": "Pg.D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_s16",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u8]_m",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "const int n"
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
       },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.B"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 3
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_s32",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u8]_x",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "const int n"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.B|Ztied.B"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 1
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNT"
+      ],
+      [
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_s64",
+    "SIMD_ISA": "SVE",
+    "name": "svcnt[_u8]_z",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b",
-      "const int n"
+      "svbool_t pg",
+      "svuint8_t op"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "svuint8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+      "op": {
+        "register": "Zop.B"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 0
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "MOVPRFX",
+        "CNT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_s8",
-    "arguments": [
-      "int8x8_t a",
-      "int8x8_t b",
-      "const int n"
-    ],
+    "SIMD_ISA": "SVE",
+    "name": "svcntb",
+    "arguments": [],
     "return_type": {
-      "value": "int8x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
-      }
+      "value": "uint64_t"
     },
+    "Arguments_Preparation": {},
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "EXT"
+        "CNTB"
       ]
     ]
   },
   {
-    "SIMD_ISA": "Neon",
-    "name": "vext_u16",
+    "SIMD_ISA": "SVE",
+    "name": "svcntb_pat",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "const int n"
+      "enum svpattern pattern"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint64_t"
     },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
-      },
-      "n": {
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntd",
+    "arguments": [],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntd_pat",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcnth",
+    "arguments": [],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcnth_pat",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntp_b16",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntp_b32",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntp_b64",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntp_b8",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcntp_c16",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "pnn": {
+        "register": "PNreg1.H"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcntp_c32",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "pnn": {
+        "register": "PNreg1.S"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcntp_c64",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "pnn": {
+        "register": "PNreg1.D"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcntp_c8",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "pnn": {
+        "register": "PNreg1.B"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntw",
+    "arguments": [],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcntw_pat",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcompact[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "COMPACT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcompact[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "COMPACT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcompact[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "COMPACT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcompact[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "COMPACT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcompact[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "COMPACT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcompact[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "COMPACT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcreate2[_b]",
+    "arguments": [
+      "svbool_t x",
+      "svbool_t y"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_f16]",
+    "arguments": [
+      "svfloat16_t x0",
+      "svfloat16_t x1"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_f32]",
+    "arguments": [
+      "svfloat32_t x0",
+      "svfloat32_t x1"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_f64]",
+    "arguments": [
+      "svfloat64_t x0",
+      "svfloat64_t x1"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_s16]",
+    "arguments": [
+      "svint16_t x0",
+      "svint16_t x1"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_s32]",
+    "arguments": [
+      "svint32_t x0",
+      "svint32_t x1"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_s64]",
+    "arguments": [
+      "svint64_t x0",
+      "svint64_t x1"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_s8]",
+    "arguments": [
+      "svint8_t x0",
+      "svint8_t x1"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_u16]",
+    "arguments": [
+      "svuint16_t x0",
+      "svuint16_t x1"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_u32]",
+    "arguments": [
+      "svuint32_t x0",
+      "svuint32_t x1"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_u64]",
+    "arguments": [
+      "svuint64_t x0",
+      "svuint64_t x1"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate2[_u8]",
+    "arguments": [
+      "svuint8_t x0",
+      "svuint8_t x1"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_f16]",
+    "arguments": [
+      "svfloat16_t x0",
+      "svfloat16_t x1",
+      "svfloat16_t x2"
+    ],
+    "return_type": {
+      "value": "svfloat16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_f32]",
+    "arguments": [
+      "svfloat32_t x0",
+      "svfloat32_t x1",
+      "svfloat32_t x2"
+    ],
+    "return_type": {
+      "value": "svfloat32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_f64]",
+    "arguments": [
+      "svfloat64_t x0",
+      "svfloat64_t x1",
+      "svfloat64_t x2"
+    ],
+    "return_type": {
+      "value": "svfloat64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_s16]",
+    "arguments": [
+      "svint16_t x0",
+      "svint16_t x1",
+      "svint16_t x2"
+    ],
+    "return_type": {
+      "value": "svint16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_s32]",
+    "arguments": [
+      "svint32_t x0",
+      "svint32_t x1",
+      "svint32_t x2"
+    ],
+    "return_type": {
+      "value": "svint32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_s64]",
+    "arguments": [
+      "svint64_t x0",
+      "svint64_t x1",
+      "svint64_t x2"
+    ],
+    "return_type": {
+      "value": "svint64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_s8]",
+    "arguments": [
+      "svint8_t x0",
+      "svint8_t x1",
+      "svint8_t x2"
+    ],
+    "return_type": {
+      "value": "svint8x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_u16]",
+    "arguments": [
+      "svuint16_t x0",
+      "svuint16_t x1",
+      "svuint16_t x2"
+    ],
+    "return_type": {
+      "value": "svuint16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_u32]",
+    "arguments": [
+      "svuint32_t x0",
+      "svuint32_t x1",
+      "svuint32_t x2"
+    ],
+    "return_type": {
+      "value": "svuint32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_u64]",
+    "arguments": [
+      "svuint64_t x0",
+      "svuint64_t x1",
+      "svuint64_t x2"
+    ],
+    "return_type": {
+      "value": "svuint64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate3[_u8]",
+    "arguments": [
+      "svuint8_t x0",
+      "svuint8_t x1",
+      "svuint8_t x2"
+    ],
+    "return_type": {
+      "value": "svuint8x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcreate4[_b]",
+    "arguments": [
+      "svbool_t x",
+      "svbool_t y",
+      "svbool_t z",
+      "svbool_t w"
+    ],
+    "return_type": {
+      "value": "svboolx4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_f16]",
+    "arguments": [
+      "svfloat16_t x0",
+      "svfloat16_t x1",
+      "svfloat16_t x2",
+      "svfloat16_t x3"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_f32]",
+    "arguments": [
+      "svfloat32_t x0",
+      "svfloat32_t x1",
+      "svfloat32_t x2",
+      "svfloat32_t x3"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_f64]",
+    "arguments": [
+      "svfloat64_t x0",
+      "svfloat64_t x1",
+      "svfloat64_t x2",
+      "svfloat64_t x3"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_s16]",
+    "arguments": [
+      "svint16_t x0",
+      "svint16_t x1",
+      "svint16_t x2",
+      "svint16_t x3"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_s32]",
+    "arguments": [
+      "svint32_t x0",
+      "svint32_t x1",
+      "svint32_t x2",
+      "svint32_t x3"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_s64]",
+    "arguments": [
+      "svint64_t x0",
+      "svint64_t x1",
+      "svint64_t x2",
+      "svint64_t x3"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_s8]",
+    "arguments": [
+      "svint8_t x0",
+      "svint8_t x1",
+      "svint8_t x2",
+      "svint8_t x3"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_u16]",
+    "arguments": [
+      "svuint16_t x0",
+      "svuint16_t x1",
+      "svuint16_t x2",
+      "svuint16_t x3"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_u32]",
+    "arguments": [
+      "svuint32_t x0",
+      "svuint32_t x1",
+      "svuint32_t x2",
+      "svuint32_t x3"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_u64]",
+    "arguments": [
+      "svuint64_t x0",
+      "svuint64_t x1",
+      "svuint64_t x2",
+      "svuint64_t x3"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcreate4[_u8]",
+    "arguments": [
+      "svuint8_t x0",
+      "svuint8_t x1",
+      "svuint8_t x2",
+      "svuint8_t x3"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_f32]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_f64]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s32]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s64]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u32]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u64]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f16[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_f16]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_f64]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_s32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_s64]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_u32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_u64]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f32[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_f16]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_f32]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVT"
+      ],
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_s32]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_s64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_u32]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_u64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ],
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_f64[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s16[_f16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s16[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s16[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f16]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f64]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s32[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f16]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f32]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_s64[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u16[_f16]_m",
+    "arguments": [
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u16[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u16[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f16]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f64]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u32[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f16]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f32]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svcvt_u64[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtlt_f32[_f16]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtlt_f32[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtlt_f64[_f32]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.D"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtlt_f64[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtnt_f16[_f32]_m",
+    "arguments": [
+      "svfloat16_t even",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtnt_f16[_f32]_x",
+    "arguments": [
+      "svfloat16_t even",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtnt_f32[_f64]_m",
+    "arguments": [
+      "svfloat32_t even",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtnt_f32[_f64]_x",
+    "arguments": [
+      "svfloat32_t even",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtx_f32[_f64]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTX"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtx_f32[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTX"
+      ],
+      [
+        "MOVPRFX",
+        "FCVTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtx_f32[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FCVTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtxnt_f32[_f64]_m",
+    "arguments": [
+      "svfloat32_t even",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTXNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svcvtxnt_f32[_f64]_x",
+    "arguments": [
+      "svfloat32_t even",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTXNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ],
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIV"
+      ],
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIV"
+      ],
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdiv[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIVR"
+      ],
+      [
+        "FDIV"
+      ],
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDIVR"
+      ],
+      [
+        "SDIV"
+      ],
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "SDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDIVR"
+      ],
+      [
+        "UDIV"
+      ],
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdivr[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UDIVR"
+      ],
+      [
+        "MOVPRFX",
+        "UDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svdot[_f32_f16]",
+    "arguments": [
+      "svfloat32_t zda",
+      "svfloat16_t zn",
+      "svfloat16_t zm"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "zda": {
+        "register": "Zreg1.S"
+      },
+      "zm": {
+        "register": "Zreg3.H"
+      },
+      "zn": {
+        "register": "Zreg2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ],
+      [
+        "MOVPRFX",
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ],
+      [
+        "MOVPRFX",
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svdot[_s32_s16]",
+    "arguments": [
+      "svint32_t zda",
+      "svint16_t zn",
+      "svint16_t zm"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "zda": {
+        "register": "Zreg1.S"
+      },
+      "zm": {
+        "register": "Zreg3.H"
+      },
+      "zn": {
+        "register": "Zreg2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ],
+      [
+        "MOVPRFX",
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svdot[_u32_u16]",
+    "arguments": [
+      "svuint32_t zda",
+      "svuint16_t zn",
+      "svuint16_t zm"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "zda": {
+        "register": "Zreg1.S"
+      },
+      "zm": {
+        "register": "Zreg3.H"
+      },
+      "zn": {
+        "register": "Zreg2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ],
+      [
+        "MOVPRFX",
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svdot_lane[_f32_f16]",
+    "arguments": [
+      "svfloat32_t zda",
+      "svfloat16_t zn",
+      "svfloat16_t zm",
+      "uint64_t imm_idx"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_idx": {
+        "immediate": "imm1"
+      },
+      "zda": {
+        "register": "Zreg1.S"
+      },
+      "zm": {
+        "register": "Zreg3.H"
+      },
+      "zn": {
+        "register": "Zreg2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "svint8_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svdot_lane[_s32_s16]",
+    "arguments": [
+      "svint32_t zda",
+      "svint16_t zn",
+      "svint16_t zm",
+      "uint64_t imm_idx"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_idx": {
+        "immediate": "imm1"
+      },
+      "zda": {
+        "register": "Zreg1.S"
+      },
+      "zm": {
+        "register": "Zreg3.H"
+      },
+      "zn": {
+        "register": "Zreg2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ],
+      [
+        "MOVPRFX",
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svdot_lane[_u32_u16]",
+    "arguments": [
+      "svuint32_t zda",
+      "svuint16_t zn",
+      "svuint16_t zm",
+      "uint64_t imm_idx"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_idx": {
+        "immediate": "imm1"
+      },
+      "zda": {
+        "register": "Zreg1.S"
+      },
+      "zm": {
+        "register": "Zreg3.H"
+      },
+      "zn": {
+        "register": "Zreg2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdot_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ],
+      [
+        "MOVPRFX",
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_b16",
+    "arguments": [
+      "bool op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_b32",
+    "arguments": [
+      "bool op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_b64",
+    "arguments": [
+      "bool op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_b8",
+    "arguments": [
+      "bool op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f16",
+    "arguments": [
+      "float16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f16_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "float16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f16_x",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f16_z",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f32",
+    "arguments": [
+      "float32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f32_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "float32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f32_x",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f32_z",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f64",
+    "arguments": [
+      "float64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f64_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "float64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.D"
+      },
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f64_x",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_f64_z",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s16",
+    "arguments": [
+      "int16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s16_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "int16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s16_x",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s16_z",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s32",
+    "arguments": [
+      "int32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s32_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "int32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s32_x",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s32_z",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s64",
+    "arguments": [
+      "int64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s64_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "int64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.D"
+      },
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s64_x",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s64_z",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s8",
+    "arguments": [
+      "int8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Bop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s8_m",
+    "arguments": [
+      "svint8_t inactive",
+      "svbool_t pg",
+      "int8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.B"
+      },
+      "op": {
+        "register": "Bop|Wop"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s8_x",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Bop|Wop"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_s8_z",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Bop|Wop"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u16",
+    "arguments": [
+      "uint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u16_m",
+    "arguments": [
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "uint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u16_x",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u16_z",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Hop|Wop"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u32",
+    "arguments": [
+      "uint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u32_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "uint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u32_x",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u32_z",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Sop|Wop"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u64",
+    "arguments": [
+      "uint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u64_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "uint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.D"
+      },
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u64_x",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u64_z",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Dop|Xop"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u8",
+    "arguments": [
+      "uint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Bop|Wop"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u8_m",
+    "arguments": [
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "uint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Ztied.B"
+      },
+      "op": {
+        "register": "Bop|Wop"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "CPY"
+      ],
+      [
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u8_x",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Bop|Wop"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "FCPY"
+      ],
+      [
+        "FDUP"
+      ],
+      [
+        "DUPM"
+      ],
+      [
+        "DUP"
+      ],
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup[_n]_u8_z",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Bop|Wop"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CPY"
+      ],
+      [
+        "DUP",
+        "FCPY"
+      ],
+      [
+        "DUP",
+        "CPY"
+      ],
+      [
+        "MOVPRFX",
+        "CPY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_f16]",
+    "arguments": [
+      "svfloat16_t data",
+      "uint16_t index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "index": {
+        "register": "Zindex.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_f32]",
+    "arguments": [
+      "svfloat32_t data",
+      "uint32_t index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index": {
+        "register": "Zindex.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_f64]",
+    "arguments": [
+      "svfloat64_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index": {
+        "register": "Zindex.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_s16]",
+    "arguments": [
+      "svint16_t data",
+      "uint16_t index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "index": {
+        "register": "Zindex.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_s32]",
+    "arguments": [
+      "svint32_t data",
+      "uint32_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index": {
+        "register": "Zindex.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_s64]",
+    "arguments": [
+      "svint64_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index": {
+        "register": "Zindex.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_s8]",
+    "arguments": [
+      "svint8_t data",
+      "uint8_t index"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.B"
+      },
+      "index": {
+        "register": "Zindex.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_u16]",
+    "arguments": [
+      "svuint16_t data",
+      "uint16_t index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "index": {
+        "register": "Zindex.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_u32]",
+    "arguments": [
+      "svuint32_t data",
+      "uint32_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index": {
+        "register": "Zindex.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_u64]",
+    "arguments": [
+      "svuint64_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index": {
+        "register": "Zindex.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdup_lane[_u8]",
+    "arguments": [
+      "svuint8_t data",
+      "uint8_t index"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.B"
+      },
+      "index": {
+        "register": "Zindex.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_b16",
+    "arguments": [
+      "bool x0",
+      "bool x1",
+      "bool x2",
+      "bool x3",
+      "bool x4",
+      "bool x5",
+      "bool x6",
+      "bool x7"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_b32",
+    "arguments": [
+      "bool x0",
+      "bool x1",
+      "bool x2",
+      "bool x3"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_b64",
+    "arguments": [
+      "bool x0",
+      "bool x1"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_b8",
+    "arguments": [
+      "bool x0",
+      "bool x1",
+      "bool x2",
+      "bool x3",
+      "bool x4",
+      "bool x5",
+      "bool x6",
+      "bool x7",
+      "bool x8",
+      "bool x9",
+      "bool x10",
+      "bool x11",
+      "bool x12",
+      "bool x13",
+      "bool x14",
+      "bool x15"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_f16",
+    "arguments": [
+      "float16_t x0",
+      "float16_t x1",
+      "float16_t x2",
+      "float16_t x3",
+      "float16_t x4",
+      "float16_t x5",
+      "float16_t x6",
+      "float16_t x7"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_f32",
+    "arguments": [
+      "float32_t x0",
+      "float32_t x1",
+      "float32_t x2",
+      "float32_t x3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_f64",
+    "arguments": [
+      "float64_t x0",
+      "float64_t x1"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_s16",
+    "arguments": [
+      "int16_t x0",
+      "int16_t x1",
+      "int16_t x2",
+      "int16_t x3",
+      "int16_t x4",
+      "int16_t x5",
+      "int16_t x6",
+      "int16_t x7"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_s32",
+    "arguments": [
+      "int32_t x0",
+      "int32_t x1",
+      "int32_t x2",
+      "int32_t x3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_s64",
+    "arguments": [
+      "int64_t x0",
+      "int64_t x1"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_s8",
+    "arguments": [
+      "int8_t x0",
+      "int8_t x1",
+      "int8_t x2",
+      "int8_t x3",
+      "int8_t x4",
+      "int8_t x5",
+      "int8_t x6",
+      "int8_t x7",
+      "int8_t x8",
+      "int8_t x9",
+      "int8_t x10",
+      "int8_t x11",
+      "int8_t x12",
+      "int8_t x13",
+      "int8_t x14",
+      "int8_t x15"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_u16",
+    "arguments": [
+      "uint16_t x0",
+      "uint16_t x1",
+      "uint16_t x2",
+      "uint16_t x3",
+      "uint16_t x4",
+      "uint16_t x5",
+      "uint16_t x6",
+      "uint16_t x7"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_u32",
+    "arguments": [
+      "uint32_t x0",
+      "uint32_t x1",
+      "uint32_t x2",
+      "uint32_t x3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_u64",
+    "arguments": [
+      "uint64_t x0",
+      "uint64_t x1"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq[_n]_u8",
+    "arguments": [
+      "uint8_t x0",
+      "uint8_t x1",
+      "uint8_t x2",
+      "uint8_t x3",
+      "uint8_t x4",
+      "uint8_t x5",
+      "uint8_t x6",
+      "uint8_t x7",
+      "uint8_t x8",
+      "uint8_t x9",
+      "uint8_t x10",
+      "uint8_t x11",
+      "uint8_t x12",
+      "uint8_t x13",
+      "uint8_t x14",
+      "uint8_t x15"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_f16]",
+    "arguments": [
+      "svfloat16_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_f32]",
+    "arguments": [
+      "svfloat32_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_f64]",
+    "arguments": [
+      "svfloat64_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_s16]",
+    "arguments": [
+      "svint16_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_s32]",
+    "arguments": [
+      "svint32_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_s64]",
+    "arguments": [
+      "svint64_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_s8]",
+    "arguments": [
+      "svint8_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_u16]",
+    "arguments": [
+      "svuint16_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_u32]",
+    "arguments": [
+      "svuint32_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_u64]",
+    "arguments": [
+      "svuint64_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svdupq_lane[_u8]",
+    "arguments": [
+      "svuint8_t data",
+      "uint64_t index"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D|Zdata.Q"
+      },
+      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
+        "register": "Zindices_d.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ],
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveor3[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "EOR3"
+      ],
+      [
+        "MOVPRFX",
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ],
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveor[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "EOR"
+      ],
+      [
+        "MOVPRFX",
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_s16]",
+    "arguments": [
+      "svint16_t odd",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_s32]",
+    "arguments": [
+      "svint32_t odd",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_s64]",
+    "arguments": [
+      "svint64_t odd",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_s8]",
+    "arguments": [
+      "svint8_t odd",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_u16]",
+    "arguments": [
+      "svuint16_t odd",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_u32]",
+    "arguments": [
+      "svuint32_t odd",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_u64]",
+    "arguments": [
+      "svuint64_t odd",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_n_u8]",
+    "arguments": [
+      "svuint8_t odd",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_s16]",
+    "arguments": [
+      "svint16_t odd",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_s32]",
+    "arguments": [
+      "svint32_t odd",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_s64]",
+    "arguments": [
+      "svint64_t odd",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_s8]",
+    "arguments": [
+      "svint8_t odd",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_u16]",
+    "arguments": [
+      "svuint16_t odd",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_u32]",
+    "arguments": [
+      "svuint32_t odd",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_u64]",
+    "arguments": [
+      "svuint64_t odd",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveorbt[_u8]",
+    "arguments": [
+      "svuint8_t odd",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "odd": {
+        "register": "Zodd.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORBT"
+      ],
+      [
+        "MOVPRFX",
+        "EORBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_s16]",
+    "arguments": [
+      "svint16_t even",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_s32]",
+    "arguments": [
+      "svint32_t even",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_s64]",
+    "arguments": [
+      "svint64_t even",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_s8]",
+    "arguments": [
+      "svint8_t even",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_u16]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_u32]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_u64]",
+    "arguments": [
+      "svuint64_t even",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_n_u8]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_s16]",
+    "arguments": [
+      "svint16_t even",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_s32]",
+    "arguments": [
+      "svint32_t even",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_s64]",
+    "arguments": [
+      "svint64_t even",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_s8]",
+    "arguments": [
+      "svint8_t even",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_u16]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.H|Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_u32]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.S|Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_u64]",
+    "arguments": [
+      "svuint64_t even",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.D|Ztied.D"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "sveortb[_u8]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Zeven.B|Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORTB"
+      ],
+      [
+        "MOVPRFX",
+        "EORTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "sveorv[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexpa[_f16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FEXPA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexpa[_f32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FEXPA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexpa[_f64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FEXPA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 127
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 127
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 255
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 127
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svext[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 255
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ],
+      [
+        "MOVPRFX",
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTB"
+      ],
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTB"
+      ],
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTB"
+      ],
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTB"
+      ],
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTB"
+      ],
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTB"
+      ],
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u16]_m",
+    "arguments": [
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTB"
+      ],
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTB"
+      ],
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTB"
+      ],
+      [
+        "MOVPRFX",
+        "UXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTB"
+      ],
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextb[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UXTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTH"
+      ],
+      [
+        "MOVPRFX",
+        "SXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTH"
+      ],
+      [
+        "MOVPRFX",
+        "SXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTH"
+      ],
+      [
+        "MOVPRFX",
+        "SXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTH"
+      ],
+      [
+        "MOVPRFX",
+        "SXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTH"
+      ],
+      [
+        "MOVPRFX",
+        "UXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTH"
+      ],
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTH"
+      ],
+      [
+        "MOVPRFX",
+        "UXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTH"
+      ],
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svexth[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UXTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextw[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTW"
+      ],
+      [
+        "MOVPRFX",
+        "SXTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextw[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SXTW"
+      ],
+      [
+        "MOVPRFX",
+        "SXTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextw[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SXTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextw[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTW"
+      ],
+      [
+        "MOVPRFX",
+        "UXTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextw[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UXTW"
+      ],
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svextw[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UXTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svget2[_b]",
+    "arguments": [
+      "svboolx2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_f16]",
+    "arguments": [
+      "svfloat16x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_f32]",
+    "arguments": [
+      "svfloat32x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_f64]",
+    "arguments": [
+      "svfloat64x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_s16]",
+    "arguments": [
+      "svint16x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_s32]",
+    "arguments": [
+      "svint32x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_s64]",
+    "arguments": [
+      "svint64x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_s8]",
+    "arguments": [
+      "svint8x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_u16]",
+    "arguments": [
+      "svuint16x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_u32]",
+    "arguments": [
+      "svuint32x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_u64]",
+    "arguments": [
+      "svuint64x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget2[_u8]",
+    "arguments": [
+      "svuint8x2_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_f16]",
+    "arguments": [
+      "svfloat16x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_f32]",
+    "arguments": [
+      "svfloat32x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_f64]",
+    "arguments": [
+      "svfloat64x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_s16]",
+    "arguments": [
+      "svint16x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_s32]",
+    "arguments": [
+      "svint32x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_s64]",
+    "arguments": [
+      "svint64x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_s8]",
+    "arguments": [
+      "svint8x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_u16]",
+    "arguments": [
+      "svuint16x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_u32]",
+    "arguments": [
+      "svuint32x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_u64]",
+    "arguments": [
+      "svuint64x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget3[_u8]",
+    "arguments": [
+      "svuint8x3_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svget4[_b]",
+    "arguments": [
+      "svboolx4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_f16]",
+    "arguments": [
+      "svfloat16x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_f32]",
+    "arguments": [
+      "svfloat32x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_f64]",
+    "arguments": [
+      "svfloat64x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_s16]",
+    "arguments": [
+      "svint16x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_s32]",
+    "arguments": [
+      "svint32x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_s64]",
+    "arguments": [
+      "svint64x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_s8]",
+    "arguments": [
+      "svint8x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_u16]",
+    "arguments": [
+      "svuint16x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_u32]",
+    "arguments": [
+      "svuint32x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_u64]",
+    "arguments": [
+      "svuint64x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svget4[_u8]",
+    "arguments": [
+      "svuint8x4_t tuple",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHADD"
+      ],
+      [
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHADD"
+      ],
+      [
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhadd[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHADD"
+      ],
+      [
+        "MOVPRFX",
+        "UHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhistcnt[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "HISTCNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhistcnt[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "HISTCNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhistcnt[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "HISTCNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhistcnt[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "HISTCNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhistseg[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "HISTSEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhistseg[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "HISTSEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUB"
+      ],
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUB"
+      ],
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsub[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHSUBR"
+      ],
+      [
+        "SHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UHSUBR"
+      ],
+      [
+        "UHSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svhsubr[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UHSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UHSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_s16",
+    "arguments": [
+      "int16_t base",
+      "int16_t step"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Wbase"
+      },
+      "step": {
+        "register": "Wstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_s32",
+    "arguments": [
+      "int32_t base",
+      "int32_t step"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Wbase"
+      },
+      "step": {
+        "register": "Wstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_s64",
+    "arguments": [
+      "int64_t base",
+      "int64_t step"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "step": {
+        "register": "Xstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_s8",
+    "arguments": [
+      "int8_t base",
+      "int8_t step"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Wbase"
+      },
+      "step": {
+        "register": "Wstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_u16",
+    "arguments": [
+      "uint16_t base",
+      "uint16_t step"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Wbase"
+      },
+      "step": {
+        "register": "Wstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_u32",
+    "arguments": [
+      "uint32_t base",
+      "uint32_t step"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Wbase"
+      },
+      "step": {
+        "register": "Wstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_u64",
+    "arguments": [
+      "uint64_t base",
+      "uint64_t step"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "step": {
+        "register": "Xstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svindex_u8",
+    "arguments": [
+      "uint8_t base",
+      "uint8_t step"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Wbase"
+      },
+      "step": {
+        "register": "Wstep"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ],
+      [
+        "INDEX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Hop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Sop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Dop2|Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Hop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Sop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Dop2|Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Bop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Hop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Sop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Dop2|Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svinsr[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Bop2|Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INSR"
+      ],
+      [
+        "INSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlasta[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTA"
+      ],
+      [
+        "LASTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlastb[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LASTB"
+      ],
+      [
+        "LASTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_f16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_f16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_f32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_f32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_f64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_f64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_s8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1[_u8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_index_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_offset_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_index_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_offset_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s32]index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u32]index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_gather_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_f16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_f16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_f32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_f32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_f64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_f64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_s8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1D"
+      ],
+      [
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LD1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svld1_vnum[_u8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROH"
+      ],
+      [
+        "LD1ROH"
+      ],
+      [
+        "LD1ROH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROW"
+      ],
+      [
+        "LD1ROW"
+      ],
+      [
+        "LD1ROW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROD"
+      ],
+      [
+        "LD1ROD"
+      ],
+      [
+        "LD1ROD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROH"
+      ],
+      [
+        "LD1ROH"
+      ],
+      [
+        "LD1ROH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROW"
+      ],
+      [
+        "LD1ROW"
+      ],
+      [
+        "LD1ROW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROD"
+      ],
+      [
+        "LD1ROD"
+      ],
+      [
+        "LD1ROD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROB"
+      ],
+      [
+        "LD1ROB"
+      ],
+      [
+        "LD1ROB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROH"
+      ],
+      [
+        "LD1ROH"
+      ],
+      [
+        "LD1ROH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROW"
+      ],
+      [
+        "LD1ROW"
+      ],
+      [
+        "LD1ROW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROD"
+      ],
+      [
+        "LD1ROD"
+      ],
+      [
+        "LD1ROD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ro[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1ROB"
+      ],
+      [
+        "LD1ROB"
+      ],
+      [
+        "LD1ROB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQH"
+      ],
+      [
+        "LD1RQH"
+      ],
+      [
+        "LD1RQH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQW"
+      ],
+      [
+        "LD1RQW"
+      ],
+      [
+        "LD1RQW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQD"
+      ],
+      [
+        "LD1RQD"
+      ],
+      [
+        "LD1RQD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQH"
+      ],
+      [
+        "LD1RQH"
+      ],
+      [
+        "LD1RQH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQW"
+      ],
+      [
+        "LD1RQW"
+      ],
+      [
+        "LD1RQW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQD"
+      ],
+      [
+        "LD1RQD"
+      ],
+      [
+        "LD1RQD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQB"
+      ],
+      [
+        "LD1RQB"
+      ],
+      [
+        "LD1RQB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQH"
+      ],
+      [
+        "LD1RQH"
+      ],
+      [
+        "LD1RQH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQW"
+      ],
+      [
+        "LD1RQW"
+      ],
+      [
+        "LD1RQW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQD"
+      ],
+      [
+        "LD1RQD"
+      ],
+      [
+        "LD1RQD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1rq[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1RQB"
+      ],
+      [
+        "LD1RQB"
+      ],
+      [
+        "LD1RQB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_vnum_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_vnum_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sb_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SB"
+      ],
+      [
+        "LD1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sh_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SH"
+      ],
+      [
+        "LD1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1sw_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1SW"
+      ],
+      [
+        "LD1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_vnum_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_vnum_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1ub_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1B"
+      ],
+      [
+        "LD1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uh_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1H"
+      ],
+      [
+        "LD1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld1uw_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD1W"
+      ],
+      [
+        "LD1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2H"
+      ],
+      [
+        "LD2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2W"
+      ],
+      [
+        "LD2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2D"
+      ],
+      [
+        "LD2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2H"
+      ],
+      [
+        "LD2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2W"
+      ],
+      [
+        "LD2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2D"
+      ],
+      [
+        "LD2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2B"
+      ],
+      [
+        "LD2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2H"
+      ],
+      [
+        "LD2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2W"
+      ],
+      [
+        "LD2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2D"
+      ],
+      [
+        "LD2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2B"
+      ],
+      [
+        "LD2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2H"
+      ],
+      [
+        "LD2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2W"
+      ],
+      [
+        "LD2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2D"
+      ],
+      [
+        "LD2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2H"
+      ],
+      [
+        "LD2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2W"
+      ],
+      [
+        "LD2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2D"
+      ],
+      [
+        "LD2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2B"
+      ],
+      [
+        "LD2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2H"
+      ],
+      [
+        "LD2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2W"
+      ],
+      [
+        "LD2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2D"
+      ],
+      [
+        "LD2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld2_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD2B"
+      ],
+      [
+        "LD2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3H"
+      ],
+      [
+        "LD3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3W"
+      ],
+      [
+        "LD3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3D"
+      ],
+      [
+        "LD3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3H"
+      ],
+      [
+        "LD3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3W"
+      ],
+      [
+        "LD3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3D"
+      ],
+      [
+        "LD3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3B"
+      ],
+      [
+        "LD3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3H"
+      ],
+      [
+        "LD3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3W"
+      ],
+      [
+        "LD3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3D"
+      ],
+      [
+        "LD3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3B"
+      ],
+      [
+        "LD3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3H"
+      ],
+      [
+        "LD3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3W"
+      ],
+      [
+        "LD3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3D"
+      ],
+      [
+        "LD3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3H"
+      ],
+      [
+        "LD3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3W"
+      ],
+      [
+        "LD3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3D"
+      ],
+      [
+        "LD3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3B"
+      ],
+      [
+        "LD3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3H"
+      ],
+      [
+        "LD3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3W"
+      ],
+      [
+        "LD3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3D"
+      ],
+      [
+        "LD3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld3_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x3_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD3B"
+      ],
+      [
+        "LD3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4H"
+      ],
+      [
+        "LD4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4W"
+      ],
+      [
+        "LD4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4D"
+      ],
+      [
+        "LD4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4H"
+      ],
+      [
+        "LD4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4W"
+      ],
+      [
+        "LD4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4D"
+      ],
+      [
+        "LD4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4B"
+      ],
+      [
+        "LD4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4H"
+      ],
+      [
+        "LD4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4W"
+      ],
+      [
+        "LD4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4D"
+      ],
+      [
+        "LD4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4B"
+      ],
+      [
+        "LD4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4H"
+      ],
+      [
+        "LD4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4W"
+      ],
+      [
+        "LD4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4D"
+      ],
+      [
+        "LD4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4H"
+      ],
+      [
+        "LD4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4W"
+      ],
+      [
+        "LD4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4D"
+      ],
+      [
+        "LD4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4B"
+      ],
+      [
+        "LD4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4H"
+      ],
+      [
+        "LD4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4W"
+      ],
+      [
+        "LD4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4D"
+      ],
+      [
+        "LD4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svld4_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LD4B"
+      ],
+      [
+        "LD4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_index_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_offset_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_index_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_offset_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ],
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s32]index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u32]index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_gather_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ],
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_vnum_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_vnum_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sb_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ],
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sh_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ],
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ],
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ],
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ],
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ],
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ],
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1sw_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ],
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_vnum_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_vnum_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1ub_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u32]index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u32]index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ],
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uh_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ],
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldff1uw_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDFF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ],
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 8": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1D"
+      ],
+      [
+        "LDNF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ],
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 8": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1D"
+      ],
+      [
+        "LDNF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntb()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ],
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 8": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1D"
+      ],
+      [
+        "LDNF1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntb()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_vnum_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ],
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ],
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ],
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_vnum_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ],
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ],
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sb_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SB"
+      ],
+      [
+        "LDNF1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ],
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ],
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ],
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sh_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SH"
+      ],
+      [
+        "LDNF1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sw_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sw_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sw_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SW"
+      ],
+      [
+        "LDNF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1sw_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1SW"
+      ],
+      [
+        "LDNF1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_vnum_s16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_vnum_u16",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcnth()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1ub_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd()": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1B"
+      ],
+      [
+        "LDNF1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_vnum_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_vnum_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntw() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uh_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 2": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1H"
+      ],
+      [
+        "LDNF1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uw_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uw_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uw_vnum_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ],
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnf1uw_vnum_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "base + vnum * svcntd() * 4": {
+        "register": "Xptr"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNF1W"
+      ],
+      [
+        "LDNF1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ],
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_f16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_f16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ],
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_f32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_f32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ],
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_f64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_f64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ],
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ],
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ],
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ],
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_s8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ],
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ],
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ],
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ],
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1[_u8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_index_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_offset_f32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_index_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_offset_f64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[s64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[s64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_gather_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "const float16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ],
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_f16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_f16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "const float32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ],
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_f32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_f32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "const float64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ],
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_f64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_f64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "float64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ],
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ],
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "const int64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ],
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ],
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_s8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "int8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ],
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u16]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u16]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ],
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u32]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u32]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint64_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1D"
+      ],
+      [
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u64]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u64]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "LDNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svldnt1_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ],
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u8]_x2",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1_vnum[_u8]_x4",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t const * rn",
+      "int64_t vnum"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MUL",
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sb_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sh_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1sw_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const int32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1SW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1ub_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint8_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u32base]_index_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u32base]_index_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u32base]_offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u32base]_offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u32base]_s32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u32base]_u32",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[u32]offset_s32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[u32]offset_u32",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint32_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uh_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint16_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather[_u64base]_index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather[_u64base]_index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather[_u64base]_offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather[_u64base]_offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather[_u64base]_s64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather[_u64base]_u64",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[s64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[s64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[s64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[s64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[u64]index_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[u64]index_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[u64]offset_s64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svldnt1uw_gather_[u64]offset_u64",
+    "arguments": [
+      "svbool_t pg",
+      "const uint32_t *base",
+      "svuint64_t offsets"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlen[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FLOGB"
+      ],
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FLOGB"
+      ],
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FLOGB"
+      ],
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FLOGB"
+      ],
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FLOGB"
+      ],
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FLOGB"
+      ],
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svlogb[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FLOGB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSLR"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsl_wide[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSRR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSRR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSR"
+      ],
+      [
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svlsr_wide[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmad[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmatch[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmatch[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmatch[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmatch[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ],
+      [
+        "MOVPRFX",
+        "FMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAX"
+      ],
+      [
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMAX"
+      ],
+      [
+        "MOVPRFX",
+        "SMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAX"
+      ],
+      [
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmax[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMAX"
+      ],
+      [
+        "MOVPRFX",
+        "UMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnm[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxnmp[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxnmp[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxnmp[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxnmp[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxnmp[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxnmp[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnmv[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnmv[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxnmv[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXNMV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "FMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "SMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmaxp[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXP"
+      ],
+      [
+        "MOVPRFX",
+        "UMAXP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmaxv[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMAXV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ],
+      [
+        "MOVPRFX",
+        "FMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMIN"
+      ],
+      [
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMIN"
+      ],
+      [
+        "MOVPRFX",
+        "SMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMIN"
+      ],
+      [
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmin[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMIN"
+      ],
+      [
+        "MOVPRFX",
+        "UMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnm[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminnmp[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminnmp[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminnmp[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminnmp[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminnmp[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminnmp[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINNMP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnmv[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnmv[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminnmv[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINNMV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINP"
+      ],
+      [
+        "MOVPRFX",
+        "FMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINP"
+      ],
+      [
+        "MOVPRFX",
+        "SMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svminp[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINP"
+      ],
+      [
+        "MOVPRFX",
+        "UMINP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svminv[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMINV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ],
+      [
+        "MOVPRFX",
+        "MAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla_lane[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmla_lane[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmla_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmla_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmla_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmla_lane[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmla_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmla_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLA"
+      ],
+      [
+        "MOVPRFX",
+        "MLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalb_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "FMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "FMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "FMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlalt_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls_lane[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmls_lane[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmls_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmls_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmls_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmls_lane[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmls_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmls_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslb_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "FMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "FMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "FMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmlslt_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "UMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmmla[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmmla[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FMMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmmla[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMMLA"
+      ],
+      [
+        "MOVPRFX",
+        "SMMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmmla[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMMLA"
+      ],
+      [
+        "MOVPRFX",
+        "UMMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmov[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlb[_s16]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlb[_s32]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlb[_s64]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlb[_u16]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlb[_u32]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlb[_u64]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlt[_s16]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlt[_s32]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlt[_s64]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlt[_u16]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlt[_u32]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmovlt[_u64]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMSB"
+      ],
+      [
+        "FMSB"
+      ],
+      [
+        "FMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]|Ztied3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "op3": {
+        "register": "Zop3.B|Ztied3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MSB"
+      ],
+      [
+        "MSB"
+      ],
+      [
+        "MLS"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmsb[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MSB"
+      ],
+      [
+        "MOVPRFX",
+        "MLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ],
+      [
+        "MOVPRFX",
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ],
+      [
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "MUL"
+      ],
+      [
+        "MOVPRFX",
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul_lane[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul_lane[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmul_lane[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmul_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmul_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmul_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmul_lane[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmul_lane[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmul_lane[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULH"
+      ],
+      [
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SMULH"
+      ],
+      [
+        "MOVPRFX",
+        "SMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULH"
+      ],
+      [
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulh[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UMULH"
+      ],
+      [
+        "MOVPRFX",
+        "UMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_n_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb_lane[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb_lane[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb_lane[_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullb_lane[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_n_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt_lane[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt_lane[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt_lane[_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svmullt_lane[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FMULX"
+      ],
+      [
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svmulx[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FMULX"
+      ],
+      [
+        "MOVPRFX",
+        "FMULX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnand[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NAND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "svuint16_t op3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnbsl[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NBSL"
+      ],
+      [
+        "MOVPRFX",
+        "NBSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNEG"
+      ],
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNEG"
+      ],
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNEG"
+      ],
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNEG"
+      ],
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNEG"
+      ],
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNEG"
+      ],
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s8]_m",
+    "arguments": [
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NEG"
+      ],
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svneg[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmad[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnmatch[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NMATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnmatch[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NMATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnmatch[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NMATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svnmatch[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NMATCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLA"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmla[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLA"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FNMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMLS"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmls[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H|Ztied3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "svfloat16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S|Ztied3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "svfloat32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D|Ztied3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "svfloat64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]|Ztied3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "float16_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]|Ztied3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "float32_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]|Ztied3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMSB"
+      ],
+      [
+        "FNMLS"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnmsb[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "float64_t op3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMSB"
+      ],
+      [
+        "MOVPRFX",
+        "FNMLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnor[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s8]_m",
+    "arguments": [
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u16]_m",
+    "arguments": [
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u8]_m",
+    "arguments": [
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "NOT"
+      ],
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svnot[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "NOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorn[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_b]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ],
+      [
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorr[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "ORR"
+      ],
+      [
+        "MOVPRFX",
+        "ORR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svorv[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ORV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c16",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c16_x2",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c32",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c32_x2",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c64",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c64_x2",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c8",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpext_lane_c8_x2",
+    "arguments": [
+      "svcount_t pnn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "pnn": {
+        "register": "PNreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svpfalse[_b]",
+    "arguments": [],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PFALSE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpfalse_c",
+    "arguments": [],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PFALSE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svpfirst[_b]",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ptied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PFIRST"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmul[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmul[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb[_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb_pair[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb_pair[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb_pair[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb_pair[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb_pair[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullb_pair[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt[_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt_pair[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt_pair[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt_pair[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt_pair[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt_pair[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpmullt_pair[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svpnext_b16",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ptied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PNEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svpnext_b32",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ptied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PNEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svpnext_b64",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ptied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PNEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svpnext_b8",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Ptied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PNEXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather[_u32base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather[_u32base]_offset",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather[_u64base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather[_u64base]_offset",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather_[s32]offset",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint32_t offsets",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather_[s64]offset",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint64_t offsets",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather_[u32]offset",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint32_t offsets",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_gather_[u64]offset",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint64_t offsets",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfb_vnum",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "int64_t vnum",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFB"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ],
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather[_u32base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather[_u32base]_index",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather[_u64base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather[_u64base]_index",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather_[s32]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint32_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather_[s64]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint64_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather_[u32]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint32_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_gather_[u64]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint64_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfd_vnum",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "int64_t vnum",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFD"
+      ],
+      [
+        "PRFD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ],
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather[_u32base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather[_u32base]_index",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather[_u64base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather[_u64base]_index",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather_[s32]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint32_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather_[s64]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint64_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather_[u32]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint32_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_gather_[u64]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint64_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfh_vnum",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "int64_t vnum",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFH"
+      ],
+      [
+        "PRFH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ],
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather[_u32base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather[_u32base]_index",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather[_u64base]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather[_u64base]_index",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ],
+      [
+        "PRFB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather_[s32]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint32_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather_[s64]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svint64_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather_[u32]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint32_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_gather_[u64]index",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "svuint64_t indices",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svprfw_vnum",
+    "arguments": [
+      "svbool_t pg",
+      "const void *base",
+      "int64_t vnum",
+      "enum svprfop op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PRFW"
+      ],
+      [
+        "PRFW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_b16",
+    "arguments": [
+      "svbool_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_b32",
+    "arguments": [
+      "svbool_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_b64",
+    "arguments": [
+      "svbool_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_b8",
+    "arguments": [
+      "svbool_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_c16",
+    "arguments": [
+      "svcount_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_c32",
+    "arguments": [
+      "svcount_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_c64",
+    "arguments": [
+      "svcount_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svpsel_lane_c8",
+    "arguments": [
+      "svcount_t pn",
+      "svbool_t pm",
+      "uint32_t idx"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "idx": {
+        "index": "[Wreg1, imm1]"
+      },
+      "pm": {
+        "register": "Preg3"
+      },
+      "pn": {
+        "register": "Preg2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptest_any",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "bool"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptest_first",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "bool"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptest_last",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "bool"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_b16",
+    "arguments": [],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_b32",
+    "arguments": [],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_b64",
+    "arguments": [],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_b8",
+    "arguments": [],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svptrue_c16",
+    "arguments": [],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svptrue_c32",
+    "arguments": [],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svptrue_c64",
+    "arguments": [],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svptrue_c8",
+    "arguments": [],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_pat_b16",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_pat_b32",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_pat_b64",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svptrue_pat_b8",
+    "arguments": [
+      "enum svpattern pattern"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PTRUE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s8]_m",
+    "arguments": [
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQABS"
+      ],
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqabs[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqadd[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ],
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqadd[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQADD"
+      ],
+      [
+        "MOVPRFX",
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcadd[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQCADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcadd[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQCADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcadd[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQCADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcadd[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQCADD"
+      ],
+      [
+        "MOVPRFX",
+        "SQCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcvtn_s16[_s32_x2]",
+    "arguments": [
+      "svint32x2_t zn"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "zn": {
+        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQCVTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcvtn_u16[_s32_x2]",
+    "arguments": [
+      "svint32x2_t zn"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "zn": {
+        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQCVTUN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqcvtn_u16[_u32_x2]",
+    "arguments": [
+      "svuint32x2_t zn"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "zn": {
+        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQCVTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecb_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd[_s64]",
+    "arguments": [
+      "svint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECD"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd[_u64]",
+    "arguments": [
+      "svuint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECD"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd_pat[_s64]",
+    "arguments": [
+      "svint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECD"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecd_pat[_u64]",
+    "arguments": [
+      "svuint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECD"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech[_s16]",
+    "arguments": [
+      "svint16_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECH"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech[_u16]",
+    "arguments": [
+      "svuint16_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECH"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech_pat[_s16]",
+    "arguments": [
+      "svint16_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECH"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdech_pat[_u16]",
+    "arguments": [
+      "svuint16_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECH"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s32]_b16",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s32]_b32",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s32]_b64",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s32]_b8",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s64]_b16",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s64]_b32",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s64]_b64",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_s64]_b8",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u32]_b16",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u32]_b32",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u32]_b64",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u32]_b8",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u64]_b16",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u64]_b32",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u64]_b64",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_n_u64]_b8",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_s16]",
+    "arguments": [
+      "svint16_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_s32]",
+    "arguments": [
+      "svint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_s64]",
+    "arguments": [
+      "svint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECP"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_u16]",
+    "arguments": [
+      "svuint16_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_u32]",
+    "arguments": [
+      "svuint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecp[_u64]",
+    "arguments": [
+      "svuint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECP"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw[_s32]",
+    "arguments": [
+      "svint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECW"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw[_u32]",
+    "arguments": [
+      "svuint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECW"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw_pat[_s32]",
+    "arguments": [
+      "svint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDECW"
+      ],
+      [
+        "MOVPRFX",
+        "SQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqdecw_pat[_u32]",
+    "arguments": [
+      "svuint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQDECW"
+      ],
+      [
+        "MOVPRFX",
+        "UQDECW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalb_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalbt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalbt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalbt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalbt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalbt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalbt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlalt_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLALT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLALT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslb_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLB"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslbt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslbt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslbt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslbt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslbt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslbt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLBT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmlslt_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSLT"
+      ],
+      [
+        "MOVPRFX",
+        "SQDMLSLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmulh_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb_lane[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullb_lane[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt_lane[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqdmullt_lane[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincb_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd[_s64]",
+    "arguments": [
+      "svint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCD"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd[_u64]",
+    "arguments": [
+      "svuint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCD"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd_pat[_s64]",
+    "arguments": [
+      "svint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCD"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincd_pat[_u64]",
+    "arguments": [
+      "svuint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCD"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch[_s16]",
+    "arguments": [
+      "svint16_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCH"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch[_u16]",
+    "arguments": [
+      "svuint16_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCH"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch_pat[_s16]",
+    "arguments": [
+      "svint16_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCH"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqinch_pat[_u16]",
+    "arguments": [
+      "svuint16_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCH"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s32]_b16",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s32]_b32",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s32]_b64",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s32]_b8",
+    "arguments": [
+      "int32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s64]_b16",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s64]_b32",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s64]_b64",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_s64]_b8",
+    "arguments": [
+      "int64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u32]_b16",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u32]_b32",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u32]_b64",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u32]_b8",
+    "arguments": [
+      "uint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Wtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u64]_b16",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u64]_b32",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u64]_b64",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_n_u64]_b8",
+    "arguments": [
+      "uint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Xtied"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_s16]",
+    "arguments": [
+      "svint16_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_s32]",
+    "arguments": [
+      "svint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_s64]",
+    "arguments": [
+      "svint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCP"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_u16]",
+    "arguments": [
+      "svuint16_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_u32]",
+    "arguments": [
+      "svuint32_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincp[_u64]",
+    "arguments": [
+      "svuint64_t op",
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCP"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw[_s32]",
+    "arguments": [
+      "svint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCW"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw[_u32]",
+    "arguments": [
+      "svuint32_t op",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCW"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw_pat[_n_s32]",
+    "arguments": [
+      "int32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw_pat[_n_s64]",
+    "arguments": [
+      "int64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw_pat[_n_u32]",
+    "arguments": [
+      "uint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Wtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw_pat[_n_u64]",
+    "arguments": [
+      "uint64_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Xtied"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw_pat[_s32]",
+    "arguments": [
+      "svint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQINCW"
+      ],
+      [
+        "MOVPRFX",
+        "SQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqincw_pat[_u32]",
+    "arguments": [
+      "svuint32_t op",
+      "enum svpattern pattern",
+      "uint64_t imm_factor"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_factor": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQINCW"
+      ],
+      [
+        "MOVPRFX",
+        "UQINCW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s8]_m",
+    "arguments": [
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQNEG"
+      ],
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqneg[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQNEG"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdcmlah[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDCMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDCMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdcmlah[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDCMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDCMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdcmlah[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDCMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDCMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdcmlah[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDCMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDCMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdcmlah_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDCMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDCMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdcmlah_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index",
+      "uint64_t imm_rotation"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDCMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDCMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlah_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLAH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLAH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "int16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "int32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "int64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "svint16_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "op3": {
+        "register": "Zop3.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "svint32_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmlsh_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "svint64_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMLSH"
+      ],
+      [
+        "MOVPRFX",
+        "SQRDMLSH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh_lane[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrdmulh_lane[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHL"
+      ],
+      [
+        "SQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHL"
+      ],
+      [
+        "UQRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshl[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrn[_n]_s16[_s32_x2]",
+    "arguments": [
+      "svint32x2_t zn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "zn": {
+        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrn[_n]_u16[_u32_x2]",
+    "arguments": [
+      "svuint32x2_t zn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "zn": {
+        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQRSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrun[_n]_u16[_s32_x2]",
+    "arguments": [
+      "svint32x2_t zn",
+      "uint64_t imm"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm": {
+        "immediate": "imm1"
+      },
+      "zn": {
+        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrunb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrunb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrunb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrunt[_n_s16]",
+    "arguments": [
+      "svuint8_t even",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrunt[_n_s32]",
+    "arguments": [
+      "svuint16_t even",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqrshrunt[_n_s64]",
+    "arguments": [
+      "svuint32_t even",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQRSHRUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "ASR"
+      ],
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "ASR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "LSR"
+      ],
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "LSR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ],
+      [
+        "SQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ],
+      [
+        "UQSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshl[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSHL"
+      ],
+      [
+        "MOVPRFX",
+        "UQSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHLU"
+      ],
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshlu[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSHLU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrunb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrunb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrunb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrunt[_n_s16]",
+    "arguments": [
+      "svuint8_t even",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrunt[_n_s32]",
+    "arguments": [
+      "svuint16_t even",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqshrunt[_n_s64]",
+    "arguments": [
+      "svuint32_t even",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHRUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQADD"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svqsub[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsub[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSUBR"
+      ],
+      [
+        "SQSUB"
+      ],
+      [
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSUBR"
+      ],
+      [
+        "UQSUB"
+      ],
+      [
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqsubr[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "UQSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "UQSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnb[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnb[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnb[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnb[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQXTNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnb[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQXTNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnb[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQXTNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnt[_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnt[_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnt[_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnt[_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQXTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnt[_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQXTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtnt[_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQXTNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtunb[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtunb[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtunb[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTUNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtunt[_s16]",
+    "arguments": [
+      "svuint8_t even",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtunt[_s32]",
+    "arguments": [
+      "svuint16_t even",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svqxtunt[_s64]",
+    "arguments": [
+      "svuint32_t even",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTUNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svraddhnt[_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RADDHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrax1[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RAX1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrax1[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RAX1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s8]_m",
+    "arguments": [
+      "svint8_t inactive",
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u16]_m",
+    "arguments": [
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u8]_m",
+    "arguments": [
+      "svuint8_t inactive",
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.B|Ztied.B"
+      },
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B|Ztied.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RBIT"
+      ],
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrbit[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "RBIT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrdffr",
+    "arguments": [],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDFFR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrdffr_z",
+    "arguments": [
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDFFR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpe[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpe[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpe[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrecpe[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URECPE"
+      ],
+      [
+        "MOVPRFX",
+        "URECPE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrecpe[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URECPE"
+      ],
+      [
+        "MOVPRFX",
+        "URECPE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrecpe[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URECPE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecps[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecps[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecps[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPX"
+      ],
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPX"
+      ],
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPX"
+      ],
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPX"
+      ],
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPX"
+      ],
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRECPX"
+      ],
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrecpx[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRECPX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svreinterpret[_b]",
+    "arguments": [
+      "svcount_t count"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svreinterpret[_c]",
+    "arguments": [
+      "svbool_t pg"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f16[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f32[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_f64[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s16[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s32[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s64[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_s8[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u16[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u32[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u64[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svreinterpret_u8[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_s16]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_s32]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_s64]",
+    "arguments": [
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_s8]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_u16]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_u32]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_u64]",
+    "arguments": [
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev[_u8]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev_b16",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev_b32",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev_b64",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrev_b8",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s16]_m",
+    "arguments": [
+      "svint16_t inactive",
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u16]_m",
+    "arguments": [
+      "svuint16_t inactive",
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVB"
+      ],
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevb[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f16]_m",
+    "arguments": [
+      "svfloat16_t zd",
+      "svbool_t pg",
+      "svfloat16_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f32]_m",
+    "arguments": [
+      "svfloat32_t zd",
+      "svbool_t pg",
+      "svfloat32_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f64]_m",
+    "arguments": [
+      "svfloat64_t zd",
+      "svbool_t pg",
+      "svfloat64_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t zn"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s16]_m",
+    "arguments": [
+      "svint16_t zd",
+      "svbool_t pg",
+      "svint16_t zn"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t zn"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t zn"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s32]_m",
+    "arguments": [
+      "svint32_t zd",
+      "svbool_t pg",
+      "svint32_t zn"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t zn"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t zn"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s64]_m",
+    "arguments": [
+      "svint64_t zd",
+      "svbool_t pg",
+      "svint64_t zn"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t zn"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t zn"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s8]_m",
+    "arguments": [
+      "svint8_t zd",
+      "svbool_t pg",
+      "svint8_t zn"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t zn"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t zn"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u16]_m",
+    "arguments": [
+      "svuint16_t zd",
+      "svbool_t pg",
+      "svuint16_t zn"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t zn"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t zn"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u32]_m",
+    "arguments": [
+      "svuint32_t zd",
+      "svbool_t pg",
+      "svuint32_t zn"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t zn"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t zn"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u64]_m",
+    "arguments": [
+      "svuint64_t zd",
+      "svbool_t pg",
+      "svuint64_t zn"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t zn"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t zn"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u8]_m",
+    "arguments": [
+      "svuint8_t zd",
+      "svbool_t pg",
+      "svuint8_t zn"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zd": {
+        "register": "Zreg1.Q"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t zn"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOV",
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrevd[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t zn"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "pg": {
+        "register": "Preg1"
+      },
+      "zn": {
+        "register": "Zreg2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_s32]_m",
+    "arguments": [
+      "svint32_t inactive",
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVH"
+      ],
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevh[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevw[_s64]_m",
+    "arguments": [
+      "svint64_t inactive",
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVW"
+      ],
+      [
+        "MOVPRFX",
+        "REVW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevw[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVW"
+      ],
+      [
+        "MOVPRFX",
+        "REVW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevw[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevw[_u64]_m",
+    "arguments": [
+      "svuint64_t inactive",
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVW"
+      ],
+      [
+        "MOVPRFX",
+        "REVW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevw[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "REVW"
+      ],
+      [
+        "MOVPRFX",
+        "REVW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrevw[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "REVW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRHADD"
+      ],
+      [
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ],
+      [
+        "MOVPRFX",
+        "SRHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URHADD"
+      ],
+      [
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrhadd[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URHADD"
+      ],
+      [
+        "MOVPRFX",
+        "URHADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTA"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTA"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTA"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTA"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTA"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTA"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinta[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTI"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTI"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTI"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTI"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTI"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTI"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrinti[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTM"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTM"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTM"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTM"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTM"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTM"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintm[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTM"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTN"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTN"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTN"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTN"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTN"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTN"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintn[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTP"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTP"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTP"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTP"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTP"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTP"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintp[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTX"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTX"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTX"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTX"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTX"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTX"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintx[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTZ"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTZ"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTZ"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTZ"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTZ"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRINTZ"
+      ],
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrintz[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FRINTZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "SRSHR"
+      ],
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LSL"
+      ],
+      [
+        "URSHR"
+      ],
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "LSL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHL"
+      ],
+      [
+        "SRSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHL"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHL"
+      ],
+      [
+        "URSHLR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshl[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHL"
+      ],
+      [
+        "MOVPRFX",
+        "URSHLR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSHR"
+      ],
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SRSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSHR"
+      ],
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshr[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSHR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrshrnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrsqrte[_f16]",
+    "arguments": [
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRSQRTE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrsqrte[_f32]",
+    "arguments": [
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRSQRTE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrsqrte[_f64]",
+    "arguments": [
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRSQRTE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsqrte[_u32]_m",
+    "arguments": [
+      "svuint32_t inactive",
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSQRTE"
+      ],
+      [
+        "MOVPRFX",
+        "URSQRTE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsqrte[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSQRTE"
+      ],
+      [
+        "MOVPRFX",
+        "URSQRTE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsqrte[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "URSQRTE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrsqrts[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRSQRTS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrsqrts[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRSQRTS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svrsqrts[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FRSQRTS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SRSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SRSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SRSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SRSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSRA"
+      ],
+      [
+        "MOVPRFX",
+        "URSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSRA"
+      ],
+      [
+        "MOVPRFX",
+        "URSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSRA"
+      ],
+      [
+        "MOVPRFX",
+        "URSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsra[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "URSRA"
+      ],
+      [
+        "MOVPRFX",
+        "URSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svrsubhnt[_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RSUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLB"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLB"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLB"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLB"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclt[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLT"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclt[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLT"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclt[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "svuint32_t op3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "op3": {
+        "register": "Zop3.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLT"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsbclt[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "svuint64_t op3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "op3": {
+        "register": "Zop3.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SBCLT"
+      ],
+      [
+        "MOVPRFX",
+        "SBCLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ],
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svscale[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_b]",
+    "arguments": [
+      "svbool_t pg",
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsel[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svset2[_b]",
+    "arguments": [
+      "svboolx2_t tuple",
+      "uint64_t imm_index",
+      "svbool_t x"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_f16]",
+    "arguments": [
+      "svfloat16x2_t tuple",
+      "uint64_t imm_index",
+      "svfloat16_t x"
+    ],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_f32]",
+    "arguments": [
+      "svfloat32x2_t tuple",
+      "uint64_t imm_index",
+      "svfloat32_t x"
+    ],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_f64]",
+    "arguments": [
+      "svfloat64x2_t tuple",
+      "uint64_t imm_index",
+      "svfloat64_t x"
+    ],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_s16]",
+    "arguments": [
+      "svint16x2_t tuple",
+      "uint64_t imm_index",
+      "svint16_t x"
+    ],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_s32]",
+    "arguments": [
+      "svint32x2_t tuple",
+      "uint64_t imm_index",
+      "svint32_t x"
+    ],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_s64]",
+    "arguments": [
+      "svint64x2_t tuple",
+      "uint64_t imm_index",
+      "svint64_t x"
+    ],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_s8]",
+    "arguments": [
+      "svint8x2_t tuple",
+      "uint64_t imm_index",
+      "svint8_t x"
+    ],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_u16]",
+    "arguments": [
+      "svuint16x2_t tuple",
+      "uint64_t imm_index",
+      "svuint16_t x"
+    ],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_u32]",
+    "arguments": [
+      "svuint32x2_t tuple",
+      "uint64_t imm_index",
+      "svuint32_t x"
+    ],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_u64]",
+    "arguments": [
+      "svuint64x2_t tuple",
+      "uint64_t imm_index",
+      "svuint64_t x"
+    ],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset2[_u8]",
+    "arguments": [
+      "svuint8x2_t tuple",
+      "uint64_t imm_index",
+      "svuint8_t x"
+    ],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_f16]",
+    "arguments": [
+      "svfloat16x3_t tuple",
+      "uint64_t imm_index",
+      "svfloat16_t x"
+    ],
+    "return_type": {
+      "value": "svfloat16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_f32]",
+    "arguments": [
+      "svfloat32x3_t tuple",
+      "uint64_t imm_index",
+      "svfloat32_t x"
+    ],
+    "return_type": {
+      "value": "svfloat32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_f64]",
+    "arguments": [
+      "svfloat64x3_t tuple",
+      "uint64_t imm_index",
+      "svfloat64_t x"
+    ],
+    "return_type": {
+      "value": "svfloat64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_s16]",
+    "arguments": [
+      "svint16x3_t tuple",
+      "uint64_t imm_index",
+      "svint16_t x"
+    ],
+    "return_type": {
+      "value": "svint16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_s32]",
+    "arguments": [
+      "svint32x3_t tuple",
+      "uint64_t imm_index",
+      "svint32_t x"
+    ],
+    "return_type": {
+      "value": "svint32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_s64]",
+    "arguments": [
+      "svint64x3_t tuple",
+      "uint64_t imm_index",
+      "svint64_t x"
+    ],
+    "return_type": {
+      "value": "svint64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_s8]",
+    "arguments": [
+      "svint8x3_t tuple",
+      "uint64_t imm_index",
+      "svint8_t x"
+    ],
+    "return_type": {
+      "value": "svint8x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_u16]",
+    "arguments": [
+      "svuint16x3_t tuple",
+      "uint64_t imm_index",
+      "svuint16_t x"
+    ],
+    "return_type": {
+      "value": "svuint16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_u32]",
+    "arguments": [
+      "svuint32x3_t tuple",
+      "uint64_t imm_index",
+      "svuint32_t x"
+    ],
+    "return_type": {
+      "value": "svuint32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_u64]",
+    "arguments": [
+      "svuint64x3_t tuple",
+      "uint64_t imm_index",
+      "svuint64_t x"
+    ],
+    "return_type": {
+      "value": "svuint64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset3[_u8]",
+    "arguments": [
+      "svuint8x3_t tuple",
+      "uint64_t imm_index",
+      "svuint8_t x"
+    ],
+    "return_type": {
+      "value": "svuint8x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svset4[_b]",
+    "arguments": [
+      "svboolx4_t tuple",
+      "uint64_t imm_index",
+      "svbool_t x"
+    ],
+    "return_type": {
+      "value": "svboolx4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_f16]",
+    "arguments": [
+      "svfloat16x4_t tuple",
+      "uint64_t imm_index",
+      "svfloat16_t x"
+    ],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_f32]",
+    "arguments": [
+      "svfloat32x4_t tuple",
+      "uint64_t imm_index",
+      "svfloat32_t x"
+    ],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_f64]",
+    "arguments": [
+      "svfloat64x4_t tuple",
+      "uint64_t imm_index",
+      "svfloat64_t x"
+    ],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_s16]",
+    "arguments": [
+      "svint16x4_t tuple",
+      "uint64_t imm_index",
+      "svint16_t x"
+    ],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_s32]",
+    "arguments": [
+      "svint32x4_t tuple",
+      "uint64_t imm_index",
+      "svint32_t x"
+    ],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_s64]",
+    "arguments": [
+      "svint64x4_t tuple",
+      "uint64_t imm_index",
+      "svint64_t x"
+    ],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_s8]",
+    "arguments": [
+      "svint8x4_t tuple",
+      "uint64_t imm_index",
+      "svint8_t x"
+    ],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_u16]",
+    "arguments": [
+      "svuint16x4_t tuple",
+      "uint64_t imm_index",
+      "svuint16_t x"
+    ],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_u32]",
+    "arguments": [
+      "svuint32x4_t tuple",
+      "uint64_t imm_index",
+      "svuint32_t x"
+    ],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_u64]",
+    "arguments": [
+      "svuint64x4_t tuple",
+      "uint64_t imm_index",
+      "svuint64_t x"
+    ],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svset4[_u8]",
+    "arguments": [
+      "svuint8x4_t tuple",
+      "uint64_t imm_index",
+      "svuint8_t x"
+    ],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsetffr",
+    "arguments": [],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {},
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SETFFR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllb[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllb[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllb[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllb[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllb[_n_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllb[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllt[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllt[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllt[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllt[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllt[_n_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshllt[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USHLLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svshrnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t imm2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "imm2": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SHRNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 31
+      },
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 63
+      },
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsli[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SLI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsm4e[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SM4E"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsm4ekey[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SM4EKEY"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsplice[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SPLICE"
+      ],
+      [
+        "MOVPRFX",
+        "SPLICE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ],
+      [
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USQADD"
+      ],
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsqadd[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "USQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f16]_m",
+    "arguments": [
+      "svfloat16_t inactive",
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.H|Ztied.H"
+      },
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSQRT"
+      ],
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H|Ztied.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSQRT"
+      ],
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f32]_m",
+    "arguments": [
+      "svfloat32_t inactive",
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.S|Ztied.S"
+      },
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSQRT"
+      ],
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S|Ztied.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSQRT"
+      ],
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f64]_m",
+    "arguments": [
+      "svfloat64_t inactive",
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "inactive": {
+        "register": "Zinactive.D|Ztied.D"
+      },
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSQRT"
+      ],
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D|Ztied.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSQRT"
+      ],
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsqrt[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSQRT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSRA"
+      ],
+      [
+        "MOVPRFX",
+        "SSRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USRA"
+      ],
+      [
+        "MOVPRFX",
+        "USRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USRA"
+      ],
+      [
+        "MOVPRFX",
+        "USRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USRA"
+      ],
+      [
+        "MOVPRFX",
+        "USRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsra[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USRA"
+      ],
+      [
+        "MOVPRFX",
+        "USRA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsri[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SRI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "svfloat16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_f16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "svfloat16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_f16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "svfloat16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_f32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "svfloat32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_f32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "svfloat32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_f64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "svfloat64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_f64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "svfloat64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "svint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "svint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "svint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "svint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "svint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "svint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "svint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_s8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "svint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "svuint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "svuint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "svuint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "svuint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "svuint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "svuint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "svuint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1[_u8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "svuint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base]_index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base]_index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base]_index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base]_offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base]_offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base]_offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u32base_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base]_index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base]_index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base]_index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base]_offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s32]index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svint32_t indices",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32_t indices",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svint32_t indices",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svint32_t offsets",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svint64_t indices",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svint64_t offsets",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u32]index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svuint32_t indices",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint32_t indices",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32_t indices",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svuint32_t offsets",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svuint64_t indices",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svuint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svuint64_t offsets",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "int64_t vnum",
+      "svfloat16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_f16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "int64_t vnum",
+      "svfloat16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_f16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "int64_t vnum",
+      "svfloat16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "int64_t vnum",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_f32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "int64_t vnum",
+      "svfloat32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_f32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "int64_t vnum",
+      "svfloat32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "int64_t vnum",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_f64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "int64_t vnum",
+      "svfloat64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_f64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "int64_t vnum",
+      "svfloat64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "int64_t vnum",
+      "svint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "int64_t vnum",
+      "svint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "int64_t vnum",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "int64_t vnum",
+      "svint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "int64_t vnum",
+      "svint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "int64_t vnum",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "int64_t vnum",
+      "svint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "int64_t vnum",
+      "svint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "int64_t vnum",
+      "svint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_s8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "int64_t vnum",
+      "svint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "int64_t vnum",
+      "svuint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "int64_t vnum",
+      "svuint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "int64_t vnum",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "int64_t vnum",
+      "svuint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "int64_t vnum",
+      "svuint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "int64_t vnum",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1D"
+      ],
+      [
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "int64_t vnum",
+      "svuint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "int64_t vnum",
+      "svuint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "int64_t vnum",
+      "svuint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svst1_vnum[_u8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "int64_t vnum",
+      "svuint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u32base]_offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u32base]_offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u32base_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u32base_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[s32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[s32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svuint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1b_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1B"
+      ],
+      [
+        "ST1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u32base]_index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u32base]_index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u32base]_offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u32base]_offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u32base_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u32base_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u64base]_index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u64base]_index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint32_t indices",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svint32_t indices",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u32]index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint32_t indices",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u32]index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint32_t indices",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1h_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1H"
+      ],
+      [
+        "ST1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter[_u64base]_index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter[_u64base]_index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "int64_t vnum",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst1w_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "int64_t vnum",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST1W"
+      ],
+      [
+        "ST1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "svfloat16x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2H"
+      ],
+      [
+        "ST2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svfloat32x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2W"
+      ],
+      [
+        "ST2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svfloat64x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2D"
+      ],
+      [
+        "ST2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint16x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2H"
+      ],
+      [
+        "ST2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2W"
+      ],
+      [
+        "ST2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2D"
+      ],
+      [
+        "ST2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint8x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B, Zdata1.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2B"
+      ],
+      [
+        "ST2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint16x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2H"
+      ],
+      [
+        "ST2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2W"
+      ],
+      [
+        "ST2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2D"
+      ],
+      [
+        "ST2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint8x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B, Zdata1.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2B"
+      ],
+      [
+        "ST2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "int64_t vnum",
+      "svfloat16x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2H"
+      ],
+      [
+        "ST2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "int64_t vnum",
+      "svfloat32x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2W"
+      ],
+      [
+        "ST2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "int64_t vnum",
+      "svfloat64x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2D"
+      ],
+      [
+        "ST2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint16x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2H"
+      ],
+      [
+        "ST2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "int64_t vnum",
+      "svint32x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2W"
+      ],
+      [
+        "ST2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "int64_t vnum",
+      "svint64x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2D"
+      ],
+      [
+        "ST2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint8x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B, Zdata1.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2B"
+      ],
+      [
+        "ST2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint16x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2H"
+      ],
+      [
+        "ST2H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "int64_t vnum",
+      "svuint32x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2W"
+      ],
+      [
+        "ST2W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "int64_t vnum",
+      "svuint64x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2D"
+      ],
+      [
+        "ST2D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst2_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint8x2_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B, Zdata1.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST2B"
+      ],
+      [
+        "ST2B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "svfloat16x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata2.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3H"
+      ],
+      [
+        "ST3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svfloat32x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata2.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3W"
+      ],
+      [
+        "ST3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svfloat64x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata2.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3D"
+      ],
+      [
+        "ST3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint16x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata2.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3H"
+      ],
+      [
+        "ST3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata2.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3W"
+      ],
+      [
+        "ST3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata2.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3D"
+      ],
+      [
+        "ST3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint8x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata2.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3B"
+      ],
+      [
+        "ST3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint16x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata2.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3H"
+      ],
+      [
+        "ST3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata2.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3W"
+      ],
+      [
+        "ST3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata2.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3D"
+      ],
+      [
+        "ST3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint8x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata2.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3B"
+      ],
+      [
+        "ST3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "int64_t vnum",
+      "svfloat16x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata2.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3H"
+      ],
+      [
+        "ST3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "int64_t vnum",
+      "svfloat32x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata2.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3W"
+      ],
+      [
+        "ST3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "int64_t vnum",
+      "svfloat64x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata2.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3D"
+      ],
+      [
+        "ST3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint16x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata2.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3H"
+      ],
+      [
+        "ST3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "int64_t vnum",
+      "svint32x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata2.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3W"
+      ],
+      [
+        "ST3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "int64_t vnum",
+      "svint64x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata2.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3D"
+      ],
+      [
+        "ST3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint8x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata2.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3B"
+      ],
+      [
+        "ST3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint16x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata2.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3H"
+      ],
+      [
+        "ST3H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "int64_t vnum",
+      "svuint32x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata2.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3W"
+      ],
+      [
+        "ST3W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "int64_t vnum",
+      "svuint64x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata2.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3D"
+      ],
+      [
+        "ST3D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst3_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint8x3_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata2.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST3B"
+      ],
+      [
+        "ST3B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "svfloat16x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata3.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4H"
+      ],
+      [
+        "ST4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svfloat32x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata3.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4W"
+      ],
+      [
+        "ST4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svfloat64x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata3.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4D"
+      ],
+      [
+        "ST4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint16x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata3.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4H"
+      ],
+      [
+        "ST4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata3.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4W"
+      ],
+      [
+        "ST4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata3.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4D"
+      ],
+      [
+        "ST4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint8x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata3.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4B"
+      ],
+      [
+        "ST4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint16x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata3.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4H"
+      ],
+      [
+        "ST4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata3.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4W"
+      ],
+      [
+        "ST4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata3.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4D"
+      ],
+      [
+        "ST4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint8x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata3.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4B"
+      ],
+      [
+        "ST4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "int64_t vnum",
+      "svfloat16x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata3.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4H"
+      ],
+      [
+        "ST4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "int64_t vnum",
+      "svfloat32x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata3.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4W"
+      ],
+      [
+        "ST4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "int64_t vnum",
+      "svfloat64x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata3.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4D"
+      ],
+      [
+        "ST4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint16x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata3.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4H"
+      ],
+      [
+        "ST4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "int64_t vnum",
+      "svint32x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata3.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4W"
+      ],
+      [
+        "ST4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "int64_t vnum",
+      "svint64x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata3.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4D"
+      ],
+      [
+        "ST4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint8x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata3.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4B"
+      ],
+      [
+        "ST4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint16x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.H - Zdata3.H}"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4H"
+      ],
+      [
+        "ST4H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "int64_t vnum",
+      "svuint32x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.S - Zdata3.S}"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4W"
+      ],
+      [
+        "ST4W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "int64_t vnum",
+      "svuint64x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.D - Zdata3.D}"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4D"
+      ],
+      [
+        "ST4D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svst4_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint8x4_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "{Zdata0.B - Zdata3.B}"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ST4B"
+      ],
+      [
+        "ST4B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "svfloat16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ],
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_f16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "svfloat16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_f16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "svfloat16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ],
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_f32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "svfloat32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_f32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "svfloat32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ],
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_f64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "svfloat64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_f64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "svfloat64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ],
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "svint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "svint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ],
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "svint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "svint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ],
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "svint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "svint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ],
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "svint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_s8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "svint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ],
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "svuint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "svuint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ],
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "svuint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "svuint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ],
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "svuint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "svuint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ],
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "svuint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1[_u8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "svuint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base]_index[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base]_index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base]_index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base]_offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base]_offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base]_offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u32base_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base]_index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base]_index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base]_index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 8": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base]_offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[s64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svint64_t indices",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[s64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svint64_t offsets",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u32]offset[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "svuint32_t offsets",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u64]index[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svuint64_t indices",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svuint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 8": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u64]offset[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "svuint64_t offsets",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_f16]",
+    "arguments": [
+      "svbool_t pg",
+      "float16_t *base",
+      "int64_t vnum",
+      "svfloat16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ],
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_f16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "int64_t vnum",
+      "svfloat16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_f16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float16_t * rn",
+      "int64_t vnum",
+      "svfloat16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_f32]",
+    "arguments": [
+      "svbool_t pg",
+      "float32_t *base",
+      "int64_t vnum",
+      "svfloat32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ],
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_f32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "int64_t vnum",
+      "svfloat32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_f32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float32_t * rn",
+      "int64_t vnum",
+      "svfloat32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_f64]",
+    "arguments": [
+      "svbool_t pg",
+      "float64_t *base",
+      "int64_t vnum",
+      "svfloat64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ],
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_f64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "int64_t vnum",
+      "svfloat64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_f64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "float64_t * rn",
+      "int64_t vnum",
+      "svfloat64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_s16]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "int64_t vnum",
+      "svint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ],
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "int64_t vnum",
+      "svint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int16_t * rn",
+      "int64_t vnum",
+      "svint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "int64_t vnum",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ],
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "int64_t vnum",
+      "svint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int32_t * rn",
+      "int64_t vnum",
+      "svint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int64_t *base",
+      "int64_t vnum",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ],
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "int64_t vnum",
+      "svint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int64_t * rn",
+      "int64_t vnum",
+      "svint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_s8]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "int64_t vnum",
+      "svint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ],
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "int64_t vnum",
+      "svint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_s8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "int8_t * rn",
+      "int64_t vnum",
+      "svint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_u16]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "int64_t vnum",
+      "svuint16_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      },
+      "vnum * svcnth()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ],
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u16_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "int64_t vnum",
+      "svuint16x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u16_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint16_t * rn",
+      "int64_t vnum",
+      "svuint16x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "int64_t vnum",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      },
+      "vnum * svcntw()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ],
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u32_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "int64_t vnum",
+      "svuint32x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u32_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint32_t * rn",
+      "int64_t vnum",
+      "svuint32x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint64_t *base",
+      "int64_t vnum",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      },
+      "vnum * svcntd()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1D"
+      ],
+      [
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u64_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "int64_t vnum",
+      "svuint64x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u64_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint64_t * rn",
+      "int64_t vnum",
+      "svuint64x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1D"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svstnt1_vnum[_u8]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "int64_t vnum",
+      "svuint8_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      },
+      "vnum * svcntb()": {
+        "register": "Xindex"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ],
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u8_x2]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "int64_t vnum",
+      "svuint8x2_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1_vnum[_u8_x4]",
+    "arguments": [
+      "svcount_t png",
+      "uint8_t * rn",
+      "int64_t vnum",
+      "svuint8x4_t zt"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "png": {
+        "register": "PNreg1"
+      },
+      "rn": {
+        "register": "Xreg2"
+      },
+      "vnum": {
+        "register": "Xreg3"
+      },
+      "zt": {
+        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "RDVL",
+        "MADD",
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u32base]_offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u32base]_offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u32base_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u32base_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svuint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int8_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1b_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint8_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1B"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u32base]_index[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u32base]_index[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t index",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u32base]_offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u32base]_offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "int64_t offset",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u32base_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u32base_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t bases",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.S"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u64base]_index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u64base]_index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 2": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[u32]offset[_s32]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint32_t offsets",
+      "svint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[u32]offset[_u32]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint32_t offsets",
+      "svuint32_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.S"
+      },
+      "offsets": {
+        "register": "Zoffsets.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 2": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int16_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1h_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint16_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1H"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter[_u64base]_index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter[_u64base]_index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t index",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "index * 4": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter[_u64base]_offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter[_u64base]_offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "int64_t offset",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offset": {
+        "register": "Xoffset"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter[_u64base_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter[_u64base_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t bases",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "bases": {
+        "register": "Zbases.D"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[s64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[s64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[s64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[s64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[u64]index[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint64_t indices",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[u64]index[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint64_t indices",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices * 4": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[u64]offset[_s64]",
+    "arguments": [
+      "svbool_t pg",
+      "int32_t *base",
+      "svuint64_t offsets",
+      "svint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svstnt1w_scatter_[u64]offset[_u64]",
+    "arguments": [
+      "svbool_t pg",
+      "uint32_t *base",
+      "svuint64_t offsets",
+      "svuint64_t data"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "base": {
+        "register": "Xbase"
+      },
+      "data": {
+        "register": "Zdata.D"
+      },
+      "offsets": {
+        "register": "Zoffsets.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STNT1W"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUB"
+      ],
+      [
+        "FADD"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FADD"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "ADD"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsub[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUB"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_n_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_n_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_n_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_n_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_n_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_n_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_s16]",
+    "arguments": [
+      "svint8_t even",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_s32]",
+    "arguments": [
+      "svint16_t even",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_s64]",
+    "arguments": [
+      "svint32_t even",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_u16]",
+    "arguments": [
+      "svuint8_t even",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.B"
+      },
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_u32]",
+    "arguments": [
+      "svuint16_t even",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.H"
+      },
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubhnt[_u64]",
+    "arguments": [
+      "svuint32_t even",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "even": {
+        "register": "Ztied.S"
+      },
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBHNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_n_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublb[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublbt[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublbt[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublbt[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublbt[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublbt[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublbt[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLBT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_n_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_n_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_n_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_u16]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_u32]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsublt[_u64]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubltb[_n_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubltb[_n_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubltb[_n_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubltb[_s16]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubltb[_s32]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubltb[_s64]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBLTB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat16_t op1",
+      "float16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat32_t op1",
+      "float32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUBR"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "FSUB"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_f64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svfloat64_t op1",
+      "float64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUBR"
+      ],
+      [
+        "MOVPRFX",
+        "FSUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]|Ztied2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]|Ztied2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]|Ztied2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]|Ztied2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_n_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUBR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUBR"
+      ],
+      [
+        "SUB"
+      ],
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsubr[_u8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUBR"
+      ],
+      [
+        "MOVPRFX",
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwb[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "int8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "int16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SSUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svsubwt[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USUBWT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsudot[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "uint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USDOT"
+      ],
+      [
+        "MOVPRFX",
+        "USDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsudot[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "svuint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USDOT"
+      ],
+      [
+        "MOVPRFX",
+        "USDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svsudot_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint8_t op2",
+      "svuint8_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUDOT"
+      ],
+      [
+        "MOVPRFX",
+        "SUDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_f16]",
+    "arguments": [
+      "svfloat16x2_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_f32]",
+    "arguments": [
+      "svfloat32x2_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_f64]",
+    "arguments": [
+      "svfloat64x2_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_s16]",
+    "arguments": [
+      "svint16x2_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_s32]",
+    "arguments": [
+      "svint32x2_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_s64]",
+    "arguments": [
+      "svint64x2_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_s8]",
+    "arguments": [
+      "svint8x2_t data",
+      "svuint8_t indices"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.B, Zdata1.B}"
+      },
+      "indices": {
+        "register": "Zindices.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_u16]",
+    "arguments": [
+      "svuint16x2_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.H, Zdata1.H}"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_u32]",
+    "arguments": [
+      "svuint32x2_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.S, Zdata1.S}"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_u64]",
+    "arguments": [
+      "svuint64x2_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.D, Zdata1.D}"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbl2[_u8]",
+    "arguments": [
+      "svuint8x2_t data",
+      "svuint8_t indices"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "{Zdata0.B, Zdata1.B}"
+      },
+      "indices": {
+        "register": "Zindices.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_f16]",
+    "arguments": [
+      "svfloat16_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_f32]",
+    "arguments": [
+      "svfloat32_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_f64]",
+    "arguments": [
+      "svfloat64_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_s16]",
+    "arguments": [
+      "svint16_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_s32]",
+    "arguments": [
+      "svint32_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_s64]",
+    "arguments": [
+      "svint64_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_s8]",
+    "arguments": [
+      "svint8_t data",
+      "svuint8_t indices"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.B"
+      },
+      "indices": {
+        "register": "Zindices.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_u16]",
+    "arguments": [
+      "svuint16_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_u32]",
+    "arguments": [
+      "svuint32_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_u64]",
+    "arguments": [
+      "svuint64_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtbl[_u8]",
+    "arguments": [
+      "svuint8_t data",
+      "svuint8_t indices"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.B"
+      },
+      "indices": {
+        "register": "Zindices.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_f16]",
+    "arguments": [
+      "svfloat16_t fallback",
+      "svfloat16_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Ztied.H"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_f32]",
+    "arguments": [
+      "svfloat32_t fallback",
+      "svfloat32_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Ztied.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_f64]",
+    "arguments": [
+      "svfloat64_t fallback",
+      "svfloat64_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Ztied.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_s16]",
+    "arguments": [
+      "svint16_t fallback",
+      "svint16_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Ztied.H"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_s32]",
+    "arguments": [
+      "svint32_t fallback",
+      "svint32_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Ztied.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_s64]",
+    "arguments": [
+      "svint64_t fallback",
+      "svint64_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Ztied.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_s8]",
+    "arguments": [
+      "svint8_t fallback",
+      "svint8_t data",
+      "svuint8_t indices"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Ztied.B"
+      },
+      "indices": {
+        "register": "Zindices.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_u16]",
+    "arguments": [
+      "svuint16_t fallback",
+      "svuint16_t data",
+      "svuint16_t indices"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.H"
+      },
+      "fallback": {
+        "register": "Ztied.H"
+      },
+      "indices": {
+        "register": "Zindices.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_u32]",
+    "arguments": [
+      "svuint32_t fallback",
+      "svuint32_t data",
+      "svuint32_t indices"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.S"
+      },
+      "fallback": {
+        "register": "Ztied.S"
+      },
+      "indices": {
+        "register": "Zindices.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_u64]",
+    "arguments": [
+      "svuint64_t fallback",
+      "svuint64_t data",
+      "svuint64_t indices"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.D"
+      },
+      "fallback": {
+        "register": "Ztied.D"
+      },
+      "indices": {
+        "register": "Zindices.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svtbx[_u8]",
+    "arguments": [
+      "svuint8_t fallback",
+      "svuint8_t data",
+      "svuint8_t indices"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Zdata.B"
+      },
+      "fallback": {
+        "register": "Ztied.B"
+      },
+      "indices": {
+        "register": "Zindices.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TBX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtmad[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FTMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtmad[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FTMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtmad[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTMAD"
+      ],
+      [
+        "MOVPRFX",
+        "FTMAD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1_b16",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.H"
+      },
+      "op2": {
+        "register": "Pop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1_b32",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.S"
+      },
+      "op2": {
+        "register": "Pop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1_b64",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.D"
+      },
+      "op2": {
+        "register": "Pop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1_b8",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn1q[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2_b16",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.H"
+      },
+      "op2": {
+        "register": "Pop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2_b32",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.S"
+      },
+      "op2": {
+        "register": "Pop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2_b64",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.D"
+      },
+      "op2": {
+        "register": "Pop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2_b8",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtrn2q[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtsmul[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTSMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtsmul[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTSMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtsmul[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTSMUL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtssel[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTSSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtssel[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTSSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svtssel[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FTSSEL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svundef2_b",
+    "arguments": [],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_f16",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_f32",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_f64",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_s16",
+    "arguments": [],
+    "return_type": {
+      "value": "svint16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_s32",
+    "arguments": [],
+    "return_type": {
+      "value": "svint32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_s64",
+    "arguments": [],
+    "return_type": {
+      "value": "svint64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_s8",
+    "arguments": [],
+    "return_type": {
+      "value": "svint8x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_u16",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint16x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_u32",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint32x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_u64",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint64x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef2_u8",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint8x2_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_f16",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_f32",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_f64",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_s16",
+    "arguments": [],
+    "return_type": {
+      "value": "svint16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_s32",
+    "arguments": [],
+    "return_type": {
+      "value": "svint32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_s64",
+    "arguments": [],
+    "return_type": {
+      "value": "svint64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_s8",
+    "arguments": [],
+    "return_type": {
+      "value": "svint8x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_u16",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint16x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_u32",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint32x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_u64",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint64x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef3_u8",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint8x3_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svundef4_b",
+    "arguments": [],
+    "return_type": {
+      "value": "svboolx4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_f16",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_f32",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_f64",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_s16",
+    "arguments": [],
+    "return_type": {
+      "value": "svint16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_s32",
+    "arguments": [],
+    "return_type": {
+      "value": "svint32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_s64",
+    "arguments": [],
+    "return_type": {
+      "value": "svint64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_s8",
+    "arguments": [],
+    "return_type": {
+      "value": "svint8x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_u16",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint16x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_u32",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint32x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_u64",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint64x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef4_u8",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint8x4_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_f16",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_f32",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_f64",
+    "arguments": [],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_s16",
+    "arguments": [],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_s32",
+    "arguments": [],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_s64",
+    "arguments": [],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_s8",
+    "arguments": [],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_u16",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_u32",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_u64",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svundef_u8",
+    "arguments": [],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Architectures": [
+      "A64"
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_b]",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_s16]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_s32]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_s64]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_u16]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_u32]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpkhi[_u64]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UUNPKHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_b]",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "PUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_s16]",
+    "arguments": [
+      "svint8_t op"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_s32]",
+    "arguments": [
+      "svint16_t op"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_s64]",
+    "arguments": [
+      "svint32_t op"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_u16]",
+    "arguments": [
+      "svuint8_t op"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_u32]",
+    "arguments": [
+      "svuint16_t op"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svunpklo[_u64]",
+    "arguments": [
+      "svuint32_t op"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Zop.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UUNPKLO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "uint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H[*]"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S[*]"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D[*]"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQADD"
+      ],
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_n_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "uint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B[*]"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s16]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s16]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s16]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      },
+      "pg": {
+        "register": "Pg.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s32]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s32]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s32]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      },
+      "pg": {
+        "register": "Pg.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s64]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s64]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s64]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      },
+      "pg": {
+        "register": "Pg.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s8]_m",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s8]_x",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ],
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svuqadd[_s8]_z",
+    "arguments": [
+      "svbool_t pg",
+      "svint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "pg": {
+        "register": "Pg.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "MOVPRFX",
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svusdot[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svuint8_t op2",
+      "int8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B[*]"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USDOT"
+      ],
+      [
+        "MOVPRFX",
+        "USDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svusdot[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svuint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USDOT"
+      ],
+      [
+        "MOVPRFX",
+        "USDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svusdot_lane[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svuint8_t op2",
+      "svint8_t op3",
+      "uint64_t imm_index"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm_index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USDOT"
+      ],
+      [
+        "MOVPRFX",
+        "USDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svusmmla[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svuint8_t op2",
+      "svint8_t op3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      },
+      "op3": {
+        "register": "Zop3.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "USMMLA"
+      ],
+      [
+        "MOVPRFX",
+        "USMMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1_b16",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.H"
+      },
+      "op2": {
+        "register": "Pop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1_b32",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.S"
+      },
+      "op2": {
+        "register": "Pop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1_b64",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.D"
+      },
+      "op2": {
+        "register": "Pop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1_b8",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp1q[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2_b16",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.H"
+      },
+      "op2": {
+        "register": "Pop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2_b32",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.S"
+      },
+      "op2": {
+        "register": "Pop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2_b64",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.D"
+      },
+      "op2": {
+        "register": "Pop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2_b8",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svuzp2q[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UZP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b16[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b16[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b16[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b16[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b16[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b16[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b32[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b32[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b32[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b32[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b32[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b32[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b64[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b64[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b64[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b64[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b64[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b64[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b8[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b8[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b8[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b8[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b8[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_b8[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c16[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c16[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c32[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c32[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c64[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c64[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c8[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilege_c8[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b16[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b16[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b16[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b16[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b16[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b16[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b32[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b32[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b32[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b32[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b32[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b32[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b64[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b64[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b64[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b64[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b64[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b64[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b8[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b8[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b8[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b8[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b8[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_b8[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c16[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c16[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c32[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c32[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c64[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c64[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c8[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilegt_c8[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b16[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b16[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b16[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b16[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b16[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b16[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b32[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b32[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b32[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b32[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b32[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b32[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b64[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b64[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b64[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b64[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b64[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b64[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b8[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b8[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b8[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b8[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b8[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_b8[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c16[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c16[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c32[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c32[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c64[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c64[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c8[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilele_c8[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b16[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b16[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b16[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b16[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b16[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b16[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b32[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b32[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b32[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b32[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b32[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b32[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b64[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b64[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_s32]",
+    "arguments": [
+      "int32_t op1",
+      "int32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_s64]",
+    "arguments": [
+      "int64_t op1",
+      "int64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b8[_s64]_x2",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_u32]",
+    "arguments": [
+      "uint32_t op1",
+      "uint32_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Wop1"
+      },
+      "op2": {
+        "register": "Wop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_u64]",
+    "arguments": [
+      "uint64_t op1",
+      "uint64_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_b8[_u64]_x2",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm"
+    ],
+    "return_type": {
+      "value": "svboolx2_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c16[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c16[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c32[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c32[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c64[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c64[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c8[_s64]",
+    "arguments": [
+      "int64_t rn",
+      "int64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilelt_c8[_u64]",
+    "arguments": [
+      "uint64_t rn",
+      "uint64_t rm",
+      "uint64_t vl"
+    ],
+    "return_type": {
+      "value": "svcount_t"
+    },
+    "Arguments_Preparation": {
+      "rm": {
+        "register": "Xreg2"
+      },
+      "rn": {
+        "register": "Xreg1"
+      },
+      "vl": {
+        "immediate": "<VL>"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILELO"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_f16]",
+    "arguments": [
+      "const float16_t *op1",
+      "const float16_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_f32]",
+    "arguments": [
+      "const float32_t *op1",
+      "const float32_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_f64]",
+    "arguments": [
+      "const float64_t *op1",
+      "const float64_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_s16]",
+    "arguments": [
+      "const int16_t *op1",
+      "const int16_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_s32]",
+    "arguments": [
+      "const int32_t *op1",
+      "const int32_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_s64]",
+    "arguments": [
+      "const int64_t *op1",
+      "const int64_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_s8]",
+    "arguments": [
+      "const int8_t *op1",
+      "const int8_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_u16]",
+    "arguments": [
+      "const uint16_t *op1",
+      "const uint16_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_u32]",
+    "arguments": [
+      "const uint32_t *op1",
+      "const uint32_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_u64]",
+    "arguments": [
+      "const uint64_t *op1",
+      "const uint64_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilerw[_u8]",
+    "arguments": [
+      "const uint8_t *op1",
+      "const uint8_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILERW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_f16]",
+    "arguments": [
+      "const float16_t *op1",
+      "const float16_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_f32]",
+    "arguments": [
+      "const float32_t *op1",
+      "const float32_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_f64]",
+    "arguments": [
+      "const float64_t *op1",
+      "const float64_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_s16]",
+    "arguments": [
+      "const int16_t *op1",
+      "const int16_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_s32]",
+    "arguments": [
+      "const int32_t *op1",
+      "const int32_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_s64]",
+    "arguments": [
+      "const int64_t *op1",
+      "const int64_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_s8]",
+    "arguments": [
+      "const int8_t *op1",
+      "const int8_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_u16]",
+    "arguments": [
+      "const uint16_t *op1",
+      "const uint16_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_u32]",
+    "arguments": [
+      "const uint32_t *op1",
+      "const uint32_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_u64]",
+    "arguments": [
+      "const uint64_t *op1",
+      "const uint64_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svwhilewr[_u8]",
+    "arguments": [
+      "const uint8_t *op1",
+      "const uint8_t *op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Xop1"
+      },
+      "op2": {
+        "register": "Xop2"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WHILEWR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svwrffr",
+    "arguments": [
+      "svbool_t op"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "op": {
+        "register": "Pop.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "WRFFR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "op1": {
+        "register": "Zop1.H|Ztied1.H"
+      },
+      "op2": {
+        "register": "Zop2.H|Ztied2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "op1": {
+        "register": "Zop1.S|Ztied1.S"
+      },
+      "op2": {
+        "register": "Zop2.S|Ztied2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 64
+      },
+      "op1": {
+        "register": "Zop1.D|Ztied1.D"
+      },
+      "op2": {
+        "register": "Zop2.D|Ztied2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE2",
+    "name": "svxar[_n_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2",
+      "uint64_t imm3"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "imm3": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "op1": {
+        "register": "Zop1.B|Ztied1.B"
+      },
+      "op2": {
+        "register": "Zop2.B|Ztied2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ],
+      [
+        "XAR"
+      ],
+      [
+        "MOVPRFX",
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1_b16",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.H"
+      },
+      "op2": {
+        "register": "Pop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1_b32",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.S"
+      },
+      "op2": {
+        "register": "Pop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1_b64",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.D"
+      },
+      "op2": {
+        "register": "Pop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1_b8",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip1q[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.H"
+      },
+      "op2": {
+        "register": "Zop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.S"
+      },
+      "op2": {
+        "register": "Zop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.D"
+      },
+      "op2": {
+        "register": "Zop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.B"
+      },
+      "op2": {
+        "register": "Zop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2_b16",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.H"
+      },
+      "op2": {
+        "register": "Pop2.H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2_b32",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.S"
+      },
+      "op2": {
+        "register": "Pop2.S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2_b64",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.D"
+      },
+      "op2": {
+        "register": "Pop2.D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2_b8",
+    "arguments": [
+      "svbool_t op1",
+      "svbool_t op2"
+    ],
+    "return_type": {
+      "value": "svbool_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Pop1.B"
+      },
+      "op2": {
+        "register": "Pop2.B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_f16]",
+    "arguments": [
+      "svfloat16_t op1",
+      "svfloat16_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_f32]",
+    "arguments": [
+      "svfloat32_t op1",
+      "svfloat32_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_f64]",
+    "arguments": [
+      "svfloat64_t op1",
+      "svfloat64_t op2"
+    ],
+    "return_type": {
+      "value": "svfloat64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_s16]",
+    "arguments": [
+      "svint16_t op1",
+      "svint16_t op2"
+    ],
+    "return_type": {
+      "value": "svint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_s32]",
+    "arguments": [
+      "svint32_t op1",
+      "svint32_t op2"
+    ],
+    "return_type": {
+      "value": "svint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_s64]",
+    "arguments": [
+      "svint64_t op1",
+      "svint64_t op2"
+    ],
+    "return_type": {
+      "value": "svint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_s8]",
+    "arguments": [
+      "svint8_t op1",
+      "svint8_t op2"
+    ],
+    "return_type": {
+      "value": "svint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_u16]",
+    "arguments": [
+      "svuint16_t op1",
+      "svuint16_t op2"
+    ],
+    "return_type": {
+      "value": "svuint16_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_u32]",
+    "arguments": [
+      "svuint32_t op1",
+      "svuint32_t op2"
+    ],
+    "return_type": {
+      "value": "svuint32_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_u64]",
+    "arguments": [
+      "svuint64_t op1",
+      "svuint64_t op2"
+    ],
+    "return_type": {
+      "value": "svuint64_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "SVE",
+    "name": "svzip2q[_u8]",
+    "arguments": [
+      "svuint8_t op1",
+      "svuint8_t op2"
+    ],
+    "return_type": {
+      "value": "svuint8_t"
+    },
+    "Arguments_Preparation": {
+      "op1": {
+        "register": "Zop1.Q"
+      },
+      "op2": {
+        "register": "Zop2.Q"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaba_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaba_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaba_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b",
+      "int8x8_t c"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaba_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "uint16x4_t c"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaba_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "uint32x2_t c"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaba_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "uint8x8_t c"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_high_s16",
+    "arguments": [
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABAL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_high_s32",
+    "arguments": [
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t c"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABAL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_high_s8",
+    "arguments": [
+      "int16x8_t a",
+      "int8x16_t b",
+      "int8x16_t c"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABAL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_high_u16",
+    "arguments": [
+      "uint32x4_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABAL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_high_u32",
+    "arguments": [
+      "uint64x2_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABAL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_high_u8",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABAL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_s16",
+    "arguments": [
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABAL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_s32",
+    "arguments": [
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABAL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_s8",
+    "arguments": [
+      "int16x8_t a",
+      "int8x8_t b",
+      "int8x8_t c"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABAL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_u16",
+    "arguments": [
+      "uint32x4_t a",
+      "uint16x4_t b",
+      "uint16x4_t c"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABAL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_u32",
+    "arguments": [
+      "uint64x2_t a",
+      "uint32x2_t b",
+      "uint32x2_t c"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABAL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabal_u8",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x8_t b",
+      "uint8x8_t c"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABAL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabaq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabaq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabaq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b",
+      "int8x16_t c"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabaq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabaq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabaq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabd_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdd_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_high_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_high_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_high_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_high_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_high_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_high_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdl_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabdq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabds_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabs_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsd_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsh_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vabsq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ABS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "poly16x4_t b"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_p64",
+    "arguments": [
+      "poly64x1_t a",
+      "poly64x1_t b"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_p8",
+    "arguments": [
+      "poly8x8_t a",
+      "poly8x8_t b"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vadd_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddd_s64",
+    "arguments": [
+      "int64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddd_u64",
+    "arguments": [
+      "uint64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_high_s16",
+    "arguments": [
+      "int8x8_t r",
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_high_s32",
+    "arguments": [
+      "int16x4_t r",
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_high_s64",
+    "arguments": [
+      "int32x2_t r",
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_high_u16",
+    "arguments": [
+      "uint8x8_t r",
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_high_u32",
+    "arguments": [
+      "uint16x4_t r",
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_high_u64",
+    "arguments": [
+      "uint32x2_t r",
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddhn_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDHN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_high_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_high_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_high_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_high_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_high_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_high_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddl_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlv_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlv_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDLP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlv_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlv_u16",
+    "arguments": [
+      "uint16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlv_u32",
+    "arguments": [
+      "uint32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDLP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlv_u8",
+    "arguments": [
+      "uint8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlvq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlvq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlvq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlvq_u16",
+    "arguments": [
+      "uint16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlvq_u32",
+    "arguments": [
+      "uint32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddlvq_u8",
+    "arguments": [
+      "uint8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDLV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_p128",
+    "arguments": [
+      "poly128_t a",
+      "poly128_t b"
+    ],
+    "return_type": {
+      "value": "poly128_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_p16",
+    "arguments": [
+      "poly16x8_t a",
+      "poly16x8_t b"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_p64",
+    "arguments": [
+      "poly64x2_t a",
+      "poly64x2_t b"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "poly8x16_t b"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_u16",
+    "arguments": [
+      "uint16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_u32",
+    "arguments": [
+      "uint32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddv_u8",
+    "arguments": [
+      "uint8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADDP",
+        "FADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_u16",
+    "arguments": [
+      "uint16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_u32",
+    "arguments": [
+      "uint32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_u64",
+    "arguments": [
+      "uint64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddvq_u8",
+    "arguments": [
+      "uint8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ADDV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_high_s16",
+    "arguments": [
+      "int32x4_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDW2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_high_s32",
+    "arguments": [
+      "int64x2_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDW2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_high_s8",
+    "arguments": [
+      "int16x8_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDW2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_high_u16",
+    "arguments": [
+      "uint32x4_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDW2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_high_u32",
+    "arguments": [
+      "uint64x2_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDW2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_high_u8",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDW2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_s16",
+    "arguments": [
+      "int32x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_s32",
+    "arguments": [
+      "int64x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_s8",
+    "arguments": [
+      "int16x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SADDW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_u16",
+    "arguments": [
+      "uint32x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_u32",
+    "arguments": [
+      "uint64x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaddw_u8",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UADDW"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaesdq_u8",
+    "arguments": [
+      "uint8x16_t data",
+      "uint8x16_t key"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Vd.16B"
+      },
+      "key": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AESD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaeseq_u8",
+    "arguments": [
+      "uint8x16_t data",
+      "uint8x16_t key"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Vd.16B"
+      },
+      "key": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AESE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaesimcq_u8",
+    "arguments": [
+      "uint8x16_t data"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AESIMC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaesmcq_u8",
+    "arguments": [
+      "uint8x16_t data"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "data": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AESMC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamax_f16",
+    "arguments": [
+      "float16x4_t vn",
+      "float16x4_t vm"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.4H"
+      },
+      "vn": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamax_f32",
+    "arguments": [
+      "float32x2_t vn",
+      "float32x2_t vm"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.2S"
+      },
+      "vn": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamaxq_f16",
+    "arguments": [
+      "float16x8_t vn",
+      "float16x8_t vm"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.8H"
+      },
+      "vn": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamaxq_f32",
+    "arguments": [
+      "float32x4_t vn",
+      "float32x4_t vm"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.4S"
+      },
+      "vn": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamaxq_f64",
+    "arguments": [
+      "float64x2_t vn",
+      "float64x2_t vm"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.2D"
+      },
+      "vn": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamin_f16",
+    "arguments": [
+      "float16x4_t vn",
+      "float16x4_t vm"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.4H"
+      },
+      "vn": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamin_f32",
+    "arguments": [
+      "float32x2_t vn",
+      "float32x2_t vm"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.2S"
+      },
+      "vn": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaminq_f16",
+    "arguments": [
+      "float16x8_t vn",
+      "float16x8_t vm"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.8H"
+      },
+      "vn": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaminq_f32",
+    "arguments": [
+      "float32x4_t vn",
+      "float32x4_t vm"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.4S"
+      },
+      "vn": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaminq_f64",
+    "arguments": [
+      "float64x2_t vn",
+      "float64x2_t vm"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "vm": {
+        "register": "Vm.2D"
+      },
+      "vn": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vand_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vandq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "AND"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b",
+      "int64x2_t c"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b",
+      "int8x16_t c"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "uint64x2_t c"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbcaxq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BCAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbic_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbicq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BIC"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_f16",
+    "arguments": [
+      "uint16x4_t a",
+      "float16x4_t b",
+      "float16x4_t c"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_f32",
+    "arguments": [
+      "uint32x2_t a",
+      "float32x2_t b",
+      "float32x2_t c"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_f64",
+    "arguments": [
+      "uint64x1_t a",
+      "float64x1_t b",
+      "float64x1_t c"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_p16",
+    "arguments": [
+      "uint16x4_t a",
+      "poly16x4_t b",
+      "poly16x4_t c"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_p64",
+    "arguments": [
+      "poly64x1_t a",
+      "poly64x1_t b",
+      "poly64x1_t c"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_p8",
+    "arguments": [
+      "uint8x8_t a",
+      "poly8x8_t b",
+      "poly8x8_t c"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_s16",
+    "arguments": [
+      "uint16x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_s32",
+    "arguments": [
+      "uint32x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_s64",
+    "arguments": [
+      "uint64x1_t a",
+      "int64x1_t b",
+      "int64x1_t c"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_s8",
+    "arguments": [
+      "uint8x8_t a",
+      "int8x8_t b",
+      "int8x8_t c"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "uint16x4_t c"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "uint32x2_t c"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b",
+      "uint64x1_t c"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbsl_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "uint8x8_t c"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_f16",
+    "arguments": [
+      "uint16x8_t a",
+      "float16x8_t b",
+      "float16x8_t c"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_f32",
+    "arguments": [
+      "uint32x4_t a",
+      "float32x4_t b",
+      "float32x4_t c"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_f64",
+    "arguments": [
+      "uint64x2_t a",
+      "float64x2_t b",
+      "float64x2_t c"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_p16",
+    "arguments": [
+      "uint16x8_t a",
+      "poly16x8_t b",
+      "poly16x8_t c"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_p64",
+    "arguments": [
+      "poly64x2_t a",
+      "poly64x2_t b",
+      "poly64x2_t c"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_p8",
+    "arguments": [
+      "uint8x16_t a",
+      "poly8x16_t b",
+      "poly8x16_t c"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_s16",
+    "arguments": [
+      "uint16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_s32",
+    "arguments": [
+      "uint32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_s64",
+    "arguments": [
+      "uint64x2_t a",
+      "int64x2_t b",
+      "int64x2_t c"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_s8",
+    "arguments": [
+      "uint8x16_t a",
+      "int8x16_t b",
+      "int8x16_t c"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "uint64x2_t c"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vbslq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "BSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcadd_rot270_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcadd_rot270_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcadd_rot90_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcadd_rot90_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaddq_rot270_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaddq_rot270_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaddq_rot270_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaddq_rot90_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaddq_rot90_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaddq_rot90_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcage_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcage_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcage_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaged_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcageh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcageq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcageq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcageq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcages_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagt_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagt_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagt_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagtd_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagth_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagtq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagtq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagtq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcagts_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcale_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcale_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcale_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaled_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaleh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaleq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaleq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaleq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcales_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcalt_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcalt_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcalt_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaltd_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcalth_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaltq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaltq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcaltq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcalts_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FACGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_p64",
+    "arguments": [
+      "poly64x1_t a",
+      "poly64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_p8",
+    "arguments": [
+      "poly8x8_t a",
+      "poly8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceq_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqd_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqd_s64",
+    "arguments": [
+      "int64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqd_u64",
+    "arguments": [
+      "uint64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_p64",
+    "arguments": [
+      "poly64x2_t a",
+      "poly64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "poly8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqs_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_p64",
+    "arguments": [
+      "poly64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_p8",
+    "arguments": [
+      "poly8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_u16",
+    "arguments": [
+      "uint16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_u32",
+    "arguments": [
+      "uint32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_u64",
+    "arguments": [
+      "uint64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqz_u8",
+    "arguments": [
+      "uint8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzd_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzd_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzd_u64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzh_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_p64",
+    "arguments": [
+      "poly64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_p8",
+    "arguments": [
+      "poly8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_u16",
+    "arguments": [
+      "uint16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_u32",
+    "arguments": [
+      "uint32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_u64",
+    "arguments": [
+      "uint64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzq_u8",
+    "arguments": [
+      "uint8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vceqzs_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMEQ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcge_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcged_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcged_s64",
+    "arguments": [
+      "int64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcged_u64",
+    "arguments": [
+      "uint64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgeq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcges_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgez_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezd_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezd_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezh_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgezs_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgt_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtd_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtd_s64",
+    "arguments": [
+      "int64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtd_u64",
+    "arguments": [
+      "uint64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgth_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgts_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtz_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzd_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzd_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzh_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcgtzs_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcle_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcled_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcled_s64",
+    "arguments": [
+      "int64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcled_u64",
+    "arguments": [
+      "uint64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcleq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcles_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclez_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezd_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezd_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezh_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclezs_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcls_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcls_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcls_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcls_u16",
+    "arguments": [
+      "uint16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcls_u32",
+    "arguments": [
+      "uint32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcls_u8",
+    "arguments": [
+      "uint8x8_t a"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclsq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclsq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclsq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclsq_u16",
+    "arguments": [
+      "uint16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclsq_u32",
+    "arguments": [
+      "uint32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclsq_u8",
+    "arguments": [
+      "uint8x16_t a"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclt_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltd_f64",
+    "arguments": [
+      "float64_t a",
+      "float64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltd_s64",
+    "arguments": [
+      "int64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltd_u64",
+    "arguments": [
+      "uint64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclth_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMHI"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclts_f32",
+    "arguments": [
+      "float32_t a",
+      "float32_t b"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMGT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltz_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzd_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzd_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzh_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcltzs_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclz_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclz_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclz_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclz_u16",
+    "arguments": [
+      "uint16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclz_u32",
+    "arguments": [
+      "uint32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclz_u8",
+    "arguments": [
+      "uint8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclzq_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclzq_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclzq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclzq_u16",
+    "arguments": [
+      "uint16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclzq_u32",
+    "arguments": [
+      "uint32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vclzq_u8",
+    "arguments": [
+      "uint8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CLZ"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_lane_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_lane_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_laneq_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_laneq_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        ""
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot180_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot180_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot180_lane_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot180_lane_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot180_laneq_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot180_laneq_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        ""
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot270_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot270_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot270_lane_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot270_lane_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot270_laneq_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot270_laneq_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        ""
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot90_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot90_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot90_lane_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot90_lane_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot90_laneq_f16",
+    "arguments": [
+      "float16x4_t r",
+      "float16x4_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmla_rot90_laneq_f32",
+    "arguments": [
+      "float32x2_t r",
+      "float32x2_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        ""
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_f64",
+    "arguments": [
+      "float64x2_t r",
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_lane_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_lane_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_laneq_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_laneq_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_f64",
+    "arguments": [
+      "float64x2_t r",
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_lane_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_lane_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_laneq_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot180_laneq_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_f64",
+    "arguments": [
+      "float64x2_t r",
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_lane_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_lane_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_laneq_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot270_laneq_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_f64",
+    "arguments": [
+      "float64x2_t r",
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_lane_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_lane_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x2_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_laneq_f16",
+    "arguments": [
+      "float16x8_t r",
+      "float16x8_t a",
+      "float16x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcmlaq_rot90_laneq_f32",
+    "arguments": [
+      "float32x4_t r",
+      "float32x4_t a",
+      "float32x4_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCMLA"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcnt_p8",
+    "arguments": [
+      "poly8x8_t a"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcnt_s8",
+    "arguments": [
+      "int8x8_t a"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcnt_u8",
+    "arguments": [
+      "uint8x8_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcntq_p8",
+    "arguments": [
+      "poly8x16_t a"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcntq_s8",
+    "arguments": [
+      "int8x16_t a"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcntq_u8",
+    "arguments": [
+      "uint8x16_t a"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CNT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_f16",
+    "arguments": [
+      "float16x4_t low",
+      "float16x4_t high"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.4H"
+      },
+      "low": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_f32",
+    "arguments": [
+      "float32x2_t low",
+      "float32x2_t high"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.2S"
+      },
+      "low": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_f64",
+    "arguments": [
+      "float64x1_t low",
+      "float64x1_t high"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.1D"
+      },
+      "low": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_p16",
+    "arguments": [
+      "poly16x4_t low",
+      "poly16x4_t high"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.4H"
+      },
+      "low": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_p64",
+    "arguments": [
+      "poly64x1_t low",
+      "poly64x1_t high"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.1D"
+      },
+      "low": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_p8",
+    "arguments": [
+      "poly8x8_t low",
+      "poly8x8_t high"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.8B"
+      },
+      "low": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_s16",
+    "arguments": [
+      "int16x4_t low",
+      "int16x4_t high"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.4H"
+      },
+      "low": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_s32",
+    "arguments": [
+      "int32x2_t low",
+      "int32x2_t high"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.2S"
+      },
+      "low": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_s64",
+    "arguments": [
+      "int64x1_t low",
+      "int64x1_t high"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.1D"
+      },
+      "low": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_s8",
+    "arguments": [
+      "int8x8_t low",
+      "int8x8_t high"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.8B"
+      },
+      "low": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_u16",
+    "arguments": [
+      "uint16x4_t low",
+      "uint16x4_t high"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.4H"
+      },
+      "low": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_u32",
+    "arguments": [
+      "uint32x2_t low",
+      "uint32x2_t high"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.2S"
+      },
+      "low": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_u64",
+    "arguments": [
+      "uint64x1_t low",
+      "uint64x1_t high"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.1D"
+      },
+      "low": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcombine_u8",
+    "arguments": [
+      "uint8x8_t low",
+      "uint8x8_t high"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "high": {
+        "register": "Vm.8B"
+      },
+      "low": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP",
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_f32",
+    "arguments": [
+      "float32x2_t a",
+      "const int lane1",
+      "float32x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_f64",
+    "arguments": [
+      "float64x1_t a",
+      "const int lane1",
+      "float64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "const int lane1",
+      "poly16x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_p64",
+    "arguments": [
+      "poly64x1_t a",
+      "const int lane1",
+      "poly64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_p8",
+    "arguments": [
+      "poly8x8_t a",
+      "const int lane1",
+      "poly8x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_s16",
+    "arguments": [
+      "int16x4_t a",
+      "const int lane1",
+      "int16x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_s32",
+    "arguments": [
+      "int32x2_t a",
+      "const int lane1",
+      "int32x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_s64",
+    "arguments": [
+      "int64x1_t a",
+      "const int lane1",
+      "int64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_s8",
+    "arguments": [
+      "int8x8_t a",
+      "const int lane1",
+      "int8x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "const int lane1",
+      "uint16x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "const int lane1",
+      "uint32x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "const int lane1",
+      "uint64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_lane_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "const int lane1",
+      "uint8x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_f32",
+    "arguments": [
+      "float32x2_t a",
+      "const int lane1",
+      "float32x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_f64",
+    "arguments": [
+      "float64x1_t a",
+      "const int lane1",
+      "float64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "const int lane1",
+      "poly16x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_p64",
+    "arguments": [
+      "poly64x1_t a",
+      "const int lane1",
+      "poly64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_p8",
+    "arguments": [
+      "poly8x8_t a",
+      "const int lane1",
+      "poly8x16_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_s16",
+    "arguments": [
+      "int16x4_t a",
+      "const int lane1",
+      "int16x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_s32",
+    "arguments": [
+      "int32x2_t a",
+      "const int lane1",
+      "int32x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_s64",
+    "arguments": [
+      "int64x1_t a",
+      "const int lane1",
+      "int64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_s8",
+    "arguments": [
+      "int8x8_t a",
+      "const int lane1",
+      "int8x16_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "const int lane1",
+      "uint16x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "const int lane1",
+      "uint32x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "const int lane1",
+      "uint64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "UNUSED"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopy_laneq_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "const int lane1",
+      "uint8x16_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_f32",
+    "arguments": [
+      "float32x4_t a",
+      "const int lane1",
+      "float32x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_f64",
+    "arguments": [
+      "float64x2_t a",
+      "const int lane1",
+      "float64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_p16",
+    "arguments": [
+      "poly16x8_t a",
+      "const int lane1",
+      "poly16x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_p64",
+    "arguments": [
+      "poly64x2_t a",
+      "const int lane1",
+      "poly64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "const int lane1",
+      "poly8x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_s16",
+    "arguments": [
+      "int16x8_t a",
+      "const int lane1",
+      "int16x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_s32",
+    "arguments": [
+      "int32x4_t a",
+      "const int lane1",
+      "int32x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_s64",
+    "arguments": [
+      "int64x2_t a",
+      "const int lane1",
+      "int64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_s8",
+    "arguments": [
+      "int8x16_t a",
+      "const int lane1",
+      "int8x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "const int lane1",
+      "uint16x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "const int lane1",
+      "uint32x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "const int lane1",
+      "uint64x1_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.1D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_lane_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "const int lane1",
+      "uint8x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "const int lane1",
+      "float32x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "const int lane1",
+      "float64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_p16",
+    "arguments": [
+      "poly16x8_t a",
+      "const int lane1",
+      "poly16x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_p64",
+    "arguments": [
+      "poly64x2_t a",
+      "const int lane1",
+      "poly64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "const int lane1",
+      "poly8x16_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "const int lane1",
+      "int16x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "const int lane1",
+      "int32x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "const int lane1",
+      "int64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "const int lane1",
+      "int8x16_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "const int lane1",
+      "uint16x8_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "const int lane1",
+      "uint32x4_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "const int lane1",
+      "uint64x2_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcopyq_laneq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "const int lane1",
+      "uint8x16_t b",
+      "const int lane2"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "lane1": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "lane2": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_f16",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_f32",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_f64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_p16",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_p64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_p8",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_s16",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_s32",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_s64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_s8",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_u16",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_u32",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_u64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcreate_u8",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Xn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f16_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f16_s16",
+    "arguments": [
+      "int16x4_t a"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f16_u16",
+    "arguments": [
+      "uint16x4_t a"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f32_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f32_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f32_s32",
+    "arguments": [
+      "int32x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f32_u32",
+    "arguments": [
+      "uint32x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f64_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f64_s64",
+    "arguments": [
+      "int64x1_t a"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_f64_u64",
+    "arguments": [
+      "uint64x1_t a"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_high_f16_f32",
+    "arguments": [
+      "float16x4_t r",
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_high_f32_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_high_f32_f64",
+    "arguments": [
+      "float32x2_t r",
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_high_f64_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTL2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_f16_s16",
+    "arguments": [
+      "int16x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_f16_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_f32_s32",
+    "arguments": [
+      "int32x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_f32_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_f64_s64",
+    "arguments": [
+      "int64x1_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_f64_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_s16_f16",
+    "arguments": [
+      "float16x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_s32_f32",
+    "arguments": [
+      "float32x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_s64_f64",
+    "arguments": [
+      "float64x1_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_u16_f16",
+    "arguments": [
+      "float16x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_u32_f32",
+    "arguments": [
+      "float32x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_n_u64_f64",
+    "arguments": [
+      "float64x1_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_s16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_s32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_s64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_u16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_u32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvt_u64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvta_s16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvta_s32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvta_s64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvta_u16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvta_u32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvta_u64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtad_s64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtad_u64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtah_s16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtah_s32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtah_s64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtah_u16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtah_u32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtah_u64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtaq_s16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtaq_s32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtaq_s64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtaq_u16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtaq_u32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtaq_u64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtas_s32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtas_u32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_f64_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_f64_u64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_n_f64_s64",
+    "arguments": [
+      "int64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_n_f64_u64",
+    "arguments": [
+      "uint64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_n_s64_f64",
+    "arguments": [
+      "float64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_n_u64_f64",
+    "arguments": [
+      "float64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_s64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_u64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_f16_s16",
+    "arguments": [
+      "int16_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_f16_s32",
+    "arguments": [
+      "int32_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_f16_s64",
+    "arguments": [
+      "int64_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_f16_u16",
+    "arguments": [
+      "uint16_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_f16_u32",
+    "arguments": [
+      "uint32_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_f16_u64",
+    "arguments": [
+      "uint64_t a"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_f16_s16",
+    "arguments": [
+      "int16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_f16_s32",
+    "arguments": [
+      "int32_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_f16_s64",
+    "arguments": [
+      "int64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_f16_u16",
+    "arguments": [
+      "uint16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_f16_u32",
+    "arguments": [
+      "uint32_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_f16_u64",
+    "arguments": [
+      "uint64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_s16_f16",
+    "arguments": [
+      "float16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_s32_f16",
+    "arguments": [
+      "float16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_s64_f16",
+    "arguments": [
+      "float16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_u16_f16",
+    "arguments": [
+      "float16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_u32_f16",
+    "arguments": [
+      "float16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_n_u64_f16",
+    "arguments": [
+      "float16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_s16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_s32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_s64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_u16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_u32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvth_u64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtm_s16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtm_s32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtm_s64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtm_u16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtm_u32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtm_u64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmd_s64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmd_u64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmh_s16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmh_s32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmh_s64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmh_u16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmh_u32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmh_u64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmq_s16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmq_s32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmq_s64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmq_u16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmq_u32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmq_u64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtms_s32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtms_u32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtn_s16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtn_s32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtn_s64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtn_u16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtn_u32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtn_u64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnd_s64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnd_u64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnh_s16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnh_s32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnh_s64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnh_u16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnh_u32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnh_u64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnq_s16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnq_s32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnq_s64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnq_u16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnq_u32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnq_u64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtns_s32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtns_u32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtp_s16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtp_s32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtp_s64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtp_u16_f16",
+    "arguments": [
+      "float16x4_t a"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtp_u32_f32",
+    "arguments": [
+      "float32x2_t a"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtp_u64_f64",
+    "arguments": [
+      "float64x1_t a"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpd_s64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpd_u64_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtph_s16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtph_s32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtph_s64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtph_u16_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtph_u32_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtph_u64_f16",
+    "arguments": [
+      "float16_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpq_s16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpq_s32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpq_s64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpq_u16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpq_u32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpq_u64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtps_s32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtps_u32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_f16_s16",
+    "arguments": [
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_f16_u16",
+    "arguments": [
+      "uint16x8_t a"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_f32_s32",
+    "arguments": [
+      "int32x4_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_f32_u32",
+    "arguments": [
+      "uint32x4_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_f64_s64",
+    "arguments": [
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_f64_u64",
+    "arguments": [
+      "uint64x2_t a"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_f16_s16",
+    "arguments": [
+      "int16x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_f16_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_f32_s32",
+    "arguments": [
+      "int32x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_f32_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_f64_s64",
+    "arguments": [
+      "int64x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_f64_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_s16_f16",
+    "arguments": [
+      "float16x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_s32_f32",
+    "arguments": [
+      "float32x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_s64_f64",
+    "arguments": [
+      "float64x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_u16_f16",
+    "arguments": [
+      "float16x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_u32_f32",
+    "arguments": [
+      "float32x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_n_u64_f64",
+    "arguments": [
+      "float64x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_s16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_s32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_s64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_u16_f16",
+    "arguments": [
+      "float16x8_t a"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_u32_f32",
+    "arguments": [
+      "float32x4_t a"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtq_u64_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_f32_s32",
+    "arguments": [
+      "int32_t a"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_f32_u32",
+    "arguments": [
+      "uint32_t a"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_n_f32_s32",
+    "arguments": [
+      "int32_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_n_f32_u32",
+    "arguments": [
+      "uint32_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UCVTF"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_n_s32_f32",
+    "arguments": [
+      "float32_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_n_u32_f32",
+    "arguments": [
+      "float32_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_s32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_u32_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtx_f32_f64",
+    "arguments": [
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTXN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtx_high_f32_f64",
+    "arguments": [
+      "float32x2_t r",
+      "float64x2_t a"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTXN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtxd_f32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTXN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdiv_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdiv_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdiv_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdivh_f16",
+    "arguments": [
+      "float16_t a",
+      "float16_t b"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdivq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdivq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "float32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdivq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "float64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FDIV"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdot_lane_s32",
+    "arguments": [
+      "int32x2_t r",
+      "int8x8_t a",
+      "int8x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdot_lane_u32",
+    "arguments": [
+      "uint32x2_t r",
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdot_laneq_s32",
+    "arguments": [
+      "int32x2_t r",
+      "int8x8_t a",
+      "int8x16_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdot_laneq_u32",
+    "arguments": [
+      "uint32x2_t r",
+      "uint8x8_t a",
+      "uint8x16_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdot_s32",
+    "arguments": [
+      "int32x2_t r",
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdot_u32",
+    "arguments": [
+      "uint32x2_t r",
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "r": {
+        "register": "Vd.2S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdotq_lane_s32",
+    "arguments": [
+      "int32x4_t r",
+      "int8x16_t a",
+      "int8x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdotq_lane_u32",
+    "arguments": [
+      "uint32x4_t r",
+      "uint8x16_t a",
+      "uint8x8_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdotq_laneq_s32",
+    "arguments": [
+      "int32x4_t r",
+      "int8x16_t a",
+      "int8x16_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdotq_laneq_u32",
+    "arguments": [
+      "uint32x4_t r",
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdotq_s32",
+    "arguments": [
+      "int32x4_t r",
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdotq_u32",
+    "arguments": [
+      "uint32x4_t r",
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "r": {
+        "register": "Vd.4S"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UDOT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_f16",
+    "arguments": [
+      "float16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_f32",
+    "arguments": [
+      "float32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_f64",
+    "arguments": [
+      "float64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_p16",
+    "arguments": [
+      "poly16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_p64",
+    "arguments": [
+      "poly64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_p8",
+    "arguments": [
+      "poly8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_s16",
+    "arguments": [
+      "int16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_s32",
+    "arguments": [
+      "int32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_s64",
+    "arguments": [
+      "int64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_s8",
+    "arguments": [
+      "int8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_u16",
+    "arguments": [
+      "uint16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_u32",
+    "arguments": [
+      "uint32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_u64",
+    "arguments": [
+      "uint64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_lane_u8",
+    "arguments": [
+      "uint8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_f16",
+    "arguments": [
+      "float16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_f32",
+    "arguments": [
+      "float32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_f64",
+    "arguments": [
+      "float64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_p16",
+    "arguments": [
+      "poly16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_p64",
+    "arguments": [
+      "poly64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_p8",
+    "arguments": [
+      "poly8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_s16",
+    "arguments": [
+      "int16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_s32",
+    "arguments": [
+      "int32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_s64",
+    "arguments": [
+      "int64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_s8",
+    "arguments": [
+      "int8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_u16",
+    "arguments": [
+      "uint16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_u32",
+    "arguments": [
+      "uint32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_u64",
+    "arguments": [
+      "uint64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_laneq_u8",
+    "arguments": [
+      "uint8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_f16",
+    "arguments": [
+      "float16_t value"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_f32",
+    "arguments": [
+      "float32_t value"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_f64",
+    "arguments": [
+      "float64_t value"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_p16",
+    "arguments": [
+      "poly16_t value"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_p64",
+    "arguments": [
+      "poly64_t value"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_p8",
+    "arguments": [
+      "poly8_t value"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_s16",
+    "arguments": [
+      "int16_t value"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_s32",
+    "arguments": [
+      "int32_t value"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_s64",
+    "arguments": [
+      "int64_t value"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_s8",
+    "arguments": [
+      "int8_t value"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_u16",
+    "arguments": [
+      "uint16_t value"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_u32",
+    "arguments": [
+      "uint32_t value"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_u64",
+    "arguments": [
+      "uint64_t value"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "INS"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdup_n_u8",
+    "arguments": [
+      "uint8_t value"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupb_lane_p8",
+    "arguments": [
+      "poly8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupb_lane_s8",
+    "arguments": [
+      "int8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupb_lane_u8",
+    "arguments": [
+      "uint8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupb_laneq_p8",
+    "arguments": [
+      "poly8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupb_laneq_s8",
+    "arguments": [
+      "int8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupb_laneq_u8",
+    "arguments": [
+      "uint8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupd_lane_f64",
+    "arguments": [
+      "float64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupd_lane_s64",
+    "arguments": [
+      "int64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupd_lane_u64",
+    "arguments": [
+      "uint64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupd_laneq_f64",
+    "arguments": [
+      "float64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupd_laneq_s64",
+    "arguments": [
+      "int64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupd_laneq_u64",
+    "arguments": [
+      "uint64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_lane_f16",
+    "arguments": [
+      "float16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_lane_p16",
+    "arguments": [
+      "poly16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_lane_s16",
+    "arguments": [
+      "int16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_lane_u16",
+    "arguments": [
+      "uint16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_laneq_f16",
+    "arguments": [
+      "float16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_laneq_p16",
+    "arguments": [
+      "poly16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_laneq_s16",
+    "arguments": [
+      "int16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vduph_laneq_u16",
+    "arguments": [
+      "uint16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_f16",
+    "arguments": [
+      "float16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_f32",
+    "arguments": [
+      "float32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_f64",
+    "arguments": [
+      "float64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_p16",
+    "arguments": [
+      "poly16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_p64",
+    "arguments": [
+      "poly64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_p8",
+    "arguments": [
+      "poly8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_s16",
+    "arguments": [
+      "int16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_s32",
+    "arguments": [
+      "int32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_s64",
+    "arguments": [
+      "int64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_s8",
+    "arguments": [
+      "int8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_u16",
+    "arguments": [
+      "uint16x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_u32",
+    "arguments": [
+      "uint32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_u64",
+    "arguments": [
+      "uint64x1_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vec": {
+        "register": "Vn.1D"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_lane_u8",
+    "arguments": [
+      "uint8x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_f16",
+    "arguments": [
+      "float16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_f32",
+    "arguments": [
+      "float32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_f64",
+    "arguments": [
+      "float64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_p16",
+    "arguments": [
+      "poly16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_p64",
+    "arguments": [
+      "poly64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_p8",
+    "arguments": [
+      "poly8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_s16",
+    "arguments": [
+      "int16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_s32",
+    "arguments": [
+      "int32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_s64",
+    "arguments": [
+      "int64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_s8",
+    "arguments": [
+      "int8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_u16",
+    "arguments": [
+      "uint16x8_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vec": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_u32",
+    "arguments": [
+      "uint32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_u64",
+    "arguments": [
+      "uint64x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_laneq_u8",
+    "arguments": [
+      "uint8x16_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "vec": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_f16",
+    "arguments": [
+      "float16_t value"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_f32",
+    "arguments": [
+      "float32_t value"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_f64",
+    "arguments": [
+      "float64_t value"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_p16",
+    "arguments": [
+      "poly16_t value"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_p64",
+    "arguments": [
+      "poly64_t value"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_p8",
+    "arguments": [
+      "poly8_t value"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_s16",
+    "arguments": [
+      "int16_t value"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_s32",
+    "arguments": [
+      "int32_t value"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_s64",
+    "arguments": [
+      "int64_t value"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_s8",
+    "arguments": [
+      "int8_t value"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_u16",
+    "arguments": [
+      "uint16_t value"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_u32",
+    "arguments": [
+      "uint32_t value"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_u64",
+    "arguments": [
+      "uint64_t value"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdupq_n_u8",
+    "arguments": [
+      "uint8_t value"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdups_lane_f32",
+    "arguments": [
+      "float32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdups_lane_s32",
+    "arguments": [
+      "int32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdups_lane_u32",
+    "arguments": [
+      "uint32x2_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vec": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdups_laneq_f32",
+    "arguments": [
+      "float32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float32_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdups_laneq_s32",
+    "arguments": [
+      "int32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vdups_laneq_u32",
+    "arguments": [
+      "uint32x4_t vec",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vec": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b",
+      "int64x2_t c"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b",
+      "int8x16_t c"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "uint64x2_t c"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor3q_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      },
+      "c": {
+        "register": "Va.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR3"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veor_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "veorq_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EOR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_f64",
+    "arguments": [
+      "float64x1_t a",
+      "float64x1_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "float64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "poly16x4_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_p64",
+    "arguments": [
+      "poly64x1_t a",
+      "poly64x1_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_p8",
+    "arguments": [
+      "poly8x8_t a",
+      "poly8x8_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 3
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 1
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_s64",
+    "arguments": [
+      "int64x1_t a",
+      "int64x1_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 0
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "EXT"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vext_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      },
+      "n": {
         "minimum": 0,
         "maximum": 3
       }
@@ -30097,7 +233346,7 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H "
+        "register": "Vd.4H"
       },
       "b": {
         "register": "Vn.4H"
@@ -30680,7 +233929,7 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H "
+        "register": "Vd.8H"
       },
       "b": {
         "register": "Vn.8H"
@@ -30846,8 +234095,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vd.2H"
+      },
       "r": {
         "register": "Vd.2S"
       }
@@ -30875,8 +234128,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -30908,8 +234165,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -30941,8 +234202,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -30974,8 +234239,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31006,8 +234275,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vd.2H"
+      },
       "r": {
         "register": "Vd.2S"
       }
@@ -31034,8 +234307,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vd.4H"
+      },
       "r": {
         "register": "Vd.4S"
       }
@@ -31063,8 +234340,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -31096,8 +234377,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -31129,8 +234414,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31162,8 +234451,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31194,8 +234487,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vd.4H"
+      },
       "r": {
         "register": "Vd.4S"
       }
@@ -31222,8 +234519,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vd.2H"
+      },
       "r": {
         "register": "Vd.2S"
       }
@@ -31251,8 +234552,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -31284,8 +234589,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -31317,8 +234626,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31350,8 +234663,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31382,8 +234699,12 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.2H"
+      },
+      "b": {
+        "register": "Vd.2H"
+      },
       "r": {
         "register": "Vd.2S"
       }
@@ -31410,8 +234731,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vd.4H"
+      },
       "r": {
         "register": "Vd.4S"
       }
@@ -31439,8 +234764,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -31472,8 +234801,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 3
@@ -31505,8 +234838,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31538,8 +234875,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vm.H"
+      },
       "lane": {
         "minimum": 0,
         "maximum": 7
@@ -31570,8 +234911,12 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vd.4H"
+      },
       "r": {
         "register": "Vd.4S"
       }
@@ -31911,7 +235256,7 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H "
+        "register": "Vd.4H"
       },
       "b": {
         "register": "Vn.4H"
@@ -32492,7 +235837,7 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H "
+        "register": "Vd.8H"
       },
       "b": {
         "register": "Vn.8H"
@@ -34868,230 +238213,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1_lane_u64",
-    "arguments": [
-      "uint64_t const * ptr",
-      "uint64x1_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "uint64x1_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.1D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1_lane_s64",
-    "arguments": [
-      "int64_t const * ptr",
-      "int64x1_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "int64x1_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.1D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1q_lane_u64",
-    "arguments": [
-      "uint64_t const * ptr",
-      "uint64x2_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "uint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1q_lane_s64",
-    "arguments": [
-      "int64_t const * ptr",
-      "int64x2_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "int64x2_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1_lane_p64",
-    "arguments": [
-      "poly64_t const * ptr",
-      "poly64x1_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "poly64x1_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.1D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1q_lane_p64",
-    "arguments": [
-      "poly64_t const * ptr",
-      "poly64x2_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "poly64x2_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vldap1q_lane_f64",
-    "arguments": [
-      "float64_t const * ptr",
-      "float64x2_t src",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "float64x2_t"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "ptr": {
-        "register": "Xn"
-      },
-      "src": {
-        "register": "Vt.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDAP1"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "Neon",
     "name": "vld1_dup_f16",
@@ -39947,7 +243068,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
         "register": "Vt2.4H"
       }
     },
@@ -39981,7 +243105,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
         "register": "Vt2.2S"
       }
     },
@@ -40015,7 +243142,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
         "register": "Vt2.1D"
       }
     },
@@ -40047,7 +243177,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
         "register": "Vt2.4H"
       }
     },
@@ -40081,7 +243214,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
         "register": "Vt2.1D"
       }
     },
@@ -40113,7 +243249,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
         "register": "Vt2.8B"
       }
     },
@@ -40147,7 +243286,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
         "register": "Vt2.4H"
       }
     },
@@ -40181,7 +243323,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
         "register": "Vt2.2S"
       }
     },
@@ -40215,7 +243360,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
         "register": "Vt2.1D"
       }
     },
@@ -40247,7 +243395,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
         "register": "Vt2.8B"
       }
     },
@@ -40281,7 +243432,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
         "register": "Vt2.4H"
       }
     },
@@ -40315,7 +243469,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
         "register": "Vt2.2S"
       }
     },
@@ -40349,7 +243506,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
         "register": "Vt2.1D"
       }
     },
@@ -40381,7 +243541,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
         "register": "Vt2.8B"
       }
     },
@@ -41104,7 +244267,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
         "register": "Vt2.8H"
       }
     },
@@ -41138,7 +244304,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
         "register": "Vt2.4S"
       }
     },
@@ -41172,7 +244341,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
         "register": "Vt2.2D"
       }
     },
@@ -41204,7 +244376,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
         "register": "Vt2.8H"
       }
     },
@@ -41238,7 +244413,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
         "register": "Vt2.2D"
       }
     },
@@ -41270,7 +244448,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
         "register": "Vt2.16B"
       }
     },
@@ -41302,7 +244483,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
         "register": "Vt2.8H"
       }
     },
@@ -41336,7 +244520,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
         "register": "Vt2.4S"
       }
     },
@@ -41370,7 +244557,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
         "register": "Vt2.2D"
       }
     },
@@ -41402,7 +244592,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
         "register": "Vt2.16B"
       }
     },
@@ -41434,7 +244627,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
         "register": "Vt2.8H"
       }
     },
@@ -41468,7 +244664,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
         "register": "Vt2.4S"
       }
     },
@@ -41502,7 +244701,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
         "register": "Vt2.2D"
       }
     },
@@ -41534,7 +244736,10 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
         "register": "Vt2.16B"
       }
     },
@@ -42255,7 +245460,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
         "register": "Vt3.4H"
       }
     },
@@ -42289,7 +245500,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "src.val[2]": {
         "register": "Vt3.2S"
       }
     },
@@ -42323,7 +245540,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
         "register": "Vt3.1D"
       }
     },
@@ -42355,7 +245578,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
         "register": "Vt3.4H"
       }
     },
@@ -42389,7 +245618,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
         "register": "Vt3.1D"
       }
     },
@@ -42421,7 +245656,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "src.val[2]": {
         "register": "Vt3.8B"
       }
     },
@@ -42455,7 +245696,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
         "register": "Vt3.4H"
       }
     },
@@ -42489,7 +245736,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "src.val[2]": {
         "register": "Vt3.2S"
       }
     },
@@ -42523,7 +245776,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
         "register": "Vt3.1D"
       }
     },
@@ -42555,7 +245814,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "src.val[2]": {
         "register": "Vt3.8B"
       }
     },
@@ -42589,7 +245854,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
         "register": "Vt3.4H"
       }
     },
@@ -42623,7 +245894,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "src.val[2]": {
         "register": "Vt3.2S"
       }
     },
@@ -42657,7 +245934,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
         "register": "Vt3.1D"
       }
     },
@@ -42689,7 +245972,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "src.val[2]": {
         "register": "Vt3.8B"
       }
     },
@@ -43412,7 +246701,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
         "register": "Vt3.8H"
       }
     },
@@ -43446,7 +246741,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "src.val[2]": {
         "register": "Vt3.4S"
       }
     },
@@ -43480,7 +246781,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
         "register": "Vt3.2D"
       }
     },
@@ -43512,7 +246819,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
         "register": "Vt3.8H"
       }
     },
@@ -43546,7 +246859,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
         "register": "Vt3.2D"
       }
     },
@@ -43578,7 +246897,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "src.val[2]": {
         "register": "Vt3.16B"
       }
     },
@@ -43610,7 +246935,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
         "register": "Vt3.8H"
       }
     },
@@ -43644,7 +246975,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "src.val[2]": {
         "register": "Vt3.4S"
       }
     },
@@ -43678,7 +247015,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
         "register": "Vt3.2D"
       }
     },
@@ -43710,7 +247053,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "src.val[2]": {
         "register": "Vt3.16B"
       }
     },
@@ -43742,7 +247091,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
         "register": "Vt3.8H"
       }
     },
@@ -43776,7 +247131,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "src.val[2]": {
         "register": "Vt3.4S"
       }
     },
@@ -43810,7 +247171,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
         "register": "Vt3.2D"
       }
     },
@@ -43842,7 +247209,13 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "src.val[2]": {
         "register": "Vt3.16B"
       }
     },
@@ -44563,7 +247936,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "src.val[3]": {
         "register": "Vt4.4H"
       }
     },
@@ -44597,7 +247979,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "src.val[3]": {
         "register": "Vt4.2S"
       }
     },
@@ -44631,7 +248022,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "src.val[3]": {
         "register": "Vt4.1D"
       }
     },
@@ -44663,7 +248063,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "src.val[3]": {
         "register": "Vt4.4H"
       }
     },
@@ -44697,7 +248106,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "src.val[3]": {
         "register": "Vt4.1D"
       }
     },
@@ -44729,7 +248147,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "src.val[3]": {
         "register": "Vt4.8B"
       }
     },
@@ -44763,7 +248190,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "src.val[3]": {
         "register": "Vt4.4H"
       }
     },
@@ -44797,7 +248233,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "src.val[3]": {
         "register": "Vt4.2S"
       }
     },
@@ -44831,7 +248276,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "src.val[3]": {
         "register": "Vt4.1D"
       }
     },
@@ -44863,7 +248317,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "src.val[3]": {
         "register": "Vt4.8B"
       }
     },
@@ -44897,7 +248360,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "src.val[3]": {
         "register": "Vt4.4H"
       }
     },
@@ -44931,7 +248403,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "src.val[3]": {
         "register": "Vt4.2S"
       }
     },
@@ -44962,10 +248443,19 @@
         "minimum": 0,
         "maximum": 0
       },
-      "ptr": {
-        "register": "Xn"
+      "ptr": {
+        "register": "Xn"
+      },
+      "src.val[0]": {
+        "register": "Vt.1D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.1D"
       },
-      "src": {
+      "src.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "src.val[3]": {
         "register": "Vt4.1D"
       }
     },
@@ -44997,7 +248487,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "src.val[3]": {
         "register": "Vt4.8B"
       }
     },
@@ -45720,7 +249219,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "src.val[3]": {
         "register": "Vt4.8H"
       }
     },
@@ -45754,7 +249262,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "src.val[3]": {
         "register": "Vt4.4S"
       }
     },
@@ -45788,7 +249305,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "src.val[3]": {
         "register": "Vt4.2D"
       }
     },
@@ -45820,7 +249346,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "src.val[3]": {
         "register": "Vt4.8H"
       }
     },
@@ -45854,7 +249389,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "src.val[3]": {
         "register": "Vt4.2D"
       }
     },
@@ -45886,7 +249430,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "src.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "src.val[3]": {
         "register": "Vt4.16B"
       }
     },
@@ -45918,7 +249471,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "src.val[3]": {
         "register": "Vt4.8H"
       }
     },
@@ -45952,7 +249514,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "src.val[3]": {
         "register": "Vt4.4S"
       }
     },
@@ -45986,7 +249557,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "src.val[3]": {
         "register": "Vt4.2D"
       }
     },
@@ -46018,7 +249598,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "src.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "src.val[3]": {
         "register": "Vt4.16B"
       }
     },
@@ -46050,7 +249639,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.8H"
+      },
+      "src.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "src.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "src.val[3]": {
         "register": "Vt4.8H"
       }
     },
@@ -46084,7 +249682,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.4S"
+      },
+      "src.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "src.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "src.val[3]": {
         "register": "Vt4.4S"
       }
     },
@@ -46118,7 +249725,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.2D"
+      },
+      "src.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "src.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "src.val[3]": {
         "register": "Vt4.2D"
       }
     },
@@ -46150,7 +249766,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "src": {
+      "src.val[0]": {
+        "register": "Vt.16B"
+      },
+      "src.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "src.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "src.val[3]": {
         "register": "Vt4.16B"
       }
     },
@@ -46434,915 +250059,89 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vldrq_p128",
-    "arguments": [
-      "poly128_t const * ptr"
-    ],
-    "return_type": {
-      "value": "poly128_t"
-    },
-    "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDR"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_f16",
-    "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
-    ],
-    "return_type": {
-      "value": "float16x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_f32",
-    "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
-    ],
-    "return_type": {
-      "value": "float32x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_f64",
-    "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
-    ],
-    "return_type": {
-      "value": "float64x1_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_s16",
-    "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
-    ],
-    "return_type": {
-      "value": "int16x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_s32",
-    "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
-    ],
-    "return_type": {
-      "value": "int32x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_s8",
-    "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
-    ],
-    "return_type": {
-      "value": "int8x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_u16",
-    "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
-    ],
-    "return_type": {
-      "value": "uint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "UMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_u32",
-    "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
-    ],
-    "return_type": {
-      "value": "uint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "UMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmax_u8",
-    "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
-    ],
-    "return_type": {
-      "value": "uint8x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "UMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxh_f16",
-    "arguments": [
-      "float16_t a",
-      "float16_t b"
-    ],
-    "return_type": {
-      "value": "float16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnm_f16",
-    "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
-    ],
-    "return_type": {
-      "value": "float16x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnm_f32",
-    "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
-    ],
-    "return_type": {
-      "value": "float32x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnm_f64",
+    "name": "vldap1_lane_f64",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "float64_t const * ptr",
+      "float64x1_t src",
+      "const int lane"
     ],
     "return_type": {
       "value": "float64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmh_f16",
-    "arguments": [
-      "float16_t a",
-      "float16_t b"
-    ],
-    "return_type": {
-      "value": "float16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmq_f16",
-    "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
-    ],
-    "return_type": {
-      "value": "float16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmq_f32",
-    "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
-    ],
-    "return_type": {
-      "value": "float32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmq_f64",
-    "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
-    ],
-    "return_type": {
-      "value": "float64x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNM"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmv_f16",
-    "arguments": [
-      "float16x4_t a"
-    ],
-    "return_type": {
-      "value": "float16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNMP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmv_f32",
-    "arguments": [
-      "float32x2_t a"
-    ],
-    "return_type": {
-      "value": "float32_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNMP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmvq_f16",
-    "arguments": [
-      "float16x8_t a"
-    ],
-    "return_type": {
-      "value": "float16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNMP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmvq_f32",
-    "arguments": [
-      "float32x4_t a"
-    ],
-    "return_type": {
-      "value": "float32_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNMV"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxnmvq_f64",
-    "arguments": [
-      "float64x2_t a"
-    ],
-    "return_type": {
-      "value": "float64_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXNMP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_f16",
-    "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
-    ],
-    "return_type": {
-      "value": "float16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_f32",
-    "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
-    ],
-    "return_type": {
-      "value": "float32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_f64",
-    "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
-    ],
-    "return_type": {
-      "value": "float64x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_s16",
-    "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
-    ],
-    "return_type": {
-      "value": "int16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.8H"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_s32",
-    "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
-    ],
-    "return_type": {
-      "value": "int32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "src": {
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMAX"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxq_s8",
+    "name": "vldap1_lane_p64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "poly64_t const * ptr",
+      "poly64x1_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.16B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_u16",
-    "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
-    ],
-    "return_type": {
-      "value": "uint16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "src": {
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMAX"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxq_u32",
+    "name": "vldap1_lane_s64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int64_t const * ptr",
+      "int64x1_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.4S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "UMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxq_u8",
-    "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
-    ],
-    "return_type": {
-      "value": "uint8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.16B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "UMAX"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxv_f16",
-    "arguments": [
-      "float16x4_t a"
-    ],
-    "return_type": {
-      "value": "float16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMAXP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmaxv_f32",
-    "arguments": [
-      "float32x2_t a"
-    ],
-    "return_type": {
-      "value": "float32_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "src": {
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
@@ -47350,22 +250149,31 @@
     ],
     "instructions": [
       [
-        "FMAXP"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxv_s16",
+    "name": "vldap1_lane_u64",
     "arguments": [
-      "int16x4_t a"
+      "uint64_t const * ptr",
+      "uint64x1_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
@@ -47373,22 +250181,31 @@
     ],
     "instructions": [
       [
-        "SMAXV"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxv_s32",
+    "name": "vldap1q_lane_f64",
     "arguments": [
-      "int32x2_t a"
+      "float64_t const * ptr",
+      "float64x2_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -47396,22 +250213,31 @@
     ],
     "instructions": [
       [
-        "SMAXP"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxv_s8",
+    "name": "vldap1q_lane_p64",
     "arguments": [
-      "int8x8_t a"
+      "poly64_t const * ptr",
+      "poly64x2_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -47419,22 +250245,31 @@
     ],
     "instructions": [
       [
-        "SMAXV"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxv_u16",
+    "name": "vldap1q_lane_s64",
     "arguments": [
-      "uint16x4_t a"
+      "int64_t const * ptr",
+      "int64x2_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -47442,22 +250277,31 @@
     ],
     "instructions": [
       [
-        "UMAXV"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxv_u32",
+    "name": "vldap1q_lane_u64",
     "arguments": [
-      "uint32x2_t a"
+      "uint64_t const * ptr",
+      "uint64x2_t src",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -47465,44 +250309,54 @@
     ],
     "instructions": [
       [
-        "UMAXP"
+        "LDAP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxv_u8",
+    "name": "vldrq_p128",
     "arguments": [
-      "uint8x8_t a"
+      "poly128_t const * ptr"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "ptr": {
+        "register": "Xn"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMAXV"
+        "LDR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_f16",
+    "name": "vluti2_lane_f16",
     "arguments": [
-      "float16x8_t a"
+      "float16x4_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
         "register": "Vn.8H"
       }
     },
@@ -47511,22 +250365,31 @@
     ],
     "instructions": [
       [
-        "FMAXP"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_f32",
+    "name": "vluti2_lane_p16",
     "arguments": [
-      "float32x4_t a"
+      "poly16x4_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -47534,22 +250397,31 @@
     ],
     "instructions": [
       [
-        "FMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_f64",
+    "name": "vluti2_lane_p8",
     "arguments": [
-      "float64x2_t a"
+      "poly8x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -47557,21 +250429,30 @@
     ],
     "instructions": [
       [
-        "FMAXP"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_s16",
+    "name": "vluti2_lane_s16",
     "arguments": [
-      "int16x8_t a"
+      "int16x4_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
         "register": "Vn.8H"
       }
     },
@@ -47580,22 +250461,31 @@
     ],
     "instructions": [
       [
-        "SMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_s32",
+    "name": "vluti2_lane_s8",
     "arguments": [
-      "int32x4_t a"
+      "int8x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -47603,22 +250493,31 @@
     ],
     "instructions": [
       [
-        "SMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_s8",
+    "name": "vluti2_lane_u16",
     "arguments": [
-      "int8x16_t a"
+      "uint16x4_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -47626,22 +250525,31 @@
     ],
     "instructions": [
       [
-        "SMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_u16",
+    "name": "vluti2_lane_u8",
     "arguments": [
-      "uint16x8_t a"
+      "uint8x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -47649,22 +250557,31 @@
     ],
     "instructions": [
       [
-        "UMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_u32",
+    "name": "vluti2_laneq_f16",
     "arguments": [
-      "uint32x4_t a"
+      "float16x4_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -47672,22 +250589,31 @@
     ],
     "instructions": [
       [
-        "UMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmaxvq_u8",
+    "name": "vluti2_laneq_p16",
     "arguments": [
-      "uint8x16_t a"
+      "poly16x4_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -47695,83 +250621,95 @@
     ],
     "instructions": [
       [
-        "UMAXV"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_f16",
+    "name": "vluti2_laneq_p8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "poly8x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_f32",
+    "name": "vluti2_laneq_s16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int16x4_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.2S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_f64",
+    "name": "vluti2_laneq_s8",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "int8x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Dm"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -47779,200 +250717,223 @@
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_s16",
+    "name": "vluti2_laneq_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint16x4_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.4H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_s32",
+    "name": "vluti2_laneq_u8",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint8x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.2S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_s8",
+    "name": "vluti2q_lane_f16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "float16x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.8B"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_u16",
+    "name": "vluti2q_lane_p16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "poly16x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_u32",
+    "name": "vluti2q_lane_p8",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "poly8x16_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmin_u8",
+    "name": "vluti2q_lane_s16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "int16x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.8B"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminh_f16",
+    "name": "vluti2q_lane_s8",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "int8x16_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Hm"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -47980,82 +250941,95 @@
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnm_f16",
+    "name": "vluti2q_lane_u16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "uint16x8_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnm_f32",
+    "name": "vluti2q_lane_u8",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "uint8x16_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnm_f64",
+    "name": "vluti2q_laneq_f16",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "float16x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Dm"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -48063,110 +251037,127 @@
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmh_f16",
+    "name": "vluti2q_laneq_p16",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "poly16x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Hm"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmq_f16",
+    "name": "vluti2q_laneq_p8",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "poly8x16_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.8H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmq_f32",
+    "name": "vluti2q_laneq_s16",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int16x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.4S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmq_f64",
+    "name": "vluti2q_laneq_s8",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "int8x16_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.2D"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -48174,22 +251165,31 @@
     ],
     "instructions": [
       [
-        "FMINNM"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmv_f16",
+    "name": "vluti2q_laneq_u16",
     "arguments": [
-      "float16x4_t a"
+      "uint16x8_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -48197,22 +251197,31 @@
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmv_f32",
+    "name": "vluti2q_laneq_u8",
     "arguments": [
-      "float32x2_t a"
+      "uint8x16_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -48220,22 +251229,34 @@
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "LUTI2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmvq_f16",
+    "name": "vluti4q_lane_f16_x2",
     "arguments": [
-      "float16x8_t a"
+      "float16x8x2_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
@@ -48243,22 +251264,34 @@
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmvq_f32",
+    "name": "vluti4q_lane_p16_x2",
     "arguments": [
-      "float32x4_t a"
+      "poly16x8x2_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
@@ -48266,22 +251299,31 @@
     ],
     "instructions": [
       [
-        "FMINNMV"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminnmvq_f64",
+    "name": "vluti4q_lane_p8",
     "arguments": [
-      "float64x2_t a"
+      "poly8x16_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "index": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -48289,83 +251331,101 @@
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_f16",
+    "name": "vluti4q_lane_s16_x2",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int16x8x2_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.8H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_f32",
+    "name": "vluti4q_lane_s8",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int8x16_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.4S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_f64",
+    "name": "vluti4q_lane_u16_x2",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "uint16x8x2_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2D"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
@@ -48373,196 +251433,235 @@
     ],
     "instructions": [
       [
-        "FMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_s16",
+    "name": "vluti4q_lane_u8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint8x16_t vn",
+      "uint8x8_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "index": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.8H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_s32",
+    "name": "vluti4q_laneq_f16_x2",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float16x8x2_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_s8",
+    "name": "vluti4q_laneq_p16_x2",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "poly16x8x2_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.16B"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_u16",
+    "name": "vluti4q_laneq_p8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "poly8x16_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.8H"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_u32",
+    "name": "vluti4q_laneq_s16_x2",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int16x8x2_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4S"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminq_u8",
+    "name": "vluti4q_laneq_s8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int8x16_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.16B"
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMIN"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_f16",
+    "name": "vluti4q_laneq_u16_x2",
     "arguments": [
-      "float16x4_t a"
+      "uint16x8x2_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn.val[0]": {
+        "register": "Vn1.8H"
+      },
+      "vn.val[1]": {
+        "register": "Vn2.8H"
       }
     },
     "Architectures": [
@@ -48570,22 +251669,31 @@
     ],
     "instructions": [
       [
-        "FMINP"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_f32",
+    "name": "vluti4q_laneq_u8",
     "arguments": [
-      "float32x2_t a"
+      "uint8x16_t vn",
+      "uint8x16_t vm",
+      "const int index"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "index": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "vm": {
+        "register": "Vm"
+      },
+      "vn": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -48593,68 +251701,83 @@
     ],
     "instructions": [
       [
-        "FMINP"
+        "LUTI4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_s16",
+    "name": "vmax_f16",
     "arguments": [
-      "int16x4_t a"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINV"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_s32",
+    "name": "vmax_f32",
     "arguments": [
-      "int32x2_t a"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINP"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_s8",
+    "name": "vmax_f64",
     "arguments": [
-      "int8x8_t a"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -48662,160 +251785,200 @@
     ],
     "instructions": [
       [
-        "SMINV"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_u16",
+    "name": "vmax_s16",
     "arguments": [
-      "uint16x4_t a"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINV"
+        "SMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_u32",
+    "name": "vmax_s32",
     "arguments": [
-      "uint32x2_t a"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINP"
+        "SMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminv_u8",
+    "name": "vmax_s8",
     "arguments": [
-      "uint8x8_t a"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINV"
+        "SMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_f16",
+    "name": "vmax_u16",
     "arguments": [
-      "float16x8_t a"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "UMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_f32",
+    "name": "vmax_u32",
     "arguments": [
-      "float32x4_t a"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINV"
+        "UMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_f64",
+    "name": "vmax_u8",
     "arguments": [
-      "float64x2_t a"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "UMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_s16",
+    "name": "vmaxh_f16",
     "arguments": [
-      "int16x8_t a"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -48823,68 +251986,82 @@
     ],
     "instructions": [
       [
-        "SMINV"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_s32",
+    "name": "vmaxnm_f16",
     "arguments": [
-      "int32x4_t a"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINV"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_s8",
+    "name": "vmaxnm_f32",
     "arguments": [
-      "int8x16_t a"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINV"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_u16",
+    "name": "vmaxnm_f64",
     "arguments": [
-      "uint16x8_t a"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -48892,109 +252069,110 @@
     ],
     "instructions": [
       [
-        "UMINV"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_u32",
+    "name": "vmaxnmh_f16",
     "arguments": [
-      "uint32x4_t a"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINV"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vminvq_u8",
+    "name": "vmaxnmq_f16",
     "arguments": [
-      "uint8x16_t a"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINV"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_f32",
+    "name": "vmaxnmq_f32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b",
-      "float32x2_t c"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "N/A"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_f64",
+    "name": "vmaxnmq_f64",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b",
-      "float64x1_t c"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "N/A"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -49002,321 +252180,198 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmla_lane_f32",
-    "arguments": [
-      "float32x2_t a",
-      "float32x2_t b",
-      "float32x2_t v",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "float32x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {}
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RESULT[I]"
+        "FMAXNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_lane_s16",
+    "name": "vmaxnmv_f16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "int16x4_t v",
-      "const int lane"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_lane_s32",
+    "name": "vmaxnmv_f32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "int32x2_t v",
-      "const int lane"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_lane_u16",
+    "name": "vmaxnmvq_f16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t v",
-      "const int lane"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_lane_u32",
+    "name": "vmaxnmvq_f32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t v",
-      "const int lane"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAXNMV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_laneq_f32",
+    "name": "vmaxnmvq_f64",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b",
-      "float32x4_t v",
-      "const int lane"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {}
+      "a": {
+        "register": "Vn.2D"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_laneq_s16",
+    "name": "vmaxq_f16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "int16x8_t v",
-      "const int lane"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
         "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_laneq_s32",
+    "name": "vmaxq_f32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "int32x4_t v",
-      "const int lane"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
         "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_laneq_u16",
+    "name": "vmaxq_f64",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "uint16x8_t v",
-      "const int lane"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -49324,66 +252379,55 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_laneq_u32",
+    "name": "vmaxq_s16",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "uint32x4_t v",
-      "const int lane"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_n_f32",
+    "name": "vmaxq_s32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b",
-      "float32_t c"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "N/A"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -49393,30 +252437,26 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "SMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_n_s16",
+    "name": "vmaxq_s8",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "int16_t c"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -49426,30 +252466,26 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "SMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_n_s32",
+    "name": "vmaxq_u16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "int32_t c"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -49459,30 +252495,26 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_n_u16",
+    "name": "vmaxq_u32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "uint16_t c"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -49492,30 +252524,26 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_n_u32",
+    "name": "vmaxq_u8",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "uint32_t c"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -49525,233 +252553,160 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMAX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_s16",
+    "name": "vmaxv_f16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_s32",
+    "name": "vmaxv_f32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_s8",
+    "name": "vmaxv_s16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b",
-      "int8x8_t c"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "c": {
-        "register": "Vm.8B"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_u16",
+    "name": "vmaxv_s32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t c"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_u32",
+    "name": "vmaxv_s8",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t c"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.2S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmla_u8",
+    "name": "vmaxv_u16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "uint8x8_t c"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "c": {
-        "register": "Vm.8B"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "UMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_lane_s16",
+    "name": "vmaxv_u32",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x4_t v",
-      "const int lane"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -49759,35 +252714,22 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_lane_s32",
+    "name": "vmaxv_u8",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x2_t v",
-      "const int lane"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -49795,35 +252737,22 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "UMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_lane_u16",
+    "name": "vmaxvq_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b",
-      "uint16x4_t v",
-      "const int lane"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -49831,35 +252760,22 @@
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_lane_u32",
+    "name": "vmaxvq_f32",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b",
-      "uint32x2_t v",
-      "const int lane"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -49867,35 +252783,22 @@
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "FMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_laneq_s16",
+    "name": "vmaxvq_f64",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t v",
-      "const int lane"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -49903,35 +252806,22 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_laneq_s32",
+    "name": "vmaxvq_s16",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t v",
-      "const int lane"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -49939,35 +252829,22 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "SMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_laneq_u16",
+    "name": "vmaxvq_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b",
-      "uint16x8_t v",
-      "const int lane"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -49975,35 +252852,22 @@
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "SMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_laneq_u32",
+    "name": "vmaxvq_s8",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b",
-      "uint32x4_t v",
-      "const int lane"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -50011,30 +252875,22 @@
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "SMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_n_s16",
+    "name": "vmaxvq_u16",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16_t c"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -50042,30 +252898,22 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "UMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_n_s32",
+    "name": "vmaxvq_u32",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32_t c"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -50073,30 +252921,22 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "UMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_n_u16",
+    "name": "vmaxvq_u8",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b",
-      "uint16_t c"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -50104,92 +252944,83 @@
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "UMAXV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_n_u32",
+    "name": "vmin_f16",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b",
-      "uint32_t c"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_s16",
+    "name": "vmin_f32",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_s32",
+    "name": "vmin_f64",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -50197,159 +253028,142 @@
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_s8",
+    "name": "vmin_s16",
     "arguments": [
-      "int16x8_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.16B"
-      },
-      "c": {
-        "register": "Vm.16B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL2"
+        "SMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_u16",
+    "name": "vmin_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "SMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_u32",
+    "name": "vmin_s8",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "SMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_high_u8",
+    "name": "vmin_u16",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.16B"
-      },
-      "c": {
-        "register": "Vm.16B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL2"
+        "UMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_lane_s16",
+    "name": "vmin_u32",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t v",
-      "const int lane"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -50359,35 +253173,26 @@
     ],
     "instructions": [
       [
-        "SMLAL"
+        "UMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_lane_s32",
+    "name": "vmin_u8",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t v",
-      "const int lane"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -50397,147 +253202,109 @@
     ],
     "instructions": [
       [
-        "SMLAL"
+        "UMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_lane_u16",
+    "name": "vminh_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t v",
-      "const int lane"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Hn"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Hm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_lane_u32",
+    "name": "vminnm_f16",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t v",
-      "const int lane"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_laneq_s16",
+    "name": "vminnm_f32",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x8_t v",
-      "const int lane"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_laneq_s32",
+    "name": "vminnm_f64",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x4_t v",
-      "const int lane"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -50545,366 +253312,280 @@
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_laneq_u16",
+    "name": "vminnmh_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b",
-      "uint16x8_t v",
-      "const int lane"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Hn"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Hm"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_laneq_u32",
+    "name": "vminnmq_f16",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b",
-      "uint32x4_t v",
-      "const int lane"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_n_s16",
+    "name": "vminnmq_f32",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16_t c"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_n_s32",
+    "name": "vminnmq_f64",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32_t c"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_n_u16",
+    "name": "vminnmv_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b",
-      "uint16_t c"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_n_u32",
+    "name": "vminnmv_f32",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b",
-      "uint32_t c"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_s16",
+    "name": "vminnmvq_f16",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.4H"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_s32",
+    "name": "vminnmvq_f32",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.2S"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNMV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_s8",
+    "name": "vminnmvq_f64",
     "arguments": [
-      "int16x8_t a",
-      "int8x8_t b",
-      "int8x8_t c"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "c": {
-        "register": "Vm.8B"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMLAL"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_u16",
+    "name": "vminq_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b",
-      "uint16x4_t c"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.4H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_u32",
+    "name": "vminq_f32",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b",
-      "uint32x2_t c"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.2S"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -50914,63 +253595,53 @@
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlal_u8",
+    "name": "vminq_f64",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b",
-      "uint8x8_t c"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.8B"
-      },
-      "c": {
-        "register": "Vm.8B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMLAL"
+        "FMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_f32",
+    "name": "vminq_s16",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b",
-      "float32x4_t c"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "N/A"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -50980,61 +253651,56 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "SMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_f64",
+    "name": "vminq_s32",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b",
-      "float64x2_t c"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "N/A"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "SMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_lane_f32",
+    "name": "vminq_s8",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b",
-      "float32x2_t v",
-      "const int lane"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.16B"
       },
-      "v": {}
+      "b": {
+        "register": "Vm.16B"
+      }
     },
     "Architectures": [
       "v7",
@@ -51043,35 +253709,26 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "SMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_lane_s16",
+    "name": "vminq_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x4_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -51081,35 +253738,26 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_lane_s32",
+    "name": "vminq_u32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x2_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -51119,35 +253767,26 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_lane_u16",
+    "name": "vminq_u8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x4_t v",
-      "const int lane"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -51157,103 +253796,68 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMIN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_lane_u32",
+    "name": "vminv_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x2_t v",
-      "const int lane"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_laneq_f32",
+    "name": "vminv_f32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b",
-      "float32x4_t v",
-      "const int lane"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {}
+      "a": {
+        "register": "Vn.2S"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_laneq_s16",
+    "name": "vminv_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t v",
-      "const int lane"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -51261,35 +253865,22 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "SMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_laneq_s32",
+    "name": "vminv_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t v",
-      "const int lane"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -51297,35 +253888,22 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_laneq_u16",
+    "name": "vminv_s8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t v",
-      "const int lane"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -51333,35 +253911,22 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "SMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_laneq_u32",
+    "name": "vminv_u16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t v",
-      "const int lane"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -51369,376 +253934,266 @@
     ],
     "instructions": [
       [
-        "MLA"
+        "UMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_n_f32",
+    "name": "vminv_u32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b",
-      "float32_t c"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "N/A"
-      },
-      "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_n_s16",
+    "name": "vminv_u8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16_t c"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "UMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_n_s32",
+    "name": "vminvq_f16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32_t c"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_n_u16",
+    "name": "vminvq_f32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16_t c"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_n_u32",
+    "name": "vminvq_f64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32_t c"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_s16",
+    "name": "vminvq_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_s32",
+    "name": "vminvq_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_s8",
+    "name": "vminvq_s8",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
-      "int8x16_t c"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
         "register": "Vn.16B"
-      },
-      "c": {
-        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "SMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_u16",
+    "name": "vminvq_u16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "UMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_u32",
+    "name": "vminvq_u32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "UMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlaq_u8",
+    "name": "vminvq_u8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
         "register": "Vn.16B"
-      },
-      "c": {
-        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MLA"
+        "UMINV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_f32",
+    "name": "vmla_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b",
@@ -51765,13 +254220,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_f64",
+    "name": "vmla_f64",
     "arguments": [
       "float64x1_t a",
       "float64x1_t b",
@@ -51796,13 +254251,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_lane_f32",
+    "name": "vmla_lane_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b",
@@ -51813,13 +254268,10 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
       "lane": {
         "minimum": 0,
         "maximum": 1
-      },
-      "v": {}
+      }
     },
     "Architectures": [
       "v7",
@@ -51828,13 +254280,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_lane_s16",
+    "name": "vmla_lane_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b",
@@ -51866,13 +254318,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_lane_s32",
+    "name": "vmla_lane_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b",
@@ -51904,13 +254356,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_lane_u16",
+    "name": "vmla_lane_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b",
@@ -51942,13 +254394,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_lane_u32",
+    "name": "vmla_lane_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b",
@@ -51980,13 +254432,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_laneq_f32",
+    "name": "vmla_laneq_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b",
@@ -51997,26 +254449,23 @@
       "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
       "lane": {
         "minimum": 0,
         "maximum": 3
-      },
-      "v": {}
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_laneq_s16",
+    "name": "vmla_laneq_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b",
@@ -52046,13 +254495,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_laneq_s32",
+    "name": "vmla_laneq_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b",
@@ -52082,13 +254531,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_laneq_u16",
+    "name": "vmla_laneq_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b",
@@ -52118,13 +254567,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_laneq_u32",
+    "name": "vmla_laneq_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b",
@@ -52154,13 +254603,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_n_f32",
+    "name": "vmla_n_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b",
@@ -52187,13 +254636,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_n_s16",
+    "name": "vmla_n_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b",
@@ -52220,13 +254669,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_n_s32",
+    "name": "vmla_n_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b",
@@ -52253,13 +254702,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_n_u16",
+    "name": "vmla_n_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b",
@@ -52286,13 +254735,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_n_u32",
+    "name": "vmla_n_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b",
@@ -52319,13 +254768,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_s16",
+    "name": "vmla_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b",
@@ -52352,13 +254801,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_s32",
+    "name": "vmla_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b",
@@ -52385,13 +254834,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_s8",
+    "name": "vmla_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b",
@@ -52418,13 +254867,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_u16",
+    "name": "vmla_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b",
@@ -52451,13 +254900,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_u32",
+    "name": "vmla_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b",
@@ -52484,13 +254933,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmls_u8",
+    "name": "vmla_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b",
@@ -52517,13 +254966,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_lane_s16",
+    "name": "vmlal_high_lane_s16",
     "arguments": [
       "int32x4_t a",
       "int16x8_t b",
@@ -52553,13 +255002,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_lane_s32",
+    "name": "vmlal_high_lane_s32",
     "arguments": [
       "int64x2_t a",
       "int32x4_t b",
@@ -52589,13 +255038,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_lane_u16",
+    "name": "vmlal_high_lane_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x8_t b",
@@ -52625,13 +255074,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_lane_u32",
+    "name": "vmlal_high_lane_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x4_t b",
@@ -52661,13 +255110,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_laneq_s16",
+    "name": "vmlal_high_laneq_s16",
     "arguments": [
       "int32x4_t a",
       "int16x8_t b",
@@ -52697,13 +255146,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_laneq_s32",
+    "name": "vmlal_high_laneq_s32",
     "arguments": [
       "int64x2_t a",
       "int32x4_t b",
@@ -52733,13 +255182,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_laneq_u16",
+    "name": "vmlal_high_laneq_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x8_t b",
@@ -52769,13 +255218,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_laneq_u32",
+    "name": "vmlal_high_laneq_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x4_t b",
@@ -52805,13 +255254,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_n_s16",
+    "name": "vmlal_high_n_s16",
     "arguments": [
       "int32x4_t a",
       "int16x8_t b",
@@ -52836,13 +255285,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_n_s32",
+    "name": "vmlal_high_n_s32",
     "arguments": [
       "int64x2_t a",
       "int32x4_t b",
@@ -52867,13 +255316,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_n_u16",
+    "name": "vmlal_high_n_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x8_t b",
@@ -52898,13 +255347,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_n_u32",
+    "name": "vmlal_high_n_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x4_t b",
@@ -52929,13 +255378,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_s16",
+    "name": "vmlal_high_s16",
     "arguments": [
       "int32x4_t a",
       "int16x8_t b",
@@ -52960,13 +255409,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_s32",
+    "name": "vmlal_high_s32",
     "arguments": [
       "int64x2_t a",
       "int32x4_t b",
@@ -52991,13 +255440,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_s8",
+    "name": "vmlal_high_s8",
     "arguments": [
       "int16x8_t a",
       "int8x16_t b",
@@ -53022,13 +255471,13 @@
     ],
     "instructions": [
       [
-        "SMLSL2"
+        "SMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_u16",
+    "name": "vmlal_high_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x8_t b",
@@ -53053,13 +255502,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_u32",
+    "name": "vmlal_high_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x4_t b",
@@ -53084,13 +255533,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_high_u8",
+    "name": "vmlal_high_u8",
     "arguments": [
       "uint16x8_t a",
       "uint8x16_t b",
@@ -53115,13 +255564,13 @@
     ],
     "instructions": [
       [
-        "UMLSL2"
+        "UMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_lane_s16",
+    "name": "vmlal_lane_s16",
     "arguments": [
       "int32x4_t a",
       "int16x4_t b",
@@ -53153,13 +255602,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_lane_s32",
+    "name": "vmlal_lane_s32",
     "arguments": [
       "int64x2_t a",
       "int32x2_t b",
@@ -53191,13 +255640,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_lane_u16",
+    "name": "vmlal_lane_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x4_t b",
@@ -53229,13 +255678,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_lane_u32",
+    "name": "vmlal_lane_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x2_t b",
@@ -53267,13 +255716,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_laneq_s16",
+    "name": "vmlal_laneq_s16",
     "arguments": [
       "int32x4_t a",
       "int16x4_t b",
@@ -53303,13 +255752,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_laneq_s32",
+    "name": "vmlal_laneq_s32",
     "arguments": [
       "int64x2_t a",
       "int32x2_t b",
@@ -53339,13 +255788,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_laneq_u16",
+    "name": "vmlal_laneq_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x4_t b",
@@ -53375,13 +255824,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_laneq_u32",
+    "name": "vmlal_laneq_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x2_t b",
@@ -53411,13 +255860,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_n_s16",
+    "name": "vmlal_n_s16",
     "arguments": [
       "int32x4_t a",
       "int16x4_t b",
@@ -53444,13 +255893,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_n_s32",
+    "name": "vmlal_n_s32",
     "arguments": [
       "int64x2_t a",
       "int32x2_t b",
@@ -53477,13 +255926,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_n_u16",
+    "name": "vmlal_n_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x4_t b",
@@ -53510,13 +255959,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_n_u32",
+    "name": "vmlal_n_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x2_t b",
@@ -53543,13 +255992,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_s16",
+    "name": "vmlal_s16",
     "arguments": [
       "int32x4_t a",
       "int16x4_t b",
@@ -53576,13 +256025,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_s32",
+    "name": "vmlal_s32",
     "arguments": [
       "int64x2_t a",
       "int32x2_t b",
@@ -53609,13 +256058,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_s8",
+    "name": "vmlal_s8",
     "arguments": [
       "int16x8_t a",
       "int8x8_t b",
@@ -53642,13 +256091,13 @@
     ],
     "instructions": [
       [
-        "SMLSL"
+        "SMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_u16",
+    "name": "vmlal_u16",
     "arguments": [
       "uint32x4_t a",
       "uint16x4_t b",
@@ -53675,13 +256124,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_u32",
+    "name": "vmlal_u32",
     "arguments": [
       "uint64x2_t a",
       "uint32x2_t b",
@@ -53708,13 +256157,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsl_u8",
+    "name": "vmlal_u8",
     "arguments": [
       "uint16x8_t a",
       "uint8x8_t b",
@@ -53741,13 +256190,13 @@
     ],
     "instructions": [
       [
-        "UMLSL"
+        "UMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_f32",
+    "name": "vmlaq_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b",
@@ -53774,13 +256223,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_f64",
+    "name": "vmlaq_f64",
     "arguments": [
       "float64x2_t a",
       "float64x2_t b",
@@ -53805,13 +256254,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_lane_f32",
+    "name": "vmlaq_lane_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b",
@@ -53822,13 +256271,10 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
       "lane": {
         "minimum": 0,
         "maximum": 1
-      },
-      "v": {}
+      }
     },
     "Architectures": [
       "v7",
@@ -53837,13 +256283,13 @@
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_lane_s16",
+    "name": "vmlaq_lane_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b",
@@ -53875,13 +256321,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_lane_s32",
+    "name": "vmlaq_lane_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b",
@@ -53913,13 +256359,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_lane_u16",
+    "name": "vmlaq_lane_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b",
@@ -53951,13 +256397,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_lane_u32",
+    "name": "vmlaq_lane_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b",
@@ -53989,13 +256435,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_laneq_f32",
+    "name": "vmlaq_laneq_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b",
@@ -54006,26 +256452,23 @@
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {},
       "lane": {
         "minimum": 0,
         "maximum": 3
-      },
-      "v": {}
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "RESULT[I]"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_laneq_s16",
+    "name": "vmlaq_laneq_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b",
@@ -54055,13 +256498,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_laneq_s32",
+    "name": "vmlaq_laneq_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b",
@@ -54091,13 +256534,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_laneq_u16",
+    "name": "vmlaq_laneq_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b",
@@ -54127,13 +256570,13 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_laneq_u32",
+    "name": "vmlaq_laneq_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b",
@@ -54163,547 +256606,30 @@
     ],
     "instructions": [
       [
-        "MLS"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmlsq_n_f32",
+    "name": "vmlaq_n_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b",
-      "float32_t c"
-    ],
-    "return_type": {
-      "value": "float32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "N/A"
-      },
-      "b": {
-        "register": "N/A"
-      },
-      "c": {
-        "register": "N/A"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RESULT[I]"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_n_s16",
-    "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16_t c"
-    ],
-    "return_type": {
-      "value": "int16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_n_s32",
-    "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32_t c"
-    ],
-    "return_type": {
-      "value": "int32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_n_u16",
-    "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16_t c"
-    ],
-    "return_type": {
-      "value": "uint16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_n_u32",
-    "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32_t c"
-    ],
-    "return_type": {
-      "value": "uint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_s16",
-    "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
-    ],
-    "return_type": {
-      "value": "int16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_s32",
-    "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
-    ],
-    "return_type": {
-      "value": "int32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_s8",
-    "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
-      "int8x16_t c"
-    ],
-    "return_type": {
-      "value": "int8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
-      },
-      "c": {
-        "register": "Vm.16B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_u16",
-    "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "uint16x8_t c"
-    ],
-    "return_type": {
-      "value": "uint16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_u32",
-    "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
-    ],
-    "return_type": {
-      "value": "uint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmlsq_u8",
-    "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "uint8x16_t c"
-    ],
-    "return_type": {
-      "value": "uint8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
-      },
-      "c": {
-        "register": "Vm.16B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "MLS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmmlaq_s32",
-    "arguments": [
-      "int32x4_t r",
-      "int8x16_t a",
-      "int8x16_t b"
-    ],
-    "return_type": {
-      "value": "int32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
-      },
-      "r": {
-        "register": "Vd.4S"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SMMLA"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmmlaq_u32",
-    "arguments": [
-      "uint32x4_t r",
-      "uint8x16_t a",
-      "uint8x16_t b"
-    ],
-    "return_type": {
-      "value": "uint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
-      },
-      "r": {
-        "register": "Vd.4S"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "UMMLA"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmov_n_f16",
-    "arguments": [
-      "float16_t value"
-    ],
-    "return_type": {
-      "value": "float16x4_t"
-    },
-    "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "DUP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmov_n_f32",
-    "arguments": [
-      "float32_t value"
-    ],
-    "return_type": {
-      "value": "float32x2_t"
-    },
-    "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "DUP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmov_n_f64",
-    "arguments": [
-      "float64_t value"
-    ],
-    "return_type": {
-      "value": "float64x1_t"
-    },
-    "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "DUP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmov_n_p16",
-    "arguments": [
-      "poly16_t value"
-    ],
-    "return_type": {
-      "value": "poly16x4_t"
-    },
-    "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "DUP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmov_n_p8",
-    "arguments": [
-      "poly8_t value"
+      "float32_t c"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "N/A"
+      },
+      "b": {
+        "register": "N/A"
+      },
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
@@ -54713,22 +256639,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_s16",
+    "name": "vmlaq_n_s16",
     "arguments": [
-      "int16_t value"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -54738,22 +256672,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_s32",
+    "name": "vmlaq_n_s32",
     "arguments": [
-      "int32_t value"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -54763,22 +256705,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_s64",
+    "name": "vmlaq_n_u16",
     "arguments": [
-      "int64_t value"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16_t c"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -54788,22 +256738,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_s8",
+    "name": "vmlaq_n_u32",
     "arguments": [
-      "int8_t value"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32_t c"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -54813,22 +256771,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_u16",
+    "name": "vmlaq_s16",
     "arguments": [
-      "uint16_t value"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -54838,22 +256804,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_u32",
+    "name": "vmlaq_s32",
     "arguments": [
-      "uint32_t value"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -54863,22 +256837,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_u64",
+    "name": "vmlaq_s8",
     "arguments": [
-      "uint64_t value"
+      "int8x16_t a",
+      "int8x16_t b",
+      "int8x16_t c"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -54888,22 +256870,30 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmov_n_u8",
+    "name": "vmlaq_u16",
     "arguments": [
-      "uint8_t value"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -54913,91 +256903,129 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_high_s16",
+    "name": "vmlaq_u32",
     "arguments": [
-      "int16x8_t a"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL2"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_high_s32",
+    "name": "vmlaq_u8",
     "arguments": [
-      "int32x4_t a"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL2"
+        "MLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_high_s8",
+    "name": "vmls_f32",
     "arguments": [
-      "int8x16_t a"
+      "float32x2_t a",
+      "float32x2_t b",
+      "float32x2_t c"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "N/A"
+      },
+      "b": {
+        "register": "N/A"
+      },
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL2"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_high_u16",
+    "name": "vmls_f64",
     "arguments": [
-      "uint16x8_t a"
+      "float64x1_t a",
+      "float64x1_t b",
+      "float64x1_t c"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "N/A"
+      },
+      "b": {
+        "register": "N/A"
+      },
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
@@ -55005,68 +257033,102 @@
     ],
     "instructions": [
       [
-        "USHLL2"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_high_u32",
+    "name": "vmls_lane_f32",
     "arguments": [
-      "uint32x4_t a"
+      "float32x2_t a",
+      "float32x2_t b",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHLL2"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_high_u8",
+    "name": "vmls_lane_s16",
     "arguments": [
-      "uint8x16_t a"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHLL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_s16",
+    "name": "vmls_lane_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -55076,22 +257138,35 @@
     ],
     "instructions": [
       [
-        "SSHLL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_s32",
+    "name": "vmls_lane_u16",
     "arguments": [
-      "int32x2_t a"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -55101,22 +257176,35 @@
     ],
     "instructions": [
       [
-        "SSHLL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_s8",
+    "name": "vmls_lane_u32",
     "arguments": [
-      "int8x8_t a"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "uint32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -55126,159 +257214,201 @@
     ],
     "instructions": [
       [
-        "SSHLL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_u16",
+    "name": "vmls_laneq_f32",
     "arguments": [
-      "uint16x4_t a"
+      "float32x2_t a",
+      "float32x2_t b",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHLL"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_u32",
+    "name": "vmls_laneq_s16",
     "arguments": [
-      "uint32x2_t a"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHLL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovl_u8",
+    "name": "vmls_laneq_s32",
     "arguments": [
-      "uint8x8_t a"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHLL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_high_s16",
+    "name": "vmls_laneq_u16",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "uint16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4H"
       },
-      "r": {
-        "register": "Vd.8B"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "XTN2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_high_s32",
+    "name": "vmls_laneq_u32",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "uint32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.2S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "XTN2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_high_s64",
+    "name": "vmls_n_f32",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a"
+      "float32x2_t a",
+      "float32x2_t b",
+      "float32_t c"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "N/A"
       },
-      "r": {
-        "register": "Vd.2S"
+      "b": {
+        "register": "N/A"
+      },
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
@@ -55288,26 +257418,30 @@
     ],
     "instructions": [
       [
-        "XTN2"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_high_u16",
+    "name": "vmls_n_s16",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4H"
       },
-      "r": {
-        "register": "Vd.8B"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -55317,26 +257451,30 @@
     ],
     "instructions": [
       [
-        "XTN2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_high_u32",
+    "name": "vmls_n_s32",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.2S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -55346,26 +257484,30 @@
     ],
     "instructions": [
       [
-        "XTN2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_high_u64",
+    "name": "vmls_n_u16",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "uint16_t c"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.4H"
       },
-      "r": {
-        "register": "Vd.2S"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -55375,22 +257517,30 @@
     ],
     "instructions": [
       [
-        "XTN2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_s16",
+    "name": "vmls_n_u32",
     "arguments": [
-      "int16x8_t a"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "uint32_t c"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -55400,22 +257550,30 @@
     ],
     "instructions": [
       [
-        "XTN"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_s32",
+    "name": "vmls_s16",
     "arguments": [
-      "int32x4_t a"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
     ],
     "return_type": {
       "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -55425,22 +257583,30 @@
     ],
     "instructions": [
       [
-        "XTN"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_s64",
+    "name": "vmls_s32",
     "arguments": [
-      "int64x2_t a"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
     ],
     "return_type": {
       "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -55450,22 +257616,30 @@
     ],
     "instructions": [
       [
-        "XTN"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_u16",
+    "name": "vmls_s8",
     "arguments": [
-      "uint16x8_t a"
+      "int8x8_t a",
+      "int8x8_t b",
+      "int8x8_t c"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -55475,22 +257649,30 @@
     ],
     "instructions": [
       [
-        "XTN"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_u32",
+    "name": "vmls_u16",
     "arguments": [
-      "uint32x4_t a"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "uint16x4_t c"
     ],
     "return_type": {
       "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -55500,22 +257682,30 @@
     ],
     "instructions": [
       [
-        "XTN"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovn_u64",
+    "name": "vmls_u32",
     "arguments": [
-      "uint64x2_t a"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "uint32x2_t c"
     ],
     "return_type": {
       "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -55525,22 +257715,30 @@
     ],
     "instructions": [
       [
-        "XTN"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_f16",
+    "name": "vmls_u8",
     "arguments": [
-      "float16_t value"
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "uint8x8_t c"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -55550,47 +257748,71 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_f32",
+    "name": "vmlsl_high_lane_s16",
     "arguments": [
-      "float32_t value"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_f64",
+    "name": "vmlsl_high_lane_s32",
     "arguments": [
-      "float64_t value"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -55598,333 +257820,432 @@
     ],
     "instructions": [
       [
-        "DUP"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_p16",
+    "name": "vmlsl_high_lane_u16",
     "arguments": [
-      "poly16_t value"
+      "uint32x4_t a",
+      "uint16x8_t b",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_p8",
+    "name": "vmlsl_high_lane_u32",
     "arguments": [
-      "poly8_t value"
+      "uint64x2_t a",
+      "uint32x4_t b",
+      "uint32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_s16",
+    "name": "vmlsl_high_laneq_s16",
     "arguments": [
-      "int16_t value"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_s32",
+    "name": "vmlsl_high_laneq_s32",
     "arguments": [
-      "int32_t value"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_s64",
+    "name": "vmlsl_high_laneq_u16",
     "arguments": [
-      "int64_t value"
+      "uint32x4_t a",
+      "uint16x8_t b",
+      "uint16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_s8",
+    "name": "vmlsl_high_laneq_u32",
     "arguments": [
-      "int8_t value"
+      "uint64x2_t a",
+      "uint32x4_t b",
+      "uint32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_u16",
+    "name": "vmlsl_high_n_s16",
     "arguments": [
-      "uint16_t value"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_u32",
+    "name": "vmlsl_high_n_s32",
     "arguments": [
-      "uint32_t value"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_u64",
+    "name": "vmlsl_high_n_u16",
     "arguments": [
-      "uint64_t value"
+      "uint32x4_t a",
+      "uint16x8_t b",
+      "uint16_t c"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmovq_n_u8",
+    "name": "vmlsl_high_n_u32",
     "arguments": [
-      "uint8_t value"
+      "uint64x2_t a",
+      "uint32x4_t b",
+      "uint32_t c"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "value": {
-        "register": "rn"
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "DUP"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_f16",
+    "name": "vmlsl_high_s16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_f32",
+    "name": "vmlsl_high_s32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2D"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_f64",
+    "name": "vmlsl_high_s8",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "int16x8_t a",
+      "int8x16_t b",
+      "int8x16_t c"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -55932,98 +258253,92 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "SMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_f16",
+    "name": "vmlsl_high_u16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "b": {
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vm.4H"
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_f32",
+    "name": "vmlsl_high_u32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t v",
-      "const int lane"
+      "uint64x2_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2D"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "b": {
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vm.2S"
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_f64",
+    "name": "vmlsl_high_u8",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "b": {
+        "register": "Vn.16B"
       },
-      "v": {
-        "register": "Vm.1D"
+      "c": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -56031,23 +258346,27 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "UMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_s16",
+    "name": "vmlsl_lane_s16",
     "arguments": [
-      "int16x4_t a",
+      "int32x4_t a",
+      "int16x4_t b",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
         "register": "Vn.4H"
       },
       "lane": {
@@ -56065,23 +258384,27 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_s32",
+    "name": "vmlsl_lane_s32",
     "arguments": [
-      "int32x2_t a",
+      "int64x2_t a",
+      "int32x2_t b",
       "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
         "register": "Vn.2S"
       },
       "lane": {
@@ -56099,23 +258422,27 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_u16",
+    "name": "vmlsl_lane_u16",
     "arguments": [
-      "uint16x4_t a",
+      "uint32x4_t a",
+      "uint16x4_t b",
       "uint16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
         "register": "Vn.4H"
       },
       "lane": {
@@ -56133,23 +258460,27 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_lane_u32",
+    "name": "vmlsl_lane_u32",
     "arguments": [
-      "uint32x2_t a",
+      "uint64x2_t a",
+      "uint32x2_t b",
       "uint32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
         "register": "Vn.2S"
       },
       "lane": {
@@ -56167,23 +258498,27 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_f16",
+    "name": "vmlsl_laneq_s16",
     "arguments": [
-      "float16x4_t a",
-      "float16x8_t v",
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
         "register": "Vn.4H"
       },
       "lane": {
@@ -56199,23 +258534,27 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_f32",
+    "name": "vmlsl_laneq_s32",
     "arguments": [
-      "float32x2_t a",
-      "float32x4_t v",
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
         "register": "Vn.2S"
       },
       "lane": {
@@ -56231,55 +258570,27 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_f64",
+    "name": "vmlsl_laneq_u16",
     "arguments": [
-      "float64x1_t a",
-      "float64x2_t v",
+      "uint32x4_t a",
+      "uint16x4_t b",
+      "uint16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vd.4S"
       },
-      "v": {
-        "register": "Vm.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FMUL"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_s16",
-    "arguments": [
-      "int16x4_t a",
-      "int16x8_t v",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "int16x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
+      "b": {
         "register": "Vn.4H"
       },
       "lane": {
@@ -56295,23 +258606,27 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_s32",
+    "name": "vmlsl_laneq_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32x4_t v",
+      "uint64x2_t a",
+      "uint32x2_t b",
+      "uint32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
         "register": "Vn.2S"
       },
       "lane": {
@@ -56327,117 +258642,128 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_u16",
+    "name": "vmlsl_n_s16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x8_t v",
-      "const int lane"
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Vn.4H"
       },
-      "v": {
-        "register": "Vm.8H"
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_laneq_u32",
+    "name": "vmlsl_n_s32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x4_t v",
-      "const int lane"
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2D"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "b": {
+        "register": "Vn.2S"
       },
-      "v": {
-        "register": "Vm.4S"
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_f16",
+    "name": "vmlsl_n_u16",
     "arguments": [
-      "float16x4_t a",
-      "float16_t n"
+      "uint32x4_t a",
+      "uint16x4_t b",
+      "uint16_t c"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
         "register": "Vn.4H"
       },
-      "n": {
+      "c": {
         "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_f32",
+    "name": "vmlsl_n_u32",
     "arguments": [
-      "float32x2_t a",
-      "float32_t b"
+      "uint64x2_t a",
+      "uint32x2_t b",
+      "uint32_t c"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2D"
       },
       "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
         "register": "Vm.S[0]"
       }
     },
@@ -56448,53 +258774,63 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_f64",
+    "name": "vmlsl_s16",
     "arguments": [
-      "float64x1_t a",
-      "float64_t b"
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Vm.D[0]"
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_s16",
+    "name": "vmlsl_s32",
     "arguments": [
-      "int16x4_t a",
-      "int16_t b"
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.2D"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -56504,26 +258840,30 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_s32",
+    "name": "vmlsl_s8",
     "arguments": [
-      "int32x2_t a",
-      "int32_t b"
+      "int16x8_t a",
+      "int8x8_t b",
+      "int8x8_t c"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.8B"
+      },
+      "c": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -56533,26 +258873,30 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "SMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_u16",
+    "name": "vmlsl_u16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16_t b"
+      "uint32x4_t a",
+      "uint16x4_t b",
+      "uint16x4_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -56562,26 +258906,30 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_n_u32",
+    "name": "vmlsl_u32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32_t b"
+      "uint64x2_t a",
+      "uint32x2_t b",
+      "uint32x2_t c"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2D"
       },
       "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -56591,25 +258939,29 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_p8",
+    "name": "vmlsl_u8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "uint16x8_t a",
+      "uint8x8_t b",
+      "uint8x8_t c"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.8H"
       },
       "b": {
+        "register": "Vn.8B"
+      },
+      "c": {
         "register": "Vm.8B"
       }
     },
@@ -56620,26 +258972,30 @@
     ],
     "instructions": [
       [
-        "PMUL"
+        "UMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_s16",
+    "name": "vmlsq_f32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "float32x4_t a",
+      "float32x4_t b",
+      "float32x4_t c"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "N/A"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "N/A"
+      },
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
@@ -56649,55 +259005,57 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_s32",
+    "name": "vmlsq_f64",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "float64x2_t a",
+      "float64x2_t b",
+      "float64x2_t c"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "N/A"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "N/A"
+      },
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_s8",
+    "name": "vmlsq_lane_f32",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "float32x4_t a",
+      "float32x4_t b",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       }
     },
     "Architectures": [
@@ -56707,25 +259065,34 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_u16",
+    "name": "vmlsq_lane_s16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.8H"
       },
       "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
         "register": "Vm.4H"
       }
     },
@@ -56736,25 +259103,34 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_u32",
+    "name": "vmlsq_lane_s32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.4S"
       },
       "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
         "register": "Vm.2S"
       }
     },
@@ -56765,26 +259141,35 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmul_u8",
+    "name": "vmlsq_lane_u16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -56794,63 +259179,64 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmuld_lane_f64",
+    "name": "vmlsq_lane_u32",
     "arguments": [
-      "float64_t a",
-      "float64x1_t v",
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 1
       },
       "v": {
-        "register": "Vm.1D"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmuld_laneq_f64",
+    "name": "vmlsq_laneq_f32",
     "arguments": [
-      "float64_t a",
-      "float64x2_t v",
+      "float32x4_t a",
+      "float32x4_t b",
+      "float32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
-      },
       "lane": {
         "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2D"
+        "maximum": 3
       }
     },
     "Architectures": [
@@ -56858,59 +259244,71 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulh_f16",
+    "name": "vmlsq_laneq_s16",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Hm"
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulh_lane_f16",
+    "name": "vmlsq_laneq_s32",
     "arguments": [
-      "float16_t a",
-      "float16x4_t v",
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
         "maximum": 3
       },
       "v": {
-        "register": "Vm.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -56918,24 +259316,28 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulh_laneq_f16",
+    "name": "vmlsq_laneq_u16",
     "arguments": [
-      "float16_t a",
-      "float16x8_t v",
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
       },
       "lane": {
         "minimum": 0,
@@ -56950,31 +259352,35 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_lane_s16",
+    "name": "vmlsq_laneq_u32",
     "arguments": [
-      "int16x8_t a",
-      "int16x4_t v",
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
         "maximum": 3
       },
       "v": {
-        "register": "Vm.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -56982,358 +259388,393 @@
     ],
     "instructions": [
       [
-        "SMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_lane_s32",
+    "name": "vmlsq_n_f32",
     "arguments": [
-      "int32x4_t a",
-      "int32x2_t v",
-      "const int lane"
+      "float32x4_t a",
+      "float32x4_t b",
+      "float32_t c"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "N/A"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "b": {
+        "register": "N/A"
       },
-      "v": {
-        "register": "Vm.2S"
+      "c": {
+        "register": "N/A"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "result"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_lane_u16",
+    "name": "vmlsq_n_s16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x4_t v",
-      "const int lane"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "b": {
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vm.4H"
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_lane_u32",
+    "name": "vmlsq_n_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x2_t v",
-      "const int lane"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "b": {
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vm.2S"
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_laneq_s16",
+    "name": "vmlsq_n_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16_t c"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vm.8H"
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_laneq_s32",
+    "name": "vmlsq_n_u32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32_t c"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "b": {
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vm.4S"
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_laneq_u16",
+    "name": "vmlsq_s16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t v",
-      "const int lane"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Vn.8H"
       },
-      "v": {
+      "c": {
         "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_laneq_u32",
+    "name": "vmlsq_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t v",
-      "const int lane"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "b": {
+        "register": "Vn.4S"
       },
-      "v": {
+      "c": {
         "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_n_s16",
+    "name": "vmlsq_s8",
     "arguments": [
-      "int16x8_t a",
-      "int16_t b"
+      "int8x16_t a",
+      "int8x16_t b",
+      "int8x16_t c"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.16B"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_n_s32",
+    "name": "vmlsq_u16",
     "arguments": [
-      "int32x4_t a",
-      "int32_t b"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "uint16x8_t c"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_n_u16",
+    "name": "vmlsq_u32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16_t b"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_n_u32",
+    "name": "vmlsq_u8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32_t b"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "uint8x16_t c"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.16B"
       },
       "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.16B"
+      },
+      "c": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "MLS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_p64",
+    "name": "vmmlaq_s32",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "int32x4_t r",
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.16B"
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -57342,19 +259783,20 @@
     ],
     "instructions": [
       [
-        "PMULL2"
+        "SMMLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_p8",
+    "name": "vmmlaq_u32",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "uint32x4_t r",
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -57362,200 +259804,231 @@
       },
       "b": {
         "register": "Vm.16B"
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "PMULL2"
+        "UMMLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_s16",
+    "name": "vmov_n_f16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float16_t value"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_s32",
+    "name": "vmov_n_f32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float32_t value"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_s8",
+    "name": "vmov_n_f64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "float64_t value"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vmov_n_p16",
+    "arguments": [
+      "poly16_t value"
+    ],
+    "return_type": {
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "DUP"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vmov_n_p8",
+    "arguments": [
+      "poly8_t value"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL2"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_u16",
+    "name": "vmov_n_s16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int16_t value"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_u32",
+    "name": "vmov_n_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int32_t value"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_high_u8",
+    "name": "vmov_n_s64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int64_t value"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL2"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_lane_s16",
+    "name": "vmov_n_s8",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t v",
-      "const int lane"
+      "int8_t value"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -57565,31 +260038,22 @@
     ],
     "instructions": [
       [
-        "SMULL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_lane_s32",
+    "name": "vmov_n_u16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t v",
-      "const int lane"
+      "uint16_t value"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -57599,31 +260063,22 @@
     ],
     "instructions": [
       [
-        "SMULL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_lane_u16",
+    "name": "vmov_n_u32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t v",
-      "const int lane"
+      "uint32_t value"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -57633,31 +260088,22 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_lane_u32",
+    "name": "vmov_n_u64",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t v",
-      "const int lane"
+      "uint64_t value"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -57667,63 +260113,47 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_laneq_s16",
+    "name": "vmov_n_u8",
     "arguments": [
-      "int16x4_t a",
-      "int16x8_t v",
-      "const int lane"
+      "uint8_t value"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_laneq_s32",
+    "name": "vmovl_high_s16",
     "arguments": [
-      "int32x2_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -57731,31 +260161,22 @@
     ],
     "instructions": [
       [
-        "SMULL"
+        "SSHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_laneq_u16",
+    "name": "vmovl_high_s32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x8_t v",
-      "const int lane"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -57763,31 +260184,22 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "SSHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_laneq_u32",
+    "name": "vmovl_high_s8",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x4_t v",
-      "const int lane"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -57795,113 +260207,91 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "SSHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_n_s16",
+    "name": "vmovl_high_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16_t b"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL"
+        "USHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_n_s32",
+    "name": "vmovl_high_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32_t b"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMULL"
+        "USHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_n_u16",
+    "name": "vmovl_high_u8",
     "arguments": [
-      "uint16x4_t a",
-      "uint16_t b"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMULL"
+        "USHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_n_u32",
+    "name": "vmovl_s16",
     "arguments": [
-      "uint32x2_t a",
-      "uint32_t b"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -57911,54 +260301,47 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "SSHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_p64",
+    "name": "vmovl_s32",
     "arguments": [
-      "poly64_t a",
-      "poly64_t b"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.1D"
-      },
-      "b": {
-        "register": "Vm.1D"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "PMULL"
+        "SSHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_p8",
+    "name": "vmovl_s8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -57968,26 +260351,22 @@
     ],
     "instructions": [
       [
-        "PMULL"
+        "SSHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_s16",
+    "name": "vmovl_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -57997,26 +260376,22 @@
     ],
     "instructions": [
       [
-        "SMULL"
+        "USHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_s32",
+    "name": "vmovl_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -58026,26 +260401,22 @@
     ],
     "instructions": [
       [
-        "SMULL"
+        "USHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_s8",
+    "name": "vmovl_u8",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -58055,26 +260426,26 @@
     ],
     "instructions": [
       [
-        "SMULL"
+        "USHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_u16",
+    "name": "vmovn_high_s16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "int8x8_t r",
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.4H"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -58084,26 +260455,26 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "XTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_u32",
+    "name": "vmovn_high_s32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "int16x4_t r",
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.2S"
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -58113,26 +260484,26 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "XTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmull_u8",
+    "name": "vmovn_high_s64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "int32x2_t r",
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -58142,54 +260513,55 @@
     ],
     "instructions": [
       [
-        "UMULL"
+        "XTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_f16",
+    "name": "vmovn_high_u16",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "uint8x8_t r",
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "XTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_f32",
+    "name": "vmovn_high_u32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "uint16x4_t r",
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -58199,91 +260571,76 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "XTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_f64",
+    "name": "vmovn_high_u64",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "uint32x2_t r",
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
       },
-      "b": {
-        "register": "Vm.2D"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "XTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_f16",
+    "name": "vmovn_s16",
     "arguments": [
-      "float16x8_t a",
-      "float16x4_t v",
-      "const int lane"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "XTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_f32",
+    "name": "vmovn_s32",
     "arguments": [
-      "float32x4_t a",
-      "float32x2_t v",
-      "const int lane"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -58293,63 +260650,47 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "XTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_f64",
+    "name": "vmovn_s64",
     "arguments": [
-      "float64x2_t a",
-      "float64x1_t v",
-      "const int lane"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "v": {
-        "register": "Vm.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "XTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_s16",
+    "name": "vmovn_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16x4_t v",
-      "const int lane"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -58359,31 +260700,22 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "XTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_s32",
+    "name": "vmovn_u32",
     "arguments": [
-      "int32x4_t a",
-      "int32x2_t v",
-      "const int lane"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -58393,31 +260725,22 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "XTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_u16",
+    "name": "vmovn_u64",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x4_t v",
-      "const int lane"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -58427,31 +260750,22 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "XTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_lane_u32",
+    "name": "vmovq_n_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x2_t v",
-      "const int lane"
+      "float16_t value"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -58461,63 +260775,47 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_f16",
+    "name": "vmovq_n_f32",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t v",
-      "const int lane"
+      "float32_t value"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_f32",
+    "name": "vmovq_n_f64",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t v",
-      "const int lane"
+      "float64_t value"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -58525,214 +260823,172 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_f64",
+    "name": "vmovq_n_p16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t v",
-      "const int lane"
+      "poly16_t value"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2D"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_s16",
+    "name": "vmovq_n_p8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t v",
-      "const int lane"
+      "poly8_t value"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_s32",
+    "name": "vmovq_n_s16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int16_t value"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_u16",
+    "name": "vmovq_n_s32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t v",
-      "const int lane"
+      "int32_t value"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_laneq_u32",
+    "name": "vmovq_n_s64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t v",
-      "const int lane"
+      "int64_t value"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_f16",
+    "name": "vmovq_n_s8",
     "arguments": [
-      "float16x8_t a",
-      "float16_t n"
+      "int8_t value"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "register": "Vm.H[0]"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_f32",
+    "name": "vmovq_n_u16",
     "arguments": [
-      "float32x4_t a",
-      "float32_t b"
+      "uint16_t value"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -58742,53 +260998,47 @@
     ],
     "instructions": [
       [
-        "FMUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_f64",
+    "name": "vmovq_n_u32",
     "arguments": [
-      "float64x2_t a",
-      "float64_t b"
+      "uint32_t value"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.D[0]"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_s16",
+    "name": "vmovq_n_u64",
     "arguments": [
-      "int16x8_t a",
-      "int16_t b"
+      "uint64_t value"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.H[0]"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -58798,26 +261048,22 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_s32",
+    "name": "vmovq_n_u8",
     "arguments": [
-      "int32x4_t a",
-      "int32_t b"
+      "uint8_t value"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+      "value": {
+        "register": "rn"
       }
     },
     "Architectures": [
@@ -58827,55 +261073,54 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "DUP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_u16",
+    "name": "vmul_f16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16_t b"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_n_u32",
+    "name": "vmul_f32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32_t b"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.S[0]"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -58885,84 +261130,91 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_p8",
+    "name": "vmul_f64",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "PMUL"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_s16",
+    "name": "vmul_lane_f16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float16x4_t a",
+      "float16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_s32",
+    "name": "vmul_lane_f32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float32x2_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -58972,55 +261224,63 @@
     ],
     "instructions": [
       [
-        "MUL"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_s8",
+    "name": "vmul_lane_f64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "float64x1_t a",
+      "float64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MUL"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_u16",
+    "name": "vmul_lane_s16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int16x4_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vm.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -59036,20 +261296,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_u32",
+    "name": "vmul_lane_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int32x2_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
-      "b": {
-        "register": "Vm.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -59065,20 +261330,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulq_u8",
+    "name": "vmul_lane_u16",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint16x4_t a",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -59094,18 +261364,18 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmuls_lane_f32",
+    "name": "vmul_lane_u32",
     "arguments": [
-      "float32_t a",
-      "float32x2_t v",
+      "uint32x2_t a",
+      "uint32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.2S"
       },
       "lane": {
         "minimum": 0,
@@ -59116,35 +261386,37 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMUL"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmuls_laneq_f32",
+    "name": "vmul_laneq_f16",
     "arguments": [
-      "float32_t a",
-      "float32x4_t v",
+      "float16x4_t a",
+      "float16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.4H"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -59158,20 +261430,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_f16",
+    "name": "vmul_laneq_f32",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "float32x2_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4H"
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -59179,26 +261456,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_f32",
+    "name": "vmul_laneq_f64",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "float64x1_t a",
+      "float64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -59206,26 +261488,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_f64",
+    "name": "vmul_laneq_s16",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "int16x4_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Dm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -59233,31 +261520,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_lane_f16",
+    "name": "vmul_laneq_s32",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t v",
+      "int32x2_t a",
+      "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2S"
       },
       "lane": {
         "minimum": 0,
         "maximum": 3
       },
       "v": {
-        "register": "Vm.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -59265,31 +261552,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_lane_f32",
+    "name": "vmul_laneq_u16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t v",
+      "uint16x4_t a",
+      "uint16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4H"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 7
       },
       "v": {
-        "register": "Vm.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -59297,31 +261584,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_lane_f64",
+    "name": "vmul_laneq_u32",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t v",
+      "uint32x2_t a",
+      "uint32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2S"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 3
       },
       "v": {
-        "register": "Vm.1D"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -59329,17 +261616,16 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_laneq_f16",
+    "name": "vmul_n_f16",
     "arguments": [
       "float16x4_t a",
-      "float16x8_t v",
-      "const int lane"
+      "float16_t n"
     ],
     "return_type": {
       "value": "float16x4_t"
@@ -59348,30 +261634,26 @@
       "a": {
         "register": "Vn.4H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+      "n": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_laneq_f32",
+    "name": "vmul_n_f32",
     "arguments": [
       "float32x2_t a",
-      "float32x4_t v",
-      "const int lane"
+      "float32_t b"
     ],
     "return_type": {
       "value": "float32x2_t"
@@ -59380,30 +261662,27 @@
       "a": {
         "register": "Vn.2S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_laneq_f64",
+    "name": "vmul_n_f64",
     "arguments": [
       "float64x1_t a",
-      "float64x2_t v",
-      "const int lane"
+      "float64_t b"
     ],
     "return_type": {
       "value": "float64x1_t"
@@ -59412,12 +261691,8 @@
       "a": {
         "register": "Dn"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2D"
+      "b": {
+        "register": "Vm.D[0]"
       }
     },
     "Architectures": [
@@ -59425,353 +261700,350 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulx_n_f16",
+    "name": "vmul_n_s16",
     "arguments": [
-      "float16x4_t a",
-      "float16_t n"
+      "int16x4_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
       },
-      "n": {
+      "b": {
         "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxd_f64",
+    "name": "vmul_n_s32",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "int32x2_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxd_lane_f64",
+    "name": "vmul_n_u16",
     "arguments": [
-      "float64_t a",
-      "float64x1_t v",
-      "const int lane"
+      "uint16x4_t a",
+      "uint16_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+        "register": "Vn.4H"
       },
-      "v": {
-        "register": "Vm.1D"
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxd_laneq_f64",
+    "name": "vmul_n_u32",
     "arguments": [
-      "float64_t a",
-      "float64x2_t v",
-      "const int lane"
+      "uint32x2_t a",
+      "uint32_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vn.2S"
       },
-      "v": {
-        "register": "Vm.2D"
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxh_f16",
+    "name": "vmul_p8",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "poly8x8_t a",
+      "poly8x8_t b"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Hm"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "PMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxh_lane_f16",
+    "name": "vmul_s16",
     "arguments": [
-      "float16_t a",
-      "float16x4_t v",
-      "const int lane"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.4H"
       },
-      "v": {
+      "b": {
         "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxh_laneq_f16",
+    "name": "vmul_s32",
     "arguments": [
-      "float16_t a",
-      "float16x8_t v",
-      "const int lane"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.2S"
       },
-      "v": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_f16",
+    "name": "vmul_s8",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_f32",
+    "name": "vmul_u16",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_f64",
+    "name": "vmul_u32",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_lane_f16",
+    "name": "vmul_u8",
     "arguments": [
-      "float16x8_t a",
-      "float16x4_t v",
-      "const int lane"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.8B"
       },
-      "v": {
-        "register": "Vm.4H"
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_lane_f32",
+    "name": "vmuld_lane_f64",
     "arguments": [
-      "float32x4_t a",
-      "float32x2_t v",
+      "float64_t a",
+      "float64x1_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Dn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "v": {
-        "register": "Vm.2S"
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
@@ -59779,31 +262051,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_lane_f64",
+    "name": "vmuld_laneq_f64",
     "arguments": [
-      "float64x2_t a",
-      "float64x1_t v",
+      "float64_t a",
+      "float64x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Dn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 1
       },
       "v": {
-        "register": "Vm.1D"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -59811,63 +262083,59 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_laneq_f16",
+    "name": "vmulh_f16",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t v",
-      "const int lane"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Hn"
       },
-      "v": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_laneq_f32",
+    "name": "vmulh_lane_f16",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t v",
+      "float16_t a",
+      "float16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Hn"
       },
       "lane": {
         "minimum": 0,
         "maximum": 3
       },
       "v": {
-        "register": "Vm.4S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -59875,31 +262143,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_laneq_f64",
+    "name": "vmulh_laneq_f16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t v",
+      "float16_t a",
+      "float16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Hn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 7
       },
       "v": {
-        "register": "Vm.2D"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -59907,26 +262175,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxq_n_f16",
+    "name": "vmull_high_lane_s16",
     "arguments": [
-      "float16x8_t a",
-      "float16_t n"
+      "int16x8_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
       },
-      "n": {
-        "register": "Vm.H[0]"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -59934,26 +262207,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxs_f32",
+    "name": "vmull_high_lane_s32",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "int32x4_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Sm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -59961,31 +262239,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxs_lane_f32",
+    "name": "vmull_high_lane_u16",
     "arguments": [
-      "float32_t a",
-      "float32x2_t v",
+      "uint16x8_t a",
+      "uint16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.8H"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "v": {
-        "register": "Vm.2S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -59993,31 +262271,31 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmulxs_laneq_f32",
+    "name": "vmull_high_lane_u32",
     "arguments": [
-      "float32_t a",
-      "float32x4_t v",
+      "uint32x4_t a",
+      "uint32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "v": {
-        "register": "Vm.4S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -60025,444 +262303,518 @@
     ],
     "instructions": [
       [
-        "FMULX"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_p8",
+    "name": "vmull_high_laneq_s16",
     "arguments": [
-      "poly8x8_t a"
+      "int16x8_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_s16",
+    "name": "vmull_high_laneq_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x4_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_s32",
+    "name": "vmull_high_laneq_u16",
     "arguments": [
-      "int32x2_t a"
+      "uint16x8_t a",
+      "uint16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_s8",
+    "name": "vmull_high_laneq_u32",
     "arguments": [
-      "int8x8_t a"
+      "uint32x4_t a",
+      "uint32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_u16",
+    "name": "vmull_high_n_s16",
     "arguments": [
-      "uint16x4_t a"
+      "int16x8_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_u32",
+    "name": "vmull_high_n_s32",
     "arguments": [
-      "uint32x2_t a"
+      "int32x4_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvn_u8",
+    "name": "vmull_high_n_u16",
     "arguments": [
-      "uint8x8_t a"
+      "uint16x8_t a",
+      "uint16_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_p8",
+    "name": "vmull_high_n_u32",
     "arguments": [
-      "poly8x16_t a"
+      "uint32x4_t a",
+      "uint32_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_s16",
+    "name": "vmull_high_p64",
     "arguments": [
-      "int16x8_t a"
+      "poly64x2_t a",
+      "poly64x2_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "PMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_s32",
+    "name": "vmull_high_p8",
     "arguments": [
-      "int32x4_t a"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "PMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_s8",
+    "name": "vmull_high_s16",
     "arguments": [
-      "int8x16_t a"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_u16",
+    "name": "vmull_high_s32",
     "arguments": [
-      "uint16x8_t a"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_u32",
+    "name": "vmull_high_s8",
     "arguments": [
-      "uint32x4_t a"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "SMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vmvnq_u8",
+    "name": "vmull_high_u16",
     "arguments": [
-      "uint8x16_t a"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MVN"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_f16",
+    "name": "vmull_high_u32",
     "arguments": [
-      "float16x4_t a"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FNEG"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_f32",
+    "name": "vmull_high_u8",
     "arguments": [
-      "float32x2_t a"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FNEG"
+        "UMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_f64",
+    "name": "vmull_lane_s16",
     "arguments": [
-      "float64x1_t a"
+      "int16x4_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FNEG"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_s16",
+    "name": "vmull_lane_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x2_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -60472,22 +262824,31 @@
     ],
     "instructions": [
       [
-        "NEG"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_s32",
+    "name": "vmull_lane_u16",
     "arguments": [
-      "int32x2_t a"
+      "uint16x4_t a",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -60497,70 +262858,97 @@
     ],
     "instructions": [
       [
-        "NEG"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_s64",
+    "name": "vmull_lane_u32",
     "arguments": [
-      "int64x1_t a"
+      "uint32x2_t a",
+      "uint32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NEG"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vneg_s8",
+    "name": "vmull_laneq_s16",
     "arguments": [
-      "int8x8_t a"
+      "int16x4_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NEG"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegd_s64",
+    "name": "vmull_laneq_s32",
     "arguments": [
-      "int64_t a"
+      "int32x2_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -60568,70 +262956,90 @@
     ],
     "instructions": [
       [
-        "NEG"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegh_f16",
+    "name": "vmull_laneq_u16",
     "arguments": [
-      "float16_t a"
+      "uint16x4_t a",
+      "uint16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FNEG"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_f16",
+    "name": "vmull_laneq_u32",
     "arguments": [
-      "float16x8_t a"
+      "uint32x2_t a",
+      "uint32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FNEG"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_f32",
+    "name": "vmull_n_s16",
     "arguments": [
-      "float32x4_t a"
+      "int16x4_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -60641,45 +263049,55 @@
     ],
     "instructions": [
       [
-        "FNEG"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_f64",
+    "name": "vmull_n_s32",
     "arguments": [
-      "float64x2_t a"
+      "int32x2_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FNEG"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_s16",
+    "name": "vmull_n_u16",
     "arguments": [
-      "int16x8_t a"
+      "uint16x4_t a",
+      "uint16_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -60689,22 +263107,26 @@
     ],
     "instructions": [
       [
-        "NEG"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_s32",
+    "name": "vmull_n_u32",
     "arguments": [
-      "int32x4_t a"
+      "uint32x2_t a",
+      "uint32_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -60714,45 +263136,54 @@
     ],
     "instructions": [
       [
-        "NEG"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_s64",
+    "name": "vmull_p64",
     "arguments": [
-      "int64x2_t a"
+      "poly64_t a",
+      "poly64_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.1D"
+      },
+      "b": {
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NEG"
+        "PMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vnegq_s8",
+    "name": "vmull_p8",
     "arguments": [
-      "int8x16_t a"
+      "poly8x8_t a",
+      "poly8x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -60762,26 +263193,26 @@
     ],
     "instructions": [
       [
-        "NEG"
+        "PMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_s16",
+    "name": "vmull_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -60791,26 +263222,26 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_s32",
+    "name": "vmull_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -60820,19 +263251,19 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_s64",
+    "name": "vmull_s8",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -60849,26 +263280,26 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "SMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_s8",
+    "name": "vmull_u16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -60878,26 +263309,26 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_u16",
+    "name": "vmull_u32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -60907,19 +263338,19 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_u32",
+    "name": "vmull_u8",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -60936,55 +263367,54 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "UMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_u64",
+    "name": "vmulq_f16",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORN"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorn_u8",
+    "name": "vmulq_f32",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -60994,84 +263424,91 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_s16",
+    "name": "vmulq_f64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORN"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_s32",
+    "name": "vmulq_lane_f16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float16x8_t a",
+      "float16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORN"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_s64",
+    "name": "vmulq_lane_f32",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "float32x4_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -61081,55 +263518,63 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_s8",
+    "name": "vmulq_lane_f64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "float64x2_t a",
+      "float64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORN"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_u16",
+    "name": "vmulq_lane_s16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int16x8_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -61139,26 +263584,31 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_u32",
+    "name": "vmulq_lane_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int32x4_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -61168,26 +263618,31 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_u64",
+    "name": "vmulq_lane_u16",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint16x8_t a",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -61197,26 +263652,31 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vornq_u8",
+    "name": "vmulq_lane_u32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint32x4_t a",
+      "uint32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -61226,258 +263686,278 @@
     ],
     "instructions": [
       [
-        "ORN"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_s16",
+    "name": "vmulq_laneq_f16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "float16x8_t a",
+      "float16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_s32",
+    "name": "vmulq_laneq_f32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "float32x4_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_s64",
+    "name": "vmulq_laneq_f64",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "float64x2_t a",
+      "float64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_s8",
+    "name": "vmulq_laneq_s16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "int16x8_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_u16",
+    "name": "vmulq_laneq_s32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "int32x4_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_u32",
+    "name": "vmulq_laneq_u16",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "uint16x8_t a",
+      "uint16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_u64",
+    "name": "vmulq_laneq_u32",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "uint32x4_t a",
+      "uint32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorr_u8",
+    "name": "vmulq_n_f16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "float16x8_t a",
+      "float16_t n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "n": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_s16",
+    "name": "vmulq_n_f32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float32x4_t a",
+      "float32_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -61487,55 +263967,53 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_s32",
+    "name": "vmulq_n_f64",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float64x2_t a",
+      "float64_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.D[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ORR"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_s64",
+    "name": "vmulq_n_s16",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int16x8_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -61545,26 +264023,26 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_s8",
+    "name": "vmulq_n_s32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int32x4_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -61574,26 +264052,26 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_u16",
+    "name": "vmulq_n_u16",
     "arguments": [
       "uint16x8_t a",
-      "uint16x8_t b"
+      "uint16_t b"
     ],
     "return_type": {
       "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -61603,26 +264081,26 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_u32",
+    "name": "vmulq_n_u32",
     "arguments": [
       "uint32x4_t a",
-      "uint32x4_t b"
+      "uint32_t b"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -61632,19 +264110,19 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_u64",
+    "name": "vmulq_p8",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -61661,26 +264139,26 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "PMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vorrq_u8",
+    "name": "vmulq_s16",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -61690,26 +264168,26 @@
     ],
     "instructions": [
       [
-        "ORR"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadal_s16",
+    "name": "vmulq_s32",
     "arguments": [
-      "int32x2_t a",
-      "int16x4_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -61719,26 +264197,26 @@
     ],
     "instructions": [
       [
-        "SADALP"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadal_s32",
+    "name": "vmulq_s8",
     "arguments": [
-      "int64x1_t a",
-      "int32x2_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.2S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -61748,26 +264226,26 @@
     ],
     "instructions": [
       [
-        "SADALP"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadal_s8",
+    "name": "vmulq_u16",
     "arguments": [
-      "int16x4_t a",
-      "int8x8_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.8B"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -61777,26 +264255,26 @@
     ],
     "instructions": [
       [
-        "SADALP"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadal_u16",
+    "name": "vmulq_u32",
     "arguments": [
-      "uint32x2_t a",
-      "uint16x4_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -61806,26 +264284,26 @@
     ],
     "instructions": [
       [
-        "UADALP"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadal_u32",
+    "name": "vmulq_u8",
     "arguments": [
-      "uint64x1_t a",
-      "uint32x2_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.2S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -61835,456 +264313,481 @@
     ],
     "instructions": [
       [
-        "UADALP"
+        "MUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadal_u8",
+    "name": "vmuls_lane_f32",
     "arguments": [
-      "uint16x4_t a",
-      "uint8x8_t b"
+      "float32_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Sn"
       },
-      "b": {
-        "register": "Vn.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADALP"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadalq_s16",
+    "name": "vmuls_laneq_f32",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b"
+      "float32_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Sn"
       },
-      "b": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADALP"
+        "FMUL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadalq_s32",
+    "name": "vmulx_f16",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.4S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADALP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadalq_s8",
+    "name": "vmulx_f32",
     "arguments": [
-      "int16x8_t a",
-      "int8x16_t b"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.16B"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADALP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadalq_u16",
+    "name": "vmulx_f64",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.8H"
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADALP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadalq_u32",
+    "name": "vmulx_lane_f16",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b"
+      "float16x4_t a",
+      "float16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADALP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadalq_u8",
+    "name": "vmulx_lane_f32",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x16_t b"
+      "float32x2_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.2S"
       },
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADALP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_f16",
+    "name": "vmulx_lane_f64",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "float64x1_t a",
+      "float64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_f32",
+    "name": "vmulx_laneq_f16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "float16x4_t a",
+      "float16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vm.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_s16",
+    "name": "vmulx_laneq_f32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "float32x2_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2S"
       },
-      "b": {
-        "register": "Vm.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_s32",
+    "name": "vmulx_laneq_f64",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "float64x1_t a",
+      "float64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_s8",
+    "name": "vmulx_n_f16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "float16x4_t a",
+      "float16_t n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vm.8B"
+      "n": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_u16",
+    "name": "vmulxd_f64",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "float64_t a",
+      "float64_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_u32",
+    "name": "vmulxd_lane_f64",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "float64_t a",
+      "float64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadd_u8",
+    "name": "vmulxd_laneq_f64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "float64_t a",
+      "float64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddd_f64",
+    "name": "vmulxh_f16",
     "arguments": [
-      "float64x2_t a"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -62292,22 +264795,31 @@
     ],
     "instructions": [
       [
-        "FADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddd_s64",
+    "name": "vmulxh_lane_f16",
     "arguments": [
-      "int64x2_t a"
+      "float16_t a",
+      "float16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Hn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -62315,22 +264827,31 @@
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddd_u64",
+    "name": "vmulxh_laneq_f16",
     "arguments": [
-      "uint64x2_t a"
+      "float16_t a",
+      "float16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Hn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -62338,326 +264859,390 @@
     ],
     "instructions": [
       [
-        "ADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddl_s16",
+    "name": "vmulxq_f16",
     "arguments": [
-      "int16x4_t a"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddl_s32",
+    "name": "vmulxq_f32",
     "arguments": [
-      "int32x2_t a"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddl_s8",
+    "name": "vmulxq_f64",
     "arguments": [
-      "int8x8_t a"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddl_u16",
+    "name": "vmulxq_lane_f16",
     "arguments": [
-      "uint16x4_t a"
+      "float16x8_t a",
+      "float16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddl_u32",
+    "name": "vmulxq_lane_f32",
     "arguments": [
-      "uint32x2_t a"
+      "float32x4_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddl_u8",
+    "name": "vmulxq_lane_f64",
     "arguments": [
-      "uint8x8_t a"
+      "float64x2_t a",
+      "float64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vm.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddlq_s16",
+    "name": "vmulxq_laneq_f16",
     "arguments": [
-      "int16x8_t a"
+      "float16x8_t a",
+      "float16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddlq_s32",
+    "name": "vmulxq_laneq_f32",
     "arguments": [
-      "int32x4_t a"
+      "float32x4_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddlq_s8",
+    "name": "vmulxq_laneq_f64",
     "arguments": [
-      "int8x16_t a"
+      "float64x2_t a",
+      "float64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddlq_u16",
+    "name": "vmulxq_n_f16",
     "arguments": [
-      "uint16x8_t a"
+      "float16x8_t a",
+      "float16_t n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
+      },
+      "n": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddlq_u32",
+    "name": "vmulxs_f32",
     "arguments": [
-      "uint32x4_t a"
+      "float32_t a",
+      "float32_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddlq_u8",
+    "name": "vmulxs_lane_f32",
     "arguments": [
-      "uint8x16_t a"
+      "float32_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UADDLP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_f16",
+    "name": "vmulxs_laneq_f32",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "float32_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Sn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -62665,347 +265250,322 @@
     ],
     "instructions": [
       [
-        "FADDP"
+        "FMULX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_f32",
+    "name": "vmvn_p8",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_f64",
+    "name": "vmvn_s16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_s16",
+    "name": "vmvn_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_s32",
+    "name": "vmvn_s8",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_s64",
+    "name": "vmvn_u16",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_s8",
+    "name": "vmvn_u32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_u16",
+    "name": "vmvn_u8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_u32",
+    "name": "vmvnq_p8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_u64",
+    "name": "vmvnq_s16",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpaddq_u8",
+    "name": "vmvnq_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpadds_f32",
+    "name": "vmvnq_s8",
     "arguments": [
-      "float32x2_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FADDP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_f16",
+    "name": "vmvnq_u16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_f32",
+    "name": "vmvnq_u32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -63015,26 +265575,22 @@
     ],
     "instructions": [
       [
-        "FMAXP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_s16",
+    "name": "vmvnq_u8",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -63044,55 +265600,46 @@
     ],
     "instructions": [
       [
-        "SMAXP"
+        "MVN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_s32",
+    "name": "vneg_f16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMAXP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_s8",
+    "name": "vneg_f32",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -63102,55 +265649,45 @@
     ],
     "instructions": [
       [
-        "SMAXP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_u16",
+    "name": "vneg_f64",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMAXP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_u32",
+    "name": "vneg_s16",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -63160,26 +265697,22 @@
     ],
     "instructions": [
       [
-        "UMAXP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmax_u8",
+    "name": "vneg_s32",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -63189,26 +265722,22 @@
     ],
     "instructions": [
       [
-        "UMAXP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnm_f16",
+    "name": "vneg_s64",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Dn"
       }
     },
     "Architectures": [
@@ -63216,53 +265745,47 @@
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnm_f32",
+    "name": "vneg_s8",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnmq_f16",
+    "name": "vnegd_s64",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int64_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Dn"
       }
     },
     "Architectures": [
@@ -63270,99 +265793,95 @@
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnmq_f32",
+    "name": "vnegh_f16",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Hn"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnmq_f64",
+    "name": "vnegq_f16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnmqd_f64",
+    "name": "vnegq_f32",
     "arguments": [
-      "float64x2_t a"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxnms_f32",
+    "name": "vnegq_f64",
     "arguments": [
-      "float32x2_t a"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -63370,80 +265889,72 @@
     ],
     "instructions": [
       [
-        "FMAXNMP"
+        "FNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_f16",
+    "name": "vnegq_s16",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_f32",
+    "name": "vnegq_s32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_f64",
+    "name": "vnegq_s64",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -63451,262 +265962,283 @@
     ],
     "instructions": [
       [
-        "FMAXP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_s16",
+    "name": "vnegq_s8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMAXP"
+        "NEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_s32",
+    "name": "vorn_s16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_s8",
+    "name": "vorn_s32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_u16",
+    "name": "vorn_s64",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_u32",
+    "name": "vorn_s8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxq_u8",
+    "name": "vorn_u16",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxqd_f64",
+    "name": "vorn_u32",
     "arguments": [
-      "float64x2_t a"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmaxs_f32",
+    "name": "vorn_u64",
     "arguments": [
-      "float32x2_t a"
+      "uint64x1_t a",
+      "uint64x1_t b"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMAXP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_f16",
+    "name": "vorn_u8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_f32",
+    "name": "vornq_s16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63716,26 +266248,26 @@
     ],
     "instructions": [
       [
-        "FMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_s16",
+    "name": "vornq_s32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63745,26 +266277,26 @@
     ],
     "instructions": [
       [
-        "SMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_s32",
+    "name": "vornq_s64",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63774,26 +266306,26 @@
     ],
     "instructions": [
       [
-        "SMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_s8",
+    "name": "vornq_s8",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63803,26 +266335,26 @@
     ],
     "instructions": [
       [
-        "SMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_u16",
+    "name": "vornq_u16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63832,26 +266364,26 @@
     ],
     "instructions": [
       [
-        "UMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_u32",
+    "name": "vornq_u32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63861,26 +266393,26 @@
     ],
     "instructions": [
       [
-        "UMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmin_u8",
+    "name": "vornq_u64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -63890,329 +266422,361 @@
     ],
     "instructions": [
       [
-        "UMINP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnm_f16",
+    "name": "vornq_u8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnm_f32",
+    "name": "vorr_s16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnmq_f16",
+    "name": "vorr_s32",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnmq_f32",
+    "name": "vorr_s64",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnmq_f64",
+    "name": "vorr_s8",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnmqd_f64",
+    "name": "vorr_u16",
     "arguments": [
-      "float64x2_t a"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminnms_f32",
+    "name": "vorr_u32",
     "arguments": [
-      "float32x2_t a"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINNMP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_f16",
+    "name": "vorr_u64",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "uint64x1_t a",
+      "uint64x1_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_f32",
+    "name": "vorr_u8",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_f64",
+    "name": "vorrq_s16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_s16",
+    "name": "vorrq_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_s32",
+    "name": "vorrq_s64",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_s8",
+    "name": "vorrq_s8",
     "arguments": [
       "int8x16_t a",
       "int8x16_t b"
@@ -64229,17 +266793,19 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_u16",
+    "name": "vorrq_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b"
@@ -64249,24 +266815,26 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_u32",
+    "name": "vorrq_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b"
@@ -64276,30 +266844,32 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminq_u8",
+    "name": "vorrq_u64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -64310,72 +266880,90 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpminqd_f64",
+    "name": "vorrq_u8",
     "arguments": [
-      "float64x2_t a"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "ORR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vpmins_f32",
+    "name": "vpadal_s16",
     "arguments": [
-      "float32x2_t a"
+      "int32x2_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FMINP"
+        "SADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabs_s16",
+    "name": "vpadal_s32",
     "arguments": [
-      "int16x4_t a"
+      "int64x1_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.1D"
+      },
+      "b": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -64385,22 +266973,26 @@
     ],
     "instructions": [
       [
-        "SQABS"
+        "SADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabs_s32",
+    "name": "vpadal_s8",
     "arguments": [
-      "int32x2_t a"
+      "int16x4_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -64410,45 +267002,55 @@
     ],
     "instructions": [
       [
-        "SQABS"
+        "SADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabs_s64",
+    "name": "vpadal_u16",
     "arguments": [
-      "int64x1_t a"
+      "uint32x2_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQABS"
+        "UADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabs_s8",
+    "name": "vpadal_u32",
     "arguments": [
-      "int8x8_t a"
+      "uint64x1_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.1D"
+      },
+      "b": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -64458,91 +267060,113 @@
     ],
     "instructions": [
       [
-        "SQABS"
+        "UADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsb_s8",
+    "name": "vpadal_u8",
     "arguments": [
-      "int8_t a"
+      "uint16x4_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQABS"
+        "UADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsd_s64",
+    "name": "vpadalq_s16",
     "arguments": [
-      "int64_t a"
+      "int32x4_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQABS"
+        "SADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsh_s16",
+    "name": "vpadalq_s32",
     "arguments": [
-      "int16_t a"
+      "int64x2_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQABS"
+        "SADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsq_s16",
+    "name": "vpadalq_s8",
     "arguments": [
-      "int16x8_t a"
+      "int16x8_t a",
+      "int8x16_t b"
     ],
     "return_type": {
       "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -64552,22 +267176,26 @@
     ],
     "instructions": [
       [
-        "SQABS"
+        "SADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsq_s32",
+    "name": "vpadalq_u16",
     "arguments": [
-      "int32x4_t a"
+      "uint32x4_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -64577,44 +267205,54 @@
     ],
     "instructions": [
       [
-        "SQABS"
+        "UADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsq_s64",
+    "name": "vpadalq_u32",
     "arguments": [
-      "int64x2_t a"
+      "uint64x2_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQABS"
+        "UADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabsq_s8",
+    "name": "vpadalq_u8",
     "arguments": [
-      "int8x16_t a"
+      "uint16x8_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
         "register": "Vn.16B"
       }
     },
@@ -64625,49 +267263,54 @@
     ],
     "instructions": [
       [
-        "SQABS"
+        "UADALP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqabss_s32",
+    "name": "vpadd_f16",
     "arguments": [
-      "int32_t a"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQABS"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_s16",
+    "name": "vpadd_f32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -64677,26 +267320,26 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_s32",
+    "name": "vpadd_s16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -64706,26 +267349,26 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_s64",
+    "name": "vpadd_s32",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -64735,13 +267378,13 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_s8",
+    "name": "vpadd_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
@@ -64764,13 +267407,13 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_u16",
+    "name": "vpadd_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
@@ -64793,13 +267436,13 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_u32",
+    "name": "vpadd_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
@@ -64822,26 +267465,26 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_u64",
+    "name": "vpadd_u8",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -64851,55 +267494,45 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadd_u8",
+    "name": "vpaddd_f64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQADD"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddb_s8",
+    "name": "vpaddd_s64",
     "arguments": [
-      "int8_t a",
-      "int8_t b"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
-      },
-      "b": {
-        "register": "Bm"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -64907,26 +267540,22 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddb_u8",
+    "name": "vpaddd_u64",
     "arguments": [
-      "uint8_t a",
-      "uint8_t b"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
-      },
-      "b": {
-        "register": "Bm"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -64934,134 +267563,122 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddd_s64",
+    "name": "vpaddl_s16",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQADD"
+        "SADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddd_u64",
+    "name": "vpaddl_s32",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQADD"
+        "SADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddh_s16",
+    "name": "vpaddl_s8",
     "arguments": [
-      "int16_t a",
-      "int16_t b"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQADD"
+        "SADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddh_u16",
+    "name": "vpaddl_u16",
     "arguments": [
-      "uint16_t a",
-      "uint16_t b"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQADD"
+        "UADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_s16",
+    "name": "vpaddl_u32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -65071,26 +267688,22 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "UADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_s32",
+    "name": "vpaddl_u8",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -65100,26 +267713,22 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "UADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_s64",
+    "name": "vpaddlq_s16",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -65129,26 +267738,22 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "SADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_s8",
+    "name": "vpaddlq_s32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -65158,26 +267763,22 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "SADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_u16",
+    "name": "vpaddlq_s8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -65187,26 +267788,22 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "SADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_u32",
+    "name": "vpaddlq_u16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "uint16x8_t a"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -65216,26 +267813,22 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "UADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_u64",
+    "name": "vpaddlq_u32",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint32x4_t a"
     ],
     "return_type": {
       "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -65245,26 +267838,22 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "UADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqaddq_u8",
+    "name": "vpaddlq_u8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -65274,26 +267863,26 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "UADDLP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadds_s32",
+    "name": "vpaddq_f16",
     "arguments": [
-      "int32_t a",
-      "int32_t b"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Sm"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -65301,26 +267890,26 @@
     ],
     "instructions": [
       [
-        "SQADD"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqadds_u32",
+    "name": "vpaddq_f32",
     "arguments": [
-      "uint32_t a",
-      "uint32_t b"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Sm"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -65328,35 +267917,26 @@
     ],
     "instructions": [
       [
-        "UQADD"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_lane_s16",
+    "name": "vpaddq_f64",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x4_t v",
-      "const int lane"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -65364,35 +267944,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_lane_s32",
+    "name": "vpaddq_s16",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x2_t v",
-      "const int lane"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -65400,35 +267971,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_laneq_s16",
+    "name": "vpaddq_s32",
     "arguments": [
       "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t v",
-      "const int lane"
+      "int32x4_t b"
     ],
     "return_type": {
       "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -65436,35 +267998,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_laneq_s32",
+    "name": "vpaddq_s64",
     "arguments": [
       "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t v",
-      "const int lane"
+      "int64x2_t b"
     ],
     "return_type": {
       "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -65472,30 +268025,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_n_s16",
+    "name": "vpaddq_s8",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16_t c"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -65503,30 +268052,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_n_s32",
+    "name": "vpaddq_u16",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32_t c"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -65534,30 +268079,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_s16",
+    "name": "vpaddq_u32",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -65565,30 +268106,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_high_s32",
+    "name": "vpaddq_u64",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.4S"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -65596,178 +268133,133 @@
     ],
     "instructions": [
       [
-        "SQDMLAL2"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_lane_s16",
+    "name": "vpaddq_u8",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t v",
-      "const int lane"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "ADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_lane_s32",
+    "name": "vpadds_f32",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t v",
-      "const int lane"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FADDP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_laneq_s16",
+    "name": "vpmax_f16",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x8_t v",
-      "const int lane"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_laneq_s32",
+    "name": "vpmax_f32",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x4_t v",
-      "const int lane"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_n_s16",
+    "name": "vpmax_s16",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16_t c"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4H"
       },
-      "c": {
-        "register": "Vm.H[0]"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -65777,30 +268269,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_n_s32",
+    "name": "vpmax_s32",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32_t c"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2S"
       },
-      "c": {
-        "register": "Vm.S[0]"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -65810,30 +268298,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_s16",
+    "name": "vpmax_s8",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.4H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -65843,30 +268327,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlal_s32",
+    "name": "vpmax_u16",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.2S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -65876,102 +268356,84 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlalh_lane_s16",
+    "name": "vpmax_u32",
     "arguments": [
-      "int32_t a",
-      "int16_t b",
-      "int16x4_t v",
-      "const int lane"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlalh_laneq_s16",
+    "name": "vpmax_u8",
     "arguments": [
-      "int32_t a",
-      "int16_t b",
-      "int16x8_t v",
-      "const int lane"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlalh_s16",
+    "name": "vpmaxnm_f16",
     "arguments": [
-      "int32_t a",
-      "int16_t b",
-      "int16_t c"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Hn"
-      },
-      "c": {
-        "register": "Hm"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -65979,34 +268441,25 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlals_lane_s32",
+    "name": "vpmaxnm_f32",
     "arguments": [
-      "int64_t a",
-      "int32_t b",
-      "int32x2_t v",
-      "const int lane"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
         "register": "Vm.2S"
       }
     },
@@ -66015,35 +268468,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlals_laneq_s32",
+    "name": "vpmaxnmq_f16",
     "arguments": [
-      "int64_t a",
-      "int32_t b",
-      "int32x4_t v",
-      "const int lane"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -66051,30 +268495,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlals_s32",
+    "name": "vpmaxnmq_f32",
     "arguments": [
-      "int64_t a",
-      "int32_t b",
-      "int32_t c"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Sn"
-      },
-      "c": {
-        "register": "Sm"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -66082,35 +268522,26 @@
     ],
     "instructions": [
       [
-        "SQDMLAL"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_lane_s16",
+    "name": "vpmaxnmq_f64",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x4_t v",
-      "const int lane"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -66118,35 +268549,22 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_lane_s32",
+    "name": "vpmaxnmqd_f64",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x2_t v",
-      "const int lane"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -66154,35 +268572,22 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_laneq_s16",
+    "name": "vpmaxnms_f32",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t v",
-      "const int lane"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -66190,35 +268595,26 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "FMAXNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_laneq_s32",
+    "name": "vpmaxq_f16",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t v",
-      "const int lane"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -66226,30 +268622,26 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_n_s16",
+    "name": "vpmaxq_f32",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16_t c"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -66257,30 +268649,26 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_n_s32",
+    "name": "vpmaxq_f64",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32_t c"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -66288,29 +268676,25 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_s16",
+    "name": "vpmaxq_s16",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.8H"
       },
-      "c": {
+      "b": {
         "register": "Vm.8H"
       }
     },
@@ -66319,29 +268703,25 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_high_s32",
+    "name": "vpmaxq_s32",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.4S"
       },
-      "c": {
+      "b": {
         "register": "Vm.4S"
       }
     },
@@ -66350,111 +268730,80 @@
     ],
     "instructions": [
       [
-        "SQDMLSL2"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_lane_s16",
+    "name": "vpmaxq_s8",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t v",
-      "const int lane"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "SMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_lane_s32",
+    "name": "vpmaxq_u16",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_laneq_s16",
+    "name": "vpmaxq_u32",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x8_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -66462,35 +268811,26 @@
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_laneq_s32",
+    "name": "vpmaxq_u8",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x4_t v",
-      "const int lane"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -66498,128 +268838,99 @@
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "UMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_n_s16",
+    "name": "vpmaxqd_f64",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16_t c"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.H[0]"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_n_s32",
+    "name": "vpmaxs_f32",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32_t c"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2S"
-      },
-      "c": {
-        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "FMAXP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_s16",
+    "name": "vpmin_f16",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4H"
       },
-      "c": {
+      "b": {
         "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsl_s32",
+    "name": "vpmin_f32",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2S"
       },
-      "c": {
+      "b": {
         "register": "Vm.2S"
       }
     },
@@ -66630,304 +268941,253 @@
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlslh_lane_s16",
+    "name": "vpmin_s16",
     "arguments": [
-      "int32_t a",
-      "int16_t b",
-      "int16x4_t v",
-      "const int lane"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
         "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlslh_laneq_s16",
+    "name": "vpmin_s32",
     "arguments": [
-      "int32_t a",
-      "int16_t b",
-      "int16x8_t v",
-      "const int lane"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlslh_s16",
+    "name": "vpmin_s8",
     "arguments": [
-      "int32_t a",
-      "int16_t b",
-      "int16_t c"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Hn"
-      },
-      "c": {
-        "register": "Hm"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsls_lane_s32",
+    "name": "vpmin_u16",
     "arguments": [
-      "int64_t a",
-      "int32_t b",
-      "int32x2_t v",
-      "const int lane"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsls_laneq_s32",
+    "name": "vpmin_u32",
     "arguments": [
-      "int64_t a",
-      "int32_t b",
-      "int32x4_t v",
-      "const int lane"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmlsls_s32",
+    "name": "vpmin_u8",
     "arguments": [
-      "int64_t a",
-      "int32_t b",
-      "int32_t c"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Sn"
-      },
-      "c": {
-        "register": "Sm"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMLSL"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_lane_s16",
+    "name": "vpminnm_f16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t v",
-      "const int lane"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
+      "b": {
         "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_lane_s32",
+    "name": "vpminnm_f32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t v",
-      "const int lane"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
+      "b": {
         "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_laneq_s16",
+    "name": "vpminnmq_f16",
     "arguments": [
-      "int16x4_t a",
-      "int16x8_t v",
-      "const int lane"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.8H"
       },
-      "v": {
+      "b": {
         "register": "Vm.8H"
       }
     },
@@ -66936,30 +269196,25 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_laneq_s32",
+    "name": "vpminnmq_f32",
     "arguments": [
-      "int32x2_t a",
-      "int32x4_t v",
-      "const int lane"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.4S"
       },
-      "v": {
+      "b": {
         "register": "Vm.4S"
       }
     },
@@ -66968,147 +269223,126 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_n_s16",
+    "name": "vpminnmq_f64",
     "arguments": [
-      "int16x4_t a",
-      "int16_t b"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_n_s32",
+    "name": "vpminnmqd_f64",
     "arguments": [
-      "int32x2_t a",
-      "int32_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_s16",
+    "name": "vpminnms_f32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINNMP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulh_s32",
+    "name": "vpminq_f16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhh_lane_s16",
+    "name": "vpminq_f32",
     "arguments": [
-      "int16_t a",
-      "int16x4_t v",
-      "const int lane"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vm.4H"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -67116,31 +269350,26 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhh_laneq_s16",
+    "name": "vpminq_f64",
     "arguments": [
-      "int16_t a",
-      "int16x8_t v",
-      "const int lane"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.2D"
       },
-      "v": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -67148,26 +269377,26 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhh_s16",
+    "name": "vpminq_s16",
     "arguments": [
-      "int16_t a",
-      "int16_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Hm"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -67175,98 +269404,79 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_lane_s16",
+    "name": "vpminq_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x4_t v",
-      "const int lane"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vm.4H"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_lane_s32",
+    "name": "vpminq_s8",
     "arguments": [
-      "int32x4_t a",
-      "int32x2_t v",
-      "const int lane"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vn.16B"
       },
-      "v": {
-        "register": "Vm.2S"
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_laneq_s16",
+    "name": "vpminq_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
+      "b": {
         "register": "Vm.8H"
       }
     },
@@ -67275,30 +269485,25 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_laneq_s32",
+    "name": "vpminq_u32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
+      "b": {
         "register": "Vm.4S"
       }
     },
@@ -67307,113 +269512,95 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_n_s16",
+    "name": "vpminq_u8",
     "arguments": [
-      "int16x8_t a",
-      "int16_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "UMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_n_s32",
+    "name": "vpminqd_f64",
     "arguments": [
-      "int32x4_t a",
-      "int32_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_s16",
+    "name": "vpmins_f32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "FMINP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhq_s32",
+    "name": "vqabs_s16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -67423,63 +269610,47 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhs_lane_s32",
+    "name": "vqabs_s32",
     "arguments": [
-      "int32_t a",
-      "int32x2_t v",
-      "const int lane"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhs_laneq_s32",
+    "name": "vqabs_s64",
     "arguments": [
-      "int32_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Dn"
       }
     },
     "Architectures": [
@@ -67487,58 +269658,47 @@
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulhs_s32",
+    "name": "vqabs_s8",
     "arguments": [
-      "int32_t a",
-      "int32_t b"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "b": {
-        "register": "Sm"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULH"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_lane_s16",
+    "name": "vqabsb_s8",
     "arguments": [
-      "int16x8_t a",
-      "int16x4_t v",
-      "const int lane"
+      "int8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4H"
+        "register": "Bn"
       }
     },
     "Architectures": [
@@ -67546,31 +269706,22 @@
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_lane_s32",
+    "name": "vqabsd_s64",
     "arguments": [
-      "int32x4_t a",
-      "int32x2_t v",
-      "const int lane"
+      "int64_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Dn"
       }
     },
     "Architectures": [
@@ -67578,31 +269729,22 @@
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_laneq_s16",
+    "name": "vqabsh_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t v",
-      "const int lane"
+      "int16_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "v": {
-        "register": "Vm.8H"
+        "register": "Hn"
       }
     },
     "Architectures": [
@@ -67610,85 +269752,72 @@
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_laneq_s32",
+    "name": "vqabsq_s16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_n_s16",
+    "name": "vqabsq_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16_t b"
+      "int32x4_t a"
     ],
     "return_type": {
       "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.H[0]"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_n_s32",
+    "name": "vqabsq_s64",
     "arguments": [
-      "int32x4_t a",
-      "int32_t b"
+      "int64x2_t a"
     ],
     "return_type": {
       "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.S[0]"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -67696,53 +269825,47 @@
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_s16",
+    "name": "vqabsq_s8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_high_s32",
+    "name": "vqabss_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int32_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Sn"
       }
     },
     "Architectures": [
@@ -67750,30 +269873,25 @@
     ],
     "instructions": [
       [
-        "SQDMULL2"
+        "SQABS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_lane_s16",
+    "name": "vqadd_s16",
     "arguments": [
       "int16x4_t a",
-      "int16x4_t v",
-      "const int lane"
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
+      "b": {
         "register": "Vm.4H"
       }
     },
@@ -67784,30 +269902,25 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_lane_s32",
+    "name": "vqadd_s32",
     "arguments": [
       "int32x2_t a",
-      "int32x2_t v",
-      "const int lane"
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
+      "b": {
         "register": "Vm.2S"
       }
     },
@@ -67818,90 +269931,84 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_laneq_s16",
+    "name": "vqadd_s64",
     "arguments": [
-      "int16x4_t a",
-      "int16x8_t v",
-      "const int lane"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Dn"
       },
-      "v": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_laneq_s32",
+    "name": "vqadd_s8",
     "arguments": [
-      "int32x2_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.8B"
       },
-      "v": {
-        "register": "Vm.4S"
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_n_s16",
+    "name": "vqadd_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.H[0]"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -67911,26 +270018,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_n_s32",
+    "name": "vqadd_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.S[0]"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -67940,26 +270047,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_s16",
+    "name": "vqadd_u64",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint64x1_t a",
+      "uint64x1_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -67969,26 +270076,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmull_s32",
+    "name": "vqadd_u8",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -67998,31 +270105,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmullh_lane_s16",
+    "name": "vqaddb_s8",
     "arguments": [
-      "int16_t a",
-      "int16x4_t v",
-      "const int lane"
+      "int8_t a",
+      "int8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Bn"
       },
-      "v": {
-        "register": "Vm.4H"
+      "b": {
+        "register": "Bm"
       }
     },
     "Architectures": [
@@ -68030,31 +270132,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmullh_laneq_s16",
+    "name": "vqaddb_u8",
     "arguments": [
-      "int16_t a",
-      "int16x8_t v",
-      "const int lane"
+      "uint8_t a",
+      "uint8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Bn"
       },
-      "v": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Bm"
       }
     },
     "Architectures": [
@@ -68062,26 +270159,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmullh_s16",
+    "name": "vqaddd_s64",
     "arguments": [
-      "int16_t a",
-      "int16_t b"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Dn"
       },
       "b": {
-        "register": "Hm"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -68089,31 +270186,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulls_lane_s32",
+    "name": "vqaddd_u64",
     "arguments": [
-      "int32_t a",
-      "int32x2_t v",
-      "const int lane"
+      "uint64_t a",
+      "uint64_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Dn"
       },
-      "v": {
-        "register": "Vm.2S"
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -68121,31 +270213,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulls_laneq_s32",
+    "name": "vqaddh_s16",
     "arguments": [
-      "int32_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int16_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Hn"
       },
-      "v": {
-        "register": "Vm.4S"
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -68153,26 +270240,26 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqdmulls_s32",
+    "name": "vqaddh_u16",
     "arguments": [
-      "int32_t a",
-      "int32_t b"
+      "uint16_t a",
+      "uint16_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Hn"
       },
       "b": {
-        "register": "Sm"
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -68180,184 +270267,200 @@
     ],
     "instructions": [
       [
-        "SQDMULL"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_high_s16",
+    "name": "vqaddq_s16",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.8B"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQXTN2"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_high_s32",
+    "name": "vqaddq_s32",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQXTN2"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_high_s64",
+    "name": "vqaddq_s64",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
       },
-      "r": {
-        "register": "Vd.2S"
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQXTN2"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_high_u16",
+    "name": "vqaddq_s8",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
-      "r": {
-        "register": "Vd.8B"
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN2"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_high_u32",
+    "name": "vqaddq_u16",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
       "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.4H"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN2"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_high_u64",
+    "name": "vqaddq_u32",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
-      "r": {
-        "register": "Vd.2S"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN2"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_s16",
+    "name": "vqaddq_u64",
     "arguments": [
-      "int16x8_t a"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -68367,22 +270470,26 @@
     ],
     "instructions": [
       [
-        "SQXTN"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_s32",
+    "name": "vqaddq_u8",
     "arguments": [
-      "int32x4_t a"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -68392,122 +270499,197 @@
     ],
     "instructions": [
       [
-        "SQXTN"
+        "UQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_s64",
+    "name": "vqadds_s32",
     "arguments": [
-      "int64x2_t a"
+      "int32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQXTN"
+        "SQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_u16",
+    "name": "vqadds_u32",
     "arguments": [
-      "uint16x8_t a"
+      "uint32_t a",
+      "uint32_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmlal_high_lane_s16",
+    "arguments": [
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x4_t v",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
         "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_u32",
+    "name": "vqdmlal_high_lane_s32",
     "arguments": [
-      "uint32x4_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
         "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovn_u64",
+    "name": "vqdmlal_high_laneq_s16",
     "arguments": [
-      "uint64x2_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovnd_s64",
+    "name": "vqdmlal_high_laneq_s32",
     "arguments": [
-      "int64_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -68515,22 +270697,30 @@
     ],
     "instructions": [
       [
-        "SQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovnd_u64",
+    "name": "vqdmlal_high_n_s16",
     "arguments": [
-      "uint64_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -68538,22 +270728,30 @@
     ],
     "instructions": [
       [
-        "UQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovnh_s16",
+    "name": "vqdmlal_high_n_s32",
     "arguments": [
-      "int16_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -68561,22 +270759,30 @@
     ],
     "instructions": [
       [
-        "SQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovnh_u16",
+    "name": "vqdmlal_high_s16",
     "arguments": [
-      "uint16_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -68584,22 +270790,30 @@
     ],
     "instructions": [
       [
-        "UQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovns_s32",
+    "name": "vqdmlal_high_s32",
     "arguments": [
-      "int32_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -68607,76 +270821,111 @@
     ],
     "instructions": [
       [
-        "SQXTN"
+        "SQDMLAL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovns_u32",
+    "name": "vqdmlal_lane_s16",
     "arguments": [
-      "uint32_t a"
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQXTN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovun_high_s16",
+    "name": "vqdmlal_lane_s32",
     "arguments": [
-      "uint8x8_t r",
-      "int16x8_t a"
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.2D"
       },
-      "r": {
-        "register": "Vd.8B"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQXTUN2"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovun_high_s32",
+    "name": "vqdmlal_laneq_s16",
     "arguments": [
-      "uint16x4_t r",
-      "int32x4_t a"
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -68684,26 +270933,35 @@
     ],
     "instructions": [
       [
-        "SQXTUN2"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovun_high_s64",
+    "name": "vqdmlal_laneq_s32",
     "arguments": [
-      "uint32x2_t r",
-      "int64x2_t a"
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.2D"
       },
-      "r": {
-        "register": "Vd.2S"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -68711,22 +270969,30 @@
     ],
     "instructions": [
       [
-        "SQXTUN2"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovun_s16",
+    "name": "vqdmlal_n_s16",
     "arguments": [
-      "int16x8_t a"
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -68736,22 +271002,30 @@
     ],
     "instructions": [
       [
-        "SQXTUN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovun_s32",
+    "name": "vqdmlal_n_s32",
     "arguments": [
-      "int32x4_t a"
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -68761,22 +271035,30 @@
     ],
     "instructions": [
       [
-        "SQXTUN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovun_s64",
+    "name": "vqdmlal_s16",
     "arguments": [
-      "int64x2_t a"
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -68786,45 +271068,68 @@
     ],
     "instructions": [
       [
-        "SQXTUN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovund_s64",
+    "name": "vqdmlal_s32",
     "arguments": [
-      "int64_t a"
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQXTUN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovunh_s16",
+    "name": "vqdmlalh_lane_s16",
     "arguments": [
-      "int16_t a"
+      "int32_t a",
+      "int16_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Sd"
+      },
+      "b": {
         "register": "Hn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -68832,22 +271137,35 @@
     ],
     "instructions": [
       [
-        "SQXTUN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqmovuns_s32",
+    "name": "vqdmlalh_laneq_s16",
     "arguments": [
-      "int32_t a"
+      "int32_t a",
+      "int16_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Sd"
+      },
+      "b": {
+        "register": "Hn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -68855,72 +271173,102 @@
     ],
     "instructions": [
       [
-        "SQXTUN"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqneg_s16",
+    "name": "vqdmlalh_s16",
     "arguments": [
-      "int16x4_t a"
+      "int32_t a",
+      "int16_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Sd"
+      },
+      "b": {
+        "register": "Hn"
+      },
+      "c": {
+        "register": "Hm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqneg_s32",
+    "name": "vqdmlals_lane_s32",
     "arguments": [
-      "int32x2_t a"
+      "int64_t a",
+      "int32_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqneg_s64",
+    "name": "vqdmlals_laneq_s32",
     "arguments": [
-      "int64x1_t a"
+      "int64_t a",
+      "int32_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -68928,47 +271276,66 @@
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqneg_s8",
+    "name": "vqdmlals_s32",
     "arguments": [
-      "int8x8_t a"
+      "int64_t a",
+      "int32_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Sn"
+      },
+      "c": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLAL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegb_s8",
+    "name": "vqdmlsl_high_lane_s16",
     "arguments": [
-      "int8_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -68976,22 +271343,35 @@
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegd_s64",
+    "name": "vqdmlsl_high_lane_s32",
     "arguments": [
-      "int64_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -68999,22 +271379,35 @@
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegh_s16",
+    "name": "vqdmlsl_high_laneq_s16",
     "arguments": [
-      "int16_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -69022,72 +271415,97 @@
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegq_s16",
+    "name": "vqdmlsl_high_laneq_s32",
     "arguments": [
-      "int16x8_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegq_s32",
+    "name": "vqdmlsl_high_n_s16",
     "arguments": [
-      "int32x4_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16_t c"
     ],
     "return_type": {
       "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegq_s64",
+    "name": "vqdmlsl_high_n_s32",
     "arguments": [
-      "int64x2_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32_t c"
     ],
     "return_type": {
       "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -69095,47 +271513,61 @@
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegq_s8",
+    "name": "vqdmlsl_high_s16",
     "arguments": [
-      "int8x16_t a"
+      "int32x4_t a",
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqnegs_s32",
+    "name": "vqdmlsl_high_s32",
     "arguments": [
-      "int32_t a"
+      "int64x2_t a",
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -69143,25 +271575,25 @@
     ],
     "instructions": [
       [
-        "SQNEG"
+        "SQDMLSL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlah_lane_s16",
+    "name": "vqdmlsl_lane_s16",
     "arguments": [
-      "int16x4_t a",
+      "int32x4_t a",
       "int16x4_t b",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.4S"
       },
       "b": {
         "register": "Vn.4H"
@@ -69175,29 +271607,31 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlah_lane_s32",
+    "name": "vqdmlsl_lane_s32",
     "arguments": [
-      "int32x2_t a",
+      "int64x2_t a",
       "int32x2_t b",
       "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.2D"
       },
       "b": {
         "register": "Vn.2S"
@@ -69211,29 +271645,31 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlah_laneq_s16",
+    "name": "vqdmlsl_laneq_s16",
     "arguments": [
-      "int16x4_t a",
+      "int32x4_t a",
       "int16x4_t b",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.4S"
       },
       "b": {
         "register": "Vn.4H"
@@ -69251,25 +271687,25 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlah_laneq_s32",
+    "name": "vqdmlsl_laneq_s32",
     "arguments": [
-      "int32x2_t a",
+      "int64x2_t a",
       "int32x2_t b",
       "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.2D"
       },
       "b": {
         "register": "Vn.2S"
@@ -69287,24 +271723,90 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlah_s16",
+    "name": "vqdmlsl_n_s16",
     "arguments": [
-      "int16x4_t a",
+      "int32x4_t a",
+      "int16x4_t b",
+      "int16_t c"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.H[0]"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmlsl_n_s32",
+    "arguments": [
+      "int64x2_t a",
+      "int32x2_t b",
+      "int32_t c"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.S[0]"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmlsl_s16",
+    "arguments": [
+      "int32x4_t a",
       "int16x4_t b",
       "int16x4_t c"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.4S"
       },
       "b": {
         "register": "Vn.4H"
@@ -69314,28 +271816,30 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlah_s32",
+    "name": "vqdmlsl_s32",
     "arguments": [
-      "int32x2_t a",
+      "int64x2_t a",
       "int32x2_t b",
       "int32x2_t c"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.2D"
       },
       "b": {
         "register": "Vn.2S"
@@ -69345,29 +271849,31 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahh_lane_s16",
+    "name": "vqdmlslh_lane_s16",
     "arguments": [
-      "int16_t a",
+      "int32_t a",
       "int16_t b",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Sd"
       },
       "b": {
         "register": "Hn"
@@ -69385,25 +271891,25 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahh_laneq_s16",
+    "name": "vqdmlslh_laneq_s16",
     "arguments": [
-      "int16_t a",
+      "int32_t a",
       "int16_t b",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Sd"
       },
       "b": {
         "register": "Hn"
@@ -69421,24 +271927,24 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahh_s16",
+    "name": "vqdmlslh_s16",
     "arguments": [
-      "int16_t a",
+      "int32_t a",
       "int16_t b",
       "int16_t c"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Sd"
       },
       "b": {
         "register": "Hn"
@@ -69452,28 +271958,127 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMLSL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahq_lane_s16",
+    "name": "vqdmlsls_lane_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x4_t v",
+      "int64_t a",
+      "int32_t b",
+      "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vn.8H"
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmlsls_laneq_s32",
+    "arguments": [
+      "int64_t a",
+      "int32_t b",
+      "int32x4_t v",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmlsls_s32",
+    "arguments": [
+      "int64_t a",
+      "int32_t b",
+      "int32_t c"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Sn"
+      },
+      "c": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMLSL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmulh_lane_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t v",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
       },
       "lane": {
         "minimum": 0,
@@ -69484,32 +272089,30 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahq_lane_s32",
+    "name": "vqdmulh_lane_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
+      "int32x2_t a",
       "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
       "lane": {
         "minimum": 0,
@@ -69520,31 +272123,29 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahq_laneq_s16",
+    "name": "vqdmulh_laneq_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
+      "int16x4_t a",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
       },
       "lane": {
@@ -69560,27 +272161,23 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahq_laneq_s32",
+    "name": "vqdmulh_laneq_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
+      "int32x2_t a",
       "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
       },
       "lane": {
@@ -69596,97 +272193,147 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahq_s16",
+    "name": "vqdmulh_n_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "int16x4_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "c": {
-        "register": "Vm.8H"
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahq_s32",
+    "name": "vqdmulh_n_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "int32x2_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.4S"
+        "register": "Vm.S[0]"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmulh_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
       },
-      "c": {
-        "register": "Vm.4S"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahs_lane_s32",
+    "name": "vqdmulh_s32",
     "arguments": [
-      "int32_t a",
-      "int32_t b",
-      "int32x2_t v",
-      "const int lane"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Sn"
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmulhh_lane_s16",
+    "arguments": [
+      "int16_t a",
+      "int16x4_t v",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "v": {
-        "register": "Vm.2S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -69694,35 +272341,31 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahs_laneq_s32",
+    "name": "vqdmulhh_laneq_s16",
     "arguments": [
-      "int32_t a",
-      "int32_t b",
-      "int32x4_t v",
+      "int16_t a",
+      "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
-      },
-      "b": {
-        "register": "Sn"
+        "register": "Hn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -69730,30 +272373,26 @@
     ],
     "instructions": [
       [
-        "SQRDMLAH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlahs_s32",
+    "name": "vqdmulhh_s16",
     "arguments": [
-      "int32_t a",
-      "int32_t b",
-      "int32_t c"
+      "int16_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Hn"
       },
       "b": {
-        "register": "Sn"
-      },
-      "c": {
-        "register": "Sm"
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -69761,28 +272400,24 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlsh_lane_s16",
+    "name": "vqdmulhq_lane_s16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
+      "int16x8_t a",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
       "lane": {
         "minimum": 0,
@@ -69793,32 +272428,30 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlsh_lane_s32",
+    "name": "vqdmulhq_lane_s32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
+      "int32x4_t a",
       "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
@@ -69829,32 +272462,30 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlsh_laneq_s16",
+    "name": "vqdmulhq_laneq_s16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
+      "int16x8_t a",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
       "lane": {
         "minimum": 0,
@@ -69869,28 +272500,24 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlsh_laneq_s32",
+    "name": "vqdmulhq_laneq_s32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
+      "int32x4_t a",
       "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
@@ -69905,97 +272532,147 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlsh_s16",
+    "name": "vqdmulhq_n_s16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "int16x4_t c"
+      "int16x8_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.4H"
-      },
-      "c": {
-        "register": "Vm.4H"
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlsh_s32",
+    "name": "vqdmulhq_n_s32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "int32x2_t c"
+      "int32x4_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.2S"
+        "register": "Vm.S[0]"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmulhq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
       },
-      "c": {
-        "register": "Vm.2S"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshh_lane_s16",
+    "name": "vqdmulhq_s32",
     "arguments": [
-      "int16_t a",
-      "int16_t b",
-      "int16x4_t v",
-      "const int lane"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Hn"
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULH"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqdmulhs_lane_s32",
+    "arguments": [
+      "int32_t a",
+      "int32x2_t v",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -70003,35 +272680,31 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshh_laneq_s16",
+    "name": "vqdmulhs_laneq_s32",
     "arguments": [
-      "int16_t a",
-      "int16_t b",
-      "int16x8_t v",
+      "int32_t a",
+      "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
-      },
-      "b": {
-        "register": "Hn"
+        "register": "Sn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "v": {
-        "register": "Vm.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -70039,30 +272712,26 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshh_s16",
+    "name": "vqdmulhs_s32",
     "arguments": [
-      "int16_t a",
-      "int16_t b",
-      "int16_t c"
+      "int32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Sn"
       },
       "b": {
-        "register": "Hn"
-      },
-      "c": {
-        "register": "Hm"
+        "register": "Sm"
       }
     },
     "Architectures": [
@@ -70070,27 +272739,23 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshq_lane_s16",
+    "name": "vqdmull_high_lane_s16",
     "arguments": [
       "int16x8_t a",
-      "int16x8_t b",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
       },
       "lane": {
@@ -70106,27 +272771,23 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshq_lane_s32",
+    "name": "vqdmull_high_lane_s32",
     "arguments": [
       "int32x4_t a",
-      "int32x4_t b",
       "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
       },
       "lane": {
@@ -70142,28 +272803,24 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshq_laneq_s16",
+    "name": "vqdmull_high_laneq_s16",
     "arguments": [
       "int16x8_t a",
-      "int16x8_t b",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
       "lane": {
         "minimum": 0,
@@ -70178,28 +272835,24 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshq_laneq_s32",
+    "name": "vqdmull_high_laneq_s32",
     "arguments": [
       "int32x4_t a",
-      "int32x4_t b",
       "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
       "lane": {
         "minimum": 0,
@@ -70214,30 +272867,26 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshq_s16",
+    "name": "vqdmull_high_n_s16",
     "arguments": [
       "int16x8_t a",
-      "int16x8_t b",
-      "int16x8_t c"
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
       },
-      "c": {
-        "register": "Vm.8H"
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -70245,66 +272894,26 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshq_s32",
+    "name": "vqdmull_high_n_s32",
     "arguments": [
       "int32x4_t a",
-      "int32x4_t b",
-      "int32x4_t c"
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
       },
-      "c": {
-        "register": "Vm.4S"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SQRDMLSH"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vqrdmlshs_lane_s32",
-    "arguments": [
-      "int32_t a",
-      "int32_t b",
-      "int32x2_t v",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "int32_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Sd"
-      },
       "b": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -70312,35 +272921,26 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshs_laneq_s32",
+    "name": "vqdmull_high_s16",
     "arguments": [
-      "int32_t a",
-      "int32_t b",
-      "int32x4_t v",
-      "const int lane"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -70348,30 +272948,26 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmlshs_s32",
+    "name": "vqdmull_high_s32",
     "arguments": [
-      "int32_t a",
-      "int32_t b",
-      "int32_t c"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Sn"
-      },
-      "c": {
-        "register": "Sm"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -70379,20 +272975,20 @@
     ],
     "instructions": [
       [
-        "SQRDMLSH"
+        "SQDMULL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_lane_s16",
+    "name": "vqdmull_lane_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70413,20 +273009,20 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_lane_s32",
+    "name": "vqdmull_lane_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70447,20 +273043,20 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_laneq_s16",
+    "name": "vqdmull_laneq_s16",
     "arguments": [
       "int16x4_t a",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70479,20 +273075,20 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_laneq_s32",
+    "name": "vqdmull_laneq_s32",
     "arguments": [
       "int32x2_t a",
       "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70511,19 +273107,19 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_n_s16",
+    "name": "vqdmull_n_s16",
     "arguments": [
       "int16x4_t a",
       "int16_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70540,19 +273136,19 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_n_s32",
+    "name": "vqdmull_n_s32",
     "arguments": [
       "int32x2_t a",
       "int32_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70569,19 +273165,19 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_s16",
+    "name": "vqdmull_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70598,19 +273194,19 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulh_s32",
+    "name": "vqdmull_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70627,20 +273223,20 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhh_lane_s16",
+    "name": "vqdmullh_lane_s16",
     "arguments": [
       "int16_t a",
       "int16x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70659,20 +273255,20 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhh_laneq_s16",
+    "name": "vqdmullh_laneq_s16",
     "arguments": [
       "int16_t a",
       "int16x8_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70691,19 +273287,19 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhh_s16",
+    "name": "vqdmullh_s16",
     "arguments": [
       "int16_t a",
       "int16_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -70718,99 +273314,117 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_lane_s16",
+    "name": "vqdmulls_lane_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x4_t v",
+      "int32_t a",
+      "int32x2_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Sn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "v": {
-        "register": "Vm.4H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_lane_s32",
+    "name": "vqdmulls_laneq_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x2_t v",
+      "int32_t a",
+      "int32x4_t v",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Sn"
       },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "v": {
-        "register": "Vm.2S"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQDMULL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_laneq_s16",
+    "name": "vqdmulls_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t v",
-      "const int lane"
+      "int32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Sn"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Sm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQDMULL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqmovn_high_s16",
+    "arguments": [
+      "int8x8_t r",
+      "int16x8_t a"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vm.8H"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -70818,31 +273432,53 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQXTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_laneq_s32",
+    "name": "vqmovn_high_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int16x4_t r",
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "r": {
+        "register": "Vd.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQXTN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqmovn_high_s64",
+    "arguments": [
+      "int32x2_t r",
+      "int64x2_t a"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
       },
-      "v": {
-        "register": "Vm.4S"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -70850,113 +273486,103 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQXTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_n_s16",
+    "name": "vqmovn_high_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16_t b"
+      "uint8x8_t r",
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vm.H[0]"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "UQXTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_n_s32",
+    "name": "vqmovn_high_u32",
     "arguments": [
-      "int32x4_t a",
-      "int32_t b"
+      "uint16x4_t r",
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
       },
-      "b": {
-        "register": "Vm.S[0]"
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "UQXTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_s16",
+    "name": "vqmovn_high_u64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint32x2_t r",
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Vm.8H"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "UQXTN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhq_s32",
+    "name": "vqmovn_s16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -70966,117 +273592,97 @@
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhs_lane_s32",
+    "name": "vqmovn_s32",
     "arguments": [
-      "int32_t a",
-      "int32x2_t v",
-      "const int lane"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vm.2S"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhs_laneq_s32",
+    "name": "vqmovn_s64",
     "arguments": [
-      "int32_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "v": {
-        "register": "Vm.4S"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "SQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrdmulhs_s32",
+    "name": "vqmovn_u16",
     "arguments": [
-      "int32_t a",
-      "int32_t b"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "b": {
-        "register": "Sm"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRDMULH"
+        "UQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_s16",
+    "name": "vqmovn_u32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -71086,26 +273692,22 @@
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "UQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_s32",
+    "name": "vqmovn_u64",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
@@ -71115,200 +273717,164 @@
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "UQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_s64",
+    "name": "vqmovnd_s64",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "int64_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_s8",
+    "name": "vqmovnd_u64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint64_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "UQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_u16",
+    "name": "vqmovnh_s16",
     "arguments": [
-      "uint16x4_t a",
-      "int16x4_t b"
+      "int16_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_u32",
+    "name": "vqmovnh_u16",
     "arguments": [
-      "uint32x2_t a",
-      "int32x2_t b"
+      "uint16_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "UQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_u64",
+    "name": "vqmovns_s32",
     "arguments": [
-      "uint64x1_t a",
-      "int64x1_t b"
+      "int32_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshl_u8",
+    "name": "vqmovns_u32",
     "arguments": [
-      "uint8x8_t a",
-      "int8x8_t b"
+      "uint32_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "UQXTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlb_s8",
+    "name": "vqmovun_high_s16",
     "arguments": [
-      "int8_t a",
-      "int8_t b"
+      "uint8x8_t r",
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Bm"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -71316,26 +273882,26 @@
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlb_u8",
+    "name": "vqmovun_high_s32",
     "arguments": [
-      "uint8_t a",
-      "int8_t b"
+      "uint16x4_t r",
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Bm"
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -71343,26 +273909,26 @@
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQXTUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshld_s64",
+    "name": "vqmovun_high_s64",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "uint32x2_t r",
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Dm"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -71370,194 +273936,166 @@
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshld_u64",
+    "name": "vqmovun_s16",
     "arguments": [
-      "uint64_t a",
-      "int64_t b"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQXTUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlh_s16",
+    "name": "vqmovun_s32",
     "arguments": [
-      "int16_t a",
-      "int16_t b"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlh_u16",
+    "name": "vqmovun_s64",
     "arguments": [
-      "uint16_t a",
-      "int16_t b"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQXTUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_s16",
+    "name": "vqmovund_s64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int64_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_s32",
+    "name": "vqmovunh_s16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int16_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_s64",
+    "name": "vqmovuns_s32",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int32_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQXTUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_s8",
+    "name": "vqneg_s16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -71567,26 +274105,22 @@
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_u16",
+    "name": "vqneg_s32",
     "arguments": [
-      "uint16x8_t a",
-      "int16x8_t b"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -71596,55 +274130,45 @@
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_u32",
+    "name": "vqneg_s64",
     "arguments": [
-      "uint32x4_t a",
-      "int32x4_t b"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_u64",
+    "name": "vqneg_s8",
     "arguments": [
-      "uint64x2_t a",
-      "int64x2_t b"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -71654,55 +274178,45 @@
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshlq_u8",
+    "name": "vqnegb_s8",
     "arguments": [
-      "uint8x16_t a",
-      "int8x16_t b"
+      "int8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Bn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshls_s32",
+    "name": "vqnegd_s64",
     "arguments": [
-      "int32_t a",
-      "int32_t b"
+      "int64_t a"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "b": {
-        "register": "Sm"
+        "register": "Dn"
       }
     },
     "Architectures": [
@@ -71710,26 +274224,22 @@
     ],
     "instructions": [
       [
-        "SQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshls_u32",
+    "name": "vqnegh_s16",
     "arguments": [
-      "uint32_t a",
-      "int32_t b"
+      "int16_t a"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "b": {
-        "register": "Sm"
+        "register": "Hn"
       }
     },
     "Architectures": [
@@ -71737,95 +274247,72 @@
     ],
     "instructions": [
       [
-        "UQRSHL"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_high_n_s16",
+    "name": "vqnegq_s16",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a",
-      "const int n"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
-      },
-      "r": {
-        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRN2"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_high_n_s32",
+    "name": "vqnegq_s32",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a",
-      "const int n"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
-      },
-      "r": {
-        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRN2"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_high_n_s64",
+    "name": "vqnegq_s64",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a",
-      "const int n"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
-      },
-      "r": {
-        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -71833,63 +274320,47 @@
     ],
     "instructions": [
       [
-        "SQRSHRN2"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_high_n_u16",
+    "name": "vqnegq_s8",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "const int n"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
-      },
-      "r": {
-        "register": "Vd.8B"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHRN2"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_high_n_u32",
+    "name": "vqnegs_s32",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "const int n"
+      "int32_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
-      },
-      "r": {
-        "register": "Vd.4H"
+        "register": "Sn"
       }
     },
     "Architectures": [
@@ -71897,31 +274368,35 @@
     ],
     "instructions": [
       [
-        "UQRSHRN2"
+        "SQNEG"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_high_n_u64",
+    "name": "vqrdmlah_lane_s16",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.4H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Vn.4H"
       },
-      "r": {
-        "register": "Vd.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -71929,207 +274404,241 @@
     ],
     "instructions": [
       [
-        "UQRSHRN2"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_n_s16",
+    "name": "vqrdmlah_lane_s32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.2S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_n_s32",
+    "name": "vqrdmlah_laneq_s16",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
       "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_n_s64",
+    "name": "vqrdmlah_laneq_s32",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
       "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.2S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_n_u16",
+    "name": "vqrdmlah_s16",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x4_t c"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Vn.4H"
+      },
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_n_u32",
+    "name": "vqrdmlah_s32",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x2_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.2S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Vn.2S"
+      },
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrn_n_u64",
+    "name": "vqrdmlahh_lane_s16",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Hd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Hn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrnd_n_s64",
+    "name": "vqrdmlahh_laneq_s16",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Hd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Hn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -72137,27 +274646,30 @@
     ],
     "instructions": [
       [
-        "SQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrnd_n_u64",
+    "name": "vqrdmlahh_s16",
     "arguments": [
-      "uint64_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Hd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Hn"
+      },
+      "c": {
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -72165,27 +274677,35 @@
     ],
     "instructions": [
       [
-        "UQRSHRN"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrnh_n_s16",
+    "name": "vqrdmlahq_lane_s16",
     "arguments": [
-      "int16_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.8H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -72193,27 +274713,35 @@
     ],
     "instructions": [
       [
-        "SQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrnh_n_u16",
+    "name": "vqrdmlahq_lane_s32",
     "arguments": [
-      "uint16_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.4S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -72221,27 +274749,35 @@
     ],
     "instructions": [
       [
-        "UQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrns_n_s32",
+    "name": "vqrdmlahq_laneq_s16",
     "arguments": [
-      "int32_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.4H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -72249,27 +274785,35 @@
     ],
     "instructions": [
       [
-        "SQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrns_n_u32",
+    "name": "vqrdmlahq_laneq_s32",
     "arguments": [
-      "uint32_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.2S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -72277,31 +274821,30 @@
     ],
     "instructions": [
       [
-        "UQRSHRN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrun_high_n_s16",
+    "name": "vqrdmlahq_s16",
     "arguments": [
-      "uint8x8_t r",
       "int16x8_t a",
-      "const int n"
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.8B"
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -72309,31 +274852,30 @@
     ],
     "instructions": [
       [
-        "SQRSHRUN2"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrun_high_n_s32",
+    "name": "vqrdmlahq_s32",
     "arguments": [
-      "uint16x4_t r",
       "int32x4_t a",
-      "const int n"
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.4S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Vn.4S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -72341,31 +274883,35 @@
     ],
     "instructions": [
       [
-        "SQRSHRUN2"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrun_high_n_s64",
+    "name": "vqrdmlahs_lane_s32",
     "arguments": [
-      "uint32x2_t r",
-      "int64x2_t a",
-      "const int n"
+      "int32_t a",
+      "int32_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Sd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Sn"
       },
-      "r": {
-        "register": "Vd.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -72373,117 +274919,138 @@
     ],
     "instructions": [
       [
-        "SQRSHRUN2"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrun_n_s16",
+    "name": "vqrdmlahs_laneq_s32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "int32_t a",
+      "int32_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Sd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRUN"
+        "SQRDMLAH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrun_n_s32",
+    "name": "vqrdmlahs_s32",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "int32_t a",
+      "int32_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Sd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Sn"
+      },
+      "c": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRUN"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrun_n_s64",
+    "name": "vqrdmlsh_lane_s16",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.4H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQRSHRUN"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrund_n_s64",
+    "name": "vqrdmlsh_lane_s32",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -72491,27 +275058,35 @@
     ],
     "instructions": [
       [
-        "SQRSHRUN"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshrunh_n_s16",
+    "name": "vqrdmlsh_laneq_s16",
     "arguments": [
-      "int16_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.4H"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -72519,27 +275094,35 @@
     ],
     "instructions": [
       [
-        "SQRSHRUN"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqrshruns_n_s32",
+    "name": "vqrdmlsh_laneq_s32",
     "arguments": [
-      "int32_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.2S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "b": {
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -72547,440 +275130,505 @@
     ],
     "instructions": [
       [
-        "SQRSHRUN"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_s16",
+    "name": "vqrdmlsh_s16",
     "arguments": [
       "int16x4_t a",
-      "const int n"
+      "int16x4_t b",
+      "int16x4_t c"
     ],
     "return_type": {
       "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
         "register": "Vn.4H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "c": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_s32",
+    "name": "vqrdmlsh_s32",
     "arguments": [
       "int32x2_t a",
-      "const int n"
+      "int32x2_t b",
+      "int32x2_t c"
     ],
     "return_type": {
       "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
         "register": "Vn.2S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "c": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_s64",
+    "name": "vqrdmlshh_lane_s16",
     "arguments": [
-      "int64x1_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Hd"
       },
-      "n": {
+      "b": {
+        "register": "Hn"
+      },
+      "lane": {
         "minimum": 0,
-        "maximum": 63
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_s8",
+    "name": "vqrdmlshh_laneq_s16",
     "arguments": [
-      "int8x8_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Hd"
       },
-      "n": {
+      "b": {
+        "register": "Hn"
+      },
+      "lane": {
         "minimum": 0,
         "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_u16",
+    "name": "vqrdmlshh_s16",
     "arguments": [
-      "uint16x4_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b",
+      "int16_t c"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Hd"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Hn"
+      },
+      "c": {
+        "register": "Hm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_u32",
+    "name": "vqrdmlshq_lane_s16",
     "arguments": [
-      "uint32x2_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.8H"
       },
-      "n": {
+      "b": {
+        "register": "Vn.8H"
+      },
+      "lane": {
         "minimum": 0,
-        "maximum": 31
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_u64",
+    "name": "vqrdmlshq_lane_s32",
     "arguments": [
-      "uint64x1_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
       },
-      "n": {
+      "b": {
+        "register": "Vn.4S"
+      },
+      "lane": {
         "minimum": 0,
-        "maximum": 63
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_n_u8",
+    "name": "vqrdmlshq_laneq_s16",
     "arguments": [
-      "uint8x8_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.4H"
       },
-      "n": {
+      "b": {
+        "register": "Vn.4H"
+      },
+      "lane": {
         "minimum": 0,
         "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_s16",
+    "name": "vqrdmlshq_laneq_s32",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.2S"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vn.2S"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_s32",
+    "name": "vqrdmlshq_s16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "int16x8_t a",
+      "int16x8_t b",
+      "int16x8_t c"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vn.8H"
+      },
+      "c": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_s64",
+    "name": "vqrdmlshq_s32",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "int32x4_t a",
+      "int32x4_t b",
+      "int32x4_t c"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vn.4S"
+      },
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_s8",
+    "name": "vqrdmlshs_lane_s32",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "int32_t a",
+      "int32_t b",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Sd"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_u16",
+    "name": "vqrdmlshs_laneq_s32",
     "arguments": [
-      "uint16x4_t a",
-      "int16x4_t b"
+      "int32_t a",
+      "int32_t b",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Sd"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Sn"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_u32",
+    "name": "vqrdmlshs_s32",
     "arguments": [
-      "uint32x2_t a",
-      "int32x2_t b"
+      "int32_t a",
+      "int32_t b",
+      "int32_t c"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Sd"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Sn"
+      },
+      "c": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMLSH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_u64",
+    "name": "vqrdmulh_lane_s16",
     "arguments": [
-      "uint64x1_t a",
-      "int64x1_t b"
+      "int16x4_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Dm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -72990,26 +275638,31 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshl_u8",
+    "name": "vqrdmulh_lane_s32",
     "arguments": [
-      "uint8x8_t a",
-      "int8x8_t b"
+      "int32x2_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2S"
       },
-      "b": {
-        "register": "Vm.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -73019,27 +275672,31 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlb_n_s8",
+    "name": "vqrdmulh_laneq_s16",
     "arguments": [
-      "int8_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.4H"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
         "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -73047,27 +275704,31 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlb_n_u8",
+    "name": "vqrdmulh_laneq_s32",
     "arguments": [
-      "uint8_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.2S"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -73075,136 +275736,147 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlb_s8",
+    "name": "vqrdmulh_n_s16",
     "arguments": [
-      "int8_t a",
-      "int8_t b"
+      "int16x4_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Bm"
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlb_u8",
+    "name": "vqrdmulh_n_s32",
     "arguments": [
-      "uint8_t a",
-      "int8_t b"
+      "int32x2_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Bm"
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshld_n_s64",
+    "name": "vqrdmulh_s16",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.4H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshld_n_u64",
+    "name": "vqrdmulh_s32",
     "arguments": [
-      "uint64_t a",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshld_s64",
+    "name": "vqrdmulhh_lane_s16",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "int16_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Hn"
       },
-      "b": {
-        "register": "Dm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -73212,26 +275884,31 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshld_u64",
+    "name": "vqrdmulhh_laneq_s16",
     "arguments": [
-      "uint64_t a",
-      "int64_t b"
+      "int16_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Hn"
       },
-      "b": {
-        "register": "Dm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -73239,16 +275916,16 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlh_n_s16",
+    "name": "vqrdmulhh_s16",
     "arguments": [
       "int16_t a",
-      "const int n"
+      "int16_t b"
     ],
     "return_type": {
       "value": "int16_t"
@@ -73257,9 +275934,8 @@
       "a": {
         "register": "Hn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -73267,81 +275943,99 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlh_n_u16",
+    "name": "vqrdmulhq_lane_s16",
     "arguments": [
-      "uint16_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.8H"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlh_s16",
+    "name": "vqrdmulhq_lane_s32",
     "arguments": [
-      "int16_t a",
-      "int16_t b"
+      "int32x4_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Hm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlh_u16",
+    "name": "vqrdmulhq_laneq_s16",
     "arguments": [
-      "uint16_t a",
-      "int16_t b"
+      "int16x8_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Hm"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -73349,57 +276043,58 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_s16",
+    "name": "vqrdmulhq_laneq_s32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_s32",
+    "name": "vqrdmulhq_n_s16",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Vm.H[0]"
       }
     },
     "Architectures": [
@@ -73409,27 +276104,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_s64",
+    "name": "vqrdmulhq_n_s32",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.S[0]"
       }
     },
     "Architectures": [
@@ -73439,27 +276133,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_s8",
+    "name": "vqrdmulhq_s16",
     "arguments": [
-      "int8x16_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -73469,27 +276162,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_u16",
+    "name": "vqrdmulhq_s32",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -73499,116 +276191,117 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_u32",
+    "name": "vqrdmulhs_lane_s32",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "int32_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Sn"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
-        "maximum": 31
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_u64",
+    "name": "vqrdmulhs_laneq_s32",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "int32_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Sn"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
-        "maximum": 63
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_n_u8",
+    "name": "vqrdmulhs_s32",
     "arguments": [
-      "uint8x16_t a",
-      "const int n"
+      "int32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Sn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSHL"
+        "SQRDMULH"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_s16",
+    "name": "vqrshl_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -73618,26 +276311,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_s32",
+    "name": "vqrshl_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -73647,26 +276340,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_s64",
+    "name": "vqrshl_s64",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -73676,26 +276369,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_s8",
+    "name": "vqrshl_s8",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -73705,26 +276398,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_u16",
+    "name": "vqrshl_u16",
     "arguments": [
-      "uint16x8_t a",
-      "int16x8_t b"
+      "uint16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -73734,26 +276427,26 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_u32",
+    "name": "vqrshl_u32",
     "arguments": [
-      "uint32x4_t a",
-      "int32x4_t b"
+      "uint32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -73763,26 +276456,26 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_u64",
+    "name": "vqrshl_u64",
     "arguments": [
-      "uint64x2_t a",
-      "int64x2_t b"
+      "uint64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -73792,26 +276485,26 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlq_u8",
+    "name": "vqrshl_u8",
     "arguments": [
-      "uint8x16_t a",
-      "int8x16_t b"
+      "uint8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -73821,27 +276514,26 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshls_n_s32",
+    "name": "vqrshlb_s8",
     "arguments": [
-      "int32_t a",
-      "const int n"
+      "int8_t a",
+      "int8_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Bn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Bm"
       }
     },
     "Architectures": [
@@ -73849,27 +276541,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshls_n_u32",
+    "name": "vqrshlb_u8",
     "arguments": [
-      "uint32_t a",
-      "const int n"
+      "uint8_t a",
+      "int8_t b"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Bn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Bm"
       }
     },
     "Architectures": [
@@ -73877,26 +276568,26 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshls_s32",
+    "name": "vqrshld_s64",
     "arguments": [
-      "int32_t a",
-      "int32_t b"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Dn"
       },
       "b": {
-        "register": "Sm"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -73904,26 +276595,26 @@
     ],
     "instructions": [
       [
-        "SQSHL"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshls_u32",
+    "name": "vqrshld_u64",
     "arguments": [
-      "uint32_t a",
-      "int32_t b"
+      "uint64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Dn"
       },
       "b": {
-        "register": "Sm"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -73931,87 +276622,80 @@
     ],
     "instructions": [
       [
-        "UQSHL"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlu_n_s16",
+    "name": "vqrshlh_s16",
     "arguments": [
-      "int16x4_t a",
-      "const int n"
+      "int16_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Hn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlu_n_s32",
+    "name": "vqrshlh_u16",
     "arguments": [
-      "int32x2_t a",
-      "const int n"
+      "uint16_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Hn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlu_n_s64",
+    "name": "vqrshlq_s16",
     "arguments": [
-      "int64x1_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -74021,27 +276705,26 @@
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlu_n_s8",
+    "name": "vqrshlq_s32",
     "arguments": [
-      "int8x8_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -74051,111 +276734,113 @@
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlub_n_s8",
+    "name": "vqrshlq_s64",
     "arguments": [
-      "int8_t a",
-      "const int n"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bn"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlud_n_s64",
+    "name": "vqrshlq_s8",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.16B"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshluh_n_s16",
+    "name": "vqrshlq_u16",
     "arguments": [
-      "int16_t a",
-      "const int n"
+      "uint16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshluq_n_s16",
+    "name": "vqrshlq_u32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "uint32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -74165,27 +276850,26 @@
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshluq_n_s32",
+    "name": "vqrshlq_u64",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "uint64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -74195,27 +276879,26 @@
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshluq_n_s64",
+    "name": "vqrshlq_u8",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "uint8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -74225,46 +276908,43 @@
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshluq_n_s8",
+    "name": "vqrshls_s32",
     "arguments": [
-      "int8x16_t a",
-      "const int n"
+      "int32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Sn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "SQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshlus_n_s32",
+    "name": "vqrshls_u32",
     "arguments": [
-      "int32_t a",
-      "const int n"
+      "uint32_t a",
+      "int32_t b"
     ],
     "return_type": {
       "value": "uint32_t"
@@ -74273,9 +276953,8 @@
       "a": {
         "register": "Sn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
@@ -74283,13 +276962,13 @@
     ],
     "instructions": [
       [
-        "SQSHLU"
+        "UQRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_high_n_s16",
+    "name": "vqrshrn_high_n_s16",
     "arguments": [
       "int8x8_t r",
       "int16x8_t a",
@@ -74315,13 +276994,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN2"
+        "SQRSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_high_n_s32",
+    "name": "vqrshrn_high_n_s32",
     "arguments": [
       "int16x4_t r",
       "int32x4_t a",
@@ -74347,13 +277026,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN2"
+        "SQRSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_high_n_s64",
+    "name": "vqrshrn_high_n_s64",
     "arguments": [
       "int32x2_t r",
       "int64x2_t a",
@@ -74379,13 +277058,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN2"
+        "SQRSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_high_n_u16",
+    "name": "vqrshrn_high_n_u16",
     "arguments": [
       "uint8x8_t r",
       "uint16x8_t a",
@@ -74411,13 +277090,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN2"
+        "UQRSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_high_n_u32",
+    "name": "vqrshrn_high_n_u32",
     "arguments": [
       "uint16x4_t r",
       "uint32x4_t a",
@@ -74443,13 +277122,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN2"
+        "UQRSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_high_n_u64",
+    "name": "vqrshrn_high_n_u64",
     "arguments": [
       "uint32x2_t r",
       "uint64x2_t a",
@@ -74475,13 +277154,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN2"
+        "UQRSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_n_s16",
+    "name": "vqrshrn_n_s16",
     "arguments": [
       "int16x8_t a",
       "const int n"
@@ -74505,13 +277184,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN"
+        "SQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_n_s32",
+    "name": "vqrshrn_n_s32",
     "arguments": [
       "int32x4_t a",
       "const int n"
@@ -74535,13 +277214,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN"
+        "SQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_n_s64",
+    "name": "vqrshrn_n_s64",
     "arguments": [
       "int64x2_t a",
       "const int n"
@@ -74565,13 +277244,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN"
+        "SQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_n_u16",
+    "name": "vqrshrn_n_u16",
     "arguments": [
       "uint16x8_t a",
       "const int n"
@@ -74595,13 +277274,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN"
+        "UQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_n_u32",
+    "name": "vqrshrn_n_u32",
     "arguments": [
       "uint32x4_t a",
       "const int n"
@@ -74625,13 +277304,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN"
+        "UQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrn_n_u64",
+    "name": "vqrshrn_n_u64",
     "arguments": [
       "uint64x2_t a",
       "const int n"
@@ -74655,13 +277334,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN"
+        "UQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrnd_n_s64",
+    "name": "vqrshrnd_n_s64",
     "arguments": [
       "int64_t a",
       "const int n"
@@ -74683,13 +277362,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN"
+        "SQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrnd_n_u64",
+    "name": "vqrshrnd_n_u64",
     "arguments": [
       "uint64_t a",
       "const int n"
@@ -74711,13 +277390,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN"
+        "UQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrnh_n_s16",
+    "name": "vqrshrnh_n_s16",
     "arguments": [
       "int16_t a",
       "const int n"
@@ -74739,13 +277418,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN"
+        "SQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrnh_n_u16",
+    "name": "vqrshrnh_n_u16",
     "arguments": [
       "uint16_t a",
       "const int n"
@@ -74767,13 +277446,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN"
+        "UQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrns_n_s32",
+    "name": "vqrshrns_n_s32",
     "arguments": [
       "int32_t a",
       "const int n"
@@ -74795,13 +277474,13 @@
     ],
     "instructions": [
       [
-        "SQSHRN"
+        "SQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrns_n_u32",
+    "name": "vqrshrns_n_u32",
     "arguments": [
       "uint32_t a",
       "const int n"
@@ -74823,13 +277502,13 @@
     ],
     "instructions": [
       [
-        "UQSHRN"
+        "UQRSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrun_high_n_s16",
+    "name": "vqrshrun_high_n_s16",
     "arguments": [
       "uint8x8_t r",
       "int16x8_t a",
@@ -74855,13 +277534,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN2"
+        "SQRSHRUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrun_high_n_s32",
+    "name": "vqrshrun_high_n_s32",
     "arguments": [
       "uint16x4_t r",
       "int32x4_t a",
@@ -74887,13 +277566,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN2"
+        "SQRSHRUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrun_high_n_s64",
+    "name": "vqrshrun_high_n_s64",
     "arguments": [
       "uint32x2_t r",
       "int64x2_t a",
@@ -74919,13 +277598,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN2"
+        "SQRSHRUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrun_n_s16",
+    "name": "vqrshrun_n_s16",
     "arguments": [
       "int16x8_t a",
       "const int n"
@@ -74949,13 +277628,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN"
+        "SQRSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrun_n_s32",
+    "name": "vqrshrun_n_s32",
     "arguments": [
       "int32x4_t a",
       "const int n"
@@ -74979,13 +277658,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN"
+        "SQRSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrun_n_s64",
+    "name": "vqrshrun_n_s64",
     "arguments": [
       "int64x2_t a",
       "const int n"
@@ -75009,13 +277688,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN"
+        "SQRSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrund_n_s64",
+    "name": "vqrshrund_n_s64",
     "arguments": [
       "int64_t a",
       "const int n"
@@ -75037,13 +277716,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN"
+        "SQRSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshrunh_n_s16",
+    "name": "vqrshrunh_n_s16",
     "arguments": [
       "int16_t a",
       "const int n"
@@ -75065,13 +277744,13 @@
     ],
     "instructions": [
       [
-        "SQSHRUN"
+        "SQRSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqshruns_n_s32",
+    "name": "vqrshruns_n_s32",
     "arguments": [
       "int32_t a",
       "const int n"
@@ -75093,13 +277772,253 @@
     ],
     "instructions": [
       [
-        "SQSHRUN"
+        "SQRSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_s16",
+    "name": "vqshl_n_s16",
+    "arguments": [
+      "int16x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_s32",
+    "arguments": [
+      "int32x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_s64",
+    "arguments": [
+      "int64x1_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_s8",
+    "arguments": [
+      "int8x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_u64",
+    "arguments": [
+      "uint64x1_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_n_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshl_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
@@ -75122,13 +278041,13 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_s32",
+    "name": "vqshl_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
@@ -75151,13 +278070,13 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_s64",
+    "name": "vqshl_s64",
     "arguments": [
       "int64x1_t a",
       "int64x1_t b"
@@ -75180,13 +278099,13 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_s8",
+    "name": "vqshl_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
@@ -75209,16 +278128,16 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_u16",
+    "name": "vqshl_u16",
     "arguments": [
       "uint16x4_t a",
-      "uint16x4_t b"
+      "int16x4_t b"
     ],
     "return_type": {
       "value": "uint16x4_t"
@@ -75238,16 +278157,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_u32",
+    "name": "vqshl_u32",
     "arguments": [
       "uint32x2_t a",
-      "uint32x2_t b"
+      "int32x2_t b"
     ],
     "return_type": {
       "value": "uint32x2_t"
@@ -75267,16 +278186,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_u64",
+    "name": "vqshl_u64",
     "arguments": [
       "uint64x1_t a",
-      "uint64x1_t b"
+      "int64x1_t b"
     ],
     "return_type": {
       "value": "uint64x1_t"
@@ -75296,16 +278215,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsub_u8",
+    "name": "vqshl_u8",
     "arguments": [
       "uint8x8_t a",
-      "uint8x8_t b"
+      "int8x8_t b"
     ],
     "return_type": {
       "value": "uint8x8_t"
@@ -75325,13 +278244,69 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubb_s8",
+    "name": "vqshlb_n_s8",
+    "arguments": [
+      "int8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Bn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlb_n_u8",
+    "arguments": [
+      "uint8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Bn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlb_s8",
     "arguments": [
       "int8_t a",
       "int8_t b"
@@ -75352,16 +278327,16 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubb_u8",
+    "name": "vqshlb_u8",
     "arguments": [
       "uint8_t a",
-      "uint8_t b"
+      "int8_t b"
     ],
     "return_type": {
       "value": "uint8_t"
@@ -75379,13 +278354,69 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubd_s64",
+    "name": "vqshld_n_s64",
+    "arguments": [
+      "int64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshld_n_u64",
+    "arguments": [
+      "uint64_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshld_s64",
     "arguments": [
       "int64_t a",
       "int64_t b"
@@ -75406,94 +278437,390 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshld_u64",
+    "arguments": [
+      "uint64_t a",
+      "int64_t b"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlh_n_s16",
+    "arguments": [
+      "int16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlh_n_u16",
+    "arguments": [
+      "uint16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlh_s16",
+    "arguments": [
+      "int16_t a",
+      "int16_t b"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlh_u16",
+    "arguments": [
+      "uint16_t a",
+      "int16_t b"
+    ],
+    "return_type": {
+      "value": "uint16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlq_n_s16",
+    "arguments": [
+      "int16x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlq_n_s32",
+    "arguments": [
+      "int32x4_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlq_n_s64",
+    "arguments": [
+      "int64x2_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlq_n_s8",
+    "arguments": [
+      "int8x16_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshlq_n_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "const int n"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubd_u64",
+    "name": "vqshlq_n_u32",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "uint32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Dm"
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubh_s16",
+    "name": "vqshlq_n_u64",
     "arguments": [
-      "int16_t a",
-      "int16_t b"
+      "uint64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Hm"
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubh_u16",
+    "name": "vqshlq_n_u8",
     "arguments": [
-      "uint16_t a",
-      "uint16_t b"
+      "uint8x16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Hm"
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_s16",
+    "name": "vqshlq_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
@@ -75516,13 +278843,13 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_s32",
+    "name": "vqshlq_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
@@ -75545,13 +278872,13 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_s64",
+    "name": "vqshlq_s64",
     "arguments": [
       "int64x2_t a",
       "int64x2_t b"
@@ -75574,13 +278901,13 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_s8",
+    "name": "vqshlq_s8",
     "arguments": [
       "int8x16_t a",
       "int8x16_t b"
@@ -75603,16 +278930,16 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_u16",
+    "name": "vqshlq_u16",
     "arguments": [
       "uint16x8_t a",
-      "uint16x8_t b"
+      "int16x8_t b"
     ],
     "return_type": {
       "value": "uint16x8_t"
@@ -75632,16 +278959,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_u32",
+    "name": "vqshlq_u32",
     "arguments": [
       "uint32x4_t a",
-      "uint32x4_t b"
+      "int32x4_t b"
     ],
     "return_type": {
       "value": "uint32x4_t"
@@ -75661,16 +278988,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_u64",
+    "name": "vqshlq_u64",
     "arguments": [
       "uint64x2_t a",
-      "uint64x2_t b"
+      "int64x2_t b"
     ],
     "return_type": {
       "value": "uint64x2_t"
@@ -75690,16 +279017,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubq_u8",
+    "name": "vqshlq_u8",
     "arguments": [
       "uint8x16_t a",
-      "uint8x16_t b"
+      "int8x16_t b"
     ],
     "return_type": {
       "value": "uint8x16_t"
@@ -75719,16 +279046,16 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubs_s32",
+    "name": "vqshls_n_s32",
     "arguments": [
       "int32_t a",
-      "int32_t b"
+      "const int n"
     ],
     "return_type": {
       "value": "int32_t"
@@ -75737,8 +279064,9 @@
       "a": {
         "register": "Sn"
       },
-      "b": {
-        "register": "Sm"
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
@@ -75746,20 +279074,48 @@
     ],
     "instructions": [
       [
-        "SQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqsubs_u32",
+    "name": "vqshls_n_u32",
     "arguments": [
       "uint32_t a",
-      "uint32_t b"
+      "const int n"
     ],
     "return_type": {
       "value": "uint32_t"
     },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "UQSHL"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vqshls_s32",
+    "arguments": [
+      "int32_t a",
+      "int32_t b"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
     "Arguments_Preparation": {
       "a": {
         "register": "Sn"
@@ -75773,26 +279129,26 @@
     ],
     "instructions": [
       [
-        "UQSUB"
+        "SQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl1_p8",
+    "name": "vqshls_u32",
     "arguments": [
-      "poly8x16_t t",
-      "uint8x8_t idx"
+      "uint32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Sn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
@@ -75800,134 +279156,147 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "UQSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl1_s8",
+    "name": "vqshlu_n_s16",
     "arguments": [
-      "int8x16_t t",
-      "uint8x8_t idx"
+      "int16x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.4H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl1_u8",
+    "name": "vqshlu_n_s32",
     "arguments": [
-      "uint8x16_t t",
-      "uint8x8_t idx"
+      "int32x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.2S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl1q_p8",
+    "name": "vqshlu_n_s64",
     "arguments": [
-      "poly8x16_t t",
-      "uint8x16_t idx"
+      "int64x1_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl1q_s8",
+    "name": "vqshlu_n_s8",
     "arguments": [
-      "int8x16_t t",
-      "uint8x16_t idx"
+      "int8x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.8B"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl1q_u8",
+    "name": "vqshlub_n_s8",
     "arguments": [
-      "uint8x16_t t",
-      "uint8x16_t idx"
+      "int8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Bn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
@@ -75935,26 +279304,27 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl2_p8",
+    "name": "vqshlud_n_s64",
     "arguments": [
-      "poly8x16x2_t t",
-      "uint8x8_t idx"
+      "int64_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
@@ -75962,26 +279332,27 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl2_s8",
+    "name": "vqshluh_n_s16",
     "arguments": [
-      "int8x16x2_t t",
-      "uint8x8_t idx"
+      "int16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Hn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
@@ -75989,134 +279360,147 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl2_u8",
+    "name": "vqshluq_n_s16",
     "arguments": [
-      "uint8x16x2_t t",
-      "uint8x8_t idx"
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.8H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl2q_p8",
+    "name": "vqshluq_n_s32",
     "arguments": [
-      "poly8x16x2_t t",
-      "uint8x16_t idx"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.4S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl2q_s8",
+    "name": "vqshluq_n_s64",
     "arguments": [
-      "int8x16x2_t t",
-      "uint8x16_t idx"
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.2D"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl2q_u8",
+    "name": "vqshluq_n_s8",
     "arguments": [
-      "uint8x16x2_t t",
-      "uint8x16_t idx"
+      "int8x16_t a",
+      "const int n"
     ],
     "return_type": {
       "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
-      },
-      "t": {
+      "a": {
         "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl3_p8",
+    "name": "vqshlus_n_s32",
     "arguments": [
-      "poly8x16x3_t t",
-      "uint8x8_t idx"
+      "int32_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Sn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
@@ -76124,26 +279508,31 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHLU"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl3_s8",
+    "name": "vqshrn_high_n_s16",
     "arguments": [
-      "int8x16x3_t t",
-      "uint8x8_t idx"
+      "int8x8_t r",
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.8H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -76151,26 +279540,31 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl3_u8",
+    "name": "vqshrn_high_n_s32",
     "arguments": [
-      "uint8x16x3_t t",
-      "uint8x8_t idx"
+      "int16x4_t r",
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.4S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -76178,26 +279572,31 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl3q_p8",
+    "name": "vqshrn_high_n_s64",
     "arguments": [
-      "poly8x16x3_t t",
-      "uint8x16_t idx"
+      "int32x2_t r",
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.2D"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -76205,26 +279604,31 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl3q_s8",
+    "name": "vqshrn_high_n_u16",
     "arguments": [
-      "int8x16x3_t t",
-      "uint8x16_t idx"
+      "uint8x8_t r",
+      "uint16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.8H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -76232,26 +279636,31 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "UQSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl3q_u8",
+    "name": "vqshrn_high_n_u32",
     "arguments": [
-      "uint8x16x3_t t",
-      "uint8x16_t idx"
+      "uint16x4_t r",
+      "uint32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.4S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -76259,26 +279668,31 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "UQSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl4_p8",
+    "name": "vqshrn_high_n_u64",
     "arguments": [
-      "poly8x16x4_t t",
-      "uint8x8_t idx"
+      "uint32x2_t r",
+      "uint64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.2D"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -76286,196 +279700,207 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "UQSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl4_s8",
+    "name": "vqshrn_n_s16",
     "arguments": [
-      "int8x16x4_t t",
-      "uint8x8_t idx"
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
       "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.8H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl4_u8",
+    "name": "vqshrn_n_s32",
     "arguments": [
-      "uint8x16x4_t t",
-      "uint8x8_t idx"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.8B"
+      "a": {
+        "register": "Vn.4S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl4q_p8",
+    "name": "vqshrn_n_s64",
     "arguments": [
-      "poly8x16x4_t t",
-      "uint8x16_t idx"
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.2D"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "SQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl4q_s8",
+    "name": "vqshrn_n_u16",
     "arguments": [
-      "int8x16x4_t t",
-      "uint8x16_t idx"
+      "uint16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.8H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "UQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbl4q_u8",
+    "name": "vqshrn_n_u32",
     "arguments": [
-      "uint8x16x4_t t",
-      "uint8x16_t idx"
+      "uint32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "idx": {
-        "register": "Vm.16B"
+      "a": {
+        "register": "Vn.4S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "UQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx1_p8",
+    "name": "vqshrn_n_u64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x16_t t",
-      "uint8x8_t idx"
+      "uint64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Vn.2D"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx1_s8",
+    "name": "vqshrnd_n_s64",
     "arguments": [
-      "int8x8_t a",
-      "int8x16_t t",
-      "uint8x8_t idx"
+      "int64_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -76483,30 +279908,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx1_u8",
+    "name": "vqshrnd_n_u64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x16_t t",
-      "uint8x8_t idx"
+      "uint64_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -76514,30 +279936,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx1q_p8",
+    "name": "vqshrnh_n_s16",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t t",
-      "uint8x16_t idx"
+      "int16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Hn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -76545,30 +279964,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx1q_s8",
+    "name": "vqshrnh_n_u16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t t",
-      "uint8x16_t idx"
+      "uint16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Hn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -76576,30 +279992,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx1q_u8",
+    "name": "vqshrns_n_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t t",
-      "uint8x16_t idx"
+      "int32_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Sn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -76607,30 +280020,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx2_p8",
+    "name": "vqshrns_n_u32",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x16x2_t t",
-      "uint8x8_t idx"
+      "uint32_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Sn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -76638,30 +280048,31 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx2_s8",
+    "name": "vqshrun_high_n_s16",
     "arguments": [
-      "int8x8_t a",
-      "int8x16x2_t t",
-      "uint8x8_t idx"
+      "uint8x8_t r",
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.8H"
       },
-      "idx": {
-        "register": "Vm.8B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       },
-      "t": {
-        "register": "Vn.16B"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -76669,30 +280080,31 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx2_u8",
+    "name": "vqshrun_high_n_s32",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x16x2_t t",
-      "uint8x8_t idx"
+      "uint16x4_t r",
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.4S"
       },
-      "idx": {
-        "register": "Vm.8B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       },
-      "t": {
-        "register": "Vn.16B"
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -76700,30 +280112,31 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx2q_p8",
+    "name": "vqshrun_high_n_s64",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16x2_t t",
-      "uint8x16_t idx"
+      "uint32x2_t r",
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vn.2D"
       },
-      "idx": {
-        "register": "Vm.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       },
-      "t": {
-        "register": "Vn.16B"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -76731,123 +280144,117 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx2q_s8",
+    "name": "vqshrun_n_s16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16x2_t t",
-      "uint8x16_t idx"
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Vn.8H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx2q_u8",
+    "name": "vqshrun_n_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16x2_t t",
-      "uint8x16_t idx"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Vn.4S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx3_p8",
+    "name": "vqshrun_n_s64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x16x3_t t",
-      "uint8x8_t idx"
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Vn.2D"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx3_s8",
+    "name": "vqshrund_n_s64",
     "arguments": [
-      "int8x8_t a",
-      "int8x16x3_t t",
-      "uint8x8_t idx"
+      "int64_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -76855,30 +280262,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx3_u8",
+    "name": "vqshrunh_n_s16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x16x3_t t",
-      "uint8x8_t idx"
+      "int16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Hn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -76886,30 +280290,27 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx3q_p8",
+    "name": "vqshruns_n_s32",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16x3_t t",
-      "uint8x16_t idx"
+      "int32_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Sn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -76917,278 +280318,258 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSHRUN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx3q_s8",
+    "name": "vqsub_s16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16x3_t t",
-      "uint8x16_t idx"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Vn.4H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx3q_u8",
+    "name": "vqsub_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16x3_t t",
-      "uint8x16_t idx"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Vn.2S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx4_p8",
+    "name": "vqsub_s64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x16x4_t t",
-      "uint8x8_t idx"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx4_s8",
+    "name": "vqsub_s8",
     "arguments": [
       "int8x8_t a",
-      "int8x16x4_t t",
-      "uint8x8_t idx"
+      "int8x8_t b"
     ],
     "return_type": {
       "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.8B"
       },
-      "idx": {
+      "b": {
         "register": "Vm.8B"
-      },
-      "t": {
-        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx4_u8",
+    "name": "vqsub_u16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x16x4_t t",
-      "uint8x8_t idx"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "idx": {
-        "register": "Vm.8B"
+        "register": "Vn.4H"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx4q_p8",
+    "name": "vqsub_u32",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16x4_t t",
-      "uint8x16_t idx"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Vn.2S"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx4q_s8",
+    "name": "vqsub_u64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16x4_t t",
-      "uint8x16_t idx"
+      "uint64x1_t a",
+      "uint64x1_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Dn"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vqtbx4q_u8",
+    "name": "vqsub_u8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16x4_t t",
-      "uint8x16_t idx"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "idx": {
-        "register": "Vm.16B"
+        "register": "Vn.8B"
       },
-      "t": {
-        "register": "Vn.16B"
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_high_s16",
+    "name": "vqsubb_s8",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a",
-      "int16x8_t b"
+      "int8_t a",
+      "int8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Bn"
       },
       "b": {
-        "register": "Vm.8H"
-      },
-      "r": {
-        "register": "Vd.8B"
+        "register": "Bm"
       }
     },
     "Architectures": [
@@ -77196,30 +280577,26 @@
     ],
     "instructions": [
       [
-        "RADDHN2"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_high_s32",
+    "name": "vqsubb_u8",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a",
-      "int32x4_t b"
+      "uint8_t a",
+      "uint8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Bn"
       },
       "b": {
-        "register": "Vm.4S"
-      },
-      "r": {
-        "register": "Vd.4H"
+        "register": "Bm"
       }
     },
     "Architectures": [
@@ -77227,30 +280604,26 @@
     ],
     "instructions": [
       [
-        "RADDHN2"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_high_s64",
+    "name": "vqsubd_s64",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a",
-      "int64x2_t b"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.2D"
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -77258,30 +280631,26 @@
     ],
     "instructions": [
       [
-        "RADDHN2"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_high_u16",
+    "name": "vqsubd_u64",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "uint64_t a",
+      "uint64_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.8H"
-      },
-      "r": {
-        "register": "Vd.8B"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -77289,30 +280658,26 @@
     ],
     "instructions": [
       [
-        "RADDHN2"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_high_u32",
+    "name": "vqsubh_s16",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int16_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Hn"
       },
       "b": {
-        "register": "Vm.4S"
-      },
-      "r": {
-        "register": "Vd.4H"
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -77320,30 +280685,26 @@
     ],
     "instructions": [
       [
-        "RADDHN2"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_high_u64",
+    "name": "vqsubh_u16",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint16_t a",
+      "uint16_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Hn"
       },
       "b": {
-        "register": "Vm.2D"
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Hm"
       }
     },
     "Architectures": [
@@ -77351,19 +280712,19 @@
     ],
     "instructions": [
       [
-        "RADDHN2"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_s16",
+    "name": "vqsubq_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -77380,19 +280741,19 @@
     ],
     "instructions": [
       [
-        "RADDHN"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_s32",
+    "name": "vqsubq_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -77409,19 +280770,19 @@
     ],
     "instructions": [
       [
-        "RADDHN"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_s64",
+    "name": "vqsubq_s64",
     "arguments": [
       "int64x2_t a",
       "int64x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -77438,26 +280799,26 @@
     ],
     "instructions": [
       [
-        "RADDHN"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_u16",
+    "name": "vqsubq_s8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -77467,26 +280828,26 @@
     ],
     "instructions": [
       [
-        "RADDHN"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_u32",
+    "name": "vqsubq_u16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -77496,26 +280857,26 @@
     ],
     "instructions": [
       [
-        "RADDHN"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vraddhn_u64",
+    "name": "vqsubq_u32",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -77525,13 +280886,13 @@
     ],
     "instructions": [
       [
-        "RADDHN"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrax1q_u64",
+    "name": "vqsubq_u64",
     "arguments": [
       "uint64x2_t a",
       "uint64x2_t b"
@@ -77543,52 +280904,66 @@
       "a": {
         "register": "Vn.2D"
       },
-      "b": {}
+      "b": {
+        "register": "Vm.2D"
+      }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RAX1"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrbit_p8",
+    "name": "vqsubq_u8",
     "arguments": [
-      "poly8x8_t a"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RBIT"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrbit_s8",
+    "name": "vqsubs_s32",
     "arguments": [
-      "int8x8_t a"
+      "int32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
@@ -77596,22 +280971,26 @@
     ],
     "instructions": [
       [
-        "RBIT"
+        "SQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrbit_u8",
+    "name": "vqsubs_u32",
     "arguments": [
-      "uint8x8_t a"
+      "uint32_t a",
+      "uint32_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
@@ -77619,21 +280998,25 @@
     ],
     "instructions": [
       [
-        "RBIT"
+        "UQSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrbitq_p8",
+    "name": "vqtbl1_p8",
     "arguments": [
-      "poly8x16_t a"
+      "poly8x16_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t": {
         "register": "Vn.16B"
       }
     },
@@ -77642,21 +281025,25 @@
     ],
     "instructions": [
       [
-        "RBIT"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrbitq_s8",
+    "name": "vqtbl1_s8",
     "arguments": [
-      "int8x16_t a"
+      "int8x16_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t": {
         "register": "Vn.16B"
       }
     },
@@ -77665,21 +281052,25 @@
     ],
     "instructions": [
       [
-        "RBIT"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrbitq_u8",
+    "name": "vqtbl1_u8",
     "arguments": [
-      "uint8x16_t a"
+      "uint8x16_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t": {
         "register": "Vn.16B"
       }
     },
@@ -77688,71 +281079,80 @@
     ],
     "instructions": [
       [
-        "RBIT"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpe_f16",
+    "name": "vqtbl1q_p8",
     "arguments": [
-      "float16x4_t a"
+      "poly8x16_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpe_f32",
+    "name": "vqtbl1q_s8",
     "arguments": [
-      "float32x2_t a"
+      "int8x16_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpe_f64",
+    "name": "vqtbl1q_u8",
     "arguments": [
-      "float64x1_t a"
+      "uint8x16_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -77760,47 +281160,59 @@
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpe_u32",
+    "name": "vqtbl2_p8",
     "arguments": [
-      "uint32x2_t a"
+      "poly8x16x2_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecped_f64",
+    "name": "vqtbl2_s8",
     "arguments": [
-      "float64_t a"
+      "int8x16x2_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
@@ -77808,22 +281220,29 @@
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpeh_f16",
+    "name": "vqtbl2_u8",
     "arguments": [
-      "float16_t a"
+      "uint8x16x2_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
@@ -77831,71 +281250,89 @@
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpeq_f16",
+    "name": "vqtbl2q_p8",
     "arguments": [
-      "float16x8_t a"
+      "poly8x16x2_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpeq_f32",
+    "name": "vqtbl2q_s8",
     "arguments": [
-      "float32x4_t a"
+      "int8x16x2_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpeq_f64",
+    "name": "vqtbl2q_u8",
     "arguments": [
-      "float64x2_t a"
+      "uint8x16x2_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
@@ -77903,47 +281340,65 @@
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpeq_u32",
+    "name": "vqtbl3_p8",
     "arguments": [
-      "uint32x4_t a"
+      "poly8x16x3_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpes_f32",
+    "name": "vqtbl3_s8",
     "arguments": [
-      "float32_t a"
+      "int8x16x3_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
@@ -77951,83 +281406,98 @@
     ],
     "instructions": [
       [
-        "FRECPE"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecps_f16",
+    "name": "vqtbl3_u8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "uint8x16x3_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "idx": {
+        "register": "Vm.8B"
       },
-      "b": {
-        "register": "Vm.4H"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecps_f32",
+    "name": "vqtbl3q_p8",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "poly8x16x3_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "idx": {
+        "register": "Vm.16B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecps_f64",
+    "name": "vqtbl3q_s8",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "int8x16x3_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "idx": {
+        "register": "Vm.16B"
       },
-      "b": {
-        "register": "Dm"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
@@ -78035,26 +281505,32 @@
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpsd_f64",
+    "name": "vqtbl3q_u8",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "uint8x16x3_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "idx": {
+        "register": "Vm.16B"
       },
-      "b": {
-        "register": "Dm"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
@@ -78062,26 +281538,35 @@
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpsh_f16",
+    "name": "vqtbl4_p8",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "poly8x16x4_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "idx": {
+        "register": "Vm.8B"
       },
-      "b": {
-        "register": "Hm"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
@@ -78089,83 +281574,107 @@
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpsq_f16",
+    "name": "vqtbl4_s8",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int8x16x4_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "idx": {
+        "register": "Vm.8B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpsq_f32",
+    "name": "vqtbl4_u8",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "uint8x16x4_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "idx": {
+        "register": "Vm.8B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpsq_f64",
+    "name": "vqtbl4q_p8",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "poly8x16x4_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "idx": {
+        "register": "Vm.16B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
@@ -78173,26 +281682,35 @@
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpss_f32",
+    "name": "vqtbl4q_s8",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "int8x16x4_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "idx": {
+        "register": "Vm.16B"
       },
-      "b": {
-        "register": "Sm"
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
@@ -78200,22 +281718,35 @@
     ],
     "instructions": [
       [
-        "FRECPS"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpxd_f64",
+    "name": "vqtbl4q_u8",
     "arguments": [
-      "float64_t a"
+      "uint8x16x4_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
@@ -78223,22 +281754,30 @@
     ],
     "instructions": [
       [
-        "FRECPX"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpxh_f16",
+    "name": "vqtbx1_p8",
     "arguments": [
-      "float16_t a"
+      "poly8x8_t a",
+      "poly8x16_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -78246,22 +281785,30 @@
     ],
     "instructions": [
       [
-        "FRECPX"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrecpxs_f32",
+    "name": "vqtbx1_s8",
     "arguments": [
-      "float32_t a"
+      "int8x8_t a",
+      "int8x16_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -78269,47 +281816,61 @@
     ],
     "instructions": [
       [
-        "FRECPX"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_f32",
+    "name": "vqtbx1_u8",
     "arguments": [
-      "float32x2_t a"
+      "uint8x8_t a",
+      "uint8x16_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_f64",
+    "name": "vqtbx1q_p8",
     "arguments": [
-      "float64x1_t a"
+      "poly8x16_t a",
+      "poly8x16_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -78317,321 +281878,450 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_p16",
+    "name": "vqtbx1q_s8",
     "arguments": [
-      "poly16x4_t a"
+      "int8x16_t a",
+      "int8x16_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_p64",
+    "name": "vqtbx1q_u8",
     "arguments": [
-      "poly64x1_t a"
+      "uint8x16_t a",
+      "uint8x16_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_p8",
+    "name": "vqtbx2_p8",
     "arguments": [
-      "poly8x8_t a"
+      "poly8x8_t a",
+      "poly8x16x2_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_s16",
+    "name": "vqtbx2_s8",
     "arguments": [
-      "int16x4_t a"
+      "int8x8_t a",
+      "int8x16x2_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_s32",
+    "name": "vqtbx2_u8",
     "arguments": [
-      "int32x2_t a"
+      "uint8x8_t a",
+      "uint8x16x2_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_s64",
+    "name": "vqtbx2q_p8",
     "arguments": [
-      "int64x1_t a"
+      "poly8x16_t a",
+      "poly8x16x2_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_s8",
+    "name": "vqtbx2q_s8",
     "arguments": [
-      "int8x8_t a"
+      "int8x16_t a",
+      "int8x16x2_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_u16",
+    "name": "vqtbx2q_u8",
     "arguments": [
-      "uint16x4_t a"
+      "uint8x16_t a",
+      "uint8x16x2_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_u32",
+    "name": "vqtbx3_p8",
     "arguments": [
-      "uint32x2_t a"
+      "poly8x8_t a",
+      "poly8x16x3_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_u64",
+    "name": "vqtbx3_s8",
     "arguments": [
-      "uint64x1_t a"
+      "int8x8_t a",
+      "int8x16x3_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f16_u8",
+    "name": "vqtbx3_u8",
     "arguments": [
-      "uint8x8_t a"
+      "uint8x8_t a",
+      "uint8x16x3_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_f16",
+    "name": "vqtbx3q_p8",
     "arguments": [
-      "float16x4_t a"
+      "poly8x16_t a",
+      "poly8x16x3_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_f64",
+    "name": "vqtbx3q_s8",
     "arguments": [
-      "float64x1_t a"
+      "int8x16_t a",
+      "int8x16x3_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
@@ -78639,272 +282329,400 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_p16",
+    "name": "vqtbx3q_u8",
     "arguments": [
-      "poly16x4_t a"
+      "uint8x16_t a",
+      "uint8x16x3_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_p8",
+    "name": "vqtbx4_p8",
     "arguments": [
-      "poly8x8_t a"
+      "poly8x8_t a",
+      "poly8x16x4_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_s16",
+    "name": "vqtbx4_s8",
     "arguments": [
-      "int16x4_t a"
+      "int8x8_t a",
+      "int8x16x4_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_s32",
+    "name": "vqtbx4_u8",
     "arguments": [
-      "int32x2_t a"
+      "uint8x8_t a",
+      "uint8x16x4_t t",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.8B"
+      },
+      "idx": {
+        "register": "Vm.8B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_s64",
+    "name": "vqtbx4q_p8",
     "arguments": [
-      "int64x1_t a"
+      "poly8x16_t a",
+      "poly8x16x4_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_s8",
+    "name": "vqtbx4q_s8",
     "arguments": [
-      "int8x8_t a"
+      "int8x16_t a",
+      "int8x16x4_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_u16",
+    "name": "vqtbx4q_u8",
     "arguments": [
-      "uint16x4_t a"
+      "uint8x16_t a",
+      "uint8x16x4_t t",
+      "uint8x16_t idx"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.16B"
+      },
+      "idx": {
+        "register": "Vm.16B"
+      },
+      "t.val[0]": {
+        "register": "Vn.16B"
+      },
+      "t.val[1]": {
+        "register": "Vn+1.16B"
+      },
+      "t.val[2]": {
+        "register": "Vn+2.16B"
+      },
+      "t.val[3]": {
+        "register": "Vn+3.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_u32",
+    "name": "vraddhn_high_s16",
     "arguments": [
-      "uint32x2_t a"
+      "int8x8_t r",
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_u64",
+    "name": "vraddhn_high_s32",
     "arguments": [
-      "uint64x1_t a"
+      "int16x4_t r",
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f32_u8",
+    "name": "vraddhn_high_s64",
     "arguments": [
-      "uint8x8_t a"
+      "int32x2_t r",
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_f16",
+    "name": "vraddhn_high_u16",
     "arguments": [
-      "float16x4_t a"
+      "uint8x8_t r",
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -78912,22 +282730,30 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_f32",
+    "name": "vraddhn_high_u32",
     "arguments": [
-      "float32x2_t a"
+      "uint16x4_t r",
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -78935,22 +282761,30 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_p16",
+    "name": "vraddhn_high_u64",
     "arguments": [
-      "poly16x4_t a"
+      "uint32x2_t r",
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -78958,160 +282792,200 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_p64",
+    "name": "vraddhn_s16",
     "arguments": [
-      "poly64x1_t a"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_p8",
+    "name": "vraddhn_s32",
     "arguments": [
-      "poly8x8_t a"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_s16",
+    "name": "vraddhn_s64",
     "arguments": [
-      "int16x4_t a"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_s32",
+    "name": "vraddhn_u16",
     "arguments": [
-      "int32x2_t a"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_s64",
+    "name": "vraddhn_u32",
     "arguments": [
-      "int64x1_t a"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_s8",
+    "name": "vraddhn_u64",
     "arguments": [
-      "int8x8_t a"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RADDHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_u16",
+    "name": "vrax1q_u64",
     "arguments": [
-      "uint16x4_t a"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -79119,22 +282993,22 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RAX1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_u32",
+    "name": "vrbit_p8",
     "arguments": [
-      "uint32x2_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -79142,22 +283016,22 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RBIT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_u64",
+    "name": "vrbit_s8",
     "arguments": [
-      "uint64x1_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -79165,22 +283039,22 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RBIT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_f64_u8",
+    "name": "vrbit_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
@@ -79188,72 +283062,68 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RBIT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_f16",
+    "name": "vrbitq_p8",
     "arguments": [
-      "float16x4_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RBIT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_f32",
+    "name": "vrbitq_s8",
     "arguments": [
-      "float32x2_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "RBIT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_f64",
+    "name": "vrbitq_u8",
     "arguments": [
-      "float64x1_t a"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
@@ -79261,22 +283131,22 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "RBIT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_p64",
+    "name": "vrecpe_f16",
     "arguments": [
-      "poly64x1_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
@@ -79285,22 +283155,22 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_p8",
+    "name": "vrecpe_f32",
     "arguments": [
-      "poly8x8_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -79310,47 +283180,45 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_s16",
+    "name": "vrecpe_f64",
     "arguments": [
-      "int16x4_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_s32",
+    "name": "vrecpe_u32",
     "arguments": [
-      "int32x2_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -79360,97 +283228,92 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "URECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_s64",
+    "name": "vrecped_f64",
     "arguments": [
-      "int64x1_t a"
+      "float64_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_s8",
+    "name": "vrecpeh_f16",
     "arguments": [
-      "int8x8_t a"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_u16",
+    "name": "vrecpeq_f16",
     "arguments": [
-      "uint16x4_t a"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_u32",
+    "name": "vrecpeq_f32",
     "arguments": [
-      "uint32x2_t a"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -79460,47 +283323,45 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_u64",
+    "name": "vrecpeq_f64",
     "arguments": [
-      "uint64x1_t a"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p16_u8",
+    "name": "vrecpeq_u32",
     "arguments": [
-      "uint8x8_t a"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -79510,46 +283371,49 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "URECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_f16",
+    "name": "vrecpes_f32",
     "arguments": [
-      "float16x4_t a"
+      "float32_t a"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_f32",
+    "name": "vrecps_f16",
     "arguments": [
-      "float32x2_t a"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -79558,117 +283422,136 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_f64",
+    "name": "vrecps_f32",
     "arguments": [
-      "float64x1_t a"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_p16",
+    "name": "vrecps_f64",
     "arguments": [
-      "poly16x4_t a"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_p8",
+    "name": "vrecpsd_f64",
     "arguments": [
-      "poly8x8_t a"
+      "float64_t a",
+      "float64_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_s16",
+    "name": "vrecpsh_f16",
     "arguments": [
-      "int16x4_t a"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Hn"
+      },
+      "b": {
+        "register": "Hm"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_s32",
+    "name": "vrecpsq_f16",
     "arguments": [
-      "int32x2_t a"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -79677,163 +283560,170 @@
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_s8",
+    "name": "vrecpsq_f32",
     "arguments": [
-      "int8x8_t a"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_u16",
+    "name": "vrecpsq_f64",
     "arguments": [
-      "uint16x4_t a"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_u32",
+    "name": "vrecpss_f32",
     "arguments": [
-      "uint32x2_t a"
+      "float32_t a",
+      "float32_t b"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Sn"
+      },
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_u64",
+    "name": "vrecpxd_f64",
     "arguments": [
-      "uint64x1_t a"
+      "float64_t a"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p64_u8",
+    "name": "vrecpxh_f16",
     "arguments": [
-      "uint8x8_t a"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_f16",
+    "name": "vrecpxs_f32",
     "arguments": [
-      "float16x4_t a"
+      "float32_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "NOP"
+        "FRECPX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_f32",
+    "name": "vreinterpret_f16_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -79853,12 +283743,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_f64",
+    "name": "vreinterpret_f16_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -79876,12 +283766,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_p16",
+    "name": "vreinterpret_f16_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -79901,12 +283791,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_p64",
+    "name": "vreinterpret_f16_p64",
     "arguments": [
       "poly64x1_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -79925,16 +283815,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_s16",
+    "name": "vreinterpret_f16_p8",
     "arguments": [
-      "int16x4_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -79950,16 +283840,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_s32",
+    "name": "vreinterpret_f16_s16",
     "arguments": [
-      "int32x2_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -79975,16 +283865,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_s64",
+    "name": "vreinterpret_f16_s32",
     "arguments": [
-      "int64x1_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -80000,16 +283890,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_s8",
+    "name": "vreinterpret_f16_s64",
     "arguments": [
-      "int8x8_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -80025,16 +283915,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_u16",
+    "name": "vreinterpret_f16_s8",
     "arguments": [
-      "uint16x4_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -80050,16 +283940,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_u32",
+    "name": "vreinterpret_f16_u16",
     "arguments": [
-      "uint32x2_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -80075,16 +283965,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_u64",
+    "name": "vreinterpret_f16_u32",
     "arguments": [
-      "uint64x1_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -80100,16 +283990,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_p8_u8",
+    "name": "vreinterpret_f16_u64",
     "arguments": [
-      "uint8x8_t a"
+      "uint64x1_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -80125,16 +284015,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_f16",
+    "name": "vreinterpret_f16_u8",
     "arguments": [
-      "float16x4_t a"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -80150,16 +284040,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_f32",
+    "name": "vreinterpret_f32_f16",
     "arguments": [
-      "float32x2_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -80175,12 +284065,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_f64",
+    "name": "vreinterpret_f32_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80198,12 +284088,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_p16",
+    "name": "vreinterpret_f32_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80223,19 +284113,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_p64",
+    "name": "vreinterpret_f32_p8",
     "arguments": [
-      "poly64x1_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -80247,16 +284138,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_p8",
+    "name": "vreinterpret_f32_s16",
     "arguments": [
-      "poly8x8_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -80272,12 +284163,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_s32",
+    "name": "vreinterpret_f32_s32",
     "arguments": [
       "int32x2_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80297,12 +284188,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_s64",
+    "name": "vreinterpret_f32_s64",
     "arguments": [
       "int64x1_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80322,12 +284213,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_s8",
+    "name": "vreinterpret_f32_s8",
     "arguments": [
       "int8x8_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80347,12 +284238,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_u16",
+    "name": "vreinterpret_f32_u16",
     "arguments": [
       "uint16x4_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80372,12 +284263,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_u32",
+    "name": "vreinterpret_f32_u32",
     "arguments": [
       "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80397,12 +284288,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_u64",
+    "name": "vreinterpret_f32_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80422,12 +284313,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s16_u8",
+    "name": "vreinterpret_f32_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80447,12 +284338,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_f16",
+    "name": "vreinterpret_f64_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80460,8 +284351,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80472,12 +284361,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_f32",
+    "name": "vreinterpret_f64_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80485,8 +284374,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80497,16 +284384,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_f64",
+    "name": "vreinterpret_f64_p16",
     "arguments": [
-      "float64x1_t a"
+      "poly16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -80520,21 +284407,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_p16",
+    "name": "vreinterpret_f64_p64",
     "arguments": [
-      "poly16x4_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80545,20 +284430,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_p64",
+    "name": "vreinterpret_f64_p8",
     "arguments": [
-      "poly64x1_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80569,21 +284453,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_p8",
+    "name": "vreinterpret_f64_s16",
     "arguments": [
-      "poly8x8_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80594,21 +284476,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_s16",
+    "name": "vreinterpret_f64_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80619,12 +284499,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_s64",
+    "name": "vreinterpret_f64_s64",
     "arguments": [
       "int64x1_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80632,8 +284512,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80644,12 +284522,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_s8",
+    "name": "vreinterpret_f64_s8",
     "arguments": [
       "int8x8_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80657,8 +284535,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80669,12 +284545,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_u16",
+    "name": "vreinterpret_f64_u16",
     "arguments": [
       "uint16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80682,8 +284558,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80694,12 +284568,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_u32",
+    "name": "vreinterpret_f64_u32",
     "arguments": [
       "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80707,8 +284581,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80719,12 +284591,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_u64",
+    "name": "vreinterpret_f64_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80732,8 +284604,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80744,12 +284614,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s32_u8",
+    "name": "vreinterpret_f64_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80757,8 +284627,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -80769,12 +284637,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_f16",
+    "name": "vreinterpret_p16_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80794,12 +284662,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_f32",
+    "name": "vreinterpret_p16_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80819,12 +284687,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_f64",
+    "name": "vreinterpret_p16_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80842,20 +284710,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_p16",
+    "name": "vreinterpret_p16_p64",
     "arguments": [
-      "poly16x4_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -80867,19 +284734,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_p64",
+    "name": "vreinterpret_p16_p8",
     "arguments": [
-      "poly64x1_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -80891,16 +284759,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_p8",
+    "name": "vreinterpret_p16_s16",
     "arguments": [
-      "poly8x8_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -80916,16 +284784,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_s16",
+    "name": "vreinterpret_p16_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -80941,16 +284809,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_s32",
+    "name": "vreinterpret_p16_s64",
     "arguments": [
-      "int32x2_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -80966,12 +284834,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_s8",
+    "name": "vreinterpret_p16_s8",
     "arguments": [
       "int8x8_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -80991,12 +284859,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_u16",
+    "name": "vreinterpret_p16_u16",
     "arguments": [
       "uint16x4_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81016,12 +284884,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_u32",
+    "name": "vreinterpret_p16_u32",
     "arguments": [
       "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81041,12 +284909,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_u64",
+    "name": "vreinterpret_p16_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81066,12 +284934,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s64_u8",
+    "name": "vreinterpret_p16_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81091,12 +284959,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_f16",
+    "name": "vreinterpret_p64_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81104,7 +284972,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81116,12 +284983,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_f32",
+    "name": "vreinterpret_p64_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81129,7 +284996,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81141,12 +285007,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_f64",
+    "name": "vreinterpret_p64_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81164,43 +285030,18 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_p16",
+    "name": "vreinterpret_p64_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vd.4H"
       }
     },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_p64",
-    "arguments": [
-      "poly64x1_t a"
-    ],
-    "return_type": {
-      "value": "int8x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.1D"
-      }
-    },
     "Architectures": [
       "A32",
       "A64"
@@ -81213,12 +285054,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_p8",
+    "name": "vreinterpret_p64_p8",
     "arguments": [
       "poly8x8_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81226,7 +285067,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81238,12 +285078,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_s16",
+    "name": "vreinterpret_p64_s16",
     "arguments": [
       "int16x4_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81251,7 +285091,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81263,12 +285102,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_s32",
+    "name": "vreinterpret_p64_s32",
     "arguments": [
       "int32x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81276,7 +285115,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81288,20 +285126,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_s64",
+    "name": "vreinterpret_p64_s8",
     "arguments": [
-      "int64x1_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81313,12 +285150,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_u16",
+    "name": "vreinterpret_p64_u16",
     "arguments": [
       "uint16x4_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81326,7 +285163,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81338,12 +285174,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_u32",
+    "name": "vreinterpret_p64_u32",
     "arguments": [
       "uint32x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81351,7 +285187,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81363,12 +285198,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_u64",
+    "name": "vreinterpret_p64_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81376,7 +285211,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81388,12 +285222,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_s8_u8",
+    "name": "vreinterpret_p64_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81401,7 +285235,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -81413,12 +285246,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_f16",
+    "name": "vreinterpret_p8_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81438,12 +285271,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_f32",
+    "name": "vreinterpret_p8_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81463,12 +285296,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_f64",
+    "name": "vreinterpret_p8_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81486,12 +285319,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_p16",
+    "name": "vreinterpret_p8_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81511,12 +285344,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_p64",
+    "name": "vreinterpret_p8_p64",
     "arguments": [
       "poly64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81535,16 +285368,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_p8",
+    "name": "vreinterpret_p8_s16",
     "arguments": [
-      "poly8x8_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -81560,16 +285393,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_s16",
+    "name": "vreinterpret_p8_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -81585,16 +285418,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_s32",
+    "name": "vreinterpret_p8_s64",
     "arguments": [
-      "int32x2_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -81610,16 +285443,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_s64",
+    "name": "vreinterpret_p8_s8",
     "arguments": [
-      "int64x1_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -81635,16 +285468,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_s8",
+    "name": "vreinterpret_p8_u16",
     "arguments": [
-      "int8x8_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -81660,12 +285493,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_u32",
+    "name": "vreinterpret_p8_u32",
     "arguments": [
       "uint32x2_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81685,12 +285518,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_u64",
+    "name": "vreinterpret_p8_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81710,12 +285543,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u16_u8",
+    "name": "vreinterpret_p8_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81735,12 +285568,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_f16",
+    "name": "vreinterpret_s16_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81760,12 +285593,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_f32",
+    "name": "vreinterpret_s16_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81785,12 +285618,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_f64",
+    "name": "vreinterpret_s16_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81808,12 +285641,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_p16",
+    "name": "vreinterpret_s16_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81833,12 +285666,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_p64",
+    "name": "vreinterpret_s16_p64",
     "arguments": [
       "poly64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81857,12 +285690,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_p8",
+    "name": "vreinterpret_s16_p8",
     "arguments": [
       "poly8x8_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -81882,16 +285715,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_s16",
+    "name": "vreinterpret_s16_s32",
     "arguments": [
-      "int16x4_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -81907,16 +285740,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_s32",
+    "name": "vreinterpret_s16_s64",
     "arguments": [
-      "int32x2_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -81932,16 +285765,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_s64",
+    "name": "vreinterpret_s16_s8",
     "arguments": [
-      "int64x1_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -81957,16 +285790,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_s8",
+    "name": "vreinterpret_s16_u16",
     "arguments": [
-      "int8x8_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -81982,16 +285815,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_u16",
+    "name": "vreinterpret_s16_u32",
     "arguments": [
-      "uint16x4_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -82007,12 +285840,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_u64",
+    "name": "vreinterpret_s16_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82032,12 +285865,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u32_u8",
+    "name": "vreinterpret_s16_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82057,12 +285890,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_f16",
+    "name": "vreinterpret_s32_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82082,12 +285915,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_f32",
+    "name": "vreinterpret_s32_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82107,12 +285940,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_f64",
+    "name": "vreinterpret_s32_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82130,12 +285963,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_p16",
+    "name": "vreinterpret_s32_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82155,12 +285988,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_p64",
+    "name": "vreinterpret_s32_p64",
     "arguments": [
       "poly64x1_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82179,12 +286012,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_p8",
+    "name": "vreinterpret_s32_p8",
     "arguments": [
       "poly8x8_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82204,12 +286037,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_s16",
+    "name": "vreinterpret_s32_s16",
     "arguments": [
       "int16x4_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82229,16 +286062,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_s32",
+    "name": "vreinterpret_s32_s64",
     "arguments": [
-      "int32x2_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -82254,16 +286087,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_s64",
+    "name": "vreinterpret_s32_s8",
     "arguments": [
-      "int64x1_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -82279,16 +286112,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_s8",
+    "name": "vreinterpret_s32_u16",
     "arguments": [
-      "int8x8_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -82304,16 +286137,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_u16",
+    "name": "vreinterpret_s32_u32",
     "arguments": [
-      "uint16x4_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -82329,16 +286162,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_u32",
+    "name": "vreinterpret_s32_u64",
     "arguments": [
-      "uint32x2_t a"
+      "uint64x1_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -82354,12 +286187,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u64_u8",
+    "name": "vreinterpret_s32_u8",
     "arguments": [
       "uint8x8_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82379,12 +286212,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_f16",
+    "name": "vreinterpret_s64_f16",
     "arguments": [
       "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82404,12 +286237,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_f32",
+    "name": "vreinterpret_s64_f32",
     "arguments": [
       "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82429,12 +286262,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_f64",
+    "name": "vreinterpret_s64_f64",
     "arguments": [
       "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82452,12 +286285,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_p16",
+    "name": "vreinterpret_s64_p16",
     "arguments": [
       "poly16x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82477,12 +286310,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_p64",
+    "name": "vreinterpret_s64_p64",
     "arguments": [
       "poly64x1_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82501,12 +286334,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_p8",
+    "name": "vreinterpret_s64_p8",
     "arguments": [
       "poly8x8_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82526,12 +286359,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_s16",
+    "name": "vreinterpret_s64_s16",
     "arguments": [
       "int16x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82551,12 +286384,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_s32",
+    "name": "vreinterpret_s64_s32",
     "arguments": [
       "int32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82576,37 +286409,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_s64",
-    "arguments": [
-      "int64x1_t a"
-    ],
-    "return_type": {
-      "value": "uint8x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.1D"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_s8",
+    "name": "vreinterpret_s64_s8",
     "arguments": [
       "int8x8_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82626,12 +286434,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_u16",
+    "name": "vreinterpret_s64_u16",
     "arguments": [
       "uint16x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82651,12 +286459,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_u32",
+    "name": "vreinterpret_s64_u32",
     "arguments": [
       "uint32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82676,12 +286484,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpret_u8_u64",
+    "name": "vreinterpret_s64_u64",
     "arguments": [
       "uint64x1_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -82701,16 +286509,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_f32",
+    "name": "vreinterpret_s64_u8",
     "arguments": [
-      "float32x4_t a"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -82726,42 +286534,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_f64",
-    "arguments": [
-      "float64x2_t a"
-    ],
-    "return_type": {
-      "value": "float16x8_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_p128",
+    "name": "vreinterpret_s8_f16",
     "arguments": [
-      "poly128_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -82773,16 +286559,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_p16",
+    "name": "vreinterpret_s8_f32",
     "arguments": [
-      "poly16x8_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -82798,20 +286584,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_p64",
+    "name": "vreinterpret_s8_f64",
     "arguments": [
-      "poly64x2_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -82822,16 +286607,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_p8",
+    "name": "vreinterpret_s8_p16",
     "arguments": [
-      "poly8x16_t a"
+      "poly16x4_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -82847,20 +286632,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_s16",
+    "name": "vreinterpret_s8_p64",
     "arguments": [
-      "int16x8_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -82872,16 +286656,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_s32",
+    "name": "vreinterpret_s8_p8",
     "arguments": [
-      "int32x4_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -82897,16 +286681,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_s64",
+    "name": "vreinterpret_s8_s16",
     "arguments": [
-      "int64x2_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -82922,16 +286706,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_s8",
+    "name": "vreinterpret_s8_s32",
     "arguments": [
-      "int8x16_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -82947,16 +286731,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_u16",
+    "name": "vreinterpret_s8_s64",
     "arguments": [
-      "uint16x8_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -82972,16 +286756,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_u32",
+    "name": "vreinterpret_s8_u16",
     "arguments": [
-      "uint32x4_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -82997,16 +286781,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_u64",
+    "name": "vreinterpret_s8_u32",
     "arguments": [
-      "uint64x2_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -83022,16 +286806,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f16_u8",
+    "name": "vreinterpret_s8_u64",
     "arguments": [
-      "uint8x16_t a"
+      "uint64x1_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -83047,16 +286831,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_f16",
+    "name": "vreinterpret_s8_u8",
     "arguments": [
-      "float16x8_t a"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -83072,39 +286856,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_f64",
-    "arguments": [
-      "float64x2_t a"
-    ],
-    "return_type": {
-      "value": "float32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_p16",
+    "name": "vreinterpret_u16_f16",
     "arguments": [
-      "poly16x8_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -83120,16 +286881,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_p8",
+    "name": "vreinterpret_u16_f32",
     "arguments": [
-      "poly8x16_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -83145,21 +286906,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_s16",
+    "name": "vreinterpret_u16_f64",
     "arguments": [
-      "int16x8_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -83170,16 +286929,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_s32",
+    "name": "vreinterpret_u16_p16",
     "arguments": [
-      "int32x4_t a"
+      "poly16x4_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -83195,20 +286954,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_s64",
+    "name": "vreinterpret_u16_p64",
     "arguments": [
-      "int64x2_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -83220,16 +286978,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_s8",
+    "name": "vreinterpret_u16_p8",
     "arguments": [
-      "int8x16_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -83245,16 +287003,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_u16",
+    "name": "vreinterpret_u16_s16",
     "arguments": [
-      "uint16x8_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -83270,16 +287028,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_u32",
+    "name": "vreinterpret_u16_s32",
     "arguments": [
-      "uint32x4_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -83295,16 +287053,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_u64",
+    "name": "vreinterpret_u16_s64",
     "arguments": [
-      "uint64x2_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -83320,16 +287078,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f32_u8",
+    "name": "vreinterpret_u16_s8",
     "arguments": [
-      "uint8x16_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -83345,19 +287103,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_f16",
+    "name": "vreinterpret_u16_u32",
     "arguments": [
-      "float16x8_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83368,19 +287128,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_f32",
+    "name": "vreinterpret_u16_u64",
     "arguments": [
-      "float32x4_t a"
+      "uint64x1_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83391,19 +287153,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_p128",
+    "name": "vreinterpret_u16_u8",
     "arguments": [
-      "poly128_t a"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83414,19 +287178,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_p16",
+    "name": "vreinterpret_u32_f16",
     "arguments": [
-      "poly16x8_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83437,19 +287203,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_p64",
+    "name": "vreinterpret_u32_f32",
     "arguments": [
-      "poly64x2_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83460,16 +287228,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_p8",
+    "name": "vreinterpret_u32_f64",
     "arguments": [
-      "poly8x16_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -83483,19 +287251,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_s16",
+    "name": "vreinterpret_u32_p16",
     "arguments": [
-      "int16x8_t a"
+      "poly16x4_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83506,19 +287276,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_s32",
+    "name": "vreinterpret_u32_p64",
     "arguments": [
-      "int32x4_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83529,19 +287300,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_s64",
+    "name": "vreinterpret_u32_p8",
     "arguments": [
-      "int64x2_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83552,19 +287325,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_s8",
+    "name": "vreinterpret_u32_s16",
     "arguments": [
-      "int8x16_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83575,19 +287350,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_u16",
+    "name": "vreinterpret_u32_s32",
     "arguments": [
-      "uint16x8_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83598,19 +287375,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_u32",
+    "name": "vreinterpret_u32_s64",
     "arguments": [
-      "uint32x4_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83621,16 +287400,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_u64",
+    "name": "vreinterpret_u32_s8",
     "arguments": [
-      "uint64x2_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -83646,19 +287425,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_f64_u8",
+    "name": "vreinterpret_u32_u16",
     "arguments": [
-      "uint8x16_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83669,19 +287450,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_f16",
+    "name": "vreinterpret_u32_u64",
     "arguments": [
-      "float16x8_t a"
+      "uint64x1_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83693,19 +287475,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_f32",
+    "name": "vreinterpret_u32_u8",
     "arguments": [
-      "float32x4_t a"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83717,19 +287500,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_f64",
+    "name": "vreinterpret_u64_f16",
     "arguments": [
-      "float64x2_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -83740,19 +287525,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_p16",
+    "name": "vreinterpret_u64_f32",
     "arguments": [
-      "poly16x8_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83764,20 +287550,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_p8",
+    "name": "vreinterpret_u64_f64",
     "arguments": [
-      "poly8x16_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -83788,19 +287573,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_s16",
+    "name": "vreinterpret_u64_p16",
     "arguments": [
-      "int16x8_t a"
+      "poly16x4_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83812,16 +287598,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_s32",
+    "name": "vreinterpret_u64_p64",
     "arguments": [
-      "int32x4_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -83836,19 +287622,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_s64",
+    "name": "vreinterpret_u64_p8",
     "arguments": [
-      "int64x2_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83860,19 +287647,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_s8",
+    "name": "vreinterpret_u64_s16",
     "arguments": [
-      "int8x16_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83884,19 +287672,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_u16",
+    "name": "vreinterpret_u64_s32",
     "arguments": [
-      "uint16x8_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83908,19 +287697,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_u32",
+    "name": "vreinterpret_u64_s64",
     "arguments": [
-      "uint32x4_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83932,19 +287722,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_u64",
+    "name": "vreinterpret_u64_s8",
     "arguments": [
-      "uint64x2_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83956,19 +287747,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p128_u8",
+    "name": "vreinterpret_u64_u16",
     "arguments": [
-      "uint8x16_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "poly128_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -83980,16 +287772,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_f16",
+    "name": "vreinterpret_u64_u32",
     "arguments": [
-      "float16x8_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -84005,16 +287797,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_f32",
+    "name": "vreinterpret_u64_u8",
     "arguments": [
-      "float32x4_t a"
+      "uint8x8_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -84030,19 +287822,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_f64",
+    "name": "vreinterpret_u8_f16",
     "arguments": [
-      "float64x2_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -84053,19 +287847,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_p128",
+    "name": "vreinterpret_u8_f32",
     "arguments": [
-      "poly128_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84077,20 +287872,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_p64",
+    "name": "vreinterpret_u8_f64",
     "arguments": [
-      "poly64x2_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -84101,16 +287895,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_p8",
+    "name": "vreinterpret_u8_p16",
     "arguments": [
-      "poly8x16_t a"
+      "poly16x4_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -84126,20 +287920,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_s16",
+    "name": "vreinterpret_u8_p64",
     "arguments": [
-      "int16x8_t a"
+      "poly64x1_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -84151,16 +287944,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_s32",
+    "name": "vreinterpret_u8_p8",
     "arguments": [
-      "int32x4_t a"
+      "poly8x8_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -84176,16 +287969,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_s64",
+    "name": "vreinterpret_u8_s16",
     "arguments": [
-      "int64x2_t a"
+      "int16x4_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -84201,16 +287994,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_s8",
+    "name": "vreinterpret_u8_s32",
     "arguments": [
-      "int8x16_t a"
+      "int32x2_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -84226,16 +288019,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_u16",
+    "name": "vreinterpret_u8_s64",
     "arguments": [
-      "uint16x8_t a"
+      "int64x1_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -84251,16 +288044,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_u32",
+    "name": "vreinterpret_u8_s8",
     "arguments": [
-      "uint32x4_t a"
+      "int8x8_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -84276,16 +288069,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_u64",
+    "name": "vreinterpret_u8_u16",
     "arguments": [
-      "uint64x2_t a"
+      "uint16x4_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -84301,16 +288094,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p16_u8",
+    "name": "vreinterpret_u8_u32",
     "arguments": [
-      "uint8x16_t a"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -84326,19 +288119,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_f16",
+    "name": "vreinterpret_u8_u64",
     "arguments": [
-      "float16x8_t a"
+      "uint64x1_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84350,12 +288144,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_f32",
+    "name": "vreinterpretq_f16_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84363,6 +288157,7 @@
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84374,12 +288169,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_f64",
+    "name": "vreinterpretq_f16_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84397,16 +288192,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_p16",
+    "name": "vreinterpretq_f16_p128",
     "arguments": [
-      "poly16x8_t a"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
@@ -84421,19 +288216,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_p8",
+    "name": "vreinterpretq_f16_p16",
     "arguments": [
-      "poly8x16_t a"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84445,16 +288241,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_s16",
+    "name": "vreinterpretq_f16_p64",
     "arguments": [
-      "int16x8_t a"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -84469,19 +288265,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_s32",
+    "name": "vreinterpretq_f16_p8",
     "arguments": [
-      "int32x4_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84493,19 +288290,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_s64",
+    "name": "vreinterpretq_f16_s16",
     "arguments": [
-      "int64x2_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84517,19 +288315,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_s8",
+    "name": "vreinterpretq_f16_s32",
     "arguments": [
-      "int8x16_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84541,19 +288340,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_u16",
+    "name": "vreinterpretq_f16_s64",
     "arguments": [
-      "uint16x8_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84565,19 +288365,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_u32",
+    "name": "vreinterpretq_f16_s8",
     "arguments": [
-      "uint32x4_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84589,19 +288390,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_u64",
+    "name": "vreinterpretq_f16_u16",
     "arguments": [
-      "uint64x2_t a"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84613,19 +288415,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p64_u8",
+    "name": "vreinterpretq_f16_u32",
     "arguments": [
-      "uint8x16_t a"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84637,16 +288440,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_f16",
+    "name": "vreinterpretq_f16_u64",
     "arguments": [
-      "float16x8_t a"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -84662,16 +288465,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_f32",
+    "name": "vreinterpretq_f16_u8",
     "arguments": [
-      "float32x4_t a"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -84687,19 +288490,21 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_f64",
+    "name": "vreinterpretq_f32_f16",
     "arguments": [
-      "float64x2_t a"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -84710,20 +288515,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_p128",
+    "name": "vreinterpretq_f32_f64",
     "arguments": [
-      "poly128_t a"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -84734,12 +288538,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_p16",
+    "name": "vreinterpretq_f32_p16",
     "arguments": [
       "poly16x8_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84759,19 +288563,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_p64",
+    "name": "vreinterpretq_f32_p8",
     "arguments": [
-      "poly64x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -84783,12 +288588,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_s16",
+    "name": "vreinterpretq_f32_s16",
     "arguments": [
       "int16x8_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84808,12 +288613,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_s32",
+    "name": "vreinterpretq_f32_s32",
     "arguments": [
       "int32x4_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84833,12 +288638,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_s64",
+    "name": "vreinterpretq_f32_s64",
     "arguments": [
       "int64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84858,12 +288663,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_s8",
+    "name": "vreinterpretq_f32_s8",
     "arguments": [
       "int8x16_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84883,12 +288688,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_u16",
+    "name": "vreinterpretq_f32_u16",
     "arguments": [
       "uint16x8_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84908,12 +288713,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_u32",
+    "name": "vreinterpretq_f32_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84933,12 +288738,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_u64",
+    "name": "vreinterpretq_f32_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84958,12 +288763,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_p8_u8",
+    "name": "vreinterpretq_f32_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84983,12 +288788,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_f16",
+    "name": "vreinterpretq_f64_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -84996,8 +288801,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85008,12 +288811,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_f32",
+    "name": "vreinterpretq_f64_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85021,8 +288824,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85033,16 +288834,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_f64",
+    "name": "vreinterpretq_f64_p128",
     "arguments": [
-      "float64x2_t a"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
@@ -85056,20 +288857,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_p128",
+    "name": "vreinterpretq_f64_p16",
     "arguments": [
-      "poly128_t a"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.1Q"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85080,21 +288880,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_p16",
+    "name": "vreinterpretq_f64_p64",
     "arguments": [
-      "poly16x8_t a"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85105,20 +288903,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_p64",
+    "name": "vreinterpretq_f64_p8",
     "arguments": [
-      "poly64x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85129,21 +288926,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_p8",
+    "name": "vreinterpretq_f64_s16",
     "arguments": [
-      "poly8x16_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85154,12 +288949,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_s32",
+    "name": "vreinterpretq_f64_s32",
     "arguments": [
       "int32x4_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85167,8 +288962,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85179,12 +288972,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_s64",
+    "name": "vreinterpretq_f64_s64",
     "arguments": [
       "int64x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85192,8 +288985,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85204,12 +288995,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_s8",
+    "name": "vreinterpretq_f64_s8",
     "arguments": [
       "int8x16_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85217,8 +289008,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85229,12 +289018,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_u16",
+    "name": "vreinterpretq_f64_u16",
     "arguments": [
       "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85242,8 +289031,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85254,12 +289041,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_u32",
+    "name": "vreinterpretq_f64_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85267,8 +289054,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85279,12 +289064,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_u64",
+    "name": "vreinterpretq_f64_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85304,12 +289089,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s16_u8",
+    "name": "vreinterpretq_f64_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85317,8 +289102,6 @@
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85329,12 +289112,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_f16",
+    "name": "vreinterpretq_p128_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85342,7 +289125,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85354,12 +289136,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_f32",
+    "name": "vreinterpretq_p128_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85367,7 +289149,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85379,35 +289160,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_f64",
+    "name": "vreinterpretq_p128_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_p128",
-    "arguments": [
-      "poly128_t a"
-    ],
-    "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85415,7 +289173,6 @@
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -85426,12 +289183,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_p16",
+    "name": "vreinterpretq_p128_p16",
     "arguments": [
       "poly16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85439,7 +289196,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85451,16 +289207,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_p64",
+    "name": "vreinterpretq_p128_p8",
     "arguments": [
-      "poly64x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -85475,20 +289231,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_p8",
+    "name": "vreinterpretq_p128_s16",
     "arguments": [
-      "poly8x16_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85500,20 +289255,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_s16",
+    "name": "vreinterpretq_p128_s32",
     "arguments": [
-      "int16x8_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85525,20 +289279,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_s64",
+    "name": "vreinterpretq_p128_s64",
     "arguments": [
       "int64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85550,12 +289303,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_s8",
+    "name": "vreinterpretq_p128_s8",
     "arguments": [
       "int8x16_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85563,7 +289316,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85575,12 +289327,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_u16",
+    "name": "vreinterpretq_p128_u16",
     "arguments": [
       "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85588,7 +289340,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85600,12 +289351,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_u32",
+    "name": "vreinterpretq_p128_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85613,7 +289364,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85625,20 +289375,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_u64",
+    "name": "vreinterpretq_p128_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85650,12 +289399,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s32_u8",
+    "name": "vreinterpretq_p128_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "poly128_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85663,7 +289412,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85675,12 +289423,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_f16",
+    "name": "vreinterpretq_p16_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85700,12 +289448,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_f32",
+    "name": "vreinterpretq_p16_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85725,12 +289473,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_f64",
+    "name": "vreinterpretq_p16_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85748,12 +289496,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_p128",
+    "name": "vreinterpretq_p16_p128",
     "arguments": [
       "poly128_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85772,20 +289520,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_p16",
+    "name": "vreinterpretq_p16_p64",
     "arguments": [
-      "poly16x8_t a"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -85797,19 +289544,20 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_p64",
+    "name": "vreinterpretq_p16_p8",
     "arguments": [
-      "poly64x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -85821,16 +289569,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_p8",
+    "name": "vreinterpretq_p16_s16",
     "arguments": [
-      "poly8x16_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -85846,16 +289594,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_s16",
+    "name": "vreinterpretq_p16_s32",
     "arguments": [
-      "int16x8_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -85871,16 +289619,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_s32",
+    "name": "vreinterpretq_p16_s64",
     "arguments": [
-      "int32x4_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -85896,12 +289644,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_s8",
+    "name": "vreinterpretq_p16_s8",
     "arguments": [
       "int8x16_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85921,12 +289669,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_u16",
+    "name": "vreinterpretq_p16_u16",
     "arguments": [
       "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85946,12 +289694,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_u32",
+    "name": "vreinterpretq_p16_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85971,12 +289719,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_u64",
+    "name": "vreinterpretq_p16_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -85996,12 +289744,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s64_u8",
+    "name": "vreinterpretq_p16_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86021,12 +289769,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_f16",
+    "name": "vreinterpretq_p64_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86034,7 +289782,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86046,12 +289793,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_f32",
+    "name": "vreinterpretq_p64_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86059,7 +289806,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86071,12 +289817,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_f64",
+    "name": "vreinterpretq_p64_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86094,36 +289840,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_p128",
-    "arguments": [
-      "poly128_t a"
-    ],
-    "return_type": {
-      "value": "int8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.1Q"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_p16",
+    "name": "vreinterpretq_p64_p16",
     "arguments": [
       "poly16x8_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86131,7 +289853,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86143,16 +289864,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_p64",
+    "name": "vreinterpretq_p64_p8",
     "arguments": [
-      "poly64x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -86167,20 +289888,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_p8",
+    "name": "vreinterpretq_p64_s16",
     "arguments": [
-      "poly8x16_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86192,20 +289912,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_s16",
+    "name": "vreinterpretq_p64_s32",
     "arguments": [
-      "int16x8_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86217,20 +289936,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_s32",
+    "name": "vreinterpretq_p64_s64",
     "arguments": [
-      "int32x4_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86242,20 +289960,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_s64",
+    "name": "vreinterpretq_p64_s8",
     "arguments": [
-      "int64x2_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86267,12 +289984,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_u16",
+    "name": "vreinterpretq_p64_u16",
     "arguments": [
       "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86280,7 +289997,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86292,12 +290008,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_u32",
+    "name": "vreinterpretq_p64_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86305,7 +290021,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86317,12 +290032,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_u64",
+    "name": "vreinterpretq_p64_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86330,7 +290045,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86342,12 +290056,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_s8_u8",
+    "name": "vreinterpretq_p64_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86355,7 +290069,6 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -86367,12 +290080,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_f16",
+    "name": "vreinterpretq_p8_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86392,12 +290105,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_f32",
+    "name": "vreinterpretq_p8_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86417,12 +290130,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_f64",
+    "name": "vreinterpretq_p8_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86440,12 +290153,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_p128",
+    "name": "vreinterpretq_p8_p128",
     "arguments": [
       "poly128_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86464,12 +290177,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_p16",
+    "name": "vreinterpretq_p8_p16",
     "arguments": [
       "poly16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86489,12 +290202,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_p64",
+    "name": "vreinterpretq_p8_p64",
     "arguments": [
       "poly64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86513,16 +290226,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_p8",
+    "name": "vreinterpretq_p8_s16",
     "arguments": [
-      "poly8x16_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -86538,16 +290251,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_s16",
+    "name": "vreinterpretq_p8_s32",
     "arguments": [
-      "int16x8_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -86563,16 +290276,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_s32",
+    "name": "vreinterpretq_p8_s64",
     "arguments": [
-      "int32x4_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -86588,16 +290301,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_s64",
+    "name": "vreinterpretq_p8_s8",
     "arguments": [
-      "int64x2_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -86613,16 +290326,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_s8",
+    "name": "vreinterpretq_p8_u16",
     "arguments": [
-      "int8x16_t a"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -86638,12 +290351,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_u32",
+    "name": "vreinterpretq_p8_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86663,12 +290376,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_u64",
+    "name": "vreinterpretq_p8_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86688,12 +290401,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u16_u8",
+    "name": "vreinterpretq_p8_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86713,12 +290426,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_f16",
+    "name": "vreinterpretq_s16_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86738,12 +290451,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_f32",
+    "name": "vreinterpretq_s16_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86763,12 +290476,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_f64",
+    "name": "vreinterpretq_s16_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86786,12 +290499,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_p128",
+    "name": "vreinterpretq_s16_p128",
     "arguments": [
       "poly128_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86810,12 +290523,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_p16",
+    "name": "vreinterpretq_s16_p16",
     "arguments": [
       "poly16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86835,12 +290548,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_p64",
+    "name": "vreinterpretq_s16_p64",
     "arguments": [
       "poly64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86859,12 +290572,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_p8",
+    "name": "vreinterpretq_s16_p8",
     "arguments": [
       "poly8x16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -86884,16 +290597,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_s16",
+    "name": "vreinterpretq_s16_s32",
     "arguments": [
-      "int16x8_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -86909,16 +290622,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_s32",
+    "name": "vreinterpretq_s16_s64",
     "arguments": [
-      "int32x4_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -86934,16 +290647,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_s64",
+    "name": "vreinterpretq_s16_s8",
     "arguments": [
-      "int64x2_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -86959,16 +290672,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_s8",
+    "name": "vreinterpretq_s16_u16",
     "arguments": [
-      "int8x16_t a"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -86984,16 +290697,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_u16",
+    "name": "vreinterpretq_s16_u32",
     "arguments": [
-      "uint16x8_t a"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -87009,12 +290722,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_u64",
+    "name": "vreinterpretq_s16_u64",
     "arguments": [
       "uint64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87034,12 +290747,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u32_u8",
+    "name": "vreinterpretq_s16_u8",
     "arguments": [
       "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87059,12 +290772,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_f16",
+    "name": "vreinterpretq_s32_f16",
     "arguments": [
       "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87084,12 +290797,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_f32",
+    "name": "vreinterpretq_s32_f32",
     "arguments": [
       "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87109,12 +290822,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_f64",
+    "name": "vreinterpretq_s32_f64",
     "arguments": [
       "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87132,12 +290845,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_p128",
+    "name": "vreinterpretq_s32_p128",
     "arguments": [
       "poly128_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87156,12 +290869,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_p16",
+    "name": "vreinterpretq_s32_p16",
     "arguments": [
       "poly16x8_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87181,12 +290894,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_p64",
+    "name": "vreinterpretq_s32_p64",
     "arguments": [
       "poly64x2_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87205,12 +290918,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_p8",
+    "name": "vreinterpretq_s32_p8",
     "arguments": [
       "poly8x16_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87230,12 +290943,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_s16",
+    "name": "vreinterpretq_s32_s16",
     "arguments": [
       "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87255,37 +290968,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_s32",
-    "arguments": [
-      "int32x4_t a"
-    ],
-    "return_type": {
-      "value": "uint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_s64",
+    "name": "vreinterpretq_s32_s64",
     "arguments": [
       "int64x2_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87305,12 +290993,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_s8",
+    "name": "vreinterpretq_s32_s8",
     "arguments": [
       "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87330,12 +291018,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_u16",
+    "name": "vreinterpretq_s32_u16",
     "arguments": [
       "uint16x8_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87355,12 +291043,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_u32",
+    "name": "vreinterpretq_s32_u32",
     "arguments": [
       "uint32x4_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87380,41 +291068,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u64_u8",
-    "arguments": [
-      "uint8x16_t a"
-    ],
-    "return_type": {
-      "value": "uint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.16B"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_f16",
+    "name": "vreinterpretq_s32_u64",
     "arguments": [
-      "float16x8_t a"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -87430,16 +291093,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_f32",
+    "name": "vreinterpretq_s32_u8",
     "arguments": [
-      "float32x4_t a"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -87455,59 +291118,12 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_f64",
-    "arguments": [
-      "float64x2_t a"
-    ],
-    "return_type": {
-      "value": "uint8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_p128",
-    "arguments": [
-      "poly128_t a"
-    ],
-    "return_type": {
-      "value": "uint8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.1Q"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_p16",
+    "name": "vreinterpretq_s64_f16",
     "arguments": [
-      "poly16x8_t a"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -87527,40 +291143,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_p64",
-    "arguments": [
-      "poly64x2_t a"
-    ],
-    "return_type": {
-      "value": "uint8x16_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.2D"
-      }
-    },
-    "Architectures": [
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "NOP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_p8",
+    "name": "vreinterpretq_s64_f32",
     "arguments": [
-      "poly8x16_t a"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -87576,21 +291168,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_s16",
+    "name": "vreinterpretq_s64_f64",
     "arguments": [
-      "int16x8_t a"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2D"
       }
     },
-    "Architectures": [
-      "v7",
-      "A32",
+    "Architectures": [
       "A64"
     ],
     "instructions": [
@@ -87601,20 +291191,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_s32",
+    "name": "vreinterpretq_s64_p128",
     "arguments": [
-      "int32x4_t a"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -87626,16 +291215,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_s64",
+    "name": "vreinterpretq_s64_p16",
     "arguments": [
-      "int64x2_t a"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -87651,20 +291240,19 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_s8",
+    "name": "vreinterpretq_s64_p64",
     "arguments": [
-      "int8x16_t a"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -87676,16 +291264,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_u16",
+    "name": "vreinterpretq_s64_p8",
     "arguments": [
-      "uint16x8_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -87701,16 +291289,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_u32",
+    "name": "vreinterpretq_s64_s16",
     "arguments": [
-      "uint32x4_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -87726,16 +291314,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vreinterpretq_u8_u64",
+    "name": "vreinterpretq_s64_s32",
     "arguments": [
-      "uint64x2_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -87751,16 +291339,16 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev16_p8",
+    "name": "vreinterpretq_s64_s8",
     "arguments": [
-      "poly8x8_t vec"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -87770,22 +291358,22 @@
     ],
     "instructions": [
       [
-        "REV16"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev16_s8",
+    "name": "vreinterpretq_s64_u16",
     "arguments": [
-      "int8x8_t vec"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -87795,22 +291383,22 @@
     ],
     "instructions": [
       [
-        "REV16"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev16_u8",
+    "name": "vreinterpretq_s64_u32",
     "arguments": [
-      "uint8x8_t vec"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -87820,22 +291408,22 @@
     ],
     "instructions": [
       [
-        "REV16"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev16q_p8",
+    "name": "vreinterpretq_s64_u64",
     "arguments": [
-      "poly8x16_t vec"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -87845,22 +291433,22 @@
     ],
     "instructions": [
       [
-        "REV16"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev16q_s8",
+    "name": "vreinterpretq_s64_u8",
     "arguments": [
-      "int8x16_t vec"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -87870,22 +291458,22 @@
     ],
     "instructions": [
       [
-        "REV16"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev16q_u8",
+    "name": "vreinterpretq_s8_f16",
     "arguments": [
-      "uint8x16_t vec"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -87895,22 +291483,22 @@
     ],
     "instructions": [
       [
-        "REV16"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32_p16",
+    "name": "vreinterpretq_s8_f32",
     "arguments": [
-      "poly16x4_t vec"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -87920,72 +291508,69 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32_p8",
+    "name": "vreinterpretq_s8_f64",
     "arguments": [
-      "poly8x8_t vec"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32_s16",
+    "name": "vreinterpretq_s8_p128",
     "arguments": [
-      "int16x4_t vec"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32_s8",
+    "name": "vreinterpretq_s8_p16",
     "arguments": [
-      "int8x8_t vec"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -87995,47 +291580,46 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32_u16",
+    "name": "vreinterpretq_s8_p64",
     "arguments": [
-      "uint16x4_t vec"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32_u8",
+    "name": "vreinterpretq_s8_p8",
     "arguments": [
-      "uint8x8_t vec"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88045,22 +291629,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32q_p16",
+    "name": "vreinterpretq_s8_s16",
     "arguments": [
-      "poly16x8_t vec"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88070,22 +291654,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32q_p8",
+    "name": "vreinterpretq_s8_s32",
     "arguments": [
-      "poly8x16_t vec"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88095,22 +291679,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32q_s16",
+    "name": "vreinterpretq_s8_s64",
     "arguments": [
-      "int16x8_t vec"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -88120,22 +291704,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32q_s8",
+    "name": "vreinterpretq_s8_u16",
     "arguments": [
-      "int8x16_t vec"
+      "uint16x8_t a"
     ],
     "return_type": {
       "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88145,22 +291729,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32q_u16",
+    "name": "vreinterpretq_s8_u32",
     "arguments": [
-      "uint16x8_t vec"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88170,22 +291754,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev32q_u8",
+    "name": "vreinterpretq_s8_u64",
     "arguments": [
-      "uint8x16_t vec"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -88195,22 +291779,22 @@
     ],
     "instructions": [
       [
-        "REV32"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_f16",
+    "name": "vreinterpretq_s8_u8",
     "arguments": [
-      "float16x4_t vec"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88220,22 +291804,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_f32",
+    "name": "vreinterpretq_u16_f16",
     "arguments": [
-      "float32x2_t vec"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.2S"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88245,22 +291829,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_p16",
+    "name": "vreinterpretq_u16_f32",
     "arguments": [
-      "poly16x4_t vec"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88270,72 +291854,69 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_p8",
+    "name": "vreinterpretq_u16_f64",
     "arguments": [
-      "poly8x8_t vec"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_s16",
+    "name": "vreinterpretq_u16_p128",
     "arguments": [
-      "int16x4_t vec"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_s32",
+    "name": "vreinterpretq_u16_p16",
     "arguments": [
-      "int32x2_t vec"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.2S"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88345,47 +291926,46 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_s8",
+    "name": "vreinterpretq_u16_p64",
     "arguments": [
-      "int8x8_t vec"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_u16",
+    "name": "vreinterpretq_u16_p8",
     "arguments": [
-      "uint16x4_t vec"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4H"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88395,22 +291975,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_u32",
+    "name": "vreinterpretq_u16_s16",
     "arguments": [
-      "uint32x2_t vec"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.2S"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88420,22 +292000,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64_u8",
+    "name": "vreinterpretq_u16_s32",
     "arguments": [
-      "uint8x8_t vec"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8B"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88445,22 +292025,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_f16",
+    "name": "vreinterpretq_u16_s64",
     "arguments": [
-      "float16x8_t vec"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -88470,22 +292050,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_f32",
+    "name": "vreinterpretq_u16_s8",
     "arguments": [
-      "float32x4_t vec"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4S"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88495,22 +292075,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_p16",
+    "name": "vreinterpretq_u16_u32",
     "arguments": [
-      "poly16x8_t vec"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88520,22 +292100,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_p8",
+    "name": "vreinterpretq_u16_u64",
     "arguments": [
-      "poly8x16_t vec"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -88545,22 +292125,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_s16",
+    "name": "vreinterpretq_u16_u8",
     "arguments": [
-      "int16x8_t vec"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88570,22 +292150,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_s32",
+    "name": "vreinterpretq_u32_f16",
     "arguments": [
-      "int32x4_t vec"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4S"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88595,22 +292175,22 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_s8",
+    "name": "vreinterpretq_u32_f32",
     "arguments": [
-      "int8x16_t vec"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88620,72 +292200,69 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_u16",
+    "name": "vreinterpretq_u32_f64",
     "arguments": [
-      "uint16x8_t vec"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.8H"
+      "a": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_u32",
+    "name": "vreinterpretq_u32_p128",
     "arguments": [
-      "uint32x4_t vec"
+      "poly128_t a"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.4S"
+      "a": {
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrev64q_u8",
+    "name": "vreinterpretq_u32_p16",
     "arguments": [
-      "uint8x16_t vec"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "vec": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88695,55 +292272,46 @@
     ],
     "instructions": [
       [
-        "REV64"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhadd_s16",
+    "name": "vreinterpretq_u32_p64",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhadd_s32",
+    "name": "vreinterpretq_u32_p8",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88753,26 +292321,22 @@
     ],
     "instructions": [
       [
-        "SRHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhadd_s8",
+    "name": "vreinterpretq_u32_s16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88782,26 +292346,22 @@
     ],
     "instructions": [
       [
-        "SRHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhadd_u16",
+    "name": "vreinterpretq_u32_s32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -88811,26 +292371,22 @@
     ],
     "instructions": [
       [
-        "URHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhadd_u32",
+    "name": "vreinterpretq_u32_s64",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -88840,26 +292396,22 @@
     ],
     "instructions": [
       [
-        "URHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhadd_u8",
+    "name": "vreinterpretq_u32_s8",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.8B"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88869,26 +292421,22 @@
     ],
     "instructions": [
       [
-        "URHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhaddq_s16",
+    "name": "vreinterpretq_u32_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88898,26 +292446,22 @@
     ],
     "instructions": [
       [
-        "SRHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhaddq_s32",
+    "name": "vreinterpretq_u32_u64",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -88927,26 +292471,22 @@
     ],
     "instructions": [
       [
-        "SRHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhaddq_s8",
+    "name": "vreinterpretq_u32_u8",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -88956,26 +292496,22 @@
     ],
     "instructions": [
       [
-        "SRHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhaddq_u16",
+    "name": "vreinterpretq_u64_f16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -88985,26 +292521,22 @@
     ],
     "instructions": [
       [
-        "URHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhaddq_u32",
+    "name": "vreinterpretq_u64_f32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -89014,350 +292546,368 @@
     ],
     "instructions": [
       [
-        "URHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrhaddq_u8",
+    "name": "vreinterpretq_u64_f64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URHADD"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32x_f32",
+    "name": "vreinterpretq_u64_p128",
     "arguments": [
-      "float32x2_t a"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32x_f64",
+    "name": "vreinterpretq_u64_p16",
     "arguments": [
-      "float64x1_t a"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32xq_f32",
+    "name": "vreinterpretq_u64_p64",
     "arguments": [
-      "float32x4_t a"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32xq_f64",
+    "name": "vreinterpretq_u64_p8",
     "arguments": [
-      "float64x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32z_f32",
+    "name": "vreinterpretq_u64_s16",
     "arguments": [
-      "float32x2_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32z_f64",
+    "name": "vreinterpretq_u64_s32",
     "arguments": [
-      "float64x1_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32zq_f32",
+    "name": "vreinterpretq_u64_s64",
     "arguments": [
-      "float32x4_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd32zq_f64",
+    "name": "vreinterpretq_u64_s8",
     "arguments": [
-      "float64x2_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT32Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64x_f32",
+    "name": "vreinterpretq_u64_u16",
     "arguments": [
-      "float32x2_t a"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64x_f64",
+    "name": "vreinterpretq_u64_u32",
     "arguments": [
-      "float64x1_t a"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64xq_f32",
+    "name": "vreinterpretq_u64_u8",
     "arguments": [
-      "float32x4_t a"
+      "uint8x16_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64xq_f64",
+    "name": "vreinterpretq_u8_f16",
     "arguments": [
-      "float64x2_t a"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64X"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64z_f32",
+    "name": "vreinterpretq_u8_f32",
     "arguments": [
-      "float32x2_t a"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64z_f64",
+    "name": "vreinterpretq_u8_f64",
     "arguments": [
-      "float64x1_t a"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -89365,68 +292915,71 @@
     ],
     "instructions": [
       [
-        "FRINT64Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64zq_f32",
+    "name": "vreinterpretq_u8_p128",
     "arguments": [
-      "float32x4_t a"
+      "poly128_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.1Q"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd64zq_f64",
+    "name": "vreinterpretq_u8_p16",
     "arguments": [
-      "float64x2_t a"
+      "poly16x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINT64Z"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd_f16",
+    "name": "vreinterpretq_u8_p64",
     "arguments": [
-      "float16x4_t a"
+      "poly64x2_t a"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -89435,1181 +292988,1256 @@
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd_f32",
+    "name": "vreinterpretq_u8_p8",
     "arguments": [
-      "float32x2_t a"
+      "poly8x16_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnd_f64",
+    "name": "vreinterpretq_u8_s16",
     "arguments": [
-      "float64x1_t a"
+      "int16x8_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnda_f16",
+    "name": "vreinterpretq_u8_s32",
     "arguments": [
-      "float16x4_t a"
+      "int32x4_t a"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnda_f32",
+    "name": "vreinterpretq_u8_s64",
     "arguments": [
-      "float32x2_t a"
+      "int64x2_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrnda_f64",
+    "name": "vreinterpretq_u8_s8",
     "arguments": [
-      "float64x1_t a"
+      "int8x16_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndah_f16",
+    "name": "vreinterpretq_u8_u16",
     "arguments": [
-      "float16_t a"
+      "uint16x8_t a"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndaq_f16",
+    "name": "vreinterpretq_u8_u32",
     "arguments": [
-      "float16x8_t a"
+      "uint32x4_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndaq_f32",
+    "name": "vreinterpretq_u8_u64",
     "arguments": [
-      "float32x4_t a"
+      "uint64x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "NOP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndaq_f64",
+    "name": "vrev16_p8",
     "arguments": [
-      "float64x2_t a"
+      "poly8x8_t vec"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTA"
+        "REV16"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndh_f16",
+    "name": "vrev16_s8",
     "arguments": [
-      "float16_t a"
+      "int8x8_t vec"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "REV16"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndi_f16",
+    "name": "vrev16_u8",
     "arguments": [
-      "float16x4_t a"
+      "uint8x8_t vec"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV16"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndi_f32",
+    "name": "vrev16q_p8",
     "arguments": [
-      "float32x2_t a"
+      "poly8x16_t vec"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV16"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndi_f64",
+    "name": "vrev16q_s8",
     "arguments": [
-      "float64x1_t a"
+      "int8x16_t vec"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV16"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndih_f16",
+    "name": "vrev16q_u8",
     "arguments": [
-      "float16_t a"
+      "uint8x16_t vec"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV16"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndiq_f16",
+    "name": "vrev32_p16",
     "arguments": [
-      "float16x8_t a"
+      "poly16x4_t vec"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndiq_f32",
+    "name": "vrev32_p8",
     "arguments": [
-      "float32x4_t a"
+      "poly8x8_t vec"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndiq_f64",
+    "name": "vrev32_s16",
     "arguments": [
-      "float64x2_t a"
+      "int16x4_t vec"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTI"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndm_f16",
+    "name": "vrev32_s8",
     "arguments": [
-      "float16x4_t a"
+      "int8x8_t vec"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndm_f32",
+    "name": "vrev32_u16",
     "arguments": [
-      "float32x2_t a"
+      "uint16x4_t vec"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndm_f64",
+    "name": "vrev32_u8",
     "arguments": [
-      "float64x1_t a"
+      "uint8x8_t vec"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndmh_f16",
+    "name": "vrev32q_p16",
     "arguments": [
-      "float16_t a"
+      "poly16x8_t vec"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "vec": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndmq_f16",
+    "name": "vrev32q_p8",
     "arguments": [
-      "float16x8_t a"
+      "poly8x16_t vec"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndmq_f32",
+    "name": "vrev32q_s16",
     "arguments": [
-      "float32x4_t a"
+      "int16x8_t vec"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "vec": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndmq_f64",
+    "name": "vrev32q_s8",
     "arguments": [
-      "float64x2_t a"
+      "int8x16_t vec"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTM"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndn_f16",
+    "name": "vrev32q_u16",
     "arguments": [
-      "float16x4_t a"
+      "uint16x8_t vec"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "vec": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndn_f32",
+    "name": "vrev32q_u8",
     "arguments": [
-      "float32x2_t a"
+      "uint8x16_t vec"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV32"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndn_f64",
+    "name": "vrev64_f16",
     "arguments": [
-      "float64x1_t a"
+      "float16x4_t vec"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndnh_f16",
+    "name": "vrev64_f32",
     "arguments": [
-      "float16_t a"
+      "float32x2_t vec"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "vec": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndnq_f16",
+    "name": "vrev64_p16",
     "arguments": [
-      "float16x8_t a"
+      "poly16x4_t vec"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndnq_f32",
+    "name": "vrev64_p8",
     "arguments": [
-      "float32x4_t a"
+      "poly8x8_t vec"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndnq_f64",
+    "name": "vrev64_s16",
     "arguments": [
-      "float64x2_t a"
+      "int16x4_t vec"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndns_f32",
+    "name": "vrev64_s32",
     "arguments": [
-      "float32_t a"
+      "int32x2_t vec"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Sn"
+      "vec": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTN"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndp_f16",
+    "name": "vrev64_s8",
     "arguments": [
-      "float16x4_t a"
+      "int8x8_t vec"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndp_f32",
+    "name": "vrev64_u16",
     "arguments": [
-      "float32x2_t a"
+      "uint16x4_t vec"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "vec": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndp_f64",
+    "name": "vrev64_u32",
     "arguments": [
-      "float64x1_t a"
+      "uint32x2_t vec"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "vec": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndph_f16",
+    "name": "vrev64_u8",
     "arguments": [
-      "float16_t a"
+      "uint8x8_t vec"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "vec": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndpq_f16",
+    "name": "vrev64q_f16",
     "arguments": [
-      "float16x8_t a"
+      "float16x8_t vec"
     ],
     "return_type": {
       "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "vec": {
         "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndpq_f32",
+    "name": "vrev64q_f32",
     "arguments": [
-      "float32x4_t a"
+      "float32x4_t vec"
     ],
     "return_type": {
       "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "vec": {
         "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndpq_f64",
+    "name": "vrev64q_p16",
     "arguments": [
-      "float64x2_t a"
+      "poly16x8_t vec"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vec": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTP"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndq_f16",
+    "name": "vrev64q_p8",
     "arguments": [
-      "float16x8_t a"
+      "poly8x16_t vec"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndq_f32",
+    "name": "vrev64q_s16",
     "arguments": [
-      "float32x4_t a"
+      "int16x8_t vec"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "vec": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndq_f64",
+    "name": "vrev64q_s32",
     "arguments": [
-      "float64x2_t a"
+      "int32x4_t vec"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vec": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTZ"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndx_f16",
+    "name": "vrev64q_s8",
     "arguments": [
-      "float16x4_t a"
+      "int8x16_t vec"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndx_f32",
+    "name": "vrev64q_u16",
     "arguments": [
-      "float32x2_t a"
+      "uint16x8_t vec"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "vec": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndx_f64",
+    "name": "vrev64q_u32",
     "arguments": [
-      "float64x1_t a"
+      "uint32x4_t vec"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "vec": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndxh_f16",
+    "name": "vrev64q_u8",
     "arguments": [
-      "float16_t a"
+      "uint8x16_t vec"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "vec": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "REV64"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndxq_f16",
+    "name": "vrhadd_s16",
     "arguments": [
-      "float16x8_t a"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "SRHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndxq_f32",
+    "name": "vrhadd_s32",
     "arguments": [
-      "float32x4_t a"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "SRHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrndxq_f64",
+    "name": "vrhadd_s8",
     "arguments": [
-      "float64x2_t a"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRINTX"
+        "SRHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_s16",
+    "name": "vrhadd_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -90626,19 +294254,19 @@
     ],
     "instructions": [
       [
-        "SRSHL"
+        "URHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_s32",
+    "name": "vrhadd_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -90655,26 +294283,26 @@
     ],
     "instructions": [
       [
-        "SRSHL"
+        "URHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_s64",
+    "name": "vrhadd_u8",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -90684,26 +294312,26 @@
     ],
     "instructions": [
       [
-        "SRSHL"
+        "URHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_s8",
+    "name": "vrhaddq_s16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -90713,26 +294341,26 @@
     ],
     "instructions": [
       [
-        "SRSHL"
+        "SRHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_u16",
+    "name": "vrhaddq_s32",
     "arguments": [
-      "uint16x4_t a",
-      "int16x4_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -90742,26 +294370,26 @@
     ],
     "instructions": [
       [
-        "URSHL"
+        "SRHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_u32",
+    "name": "vrhaddq_s8",
     "arguments": [
-      "uint32x2_t a",
-      "int32x2_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -90771,26 +294399,26 @@
     ],
     "instructions": [
       [
-        "URSHL"
+        "SRHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_u64",
+    "name": "vrhaddq_u16",
     "arguments": [
-      "uint64x1_t a",
-      "int64x1_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -90800,26 +294428,26 @@
     ],
     "instructions": [
       [
-        "URSHL"
+        "URHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshl_u8",
+    "name": "vrhaddq_u32",
     "arguments": [
-      "uint8x8_t a",
-      "int8x8_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -90829,53 +294457,51 @@
     ],
     "instructions": [
       [
-        "URSHL"
+        "URHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshld_s64",
+    "name": "vrhaddq_u8",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHL"
+        "URHADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshld_u64",
+    "name": "vrnd32x_f32",
     "arguments": [
-      "uint64_t a",
-      "int64_t b"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
+        "register": "Vn"
       }
     },
     "Architectures": [
@@ -90883,527 +294509,415 @@
     ],
     "instructions": [
       [
-        "URSHL"
+        "FRINT32X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_s16",
+    "name": "vrnd32x_f64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHL"
+        "FRINT32X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_s32",
+    "name": "vrnd32xq_f32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHL"
+        "FRINT32X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_s64",
+    "name": "vrnd32xq_f64",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHL"
+        "FRINT32X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_s8",
+    "name": "vrnd32z_f32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHL"
+        "FRINT32Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_u16",
+    "name": "vrnd32z_f64",
     "arguments": [
-      "uint16x8_t a",
-      "int16x8_t b"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHL"
+        "FRINT32Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_u32",
+    "name": "vrnd32zq_f32",
     "arguments": [
-      "uint32x4_t a",
-      "int32x4_t b"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHL"
+        "FRINT32Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_u64",
+    "name": "vrnd32zq_f64",
     "arguments": [
-      "uint64x2_t a",
-      "int64x2_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHL"
+        "FRINT32Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshlq_u8",
+    "name": "vrnd64x_f32",
     "arguments": [
-      "uint8x16_t a",
-      "int8x16_t b"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "b": {
-        "register": "Vm.16B"
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHL"
+        "FRINT64X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_s16",
+    "name": "vrnd64x_f64",
     "arguments": [
-      "int16x4_t a",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINT64X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_s32",
+    "name": "vrnd64xq_f32",
     "arguments": [
-      "int32x2_t a",
-      "const int n"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINT64X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_s64",
+    "name": "vrnd64xq_f64",
     "arguments": [
-      "int64x1_t a",
-      "const int n"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINT64X"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_s8",
+    "name": "vrnd64z_f32",
     "arguments": [
-      "int8x8_t a",
-      "const int n"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINT64Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_u16",
+    "name": "vrnd64z_f64",
     "arguments": [
-      "uint16x4_t a",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINT64Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_u32",
+    "name": "vrnd64zq_f32",
     "arguments": [
-      "uint32x2_t a",
-      "const int n"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINT64Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_u64",
+    "name": "vrnd64zq_f64",
     "arguments": [
-      "uint64x1_t a",
-      "const int n"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINT64Z"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshr_n_u8",
+    "name": "vrnd_f16",
     "arguments": [
-      "uint8x8_t a",
-      "const int n"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrd_n_s64",
+    "name": "vrnd_f32",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrd_n_u64",
+    "name": "vrnd_f64",
     "arguments": [
-      "uint64_t a",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
       }
     },
     "Architectures": [
@@ -91411,95 +294925,70 @@
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_high_n_s16",
+    "name": "vrnda_f16",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a",
-      "const int n"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
-      },
-      "r": {
-        "register": "Vd.8B"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN2"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_high_n_s32",
+    "name": "vrnda_f32",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a",
-      "const int n"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
-      },
-      "r": {
-        "register": "Vd.4H"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN2"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_high_n_s64",
+    "name": "vrnda_f64",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Dn"
       }
     },
     "Architectures": [
@@ -91507,538 +294996,424 @@
     ],
     "instructions": [
       [
-        "RSHRN2"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_high_n_u16",
+    "name": "vrndah_f16",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "const int n"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
-      },
-      "r": {
-        "register": "Vd.8B"
+        "register": "Hn"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN2"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_high_n_u32",
+    "name": "vrndaq_f16",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "const int n"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
-      },
-      "r": {
-        "register": "Vd.4H"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN2"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_high_n_u64",
+    "name": "vrndaq_f32",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "const int n"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
-      },
-      "r": {
-        "register": "32(Vd)"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN2"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_n_s16",
+    "name": "vrndaq_f64",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN"
+        "FRINTA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_n_s32",
+    "name": "vrndh_f16",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_n_s64",
+    "name": "vrndi_f16",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_n_u16",
+    "name": "vrndi_f32",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_n_u32",
+    "name": "vrndi_f64",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrn_n_u64",
+    "name": "vrndih_f16",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSHRN"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_s16",
+    "name": "vrndiq_f16",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_s32",
+    "name": "vrndiq_f32",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_s64",
+    "name": "vrndiq_f64",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINTI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_s8",
+    "name": "vrndm_f16",
     "arguments": [
-      "int8x16_t a",
-      "const int n"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSHR"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_u16",
+    "name": "vrndm_f32",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_u32",
+    "name": "vrndm_f64",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_u64",
+    "name": "vrndmh_f16",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrshrq_n_u8",
+    "name": "vrndmq_f16",
     "arguments": [
-      "uint8x16_t a",
-      "const int n"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSHR"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrte_f16",
+    "name": "vrndmq_f32",
     "arguments": [
-      "float16x4_t a"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -92047,66 +295422,65 @@
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrte_f32",
+    "name": "vrndmq_f64",
     "arguments": [
-      "float32x2_t a"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTM"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrte_f64",
+    "name": "vrndn_f16",
     "arguments": [
-      "float64x1_t a"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrte_u32",
+    "name": "vrndn_f32",
     "arguments": [
-      "uint32x2_t a"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -92114,24 +295488,23 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrted_f64",
+    "name": "vrndn_f64",
     "arguments": [
-      "float64_t a"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -92139,17 +295512,18 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrteh_f16",
+    "name": "vrndnh_f16",
     "arguments": [
       "float16_t a"
     ],
@@ -92162,17 +295536,18 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrteq_f16",
+    "name": "vrndnq_f16",
     "arguments": [
       "float16x8_t a"
     ],
@@ -92190,13 +295565,13 @@
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrteq_f32",
+    "name": "vrndnq_f32",
     "arguments": [
       "float32x4_t a"
     ],
@@ -92209,19 +295584,18 @@
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrteq_f64",
+    "name": "vrndnq_f64",
     "arguments": [
       "float64x2_t a"
     ],
@@ -92234,42 +295608,18 @@
       }
     },
     "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FRSQRTE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vrsqrteq_u32",
-    "arguments": [
-      "uint32x4_t a"
-    ],
-    "return_type": {
-      "value": "uint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      }
-    },
-    "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtes_f32",
+    "name": "vrndns_f32",
     "arguments": [
       "float32_t a"
     ],
@@ -92282,20 +295632,20 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTE"
+        "FRINTN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrts_f16",
+    "name": "vrndp_f16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "float16x4_t a"
     ],
     "return_type": {
       "value": "float16x4_t"
@@ -92303,9 +295653,6 @@
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -92314,16 +295661,15 @@
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrts_f32",
+    "name": "vrndp_f32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "float32x2_t a"
     ],
     "return_type": {
       "value": "float32x2_t"
@@ -92331,28 +295677,23 @@
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2S"
-      },
-      "b": {
-        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrts_f64",
+    "name": "vrndp_f64",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "float64x1_t a"
     ],
     "return_type": {
       "value": "float64x1_t"
@@ -92360,9 +295701,6 @@
     "Arguments_Preparation": {
       "a": {
         "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
       }
     },
     "Architectures": [
@@ -92370,80 +295708,70 @@
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtsd_f64",
+    "name": "vrndph_f16",
     "arguments": [
-      "float64_t a",
-      "float64_t b"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "float64_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
-      },
-      "b": {
-        "register": "Dm"
+        "register": "Hn"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtsh_f16",
+    "name": "vrndpq_f16",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
-      },
-      "b": {
-        "register": "Hm"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtsq_f16",
+    "name": "vrndpq_f32",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
-      },
-      "b": {
-        "register": "Vm.8H"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
@@ -92452,450 +295780,344 @@
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtsq_f32",
+    "name": "vrndpq_f64",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
-      },
-      "b": {
-        "register": "Vm.4S"
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTP"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtsq_f64",
+    "name": "vrndq_f16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
-      },
-      "b": {
-        "register": "Vm.2D"
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsqrtss_f32",
+    "name": "vrndq_f32",
     "arguments": [
-      "float32_t a",
-      "float32_t b"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "float32_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sn"
-      },
-      "b": {
-        "register": "Sm"
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FRSQRTS"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_s16",
+    "name": "vrndq_f64",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
-      "const int n"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSRA"
+        "FRINTZ"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_s32",
+    "name": "vrndx_f16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
-      "const int n"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_s64",
+    "name": "vrndx_f32",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b",
-      "const int n"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_s8",
+    "name": "vrndx_f64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b",
-      "const int n"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_u16",
+    "name": "vrndxh_f16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
-      "const int n"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_u32",
+    "name": "vrndxq_f16",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
-      "const int n"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_u64",
+    "name": "vrndxq_f32",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b",
-      "const int n"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsra_n_u8",
+    "name": "vrndxq_f64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "const int n"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "FRINTX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsrad_n_s64",
+    "name": "vrshl_s16",
     "arguments": [
-      "int64_t a",
-      "int64_t b",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRSRA"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsrad_n_u64",
+    "name": "vrshl_s32",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_s16",
+    "name": "vrshl_s64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "const int n"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -92905,31 +296127,26 @@
     ],
     "instructions": [
       [
-        "SRSRA"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_s32",
+    "name": "vrshl_s8",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "const int n"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -92939,31 +296156,26 @@
     ],
     "instructions": [
       [
-        "SRSRA"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_s64",
+    "name": "vrshl_u16",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b",
-      "const int n"
+      "uint16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -92973,31 +296185,26 @@
     ],
     "instructions": [
       [
-        "SRSRA"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_s8",
+    "name": "vrshl_u32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
-      "const int n"
+      "uint32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.16B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -93007,31 +296214,26 @@
     ],
     "instructions": [
       [
-        "SRSRA"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_u16",
+    "name": "vrshl_u64",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
-      "const int n"
+      "uint64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -93041,31 +296243,26 @@
     ],
     "instructions": [
       [
-        "URSRA"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_u32",
+    "name": "vrshl_u8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "const int n"
+      "uint8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -93075,88 +296272,73 @@
     ],
     "instructions": [
       [
-        "URSRA"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_u64",
+    "name": "vrshld_s64",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
-      "const int n"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsraq_n_u8",
+    "name": "vrshld_u64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "const int n"
+      "uint64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.16B"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "URSRA"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_high_s16",
+    "name": "vrshlq_s16",
     "arguments": [
-      "int8x8_t r",
       "int16x8_t a",
       "int16x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -93164,30 +296346,28 @@
       },
       "b": {
         "register": "Vm.8H"
-      },
-      "r": {
-        "register": "Vd.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSUBHN2"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_high_s32",
+    "name": "vrshlq_s32",
     "arguments": [
-      "int16x4_t r",
       "int32x4_t a",
       "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -93195,30 +296375,28 @@
       },
       "b": {
         "register": "Vm.4S"
-      },
-      "r": {
-        "register": "Vd.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSUBHN2"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_high_s64",
+    "name": "vrshlq_s64",
     "arguments": [
-      "int32x2_t r",
       "int64x2_t a",
       "int64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -93226,129 +296404,122 @@
       },
       "b": {
         "register": "Vm.2D"
-      },
-      "r": {
-        "register": "Vd.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSUBHN2"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_high_u16",
+    "name": "vrshlq_s8",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
-      },
-      "r": {
-        "register": "Vd.8B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSUBHN2"
+        "SRSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_high_u32",
+    "name": "vrshlq_u16",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "uint16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
       "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4S"
-      },
-      "r": {
-        "register": "Vd.4H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSUBHN2"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_high_u64",
+    "name": "vrshlq_u32",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2D"
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "RSUBHN2"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_s16",
+    "name": "vrshlq_u64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -93358,26 +296529,26 @@
     ],
     "instructions": [
       [
-        "RSUBHN"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_s32",
+    "name": "vrshlq_u8",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "uint8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -93387,26 +296558,27 @@
     ],
     "instructions": [
       [
-        "RSUBHN"
+        "URSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_s64",
+    "name": "vrshr_n_s16",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int16x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4H"
       },
-      "b": {
-        "register": "Vm.2D"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -93416,26 +296588,27 @@
     ],
     "instructions": [
       [
-        "RSUBHN"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_u16",
+    "name": "vrshr_n_s32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int32x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
-      "b": {
-        "register": "Vm.8H"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -93445,26 +296618,27 @@
     ],
     "instructions": [
       [
-        "RSUBHN"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_u32",
+    "name": "vrshr_n_s64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int64x1_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Dn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -93474,26 +296648,27 @@
     ],
     "instructions": [
       [
-        "RSUBHN"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vrsubhn_u64",
+    "name": "vrshr_n_s8",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "int8x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -93503,31 +296678,27 @@
     ],
     "instructions": [
       [
-        "RSUBHN"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_f16",
+    "name": "vrshr_n_u16",
     "arguments": [
-      "float16_t a",
-      "float16x4_t v",
-      "const int lane"
+      "uint16x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "VnH"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.4H"
       },
-      "v": {
-        "register": "Vd.4H"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -93537,31 +296708,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_f32",
+    "name": "vrshr_n_u32",
     "arguments": [
-      "float32_t a",
-      "float32x2_t v",
-      "const int lane"
+      "uint32x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vn.2S"
       },
-      "v": {
-        "register": "Vd.2S"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -93571,63 +296738,57 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_f64",
+    "name": "vrshr_n_u64",
     "arguments": [
-      "float64_t a",
-      "float64x1_t v",
-      "const int lane"
+      "uint64x1_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+        "register": "Dn"
       },
-      "v": {
-        "register": "Vd.1D"
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_p16",
+    "name": "vrshr_n_u8",
     "arguments": [
-      "poly16_t a",
-      "poly16x4_t v",
-      "const int lane"
+      "uint8x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.8B"
       },
-      "v": {
-        "register": "Vd.4H"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -93637,302 +296798,275 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_p64",
+    "name": "vrshrd_n_s64",
     "arguments": [
-      "poly64_t a",
-      "poly64x1_t v",
-      "const int lane"
+      "int64_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+        "register": "Dn"
       },
-      "v": {
-        "register": "Vd.1D"
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_p8",
+    "name": "vrshrd_n_u64",
     "arguments": [
-      "poly8_t a",
-      "poly8x8_t v",
-      "const int lane"
+      "uint64_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Dn"
       },
-      "v": {
-        "register": "Vd.8B"
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_s16",
+    "name": "vrshrn_high_n_s16",
     "arguments": [
-      "int16_t a",
-      "int16x4_t v",
-      "const int lane"
+      "int8x8_t r",
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
+        "register": "Vn.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       },
-      "v": {
-        "register": "Vd.4H"
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_s32",
+    "name": "vrshrn_high_n_s32",
     "arguments": [
-      "int32_t a",
-      "int32x2_t v",
-      "const int lane"
+      "int16x4_t r",
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
+        "register": "Vn.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       },
-      "v": {
-        "register": "Vd.2S"
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_s64",
+    "name": "vrshrn_high_n_s64",
     "arguments": [
-      "int64_t a",
-      "int64x1_t v",
-      "const int lane"
+      "int32x2_t r",
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
+        "register": "Vn.2D"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       },
-      "v": {
-        "register": "Vd.1D"
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_s8",
+    "name": "vrshrn_high_n_u16",
     "arguments": [
-      "int8_t a",
-      "int8x8_t v",
-      "const int lane"
+      "uint8x8_t r",
+      "uint16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
+        "register": "Vn.8H"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       },
-      "v": {
+      "r": {
         "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_u16",
+    "name": "vrshrn_high_n_u32",
     "arguments": [
-      "uint16_t a",
-      "uint16x4_t v",
-      "const int lane"
+      "uint16x4_t r",
+      "uint32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
+        "register": "Vn.4S"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       },
-      "v": {
+      "r": {
         "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_u32",
+    "name": "vrshrn_high_n_u64",
     "arguments": [
-      "uint32_t a",
-      "uint32x2_t v",
-      "const int lane"
+      "uint32x2_t r",
+      "uint64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
+        "register": "Vn.2D"
       },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       },
-      "v": {
-        "register": "Vd.2S"
+      "r": {
+        "register": "32(Vd)"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_u64",
+    "name": "vrshrn_n_s16",
     "arguments": [
-      "uint64_t a",
-      "uint64x1_t v",
-      "const int lane"
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vd.1D"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -93942,31 +297076,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vset_lane_u8",
+    "name": "vrshrn_n_s32",
     "arguments": [
-      "uint8_t a",
-      "uint8x8_t v",
-      "const int lane"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vd.8B"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -93976,31 +297106,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_f16",
+    "name": "vrshrn_n_s64",
     "arguments": [
-      "float16_t a",
-      "float16x8_t v",
-      "const int lane"
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "VnH"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.2D"
       },
-      "v": {
-        "register": "Vd.8H"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -94010,31 +297136,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_f32",
+    "name": "vrshrn_n_u16",
     "arguments": [
-      "float32_t a",
-      "float32x4_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vd.4S"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -94044,63 +297166,57 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_f64",
+    "name": "vrshrn_n_u32",
     "arguments": [
-      "float64_t a",
-      "float64x2_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vd.2D"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_p16",
+    "name": "vrshrn_n_u64",
     "arguments": [
-      "poly16_t a",
-      "poly16x8_t v",
-      "const int lane"
+      "uint64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.2D"
       },
-      "v": {
-        "register": "Vd.8H"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -94110,64 +297226,57 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "RSHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_p64",
+    "name": "vrshrq_n_s16",
     "arguments": [
-      "poly64_t a",
-      "poly64x2_t v",
-      "const int lane"
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vd.2D"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_p8",
+    "name": "vrshrq_n_s32",
     "arguments": [
-      "poly8_t a",
-      "poly8x16_t v",
-      "const int lane"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vd.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -94177,31 +297286,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_s16",
+    "name": "vrshrq_n_s64",
     "arguments": [
-      "int16_t a",
-      "int16x8_t v",
-      "const int lane"
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.2D"
       },
-      "v": {
-        "register": "Vd.8H"
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -94211,31 +297316,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_s32",
+    "name": "vrshrq_n_s8",
     "arguments": [
-      "int32_t a",
-      "int32x4_t v",
-      "const int lane"
+      "int8x16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.16B"
       },
-      "v": {
-        "register": "Vd.4S"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -94245,31 +297346,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "SRSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_s64",
+    "name": "vrshrq_n_u16",
     "arguments": [
-      "int64_t a",
-      "int64x2_t v",
-      "const int lane"
+      "uint16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+        "register": "Vn.8H"
       },
-      "v": {
-        "register": "Vd.2D"
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -94279,31 +297376,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_s8",
+    "name": "vrshrq_n_u32",
     "arguments": [
-      "int8_t a",
-      "int8x16_t v",
-      "const int lane"
+      "uint32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
+        "register": "Vn.4S"
       },
-      "v": {
-        "register": "Vd.16B"
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -94313,31 +297406,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_u16",
+    "name": "vrshrq_n_u64",
     "arguments": [
-      "uint16_t a",
-      "uint16x8_t v",
-      "const int lane"
+      "uint64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vn.2D"
       },
-      "v": {
-        "register": "Vd.8H"
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -94347,31 +297436,27 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_u32",
+    "name": "vrshrq_n_u8",
     "arguments": [
-      "uint32_t a",
-      "uint32x4_t v",
-      "const int lane"
+      "uint8x16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+        "register": "Vn.16B"
       },
-      "v": {
-        "register": "Vd.4S"
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -94381,65 +297466,46 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "URSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_u64",
+    "name": "vrsqrte_f16",
     "arguments": [
-      "uint64_t a",
-      "uint64x2_t v",
-      "const int lane"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "v": {
-        "register": "Vd.2D"
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOV"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsetq_lane_u8",
+    "name": "vrsqrte_f32",
     "arguments": [
-      "uint8_t a",
-      "uint8x16_t v",
-      "const int lane"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Rn"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
-      },
-      "v": {
-        "register": "Vd.16B"
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
@@ -94449,150 +297515,116 @@
     ],
     "instructions": [
       [
-        "MOV"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha1cq_u32",
+    "name": "vrsqrte_f64",
     "arguments": [
-      "uint32x4_t hash_abcd",
-      "uint32_t hash_e",
-      "uint32x4_t wk"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
-      "hash_abcd": {
-        "register": "Qd"
-      },
-      "hash_e": {
-        "register": "Sn"
-      },
-      "wk": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA1C"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha1h_u32",
+    "name": "vrsqrte_u32",
     "arguments": [
-      "uint32_t hash_e"
+      "uint32x2_t a"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "hash_e": {
-        "register": "Sn"
+      "a": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA1H"
+        "URSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha1mq_u32",
+    "name": "vrsqrted_f64",
     "arguments": [
-      "uint32x4_t hash_abcd",
-      "uint32_t hash_e",
-      "uint32x4_t wk"
+      "float64_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "hash_abcd": {
-        "register": "Qd"
-      },
-      "hash_e": {
-        "register": "Sn"
-      },
-      "wk": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA1M"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha1pq_u32",
+    "name": "vrsqrteh_f16",
     "arguments": [
-      "uint32x4_t hash_abcd",
-      "uint32_t hash_e",
-      "uint32x4_t wk"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "hash_abcd": {
-        "register": "Qd"
-      },
-      "hash_e": {
-        "register": "Sn"
-      },
-      "wk": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA1P"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha1su0q_u32",
+    "name": "vrsqrteq_f16",
     "arguments": [
-      "uint32x4_t w0_3",
-      "uint32x4_t w4_7",
-      "uint32x4_t w8_11"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "w0_3": {
-        "register": "Vd.4S"
-      },
-      "w4_7": {
-        "register": "Vn.4S"
-      },
-      "w8_11": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
@@ -94601,150 +297633,122 @@
     ],
     "instructions": [
       [
-        "SHA1SU0"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha1su1q_u32",
+    "name": "vrsqrteq_f32",
     "arguments": [
-      "uint32x4_t tw0_3",
-      "uint32x4_t w12_15"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "tw0_3": {
-        "register": "Vd.4S"
-      },
-      "w12_15": {
+      "a": {
         "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA1SU1"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha256h2q_u32",
+    "name": "vrsqrteq_f64",
     "arguments": [
-      "uint32x4_t hash_efgh",
-      "uint32x4_t hash_abcd",
-      "uint32x4_t wk"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
-      "hash_abcd": {
-        "register": "Qn"
-      },
-      "hash_efgh": {
-        "register": "Qd"
-      },
-      "wk": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA256H2"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha256hq_u32",
+    "name": "vrsqrteq_u32",
     "arguments": [
-      "uint32x4_t hash_abcd",
-      "uint32x4_t hash_efgh",
-      "uint32x4_t wk"
+      "uint32x4_t a"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "hash_abcd": {
-        "register": "Qd"
-      },
-      "hash_efgh": {
-        "register": "Qn"
-      },
-      "wk": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA256H"
+        "URSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha256su0q_u32",
+    "name": "vrsqrtes_f32",
     "arguments": [
-      "uint32x4_t w0_3",
-      "uint32x4_t w4_7"
+      "float32_t a"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
-      "w0_3": {
-        "register": "Vd.4S"
-      },
-      "w4_7": {
-        "register": "Vn.4S"
+      "a": {
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA256SU0"
+        "FRSQRTE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha256su1q_u32",
+    "name": "vrsqrts_f16",
     "arguments": [
-      "uint32x4_t tw0_3",
-      "uint32x4_t w8_11",
-      "uint32x4_t w12_15"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
-      "tw0_3": {
-        "register": "Vd.4S"
-      },
-      "w12_15": {
-        "register": "Vm.4S"
+      "a": {
+        "register": "Vn.4H"
       },
-      "w8_11": {
-        "register": "Vn.4S"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -94753,84 +297757,82 @@
     ],
     "instructions": [
       [
-        "SHA256SU1"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha512h2q_u64",
+    "name": "vrsqrts_f32",
     "arguments": [
-      "uint64x2_t sum_ab",
-      "uint64x2_t hash_c_",
-      "uint64x2_t hash_ab"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "hash_ab": {},
-      "hash_c_": {
-        "register": "Qn"
+      "a": {
+        "register": "Vn.2S"
       },
-      "sum_ab": {
-        "register": "Qd"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHA512H2"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha512hq_u64",
+    "name": "vrsqrts_f64",
     "arguments": [
-      "uint64x2_t hash_ed",
-      "uint64x2_t hash_gf",
-      "uint64x2_t kwh_kwh2"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
-      "hash_ed": {
-        "register": "Qd"
-      },
-      "hash_gf": {
-        "register": "Qn"
+      "a": {
+        "register": "Dn"
       },
-      "kwh_kwh2": {}
+      "b": {
+        "register": "Dm"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "SHA512H"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha512su0q_u64",
+    "name": "vrsqrtsd_f64",
     "arguments": [
-      "uint64x2_t w0_1",
-      "uint64x2_t w2_"
+      "float64_t a",
+      "float64_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float64_t"
     },
     "Arguments_Preparation": {
-      "w0_1": {
-        "register": "Vd.2D"
+      "a": {
+        "register": "Dn"
       },
-      "w2_": {
-        "register": "Vn.2D"
+      "b": {
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -94838,86 +297840,81 @@
     ],
     "instructions": [
       [
-        "SHA512SU0"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsha512su1q_u64",
+    "name": "vrsqrtsh_f16",
     "arguments": [
-      "uint64x2_t s01_s02",
-      "uint64x2_t w14_15",
-      "uint64x2_t w9_10"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "s01_s02": {
-        "register": "Vd.2D"
-      },
-      "w14_15": {
-        "register": "Vn.2D"
+      "a": {
+        "register": "Hn"
       },
-      "w9_10": {}
+      "b": {
+        "register": "Hm"
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "SHA512SU1"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_s16",
+    "name": "vrsqrtsq_f16",
     "arguments": [
-      "int16x4_t a",
-      "const int n"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_s32",
+    "name": "vrsqrtsq_f32",
     "arguments": [
-      "int32x2_t a",
-      "const int n"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -94927,87 +297924,85 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_s64",
+    "name": "vrsqrtsq_f64",
     "arguments": [
-      "int64x1_t a",
-      "const int n"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_s8",
+    "name": "vrsqrtss_f32",
     "arguments": [
-      "int8x8_t a",
-      "const int n"
+      "float32_t a",
+      "float32_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float32_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Sn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "b": {
+        "register": "Sm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FRSQRTS"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_u16",
+    "name": "vrsra_n_s16",
     "arguments": [
-      "uint16x4_t a",
+      "int16x4_t a",
+      "int16x4_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
         "register": "Vn.4H"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 15
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -95017,27 +298012,31 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_u32",
+    "name": "vrsra_n_s32",
     "arguments": [
-      "uint32x2_t a",
+      "int32x2_t a",
+      "int32x2_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
         "register": "Vn.2S"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 31
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -95047,27 +298046,31 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_u64",
+    "name": "vrsra_n_s64",
     "arguments": [
-      "uint64x1_t a",
+      "int64x1_t a",
+      "int64x1_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Dd"
+      },
+      "b": {
         "register": "Dn"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 63
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -95077,27 +298080,31 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_n_u8",
+    "name": "vrsra_n_s8",
     "arguments": [
-      "uint8x8_t a",
+      "int8x8_t a",
+      "int8x8_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
         "register": "Vn.8B"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 7
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -95107,26 +298114,31 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_s16",
+    "name": "vrsra_n_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.4H"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -95136,26 +298148,31 @@
     ],
     "instructions": [
       [
-        "SSHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_s32",
+    "name": "vrsra_n_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.2S"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -95165,26 +298182,31 @@
     ],
     "instructions": [
       [
-        "SSHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_s64",
+    "name": "vrsra_n_u64",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "uint64x1_t a",
+      "uint64x1_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Dd"
       },
       "b": {
-        "register": "Dm"
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -95194,26 +298216,31 @@
     ],
     "instructions": [
       [
-        "SSHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_s8",
+    "name": "vrsra_n_u8",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.8B"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -95223,84 +298250,95 @@
     ],
     "instructions": [
       [
-        "SSHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_u16",
+    "name": "vrsrad_n_s64",
     "arguments": [
-      "uint16x4_t a",
-      "int16x4_t b"
+      "int64_t a",
+      "int64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_u32",
+    "name": "vrsrad_n_u64",
     "arguments": [
-      "uint32x2_t a",
-      "int32x2_t b"
+      "uint64_t a",
+      "uint64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_u64",
+    "name": "vrsraq_n_s16",
     "arguments": [
-      "uint64x1_t a",
-      "int64x1_t b"
+      "int16x8_t a",
+      "int16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -95310,26 +298348,31 @@
     ],
     "instructions": [
       [
-        "USHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshl_u8",
+    "name": "vrsraq_n_s32",
     "arguments": [
-      "uint8x8_t a",
-      "int8x8_t b"
+      "int32x4_t a",
+      "int32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -95339,193 +298382,234 @@
     ],
     "instructions": [
       [
-        "USHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshld_n_s64",
+    "name": "vrsraq_n_s64",
     "arguments": [
-      "int64_t a",
+      "int64x2_t a",
+      "int64x2_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 63
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshld_n_u64",
+    "name": "vrsraq_n_s8",
     "arguments": [
-      "uint64_t a",
+      "int8x16_t a",
+      "int8x16_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 63
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "SRSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshld_s64",
+    "name": "vrsraq_n_u16",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8H"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshld_u64",
+    "name": "vrsraq_n_u32",
     "arguments": [
-      "uint64_t a",
-      "int64_t b"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.4S"
       },
       "b": {
-        "register": "Dm"
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHL"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_high_n_s16",
+    "name": "vrsraq_n_u64",
     "arguments": [
-      "int16x8_t a",
+      "uint64x2_t a",
+      "uint64x2_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 16
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL2"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_high_n_s32",
+    "name": "vrsraq_n_u8",
     "arguments": [
-      "int32x4_t a",
+      "uint8x16_t a",
+      "uint8x16_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
       },
       "n": {
-        "minimum": 0,
-        "maximum": 32
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL2"
+        "URSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_high_n_s8",
+    "name": "vrsubhn_high_s16",
     "arguments": [
-      "int8x16_t a",
-      "const int n"
+      "int8x8_t r",
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 8
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -95533,27 +298617,30 @@
     ],
     "instructions": [
       [
-        "SSHLL2"
+        "RSUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_high_n_u16",
+    "name": "vrsubhn_high_s32",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "int16x4_t r",
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 16
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -95561,27 +298648,30 @@
     ],
     "instructions": [
       [
-        "USHLL2"
+        "RSUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_high_n_u32",
+    "name": "vrsubhn_high_s64",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "int32x2_t r",
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 32
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -95589,27 +298679,30 @@
     ],
     "instructions": [
       [
-        "USHLL2"
+        "RSUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_high_n_u8",
+    "name": "vrsubhn_high_u16",
     "arguments": [
-      "uint8x16_t a",
-      "const int n"
+      "uint8x8_t r",
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 8
+      "b": {
+        "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -95617,87 +298710,88 @@
     ],
     "instructions": [
       [
-        "USHLL2"
+        "RSUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_n_s16",
+    "name": "vrsubhn_high_u32",
     "arguments": [
-      "int16x4_t a",
-      "const int n"
+      "uint16x4_t r",
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 16
+      "b": {
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL"
+        "RSUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_n_s32",
+    "name": "vrsubhn_high_u64",
     "arguments": [
-      "int32x2_t a",
-      "const int n"
+      "uint32x2_t r",
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 32
+      "b": {
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHLL"
+        "RSUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_n_s8",
+    "name": "vrsubhn_s16",
     "arguments": [
-      "int8x8_t a",
-      "const int n"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 8
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -95707,27 +298801,26 @@
     ],
     "instructions": [
       [
-        "SSHLL"
+        "RSUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_n_u16",
+    "name": "vrsubhn_s32",
     "arguments": [
-      "uint16x4_t a",
-      "const int n"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 16
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -95737,27 +298830,26 @@
     ],
     "instructions": [
       [
-        "USHLL"
+        "RSUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_n_u32",
+    "name": "vrsubhn_s64",
     "arguments": [
-      "uint32x2_t a",
-      "const int n"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 32
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -95767,27 +298859,26 @@
     ],
     "instructions": [
       [
-        "USHLL"
+        "RSUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshll_n_u8",
+    "name": "vrsubhn_u16",
     "arguments": [
-      "uint8x8_t a",
-      "const int n"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 8
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -95797,27 +298888,26 @@
     ],
     "instructions": [
       [
-        "USHLL"
+        "RSUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_s16",
+    "name": "vrsubhn_u32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -95827,27 +298917,26 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "RSUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_s32",
+    "name": "vrsubhn_u64",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -95857,177 +298946,166 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "RSUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_s64",
+    "name": "vscale_f16",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "float16x4_t vn",
+      "int16x4_t vm"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vm": {
+        "register": "Vm.4H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "vn": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FSCALE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_s8",
+    "name": "vscale_f32",
     "arguments": [
-      "int8x16_t a",
-      "const int n"
+      "float32x2_t vn",
+      "int32x2_t vm"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "vm": {
+        "register": "Vm.2S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "vn": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FSCALE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_u16",
+    "name": "vscaleq_f16",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "float16x8_t vn",
+      "int16x8_t vm"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "vm": {
+        "register": "Vm.8H"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "vn": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FSCALE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_u32",
+    "name": "vscaleq_f32",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "float32x4_t vn",
+      "int32x4_t vm"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "vm": {
+        "register": "Vm.4S"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+      "vn": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FSCALE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_u64",
+    "name": "vscaleq_f64",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "float64x2_t vn",
+      "int64x2_t vm"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "vm": {
+        "register": "Vm.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "vn": {
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHL"
+        "FSCALE"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_n_u8",
+    "name": "vset_lane_f16",
     "arguments": [
-      "uint8x16_t a",
-      "const int n"
+      "float16_t a",
+      "float16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "VnH"
       },
-      "n": {
+      "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -96037,26 +299115,31 @@
     ],
     "instructions": [
       [
-        "SHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_s16",
+    "name": "vset_lane_f32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float32_t a",
+      "float32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -96066,55 +299149,63 @@
     ],
     "instructions": [
       [
-        "SSHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_s32",
+    "name": "vset_lane_f64",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float64_t a",
+      "float64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_s64",
+    "name": "vset_lane_p16",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "poly16_t a",
+      "poly16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -96124,55 +299215,64 @@
     ],
     "instructions": [
       [
-        "SSHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_s8",
+    "name": "vset_lane_p64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "poly64_t a",
+      "poly64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_u16",
+    "name": "vset_lane_p8",
     "arguments": [
-      "uint16x8_t a",
-      "int16x8_t b"
+      "poly8_t a",
+      "poly8x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -96182,26 +299282,31 @@
     ],
     "instructions": [
       [
-        "USHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_u32",
+    "name": "vset_lane_s16",
     "arguments": [
-      "uint32x4_t a",
-      "int32x4_t b"
+      "int16_t a",
+      "int16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -96211,26 +299316,31 @@
     ],
     "instructions": [
       [
-        "USHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_u64",
+    "name": "vset_lane_s32",
     "arguments": [
-      "uint64x2_t a",
-      "int64x2_t b"
+      "int32_t a",
+      "int32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -96240,26 +299350,31 @@
     ],
     "instructions": [
       [
-        "USHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshlq_u8",
+    "name": "vset_lane_s64",
     "arguments": [
-      "uint8x16_t a",
-      "int8x16_t b"
+      "int64_t a",
+      "int64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Rn"
       },
-      "b": {
-        "register": "Vm.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -96269,27 +299384,31 @@
     ],
     "instructions": [
       [
-        "USHL"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_s16",
+    "name": "vset_lane_s8",
     "arguments": [
-      "int16x4_t a",
-      "const int n"
+      "int8_t a",
+      "int8x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -96299,27 +299418,31 @@
     ],
     "instructions": [
       [
-        "SSHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_s32",
+    "name": "vset_lane_u16",
     "arguments": [
-      "int32x2_t a",
-      "const int n"
+      "uint16_t a",
+      "uint16x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -96329,27 +299452,31 @@
     ],
     "instructions": [
       [
-        "SSHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_s64",
+    "name": "vset_lane_u32",
     "arguments": [
-      "int64x1_t a",
-      "const int n"
+      "uint32_t a",
+      "uint32x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -96359,27 +299486,31 @@
     ],
     "instructions": [
       [
-        "SSHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_s8",
+    "name": "vset_lane_u64",
     "arguments": [
-      "int8x8_t a",
-      "const int n"
+      "uint64_t a",
+      "uint64x1_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "v": {
+        "register": "Vd.1D"
       }
     },
     "Architectures": [
@@ -96389,27 +299520,31 @@
     ],
     "instructions": [
       [
-        "SSHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_u16",
+    "name": "vset_lane_u8",
     "arguments": [
-      "uint16x4_t a",
-      "const int n"
+      "uint8_t a",
+      "uint8x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -96419,27 +299554,31 @@
     ],
     "instructions": [
       [
-        "USHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_u32",
+    "name": "vsetq_lane_f16",
     "arguments": [
-      "uint32x2_t a",
-      "const int n"
+      "float16_t a",
+      "float16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "VnH"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
@@ -96449,27 +299588,31 @@
     ],
     "instructions": [
       [
-        "USHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_u64",
+    "name": "vsetq_lane_f32",
     "arguments": [
-      "uint64x1_t a",
-      "const int n"
+      "float32_t a",
+      "float32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -96479,305 +299622,334 @@
     ],
     "instructions": [
       [
-        "USHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshr_n_u8",
+    "name": "vsetq_lane_f64",
     "arguments": [
-      "uint8x8_t a",
-      "const int n"
+      "float64_t a",
+      "float64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrd_n_s64",
+    "name": "vsetq_lane_p16",
     "arguments": [
-      "int64_t a",
-      "const int n"
+      "poly16_t a",
+      "poly16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "v": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrd_n_u64",
+    "name": "vsetq_lane_p64",
     "arguments": [
-      "uint64_t a",
-      "const int n"
+      "poly64_t a",
+      "poly64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHR"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_high_n_s16",
+    "name": "vsetq_lane_p8",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a",
-      "const int n"
+      "poly8_t a",
+      "poly8x16_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
       },
-      "r": {
-        "register": "Vd.8B"
+      "v": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN2"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_high_n_s32",
+    "name": "vsetq_lane_s16",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a",
-      "const int n"
+      "int16_t a",
+      "int16x8_t v",
+      "const int lane"
     ],
     "return_type": {
       "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "r": {
-        "register": "Vd.4H"
+      "v": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN2"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_high_n_s64",
+    "name": "vsetq_lane_s32",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a",
-      "const int n"
+      "int32_t a",
+      "int32x4_t v",
+      "const int lane"
     ],
     "return_type": {
       "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "r": {
-        "register": "Vd.2S"
+      "v": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN2"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_high_n_u16",
+    "name": "vsetq_lane_s64",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "const int n"
+      "int64_t a",
+      "int64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "r": {
-        "register": "Vd.8B"
+      "v": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN2"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_high_n_u32",
+    "name": "vsetq_lane_s8",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "const int n"
+      "int8_t a",
+      "int8x16_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
       },
-      "r": {
-        "register": "Vd.4H"
+      "v": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN2"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_high_n_u64",
+    "name": "vsetq_lane_u16",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "const int n"
+      "uint16_t a",
+      "uint16x8_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "r": {
-        "register": "Vd.2S"
+      "v": {
+        "register": "Vd.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN2"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_n_s16",
+    "name": "vsetq_lane_u32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "uint32_t a",
+      "uint32x4_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "v": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
@@ -96787,27 +299959,31 @@
     ],
     "instructions": [
       [
-        "SHRN"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_n_s32",
+    "name": "vsetq_lane_u64",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "uint64_t a",
+      "uint64x2_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "v": {
+        "register": "Vd.2D"
       }
     },
     "Architectures": [
@@ -96817,27 +299993,31 @@
     ],
     "instructions": [
       [
-        "SHRN"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_n_s64",
+    "name": "vsetq_lane_u8",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "uint8_t a",
+      "uint8x16_t v",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Rn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "v": {
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -96847,447 +300027,439 @@
     ],
     "instructions": [
       [
-        "SHRN"
+        "MOV"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_n_u16",
+    "name": "vsha1cq_u32",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "uint32x4_t hash_abcd",
+      "uint32_t hash_e",
+      "uint32x4_t wk"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "hash_abcd": {
+        "register": "Qd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "hash_e": {
+        "register": "Sn"
+      },
+      "wk": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN"
+        "SHA1C"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_n_u32",
+    "name": "vsha1h_u32",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "uint32_t hash_e"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "hash_e": {
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN"
+        "SHA1H"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrn_n_u64",
+    "name": "vsha1mq_u32",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "uint32x4_t hash_abcd",
+      "uint32_t hash_e",
+      "uint32x4_t wk"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "hash_abcd": {
+        "register": "Qd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "hash_e": {
+        "register": "Sn"
+      },
+      "wk": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SHRN"
+        "SHA1M"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_s16",
+    "name": "vsha1pq_u32",
     "arguments": [
-      "int16x8_t a",
-      "const int n"
+      "uint32x4_t hash_abcd",
+      "uint32_t hash_e",
+      "uint32x4_t wk"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "hash_abcd": {
+        "register": "Qd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "hash_e": {
+        "register": "Sn"
+      },
+      "wk": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHR"
+        "SHA1P"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_s32",
+    "name": "vsha1su0q_u32",
     "arguments": [
-      "int32x4_t a",
-      "const int n"
+      "uint32x4_t w0_3",
+      "uint32x4_t w4_7",
+      "uint32x4_t w8_11"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "w0_3": {
+        "register": "Vd.4S"
+      },
+      "w4_7": {
         "register": "Vn.4S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "w8_11": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHR"
+        "SHA1SU0"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_s64",
+    "name": "vsha1su1q_u32",
     "arguments": [
-      "int64x2_t a",
-      "const int n"
+      "uint32x4_t tw0_3",
+      "uint32x4_t w12_15"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "tw0_3": {
+        "register": "Vd.4S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "w12_15": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHR"
+        "SHA1SU1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_s8",
+    "name": "vsha256h2q_u32",
     "arguments": [
-      "int8x16_t a",
-      "const int n"
+      "uint32x4_t hash_efgh",
+      "uint32x4_t hash_abcd",
+      "uint32x4_t wk"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "hash_abcd": {
+        "register": "Qn"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "hash_efgh": {
+        "register": "Qd"
+      },
+      "wk": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSHR"
+        "SHA256H2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_u16",
+    "name": "vsha256hq_u32",
     "arguments": [
-      "uint16x8_t a",
-      "const int n"
+      "uint32x4_t hash_abcd",
+      "uint32x4_t hash_efgh",
+      "uint32x4_t wk"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "hash_abcd": {
+        "register": "Qd"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 16
+      "hash_efgh": {
+        "register": "Qn"
+      },
+      "wk": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHR"
+        "SHA256H"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_u32",
+    "name": "vsha256su0q_u32",
     "arguments": [
-      "uint32x4_t a",
-      "const int n"
+      "uint32x4_t w0_3",
+      "uint32x4_t w4_7"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "w0_3": {
+        "register": "Vd.4S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 32
+      "w4_7": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHR"
+        "SHA256SU0"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_u64",
+    "name": "vsha256su1q_u32",
     "arguments": [
-      "uint64x2_t a",
-      "const int n"
+      "uint32x4_t tw0_3",
+      "uint32x4_t w8_11",
+      "uint32x4_t w12_15"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "tw0_3": {
+        "register": "Vd.4S"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 64
+      "w12_15": {
+        "register": "Vm.4S"
+      },
+      "w8_11": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHR"
+        "SHA256SU1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vshrq_n_u8",
+    "name": "vsha512h2q_u64",
     "arguments": [
-      "uint8x16_t a",
-      "const int n"
+      "uint64x2_t sum_ab",
+      "uint64x2_t hash_c_",
+      "uint64x2_t hash_ab"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "hash_ab": {
+        "register": "Vm.2D"
       },
-      "n": {
-        "minimum": 1,
-        "maximum": 8
+      "hash_c_": {
+        "register": "Qn"
+      },
+      "sum_ab": {
+        "register": "Qd"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USHR"
+        "SHA512H2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_p16",
+    "name": "vsha512hq_u64",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b",
-      "const int n"
+      "uint64x2_t hash_ed",
+      "uint64x2_t hash_gf",
+      "uint64x2_t kwh_kwh2"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4H"
+      "hash_ed": {
+        "register": "Qd"
       },
-      "b": {
-        "register": "Vn.4H"
+      "hash_gf": {
+        "register": "Qn"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+      "kwh_kwh2": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SHA512H"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_p64",
+    "name": "vsha512su0q_u64",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b",
-      "const int n"
+      "uint64x2_t w0_1",
+      "uint64x2_t w2_"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
+      "w0_1": {
+        "register": "Vd.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+      "w2_": {
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SHA512SU0"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_p8",
+    "name": "vsha512su1q_u64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b",
-      "const int n"
+      "uint64x2_t s01_s02",
+      "uint64x2_t w14_15",
+      "uint64x2_t w9_10"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.8B"
+      "s01_s02": {
+        "register": "Vd.2D"
       },
-      "b": {
-        "register": "Vn.8B"
+      "w14_15": {
+        "register": "Vn.2D"
       },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+      "w9_10": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SHA512SU1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_s16",
+    "name": "vshl_n_s16",
     "arguments": [
       "int16x4_t a",
-      "int16x4_t b",
       "const int n"
     ],
     "return_type": {
@@ -97295,9 +300467,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
       },
       "n": {
@@ -97312,16 +300481,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_s32",
+    "name": "vshl_n_s32",
     "arguments": [
       "int32x2_t a",
-      "int32x2_t b",
       "const int n"
     ],
     "return_type": {
@@ -97329,9 +300497,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
       },
       "n": {
@@ -97346,16 +300511,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_s64",
+    "name": "vshl_n_s64",
     "arguments": [
       "int64x1_t a",
-      "int64x1_t b",
       "const int n"
     ],
     "return_type": {
@@ -97363,9 +300527,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
         "register": "Dn"
       },
       "n": {
@@ -97380,16 +300541,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_s8",
+    "name": "vshl_n_s8",
     "arguments": [
       "int8x8_t a",
-      "int8x8_t b",
       "const int n"
     ],
     "return_type": {
@@ -97397,9 +300557,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
         "register": "Vn.8B"
       },
       "n": {
@@ -97414,16 +300571,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_u16",
+    "name": "vshl_n_u16",
     "arguments": [
       "uint16x4_t a",
-      "uint16x4_t b",
       "const int n"
     ],
     "return_type": {
@@ -97431,9 +300587,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
       },
       "n": {
@@ -97448,16 +300601,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_u32",
+    "name": "vshl_n_u32",
     "arguments": [
       "uint32x2_t a",
-      "uint32x2_t b",
       "const int n"
     ],
     "return_type": {
@@ -97465,9 +300617,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
       },
       "n": {
@@ -97482,16 +300631,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_u64",
+    "name": "vshl_n_u64",
     "arguments": [
       "uint64x1_t a",
-      "uint64x1_t b",
       "const int n"
     ],
     "return_type": {
@@ -97499,9 +300647,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
         "register": "Dn"
       },
       "n": {
@@ -97516,16 +300661,15 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsli_n_u8",
+    "name": "vshl_n_u8",
     "arguments": [
       "uint8x8_t a",
-      "uint8x8_t b",
       "const int n"
     ],
     "return_type": {
@@ -97533,9 +300677,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
         "register": "Vn.8B"
       },
       "n": {
@@ -97550,95 +300691,84 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vslid_n_s64",
+    "name": "vshl_s16",
     "arguments": [
-      "int64_t a",
-      "int64_t b",
-      "const int n"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vslid_n_u64",
+    "name": "vshl_s32",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b",
-      "const int n"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Dn"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_p16",
+    "name": "vshl_s64",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b",
-      "const int n"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -97648,64 +300778,55 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_p64",
+    "name": "vshl_s8",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b",
-      "const int n"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_p8",
+    "name": "vshl_u16",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b",
-      "const int n"
+      "uint16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.16B"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 7
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -97715,31 +300836,26 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_s16",
+    "name": "vshl_u32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
-      "const int n"
+      "uint32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.8H"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 15
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -97749,31 +300865,26 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_s32",
+    "name": "vshl_u64",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
-      "const int n"
+      "uint64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -97783,31 +300894,26 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_s64",
+    "name": "vshl_u8",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b",
-      "const int n"
+      "uint8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -97817,282 +300923,221 @@
     ],
     "instructions": [
       [
-        "SLI"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_s8",
+    "name": "vshld_n_s64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
+      "int64_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
+        "register": "Dn"
       },
       "n": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 63
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_u16",
+    "name": "vshld_n_u64",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
+      "uint64_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
+        "register": "Dn"
       },
       "n": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 63
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_u32",
+    "name": "vshld_s64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "const int n"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.4S"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 31
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_u64",
+    "name": "vshld_u64",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
-      "const int n"
+      "uint64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vn.2D"
-      },
-      "n": {
-        "minimum": 0,
-        "maximum": 63
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SLI"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsliq_n_u8",
+    "name": "vshll_high_n_s16",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
+      "int16x8_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "n": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 16
       }
     },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "SLI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vsm3partw1q_u32",
-    "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
-    ],
-    "return_type": {
-      "value": "uint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vd.4S"
-      },
-      "b": {},
-      "c": {}
-    },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "SM3PARTW1"
+        "SSHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm3partw2q_u32",
+    "name": "vshll_high_n_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
-      "b": {},
-      "c": {}
+      "n": {
+        "minimum": 0,
+        "maximum": 32
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "SM3PARTW2"
+        "SSHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm3ss1q_u32",
+    "name": "vshll_high_n_s8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c"
+      "int8x16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.16B"
       },
-      "b": {},
-      "c": {}
+      "n": {
+        "minimum": 0,
+        "maximum": 8
+      }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
       [
-        "SM3SS1"
+        "SSHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm3tt1aq_u32",
+    "name": "vshll_high_n_u16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c",
-      "const int imm2"
+      "uint16x8_t a",
+      "const int n"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.8H"
       },
-      "b": {},
-      "c": {},
-      "imm2": {
+      "n": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -98100,31 +301145,27 @@
     ],
     "instructions": [
       [
-        "SM3TT1A"
+        "USHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm3tt1bq_u32",
+    "name": "vshll_high_n_u32",
     "arguments": [
       "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c",
-      "const int imm2"
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4S"
       },
-      "b": {},
-      "c": {},
-      "imm2": {
+      "n": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -98132,31 +301173,27 @@
     ],
     "instructions": [
       [
-        "SM3TT1B"
+        "USHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm3tt2aq_u32",
+    "name": "vshll_high_n_u8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c",
-      "const int imm2"
+      "uint8x16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.16B"
       },
-      "b": {},
-      "c": {},
-      "imm2": {
+      "n": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -98164,584 +301201,667 @@
     ],
     "instructions": [
       [
-        "SM3TT2A"
+        "USHLL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm3tt2bq_u32",
+    "name": "vshll_n_s16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
-      "uint32x4_t c",
-      "const int imm2"
+      "int16x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.4H"
       },
-      "b": {},
-      "c": {},
-      "imm2": {
+      "n": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SM3TT2B"
+        "SSHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm4ekeyq_u32",
+    "name": "vshll_n_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int32x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
-      "b": {}
+      "n": {
+        "minimum": 0,
+        "maximum": 32
+      }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SM4EKEY"
+        "SSHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsm4eq_u32",
+    "name": "vshll_n_s8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int8x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.8B"
       },
-      "b": {}
+      "n": {
+        "minimum": 0,
+        "maximum": 8
+      }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SM4E"
+        "SSHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqadd_u16",
+    "name": "vshll_n_u16",
     "arguments": [
       "uint16x4_t a",
-      "int16x4_t b"
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "USHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqadd_u32",
+    "name": "vshll_n_u32",
     "arguments": [
       "uint32x2_t a",
-      "int32x2_t b"
+      "const int n"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 32
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "USHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqadd_u64",
+    "name": "vshll_n_u8",
     "arguments": [
-      "uint64x1_t a",
-      "int64x1_t b"
+      "uint8x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.8B"
       },
-      "b": {
-        "register": "Dn"
+      "n": {
+        "minimum": 0,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "USHLL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqadd_u8",
+    "name": "vshlq_n_s16",
     "arguments": [
-      "uint8x8_t a",
-      "int8x8_t b"
+      "int16x8_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.8H"
       },
-      "b": {
-        "register": "Vn.8B"
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddb_u8",
+    "name": "vshlq_n_s32",
     "arguments": [
-      "uint8_t a",
-      "int8_t b"
+      "int32x4_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint8_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bd"
+        "register": "Vn.4S"
       },
-      "b": {
-        "register": "Bn"
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddd_u64",
+    "name": "vshlq_n_s64",
     "arguments": [
-      "uint64_t a",
-      "int64_t b"
+      "int64x2_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.2D"
       },
-      "b": {
-        "register": "Dn"
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddh_u16",
+    "name": "vshlq_n_s8",
     "arguments": [
-      "uint16_t a",
-      "int16_t b"
+      "int8x16_t a",
+      "const int n"
     ],
     "return_type": {
-      "value": "uint16_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Hn"
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddq_u16",
+    "name": "vshlq_n_u16",
     "arguments": [
       "uint16x8_t a",
-      "int16x8_t b"
+      "const int n"
     ],
     "return_type": {
       "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddq_u32",
+    "name": "vshlq_n_u32",
     "arguments": [
       "uint32x4_t a",
-      "int32x4_t b"
+      "const int n"
     ],
     "return_type": {
       "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddq_u64",
+    "name": "vshlq_n_u64",
     "arguments": [
       "uint64x2_t a",
-      "int64x2_t b"
+      "const int n"
     ],
     "return_type": {
       "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqaddq_u8",
+    "name": "vshlq_n_u8",
     "arguments": [
       "uint8x16_t a",
-      "int8x16_t b"
+      "const int n"
     ],
     "return_type": {
       "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
         "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqadds_u32",
+    "name": "vshlq_s16",
     "arguments": [
-      "uint32_t a",
-      "int32_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint32_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Sn"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USQADD"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrt_f16",
+    "name": "vshlq_s32",
     "arguments": [
-      "float16x4_t a"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrt_f32",
+    "name": "vshlq_s64",
     "arguments": [
-      "float32x2_t a"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrt_f64",
+    "name": "vshlq_s8",
     "arguments": [
-      "float64x1_t a"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "SSHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrth_f16",
+    "name": "vshlq_u16",
     "arguments": [
-      "float16_t a"
+      "uint16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hn"
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrtq_f16",
+    "name": "vshlq_u32",
     "arguments": [
-      "float16x8_t a"
+      "uint32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrtq_f32",
+    "name": "vshlq_u64",
     "arguments": [
-      "float32x4_t a"
+      "uint64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsqrtq_f64",
+    "name": "vshlq_u8",
     "arguments": [
-      "float64x2_t a"
+      "uint8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSQRT"
+        "USHL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_s16",
+    "name": "vshr_n_s16",
     "arguments": [
       "int16x4_t a",
-      "int16x4_t b",
       "const int n"
     ],
     "return_type": {
@@ -98749,9 +301869,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
       },
       "n": {
@@ -98766,16 +301883,15 @@
     ],
     "instructions": [
       [
-        "SSRA"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_s32",
+    "name": "vshr_n_s32",
     "arguments": [
       "int32x2_t a",
-      "int32x2_t b",
       "const int n"
     ],
     "return_type": {
@@ -98783,9 +301899,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
       },
       "n": {
@@ -98800,16 +301913,15 @@
     ],
     "instructions": [
       [
-        "SSRA"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_s64",
+    "name": "vshr_n_s64",
     "arguments": [
       "int64x1_t a",
-      "int64x1_t b",
       "const int n"
     ],
     "return_type": {
@@ -98817,9 +301929,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
         "register": "Dn"
       },
       "n": {
@@ -98834,16 +301943,15 @@
     ],
     "instructions": [
       [
-        "SSRA"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_s8",
+    "name": "vshr_n_s8",
     "arguments": [
       "int8x8_t a",
-      "int8x8_t b",
       "const int n"
     ],
     "return_type": {
@@ -98851,9 +301959,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
         "register": "Vn.8B"
       },
       "n": {
@@ -98868,16 +301973,15 @@
     ],
     "instructions": [
       [
-        "SSRA"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_u16",
+    "name": "vshr_n_u16",
     "arguments": [
       "uint16x4_t a",
-      "uint16x4_t b",
       "const int n"
     ],
     "return_type": {
@@ -98885,9 +301989,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
         "register": "Vn.4H"
       },
       "n": {
@@ -98902,16 +302003,15 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_u32",
+    "name": "vshr_n_u32",
     "arguments": [
       "uint32x2_t a",
-      "uint32x2_t b",
       "const int n"
     ],
     "return_type": {
@@ -98919,9 +302019,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
         "register": "Vn.2S"
       },
       "n": {
@@ -98936,16 +302033,15 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_u64",
+    "name": "vshr_n_u64",
     "arguments": [
       "uint64x1_t a",
-      "uint64x1_t b",
       "const int n"
     ],
     "return_type": {
@@ -98953,9 +302049,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
         "register": "Dn"
       },
       "n": {
@@ -98970,16 +302063,15 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsra_n_u8",
+    "name": "vshr_n_u8",
     "arguments": [
       "uint8x8_t a",
-      "uint8x8_t b",
       "const int n"
     ],
     "return_type": {
@@ -98987,9 +302079,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
         "register": "Vn.8B"
       },
       "n": {
@@ -99004,16 +302093,15 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsrad_n_s64",
+    "name": "vshrd_n_s64",
     "arguments": [
       "int64_t a",
-      "int64_t b",
       "const int n"
     ],
     "return_type": {
@@ -99021,9 +302109,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
         "register": "Dn"
       },
       "n": {
@@ -99036,16 +302121,15 @@
     ],
     "instructions": [
       [
-        "SSRA"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsrad_n_u64",
+    "name": "vshrd_n_u64",
     "arguments": [
       "uint64_t a",
-      "uint64_t b",
       "const int n"
     ],
     "return_type": {
@@ -99053,9 +302137,6 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
         "register": "Dn"
       },
       "n": {
@@ -99068,152 +302149,144 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_s16",
+    "name": "vshrn_high_n_s16",
     "arguments": [
+      "int8x8_t r",
       "int16x8_t a",
-      "int16x8_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
         "register": "Vn.8H"
       },
       "n": {
         "minimum": 1,
-        "maximum": 16
+        "maximum": 8
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSRA"
+        "SHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_s32",
+    "name": "vshrn_high_n_s32",
     "arguments": [
+      "int16x4_t r",
       "int32x4_t a",
-      "int32x4_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
         "register": "Vn.4S"
       },
       "n": {
         "minimum": 1,
-        "maximum": 32
+        "maximum": 16
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSRA"
+        "SHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_s64",
+    "name": "vshrn_high_n_s64",
     "arguments": [
+      "int32x2_t r",
       "int64x2_t a",
-      "int64x2_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
         "register": "Vn.2D"
       },
       "n": {
         "minimum": 1,
-        "maximum": 64
+        "maximum": 32
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSRA"
+        "SHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_s8",
+    "name": "vshrn_high_n_u16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
+      "uint8x8_t r",
+      "uint16x8_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "n": {
         "minimum": 1,
         "maximum": 8
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSRA"
+        "SHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_u16",
+    "name": "vshrn_high_n_u32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
+      "uint16x4_t r",
+      "uint32x4_t a",
       "const int n"
     ],
     "return_type": {
@@ -99221,33 +302294,31 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
-      },
-      "b": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
       "n": {
         "minimum": 1,
         "maximum": 16
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USRA"
+        "SHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_u32",
+    "name": "vshrn_high_n_u64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
+      "uint32x2_t r",
+      "uint64x2_t a",
       "const int n"
     ],
     "return_type": {
@@ -99255,48 +302326,42 @@
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
-      },
-      "b": {
-        "register": "Vn.4S"
+        "register": "Vn.2D"
       },
       "n": {
         "minimum": 1,
         "maximum": 32
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USRA"
+        "SHRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_u64",
+    "name": "vshrn_n_s16",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
+      "int16x8_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
-      },
-      "b": {
-        "register": "Vn.2D"
+        "register": "Vn.8H"
       },
       "n": {
         "minimum": 1,
-        "maximum": 64
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -99306,31 +302371,27 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "SHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsraq_n_u8",
+    "name": "vshrn_n_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
+      "int32x4_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
-      },
-      "b": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "n": {
         "minimum": 1,
-        "maximum": 8
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -99340,31 +302401,27 @@
     ],
     "instructions": [
       [
-        "USRA"
+        "SHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_p16",
+    "name": "vshrn_n_s64",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b",
+      "int64x2_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+        "register": "Vn.2D"
       },
       "n": {
         "minimum": 1,
-        "maximum": 16
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -99374,64 +302431,57 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_p64",
+    "name": "vshrn_n_u16",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b",
+      "uint16x8_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "poly64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
+        "register": "Vn.8H"
       },
       "n": {
         "minimum": 1,
-        "maximum": 64
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRI"
+        "SHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_p8",
+    "name": "vshrn_n_u32",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b",
+      "uint32x4_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
       "n": {
         "minimum": 1,
-        "maximum": 8
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -99441,31 +302491,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_s16",
+    "name": "vshrn_n_u64",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b",
+      "uint64x2_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+        "register": "Vn.2D"
       },
       "n": {
         "minimum": 1,
-        "maximum": 16
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -99475,31 +302521,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SHRN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_s32",
+    "name": "vshrq_n_s16",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b",
+      "int16x8_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+        "register": "Vn.8H"
       },
       "n": {
         "minimum": 1,
-        "maximum": 32
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -99509,31 +302551,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_s64",
+    "name": "vshrq_n_s32",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b",
+      "int32x4_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
+        "register": "Vn.4S"
       },
       "n": {
         "minimum": 1,
-        "maximum": 64
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -99543,31 +302581,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_s8",
+    "name": "vshrq_n_s64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b",
+      "int64x2_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
       },
       "n": {
         "minimum": 1,
-        "maximum": 8
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -99577,31 +302611,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_u16",
+    "name": "vshrq_n_s8",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b",
+      "int8x16_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
-      },
-      "b": {
-        "register": "Vn.4H"
+        "register": "Vn.16B"
       },
       "n": {
         "minimum": 1,
-        "maximum": 16
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -99611,31 +302641,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SSHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_u32",
+    "name": "vshrq_n_u16",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b",
+      "uint16x8_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
-      },
-      "b": {
-        "register": "Vn.2S"
+        "register": "Vn.8H"
       },
       "n": {
         "minimum": 1,
-        "maximum": 32
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -99645,31 +302671,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_u64",
+    "name": "vshrq_n_u32",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b",
+      "uint32x4_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
+        "register": "Vn.4S"
       },
       "n": {
         "minimum": 1,
-        "maximum": 64
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -99679,31 +302701,27 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsri_n_u8",
+    "name": "vshrq_n_u64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
+      "uint64x2_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
-      },
-      "b": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
       },
       "n": {
         "minimum": 1,
-        "maximum": 8
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -99713,162 +302731,162 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsrid_n_s64",
+    "name": "vshrq_n_u8",
     "arguments": [
-      "int64_t a",
-      "int64_t b",
+      "uint8x16_t a",
       "const int n"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
-      },
-      "b": {
-        "register": "Dn"
+        "register": "Vn.16B"
       },
       "n": {
         "minimum": 1,
-        "maximum": 64
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRI"
+        "USHR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsrid_n_u64",
+    "name": "vsli_n_p16",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b",
+      "poly16x4_t a",
+      "poly16x4_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vd.4H"
       },
       "b": {
-        "register": "Dn"
+        "register": "Vn.4H"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 64
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_p16",
+    "name": "vsli_n_p64",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b",
+      "poly64x1_t a",
+      "poly64x1_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vn.8H"
+        "register": "Dn"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 16
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_p64",
+    "name": "vsli_n_p8",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b",
+      "poly8x8_t a",
+      "poly8x8_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8B"
       },
       "b": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 64
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_p8",
+    "name": "vsli_n_s16",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b",
+      "int16x4_t a",
+      "int16x4_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       },
       "b": {
-        "register": "Vn.16B"
+        "register": "Vn.4H"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 8
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
@@ -99878,31 +302896,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_s16",
+    "name": "vsli_n_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b",
+      "int32x2_t a",
+      "int32x2_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       },
       "b": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 16
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
@@ -99912,31 +302930,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_s32",
+    "name": "vsli_n_s64",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b",
+      "int64x1_t a",
+      "int64x1_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vn.4S"
+        "register": "Dn"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 32
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
@@ -99946,31 +302964,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_s64",
+    "name": "vsli_n_s8",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b",
+      "int8x8_t a",
+      "int8x8_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8B"
       },
       "b": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 64
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
@@ -99980,31 +302998,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_s8",
+    "name": "vsli_n_u16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b",
+      "uint16x4_t a",
+      "uint16x4_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vd.4H"
       },
       "b": {
-        "register": "Vn.16B"
+        "register": "Vn.4H"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 8
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
@@ -100014,31 +303032,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_u16",
+    "name": "vsli_n_u32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b",
+      "uint32x2_t a",
+      "uint32x2_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vd.2S"
       },
       "b": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 16
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
@@ -100048,31 +303066,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_u32",
+    "name": "vsli_n_u64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b",
+      "uint64x1_t a",
+      "uint64x1_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vn.4S"
+        "register": "Dn"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 32
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
@@ -100082,31 +303100,31 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_u64",
+    "name": "vsli_n_u8",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
+      "uint8x8_t a",
+      "uint8x8_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vd.8B"
       },
       "b": {
-        "register": "Vn.2D"
+        "register": "Vn.8B"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 64
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
@@ -100116,89 +303134,95 @@
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsriq_n_u8",
+    "name": "vslid_n_s64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
+      "int64_t a",
+      "int64_t b",
       "const int n"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Dd"
       },
       "b": {
-        "register": "Vn.16B"
+        "register": "Dn"
       },
       "n": {
-        "minimum": 1,
-        "maximum": 8
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SRI"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f16",
+    "name": "vslid_n_u64",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4_t val"
+      "uint64_t a",
+      "uint64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt.4H"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f16_x2",
+    "name": "vsliq_n_p16",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x2_t val"
+      "poly16x8_t a",
+      "poly16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
@@ -100208,55 +303232,64 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f16_x3",
+    "name": "vsliq_n_p64",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x3_t val"
+      "poly64x2_t a",
+      "poly64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f16_x4",
+    "name": "vsliq_n_p8",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x4_t val"
+      "poly8x16_t a",
+      "poly8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
@@ -100266,26 +303299,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f32",
+    "name": "vsliq_n_s16",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2_t val"
+      "int16x8_t a",
+      "int16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt.2S"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
@@ -100295,26 +303333,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f32_x2",
+    "name": "vsliq_n_s32",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x2_t val"
+      "int32x4_t a",
+      "int32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt2.2S"
+      "b": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
@@ -100324,26 +303367,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f32_x3",
+    "name": "vsliq_n_s64",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x3_t val"
+      "int64x2_t a",
+      "int64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
@@ -100353,26 +303401,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f32_x4",
+    "name": "vsliq_n_s8",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x4_t val"
+      "int8x16_t a",
+      "int8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
@@ -100382,207 +303435,228 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f64",
+    "name": "vsliq_n_u16",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1_t val"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt.1D"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 15
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f64_x2",
+    "name": "vsliq_n_u32",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x2_t val"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "b": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 31
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f64_x3",
+    "name": "vsliq_n_u64",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x3_t val"
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 63
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_f64_x4",
+    "name": "vsliq_n_u8",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x4_t val"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 0,
+        "maximum": 7
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SLI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_f16",
+    "name": "vsm3partw1q_u32",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vd.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.4H"
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3PARTW1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_f32",
+    "name": "vsm3partw2q_u32",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vd.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.2S"
+      "c": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3PARTW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_f64",
+    "name": "vsm3ss1q_u32",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "a": {
+        "register": "Vn.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vm.4S"
       },
-      "val": {
-        "register": "Vt.1D"
+      "c": {
+        "register": "Va.4S"
       }
     },
     "Architectures": [
@@ -100590,801 +303664,715 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3SS1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_p16",
+    "name": "vsm3tt1aq_u32",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c",
+      "const int imm2"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vd.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.4H"
+      "c": {
+        "register": "Vm.4S"
+      },
+      "imm2": {
+        "minimum": 0,
+        "maximum": 3
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3TT1A"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_p64",
+    "name": "vsm3tt1bq_u32",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c",
+      "const int imm2"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
+      "a": {
+        "register": "Vd.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.1D"
+      "c": {
+        "register": "Vm.4S"
+      },
+      "imm2": {
+        "minimum": 0,
+        "maximum": 3
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3TT1B"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_p8",
+    "name": "vsm3tt2aq_u32",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c",
+      "const int imm2"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
+      "a": {
+        "register": "Vd.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.8B"
+      "c": {
+        "register": "Vm.4S"
+      },
+      "imm2": {
+        "minimum": 0,
+        "maximum": 3
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3TT2A"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_s16",
+    "name": "vsm3tt2bq_u32",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "uint32x4_t c",
+      "const int imm2"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vd.4S"
       },
-      "ptr": {
-        "register": "Xn"
+      "b": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.4H"
+      "c": {
+        "register": "Vm.4S"
+      },
+      "imm2": {
+        "minimum": 0,
+        "maximum": 3
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM3TT2B"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_s32",
+    "name": "vsm4ekeyq_u32",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vn.4S"
       },
-      "val": {
-        "register": "Vt.2S"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM4EKEY"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_s64",
+    "name": "vsm4eq_u32",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1_t val",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt.1D"
+      "b": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SM4E"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_s8",
+    "name": "vsqadd_u16",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8_t val",
-      "const int lane"
+      "uint16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4H"
       },
-      "val": {
-        "register": "Vt.8B"
+      "b": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_u16",
+    "name": "vsqadd_u32",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4_t val",
-      "const int lane"
+      "uint32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2S"
       },
-      "val": {
-        "register": "Vt.4H"
+      "b": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_u32",
+    "name": "vsqadd_u64",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2_t val",
-      "const int lane"
+      "uint64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt.2S"
+      "b": {
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_u64",
+    "name": "vsqadd_u8",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1_t val",
-      "const int lane"
+      "uint8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8B"
       },
-      "val": {
-        "register": "Vt.1D"
+      "b": {
+        "register": "Vn.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_lane_u8",
+    "name": "vsqaddb_u8",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8_t val",
-      "const int lane"
+      "uint8_t a",
+      "int8_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8_t"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Bd"
       },
-      "val": {
-        "register": "Vt.8B"
+      "b": {
+        "register": "Bn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p16",
+    "name": "vsqaddd_u64",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4_t val"
+      "uint64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt.4H"
+      "b": {
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p16_x2",
+    "name": "vsqaddh_u16",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x2_t val"
+      "uint16_t a",
+      "int16_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Hd"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "b": {
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p16_x3",
+    "name": "vsqaddq_u16",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x3_t val"
+      "uint16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "b": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p16_x4",
+    "name": "vsqaddq_u32",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x4_t val"
+      "uint32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "b": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p64",
+    "name": "vsqaddq_u64",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1_t val"
+      "uint64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt.1D"
+      "b": {
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p64_x2",
+    "name": "vsqaddq_u8",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x2_t val"
+      "uint8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "b": {
+        "register": "Vn.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p64_x3",
+    "name": "vsqadds_u32",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x3_t val"
+      "uint32_t a",
+      "int32_t b"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Sd"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "b": {
+        "register": "Sn"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USQADD"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p64_x4",
+    "name": "vsqrt_f16",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x4_t val"
+      "float16x4_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt4.1D"
+      "a": {
+        "register": "Vn.4H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p8",
+    "name": "vsqrt_f32",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8_t val"
+      "float32x2_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt.8B"
+      "a": {
+        "register": "Vn.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p8_x2",
+    "name": "vsqrt_f64",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x2_t val"
+      "float64x1_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt2.8B"
+      "a": {
+        "register": "Dn"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p8_x3",
+    "name": "vsqrth_f16",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x3_t val"
+      "float16_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt3.8B"
+      "a": {
+        "register": "Hn"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_p8_x4",
+    "name": "vsqrtq_f16",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x4_t val"
+      "float16x8_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt4.8B"
+      "a": {
+        "register": "Vn.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s16",
+    "name": "vsqrtq_f32",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4_t val"
+      "float32x4_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt.4H"
+      "a": {
+        "register": "Vn.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s16_x2",
+    "name": "vsqrtq_f64",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x2_t val"
+      "float64x2_t a"
     ],
     "return_type": {
-      "value": "void"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
-      },
-      "val": {
-        "register": "Vt2.4H"
+      "a": {
+        "register": "Vn.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "FSQRT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s16_x3",
+    "name": "vsra_n_s16",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x3_t val"
+      "int16x4_t a",
+      "int16x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4H"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -101394,26 +304382,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s16_x4",
+    "name": "vsra_n_s32",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x4_t val"
+      "int32x2_t a",
+      "int32x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2S"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -101423,26 +304416,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s32",
+    "name": "vsra_n_s64",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2_t val"
+      "int64x1_t a",
+      "int64x1_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt.2S"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -101452,26 +304450,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s32_x2",
+    "name": "vsra_n_s8",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x2_t val"
+      "int8x8_t a",
+      "int8x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8B"
       },
-      "val": {
-        "register": "Vt2.2S"
+      "b": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -101481,26 +304484,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s32_x3",
+    "name": "vsra_n_u16",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x3_t val"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4H"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -101510,26 +304518,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s32_x4",
+    "name": "vsra_n_u32",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x4_t val"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2S"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -101539,26 +304552,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s64",
+    "name": "vsra_n_u64",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1_t val"
+      "uint64x1_t a",
+      "uint64x1_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt.1D"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -101568,26 +304586,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s64_x2",
+    "name": "vsra_n_u8",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x2_t val"
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8B"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "b": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -101597,84 +304620,95 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s64_x3",
+    "name": "vsrad_n_s64",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x3_t val"
+      "int64_t a",
+      "int64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s64_x4",
+    "name": "vsrad_n_u64",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x4_t val"
+      "uint64_t a",
+      "uint64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s8",
+    "name": "vsraq_n_s16",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8_t val"
+      "int16x8_t a",
+      "int16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt.8B"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -101684,26 +304718,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s8_x2",
+    "name": "vsraq_n_s32",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x2_t val"
+      "int32x4_t a",
+      "int32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt2.8B"
+      "b": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -101713,26 +304752,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s8_x3",
+    "name": "vsraq_n_s64",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x3_t val"
+      "int64x2_t a",
+      "int64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.8B"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -101742,26 +304786,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_s8_x4",
+    "name": "vsraq_n_s8",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x4_t val"
+      "int8x16_t a",
+      "int8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -101771,26 +304820,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SSRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u16",
+    "name": "vsraq_n_u16",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4_t val"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt.4H"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -101800,26 +304854,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u16_x2",
+    "name": "vsraq_n_u32",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4x2_t val"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "b": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -101829,26 +304888,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u16_x3",
+    "name": "vsraq_n_u64",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4x3_t val"
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -101858,26 +304922,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u16_x4",
+    "name": "vsraq_n_u8",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4x4_t val"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -101887,26 +304956,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "USRA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u32",
+    "name": "vsri_n_p16",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2_t val"
+      "poly16x4_t a",
+      "poly16x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4H"
       },
-      "val": {
-        "register": "Vt.2S"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -101916,55 +304990,64 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u32_x2",
+    "name": "vsri_n_p64",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x2_t val"
+      "poly64x1_t a",
+      "poly64x1_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly64x1_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt2.2S"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u32_x3",
+    "name": "vsri_n_p8",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x3_t val"
+      "poly8x8_t a",
+      "poly8x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8B"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "b": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -101974,26 +305057,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u32_x4",
+    "name": "vsri_n_s16",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x4_t val"
+      "int16x4_t a",
+      "int16x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4H"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -102003,26 +305091,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u64",
+    "name": "vsri_n_s32",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1_t val"
+      "int32x2_t a",
+      "int32x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2S"
       },
-      "val": {
-        "register": "Vt.1D"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -102032,26 +305125,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u64_x2",
+    "name": "vsri_n_s64",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x2_t val"
+      "int64x1_t a",
+      "int64x1_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -102061,26 +305159,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u64_x3",
+    "name": "vsri_n_s8",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x3_t val"
+      "int8x8_t a",
+      "int8x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8B"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "b": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -102090,26 +305193,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u64_x4",
+    "name": "vsri_n_u16",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x4_t val"
+      "uint16x4_t a",
+      "uint16x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4H"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "b": {
+        "register": "Vn.4H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -102119,26 +305227,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u8",
+    "name": "vsri_n_u32",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8_t val"
+      "uint32x2_t a",
+      "uint32x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2S"
       },
-      "val": {
-        "register": "Vt.8B"
+      "b": {
+        "register": "Vn.2S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -102148,26 +305261,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u8_x2",
+    "name": "vsri_n_u64",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8x2_t val"
+      "uint64x1_t a",
+      "uint64x1_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt2.8B"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -102177,26 +305295,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u8_x3",
+    "name": "vsri_n_u8",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8x3_t val"
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8B"
       },
-      "val": {
-        "register": "Vt3.8B"
+      "b": {
+        "register": "Vn.8B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -102206,84 +305329,95 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1_u8_x4",
+    "name": "vsrid_n_s64",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8x4_t val"
+      "int64_t a",
+      "int64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f16",
+    "name": "vsrid_n_u64",
     "arguments": [
-      "float16_t * ptr",
-      "float16x8_t val"
+      "uint64_t a",
+      "uint64_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Dd"
       },
-      "val": {
-        "register": "Vt.8H"
+      "b": {
+        "register": "Dn"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f16_x2",
+    "name": "vsriq_n_p16",
     "arguments": [
-      "float16_t * ptr",
-      "float16x8x2_t val"
+      "poly16x8_t a",
+      "poly16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt2.8H"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -102293,55 +305427,64 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f16_x3",
+    "name": "vsriq_n_p64",
     "arguments": [
-      "float16_t * ptr",
-      "float16x8x3_t val"
+      "poly64x2_t a",
+      "poly64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f16_x4",
+    "name": "vsriq_n_p8",
     "arguments": [
-      "float16_t * ptr",
-      "float16x8x4_t val"
+      "poly8x16_t a",
+      "poly8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -102351,26 +305494,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f32",
+    "name": "vsriq_n_s16",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4_t val"
+      "int16x8_t a",
+      "int16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt.4S"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
@@ -102380,26 +305528,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f32_x2",
+    "name": "vsriq_n_s32",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4x2_t val"
+      "int32x4_t a",
+      "int32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt2.4S"
+      "b": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
@@ -102409,26 +305562,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f32_x3",
+    "name": "vsriq_n_s64",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4x3_t val"
+      "int64x2_t a",
+      "int64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
@@ -102438,26 +305596,31 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f32_x4",
+    "name": "vsriq_n_s8",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4x4_t val"
+      "int8x16_t a",
+      "int8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
@@ -102467,139 +305630,162 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f64",
+    "name": "vsriq_n_u16",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2_t val"
+      "uint16x8_t a",
+      "uint16x8_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.8H"
       },
-      "val": {
-        "register": "Vt.2D"
+      "b": {
+        "register": "Vn.8H"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 16
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f64_x2",
+    "name": "vsriq_n_u32",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2x2_t val"
+      "uint32x4_t a",
+      "uint32x4_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.4S"
       },
-      "val": {
-        "register": "Vt2.2D"
+      "b": {
+        "register": "Vn.4S"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 32
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f64_x3",
+    "name": "vsriq_n_u64",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2x3_t val"
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.2D"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "b": {
+        "register": "Vn.2D"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 64
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_f64_x4",
+    "name": "vsriq_n_u8",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2x4_t val"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "const int n"
     ],
     "return_type": {
-      "value": "void"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
-      "ptr": {
-        "register": "Xn"
+      "a": {
+        "register": "Vd.16B"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "b": {
+        "register": "Vn.16B"
+      },
+      "n": {
+        "minimum": 1,
+        "maximum": 8
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "SRI"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_f16",
+    "name": "vst1_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x8_t val",
-      "const int lane"
+      "float16x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.8H"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -102615,25 +305801,23 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_f32",
+    "name": "vst1_f16_x2",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.4S"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -102649,28 +305833,31 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_f64",
+    "name": "vst1_f16_x3",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.2D"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -102681,25 +305868,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_p16",
+    "name": "vst1_f16_x4",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x8_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x4x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -102715,28 +305906,24 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_p64",
+    "name": "vst1_f32",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2_t val",
-      "const int lane"
+      "float32_t * ptr",
+      "float32x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.2D"
+        "register": "Vt.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -102748,25 +305935,23 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_p8",
+    "name": "vst1_f32_x2",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16_t val",
-      "const int lane"
+      "float32_t * ptr",
+      "float32x2x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.16B"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -102782,25 +305967,26 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_s16",
+    "name": "vst1_f32_x3",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8_t val",
-      "const int lane"
+      "float32_t * ptr",
+      "float32x2x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.8H"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -102816,25 +306002,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_s32",
+    "name": "vst1_f32_x4",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4_t val",
-      "const int lane"
+      "float32_t * ptr",
+      "float32x2x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -102850,30 +306040,23 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_s64",
+    "name": "vst1_f64",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2_t val",
-      "const int lane"
+      "float64_t * ptr",
+      "float64x1_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.2D"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -102884,30 +306067,26 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_s8",
+    "name": "vst1_f64_x2",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16_t val",
-      "const int lane"
+      "float64_t * ptr",
+      "float64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.16B"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -102918,30 +306097,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_u16",
+    "name": "vst1_f64_x3",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8_t val",
-      "const int lane"
+      "float64_t * ptr",
+      "float64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.8H"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -102952,30 +306130,32 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_u32",
+    "name": "vst1_f64_x4",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4_t val",
-      "const int lane"
+      "float64_t * ptr",
+      "float64x1x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.4S"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -102986,10 +306166,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_u64",
+    "name": "vst1_lane_f16",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2_t val",
+      "float16_t * ptr",
+      "float16x4_t val",
       "const int lane"
     ],
     "return_type": {
@@ -102998,13 +306178,13 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.2D"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -103020,10 +306200,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_lane_u8",
+    "name": "vst1_lane_f32",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16_t val",
+      "float32_t * ptr",
+      "float32x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -103032,13 +306212,13 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.16B"
+        "register": "Vt.2S"
       }
     },
     "Architectures": [
@@ -103054,25 +306234,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p16",
+    "name": "vst1_lane_f64",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x8_t val"
+      "float64_t * ptr",
+      "float64x1_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.8H"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -103083,20 +306266,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p16_x2",
+    "name": "vst1_lane_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x8x2_t val"
+      "poly16x4_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -103112,24 +306300,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p16_x3",
+    "name": "vst1_lane_p64",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x8x3_t val"
+      "poly64_t * ptr",
+      "poly64x1_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.8H"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -103141,20 +306333,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p16_x4",
+    "name": "vst1_lane_p8",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x8x4_t val"
+      "poly8_t * ptr",
+      "poly8x8_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt4.8H"
+        "register": "Vt.8B"
       }
     },
     "Architectures": [
@@ -103170,23 +306367,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p64",
+    "name": "vst1_lane_s16",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2_t val"
+      "int16_t * ptr",
+      "int16x4_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.2D"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -103198,23 +306401,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p64_x2",
+    "name": "vst1_lane_s32",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2x2_t val"
+      "int32_t * ptr",
+      "int32x2_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2D"
+        "register": "Vt.2S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -103226,20 +306435,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p64_x3",
+    "name": "vst1_lane_s64",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2x3_t val"
+      "int64_t * ptr",
+      "int64x1_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.2D"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
@@ -103255,23 +306469,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p64_x4",
+    "name": "vst1_lane_s8",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2x4_t val"
+      "int8_t * ptr",
+      "int8x8_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt4.2D"
+        "register": "Vt.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -103283,20 +306503,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p8",
+    "name": "vst1_lane_u16",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16_t val"
+      "uint16_t * ptr",
+      "uint16x4_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt.16B"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -103312,20 +306537,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p8_x2",
+    "name": "vst1_lane_u32",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16x2_t val"
+      "uint32_t * ptr",
+      "uint32x2_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.16B"
+        "register": "Vt.2S"
       }
     },
     "Architectures": [
@@ -103341,20 +306571,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p8_x3",
+    "name": "vst1_lane_u64",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16x3_t val"
+      "uint64_t * ptr",
+      "uint64x1_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.16B"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
@@ -103370,20 +306605,25 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_p8_x4",
+    "name": "vst1_lane_u8",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16x4_t val"
+      "uint8_t * ptr",
+      "uint8x8_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt4.16B"
+        "register": "Vt.8B"
       }
     },
     "Architectures": [
@@ -103399,10 +306639,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s16",
+    "name": "vst1_mf8_x4",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8_t val"
+      "int8_t * ptr",
+      "int8x8x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103411,13 +306651,20 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.8H"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -103428,10 +306675,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s16_x2",
+    "name": "vst1_p16",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8x2_t val"
+      "poly16_t * ptr",
+      "poly16x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103441,7 +306688,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -103457,10 +306704,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s16_x3",
+    "name": "vst1_p16_x2",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8x3_t val"
+      "poly16_t * ptr",
+      "poly16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103469,8 +306716,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -103486,10 +306736,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s16_x4",
+    "name": "vst1_p16_x3",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8x4_t val"
+      "poly16_t * ptr",
+      "poly16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103498,8 +306748,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -103515,10 +306771,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s32",
+    "name": "vst1_p16_x4",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4_t val"
+      "poly16_t * ptr",
+      "poly16x4x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103527,8 +306783,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.4S"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -103544,10 +306809,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s32_x2",
+    "name": "vst1_p64",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4x2_t val"
+      "poly64_t * ptr",
+      "poly64x1_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103557,11 +306822,10 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4S"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -103573,10 +306837,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s32_x3",
+    "name": "vst1_p64_x2",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4x3_t val"
+      "poly64_t * ptr",
+      "poly64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103585,12 +306849,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -103602,10 +306868,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s32_x4",
+    "name": "vst1_p64_x3",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4x4_t val"
+      "poly64_t * ptr",
+      "poly64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103614,12 +306880,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -103631,10 +306902,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s64",
+    "name": "vst1_p64_x4",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2_t val"
+      "poly64_t * ptr",
+      "poly64x1x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103643,12 +306914,20 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
@@ -103660,10 +306939,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s64_x2",
+    "name": "vst1_p8",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2x2_t val"
+      "poly8_t * ptr",
+      "poly8x8_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103673,7 +306952,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2D"
+        "register": "Vt.8B"
       }
     },
     "Architectures": [
@@ -103689,10 +306968,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s64_x3",
+    "name": "vst1_p8_x2",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2x3_t val"
+      "poly8_t * ptr",
+      "poly8x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103701,8 +306980,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -103718,10 +307000,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s64_x4",
+    "name": "vst1_p8_x3",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2x4_t val"
+      "poly8_t * ptr",
+      "poly8x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103730,8 +307012,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
@@ -103747,10 +307035,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s8",
+    "name": "vst1_p8_x4",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16_t val"
+      "poly8_t * ptr",
+      "poly8x8x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103759,8 +307047,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -103776,10 +307073,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s8_x2",
+    "name": "vst1_s16",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16x2_t val"
+      "int16_t * ptr",
+      "int16x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103789,7 +307086,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.16B"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -103805,10 +307102,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s8_x3",
+    "name": "vst1_s16_x2",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16x3_t val"
+      "int16_t * ptr",
+      "int16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103817,8 +307114,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -103834,10 +307134,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_s8_x4",
+    "name": "vst1_s16_x3",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16x4_t val"
+      "int16_t * ptr",
+      "int16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103846,8 +307146,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -103863,10 +307169,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u16",
+    "name": "vst1_s16_x4",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8_t val"
+      "int16_t * ptr",
+      "int16x4x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103875,8 +307181,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -103892,10 +307207,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u16_x2",
+    "name": "vst1_s32",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8x2_t val"
+      "int32_t * ptr",
+      "int32x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103905,7 +307220,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.2S"
       }
     },
     "Architectures": [
@@ -103921,10 +307236,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u16_x3",
+    "name": "vst1_s32_x2",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8x3_t val"
+      "int32_t * ptr",
+      "int32x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103933,8 +307248,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -103950,10 +307268,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u16_x4",
+    "name": "vst1_s32_x3",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8x4_t val"
+      "int32_t * ptr",
+      "int32x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103962,8 +307280,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -103979,10 +307303,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u32",
+    "name": "vst1_s32_x4",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4_t val"
+      "int32_t * ptr",
+      "int32x2x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -103991,8 +307315,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -104008,10 +307341,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u32_x2",
+    "name": "vst1_s64",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4x2_t val"
+      "int64_t * ptr",
+      "int64x1_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104021,7 +307354,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4S"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
@@ -104037,10 +307370,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u32_x3",
+    "name": "vst1_s64_x2",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4x3_t val"
+      "int64_t * ptr",
+      "int64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104049,8 +307382,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -104066,10 +307402,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u32_x4",
+    "name": "vst1_s64_x3",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4x4_t val"
+      "int64_t * ptr",
+      "int64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104078,8 +307414,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
@@ -104095,10 +307437,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u64",
+    "name": "vst1_s64_x4",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2_t val"
+      "int64_t * ptr",
+      "int64x1x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104107,8 +307449,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
@@ -104124,10 +307475,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u64_x2",
+    "name": "vst1_s8",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2x2_t val"
+      "int8_t * ptr",
+      "int8x8_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104137,7 +307488,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2D"
+        "register": "Vt.8B"
       }
     },
     "Architectures": [
@@ -104153,10 +307504,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u64_x3",
+    "name": "vst1_s8_x2",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2x3_t val"
+      "int8_t * ptr",
+      "int8x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104165,8 +307516,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -104182,10 +307536,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u64_x4",
+    "name": "vst1_s8_x3",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2x4_t val"
+      "int8_t * ptr",
+      "int8x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104194,8 +307548,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
@@ -104211,10 +307571,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u8",
+    "name": "vst1_s8_x4",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16_t val"
+      "int8_t * ptr",
+      "int8x8x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104223,8 +307583,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -104240,10 +307609,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u8_x2",
+    "name": "vst1_u16",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16x2_t val"
+      "uint16_t * ptr",
+      "uint16x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104253,7 +307622,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.16B"
+        "register": "Vt.4H"
       }
     },
     "Architectures": [
@@ -104269,10 +307638,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u8_x3",
+    "name": "vst1_u16_x2",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16x3_t val"
+      "uint16_t * ptr",
+      "uint16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104281,8 +307650,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -104298,10 +307670,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst1q_u8_x4",
+    "name": "vst1_u16_x3",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16x4_t val"
+      "uint16_t * ptr",
+      "uint16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104310,8 +307682,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -104327,10 +307705,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_f16",
+    "name": "vst1_u16_x4",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x2_t val"
+      "uint16_t * ptr",
+      "uint16x4x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104339,8 +307717,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
         "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -104350,16 +307737,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_f32",
+    "name": "vst1_u32",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x2_t val"
+      "uint32_t * ptr",
+      "uint32x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104369,7 +307756,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2S"
+        "register": "Vt.2S"
       }
     },
     "Architectures": [
@@ -104379,16 +307766,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_f64",
+    "name": "vst1_u32_x2",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x2_t val"
+      "uint32_t * ptr",
+      "uint32x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104397,11 +307784,16 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -104412,25 +307804,26 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_f16",
+    "name": "vst1_u32_x3",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x2_t val",
-      "const int lane"
+      "uint32_t * ptr",
+      "uint32x2x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -104440,31 +307833,35 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_f32",
+    "name": "vst1_u32_x4",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x2_t val",
-      "const int lane"
+      "uint32_t * ptr",
+      "uint32x2x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
         "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -104474,63 +307871,58 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_f64",
+    "name": "vst1_u64",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x2_t val",
-      "const int lane"
+      "uint64_t * ptr",
+      "uint64x1_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.1D"
+        "register": "Vt.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_p16",
+    "name": "vst1_u64_x2",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x2_t val",
-      "const int lane"
+      "uint64_t * ptr",
+      "uint64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -104540,63 +307932,70 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_p64",
+    "name": "vst1_u64_x3",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x2_t val",
-      "const int lane"
+      "uint64_t * ptr",
+      "uint64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
         "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_p8",
+    "name": "vst1_u64_x4",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x2_t val",
-      "const int lane"
+      "uint64_t * ptr",
+      "uint64x1x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.8B"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
@@ -104606,31 +308005,26 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_s16",
+    "name": "vst1_u8",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x2_t val",
-      "const int lane"
+      "uint8_t * ptr",
+      "uint8x8_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4H"
+        "register": "Vt.8B"
       }
     },
     "Architectures": [
@@ -104640,31 +308034,29 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_s32",
+    "name": "vst1_u8_x2",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x2_t val",
-      "const int lane"
+      "uint8_t * ptr",
+      "uint8x8x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.2S"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -104674,63 +308066,70 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_s64",
+    "name": "vst1_u8_x3",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x2_t val",
-      "const int lane"
+      "uint8_t * ptr",
+      "uint8x8x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_s8",
+    "name": "vst1_u8_x4",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x2_t val",
-      "const int lane"
+      "uint8_t * ptr",
+      "uint8x8x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
         "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -104740,31 +308139,26 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_u16",
+    "name": "vst1q_f16",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4x2_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x8_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4H"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
@@ -104774,31 +308168,29 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_u32",
+    "name": "vst1q_f16_x2",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x2_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.2S"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -104808,63 +308200,70 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_u64",
+    "name": "vst1q_f16_x3",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x2_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x8x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_lane_u8",
+    "name": "vst1q_f16_x4",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8x2_t val",
-      "const int lane"
+      "float16_t * ptr",
+      "float16x8x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.8B"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
@@ -104874,16 +308273,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_p16",
+    "name": "vst1q_f32",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x2_t val"
+      "float32_t * ptr",
+      "float32x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104893,7 +308292,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4H"
+        "register": "Vt.4S"
       }
     },
     "Architectures": [
@@ -104903,16 +308302,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_p64",
+    "name": "vst1q_f32_x2",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x2_t val"
+      "float32_t * ptr",
+      "float32x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104921,11 +308320,15 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -104937,10 +308340,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_p8",
+    "name": "vst1q_f32_x3",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x2_t val"
+      "float32_t * ptr",
+      "float32x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104949,8 +308352,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.8B"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
@@ -104960,16 +308369,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_s16",
+    "name": "vst1q_f32_x4",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x2_t val"
+      "float32_t * ptr",
+      "float32x4x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -104978,8 +308387,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
@@ -104989,16 +308407,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_s32",
+    "name": "vst1q_f64",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x2_t val"
+      "float64_t * ptr",
+      "float64x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105008,26 +308426,24 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2S"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_s64",
+    "name": "vst1q_f64_x2",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x2_t val"
+      "float64_t * ptr",
+      "float64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105036,13 +308452,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
@@ -105053,10 +308470,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_s8",
+    "name": "vst1q_f64_x3",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x2_t val"
+      "float64_t * ptr",
+      "float64x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105065,27 +308482,31 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.8B"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_u16",
+    "name": "vst1q_f64_x4",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4x2_t val"
+      "float64_t * ptr",
+      "float64x2x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105094,37 +308515,49 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4H"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_u32",
+    "name": "vst1q_lane_f16",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x2_t val"
+      "float16_t * ptr",
+      "float16x8_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2S"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
@@ -105134,26 +308567,31 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_u64",
+    "name": "vst1q_lane_f32",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x2_t val"
+      "float32_t * ptr",
+      "float32x4_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.1D"
+        "register": "Vt.4S"
       }
     },
     "Architectures": [
@@ -105169,49 +308607,57 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2_u8",
+    "name": "vst1q_lane_f64",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8x2_t val"
+      "float64_t * ptr",
+      "float64x2_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8B"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_f16",
+    "name": "vst1q_lane_p16",
     "arguments": [
-      "float16_t * ptr",
-      "float16x8x2_t val"
+      "poly16_t * ptr",
+      "poly16x8_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
@@ -105221,72 +308667,83 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_f32",
+    "name": "vst1q_lane_p64",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4x2_t val"
+      "poly64_t * ptr",
+      "poly64x2_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4S"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_f64",
+    "name": "vst1q_lane_p8",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2x2_t val"
+      "poly8_t * ptr",
+      "poly8x16_t val",
+      "const int lane"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2D"
+        "register": "Vt.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_f16",
+    "name": "vst1q_lane_s16",
     "arguments": [
-      "float16_t * ptr",
-      "float16x8x2_t val",
+      "int16_t * ptr",
+      "int16x8_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105301,7 +308758,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
@@ -105311,16 +308768,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_f32",
+    "name": "vst1q_lane_s32",
     "arguments": [
-      "float32_t * ptr",
-      "float32x4x2_t val",
+      "int32_t * ptr",
+      "int32x4_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105335,7 +308792,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4S"
+        "register": "Vt.4S"
       }
     },
     "Architectures": [
@@ -105345,16 +308802,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_f64",
+    "name": "vst1q_lane_s64",
     "arguments": [
-      "float64_t * ptr",
-      "float64x2x2_t val",
+      "int64_t * ptr",
+      "int64x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105363,30 +308820,32 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 2
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2D"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_p16",
+    "name": "vst1q_lane_s8",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x8x2_t val",
+      "int8_t * ptr",
+      "int8x16_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105395,13 +308854,13 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 15
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.16B"
       }
     },
     "Architectures": [
@@ -105411,16 +308870,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_p64",
+    "name": "vst1q_lane_u16",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2x2_t val",
+      "uint16_t * ptr",
+      "uint16x8_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105429,30 +308888,32 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.2D"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_p8",
+    "name": "vst1q_lane_u32",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16x2_t val",
+      "uint32_t * ptr",
+      "uint32x4_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105461,30 +308922,32 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.16B"
+        "register": "Vt.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_s16",
+    "name": "vst1q_lane_u64",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8x2_t val",
+      "uint64_t * ptr",
+      "uint64x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105493,13 +308956,13 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -105509,16 +308972,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_s32",
+    "name": "vst1q_lane_u8",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4x2_t val",
+      "uint8_t * ptr",
+      "uint8x16_t val",
       "const int lane"
     ],
     "return_type": {
@@ -105527,13 +308990,13 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 15
       },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.4S"
+        "register": "Vt.16B"
       }
     },
     "Architectures": [
@@ -105543,31 +309006,35 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_s64",
+    "name": "vst1q_mf8_x4",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2x2_t val",
-      "const int lane"
+      "int8_t * ptr",
+      "int8x16x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.2D"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.16B"
       }
     },
     "Architectures": [
@@ -105575,62 +309042,57 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_s8",
+    "name": "vst1q_p16",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16x2_t val",
-      "const int lane"
+      "poly16_t * ptr",
+      "poly16x8_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.16B"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_u16",
+    "name": "vst1q_p16_x2",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8x2_t val",
-      "const int lane"
+      "poly16_t * ptr",
+      "poly16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
         "register": "Vt2.8H"
       }
     },
@@ -105641,31 +309103,32 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_u32",
+    "name": "vst1q_p16_x3",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4x2_t val",
-      "const int lane"
+      "poly16_t * ptr",
+      "poly16x8x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4S"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
@@ -105675,80 +309138,82 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_u64",
+    "name": "vst1q_p16_x4",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2x2_t val",
-      "const int lane"
+      "poly16_t * ptr",
+      "poly16x8x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.2D"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_lane_u8",
+    "name": "vst1q_p64",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16x2_t val",
-      "const int lane"
+      "poly64_t * ptr",
+      "poly64x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 15
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.16B"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_p16",
+    "name": "vst1q_p64_x2",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x8x2_t val"
+      "poly64_t * ptr",
+      "poly64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105757,27 +309222,29 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.8H"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_p64",
+    "name": "vst1q_p64_x3",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x2x2_t val"
+      "poly64x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105786,25 +309253,33 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
         "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_p8",
+    "name": "vst1q_p64_x4",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x16x2_t val"
+      "poly64_t * ptr",
+      "poly64x2x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105813,27 +309288,35 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.16B"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_s16",
+    "name": "vst1q_p8",
     "arguments": [
-      "int16_t * ptr",
-      "int16x8x2_t val"
+      "poly8_t * ptr",
+      "poly8x16_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105843,7 +309326,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.16B"
       }
     },
     "Architectures": [
@@ -105853,16 +309336,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_s32",
+    "name": "vst1q_p8_x2",
     "arguments": [
-      "int32_t * ptr",
-      "int32x4x2_t val"
+      "poly8_t * ptr",
+      "poly8x16x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105871,8 +309354,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4S"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
@@ -105882,16 +309368,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_s64",
+    "name": "vst1q_p8_x3",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2x2_t val"
+      "poly8_t * ptr",
+      "poly8x16x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105900,25 +309386,33 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.2D"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_s8",
+    "name": "vst1q_p8_x4",
     "arguments": [
-      "int8_t * ptr",
-      "int8x16x2_t val"
+      "poly8_t * ptr",
+      "poly8x16x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105927,8 +309421,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
         "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.16B"
       }
     },
     "Architectures": [
@@ -105938,16 +309441,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_u16",
+    "name": "vst1q_s16",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x8x2_t val"
+      "int16_t * ptr",
+      "int16x8_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105957,7 +309460,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt2.8H"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
@@ -105967,16 +309470,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_u32",
+    "name": "vst1q_s16_x2",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x4x2_t val"
+      "int16_t * ptr",
+      "int16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -105985,8 +309488,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.4S"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -105996,16 +309502,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_u64",
+    "name": "vst1q_s16_x3",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2x2_t val"
+      "int16_t * ptr",
+      "int16x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106014,25 +309520,33 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.2D"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst2q_u8",
+    "name": "vst1q_s16_x4",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x16x2_t val"
+      "int16_t * ptr",
+      "int16x8x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106041,8 +309555,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt2.16B"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
@@ -106052,16 +309575,16 @@
     ],
     "instructions": [
       [
-        "ST2"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_f16",
+    "name": "vst1q_s32",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x3_t val"
+      "int32_t * ptr",
+      "int32x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106071,7 +309594,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.4H"
+        "register": "Vt.4S"
       }
     },
     "Architectures": [
@@ -106081,16 +309604,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_f32",
+    "name": "vst1q_s32_x2",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x3_t val"
+      "int32_t * ptr",
+      "int32x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106099,8 +309622,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -106110,16 +309636,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_f64",
+    "name": "vst1q_s32_x3",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x3_t val"
+      "int32_t * ptr",
+      "int32x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106128,11 +309654,19 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -106143,25 +309677,29 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_f16",
+    "name": "vst1q_s32_x4",
     "arguments": [
-      "float16_t * ptr",
-      "float16x4x3_t val",
-      "const int lane"
+      "int32_t * ptr",
+      "int32x4x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
@@ -106171,31 +309709,26 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_f32",
+    "name": "vst1q_s64",
     "arguments": [
-      "float32_t * ptr",
-      "float32x2x3_t val",
-      "const int lane"
+      "int64_t * ptr",
+      "int64x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.2S"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -106205,63 +309738,64 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_f64",
+    "name": "vst1q_s64_x2",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1x3_t val",
-      "const int lane"
+      "int64_t * ptr",
+      "int64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_p16",
+    "name": "vst1q_s64_x3",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x3_t val",
-      "const int lane"
+      "int64_t * ptr",
+      "int64x2x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -106271,63 +309805,64 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_p64",
+    "name": "vst1q_s64_x4",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x3_t val",
-      "const int lane"
+      "int64_t * ptr",
+      "int64x2x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_p8",
+    "name": "vst1q_s8",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x3_t val",
-      "const int lane"
+      "int8_t * ptr",
+      "int8x16_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.8B"
+        "register": "Vt.16B"
       }
     },
     "Architectures": [
@@ -106337,31 +309872,29 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_s16",
+    "name": "vst1q_s8_x2",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x3_t val",
-      "const int lane"
+      "int8_t * ptr",
+      "int8x16x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
@@ -106371,31 +309904,32 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_s32",
+    "name": "vst1q_s8_x3",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x3_t val",
-      "const int lane"
+      "int8_t * ptr",
+      "int8x16x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
@@ -106405,63 +309939,64 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_s64",
+    "name": "vst1q_s8_x4",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x3_t val",
-      "const int lane"
+      "int8_t * ptr",
+      "int8x16x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_s8",
+    "name": "vst1q_u16",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x3_t val",
-      "const int lane"
+      "uint16_t * ptr",
+      "uint16x8_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.8B"
+        "register": "Vt.8H"
       }
     },
     "Architectures": [
@@ -106471,31 +310006,29 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_u16",
+    "name": "vst1q_u16_x2",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x4x3_t val",
-      "const int lane"
+      "uint16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -106505,31 +310038,32 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_u32",
+    "name": "vst1q_u16_x3",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x3_t val",
-      "const int lane"
+      "uint16_t * ptr",
+      "uint16x8x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
@@ -106539,63 +310073,64 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_u64",
+    "name": "vst1q_u16_x4",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x3_t val",
-      "const int lane"
+      "uint16_t * ptr",
+      "uint16x8x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_lane_u8",
+    "name": "vst1q_u32",
     "arguments": [
-      "uint8_t * ptr",
-      "uint8x8x3_t val",
-      "const int lane"
+      "uint32_t * ptr",
+      "uint32x4_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 7
-      },
       "ptr": {
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.8B"
+        "register": "Vt.4S"
       }
     },
     "Architectures": [
@@ -106605,16 +310140,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_p16",
+    "name": "vst1q_u32_x2",
     "arguments": [
-      "poly16_t * ptr",
-      "poly16x4x3_t val"
+      "uint32_t * ptr",
+      "uint32x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106623,8 +310158,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4H"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -106634,16 +310172,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_p64",
+    "name": "vst1q_u32_x3",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x1x3_t val"
+      "uint32_t * ptr",
+      "uint32x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106652,11 +310190,18 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
@@ -106668,10 +310213,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_p8",
+    "name": "vst1q_u32_x4",
     "arguments": [
-      "poly8_t * ptr",
-      "poly8x8x3_t val"
+      "uint32_t * ptr",
+      "uint32x4x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106680,8 +310225,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8B"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
@@ -106691,16 +310245,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_s16",
+    "name": "vst1q_u64",
     "arguments": [
-      "int16_t * ptr",
-      "int16x4x3_t val"
+      "uint64_t * ptr",
+      "uint64x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106710,7 +310264,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.4H"
+        "register": "Vt.2D"
       }
     },
     "Architectures": [
@@ -106720,16 +310274,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_s32",
+    "name": "vst1q_u64_x2",
     "arguments": [
-      "int32_t * ptr",
-      "int32x2x3_t val"
+      "uint64_t * ptr",
+      "uint64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106738,8 +310292,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
@@ -106749,16 +310306,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_s64",
+    "name": "vst1q_u64_x3",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1x3_t val"
+      "uint64_t * ptr",
+      "uint64x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106767,8 +310324,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -106784,10 +310347,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_s8",
+    "name": "vst1q_u64_x4",
     "arguments": [
-      "int8_t * ptr",
-      "int8x8x3_t val"
+      "uint64_t * ptr",
+      "uint64x2x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106796,8 +310359,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8B"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
@@ -106807,16 +310379,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_u16",
+    "name": "vst1q_u8",
     "arguments": [
-      "uint16_t * ptr",
-      "uint16x4x3_t val"
+      "uint8_t * ptr",
+      "uint8x16_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106826,7 +310398,7 @@
         "register": "Xn"
       },
       "val": {
-        "register": "Vt3.4H"
+        "register": "Vt.16B"
       }
     },
     "Architectures": [
@@ -106836,16 +310408,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_u32",
+    "name": "vst1q_u8_x2",
     "arguments": [
-      "uint32_t * ptr",
-      "uint32x2x3_t val"
+      "uint8_t * ptr",
+      "uint8x16x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106854,8 +310426,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2S"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
@@ -106865,16 +310440,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_u64",
+    "name": "vst1q_u8_x3",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1x3_t val"
+      "uint8_t * ptr",
+      "uint8x16x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106883,8 +310458,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.1D"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
@@ -106900,10 +310481,10 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3_u8",
+    "name": "vst1q_u8_x4",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x8x3_t val"
+      "uint8x16x4_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106912,8 +310493,17 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.16B"
       }
     },
     "Architectures": [
@@ -106923,16 +310513,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_f16",
+    "name": "vst2_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x8x3_t val"
+      "float16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106941,8 +310531,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -106952,16 +310545,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_f32",
+    "name": "vst2_f32",
     "arguments": [
       "float32_t * ptr",
-      "float32x4x3_t val"
+      "float32x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106970,8 +310563,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -106981,16 +310577,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_f64",
+    "name": "vst2_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x2x3_t val"
+      "float64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -106999,8 +310595,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -107008,16 +310607,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_f16",
+    "name": "vst2_lane_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x8x3_t val",
+      "float16x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107026,13 +310625,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107042,16 +310644,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_f32",
+    "name": "vst2_lane_f32",
     "arguments": [
       "float32_t * ptr",
-      "float32x4x3_t val",
+      "float32x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107060,13 +310662,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -107076,16 +310681,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_f64",
+    "name": "vst2_lane_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x2x3_t val",
+      "float64x1x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107094,13 +310699,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -107108,16 +310716,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_p16",
+    "name": "vst2_lane_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x8x3_t val",
+      "poly16x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107126,13 +310734,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107142,16 +310753,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_p64",
+    "name": "vst2_lane_p64",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x2x3_t val",
+      "poly64x1x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107160,13 +310771,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -107174,16 +310788,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_p8",
+    "name": "vst2_lane_p8",
     "arguments": [
       "poly8_t * ptr",
-      "poly8x16x3_t val",
+      "poly8x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107192,13 +310806,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -107208,16 +310825,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_s16",
+    "name": "vst2_lane_s16",
     "arguments": [
       "int16_t * ptr",
-      "int16x8x3_t val",
+      "int16x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107226,13 +310843,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107242,16 +310862,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_s32",
+    "name": "vst2_lane_s32",
     "arguments": [
       "int32_t * ptr",
-      "int32x4x3_t val",
+      "int32x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107260,13 +310880,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -107276,16 +310899,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_s64",
+    "name": "vst2_lane_s64",
     "arguments": [
       "int64_t * ptr",
-      "int64x2x3_t val",
+      "int64x1x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107294,13 +310917,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -107308,16 +310934,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_s8",
+    "name": "vst2_lane_s8",
     "arguments": [
       "int8_t * ptr",
-      "int8x16x3_t val",
+      "int8x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107326,13 +310952,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -107342,16 +310971,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_u16",
+    "name": "vst2_lane_u16",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x8x3_t val",
+      "uint16x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107360,13 +310989,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107376,16 +311008,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_u32",
+    "name": "vst2_lane_u32",
     "arguments": [
       "uint32_t * ptr",
-      "uint32x4x3_t val",
+      "uint32x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107394,13 +311026,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -107410,16 +311045,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_u64",
+    "name": "vst2_lane_u64",
     "arguments": [
       "uint64_t * ptr",
-      "uint64x2x3_t val",
+      "uint64x1x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107428,13 +311063,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
@@ -107442,16 +311080,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_lane_u8",
+    "name": "vst2_lane_u8",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x16x3_t val",
+      "uint8x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107460,13 +311098,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -107476,16 +311117,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_p16",
+    "name": "vst2_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x8x3_t val"
+      "poly16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107494,8 +311135,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107505,16 +311149,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_p64",
+    "name": "vst2_p64",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x2x3_t val"
+      "poly64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107523,25 +311167,29 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_p8",
+    "name": "vst2_p8",
     "arguments": [
       "poly8_t * ptr",
-      "poly8x16x3_t val"
+      "poly8x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107550,8 +311198,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -107561,16 +311212,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_s16",
+    "name": "vst2_s16",
     "arguments": [
       "int16_t * ptr",
-      "int16x8x3_t val"
+      "int16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107579,8 +311230,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107590,16 +311244,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_s32",
+    "name": "vst2_s32",
     "arguments": [
       "int32_t * ptr",
-      "int32x4x3_t val"
+      "int32x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107608,8 +311262,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -107619,16 +311276,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_s64",
+    "name": "vst2_s64",
     "arguments": [
       "int64_t * ptr",
-      "int64x2x3_t val"
+      "int64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107637,25 +311294,30 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_s8",
+    "name": "vst2_s8",
     "arguments": [
       "int8_t * ptr",
-      "int8x16x3_t val"
+      "int8x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107664,8 +311326,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -107675,16 +311340,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_u16",
+    "name": "vst2_u16",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x8x3_t val"
+      "uint16x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107693,8 +311358,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
       }
     },
     "Architectures": [
@@ -107704,16 +311372,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_u32",
+    "name": "vst2_u32",
     "arguments": [
       "uint32_t * ptr",
-      "uint32x4x3_t val"
+      "uint32x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107722,8 +311390,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
       }
     },
     "Architectures": [
@@ -107733,16 +311404,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_u64",
+    "name": "vst2_u64",
     "arguments": [
       "uint64_t * ptr",
-      "uint64x2x3_t val"
+      "uint64x1x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107751,25 +311422,30 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST3"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst3q_u8",
+    "name": "vst2_u8",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x16x3_t val"
+      "uint8x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107778,8 +311454,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt3.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
       }
     },
     "Architectures": [
@@ -107789,16 +311468,16 @@
     ],
     "instructions": [
       [
-        "ST3"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_f16",
+    "name": "vst2q_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x4x4_t val"
+      "float16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107807,8 +311486,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -107818,16 +311500,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_f32",
+    "name": "vst2q_f32",
     "arguments": [
       "float32_t * ptr",
-      "float32x2x4_t val"
+      "float32x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107836,8 +311518,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -107847,16 +311532,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_f64",
+    "name": "vst2q_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x1x4_t val"
+      "float64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -107865,8 +311550,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
@@ -107874,16 +311562,16 @@
     ],
     "instructions": [
       [
-        "ST1"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_f16",
+    "name": "vst2q_lane_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x4x4_t val",
+      "float16x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107892,13 +311580,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -107908,16 +311599,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_f32",
+    "name": "vst2q_lane_f32",
     "arguments": [
       "float32_t * ptr",
-      "float32x2x4_t val",
+      "float32x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107926,13 +311617,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -107942,16 +311636,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_f64",
+    "name": "vst2q_lane_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x1x4_t val",
+      "float64x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107960,13 +311654,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
@@ -107974,16 +311671,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_p16",
+    "name": "vst2q_lane_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x4x4_t val",
+      "poly16x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -107992,13 +311689,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -108008,16 +311708,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_p64",
+    "name": "vst2q_lane_p64",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x1x4_t val",
+      "poly64x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108026,13 +311726,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
@@ -108040,16 +311743,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_p8",
+    "name": "vst2q_lane_p8",
     "arguments": [
       "poly8_t * ptr",
-      "poly8x8x4_t val",
+      "poly8x16x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108058,32 +311761,33 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 15
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_s16",
+    "name": "vst2q_lane_s16",
     "arguments": [
       "int16_t * ptr",
-      "int16x4x4_t val",
+      "int16x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108092,13 +311796,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -108108,16 +311815,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_s32",
+    "name": "vst2q_lane_s32",
     "arguments": [
       "int32_t * ptr",
-      "int32x2x4_t val",
+      "int32x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108126,13 +311833,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -108142,16 +311852,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_s64",
+    "name": "vst2q_lane_s64",
     "arguments": [
       "int64_t * ptr",
-      "int64x1x4_t val",
+      "int64x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108160,13 +311870,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
@@ -108174,16 +311887,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_s8",
+    "name": "vst2q_lane_s8",
     "arguments": [
       "int8_t * ptr",
-      "int8x8x4_t val",
+      "int8x16x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108192,32 +311905,33 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 15
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_u16",
+    "name": "vst2q_lane_u16",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x4x4_t val",
+      "uint16x8x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108226,13 +311940,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -108242,16 +311959,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_u32",
+    "name": "vst2q_lane_u32",
     "arguments": [
       "uint32_t * ptr",
-      "uint32x2x4_t val",
+      "uint32x4x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108260,13 +311977,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -108276,16 +311996,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_u64",
+    "name": "vst2q_lane_u64",
     "arguments": [
       "uint64_t * ptr",
-      "uint64x1x4_t val",
+      "uint64x2x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108294,13 +312014,16 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
@@ -108308,16 +312031,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_lane_u8",
+    "name": "vst2q_lane_u8",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x8x4_t val",
+      "uint8x16x2_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108326,32 +312049,33 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 15
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_p16",
+    "name": "vst2q_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x4x4_t val"
+      "poly16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108360,8 +312084,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -108371,16 +312098,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_p64",
+    "name": "vst2q_p64",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x1x4_t val"
+      "poly64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108389,26 +312116,28 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_p8",
+    "name": "vst2q_p8",
     "arguments": [
       "poly8_t * ptr",
-      "poly8x8x4_t val"
+      "poly8x16x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108417,8 +312146,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
@@ -108428,16 +312160,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_s16",
+    "name": "vst2q_s16",
     "arguments": [
       "int16_t * ptr",
-      "int16x4x4_t val"
+      "int16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108446,8 +312178,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -108457,16 +312192,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_s32",
+    "name": "vst2q_s32",
     "arguments": [
       "int32_t * ptr",
-      "int32x2x4_t val"
+      "int32x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108475,8 +312210,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -108486,16 +312224,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_s64",
+    "name": "vst2q_s64",
     "arguments": [
       "int64_t * ptr",
-      "int64x1x4_t val"
+      "int64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108504,27 +312242,28 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_s8",
+    "name": "vst2q_s8",
     "arguments": [
       "int8_t * ptr",
-      "int8x8x4_t val"
+      "int8x16x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108533,8 +312272,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
@@ -108544,16 +312286,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_u16",
+    "name": "vst2q_u16",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x4x4_t val"
+      "uint16x8x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108562,8 +312304,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
       }
     },
     "Architectures": [
@@ -108573,16 +312318,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_u32",
+    "name": "vst2q_u32",
     "arguments": [
       "uint32_t * ptr",
-      "uint32x2x4_t val"
+      "uint32x4x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108591,8 +312336,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
       }
     },
     "Architectures": [
@@ -108602,16 +312350,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_u64",
+    "name": "vst2q_u64",
     "arguments": [
       "uint64_t * ptr",
-      "uint64x1x4_t val"
+      "uint64x2x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108620,27 +312368,28 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.1D"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST1"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4_u8",
+    "name": "vst2q_u8",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x8x4_t val"
+      "uint8x16x2_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108649,8 +312398,11 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8B"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
       }
     },
     "Architectures": [
@@ -108660,16 +312412,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_f16",
+    "name": "vst3_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x8x4_t val"
+      "float16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108678,8 +312430,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -108689,16 +312447,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_f32",
+    "name": "vst3_f32",
     "arguments": [
       "float32_t * ptr",
-      "float32x4x4_t val"
+      "float32x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108707,8 +312465,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -108718,16 +312482,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_f64",
+    "name": "vst3_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x2x4_t val"
+      "float64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -108736,8 +312500,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
@@ -108745,16 +312515,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_f16",
+    "name": "vst3_lane_f16",
     "arguments": [
       "float16_t * ptr",
-      "float16x8x4_t val",
+      "float16x4x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108763,13 +312533,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -108779,16 +312555,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_f32",
+    "name": "vst3_lane_f32",
     "arguments": [
       "float32_t * ptr",
-      "float32x4x4_t val",
+      "float32x2x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108797,13 +312573,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -108813,16 +312595,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_f64",
+    "name": "vst3_lane_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x2x4_t val",
+      "float64x1x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108831,13 +312613,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
@@ -108845,16 +312633,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_p16",
+    "name": "vst3_lane_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x8x4_t val",
+      "poly16x4x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108863,13 +312651,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -108879,16 +312673,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_p64",
+    "name": "vst3_lane_p64",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x2x4_t val",
+      "poly64x1x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108897,13 +312691,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
@@ -108911,16 +312711,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_p8",
+    "name": "vst3_lane_p8",
     "arguments": [
       "poly8_t * ptr",
-      "poly8x16x4_t val",
+      "poly8x8x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108929,30 +312729,38 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_s16",
+    "name": "vst3_lane_s16",
     "arguments": [
       "int16_t * ptr",
-      "int16x8x4_t val",
+      "int16x4x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108961,13 +312769,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -108977,16 +312791,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_s32",
+    "name": "vst3_lane_s32",
     "arguments": [
       "int32_t * ptr",
-      "int32x4x4_t val",
+      "int32x2x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -108995,13 +312809,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -109011,16 +312831,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_s64",
+    "name": "vst3_lane_s64",
     "arguments": [
       "int64_t * ptr",
-      "int64x2x4_t val",
+      "int64x1x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109029,13 +312849,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
@@ -109043,16 +312869,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_s8",
+    "name": "vst3_lane_s8",
     "arguments": [
       "int8_t * ptr",
-      "int8x16x4_t val",
+      "int8x8x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109061,30 +312887,38 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_u16",
+    "name": "vst3_lane_u16",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x8x4_t val",
+      "uint16x4x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109093,13 +312927,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 7
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -109109,16 +312949,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_u32",
+    "name": "vst3_lane_u32",
     "arguments": [
       "uint32_t * ptr",
-      "uint32x4x4_t val",
+      "uint32x2x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109127,13 +312967,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -109143,16 +312989,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_u64",
+    "name": "vst3_lane_u64",
     "arguments": [
       "uint64_t * ptr",
-      "uint64x2x4_t val",
+      "uint64x1x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109161,13 +313007,19 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 0
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
@@ -109175,16 +313027,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_lane_u8",
+    "name": "vst3_lane_u8",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x16x4_t val",
+      "uint8x8x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109193,30 +313045,38 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 15
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_p16",
+    "name": "vst3_p16",
     "arguments": [
       "poly16_t * ptr",
-      "poly16x8x4_t val"
+      "poly16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109225,8 +313085,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -109236,16 +313102,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_p64",
+    "name": "vst3_p64",
     "arguments": [
       "poly64_t * ptr",
-      "poly64x2x4_t val"
+      "poly64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109254,25 +313120,32 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_p8",
+    "name": "vst3_p8",
     "arguments": [
       "poly8_t * ptr",
-      "poly8x16x4_t val"
+      "poly8x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109281,8 +313154,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
@@ -109292,16 +313171,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_s16",
+    "name": "vst3_s16",
     "arguments": [
       "int16_t * ptr",
-      "int16x8x4_t val"
+      "int16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109310,8 +313189,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -109321,16 +313206,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_s32",
+    "name": "vst3_s32",
     "arguments": [
       "int32_t * ptr",
-      "int32x4x4_t val"
+      "int32x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109339,8 +313224,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -109350,16 +313241,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_s64",
+    "name": "vst3_s64",
     "arguments": [
       "int64_t * ptr",
-      "int64x2x4_t val"
+      "int64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109368,25 +313259,33 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_s8",
+    "name": "vst3_s8",
     "arguments": [
       "int8_t * ptr",
-      "int8x16x4_t val"
+      "int8x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109395,8 +313294,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
@@ -109406,16 +313311,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_u16",
+    "name": "vst3_u16",
     "arguments": [
       "uint16_t * ptr",
-      "uint16x8x4_t val"
+      "uint16x4x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109424,8 +313329,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
       }
     },
     "Architectures": [
@@ -109435,16 +313346,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_u32",
+    "name": "vst3_u32",
     "arguments": [
       "uint32_t * ptr",
-      "uint32x4x4_t val"
+      "uint32x2x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109453,8 +313364,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
       }
     },
     "Architectures": [
@@ -109464,16 +313381,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_u64",
+    "name": "vst3_u64",
     "arguments": [
       "uint64_t * ptr",
-      "uint64x2x4_t val"
+      "uint64x1x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109482,25 +313399,33 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "ST4"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vst4q_u8",
+    "name": "vst3_u8",
     "arguments": [
       "uint8_t * ptr",
-      "uint8x16x4_t val"
+      "uint8x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109509,8 +313434,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt4.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
       }
     },
     "Architectures": [
@@ -109520,16 +313451,16 @@
     ],
     "instructions": [
       [
-        "ST4"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstrq_p128",
+    "name": "vst3q_f16",
     "arguments": [
-      "poly128_t * ptr",
-      "poly128_t val"
+      "float16_t * ptr",
+      "float16x8x3_t val"
     ],
     "return_type": {
       "value": "void"
@@ -109538,105 +313469,84 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Qt"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "STR"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1_lane_f64",
+    "name": "vst3q_f32",
     "arguments": [
-      "float64_t * ptr",
-      "float64x1_t val",
-      "const int lane"
+      "float32_t * ptr",
+      "float32x4x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.1D"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1q_lane_f64",
+    "name": "vst3q_f64",
     "arguments": [
       "float64_t * ptr",
-      "float64x2_t val",
-      "const int lane"
+      "float64x2x3_t val"
     ],
     "return_type": {
       "value": "void"
     },
     "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
         "register": "Vt.2D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STL1"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vstl1_lane_p64",
-    "arguments": [
-      "poly64_t * ptr",
-      "poly64x1_t val",
-      "const int lane"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "lane": {
-        "minimum": 0,
-        "maximum": 0
-      },
-      "ptr": {
-        "register": "Xn"
       },
-      "val": {
-        "register": "Vt.1D"
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -109644,16 +313554,16 @@
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1q_lane_p64",
+    "name": "vst3q_lane_f16",
     "arguments": [
-      "poly64_t * ptr",
-      "poly64x2_t val",
+      "float16_t * ptr",
+      "float16x8x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109662,30 +313572,38 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.2D"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1_lane_u64",
+    "name": "vst3q_lane_f32",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x1_t val",
+      "float32_t * ptr",
+      "float32x4x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109694,30 +313612,38 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 3
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.1D"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1q_lane_u64",
+    "name": "vst3q_lane_f64",
     "arguments": [
-      "uint64_t * ptr",
-      "uint64x2_t val",
+      "float64_t * ptr",
+      "float64x2x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109731,8 +313657,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
         "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -109740,16 +313672,16 @@
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1_lane_s64",
+    "name": "vst3q_lane_p16",
     "arguments": [
-      "int64_t * ptr",
-      "int64x1_t val",
+      "poly16_t * ptr",
+      "poly16x8x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109758,30 +313690,38 @@
     "Arguments_Preparation": {
       "lane": {
         "minimum": 0,
-        "maximum": 0
+        "maximum": 7
       },
       "ptr": {
         "register": "Xn"
       },
-      "val": {
-        "register": "Vt.1D"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vstl1q_lane_s64",
+    "name": "vst3q_lane_p64",
     "arguments": [
-      "int64_t * ptr",
-      "int64x2_t val",
+      "poly64_t * ptr",
+      "poly64x2x3_t val",
       "const int lane"
     ],
     "return_type": {
@@ -109795,8 +313735,14 @@
       "ptr": {
         "register": "Xn"
       },
-      "val": {
+      "val.val[0]": {
         "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -109804,54 +313750,77 @@
     ],
     "instructions": [
       [
-        "STL1"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_f16",
+    "name": "vst3q_lane_p8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "poly8_t * ptr",
+      "poly8x16x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
       },
-      "b": {
-        "register": "Vm.4H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_f32",
+    "name": "vst3q_lane_s16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int16_t * ptr",
+      "int16x8x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
@@ -109861,53 +313830,37 @@
     ],
     "instructions": [
       [
-        "FSUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_f64",
+    "name": "vst3q_lane_s32",
     "arguments": [
-      "float64x1_t a",
-      "float64x1_t b"
+      "int32_t * ptr",
+      "int32x4x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float64x1_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Dm"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "FSUB"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vsub_s16",
-    "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
-    ],
-    "return_type": {
-      "value": "int16x4_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4H"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
@@ -109917,55 +313870,75 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_s32",
+    "name": "vst3q_lane_s64",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "int64_t * ptr",
+      "int64x2x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_s64",
+    "name": "vst3q_lane_s8",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "int8_t * ptr",
+      "int8x16x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
       },
-      "b": {
-        "register": "Dm"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
@@ -109975,26 +313948,37 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_s8",
+    "name": "vst3q_lane_u16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint16_t * ptr",
+      "uint16x8x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.8B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
@@ -110004,26 +313988,37 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_u16",
+    "name": "vst3q_lane_u32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "uint32_t * ptr",
+      "uint32x4x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
@@ -110033,55 +314028,75 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_u32",
+    "name": "vst3q_lane_u64",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "uint64_t * ptr",
+      "uint64x2x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_u64",
+    "name": "vst3q_lane_u8",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "uint8_t * ptr",
+      "uint8x16x3_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
       },
-      "b": {
-        "register": "Dm"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
@@ -110091,26 +314106,32 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsub_u8",
+    "name": "vst3q_p16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "poly16_t * ptr",
+      "poly16x8x3_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8B"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
@@ -110120,26 +314141,32 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubd_s64",
+    "name": "vst3q_p64",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "poly64_t * ptr",
+      "poly64x2x3_t val"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Dm"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -110147,116 +314174,137 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubd_u64",
+    "name": "vst3q_p8",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "poly8_t * ptr",
+      "poly8x16x3_t val"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Dm"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubh_f16",
+    "name": "vst3q_s16",
     "arguments": [
-      "float16_t a",
-      "float16_t b"
+      "int16_t * ptr",
+      "int16x8x3_t val"
     ],
     "return_type": {
-      "value": "float16_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Hn"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Hm"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSUB"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_high_s16",
+    "name": "vst3q_s32",
     "arguments": [
-      "int8x8_t r",
-      "int16x8_t a",
-      "int16x8_t b"
+      "int32_t * ptr",
+      "int32x4x3_t val"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.4S"
       },
-      "r": {
-        "register": "Vd.8B"
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUBHN2"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_high_s32",
+    "name": "vst3q_s64",
     "arguments": [
-      "int16x4_t r",
-      "int32x4_t a",
-      "int32x4_t b"
+      "int64_t * ptr",
+      "int64x2x3_t val"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.2D"
       },
-      "r": {
-        "register": "Vd.4H"
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -110264,123 +314312,137 @@
     ],
     "instructions": [
       [
-        "SUBHN2"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_high_s64",
+    "name": "vst3q_s8",
     "arguments": [
-      "int32x2_t r",
-      "int64x2_t a",
-      "int64x2_t b"
+      "int8_t * ptr",
+      "int8x16x3_t val"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "val.val[0]": {
+        "register": "Vt.16B"
       },
-      "r": {
-        "register": "Vd.2S"
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUBHN2"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_high_u16",
+    "name": "vst3q_u16",
     "arguments": [
-      "uint8x8_t r",
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "uint16_t * ptr",
+      "uint16x8x3_t val"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.8H"
       },
-      "r": {
-        "register": "Vd.8B"
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUBHN2"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_high_u32",
+    "name": "vst3q_u32",
     "arguments": [
-      "uint16x4_t r",
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "uint32_t * ptr",
+      "uint32x4x3_t val"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.4S"
       },
-      "r": {
-        "register": "Vd.4H"
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUBHN2"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_high_u64",
+    "name": "vst3q_u64",
     "arguments": [
-      "uint32x2_t r",
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint64_t * ptr",
+      "uint64x2x3_t val"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "val.val[0]": {
+        "register": "Vt.2D"
       },
-      "r": {
-        "register": "Vd.2S"
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       }
     },
     "Architectures": [
@@ -110388,26 +314450,32 @@
     ],
     "instructions": [
       [
-        "SUBHN2"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_s16",
+    "name": "vst3q_u8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint8_t * ptr",
+      "uint8x16x3_t val"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       }
     },
     "Architectures": [
@@ -110417,26 +314485,35 @@
     ],
     "instructions": [
       [
-        "SUBHN"
+        "ST3"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_s32",
+    "name": "vst4_f16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "float16_t * ptr",
+      "float16x4x4_t val"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -110446,26 +314523,35 @@
     ],
     "instructions": [
       [
-        "SUBHN"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_s64",
+    "name": "vst4_f32",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "float32_t * ptr",
+      "float32x2x4_t val"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -110475,55 +314561,76 @@
     ],
     "instructions": [
       [
-        "SUBHN"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_u16",
+    "name": "vst4_f64",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "float64_t * ptr",
+      "float64x1x4_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUBHN"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_u32",
+    "name": "vst4_lane_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "float16_t * ptr",
+      "float16x4x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -110533,26 +314640,40 @@
     ],
     "instructions": [
       [
-        "SUBHN"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubhn_u64",
+    "name": "vst4_lane_f32",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "float32_t * ptr",
+      "float32x2x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2D"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -110562,26 +314683,40 @@
     ],
     "instructions": [
       [
-        "SUBHN"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_high_s16",
+    "name": "vst4_lane_f64",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "float64_t * ptr",
+      "float64x1x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.8H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
@@ -110589,53 +314724,83 @@
     ],
     "instructions": [
       [
-        "SSUBL2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_high_s32",
+    "name": "vst4_lane_p16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "poly16_t * ptr",
+      "poly16x4x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSUBL2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_high_s8",
+    "name": "vst4_lane_p64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "poly64_t * ptr",
+      "poly64x1x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
@@ -110643,136 +314808,210 @@
     ],
     "instructions": [
       [
-        "SSUBL2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_high_u16",
+    "name": "vst4_lane_p8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "poly8_t * ptr",
+      "poly8x8x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.8H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBL2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_high_u32",
+    "name": "vst4_lane_s16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int16_t * ptr",
+      "int16x4x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBL2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_high_u8",
+    "name": "vst4_lane_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int32_t * ptr",
+      "int32x2x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBL2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_s16",
+    "name": "vst4_lane_s64",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "int64_t * ptr",
+      "int64x1x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.4H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSUBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_s32",
+    "name": "vst4_lane_s8",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "int8_t * ptr",
+      "int8x8x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -110782,26 +315021,40 @@
     ],
     "instructions": [
       [
-        "SSUBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_s8",
+    "name": "vst4_lane_u16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint16_t * ptr",
+      "uint16x4x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.8B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -110811,26 +315064,40 @@
     ],
     "instructions": [
       [
-        "SSUBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_u16",
+    "name": "vst4_lane_u32",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "uint32_t * ptr",
+      "uint32x2x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.4H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -110840,55 +315107,81 @@
     ],
     "instructions": [
       [
-        "USUBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_u32",
+    "name": "vst4_lane_u64",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "uint64_t * ptr",
+      "uint64x1x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubl_u8",
+    "name": "vst4_lane_u8",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "uint8_t * ptr",
+      "uint8x8x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.8B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -110898,110 +315191,148 @@
     ],
     "instructions": [
       [
-        "USUBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_f16",
+    "name": "vst4_p16",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "poly16_t * ptr",
+      "poly16x4x4_t val"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_f32",
+    "name": "vst4_p64",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "poly64_t * ptr",
+      "poly64x1x4_t val"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSUB"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_f64",
+    "name": "vst4_p8",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "poly8_t * ptr",
+      "poly8x8x4_t val"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "FSUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_s16",
+    "name": "vst4_s16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int16_t * ptr",
+      "int16x4x4_t val"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -111011,26 +315342,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_s32",
+    "name": "vst4_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int32_t * ptr",
+      "int32x2x4_t val"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -111040,26 +315380,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_s64",
+    "name": "vst4_s64",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int64_t * ptr",
+      "int64x1x4_t val"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
@@ -111069,26 +315418,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_s8",
+    "name": "vst4_s8",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int8_t * ptr",
+      "int8x8x4_t val"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -111098,26 +315456,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_u16",
+    "name": "vst4_u16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "uint16_t * ptr",
+      "uint16x4x4_t val"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.4H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4H"
       }
     },
     "Architectures": [
@@ -111127,26 +315494,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_u32",
+    "name": "vst4_u32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "uint32_t * ptr",
+      "uint32x2x4_t val"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.2S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2S"
       }
     },
     "Architectures": [
@@ -111156,26 +315532,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_u64",
+    "name": "vst4_u64",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "uint64_t * ptr",
+      "uint64x1x4_t val"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.2D"
+      "val.val[0]": {
+        "register": "Vt.1D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.1D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.1D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.1D"
       }
     },
     "Architectures": [
@@ -111185,26 +315570,35 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubq_u8",
+    "name": "vst4_u8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint8_t * ptr",
+      "uint8x8x4_t val"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.16B"
+      "val.val[0]": {
+        "register": "Vt.8B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8B"
       }
     },
     "Architectures": [
@@ -111214,80 +315608,111 @@
     ],
     "instructions": [
       [
-        "SUB"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_high_s16",
+    "name": "vst4q_f16",
     "arguments": [
-      "int32x4_t a",
-      "int16x8_t b"
+      "float16_t * ptr",
+      "float16x8x4_t val"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.8H"
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSUBW2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_high_s32",
+    "name": "vst4q_f32",
     "arguments": [
-      "int64x2_t a",
-      "int32x4_t b"
+      "float32_t * ptr",
+      "float32x4x4_t val"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.4S"
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSUBW2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_high_s8",
+    "name": "vst4q_f64",
     "arguments": [
-      "int16x8_t a",
-      "int8x16_t b"
+      "float64_t * ptr",
+      "float64x2x4_t val"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "ptr": {
+        "register": "Xn"
       },
-      "b": {
-        "register": "Vm.16B"
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
@@ -111295,80 +315720,126 @@
     ],
     "instructions": [
       [
-        "SSUBW2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_high_u16",
+    "name": "vst4q_lane_f16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x8_t b"
+      "float16_t * ptr",
+      "float16x8x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.8H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBW2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_high_u32",
+    "name": "vst4q_lane_f32",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x4_t b"
+      "float32_t * ptr",
+      "float32x4x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.4S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBW2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_high_u8",
+    "name": "vst4q_lane_f64",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x16_t b"
+      "float64_t * ptr",
+      "float64x2x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
@@ -111376,26 +315847,40 @@
     ],
     "instructions": [
       [
-        "USUBW2"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_s16",
+    "name": "vst4q_lane_p16",
     "arguments": [
-      "int32x4_t a",
-      "int16x4_t b"
+      "poly16_t * ptr",
+      "poly16x8x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.4H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
@@ -111405,84 +315890,122 @@
     ],
     "instructions": [
       [
-        "SSUBW"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_s32",
+    "name": "vst4q_lane_p64",
     "arguments": [
-      "int64x2_t a",
-      "int32x2_t b"
+      "poly64_t * ptr",
+      "poly64x2x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSUBW"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_s8",
+    "name": "vst4q_lane_p8",
     "arguments": [
-      "int16x8_t a",
-      "int8x8_t b"
+      "poly8_t * ptr",
+      "poly8x16x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
       },
-      "b": {
-        "register": "Vm.8B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SSUBW"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_u16",
+    "name": "vst4q_lane_s16",
     "arguments": [
-      "uint32x4_t a",
-      "uint16x4_t b"
+      "int16_t * ptr",
+      "int16x8x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "lane": {
+        "minimum": 0,
+        "maximum": 7
       },
-      "b": {
-        "register": "Vm.4H"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
@@ -111492,26 +316015,40 @@
     ],
     "instructions": [
       [
-        "USUBW"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_u32",
+    "name": "vst4q_lane_s32",
     "arguments": [
-      "uint64x2_t a",
-      "uint32x2_t b"
+      "int32_t * ptr",
+      "int32x4x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2D"
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
       },
-      "b": {
-        "register": "Vm.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
@@ -111521,174 +316058,208 @@
     ],
     "instructions": [
       [
-        "USUBW"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsubw_u8",
+    "name": "vst4q_lane_s64",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b"
+      "int64_t * ptr",
+      "int64x2x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
       },
-      "b": {
-        "register": "Vm.8B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USUBW"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsudot_lane_s32",
+    "name": "vst4q_lane_s8",
     "arguments": [
-      "int32x2_t r",
-      "int8x8_t a",
-      "uint8x8_t b",
+      "int8_t * ptr",
+      "int8x16x4_t val",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
-      },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 15
       },
-      "r": {
-        "register": "Vd.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
+      },
+      "val.val[3]": {
+        "register": "Vt4.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUDOT"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsudot_laneq_s32",
+    "name": "vst4q_lane_u16",
     "arguments": [
-      "int32x2_t r",
-      "int8x8_t a",
-      "uint8x16_t b",
+      "uint16_t * ptr",
+      "uint16x8x4_t val",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
-      },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
-      "r": {
-        "register": "Vd.2S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
+      },
+      "val.val[3]": {
+        "register": "Vt4.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUDOT"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsudotq_lane_s32",
+    "name": "vst4q_lane_u32",
     "arguments": [
-      "int32x4_t r",
-      "int8x16_t a",
-      "uint8x8_t b",
+      "uint32_t * ptr",
+      "uint32x4x4_t val",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
-      },
       "lane": {
         "minimum": 0,
-        "maximum": 1
+        "maximum": 3
       },
-      "r": {
-        "register": "Vd.4S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
+      },
+      "val.val[3]": {
+        "register": "Vt4.4S"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "SUDOT"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vsudotq_laneq_s32",
+    "name": "vst4q_lane_u64",
     "arguments": [
-      "int32x4_t r",
-      "int8x16_t a",
-      "uint8x16_t b",
+      "uint64_t * ptr",
+      "uint64x2x4_t val",
       "const int lane"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
-      },
-      "b": {
-        "register": "Vm.4B"
-      },
       "lane": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 1
       },
-      "r": {
-        "register": "Vd.4S"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
+      },
+      "val.val[3]": {
+        "register": "Vt4.2D"
       }
     },
     "Architectures": [
@@ -111696,52 +316267,77 @@
     ],
     "instructions": [
       [
-        "SUDOT"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl1_p8",
+    "name": "vst4q_lane_u8",
     "arguments": [
-      "poly8x8_t a",
-      "uint8x8_t idx"
+      "uint8_t * ptr",
+      "uint8x16x4_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 15
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.16B"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl1_s8",
+    "name": "vst4q_p16",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t idx"
+      "poly16_t * ptr",
+      "poly16x8x4_t val"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.8H"
+      }
     },
     "Architectures": [
       "v7",
@@ -111750,52 +316346,72 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl1_u8",
+    "name": "vst4q_p64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t idx"
+      "poly64_t * ptr",
+      "poly64x2x4_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl2_p8",
+    "name": "vst4q_p8",
     "arguments": [
-      "poly8x8x2_t a",
-      "uint8x8_t idx"
+      "poly8_t * ptr",
+      "poly8x16x4_t val"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.16B"
+      }
     },
     "Architectures": [
       "v7",
@@ -111804,25 +316420,36 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl2_s8",
+    "name": "vst4q_s16",
     "arguments": [
-      "int8x8x2_t a",
-      "int8x8_t idx"
+      "int16_t * ptr",
+      "int16x8x4_t val"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.8H"
+      }
     },
     "Architectures": [
       "v7",
@@ -111831,25 +316458,36 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl2_u8",
+    "name": "vst4q_s32",
     "arguments": [
-      "uint8x8x2_t a",
-      "uint8x8_t idx"
+      "int32_t * ptr",
+      "int32x4x4_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.4S"
+      }
     },
     "Architectures": [
       "v7",
@@ -111858,52 +316496,72 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl3_p8",
+    "name": "vst4q_s64",
     "arguments": [
-      "poly8x8x3_t a",
-      "uint8x8_t idx"
+      "int64_t * ptr",
+      "int64x2x4_t val"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl3_s8",
+    "name": "vst4q_s8",
     "arguments": [
-      "int8x8x3_t a",
-      "int8x8_t idx"
+      "int8_t * ptr",
+      "int8x16x4_t val"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.16B"
+      }
     },
     "Architectures": [
       "v7",
@@ -111912,25 +316570,36 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl3_u8",
+    "name": "vst4q_u16",
     "arguments": [
-      "uint8x8x3_t a",
-      "uint8x8_t idx"
+      "uint16_t * ptr",
+      "uint16x8x4_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.8H"
+      },
+      "val.val[1]": {
+        "register": "Vt2.8H"
+      },
+      "val.val[2]": {
+        "register": "Vt3.8H"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.8H"
+      }
     },
     "Architectures": [
       "v7",
@@ -111939,25 +316608,36 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl4_p8",
+    "name": "vst4q_u32",
     "arguments": [
-      "poly8x8x4_t a",
-      "uint8x8_t idx"
+      "uint32_t * ptr",
+      "uint32x4x4_t val"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.4S"
+      },
+      "val.val[1]": {
+        "register": "Vt2.4S"
+      },
+      "val.val[2]": {
+        "register": "Vt3.4S"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.4S"
+      }
     },
     "Architectures": [
       "v7",
@@ -111966,52 +316646,72 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl4_s8",
+    "name": "vst4q_u64",
     "arguments": [
-      "int8x8x4_t a",
-      "int8x8_t idx"
+      "uint64_t * ptr",
+      "uint64x2x4_t val"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.2D"
+      },
+      "val.val[1]": {
+        "register": "Vt2.2D"
+      },
+      "val.val[2]": {
+        "register": "Vt3.2D"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbl4_u8",
+    "name": "vst4q_u8",
     "arguments": [
-      "uint8x8x4_t a",
-      "uint8x8_t idx"
+      "uint8_t * ptr",
+      "uint8x16x4_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
+      },
+      "val.val[0]": {
+        "register": "Vt.16B"
+      },
+      "val.val[1]": {
+        "register": "Vt2.16B"
+      },
+      "val.val[2]": {
+        "register": "Vt3.16B"
       },
-      "idx": {}
+      "val.val[3]": {
+        "register": "Vt4.16B"
+      }
     },
     "Architectures": [
       "v7",
@@ -112020,335 +316720,339 @@
     ],
     "instructions": [
       [
-        "TBL"
+        "ST4"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx1_p8",
+    "name": "vstl1_lane_f64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b",
-      "uint8x8_t idx"
+      "float64_t * ptr",
+      "float64x1_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "idx": {}
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOVI",
-        "CMHS",
-        "TBL",
-        "BIF"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx1_s8",
+    "name": "vstl1_lane_p64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b",
-      "int8x8_t idx"
+      "poly64_t * ptr",
+      "poly64x1_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "idx": {}
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOVI",
-        "CMHS",
-        "TBL",
-        "BIF"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx1_u8",
+    "name": "vstl1_lane_s64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "uint8x8_t idx"
+      "int64_t * ptr",
+      "int64x1_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "idx": {}
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOVI",
-        "CMHS",
-        "TBL",
-        "BIF"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx2_p8",
+    "name": "vstl1_lane_u64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8x2_t b",
-      "uint8x8_t idx"
+      "uint64_t * ptr",
+      "uint64x1_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
       },
-      "idx": {}
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx2_s8",
+    "name": "vstl1q_lane_f64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8x2_t b",
-      "int8x8_t idx"
+      "float64_t * ptr",
+      "float64x2_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
       },
-      "idx": {}
+      "val": {
+        "register": "Vt.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx2_u8",
+    "name": "vstl1q_lane_p64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8x2_t b",
-      "uint8x8_t idx"
+      "poly64_t * ptr",
+      "poly64x2_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
       },
-      "idx": {}
+      "val": {
+        "register": "Vt.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx3_p8",
+    "name": "vstl1q_lane_s64",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8x3_t b",
-      "uint8x8_t idx"
+      "int64_t * ptr",
+      "int64x2_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
       },
-      "idx": {}
+      "val": {
+        "register": "Vt.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOVI",
-        "CMHS",
-        "TBL",
-        "BIF"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx3_s8",
+    "name": "vstl1q_lane_u64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8x3_t b",
-      "int8x8_t idx"
+      "uint64_t * ptr",
+      "uint64x2_t val",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
       },
-      "idx": {}
+      "val": {
+        "register": "Vt.2D"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOVI",
-        "CMHS",
-        "TBL",
-        "BIF"
+        "STL1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx3_u8",
+    "name": "vstrq_p128",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8x3_t b",
-      "uint8x8_t idx"
+      "poly128_t * ptr",
+      "poly128_t val"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "void"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "ptr": {
+        "register": "Xn"
       },
-      "idx": {}
+      "val": {
+        "register": "Qt"
+      }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "MOVI",
-        "CMHS",
-        "TBL",
-        "BIF"
+        "STR"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx4_p8",
+    "name": "vsub_f16",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8x4_t b",
-      "uint8x8_t idx"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vn.4H"
       },
-      "idx": {}
+      "b": {
+        "register": "Vm.4H"
+      }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx4_s8",
+    "name": "vsub_f32",
     "arguments": [
-      "int8x8_t a",
-      "int8x8x4_t b",
-      "int8x8_t idx"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Vn.2S"
       },
-      "idx": {}
+      "b": {
+        "register": "Vm.2S"
+      }
     },
     "Architectures": [
       "v7",
@@ -112357,48 +317061,46 @@
     ],
     "instructions": [
       [
-        "TBX"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtbx4_u8",
+    "name": "vsub_f64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8x4_t b",
-      "uint8x8_t idx"
+      "float64x1_t a",
+      "float64x1_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float64x1_t"
     },
     "Arguments_Preparation": {
-      "a": {},
-      "b": {
-        "register": "Vn.16B"
+      "a": {
+        "register": "Dn"
       },
-      "idx": {}
+      "b": {
+        "register": "Dm"
+      }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TBX"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_f16",
+    "name": "vsub_s16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112409,23 +317111,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_f32",
+    "name": "vsub_s32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112436,50 +317140,54 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_p16",
+    "name": "vsub_s64",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "int64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dm"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_p8",
+    "name": "vsub_s8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112490,23 +317198,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_s16",
+    "name": "vsub_u16",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112517,23 +317227,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_s32",
+    "name": "vsub_u32",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112544,23 +317256,54 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_s8",
+    "name": "vsub_u64",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint64x1_t a",
+      "uint64x1_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      },
+      "b": {
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUB"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vsub_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112571,30 +317314,32 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_u16",
+    "name": "vsubd_s64",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "int64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -112602,26 +317347,26 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_u32",
+    "name": "vsubd_u64",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "uint64_t a",
+      "uint64_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -112629,46 +317374,48 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1_u8",
+    "name": "vsubh_f16",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "float16_t a",
+      "float16_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "float16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Hn"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Hm"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_f16",
+    "name": "vsubhn_high_s16",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int8x8_t r",
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112676,6 +317423,9 @@
       },
       "b": {
         "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -112683,19 +317433,20 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_f32",
+    "name": "vsubhn_high_s32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int16x4_t r",
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112703,6 +317454,9 @@
       },
       "b": {
         "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -112710,19 +317464,20 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_f64",
+    "name": "vsubhn_high_s64",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "int32x2_t r",
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112730,6 +317485,9 @@
       },
       "b": {
         "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -112737,19 +317495,20 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_p16",
+    "name": "vsubhn_high_u16",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b"
+      "uint8x8_t r",
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112757,6 +317516,9 @@
       },
       "b": {
         "register": "Vm.8H"
+      },
+      "r": {
+        "register": "Vd.8B"
       }
     },
     "Architectures": [
@@ -112764,26 +317526,30 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_p64",
+    "name": "vsubhn_high_u32",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "uint16x4_t r",
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4S"
+      },
+      "r": {
+        "register": "Vd.4H"
       }
     },
     "Architectures": [
@@ -112791,26 +317557,30 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_p8",
+    "name": "vsubhn_high_u64",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "uint32x2_t r",
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.2D"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
@@ -112818,19 +317588,19 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_s16",
+    "name": "vsubhn_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112841,23 +317611,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_s32",
+    "name": "vsubhn_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112868,23 +317640,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_s64",
+    "name": "vsubhn_s64",
     "arguments": [
       "int64x2_t a",
       "int64x2_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -112895,111 +317669,119 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_s8",
+    "name": "vsubhn_u16",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_u16",
+    "name": "vsubhn_u32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_u32",
+    "name": "vsubhn_u64",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1"
+        "SUBHN"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_u64",
+    "name": "vsubl_high_s16",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -113007,26 +317789,26 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SSUBL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn1q_u8",
+    "name": "vsubl_high_s32",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -113034,26 +317816,26 @@
     ],
     "instructions": [
       [
-        "TRN1"
+        "SSUBL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_f16",
+    "name": "vsubl_high_s8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -113061,26 +317843,26 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "SSUBL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_f32",
+    "name": "vsubl_high_u16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -113088,26 +317870,26 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "USUBL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_p16",
+    "name": "vsubl_high_u32",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -113115,26 +317897,26 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "USUBL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_p8",
+    "name": "vsubl_high_u8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -113142,19 +317924,19 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "USUBL2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_s16",
+    "name": "vsubl_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113165,23 +317947,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SSUBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_s32",
+    "name": "vsubl_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113192,23 +317976,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SSUBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_s8",
+    "name": "vsubl_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113219,23 +318005,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SSUBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_u16",
+    "name": "vsubl_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113246,23 +318034,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "USUBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_u32",
+    "name": "vsubl_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113273,23 +318063,25 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "USUBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2_u8",
+    "name": "vsubl_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113300,17 +318092,19 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "USUBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_f16",
+    "name": "vsubq_f16",
     "arguments": [
       "float16x8_t a",
       "float16x8_t b"
@@ -113327,17 +318121,18 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_f32",
+    "name": "vsubq_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
@@ -113354,17 +318149,19 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_f64",
+    "name": "vsubq_f64",
     "arguments": [
       "float64x2_t a",
       "float64x2_t b"
@@ -113385,19 +318182,19 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "FSUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_p16",
+    "name": "vsubq_s16",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -113408,219 +318205,235 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_p64",
+    "name": "vsubq_s32",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_p8",
+    "name": "vsubq_s64",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_s16",
+    "name": "vsubq_s8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_s32",
+    "name": "vsubq_u16",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_s64",
+    "name": "vsubq_u32",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_s8",
+    "name": "vsubq_u64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_u16",
+    "name": "vsubq_u8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN2"
+        "SUB"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_u32",
+    "name": "vsubw_high_s16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int32x4_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -113628,26 +318441,26 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "SSUBW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_u64",
+    "name": "vsubw_high_s32",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "int64x2_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -113655,23 +318468,23 @@
     ],
     "instructions": [
       [
-        "TRN2"
+        "SSUBW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn2q_u8",
+    "name": "vsubw_high_s8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int16x8_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
         "register": "Vm.16B"
@@ -113682,143 +318495,104 @@
     ],
     "instructions": [
       [
-        "TRN2"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "Neon",
-    "name": "vtrn_f16",
-    "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
-    ],
-    "return_type": {
-      "value": "float16x4x2_t"
-    },
-    "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
-      },
-      "b": {
-        "register": "Vm.4H"
-      }
-    },
-    "Architectures": [
-      "v7",
-      "A32",
-      "A64"
-    ],
-    "instructions": [
-      [
-        "TRN1",
-        "TRN2"
+        "SSUBW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_f32",
+    "name": "vsubw_high_u16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "uint32x4_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "float32x2x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "USUBW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_p16",
+    "name": "vsubw_high_u32",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b"
+      "uint64x2_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "poly16x4x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "USUBW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_p8",
+    "name": "vsubw_high_u8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "uint16x8_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "poly8x8x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "USUBW2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_s16",
+    "name": "vsubw_s16",
     "arguments": [
-      "int16x4_t a",
+      "int32x4_t a",
       "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       },
       "b": {
         "register": "Vm.4H"
@@ -113831,24 +318605,23 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SSUBW"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_s32",
+    "name": "vsubw_s32",
     "arguments": [
-      "int32x2_t a",
+      "int64x2_t a",
       "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
       },
       "b": {
         "register": "Vm.2S"
@@ -113861,24 +318634,23 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SSUBW"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_s8",
+    "name": "vsubw_s8",
     "arguments": [
-      "int8x8_t a",
+      "int16x8_t a",
       "int8x8_t b"
     ],
     "return_type": {
-      "value": "int8x8x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
       "b": {
         "register": "Vm.8B"
@@ -113891,24 +318663,23 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SSUBW"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_u16",
+    "name": "vsubw_u16",
     "arguments": [
-      "uint16x4_t a",
+      "uint32x4_t a",
       "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x4x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.4S"
       },
       "b": {
         "register": "Vm.4H"
@@ -113921,24 +318692,23 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "USUBW"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_u32",
+    "name": "vsubw_u32",
     "arguments": [
-      "uint32x2_t a",
+      "uint64x2_t a",
       "uint32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x2x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.2D"
       },
       "b": {
         "register": "Vm.2S"
@@ -113951,24 +318721,23 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "USUBW"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrn_u8",
+    "name": "vsubw_u8",
     "arguments": [
-      "uint8x8_t a",
+      "uint16x8_t a",
       "uint8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x8x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
       "b": {
         "register": "Vm.8B"
@@ -113981,147 +318750,171 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "USUBW"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_f16",
+    "name": "vsudot_lane_s32",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "int32x2_t r",
+      "int8x8_t a",
+      "uint8x8_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float16x8x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SUDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_f32",
+    "name": "vsudot_laneq_s32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int32x2_t r",
+      "int8x8_t a",
+      "uint8x16_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "float32x4x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SUDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_p16",
+    "name": "vsudotq_lane_s32",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b"
+      "int32x4_t r",
+      "int8x16_t a",
+      "uint8x8_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly16x8x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SUDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_p8",
+    "name": "vsudotq_laneq_s32",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "int32x4_t r",
+      "int8x16_t a",
+      "uint8x16_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "poly8x16x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "SUDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_s16",
+    "name": "vtbl1_p8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "poly8x8_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "int16x8x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "Zeros(64):a": {
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114131,27 +318924,26 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_s32",
+    "name": "vtbl1_s8",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int8x8_t a",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "int32x4x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "Zeros(64):a": {
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114161,27 +318953,26 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_s8",
+    "name": "vtbl1_u8",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "uint8x8_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "int8x16x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "Zeros(64):a": {
         "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114191,27 +318982,26 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_u16",
+    "name": "vtbl2_p8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "poly8x8x2_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint16x8x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8H"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114221,27 +319011,26 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_u32",
+    "name": "vtbl2_s8",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int8x8x2_t a",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint32x4x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4S"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114251,27 +319040,26 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtrnq_u8",
+    "name": "vtbl2_u8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "uint8x8x2_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint8x16x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
+      "a.val[1]:a.val[0]": {
         "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114281,54 +319069,60 @@
     ],
     "instructions": [
       [
-        "TRN1",
-        "TRN2"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_p64",
+    "name": "vtbl3_p8",
     "arguments": [
-      "poly64x1_t a",
-      "poly64x1_t b"
+      "poly8x8x3_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "Zeros(64):a.val[2]": {
+        "register": "Vn+1.16B"
       },
-      "b": {
-        "register": "Dm"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_p8",
+    "name": "vtbl3_s8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "int8x8x3_t a",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "Zeros(64):a.val[2]": {
+        "register": "Vn+1.16B"
       },
-      "b": {
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
         "register": "Vm.8B"
       }
     },
@@ -114339,26 +319133,29 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_s16",
+    "name": "vtbl3_u8",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "uint8x8x3_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.4H"
+      "Zeros(64):a.val[2]": {
+        "register": "Vn+1.16B"
       },
-      "b": {
-        "register": "Vm.4H"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114368,26 +319165,29 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_s32",
+    "name": "vtbl4_p8",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "poly8x8x4_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.2S"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "a.val[3]:a.val[2]": {
+        "register": "Vn+1.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114397,52 +319197,60 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_s64",
+    "name": "vtbl4_s8",
     "arguments": [
-      "int64x1_t a",
-      "int64x1_t b"
+      "int8x8x4_t a",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Dn"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
       },
-      "b": {
-        "register": "Dm"
+      "a.val[3]:a.val[2]": {
+        "register": "Vn+1.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_s8",
+    "name": "vtbl4_u8",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "uint8x8x4_t a",
+      "uint8x8_t idx"
     ],
     "return_type": {
       "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
-      "a": {
-        "register": "Vn.8B"
+      "a.val[1]:a.val[0]": {
+        "register": "Vn.16B"
       },
-      "b": {
+      "a.val[3]:a.val[2]": {
+        "register": "Vn+1.16B"
+      },
+      "idx": {
         "register": "Vm.8B"
       }
     },
@@ -114453,26 +319261,30 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBL"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_u16",
+    "name": "vtbx1_p8",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "poly8x8_t a",
+      "poly8x8_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
+      "Zeros(64):b": {
+        "register": "Vn.16B"
+      },
       "a": {
-        "register": "Vn.4H"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Vm.4H"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114482,26 +319294,33 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "MOVI",
+        "CMHS",
+        "TBL",
+        "BIF"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_u32",
+    "name": "vtbx1_s8",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "int8x8_t a",
+      "int8x8_t b",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
+      "Zeros(64):b": {
+        "register": "Vn.16B"
+      },
       "a": {
-        "register": "Vn.2S"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Vm.2S"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114511,52 +319330,68 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "MOVI",
+        "CMHS",
+        "TBL",
+        "BIF"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_u64",
+    "name": "vtbx1_u8",
     "arguments": [
-      "uint64x1_t a",
-      "uint64x1_t b"
+      "uint8x8_t a",
+      "uint8x8_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64x1_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
+      "Zeros(64):b": {
+        "register": "Vn.16B"
+      },
       "a": {
-        "register": "Dn"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Dm"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "MOVI",
+        "CMHS",
+        "TBL",
+        "BIF"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtst_u8",
+    "name": "vtbx2_p8",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "poly8x8_t a",
+      "poly8x8x2_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vd.8B"
       },
-      "b": {
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
         "register": "Vm.8B"
       }
     },
@@ -114567,108 +319402,138 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstd_s64",
+    "name": "vtbx2_s8",
     "arguments": [
-      "int64_t a",
-      "int64_t b"
+      "int8x8_t a",
+      "int8x8x2_t b",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Dm"
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstd_u64",
+    "name": "vtbx2_u8",
     "arguments": [
-      "uint64_t a",
-      "uint64_t b"
+      "uint8x8_t a",
+      "uint8x8x2_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dn"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Dm"
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_p64",
+    "name": "vtbx3_p8",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "poly8x8_t a",
+      "poly8x8x3_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
+      "Zeros(64):b.val[2]": {
+        "register": "Vn+1.16B"
+      },
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "MOVI",
+        "CMHS",
+        "TBL",
+        "BIF"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_p8",
+    "name": "vtbx3_s8",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "int8x8_t a",
+      "int8x8x3_t b",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
+      "Zeros(64):b.val[2]": {
+        "register": "Vn+1.16B"
+      },
       "a": {
+        "register": "Vd.8B"
+      },
+      "b.val[1]:b.val[0]": {
         "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114678,26 +319543,36 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "MOVI",
+        "CMHS",
+        "TBL",
+        "BIF"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_s16",
+    "name": "vtbx3_u8",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint8x8_t a",
+      "uint8x8x3_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
+      "Zeros(64):b.val[2]": {
+        "register": "Vn+1.16B"
+      },
       "a": {
-        "register": "Vn.8H"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Vm.8H"
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "idx": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114707,26 +319582,36 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "MOVI",
+        "CMHS",
+        "TBL",
+        "BIF"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_s32",
+    "name": "vtbx4_p8",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "poly8x8_t a",
+      "poly8x8x4_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Vm.4S"
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "b.val[3]:b.val[2]": {
+        "register": "Vn+1.16B"
+      },
+      "c": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114736,53 +319621,69 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_s64",
+    "name": "vtbx4_s8",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "int8x8_t a",
+      "int8x8x4_t b",
+      "int8x8_t idx"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vd.8B"
       },
-      "b": {
-        "register": "Vm.2D"
+      "b.val[1]:b.val[0]": {
+        "register": "Vn.16B"
+      },
+      "b.val[3]:b.val[2]": {
+        "register": "Vn+1.16B"
+      },
+      "c": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_s8",
+    "name": "vtbx4_u8",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "uint8x8_t a",
+      "uint8x8x4_t b",
+      "uint8x8_t idx"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
+        "register": "Vd.8B"
+      },
+      "b.val[1]:b.val[0]": {
         "register": "Vn.16B"
       },
-      "b": {
-        "register": "Vm.16B"
+      "b.val[3]:b.val[2]": {
+        "register": "Vn+1.16B"
+      },
+      "c": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114792,84 +319693,80 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TBX"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_u16",
+    "name": "vtrn1_f16",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_u32",
+    "name": "vtrn1_f32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_u64",
+    "name": "vtrn1_p16",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "poly16x4_t a",
+      "poly16x4_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -114877,55 +319774,53 @@
     ],
     "instructions": [
       [
-        "CMTST"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vtstq_u8",
+    "name": "vtrn1_p8",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "poly8x8_t a",
+      "poly8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "CMTST"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqadd_s16",
+    "name": "vtrn1_s16",
     "arguments": [
       "int16x4_t a",
-      "uint16x4_t b"
+      "int16x4_t b"
     ],
     "return_type": {
       "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.4H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -114933,26 +319828,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqadd_s32",
+    "name": "vtrn1_s32",
     "arguments": [
       "int32x2_t a",
-      "uint32x2_t b"
+      "int32x2_t b"
     ],
     "return_type": {
       "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2S"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vn.2S"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -114960,26 +319855,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqadd_s64",
+    "name": "vtrn1_s8",
     "arguments": [
-      "int64x1_t a",
-      "uint64x1_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int64x1_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Dn"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -114987,26 +319882,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqadd_s8",
+    "name": "vtrn1_u16",
     "arguments": [
-      "int8x8_t a",
-      "uint8x8_t b"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vn.8B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -115014,26 +319909,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddb_s8",
+    "name": "vtrn1_u32",
     "arguments": [
-      "int8_t a",
-      "uint8_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Bd"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Bn"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -115041,26 +319936,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddd_s64",
+    "name": "vtrn1_u8",
     "arguments": [
-      "int64_t a",
-      "uint64_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int64_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Dd"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Dn"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -115068,26 +319963,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddh_s16",
+    "name": "vtrn1q_f16",
     "arguments": [
-      "int16_t a",
-      "uint16_t b"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "int16_t"
+      "value": "float16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Hd"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Hn"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -115095,26 +319990,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddq_s16",
+    "name": "vtrn1q_f32",
     "arguments": [
-      "int16x8_t a",
-      "uint16x8_t b"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.8H"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vn.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -115122,26 +320017,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddq_s32",
+    "name": "vtrn1q_f64",
     "arguments": [
-      "int32x4_t a",
-      "uint32x4_t b"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.4S"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.4S"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -115149,26 +320044,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddq_s64",
+    "name": "vtrn1q_p16",
     "arguments": [
-      "int64x2_t a",
-      "uint64x2_t b"
+      "poly16x8_t a",
+      "poly16x8_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vn.2D"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -115176,26 +320071,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqaddq_s8",
+    "name": "vtrn1q_p64",
     "arguments": [
-      "int8x16_t a",
-      "uint8x16_t b"
+      "poly64x2_t a",
+      "poly64x2_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vd.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vn.16B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -115203,26 +320098,26 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuqadds_s32",
+    "name": "vtrn1q_p8",
     "arguments": [
-      "int32_t a",
-      "uint32_t b"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "int32_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Sd"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Sn"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -115230,72 +320125,53 @@
     ],
     "instructions": [
       [
-        "SUQADD"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusdot_lane_s32",
+    "name": "vtrn1q_s16",
     "arguments": [
-      "int32x2_t r",
-      "uint8x8_t a",
-      "int8x8_t b",
-      "const int lane"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4B"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USDOT"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusdot_laneq_s32",
+    "name": "vtrn1q_s32",
     "arguments": [
-      "int32x2_t r",
-      "uint8x8_t a",
-      "int8x16_t b",
-      "const int lane"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.4B"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -115303,104 +320179,80 @@
     ],
     "instructions": [
       [
-        "USDOT"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusdot_s32",
+    "name": "vtrn1q_s64",
     "arguments": [
-      "int32x2_t r",
-      "uint8x8_t a",
-      "int8x8_t b"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.8B"
-      },
-      "r": {
-        "register": "Vd.2S"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USDOT"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusdotq_lane_s32",
+    "name": "vtrn1q_s8",
     "arguments": [
-      "int32x4_t r",
-      "uint8x16_t a",
-      "int8x8_t b",
-      "const int lane"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4B"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.4S"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USDOT"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusdotq_laneq_s32",
+    "name": "vtrn1q_u16",
     "arguments": [
-      "int32x4_t r",
-      "uint8x16_t a",
-      "int8x16_t b",
-      "const int lane"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4B"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.4S"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -115408,30 +320260,53 @@
     ],
     "instructions": [
       [
-        "USDOT"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusdotq_s32",
+    "name": "vtrn1q_u32",
     "arguments": [
-      "int32x4_t r",
-      "uint8x16_t a",
-      "int8x16_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vtrn1q_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
       },
-      "r": {
-        "register": "Vd.4S"
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -115439,20 +320314,19 @@
     ],
     "instructions": [
       [
-        "USDOT"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vusmmlaq_s32",
+    "name": "vtrn1q_u8",
     "arguments": [
-      "int32x4_t r",
       "uint8x16_t a",
-      "int8x16_t b"
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -115460,24 +320334,20 @@
       },
       "b": {
         "register": "Vm.16B"
-      },
-      "r": {
-        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "USMMLA"
+        "TRN1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_f16",
+    "name": "vtrn2_f16",
     "arguments": [
       "float16x4_t a",
       "float16x4_t b"
@@ -115498,13 +320368,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_f32",
+    "name": "vtrn2_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b"
@@ -115525,13 +320395,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_p16",
+    "name": "vtrn2_p16",
     "arguments": [
       "poly16x4_t a",
       "poly16x4_t b"
@@ -115552,13 +320422,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_p8",
+    "name": "vtrn2_p8",
     "arguments": [
       "poly8x8_t a",
       "poly8x8_t b"
@@ -115579,13 +320449,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_s16",
+    "name": "vtrn2_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
@@ -115606,13 +320476,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_s32",
+    "name": "vtrn2_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
@@ -115633,13 +320503,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_s8",
+    "name": "vtrn2_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
@@ -115660,13 +320530,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_u16",
+    "name": "vtrn2_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
@@ -115687,13 +320557,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_u32",
+    "name": "vtrn2_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
@@ -115714,13 +320584,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1_u8",
+    "name": "vtrn2_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b"
@@ -115741,13 +320611,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_f16",
+    "name": "vtrn2q_f16",
     "arguments": [
       "float16x8_t a",
       "float16x8_t b"
@@ -115768,13 +320638,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_f32",
+    "name": "vtrn2q_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
@@ -115795,13 +320665,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_f64",
+    "name": "vtrn2q_f64",
     "arguments": [
       "float64x2_t a",
       "float64x2_t b"
@@ -115822,13 +320692,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_p16",
+    "name": "vtrn2q_p16",
     "arguments": [
       "poly16x8_t a",
       "poly16x8_t b"
@@ -115849,13 +320719,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_p64",
+    "name": "vtrn2q_p64",
     "arguments": [
       "poly64x2_t a",
       "poly64x2_t b"
@@ -115876,13 +320746,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_p8",
+    "name": "vtrn2q_p8",
     "arguments": [
       "poly8x16_t a",
       "poly8x16_t b"
@@ -115903,13 +320773,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_s16",
+    "name": "vtrn2q_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
@@ -115930,13 +320800,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_s32",
+    "name": "vtrn2q_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
@@ -115957,13 +320827,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_s64",
+    "name": "vtrn2q_s64",
     "arguments": [
       "int64x2_t a",
       "int64x2_t b"
@@ -115984,13 +320854,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_s8",
+    "name": "vtrn2q_s8",
     "arguments": [
       "int8x16_t a",
       "int8x16_t b"
@@ -116011,13 +320881,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_u16",
+    "name": "vtrn2q_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b"
@@ -116038,13 +320908,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_u32",
+    "name": "vtrn2q_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b"
@@ -116065,13 +320935,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_u64",
+    "name": "vtrn2q_u64",
     "arguments": [
       "uint64x2_t a",
       "uint64x2_t b"
@@ -116092,13 +320962,13 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp1q_u8",
+    "name": "vtrn2q_u8",
     "arguments": [
       "uint8x16_t a",
       "uint8x16_t b"
@@ -116119,19 +320989,19 @@
     ],
     "instructions": [
       [
-        "UZP1"
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_f16",
+    "name": "vtrn_f16",
     "arguments": [
       "float16x4_t a",
       "float16x4_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "float16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116142,23 +321012,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_f32",
+    "name": "vtrn_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "float32x2x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116169,23 +321042,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_p16",
+    "name": "vtrn_p16",
     "arguments": [
       "poly16x4_t a",
       "poly16x4_t b"
     ],
     "return_type": {
-      "value": "poly16x4_t"
+      "value": "poly16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116196,23 +321072,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_p8",
+    "name": "vtrn_p8",
     "arguments": [
       "poly8x8_t a",
       "poly8x8_t b"
     ],
     "return_type": {
-      "value": "poly8x8_t"
+      "value": "poly8x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116223,23 +321102,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_s16",
+    "name": "vtrn_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
     ],
     "return_type": {
-      "value": "int16x4_t"
+      "value": "int16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116250,23 +321132,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_s32",
+    "name": "vtrn_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
     ],
     "return_type": {
-      "value": "int32x2_t"
+      "value": "int32x2x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116277,23 +321162,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_s8",
+    "name": "vtrn_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
     ],
     "return_type": {
-      "value": "int8x8_t"
+      "value": "int8x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116304,23 +321192,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_u16",
+    "name": "vtrn_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x4_t"
+      "value": "uint16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116331,23 +321222,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_u32",
+    "name": "vtrn_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
     ],
     "return_type": {
-      "value": "uint32x2_t"
+      "value": "uint32x2x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116358,23 +321252,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2_u8",
+    "name": "vtrn_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x8_t"
+      "value": "uint8x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116385,23 +321282,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_f16",
+    "name": "vtrnq_f16",
     "arguments": [
       "float16x8_t a",
       "float16x8_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "float16x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116412,23 +321312,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_f32",
+    "name": "vtrnq_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "float32x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116439,50 +321342,86 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_f64",
+    "name": "vtrnq_p16",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "poly16x8_t a",
+      "poly16x8_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "poly16x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_p16",
+    "name": "vtrnq_p8",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "poly8x16x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "TRN1",
+        "TRN2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vtrnq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116493,50 +321432,56 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_p64",
+    "name": "vtrnq_s32",
     "arguments": [
-      "poly64x2_t a",
-      "poly64x2_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "poly64x2_t"
+      "value": "int32x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_p8",
+    "name": "vtrnq_s8",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int8x16x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116547,23 +321492,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_s16",
+    "name": "vtrnq_u16",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116574,23 +321522,26 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_s32",
+    "name": "vtrnq_u32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "int32x4_t"
+      "value": "uint32x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116601,165 +321552,178 @@
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_s64",
+    "name": "vtrnq_u8",
     "arguments": [
-      "int64x2_t a",
-      "int64x2_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "int64x2_t"
+      "value": "uint8x16x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "TRN1",
+        "TRN2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_s8",
+    "name": "vtst_p64",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "poly64x1_t a",
+      "poly64x1_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Dm"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_u16",
+    "name": "vtst_p8",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "poly8x8_t a",
+      "poly8x8_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_u32",
+    "name": "vtst_s16",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "uint32x4_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_u64",
+    "name": "vtst_s32",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp2q_u8",
+    "name": "vtst_s64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b"
+      "int64x1_t a",
+      "int64x1_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Dm"
       }
     },
     "Architectures": [
@@ -116767,19 +321731,48 @@
     ],
     "instructions": [
       [
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_f16",
+    "name": "vtst_s8",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "float16x4x2_t"
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "v7",
+      "A32",
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMTST"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vtst_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116796,20 +321789,19 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_f32",
+    "name": "vtst_u32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "float32x2x2_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116826,50 +321818,46 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_p16",
+    "name": "vtst_u64",
     "arguments": [
-      "poly16x4_t a",
-      "poly16x4_t b"
+      "uint64x1_t a",
+      "uint64x1_t b"
     ],
     "return_type": {
-      "value": "poly16x4x2_t"
+      "value": "uint64x1_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_p8",
+    "name": "vtst_u8",
     "arguments": [
-      "poly8x8_t a",
-      "poly8x8_t b"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "poly8x8x2_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -116886,87 +321874,108 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_s16",
+    "name": "vtstd_s64",
     "arguments": [
-      "int16x4_t a",
-      "int16x4_t b"
+      "int64_t a",
+      "int64_t b"
     ],
     "return_type": {
-      "value": "int16x4x2_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Dm"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_s32",
+    "name": "vtstd_u64",
     "arguments": [
-      "int32x2_t a",
-      "int32x2_t b"
+      "uint64_t a",
+      "uint64_t b"
     ],
     "return_type": {
-      "value": "int32x2x2_t"
+      "value": "uint64_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Dn"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Dm"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMTST"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vtstq_p64",
+    "arguments": [
+      "poly64x2_t a",
+      "poly64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_s8",
+    "name": "vtstq_p8",
     "arguments": [
-      "int8x8_t a",
-      "int8x8_t b"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "int8x8x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -116976,27 +321985,26 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_u16",
+    "name": "vtstq_s16",
     "arguments": [
-      "uint16x4_t a",
-      "uint16x4_t b"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x4x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -117006,27 +322014,26 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_u32",
+    "name": "vtstq_s32",
     "arguments": [
-      "uint32x2_t a",
-      "uint32x2_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint32x2x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -117036,27 +322043,53 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzp_u8",
+    "name": "vtstq_s64",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "uint8x8x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.8B"
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "CMTST"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vtstq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -117066,20 +322099,19 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_f16",
+    "name": "vtstq_u16",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "float16x8x2_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -117096,20 +322128,19 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_f32",
+    "name": "vtstq_u32",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "float32x4x2_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -117126,50 +322157,46 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_p16",
+    "name": "vtstq_u64",
     "arguments": [
-      "poly16x8_t a",
-      "poly16x8_t b"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "poly16x8x2_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_p8",
+    "name": "vtstq_u8",
     "arguments": [
-      "poly8x16_t a",
-      "poly8x16_t b"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "poly8x16x2_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -117186,170 +322213,522 @@
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "CMTST"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_s16",
+    "name": "vuqadd_s16",
+    "arguments": [
+      "int16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4H"
+      },
+      "b": {
+        "register": "Vn.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqadd_s32",
+    "arguments": [
+      "int32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2S"
+      },
+      "b": {
+        "register": "Vn.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqadd_s64",
+    "arguments": [
+      "int64x1_t a",
+      "uint64x1_t b"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqadd_s8",
+    "arguments": [
+      "int8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8B"
+      },
+      "b": {
+        "register": "Vn.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddb_s8",
+    "arguments": [
+      "int8_t a",
+      "uint8_t b"
+    ],
+    "return_type": {
+      "value": "int8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Bd"
+      },
+      "b": {
+        "register": "Bn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddd_s64",
+    "arguments": [
+      "int64_t a",
+      "uint64_t b"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dd"
+      },
+      "b": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddh_s16",
+    "arguments": [
+      "int16_t a",
+      "uint16_t b"
+    ],
+    "return_type": {
+      "value": "int16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Hd"
+      },
+      "b": {
+        "register": "Hn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.8H"
+      },
+      "b": {
+        "register": "Vn.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddq_s32",
+    "arguments": [
+      "int32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "int32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.4S"
+      },
+      "b": {
+        "register": "Vn.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddq_s64",
+    "arguments": [
+      "int64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.2D"
+      },
+      "b": {
+        "register": "Vn.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqaddq_s8",
+    "arguments": [
+      "int8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vd.16B"
+      },
+      "b": {
+        "register": "Vn.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vuqadds_s32",
+    "arguments": [
+      "int32_t a",
+      "uint32_t b"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sd"
+      },
+      "b": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "SUQADD"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vusdot_lane_s32",
     "arguments": [
-      "int16x8_t a",
-      "int16x8_t b"
+      "int32x2_t r",
+      "uint8x8_t a",
+      "int8x8_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int16x8x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "USDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_s32",
+    "name": "vusdot_laneq_s32",
     "arguments": [
-      "int32x4_t a",
-      "int32x4_t b"
+      "int32x2_t r",
+      "uint8x8_t a",
+      "int8x16_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "int32x4x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "USDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_s8",
+    "name": "vusdot_s32",
     "arguments": [
-      "int8x16_t a",
-      "int8x16_t b"
+      "int32x2_t r",
+      "uint8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "int8x16x2_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm.16B"
+        "register": "Vm.8B"
+      },
+      "r": {
+        "register": "Vd.2S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "USDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_u16",
+    "name": "vusdotq_lane_s32",
     "arguments": [
-      "uint16x8_t a",
-      "uint16x8_t b"
+      "int32x4_t r",
+      "uint8x16_t a",
+      "int8x8_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint16x8x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "USDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_u32",
+    "name": "vusdotq_laneq_s32",
     "arguments": [
-      "uint32x4_t a",
-      "uint32x4_t b"
+      "int32x4_t r",
+      "uint8x16_t a",
+      "int8x16_t b",
+      "const int lane"
     ],
     "return_type": {
-      "value": "uint32x4x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4S"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm.4S"
+        "register": "Vm.4B"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
-      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "USDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vuzpq_u8",
+    "name": "vusdotq_s32",
     "arguments": [
+      "int32x4_t r",
       "uint8x16_t a",
-      "uint8x16_t b"
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint8x16x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -117357,53 +322736,56 @@
       },
       "b": {
         "register": "Vm.16B"
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
-      "v7",
       "A32",
       "A64"
     ],
     "instructions": [
       [
-        "UZP1",
-        "UZP2"
+        "USDOT"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vxarq_u64",
+    "name": "vusmmlaq_s32",
     "arguments": [
-      "uint64x2_t a",
-      "uint64x2_t b",
-      "const int imm6"
+      "int32x4_t r",
+      "uint8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "uint64x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.16B"
       },
-      "b": {},
-      "imm6": {
-        "minimum": 0,
-        "maximum": 63
+      "b": {
+        "register": "Vm.16B"
+      },
+      "r": {
+        "register": "Vd.4S"
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "XAR"
+        "USMMLA"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_f16",
+    "name": "vuzp1_f16",
     "arguments": [
       "float16x4_t a",
       "float16x4_t b"
@@ -117424,13 +322806,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_f32",
+    "name": "vuzp1_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b"
@@ -117451,13 +322833,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_p16",
+    "name": "vuzp1_p16",
     "arguments": [
       "poly16x4_t a",
       "poly16x4_t b"
@@ -117478,13 +322860,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_p8",
+    "name": "vuzp1_p8",
     "arguments": [
       "poly8x8_t a",
       "poly8x8_t b"
@@ -117505,13 +322887,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_s16",
+    "name": "vuzp1_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
@@ -117532,13 +322914,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_s32",
+    "name": "vuzp1_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
@@ -117559,13 +322941,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_s8",
+    "name": "vuzp1_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
@@ -117586,13 +322968,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_u16",
+    "name": "vuzp1_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
@@ -117613,13 +322995,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_u32",
+    "name": "vuzp1_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
@@ -117640,13 +323022,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1_u8",
+    "name": "vuzp1_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b"
@@ -117667,13 +323049,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_f16",
+    "name": "vuzp1q_f16",
     "arguments": [
       "float16x8_t a",
       "float16x8_t b"
@@ -117694,13 +323076,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_f32",
+    "name": "vuzp1q_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
@@ -117721,13 +323103,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_f64",
+    "name": "vuzp1q_f64",
     "arguments": [
       "float64x2_t a",
       "float64x2_t b"
@@ -117748,13 +323130,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_p16",
+    "name": "vuzp1q_p16",
     "arguments": [
       "poly16x8_t a",
       "poly16x8_t b"
@@ -117775,13 +323157,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_p64",
+    "name": "vuzp1q_p64",
     "arguments": [
       "poly64x2_t a",
       "poly64x2_t b"
@@ -117802,13 +323184,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_p8",
+    "name": "vuzp1q_p8",
     "arguments": [
       "poly8x16_t a",
       "poly8x16_t b"
@@ -117829,13 +323211,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_s16",
+    "name": "vuzp1q_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
@@ -117856,13 +323238,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_s32",
+    "name": "vuzp1q_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
@@ -117883,13 +323265,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_s64",
+    "name": "vuzp1q_s64",
     "arguments": [
       "int64x2_t a",
       "int64x2_t b"
@@ -117910,13 +323292,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_s8",
+    "name": "vuzp1q_s8",
     "arguments": [
       "int8x16_t a",
       "int8x16_t b"
@@ -117937,13 +323319,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_u16",
+    "name": "vuzp1q_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b"
@@ -117964,13 +323346,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_u32",
+    "name": "vuzp1q_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b"
@@ -117991,13 +323373,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_u64",
+    "name": "vuzp1q_u64",
     "arguments": [
       "uint64x2_t a",
       "uint64x2_t b"
@@ -118018,13 +323400,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip1q_u8",
+    "name": "vuzp1q_u8",
     "arguments": [
       "uint8x16_t a",
       "uint8x16_t b"
@@ -118045,13 +323427,13 @@
     ],
     "instructions": [
       [
-        "ZIP1"
+        "UZP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_f16",
+    "name": "vuzp2_f16",
     "arguments": [
       "float16x4_t a",
       "float16x4_t b"
@@ -118072,13 +323454,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_f32",
+    "name": "vuzp2_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b"
@@ -118099,13 +323481,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_p16",
+    "name": "vuzp2_p16",
     "arguments": [
       "poly16x4_t a",
       "poly16x4_t b"
@@ -118126,13 +323508,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_p8",
+    "name": "vuzp2_p8",
     "arguments": [
       "poly8x8_t a",
       "poly8x8_t b"
@@ -118153,13 +323535,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_s16",
+    "name": "vuzp2_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
@@ -118180,13 +323562,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_s32",
+    "name": "vuzp2_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
@@ -118207,13 +323589,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_s8",
+    "name": "vuzp2_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
@@ -118234,13 +323616,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_u16",
+    "name": "vuzp2_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
@@ -118261,13 +323643,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_u32",
+    "name": "vuzp2_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
@@ -118288,13 +323670,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2_u8",
+    "name": "vuzp2_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b"
@@ -118315,13 +323697,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_f16",
+    "name": "vuzp2q_f16",
     "arguments": [
       "float16x8_t a",
       "float16x8_t b"
@@ -118342,13 +323724,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_f32",
+    "name": "vuzp2q_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
@@ -118369,13 +323751,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_f64",
+    "name": "vuzp2q_f64",
     "arguments": [
       "float64x2_t a",
       "float64x2_t b"
@@ -118396,13 +323778,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_p16",
+    "name": "vuzp2q_p16",
     "arguments": [
       "poly16x8_t a",
       "poly16x8_t b"
@@ -118423,13 +323805,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_p64",
+    "name": "vuzp2q_p64",
     "arguments": [
       "poly64x2_t a",
       "poly64x2_t b"
@@ -118450,13 +323832,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_p8",
+    "name": "vuzp2q_p8",
     "arguments": [
       "poly8x16_t a",
       "poly8x16_t b"
@@ -118477,13 +323859,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_s16",
+    "name": "vuzp2q_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
@@ -118504,13 +323886,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_s32",
+    "name": "vuzp2q_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
@@ -118531,13 +323913,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_s64",
+    "name": "vuzp2q_s64",
     "arguments": [
       "int64x2_t a",
       "int64x2_t b"
@@ -118558,13 +323940,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_s8",
+    "name": "vuzp2q_s8",
     "arguments": [
       "int8x16_t a",
       "int8x16_t b"
@@ -118585,13 +323967,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_u16",
+    "name": "vuzp2q_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b"
@@ -118612,13 +323994,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_u32",
+    "name": "vuzp2q_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b"
@@ -118639,13 +324021,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_u64",
+    "name": "vuzp2q_u64",
     "arguments": [
       "uint64x2_t a",
       "uint64x2_t b"
@@ -118666,13 +324048,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip2q_u8",
+    "name": "vuzp2q_u8",
     "arguments": [
       "uint8x16_t a",
       "uint8x16_t b"
@@ -118693,13 +324075,13 @@
     ],
     "instructions": [
       [
-        "ZIP2"
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_f16",
+    "name": "vuzp_f16",
     "arguments": [
       "float16x4_t a",
       "float16x4_t b"
@@ -118722,14 +324104,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_f32",
+    "name": "vuzp_f32",
     "arguments": [
       "float32x2_t a",
       "float32x2_t b"
@@ -118752,14 +324134,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_p16",
+    "name": "vuzp_p16",
     "arguments": [
       "poly16x4_t a",
       "poly16x4_t b"
@@ -118782,14 +324164,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_p8",
+    "name": "vuzp_p8",
     "arguments": [
       "poly8x8_t a",
       "poly8x8_t b"
@@ -118812,14 +324194,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_s16",
+    "name": "vuzp_s16",
     "arguments": [
       "int16x4_t a",
       "int16x4_t b"
@@ -118842,14 +324224,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_s32",
+    "name": "vuzp_s32",
     "arguments": [
       "int32x2_t a",
       "int32x2_t b"
@@ -118872,14 +324254,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_s8",
+    "name": "vuzp_s8",
     "arguments": [
       "int8x8_t a",
       "int8x8_t b"
@@ -118902,14 +324284,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_u16",
+    "name": "vuzp_u16",
     "arguments": [
       "uint16x4_t a",
       "uint16x4_t b"
@@ -118932,14 +324314,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_u32",
+    "name": "vuzp_u32",
     "arguments": [
       "uint32x2_t a",
       "uint32x2_t b"
@@ -118962,14 +324344,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzip_u8",
+    "name": "vuzp_u8",
     "arguments": [
       "uint8x8_t a",
       "uint8x8_t b"
@@ -118992,14 +324374,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_f16",
+    "name": "vuzpq_f16",
     "arguments": [
       "float16x8_t a",
       "float16x8_t b"
@@ -119022,14 +324404,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_f32",
+    "name": "vuzpq_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
@@ -119052,14 +324434,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_p16",
+    "name": "vuzpq_p16",
     "arguments": [
       "poly16x8_t a",
       "poly16x8_t b"
@@ -119082,14 +324464,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_p8",
+    "name": "vuzpq_p8",
     "arguments": [
       "poly8x16_t a",
       "poly8x16_t b"
@@ -119112,14 +324494,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_s16",
+    "name": "vuzpq_s16",
     "arguments": [
       "int16x8_t a",
       "int16x8_t b"
@@ -119142,14 +324524,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_s32",
+    "name": "vuzpq_s32",
     "arguments": [
       "int32x4_t a",
       "int32x4_t b"
@@ -119172,14 +324554,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_s8",
+    "name": "vuzpq_s8",
     "arguments": [
       "int8x16_t a",
       "int8x16_t b"
@@ -119202,14 +324584,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_u16",
+    "name": "vuzpq_u16",
     "arguments": [
       "uint16x8_t a",
       "uint16x8_t b"
@@ -119232,14 +324614,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_u32",
+    "name": "vuzpq_u32",
     "arguments": [
       "uint32x4_t a",
       "uint32x4_t b"
@@ -119262,14 +324644,14 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vzipq_u8",
+    "name": "vuzpq_u8",
     "arguments": [
       "uint8x16_t a",
       "uint8x16_t b"
@@ -119292,14 +324674,46 @@
     ],
     "instructions": [
       [
-        "ZIP1",
-        "ZIP2"
+        "UZP1",
+        "UZP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamin_f16",
+    "name": "vxarq_u64",
+    "arguments": [
+      "uint64x2_t a",
+      "uint64x2_t b",
+      "const int imm6"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      },
+      "imm6": {
+        "minimum": 0,
+        "maximum": 63
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "XAR"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_f16",
     "arguments": [
       "float16x4_t a",
       "float16x4_t b"
@@ -119320,26 +324734,26 @@
     ],
     "instructions": [
       [
-        "FAMIN"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vaminq_f16",
+    "name": "vzip1_f32",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -119347,19 +324761,100 @@
     ],
     "instructions": [
       [
-        "FAMIN"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamin_f32",
+    "name": "vzip1_p16",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "poly16x4_t a",
+      "poly16x4_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "poly16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_p8",
+    "arguments": [
+      "poly8x8_t a",
+      "poly8x8_t b"
+    ],
+    "return_type": {
+      "value": "poly8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_s16",
+    "arguments": [
+      "int16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "int16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_s32",
+    "arguments": [
+      "int32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -119374,13 +324869,148 @@
     ],
     "instructions": [
       [
-        "FAMIN"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vaminq_f32",
+    "name": "vzip1_s8",
+    "arguments": [
+      "int8x8_t a",
+      "int8x8_t b"
+    ],
+    "return_type": {
+      "value": "int8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint16x4_t b"
+    ],
+    "return_type": {
+      "value": "uint16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_u32",
+    "arguments": [
+      "uint32x2_t a",
+      "uint32x2_t b"
+    ],
+    "return_type": {
+      "value": "uint32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1_u8",
+    "arguments": [
+      "uint8x8_t a",
+      "uint8x8_t b"
+    ],
+    "return_type": {
+      "value": "uint8x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8B"
+      },
+      "b": {
+        "register": "Vm.8B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_f32",
     "arguments": [
       "float32x4_t a",
       "float32x4_t b"
@@ -119401,13 +325031,13 @@
     ],
     "instructions": [
       [
-        "FAMIN"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vaminq_f64",
+    "name": "vzip1q_f64",
     "arguments": [
       "float64x2_t a",
       "float64x2_t b"
@@ -119428,26 +325058,26 @@
     ],
     "instructions": [
       [
-        "FAMIN"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamax_f16",
+    "name": "vzip1q_p16",
     "arguments": [
-      "float16x4_t a",
-      "float16x4_t b"
+      "poly16x8_t a",
+      "poly16x8_t b"
     ],
     "return_type": {
-      "value": "float16x4_t"
+      "value": "poly16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.4H"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm.4H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -119455,19 +325085,73 @@
     ],
     "instructions": [
       [
-        "FAMAX"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamaxq_f16",
+    "name": "vzip1q_p64",
     "arguments": [
-      "float16x8_t a",
-      "float16x8_t b"
+      "poly64x2_t a",
+      "poly64x2_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "poly8x16_t b"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_s16",
+    "arguments": [
+      "int16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -119482,26 +325166,26 @@
     ],
     "instructions": [
       [
-        "FAMAX"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamax_f32",
+    "name": "vzip1q_s32",
     "arguments": [
-      "float32x2_t a",
-      "float32x2_t b"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "float32x2_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2S"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm.2S"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -119509,19 +325193,100 @@
     ],
     "instructions": [
       [
-        "FAMAX"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamaxq_f32",
+    "name": "vzip1q_s64",
     "arguments": [
-      "float32x4_t a",
-      "float32x4_t b"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "float32x4_t"
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_s8",
+    "arguments": [
+      "int8x16_t a",
+      "int8x16_t b"
+    ],
+    "return_type": {
+      "value": "int8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint16x8_t b"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_u32",
+    "arguments": [
+      "uint32x4_t a",
+      "uint32x4_t b"
+    ],
+    "return_type": {
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
@@ -119536,26 +325301,107 @@
     ],
     "instructions": [
       [
-        "FAMAX"
+        "ZIP1"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vamaxq_f64",
+    "name": "vzip1q_u64",
     "arguments": [
-      "float64x2_t a",
-      "float64x2_t b"
+      "uint64x2_t a",
+      "uint64x2_t b"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip1q_u8",
+    "arguments": [
+      "uint8x16_t a",
+      "uint8x16_t b"
+    ],
+    "return_type": {
+      "value": "uint8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip2_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "ZIP2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vzip2_f32",
+    "arguments": [
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "float64x2_t"
+      "value": "float32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.2D"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm.2D"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -119563,34 +325409,26 @@
     ],
     "instructions": [
       [
-        "FAMAX"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_f16",
+    "name": "vzip2_p16",
     "arguments": [
-      "float16x4_t a",
-      "uint8x8_t b",
-      "const int index"
+      "poly16x4_t a",
+      "poly16x4_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -119598,34 +325436,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_s16",
+    "name": "vzip2_p8",
     "arguments": [
-      "int16x4_t a",
-      "uint8x8_t b",
-      "const int index"
+      "poly8x8_t a",
+      "poly8x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "poly8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -119633,34 +325463,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_u16",
+    "name": "vzip2_s16",
     "arguments": [
-      "uint16x4_t a",
-      "uint8x8_t b",
-      "const int index"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "lane": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -119668,34 +325490,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_p16",
+    "name": "vzip2_s32",
     "arguments": [
-      "poly16x4_t a",
-      "uint8x8_t b",
-      "const int index"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "int32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -119703,34 +325517,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_f16",
+    "name": "vzip2_s8",
     "arguments": [
-      "float16x4_t a",
-      "uint8x16_t b",
-      "const int index"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -119738,34 +325544,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_s16",
+    "name": "vzip2_u16",
     "arguments": [
-      "int16x4_t a",
-      "uint8x16_t b",
-      "const int index"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "uint16x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
@@ -119773,34 +325571,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_u16",
+    "name": "vzip2_u32",
     "arguments": [
-      "uint16x4_t a",
-      "uint8x16_t b",
-      "const int index"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint32x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
@@ -119808,34 +325598,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_p16",
+    "name": "vzip2_u8",
     "arguments": [
-      "poly16x4_t a",
-      "uint8x16_t b",
-      "const int index"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
@@ -119843,17 +325625,16 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_f16",
+    "name": "vzip2q_f16",
     "arguments": [
       "float16x8_t a",
-      "uint8x8_t b",
-      "const int index"
+      "float16x8_t b"
     ],
     "return_type": {
       "value": "float16x8_t"
@@ -119863,14 +325644,7 @@
         "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -119878,34 +325652,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_s16",
+    "name": "vzip2q_f32",
     "arguments": [
-      "int16x8_t a",
-      "uint8x8_t b",
-      "const int index"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "float32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -119913,34 +325679,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_u16",
+    "name": "vzip2q_f64",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b",
-      "const int index"
+      "float64x2_t a",
+      "float64x2_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "float64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -119948,17 +325706,16 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_p16",
+    "name": "vzip2q_p16",
     "arguments": [
       "poly16x8_t a",
-      "uint8x8_t b",
-      "const int index"
+      "poly16x8_t b"
     ],
     "return_type": {
       "value": "poly16x8_t"
@@ -119968,14 +325725,7 @@
         "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -119983,34 +325733,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_f16",
+    "name": "vzip2q_p64",
     "arguments": [
-      "float16x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "poly64x2_t a",
+      "poly64x2_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "poly64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -120018,34 +325760,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_s16",
+    "name": "vzip2q_p8",
     "arguments": [
-      "int16x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -120053,34 +325787,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_u16",
+    "name": "vzip2q_s16",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "int16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
         "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -120088,34 +325814,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_u8",
+    "name": "vzip2q_s32",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -120123,34 +325841,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_u8",
+    "name": "vzip2q_s64",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int64x2_t a",
+      "int64x2_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -120158,17 +325868,16 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_s8",
+    "name": "vzip2q_s8",
     "arguments": [
-      "int8x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
       "value": "int8x16_t"
@@ -120178,14 +325887,7 @@
         "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -120193,34 +325895,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_s8",
+    "name": "vzip2q_u16",
     "arguments": [
-      "int8x16_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint16x8_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
@@ -120228,34 +325922,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_p8",
+    "name": "vzip2q_u32",
     "arguments": [
-      "poly8x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint32x4_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
@@ -120263,34 +325949,26 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_p8",
+    "name": "vzip2q_u64",
     "arguments": [
-      "poly8x16_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint64x2_t a",
+      "uint64x2_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "uint64x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2D"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.2D"
       }
     },
     "Architectures": [
@@ -120298,17 +325976,16 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_u8",
+    "name": "vzip2q_u8",
     "arguments": [
-      "uint8x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
       "value": "uint8x16_t"
@@ -120318,14 +325995,7 @@
         "register": "Vn.16B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
@@ -120333,707 +326003,607 @@
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_u8",
+    "name": "vzip_f16",
     "arguments": [
-      "uint8x16_t a",
-      "uint8x16_t b",
-      "const int index"
+      "float16x4_t a",
+      "float16x4_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "float16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_s8",
+    "name": "vzip_f32",
     "arguments": [
-      "int8x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "float32x2_t a",
+      "float32x2_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "float32x2x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_s8",
+    "name": "vzip_p16",
     "arguments": [
-      "int8x16_t a",
-      "uint8x16_t b",
-      "const int index"
+      "poly16x4_t a",
+      "poly16x4_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "poly16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_laneq_p8",
+    "name": "vzip_p8",
     "arguments": [
       "poly8x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "poly8x8_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "poly8x8x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.8B"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_p8",
+    "name": "vzip_s16",
     "arguments": [
-      "poly8x16_t a",
-      "uint8x16_t b",
-      "const int index"
+      "int16x4_t a",
+      "int16x4_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "int16x4x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.16B"
+        "register": "Vn.4H"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
-      },
-      "r": {
-        "register": "Vd.16B"
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_laneq_p16",
+    "name": "vzip_s32",
     "arguments": [
-      "poly16x8_t a",
-      "uint8x16_t b",
-      "const int index"
+      "int32x2_t a",
+      "int32x2_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "int32x2x2_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.2S"
       },
       "b": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 7
-      },
-      "r": {
-        "register": "Vd.8H"
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI2"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_u8",
+    "name": "vzip_s8",
     "arguments": [
-      "uint8x16_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "int8x8_t a",
+      "int8x8_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "int8x8x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn.16B"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 0
+      "a": {
+        "register": "Vn.8B"
       },
-      "r": {
-        "register": "Vd.16B"
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_u8",
+    "name": "vzip_u16",
     "arguments": [
-      "uint8x16_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "uint16x4_t a",
+      "uint16x4_t b"
     ],
     "return_type": {
-      "value": "uint8x16_t"
+      "value": "uint16x4x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn.16B"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.4H"
       },
-      "r": {
-        "register": "Vd.16B"
+      "b": {
+        "register": "Vm.4H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_s8",
+    "name": "vzip_u32",
     "arguments": [
-      "int8x16_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "uint32x2_t a",
+      "uint32x2_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint32x2x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn.16B"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 0
+      "a": {
+        "register": "Vn.2S"
       },
-      "r": {
-        "register": "Vd.16B"
+      "b": {
+        "register": "Vm.2S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_s8",
+    "name": "vzip_u8",
     "arguments": [
-      "int8x16_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "uint8x8_t a",
+      "uint8x8_t b"
     ],
     "return_type": {
-      "value": "int8x16_t"
+      "value": "uint8x8x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn.16B"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.8B"
       },
-      "r": {
-        "register": "Vd.16B"
+      "b": {
+        "register": "Vm.8B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_p8",
+    "name": "vzipq_f16",
     "arguments": [
-      "poly8x16_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "float16x8_t a",
+      "float16x8_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float16x8x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn.16B"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 0
+      "a": {
+        "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.16B"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_p8",
+    "name": "vzipq_f32",
     "arguments": [
-      "poly8x16_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "float32x4_t a",
+      "float32x4_t b"
     ],
     "return_type": {
-      "value": "poly8x16_t"
+      "value": "float32x4x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn.16B"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.4S"
       },
-      "r": {
-        "register": "Vd.16B"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_u16_x2",
+    "name": "vzipq_p16",
     "arguments": [
-      "uint16x8x2_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "poly16x8_t a",
+      "poly16x8_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly16x8x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_u16_x2",
+    "name": "vzipq_p8",
     "arguments": [
-      "uint16x8x2_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "poly8x16_t a",
+      "poly8x16_t b"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "poly8x16x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vn.16B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_s16_x2",
+    "name": "vzipq_s16",
     "arguments": [
-      "int16x8x2_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "int16x8_t a",
+      "int16x8_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int16x8x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_s16_x2",
+    "name": "vzipq_s32",
     "arguments": [
-      "int16x8x2_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "int32x4_t a",
+      "int32x4_t b"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int32x4x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vn.4S"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_f16_x2",
+    "name": "vzipq_s8",
     "arguments": [
-      "float16x8x2_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "int8x16_t a",
+      "int8x16_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "int8x16x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.16B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_f16_x2",
+    "name": "vzipq_u16",
     "arguments": [
-      "float16x8x2_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "uint16x8_t a",
+      "uint16x8_t b"
     ],
     "return_type": {
-      "value": "float16x8_t"
+      "value": "uint16x8x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vn.8H"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.8H"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_lane_p16_x2",
+    "name": "vzipq_u32",
     "arguments": [
-      "poly16x8x2_t vn",
-      "uint8x8_t vm",
-      "const int index"
+      "uint32x4_t a",
+      "uint32x4_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint32x4x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 1
+      "a": {
+        "register": "Vn.4S"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.4S"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti4q_laneq_p16_x2",
+    "name": "vzipq_u8",
     "arguments": [
-      "poly16x8x2_t vn",
-      "uint8x16_t vm",
-      "const int index"
+      "uint8x16_t a",
+      "uint8x16_t b"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "uint8x16x2_t"
     },
     "Arguments_Preparation": {
-      "vn": {
-        "register": "Vn1.8H"
-      },
-      "vm": {
-        "register": "Vm"
-      },
-      "index": {
-        "minimum": 0,
-        "maximum": 3
+      "a": {
+        "register": "Vn.16B"
       },
-      "r": {
-        "register": "Vd.8H"
+      "b": {
+        "register": "Vm.16B"
       }
     },
     "Architectures": [
+      "v7",
+      "A32",
       "A64"
     ],
     "instructions": [
       [
-        "LUTI4"
+        "ZIP1",
+        "ZIP2"
       ]
     ]
   },

From 1c57120d413753d210d9966f3864fe8ce069f70d Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Fri, 16 Jan 2026 12:46:33 +0000
Subject: [PATCH 239/326] stdarch-verify: support sve

Co-authored-by: Adam Gemmell <Adam.Gemmell@arm.com>
Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
---
 crates/stdarch-verify/src/lib.rs   |  67 ++++++++--
 crates/stdarch-verify/tests/arm.rs | 195 ++++++++++++++++++++++++-----
 2 files changed, 225 insertions(+), 37 deletions(-)

diff --git a/crates/stdarch-verify/src/lib.rs b/crates/stdarch-verify/src/lib.rs
index c81f5f45bc..f7304ab326 100644
--- a/crates/stdarch-verify/src/lib.rs
+++ b/crates/stdarch-verify/src/lib.rs
@@ -120,6 +120,13 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
                 );
             }
 
+            // Newer intrinsics don't have `rustc_legacy_const_generics` - assume they belong at
+            // the end of the argument list
+            if required_const.is_empty() && legacy_const_generics.is_empty() {
+                legacy_const_generics =
+                    (arguments.len()..(arguments.len() + const_arguments.len())).collect();
+            }
+
             // The list of required consts, used to verify the arguments, comes from either the
             // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute.
             let required_const = if required_const.is_empty() {
@@ -136,14 +143,14 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
                 arguments.insert(idx, ty);
             }
 
-            // strip leading underscore from fn name when building a test
-            // _mm_foo -> mm_foo such that the test name is test_mm_foo.
-            let test_name_string = format!("{name}");
-            let mut test_name_id = test_name_string.as_str();
-            while test_name_id.starts_with('_') {
-                test_name_id = &test_name_id[1..];
-            }
-            let has_test = tests.contains(&format!("test_{test_name_id}"));
+            // Strip leading underscore from fn name when building a test
+            // `_mm_foo` -> `mm_foo` such that the test name is `test_mm_foo`.
+            let test_name = name.to_string();
+            let test_name = test_name.trim_start_matches('_');
+            let has_test = tests.contains(&format!("test_{test_name}"))
+                // SVE load/store tests start with `test` or `_with_`
+                || tests.iter().any(|t| t.starts_with(&format!("test_{test_name}"))
+                                        || t.ends_with(&format!("_with_{test_name}")));
 
             let doc = find_doc(&f.attrs);
 
@@ -347,6 +354,50 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream {
             "v4f32" => quote! { &v4f32 },
             "v2f64" => quote! { &v2f64 },
 
+            "svbool_t" => quote! { &SVBOOL },
+            "svint8_t" => quote! { &SVI8 },
+            "svint8x2_t" => quote! { &SVI8X2 },
+            "svint8x3_t" => quote! { &SVI8X3 },
+            "svint8x4_t" => quote! { &SVI8X4 },
+            "svint16_t" => quote! { &SVI16 },
+            "svint16x2_t" => quote! { &SVI16X2 },
+            "svint16x3_t" => quote! { &SVI16X3 },
+            "svint16x4_t" => quote! { &SVI16X4 },
+            "svint32_t" => quote! { &SVI32 },
+            "svint32x2_t" => quote! { &SVI32X2 },
+            "svint32x3_t" => quote! { &SVI32X3 },
+            "svint32x4_t" => quote! { &SVI32X4 },
+            "svint64_t" => quote! { &SVI64 },
+            "svint64x2_t" => quote! { &SVI64X2 },
+            "svint64x3_t" => quote! { &SVI64X3 },
+            "svint64x4_t" => quote! { &SVI64X4 },
+            "svuint8_t" => quote! { &SVU8 },
+            "svuint8x2_t" => quote! { &SVU8X2 },
+            "svuint8x3_t" => quote! { &SVU8X3 },
+            "svuint8x4_t" => quote! { &SVU8X4 },
+            "svuint16_t" => quote! { &SVU16 },
+            "svuint16x2_t" => quote! { &SVU16X2 },
+            "svuint16x3_t" => quote! { &SVU16X3 },
+            "svuint16x4_t" => quote! { &SVU16X4 },
+            "svuint32_t" => quote! { &SVU32 },
+            "svuint32x2_t" => quote! { &SVU32X2 },
+            "svuint32x3_t" => quote! { &SVU32X3 },
+            "svuint32x4_t" => quote! { &SVU32X4 },
+            "svuint64_t" => quote! { &SVU64 },
+            "svuint64x2_t" => quote! { &SVU64X2 },
+            "svuint64x3_t" => quote! { &SVU64X3 },
+            "svuint64x4_t" => quote! { &SVU64X4 },
+            "svfloat32_t" => quote! { &SVF32 },
+            "svfloat32x2_t" => quote! { &SVF32X2 },
+            "svfloat32x3_t" => quote! { &SVF32X3 },
+            "svfloat32x4_t" => quote! { &SVF32X4 },
+            "svfloat64_t" => quote! { &SVF64 },
+            "svfloat64x2_t" => quote! { &SVF64X2 },
+            "svfloat64x3_t" => quote! { &SVF64X3 },
+            "svfloat64x4_t" => quote! { &SVF64X4 },
+            "svprfop" => quote! { &SVPRFOP },
+            "svpattern" => quote! { &SVPATTERN },
+
             // Generic types
             "T" => quote! { &GENERICT },
             "U" => quote! { &GENERICU },
diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs
index c5744de3f6..a37af2222a 100644
--- a/crates/stdarch-verify/tests/arm.rs
+++ b/crates/stdarch-verify/tests/arm.rs
@@ -16,6 +16,7 @@ struct Function {
     doc: &'static str,
 }
 
+static BOOL: Type = Type::PrimBool;
 static F16: Type = Type::PrimFloat(16);
 static F32: Type = Type::PrimFloat(32);
 static F64: Type = Type::PrimFloat(64);
@@ -28,6 +29,7 @@ static U32: Type = Type::PrimUnsigned(32);
 static U64: Type = Type::PrimUnsigned(64);
 static U8: Type = Type::PrimUnsigned(8);
 static NEVER: Type = Type::Never;
+static VOID: Type = Type::Void;
 static GENERICT: Type = Type::GenericParam("T");
 static GENERICU: Type = Type::GenericParam("U");
 
@@ -151,19 +153,78 @@ static U8X8X2: Type = Type::U(8, 8, 2);
 static U8X8X3: Type = Type::U(8, 8, 3);
 static U8X8X4: Type = Type::U(8, 8, 4);
 
+static SVBOOL: Type = Type::Pred(1);
+static SVBOOLX2: Type = Type::Pred(2);
+static SVBOOLX3: Type = Type::Pred(3);
+static SVBOOLX4: Type = Type::Pred(4);
+static SVCOUNT: Type = Type::Pred(1);
+static SVF16: Type = Type::SVF(16, 1);
+static SVF16X2: Type = Type::SVF(16, 2);
+static SVF16X3: Type = Type::SVF(16, 3);
+static SVF16X4: Type = Type::SVF(16, 4);
+static SVF32: Type = Type::SVF(32, 1);
+static SVF32X2: Type = Type::SVF(32, 2);
+static SVF32X3: Type = Type::SVF(32, 3);
+static SVF32X4: Type = Type::SVF(32, 4);
+static SVF64: Type = Type::SVF(64, 1);
+static SVF64X2: Type = Type::SVF(64, 2);
+static SVF64X3: Type = Type::SVF(64, 3);
+static SVF64X4: Type = Type::SVF(64, 4);
+static SVI8: Type = Type::SVI(8, 1);
+static SVI8X2: Type = Type::SVI(8, 2);
+static SVI8X3: Type = Type::SVI(8, 3);
+static SVI8X4: Type = Type::SVI(8, 4);
+static SVI16: Type = Type::SVI(16, 1);
+static SVI16X2: Type = Type::SVI(16, 2);
+static SVI16X3: Type = Type::SVI(16, 3);
+static SVI16X4: Type = Type::SVI(16, 4);
+static SVI32: Type = Type::SVI(32, 1);
+static SVI32X2: Type = Type::SVI(32, 2);
+static SVI32X3: Type = Type::SVI(32, 3);
+static SVI32X4: Type = Type::SVI(32, 4);
+static SVI64: Type = Type::SVI(64, 1);
+static SVI64X2: Type = Type::SVI(64, 2);
+static SVI64X3: Type = Type::SVI(64, 3);
+static SVI64X4: Type = Type::SVI(64, 4);
+static SVU8: Type = Type::SVU(8, 1);
+static SVU8X2: Type = Type::SVU(8, 2);
+static SVU8X3: Type = Type::SVU(8, 3);
+static SVU8X4: Type = Type::SVU(8, 4);
+static SVU16: Type = Type::SVU(16, 1);
+static SVU16X2: Type = Type::SVU(16, 2);
+static SVU16X3: Type = Type::SVU(16, 3);
+static SVU16X4: Type = Type::SVU(16, 4);
+static SVU32: Type = Type::SVU(32, 1);
+static SVU32X2: Type = Type::SVU(32, 2);
+static SVU32X3: Type = Type::SVU(32, 3);
+static SVU32X4: Type = Type::SVU(32, 4);
+static SVU64: Type = Type::SVU(64, 1);
+static SVU64X2: Type = Type::SVU(64, 2);
+static SVU64X3: Type = Type::SVU(64, 3);
+static SVU64X4: Type = Type::SVU(64, 4);
+static SVPRFOP: Type = Type::Enum("svprfop");
+static SVPATTERN: Type = Type::Enum("svpattern");
+
 #[derive(Debug, Copy, Clone, PartialEq)]
 enum Type {
+    Void,
+    PrimBool,
     PrimFloat(u8),
     PrimSigned(u8),
     PrimUnsigned(u8),
     PrimPoly(u8),
     MutPtr(&'static Type),
     ConstPtr(&'static Type),
+    Enum(&'static str),
     GenericParam(&'static str),
     I(u8, u8, u8),
     U(u8, u8, u8),
     P(u8, u8, u8),
     F(u8, u8, u8),
+    Pred(u8),
+    SVI(u8, u8),
+    SVU(u8, u8),
+    SVF(u8, u8),
     Never,
 }
 
@@ -182,19 +243,18 @@ fn verify_all_signatures() {
 
     let mut all_valid = true;
     for rust in FUNCTIONS {
+        // Most SVE intrinsics just rely on the intrinsics test tool for validation
         if !rust.has_test {
-            if !SKIP_RUNTIME_TESTS.contains(&rust.name) {
-                println!(
-                    "missing run-time test named `test_{}` for `{}`",
-                    {
-                        let mut id = rust.name;
-                        while id.starts_with('_') {
-                            id = &id[1..];
-                        }
-                        id
-                    },
-                    rust.name
-                );
+            if !SKIP_RUNTIME_TESTS.contains(&rust.name)
+                // Most run-time tests are handled by the intrinsic-test tool, except for
+                // load/stores (which have generated tests)
+                && (!rust.name.starts_with("sv") || rust.name.starts_with("svld")
+                    || rust.name.starts_with("svst"))
+                // The load/store test generator can't handle these cases yet
+                && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset"))
+                && !(rust.name.starts_with("svldff1") && rust.name.contains("gather"))
+            {
+                println!("missing run-time test for `{}`", rust.name);
                 all_valid = false;
             }
         }
@@ -269,12 +329,21 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
     let mut nconst = 0;
     let iter = rust.arguments.iter().zip(&arm.arguments).enumerate();
     for (i, (rust_ty, (arm, arm_const))) in iter {
-        if *rust_ty != arm {
-            bail!("mismatched arguments: {rust_ty:?} != {arm:?}")
+        match (*rust_ty, arm) {
+            // SVE uses generic type parameters to handle void pointers
+            (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (),
+            // SVE const generics use i32 over u64 for usability reasons
+            (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => {
+                ()
+            }
+            // svset doesn't have its const argument last as we assumed when building the Function
+            _ if rust.name.starts_with("svset") => (),
+            (x, y) if x == y => (),
+            _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"),
         }
         if *arm_const {
             nconst += 1;
-            if !rust.required_const.contains(&i) {
+            if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") {
                 bail!("argument const mismatch");
             }
         }
@@ -283,7 +352,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
         bail!("wrong number of const arguments");
     }
 
-    if rust.instrs.is_empty() {
+    if rust.instrs.is_empty() && arm.instruction != "" {
         bail!(
             "instruction not listed for `{}`, but arm lists {:?}",
             rust.name,
@@ -322,7 +391,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
     Ok(())
 }
 
-#[derive(PartialEq)]
+#[derive(Debug, PartialEq)]
 struct Intrinsic {
     name: String,
     ret: Option<Type>,
@@ -337,7 +406,7 @@ struct JsonIntrinsic {
     arguments: Vec<String>,
     return_type: ReturnType,
     #[serde(default)]
-    instructions: Vec<Vec<String>>,
+    instructions: Option<Vec<Vec<String>>>,
 }
 
 #[derive(Deserialize, Debug)]
@@ -356,6 +425,8 @@ fn parse_intrinsics(intrinsics: Vec<JsonIntrinsic>) -> HashMap<String, Intrinsic
 
 fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic {
     let name = intr.name;
+    // Remove '[' and ']' so that intrinsics of the form `svwhilerw[_s16]` becomes `svwhilerw_s16`.
+    let name = name.replace('[', "").replace(']', "");
     let ret = if intr.return_type.value == "void" {
         None
     } else {
@@ -364,18 +435,24 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic {
 
     // This ignores multiple instructions and different optional sequences for now to mimic
     // the old HTML scraping behaviour
-    let instruction = intr.instructions.swap_remove(0).swap_remove(0);
+    let instruction = intr
+        .instructions
+        .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0));
 
     let arguments = intr
         .arguments
         .iter()
         .map(|s| {
-            let (ty, konst) = match s.strip_prefix("const") {
-                Some(stripped) => (stripped.trim_start(), true),
-                None => (s.as_str(), false),
+            let ty = if let Some(i) = s.find('*') {
+                &s[..i + 1]
+            } else {
+                s.rsplit_once(' ').unwrap().0.trim_start_matches("const ")
             };
-            let ty = ty.rsplit_once(' ').unwrap().0;
-            (parse_ty(ty), konst)
+            let ty = parse_ty(ty);
+            let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_))
+                || s.starts_with("enum")
+                || s.rsplit_once(" ").unwrap().1.starts_with("imm");
+            (ty, konst)
         })
         .collect::<Vec<_>>();
 
@@ -388,18 +465,27 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic {
 }
 
 fn parse_ty(s: &str) -> Type {
-    let suffix = " const *";
-    if let Some(base) = s.strip_suffix(suffix) {
-        Type::ConstPtr(parse_ty_base(base))
-    } else if let Some(base) = s.strip_suffix(" *") {
-        Type::MutPtr(parse_ty_base(base))
+    if let Some(ty) = s.strip_suffix("*") {
+        let ty = ty.trim();
+        if let Some(ty) = ty.strip_prefix("const") {
+            // SVE intrinsics are west-const (`const int8_t *`)
+            Type::ConstPtr(parse_ty_base(ty))
+        } else if let Some(ty) = ty.strip_suffix("const") {
+            // Neon intrinsics are east-const (`int8_t const *`)
+            Type::ConstPtr(parse_ty_base(ty))
+        } else {
+            Type::MutPtr(parse_ty_base(ty))
+        }
     } else {
         *parse_ty_base(s)
     }
 }
 
 fn parse_ty_base(s: &str) -> &'static Type {
+    let s = s.trim();
     match s {
+        "bool" => &BOOL,
+        "void" => &VOID,
         "float16_t" => &F16,
         "float16x4_t" => &F16X4,
         "float16x4x2_t" => &F16X4X2,
@@ -529,6 +615,57 @@ fn parse_ty_base(s: &str) -> &'static Type {
         "uint8x8x2_t" => &U8X8X2,
         "uint8x8x3_t" => &U8X8X3,
         "uint8x8x4_t" => &U8X8X4,
+        "svbool_t" => &SVBOOL,
+        "svboolx2_t" => &SVBOOLX2,
+        "svboolx3_t" => &SVBOOLX3,
+        "svboolx4_t" => &SVBOOLX4,
+        "svcount_t" => &SVCOUNT,
+        "svfloat16_t" => &SVF16,
+        "svfloat16x2_t" => &SVF16X2,
+        "svfloat16x3_t" => &SVF16X3,
+        "svfloat16x4_t" => &SVF16X4,
+        "svfloat32_t" => &SVF32,
+        "svfloat32x2_t" => &SVF32X2,
+        "svfloat32x3_t" => &SVF32X3,
+        "svfloat32x4_t" => &SVF32X4,
+        "svfloat64_t" => &SVF64,
+        "svfloat64x2_t" => &SVF64X2,
+        "svfloat64x3_t" => &SVF64X3,
+        "svfloat64x4_t" => &SVF64X4,
+        "svint8_t" => &SVI8,
+        "svint8x2_t" => &SVI8X2,
+        "svint8x3_t" => &SVI8X3,
+        "svint8x4_t" => &SVI8X4,
+        "svint16_t" => &SVI16,
+        "svint16x2_t" => &SVI16X2,
+        "svint16x3_t" => &SVI16X3,
+        "svint16x4_t" => &SVI16X4,
+        "svint32_t" => &SVI32,
+        "svint32x2_t" => &SVI32X2,
+        "svint32x3_t" => &SVI32X3,
+        "svint32x4_t" => &SVI32X4,
+        "svint64_t" => &SVI64,
+        "svint64x2_t" => &SVI64X2,
+        "svint64x3_t" => &SVI64X3,
+        "svint64x4_t" => &SVI64X4,
+        "svuint8_t" => &SVU8,
+        "svuint8x2_t" => &SVU8X2,
+        "svuint8x3_t" => &SVU8X3,
+        "svuint8x4_t" => &SVU8X4,
+        "svuint16_t" => &SVU16,
+        "svuint16x2_t" => &SVU16X2,
+        "svuint16x3_t" => &SVU16X3,
+        "svuint16x4_t" => &SVU16X4,
+        "svuint32_t" => &SVU32,
+        "svuint32x2_t" => &SVU32X2,
+        "svuint32x3_t" => &SVU32X3,
+        "svuint32x4_t" => &SVU32X4,
+        "svuint64_t" => &SVU64,
+        "svuint64x2_t" => &SVU64X2,
+        "svuint64x3_t" => &SVU64X3,
+        "svuint64x4_t" => &SVU64X4,
+        "enum svprfop" => &SVPRFOP,
+        "enum svpattern" => &SVPATTERN,
 
         _ => panic!("failed to parse json type {s:?}"),
     }

From 16201513be1ec58c7ceb0d759a977cbd1b88815e Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Wed, 4 Mar 2026 14:16:40 +0000
Subject: [PATCH 240/326] core_arch: no SVE on arm64ec

arm64ec doesn't support SVE.
---
 crates/core_arch/src/aarch64/mod.rs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/crates/core_arch/src/aarch64/mod.rs b/crates/core_arch/src/aarch64/mod.rs
index 9376e04b3b..0292be2e0d 100644
--- a/crates/core_arch/src/aarch64/mod.rs
+++ b/crates/core_arch/src/aarch64/mod.rs
@@ -25,11 +25,17 @@ mod neon;
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub use self::neon::*;
 
+// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`.
+#[cfg(any(target_arch = "aarch64", doc))]
 mod sve;
+#[cfg(any(target_arch = "aarch64", doc))]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub use self::sve::*;
 
+// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`.
+#[cfg(any(target_arch = "aarch64", doc))]
 mod sve2;
+#[cfg(any(target_arch = "aarch64", doc))]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub use self::sve2::*;
 

From f3350a210eb55fe0c55ec3077da36e39a87cca13 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Wed, 4 Mar 2026 14:16:40 +0000
Subject: [PATCH 241/326] intrinsic-test: update parsing for SVE intrinsics

With SVE intrinsics in the `arm_intrinsics.json`, the parsing needs to be
updated to know to expect any new fields.
---
 crates/intrinsic-test/src/arm/json_parser.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/crates/intrinsic-test/src/arm/json_parser.rs b/crates/intrinsic-test/src/arm/json_parser.rs
index 65c179ef0d..c1563a7364 100644
--- a/crates/intrinsic-test/src/arm/json_parser.rs
+++ b/crates/intrinsic-test/src/arm/json_parser.rs
@@ -12,6 +12,8 @@ use std::path::Path;
 #[serde(deny_unknown_fields)]
 struct ReturnType {
     value: String,
+    #[serde(rename = "element_bit_size")]
+    _element_bit_size: Option<String>,
 }
 
 #[derive(Deserialize, Debug)]
@@ -50,6 +52,8 @@ struct JsonIntrinsic {
     args_prep: Option<HashMap<String, Value>>,
     #[serde(rename = "Architectures")]
     architectures: Vec<String>,
+    #[serde(rename = "instructions")]
+    _instructions: Option<Vec<Vec<String>>>,
 }
 
 pub fn get_neon_intrinsics(

From 9940d661bd924a00953214df2709186c9d26f1e8 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 9 Apr 2026 09:14:28 +0000
Subject: [PATCH 242/326] assert-instr: support type generics

SVE intrinsics have both type and const generics and so the
`assert_instr` macro needs to be able to generate test cases with the
type generics instantiated with the types provided in the attribute.

Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Co-authored-by: Luca Vizzarro <Luca.Vizzarro@arm.com>
Co-authored-by: Adam Gemmell <adam.gemmell@arm.com>
Co-authored-by: Jacob Bramley <jacob.bramley@arm.com>
---
 crates/assert-instr-macro/src/lib.rs | 79 +++++++++++++++++++++++-----
 1 file changed, 65 insertions(+), 14 deletions(-)

diff --git a/crates/assert-instr-macro/src/lib.rs b/crates/assert-instr-macro/src/lib.rs
index 13c3c3851b..839aae67cb 100644
--- a/crates/assert-instr-macro/src/lib.rs
+++ b/crates/assert-instr-macro/src/lib.rs
@@ -14,6 +14,7 @@ extern crate quote;
 
 use proc_macro2::TokenStream;
 use quote::ToTokens;
+use syn::spanned::Spanned;
 
 #[proc_macro_attribute]
 pub fn assert_instr(
@@ -67,21 +68,21 @@ pub fn assert_instr(
     );
     let mut inputs = Vec::new();
     let mut input_vals = Vec::new();
-    let mut const_vals = Vec::new();
+    let mut param_vals = Vec::new();
     let ret = &func.sig.output;
     for arg in func.sig.inputs.iter() {
         let capture = match *arg {
-            syn::FnArg::Typed(ref c) => c,
+            syn::FnArg::Typed(ref c) => c.to_owned(),
             ref v => panic!(
                 "arguments must not have patterns: `{:?}`",
                 v.clone().into_token_stream()
             ),
         };
-        let ident = match *capture.pat {
-            syn::Pat::Ident(ref i) => &i.ident,
+        let ident = match capture.pat.as_ref() {
+            syn::Pat::Ident(i) => &i.ident.to_owned(),
             _ => panic!("must have bare arguments"),
         };
-        if let Some((_, tokens)) = invoc.args.iter().find(|a| *ident == a.0) {
+        if let Some(&(_, ref tokens)) = invoc.args.iter().find(|a| *ident == a.0) {
             input_vals.push(quote! { #tokens });
         } else {
             inputs.push(capture);
@@ -89,18 +90,48 @@ pub fn assert_instr(
         }
     }
     for arg in func.sig.generics.params.iter() {
-        let c = match *arg {
-            syn::GenericParam::Const(ref c) => c,
+        match *arg {
+            syn::GenericParam::Const(ref c) => {
+                if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) {
+                    param_vals.push(quote! { #tokens });
+                } else {
+                    panic!("const generics must have a value for tests");
+                }
+            }
+            syn::GenericParam::Type(ref t) => {
+                if let Some((_, tokens)) = invoc.args.iter().find(|a| t.ident == a.0)
+                    && let syn::Expr::Path(syn::ExprPath { qself, path, .. }) = tokens
+                {
+                    param_vals.push(syn::Token![_](tokens.span()).to_token_stream());
+
+                    let generic_ty_value = syn::TypePath {
+                        qself: qself.clone(),
+                        path: path.clone(),
+                    };
+
+                    // Replace any function arguments that use generic parameters with the
+                    // instantiation provided in the macro invocation.
+                    inputs.iter_mut().for_each(|arg| {
+                        update_type_path(arg.ty.as_mut(), |type_path: &mut syn::TypePath| {
+                            if let Some(syn::PathSegment {
+                                ident: last_ident, ..
+                            }) = type_path.path.segments.last_mut()
+                            {
+                                if *last_ident == t.ident {
+                                    *type_path = generic_ty_value.to_owned()
+                                }
+                            }
+                        })
+                    });
+                } else {
+                    panic!("type generics must have a type for tests");
+                }
+            }
             ref v => panic!(
-                "only const generics are allowed: `{:?}`",
+                "only type and const generics are allowed: `{:?}`",
                 v.clone().into_token_stream()
             ),
         };
-        if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) {
-            const_vals.push(quote! { #tokens });
-        } else {
-            panic!("const generics must have a value for tests");
-        }
     }
 
     let attrs = func
@@ -138,7 +169,7 @@ pub fn assert_instr(
         #[unsafe(no_mangle)]
         #[inline(never)]
         pub unsafe extern #abi fn #shim_name(#(#inputs),*) #ret {
-            #name::<#(#const_vals),*>(#(#input_vals),*)
+            #name::<#(#param_vals),*>(#(#input_vals),*)
         }
     };
 
@@ -222,3 +253,23 @@ where
         }
     }
 }
+
+/// Calls `update` on type paths so that type generics can be replaced with the instantiation from
+/// the attribute.
+fn update_type_path<F>(ty: &mut syn::Type, update: F)
+where
+    F: Fn(&mut syn::TypePath),
+{
+    use syn::Type::*;
+    match ty {
+        Array(syn::TypeArray { elem, .. })
+        | Group(syn::TypeGroup { elem, .. })
+        | Paren(syn::TypeParen { elem, .. })
+        | Ptr(syn::TypePtr { elem, .. })
+        | Reference(syn::TypeReference { elem, .. })
+        | Slice(syn::TypeSlice { elem, .. }) => update_type_path(elem.as_mut(), update),
+        Path(path @ syn::TypePath { .. }) => update(path),
+        Tuple(..) => panic!("tuples and generic types together are not yet supported"),
+        _ => {}
+    }
+}

From 98405ca27f40377b76ed8451ca3fec6f2abff824 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 13 Apr 2026 04:42:58 +0000
Subject: [PATCH 243/326] gen-arm: disable `assert_instr` for `pfalse`

The implementation for this has the same behaviour as a `pfalse` but
doesn't currently emit one until an intrinsic is added to emit a
`zeroinitializer` for this.
---
 crates/core_arch/src/aarch64/sve/generated.rs    |  1 -
 crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml |  4 +++-
 crates/stdarch-verify/tests/arm.rs               | 10 +++++++++-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/crates/core_arch/src/aarch64/sve/generated.rs b/crates/core_arch/src/aarch64/sve/generated.rs
index 6edfc8e159..ed28e98a81 100644
--- a/crates/core_arch/src/aarch64/sve/generated.rs
+++ b/crates/core_arch/src/aarch64/sve/generated.rs
@@ -30819,7 +30819,6 @@ pub fn svorv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 #[inline(always)]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(pfalse))]
 pub fn svpfalse_b() -> svbool_t {
     svdupq_n_b8(
         false, false, false, false, false, false, false, false, false, false, false, false, false,
diff --git a/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
index 1fad8bb371..383e50b7cc 100644
--- a/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
@@ -3611,7 +3611,9 @@ intrinsics:
     doc: Set all predicate elements to false
     arguments: []
     return_type: "svbool_t"
-    assert_instr: [pfalse]
+    # TODO: With current implementation, `pfalse` isn't generated, will need to add intrinsic to
+    # generate `zeroinitializer`
+    # assert_instr: [pfalse] 
     compose:
       - FnCall:
           - "svdupq_n_b8"
diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs
index a37af2222a..2242bf4264 100644
--- a/crates/stdarch-verify/tests/arm.rs
+++ b/crates/stdarch-verify/tests/arm.rs
@@ -352,7 +352,10 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
         bail!("wrong number of const arguments");
     }
 
-    if rust.instrs.is_empty() && arm.instruction != "" {
+    if rust.instrs.is_empty()
+        && arm.instruction != ""
+        && !SKIP_ASSERT_INSTR_TESTS.contains(&rust.name)
+    {
         bail!(
             "instruction not listed for `{}`, but arm lists {:?}",
             rust.name,
@@ -671,6 +674,11 @@ fn parse_ty_base(s: &str) -> &'static Type {
     }
 }
 
+// FIXME(arm-maintainers): Some tests require new rustc intrinsics in order to generate
+// the appropriate instruction, though they do have the correct behaviour - these will be fixed
+// but are disabled for now.
+static SKIP_ASSERT_INSTR_TESTS: &'static [&'static str] = &["svpfalse_b"];
+
 // FIXME(arm-maintainers): With the advent of the `intrinsic-test` tool, new tests of this kind
 // are no longer being added and just adding to this list indefinitely isn't the best solution for
 // dealing with that.

From f0dbe83a14902ef4fc635e82c3eeff4a72414cfb Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Tue, 14 Apr 2026 00:03:19 +0000
Subject: [PATCH 244/326] stdarch-test: `[us]shll[tb]` have no aliases

SVE's `[us]shll[tb]` intructions have no aliases unlike Neon's
`[us]hll{2}` so this logic needs adjusted to not accidentally rewrite
the instruction.
---
 crates/stdarch-test/src/disassembly.rs | 24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/crates/stdarch-test/src/disassembly.rs b/crates/stdarch-test/src/disassembly.rs
index 237e8d2dc2..7cf657baa0 100644
--- a/crates/stdarch-test/src/disassembly.rs
+++ b/crates/stdarch-test/src/disassembly.rs
@@ -158,16 +158,26 @@ fn parse(output: &str) -> HashSet<Function> {
             };
 
             if cfg!(any(target_arch = "aarch64", target_arch = "arm64ec")) {
-                // Normalize [us]shll.* ..., #0 instructions to the preferred form: [us]xtl.* ...
-                // as neither LLVM objdump nor dumpbin does that.
-                // See https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-Long--an-alias-of-USHLL--USHLL2-
-                // and https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-Long--an-alias-of-SSHLL--SSHLL2-
-                // for details.
+                // Normalize `[us]shll{2}.* ..., #0` instructions to the preferred
+                // form: `[us]xtl{2}.* ...` as neither LLVM objdump nor dumpbin does that.
+                //
+                // SVE has `[us]shll[tb]` instructions that don't have an equivalent alias.
+                //
+                // See Arm documentation for details:
+                //
+                // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-long--an-alias-of-USHLL--USHLL2-?lang=en
+                // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-long--an-alias-of-SSHLL--SSHLL2-?lang=en
                 fn is_shll(instr: &str) -> bool {
                     if cfg!(target_env = "msvc") {
-                        instr.starts_with("ushll") || instr.starts_with("sshll")
+                        instr == "ushll"
+                            || instr == "ushll2"
+                            || instr == "sshll"
+                            || instr == "sshll2"
                     } else {
-                        instr.starts_with("ushll.") || instr.starts_with("sshll.")
+                        instr == "ushll."
+                            || instr == "ushll2."
+                            || instr == "sshll."
+                            || instr == "sshll2."
                     }
                 }
                 match (parts.first(), parts.last()) {

From b661e23a496949e389f2633bd9c4accea59196eb Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Tue, 14 Apr 2026 01:09:25 +0000
Subject: [PATCH 245/326] gen-arm: `assert_instr` on msvc for `[su]mull[tb]`

`dumpbin.exe` produces `44a1c000`/`44e1c000`/`44a1c400`/`44e1c400` for
`[su]mull[tb]` instead of the instruction name - so skip `assert_instr`
for these intrinsics on MSVC targets.
---
 .../core_arch/src/aarch64/sve2/generated.rs   | 64 +++++++++++++------
 .../spec/sve2/aarch64.spec.yml                | 22 +++++--
 2 files changed, 60 insertions(+), 26 deletions(-)

diff --git a/crates/core_arch/src/aarch64/sve2/generated.rs b/crates/core_arch/src/aarch64/sve2/generated.rs
index 79be8a8889..c5b0149c9c 100644
--- a/crates/core_arch/src/aarch64/sve2/generated.rs
+++ b/crates/core_arch/src/aarch64/sve2/generated.rs
@@ -10281,7 +10281,10 @@ pub fn svmul_lane_u64<const IMM_INDEX: i32>(op1: svuint64_t, op2: svuint64_t) ->
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullb, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(smullb, IMM_INDEX = 0)
+)]
 pub fn svmullb_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint32_t {
     static_assert_range!(IMM_INDEX, 0..=7);
     unsafe extern "unadjusted" {
@@ -10298,7 +10301,10 @@ pub fn svmullb_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) ->
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullb, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(smullb, IMM_INDEX = 0)
+)]
 pub fn svmullb_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint64_t {
     static_assert_range!(IMM_INDEX, 0..=3);
     unsafe extern "unadjusted" {
@@ -10315,7 +10321,10 @@ pub fn svmullb_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) ->
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullb, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(umullb, IMM_INDEX = 0)
+)]
 pub fn svmullb_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
     static_assert_range!(IMM_INDEX, 0..=7);
     unsafe extern "unadjusted" {
@@ -10332,7 +10341,10 @@ pub fn svmullb_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t)
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullb, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(umullb, IMM_INDEX = 0)
+)]
 pub fn svmullb_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
     static_assert_range!(IMM_INDEX, 0..=3);
     unsafe extern "unadjusted" {
@@ -10481,7 +10493,10 @@ pub fn svmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(smullt, IMM_INDEX = 0)
+)]
 pub fn svmullt_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> svint32_t {
     static_assert_range!(IMM_INDEX, 0..=7);
     unsafe extern "unadjusted" {
@@ -10498,7 +10513,10 @@ pub fn svmullt_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) ->
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(smullt, IMM_INDEX = 0)
+)]
 pub fn svmullt_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> svint64_t {
     static_assert_range!(IMM_INDEX, 0..=3);
     unsafe extern "unadjusted" {
@@ -10515,7 +10533,10 @@ pub fn svmullt_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) ->
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(umullt, IMM_INDEX = 0)
+)]
 pub fn svmullt_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
     static_assert_range!(IMM_INDEX, 0..=7);
     unsafe extern "unadjusted" {
@@ -10532,7 +10553,10 @@ pub fn svmullt_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t)
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt, IMM_INDEX = 0))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc")),
+    assert_instr(umullt, IMM_INDEX = 0)
+)]
 pub fn svmullt_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
     static_assert_range!(IMM_INDEX, 0..=3);
     unsafe extern "unadjusted" {
@@ -10549,7 +10573,7 @@ pub fn svmullt_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t)
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
 pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv8i16")]
@@ -10562,7 +10586,7 @@ pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
 pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
     svmullt_s16(op1, svdup_n_s8(op2))
 }
@@ -10571,7 +10595,7 @@ pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
 pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv4i32")]
@@ -10584,7 +10608,7 @@ pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
 pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
     svmullt_s32(op1, svdup_n_s16(op2))
 }
@@ -10593,7 +10617,7 @@ pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
 pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv2i64")]
@@ -10606,7 +10630,7 @@ pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(smullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
 pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
     svmullt_s64(op1, svdup_n_s32(op2))
 }
@@ -10615,7 +10639,7 @@ pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
 pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv8i16")]
@@ -10628,7 +10652,7 @@ pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
 pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
     svmullt_u16(op1, svdup_n_u8(op2))
 }
@@ -10637,7 +10661,7 @@ pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
 pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv4i32")]
@@ -10650,7 +10674,7 @@ pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
 pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
     svmullt_u32(op1, svdup_n_u16(op2))
 }
@@ -10659,7 +10683,7 @@ pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
 pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv2i64")]
@@ -10672,7 +10696,7 @@ pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 #[inline(always)]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(umullt))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
 pub fn svmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
     svmullt_u64(op1, svdup_n_u32(op2))
 }
diff --git a/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml
index 6365bea21b..269d7ff0ea 100644
--- a/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml
@@ -10,6 +10,10 @@ generate_load_store_tests: true
 sve-unstable: &sve-unstable
   FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']]
 
+# `#[cfg_attr(all(test, not(target_env = "msvc"))]`
+msvc-disabled: &msvc-disabled
+  FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]
+
 intrinsics:
   - name: svbext[{_n}_{type}]
     attr: [*sve-unstable]
@@ -2429,7 +2433,10 @@ intrinsics:
       - LLVMLink: { name: "{type_kind[0].su}mullb.{sve_type[0]}" }
 
   - name: svmullb_lane[_{type[0]}]
-    attr: [*sve-unstable]
+    attr:
+      - *sve-unstable
+      # FIXME(arm-maintainers): MSVC disassembly of `[su]mullb` fails
+      - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullb", "IMM_INDEX = 0"]]}]]
     doc: Multiply long (bottom)
     arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
     return_type: "{sve_type[0]}"
@@ -2440,7 +2447,6 @@ intrinsics:
       - [u64, u32]
     static_defs: ["const IMM_INDEX: i32"]
     constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
-    assert_instr: [["{type_kind[0].su}mullb", "IMM_INDEX = 0"]]
     compose:
       - LLVMLink:
           name: "{type_kind[0].su}mullb.lane.{sve_type[0]}"
@@ -2449,7 +2455,10 @@ intrinsics:
       - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]]
 
   - name: svmullt[{_n}_{type[0]}]
-    attr: [*sve-unstable]
+    attr:
+      - *sve-unstable
+      # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails
+      - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt"]]}]]
     doc: Multiply long (top)
     arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
     return_type: "{sve_type[0]}"
@@ -2460,13 +2469,15 @@ intrinsics:
       - [u16, u8]
       - [u32, u16]
       - [u64, u32]
-    assert_instr: ["{type_kind[0].su}mullt"]
     n_variant_op: op2
     compose:
       - LLVMLink: { name: "{type_kind[0].su}mullt.{sve_type[0]}" }
 
   - name: svmullt_lane[_{type[0]}]
-    attr: [*sve-unstable]
+    attr:
+      - *sve-unstable
+      # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails
+      - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt", "IMM_INDEX = 0"]]}]]
     doc: Multiply long (top)
     arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"]
     return_type: "{sve_type[0]}"
@@ -2477,7 +2488,6 @@ intrinsics:
       - [u64, u32]
     static_defs: ["const IMM_INDEX: i32"]
     constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }]
-    assert_instr: [["{type_kind[0].su}mullt", "IMM_INDEX = 0"]]
     compose:
       - LLVMLink:
           name: "{type_kind[0].su}mullt.lane.{sve_type[0]}"

From ae9cb1c69c970b796a824bc4a69fc18f82642e82 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Tue, 14 Apr 2026 04:05:07 +0000
Subject: [PATCH 246/326] core_arch: disable ld/st tests on msvc

There seemed to be non-deterministic failures on MSVC that looked like
corruption of the FFR in CI. Until this can be investigated, to avoid any
spurious failures, these tests are disabled.
---
 crates/core_arch/src/aarch64/sve/mod.rs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/crates/core_arch/src/aarch64/sve/mod.rs b/crates/core_arch/src/aarch64/sve/mod.rs
index a3f70ab61c..04a92359a0 100644
--- a/crates/core_arch/src/aarch64/sve/mod.rs
+++ b/crates/core_arch/src/aarch64/sve/mod.rs
@@ -374,6 +374,9 @@ pub enum svprfop {
     SV_PSTL3STRM = 13,
 }
 
-#[cfg(test)]
+// FIXME(arm-maintainers): On MSVC targets, it seemed like spurious corruption of the FFR was being
+// observed non-deterministically on CI. Disabling these tests out of caution on that platform until
+// it is investigated.
+#[cfg(all(test, not(target_env = "msvc")))]
 #[path = "ld_st_tests_aarch64.rs"]
 mod ld_st_tests;

From 913e49c4f7b443cc28e61cff3e305792c6701ec8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Sat, 11 Apr 2026 17:22:53 +0200
Subject: [PATCH 247/326] Fix MIPS tests

Tests failed to build due to use of legacy const generics syntax, out-of-bounds immediates and incorrect name of const generics in `assert_instr`
---
 .../mips64-unknown-linux-gnuabi64/Dockerfile  |   2 +-
 .../Dockerfile                                |   2 +-
 crates/core_arch/src/lib.rs                   |   6 +-
 crates/core_arch/src/mips/msa.rs              | 550 +++++++++---------
 crates/simd-test-macro/src/lib.rs             |   1 +
 5 files changed, 286 insertions(+), 275 deletions(-)

diff --git a/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile
index a8b352881e..8bcd640945 100644
--- a/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile
+++ b/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile
@@ -1,4 +1,4 @@
-FROM ubuntu:25.10
+FROM ubuntu:25.04 # gcc-mips64-linux-gnuabi64 not available in 25.10
 
 RUN apt-get update && apt-get install -y --no-install-recommends \
         gcc libc6-dev qemu-user ca-certificates \
diff --git a/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile
index 147a3df614..9aa0ce0578 100644
--- a/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile
+++ b/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile
@@ -1,4 +1,4 @@
-FROM ubuntu:25.10
+FROM ubuntu:25.04 # gcc-mips64el-linux-gnuabi64 not available in 25.10
 
 RUN apt-get update && apt-get install -y --no-install-recommends \
         gcc libc6-dev qemu-user ca-certificates \
diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 9255994e5e..d0a4ac9260 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -70,7 +70,11 @@
 )]
 #![cfg_attr(
     test,
-    feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection,)
+    feature(
+        stdarch_arm_feature_detection,
+        stdarch_mips_feature_detection,
+        stdarch_powerpc_feature_detection,
+    )
 )]
 
 #[cfg(test)]
diff --git a/crates/core_arch/src/mips/msa.rs b/crates/core_arch/src/mips/msa.rs
index 6246433da5..bc601baef9 100644
--- a/crates/core_arch/src/mips/msa.rs
+++ b/crates/core_arch/src/mips/msa.rs
@@ -1407,7 +1407,7 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(addvi.b, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(addvi.b, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_addvi_b<const IMM5: i32>(a: v16i8) -> v16i8 {
@@ -1423,7 +1423,7 @@ pub unsafe fn __msa_addvi_b<const IMM5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(addvi.h, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(addvi.h, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_addvi_h<const IMM5: i32>(a: v8i16) -> v8i16 {
@@ -1439,7 +1439,7 @@ pub unsafe fn __msa_addvi_h<const IMM5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(addvi.w, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(addvi.w, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_addvi_w<const IMM5: i32>(a: v4i32) -> v4i32 {
@@ -1455,7 +1455,7 @@ pub unsafe fn __msa_addvi_w<const IMM5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(addvi.d, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(addvi.d, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_addvi_d<const IMM5: i32>(a: v2i64) -> v2i64 {
@@ -1486,7 +1486,7 @@ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(andi.b, imm8 = 0b10010111))]
+#[cfg_attr(test, assert_instr(andi.b, IMM8 = 0b10010111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_andi_b<const IMM8: i32>(a: v16u8) -> v16u8 {
@@ -1938,7 +1938,7 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bclri.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(bclri.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bclri_b<const IMM3: i32>(a: v16u8) -> v16u8 {
@@ -1954,7 +1954,7 @@ pub unsafe fn __msa_bclri_b<const IMM3: i32>(a: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bclri.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(bclri.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bclri_h<const IMM4: i32>(a: v8u16) -> v8u16 {
@@ -1970,7 +1970,7 @@ pub unsafe fn __msa_bclri_h<const IMM4: i32>(a: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bclri.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(bclri.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bclri_w<const IMM5: i32>(a: v4u32) -> v4u32 {
@@ -1986,7 +1986,7 @@ pub unsafe fn __msa_bclri_w<const IMM5: i32>(a: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bclri.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(bclri.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bclri_d<const IMM6: i32>(a: v2u64) -> v2u64 {
@@ -2062,7 +2062,7 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsli.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(binsli.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsli_b<const IMM3: i32>(a: v16u8, b: v16u8) -> v16u8 {
@@ -2078,7 +2078,7 @@ pub unsafe fn __msa_binsli_b<const IMM3: i32>(a: v16u8, b: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsli.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(binsli.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsli_h<const IMM4: i32>(a: v8u16, b: v8u16) -> v8u16 {
@@ -2094,7 +2094,7 @@ pub unsafe fn __msa_binsli_h<const IMM4: i32>(a: v8u16, b: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsli.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(binsli.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsli_w<const IMM5: i32>(a: v4u32, b: v4u32) -> v4u32 {
@@ -2110,7 +2110,7 @@ pub unsafe fn __msa_binsli_w<const IMM5: i32>(a: v4u32, b: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsli.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(binsli.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsli_d<const IMM6: i32>(a: v2u64, b: v2u64) -> v2u64 {
@@ -2186,7 +2186,7 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsri.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(binsri.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsri_b<const IMM3: i32>(a: v16u8, b: v16u8) -> v16u8 {
@@ -2202,7 +2202,7 @@ pub unsafe fn __msa_binsri_b<const IMM3: i32>(a: v16u8, b: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsri.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(binsri.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsri_h<const IMM4: i32>(a: v8u16, b: v8u16) -> v8u16 {
@@ -2218,7 +2218,7 @@ pub unsafe fn __msa_binsri_h<const IMM4: i32>(a: v8u16, b: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsri.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(binsri.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsri_w<const IMM5: i32>(a: v4u32, b: v4u32) -> v4u32 {
@@ -2234,7 +2234,7 @@ pub unsafe fn __msa_binsri_w<const IMM5: i32>(a: v4u32, b: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(binsri.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(binsri.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_binsri_d<const IMM6: i32>(a: v2u64, b: v2u64) -> v2u64 {
@@ -2265,7 +2265,7 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bmnzi.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(bmnzi.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bmnzi_b<const IMM8: i32>(a: v16u8, b: v16u8) -> v16u8 {
@@ -2296,7 +2296,7 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bmzi.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(bmzi.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bmzi_b<const IMM8: i32>(a: v16u8, b: v16u8) -> v16u8 {
@@ -2372,7 +2372,7 @@ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bnegi.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(bnegi.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bnegi_b<const IMM3: i32>(a: v16u8) -> v16u8 {
@@ -2388,7 +2388,7 @@ pub unsafe fn __msa_bnegi_b<const IMM3: i32>(a: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bnegi.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(bnegi.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bnegi_h<const IMM4: i32>(a: v8u16) -> v8u16 {
@@ -2404,7 +2404,7 @@ pub unsafe fn __msa_bnegi_h<const IMM4: i32>(a: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bnegi.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(bnegi.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bnegi_w<const IMM5: i32>(a: v4u32) -> v4u32 {
@@ -2420,7 +2420,7 @@ pub unsafe fn __msa_bnegi_w<const IMM5: i32>(a: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bnegi.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(bnegi.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bnegi_d<const IMM6: i32>(a: v2u64) -> v2u64 {
@@ -2512,7 +2512,7 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bseli.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(bseli.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bseli_b<const IMM8: i32>(a: v16u8, b: v16u8) -> v16u8 {
@@ -2588,7 +2588,7 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bseti.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(bseti.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bseti_b<const IMM3: i32>(a: v16u8) -> v16u8 {
@@ -2604,7 +2604,7 @@ pub unsafe fn __msa_bseti_b<const IMM3: i32>(a: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bseti.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(bseti.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bseti_h<const IMM4: i32>(a: v8u16) -> v8u16 {
@@ -2620,7 +2620,7 @@ pub unsafe fn __msa_bseti_h<const IMM4: i32>(a: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bseti.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(bseti.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bseti_w<const IMM5: i32>(a: v4u32) -> v4u32 {
@@ -2636,7 +2636,7 @@ pub unsafe fn __msa_bseti_w<const IMM5: i32>(a: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(bseti.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(bseti.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_bseti_d<const IMM6: i32>(a: v2u64) -> v2u64 {
@@ -2769,7 +2769,7 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ceqi.b, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(ceqi.b, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ceqi_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
@@ -2785,7 +2785,7 @@ pub unsafe fn __msa_ceqi_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ceqi.h, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(ceqi.h, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ceqi_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
@@ -2801,7 +2801,7 @@ pub unsafe fn __msa_ceqi_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ceqi.w, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(ceqi.w, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ceqi_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
@@ -2817,7 +2817,7 @@ pub unsafe fn __msa_ceqi_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ceqi.d, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(ceqi.d, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ceqi_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
@@ -2832,7 +2832,7 @@ pub unsafe fn __msa_ceqi_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
 /// Can not be tested in user mode
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(cfcmsa, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(cfcmsa, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_cfcmsa<const IMM5: i32>() -> i32 {
@@ -2969,7 +2969,7 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_s.b, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_s.b, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
@@ -2986,7 +2986,7 @@ pub unsafe fn __msa_clei_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_s.h, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_s.h, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
@@ -3003,7 +3003,7 @@ pub unsafe fn __msa_clei_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_s.w, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_s.w, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
@@ -3020,7 +3020,7 @@ pub unsafe fn __msa_clei_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_s.d, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_s.d, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
@@ -3037,7 +3037,7 @@ pub unsafe fn __msa_clei_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_u.b, imm5 = 0b111))]
+#[cfg_attr(test, assert_instr(clei_u.b, IMM5 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_u_b<const IMM5: i32>(a: v16u8) -> v16i8 {
@@ -3054,7 +3054,7 @@ pub unsafe fn __msa_clei_u_b<const IMM5: i32>(a: v16u8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_u.h, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_u.h, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_u_h<const IMM5: i32>(a: v8u16) -> v8i16 {
@@ -3071,7 +3071,7 @@ pub unsafe fn __msa_clei_u_h<const IMM5: i32>(a: v8u16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_u.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_u.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_u_w<const IMM5: i32>(a: v4u32) -> v4i32 {
@@ -3088,7 +3088,7 @@ pub unsafe fn __msa_clei_u_w<const IMM5: i32>(a: v4u32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clei_u.d, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clei_u.d, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clei_u_d<const IMM5: i32>(a: v2u64) -> v2i64 {
@@ -3225,7 +3225,7 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_s.b, imm_s5 = 0b111))]
+#[cfg_attr(test, assert_instr(clti_s.b, IMM_S5 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
@@ -3242,7 +3242,7 @@ pub unsafe fn __msa_clti_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_s.h, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clti_s.h, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
@@ -3259,7 +3259,7 @@ pub unsafe fn __msa_clti_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_s.w, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clti_s.w, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
@@ -3276,7 +3276,7 @@ pub unsafe fn __msa_clti_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_s.d, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clti_s.d, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
@@ -3293,7 +3293,7 @@ pub unsafe fn __msa_clti_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_u.b, imm5 = 0b111))]
+#[cfg_attr(test, assert_instr(clti_u.b, IMM5 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_u_b<const IMM5: i32>(a: v16u8) -> v16i8 {
@@ -3310,7 +3310,7 @@ pub unsafe fn __msa_clti_u_b<const IMM5: i32>(a: v16u8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_u.h, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clti_u.h, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_u_h<const IMM5: i32>(a: v8u16) -> v8i16 {
@@ -3327,7 +3327,7 @@ pub unsafe fn __msa_clti_u_h<const IMM5: i32>(a: v8u16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_u.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clti_u.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_u_w<const IMM5: i32>(a: v4u32) -> v4i32 {
@@ -3344,7 +3344,7 @@ pub unsafe fn __msa_clti_u_w<const IMM5: i32>(a: v4u32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(clti_u.d, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(clti_u.d, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_clti_u_d<const IMM5: i32>(a: v2u64) -> v2i64 {
@@ -3359,7 +3359,7 @@ pub unsafe fn __msa_clti_u_d<const IMM5: i32>(a: v2u64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_s.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(copy_s.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_s_b<const IMM4: i32>(a: v16i8) -> i32 {
@@ -3374,7 +3374,7 @@ pub unsafe fn __msa_copy_s_b<const IMM4: i32>(a: v16i8) -> i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_s.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(copy_s.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_s_h<const IMM3: i32>(a: v8i16) -> i32 {
@@ -3389,7 +3389,7 @@ pub unsafe fn __msa_copy_s_h<const IMM3: i32>(a: v8i16) -> i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_s.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(copy_s.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_s_w<const IMM2: i32>(a: v4i32) -> i32 {
@@ -3404,7 +3404,7 @@ pub unsafe fn __msa_copy_s_w<const IMM2: i32>(a: v4i32) -> i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_s.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(copy_s.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_s_d<const IMM1: i32>(a: v2i64) -> i64 {
@@ -3419,7 +3419,7 @@ pub unsafe fn __msa_copy_s_d<const IMM1: i32>(a: v2i64) -> i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_u.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(copy_u.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_u_b<const IMM4: i32>(a: v16i8) -> u32 {
@@ -3434,7 +3434,7 @@ pub unsafe fn __msa_copy_u_b<const IMM4: i32>(a: v16i8) -> u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_u.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(copy_u.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_u_h<const IMM3: i32>(a: v8i16) -> u32 {
@@ -3449,7 +3449,7 @@ pub unsafe fn __msa_copy_u_h<const IMM3: i32>(a: v8i16) -> u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_u.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(copy_u.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_u_w<const IMM2: i32>(a: v4i32) -> u32 {
@@ -3464,7 +3464,7 @@ pub unsafe fn __msa_copy_u_w<const IMM2: i32>(a: v4i32) -> u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(copy_u.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(copy_u.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_copy_u_d<const IMM1: i32>(a: v2i64) -> u64 {
@@ -3481,7 +3481,7 @@ pub unsafe fn __msa_copy_u_d<const IMM1: i32>(a: v2i64) -> u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ctcmsa, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(ctcmsa, IMM5 = 0b1))]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ctcmsa<const IMM5: i32>(a: i32) -> () {
@@ -5855,7 +5855,7 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insert.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(insert.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insert_b<const IMM4: i32>(a: v16i8, c: i32) -> v16i8 {
@@ -5871,7 +5871,7 @@ pub unsafe fn __msa_insert_b<const IMM4: i32>(a: v16i8, c: i32) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insert.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(insert.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insert_h<const IMM3: i32>(a: v8i16, c: i32) -> v8i16 {
@@ -5887,7 +5887,7 @@ pub unsafe fn __msa_insert_h<const IMM3: i32>(a: v8i16, c: i32) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insert.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(insert.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insert_w<const IMM2: i32>(a: v4i32, c: i32) -> v4i32 {
@@ -5903,7 +5903,7 @@ pub unsafe fn __msa_insert_w<const IMM2: i32>(a: v4i32, c: i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insert.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(insert.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insert_d<const IMM1: i32>(a: v2i64, c: i64) -> v2i64 {
@@ -5919,7 +5919,7 @@ pub unsafe fn __msa_insert_d<const IMM1: i32>(a: v2i64, c: i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insve.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(insve.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insve_b<const IMM4: i32>(a: v16i8, c: v16i8) -> v16i8 {
@@ -5935,7 +5935,7 @@ pub unsafe fn __msa_insve_b<const IMM4: i32>(a: v16i8, c: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insve.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(insve.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insve_h<const IMM3: i32>(a: v8i16, c: v8i16) -> v8i16 {
@@ -5951,7 +5951,7 @@ pub unsafe fn __msa_insve_h<const IMM3: i32>(a: v8i16, c: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insve.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(insve.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insve_w<const IMM2: i32>(a: v4i32, c: v4i32) -> v4i32 {
@@ -5967,7 +5967,7 @@ pub unsafe fn __msa_insve_w<const IMM2: i32>(a: v4i32, c: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(insve.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(insve.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_insve_d<const IMM1: i32>(a: v2i64, c: v2i64) -> v2i64 {
@@ -5983,7 +5983,7 @@ pub unsafe fn __msa_insve_d<const IMM1: i32>(a: v2i64, c: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ld.b, imm_s10 = 0b1111111111))]
+#[cfg_attr(test, assert_instr(ld.b, IMM_S10 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ld_b<const IMM_S10: i32>(mem_addr: *mut u8) -> v16i8 {
@@ -5999,7 +5999,7 @@ pub unsafe fn __msa_ld_b<const IMM_S10: i32>(mem_addr: *mut u8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ld.h, imm_s11 = 0b11111111111))]
+#[cfg_attr(test, assert_instr(ld.h, IMM_S11 = -2))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ld_h<const IMM_S11: i32>(mem_addr: *mut u8) -> v8i16 {
@@ -6016,7 +6016,7 @@ pub unsafe fn __msa_ld_h<const IMM_S11: i32>(mem_addr: *mut u8) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ld.w, imm_s12 = 0b111111111111))]
+#[cfg_attr(test, assert_instr(ld.w, IMM_S12 = -4))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ld_w<const IMM_S12: i32>(mem_addr: *mut u8) -> v4i32 {
@@ -6033,7 +6033,7 @@ pub unsafe fn __msa_ld_w<const IMM_S12: i32>(mem_addr: *mut u8) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ld.d, imm_s13 = 0b1111111111111))]
+#[cfg_attr(test, assert_instr(ld.d, IMM_S13 = -8))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ld_d<const IMM_S13: i32>(mem_addr: *mut u8) -> v2i64 {
@@ -6050,7 +6050,7 @@ pub unsafe fn __msa_ld_d<const IMM_S13: i32>(mem_addr: *mut u8) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ldi.b, imm_s10 = 0b1111111111))]
+#[cfg_attr(test, assert_instr(ldi.b, IMM_S10 = -1))]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ldi_b<const IMM_S10: i32>() -> v16i8 {
@@ -6066,7 +6066,7 @@ pub unsafe fn __msa_ldi_b<const IMM_S10: i32>() -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ldi.h, imm_s10 = 0b1111111111))]
+#[cfg_attr(test, assert_instr(ldi.h, IMM_S10 = -1))]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ldi_h<const IMM_S10: i32>() -> v8i16 {
@@ -6082,7 +6082,7 @@ pub unsafe fn __msa_ldi_h<const IMM_S10: i32>() -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ldi.w, imm_s10 = 0b1111111111))]
+#[cfg_attr(test, assert_instr(ldi.w, IMM_S10 = -1))]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ldi_w<const IMM_S10: i32>() -> v4i32 {
@@ -6098,7 +6098,7 @@ pub unsafe fn __msa_ldi_w<const IMM_S10: i32>() -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ldi.d, imm_s10 = 0b1111111111))]
+#[cfg_attr(test, assert_instr(ldi.d, IMM_S10 = -1))]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ldi_d<const IMM_S10: i32>() -> v2i64 {
@@ -6410,7 +6410,7 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_s.b, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_s.b, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
@@ -6426,7 +6426,7 @@ pub unsafe fn __msa_maxi_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_s.h, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_s.h, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
@@ -6442,7 +6442,7 @@ pub unsafe fn __msa_maxi_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_s.w, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_s.w, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
@@ -6458,7 +6458,7 @@ pub unsafe fn __msa_maxi_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_s.d, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_s.d, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
@@ -6474,7 +6474,7 @@ pub unsafe fn __msa_maxi_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_u.b, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_u.b, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_u_b<const IMM5: i32>(a: v16u8) -> v16u8 {
@@ -6490,7 +6490,7 @@ pub unsafe fn __msa_maxi_u_b<const IMM5: i32>(a: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_u.h, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_u.h, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_u_h<const IMM5: i32>(a: v8u16) -> v8u16 {
@@ -6506,7 +6506,7 @@ pub unsafe fn __msa_maxi_u_h<const IMM5: i32>(a: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_u.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_u.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
@@ -6522,7 +6522,7 @@ pub unsafe fn __msa_maxi_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(maxi_u.d, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(maxi_u.d, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_maxi_u_d<const IMM5: i32>(a: v2u64) -> v2u64 {
@@ -6654,7 +6654,7 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_s.b, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_s.b, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
@@ -6670,7 +6670,7 @@ pub unsafe fn __msa_mini_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_s.h, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_s.h, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
@@ -6686,7 +6686,7 @@ pub unsafe fn __msa_mini_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_s.w, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_s.w, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
@@ -6702,7 +6702,7 @@ pub unsafe fn __msa_mini_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_s.d, imm_s5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_s.d, IMM_S5 = -1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
@@ -6774,7 +6774,7 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_u.b, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_u.b, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_u_b<const IMM5: i32>(a: v16u8) -> v16u8 {
@@ -6790,7 +6790,7 @@ pub unsafe fn __msa_mini_u_b<const IMM5: i32>(a: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_u.h, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_u.h, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_u_h<const IMM5: i32>(a: v8u16) -> v8u16 {
@@ -6806,7 +6806,7 @@ pub unsafe fn __msa_mini_u_h<const IMM5: i32>(a: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_u.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_u.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
@@ -6822,7 +6822,7 @@ pub unsafe fn __msa_mini_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(mini_u.d, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(mini_u.d, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_mini_u_d<const IMM5: i32>(a: v2u64) -> v2u64 {
@@ -7343,7 +7343,7 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(nori.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(nori.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_nori_b<const IMM8: i32>(a: v16u8) -> v16u8 {
@@ -7375,7 +7375,7 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(ori.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(ori.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_ori_b<const IMM8: i32>(a: v16u8) -> v16u8 {
@@ -7555,7 +7555,7 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_s.b, imm4 = 0b111))]
+#[cfg_attr(test, assert_instr(sat_s.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_s_b<const IMM3: i32>(a: v16i8) -> v16i8 {
@@ -7571,7 +7571,7 @@ pub unsafe fn __msa_sat_s_b<const IMM3: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_s.h, imm3 = 0b1111))]
+#[cfg_attr(test, assert_instr(sat_s.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_s_h<const IMM4: i32>(a: v8i16) -> v8i16 {
@@ -7587,7 +7587,7 @@ pub unsafe fn __msa_sat_s_h<const IMM4: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_s.w, imm2 = 0b11111))]
+#[cfg_attr(test, assert_instr(sat_s.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_s_w<const IMM5: i32>(a: v4i32) -> v4i32 {
@@ -7603,7 +7603,7 @@ pub unsafe fn __msa_sat_s_w<const IMM5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_s.d, imm1 = 0b111111))]
+#[cfg_attr(test, assert_instr(sat_s.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_s_d<const IMM6: i32>(a: v2i64) -> v2i64 {
@@ -7619,7 +7619,7 @@ pub unsafe fn __msa_sat_s_d<const IMM6: i32>(a: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_u.b, imm4 = 0b111))]
+#[cfg_attr(test, assert_instr(sat_u.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_u_b<const IMM3: i32>(a: v16u8) -> v16u8 {
@@ -7635,7 +7635,7 @@ pub unsafe fn __msa_sat_u_b<const IMM3: i32>(a: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_u.h, imm3 = 0b1111))]
+#[cfg_attr(test, assert_instr(sat_u.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_u_h<const IMM4: i32>(a: v8u16) -> v8u16 {
@@ -7651,7 +7651,7 @@ pub unsafe fn __msa_sat_u_h<const IMM4: i32>(a: v8u16) -> v8u16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_u.w, imm2 = 0b11111))]
+#[cfg_attr(test, assert_instr(sat_u.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
@@ -7667,7 +7667,7 @@ pub unsafe fn __msa_sat_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sat_u.d, imm1 = 0b111111))]
+#[cfg_attr(test, assert_instr(sat_u.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sat_u_d<const IMM6: i32>(a: v2u64) -> v2u64 {
@@ -7684,7 +7684,7 @@ pub unsafe fn __msa_sat_u_d<const IMM6: i32>(a: v2u64) -> v2u64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(shf.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(shf.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_shf_b<const IMM8: i32>(a: v16i8) -> v16i8 {
@@ -7701,7 +7701,7 @@ pub unsafe fn __msa_shf_b<const IMM8: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(shf.h, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(shf.h, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_shf_h<const IMM8: i32>(a: v8i16) -> v8i16 {
@@ -7718,7 +7718,7 @@ pub unsafe fn __msa_shf_h<const IMM8: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(shf.w, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(shf.w, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_shf_w<const IMM8: i32>(a: v4i32) -> v4i32 {
@@ -7823,7 +7823,7 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sldi.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(sldi.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sldi_b<const IMM4: i32>(a: v16i8, b: v16i8) -> v16i8 {
@@ -7844,7 +7844,7 @@ pub unsafe fn __msa_sldi_b<const IMM4: i32>(a: v16i8, b: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sldi.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(sldi.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sldi_h<const IMM3: i32>(a: v8i16, b: v8i16) -> v8i16 {
@@ -7865,7 +7865,7 @@ pub unsafe fn __msa_sldi_h<const IMM3: i32>(a: v8i16, b: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sldi.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(sldi.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sldi_w<const IMM2: i32>(a: v4i32, b: v4i32) -> v4i32 {
@@ -7886,7 +7886,7 @@ pub unsafe fn __msa_sldi_w<const IMM2: i32>(a: v4i32, b: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(sldi.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(sldi.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_sldi_d<const IMM1: i32>(a: v2i64, b: v2i64) -> v2i64 {
@@ -7962,7 +7962,7 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(slli.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(slli.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_slli_b<const IMM4: i32>(a: v16i8) -> v16i8 {
@@ -7978,7 +7978,7 @@ pub unsafe fn __msa_slli_b<const IMM4: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(slli.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(slli.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_slli_h<const IMM3: i32>(a: v8i16) -> v8i16 {
@@ -7994,7 +7994,7 @@ pub unsafe fn __msa_slli_h<const IMM3: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(slli.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(slli.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_slli_w<const IMM2: i32>(a: v4i32) -> v4i32 {
@@ -8010,7 +8010,7 @@ pub unsafe fn __msa_slli_w<const IMM2: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(slli.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(slli.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_slli_d<const IMM1: i32>(a: v2i64) -> v2i64 {
@@ -8085,7 +8085,7 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(splati.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(splati.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_splati_b<const IMM4: i32>(a: v16i8) -> v16i8 {
@@ -8100,7 +8100,7 @@ pub unsafe fn __msa_splati_b<const IMM4: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(splati.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(splati.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_splati_h<const IMM3: i32>(a: v8i16) -> v8i16 {
@@ -8115,7 +8115,7 @@ pub unsafe fn __msa_splati_h<const IMM3: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(splati.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(splati.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_splati_w<const IMM2: i32>(a: v4i32) -> v4i32 {
@@ -8130,7 +8130,7 @@ pub unsafe fn __msa_splati_w<const IMM2: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(splati.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(splati.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_splati_d<const IMM1: i32>(a: v2i64) -> v2i64 {
@@ -8206,7 +8206,7 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srai.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(srai.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srai_b<const IMM3: i32>(a: v16i8) -> v16i8 {
@@ -8222,7 +8222,7 @@ pub unsafe fn __msa_srai_b<const IMM3: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srai.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(srai.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srai_h<const IMM4: i32>(a: v8i16) -> v8i16 {
@@ -8238,7 +8238,7 @@ pub unsafe fn __msa_srai_h<const IMM4: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srai.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(srai.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srai_w<const IMM5: i32>(a: v4i32) -> v4i32 {
@@ -8254,7 +8254,7 @@ pub unsafe fn __msa_srai_w<const IMM5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srai.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(srai.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srai_d<const IMM6: i32>(a: v2i64) -> v2i64 {
@@ -8335,7 +8335,7 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srari.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(srari.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srari_b<const IMM3: i32>(a: v16i8) -> v16i8 {
@@ -8352,7 +8352,7 @@ pub unsafe fn __msa_srari_b<const IMM3: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srari.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(srari.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srari_h<const IMM4: i32>(a: v8i16) -> v8i16 {
@@ -8369,7 +8369,7 @@ pub unsafe fn __msa_srari_h<const IMM4: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srari.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(srari.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srari_w<const IMM5: i32>(a: v4i32) -> v4i32 {
@@ -8386,7 +8386,7 @@ pub unsafe fn __msa_srari_w<const IMM5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srari.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(srari.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srari_d<const IMM6: i32>(a: v2i64) -> v2i64 {
@@ -8462,7 +8462,7 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srli.b, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(srli.b, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srli_b<const IMM4: i32>(a: v16i8) -> v16i8 {
@@ -8478,7 +8478,7 @@ pub unsafe fn __msa_srli_b<const IMM4: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srli.h, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(srli.h, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srli_h<const IMM3: i32>(a: v8i16) -> v8i16 {
@@ -8494,7 +8494,7 @@ pub unsafe fn __msa_srli_h<const IMM3: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srli.w, imm2 = 0b11))]
+#[cfg_attr(test, assert_instr(srli.w, IMM2 = 0b11))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srli_w<const IMM2: i32>(a: v4i32) -> v4i32 {
@@ -8510,7 +8510,7 @@ pub unsafe fn __msa_srli_w<const IMM2: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srli.d, imm1 = 0b1))]
+#[cfg_attr(test, assert_instr(srli.d, IMM1 = 0b1))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srli_d<const IMM1: i32>(a: v2i64) -> v2i64 {
@@ -8591,7 +8591,7 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srlri.b, imm3 = 0b111))]
+#[cfg_attr(test, assert_instr(srlri.b, IMM3 = 0b111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srlri_b<const IMM3: i32>(a: v16i8) -> v16i8 {
@@ -8608,7 +8608,7 @@ pub unsafe fn __msa_srlri_b<const IMM3: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srlri.h, imm4 = 0b1111))]
+#[cfg_attr(test, assert_instr(srlri.h, IMM4 = 0b1111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srlri_h<const IMM4: i32>(a: v8i16) -> v8i16 {
@@ -8625,7 +8625,7 @@ pub unsafe fn __msa_srlri_h<const IMM4: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srlri.w, imm5 = 0b11111))]
+#[cfg_attr(test, assert_instr(srlri.w, IMM5 = 0b11111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srlri_w<const IMM5: i32>(a: v4i32) -> v4i32 {
@@ -8642,7 +8642,7 @@ pub unsafe fn __msa_srlri_w<const IMM5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(srlri.d, imm6 = 0b111111))]
+#[cfg_attr(test, assert_instr(srlri.d, IMM6 = 0b111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_srlri_d<const IMM6: i32>(a: v2i64) -> v2i64 {
@@ -8658,7 +8658,7 @@ pub unsafe fn __msa_srlri_d<const IMM6: i32>(a: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(st.b, imm_s10 = 0b1111111111))]
+#[cfg_attr(test, assert_instr(st.b, IMM_S10 = -1))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_st_b<const IMM_S10: i32>(a: v16i8, mem_addr: *mut u8) -> () {
@@ -8674,7 +8674,7 @@ pub unsafe fn __msa_st_b<const IMM_S10: i32>(a: v16i8, mem_addr: *mut u8) -> ()
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(st.h, imm_s11 = 0b11111111111))]
+#[cfg_attr(test, assert_instr(st.h, IMM_S11 = -2))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_st_h<const IMM_S11: i32>(a: v8i16, mem_addr: *mut u8) -> () {
@@ -8691,7 +8691,7 @@ pub unsafe fn __msa_st_h<const IMM_S11: i32>(a: v8i16, mem_addr: *mut u8) -> ()
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(st.w, imm_s12 = 0b111111111111))]
+#[cfg_attr(test, assert_instr(st.w, IMM_S12 = -4))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_st_w<const IMM_S12: i32>(a: v4i32, mem_addr: *mut u8) -> () {
@@ -8708,7 +8708,7 @@ pub unsafe fn __msa_st_w<const IMM_S12: i32>(a: v4i32, mem_addr: *mut u8) -> ()
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(st.d, imm_s13 = 0b1111111111111))]
+#[cfg_attr(test, assert_instr(st.d, IMM_S13 = -8))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_st_d<const IMM_S13: i32>(a: v2i64, mem_addr: *mut u8) -> () {
@@ -9021,7 +9021,7 @@ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(subvi.b, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(subvi.b, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_subvi_b<const IMM5: i32>(a: v16i8) -> v16i8 {
@@ -9037,7 +9037,7 @@ pub unsafe fn __msa_subvi_b<const IMM5: i32>(a: v16i8) -> v16i8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(subvi.h, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(subvi.h, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_subvi_h<const IMM5: i32>(a: v8i16) -> v8i16 {
@@ -9053,7 +9053,7 @@ pub unsafe fn __msa_subvi_h<const IMM5: i32>(a: v8i16) -> v8i16 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(subvi.w, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(subvi.w, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_subvi_w<const IMM5: i32>(a: v4i32) -> v4i32 {
@@ -9069,7 +9069,7 @@ pub unsafe fn __msa_subvi_w<const IMM5: i32>(a: v4i32) -> v4i32 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(subvi.d, imm5 = 0b10111))]
+#[cfg_attr(test, assert_instr(subvi.d, IMM5 = 0b10111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_subvi_d<const IMM5: i32>(a: v2i64) -> v2i64 {
@@ -9173,7 +9173,7 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 {
 ///
 #[inline]
 #[target_feature(enable = "msa")]
-#[cfg_attr(test, assert_instr(xori.b, imm8 = 0b11111111))]
+#[cfg_attr(test, assert_instr(xori.b, IMM8 = 0b11111111))]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_mips", issue = "111198")]
 pub unsafe fn __msa_xori_b<const IMM8: i32>(a: v16u8) -> v16u8 {
@@ -9602,7 +9602,7 @@ mod tests {
             103, -126, 103, -126
         );
 
-        assert_eq!(r, mem::transmute(__msa_addvi_b(mem::transmute(a), 67)));
+        assert_eq!(r, mem::transmute(__msa_addvi_b::<3>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -9618,7 +9618,7 @@ mod tests {
             -32766, 3279, -97, -124
         );
 
-        assert_eq!(r, mem::transmute(__msa_addvi_h(mem::transmute(a), 67)));
+        assert_eq!(r, mem::transmute(__msa_addvi_h::<3>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -9628,7 +9628,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(103, -2147483646, 103, -2147483645);
 
-        assert_eq!(r, mem::transmute(__msa_addvi_w(mem::transmute(a), 67)));
+        assert_eq!(r, mem::transmute(__msa_addvi_w::<3>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -9638,7 +9638,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(117, -9223372036854775791);
 
-        assert_eq!(r, mem::transmute(__msa_addvi_d(mem::transmute(a), 17)));
+        assert_eq!(r, mem::transmute(__msa_addvi_d::<17>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -9688,7 +9688,7 @@ mod tests {
             4, 5, 4, 5
         );
 
-        assert_eq!(r, mem::transmute(__msa_andi_b(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_andi_b::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10233,7 +10233,7 @@ mod tests {
             247, 147, 55, 1
         );
 
-        assert_eq!(r, mem::transmute(__msa_bclri_b(mem::transmute(a), 3)));
+        assert_eq!(r, mem::transmute(__msa_bclri_b::<3>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10243,7 +10243,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u16x8::new(107, 1155, 155, 1, 107, 1155, 155, 1);
 
-        assert_eq!(r, mem::transmute(__msa_bclri_h(mem::transmute(a), 11)));
+        assert_eq!(r, mem::transmute(__msa_bclri_h::<11>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10253,7 +10253,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u32x4::new(202722547, 102722547, 2722547, 1);
 
-        assert_eq!(r, mem::transmute(__msa_bclri_w(mem::transmute(a), 23)));
+        assert_eq!(r, mem::transmute(__msa_bclri_w::<23>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10263,7 +10263,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u64x2::new(73672157683, 11110973672157683);
 
-        assert_eq!(r, mem::transmute(__msa_bclri_d(mem::transmute(a), 37)));
+        assert_eq!(r, mem::transmute(__msa_bclri_d::<37>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10408,7 +10408,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsli_b(mem::transmute(a), mem::transmute(b), 5))
+            mem::transmute(__msa_binsli_b::<5>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10432,7 +10432,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsli_h(mem::transmute(a), mem::transmute(b), 13))
+            mem::transmute(__msa_binsli_h::<13>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10447,7 +10447,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsli_w(mem::transmute(a), mem::transmute(b), 17))
+            mem::transmute(__msa_binsli_w::<17>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10462,7 +10462,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsli_d(mem::transmute(a), mem::transmute(b), 48))
+            mem::transmute(__msa_binsli_d::<48>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10608,7 +10608,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsri_b(mem::transmute(a), mem::transmute(b), 5))
+            mem::transmute(__msa_binsri_b::<5>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10632,7 +10632,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsri_h(mem::transmute(a), mem::transmute(b), 13))
+            mem::transmute(__msa_binsri_h::<13>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10647,7 +10647,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsri_w(mem::transmute(a), mem::transmute(b), 17))
+            mem::transmute(__msa_binsri_w::<17>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10662,7 +10662,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_binsri_d(mem::transmute(a), mem::transmute(b), 48))
+            mem::transmute(__msa_binsri_d::<48>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10733,7 +10733,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_bmnzi_b(mem::transmute(a), mem::transmute(b), 7))
+            mem::transmute(__msa_bmnzi_b::<7>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10804,7 +10804,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_bmzi_b(mem::transmute(a), mem::transmute(b), 7))
+            mem::transmute(__msa_bmzi_b::<7>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -10900,7 +10900,7 @@ mod tests {
             34, 116, 111, 239
         );
 
-        assert_eq!(r, mem::transmute(__msa_bnegi_b(mem::transmute(a), 4)));
+        assert_eq!(r, mem::transmute(__msa_bnegi_b::<4>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10916,7 +10916,7 @@ mod tests {
             30719, 1228, 2148, 2175
         );
 
-        assert_eq!(r, mem::transmute(__msa_bnegi_h(mem::transmute(a), 11)));
+        assert_eq!(r, mem::transmute(__msa_bnegi_h::<11>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10926,7 +10926,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u32x4::new(16777316, 2130706431, 16777316, 2164260864);
 
-        assert_eq!(r, mem::transmute(__msa_bnegi_w(mem::transmute(a), 24)));
+        assert_eq!(r, mem::transmute(__msa_bnegi_w::<24>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -10936,7 +10936,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u64x2::new(4398046511204, 9223376434901286912);
 
-        assert_eq!(r, mem::transmute(__msa_bnegi_d(mem::transmute(a), 42)));
+        assert_eq!(r, mem::transmute(__msa_bnegi_d::<42>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11065,7 +11065,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_bseli_b(mem::transmute(a), mem::transmute(b), 121))
+            mem::transmute(__msa_bseli_b::<121>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -11161,7 +11161,7 @@ mod tests {
             255, 159, 55, 5
         );
 
-        assert_eq!(r, mem::transmute(__msa_bseti_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_bseti_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11171,7 +11171,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u16x8::new(255, 159, 55, 5, 255, 159, 55, 5);
 
-        assert_eq!(r, mem::transmute(__msa_bseti_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_bseti_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11181,7 +11181,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u32x4::new(255, 159, 55, 5);
 
-        assert_eq!(r, mem::transmute(__msa_bseti_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_bseti_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11191,7 +11191,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u64x2::new(255, 159);
 
-        assert_eq!(r, mem::transmute(__msa_bseti_d(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_bseti_d::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11341,7 +11341,7 @@ mod tests {
             0, 0, -1, 0
         );
 
-        assert_eq!(r, mem::transmute(__msa_ceqi_b(mem::transmute(a), -4)));
+        assert_eq!(r, mem::transmute(__msa_ceqi_b::<-4>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11354,7 +11354,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1);
 
-        assert_eq!(r, mem::transmute(__msa_ceqi_h(mem::transmute(a), -11)));
+        assert_eq!(r, mem::transmute(__msa_ceqi_h::<-11>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11364,7 +11364,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(0, 0, -1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_ceqi_w(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_ceqi_w::<5>(mem::transmute(a))));
     }
 
     // FIXME: https://reviews.llvm.org/D59884
@@ -11551,7 +11551,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i8x16::new(-1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1);
 
-        assert_eq!(r, mem::transmute(__msa_clei_s_b(mem::transmute(a), -2)));
+        assert_eq!(r, mem::transmute(__msa_clei_s_b::<-2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11564,7 +11564,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1);
 
-        assert_eq!(r, mem::transmute(__msa_clei_s_h(mem::transmute(a), -1)));
+        assert_eq!(r, mem::transmute(__msa_clei_s_h::<-1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11574,7 +11574,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(0, 0, -1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clei_s_w(mem::transmute(a), 6)));
+        assert_eq!(r, mem::transmute(__msa_clei_s_w::<6>(mem::transmute(a))));
     }
 
     // FIXME: https://reviews.llvm.org/D59884
@@ -11607,7 +11607,7 @@ mod tests {
             -1, 0, 0, 0
         );
 
-        assert_eq!(r, mem::transmute(__msa_clei_u_b(mem::transmute(a), 25)));
+        assert_eq!(r, mem::transmute(__msa_clei_u_b::<25>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11620,7 +11620,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(-1, 0, -1, 0, -1, 0, -1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clei_u_h(mem::transmute(a), 25)));
+        assert_eq!(r, mem::transmute(__msa_clei_u_h::<25>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11630,7 +11630,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(-1, 0, -1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clei_u_w(mem::transmute(a), 31)));
+        assert_eq!(r, mem::transmute(__msa_clei_u_w::<31>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11640,7 +11640,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(-1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clei_u_d(mem::transmute(a), 25)));
+        assert_eq!(r, mem::transmute(__msa_clei_u_d::<25>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11810,7 +11810,7 @@ mod tests {
             0, -1, 0, 0
         );
 
-        assert_eq!(r, mem::transmute(__msa_clti_s_b(mem::transmute(a), -5)));
+        assert_eq!(r, mem::transmute(__msa_clti_s_b::<-5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11823,7 +11823,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(-1, 0, 0, 0, -1, 0, 0, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clti_s_h(mem::transmute(a), 15)));
+        assert_eq!(r, mem::transmute(__msa_clti_s_h::<15>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11833,7 +11833,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(-1, 0, -1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clti_s_w(mem::transmute(a), -10)));
+        assert_eq!(r, mem::transmute(__msa_clti_s_w::<-10>(mem::transmute(a))));
     }
 
     // FIXME: https://reviews.llvm.org/D59884
@@ -11866,7 +11866,7 @@ mod tests {
             -1, 0, 0, 0
         );
 
-        assert_eq!(r, mem::transmute(__msa_clti_u_b(mem::transmute(a), 50)));
+        assert_eq!(r, mem::transmute(__msa_clti_u_b::<3>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11879,7 +11879,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clti_u_h(mem::transmute(a), 30)));
+        assert_eq!(r, mem::transmute(__msa_clti_u_h::<30>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11889,7 +11889,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(0, 0, 0, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clti_u_w(mem::transmute(a), 10)));
+        assert_eq!(r, mem::transmute(__msa_clti_u_w::<10>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11899,7 +11899,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(-1, 0);
 
-        assert_eq!(r, mem::transmute(__msa_clti_u_d(mem::transmute(a), 10)));
+        assert_eq!(r, mem::transmute(__msa_clti_u_d::<10>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11914,7 +11914,7 @@ mod tests {
         #[rustfmt::skip]
         let r = -100 as i32;
 
-        assert_eq!(r, mem::transmute(__msa_copy_s_b(mem::transmute(a), 12)));
+        assert_eq!(r, mem::transmute(__msa_copy_s_b::<12>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11927,7 +11927,7 @@ mod tests {
         #[rustfmt::skip]
         let r = 32767 as i32;
 
-        assert_eq!(r, mem::transmute(__msa_copy_s_h(mem::transmute(a), 4)));
+        assert_eq!(r, mem::transmute(__msa_copy_s_h::<4>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11936,7 +11936,7 @@ mod tests {
         let a = i32x4::new(100, 2147483647, 5, -2147483647);
         let r = 2147483647 as i32;
 
-        assert_eq!(r, mem::transmute(__msa_copy_s_w(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_copy_s_w::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11946,7 +11946,7 @@ mod tests {
         #[rustfmt::skip]
         let r = 9223372036854775807 as i64;
 
-        assert_eq!(r, mem::transmute(__msa_copy_s_d(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_copy_s_d::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11961,7 +11961,7 @@ mod tests {
         #[rustfmt::skip]
         let r = 100 as u32;
 
-        assert_eq!(r, mem::transmute(__msa_copy_u_b(mem::transmute(a), 12)));
+        assert_eq!(r, mem::transmute(__msa_copy_u_b::<12>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11974,7 +11974,7 @@ mod tests {
         #[rustfmt::skip]
         let r = 32767 as u32;
 
-        assert_eq!(r, mem::transmute(__msa_copy_u_h(mem::transmute(a), 4)));
+        assert_eq!(r, mem::transmute(__msa_copy_u_h::<4>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11984,7 +11984,7 @@ mod tests {
         #[rustfmt::skip]
         let r = 2147483647 as u32;
 
-        assert_eq!(r, mem::transmute(__msa_copy_u_w(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_copy_u_w::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -11994,7 +11994,7 @@ mod tests {
         #[rustfmt::skip]
         let r = 9223372036854775807 as u64;
 
-        assert_eq!(r, mem::transmute(__msa_copy_u_d(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_copy_u_d::<1>(mem::transmute(a))));
     }
 
     // Can not be tested in user mode
@@ -14618,7 +14618,10 @@ mod tests {
             5, 127, 4, 127
         );
 
-        assert_eq!(r, mem::transmute(__msa_insert_b(mem::transmute(a), 12, 5)));
+        assert_eq!(
+            r,
+            mem::transmute(__msa_insert_b::<12>(mem::transmute(a), 5))
+        );
     }
 
     #[simd_test(enable = "msa")]
@@ -14634,7 +14637,7 @@ mod tests {
             5, 3276, 100, 11
         );
 
-        assert_eq!(r, mem::transmute(__msa_insert_h(mem::transmute(a), 4, 5)));
+        assert_eq!(r, mem::transmute(__msa_insert_h::<4>(mem::transmute(a), 5)));
     }
 
     #[simd_test(enable = "msa")]
@@ -14644,7 +14647,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(100, 7, 5, -2147483647);
 
-        assert_eq!(r, mem::transmute(__msa_insert_w(mem::transmute(a), 1, 7)));
+        assert_eq!(r, mem::transmute(__msa_insert_w::<1>(mem::transmute(a), 7)));
     }
 
     #[simd_test(enable = "msa")]
@@ -14654,7 +14657,10 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(3, 100);
 
-        assert_eq!(r, mem::transmute(__msa_insert_d(mem::transmute(a), 1, 100)));
+        assert_eq!(
+            r,
+            mem::transmute(__msa_insert_d::<1>(mem::transmute(a), 100))
+        );
     }
 
     #[simd_test(enable = "msa")]
@@ -14683,7 +14689,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_insve_b(mem::transmute(a), 12, mem::transmute(b)))
+            mem::transmute(__msa_insve_b::<12>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -14707,7 +14713,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_insve_h(mem::transmute(a), 4, mem::transmute(b)))
+            mem::transmute(__msa_insve_h::<4>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -14722,7 +14728,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_insve_w(mem::transmute(a), 3, mem::transmute(b)))
+            mem::transmute(__msa_insve_w::<3>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -14737,7 +14743,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_insve_d(mem::transmute(a), 1, mem::transmute(b)))
+            mem::transmute(__msa_insve_d::<1>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -14759,7 +14765,7 @@ mod tests {
             25, 26, 27, 28
         );
 
-        assert_eq!(r, mem::transmute(__msa_ld_b(p, 9)));
+        assert_eq!(r, mem::transmute(__msa_ld_b::<9>(p)));
     }
 
     #[simd_test(enable = "msa")]
@@ -14773,7 +14779,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(3, 4, 5, 6, 7, 8, 9, 10);
 
-        assert_eq!(r, mem::transmute(__msa_ld_h(p, -2)));
+        assert_eq!(r, mem::transmute(__msa_ld_h::<-2>(p)));
     }
 
     #[simd_test(enable = "msa")]
@@ -14784,7 +14790,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(2, 3, 4, 5);
 
-        assert_eq!(r, mem::transmute(__msa_ld_w(p, -4)));
+        assert_eq!(r, mem::transmute(__msa_ld_w::<-4>(p)));
     }
 
     #[simd_test(enable = "msa")]
@@ -14795,7 +14801,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(0, 1);
 
-        assert_eq!(r, mem::transmute(__msa_ld_d(p, -32)));
+        assert_eq!(r, mem::transmute(__msa_ld_d::<-32>(p)));
     }
 
     #[simd_test(enable = "msa")]
@@ -14808,7 +14814,7 @@ mod tests {
             -20, -20, -20, -20
         );
 
-        assert_eq!(r, mem::transmute(__msa_ldi_b(-20)));
+        assert_eq!(r, mem::transmute(__msa_ldi_b::<-20>()));
     }
 
     #[simd_test(enable = "msa")]
@@ -14819,7 +14825,7 @@ mod tests {
             255, 255, 255, 255
         );
 
-        assert_eq!(r, mem::transmute(__msa_ldi_h(255)));
+        assert_eq!(r, mem::transmute(__msa_ldi_h::<255>()));
     }
 
     #[simd_test(enable = "msa")]
@@ -14827,7 +14833,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(-509, -509, -509, -509);
 
-        assert_eq!(r, mem::transmute(__msa_ldi_w(-509)));
+        assert_eq!(r, mem::transmute(__msa_ldi_w::<-509>()));
     }
 
     // FIXME: https://reviews.llvm.org/D59884
@@ -15288,7 +15294,7 @@ mod tests {
             1, -16, -6, 8
         );
 
-        assert_eq!(r, mem::transmute(__msa_maxi_s_b(mem::transmute(a), -16)));
+        assert_eq!(r, mem::transmute(__msa_maxi_s_b::<-16>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15298,7 +15304,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15);
 
-        assert_eq!(r, mem::transmute(__msa_maxi_s_h(mem::transmute(a), 15)));
+        assert_eq!(r, mem::transmute(__msa_maxi_s_h::<15>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15308,7 +15314,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(1, 3, -5, -5);
 
-        assert_eq!(r, mem::transmute(__msa_maxi_s_w(mem::transmute(a), -5)));
+        assert_eq!(r, mem::transmute(__msa_maxi_s_w::<-5>(mem::transmute(a))));
     }
 
     // FIXME: https://reviews.llvm.org/D59884
@@ -15341,7 +15347,7 @@ mod tests {
             5, 5, 6, 8
         );
 
-        assert_eq!(r, mem::transmute(__msa_maxi_u_b(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_maxi_u_b::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15351,7 +15357,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u16x8::new(5, 5, 6, 8, 5, 5, 6, 8);
 
-        assert_eq!(r, mem::transmute(__msa_maxi_u_h(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_maxi_u_h::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15361,7 +15367,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u32x4::new(5, 5, 6, 8);
 
-        assert_eq!(r, mem::transmute(__msa_maxi_u_w(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_maxi_u_w::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15371,7 +15377,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u64x2::new(5, 8);
 
-        assert_eq!(r, mem::transmute(__msa_maxi_u_d(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_maxi_u_d::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15541,7 +15547,7 @@ mod tests {
             -10, -10, -10, -10
         );
 
-        assert_eq!(r, mem::transmute(__msa_mini_s_b(mem::transmute(a), -10)));
+        assert_eq!(r, mem::transmute(__msa_mini_s_b::<-10>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15551,7 +15557,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(-3, -3, -3, -4, -3, -3, -3, -4);
 
-        assert_eq!(r, mem::transmute(__msa_mini_s_h(mem::transmute(a), -3)));
+        assert_eq!(r, mem::transmute(__msa_mini_s_h::<-3>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15561,7 +15567,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(-3, -3, -3, -4);
 
-        assert_eq!(r, mem::transmute(__msa_mini_s_w(mem::transmute(a), -3)));
+        assert_eq!(r, mem::transmute(__msa_mini_s_w::<-3>(mem::transmute(a))));
     }
 
     // FIXME: https://reviews.llvm.org/D59884
@@ -15669,7 +15675,7 @@ mod tests {
             1, 3, 5, 5
         );
 
-        assert_eq!(r, mem::transmute(__msa_mini_u_b(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_mini_u_b::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15679,7 +15685,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u16x8::new(1, 3, 5, 5, 1, 3, 5, 5);
 
-        assert_eq!(r, mem::transmute(__msa_mini_u_h(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_mini_u_h::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15689,7 +15695,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u32x4::new(1, 3, 5, 5);
 
-        assert_eq!(r, mem::transmute(__msa_mini_u_w(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_mini_u_w::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -15699,7 +15705,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u64x2::new(1, 5);
 
-        assert_eq!(r, mem::transmute(__msa_mini_u_d(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_mini_u_d::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16393,7 +16399,7 @@ mod tests {
             242, 241, 240, 235
         );
 
-        assert_eq!(r, mem::transmute(__msa_nori_b(mem::transmute(a), 4)));
+        assert_eq!(r, mem::transmute(__msa_nori_b::<4>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16443,7 +16449,7 @@ mod tests {
             13, 14, 15, 20
         );
 
-        assert_eq!(r, mem::transmute(__msa_ori_b(mem::transmute(a), 4)));
+        assert_eq!(r, mem::transmute(__msa_ori_b::<4>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16669,7 +16675,7 @@ mod tests {
             3, 3, 3, 1
         );
 
-        assert_eq!(r, mem::transmute(__msa_sat_s_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_sat_s_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16682,7 +16688,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(127, 127, 127, 1, 127, 127, 127, 1);
 
-        assert_eq!(r, mem::transmute(__msa_sat_s_h(mem::transmute(a), 7)));
+        assert_eq!(r, mem::transmute(__msa_sat_s_h::<7>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16692,7 +16698,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(131071, 131071, 131071, 1);
 
-        assert_eq!(r, mem::transmute(__msa_sat_s_w(mem::transmute(a), 17)));
+        assert_eq!(r, mem::transmute(__msa_sat_s_w::<17>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16702,7 +16708,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(137438953471, 1);
 
-        assert_eq!(r, mem::transmute(__msa_sat_s_d(mem::transmute(a), 37)));
+        assert_eq!(r, mem::transmute(__msa_sat_s_d::<37>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16722,7 +16728,7 @@ mod tests {
             7, 7, 7, 1
         );
 
-        assert_eq!(r, mem::transmute(__msa_sat_u_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_sat_u_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16735,7 +16741,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u16x8::new(255, 255, 155, 1, 255, 255, 155, 1);
 
-        assert_eq!(r, mem::transmute(__msa_sat_u_h(mem::transmute(a), 7)));
+        assert_eq!(r, mem::transmute(__msa_sat_u_h::<7>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16745,7 +16751,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u32x4::new(262143, 262143, 262143, 1);
 
-        assert_eq!(r, mem::transmute(__msa_sat_u_w(mem::transmute(a), 17)));
+        assert_eq!(r, mem::transmute(__msa_sat_u_w::<17>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16755,7 +16761,7 @@ mod tests {
         #[rustfmt::skip]
         let r = u64x2::new(274877906943, 1);
 
-        assert_eq!(r, mem::transmute(__msa_sat_u_d(mem::transmute(a), 37)));
+        assert_eq!(r, mem::transmute(__msa_sat_u_d::<37>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16775,7 +16781,7 @@ mod tests {
             11, 3, 4, 12
         );
 
-        assert_eq!(r, mem::transmute(__msa_shf_b(mem::transmute(a), 120)));
+        assert_eq!(r, mem::transmute(__msa_shf_b::<120>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16788,7 +16794,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(11, 14, 12, 13, 11, 14, 12, 13);
 
-        assert_eq!(r, mem::transmute(__msa_shf_h(mem::transmute(a), 156)));
+        assert_eq!(r, mem::transmute(__msa_shf_h::<156>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16798,7 +16804,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(1, 3, 2, 4);
 
-        assert_eq!(r, mem::transmute(__msa_shf_w(mem::transmute(a), 216)));
+        assert_eq!(r, mem::transmute(__msa_shf_w::<216>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -16902,7 +16908,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_sldi_b(mem::transmute(a), mem::transmute(b), 5))
+            mem::transmute(__msa_sldi_b::<5>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -16917,7 +16923,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_sldi_h(mem::transmute(a), mem::transmute(b), 2))
+            mem::transmute(__msa_sldi_h::<2>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -16932,7 +16938,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_sldi_w(mem::transmute(a), mem::transmute(b), 4))
+            mem::transmute(__msa_sldi_w::<0>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -16947,7 +16953,7 @@ mod tests {
 
         assert_eq!(
             r,
-            mem::transmute(__msa_sldi_d(mem::transmute(a), mem::transmute(b), 2))
+            mem::transmute(__msa_sldi_d::<0>(mem::transmute(a), mem::transmute(b)))
         );
     }
 
@@ -17043,7 +17049,7 @@ mod tests {
             4, 8, 12, 16
         );
 
-        assert_eq!(r, mem::transmute(__msa_slli_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_slli_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17056,7 +17062,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(4, 8, 12, 16, 4, 8, 12, 16);
 
-        assert_eq!(r, mem::transmute(__msa_slli_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_slli_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17066,7 +17072,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(4, 8, 12, 16);
 
-        assert_eq!(r, mem::transmute(__msa_slli_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_slli_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17076,7 +17082,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(2, 4);
 
-        assert_eq!(r, mem::transmute(__msa_slli_d(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_slli_d::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17149,7 +17155,7 @@ mod tests {
             3, 3, 3, 3
         );
 
-        assert_eq!(r, mem::transmute(__msa_splati_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_splati_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17162,7 +17168,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3);
 
-        assert_eq!(r, mem::transmute(__msa_splati_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_splati_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17172,7 +17178,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(3, 3, 3, 3);
 
-        assert_eq!(r, mem::transmute(__msa_splati_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_splati_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17182,7 +17188,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(2, 2);
 
-        assert_eq!(r, mem::transmute(__msa_splati_d(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_splati_d::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17286,7 +17292,7 @@ mod tests {
             31, 31, 13, 0
         );
 
-        assert_eq!(r, mem::transmute(__msa_srai_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srai_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17299,7 +17305,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(8191, 31, 13, 0, 8191, 31, 13, 0);
 
-        assert_eq!(r, mem::transmute(__msa_srai_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srai_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17308,7 +17314,7 @@ mod tests {
         let a = i32x4::new(i32::MAX, 125, 55, 1);
         let r = i32x4::new(536870911, 31, 13, 0);
 
-        assert_eq!(r, mem::transmute(__msa_srai_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srai_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17318,7 +17324,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(2305843009213693951, 13);
 
-        assert_eq!(r, mem::transmute(__msa_srai_d(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srai_d::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17422,7 +17428,7 @@ mod tests {
             31, 32, 14, 0
         );
 
-        assert_eq!(r, mem::transmute(__msa_srari_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srari_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17432,7 +17438,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i16x8::new(539, 289, 39, 0, 539, 289, 39, 0);
 
-        assert_eq!(r, mem::transmute(__msa_srari_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srari_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17442,7 +17448,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(52777789, 27777789, 2777789, 0);
 
-        assert_eq!(r, mem::transmute(__msa_srari_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srari_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17452,7 +17458,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(52777777789, 27777777789);
 
-        assert_eq!(r, mem::transmute(__msa_srari_d(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srari_d::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17553,7 +17559,7 @@ mod tests {
             6, 12, 25, 31
         );
 
-        assert_eq!(r, mem::transmute(__msa_srli_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srli_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17569,7 +17575,7 @@ mod tests {
             8191, 819, 25, 31
         );
 
-        assert_eq!(r, mem::transmute(__msa_srli_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srli_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17579,7 +17585,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(25, 536870911, 25, 536870911);
 
-        assert_eq!(r, mem::transmute(__msa_srli_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srli_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17589,7 +17595,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(50, 4611686018427387903);
 
-        assert_eq!(r, mem::transmute(__msa_srli_d(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_srli_d::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17689,7 +17695,7 @@ mod tests {
             6, 13, 25, 32
         );
 
-        assert_eq!(r, mem::transmute(__msa_srlri_b(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srlri_b::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17701,7 +17707,7 @@ mod tests {
         );
         let r = i16x8::new(8192, 819, 25, 32, 8192, 819, 25, 32);
 
-        assert_eq!(r, mem::transmute(__msa_srlri_h(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srlri_h::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17711,7 +17717,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(25, 38, 50, 536870912);
 
-        assert_eq!(r, mem::transmute(__msa_srlri_w(mem::transmute(a), 2)));
+        assert_eq!(r, mem::transmute(__msa_srlri_w::<2>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17721,7 +17727,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(50, 4611686018427387904);
 
-        assert_eq!(r, mem::transmute(__msa_srlri_d(mem::transmute(a), 1)));
+        assert_eq!(r, mem::transmute(__msa_srlri_d::<1>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -17747,7 +17753,7 @@ mod tests {
             21, 22, 23, 24,
             25, 26, 27, 28
         ];
-        __msa_st_b(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+        __msa_st_b::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8);
         assert_eq!(arr, r);
     }
 
@@ -17758,7 +17764,7 @@ mod tests {
         let mut arr: [i16; 8] = [0, 0, 0, 0, 0, 0, 0, 0];
         #[rustfmt::skip]
         let r  : [i16; 8] = [13, 14, 15, 16, 17, 18, 19, 20];
-        __msa_st_h(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+        __msa_st_h::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8);
         assert_eq!(arr, r);
     }
 
@@ -17769,7 +17775,7 @@ mod tests {
         let mut arr: [i32; 4] = [0, 0, 0, 0];
         #[rustfmt::skip]
         let r  : [i32; 4] = [13, 14, 15, 16];
-        __msa_st_w(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+        __msa_st_w::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8);
         assert_eq!(arr, r);
     }
 
@@ -17780,7 +17786,7 @@ mod tests {
         let mut arr: [i64; 2] = [0, 0];
         #[rustfmt::skip]
         let r : [i64; 2] = [13, 14];
-        __msa_st_d(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+        __msa_st_d::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8);
         assert_eq!(arr, r);
     }
 
@@ -18194,7 +18200,7 @@ mod tests {
             95, 122, 45, 123
         );
 
-        assert_eq!(r, mem::transmute(__msa_subvi_b(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_subvi_b::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -18210,7 +18216,7 @@ mod tests {
             32762, 3271, -105, 32763
         );
 
-        assert_eq!(r, mem::transmute(__msa_subvi_h(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_subvi_h::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -18220,7 +18226,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i32x4::new(95, 145, 195, 2147483642);
 
-        assert_eq!(r, mem::transmute(__msa_subvi_w(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_subvi_w::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -18230,7 +18236,7 @@ mod tests {
         #[rustfmt::skip]
         let r = i64x2::new(95, 9223372036854775802);
 
-        assert_eq!(r, mem::transmute(__msa_subvi_d(mem::transmute(a), 5)));
+        assert_eq!(r, mem::transmute(__msa_subvi_d::<5>(mem::transmute(a))));
     }
 
     #[simd_test(enable = "msa")]
@@ -18392,6 +18398,6 @@ mod tests {
             9, 10, 11, 20
         );
 
-        assert_eq!(r, mem::transmute(__msa_xori_b(mem::transmute(a), 4)));
+        assert_eq!(r, mem::transmute(__msa_xori_b::<4>(mem::transmute(a))));
     }
 }
diff --git a/crates/simd-test-macro/src/lib.rs b/crates/simd-test-macro/src/lib.rs
index 92bb40946e..9219540a10 100644
--- a/crates/simd-test-macro/src/lib.rs
+++ b/crates/simd-test-macro/src/lib.rs
@@ -71,6 +71,7 @@ pub fn simd_test(
         "powerpc64" | "powerpc64le" => "is_powerpc64_feature_detected",
         "loongarch32" | "loongarch64" => "is_loongarch_feature_detected",
         "s390x" => "is_s390x_feature_detected",
+        "mips64" | "mips64el" => "is_mips64_feature_detected",
         t => panic!("unknown target: {t}"),
     };
     let macro_test = Ident::new(macro_test, Span::call_site());

From fbbd31b1b3335514dc11087f1e93f636e3410896 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 15 Apr 2026 12:26:33 +0200
Subject: [PATCH 248/326] provide a reminder on the signedness of a failed
 `assert_simm_bits`

---
 crates/core_arch/src/macros.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/core_arch/src/macros.rs b/crates/core_arch/src/macros.rs
index 00e92428b3..ee16f5eb69 100644
--- a/crates/core_arch/src/macros.rs
+++ b/crates/core_arch/src/macros.rs
@@ -26,7 +26,7 @@ macro_rules! static_assert_uimm_bits {
                     stringify!($imm),
                     " doesn't fit in ",
                     stringify!($bits),
-                    " bits",
+                    " bits (unsigned)",
                 )
             )
         }
@@ -42,7 +42,7 @@ macro_rules! static_assert_simm_bits {
                 stringify!($imm),
                 " doesn't fit in ",
                 stringify!($bits),
-                " bits",
+                " bits (signed)",
             )
         )
     };

From a690147be84ac1c7dd305f6a02d38ad7f430b0dc Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Fri, 20 Mar 2026 10:05:34 +0800
Subject: [PATCH 249/326] stdarch-gen-loongarch: Support marking intrinsics as
 portable

---
 crates/stdarch-gen-loongarch/src/main.rs      | 23 ++++++++++++++++++-
 .../src/portable-intrinsics.txt               |  2 ++
 2 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 crates/stdarch-gen-loongarch/src/portable-intrinsics.txt

diff --git a/crates/stdarch-gen-loongarch/src/main.rs b/crates/stdarch-gen-loongarch/src/main.rs
index 3a946a12d6..8bdee521a3 100644
--- a/crates/stdarch-gen-loongarch/src/main.rs
+++ b/crates/stdarch-gen-loongarch/src/main.rs
@@ -1,3 +1,4 @@
+use std::collections::HashSet;
 use std::env;
 use std::fmt;
 use std::fs::File;
@@ -90,6 +91,14 @@ impl TargetFeature {
     }
 }
 
+fn portable_intrinsics() -> HashSet<&'static str> {
+    include_str!("portable-intrinsics.txt")
+        .lines()
+        .map(str::trim)
+        .filter(|line| !line.is_empty() && !line.starts_with('#'))
+        .collect()
+}
+
 fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> {
     let f = File::open(in_file.clone()).unwrap_or_else(|_| panic!("Failed to open {in_file}"));
     let f = BufReader::new(f);
@@ -105,6 +114,7 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> {
     let mut asm_fmts = String::new();
     let mut data_types = String::new();
     let fn_pat = format!("__{ext_name}_");
+    let portable_intrinsics = portable_intrinsics();
     for line in f.lines() {
         let line = line.unwrap();
         if line.is_empty() {
@@ -121,6 +131,9 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> {
             let e = line.find('(').unwrap();
             let name = line.get(s + 2..e).unwrap().trim().to_string();
             out.push_str(&format!("/// {name}\n"));
+            if portable_intrinsics.contains(name.as_str()) {
+                out.push_str("impl = portable\n");
+            }
             out.push_str(&format!("name = {name}\n"));
             out.push_str(&format!("asm-fmts = {asm_fmts}\n"));
             out.push_str(&format!("data-types = {data_types}\n"));
@@ -146,6 +159,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> {
     let mut link_function_str = String::new();
     let mut function_str = String::new();
     let mut out = String::new();
+    let mut skip = false;
 
     out.push_str(&format!(
         r#"// This code is automatically generated. DO NOT MODIFY.
@@ -173,7 +187,9 @@ unsafe extern "unadjusted" {
         if line.is_empty() {
             continue;
         }
-        if let Some(name) = line.strip_prefix("name = ") {
+        if line.starts_with("impl = portable") {
+            skip = true;
+        } else if let Some(name) = line.strip_prefix("name = ") {
             current_name = Some(String::from(name));
         } else if line.starts_with("asm-fmts = ") {
             asm_fmts = line[10..]
@@ -210,6 +226,11 @@ unsafe extern "unadjusted" {
                 panic!("DEBUG: line: {0} len: {1}", line, data_types.len());
             }
 
+            if skip {
+                skip = false;
+                continue;
+            }
+
             let (link_function, function) =
                 gen_bind_body(&current_name, &asm_fmts, &in_t, out_t, para_num, target);
             link_function_str.push_str(&link_function);
diff --git a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
new file mode 100644
index 0000000000..b62f7f5f8f
--- /dev/null
+++ b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -0,0 +1,2 @@
+# LSX intrinsics
+# LASX intrinsics

From b749efb9dd7e9c5b79cf90c551b455772acade59 Mon Sep 17 00:00:00 2001
From: teor <teor@riseup.net>
Date: Wed, 8 Apr 2026 15:02:38 +1000
Subject: [PATCH 250/326] Fix typos near the refactor

---
 crates/stdarch-gen-arm/src/intrinsic.rs | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index ce427d54b3..7ce0e31750 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -550,7 +550,7 @@ impl LLVMLink {
 
     /// Alters all the unsigned types from the signature. This is required where
     /// a signed and unsigned variant require the same binding to an exposed
-    /// LLVM instrinsic.
+    /// LLVM intrinsic.
     pub fn sanitise_uints(&mut self) {
         let transform = |tk: &mut TypeKind| {
             if let Some(BaseType::Sized(BaseTypeKind::UInt, size)) = tk.base_type() {
@@ -1139,7 +1139,7 @@ impl Intrinsic {
             } else {
                 /* If we do not need to reorder anything then immediately add
                  * the expressions from the big_endian_expressions and
-                 * concatinate the compose vector */
+                 * concatenate the compose vector */
                 variant.big_endian_compose.extend(big_endian_expressions);
                 variant
                     .big_endian_compose
@@ -1157,11 +1157,11 @@ impl Intrinsic {
 
             /* If we do not create a shuffle call we do not need modify the
              * return value and append to the big endian ast array. A bit confusing
-             * as in code we are making the final call before caputuring the return
+             * as in code we are making the final call before capturing the return
              * value of the intrinsic that has been called.*/
             let ret_val_name = "ret_val".to_string();
             if let Some(simd_shuffle_call) = create_shuffle_call(&ret_val_name, return_type) {
-                /* There is a possibility that the funcion arguments did not
+                /* There is a possibility that the function arguments did not
                  * require big endian treatment, thus we need to now add the
                  * original function body before appending the return value.*/
                 if variant.big_endian_compose.is_empty() {
@@ -1695,8 +1695,8 @@ enum Endianness {
     NA,
 }
 
-/// Based on the endianess will create the appropriate intrinsic, or simply
-/// create the desired intrinsic without any endianess
+/// Based on the endianness will create the appropriate intrinsic, or simply
+/// create the desired intrinsic without any endianness
 fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut TokenStream) {
     let signature = &intrinsic.signature;
     let fn_name = signature.fn_name().to_string();

From 9a093762ca2ec102d75fab447ef86159f198ff38 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Wed, 8 Apr 2026 09:52:17 -0700
Subject: [PATCH 251/326] hexagon: Add scalar DSP intrinsics

---
 Cargo.lock                                    |   150 +-
 crates/core_arch/src/hexagon/mod.rs           |    15 +-
 crates/core_arch/src/hexagon/scalar.rs        | 12181 ++++++++++++++++
 crates/stdarch-gen-hexagon-scalar/Cargo.toml  |     9 +
 .../hexagon_protos.h                          |  8439 +++++++++++
 crates/stdarch-gen-hexagon-scalar/src/main.rs |   672 +
 examples/gaussian.rs                          |     7 +-
 7 files changed, 21392 insertions(+), 81 deletions(-)
 create mode 100644 crates/core_arch/src/hexagon/scalar.rs
 create mode 100644 crates/stdarch-gen-hexagon-scalar/Cargo.toml
 create mode 100644 crates/stdarch-gen-hexagon-scalar/hexagon_protos.h
 create mode 100644 crates/stdarch-gen-hexagon-scalar/src/main.rs

diff --git a/Cargo.lock b/Cargo.lock
index 7e7cb59288..a1c31fa9f0 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -13,9 +13,9 @@ dependencies = [
 
 [[package]]
 name = "anstream"
-version = "0.6.21"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a"
+checksum = "824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d"
 dependencies = [
  "anstyle",
  "anstyle-parse",
@@ -28,15 +28,15 @@ dependencies = [
 
 [[package]]
 name = "anstyle"
-version = "1.0.13"
+version = "1.0.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78"
+checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000"
 
 [[package]]
 name = "anstyle-parse"
-version = "0.2.7"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4e7644824f0aa2c7b9384579234ef10eb7efb6a0deb83f9630a49594dd9c15c2"
+checksum = "52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e"
 dependencies = [
  "utf8parse",
 ]
@@ -63,9 +63,9 @@ dependencies = [
 
 [[package]]
 name = "anyhow"
-version = "1.0.101"
+version = "1.0.102"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5f0e0fee31ef5ed1ba1316088939cea399010ed7731dba877ed44aeb407a75ea"
+checksum = "7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c"
 
 [[package]]
 name = "assert-instr-macro"
@@ -84,15 +84,15 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8"
 
 [[package]]
 name = "bitflags"
-version = "2.10.0"
+version = "2.11.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "812e12b5285cc515a9c72a5c1d3b6d46a19dac5acfef5265968c166106e31dd3"
+checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af"
 
 [[package]]
 name = "cc"
-version = "1.2.55"
+version = "1.2.59"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "47b26a0954ae34af09b50f0de26458fa95369a0d478d8236d3f93082b219bd29"
+checksum = "b7a4d3ec6524d28a329fc53654bbadc9bdd7b0431f5d65f1a56ffb28a1ee5283"
 dependencies = [
  "find-msvc-tools",
  "shlex",
@@ -106,9 +106,9 @@ checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801"
 
 [[package]]
 name = "clap"
-version = "4.5.58"
+version = "4.6.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "63be97961acde393029492ce0be7a1af7e323e6bae9511ebfac33751be5e6806"
+checksum = "b193af5b67834b676abd72466a96c1024e6a6ad978a1f484bd90b85c94041351"
 dependencies = [
  "clap_builder",
  "clap_derive",
@@ -116,9 +116,9 @@ dependencies = [
 
 [[package]]
 name = "clap_builder"
-version = "4.5.58"
+version = "4.6.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7f13174bda5dfd69d7e947827e5af4b0f2f94a4a3ee92912fba07a66150f21e2"
+checksum = "714a53001bf66416adb0e2ef5ac857140e7dc3a0c48fb28b2f10762fc4b5069f"
 dependencies = [
  "anstream",
  "anstyle",
@@ -128,9 +128,9 @@ dependencies = [
 
 [[package]]
 name = "clap_derive"
-version = "4.5.55"
+version = "4.6.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5"
+checksum = "1110bd8a634a1ab8cb04345d8d878267d57c3cf1b38d91b71af6686408bbca6a"
 dependencies = [
  "heck",
  "proc-macro2",
@@ -140,15 +140,15 @@ dependencies = [
 
 [[package]]
 name = "clap_lex"
-version = "1.0.0"
+version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831"
+checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9"
 
 [[package]]
 name = "colorchoice"
-version = "1.0.4"
+version = "1.0.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75"
+checksum = "1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570"
 
 [[package]]
 name = "core_arch"
@@ -185,9 +185,9 @@ checksum = "d0a5c400df2834b80a4c3327b3aad3a4c4cd4de0629063962b03235697506a28"
 
 [[package]]
 name = "darling"
-version = "0.21.3"
+version = "0.23.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9cdf337090841a411e2a7f3deb9187445851f91b309c0c0a29e05f74a00a48c0"
+checksum = "25ae13da2f202d56bd7f91c25fba009e7717a1e4a1cc98a76d844b65ae912e9d"
 dependencies = [
  "darling_core",
  "darling_macro",
@@ -195,11 +195,10 @@ dependencies = [
 
 [[package]]
 name = "darling_core"
-version = "0.21.3"
+version = "0.23.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1247195ecd7e3c85f83c8d2a366e4210d588e802133e1e355180a9870b517ea4"
+checksum = "9865a50f7c335f53564bb694ef660825eb8610e0a53d3e11bf1b0d3df31e03b0"
 dependencies = [
- "fnv",
  "ident_case",
  "proc-macro2",
  "quote",
@@ -209,9 +208,9 @@ dependencies = [
 
 [[package]]
 name = "darling_macro"
-version = "0.21.3"
+version = "0.23.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d38308df82d1080de0afee5d069fa14b0326a88c14f15c5ccda35b4a6c414c81"
+checksum = "ac3984ec7bd6cfa798e62b4a642426a5be0e68f9401cfc2a01e3fa9ea2fcdb8d"
 dependencies = [
  "darling_core",
  "quote",
@@ -232,9 +231,9 @@ checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719"
 
 [[package]]
 name = "env_filter"
-version = "1.0.0"
+version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7a1c3cc8e57274ec99de65301228b537f1e4eedc1b8e0f9411c6caac8ae7308f"
+checksum = "32e90c2accc4b07a8456ea0debdc2e7587bdd890680d71173a15d4ae604f6eef"
 dependencies = [
  "log",
  "regex",
@@ -255,9 +254,9 @@ dependencies = [
 
 [[package]]
 name = "env_logger"
-version = "0.11.9"
+version = "0.11.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b2daee4ea451f429a58296525ddf28b45a3b64f1acf6587e2067437bb11e218d"
+checksum = "0621c04f2196ac3f488dd583365b9c09be011a4ab8b9f37248ffcc8f6198b56a"
 dependencies = [
  "env_filter",
  "log",
@@ -275,12 +274,6 @@ version = "0.1.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582"
 
-[[package]]
-name = "fnv"
-version = "1.0.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1"
-
 [[package]]
 name = "foldhash"
 version = "0.1.5"
@@ -300,9 +293,9 @@ dependencies = [
 
 [[package]]
 name = "getrandom"
-version = "0.4.1"
+version = "0.4.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "139ef39800118c7683f2fd3c98c1b23c09ae076556b435f8e9064ae108aaeeec"
+checksum = "0de51e6874e94e7bf76d726fc5d13ba782deca734ff60d5bb2fb2607c7406555"
 dependencies = [
  "cfg-if",
  "libc",
@@ -375,9 +368,9 @@ dependencies = [
 
 [[package]]
 name = "indexmap"
-version = "2.13.0"
+version = "2.13.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017"
+checksum = "45a8a2b9cb3e0b0c1803dbb0758ffac5de2f425b23c28f518faabd9d805342ff"
 dependencies = [
  "equivalent",
  "hashbrown 0.16.1",
@@ -430,9 +423,9 @@ dependencies = [
 
 [[package]]
 name = "itoa"
-version = "1.0.17"
+version = "1.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "92ecc6618181def0457392ccd0ee51198e065e016d1d527a7ac1b6dc7c1f09d2"
+checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682"
 
 [[package]]
 name = "leb128fmt"
@@ -442,9 +435,9 @@ checksum = "09edd9e8b54e49e587e4f6295a7d29c3ea94d469cb40ab8ca70b288248a81db2"
 
 [[package]]
 name = "libc"
-version = "0.2.181"
+version = "0.2.184"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "459427e2af2b9c839b132acb702a1c654d95e10f8c326bfc2ad11310e458b1c5"
+checksum = "48f5d2a454e16a5ea0f4ced81bd44e4cfc7bd3a507b61887c99fd3538b28e4af"
 
 [[package]]
 name = "linked-hash-map"
@@ -534,25 +527,25 @@ version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "95c589f335db0f6aaa168a7cd27b1fc6920f5e1470c804f814d9cd6e62a0f70b"
 dependencies = [
- "env_logger 0.11.9",
+ "env_logger 0.11.10",
  "log",
  "rand 0.10.0",
 ]
 
 [[package]]
 name = "quote"
-version = "1.0.44"
+version = "1.0.45"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4"
+checksum = "41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924"
 dependencies = [
  "proc-macro2",
 ]
 
 [[package]]
 name = "r-efi"
-version = "5.3.0"
+version = "6.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
+checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf"
 
 [[package]]
 name = "rand"
@@ -571,7 +564,7 @@ version = "0.10.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "bc266eb313df6c5c09c1c7b1fbe2510961e5bcd3add930c1e31f7ed9da0feff8"
 dependencies = [
- "getrandom 0.4.1",
+ "getrandom 0.4.2",
  "rand_core 0.10.0",
 ]
 
@@ -645,9 +638,9 @@ dependencies = [
 
 [[package]]
 name = "regex-syntax"
-version = "0.8.9"
+version = "0.8.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a96887878f22d7bad8a3b6dc5b7440e0ada9a245242924394987b21cf2210a4c"
+checksum = "dc897dd8d9e8bd1ed8cdad82b5966c3e0ecae09fb1907d58efaa013543185d0a"
 
 [[package]]
 name = "rustc-demangle"
@@ -672,9 +665,9 @@ dependencies = [
 
 [[package]]
 name = "semver"
-version = "1.0.27"
+version = "1.0.28"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d767eb0aabc880b29956c35734170f26ed551a859dbd361d140cdbeca61ab1e2"
+checksum = "8a7852d02fc848982e0c167ef163aaff9cd91dc640ba85e263cb1ce46fae51cd"
 
 [[package]]
 name = "serde"
@@ -733,9 +726,9 @@ dependencies = [
 
 [[package]]
 name = "serde_with"
-version = "3.16.1"
+version = "3.18.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4fa237f2807440d238e0364a218270b98f767a00d3dada77b1c53ae88940e2e7"
+checksum = "dd5414fad8e6907dbdd5bc441a50ae8d6e26151a03b1de04d89a5576de61d01f"
 dependencies = [
  "serde_core",
  "serde_with_macros",
@@ -743,9 +736,9 @@ dependencies = [
 
 [[package]]
 name = "serde_with_macros"
-version = "3.16.1"
+version = "3.18.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "52a8e3ca0ca629121f70ab50f95249e5a6f925cc0f6ffe8256c45b728875706c"
+checksum = "d3db8978e608f1fe7357e211969fd9abdcae80bac1ba7a3369bb7eb6b404eb65"
 dependencies = [
  "darling",
  "proc-macro2",
@@ -801,6 +794,13 @@ dependencies = [
  "regex",
 ]
 
+[[package]]
+name = "stdarch-gen-hexagon-scalar"
+version = "0.1.0"
+dependencies = [
+ "regex",
+]
+
 [[package]]
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
@@ -849,9 +849,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.115"
+version = "2.0.117"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6e614ed320ac28113fa64972c4262d5dbc89deacdfd00c34a3e4cea073243c12"
+checksum = "e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -895,9 +895,9 @@ dependencies = [
 
 [[package]]
 name = "unicode-ident"
-version = "1.0.23"
+version = "1.0.24"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "537dd038a89878be9b64dd4bd1b260315c1bb94f4d784956b81e27a088d9a09e"
+checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75"
 
 [[package]]
 name = "unicode-xid"
@@ -962,7 +962,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "bb0e353e6a2fbdc176932bbaab493762eb1255a7900fe0fea1a2f96c296cc909"
 dependencies = [
  "anyhow",
- "indexmap 2.13.0",
+ "indexmap 2.13.1",
  "wasm-encoder",
  "wasmparser 0.244.0",
 ]
@@ -974,7 +974,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917"
 dependencies = [
  "bitflags",
- "indexmap 2.13.0",
+ "indexmap 2.13.1",
  "semver",
 ]
 
@@ -986,7 +986,7 @@ checksum = "47b807c72e1bac69382b3a6fb3dbe8ea4c0ed87ff5629b8685ae6b9a611028fe"
 dependencies = [
  "bitflags",
  "hashbrown 0.15.5",
- "indexmap 2.13.0",
+ "indexmap 2.13.1",
  "semver",
 ]
 
@@ -1053,7 +1053,7 @@ checksum = "b7c566e0f4b284dd6561c786d9cb0142da491f46a9fbed79ea69cdad5db17f21"
 dependencies = [
  "anyhow",
  "heck",
- "indexmap 2.13.0",
+ "indexmap 2.13.1",
  "prettyplease",
  "syn",
  "wasm-metadata",
@@ -1084,7 +1084,7 @@ checksum = "9d66ea20e9553b30172b5e831994e35fbde2d165325bec84fc43dbf6f4eb9cb2"
 dependencies = [
  "anyhow",
  "bitflags",
- "indexmap 2.13.0",
+ "indexmap 2.13.1",
  "log",
  "serde",
  "serde_derive",
@@ -1103,7 +1103,7 @@ checksum = "ecc8ac4bc1dc3381b7f59c34f00b67e18f910c2c0f50015669dde7def656a736"
 dependencies = [
  "anyhow",
  "id-arena",
- "indexmap 2.13.0",
+ "indexmap 2.13.1",
  "log",
  "semver",
  "serde",
@@ -1130,18 +1130,18 @@ dependencies = [
 
 [[package]]
 name = "zerocopy"
-version = "0.8.39"
+version = "0.8.48"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a"
+checksum = "eed437bf9d6692032087e337407a86f04cd8d6a16a37199ed57949d415bd68e9"
 dependencies = [
  "zerocopy-derive",
 ]
 
 [[package]]
 name = "zerocopy-derive"
-version = "0.8.39"
+version = "0.8.48"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517"
+checksum = "70e3cd084b1788766f53af483dd21f93881ff30d7320490ec3ef7526d203bad4"
 dependencies = [
  "proc-macro2",
  "quote",
diff --git a/crates/core_arch/src/hexagon/mod.rs b/crates/core_arch/src/hexagon/mod.rs
index c370f3da15..c973f7dc62 100644
--- a/crates/core_arch/src/hexagon/mod.rs
+++ b/crates/core_arch/src/hexagon/mod.rs
@@ -1,13 +1,18 @@
 //! Hexagon architecture intrinsics
 //!
 //! This module contains intrinsics for the Qualcomm Hexagon DSP architecture,
-//! including the Hexagon Vector Extensions (HVX).
+//! including scalar operations and the Hexagon Vector Extensions (HVX).
+//!
+//! ## Scalar Intrinsics
+//!
+//! The [`scalar`] module provides intrinsics for scalar DSP operations including
+//! arithmetic, multiply, shift, saturate, compare, and floating-point operations.
+//!
+//! ## HVX Vector Intrinsics
 //!
 //! HVX is a wide SIMD architecture designed for high-performance signal processing,
 //! machine learning, and image processing workloads.
 //!
-//! ## Vector Length Modes
-//!
 //! HVX supports two vector length modes:
 //! - 64-byte mode (512-bit vectors): Use the [`v64`] module
 //! - 128-byte mode (1024-bit vectors): Use the [`v128`] module
@@ -20,6 +25,10 @@
 //! Note that HVX v66 and later default to 128-byte mode, while earlier versions
 //! (v60-v65) default to 64-byte mode.
 
+/// Scalar intrinsics for Hexagon DSP operations
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub mod scalar;
+
 /// HVX intrinsics for 64-byte vector mode (512-bit vectors)
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub mod v64;
diff --git a/crates/core_arch/src/hexagon/scalar.rs b/crates/core_arch/src/hexagon/scalar.rs
new file mode 100644
index 0000000000..c906ec5166
--- /dev/null
+++ b/crates/core_arch/src/hexagon/scalar.rs
@@ -0,0 +1,12181 @@
+//! Hexagon scalar intrinsics
+//!
+//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations,
+//! including arithmetic, multiply, shift, saturate, compare, and floating-point
+//! operations.
+//!
+//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45)
+//!
+//! ## Naming Convention
+//!
+//! Function names preserve the original Q6 naming case because the convention
+//! uses case to distinguish register types:
+//! - `P` (uppercase) = 64-bit register pair (`Word64`)
+//! - `p` (lowercase) = predicate register (`Byte`)
+//!
+//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp`
+//! operates on predicate registers.
+//!
+//! ## Architecture Versions
+//!
+//! Most scalar intrinsics are available on all Hexagon architectures.
+//! Some intrinsics require specific architecture versions (v60, v62, v65,
+//! v66, v67, v68, or v67+audio) and carry
+//! `#[target_feature(enable = "v68")]` (or the appropriate version).
+//! Enable these with `-C target-feature=+v68` or by setting the target CPU
+//! via `-C target-cpu=hexagonv68`.
+//!
+//! Each version includes all features from previous versions.
+
+#![allow(non_snake_case)]
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+// LLVM intrinsic declarations for Hexagon scalar operations
+#[allow(improper_ctypes)]
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.hexagon.A2.abs"]
+    fn hexagon_A2_abs(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.absp"]
+    fn hexagon_A2_absp(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.abssat"]
+    fn hexagon_A2_abssat(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.add"]
+    fn hexagon_A2_add(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.hh"]
+    fn hexagon_A2_addh_h16_hh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.hl"]
+    fn hexagon_A2_addh_h16_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.lh"]
+    fn hexagon_A2_addh_h16_lh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.ll"]
+    fn hexagon_A2_addh_h16_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.sat.hh"]
+    fn hexagon_A2_addh_h16_sat_hh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.sat.hl"]
+    fn hexagon_A2_addh_h16_sat_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.sat.lh"]
+    fn hexagon_A2_addh_h16_sat_lh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.h16.sat.ll"]
+    fn hexagon_A2_addh_h16_sat_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.l16.hl"]
+    fn hexagon_A2_addh_l16_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.l16.ll"]
+    fn hexagon_A2_addh_l16_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.l16.sat.hl"]
+    fn hexagon_A2_addh_l16_sat_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addh.l16.sat.ll"]
+    fn hexagon_A2_addh_l16_sat_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addi"]
+    fn hexagon_A2_addi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addp"]
+    fn hexagon_A2_addp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.addpsat"]
+    fn hexagon_A2_addpsat(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.addsat"]
+    fn hexagon_A2_addsat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.addsp"]
+    fn hexagon_A2_addsp(_: i32, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.and"]
+    fn hexagon_A2_and(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.andir"]
+    fn hexagon_A2_andir(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.andp"]
+    fn hexagon_A2_andp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.aslh"]
+    fn hexagon_A2_aslh(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.asrh"]
+    fn hexagon_A2_asrh(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.combine.hh"]
+    fn hexagon_A2_combine_hh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.combine.hl"]
+    fn hexagon_A2_combine_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.combine.lh"]
+    fn hexagon_A2_combine_lh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.combine.ll"]
+    fn hexagon_A2_combine_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.combineii"]
+    fn hexagon_A2_combineii(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A2.combinew"]
+    fn hexagon_A2_combinew(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A2.max"]
+    fn hexagon_A2_max(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.maxp"]
+    fn hexagon_A2_maxp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.maxu"]
+    fn hexagon_A2_maxu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.maxup"]
+    fn hexagon_A2_maxup(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.min"]
+    fn hexagon_A2_min(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.minp"]
+    fn hexagon_A2_minp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.minu"]
+    fn hexagon_A2_minu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.minup"]
+    fn hexagon_A2_minup(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.neg"]
+    fn hexagon_A2_neg(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.negp"]
+    fn hexagon_A2_negp(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.negsat"]
+    fn hexagon_A2_negsat(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.not"]
+    fn hexagon_A2_not(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.notp"]
+    fn hexagon_A2_notp(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.or"]
+    fn hexagon_A2_or(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.orir"]
+    fn hexagon_A2_orir(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.orp"]
+    fn hexagon_A2_orp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.roundsat"]
+    fn hexagon_A2_roundsat(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.sat"]
+    fn hexagon_A2_sat(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.satb"]
+    fn hexagon_A2_satb(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.sath"]
+    fn hexagon_A2_sath(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.satub"]
+    fn hexagon_A2_satub(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.satuh"]
+    fn hexagon_A2_satuh(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.sub"]
+    fn hexagon_A2_sub(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.hh"]
+    fn hexagon_A2_subh_h16_hh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.hl"]
+    fn hexagon_A2_subh_h16_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.lh"]
+    fn hexagon_A2_subh_h16_lh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.ll"]
+    fn hexagon_A2_subh_h16_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.sat.hh"]
+    fn hexagon_A2_subh_h16_sat_hh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.sat.hl"]
+    fn hexagon_A2_subh_h16_sat_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.sat.lh"]
+    fn hexagon_A2_subh_h16_sat_lh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.h16.sat.ll"]
+    fn hexagon_A2_subh_h16_sat_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.l16.hl"]
+    fn hexagon_A2_subh_l16_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.l16.ll"]
+    fn hexagon_A2_subh_l16_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.l16.sat.hl"]
+    fn hexagon_A2_subh_l16_sat_hl(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subh.l16.sat.ll"]
+    fn hexagon_A2_subh_l16_sat_ll(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subp"]
+    fn hexagon_A2_subp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.subri"]
+    fn hexagon_A2_subri(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.subsat"]
+    fn hexagon_A2_subsat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svaddh"]
+    fn hexagon_A2_svaddh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svaddhs"]
+    fn hexagon_A2_svaddhs(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svadduhs"]
+    fn hexagon_A2_svadduhs(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svavgh"]
+    fn hexagon_A2_svavgh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svavghs"]
+    fn hexagon_A2_svavghs(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svnavgh"]
+    fn hexagon_A2_svnavgh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svsubh"]
+    fn hexagon_A2_svsubh(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svsubhs"]
+    fn hexagon_A2_svsubhs(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.svsubuhs"]
+    fn hexagon_A2_svsubuhs(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.swiz"]
+    fn hexagon_A2_swiz(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.sxtb"]
+    fn hexagon_A2_sxtb(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.sxth"]
+    fn hexagon_A2_sxth(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.sxtw"]
+    fn hexagon_A2_sxtw(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.A2.tfr"]
+    fn hexagon_A2_tfr(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.tfrih"]
+    fn hexagon_A2_tfrih(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.tfril"]
+    fn hexagon_A2_tfril(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.tfrp"]
+    fn hexagon_A2_tfrp(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.tfrpi"]
+    fn hexagon_A2_tfrpi(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.A2.tfrsi"]
+    fn hexagon_A2_tfrsi(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.vabsh"]
+    fn hexagon_A2_vabsh(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vabshsat"]
+    fn hexagon_A2_vabshsat(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vabsw"]
+    fn hexagon_A2_vabsw(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vabswsat"]
+    fn hexagon_A2_vabswsat(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddb.map"]
+    fn hexagon_A2_vaddb_map(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddh"]
+    fn hexagon_A2_vaddh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddhs"]
+    fn hexagon_A2_vaddhs(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddub"]
+    fn hexagon_A2_vaddub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddubs"]
+    fn hexagon_A2_vaddubs(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vadduhs"]
+    fn hexagon_A2_vadduhs(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddw"]
+    fn hexagon_A2_vaddw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vaddws"]
+    fn hexagon_A2_vaddws(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavgh"]
+    fn hexagon_A2_vavgh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavghcr"]
+    fn hexagon_A2_vavghcr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavghr"]
+    fn hexagon_A2_vavghr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavgub"]
+    fn hexagon_A2_vavgub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavgubr"]
+    fn hexagon_A2_vavgubr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavguh"]
+    fn hexagon_A2_vavguh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavguhr"]
+    fn hexagon_A2_vavguhr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavguw"]
+    fn hexagon_A2_vavguw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavguwr"]
+    fn hexagon_A2_vavguwr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavgw"]
+    fn hexagon_A2_vavgw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavgwcr"]
+    fn hexagon_A2_vavgwcr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vavgwr"]
+    fn hexagon_A2_vavgwr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vcmpbeq"]
+    fn hexagon_A2_vcmpbeq(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmpbgtu"]
+    fn hexagon_A2_vcmpbgtu(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmpheq"]
+    fn hexagon_A2_vcmpheq(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmphgt"]
+    fn hexagon_A2_vcmphgt(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmphgtu"]
+    fn hexagon_A2_vcmphgtu(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmpweq"]
+    fn hexagon_A2_vcmpweq(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmpwgt"]
+    fn hexagon_A2_vcmpwgt(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vcmpwgtu"]
+    fn hexagon_A2_vcmpwgtu(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A2.vconj"]
+    fn hexagon_A2_vconj(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vmaxb"]
+    fn hexagon_A2_vmaxb(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vmaxh"]
+    fn hexagon_A2_vmaxh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vmaxub"]
+    fn hexagon_A2_vmaxub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vmaxuh"]
+    fn hexagon_A2_vmaxuh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vmaxuw"]
+    fn hexagon_A2_vmaxuw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vmaxw"]
+    fn hexagon_A2_vmaxw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vminb"]
+    fn hexagon_A2_vminb(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vminh"]
+    fn hexagon_A2_vminh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vminub"]
+    fn hexagon_A2_vminub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vminuh"]
+    fn hexagon_A2_vminuh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vminuw"]
+    fn hexagon_A2_vminuw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vminw"]
+    fn hexagon_A2_vminw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vnavgh"]
+    fn hexagon_A2_vnavgh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vnavghcr"]
+    fn hexagon_A2_vnavghcr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vnavghr"]
+    fn hexagon_A2_vnavghr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vnavgw"]
+    fn hexagon_A2_vnavgw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vnavgwcr"]
+    fn hexagon_A2_vnavgwcr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vnavgwr"]
+    fn hexagon_A2_vnavgwr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vraddub"]
+    fn hexagon_A2_vraddub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vraddub.acc"]
+    fn hexagon_A2_vraddub_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vrsadub"]
+    fn hexagon_A2_vrsadub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vrsadub.acc"]
+    fn hexagon_A2_vrsadub_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubb.map"]
+    fn hexagon_A2_vsubb_map(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubh"]
+    fn hexagon_A2_vsubh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubhs"]
+    fn hexagon_A2_vsubhs(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubub"]
+    fn hexagon_A2_vsubub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsububs"]
+    fn hexagon_A2_vsububs(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubuhs"]
+    fn hexagon_A2_vsubuhs(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubw"]
+    fn hexagon_A2_vsubw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.vsubws"]
+    fn hexagon_A2_vsubws(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.xor"]
+    fn hexagon_A2_xor(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.xorp"]
+    fn hexagon_A2_xorp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A2.zxtb"]
+    fn hexagon_A2_zxtb(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A2.zxth"]
+    fn hexagon_A2_zxth(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.andn"]
+    fn hexagon_A4_andn(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.andnp"]
+    fn hexagon_A4_andnp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A4.bitsplit"]
+    fn hexagon_A4_bitsplit(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.bitspliti"]
+    fn hexagon_A4_bitspliti(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.boundscheck"]
+    fn hexagon_A4_boundscheck(_: i32, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpbeq"]
+    fn hexagon_A4_cmpbeq(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpbeqi"]
+    fn hexagon_A4_cmpbeqi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpbgt"]
+    fn hexagon_A4_cmpbgt(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpbgti"]
+    fn hexagon_A4_cmpbgti(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpbgtu"]
+    fn hexagon_A4_cmpbgtu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpbgtui"]
+    fn hexagon_A4_cmpbgtui(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpheq"]
+    fn hexagon_A4_cmpheq(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmpheqi"]
+    fn hexagon_A4_cmpheqi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmphgt"]
+    fn hexagon_A4_cmphgt(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmphgti"]
+    fn hexagon_A4_cmphgti(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmphgtu"]
+    fn hexagon_A4_cmphgtu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cmphgtui"]
+    fn hexagon_A4_cmphgtui(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.combineir"]
+    fn hexagon_A4_combineir(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.combineri"]
+    fn hexagon_A4_combineri(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.cround.ri"]
+    fn hexagon_A4_cround_ri(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.cround.rr"]
+    fn hexagon_A4_cround_rr(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.modwrapu"]
+    fn hexagon_A4_modwrapu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.orn"]
+    fn hexagon_A4_orn(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.ornp"]
+    fn hexagon_A4_ornp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A4.rcmpeq"]
+    fn hexagon_A4_rcmpeq(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.rcmpeqi"]
+    fn hexagon_A4_rcmpeqi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.rcmpneq"]
+    fn hexagon_A4_rcmpneq(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.rcmpneqi"]
+    fn hexagon_A4_rcmpneqi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.round.ri"]
+    fn hexagon_A4_round_ri(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.round.ri.sat"]
+    fn hexagon_A4_round_ri_sat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.round.rr"]
+    fn hexagon_A4_round_rr(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.round.rr.sat"]
+    fn hexagon_A4_round_rr_sat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.tlbmatch"]
+    fn hexagon_A4_tlbmatch(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpbeq.any"]
+    fn hexagon_A4_vcmpbeq_any(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpbeqi"]
+    fn hexagon_A4_vcmpbeqi(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpbgt"]
+    fn hexagon_A4_vcmpbgt(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpbgti"]
+    fn hexagon_A4_vcmpbgti(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpbgtui"]
+    fn hexagon_A4_vcmpbgtui(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpheqi"]
+    fn hexagon_A4_vcmpheqi(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmphgti"]
+    fn hexagon_A4_vcmphgti(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmphgtui"]
+    fn hexagon_A4_vcmphgtui(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpweqi"]
+    fn hexagon_A4_vcmpweqi(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpwgti"]
+    fn hexagon_A4_vcmpwgti(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vcmpwgtui"]
+    fn hexagon_A4_vcmpwgtui(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A4.vrmaxh"]
+    fn hexagon_A4_vrmaxh(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrmaxuh"]
+    fn hexagon_A4_vrmaxuh(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrmaxuw"]
+    fn hexagon_A4_vrmaxuw(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrmaxw"]
+    fn hexagon_A4_vrmaxw(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrminh"]
+    fn hexagon_A4_vrminh(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrminuh"]
+    fn hexagon_A4_vrminuh(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrminuw"]
+    fn hexagon_A4_vrminuw(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A4.vrminw"]
+    fn hexagon_A4_vrminw(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A5.vaddhubs"]
+    fn hexagon_A5_vaddhubs(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.C2.all8"]
+    fn hexagon_C2_all8(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.and"]
+    fn hexagon_C2_and(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.andn"]
+    fn hexagon_C2_andn(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.any8"]
+    fn hexagon_C2_any8(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.bitsclr"]
+    fn hexagon_C2_bitsclr(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.bitsclri"]
+    fn hexagon_C2_bitsclri(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.bitsset"]
+    fn hexagon_C2_bitsset(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpeq"]
+    fn hexagon_C2_cmpeq(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpeqi"]
+    fn hexagon_C2_cmpeqi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpeqp"]
+    fn hexagon_C2_cmpeqp(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgei"]
+    fn hexagon_C2_cmpgei(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgeui"]
+    fn hexagon_C2_cmpgeui(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgt"]
+    fn hexagon_C2_cmpgt(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgti"]
+    fn hexagon_C2_cmpgti(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgtp"]
+    fn hexagon_C2_cmpgtp(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgtu"]
+    fn hexagon_C2_cmpgtu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgtui"]
+    fn hexagon_C2_cmpgtui(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpgtup"]
+    fn hexagon_C2_cmpgtup(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmplt"]
+    fn hexagon_C2_cmplt(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.cmpltu"]
+    fn hexagon_C2_cmpltu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.mask"]
+    fn hexagon_C2_mask(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.C2.mux"]
+    fn hexagon_C2_mux(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.muxii"]
+    fn hexagon_C2_muxii(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.muxir"]
+    fn hexagon_C2_muxir(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.muxri"]
+    fn hexagon_C2_muxri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.not"]
+    fn hexagon_C2_not(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.or"]
+    fn hexagon_C2_or(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.orn"]
+    fn hexagon_C2_orn(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.pxfer.map"]
+    fn hexagon_C2_pxfer_map(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.tfrpr"]
+    fn hexagon_C2_tfrpr(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.tfrrp"]
+    fn hexagon_C2_tfrrp(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.vitpack"]
+    fn hexagon_C2_vitpack(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C2.vmux"]
+    fn hexagon_C2_vmux(_: i32, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.C2.xor"]
+    fn hexagon_C2_xor(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.and.and"]
+    fn hexagon_C4_and_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.and.andn"]
+    fn hexagon_C4_and_andn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.and.or"]
+    fn hexagon_C4_and_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.and.orn"]
+    fn hexagon_C4_and_orn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.cmplte"]
+    fn hexagon_C4_cmplte(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.cmpltei"]
+    fn hexagon_C4_cmpltei(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.cmplteu"]
+    fn hexagon_C4_cmplteu(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.cmplteui"]
+    fn hexagon_C4_cmplteui(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.cmpneq"]
+    fn hexagon_C4_cmpneq(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.cmpneqi"]
+    fn hexagon_C4_cmpneqi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.fastcorner9"]
+    fn hexagon_C4_fastcorner9(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.fastcorner9.not"]
+    fn hexagon_C4_fastcorner9_not(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.nbitsclr"]
+    fn hexagon_C4_nbitsclr(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.nbitsclri"]
+    fn hexagon_C4_nbitsclri(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.nbitsset"]
+    fn hexagon_C4_nbitsset(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.or.and"]
+    fn hexagon_C4_or_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.or.andn"]
+    fn hexagon_C4_or_andn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.or.or"]
+    fn hexagon_C4_or_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.C4.or.orn"]
+    fn hexagon_C4_or_orn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.d2df"]
+    fn hexagon_F2_conv_d2df(_: i64) -> f64;
+    #[link_name = "llvm.hexagon.F2.conv.d2sf"]
+    fn hexagon_F2_conv_d2sf(_: i64) -> f32;
+    #[link_name = "llvm.hexagon.F2.conv.df2d"]
+    fn hexagon_F2_conv_df2d(_: f64) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.df2d.chop"]
+    fn hexagon_F2_conv_df2d_chop(_: f64) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.df2sf"]
+    fn hexagon_F2_conv_df2sf(_: f64) -> f32;
+    #[link_name = "llvm.hexagon.F2.conv.df2ud"]
+    fn hexagon_F2_conv_df2ud(_: f64) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.df2ud.chop"]
+    fn hexagon_F2_conv_df2ud_chop(_: f64) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.df2uw"]
+    fn hexagon_F2_conv_df2uw(_: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.df2uw.chop"]
+    fn hexagon_F2_conv_df2uw_chop(_: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.df2w"]
+    fn hexagon_F2_conv_df2w(_: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.df2w.chop"]
+    fn hexagon_F2_conv_df2w_chop(_: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.sf2d"]
+    fn hexagon_F2_conv_sf2d(_: f32) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.sf2d.chop"]
+    fn hexagon_F2_conv_sf2d_chop(_: f32) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.sf2df"]
+    fn hexagon_F2_conv_sf2df(_: f32) -> f64;
+    #[link_name = "llvm.hexagon.F2.conv.sf2ud"]
+    fn hexagon_F2_conv_sf2ud(_: f32) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.sf2ud.chop"]
+    fn hexagon_F2_conv_sf2ud_chop(_: f32) -> i64;
+    #[link_name = "llvm.hexagon.F2.conv.sf2uw"]
+    fn hexagon_F2_conv_sf2uw(_: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.sf2uw.chop"]
+    fn hexagon_F2_conv_sf2uw_chop(_: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.sf2w"]
+    fn hexagon_F2_conv_sf2w(_: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.sf2w.chop"]
+    fn hexagon_F2_conv_sf2w_chop(_: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.conv.ud2df"]
+    fn hexagon_F2_conv_ud2df(_: i64) -> f64;
+    #[link_name = "llvm.hexagon.F2.conv.ud2sf"]
+    fn hexagon_F2_conv_ud2sf(_: i64) -> f32;
+    #[link_name = "llvm.hexagon.F2.conv.uw2df"]
+    fn hexagon_F2_conv_uw2df(_: i32) -> f64;
+    #[link_name = "llvm.hexagon.F2.conv.uw2sf"]
+    fn hexagon_F2_conv_uw2sf(_: i32) -> f32;
+    #[link_name = "llvm.hexagon.F2.conv.w2df"]
+    fn hexagon_F2_conv_w2df(_: i32) -> f64;
+    #[link_name = "llvm.hexagon.F2.conv.w2sf"]
+    fn hexagon_F2_conv_w2sf(_: i32) -> f32;
+    #[link_name = "llvm.hexagon.F2.dfclass"]
+    fn hexagon_F2_dfclass(_: f64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.F2.dfcmpeq"]
+    fn hexagon_F2_dfcmpeq(_: f64, _: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.dfcmpge"]
+    fn hexagon_F2_dfcmpge(_: f64, _: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.dfcmpgt"]
+    fn hexagon_F2_dfcmpgt(_: f64, _: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.dfcmpuo"]
+    fn hexagon_F2_dfcmpuo(_: f64, _: f64) -> i32;
+    #[link_name = "llvm.hexagon.F2.dfimm.n"]
+    fn hexagon_F2_dfimm_n(_: i32) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfimm.p"]
+    fn hexagon_F2_dfimm_p(_: i32) -> f64;
+    #[link_name = "llvm.hexagon.F2.sfadd"]
+    fn hexagon_F2_sfadd(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfclass"]
+    fn hexagon_F2_sfclass(_: f32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.F2.sfcmpeq"]
+    fn hexagon_F2_sfcmpeq(_: f32, _: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.sfcmpge"]
+    fn hexagon_F2_sfcmpge(_: f32, _: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.sfcmpgt"]
+    fn hexagon_F2_sfcmpgt(_: f32, _: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.sfcmpuo"]
+    fn hexagon_F2_sfcmpuo(_: f32, _: f32) -> i32;
+    #[link_name = "llvm.hexagon.F2.sffixupd"]
+    fn hexagon_F2_sffixupd(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffixupn"]
+    fn hexagon_F2_sffixupn(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffixupr"]
+    fn hexagon_F2_sffixupr(_: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffma"]
+    fn hexagon_F2_sffma(_: f32, _: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffma.lib"]
+    fn hexagon_F2_sffma_lib(_: f32, _: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffma.sc"]
+    fn hexagon_F2_sffma_sc(_: f32, _: f32, _: f32, _: i32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffms"]
+    fn hexagon_F2_sffms(_: f32, _: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sffms.lib"]
+    fn hexagon_F2_sffms_lib(_: f32, _: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfimm.n"]
+    fn hexagon_F2_sfimm_n(_: i32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfimm.p"]
+    fn hexagon_F2_sfimm_p(_: i32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfmax"]
+    fn hexagon_F2_sfmax(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfmin"]
+    fn hexagon_F2_sfmin(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfmpy"]
+    fn hexagon_F2_sfmpy(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.F2.sfsub"]
+    fn hexagon_F2_sfsub(_: f32, _: f32) -> f32;
+    #[link_name = "llvm.hexagon.M2.acci"]
+    fn hexagon_M2_acci(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.accii"]
+    fn hexagon_M2_accii(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.cmaci.s0"]
+    fn hexagon_M2_cmaci_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmacr.s0"]
+    fn hexagon_M2_cmacr_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmacs.s0"]
+    fn hexagon_M2_cmacs_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmacs.s1"]
+    fn hexagon_M2_cmacs_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmacsc.s0"]
+    fn hexagon_M2_cmacsc_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmacsc.s1"]
+    fn hexagon_M2_cmacsc_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmpyi.s0"]
+    fn hexagon_M2_cmpyi_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmpyr.s0"]
+    fn hexagon_M2_cmpyr_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmpyrs.s0"]
+    fn hexagon_M2_cmpyrs_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.cmpyrs.s1"]
+    fn hexagon_M2_cmpyrs_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.cmpyrsc.s0"]
+    fn hexagon_M2_cmpyrsc_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.cmpyrsc.s1"]
+    fn hexagon_M2_cmpyrsc_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.cmpys.s0"]
+    fn hexagon_M2_cmpys_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmpys.s1"]
+    fn hexagon_M2_cmpys_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmpysc.s0"]
+    fn hexagon_M2_cmpysc_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cmpysc.s1"]
+    fn hexagon_M2_cmpysc_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cnacs.s0"]
+    fn hexagon_M2_cnacs_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cnacs.s1"]
+    fn hexagon_M2_cnacs_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cnacsc.s0"]
+    fn hexagon_M2_cnacsc_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.cnacsc.s1"]
+    fn hexagon_M2_cnacsc_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.dpmpyss.acc.s0"]
+    fn hexagon_M2_dpmpyss_acc_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.dpmpyss.nac.s0"]
+    fn hexagon_M2_dpmpyss_nac_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.dpmpyss.rnd.s0"]
+    fn hexagon_M2_dpmpyss_rnd_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.dpmpyss.s0"]
+    fn hexagon_M2_dpmpyss_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.dpmpyuu.acc.s0"]
+    fn hexagon_M2_dpmpyuu_acc_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.dpmpyuu.nac.s0"]
+    fn hexagon_M2_dpmpyuu_nac_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.dpmpyuu.s0"]
+    fn hexagon_M2_dpmpyuu_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.hmmpyh.rs1"]
+    fn hexagon_M2_hmmpyh_rs1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.hmmpyh.s1"]
+    fn hexagon_M2_hmmpyh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.hmmpyl.rs1"]
+    fn hexagon_M2_hmmpyl_rs1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.hmmpyl.s1"]
+    fn hexagon_M2_hmmpyl_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.maci"]
+    fn hexagon_M2_maci(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.macsin"]
+    fn hexagon_M2_macsin(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.macsip"]
+    fn hexagon_M2_macsip(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mmachs.rs0"]
+    fn hexagon_M2_mmachs_rs0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmachs.rs1"]
+    fn hexagon_M2_mmachs_rs1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmachs.s0"]
+    fn hexagon_M2_mmachs_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmachs.s1"]
+    fn hexagon_M2_mmachs_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacls.rs0"]
+    fn hexagon_M2_mmacls_rs0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacls.rs1"]
+    fn hexagon_M2_mmacls_rs1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacls.s0"]
+    fn hexagon_M2_mmacls_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacls.s1"]
+    fn hexagon_M2_mmacls_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacuhs.rs0"]
+    fn hexagon_M2_mmacuhs_rs0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacuhs.rs1"]
+    fn hexagon_M2_mmacuhs_rs1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacuhs.s0"]
+    fn hexagon_M2_mmacuhs_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmacuhs.s1"]
+    fn hexagon_M2_mmacuhs_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmaculs.rs0"]
+    fn hexagon_M2_mmaculs_rs0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmaculs.rs1"]
+    fn hexagon_M2_mmaculs_rs1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmaculs.s0"]
+    fn hexagon_M2_mmaculs_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmaculs.s1"]
+    fn hexagon_M2_mmaculs_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyh.rs0"]
+    fn hexagon_M2_mmpyh_rs0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyh.rs1"]
+    fn hexagon_M2_mmpyh_rs1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyh.s0"]
+    fn hexagon_M2_mmpyh_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyh.s1"]
+    fn hexagon_M2_mmpyh_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyl.rs0"]
+    fn hexagon_M2_mmpyl_rs0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyl.rs1"]
+    fn hexagon_M2_mmpyl_rs1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyl.s0"]
+    fn hexagon_M2_mmpyl_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyl.s1"]
+    fn hexagon_M2_mmpyl_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyuh.rs0"]
+    fn hexagon_M2_mmpyuh_rs0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyuh.rs1"]
+    fn hexagon_M2_mmpyuh_rs1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyuh.s0"]
+    fn hexagon_M2_mmpyuh_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyuh.s1"]
+    fn hexagon_M2_mmpyuh_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyul.rs0"]
+    fn hexagon_M2_mmpyul_rs0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyul.rs1"]
+    fn hexagon_M2_mmpyul_rs1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyul.s0"]
+    fn hexagon_M2_mmpyul_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mmpyul.s1"]
+    fn hexagon_M2_mmpyul_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s0"]
+    fn hexagon_M2_mpy_acc_hh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s1"]
+    fn hexagon_M2_mpy_acc_hh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s0"]
+    fn hexagon_M2_mpy_acc_hl_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s1"]
+    fn hexagon_M2_mpy_acc_hl_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s0"]
+    fn hexagon_M2_mpy_acc_lh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s1"]
+    fn hexagon_M2_mpy_acc_lh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s0"]
+    fn hexagon_M2_mpy_acc_ll_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s1"]
+    fn hexagon_M2_mpy_acc_ll_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s0"]
+    fn hexagon_M2_mpy_acc_sat_hh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s1"]
+    fn hexagon_M2_mpy_acc_sat_hh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s0"]
+    fn hexagon_M2_mpy_acc_sat_hl_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s1"]
+    fn hexagon_M2_mpy_acc_sat_hl_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s0"]
+    fn hexagon_M2_mpy_acc_sat_lh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s1"]
+    fn hexagon_M2_mpy_acc_sat_lh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s0"]
+    fn hexagon_M2_mpy_acc_sat_ll_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s1"]
+    fn hexagon_M2_mpy_acc_sat_ll_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.hh.s0"]
+    fn hexagon_M2_mpy_hh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.hh.s1"]
+    fn hexagon_M2_mpy_hh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.hl.s0"]
+    fn hexagon_M2_mpy_hl_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.hl.s1"]
+    fn hexagon_M2_mpy_hl_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.lh.s0"]
+    fn hexagon_M2_mpy_lh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.lh.s1"]
+    fn hexagon_M2_mpy_lh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.ll.s0"]
+    fn hexagon_M2_mpy_ll_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.ll.s1"]
+    fn hexagon_M2_mpy_ll_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s0"]
+    fn hexagon_M2_mpy_nac_hh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s1"]
+    fn hexagon_M2_mpy_nac_hh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s0"]
+    fn hexagon_M2_mpy_nac_hl_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s1"]
+    fn hexagon_M2_mpy_nac_hl_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s0"]
+    fn hexagon_M2_mpy_nac_lh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s1"]
+    fn hexagon_M2_mpy_nac_lh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s0"]
+    fn hexagon_M2_mpy_nac_ll_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s1"]
+    fn hexagon_M2_mpy_nac_ll_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s0"]
+    fn hexagon_M2_mpy_nac_sat_hh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s1"]
+    fn hexagon_M2_mpy_nac_sat_hh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s0"]
+    fn hexagon_M2_mpy_nac_sat_hl_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s1"]
+    fn hexagon_M2_mpy_nac_sat_hl_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s0"]
+    fn hexagon_M2_mpy_nac_sat_lh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s1"]
+    fn hexagon_M2_mpy_nac_sat_lh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s0"]
+    fn hexagon_M2_mpy_nac_sat_ll_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s1"]
+    fn hexagon_M2_mpy_nac_sat_ll_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s0"]
+    fn hexagon_M2_mpy_rnd_hh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s1"]
+    fn hexagon_M2_mpy_rnd_hh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s0"]
+    fn hexagon_M2_mpy_rnd_hl_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s1"]
+    fn hexagon_M2_mpy_rnd_hl_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s0"]
+    fn hexagon_M2_mpy_rnd_lh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s1"]
+    fn hexagon_M2_mpy_rnd_lh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s0"]
+    fn hexagon_M2_mpy_rnd_ll_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s1"]
+    fn hexagon_M2_mpy_rnd_ll_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s0"]
+    fn hexagon_M2_mpy_sat_hh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s1"]
+    fn hexagon_M2_mpy_sat_hh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s0"]
+    fn hexagon_M2_mpy_sat_hl_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s1"]
+    fn hexagon_M2_mpy_sat_hl_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s0"]
+    fn hexagon_M2_mpy_sat_lh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s1"]
+    fn hexagon_M2_mpy_sat_lh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s0"]
+    fn hexagon_M2_mpy_sat_ll_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s1"]
+    fn hexagon_M2_mpy_sat_ll_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s0"]
+    fn hexagon_M2_mpy_sat_rnd_hh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s1"]
+    fn hexagon_M2_mpy_sat_rnd_hh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s0"]
+    fn hexagon_M2_mpy_sat_rnd_hl_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s1"]
+    fn hexagon_M2_mpy_sat_rnd_hl_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s0"]
+    fn hexagon_M2_mpy_sat_rnd_lh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s1"]
+    fn hexagon_M2_mpy_sat_rnd_lh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s0"]
+    fn hexagon_M2_mpy_sat_rnd_ll_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s1"]
+    fn hexagon_M2_mpy_sat_rnd_ll_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.up"]
+    fn hexagon_M2_mpy_up(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.up.s1"]
+    fn hexagon_M2_mpy_up_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpy.up.s1.sat"]
+    fn hexagon_M2_mpy_up_s1_sat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s0"]
+    fn hexagon_M2_mpyd_acc_hh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s1"]
+    fn hexagon_M2_mpyd_acc_hh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s0"]
+    fn hexagon_M2_mpyd_acc_hl_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s1"]
+    fn hexagon_M2_mpyd_acc_hl_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s0"]
+    fn hexagon_M2_mpyd_acc_lh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s1"]
+    fn hexagon_M2_mpyd_acc_lh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s0"]
+    fn hexagon_M2_mpyd_acc_ll_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s1"]
+    fn hexagon_M2_mpyd_acc_ll_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.hh.s0"]
+    fn hexagon_M2_mpyd_hh_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.hh.s1"]
+    fn hexagon_M2_mpyd_hh_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.hl.s0"]
+    fn hexagon_M2_mpyd_hl_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.hl.s1"]
+    fn hexagon_M2_mpyd_hl_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.lh.s0"]
+    fn hexagon_M2_mpyd_lh_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.lh.s1"]
+    fn hexagon_M2_mpyd_lh_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.ll.s0"]
+    fn hexagon_M2_mpyd_ll_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.ll.s1"]
+    fn hexagon_M2_mpyd_ll_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s0"]
+    fn hexagon_M2_mpyd_nac_hh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s1"]
+    fn hexagon_M2_mpyd_nac_hh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s0"]
+    fn hexagon_M2_mpyd_nac_hl_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s1"]
+    fn hexagon_M2_mpyd_nac_hl_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s0"]
+    fn hexagon_M2_mpyd_nac_lh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s1"]
+    fn hexagon_M2_mpyd_nac_lh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s0"]
+    fn hexagon_M2_mpyd_nac_ll_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s1"]
+    fn hexagon_M2_mpyd_nac_ll_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s0"]
+    fn hexagon_M2_mpyd_rnd_hh_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s1"]
+    fn hexagon_M2_mpyd_rnd_hh_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s0"]
+    fn hexagon_M2_mpyd_rnd_hl_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s1"]
+    fn hexagon_M2_mpyd_rnd_hl_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s0"]
+    fn hexagon_M2_mpyd_rnd_lh_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s1"]
+    fn hexagon_M2_mpyd_rnd_lh_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s0"]
+    fn hexagon_M2_mpyd_rnd_ll_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s1"]
+    fn hexagon_M2_mpyd_rnd_ll_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyi"]
+    fn hexagon_M2_mpyi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpysmi"]
+    fn hexagon_M2_mpysmi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpysu.up"]
+    fn hexagon_M2_mpysu_up(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s0"]
+    fn hexagon_M2_mpyu_acc_hh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s1"]
+    fn hexagon_M2_mpyu_acc_hh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s0"]
+    fn hexagon_M2_mpyu_acc_hl_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s1"]
+    fn hexagon_M2_mpyu_acc_hl_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s0"]
+    fn hexagon_M2_mpyu_acc_lh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s1"]
+    fn hexagon_M2_mpyu_acc_lh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s0"]
+    fn hexagon_M2_mpyu_acc_ll_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s1"]
+    fn hexagon_M2_mpyu_acc_ll_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.hh.s0"]
+    fn hexagon_M2_mpyu_hh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.hh.s1"]
+    fn hexagon_M2_mpyu_hh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.hl.s0"]
+    fn hexagon_M2_mpyu_hl_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.hl.s1"]
+    fn hexagon_M2_mpyu_hl_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.lh.s0"]
+    fn hexagon_M2_mpyu_lh_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.lh.s1"]
+    fn hexagon_M2_mpyu_lh_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.ll.s0"]
+    fn hexagon_M2_mpyu_ll_s0(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.ll.s1"]
+    fn hexagon_M2_mpyu_ll_s1(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s0"]
+    fn hexagon_M2_mpyu_nac_hh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s1"]
+    fn hexagon_M2_mpyu_nac_hh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s0"]
+    fn hexagon_M2_mpyu_nac_hl_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s1"]
+    fn hexagon_M2_mpyu_nac_hl_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s0"]
+    fn hexagon_M2_mpyu_nac_lh_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s1"]
+    fn hexagon_M2_mpyu_nac_lh_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s0"]
+    fn hexagon_M2_mpyu_nac_ll_s0(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s1"]
+    fn hexagon_M2_mpyu_nac_ll_s1(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyu.up"]
+    fn hexagon_M2_mpyu_up(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s0"]
+    fn hexagon_M2_mpyud_acc_hh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s1"]
+    fn hexagon_M2_mpyud_acc_hh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s0"]
+    fn hexagon_M2_mpyud_acc_hl_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s1"]
+    fn hexagon_M2_mpyud_acc_hl_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s0"]
+    fn hexagon_M2_mpyud_acc_lh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s1"]
+    fn hexagon_M2_mpyud_acc_lh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s0"]
+    fn hexagon_M2_mpyud_acc_ll_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s1"]
+    fn hexagon_M2_mpyud_acc_ll_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.hh.s0"]
+    fn hexagon_M2_mpyud_hh_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.hh.s1"]
+    fn hexagon_M2_mpyud_hh_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.hl.s0"]
+    fn hexagon_M2_mpyud_hl_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.hl.s1"]
+    fn hexagon_M2_mpyud_hl_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.lh.s0"]
+    fn hexagon_M2_mpyud_lh_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.lh.s1"]
+    fn hexagon_M2_mpyud_lh_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.ll.s0"]
+    fn hexagon_M2_mpyud_ll_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.ll.s1"]
+    fn hexagon_M2_mpyud_ll_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s0"]
+    fn hexagon_M2_mpyud_nac_hh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s1"]
+    fn hexagon_M2_mpyud_nac_hh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s0"]
+    fn hexagon_M2_mpyud_nac_hl_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s1"]
+    fn hexagon_M2_mpyud_nac_hl_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s0"]
+    fn hexagon_M2_mpyud_nac_lh_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s1"]
+    fn hexagon_M2_mpyud_nac_lh_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s0"]
+    fn hexagon_M2_mpyud_nac_ll_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s1"]
+    fn hexagon_M2_mpyud_nac_ll_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.mpyui"]
+    fn hexagon_M2_mpyui(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.nacci"]
+    fn hexagon_M2_nacci(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.naccii"]
+    fn hexagon_M2_naccii(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.subacc"]
+    fn hexagon_M2_subacc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.vabsdiffh"]
+    fn hexagon_M2_vabsdiffh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vabsdiffw"]
+    fn hexagon_M2_vabsdiffw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.i"]
+    fn hexagon_M2_vcmac_s0_sat_i(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.r"]
+    fn hexagon_M2_vcmac_s0_sat_r(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.i"]
+    fn hexagon_M2_vcmpy_s0_sat_i(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.r"]
+    fn hexagon_M2_vcmpy_s0_sat_r(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.i"]
+    fn hexagon_M2_vcmpy_s1_sat_i(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.r"]
+    fn hexagon_M2_vcmpy_s1_sat_r(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vdmacs.s0"]
+    fn hexagon_M2_vdmacs_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vdmacs.s1"]
+    fn hexagon_M2_vdmacs_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vdmpyrs.s0"]
+    fn hexagon_M2_vdmpyrs_s0(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M2.vdmpyrs.s1"]
+    fn hexagon_M2_vdmpyrs_s1(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M2.vdmpys.s0"]
+    fn hexagon_M2_vdmpys_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vdmpys.s1"]
+    fn hexagon_M2_vdmpys_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2"]
+    fn hexagon_M2_vmac2(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2es"]
+    fn hexagon_M2_vmac2es(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2es.s0"]
+    fn hexagon_M2_vmac2es_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2es.s1"]
+    fn hexagon_M2_vmac2es_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2s.s0"]
+    fn hexagon_M2_vmac2s_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2s.s1"]
+    fn hexagon_M2_vmac2s_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2su.s0"]
+    fn hexagon_M2_vmac2su_s0(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmac2su.s1"]
+    fn hexagon_M2_vmac2su_s1(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmpy2es.s0"]
+    fn hexagon_M2_vmpy2es_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmpy2es.s1"]
+    fn hexagon_M2_vmpy2es_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmpy2s.s0"]
+    fn hexagon_M2_vmpy2s_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmpy2s.s0pack"]
+    fn hexagon_M2_vmpy2s_s0pack(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.vmpy2s.s1"]
+    fn hexagon_M2_vmpy2s_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmpy2s.s1pack"]
+    fn hexagon_M2_vmpy2s_s1pack(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.vmpy2su.s0"]
+    fn hexagon_M2_vmpy2su_s0(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vmpy2su.s1"]
+    fn hexagon_M2_vmpy2su_s1(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vraddh"]
+    fn hexagon_M2_vraddh(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M2.vradduh"]
+    fn hexagon_M2_vradduh(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M2.vrcmaci.s0"]
+    fn hexagon_M2_vrcmaci_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmaci.s0c"]
+    fn hexagon_M2_vrcmaci_s0c(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmacr.s0"]
+    fn hexagon_M2_vrcmacr_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmacr.s0c"]
+    fn hexagon_M2_vrcmacr_s0c(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpyi.s0"]
+    fn hexagon_M2_vrcmpyi_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpyi.s0c"]
+    fn hexagon_M2_vrcmpyi_s0c(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpyr.s0"]
+    fn hexagon_M2_vrcmpyr_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpyr.s0c"]
+    fn hexagon_M2_vrcmpyr_s0c(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpys.acc.s1"]
+    fn hexagon_M2_vrcmpys_acc_s1(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpys.s1"]
+    fn hexagon_M2_vrcmpys_s1(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrcmpys.s1rp"]
+    fn hexagon_M2_vrcmpys_s1rp(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M2.vrmac.s0"]
+    fn hexagon_M2_vrmac_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.vrmpy.s0"]
+    fn hexagon_M2_vrmpy_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M2.xor.xacc"]
+    fn hexagon_M2_xor_xacc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.and.and"]
+    fn hexagon_M4_and_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.and.andn"]
+    fn hexagon_M4_and_andn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.and.or"]
+    fn hexagon_M4_and_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.and.xor"]
+    fn hexagon_M4_and_xor(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.cmpyi.wh"]
+    fn hexagon_M4_cmpyi_wh(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.cmpyi.whc"]
+    fn hexagon_M4_cmpyi_whc(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.cmpyr.wh"]
+    fn hexagon_M4_cmpyr_wh(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.cmpyr.whc"]
+    fn hexagon_M4_cmpyr_whc(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.mac.up.s1.sat"]
+    fn hexagon_M4_mac_up_s1_sat(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.mpyri.addi"]
+    fn hexagon_M4_mpyri_addi(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.mpyri.addr"]
+    fn hexagon_M4_mpyri_addr(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.mpyri.addr.u2"]
+    fn hexagon_M4_mpyri_addr_u2(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.mpyrr.addi"]
+    fn hexagon_M4_mpyrr_addi(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.mpyrr.addr"]
+    fn hexagon_M4_mpyrr_addr(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.nac.up.s1.sat"]
+    fn hexagon_M4_nac_up_s1_sat(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.or.and"]
+    fn hexagon_M4_or_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.or.andn"]
+    fn hexagon_M4_or_andn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.or.or"]
+    fn hexagon_M4_or_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.or.xor"]
+    fn hexagon_M4_or_xor(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.pmpyw"]
+    fn hexagon_M4_pmpyw(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M4.pmpyw.acc"]
+    fn hexagon_M4_pmpyw_acc(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M4.vpmpyh"]
+    fn hexagon_M4_vpmpyh(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M4.vpmpyh.acc"]
+    fn hexagon_M4_vpmpyh_acc(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s0"]
+    fn hexagon_M4_vrmpyeh_acc_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s1"]
+    fn hexagon_M4_vrmpyeh_acc_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyeh.s0"]
+    fn hexagon_M4_vrmpyeh_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyeh.s1"]
+    fn hexagon_M4_vrmpyeh_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s0"]
+    fn hexagon_M4_vrmpyoh_acc_s0(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s1"]
+    fn hexagon_M4_vrmpyoh_acc_s1(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyoh.s0"]
+    fn hexagon_M4_vrmpyoh_s0(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.vrmpyoh.s1"]
+    fn hexagon_M4_vrmpyoh_s1(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M4.xor.and"]
+    fn hexagon_M4_xor_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.xor.andn"]
+    fn hexagon_M4_xor_andn(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.xor.or"]
+    fn hexagon_M4_xor_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M4.xor.xacc"]
+    fn hexagon_M4_xor_xacc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M5.vdmacbsu"]
+    fn hexagon_M5_vdmacbsu(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M5.vdmpybsu"]
+    fn hexagon_M5_vdmpybsu(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M5.vmacbsu"]
+    fn hexagon_M5_vmacbsu(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M5.vmacbuu"]
+    fn hexagon_M5_vmacbuu(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M5.vmpybsu"]
+    fn hexagon_M5_vmpybsu(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M5.vmpybuu"]
+    fn hexagon_M5_vmpybuu(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.M5.vrmacbsu"]
+    fn hexagon_M5_vrmacbsu(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M5.vrmacbuu"]
+    fn hexagon_M5_vrmacbuu(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M5.vrmpybsu"]
+    fn hexagon_M5_vrmpybsu(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M5.vrmpybuu"]
+    fn hexagon_M5_vrmpybuu(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.addasl.rrri"]
+    fn hexagon_S2_addasl_rrri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.p"]
+    fn hexagon_S2_asl_i_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.p.acc"]
+    fn hexagon_S2_asl_i_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.p.and"]
+    fn hexagon_S2_asl_i_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.p.nac"]
+    fn hexagon_S2_asl_i_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.p.or"]
+    fn hexagon_S2_asl_i_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.p.xacc"]
+    fn hexagon_S2_asl_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.r"]
+    fn hexagon_S2_asl_i_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.r.acc"]
+    fn hexagon_S2_asl_i_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.r.and"]
+    fn hexagon_S2_asl_i_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.r.nac"]
+    fn hexagon_S2_asl_i_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.r.or"]
+    fn hexagon_S2_asl_i_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.r.sat"]
+    fn hexagon_S2_asl_i_r_sat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.r.xacc"]
+    fn hexagon_S2_asl_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.i.vh"]
+    fn hexagon_S2_asl_i_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.i.vw"]
+    fn hexagon_S2_asl_i_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.p"]
+    fn hexagon_S2_asl_r_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.p.acc"]
+    fn hexagon_S2_asl_r_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.p.and"]
+    fn hexagon_S2_asl_r_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.p.nac"]
+    fn hexagon_S2_asl_r_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.p.or"]
+    fn hexagon_S2_asl_r_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.p.xor"]
+    fn hexagon_S2_asl_r_p_xor(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.r"]
+    fn hexagon_S2_asl_r_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.r.r.acc"]
+    fn hexagon_S2_asl_r_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.r.r.and"]
+    fn hexagon_S2_asl_r_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.r.r.nac"]
+    fn hexagon_S2_asl_r_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.r.r.or"]
+    fn hexagon_S2_asl_r_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.r.r.sat"]
+    fn hexagon_S2_asl_r_r_sat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asl.r.vh"]
+    fn hexagon_S2_asl_r_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asl.r.vw"]
+    fn hexagon_S2_asl_r_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p"]
+    fn hexagon_S2_asr_i_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p.acc"]
+    fn hexagon_S2_asr_i_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p.and"]
+    fn hexagon_S2_asr_i_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p.nac"]
+    fn hexagon_S2_asr_i_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p.or"]
+    fn hexagon_S2_asr_i_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p.rnd"]
+    fn hexagon_S2_asr_i_p_rnd(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax"]
+    fn hexagon_S2_asr_i_p_rnd_goodsyntax(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.r"]
+    fn hexagon_S2_asr_i_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.r.acc"]
+    fn hexagon_S2_asr_i_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.r.and"]
+    fn hexagon_S2_asr_i_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.r.nac"]
+    fn hexagon_S2_asr_i_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.r.or"]
+    fn hexagon_S2_asr_i_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.r.rnd"]
+    fn hexagon_S2_asr_i_r_rnd(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax"]
+    fn hexagon_S2_asr_i_r_rnd_goodsyntax(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.svw.trun"]
+    fn hexagon_S2_asr_i_svw_trun(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.i.vh"]
+    fn hexagon_S2_asr_i_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.i.vw"]
+    fn hexagon_S2_asr_i_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.p"]
+    fn hexagon_S2_asr_r_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.p.acc"]
+    fn hexagon_S2_asr_r_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.p.and"]
+    fn hexagon_S2_asr_r_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.p.nac"]
+    fn hexagon_S2_asr_r_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.p.or"]
+    fn hexagon_S2_asr_r_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.p.xor"]
+    fn hexagon_S2_asr_r_p_xor(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.r"]
+    fn hexagon_S2_asr_r_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.r.acc"]
+    fn hexagon_S2_asr_r_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.r.and"]
+    fn hexagon_S2_asr_r_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.r.nac"]
+    fn hexagon_S2_asr_r_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.r.or"]
+    fn hexagon_S2_asr_r_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.r.sat"]
+    fn hexagon_S2_asr_r_r_sat(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.svw.trun"]
+    fn hexagon_S2_asr_r_svw_trun(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.asr.r.vh"]
+    fn hexagon_S2_asr_r_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.asr.r.vw"]
+    fn hexagon_S2_asr_r_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.brev"]
+    fn hexagon_S2_brev(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.brevp"]
+    fn hexagon_S2_brevp(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.cl0"]
+    fn hexagon_S2_cl0(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.cl0p"]
+    fn hexagon_S2_cl0p(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.cl1"]
+    fn hexagon_S2_cl1(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.cl1p"]
+    fn hexagon_S2_cl1p(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.clb"]
+    fn hexagon_S2_clb(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.clbnorm"]
+    fn hexagon_S2_clbnorm(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.clbp"]
+    fn hexagon_S2_clbp(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.clrbit.i"]
+    fn hexagon_S2_clrbit_i(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.clrbit.r"]
+    fn hexagon_S2_clrbit_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.ct0"]
+    fn hexagon_S2_ct0(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.ct0p"]
+    fn hexagon_S2_ct0p(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.ct1"]
+    fn hexagon_S2_ct1(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.ct1p"]
+    fn hexagon_S2_ct1p(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.deinterleave"]
+    fn hexagon_S2_deinterleave(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.extractu"]
+    fn hexagon_S2_extractu(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.extractu.rp"]
+    fn hexagon_S2_extractu_rp(_: i32, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.extractup"]
+    fn hexagon_S2_extractup(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.extractup.rp"]
+    fn hexagon_S2_extractup_rp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.insert"]
+    fn hexagon_S2_insert(_: i32, _: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.insert.rp"]
+    fn hexagon_S2_insert_rp(_: i32, _: i32, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.insertp"]
+    fn hexagon_S2_insertp(_: i64, _: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.insertp.rp"]
+    fn hexagon_S2_insertp_rp(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.interleave"]
+    fn hexagon_S2_interleave(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.lfsp"]
+    fn hexagon_S2_lfsp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.p"]
+    fn hexagon_S2_lsl_r_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.p.acc"]
+    fn hexagon_S2_lsl_r_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.p.and"]
+    fn hexagon_S2_lsl_r_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.p.nac"]
+    fn hexagon_S2_lsl_r_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.p.or"]
+    fn hexagon_S2_lsl_r_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.p.xor"]
+    fn hexagon_S2_lsl_r_p_xor(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.r"]
+    fn hexagon_S2_lsl_r_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsl.r.r.acc"]
+    fn hexagon_S2_lsl_r_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsl.r.r.and"]
+    fn hexagon_S2_lsl_r_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsl.r.r.nac"]
+    fn hexagon_S2_lsl_r_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsl.r.r.or"]
+    fn hexagon_S2_lsl_r_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsl.r.vh"]
+    fn hexagon_S2_lsl_r_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsl.r.vw"]
+    fn hexagon_S2_lsl_r_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.p"]
+    fn hexagon_S2_lsr_i_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.p.acc"]
+    fn hexagon_S2_lsr_i_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.p.and"]
+    fn hexagon_S2_lsr_i_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.p.nac"]
+    fn hexagon_S2_lsr_i_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.p.or"]
+    fn hexagon_S2_lsr_i_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.p.xacc"]
+    fn hexagon_S2_lsr_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.r"]
+    fn hexagon_S2_lsr_i_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.i.r.acc"]
+    fn hexagon_S2_lsr_i_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.i.r.and"]
+    fn hexagon_S2_lsr_i_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.i.r.nac"]
+    fn hexagon_S2_lsr_i_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.i.r.or"]
+    fn hexagon_S2_lsr_i_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.i.r.xacc"]
+    fn hexagon_S2_lsr_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.i.vh"]
+    fn hexagon_S2_lsr_i_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.i.vw"]
+    fn hexagon_S2_lsr_i_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.p"]
+    fn hexagon_S2_lsr_r_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.p.acc"]
+    fn hexagon_S2_lsr_r_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.p.and"]
+    fn hexagon_S2_lsr_r_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.p.nac"]
+    fn hexagon_S2_lsr_r_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.p.or"]
+    fn hexagon_S2_lsr_r_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.p.xor"]
+    fn hexagon_S2_lsr_r_p_xor(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.r"]
+    fn hexagon_S2_lsr_r_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.r.r.acc"]
+    fn hexagon_S2_lsr_r_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.r.r.and"]
+    fn hexagon_S2_lsr_r_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.r.r.nac"]
+    fn hexagon_S2_lsr_r_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.r.r.or"]
+    fn hexagon_S2_lsr_r_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.lsr.r.vh"]
+    fn hexagon_S2_lsr_r_vh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.lsr.r.vw"]
+    fn hexagon_S2_lsr_r_vw(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.packhl"]
+    fn hexagon_S2_packhl(_: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.parityp"]
+    fn hexagon_S2_parityp(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.setbit.i"]
+    fn hexagon_S2_setbit_i(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.setbit.r"]
+    fn hexagon_S2_setbit_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.shuffeb"]
+    fn hexagon_S2_shuffeb(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.shuffeh"]
+    fn hexagon_S2_shuffeh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.shuffob"]
+    fn hexagon_S2_shuffob(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.shuffoh"]
+    fn hexagon_S2_shuffoh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.svsathb"]
+    fn hexagon_S2_svsathb(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.svsathub"]
+    fn hexagon_S2_svsathub(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.tableidxb.goodsyntax"]
+    fn hexagon_S2_tableidxb_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.tableidxd.goodsyntax"]
+    fn hexagon_S2_tableidxd_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.tableidxh.goodsyntax"]
+    fn hexagon_S2_tableidxh_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.tableidxw.goodsyntax"]
+    fn hexagon_S2_tableidxw_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.togglebit.i"]
+    fn hexagon_S2_togglebit_i(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.togglebit.r"]
+    fn hexagon_S2_togglebit_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.tstbit.i"]
+    fn hexagon_S2_tstbit_i(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.tstbit.r"]
+    fn hexagon_S2_tstbit_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.valignib"]
+    fn hexagon_S2_valignib(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.valignrb"]
+    fn hexagon_S2_valignrb(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vcnegh"]
+    fn hexagon_S2_vcnegh(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vcrotate"]
+    fn hexagon_S2_vcrotate(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vrcnegh"]
+    fn hexagon_S2_vrcnegh(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vrndpackwh"]
+    fn hexagon_S2_vrndpackwh(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vrndpackwhs"]
+    fn hexagon_S2_vrndpackwhs(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vsathb"]
+    fn hexagon_S2_vsathb(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vsathb.nopack"]
+    fn hexagon_S2_vsathb_nopack(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsathub"]
+    fn hexagon_S2_vsathub(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vsathub.nopack"]
+    fn hexagon_S2_vsathub_nopack(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsatwh"]
+    fn hexagon_S2_vsatwh(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vsatwh.nopack"]
+    fn hexagon_S2_vsatwh_nopack(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsatwuh"]
+    fn hexagon_S2_vsatwuh(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vsatwuh.nopack"]
+    fn hexagon_S2_vsatwuh_nopack(_: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsplatrb"]
+    fn hexagon_S2_vsplatrb(_: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.vsplatrh"]
+    fn hexagon_S2_vsplatrh(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vspliceib"]
+    fn hexagon_S2_vspliceib(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsplicerb"]
+    fn hexagon_S2_vsplicerb(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsxtbh"]
+    fn hexagon_S2_vsxtbh(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vsxthw"]
+    fn hexagon_S2_vsxthw(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vtrunehb"]
+    fn hexagon_S2_vtrunehb(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vtrunewh"]
+    fn hexagon_S2_vtrunewh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.vtrunohb"]
+    fn hexagon_S2_vtrunohb(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S2.vtrunowh"]
+    fn hexagon_S2_vtrunowh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S2.vzxtbh"]
+    fn hexagon_S2_vzxtbh(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.S2.vzxthw"]
+    fn hexagon_S2_vzxthw(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.S4.addaddi"]
+    fn hexagon_S4_addaddi(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.addi.asl.ri"]
+    fn hexagon_S4_addi_asl_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.addi.lsr.ri"]
+    fn hexagon_S4_addi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.andi.asl.ri"]
+    fn hexagon_S4_andi_asl_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.andi.lsr.ri"]
+    fn hexagon_S4_andi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.clbaddi"]
+    fn hexagon_S4_clbaddi(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.clbpaddi"]
+    fn hexagon_S4_clbpaddi(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.clbpnorm"]
+    fn hexagon_S4_clbpnorm(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S4.extract"]
+    fn hexagon_S4_extract(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.extract.rp"]
+    fn hexagon_S4_extract_rp(_: i32, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.S4.extractp"]
+    fn hexagon_S4_extractp(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S4.extractp.rp"]
+    fn hexagon_S4_extractp_rp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S4.lsli"]
+    fn hexagon_S4_lsli(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.ntstbit.i"]
+    fn hexagon_S4_ntstbit_i(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.ntstbit.r"]
+    fn hexagon_S4_ntstbit_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.or.andi"]
+    fn hexagon_S4_or_andi(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.or.andix"]
+    fn hexagon_S4_or_andix(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.or.ori"]
+    fn hexagon_S4_or_ori(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.ori.asl.ri"]
+    fn hexagon_S4_ori_asl_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.ori.lsr.ri"]
+    fn hexagon_S4_ori_lsr_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.parity"]
+    fn hexagon_S4_parity(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.subaddi"]
+    fn hexagon_S4_subaddi(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.subi.asl.ri"]
+    fn hexagon_S4_subi_asl_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.subi.lsr.ri"]
+    fn hexagon_S4_subi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S4.vrcrotate"]
+    fn hexagon_S4_vrcrotate(_: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S4.vrcrotate.acc"]
+    fn hexagon_S4_vrcrotate_acc(_: i64, _: i64, _: i32, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S4.vxaddsubh"]
+    fn hexagon_S4_vxaddsubh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S4.vxaddsubhr"]
+    fn hexagon_S4_vxaddsubhr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S4.vxaddsubw"]
+    fn hexagon_S4_vxaddsubw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S4.vxsubaddh"]
+    fn hexagon_S4_vxsubaddh(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S4.vxsubaddhr"]
+    fn hexagon_S4_vxsubaddhr(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S4.vxsubaddw"]
+    fn hexagon_S4_vxsubaddw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax"]
+    fn hexagon_S5_asrhub_rnd_sat_goodsyntax(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S5.asrhub.sat"]
+    fn hexagon_S5_asrhub_sat(_: i64, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S5.popcountp"]
+    fn hexagon_S5_popcountp(_: i64) -> i32;
+    #[link_name = "llvm.hexagon.S5.vasrhrnd.goodsyntax"]
+    fn hexagon_S5_vasrhrnd_goodsyntax(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.Y2.dccleana"]
+    fn hexagon_Y2_dccleana(_: i32);
+    #[link_name = "llvm.hexagon.Y2.dccleaninva"]
+    fn hexagon_Y2_dccleaninva(_: i32);
+    #[link_name = "llvm.hexagon.Y2.dcfetch"]
+    fn hexagon_Y2_dcfetch(_: i32);
+    #[link_name = "llvm.hexagon.Y2.dcinva"]
+    fn hexagon_Y2_dcinva(_: i32);
+    #[link_name = "llvm.hexagon.Y2.dczeroa"]
+    fn hexagon_Y2_dczeroa(_: i32);
+    #[link_name = "llvm.hexagon.Y4.l2fetch"]
+    fn hexagon_Y4_l2fetch(_: i32, _: i32);
+    #[link_name = "llvm.hexagon.Y5.l2fetch"]
+    fn hexagon_Y5_l2fetch(_: i32, _: i64);
+    #[link_name = "llvm.hexagon.S6.rol.i.p"]
+    fn hexagon_S6_rol_i_p(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.rol.i.p.acc"]
+    fn hexagon_S6_rol_i_p_acc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.rol.i.p.and"]
+    fn hexagon_S6_rol_i_p_and(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.rol.i.p.nac"]
+    fn hexagon_S6_rol_i_p_nac(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.rol.i.p.or"]
+    fn hexagon_S6_rol_i_p_or(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.rol.i.p.xacc"]
+    fn hexagon_S6_rol_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.rol.i.r"]
+    fn hexagon_S6_rol_i_r(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S6.rol.i.r.acc"]
+    fn hexagon_S6_rol_i_r_acc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S6.rol.i.r.and"]
+    fn hexagon_S6_rol_i_r_and(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S6.rol.i.r.nac"]
+    fn hexagon_S6_rol_i_r_nac(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S6.rol.i.r.or"]
+    fn hexagon_S6_rol_i_r_or(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S6.rol.i.r.xacc"]
+    fn hexagon_S6_rol_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.M6.vabsdiffb"]
+    fn hexagon_M6_vabsdiffb(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M6.vabsdiffub"]
+    fn hexagon_M6_vabsdiffub(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S6.vsplatrbp"]
+    fn hexagon_S6_vsplatrbp(_: i32) -> i64;
+    #[link_name = "llvm.hexagon.S6.vtrunehb.ppp"]
+    fn hexagon_S6_vtrunehb_ppp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.S6.vtrunohb.ppp"]
+    fn hexagon_S6_vtrunohb_ppp(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.A6.vcmpbeq.notany"]
+    fn hexagon_A6_vcmpbeq_notany(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.F2.dfadd"]
+    fn hexagon_F2_dfadd(_: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfsub"]
+    fn hexagon_F2_dfsub(_: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.M2.mnaci"]
+    fn hexagon_M2_mnaci(_: i32, _: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.S2.mask"]
+    fn hexagon_S2_mask(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A7.clip"]
+    fn hexagon_A7_clip(_: i32, _: i32) -> i32;
+    #[link_name = "llvm.hexagon.A7.croundd.ri"]
+    fn hexagon_A7_croundd_ri(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A7.croundd.rr"]
+    fn hexagon_A7_croundd_rr(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.A7.vclip"]
+    fn hexagon_A7_vclip(_: i64, _: i32) -> i64;
+    #[link_name = "llvm.hexagon.F2.dfmax"]
+    fn hexagon_F2_dfmax(_: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfmin"]
+    fn hexagon_F2_dfmin(_: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfmpyfix"]
+    fn hexagon_F2_dfmpyfix(_: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfmpyhh"]
+    fn hexagon_F2_dfmpyhh(_: f64, _: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfmpylh"]
+    fn hexagon_F2_dfmpylh(_: f64, _: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.F2.dfmpyll"]
+    fn hexagon_F2_dfmpyll(_: f64, _: f64) -> f64;
+    #[link_name = "llvm.hexagon.M7.dcmpyiw"]
+    fn hexagon_M7_dcmpyiw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyiw.acc"]
+    fn hexagon_M7_dcmpyiw_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyiwc"]
+    fn hexagon_M7_dcmpyiwc(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyiwc.acc"]
+    fn hexagon_M7_dcmpyiwc_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyrw"]
+    fn hexagon_M7_dcmpyrw(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyrw.acc"]
+    fn hexagon_M7_dcmpyrw_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyrwc"]
+    fn hexagon_M7_dcmpyrwc(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.dcmpyrwc.acc"]
+    fn hexagon_M7_dcmpyrwc_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.vdmpy"]
+    fn hexagon_M7_vdmpy(_: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.vdmpy.acc"]
+    fn hexagon_M7_vdmpy_acc(_: i64, _: i64, _: i64) -> i64;
+    #[link_name = "llvm.hexagon.M7.wcmpyiw"]
+    fn hexagon_M7_wcmpyiw(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyiw.rnd"]
+    fn hexagon_M7_wcmpyiw_rnd(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyiwc"]
+    fn hexagon_M7_wcmpyiwc(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyiwc.rnd"]
+    fn hexagon_M7_wcmpyiwc_rnd(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyrw"]
+    fn hexagon_M7_wcmpyrw(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyrw.rnd"]
+    fn hexagon_M7_wcmpyrw_rnd(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyrwc"]
+    fn hexagon_M7_wcmpyrwc(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.M7.wcmpyrwc.rnd"]
+    fn hexagon_M7_wcmpyrwc_rnd(_: i64, _: i64) -> i32;
+    #[link_name = "llvm.hexagon.Y6.dmlink"]
+    fn hexagon_Y6_dmlink(_: i32, _: i32);
+    #[link_name = "llvm.hexagon.Y6.dmpause"]
+    fn hexagon_Y6_dmpause() -> i32;
+    #[link_name = "llvm.hexagon.Y6.dmpoll"]
+    fn hexagon_Y6_dmpoll() -> i32;
+    #[link_name = "llvm.hexagon.Y6.dmresume"]
+    fn hexagon_Y6_dmresume(_: i32);
+    #[link_name = "llvm.hexagon.Y6.dmstart"]
+    fn hexagon_Y6_dmstart(_: i32);
+    #[link_name = "llvm.hexagon.Y6.dmwait"]
+    fn hexagon_Y6_dmwait() -> i32;
+}
+
+/// `Rd32=abs(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(abs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_abs_R(rs: i32) -> i32 {
+    hexagon_A2_abs(rs)
+}
+
+/// `Rdd32=abs(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(abs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_abs_P(rss: i64) -> i64 {
+    hexagon_A2_absp(rss)
+}
+
+/// `Rd32=abs(Rs32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(abs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_abs_R_sat(rs: i32) -> i32 {
+    hexagon_A2_abssat(rs)
+}
+
+/// `Rd32=add(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_add(rs, rt)
+}
+
+/// `Rd32=add(Rt32.h,Rs32.h):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RhRh_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_hh(rt, rs)
+}
+
+/// `Rd32=add(Rt32.h,Rs32.l):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RhRl_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_hl(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.h):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRh_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_lh(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.l):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRl_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_ll(rt, rs)
+}
+
+/// `Rd32=add(Rt32.h,Rs32.h):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RhRh_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_sat_hh(rt, rs)
+}
+
+/// `Rd32=add(Rt32.h,Rs32.l):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RhRl_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_sat_hl(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.h):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRh_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_sat_lh(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.l):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRl_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_h16_sat_ll(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.h)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRh(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_l16_hl(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.l)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRl(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_l16_ll(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.h):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRh_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_l16_sat_hl(rt, rs)
+}
+
+/// `Rd32=add(Rt32.l,Rs32.l):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RlRl_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_addh_l16_sat_ll(rt, rs)
+}
+
+/// `Rd32=add(Rs32,#s16)`
+///
+/// Instruction Type: ALU32_ADDI
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(add, IS16 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RI<const IS16: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS16, 16);
+    hexagon_A2_addi(rs, IS16)
+}
+
+/// `Rdd32=add(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_add_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_addp(rss, rtt)
+}
+
+/// `Rdd32=add(Rss32,Rtt32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_add_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_addpsat(rss, rtt)
+}
+
+/// `Rd32=add(Rs32,Rt32):sat`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_RR_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_addsat(rs, rt)
+}
+
+/// `Rdd32=add(Rs32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_add_RP(rs: i32, rtt: i64) -> i64 {
+    hexagon_A2_addsp(rs, rtt)
+}
+
+/// `Rd32=and(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_and_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_and(rs, rt)
+}
+
+/// `Rd32=and(Rs32,#s10)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(and, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_and_RI<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_A2_andir(rs, IS10)
+}
+
+/// `Rdd32=and(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_and_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_andp(rss, rtt)
+}
+
+/// `Rd32=aslh(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(aslh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslh_R(rs: i32) -> i32 {
+    hexagon_A2_aslh(rs)
+}
+
+/// `Rd32=asrh(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asrh_R(rs: i32) -> i32 {
+    hexagon_A2_asrh(rs)
+}
+
+/// `Rd32=combine(Rt32.h,Rs32.h)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(combine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_combine_RhRh(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_combine_hh(rt, rs)
+}
+
+/// `Rd32=combine(Rt32.h,Rs32.l)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(combine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_combine_RhRl(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_combine_hl(rt, rs)
+}
+
+/// `Rd32=combine(Rt32.l,Rs32.h)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(combine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_combine_RlRh(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_combine_lh(rt, rs)
+}
+
+/// `Rd32=combine(Rt32.l,Rs32.l)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(combine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_combine_RlRl(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_combine_ll(rt, rs)
+}
+
+/// `Rdd32=combine(#s8,#S8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 1)]
+#[cfg_attr(test, assert_instr(combine, IS8 = 0, IS8_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_combine_II<const IS8: i32, const IS8_2: i32>() -> i64 {
+    static_assert_simm_bits!(IS8, 8);
+    static_assert_simm_bits!(IS8_2, 8);
+    hexagon_A2_combineii(IS8, IS8_2)
+}
+
+/// `Rdd32=combine(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(combine))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_combine_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_A2_combinew(rs, rt)
+}
+
+/// `Rd32=max(Rs32,Rt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(max))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_max_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_max(rs, rt)
+}
+
+/// `Rdd32=max(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(max))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_max_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_maxp(rss, rtt)
+}
+
+/// `Rd32=maxu(Rs32,Rt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(maxu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_maxu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_maxu(rs, rt)
+}
+
+/// `Rdd32=maxu(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(maxu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_maxu_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_maxup(rss, rtt)
+}
+
+/// `Rd32=min(Rt32,Rs32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(min))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_min_RR(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_min(rt, rs)
+}
+
+/// `Rdd32=min(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(min))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_min_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_minp(rtt, rss)
+}
+
+/// `Rd32=minu(Rt32,Rs32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(minu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_minu_RR(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_minu(rt, rs)
+}
+
+/// `Rdd32=minu(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(minu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_minu_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_minup(rtt, rss)
+}
+
+/// `Rd32=neg(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(neg))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_neg_R(rs: i32) -> i32 {
+    hexagon_A2_neg(rs)
+}
+
+/// `Rdd32=neg(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(neg))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_neg_P(rss: i64) -> i64 {
+    hexagon_A2_negp(rss)
+}
+
+/// `Rd32=neg(Rs32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(neg))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_neg_R_sat(rs: i32) -> i32 {
+    hexagon_A2_negsat(rs)
+}
+
+/// `Rd32=not(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(not))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_not_R(rs: i32) -> i32 {
+    hexagon_A2_not(rs)
+}
+
+/// `Rdd32=not(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(not))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_not_P(rss: i64) -> i64 {
+    hexagon_A2_notp(rss)
+}
+
+/// `Rd32=or(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_or_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_or(rs, rt)
+}
+
+/// `Rd32=or(Rs32,#s10)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(or, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_or_RI<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_A2_orir(rs, IS10)
+}
+
+/// `Rdd32=or(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_or_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_orp(rss, rtt)
+}
+
+/// `Rd32=round(Rss32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(round))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_round_P_sat(rss: i64) -> i32 {
+    hexagon_A2_roundsat(rss)
+}
+
+/// `Rd32=sat(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sat))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sat_P(rss: i64) -> i32 {
+    hexagon_A2_sat(rss)
+}
+
+/// `Rd32=satb(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(satb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_satb_R(rs: i32) -> i32 {
+    hexagon_A2_satb(rs)
+}
+
+/// `Rd32=sath(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sath))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sath_R(rs: i32) -> i32 {
+    hexagon_A2_sath(rs)
+}
+
+/// `Rd32=satub(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(satub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_satub_R(rs: i32) -> i32 {
+    hexagon_A2_satub(rs)
+}
+
+/// `Rd32=satuh(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(satuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_satuh_R(rs: i32) -> i32 {
+    hexagon_A2_satuh(rs)
+}
+
+/// `Rd32=sub(Rt32,Rs32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RR(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_sub(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.h,Rs32.h):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RhRh_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_hh(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.h,Rs32.l):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RhRl_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_hl(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.h):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRh_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_lh(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.l):<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRl_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_ll(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.h,Rs32.h):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RhRh_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_sat_hh(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.h,Rs32.l):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RhRl_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_sat_hl(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.h):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRh_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_sat_lh(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.l):sat:<<16`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRl_sat_s16(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_h16_sat_ll(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.h)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRh(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_l16_hl(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.l)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRl(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_l16_ll(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.h):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRh_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_l16_sat_hl(rt, rs)
+}
+
+/// `Rd32=sub(Rt32.l,Rs32.l):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RlRl_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subh_l16_sat_ll(rt, rs)
+}
+
+/// `Rdd32=sub(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_sub_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_subp(rtt, rss)
+}
+
+/// `Rd32=sub(#s10,Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(sub, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_IR<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_A2_subri(IS10, rs)
+}
+
+/// `Rd32=sub(Rt32,Rs32):sat`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_RR_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_subsat(rt, rs)
+}
+
+/// `Rd32=vaddh(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vaddh_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_svaddh(rs, rt)
+}
+
+/// `Rd32=vaddh(Rs32,Rt32):sat`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vaddh_RR_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_svaddhs(rs, rt)
+}
+
+/// `Rd32=vadduh(Rs32,Rt32):sat`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vadduh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vadduh_RR_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_svadduhs(rs, rt)
+}
+
+/// `Rd32=vavgh(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vavgh_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_svavgh(rs, rt)
+}
+
+/// `Rd32=vavgh(Rs32,Rt32):rnd`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vavgh_RR_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_svavghs(rs, rt)
+}
+
+/// `Rd32=vnavgh(Rt32,Rs32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vnavgh_RR(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_svnavgh(rt, rs)
+}
+
+/// `Rd32=vsubh(Rt32,Rs32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsubh_RR(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_svsubh(rt, rs)
+}
+
+/// `Rd32=vsubh(Rt32,Rs32):sat`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsubh_RR_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_svsubhs(rt, rs)
+}
+
+/// `Rd32=vsubuh(Rt32,Rs32):sat`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsubuh_RR_sat(rt: i32, rs: i32) -> i32 {
+    hexagon_A2_svsubuhs(rt, rs)
+}
+
+/// `Rd32=swiz(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(swiz))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_swiz_R(rs: i32) -> i32 {
+    hexagon_A2_swiz(rs)
+}
+
+/// `Rd32=sxtb(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sxtb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sxtb_R(rs: i32) -> i32 {
+    hexagon_A2_sxtb(rs)
+}
+
+/// `Rd32=sxth(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sxth))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sxth_R(rs: i32) -> i32 {
+    hexagon_A2_sxth(rs)
+}
+
+/// `Rdd32=sxtw(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sxtw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_sxtw_R(rs: i32) -> i64 {
+    hexagon_A2_sxtw(rs)
+}
+
+/// `Rd32=Rs32`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_equals_R(rs: i32) -> i32 {
+    hexagon_A2_tfr(rs)
+}
+
+/// `Rx32.h=#u16`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_Rh_equals_I<const IU16: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU16, 16);
+    hexagon_A2_tfrih(rx, IU16 as i32)
+}
+
+/// `Rx32.l=#u16`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_Rl_equals_I<const IU16: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU16, 16);
+    hexagon_A2_tfril(rx, IU16 as i32)
+}
+
+/// `Rdd32=Rss32`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_equals_P(rss: i64) -> i64 {
+    hexagon_A2_tfrp(rss)
+}
+
+/// `Rdd32=#s8`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_equals_I<const IS8: i32>() -> i64 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A2_tfrpi(IS8)
+}
+
+/// `Rd32=#s16`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_equals_I<const IS16: i32>() -> i32 {
+    static_assert_simm_bits!(IS16, 16);
+    hexagon_A2_tfrsi(IS16)
+}
+
+/// `Rdd32=vabsh(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vabsh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsh_P(rss: i64) -> i64 {
+    hexagon_A2_vabsh(rss)
+}
+
+/// `Rdd32=vabsh(Rss32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vabsh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsh_P_sat(rss: i64) -> i64 {
+    hexagon_A2_vabshsat(rss)
+}
+
+/// `Rdd32=vabsw(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vabsw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsw_P(rss: i64) -> i64 {
+    hexagon_A2_vabsw(rss)
+}
+
+/// `Rdd32=vabsw(Rss32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vabsw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsw_P_sat(rss: i64) -> i64 {
+    hexagon_A2_vabswsat(rss)
+}
+
+/// `Rdd32=vaddb(Rss32,Rtt32)`
+///
+/// Instruction Type: MAPPING
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddb_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddb_map(rss, rtt)
+}
+
+/// `Rdd32=vaddh(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddh(rss, rtt)
+}
+
+/// `Rdd32=vaddh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddhs(rss, rtt)
+}
+
+/// `Rdd32=vaddub(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddub_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddub(rss, rtt)
+}
+
+/// `Rdd32=vaddub(Rss32,Rtt32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddub_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddubs(rss, rtt)
+}
+
+/// `Rdd32=vadduh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vadduh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vadduh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vadduhs(rss, rtt)
+}
+
+/// `Rdd32=vaddw(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddw_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddw(rss, rtt)
+}
+
+/// `Rdd32=vaddw(Rss32,Rtt32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaddw_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vaddws(rss, rtt)
+}
+
+/// `Rdd32=vavgh(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavgh(rss, rtt)
+}
+
+/// `Rdd32=vavgh(Rss32,Rtt32):crnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgh_PP_crnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavghcr(rss, rtt)
+}
+
+/// `Rdd32=vavgh(Rss32,Rtt32):rnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgh_PP_rnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavghr(rss, rtt)
+}
+
+/// `Rdd32=vavgub(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgub_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavgub(rss, rtt)
+}
+
+/// `Rdd32=vavgub(Rss32,Rtt32):rnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgub_PP_rnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavgubr(rss, rtt)
+}
+
+/// `Rdd32=vavguh(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavguh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavguh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavguh(rss, rtt)
+}
+
+/// `Rdd32=vavguh(Rss32,Rtt32):rnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavguh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavguh_PP_rnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavguhr(rss, rtt)
+}
+
+/// `Rdd32=vavguw(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavguw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavguw_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavguw(rss, rtt)
+}
+
+/// `Rdd32=vavguw(Rss32,Rtt32):rnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavguw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavguw_PP_rnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavguwr(rss, rtt)
+}
+
+/// `Rdd32=vavgw(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgw_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavgw(rss, rtt)
+}
+
+/// `Rdd32=vavgw(Rss32,Rtt32):crnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgw_PP_crnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavgwcr(rss, rtt)
+}
+
+/// `Rdd32=vavgw(Rss32,Rtt32):rnd`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vavgw_PP_rnd(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vavgwr(rss, rtt)
+}
+
+/// `Pd4=vcmpb.eq(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmpbeq(rss, rtt)
+}
+
+/// `Pd4=vcmpb.gtu(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpb_gtu_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmpbgtu(rss, rtt)
+}
+
+/// `Pd4=vcmph.eq(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmph))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmph_eq_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmpheq(rss, rtt)
+}
+
+/// `Pd4=vcmph.gt(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmph))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmph_gt_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmphgt(rss, rtt)
+}
+
+/// `Pd4=vcmph.gtu(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmph))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmph_gtu_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmphgtu(rss, rtt)
+}
+
+/// `Pd4=vcmpw.eq(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpw_eq_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmpweq(rss, rtt)
+}
+
+/// `Pd4=vcmpw.gt(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpw_gt_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmpwgt(rss, rtt)
+}
+
+/// `Pd4=vcmpw.gtu(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpw_gtu_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A2_vcmpwgtu(rss, rtt)
+}
+
+/// `Rdd32=vconj(Rss32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vconj))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vconj_P_sat(rss: i64) -> i64 {
+    hexagon_A2_vconj(rss)
+}
+
+/// `Rdd32=vmaxb(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmaxb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmaxb_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vmaxb(rtt, rss)
+}
+
+/// `Rdd32=vmaxh(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmaxh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmaxh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vmaxh(rtt, rss)
+}
+
+/// `Rdd32=vmaxub(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmaxub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmaxub_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vmaxub(rtt, rss)
+}
+
+/// `Rdd32=vmaxuh(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmaxuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmaxuh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vmaxuh(rtt, rss)
+}
+
+/// `Rdd32=vmaxuw(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmaxuw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmaxuw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vmaxuw(rtt, rss)
+}
+
+/// `Rdd32=vmaxw(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmaxw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmaxw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vmaxw(rtt, rss)
+}
+
+/// `Rdd32=vminb(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vminb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vminb_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vminb(rtt, rss)
+}
+
+/// `Rdd32=vminh(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vminh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vminh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vminh(rtt, rss)
+}
+
+/// `Rdd32=vminub(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vminub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vminub_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vminub(rtt, rss)
+}
+
+/// `Rdd32=vminuh(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vminuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vminuh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vminuh(rtt, rss)
+}
+
+/// `Rdd32=vminuw(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vminuw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vminuw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vminuw(rtt, rss)
+}
+
+/// `Rdd32=vminw(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vminw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vminw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vminw(rtt, rss)
+}
+
+/// `Rdd32=vnavgh(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vnavgh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vnavgh(rtt, rss)
+}
+
+/// `Rdd32=vnavgh(Rtt32,Rss32):crnd:sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vnavgh_PP_crnd_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vnavghcr(rtt, rss)
+}
+
+/// `Rdd32=vnavgh(Rtt32,Rss32):rnd:sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vnavgh_PP_rnd_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vnavghr(rtt, rss)
+}
+
+/// `Rdd32=vnavgw(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vnavgw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vnavgw(rtt, rss)
+}
+
+/// `Rdd32=vnavgw(Rtt32,Rss32):crnd:sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vnavgw_PP_crnd_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vnavgwcr(rtt, rss)
+}
+
+/// `Rdd32=vnavgw(Rtt32,Rss32):rnd:sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vnavgw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vnavgw_PP_rnd_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vnavgwr(rtt, rss)
+}
+
+/// `Rdd32=vraddub(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vraddub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vraddub_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vraddub(rss, rtt)
+}
+
+/// `Rxx32+=vraddub(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vraddub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vraddubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vraddub_acc(rxx, rss, rtt)
+}
+
+/// `Rdd32=vrsadub(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrsadub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrsadub_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vrsadub(rss, rtt)
+}
+
+/// `Rxx32+=vrsadub(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrsadub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrsadubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vrsadub_acc(rxx, rss, rtt)
+}
+
+/// `Rdd32=vsubb(Rss32,Rtt32)`
+///
+/// Instruction Type: MAPPING
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubb_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_vsubb_map(rss, rtt)
+}
+
+/// `Rdd32=vsubh(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsubh(rtt, rss)
+}
+
+/// `Rdd32=vsubh(Rtt32,Rss32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubh_PP_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsubhs(rtt, rss)
+}
+
+/// `Rdd32=vsubub(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubub_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsubub(rtt, rss)
+}
+
+/// `Rdd32=vsubub(Rtt32,Rss32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubub_PP_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsububs(rtt, rss)
+}
+
+/// `Rdd32=vsubuh(Rtt32,Rss32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubuh_PP_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsubuhs(rtt, rss)
+}
+
+/// `Rdd32=vsubw(Rtt32,Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsubw(rtt, rss)
+}
+
+/// `Rdd32=vsubw(Rtt32,Rss32):sat`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsubw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsubw_PP_sat(rtt: i64, rss: i64) -> i64 {
+    hexagon_A2_vsubws(rtt, rss)
+}
+
+/// `Rd32=xor(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_xor_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A2_xor(rs, rt)
+}
+
+/// `Rdd32=xor(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_xor_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_A2_xorp(rss, rtt)
+}
+
+/// `Rd32=zxtb(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(zxtb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_zxtb_R(rs: i32) -> i32 {
+    hexagon_A2_zxtb(rs)
+}
+
+/// `Rd32=zxth(Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(zxth))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_zxth_R(rs: i32) -> i32 {
+    hexagon_A2_zxth(rs)
+}
+
+/// `Rd32=and(Rt32,~Rs32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_and_RnR(rt: i32, rs: i32) -> i32 {
+    hexagon_A4_andn(rt, rs)
+}
+
+/// `Rdd32=and(Rtt32,~Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_and_PnP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A4_andnp(rtt, rss)
+}
+
+/// `Rdd32=bitsplit(Rs32,Rt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(bitsplit))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_bitsplit_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_A4_bitsplit(rs, rt)
+}
+
+/// `Rdd32=bitsplit(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(bitsplit, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_bitsplit_RI<const IU5: u32>(rs: i32) -> i64 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_A4_bitspliti(rs, IU5 as i32)
+}
+
+/// `Pd4=boundscheck(Rs32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(boundscheck))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_boundscheck_RP(rs: i32, rtt: i64) -> i32 {
+    hexagon_A4_boundscheck(rs, rtt)
+}
+
+/// `Pd4=cmpb.eq(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmpb_eq_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cmpbeq(rs, rt)
+}
+
+/// `Pd4=cmpb.eq(Rs32,#u8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmpb, IU8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmpb_eq_RI<const IU8: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    hexagon_A4_cmpbeqi(rs, IU8 as i32)
+}
+
+/// `Pd4=cmpb.gt(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmpb_gt_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cmpbgt(rs, rt)
+}
+
+/// `Pd4=cmpb.gt(Rs32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmpb, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmpb_gt_RI<const IS8: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_cmpbgti(rs, IS8)
+}
+
+/// `Pd4=cmpb.gtu(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmpb_gtu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cmpbgtu(rs, rt)
+}
+
+/// `Pd4=cmpb.gtu(Rs32,#u7)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmpb, IU7 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmpb_gtu_RI<const IU7: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU7, 7);
+    hexagon_A4_cmpbgtui(rs, IU7 as i32)
+}
+
+/// `Pd4=cmph.eq(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmph))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmph_eq_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cmpheq(rs, rt)
+}
+
+/// `Pd4=cmph.eq(Rs32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmph, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmph_eq_RI<const IS8: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_cmpheqi(rs, IS8)
+}
+
+/// `Pd4=cmph.gt(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmph))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmph_gt_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cmphgt(rs, rt)
+}
+
+/// `Pd4=cmph.gt(Rs32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmph, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmph_gt_RI<const IS8: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_cmphgti(rs, IS8)
+}
+
+/// `Pd4=cmph.gtu(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmph))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmph_gtu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cmphgtu(rs, rt)
+}
+
+/// `Pd4=cmph.gtu(Rs32,#u7)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmph, IU7 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmph_gtu_RI<const IU7: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU7, 7);
+    hexagon_A4_cmphgtui(rs, IU7 as i32)
+}
+
+/// `Rdd32=combine(#s8,Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(combine, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_combine_IR<const IS8: i32>(rs: i32) -> i64 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_combineir(IS8, rs)
+}
+
+/// `Rdd32=combine(Rs32,#s8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(combine, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_combine_RI<const IS8: i32>(rs: i32) -> i64 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_combineri(rs, IS8)
+}
+
+/// `Rd32=cround(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cround, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cround_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_A4_cround_ri(rs, IU5 as i32)
+}
+
+/// `Rd32=cround(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cround))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cround_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_cround_rr(rs, rt)
+}
+
+/// `Rd32=modwrap(Rs32,Rt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(modwrap))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_modwrap_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_modwrapu(rs, rt)
+}
+
+/// `Rd32=or(Rt32,~Rs32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_or_RnR(rt: i32, rs: i32) -> i32 {
+    hexagon_A4_orn(rt, rs)
+}
+
+/// `Rdd32=or(Rtt32,~Rss32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_or_PnP(rtt: i64, rss: i64) -> i64 {
+    hexagon_A4_ornp(rtt, rss)
+}
+
+/// `Rd32=cmp.eq(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_rcmpeq(rs, rt)
+}
+
+/// `Rd32=cmp.eq(Rs32,#s8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmp, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmp_eq_RI<const IS8: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_rcmpeqi(rs, IS8)
+}
+
+/// `Rd32=!cmp.eq(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_rcmpneq(rs, rt)
+}
+
+/// `Rd32=!cmp.eq(Rs32,#s8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_not_cmp_eq_RI<const IS8: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_rcmpneqi(rs, IS8)
+}
+
+/// `Rd32=round(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(round, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_round_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_A4_round_ri(rs, IU5 as i32)
+}
+
+/// `Rd32=round(Rs32,#u5):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(round, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_round_RI_sat<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_A4_round_ri_sat(rs, IU5 as i32)
+}
+
+/// `Rd32=round(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(round))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_round_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_round_rr(rs, rt)
+}
+
+/// `Rd32=round(Rs32,Rt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(round))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_round_RR_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_A4_round_rr_sat(rs, rt)
+}
+
+/// `Pd4=tlbmatch(Rss32,Rt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(tlbmatch))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_tlbmatch_PR(rss: i64, rt: i32) -> i32 {
+    hexagon_A4_tlbmatch(rss, rt)
+}
+
+/// `Pd4=any8(vcmpb.eq(Rss32,Rtt32))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(any8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A4_vcmpbeq_any(rss, rtt)
+}
+
+/// `Pd4=vcmpb.eq(Rss32,#u8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmpb, IU8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpb_eq_PI<const IU8: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    hexagon_A4_vcmpbeqi(rss, IU8 as i32)
+}
+
+/// `Pd4=vcmpb.gt(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpb_gt_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A4_vcmpbgt(rss, rtt)
+}
+
+/// `Pd4=vcmpb.gt(Rss32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmpb, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpb_gt_PI<const IS8: i32>(rss: i64) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_vcmpbgti(rss, IS8)
+}
+
+/// `Pd4=vcmpb.gtu(Rss32,#u7)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmpb, IU7 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpb_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU7, 7);
+    hexagon_A4_vcmpbgtui(rss, IU7 as i32)
+}
+
+/// `Pd4=vcmph.eq(Rss32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmph_eq_PI<const IS8: i32>(rss: i64) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_vcmpheqi(rss, IS8)
+}
+
+/// `Pd4=vcmph.gt(Rss32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmph_gt_PI<const IS8: i32>(rss: i64) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_vcmphgti(rss, IS8)
+}
+
+/// `Pd4=vcmph.gtu(Rss32,#u7)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmph, IU7 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmph_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU7, 7);
+    hexagon_A4_vcmphgtui(rss, IU7 as i32)
+}
+
+/// `Pd4=vcmpw.eq(Rss32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpw_eq_PI<const IS8: i32>(rss: i64) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_vcmpweqi(rss, IS8)
+}
+
+/// `Pd4=vcmpw.gt(Rss32,#s8)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpw_gt_PI<const IS8: i32>(rss: i64) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_A4_vcmpwgti(rss, IS8)
+}
+
+/// `Pd4=vcmpw.gtu(Rss32,#u7)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vcmpw, IU7 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_vcmpw_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU7, 7);
+    hexagon_A4_vcmpwgtui(rss, IU7 as i32)
+}
+
+/// `Rxx32=vrmaxh(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmaxh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmaxh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrmaxh(rxx, rss, ru)
+}
+
+/// `Rxx32=vrmaxuh(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmaxuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmaxuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrmaxuh(rxx, rss, ru)
+}
+
+/// `Rxx32=vrmaxuw(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmaxuw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmaxuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrmaxuw(rxx, rss, ru)
+}
+
+/// `Rxx32=vrmaxw(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmaxw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmaxw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrmaxw(rxx, rss, ru)
+}
+
+/// `Rxx32=vrminh(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrminh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrminh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrminh(rxx, rss, ru)
+}
+
+/// `Rxx32=vrminuh(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrminuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrminuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrminuh(rxx, rss, ru)
+}
+
+/// `Rxx32=vrminuw(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrminuw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrminuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrminuw(rxx, rss, ru)
+}
+
+/// `Rxx32=vrminw(Rss32,Ru32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrminw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrminw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
+    hexagon_A4_vrminw(rxx, rss, ru)
+}
+
+/// `Rd32=vaddhub(Rss32,Rtt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaddhub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vaddhub_PP_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_A5_vaddhubs(rss, rtt)
+}
+
+/// `Pd4=all8(Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(all8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_all8_p(ps: i32) -> i32 {
+    hexagon_C2_all8(ps)
+}
+
+/// `Pd4=and(Pt4,Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_and_pp(pt: i32, ps: i32) -> i32 {
+    hexagon_C2_and(pt, ps)
+}
+
+/// `Pd4=and(Pt4,!Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_and_pnp(pt: i32, ps: i32) -> i32 {
+    hexagon_C2_andn(pt, ps)
+}
+
+/// `Pd4=any8(Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(any8))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_any8_p(ps: i32) -> i32 {
+    hexagon_C2_any8(ps)
+}
+
+/// `Pd4=bitsclr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(bitsclr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_bitsclr_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_bitsclr(rs, rt)
+}
+
+/// `Pd4=bitsclr(Rs32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(bitsclr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_bitsclr_RI<const IU6: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_C2_bitsclri(rs, IU6 as i32)
+}
+
+/// `Pd4=bitsset(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(bitsset))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_bitsset_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_bitsset(rs, rt)
+}
+
+/// `Pd4=cmp.eq(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_cmpeq(rs, rt)
+}
+
+/// `Pd4=cmp.eq(Rs32,#s10)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmp, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_eq_RI<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_C2_cmpeqi(rs, IS10)
+}
+
+/// `Pd4=cmp.eq(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_eq_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_C2_cmpeqp(rss, rtt)
+}
+
+/// `Pd4=cmp.ge(Rs32,#s8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmp, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_ge_RI<const IS8: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_C2_cmpgei(rs, IS8)
+}
+
+/// `Pd4=cmp.geu(Rs32,#u8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmp, IU8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_geu_RI<const IU8: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    hexagon_C2_cmpgeui(rs, IU8 as i32)
+}
+
+/// `Pd4=cmp.gt(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_gt_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_cmpgt(rs, rt)
+}
+
+/// `Pd4=cmp.gt(Rs32,#s10)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmp, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_gt_RI<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_C2_cmpgti(rs, IS10)
+}
+
+/// `Pd4=cmp.gt(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_gt_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_C2_cmpgtp(rss, rtt)
+}
+
+/// `Pd4=cmp.gtu(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_gtu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_cmpgtu(rs, rt)
+}
+
+/// `Pd4=cmp.gtu(Rs32,#u9)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cmp, IU9 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_gtu_RI<const IU9: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU9, 9);
+    hexagon_C2_cmpgtui(rs, IU9 as i32)
+}
+
+/// `Pd4=cmp.gtu(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_gtu_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_C2_cmpgtup(rss, rtt)
+}
+
+/// `Pd4=cmp.lt(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_lt_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_cmplt(rs, rt)
+}
+
+/// `Pd4=cmp.ltu(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_cmp_ltu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C2_cmpltu(rs, rt)
+}
+
+/// `Rdd32=mask(Pt4)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mask))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mask_p(pt: i32) -> i64 {
+    hexagon_C2_mask(pt)
+}
+
+/// `Rd32=mux(Pu4,Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mux))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mux_pRR(pu: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_C2_mux(pu, rs, rt)
+}
+
+/// `Rd32=mux(Pu4,#s8,#S8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1, 2)]
+#[cfg_attr(test, assert_instr(mux, IS8 = 0, IS8_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mux_pII<const IS8: i32, const IS8_2: i32>(pu: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    static_assert_simm_bits!(IS8_2, 8);
+    hexagon_C2_muxii(pu, IS8, IS8_2)
+}
+
+/// `Rd32=mux(Pu4,Rs32,#s8)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(mux, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mux_pRI<const IS8: i32>(pu: i32, rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_C2_muxir(pu, rs, IS8)
+}
+
+/// `Rd32=mux(Pu4,#s8,Rs32)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(mux, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mux_pIR<const IS8: i32>(pu: i32, rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_C2_muxri(pu, IS8, rs)
+}
+
+/// `Pd4=not(Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(not))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_p(ps: i32) -> i32 {
+    hexagon_C2_not(ps)
+}
+
+/// `Pd4=or(Pt4,Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_or_pp(pt: i32, ps: i32) -> i32 {
+    hexagon_C2_or(pt, ps)
+}
+
+/// `Pd4=or(Pt4,!Ps4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_or_pnp(pt: i32, ps: i32) -> i32 {
+    hexagon_C2_orn(pt, ps)
+}
+
+/// `Pd4=Ps4`
+///
+/// Instruction Type: MAPPING
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_equals_p(ps: i32) -> i32 {
+    hexagon_C2_pxfer_map(ps)
+}
+
+/// `Rd32=Ps4`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_equals_p(ps: i32) -> i32 {
+    hexagon_C2_tfrpr(ps)
+}
+
+/// `Pd4=Rs32`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_equals_R(rs: i32) -> i32 {
+    hexagon_C2_tfrrp(rs)
+}
+
+/// `Rd32=vitpack(Ps4,Pt4)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vitpack))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vitpack_pp(ps: i32, pt: i32) -> i32 {
+    hexagon_C2_vitpack(ps, pt)
+}
+
+/// `Rdd32=vmux(Pu4,Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmux))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmux_pPP(pu: i32, rss: i64, rtt: i64) -> i64 {
+    hexagon_C2_vmux(pu, rss, rtt)
+}
+
+/// `Pd4=xor(Ps4,Pt4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_xor_pp(ps: i32, pt: i32) -> i32 {
+    hexagon_C2_xor(ps, pt)
+}
+
+/// `Pd4=and(Ps4,and(Pt4,Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_and_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_and_and(ps, pt, pu)
+}
+
+/// `Pd4=and(Ps4,and(Pt4,!Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_and_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_and_andn(ps, pt, pu)
+}
+
+/// `Pd4=and(Ps4,or(Pt4,Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_and_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_and_or(ps, pt, pu)
+}
+
+/// `Pd4=and(Ps4,or(Pt4,!Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_and_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_and_orn(ps, pt, pu)
+}
+
+/// `Pd4=!cmp.gt(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_cmp_gt_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C4_cmplte(rs, rt)
+}
+
+/// `Pd4=!cmp.gt(Rs32,#s10)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_cmp_gt_RI<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_C4_cmpltei(rs, IS10)
+}
+
+/// `Pd4=!cmp.gtu(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_cmp_gtu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C4_cmplteu(rs, rt)
+}
+
+/// `Pd4=!cmp.gtu(Rs32,#u9)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_cmp_gtu_RI<const IU9: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU9, 9);
+    hexagon_C4_cmplteui(rs, IU9 as i32)
+}
+
+/// `Pd4=!cmp.eq(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C4_cmpneq(rs, rt)
+}
+
+/// `Pd4=!cmp.eq(Rs32,#s10)`
+///
+/// Instruction Type: ALU32_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_cmp_eq_RI<const IS10: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_C4_cmpneqi(rs, IS10)
+}
+
+/// `Pd4=fastcorner9(Ps4,Pt4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(fastcorner9))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_fastcorner9_pp(ps: i32, pt: i32) -> i32 {
+    hexagon_C4_fastcorner9(ps, pt)
+}
+
+/// `Pd4=!fastcorner9(Ps4,Pt4)`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_fastcorner9_pp(ps: i32, pt: i32) -> i32 {
+    hexagon_C4_fastcorner9_not(ps, pt)
+}
+
+/// `Pd4=!bitsclr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_bitsclr_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C4_nbitsclr(rs, rt)
+}
+
+/// `Pd4=!bitsclr(Rs32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_bitsclr_RI<const IU6: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_C4_nbitsclri(rs, IU6 as i32)
+}
+
+/// `Pd4=!bitsset(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_bitsset_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_C4_nbitsset(rs, rt)
+}
+
+/// `Pd4=or(Ps4,and(Pt4,Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_or_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_or_and(ps, pt, pu)
+}
+
+/// `Pd4=or(Ps4,and(Pt4,!Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_or_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_or_andn(ps, pt, pu)
+}
+
+/// `Pd4=or(Ps4,or(Pt4,Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_or_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_or_or(ps, pt, pu)
+}
+
+/// `Pd4=or(Ps4,or(Pt4,!Pu4))`
+///
+/// Instruction Type: CR
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_or_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
+    hexagon_C4_or_orn(ps, pt, pu)
+}
+
+/// `Rdd32=convert_d2df(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_d2df))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_d2df_P(rss: i64) -> f64 {
+    hexagon_F2_conv_d2df(rss)
+}
+
+/// `Rd32=convert_d2sf(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_d2sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_d2sf_P(rss: i64) -> f32 {
+    hexagon_F2_conv_d2sf(rss)
+}
+
+/// `Rdd32=convert_df2d(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2d))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_df2d_P(rss: f64) -> i64 {
+    hexagon_F2_conv_df2d(rss)
+}
+
+/// `Rdd32=convert_df2d(Rss32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2d))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_df2d_P_chop(rss: f64) -> i64 {
+    hexagon_F2_conv_df2d_chop(rss)
+}
+
+/// `Rd32=convert_df2sf(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_df2sf_P(rss: f64) -> f32 {
+    hexagon_F2_conv_df2sf(rss)
+}
+
+/// `Rdd32=convert_df2ud(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2ud))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_df2ud_P(rss: f64) -> i64 {
+    hexagon_F2_conv_df2ud(rss)
+}
+
+/// `Rdd32=convert_df2ud(Rss32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2ud))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_df2ud_P_chop(rss: f64) -> i64 {
+    hexagon_F2_conv_df2ud_chop(rss)
+}
+
+/// `Rd32=convert_df2uw(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2uw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_df2uw_P(rss: f64) -> i32 {
+    hexagon_F2_conv_df2uw(rss)
+}
+
+/// `Rd32=convert_df2uw(Rss32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2uw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_df2uw_P_chop(rss: f64) -> i32 {
+    hexagon_F2_conv_df2uw_chop(rss)
+}
+
+/// `Rd32=convert_df2w(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_df2w_P(rss: f64) -> i32 {
+    hexagon_F2_conv_df2w(rss)
+}
+
+/// `Rd32=convert_df2w(Rss32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_df2w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_df2w_P_chop(rss: f64) -> i32 {
+    hexagon_F2_conv_df2w_chop(rss)
+}
+
+/// `Rdd32=convert_sf2d(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2d))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_sf2d_R(rs: f32) -> i64 {
+    hexagon_F2_conv_sf2d(rs)
+}
+
+/// `Rdd32=convert_sf2d(Rs32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2d))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_sf2d_R_chop(rs: f32) -> i64 {
+    hexagon_F2_conv_sf2d_chop(rs)
+}
+
+/// `Rdd32=convert_sf2df(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2df))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_sf2df_R(rs: f32) -> f64 {
+    hexagon_F2_conv_sf2df(rs)
+}
+
+/// `Rdd32=convert_sf2ud(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2ud))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_sf2ud_R(rs: f32) -> i64 {
+    hexagon_F2_conv_sf2ud(rs)
+}
+
+/// `Rdd32=convert_sf2ud(Rs32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2ud))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_sf2ud_R_chop(rs: f32) -> i64 {
+    hexagon_F2_conv_sf2ud_chop(rs)
+}
+
+/// `Rd32=convert_sf2uw(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2uw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_sf2uw_R(rs: f32) -> i32 {
+    hexagon_F2_conv_sf2uw(rs)
+}
+
+/// `Rd32=convert_sf2uw(Rs32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2uw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_sf2uw_R_chop(rs: f32) -> i32 {
+    hexagon_F2_conv_sf2uw_chop(rs)
+}
+
+/// `Rd32=convert_sf2w(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_sf2w_R(rs: f32) -> i32 {
+    hexagon_F2_conv_sf2w(rs)
+}
+
+/// `Rd32=convert_sf2w(Rs32):chop`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_sf2w))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_sf2w_R_chop(rs: f32) -> i32 {
+    hexagon_F2_conv_sf2w_chop(rs)
+}
+
+/// `Rdd32=convert_ud2df(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_ud2df))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_ud2df_P(rss: i64) -> f64 {
+    hexagon_F2_conv_ud2df(rss)
+}
+
+/// `Rd32=convert_ud2sf(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_ud2sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_ud2sf_P(rss: i64) -> f32 {
+    hexagon_F2_conv_ud2sf(rss)
+}
+
+/// `Rdd32=convert_uw2df(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_uw2df))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_uw2df_R(rs: i32) -> f64 {
+    hexagon_F2_conv_uw2df(rs)
+}
+
+/// `Rd32=convert_uw2sf(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_uw2sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_uw2sf_R(rs: i32) -> f32 {
+    hexagon_F2_conv_uw2sf(rs)
+}
+
+/// `Rdd32=convert_w2df(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_w2df))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_convert_w2df_R(rs: i32) -> f64 {
+    hexagon_F2_conv_w2df(rs)
+}
+
+/// `Rd32=convert_w2sf(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(convert_w2sf))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_convert_w2sf_R(rs: i32) -> f32 {
+    hexagon_F2_conv_w2sf(rs)
+}
+
+/// `Pd4=dfclass(Rss32,#u5)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(dfclass, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_dfclass_PI<const IU5: u32>(rss: f64) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_F2_dfclass(rss, IU5 as i32)
+}
+
+/// `Pd4=dfcmp.eq(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_dfcmp_eq_PP(rss: f64, rtt: f64) -> i32 {
+    hexagon_F2_dfcmpeq(rss, rtt)
+}
+
+/// `Pd4=dfcmp.ge(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_dfcmp_ge_PP(rss: f64, rtt: f64) -> i32 {
+    hexagon_F2_dfcmpge(rss, rtt)
+}
+
+/// `Pd4=dfcmp.gt(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_dfcmp_gt_PP(rss: f64, rtt: f64) -> i32 {
+    hexagon_F2_dfcmpgt(rss, rtt)
+}
+
+/// `Pd4=dfcmp.uo(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_dfcmp_uo_PP(rss: f64, rtt: f64) -> i32 {
+    hexagon_F2_dfcmpuo(rss, rtt)
+}
+
+/// `Rdd32=dfmake(#u10):neg`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmake_I_neg<const IU10: u32>() -> f64 {
+    static_assert_uimm_bits!(IU10, 10);
+    hexagon_F2_dfimm_n(IU10 as i32)
+}
+
+/// `Rdd32=dfmake(#u10):pos`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmake_I_pos<const IU10: u32>() -> f64 {
+    static_assert_uimm_bits!(IU10, 10);
+    hexagon_F2_dfimm_p(IU10 as i32)
+}
+
+/// `Rd32=sfadd(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfadd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfadd_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sfadd(rs, rt)
+}
+
+/// `Pd4=sfclass(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(sfclass, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_sfclass_RI<const IU5: u32>(rs: f32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_F2_sfclass(rs, IU5 as i32)
+}
+
+/// `Pd4=sfcmp.eq(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_sfcmp_eq_RR(rs: f32, rt: f32) -> i32 {
+    hexagon_F2_sfcmpeq(rs, rt)
+}
+
+/// `Pd4=sfcmp.ge(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_sfcmp_ge_RR(rs: f32, rt: f32) -> i32 {
+    hexagon_F2_sfcmpge(rs, rt)
+}
+
+/// `Pd4=sfcmp.gt(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_sfcmp_gt_RR(rs: f32, rt: f32) -> i32 {
+    hexagon_F2_sfcmpgt(rs, rt)
+}
+
+/// `Pd4=sfcmp.uo(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfcmp))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_sfcmp_uo_RR(rs: f32, rt: f32) -> i32 {
+    hexagon_F2_sfcmpuo(rs, rt)
+}
+
+/// `Rd32=sffixupd(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sffixupd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sffixupd_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sffixupd(rs, rt)
+}
+
+/// `Rd32=sffixupn(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sffixupn))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sffixupn_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sffixupn(rs, rt)
+}
+
+/// `Rd32=sffixupr(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sffixupr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sffixupr_R(rs: f32) -> f32 {
+    hexagon_F2_sffixupr(rs)
+}
+
+/// `Rx32+=sfmpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmpyacc_RR(rx: f32, rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sffma(rx, rs, rt)
+}
+
+/// `Rx32+=sfmpy(Rs32,Rt32):lib`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmpyacc_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sffma_lib(rx, rs, rt)
+}
+
+/// `Rx32+=sfmpy(Rs32,Rt32,Pu4):scale`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmpyacc_RRp_scale(rx: f32, rs: f32, rt: f32, pu: i32) -> f32 {
+    hexagon_F2_sffma_sc(rx, rs, rt, pu)
+}
+
+/// `Rx32-=sfmpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmpynac_RR(rx: f32, rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sffms(rx, rs, rt)
+}
+
+/// `Rx32-=sfmpy(Rs32,Rt32):lib`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmpynac_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sffms_lib(rx, rs, rt)
+}
+
+/// `Rd32=sfmake(#u10):neg`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmake_I_neg<const IU10: u32>() -> f32 {
+    static_assert_uimm_bits!(IU10, 10);
+    hexagon_F2_sfimm_n(IU10 as i32)
+}
+
+/// `Rd32=sfmake(#u10):pos`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmake_I_pos<const IU10: u32>() -> f32 {
+    static_assert_uimm_bits!(IU10, 10);
+    hexagon_F2_sfimm_p(IU10 as i32)
+}
+
+/// `Rd32=sfmax(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmax))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmax_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sfmax(rs, rt)
+}
+
+/// `Rd32=sfmin(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmin))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmin_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sfmin(rs, rt)
+}
+
+/// `Rd32=sfmpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfmpy_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sfmpy(rs, rt)
+}
+
+/// `Rd32=sfsub(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sfsub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sfsub_RR(rs: f32, rt: f32) -> f32 {
+    hexagon_F2_sfsub(rs, rt)
+}
+
+/// `Rx32+=add(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_addacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_acci(rx, rs, rt)
+}
+
+/// `Rx32+=add(Rs32,#s8)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(add, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_addacc_RI<const IS8: i32>(rx: i32, rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_M2_accii(rx, rs, IS8)
+}
+
+/// `Rxx32+=cmpyi(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyiacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmaci_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=cmpyr(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyracc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmacr_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=cmpy(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmacs_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=cmpy(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmacs_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=cmpy(Rs32,Rt32*):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyacc_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmacsc_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=cmpy(Rs32,Rt32*):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyacc_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmacsc_s1(rxx, rs, rt)
+}
+
+/// `Rdd32=cmpyi(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyi_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmpyi_s0(rs, rt)
+}
+
+/// `Rdd32=cmpyr(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyr_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmpyr_s0(rs, rt)
+}
+
+/// `Rd32=cmpy(Rs32,Rt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpy_RR_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_cmpyrs_s0(rs, rt)
+}
+
+/// `Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpy_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_cmpyrs_s1(rs, rt)
+}
+
+/// `Rd32=cmpy(Rs32,Rt32*):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpy_RR_conj_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_cmpyrsc_s0(rs, rt)
+}
+
+/// `Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpy_RR_conj_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_cmpyrsc_s1(rs, rt)
+}
+
+/// `Rdd32=cmpy(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpy_RR_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmpys_s0(rs, rt)
+}
+
+/// `Rdd32=cmpy(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpy_RR_s1_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmpys_s1(rs, rt)
+}
+
+/// `Rdd32=cmpy(Rs32,Rt32*):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpy_RR_conj_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmpysc_s0(rs, rt)
+}
+
+/// `Rdd32=cmpy(Rs32,Rt32*):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpy_RR_conj_s1_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cmpysc_s1(rs, rt)
+}
+
+/// `Rxx32-=cmpy(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpynac_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cnacs_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=cmpy(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpynac_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cnacs_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=cmpy(Rs32,Rt32*):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpynac_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cnacsc_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=cmpy(Rs32,Rt32*):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpynac_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_cnacsc_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_dpmpyss_acc_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_dpmpyss_nac_s0(rxx, rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RR_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_dpmpyss_rnd_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_dpmpyss_s0(rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_dpmpyuu_acc_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_dpmpyuu_nac_s0(rxx, rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_dpmpyuu_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_hmmpyh_rs1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RRh_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_hmmpyh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_hmmpyl_rs1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RRl_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_hmmpyl_s1(rs, rt)
+}
+
+/// `Rx32+=mpyi(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyiacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_maci(rx, rs, rt)
+}
+
+/// `Rx32-=mpyi(Rs32,#u8)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyinac_RI<const IU8: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    hexagon_M2_macsin(rx, rs, IU8 as i32)
+}
+
+/// `Rx32+=mpyi(Rs32,#u8)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyiacc_RI<const IU8: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    hexagon_M2_macsip(rx, rs, IU8 as i32)
+}
+
+/// `Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywohacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmachs_rs0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywohacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmachs_rs1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywoh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywohacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmachs_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywohacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmachs_s1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywehacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacls_rs0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywehacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacls_rs1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacls_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacls_s1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacuhs_rs0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacuhs_rs1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywouh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacuhs_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmacuhs_s1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmaculs_rs0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmaculs_rs1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweuh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmaculs_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmaculs_s1(rxx, rss, rtt)
+}
+
+/// `Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywoh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyh_rs0(rss, rtt)
+}
+
+/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywoh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyh_rs1(rss, rtt)
+}
+
+/// `Rdd32=vmpywoh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywoh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyh_s0(rss, rtt)
+}
+
+/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywoh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyh_s1(rss, rtt)
+}
+
+/// `Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyl_rs0(rss, rtt)
+}
+
+/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyl_rs1(rss, rtt)
+}
+
+/// `Rdd32=vmpyweh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyl_s0(rss, rtt)
+}
+
+/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyl_s1(rss, rtt)
+}
+
+/// `Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyuh_rs0(rss, rtt)
+}
+
+/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyuh_rs1(rss, rtt)
+}
+
+/// `Rdd32=vmpywouh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyuh_s0(rss, rtt)
+}
+
+/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpywouh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpywouh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyuh_s1(rss, rtt)
+}
+
+/// `Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyul_rs0(rss, rtt)
+}
+
+/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyul_rs1(rss, rtt)
+}
+
+/// `Rdd32=vmpyweuh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyul_s0(rss, rtt)
+}
+
+/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyweuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyweuh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_mmpyul_s1(rss, rtt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_hh_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_hh_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_hl_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_hl_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_lh_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_lh_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_ll_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_ll_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.h):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_hh_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_hh_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.l):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_hl_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_hl_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.h):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_lh_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_lh_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.l):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_ll_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_acc_sat_ll_s1(rx, rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_hh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_hh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_hl_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_hl_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_lh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_lh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_ll_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_ll_s1(rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_hh_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_hh_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_hl_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_hl_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_lh_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_lh_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_ll_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_ll_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.h):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_hh_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_hh_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.l):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_hl_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_hl_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.h):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_lh_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_lh_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.l):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_ll_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_nac_sat_ll_s1(rx, rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_hh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_hh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_hl_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_hl_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_lh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_lh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_ll_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_rnd_ll_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_hh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_hh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_hl_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_hl_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_lh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_lh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_ll_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_ll_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_hh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_hh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_hl_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RhRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_hl_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_lh_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_lh_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_ll_s0(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RlRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_sat_rnd_ll_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_up(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RR_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_up_s1(rs, rt)
+}
+
+/// `Rd32=mpy(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpy_RR_s1_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpy_up_s1_sat(rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_hh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_hh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_hl_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_hl_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_lh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_lh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_ll_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpy(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_acc_ll_s1(rxx, rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRh(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_hh_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRh_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_hh_s1(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRl(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_hl_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRl_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_hl_s1(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRh(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_lh_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRh_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_lh_s1(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRl(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_ll_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRl_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_ll_s1(rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_hh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_hh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_hl_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_hl_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_lh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_lh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_ll_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpy(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpynac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_nac_ll_s1(rxx, rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.h):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRh_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_hh_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_hh_s1(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.l):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRl_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_hl_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_hl_s1(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.h):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRh_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_lh_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_lh_s1(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.l):rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRl_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_ll_s0(rs, rt)
+}
+
+/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyd_rnd_ll_s1(rs, rt)
+}
+
+/// `Rd32=mpyi(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyi_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyi(rs, rt)
+}
+
+/// `Rd32=mpyi(Rs32,#m9)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyi_RI(rs: i32, im9: i32) -> i32 {
+    hexagon_M2_mpysmi(rs, im9)
+}
+
+/// `Rd32=mpysu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpysu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpysu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpysu_up(rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_hh_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_hh_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_hl_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_hl_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_lh_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_lh_s1(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_ll_s0(rx, rs, rt)
+}
+
+/// `Rx32+=mpyu(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyuacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_acc_ll_s1(rx, rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RhRh(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_hh_s0(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RhRh_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_hh_s1(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RhRl(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_hl_s0(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RhRl_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_hl_s1(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RlRh(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_lh_s0(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RlRh_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_lh_s1(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RlRl(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_ll_s0(rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RlRl_s1(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_ll_s1(rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_hh_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_hh_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_hl_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_hl_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_lh_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_lh_s1(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_ll_s0(rx, rs, rt)
+}
+
+/// `Rx32-=mpyu(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyunac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_nac_ll_s1(rx, rs, rt)
+}
+
+/// `Rd32=mpyu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyu_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyu_up(rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_hh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_hh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_hl_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_hl_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_lh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_lh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_ll_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=mpyu(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyuacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_acc_ll_s1(rxx, rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RhRh(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_hh_s0(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RhRh_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_hh_s1(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RhRl(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_hl_s0(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RhRl_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_hl_s1(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RlRh(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_lh_s0(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RlRh_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_lh_s1(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RlRl(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_ll_s0(rs, rt)
+}
+
+/// `Rdd32=mpyu(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyu_RlRl_s1(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_ll_s1(rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.h,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_hh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.h,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_hh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.h,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_hl_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.h,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_hl_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.l,Rt32.h)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_lh_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.l,Rt32.h):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_lh_s1(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.l,Rt32.l)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_ll_s0(rxx, rs, rt)
+}
+
+/// `Rxx32-=mpyu(Rs32.l,Rt32.l):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_mpyunac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_mpyud_nac_ll_s1(rxx, rs, rt)
+}
+
+/// `Rd32=mpyui(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpyui))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyui_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mpyui(rs, rt)
+}
+
+/// `Rx32-=add(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_addnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_nacci(rx, rs, rt)
+}
+
+/// `Rx32-=add(Rs32,#s8)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(add, IS8 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_addnac_RI<const IS8: i32>(rx: i32, rs: i32) -> i32 {
+    static_assert_simm_bits!(IS8, 8);
+    hexagon_M2_naccii(rx, rs, IS8)
+}
+
+/// `Rx32+=sub(Rt32,Rs32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(sub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_subacc_RR(rx: i32, rt: i32, rs: i32) -> i32 {
+    hexagon_M2_subacc(rx, rt, rs)
+}
+
+/// `Rdd32=vabsdiffh(Rtt32,Rss32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vabsdiffh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsdiffh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_M2_vabsdiffh(rtt, rss)
+}
+
+/// `Rdd32=vabsdiffw(Rtt32,Rss32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vabsdiffw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsdiffw_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_M2_vabsdiffw(rtt, rss)
+}
+
+/// `Rxx32+=vcmpyi(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcmpyiacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vcmac_s0_sat_i(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vcmpyr(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcmpyracc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vcmac_s0_sat_r(rxx, rss, rtt)
+}
+
+/// `Rdd32=vcmpyi(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcmpyi_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vcmpy_s0_sat_i(rss, rtt)
+}
+
+/// `Rdd32=vcmpyr(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcmpyr_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vcmpy_s0_sat_r(rss, rtt)
+}
+
+/// `Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcmpyi_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vcmpy_s1_sat_i(rss, rtt)
+}
+
+/// `Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcmpyr_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vcmpy_s1_sat_r(rss, rtt)
+}
+
+/// `Rxx32+=vdmpy(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpyacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vdmacs_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpyacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vdmacs_s1(rxx, rss, rtt)
+}
+
+/// `Rd32=vdmpy(Rss32,Rtt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vdmpy_PP_rnd_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M2_vdmpyrs_s0(rss, rtt)
+}
+
+/// `Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vdmpy_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M2_vdmpyrs_s1(rss, rtt)
+}
+
+/// `Rdd32=vdmpy(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpy_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vdmpys_s0(rss, rtt)
+}
+
+/// `Rdd32=vdmpy(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpy_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vdmpys_s1(rss, rtt)
+}
+
+/// `Rxx32+=vmpyh(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmac2(rxx, rs, rt)
+}
+
+/// `Rxx32+=vmpyeh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vmac2es(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyeh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vmac2es_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vmac2es_s1(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vmpyh(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmac2s_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=vmpyh(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmac2s_s1(rxx, rs, rt)
+}
+
+/// `Rxx32+=vmpyhsu(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyhsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhsuacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmac2su_s0(rxx, rs, rt)
+}
+
+/// `Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyhsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhsuacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmac2su_s1(rxx, rs, rt)
+}
+
+/// `Rdd32=vmpyeh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyeh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vmpy2es_s0(rss, rtt)
+}
+
+/// `Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyeh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vmpy2es_s1(rss, rtt)
+}
+
+/// `Rdd32=vmpyh(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyh_RR_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmpy2s_s0(rs, rt)
+}
+
+/// `Rd32=vmpyh(Rs32,Rt32):rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vmpyh_RR_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_vmpy2s_s0pack(rs, rt)
+}
+
+/// `Rdd32=vmpyh(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyh_RR_s1_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmpy2s_s1(rs, rt)
+}
+
+/// `Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vmpyh_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_M2_vmpy2s_s1pack(rs, rt)
+}
+
+/// `Rdd32=vmpyhsu(Rs32,Rt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyhsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhsu_RR_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmpy2su_s0(rs, rt)
+}
+
+/// `Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpyhsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpyhsu_RR_s1_sat(rs: i32, rt: i32) -> i64 {
+    hexagon_M2_vmpy2su_s1(rs, rt)
+}
+
+/// `Rd32=vraddh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vraddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vraddh_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_M2_vraddh(rss, rtt)
+}
+
+/// `Rd32=vradduh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vradduh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vradduh_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_M2_vradduh(rss, rtt)
+}
+
+/// `Rxx32+=vrcmpyi(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyiacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmaci_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vrcmpyi(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyiacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmaci_s0c(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vrcmpyr(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyracc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmacr_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vrcmpyr(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyracc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmacr_s0c(rxx, rss, rtt)
+}
+
+/// `Rdd32=vrcmpyi(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyi_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmpyi_s0(rss, rtt)
+}
+
+/// `Rdd32=vrcmpyi(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyi_PP_conj(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmpyi_s0c(rss, rtt)
+}
+
+/// `Rdd32=vrcmpyr(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyr_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmpyr_s0(rss, rtt)
+}
+
+/// `Rdd32=vrcmpyr(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpyr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpyr_PP_conj(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrcmpyr_s0c(rss, rtt)
+}
+
+/// `Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpys))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpysacc_PR_s1_sat(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_M2_vrcmpys_acc_s1(rxx, rss, rt)
+}
+
+/// `Rdd32=vrcmpys(Rss32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpys))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcmpys_PR_s1_sat(rss: i64, rt: i32) -> i64 {
+    hexagon_M2_vrcmpys_s1(rss, rt)
+}
+
+/// `Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcmpys))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vrcmpys_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
+    hexagon_M2_vrcmpys_s1rp(rss, rt)
+}
+
+/// `Rxx32+=vrmpyh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpyhacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrmac_s0(rxx, rss, rtt)
+}
+
+/// `Rdd32=vrmpyh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpyh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M2_vrmpy_s0(rss, rtt)
+}
+
+/// `Rx32^=xor(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_xorxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_xor_xacc(rx, rs, rt)
+}
+
+/// `Rx32&=and(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_and_and(rx, rs, rt)
+}
+
+/// `Rx32&=and(Rs32,~Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andand_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_and_andn(rx, rs, rt)
+}
+
+/// `Rx32&=or(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_orand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_and_or(rx, rs, rt)
+}
+
+/// `Rx32&=xor(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_xorand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_and_xor(rx, rs, rt)
+}
+
+/// `Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyiwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyiwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
+    hexagon_M4_cmpyi_wh(rss, rt)
+}
+
+/// `Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyiwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
+    hexagon_M4_cmpyi_whc(rss, rt)
+}
+
+/// `Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyrwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyrwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
+    hexagon_M4_cmpyr_wh(rss, rt)
+}
+
+/// `Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cmpyrwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
+    hexagon_M4_cmpyr_whc(rss, rt)
+}
+
+/// `Rx32+=mpy(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyacc_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_mac_up_s1_sat(rx, rs, rt)
+}
+
+/// `Rd32=add(#u6,mpyi(Rs32,#U6))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(add, IU6 = 0, IU6_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_mpyi_IRI<const IU6: u32, const IU6_2: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU6, 6);
+    static_assert_uimm_bits!(IU6_2, 6);
+    hexagon_M4_mpyri_addi(IU6 as i32, rs, IU6_2 as i32)
+}
+
+/// `Rd32=add(Ru32,mpyi(Rs32,#u6))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(add, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_mpyi_RRI<const IU6: u32>(ru: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_M4_mpyri_addr(ru, rs, IU6 as i32)
+}
+
+/// `Rd32=add(Ru32,mpyi(#u6:2,Rs32))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(add, IU6_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_mpyi_RIR<const IU6_2: u32>(ru: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU6_2, 6);
+    hexagon_M4_mpyri_addr_u2(ru, IU6_2 as i32, rs)
+}
+
+/// `Rd32=add(#u6,mpyi(Rs32,Rt32))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(add, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_mpyi_IRR<const IU6: u32>(rs: i32, rt: i32) -> i32 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_M4_mpyrr_addi(IU6 as i32, rs, rt)
+}
+
+/// `Ry32=add(Ru32,mpyi(Ry32,Rs32))`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(add))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_mpyi_RRR(ru: i32, ry: i32, rs: i32) -> i32 {
+    hexagon_M4_mpyrr_addr(ru, ry, rs)
+}
+
+/// `Rx32-=mpy(Rs32,Rt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(mpy))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpynac_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_nac_up_s1_sat(rx, rs, rt)
+}
+
+/// `Rx32|=and(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_or_and(rx, rs, rt)
+}
+
+/// `Rx32|=and(Rs32,~Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andor_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_or_andn(rx, rs, rt)
+}
+
+/// `Rx32|=or(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_oror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_or_or(rx, rs, rt)
+}
+
+/// `Rx32|=xor(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_xoror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_or_xor(rx, rs, rt)
+}
+
+/// `Rdd32=pmpyw(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(pmpyw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_pmpyw_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M4_pmpyw(rs, rt)
+}
+
+/// `Rxx32^=pmpyw(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(pmpyw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_pmpywxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M4_pmpyw_acc(rxx, rs, rt)
+}
+
+/// `Rdd32=vpmpyh(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vpmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vpmpyh_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M4_vpmpyh(rs, rt)
+}
+
+/// `Rxx32^=vpmpyh(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vpmpyh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vpmpyhxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M4_vpmpyh_acc(rxx, rs, rt)
+}
+
+/// `Rxx32+=vrmpyweh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpywehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyeh_acc_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vrmpyweh(Rss32,Rtt32):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpywehacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyeh_acc_s1(rxx, rss, rtt)
+}
+
+/// `Rdd32=vrmpyweh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpyweh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyeh_s0(rss, rtt)
+}
+
+/// `Rdd32=vrmpyweh(Rss32,Rtt32):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpyweh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpyweh_PP_s1(rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyeh_s1(rss, rtt)
+}
+
+/// `Rxx32+=vrmpywoh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpywohacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyoh_acc_s0(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vrmpywoh(Rss32,Rtt32):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpywohacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyoh_acc_s1(rxx, rss, rtt)
+}
+
+/// `Rdd32=vrmpywoh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpywoh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyoh_s0(rss, rtt)
+}
+
+/// `Rdd32=vrmpywoh(Rss32,Rtt32):<<1`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpywoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpywoh_PP_s1(rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_vrmpyoh_s1(rss, rtt)
+}
+
+/// `Rx32^=and(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_xor_and(rx, rs, rt)
+}
+
+/// `Rx32^=and(Rs32,~Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(and))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andxacc_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_xor_andn(rx, rs, rt)
+}
+
+/// `Rx32^=or(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(or))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_orxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M4_xor_or(rx, rs, rt)
+}
+
+/// `Rxx32^=xor(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(xor))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_xorxacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M4_xor_xacc(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vdmpybsu(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpybsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpybsuacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M5_vdmacbsu(rxx, rss, rtt)
+}
+
+/// `Rdd32=vdmpybsu(Rss32,Rtt32):sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vdmpybsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpybsu_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_M5_vdmpybsu(rss, rtt)
+}
+
+/// `Rxx32+=vmpybsu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpybsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpybsuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M5_vmacbsu(rxx, rs, rt)
+}
+
+/// `Rxx32+=vmpybu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpybu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpybuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
+    hexagon_M5_vmacbuu(rxx, rs, rt)
+}
+
+/// `Rdd32=vmpybsu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpybsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpybsu_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M5_vmpybsu(rs, rt)
+}
+
+/// `Rdd32=vmpybu(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vmpybu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vmpybu_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_M5_vmpybuu(rs, rt)
+}
+
+/// `Rxx32+=vrmpybsu(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpybsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpybsuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M5_vrmacbsu(rxx, rss, rtt)
+}
+
+/// `Rxx32+=vrmpybu(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpybu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpybuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M5_vrmacbuu(rxx, rss, rtt)
+}
+
+/// `Rdd32=vrmpybsu(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpybsu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpybsu_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M5_vrmpybsu(rss, rtt)
+}
+
+/// `Rdd32=vrmpybu(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrmpybu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrmpybu_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M5_vrmpybuu(rss, rtt)
+}
+
+/// `Rd32=addasl(Rt32,Rs32,#u3)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(addasl, IU3 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_addasl_RRI<const IU3: u32>(rt: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU3, 3);
+    hexagon_S2_addasl_rrri(rt, rs, IU3 as i32)
+}
+
+/// `Rdd32=asl(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asl_PI<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asl_i_p(rss, IU6 as i32)
+}
+
+/// `Rxx32+=asl(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asl_i_p_acc(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32&=asl(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asland_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asl_i_p_and(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32-=asl(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asl_i_p_nac(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32|=asl(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslor_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asl_i_p_or(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32^=asl(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asl_i_p_xacc(rxx, rss, IU6 as i32)
+}
+
+/// `Rd32=asl(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asl_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r(rs, IU5 as i32)
+}
+
+/// `Rx32+=asl(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r_acc(rx, rs, IU5 as i32)
+}
+
+/// `Rx32&=asl(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asland_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r_and(rx, rs, IU5 as i32)
+}
+
+/// `Rx32-=asl(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r_nac(rx, rs, IU5 as i32)
+}
+
+/// `Rx32|=asl(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslor_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r_or(rx, rs, IU5 as i32)
+}
+
+/// `Rd32=asl(Rs32,#u5):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asl_RI_sat<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r_sat(rs, IU5 as i32)
+}
+
+/// `Rx32^=asl(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_r_xacc(rx, rs, IU5 as i32)
+}
+
+/// `Rdd32=vaslh(Rss32,#u4)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vaslh, IU4 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaslh_PI<const IU4: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU4, 4);
+    hexagon_S2_asl_i_vh(rss, IU4 as i32)
+}
+
+/// `Rdd32=vaslw(Rss32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vaslw, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaslw_PI<const IU5: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asl_i_vw(rss, IU5 as i32)
+}
+
+/// `Rdd32=asl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asl_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_p(rss, rt)
+}
+
+/// `Rxx32+=asl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_p_acc(rxx, rss, rt)
+}
+
+/// `Rxx32&=asl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asland_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_p_and(rxx, rss, rt)
+}
+
+/// `Rxx32-=asl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_p_nac(rxx, rss, rt)
+}
+
+/// `Rxx32|=asl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_p_or(rxx, rss, rt)
+}
+
+/// `Rxx32^=asl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_aslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_p_xor(rxx, rss, rt)
+}
+
+/// `Rd32=asl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asl_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asl_r_r(rs, rt)
+}
+
+/// `Rx32+=asl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asl_r_r_acc(rx, rs, rt)
+}
+
+/// `Rx32&=asl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asland_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asl_r_r_and(rx, rs, rt)
+}
+
+/// `Rx32-=asl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asl_r_r_nac(rx, rs, rt)
+}
+
+/// `Rx32|=asl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_aslor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asl_r_r_or(rx, rs, rt)
+}
+
+/// `Rd32=asl(Rs32,Rt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asl_RR_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asl_r_r_sat(rs, rt)
+}
+
+/// `Rdd32=vaslh(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaslh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaslh_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_vh(rss, rt)
+}
+
+/// `Rdd32=vaslw(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vaslw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vaslw_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asl_r_vw(rss, rt)
+}
+
+/// `Rdd32=asr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asr_PI<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p(rss, IU6 as i32)
+}
+
+/// `Rxx32+=asr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asracc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p_acc(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32&=asr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asrand_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p_and(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32-=asr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asrnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p_nac(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32|=asr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asror_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p_or(rxx, rss, IU6 as i32)
+}
+
+/// `Rdd32=asr(Rss32,#u6):rnd`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asr_PI_rnd<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p_rnd(rss, IU6 as i32)
+}
+
+/// `Rdd32=asrrnd(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asrrnd, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asrrnd_PI<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_asr_i_p_rnd_goodsyntax(rss, IU6 as i32)
+}
+
+/// `Rd32=asr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asr_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r(rs, IU5 as i32)
+}
+
+/// `Rx32+=asr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asracc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r_acc(rx, rs, IU5 as i32)
+}
+
+/// `Rx32&=asr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asrand_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r_and(rx, rs, IU5 as i32)
+}
+
+/// `Rx32-=asr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asrnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r_nac(rx, rs, IU5 as i32)
+}
+
+/// `Rx32|=asr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asror_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r_or(rx, rs, IU5 as i32)
+}
+
+/// `Rd32=asr(Rs32,#u5):rnd`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asr_RI_rnd<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r_rnd(rs, IU5 as i32)
+}
+
+/// `Rd32=asrrnd(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(asrrnd, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asrrnd_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_r_rnd_goodsyntax(rs, IU5 as i32)
+}
+
+/// `Rd32=vasrw(Rss32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vasrw_PI<const IU5: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_svw_trun(rss, IU5 as i32)
+}
+
+/// `Rdd32=vasrh(Rss32,#u4)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vasrh_PI<const IU4: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU4, 4);
+    hexagon_S2_asr_i_vh(rss, IU4 as i32)
+}
+
+/// `Rdd32=vasrw(Rss32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vasrw_PI<const IU5: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_asr_i_vw(rss, IU5 as i32)
+}
+
+/// `Rdd32=asr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asr_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_p(rss, rt)
+}
+
+/// `Rxx32+=asr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_p_acc(rxx, rss, rt)
+}
+
+/// `Rxx32&=asr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_p_and(rxx, rss, rt)
+}
+
+/// `Rxx32-=asr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_p_nac(rxx, rss, rt)
+}
+
+/// `Rxx32|=asr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asror_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_p_or(rxx, rss, rt)
+}
+
+/// `Rxx32^=asr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_asrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_p_xor(rxx, rss, rt)
+}
+
+/// `Rd32=asr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asr_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asr_r_r(rs, rt)
+}
+
+/// `Rx32+=asr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asracc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asr_r_r_acc(rx, rs, rt)
+}
+
+/// `Rx32&=asr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asrand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asr_r_r_and(rx, rs, rt)
+}
+
+/// `Rx32-=asr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asr_r_r_nac(rx, rs, rt)
+}
+
+/// `Rx32|=asr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asr_r_r_or(rx, rs, rt)
+}
+
+/// `Rd32=asr(Rs32,Rt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(asr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_asr_RR_sat(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_asr_r_r_sat(rs, rt)
+}
+
+/// `Rd32=vasrw(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vasrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vasrw_PR(rss: i64, rt: i32) -> i32 {
+    hexagon_S2_asr_r_svw_trun(rss, rt)
+}
+
+/// `Rdd32=vasrh(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vasrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vasrh_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_vh(rss, rt)
+}
+
+/// `Rdd32=vasrw(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vasrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vasrw_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_asr_r_vw(rss, rt)
+}
+
+/// `Rd32=brev(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(brev))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_brev_R(rs: i32) -> i32 {
+    hexagon_S2_brev(rs)
+}
+
+/// `Rdd32=brev(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(brev))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_brev_P(rss: i64) -> i64 {
+    hexagon_S2_brevp(rss)
+}
+
+/// `Rd32=cl0(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cl0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cl0_R(rs: i32) -> i32 {
+    hexagon_S2_cl0(rs)
+}
+
+/// `Rd32=cl0(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cl0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cl0_P(rss: i64) -> i32 {
+    hexagon_S2_cl0p(rss)
+}
+
+/// `Rd32=cl1(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cl1))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cl1_R(rs: i32) -> i32 {
+    hexagon_S2_cl1(rs)
+}
+
+/// `Rd32=cl1(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cl1))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cl1_P(rss: i64) -> i32 {
+    hexagon_S2_cl1p(rss)
+}
+
+/// `Rd32=clb(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(clb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_clb_R(rs: i32) -> i32 {
+    hexagon_S2_clb(rs)
+}
+
+/// `Rd32=normamt(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(normamt))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_normamt_R(rs: i32) -> i32 {
+    hexagon_S2_clbnorm(rs)
+}
+
+/// `Rd32=clb(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(clb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_clb_P(rss: i64) -> i32 {
+    hexagon_S2_clbp(rss)
+}
+
+/// `Rd32=clrbit(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(clrbit, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_clrbit_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_clrbit_i(rs, IU5 as i32)
+}
+
+/// `Rd32=clrbit(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(clrbit))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_clrbit_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_clrbit_r(rs, rt)
+}
+
+/// `Rd32=ct0(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(ct0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_ct0_R(rs: i32) -> i32 {
+    hexagon_S2_ct0(rs)
+}
+
+/// `Rd32=ct0(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(ct0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_ct0_P(rss: i64) -> i32 {
+    hexagon_S2_ct0p(rss)
+}
+
+/// `Rd32=ct1(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(ct1))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_ct1_R(rs: i32) -> i32 {
+    hexagon_S2_ct1(rs)
+}
+
+/// `Rd32=ct1(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(ct1))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_ct1_P(rss: i64) -> i32 {
+    hexagon_S2_ct1p(rss)
+}
+
+/// `Rdd32=deinterleave(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(deinterleave))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_deinterleave_P(rss: i64) -> i64 {
+    hexagon_S2_deinterleave(rss)
+}
+
+/// `Rd32=extractu(Rs32,#u5,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1, 2)]
+#[cfg_attr(test, assert_instr(extractu, IU5 = 0, IU5_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_extractu_RII<const IU5: u32, const IU5_2: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    static_assert_uimm_bits!(IU5_2, 5);
+    hexagon_S2_extractu(rs, IU5 as i32, IU5_2 as i32)
+}
+
+/// `Rd32=extractu(Rs32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(extractu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_extractu_RP(rs: i32, rtt: i64) -> i32 {
+    hexagon_S2_extractu_rp(rs, rtt)
+}
+
+/// `Rdd32=extractu(Rss32,#u6,#U6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1, 2)]
+#[cfg_attr(test, assert_instr(extractu, IU6 = 0, IU6_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_extractu_PII<const IU6: u32, const IU6_2: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    static_assert_uimm_bits!(IU6_2, 6);
+    hexagon_S2_extractup(rss, IU6 as i32, IU6_2 as i32)
+}
+
+/// `Rdd32=extractu(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(extractu))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_extractu_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_extractup_rp(rss, rtt)
+}
+
+/// `Rx32=insert(Rs32,#u5,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2, 3)]
+#[cfg_attr(test, assert_instr(insert, IU5 = 0, IU5_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_insert_RII<const IU5: u32, const IU5_2: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    static_assert_uimm_bits!(IU5_2, 5);
+    hexagon_S2_insert(rx, rs, IU5 as i32, IU5_2 as i32)
+}
+
+/// `Rx32=insert(Rs32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(insert))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_insert_RP(rx: i32, rs: i32, rtt: i64) -> i32 {
+    hexagon_S2_insert_rp(rx, rs, rtt)
+}
+
+/// `Rxx32=insert(Rss32,#u6,#U6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2, 3)]
+#[cfg_attr(test, assert_instr(insert, IU6 = 0, IU6_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_insert_PII<const IU6: u32, const IU6_2: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    static_assert_uimm_bits!(IU6_2, 6);
+    hexagon_S2_insertp(rxx, rss, IU6 as i32, IU6_2 as i32)
+}
+
+/// `Rxx32=insert(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(insert))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_insert_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_insertp_rp(rxx, rss, rtt)
+}
+
+/// `Rdd32=interleave(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(interleave))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_interleave_P(rss: i64) -> i64 {
+    hexagon_S2_interleave(rss)
+}
+
+/// `Rdd32=lfs(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lfs))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lfs_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_lfsp(rss, rtt)
+}
+
+/// `Rdd32=lsl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsl_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_p(rss, rt)
+}
+
+/// `Rxx32+=lsl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_p_acc(rxx, rss, rt)
+}
+
+/// `Rxx32&=lsl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsland_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_p_and(rxx, rss, rt)
+}
+
+/// `Rxx32-=lsl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_p_nac(rxx, rss, rt)
+}
+
+/// `Rxx32|=lsl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_p_or(rxx, rss, rt)
+}
+
+/// `Rxx32^=lsl(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_p_xor(rxx, rss, rt)
+}
+
+/// `Rd32=lsl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsl_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsl_r_r(rs, rt)
+}
+
+/// `Rx32+=lsl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsl_r_r_acc(rx, rs, rt)
+}
+
+/// `Rx32&=lsl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsland_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsl_r_r_and(rx, rs, rt)
+}
+
+/// `Rx32-=lsl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsl_r_r_nac(rx, rs, rt)
+}
+
+/// `Rx32|=lsl(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lslor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsl_r_r_or(rx, rs, rt)
+}
+
+/// `Rdd32=vlslh(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vlslh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vlslh_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_vh(rss, rt)
+}
+
+/// `Rdd32=vlslw(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vlslw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vlslw_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsl_r_vw(rss, rt)
+}
+
+/// `Rdd32=lsr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsr_PI<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_lsr_i_p(rss, IU6 as i32)
+}
+
+/// `Rxx32+=lsr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsracc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_lsr_i_p_acc(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32&=lsr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsrand_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_lsr_i_p_and(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32-=lsr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsrnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_lsr_i_p_nac(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32|=lsr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsror_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_lsr_i_p_or(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32^=lsr(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsrxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S2_lsr_i_p_xacc(rxx, rss, IU6 as i32)
+}
+
+/// `Rd32=lsr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsr_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_r(rs, IU5 as i32)
+}
+
+/// `Rx32+=lsr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsracc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_r_acc(rx, rs, IU5 as i32)
+}
+
+/// `Rx32&=lsr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsrand_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_r_and(rx, rs, IU5 as i32)
+}
+
+/// `Rx32-=lsr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsrnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_r_nac(rx, rs, IU5 as i32)
+}
+
+/// `Rx32|=lsr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsror_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_r_or(rx, rs, IU5 as i32)
+}
+
+/// `Rx32^=lsr(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsrxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_r_xacc(rx, rs, IU5 as i32)
+}
+
+/// `Rdd32=vlsrh(Rss32,#u4)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vlsrh, IU4 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vlsrh_PI<const IU4: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU4, 4);
+    hexagon_S2_lsr_i_vh(rss, IU4 as i32)
+}
+
+/// `Rdd32=vlsrw(Rss32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vlsrw, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vlsrw_PI<const IU5: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_lsr_i_vw(rss, IU5 as i32)
+}
+
+/// `Rdd32=lsr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsr_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_p(rss, rt)
+}
+
+/// `Rxx32+=lsr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_p_acc(rxx, rss, rt)
+}
+
+/// `Rxx32&=lsr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_p_and(rxx, rss, rt)
+}
+
+/// `Rxx32-=lsr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_p_nac(rxx, rss, rt)
+}
+
+/// `Rxx32|=lsr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsror_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_p_or(rxx, rss, rt)
+}
+
+/// `Rxx32^=lsr(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_lsrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_p_xor(rxx, rss, rt)
+}
+
+/// `Rd32=lsr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsr_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsr_r_r(rs, rt)
+}
+
+/// `Rx32+=lsr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsracc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsr_r_r_acc(rx, rs, rt)
+}
+
+/// `Rx32&=lsr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsrand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsr_r_r_and(rx, rs, rt)
+}
+
+/// `Rx32-=lsr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsr_r_r_nac(rx, rs, rt)
+}
+
+/// `Rx32|=lsr(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(lsr))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_S2_lsr_r_r_or(rx, rs, rt)
+}
+
+/// `Rdd32=vlsrh(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vlsrh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vlsrh_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_vh(rss, rt)
+}
+
+/// `Rdd32=vlsrw(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vlsrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vlsrw_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_lsr_r_vw(rss, rt)
+}
+
+/// `Rdd32=packhl(Rs32,Rt32)`
+///
+/// Instruction Type: ALU32_3op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(packhl))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_packhl_RR(rs: i32, rt: i32) -> i64 {
+    hexagon_S2_packhl(rs, rt)
+}
+
+/// `Rd32=parity(Rss32,Rtt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(parity))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_parity_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_S2_parityp(rss, rtt)
+}
+
+/// `Rd32=setbit(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(setbit, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_setbit_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_setbit_i(rs, IU5 as i32)
+}
+
+/// `Rd32=setbit(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(setbit))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_setbit_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_setbit_r(rs, rt)
+}
+
+/// `Rdd32=shuffeb(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(shuffeb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_shuffeb_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_shuffeb(rss, rtt)
+}
+
+/// `Rdd32=shuffeh(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(shuffeh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_shuffeh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_shuffeh(rss, rtt)
+}
+
+/// `Rdd32=shuffob(Rtt32,Rss32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(shuffob))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_shuffob_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_S2_shuffob(rtt, rss)
+}
+
+/// `Rdd32=shuffoh(Rtt32,Rss32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(shuffoh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_shuffoh_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_S2_shuffoh(rtt, rss)
+}
+
+/// `Rd32=vsathb(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsathb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsathb_R(rs: i32) -> i32 {
+    hexagon_S2_svsathb(rs)
+}
+
+/// `Rd32=vsathub(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsathub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsathub_R(rs: i32) -> i32 {
+    hexagon_S2_svsathub(rs)
+}
+
+/// `Rx32=tableidxb(Rs32,#u4,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(2, 3)]
+#[cfg_attr(test, assert_instr(tableidxb, IU4 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_tableidxb_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU4, 4);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_tableidxb_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
+}
+
+/// `Rx32=tableidxd(Rs32,#u4,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(2, 3)]
+#[cfg_attr(test, assert_instr(tableidxd, IU4 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_tableidxd_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU4, 4);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_tableidxd_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
+}
+
+/// `Rx32=tableidxh(Rs32,#u4,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(2, 3)]
+#[cfg_attr(test, assert_instr(tableidxh, IU4 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_tableidxh_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU4, 4);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_tableidxh_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
+}
+
+/// `Rx32=tableidxw(Rs32,#u4,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(2, 3)]
+#[cfg_attr(test, assert_instr(tableidxw, IU4 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_tableidxw_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU4, 4);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_tableidxw_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
+}
+
+/// `Rd32=togglebit(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(togglebit, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_togglebit_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_togglebit_i(rs, IU5 as i32)
+}
+
+/// `Rd32=togglebit(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(togglebit))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_togglebit_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_togglebit_r(rs, rt)
+}
+
+/// `Pd4=tstbit(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(tstbit, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_tstbit_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S2_tstbit_i(rs, IU5 as i32)
+}
+
+/// `Pd4=tstbit(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(tstbit))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_tstbit_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S2_tstbit_r(rs, rt)
+}
+
+/// `Rdd32=valignb(Rtt32,Rss32,#u3)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(valignb, IU3 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_valignb_PPI<const IU3: u32>(rtt: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU3, 3);
+    hexagon_S2_valignib(rtt, rss, IU3 as i32)
+}
+
+/// `Rdd32=valignb(Rtt32,Rss32,Pu4)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(valignb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_valignb_PPp(rtt: i64, rss: i64, pu: i32) -> i64 {
+    hexagon_S2_valignrb(rtt, rss, pu)
+}
+
+/// `Rdd32=vcnegh(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcnegh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcnegh_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_vcnegh(rss, rt)
+}
+
+/// `Rdd32=vcrotate(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vcrotate))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vcrotate_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_S2_vcrotate(rss, rt)
+}
+
+/// `Rxx32+=vrcnegh(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrcnegh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcneghacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
+    hexagon_S2_vrcnegh(rxx, rss, rt)
+}
+
+/// `Rd32=vrndwh(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrndwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vrndwh_P(rss: i64) -> i32 {
+    hexagon_S2_vrndpackwh(rss)
+}
+
+/// `Rd32=vrndwh(Rss32):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vrndwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vrndwh_P_sat(rss: i64) -> i32 {
+    hexagon_S2_vrndpackwhs(rss)
+}
+
+/// `Rd32=vsathb(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsathb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsathb_P(rss: i64) -> i32 {
+    hexagon_S2_vsathb(rss)
+}
+
+/// `Rdd32=vsathb(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsathb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsathb_P(rss: i64) -> i64 {
+    hexagon_S2_vsathb_nopack(rss)
+}
+
+/// `Rd32=vsathub(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsathub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsathub_P(rss: i64) -> i32 {
+    hexagon_S2_vsathub(rss)
+}
+
+/// `Rdd32=vsathub(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsathub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsathub_P(rss: i64) -> i64 {
+    hexagon_S2_vsathub_nopack(rss)
+}
+
+/// `Rd32=vsatwh(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsatwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsatwh_P(rss: i64) -> i32 {
+    hexagon_S2_vsatwh(rss)
+}
+
+/// `Rdd32=vsatwh(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsatwh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsatwh_P(rss: i64) -> i64 {
+    hexagon_S2_vsatwh_nopack(rss)
+}
+
+/// `Rd32=vsatwuh(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsatwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsatwuh_P(rss: i64) -> i32 {
+    hexagon_S2_vsatwuh(rss)
+}
+
+/// `Rdd32=vsatwuh(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsatwuh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsatwuh_P(rss: i64) -> i64 {
+    hexagon_S2_vsatwuh_nopack(rss)
+}
+
+/// `Rd32=vsplatb(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsplatb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vsplatb_R(rs: i32) -> i32 {
+    hexagon_S2_vsplatrb(rs)
+}
+
+/// `Rdd32=vsplath(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsplath))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsplath_R(rs: i32) -> i64 {
+    hexagon_S2_vsplatrh(rs)
+}
+
+/// `Rdd32=vspliceb(Rss32,Rtt32,#u3)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(vspliceb, IU3 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vspliceb_PPI<const IU3: u32>(rss: i64, rtt: i64) -> i64 {
+    static_assert_uimm_bits!(IU3, 3);
+    hexagon_S2_vspliceib(rss, rtt, IU3 as i32)
+}
+
+/// `Rdd32=vspliceb(Rss32,Rtt32,Pu4)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vspliceb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vspliceb_PPp(rss: i64, rtt: i64, pu: i32) -> i64 {
+    hexagon_S2_vsplicerb(rss, rtt, pu)
+}
+
+/// `Rdd32=vsxtbh(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsxtbh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsxtbh_R(rs: i32) -> i64 {
+    hexagon_S2_vsxtbh(rs)
+}
+
+/// `Rdd32=vsxthw(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vsxthw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsxthw_R(rs: i32) -> i64 {
+    hexagon_S2_vsxthw(rs)
+}
+
+/// `Rd32=vtrunehb(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vtrunehb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vtrunehb_P(rss: i64) -> i32 {
+    hexagon_S2_vtrunehb(rss)
+}
+
+/// `Rdd32=vtrunewh(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vtrunewh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vtrunewh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_vtrunewh(rss, rtt)
+}
+
+/// `Rd32=vtrunohb(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vtrunohb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vtrunohb_P(rss: i64) -> i32 {
+    hexagon_S2_vtrunohb(rss)
+}
+
+/// `Rdd32=vtrunowh(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vtrunowh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vtrunowh_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S2_vtrunowh(rss, rtt)
+}
+
+/// `Rdd32=vzxtbh(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vzxtbh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vzxtbh_R(rs: i32) -> i64 {
+    hexagon_S2_vzxtbh(rs)
+}
+
+/// `Rdd32=vzxthw(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vzxthw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vzxthw_R(rs: i32) -> i64 {
+    hexagon_S2_vzxthw(rs)
+}
+
+/// `Rd32=add(Rs32,add(Ru32,#s6))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(add, IS6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_add_RRI<const IS6: i32>(rs: i32, ru: i32) -> i32 {
+    static_assert_simm_bits!(IS6, 6);
+    hexagon_S4_addaddi(rs, ru, IS6)
+}
+
+/// `Rx32=add(#u8,asl(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_addi_asl_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rx32=add(#u8,lsr(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_addi_lsr_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rx32=and(#u8,asl(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_and_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_andi_asl_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rx32=and(#u8,lsr(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_and_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_andi_lsr_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rd32=add(clb(Rs32),#s6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(add, IS6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_clb_RI<const IS6: i32>(rs: i32) -> i32 {
+    static_assert_simm_bits!(IS6, 6);
+    hexagon_S4_clbaddi(rs, IS6)
+}
+
+/// `Rd32=add(clb(Rss32),#s6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(add, IS6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_clb_PI<const IS6: i32>(rss: i64) -> i32 {
+    static_assert_simm_bits!(IS6, 6);
+    hexagon_S4_clbpaddi(rss, IS6)
+}
+
+/// `Rd32=normamt(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(normamt))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_normamt_P(rss: i64) -> i32 {
+    hexagon_S4_clbpnorm(rss)
+}
+
+/// `Rd32=extract(Rs32,#u5,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1, 2)]
+#[cfg_attr(test, assert_instr(extract, IU5 = 0, IU5_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_extract_RII<const IU5: u32, const IU5_2: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    static_assert_uimm_bits!(IU5_2, 5);
+    hexagon_S4_extract(rs, IU5 as i32, IU5_2 as i32)
+}
+
+/// `Rd32=extract(Rs32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(extract))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_extract_RP(rs: i32, rtt: i64) -> i32 {
+    hexagon_S4_extract_rp(rs, rtt)
+}
+
+/// `Rdd32=extract(Rss32,#u6,#U6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1, 2)]
+#[cfg_attr(test, assert_instr(extract, IU6 = 0, IU6_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_extract_PII<const IU6: u32, const IU6_2: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    static_assert_uimm_bits!(IU6_2, 6);
+    hexagon_S4_extractp(rss, IU6 as i32, IU6_2 as i32)
+}
+
+/// `Rdd32=extract(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(extract))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_extract_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_extractp_rp(rss, rtt)
+}
+
+/// `Rd32=lsl(#s6,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+#[cfg_attr(test, assert_instr(lsl, IS6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_lsl_IR<const IS6: i32>(rt: i32) -> i32 {
+    static_assert_simm_bits!(IS6, 6);
+    hexagon_S4_lsli(IS6, rt)
+}
+
+/// `Pd4=!tstbit(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_tstbit_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_ntstbit_i(rs, IU5 as i32)
+}
+
+/// `Pd4=!tstbit(Rs32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_tstbit_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S4_ntstbit_r(rs, rt)
+}
+
+/// `Rx32|=and(Rs32,#s10)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(and, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_andor_RI<const IS10: i32>(rx: i32, rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_S4_or_andi(rx, rs, IS10)
+}
+
+/// `Rx32=or(Ru32,and(Rx32,#s10))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(or, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_or_and_RRI<const IS10: i32>(ru: i32, rx: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_S4_or_andix(ru, rx, IS10)
+}
+
+/// `Rx32|=or(Rs32,#s10)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(or, IS10 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_oror_RI<const IS10: i32>(rx: i32, rs: i32) -> i32 {
+    static_assert_simm_bits!(IS10, 10);
+    hexagon_S4_or_ori(rx, rs, IS10)
+}
+
+/// `Rx32=or(#u8,asl(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_or_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_ori_asl_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rx32=or(#u8,lsr(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_or_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_ori_lsr_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rd32=parity(Rs32,Rt32)`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(parity))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_parity_RR(rs: i32, rt: i32) -> i32 {
+    hexagon_S4_parity(rs, rt)
+}
+
+/// `Rd32=add(Rs32,sub(#s6,Ru32))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(add, IS6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_add_sub_RIR<const IS6: i32>(rs: i32, ru: i32) -> i32 {
+    static_assert_simm_bits!(IS6, 6);
+    hexagon_S4_subaddi(rs, IS6, ru)
+}
+
+/// `Rx32=sub(#u8,asl(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_subi_asl_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rx32=sub(#u8,lsr(Rx32,#U5))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(0, 2)]
+#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_sub_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
+    static_assert_uimm_bits!(IU8, 8);
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S4_subi_lsr_ri(IU8 as i32, rx, IU5 as i32)
+}
+
+/// `Rdd32=vrcrotate(Rss32,Rt32,#u2)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcrotate_PRI<const IU2: u32>(rss: i64, rt: i32) -> i64 {
+    static_assert_uimm_bits!(IU2, 2);
+    hexagon_S4_vrcrotate(rss, rt, IU2 as i32)
+}
+
+/// `Rxx32+=vrcrotate(Rss32,Rt32,#u2)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(3)]
+#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vrcrotateacc_PRI<const IU2: u32>(rxx: i64, rss: i64, rt: i32) -> i64 {
+    static_assert_uimm_bits!(IU2, 2);
+    hexagon_S4_vrcrotate_acc(rxx, rss, rt, IU2 as i32)
+}
+
+/// `Rdd32=vxaddsubh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vxaddsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vxaddsubh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_vxaddsubh(rss, rtt)
+}
+
+/// `Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vxaddsubh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vxaddsubh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_vxaddsubhr(rss, rtt)
+}
+
+/// `Rdd32=vxaddsubw(Rss32,Rtt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vxaddsubw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vxaddsubw_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_vxaddsubw(rss, rtt)
+}
+
+/// `Rdd32=vxsubaddh(Rss32,Rtt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vxsubaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vxsubaddh_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_vxsubaddh(rss, rtt)
+}
+
+/// `Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vxsubaddh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vxsubaddh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_vxsubaddhr(rss, rtt)
+}
+
+/// `Rdd32=vxsubaddw(Rss32,Rtt32):sat`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(vxsubaddw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vxsubaddw_PP_sat(rss: i64, rtt: i64) -> i64 {
+    hexagon_S4_vxsubaddw(rss, rtt)
+}
+
+/// `Rd32=vasrhub(Rss32,#u4):rnd:sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vasrhub_PI_rnd_sat<const IU4: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU4, 4);
+    hexagon_S5_asrhub_rnd_sat_goodsyntax(rss, IU4 as i32)
+}
+
+/// `Rd32=vasrhub(Rss32,#u4):sat`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_vasrhub_PI_sat<const IU4: u32>(rss: i64) -> i32 {
+    static_assert_uimm_bits!(IU4, 4);
+    hexagon_S5_asrhub_sat(rss, IU4 as i32)
+}
+
+/// `Rd32=popcount(Rss32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+#[inline(always)]
+#[cfg_attr(test, assert_instr(popcount))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_popcount_P(rss: i64) -> i32 {
+    hexagon_S5_popcountp(rss)
+}
+
+/// `Rdd32=vasrh(Rss32,#u4):rnd`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vasrh_PI_rnd<const IU4: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU4, 4);
+    hexagon_S5_vasrhrnd_goodsyntax(rss, IU4 as i32)
+}
+
+/// `dccleana(Rs32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dccleana))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dccleana_A(rs: i32) {
+    hexagon_Y2_dccleana(rs)
+}
+
+/// `dccleaninva(Rs32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dccleaninva))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dccleaninva_A(rs: i32) {
+    hexagon_Y2_dccleaninva(rs)
+}
+
+/// `dcfetch(Rs32)`
+///
+/// Instruction Type: MAPPING
+/// Execution Slots: SLOT0123
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dcfetch))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dcfetch_A(rs: i32) {
+    hexagon_Y2_dcfetch(rs)
+}
+
+/// `dcinva(Rs32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dcinva))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dcinva_A(rs: i32) {
+    hexagon_Y2_dcinva(rs)
+}
+
+/// `dczeroa(Rs32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(test, assert_instr(dczeroa))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dczeroa_A(rs: i32) {
+    hexagon_Y2_dczeroa(rs)
+}
+
+/// `l2fetch(Rs32,Rt32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(test, assert_instr(l2fetch))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_l2fetch_AR(rs: i32, rt: i32) {
+    hexagon_Y4_l2fetch(rs, rt)
+}
+
+/// `l2fetch(Rs32,Rtt32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+#[inline(always)]
+#[cfg_attr(test, assert_instr(l2fetch))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_l2fetch_AP(rs: i32, rtt: i64) {
+    hexagon_Y5_l2fetch(rs, rtt)
+}
+
+/// `Rdd32=rol(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_rol_PI<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S6_rol_i_p(rss, IU6 as i32)
+}
+
+/// `Rxx32+=rol(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_rolacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S6_rol_i_p_acc(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32&=rol(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_roland_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S6_rol_i_p_and(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32-=rol(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_rolnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S6_rol_i_p_nac(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32|=rol(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_rolor_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S6_rol_i_p_or(rxx, rss, IU6 as i32)
+}
+
+/// `Rxx32^=rol(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_rolxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_S6_rol_i_p_xacc(rxx, rss, IU6 as i32)
+}
+
+/// `Rd32=rol(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_rol_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S6_rol_i_r(rs, IU5 as i32)
+}
+
+/// `Rx32+=rol(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_rolacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S6_rol_i_r_acc(rx, rs, IU5 as i32)
+}
+
+/// `Rx32&=rol(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_roland_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S6_rol_i_r_and(rx, rs, IU5 as i32)
+}
+
+/// `Rx32-=rol(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_rolnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S6_rol_i_r_nac(rx, rs, IU5 as i32)
+}
+
+/// `Rx32|=rol(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_rolor_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S6_rol_i_r_or(rx, rs, IU5 as i32)
+}
+
+/// `Rx32^=rol(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V60
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
+#[rustc_legacy_const_generics(2)]
+#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_rolxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_S6_rol_i_r_xacc(rx, rs, IU5 as i32)
+}
+
+/// `Rdd32=vabsdiffb(Rtt32,Rss32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V62
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
+#[cfg_attr(test, assert_instr(vabsdiffb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsdiffb_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_M6_vabsdiffb(rtt, rss)
+}
+
+/// `Rdd32=vabsdiffub(Rtt32,Rss32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V62
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
+#[cfg_attr(test, assert_instr(vabsdiffub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vabsdiffub_PP(rtt: i64, rss: i64) -> i64 {
+    hexagon_M6_vabsdiffub(rtt, rss)
+}
+
+/// `Rdd32=vsplatb(Rs32)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V62
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
+#[cfg_attr(test, assert_instr(vsplatb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vsplatb_R(rs: i32) -> i64 {
+    hexagon_S6_vsplatrbp(rs)
+}
+
+/// `Rdd32=vtrunehb(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+/// Requires: V62
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
+#[cfg_attr(test, assert_instr(vtrunehb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vtrunehb_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S6_vtrunehb_ppp(rss, rtt)
+}
+
+/// `Rdd32=vtrunohb(Rss32,Rtt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+/// Requires: V62
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
+#[cfg_attr(test, assert_instr(vtrunohb))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vtrunohb_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_S6_vtrunohb_ppp(rss, rtt)
+}
+
+/// `Pd4=!any8(vcmpb.eq(Rss32,Rtt32))`
+///
+/// Instruction Type: ALU64
+/// Execution Slots: SLOT23
+/// Requires: V65
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v65"))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_p_not_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
+    hexagon_A6_vcmpbeq_notany(rss, rtt)
+}
+
+/// `Rdd32=dfadd(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V66
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
+#[cfg_attr(test, assert_instr(dfadd))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfadd_PP(rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfadd(rss, rtt)
+}
+
+/// `Rdd32=dfsub(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V66
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
+#[cfg_attr(test, assert_instr(dfsub))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfsub_PP(rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfsub(rss, rtt)
+}
+
+/// `Rx32-=mpyi(Rs32,Rt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V66
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
+#[cfg_attr(test, assert_instr(mpyi))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mpyinac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
+    hexagon_M2_mnaci(rx, rs, rt)
+}
+
+/// `Rd32=mask(#u5,#U5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V66
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
+#[rustc_legacy_const_generics(0, 1)]
+#[cfg_attr(test, assert_instr(mask, IU5 = 0, IU5_2 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_mask_II<const IU5: u32, const IU5_2: u32>() -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    static_assert_uimm_bits!(IU5_2, 5);
+    hexagon_S2_mask(IU5 as i32, IU5_2 as i32)
+}
+
+/// `Rd32=clip(Rs32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(clip, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_clip_RI<const IU5: u32>(rs: i32) -> i32 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_A7_clip(rs, IU5 as i32)
+}
+
+/// `Rdd32=cround(Rss32,#u6)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(cround, IU6 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cround_PI<const IU6: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU6, 6);
+    hexagon_A7_croundd_ri(rss, IU6 as i32)
+}
+
+/// `Rdd32=cround(Rss32,Rt32)`
+///
+/// Instruction Type: S_3op
+/// Execution Slots: SLOT23
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cround))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cround_PR(rss: i64, rt: i32) -> i64 {
+    hexagon_A7_croundd_rr(rss, rt)
+}
+
+/// `Rdd32=vclip(Rss32,#u5)`
+///
+/// Instruction Type: S_2op
+/// Execution Slots: SLOT23
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(vclip, IU5 = 0))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vclip_PI<const IU5: u32>(rss: i64) -> i64 {
+    static_assert_uimm_bits!(IU5, 5);
+    hexagon_A7_vclip(rss, IU5 as i32)
+}
+
+/// `Rdd32=dfmax(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V67
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
+#[cfg_attr(test, assert_instr(dfmax))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmax_PP(rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfmax(rss, rtt)
+}
+
+/// `Rdd32=dfmin(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V67
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
+#[cfg_attr(test, assert_instr(dfmin))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmin_PP(rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfmin(rss, rtt)
+}
+
+/// `Rdd32=dfmpyfix(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V67
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
+#[cfg_attr(test, assert_instr(dfmpyfix))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmpyfix_PP(rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfmpyfix(rss, rtt)
+}
+
+/// `Rxx32+=dfmpyhh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V67
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
+#[cfg_attr(test, assert_instr(dfmpyhh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmpyhhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfmpyhh(rxx, rss, rtt)
+}
+
+/// `Rxx32+=dfmpylh(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V67
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
+#[cfg_attr(test, assert_instr(dfmpylh))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmpylhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfmpylh(rxx, rss, rtt)
+}
+
+/// `Rdd32=dfmpyll(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT23
+/// Requires: V67
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
+#[cfg_attr(test, assert_instr(dfmpyll))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_dfmpyll_PP(rss: f64, rtt: f64) -> f64 {
+    hexagon_F2_dfmpyll(rss, rtt)
+}
+
+/// `Rdd32=cmpyiw(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyiw_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyiw(rss, rtt)
+}
+
+/// `Rxx32+=cmpyiw(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyiwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyiw_acc(rxx, rss, rtt)
+}
+
+/// `Rdd32=cmpyiw(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyiw_PP_conj(rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyiwc(rss, rtt)
+}
+
+/// `Rxx32+=cmpyiw(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyiwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyiwc_acc(rxx, rss, rtt)
+}
+
+/// `Rdd32=cmpyrw(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyrw_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyrw(rss, rtt)
+}
+
+/// `Rxx32+=cmpyrw(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyrwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyrw_acc(rxx, rss, rtt)
+}
+
+/// `Rdd32=cmpyrw(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyrw_PP_conj(rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyrwc(rss, rtt)
+}
+
+/// `Rxx32+=cmpyrw(Rss32,Rtt32*)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_cmpyrwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_dcmpyrwc_acc(rxx, rss, rtt)
+}
+
+/// `Rdd32=vdmpyw(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(vdmpyw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpyw_PP(rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_vdmpy(rss, rtt)
+}
+
+/// `Rxx32+=vdmpyw(Rss32,Rtt32)`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(vdmpyw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_P_vdmpywacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
+    hexagon_M7_vdmpy_acc(rxx, rss, rtt)
+}
+
+/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyiw_PP_s1_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyiw(rss, rtt)
+}
+
+/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyiw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyiw_rnd(rss, rtt)
+}
+
+/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyiwc(rss, rtt)
+}
+
+/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyiw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyiwc_rnd(rss, rtt)
+}
+
+/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyrw_PP_s1_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyrw(rss, rtt)
+}
+
+/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyrw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyrw_rnd(rss, rtt)
+}
+
+/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyrwc(rss, rtt)
+}
+
+/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat`
+///
+/// Instruction Type: M
+/// Execution Slots: SLOT3
+/// Requires: V67, Audio
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
+#[cfg_attr(test, assert_instr(cmpyrw))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
+    hexagon_M7_wcmpyrwc_rnd(rss, rtt)
+}
+
+/// `dmlink(Rs32,Rt32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+/// Requires: V68
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
+#[cfg_attr(test, assert_instr(dmlink))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dmlink_AA(rs: i32, rt: i32) {
+    hexagon_Y6_dmlink(rs, rt)
+}
+
+/// `Rd32=dmpause`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+/// Requires: V68
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
+#[cfg_attr(test, assert_instr(dmpause))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_dmpause() -> i32 {
+    hexagon_Y6_dmpause()
+}
+
+/// `Rd32=dmpoll`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+/// Requires: V68
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
+#[cfg_attr(test, assert_instr(dmpoll))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_dmpoll() -> i32 {
+    hexagon_Y6_dmpoll()
+}
+
+/// `dmresume(Rs32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+/// Requires: V68
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
+#[cfg_attr(test, assert_instr(dmresume))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dmresume_A(rs: i32) {
+    hexagon_Y6_dmresume(rs)
+}
+
+/// `dmstart(Rs32)`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+/// Requires: V68
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
+#[cfg_attr(test, assert_instr(dmstart))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_dmstart_A(rs: i32) {
+    hexagon_Y6_dmstart(rs)
+}
+
+/// `Rd32=dmwait`
+///
+/// Instruction Type: ST
+/// Execution Slots: SLOT0
+/// Requires: V68
+#[inline(always)]
+#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
+#[cfg_attr(test, assert_instr(dmwait))]
+#[unstable(feature = "stdarch_hexagon", issue = "151523")]
+pub unsafe fn Q6_R_dmwait() -> i32 {
+    hexagon_Y6_dmwait()
+}
diff --git a/crates/stdarch-gen-hexagon-scalar/Cargo.toml b/crates/stdarch-gen-hexagon-scalar/Cargo.toml
new file mode 100644
index 0000000000..04bee944f4
--- /dev/null
+++ b/crates/stdarch-gen-hexagon-scalar/Cargo.toml
@@ -0,0 +1,9 @@
+[package]
+name = "stdarch-gen-hexagon-scalar"
+version = "0.1.0"
+authors = ["The Rust Project Developers"]
+license = "MIT OR Apache-2.0"
+edition = "2021"
+
+[dependencies]
+regex = "1.10"
diff --git a/crates/stdarch-gen-hexagon-scalar/hexagon_protos.h b/crates/stdarch-gen-hexagon-scalar/hexagon_protos.h
new file mode 100644
index 0000000000..2642f3c842
--- /dev/null
+++ b/crates/stdarch-gen-hexagon-scalar/hexagon_protos.h
@@ -0,0 +1,8439 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// Automatically generated file, do not edit!
+//===----------------------------------------------------------------------===//
+
+
+
+#ifndef __HEXAGON_PROTOS_H_
+#define __HEXAGON_PROTOS_H_ 1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=abs(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_abs_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_abs_R __builtin_HEXAGON_A2_abs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=abs(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_abs_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_abs_P __builtin_HEXAGON_A2_absp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=abs(Rs32):sat
+   C Intrinsic Prototype: Word32 Q6_R_abs_R_sat(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_abs_R_sat __builtin_HEXAGON_A2_abssat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_add_RR __builtin_HEXAGON_A2_add
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.h,Rs32.h):<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RhRh_s16 __builtin_HEXAGON_A2_addh_h16_hh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.h,Rs32.l):<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RhRl_s16 __builtin_HEXAGON_A2_addh_h16_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h):<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRh_s16 __builtin_HEXAGON_A2_addh_h16_lh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l):<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRl_s16 __builtin_HEXAGON_A2_addh_h16_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.h,Rs32.h):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RhRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.h,Rs32.l):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RhRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_lh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h)
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRh __builtin_HEXAGON_A2_addh_l16_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l)
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRl __builtin_HEXAGON_A2_addh_l16_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRh_sat __builtin_HEXAGON_A2_addh_l16_sat_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rt32.l,Rs32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_RlRl_sat __builtin_HEXAGON_A2_addh_l16_sat_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rs32,#s16)
+   C Intrinsic Prototype: Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16)
+   Instruction Type:      ALU32_ADDI
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_add_RI __builtin_HEXAGON_A2_addi
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=add(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_add_PP __builtin_HEXAGON_A2_addp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=add(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_add_PP_sat __builtin_HEXAGON_A2_addpsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_add_RR_sat __builtin_HEXAGON_A2_addsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=add(Rs32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_add_RP __builtin_HEXAGON_A2_addsp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=and(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_and_RR __builtin_HEXAGON_A2_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=and(Rs32,#s10)
+   C Intrinsic Prototype: Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_and_RI __builtin_HEXAGON_A2_andir
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=and(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_and_PP __builtin_HEXAGON_A2_andp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=aslh(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_aslh_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_aslh_R __builtin_HEXAGON_A2_aslh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asrh(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_asrh_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_asrh_R __builtin_HEXAGON_A2_asrh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=combine(Rt32.h,Rs32.h)
+   C Intrinsic Prototype: Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_combine_RhRh __builtin_HEXAGON_A2_combine_hh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=combine(Rt32.h,Rs32.l)
+   C Intrinsic Prototype: Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_combine_RhRl __builtin_HEXAGON_A2_combine_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=combine(Rt32.l,Rs32.h)
+   C Intrinsic Prototype: Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_combine_RlRh __builtin_HEXAGON_A2_combine_lh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=combine(Rt32.l,Rs32.l)
+   C Intrinsic Prototype: Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_combine_RlRl __builtin_HEXAGON_A2_combine_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=combine(#s8,#S8)
+   C Intrinsic Prototype: Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_combine_II __builtin_HEXAGON_A2_combineii
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=combine(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_combine_RR __builtin_HEXAGON_A2_combinew
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=max(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_max_RR __builtin_HEXAGON_A2_max
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=max(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_max_PP __builtin_HEXAGON_A2_maxp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=maxu(Rs32,Rt32)
+   C Intrinsic Prototype: UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_maxu_RR __builtin_HEXAGON_A2_maxu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=maxu(Rss32,Rtt32)
+   C Intrinsic Prototype: UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_maxu_PP __builtin_HEXAGON_A2_maxup
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=min(Rt32,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_min_RR __builtin_HEXAGON_A2_min
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=min(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_min_PP __builtin_HEXAGON_A2_minp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=minu(Rt32,Rs32)
+   C Intrinsic Prototype: UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_minu_RR __builtin_HEXAGON_A2_minu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=minu(Rtt32,Rss32)
+   C Intrinsic Prototype: UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_minu_PP __builtin_HEXAGON_A2_minup
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=neg(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_neg_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_neg_R __builtin_HEXAGON_A2_neg
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=neg(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_neg_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_neg_P __builtin_HEXAGON_A2_negp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=neg(Rs32):sat
+   C Intrinsic Prototype: Word32 Q6_R_neg_R_sat(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_neg_R_sat __builtin_HEXAGON_A2_negsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=not(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_not_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_not_R __builtin_HEXAGON_A2_not
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=not(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_not_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_not_P __builtin_HEXAGON_A2_notp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=or(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_or_RR __builtin_HEXAGON_A2_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=or(Rs32,#s10)
+   C Intrinsic Prototype: Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_or_RI __builtin_HEXAGON_A2_orir
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=or(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_or_PP __builtin_HEXAGON_A2_orp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=round(Rss32):sat
+   C Intrinsic Prototype: Word32 Q6_R_round_P_sat(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_round_P_sat __builtin_HEXAGON_A2_roundsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sat(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_sat_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sat_P __builtin_HEXAGON_A2_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=satb(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_satb_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_satb_R __builtin_HEXAGON_A2_satb
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sath(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_sath_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sath_R __builtin_HEXAGON_A2_sath
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=satub(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_satub_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_satub_R __builtin_HEXAGON_A2_satub
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=satuh(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_satuh_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_satuh_R __builtin_HEXAGON_A2_satuh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_sub_RR __builtin_HEXAGON_A2_sub
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.h):<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RhRh_s16 __builtin_HEXAGON_A2_subh_h16_hh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.l):<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RhRl_s16 __builtin_HEXAGON_A2_subh_h16_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h):<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRh_s16 __builtin_HEXAGON_A2_subh_h16_lh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l):<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRl_s16 __builtin_HEXAGON_A2_subh_h16_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.h):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RhRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.h,Rs32.l):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RhRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_lh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l):sat:<<16
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h)
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRh __builtin_HEXAGON_A2_subh_l16_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l)
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRl __builtin_HEXAGON_A2_subh_l16_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRh_sat __builtin_HEXAGON_A2_subh_l16_sat_hl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32.l,Rs32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_RlRl_sat __builtin_HEXAGON_A2_subh_l16_sat_ll
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=sub(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_sub_PP __builtin_HEXAGON_A2_subp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(#s10,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_sub_IR __builtin_HEXAGON_A2_subri
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sub(Rt32,Rs32):sat
+   C Intrinsic Prototype: Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_sub_RR_sat __builtin_HEXAGON_A2_subsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vaddh(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vaddh_RR __builtin_HEXAGON_A2_svaddh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vaddh(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vaddh_RR_sat __builtin_HEXAGON_A2_svaddhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vadduh(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vadduh_RR_sat __builtin_HEXAGON_A2_svadduhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vavgh(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vavgh_RR __builtin_HEXAGON_A2_svavgh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vavgh(Rs32,Rt32):rnd
+   C Intrinsic Prototype: Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vavgh_RR_rnd __builtin_HEXAGON_A2_svavghs
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vnavgh(Rt32,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vnavgh_RR __builtin_HEXAGON_A2_svnavgh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsubh(Rt32,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vsubh_RR __builtin_HEXAGON_A2_svsubh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsubh(Rt32,Rs32):sat
+   C Intrinsic Prototype: Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vsubh_RR_sat __builtin_HEXAGON_A2_svsubhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsubuh(Rt32,Rs32):sat
+   C Intrinsic Prototype: Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vsubuh_RR_sat __builtin_HEXAGON_A2_svsubuhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=swiz(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_swiz_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_swiz_R __builtin_HEXAGON_A2_swiz
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sxtb(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_sxtb_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_sxtb_R __builtin_HEXAGON_A2_sxtb
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sxth(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_sxth_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_sxth_R __builtin_HEXAGON_A2_sxth
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=sxtw(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_sxtw_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_sxtw_R __builtin_HEXAGON_A2_sxtw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=Rs32
+   C Intrinsic Prototype: Word32 Q6_R_equals_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_equals_R __builtin_HEXAGON_A2_tfr
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32.h=#u16
+   C Intrinsic Prototype: Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Rh_equals_I __builtin_HEXAGON_A2_tfrih
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32.l=#u16
+   C Intrinsic Prototype: Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_Rl_equals_I __builtin_HEXAGON_A2_tfril
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=Rss32
+   C Intrinsic Prototype: Word64 Q6_P_equals_P(Word64 Rss)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_equals_P __builtin_HEXAGON_A2_tfrp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=#s8
+   C Intrinsic Prototype: Word64 Q6_P_equals_I(Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_equals_I __builtin_HEXAGON_A2_tfrpi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=#s16
+   C Intrinsic Prototype: Word32 Q6_R_equals_I(Word32 Is16)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_equals_I __builtin_HEXAGON_A2_tfrsi
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsh(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vabsh_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsh_P __builtin_HEXAGON_A2_vabsh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsh(Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vabsh_P_sat(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsh_P_sat __builtin_HEXAGON_A2_vabshsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsw(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vabsw_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsw_P __builtin_HEXAGON_A2_vabsw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsw(Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vabsw_P_sat(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsw_P_sat __builtin_HEXAGON_A2_vabswsat
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddb(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      MAPPING
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_vaddb_PP __builtin_HEXAGON_A2_vaddb_map
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaddh_PP __builtin_HEXAGON_A2_vaddh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaddh_PP_sat __builtin_HEXAGON_A2_vaddhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddub(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaddub_PP __builtin_HEXAGON_A2_vaddub
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddub(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaddub_PP_sat __builtin_HEXAGON_A2_vaddubs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vadduh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vadduh_PP_sat __builtin_HEXAGON_A2_vadduhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaddw_PP __builtin_HEXAGON_A2_vaddw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaddw(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaddw_PP_sat __builtin_HEXAGON_A2_vaddws
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgh_PP __builtin_HEXAGON_A2_vavgh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgh(Rss32,Rtt32):crnd
+   C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgh_PP_crnd __builtin_HEXAGON_A2_vavghcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgh(Rss32,Rtt32):rnd
+   C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgh_PP_rnd __builtin_HEXAGON_A2_vavghr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgub(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgub_PP __builtin_HEXAGON_A2_vavgub
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgub(Rss32,Rtt32):rnd
+   C Intrinsic Prototype: Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgub_PP_rnd __builtin_HEXAGON_A2_vavgubr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavguh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavguh_PP __builtin_HEXAGON_A2_vavguh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavguh(Rss32,Rtt32):rnd
+   C Intrinsic Prototype: Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavguh_PP_rnd __builtin_HEXAGON_A2_vavguhr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavguw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavguw_PP __builtin_HEXAGON_A2_vavguw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavguw(Rss32,Rtt32):rnd
+   C Intrinsic Prototype: Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavguw_PP_rnd __builtin_HEXAGON_A2_vavguwr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgw_PP __builtin_HEXAGON_A2_vavgw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgw(Rss32,Rtt32):crnd
+   C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgw_PP_crnd __builtin_HEXAGON_A2_vavgwcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vavgw(Rss32,Rtt32):rnd
+   C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vavgw_PP_rnd __builtin_HEXAGON_A2_vavgwr
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpb.eq(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpb_eq_PP __builtin_HEXAGON_A2_vcmpbeq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpb.gtu(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpb_gtu_PP __builtin_HEXAGON_A2_vcmpbgtu
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmph.eq(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmph_eq_PP __builtin_HEXAGON_A2_vcmpheq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmph.gt(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmph_gt_PP __builtin_HEXAGON_A2_vcmphgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmph.gtu(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmph_gtu_PP __builtin_HEXAGON_A2_vcmphgtu
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpw.eq(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpw_eq_PP __builtin_HEXAGON_A2_vcmpweq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpw.gt(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpw_gt_PP __builtin_HEXAGON_A2_vcmpwgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpw.gtu(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpw_gtu_PP __builtin_HEXAGON_A2_vcmpwgtu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vconj(Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vconj_P_sat(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vconj_P_sat __builtin_HEXAGON_A2_vconj
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmaxb(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmaxb_PP __builtin_HEXAGON_A2_vmaxb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmaxh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmaxh_PP __builtin_HEXAGON_A2_vmaxh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmaxub(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmaxub_PP __builtin_HEXAGON_A2_vmaxub
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmaxuh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmaxuh_PP __builtin_HEXAGON_A2_vmaxuh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmaxuw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmaxuw_PP __builtin_HEXAGON_A2_vmaxuw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmaxw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmaxw_PP __builtin_HEXAGON_A2_vmaxw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vminb(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vminb_PP __builtin_HEXAGON_A2_vminb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vminh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vminh_PP __builtin_HEXAGON_A2_vminh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vminub(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vminub_PP __builtin_HEXAGON_A2_vminub
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vminuh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vminuh_PP __builtin_HEXAGON_A2_vminuh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vminuw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vminuw_PP __builtin_HEXAGON_A2_vminuw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vminw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vminw_PP __builtin_HEXAGON_A2_vminw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vnavgh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vnavgh_PP __builtin_HEXAGON_A2_vnavgh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vnavgh(Rtt32,Rss32):crnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vnavgh_PP_crnd_sat __builtin_HEXAGON_A2_vnavghcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vnavgh(Rtt32,Rss32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vnavgh_PP_rnd_sat __builtin_HEXAGON_A2_vnavghr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vnavgw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vnavgw_PP __builtin_HEXAGON_A2_vnavgw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vnavgw(Rtt32,Rss32):crnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vnavgw_PP_crnd_sat __builtin_HEXAGON_A2_vnavgwcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vnavgw(Rtt32,Rss32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vnavgw_PP_rnd_sat __builtin_HEXAGON_A2_vnavgwr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vraddub(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vraddub_PP __builtin_HEXAGON_A2_vraddub
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vraddub(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vraddubacc_PP __builtin_HEXAGON_A2_vraddub_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrsadub(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrsadub_PP __builtin_HEXAGON_A2_vrsadub
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrsadub(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrsadubacc_PP __builtin_HEXAGON_A2_vrsadub_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubb(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      MAPPING
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_vsubb_PP __builtin_HEXAGON_A2_vsubb_map
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubh_PP __builtin_HEXAGON_A2_vsubh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubh(Rtt32,Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubh_PP_sat __builtin_HEXAGON_A2_vsubhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubub(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubub_PP __builtin_HEXAGON_A2_vsubub
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubub(Rtt32,Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubub_PP_sat __builtin_HEXAGON_A2_vsububs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubuh(Rtt32,Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubuh_PP_sat __builtin_HEXAGON_A2_vsubuhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubw_PP __builtin_HEXAGON_A2_vsubw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsubw(Rtt32,Rss32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsubw_PP_sat __builtin_HEXAGON_A2_vsubws
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=xor(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_xor_RR __builtin_HEXAGON_A2_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=xor(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_xor_PP __builtin_HEXAGON_A2_xorp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=zxtb(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_zxtb_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_zxtb_R __builtin_HEXAGON_A2_zxtb
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=zxth(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_zxth_R(Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_zxth_R __builtin_HEXAGON_A2_zxth
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=and(Rt32,~Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_and_RnR __builtin_HEXAGON_A4_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=and(Rtt32,~Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_and_PnP __builtin_HEXAGON_A4_andnp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=bitsplit(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_bitsplit_RR __builtin_HEXAGON_A4_bitsplit
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=bitsplit(Rs32,#u5)
+   C Intrinsic Prototype: Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_bitsplit_RI __builtin_HEXAGON_A4_bitspliti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=boundscheck(Rs32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_boundscheck_RP __builtin_HEXAGON_A4_boundscheck
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmpb.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmpb_eq_RR __builtin_HEXAGON_A4_cmpbeq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmpb.eq(Rs32,#u8)
+   C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmpb_eq_RI __builtin_HEXAGON_A4_cmpbeqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmpb.gt(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmpb_gt_RR __builtin_HEXAGON_A4_cmpbgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmpb.gt(Rs32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmpb_gt_RI __builtin_HEXAGON_A4_cmpbgti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmpb.gtu(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmpb_gtu_RR __builtin_HEXAGON_A4_cmpbgtu
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmpb.gtu(Rs32,#u7)
+   C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmpb_gtu_RI __builtin_HEXAGON_A4_cmpbgtui
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmph.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmph_eq_RR __builtin_HEXAGON_A4_cmpheq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmph.eq(Rs32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmph_eq_RI __builtin_HEXAGON_A4_cmpheqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmph.gt(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmph_gt_RR __builtin_HEXAGON_A4_cmphgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmph.gt(Rs32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmph_gt_RI __builtin_HEXAGON_A4_cmphgti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmph.gtu(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmph_gtu_RR __builtin_HEXAGON_A4_cmphgtu
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmph.gtu(Rs32,#u7)
+   C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmph_gtu_RI __builtin_HEXAGON_A4_cmphgtui
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=combine(#s8,Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_combine_IR __builtin_HEXAGON_A4_combineir
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=combine(Rs32,#s8)
+   C Intrinsic Prototype: Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_combine_RI __builtin_HEXAGON_A4_combineri
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cround(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cround_RI __builtin_HEXAGON_A4_cround_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cround(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cround_RR __builtin_HEXAGON_A4_cround_rr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=modwrap(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_modwrap_RR __builtin_HEXAGON_A4_modwrapu
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=or(Rt32,~Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_or_RnR __builtin_HEXAGON_A4_orn
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=or(Rtt32,~Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_or_PnP __builtin_HEXAGON_A4_ornp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmp.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_cmp_eq_RR __builtin_HEXAGON_A4_rcmpeq
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmp.eq(Rs32,#s8)
+   C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_cmp_eq_RI __builtin_HEXAGON_A4_rcmpeqi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=!cmp.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_not_cmp_eq_RR __builtin_HEXAGON_A4_rcmpneq
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=!cmp.eq(Rs32,#s8)
+   C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_not_cmp_eq_RI __builtin_HEXAGON_A4_rcmpneqi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=round(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_round_RI __builtin_HEXAGON_A4_round_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=round(Rs32,#u5):sat
+   C Intrinsic Prototype: Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_round_RI_sat __builtin_HEXAGON_A4_round_ri_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=round(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_round_RR __builtin_HEXAGON_A4_round_rr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=round(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_round_RR_sat __builtin_HEXAGON_A4_round_rr_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=tlbmatch(Rss32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_tlbmatch_PR __builtin_HEXAGON_A4_tlbmatch
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=any8(vcmpb.eq(Rss32,Rtt32))
+   C Intrinsic Prototype: Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_any8_vcmpb_eq_PP __builtin_HEXAGON_A4_vcmpbeq_any
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpb.eq(Rss32,#u8)
+   C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpb_eq_PI __builtin_HEXAGON_A4_vcmpbeqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpb.gt(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpb_gt_PP __builtin_HEXAGON_A4_vcmpbgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpb.gt(Rss32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpb_gt_PI __builtin_HEXAGON_A4_vcmpbgti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpb.gtu(Rss32,#u7)
+   C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpb_gtu_PI __builtin_HEXAGON_A4_vcmpbgtui
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmph.eq(Rss32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmph_eq_PI __builtin_HEXAGON_A4_vcmpheqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmph.gt(Rss32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmph_gt_PI __builtin_HEXAGON_A4_vcmphgti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmph.gtu(Rss32,#u7)
+   C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmph_gtu_PI __builtin_HEXAGON_A4_vcmphgtui
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpw.eq(Rss32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpw_eq_PI __builtin_HEXAGON_A4_vcmpweqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpw.gt(Rss32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpw_gt_PI __builtin_HEXAGON_A4_vcmpwgti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=vcmpw.gtu(Rss32,#u7)
+   C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_vcmpw_gtu_PI __builtin_HEXAGON_A4_vcmpwgtui
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrmaxh(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmaxh_PR __builtin_HEXAGON_A4_vrmaxh
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrmaxuh(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmaxuh_PR __builtin_HEXAGON_A4_vrmaxuh
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrmaxuw(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmaxuw_PR __builtin_HEXAGON_A4_vrmaxuw
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrmaxw(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmaxw_PR __builtin_HEXAGON_A4_vrmaxw
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrminh(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrminh_PR __builtin_HEXAGON_A4_vrminh
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrminuh(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrminuh_PR __builtin_HEXAGON_A4_vrminuh
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrminuw(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrminuw_PR __builtin_HEXAGON_A4_vrminuw
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=vrminw(Rss32,Ru32)
+   C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrminw_PR __builtin_HEXAGON_A4_vrminw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vaddhub(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vaddhub_PP_sat __builtin_HEXAGON_A5_vaddhubs
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=all8(Ps4)
+   C Intrinsic Prototype: Byte Q6_p_all8_p(Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_all8_p __builtin_HEXAGON_C2_all8
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=and(Pt4,Ps4)
+   C Intrinsic Prototype: Byte Q6_p_and_pp(Byte Pt, Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_and_pp __builtin_HEXAGON_C2_and
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=and(Pt4,!Ps4)
+   C Intrinsic Prototype: Byte Q6_p_and_pnp(Byte Pt, Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_and_pnp __builtin_HEXAGON_C2_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=any8(Ps4)
+   C Intrinsic Prototype: Byte Q6_p_any8_p(Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_any8_p __builtin_HEXAGON_C2_any8
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=bitsclr(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_bitsclr_RR __builtin_HEXAGON_C2_bitsclr
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=bitsclr(Rs32,#u6)
+   C Intrinsic Prototype: Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_bitsclr_RI __builtin_HEXAGON_C2_bitsclri
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=bitsset(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_bitsset_RR __builtin_HEXAGON_C2_bitsset
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_eq_RR __builtin_HEXAGON_C2_cmpeq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.eq(Rs32,#s10)
+   C Intrinsic Prototype: Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_eq_RI __builtin_HEXAGON_C2_cmpeqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.eq(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmp_eq_PP __builtin_HEXAGON_C2_cmpeqp
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.ge(Rs32,#s8)
+   C Intrinsic Prototype: Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_ge_RI __builtin_HEXAGON_C2_cmpgei
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.geu(Rs32,#u8)
+   C Intrinsic Prototype: Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_geu_RI __builtin_HEXAGON_C2_cmpgeui
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.gt(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_gt_RR __builtin_HEXAGON_C2_cmpgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.gt(Rs32,#s10)
+   C Intrinsic Prototype: Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_gt_RI __builtin_HEXAGON_C2_cmpgti
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.gt(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmp_gt_PP __builtin_HEXAGON_C2_cmpgtp
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.gtu(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_gtu_RR __builtin_HEXAGON_C2_cmpgtu
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.gtu(Rs32,#u9)
+   C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_gtu_RI __builtin_HEXAGON_C2_cmpgtui
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.gtu(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_cmp_gtu_PP __builtin_HEXAGON_C2_cmpgtup
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.lt(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_lt_RR __builtin_HEXAGON_C2_cmplt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=cmp.ltu(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_cmp_ltu_RR __builtin_HEXAGON_C2_cmpltu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mask(Pt4)
+   C Intrinsic Prototype: Word64 Q6_P_mask_p(Byte Pt)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mask_p __builtin_HEXAGON_C2_mask
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mux(Pu4,Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_mux_pRR __builtin_HEXAGON_C2_mux
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mux(Pu4,#s8,#S8)
+   C Intrinsic Prototype: Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_mux_pII __builtin_HEXAGON_C2_muxii
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mux(Pu4,Rs32,#s8)
+   C Intrinsic Prototype: Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_mux_pRI __builtin_HEXAGON_C2_muxir
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mux(Pu4,#s8,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_mux_pIR __builtin_HEXAGON_C2_muxri
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=not(Ps4)
+   C Intrinsic Prototype: Byte Q6_p_not_p(Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_p __builtin_HEXAGON_C2_not
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=or(Pt4,Ps4)
+   C Intrinsic Prototype: Byte Q6_p_or_pp(Byte Pt, Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_or_pp __builtin_HEXAGON_C2_or
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=or(Pt4,!Ps4)
+   C Intrinsic Prototype: Byte Q6_p_or_pnp(Byte Pt, Byte Ps)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_or_pnp __builtin_HEXAGON_C2_orn
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=Ps4
+   C Intrinsic Prototype: Byte Q6_p_equals_p(Byte Ps)
+   Instruction Type:      MAPPING
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_equals_p __builtin_HEXAGON_C2_pxfer_map
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=Ps4
+   C Intrinsic Prototype: Word32 Q6_R_equals_p(Byte Ps)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_equals_p __builtin_HEXAGON_C2_tfrpr
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=Rs32
+   C Intrinsic Prototype: Byte Q6_p_equals_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_equals_R __builtin_HEXAGON_C2_tfrrp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vitpack(Ps4,Pt4)
+   C Intrinsic Prototype: Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vitpack_pp __builtin_HEXAGON_C2_vitpack
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmux(Pu4,Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmux_pPP __builtin_HEXAGON_C2_vmux
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=xor(Ps4,Pt4)
+   C Intrinsic Prototype: Byte Q6_p_xor_pp(Byte Ps, Byte Pt)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_xor_pp __builtin_HEXAGON_C2_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=and(Ps4,and(Pt4,Pu4))
+   C Intrinsic Prototype: Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_and_and_ppp __builtin_HEXAGON_C4_and_and
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=and(Ps4,and(Pt4,!Pu4))
+   C Intrinsic Prototype: Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_and_and_ppnp __builtin_HEXAGON_C4_and_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=and(Ps4,or(Pt4,Pu4))
+   C Intrinsic Prototype: Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_and_or_ppp __builtin_HEXAGON_C4_and_or
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=and(Ps4,or(Pt4,!Pu4))
+   C Intrinsic Prototype: Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_and_or_ppnp __builtin_HEXAGON_C4_and_orn
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!cmp.gt(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_not_cmp_gt_RR __builtin_HEXAGON_C4_cmplte
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!cmp.gt(Rs32,#s10)
+   C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_not_cmp_gt_RI __builtin_HEXAGON_C4_cmpltei
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!cmp.gtu(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_not_cmp_gtu_RR __builtin_HEXAGON_C4_cmplteu
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!cmp.gtu(Rs32,#u9)
+   C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_not_cmp_gtu_RI __builtin_HEXAGON_C4_cmplteui
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!cmp.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_not_cmp_eq_RR __builtin_HEXAGON_C4_cmpneq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!cmp.eq(Rs32,#s10)
+   C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU32_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_p_not_cmp_eq_RI __builtin_HEXAGON_C4_cmpneqi
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=fastcorner9(Ps4,Pt4)
+   C Intrinsic Prototype: Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!fastcorner9(Ps4,Pt4)
+   C Intrinsic Prototype: Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9_not
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!bitsclr(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_bitsclr_RR __builtin_HEXAGON_C4_nbitsclr
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!bitsclr(Rs32,#u6)
+   C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_bitsclr_RI __builtin_HEXAGON_C4_nbitsclri
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!bitsset(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_bitsset_RR __builtin_HEXAGON_C4_nbitsset
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=or(Ps4,and(Pt4,Pu4))
+   C Intrinsic Prototype: Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_or_and_ppp __builtin_HEXAGON_C4_or_and
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=or(Ps4,and(Pt4,!Pu4))
+   C Intrinsic Prototype: Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_or_and_ppnp __builtin_HEXAGON_C4_or_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=or(Ps4,or(Pt4,Pu4))
+   C Intrinsic Prototype: Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_or_or_ppp __builtin_HEXAGON_C4_or_or
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=or(Ps4,or(Pt4,!Pu4))
+   C Intrinsic Prototype: Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu)
+   Instruction Type:      CR
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_or_or_ppnp __builtin_HEXAGON_C4_or_orn
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_d2df(Rss32)
+   C Intrinsic Prototype: Float64 Q6_P_convert_d2df_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_d2df_P __builtin_HEXAGON_F2_conv_d2df
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_d2sf(Rss32)
+   C Intrinsic Prototype: Float32 Q6_R_convert_d2sf_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_d2sf_P __builtin_HEXAGON_F2_conv_d2sf
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_df2d(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_df2d_P __builtin_HEXAGON_F2_conv_df2d
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_df2d(Rss32):chop
+   C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P_chop(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_df2d_P_chop __builtin_HEXAGON_F2_conv_df2d_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_df2sf(Rss32)
+   C Intrinsic Prototype: Float32 Q6_R_convert_df2sf_P(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_df2sf_P __builtin_HEXAGON_F2_conv_df2sf
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_df2ud(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_df2ud_P __builtin_HEXAGON_F2_conv_df2ud
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_df2ud(Rss32):chop
+   C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P_chop(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_df2ud_P_chop __builtin_HEXAGON_F2_conv_df2ud_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_df2uw(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_df2uw_P __builtin_HEXAGON_F2_conv_df2uw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_df2uw(Rss32):chop
+   C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P_chop(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_df2uw_P_chop __builtin_HEXAGON_F2_conv_df2uw_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_df2w(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_df2w_P __builtin_HEXAGON_F2_conv_df2w
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_df2w(Rss32):chop
+   C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P_chop(Float64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_df2w_P_chop __builtin_HEXAGON_F2_conv_df2w_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_sf2d(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_sf2d_R __builtin_HEXAGON_F2_conv_sf2d
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_sf2d(Rs32):chop
+   C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R_chop(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_sf2d_R_chop __builtin_HEXAGON_F2_conv_sf2d_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_sf2df(Rs32)
+   C Intrinsic Prototype: Float64 Q6_P_convert_sf2df_R(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_sf2df_R __builtin_HEXAGON_F2_conv_sf2df
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_sf2ud(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_sf2ud_R __builtin_HEXAGON_F2_conv_sf2ud
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_sf2ud(Rs32):chop
+   C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R_chop(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_sf2ud_R_chop __builtin_HEXAGON_F2_conv_sf2ud_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_sf2uw(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_sf2uw_R __builtin_HEXAGON_F2_conv_sf2uw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_sf2uw(Rs32):chop
+   C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R_chop(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_sf2uw_R_chop __builtin_HEXAGON_F2_conv_sf2uw_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_sf2w(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_sf2w_R __builtin_HEXAGON_F2_conv_sf2w
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_sf2w(Rs32):chop
+   C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R_chop(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_sf2w_R_chop __builtin_HEXAGON_F2_conv_sf2w_chop
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_ud2df(Rss32)
+   C Intrinsic Prototype: Float64 Q6_P_convert_ud2df_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_ud2df_P __builtin_HEXAGON_F2_conv_ud2df
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_ud2sf(Rss32)
+   C Intrinsic Prototype: Float32 Q6_R_convert_ud2sf_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_ud2sf_P __builtin_HEXAGON_F2_conv_ud2sf
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_uw2df(Rs32)
+   C Intrinsic Prototype: Float64 Q6_P_convert_uw2df_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_uw2df_R __builtin_HEXAGON_F2_conv_uw2df
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_uw2sf(Rs32)
+   C Intrinsic Prototype: Float32 Q6_R_convert_uw2sf_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_uw2sf_R __builtin_HEXAGON_F2_conv_uw2sf
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=convert_w2df(Rs32)
+   C Intrinsic Prototype: Float64 Q6_P_convert_w2df_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_convert_w2df_R __builtin_HEXAGON_F2_conv_w2df
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=convert_w2sf(Rs32)
+   C Intrinsic Prototype: Float32 Q6_R_convert_w2sf_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_convert_w2sf_R __builtin_HEXAGON_F2_conv_w2sf
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=dfclass(Rss32,#u5)
+   C Intrinsic Prototype: Byte Q6_p_dfclass_PI(Float64 Rss, Word32 Iu5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_dfclass_PI __builtin_HEXAGON_F2_dfclass
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=dfcmp.eq(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_dfcmp_eq_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_dfcmp_eq_PP __builtin_HEXAGON_F2_dfcmpeq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=dfcmp.ge(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_dfcmp_ge_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_dfcmp_ge_PP __builtin_HEXAGON_F2_dfcmpge
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=dfcmp.gt(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_dfcmp_gt_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_dfcmp_gt_PP __builtin_HEXAGON_F2_dfcmpgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=dfcmp.uo(Rss32,Rtt32)
+   C Intrinsic Prototype: Byte Q6_p_dfcmp_uo_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_dfcmp_uo_PP __builtin_HEXAGON_F2_dfcmpuo
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfmake(#u10):neg
+   C Intrinsic Prototype: Float64 Q6_P_dfmake_I_neg(Word32 Iu10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmake_I_neg __builtin_HEXAGON_F2_dfimm_n
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfmake(#u10):pos
+   C Intrinsic Prototype: Float64 Q6_P_dfmake_I_pos(Word32 Iu10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmake_I_pos __builtin_HEXAGON_F2_dfimm_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfadd(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfadd_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfadd_RR __builtin_HEXAGON_F2_sfadd
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=sfclass(Rs32,#u5)
+   C Intrinsic Prototype: Byte Q6_p_sfclass_RI(Float32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_sfclass_RI __builtin_HEXAGON_F2_sfclass
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=sfcmp.eq(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_sfcmp_eq_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_sfcmp_eq_RR __builtin_HEXAGON_F2_sfcmpeq
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=sfcmp.ge(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_sfcmp_ge_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_sfcmp_ge_RR __builtin_HEXAGON_F2_sfcmpge
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=sfcmp.gt(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_sfcmp_gt_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_sfcmp_gt_RR __builtin_HEXAGON_F2_sfcmpgt
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=sfcmp.uo(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_sfcmp_uo_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_sfcmp_uo_RR __builtin_HEXAGON_F2_sfcmpuo
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sffixupd(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sffixupd_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sffixupd_RR __builtin_HEXAGON_F2_sffixupd
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sffixupn(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sffixupn_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sffixupn_RR __builtin_HEXAGON_F2_sffixupn
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sffixupr(Rs32)
+   C Intrinsic Prototype: Float32 Q6_R_sffixupr_R(Float32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sffixupr_R __builtin_HEXAGON_F2_sffixupr
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=sfmpy(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmpyacc_RR __builtin_HEXAGON_F2_sffma
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=sfmpy(Rs32,Rt32):lib
+   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmpyacc_RR_lib __builtin_HEXAGON_F2_sffma_lib
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=sfmpy(Rs32,Rt32,Pu4):scale
+   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmpyacc_RRp_scale __builtin_HEXAGON_F2_sffma_sc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=sfmpy(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmpynac_RR __builtin_HEXAGON_F2_sffms
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=sfmpy(Rs32,Rt32):lib
+   C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmpynac_RR_lib __builtin_HEXAGON_F2_sffms_lib
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfmake(#u10):neg
+   C Intrinsic Prototype: Float32 Q6_R_sfmake_I_neg(Word32 Iu10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmake_I_neg __builtin_HEXAGON_F2_sfimm_n
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfmake(#u10):pos
+   C Intrinsic Prototype: Float32 Q6_R_sfmake_I_pos(Word32 Iu10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmake_I_pos __builtin_HEXAGON_F2_sfimm_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfmax(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfmax_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmax_RR __builtin_HEXAGON_F2_sfmax
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfmin(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfmin_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmin_RR __builtin_HEXAGON_F2_sfmin
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfmpy(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfmpy_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfmpy_RR __builtin_HEXAGON_F2_sfmpy
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=sfsub(Rs32,Rt32)
+   C Intrinsic Prototype: Float32 Q6_R_sfsub_RR(Float32 Rs, Float32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sfsub_RR __builtin_HEXAGON_F2_sfsub
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memb(Rx32++#s4:0:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memb_IM_circ __builtin_HEXAGON_L2_loadrb_pci
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memb(Rx32++I:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memb_M_circ __builtin_HEXAGON_L2_loadrb_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=memd(Rx32++#s4:3:circ(Mu2))
+   C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_P_memd_IM_circ __builtin_HEXAGON_L2_loadrd_pci
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=memd(Rx32++I:circ(Mu2))
+   C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_P_memd_M_circ __builtin_HEXAGON_L2_loadrd_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memh(Rx32++#s4:1:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memh_IM_circ __builtin_HEXAGON_L2_loadrh_pci
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memh(Rx32++I:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memh_M_circ __builtin_HEXAGON_L2_loadrh_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memw(Rx32++#s4:2:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memw_IM_circ __builtin_HEXAGON_L2_loadri_pci
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memw(Rx32++I:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memw_M_circ __builtin_HEXAGON_L2_loadri_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memub(Rx32++#s4:0:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memub_IM_circ __builtin_HEXAGON_L2_loadrub_pci
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memub(Rx32++I:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memub_M_circ __builtin_HEXAGON_L2_loadrub_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memuh(Rx32++#s4:1:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memuh_IM_circ __builtin_HEXAGON_L2_loadruh_pci
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=memuh(Rx32++I:circ(Mu2))
+   C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
+   Instruction Type:      LD
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_R_memuh_M_circ __builtin_HEXAGON_L2_loadruh_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=add(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_addacc_RR __builtin_HEXAGON_M2_acci
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=add(Rs32,#s8)
+   C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_addacc_RI __builtin_HEXAGON_M2_accii
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpyi(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyiacc_RR __builtin_HEXAGON_M2_cmaci_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpyr(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyracc_RR __builtin_HEXAGON_M2_cmacr_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyacc_RR_sat __builtin_HEXAGON_M2_cmacs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyacc_RR_s1_sat __builtin_HEXAGON_M2_cmacs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32*):sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyacc_RR_conj_sat __builtin_HEXAGON_M2_cmacsc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpy(Rs32,Rt32*):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyacc_RR_conj_s1_sat __builtin_HEXAGON_M2_cmacsc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpyi(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyi_RR __builtin_HEXAGON_M2_cmpyi_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpyr(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpyr_RR __builtin_HEXAGON_M2_cmpyr_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpy(Rs32,Rt32):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpy_RR_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpy_RR_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpy(Rs32,Rt32*):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpy_RR_conj_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpy_RR_conj_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpy_RR_sat __builtin_HEXAGON_M2_cmpys_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpy_RR_s1_sat __builtin_HEXAGON_M2_cmpys_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32*):sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpy_RR_conj_sat __builtin_HEXAGON_M2_cmpysc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpy(Rs32,Rt32*):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpy_RR_conj_s1_sat __builtin_HEXAGON_M2_cmpysc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpynac_RR_sat __builtin_HEXAGON_M2_cnacs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpynac_RR_s1_sat __builtin_HEXAGON_M2_cnacs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32*):sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpynac_RR_conj_sat __builtin_HEXAGON_M2_cnacsc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=cmpy(Rs32,Rt32*):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cmpynac_RR_conj_s1_sat __builtin_HEXAGON_M2_cnacsc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RR __builtin_HEXAGON_M2_dpmpyss_acc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RR __builtin_HEXAGON_M2_dpmpyss_nac_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32):rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RR_rnd __builtin_HEXAGON_M2_dpmpyss_rnd_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RR __builtin_HEXAGON_M2_dpmpyss_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RR __builtin_HEXAGON_M2_dpmpyuu_acc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RR __builtin_HEXAGON_M2_dpmpyuu_nac_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32,Rt32)
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RR __builtin_HEXAGON_M2_dpmpyuu_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RRh_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyh_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RRh_s1_sat __builtin_HEXAGON_M2_hmmpyh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RRl_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyl_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RRl_s1_sat __builtin_HEXAGON_M2_hmmpyl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyi(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyiacc_RR __builtin_HEXAGON_M2_maci
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyi(Rs32,#u8)
+   C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyinac_RI __builtin_HEXAGON_M2_macsin
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyi(Rs32,#u8)
+   C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyiacc_RI __builtin_HEXAGON_M2_macsip
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywohacc_PP_rnd_sat __builtin_HEXAGON_M2_mmachs_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywohacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmachs_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywohacc_PP_sat __builtin_HEXAGON_M2_mmachs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywohacc_PP_s1_sat __builtin_HEXAGON_M2_mmachs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywehacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacls_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywehacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacls_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywehacc_PP_sat __builtin_HEXAGON_M2_mmacls_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywehacc_PP_s1_sat __builtin_HEXAGON_M2_mmacls_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouhacc_PP_sat __builtin_HEXAGON_M2_mmacuhs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouhacc_PP_s1_sat __builtin_HEXAGON_M2_mmacuhs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuhacc_PP_sat __builtin_HEXAGON_M2_mmaculs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuhacc_PP_s1_sat __builtin_HEXAGON_M2_mmaculs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywoh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywoh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywoh_PP_sat __builtin_HEXAGON_M2_mmpyh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywoh_PP_s1_sat __builtin_HEXAGON_M2_mmpyh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweh_PP_sat __builtin_HEXAGON_M2_mmpyl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweh_PP_s1_sat __builtin_HEXAGON_M2_mmpyl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouh_PP_sat __builtin_HEXAGON_M2_mmpyuh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpywouh_PP_s1_sat __builtin_HEXAGON_M2_mmpyuh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuh_PP_sat __builtin_HEXAGON_M2_mmpyul_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyweuh_PP_s1_sat __builtin_HEXAGON_M2_mmpyul_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRh __builtin_HEXAGON_M2_mpy_acc_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpy_acc_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRl __builtin_HEXAGON_M2_mpy_acc_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpy_acc_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRh __builtin_HEXAGON_M2_mpy_acc_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpy_acc_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRl __builtin_HEXAGON_M2_mpy_acc_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpy_acc_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh __builtin_HEXAGON_M2_mpy_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpy_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl __builtin_HEXAGON_M2_mpy_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpy_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh __builtin_HEXAGON_M2_mpy_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpy_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl __builtin_HEXAGON_M2_mpy_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpy_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRh __builtin_HEXAGON_M2_mpy_nac_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpy_nac_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRl __builtin_HEXAGON_M2_mpy_nac_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpy_nac_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRh __builtin_HEXAGON_M2_mpy_nac_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpy_nac_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRl __builtin_HEXAGON_M2_mpy_nac_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpy_nac_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_sat __builtin_HEXAGON_M2_mpy_sat_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_sat __builtin_HEXAGON_M2_mpy_sat_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_sat __builtin_HEXAGON_M2_mpy_sat_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_sat __builtin_HEXAGON_M2_mpy_sat_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RhRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RlRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RR __builtin_HEXAGON_M2_mpy_up
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RR_s1 __builtin_HEXAGON_M2_mpy_up_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpy(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpy_RR_s1_sat __builtin_HEXAGON_M2_mpy_up_s1_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RhRh __builtin_HEXAGON_M2_mpyd_acc_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpyd_acc_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RhRl __builtin_HEXAGON_M2_mpyd_acc_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpyd_acc_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RlRh __builtin_HEXAGON_M2_mpyd_acc_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpyd_acc_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RlRl __builtin_HEXAGON_M2_mpyd_acc_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpy(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpyd_acc_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRh __builtin_HEXAGON_M2_mpyd_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpyd_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRl __builtin_HEXAGON_M2_mpyd_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpyd_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRh __builtin_HEXAGON_M2_mpyd_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpyd_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRl __builtin_HEXAGON_M2_mpyd_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpyd_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RhRh __builtin_HEXAGON_M2_mpyd_nac_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpyd_nac_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RhRl __builtin_HEXAGON_M2_mpyd_nac_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpyd_nac_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RlRh __builtin_HEXAGON_M2_mpyd_nac_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpyd_nac_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RlRl __builtin_HEXAGON_M2_mpyd_nac_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpy(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpyd_nac_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h):rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l):rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h):rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l):rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd
+   C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyi(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyi_RR __builtin_HEXAGON_M2_mpyi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyi(Rs32,#m9)
+   C Intrinsic Prototype: Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9)
+   Instruction Type:      M
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_mpyi_RI __builtin_HEXAGON_M2_mpysmi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpysu(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpysu_RR __builtin_HEXAGON_M2_mpysu_up
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyu_acc_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyu_acc_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyu_acc_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyu_acc_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyu_acc_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyu_acc_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyu_acc_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpyu(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyu_acc_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RhRh __builtin_HEXAGON_M2_mpyu_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyu_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RhRl __builtin_HEXAGON_M2_mpyu_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyu_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RlRh __builtin_HEXAGON_M2_mpyu_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyu_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RlRl __builtin_HEXAGON_M2_mpyu_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyu_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RhRh __builtin_HEXAGON_M2_mpyu_nac_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyu_nac_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RhRl __builtin_HEXAGON_M2_mpyu_nac_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyu_nac_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RlRh __builtin_HEXAGON_M2_mpyu_nac_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyu_nac_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RlRl __builtin_HEXAGON_M2_mpyu_nac_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyu(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyu_nac_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyu(Rs32,Rt32)
+   C Intrinsic Prototype: UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyu_RR __builtin_HEXAGON_M2_mpyu_up
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyud_acc_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyud_acc_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyud_acc_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyud_acc_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyud_acc_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyud_acc_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyud_acc_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=mpyu(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyud_acc_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RhRh __builtin_HEXAGON_M2_mpyud_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyud_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RhRl __builtin_HEXAGON_M2_mpyud_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyud_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RlRh __builtin_HEXAGON_M2_mpyud_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyud_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RlRl __builtin_HEXAGON_M2_mpyud_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=mpyu(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyud_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RhRh __builtin_HEXAGON_M2_mpyud_nac_hh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyud_nac_hh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RhRl __builtin_HEXAGON_M2_mpyud_nac_hl_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.h,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyud_nac_hl_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.h)
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RlRh __builtin_HEXAGON_M2_mpyud_nac_lh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.h):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyud_nac_lh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.l)
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RlRl __builtin_HEXAGON_M2_mpyud_nac_ll_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=mpyu(Rs32.l,Rt32.l):<<1
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyud_nac_ll_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mpyui(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_mpyui_RR __builtin_HEXAGON_M2_mpyui
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=add(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_addnac_RR __builtin_HEXAGON_M2_nacci
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=add(Rs32,#s8)
+   C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_addnac_RI __builtin_HEXAGON_M2_naccii
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=sub(Rt32,Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_subacc_RR __builtin_HEXAGON_M2_subacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsdiffh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsdiffh_PP __builtin_HEXAGON_M2_vabsdiffh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsdiffw(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsdiffw_PP __builtin_HEXAGON_M2_vabsdiffw
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vcmpyi(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcmpyiacc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_i
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vcmpyr(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcmpyracc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vcmpyi(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcmpyi_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_i
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vcmpyr(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcmpyr_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcmpyi_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_i
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcmpyr_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vdmpy(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vdmpyacc_PP_sat __builtin_HEXAGON_M2_vdmacs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vdmpyacc_PP_s1_sat __builtin_HEXAGON_M2_vdmacs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vdmpy(Rss32,Rtt32):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vdmpy_PP_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vdmpy_PP_s1_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vdmpy(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vdmpy_PP_sat __builtin_HEXAGON_M2_vdmpys_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vdmpy(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vdmpy_PP_s1_sat __builtin_HEXAGON_M2_vdmpys_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyh(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhacc_RR __builtin_HEXAGON_M2_vmac2
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyeh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyehacc_PP __builtin_HEXAGON_M2_vmac2es
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyeh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyehacc_PP_sat __builtin_HEXAGON_M2_vmac2es_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyehacc_PP_s1_sat __builtin_HEXAGON_M2_vmac2es_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyh(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhacc_RR_sat __builtin_HEXAGON_M2_vmac2s_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyh(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2s_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyhsu(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhsuacc_RR_sat __builtin_HEXAGON_M2_vmac2su_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhsuacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2su_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyeh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyeh_PP_sat __builtin_HEXAGON_M2_vmpy2es_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyeh_PP_s1_sat __builtin_HEXAGON_M2_vmpy2es_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyh(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyh_RR_sat __builtin_HEXAGON_M2_vmpy2s_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vmpyh(Rs32,Rt32):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vmpyh_RR_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s0pack
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyh(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyh_RR_s1_sat __builtin_HEXAGON_M2_vmpy2s_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vmpyh_RR_s1_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s1pack
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyhsu(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhsu_RR_sat __builtin_HEXAGON_M2_vmpy2su_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpyhsu_RR_s1_sat __builtin_HEXAGON_M2_vmpy2su_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vraddh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vraddh_PP __builtin_HEXAGON_M2_vraddh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vradduh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vradduh_PP __builtin_HEXAGON_M2_vradduh
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcmpyi(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyiacc_PP __builtin_HEXAGON_M2_vrcmaci_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcmpyi(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyiacc_PP_conj __builtin_HEXAGON_M2_vrcmaci_s0c
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcmpyr(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyracc_PP __builtin_HEXAGON_M2_vrcmacr_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcmpyr(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyracc_PP_conj __builtin_HEXAGON_M2_vrcmacr_s0c
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrcmpyi(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyi_PP __builtin_HEXAGON_M2_vrcmpyi_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrcmpyi(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyi_PP_conj __builtin_HEXAGON_M2_vrcmpyi_s0c
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrcmpyr(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyr_PP __builtin_HEXAGON_M2_vrcmpyr_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrcmpyr(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcmpyr_PP_conj __builtin_HEXAGON_M2_vrcmpyr_s0c
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_vrcmpysacc_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_acc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrcmpys(Rss32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_vrcmpys_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vrcmpys_PR_s1_rnd_sat __builtin_HEXAGON_M2_vrcmpys_s1rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpyh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpyhacc_PP __builtin_HEXAGON_M2_vrmac_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpyh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpyh_PP __builtin_HEXAGON_M2_vrmpy_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=xor(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_xorxacc_RR __builtin_HEXAGON_M2_xor_xacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=and(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andand_RR __builtin_HEXAGON_M4_and_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=and(Rs32,~Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andand_RnR __builtin_HEXAGON_M4_and_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=or(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_orand_RR __builtin_HEXAGON_M4_and_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=xor(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_xorand_RR __builtin_HEXAGON_M4_and_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpyiwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_wh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpyiwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_whc
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpyrwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_wh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cmpyrwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_whc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=mpy(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyacc_RR_s1_sat __builtin_HEXAGON_M4_mac_up_s1_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(#u6,mpyi(Rs32,#U6))
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_mpyi_IRI __builtin_HEXAGON_M4_mpyri_addi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Ru32,mpyi(Rs32,#u6))
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_mpyi_RRI __builtin_HEXAGON_M4_mpyri_addr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Ru32,mpyi(#u6:2,Rs32))
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_mpyi_RIR __builtin_HEXAGON_M4_mpyri_addr_u2
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(#u6,mpyi(Rs32,Rt32))
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_mpyi_IRR __builtin_HEXAGON_M4_mpyrr_addi
+
+/* ==========================================================================
+   Assembly Syntax:       Ry32=add(Ru32,mpyi(Ry32,Rs32))
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_mpyi_RRR __builtin_HEXAGON_M4_mpyrr_addr
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpy(Rs32,Rt32):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpynac_RR_s1_sat __builtin_HEXAGON_M4_nac_up_s1_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=and(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andor_RR __builtin_HEXAGON_M4_or_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=and(Rs32,~Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andor_RnR __builtin_HEXAGON_M4_or_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=or(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_oror_RR __builtin_HEXAGON_M4_or_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=xor(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_xoror_RR __builtin_HEXAGON_M4_or_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=pmpyw(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_pmpyw_RR __builtin_HEXAGON_M4_pmpyw
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=pmpyw(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_pmpywxacc_RR __builtin_HEXAGON_M4_pmpyw_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vpmpyh(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vpmpyh_RR __builtin_HEXAGON_M4_vpmpyh
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=vpmpyh(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vpmpyhxacc_RR __builtin_HEXAGON_M4_vpmpyh_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpyweh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpywehacc_PP __builtin_HEXAGON_M4_vrmpyeh_acc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpyweh(Rss32,Rtt32):<<1
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpywehacc_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_acc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpyweh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpyweh_PP __builtin_HEXAGON_M4_vrmpyeh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpyweh(Rss32,Rtt32):<<1
+   C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpyweh_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpywoh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpywohacc_PP __builtin_HEXAGON_M4_vrmpyoh_acc_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpywoh(Rss32,Rtt32):<<1
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpywohacc_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_acc_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpywoh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpywoh_PP __builtin_HEXAGON_M4_vrmpyoh_s0
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpywoh(Rss32,Rtt32):<<1
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpywoh_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_s1
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=and(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andxacc_RR __builtin_HEXAGON_M4_xor_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=and(Rs32,~Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andxacc_RnR __builtin_HEXAGON_M4_xor_andn
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=or(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_orxacc_RR __builtin_HEXAGON_M4_xor_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=xor(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_xorxacc_PP __builtin_HEXAGON_M4_xor_xacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vdmpybsu(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vdmpybsuacc_PP_sat __builtin_HEXAGON_M5_vdmacbsu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vdmpybsu(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vdmpybsu_PP_sat __builtin_HEXAGON_M5_vdmpybsu
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpybsu(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpybsuacc_RR __builtin_HEXAGON_M5_vmacbsu
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vmpybu(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpybuacc_RR __builtin_HEXAGON_M5_vmacbuu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpybsu(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpybsu_RR __builtin_HEXAGON_M5_vmpybsu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vmpybu(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vmpybu_RR __builtin_HEXAGON_M5_vmpybuu
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpybsu(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpybsuacc_PP __builtin_HEXAGON_M5_vrmacbsu
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrmpybu(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpybuacc_PP __builtin_HEXAGON_M5_vrmacbuu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpybsu(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpybsu_PP __builtin_HEXAGON_M5_vrmpybsu
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrmpybu(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrmpybu_PP __builtin_HEXAGON_M5_vrmpybuu
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=addasl(Rt32,Rs32,#u3)
+   C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_addasl_RRI __builtin_HEXAGON_S2_addasl_rrri
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=asl(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asl_PI __builtin_HEXAGON_S2_asl_i_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=asl(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslacc_PI __builtin_HEXAGON_S2_asl_i_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=asl(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asland_PI __builtin_HEXAGON_S2_asl_i_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=asl(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslnac_PI __builtin_HEXAGON_S2_asl_i_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=asl(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslor_PI __builtin_HEXAGON_S2_asl_i_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=asl(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslxacc_PI __builtin_HEXAGON_S2_asl_i_p_xacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asl(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asl_RI __builtin_HEXAGON_S2_asl_i_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=asl(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslacc_RI __builtin_HEXAGON_S2_asl_i_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=asl(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asland_RI __builtin_HEXAGON_S2_asl_i_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=asl(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslnac_RI __builtin_HEXAGON_S2_asl_i_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=asl(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslor_RI __builtin_HEXAGON_S2_asl_i_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asl(Rs32,#u5):sat
+   C Intrinsic Prototype: Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asl_RI_sat __builtin_HEXAGON_S2_asl_i_r_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=asl(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslxacc_RI __builtin_HEXAGON_S2_asl_i_r_xacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaslh(Rss32,#u4)
+   C Intrinsic Prototype: Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaslh_PI __builtin_HEXAGON_S2_asl_i_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaslw(Rss32,#u5)
+   C Intrinsic Prototype: Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaslw_PI __builtin_HEXAGON_S2_asl_i_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=asl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asl_PR __builtin_HEXAGON_S2_asl_r_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=asl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslacc_PR __builtin_HEXAGON_S2_asl_r_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=asl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asland_PR __builtin_HEXAGON_S2_asl_r_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=asl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslnac_PR __builtin_HEXAGON_S2_asl_r_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=asl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslor_PR __builtin_HEXAGON_S2_asl_r_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=asl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_aslxacc_PR __builtin_HEXAGON_S2_asl_r_p_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asl_RR __builtin_HEXAGON_S2_asl_r_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=asl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslacc_RR __builtin_HEXAGON_S2_asl_r_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=asl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asland_RR __builtin_HEXAGON_S2_asl_r_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=asl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslnac_RR __builtin_HEXAGON_S2_asl_r_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=asl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_aslor_RR __builtin_HEXAGON_S2_asl_r_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asl(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asl_RR_sat __builtin_HEXAGON_S2_asl_r_r_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaslh(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaslh_PR __builtin_HEXAGON_S2_asl_r_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vaslw(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vaslw_PR __builtin_HEXAGON_S2_asl_r_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=asr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asr_PI __builtin_HEXAGON_S2_asr_i_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=asr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asracc_PI __builtin_HEXAGON_S2_asr_i_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=asr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asrand_PI __builtin_HEXAGON_S2_asr_i_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=asr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asrnac_PI __builtin_HEXAGON_S2_asr_i_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=asr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asror_PI __builtin_HEXAGON_S2_asr_i_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=asr(Rss32,#u6):rnd
+   C Intrinsic Prototype: Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asr_PI_rnd __builtin_HEXAGON_S2_asr_i_p_rnd
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=asrrnd(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_asrrnd_PI __builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asr_RI __builtin_HEXAGON_S2_asr_i_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=asr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asracc_RI __builtin_HEXAGON_S2_asr_i_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=asr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asrand_RI __builtin_HEXAGON_S2_asr_i_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=asr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asrnac_RI __builtin_HEXAGON_S2_asr_i_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=asr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asror_RI __builtin_HEXAGON_S2_asr_i_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asr(Rs32,#u5):rnd
+   C Intrinsic Prototype: Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asr_RI_rnd __builtin_HEXAGON_S2_asr_i_r_rnd
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asrrnd(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_asrrnd_RI __builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vasrw(Rss32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vasrw_PI __builtin_HEXAGON_S2_asr_i_svw_trun
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vasrh(Rss32,#u4)
+   C Intrinsic Prototype: Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vasrh_PI __builtin_HEXAGON_S2_asr_i_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vasrw(Rss32,#u5)
+   C Intrinsic Prototype: Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vasrw_PI __builtin_HEXAGON_S2_asr_i_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=asr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asr_PR __builtin_HEXAGON_S2_asr_r_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=asr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asracc_PR __builtin_HEXAGON_S2_asr_r_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=asr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asrand_PR __builtin_HEXAGON_S2_asr_r_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=asr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asrnac_PR __builtin_HEXAGON_S2_asr_r_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=asr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asror_PR __builtin_HEXAGON_S2_asr_r_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=asr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_asrxacc_PR __builtin_HEXAGON_S2_asr_r_p_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asr_RR __builtin_HEXAGON_S2_asr_r_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=asr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asracc_RR __builtin_HEXAGON_S2_asr_r_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=asr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asrand_RR __builtin_HEXAGON_S2_asr_r_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=asr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asrnac_RR __builtin_HEXAGON_S2_asr_r_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=asr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asror_RR __builtin_HEXAGON_S2_asr_r_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=asr(Rs32,Rt32):sat
+   C Intrinsic Prototype: Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_asr_RR_sat __builtin_HEXAGON_S2_asr_r_r_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vasrw(Rss32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vasrw_PR __builtin_HEXAGON_S2_asr_r_svw_trun
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vasrh(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vasrh_PR __builtin_HEXAGON_S2_asr_r_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vasrw(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vasrw_PR __builtin_HEXAGON_S2_asr_r_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=brev(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_brev_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_brev_R __builtin_HEXAGON_S2_brev
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=brev(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_brev_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_brev_P __builtin_HEXAGON_S2_brevp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cl0(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_cl0_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cl0_R __builtin_HEXAGON_S2_cl0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cl0(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_cl0_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cl0_P __builtin_HEXAGON_S2_cl0p
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cl1(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_cl1_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cl1_R __builtin_HEXAGON_S2_cl1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cl1(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_cl1_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_cl1_P __builtin_HEXAGON_S2_cl1p
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=clb(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_clb_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_clb_R __builtin_HEXAGON_S2_clb
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=normamt(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_normamt_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_normamt_R __builtin_HEXAGON_S2_clbnorm
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=clb(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_clb_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_clb_P __builtin_HEXAGON_S2_clbp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=clrbit(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_clrbit_RI __builtin_HEXAGON_S2_clrbit_i
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=clrbit(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_clrbit_RR __builtin_HEXAGON_S2_clrbit_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=ct0(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_ct0_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_ct0_R __builtin_HEXAGON_S2_ct0
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=ct0(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_ct0_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_ct0_P __builtin_HEXAGON_S2_ct0p
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=ct1(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_ct1_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_ct1_R __builtin_HEXAGON_S2_ct1
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=ct1(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_ct1_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_ct1_P __builtin_HEXAGON_S2_ct1p
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=deinterleave(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_deinterleave_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_deinterleave_P __builtin_HEXAGON_S2_deinterleave
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=extractu(Rs32,#u5,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_extractu_RII __builtin_HEXAGON_S2_extractu
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=extractu(Rs32,Rtt32)
+   C Intrinsic Prototype: Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_extractu_RP __builtin_HEXAGON_S2_extractu_rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=extractu(Rss32,#u6,#U6)
+   C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_extractu_PII __builtin_HEXAGON_S2_extractup
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=extractu(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_extractu_PP __builtin_HEXAGON_S2_extractup_rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=insert(Rs32,#u5,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_insert_RII __builtin_HEXAGON_S2_insert
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=insert(Rs32,Rtt32)
+   C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_insert_RP __builtin_HEXAGON_S2_insert_rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=insert(Rss32,#u6,#U6)
+   C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_insert_PII __builtin_HEXAGON_S2_insertp
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32=insert(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_insert_PP __builtin_HEXAGON_S2_insertp_rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=interleave(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_interleave_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_interleave_P __builtin_HEXAGON_S2_interleave
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=lfs(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lfs_PP __builtin_HEXAGON_S2_lfsp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=lsl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsl_PR __builtin_HEXAGON_S2_lsl_r_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=lsl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lslacc_PR __builtin_HEXAGON_S2_lsl_r_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=lsl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsland_PR __builtin_HEXAGON_S2_lsl_r_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=lsl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lslnac_PR __builtin_HEXAGON_S2_lsl_r_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=lsl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lslor_PR __builtin_HEXAGON_S2_lsl_r_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=lsl(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lslxacc_PR __builtin_HEXAGON_S2_lsl_r_p_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=lsl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsl_RR __builtin_HEXAGON_S2_lsl_r_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=lsl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lslacc_RR __builtin_HEXAGON_S2_lsl_r_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=lsl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsland_RR __builtin_HEXAGON_S2_lsl_r_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=lsl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lslnac_RR __builtin_HEXAGON_S2_lsl_r_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=lsl(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lslor_RR __builtin_HEXAGON_S2_lsl_r_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vlslh(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vlslh_PR __builtin_HEXAGON_S2_lsl_r_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vlslw(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vlslw_PR __builtin_HEXAGON_S2_lsl_r_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=lsr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsr_PI __builtin_HEXAGON_S2_lsr_i_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=lsr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsracc_PI __builtin_HEXAGON_S2_lsr_i_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=lsr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsrand_PI __builtin_HEXAGON_S2_lsr_i_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=lsr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsrnac_PI __builtin_HEXAGON_S2_lsr_i_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=lsr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsror_PI __builtin_HEXAGON_S2_lsr_i_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=lsr(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsrxacc_PI __builtin_HEXAGON_S2_lsr_i_p_xacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=lsr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsr_RI __builtin_HEXAGON_S2_lsr_i_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=lsr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsracc_RI __builtin_HEXAGON_S2_lsr_i_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=lsr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsrand_RI __builtin_HEXAGON_S2_lsr_i_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=lsr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsrnac_RI __builtin_HEXAGON_S2_lsr_i_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=lsr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsror_RI __builtin_HEXAGON_S2_lsr_i_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=lsr(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsrxacc_RI __builtin_HEXAGON_S2_lsr_i_r_xacc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vlsrh(Rss32,#u4)
+   C Intrinsic Prototype: Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vlsrh_PI __builtin_HEXAGON_S2_lsr_i_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vlsrw(Rss32,#u5)
+   C Intrinsic Prototype: Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vlsrw_PI __builtin_HEXAGON_S2_lsr_i_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=lsr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsr_PR __builtin_HEXAGON_S2_lsr_r_p
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=lsr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsracc_PR __builtin_HEXAGON_S2_lsr_r_p_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=lsr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsrand_PR __builtin_HEXAGON_S2_lsr_r_p_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=lsr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsrnac_PR __builtin_HEXAGON_S2_lsr_r_p_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=lsr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsror_PR __builtin_HEXAGON_S2_lsr_r_p_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=lsr(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_lsrxacc_PR __builtin_HEXAGON_S2_lsr_r_p_xor
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=lsr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsr_RR __builtin_HEXAGON_S2_lsr_r_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=lsr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsracc_RR __builtin_HEXAGON_S2_lsr_r_r_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=lsr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsrand_RR __builtin_HEXAGON_S2_lsr_r_r_and
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=lsr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsrnac_RR __builtin_HEXAGON_S2_lsr_r_r_nac
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=lsr(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsror_RR __builtin_HEXAGON_S2_lsr_r_r_or
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vlsrh(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vlsrh_PR __builtin_HEXAGON_S2_lsr_r_vh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vlsrw(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vlsrw_PR __builtin_HEXAGON_S2_lsr_r_vw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=packhl(Rs32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU32_3op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_packhl_RR __builtin_HEXAGON_S2_packhl
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=parity(Rss32,Rtt32)
+   C Intrinsic Prototype: Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_parity_PP __builtin_HEXAGON_S2_parityp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=setbit(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_setbit_RI __builtin_HEXAGON_S2_setbit_i
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=setbit(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_setbit_RR __builtin_HEXAGON_S2_setbit_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=shuffeb(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_shuffeb_PP __builtin_HEXAGON_S2_shuffeb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=shuffeh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_shuffeh_PP __builtin_HEXAGON_S2_shuffeh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=shuffob(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_shuffob_PP __builtin_HEXAGON_S2_shuffob
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=shuffoh(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_shuffoh_PP __builtin_HEXAGON_S2_shuffoh
+
+/* ==========================================================================
+   Assembly Syntax:       memb(Rx32++#s4:0:circ(Mu2))=Rt32
+   C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memb_IMR_circ __builtin_HEXAGON_S2_storerb_pci
+
+/* ==========================================================================
+   Assembly Syntax:       memb(Rx32++I:circ(Mu2))=Rt32
+   C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memb_MR_circ __builtin_HEXAGON_S2_storerb_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       memd(Rx32++#s4:3:circ(Mu2))=Rtt32
+   C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memd_IMP_circ __builtin_HEXAGON_S2_storerd_pci
+
+/* ==========================================================================
+   Assembly Syntax:       memd(Rx32++I:circ(Mu2))=Rtt32
+   C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memd_MP_circ __builtin_HEXAGON_S2_storerd_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       memh(Rx32++#s4:1:circ(Mu2))=Rt32.h
+   C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memh_IMRh_circ __builtin_HEXAGON_S2_storerf_pci
+
+/* ==========================================================================
+   Assembly Syntax:       memh(Rx32++I:circ(Mu2))=Rt32.h
+   C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memh_MRh_circ __builtin_HEXAGON_S2_storerf_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       memh(Rx32++#s4:1:circ(Mu2))=Rt32
+   C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memh_IMR_circ __builtin_HEXAGON_S2_storerh_pci
+
+/* ==========================================================================
+   Assembly Syntax:       memh(Rx32++I:circ(Mu2))=Rt32
+   C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memh_MR_circ __builtin_HEXAGON_S2_storerh_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       memw(Rx32++#s4:2:circ(Mu2))=Rt32
+   C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memw_IMR_circ __builtin_HEXAGON_S2_storeri_pci
+
+/* ==========================================================================
+   Assembly Syntax:       memw(Rx32++I:circ(Mu2))=Rt32
+   C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
+   Instruction Type:      ST
+   Execution Slots:       SLOT01
+   ========================================================================== */
+
+#define Q6_memw_MR_circ __builtin_HEXAGON_S2_storeri_pcr
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsathb(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_vsathb_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsathb_R __builtin_HEXAGON_S2_svsathb
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsathub(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_vsathub_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsathub_R __builtin_HEXAGON_S2_svsathub
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=tableidxb(Rs32,#u4,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_tableidxb_RII __builtin_HEXAGON_S2_tableidxb_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=tableidxd(Rs32,#u4,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_tableidxd_RII __builtin_HEXAGON_S2_tableidxd_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=tableidxh(Rs32,#u4,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_tableidxh_RII __builtin_HEXAGON_S2_tableidxh_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=tableidxw(Rs32,#u4,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_tableidxw_RII __builtin_HEXAGON_S2_tableidxw_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=togglebit(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_togglebit_RI __builtin_HEXAGON_S2_togglebit_i
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=togglebit(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_togglebit_RR __builtin_HEXAGON_S2_togglebit_r
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=tstbit(Rs32,#u5)
+   C Intrinsic Prototype: Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_tstbit_RI __builtin_HEXAGON_S2_tstbit_i
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=tstbit(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_tstbit_RR __builtin_HEXAGON_S2_tstbit_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=valignb(Rtt32,Rss32,#u3)
+   C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_valignb_PPI __builtin_HEXAGON_S2_valignib
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=valignb(Rtt32,Rss32,Pu4)
+   C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_valignb_PPp __builtin_HEXAGON_S2_valignrb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vcnegh(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcnegh_PR __builtin_HEXAGON_S2_vcnegh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vcrotate(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vcrotate_PR __builtin_HEXAGON_S2_vcrotate
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcnegh(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcneghacc_PR __builtin_HEXAGON_S2_vrcnegh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vrndwh(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vrndwh_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vrndwh_P __builtin_HEXAGON_S2_vrndpackwh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vrndwh(Rss32):sat
+   C Intrinsic Prototype: Word32 Q6_R_vrndwh_P_sat(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vrndwh_P_sat __builtin_HEXAGON_S2_vrndpackwhs
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsathb(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vsathb_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsathb_P __builtin_HEXAGON_S2_vsathb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsathb(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsathb_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsathb_P __builtin_HEXAGON_S2_vsathb_nopack
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsathub(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vsathub_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsathub_P __builtin_HEXAGON_S2_vsathub
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsathub(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsathub_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsathub_P __builtin_HEXAGON_S2_vsathub_nopack
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsatwh(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vsatwh_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsatwh_P __builtin_HEXAGON_S2_vsatwh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsatwh(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsatwh_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsatwh_P __builtin_HEXAGON_S2_vsatwh_nopack
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsatwuh(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vsatwuh_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsatwuh(Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vsatwuh_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh_nopack
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vsplatb(Rs32)
+   C Intrinsic Prototype: Word32 Q6_R_vsplatb_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vsplatb_R __builtin_HEXAGON_S2_vsplatrb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsplath(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_vsplath_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsplath_R __builtin_HEXAGON_S2_vsplatrh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vspliceb(Rss32,Rtt32,#u3)
+   C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vspliceb_PPI __builtin_HEXAGON_S2_vspliceib
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vspliceb(Rss32,Rtt32,Pu4)
+   C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vspliceb_PPp __builtin_HEXAGON_S2_vsplicerb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsxtbh(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_vsxtbh_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsxtbh_R __builtin_HEXAGON_S2_vsxtbh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsxthw(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_vsxthw_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsxthw_R __builtin_HEXAGON_S2_vsxthw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vtrunehb(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vtrunehb_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vtrunehb_P __builtin_HEXAGON_S2_vtrunehb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vtrunewh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vtrunewh_PP __builtin_HEXAGON_S2_vtrunewh
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vtrunohb(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_vtrunohb_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vtrunohb_P __builtin_HEXAGON_S2_vtrunohb
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vtrunowh(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vtrunowh_PP __builtin_HEXAGON_S2_vtrunowh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vzxtbh(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_vzxtbh_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vzxtbh_R __builtin_HEXAGON_S2_vzxtbh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vzxthw(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_vzxthw_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vzxthw_R __builtin_HEXAGON_S2_vzxthw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rs32,add(Ru32,#s6))
+   C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_add_RRI __builtin_HEXAGON_S4_addaddi
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=add(#u8,asl(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_asl_IRI __builtin_HEXAGON_S4_addi_asl_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=add(#u8,lsr(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_lsr_IRI __builtin_HEXAGON_S4_addi_lsr_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=and(#u8,asl(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_and_asl_IRI __builtin_HEXAGON_S4_andi_asl_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=and(#u8,lsr(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_and_lsr_IRI __builtin_HEXAGON_S4_andi_lsr_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(clb(Rs32),#s6)
+   C Intrinsic Prototype: Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_clb_RI __builtin_HEXAGON_S4_clbaddi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(clb(Rss32),#s6)
+   C Intrinsic Prototype: Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_clb_PI __builtin_HEXAGON_S4_clbpaddi
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=normamt(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_normamt_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_normamt_P __builtin_HEXAGON_S4_clbpnorm
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=extract(Rs32,#u5,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_extract_RII __builtin_HEXAGON_S4_extract
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=extract(Rs32,Rtt32)
+   C Intrinsic Prototype: Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_extract_RP __builtin_HEXAGON_S4_extract_rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=extract(Rss32,#u6,#U6)
+   C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_extract_PII __builtin_HEXAGON_S4_extractp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=extract(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_extract_PP __builtin_HEXAGON_S4_extractp_rp
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=lsl(#s6,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_lsl_IR __builtin_HEXAGON_S4_lsli
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!tstbit(Rs32,#u5)
+   C Intrinsic Prototype: Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_tstbit_RI __builtin_HEXAGON_S4_ntstbit_i
+
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!tstbit(Rs32,Rt32)
+   C Intrinsic Prototype: Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_tstbit_RR __builtin_HEXAGON_S4_ntstbit_r
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=and(Rs32,#s10)
+   C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_andor_RI __builtin_HEXAGON_S4_or_andi
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=or(Ru32,and(Rx32,#s10))
+   C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_or_and_RRI __builtin_HEXAGON_S4_or_andix
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=or(Rs32,#s10)
+   C Intrinsic Prototype: Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_oror_RI __builtin_HEXAGON_S4_or_ori
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=or(#u8,asl(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_or_asl_IRI __builtin_HEXAGON_S4_ori_asl_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=or(#u8,lsr(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_or_lsr_IRI __builtin_HEXAGON_S4_ori_lsr_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=parity(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_parity_RR __builtin_HEXAGON_S4_parity
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=add(Rs32,sub(#s6,Ru32))
+   C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_add_sub_RIR __builtin_HEXAGON_S4_subaddi
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=sub(#u8,asl(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_asl_IRI __builtin_HEXAGON_S4_subi_asl_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rx32=sub(#u8,lsr(Rx32,#U5))
+   C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_sub_lsr_IRI __builtin_HEXAGON_S4_subi_lsr_ri
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vrcrotate(Rss32,Rt32,#u2)
+   C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcrotate_PRI __builtin_HEXAGON_S4_vrcrotate
+
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vrcrotate(Rss32,Rt32,#u2)
+   C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vrcrotateacc_PRI __builtin_HEXAGON_S4_vrcrotate_acc
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vxaddsubh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vxaddsubh_PP_sat __builtin_HEXAGON_S4_vxaddsubh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vxaddsubh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxaddsubhr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vxaddsubw(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vxaddsubw_PP_sat __builtin_HEXAGON_S4_vxaddsubw
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vxsubaddh(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vxsubaddh_PP_sat __builtin_HEXAGON_S4_vxsubaddh
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat
+   C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vxsubaddh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxsubaddhr
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vxsubaddw(Rss32,Rtt32):sat
+   C Intrinsic Prototype: Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vxsubaddw_PP_sat __builtin_HEXAGON_S4_vxsubaddw
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vasrhub(Rss32,#u4):rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_R_vasrhub_PI_rnd_sat __builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=vasrhub(Rss32,#u4):sat
+   C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_vasrhub_PI_sat __builtin_HEXAGON_S5_asrhub_sat
+
+/* ==========================================================================
+   Assembly Syntax:       Rd32=popcount(Rss32)
+   C Intrinsic Prototype: Word32 Q6_R_popcount_P(Word64 Rss)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_popcount_P __builtin_HEXAGON_S5_popcountp
+
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vasrh(Rss32,#u4):rnd
+   C Intrinsic Prototype: Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_P_vasrh_PI_rnd __builtin_HEXAGON_S5_vasrhrnd_goodsyntax
+
+/* ==========================================================================
+   Assembly Syntax:       dccleana(Rs32)
+   C Intrinsic Prototype: void Q6_dccleana_A(Address Rs)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dccleana_A __builtin_HEXAGON_Y2_dccleana
+
+/* ==========================================================================
+   Assembly Syntax:       dccleaninva(Rs32)
+   C Intrinsic Prototype: void Q6_dccleaninva_A(Address Rs)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dccleaninva_A __builtin_HEXAGON_Y2_dccleaninva
+
+/* ==========================================================================
+   Assembly Syntax:       dcfetch(Rs32)
+   C Intrinsic Prototype: void Q6_dcfetch_A(Address Rs)
+   Instruction Type:      MAPPING
+   Execution Slots:       SLOT0123
+   ========================================================================== */
+
+#define Q6_dcfetch_A __builtin_HEXAGON_Y2_dcfetch
+
+/* ==========================================================================
+   Assembly Syntax:       dcinva(Rs32)
+   C Intrinsic Prototype: void Q6_dcinva_A(Address Rs)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dcinva_A __builtin_HEXAGON_Y2_dcinva
+
+/* ==========================================================================
+   Assembly Syntax:       dczeroa(Rs32)
+   C Intrinsic Prototype: void Q6_dczeroa_A(Address Rs)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa
+
+/* ==========================================================================
+   Assembly Syntax:       l2fetch(Rs32,Rt32)
+   C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_l2fetch_AR __builtin_HEXAGON_Y4_l2fetch
+
+/* ==========================================================================
+   Assembly Syntax:       l2fetch(Rs32,Rtt32)
+   C Intrinsic Prototype: void Q6_l2fetch_AP(Address Rs, Word64 Rtt)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_l2fetch_AP __builtin_HEXAGON_Y5_l2fetch
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=rol(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_rol_PI __builtin_HEXAGON_S6_rol_i_p
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=rol(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_rolacc_PI __builtin_HEXAGON_S6_rol_i_p_acc
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rxx32&=rol(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_roland_PI __builtin_HEXAGON_S6_rol_i_p_and
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rxx32-=rol(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_rolnac_PI __builtin_HEXAGON_S6_rol_i_p_nac
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rxx32|=rol(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_rolor_PI __builtin_HEXAGON_S6_rol_i_p_or
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rxx32^=rol(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_rolxacc_PI __builtin_HEXAGON_S6_rol_i_p_xacc
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rd32=rol(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_rol_RI __builtin_HEXAGON_S6_rol_i_r
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rx32+=rol(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_rolacc_RI __builtin_HEXAGON_S6_rol_i_r_acc
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rx32&=rol(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_roland_RI __builtin_HEXAGON_S6_rol_i_r_and
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=rol(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_rolnac_RI __builtin_HEXAGON_S6_rol_i_r_nac
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rx32|=rol(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_rolor_RI __builtin_HEXAGON_S6_rol_i_r_or
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 60
+/* ==========================================================================
+   Assembly Syntax:       Rx32^=rol(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_rolxacc_RI __builtin_HEXAGON_S6_rol_i_r_xacc
+#endif /* __HEXAGON_ARCH___ >= 60 */
+
+#if __HEXAGON_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsdiffb(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsdiffb_PP __builtin_HEXAGON_M6_vabsdiffb
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HEXAGON_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vabsdiffub(Rtt32,Rss32)
+   C Intrinsic Prototype: Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vabsdiffub_PP __builtin_HEXAGON_M6_vabsdiffub
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HEXAGON_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vsplatb(Rs32)
+   C Intrinsic Prototype: Word64 Q6_P_vsplatb_R(Word32 Rs)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vsplatb_R __builtin_HEXAGON_S6_vsplatrbp
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HEXAGON_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vtrunehb(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vtrunehb_PP __builtin_HEXAGON_S6_vtrunehb_ppp
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HEXAGON_ARCH__ >= 62
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vtrunohb(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vtrunohb_PP __builtin_HEXAGON_S6_vtrunohb_ppp
+#endif /* __HEXAGON_ARCH___ >= 62 */
+
+#if __HEXAGON_ARCH__ >= 65
+/* ==========================================================================
+   Assembly Syntax:       Pd4=!any8(vcmpb.eq(Rss32,Rtt32))
+   C Intrinsic Prototype: Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      ALU64
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_p_not_any8_vcmpb_eq_PP __builtin_HEXAGON_A6_vcmpbeq_notany
+#endif /* __HEXAGON_ARCH___ >= 65 */
+
+#if __HEXAGON_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfadd(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfadd_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfadd_PP __builtin_HEXAGON_F2_dfadd
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HEXAGON_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfsub(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfsub_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfsub_PP __builtin_HEXAGON_F2_dfsub
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HEXAGON_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Rx32-=mpyi(Rs32,Rt32)
+   C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mpyinac_RR __builtin_HEXAGON_M2_mnaci
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HEXAGON_ARCH__ >= 66
+/* ==========================================================================
+   Assembly Syntax:       Rd32=mask(#u5,#U5)
+   C Intrinsic Prototype: Word32 Q6_R_mask_II(Word32 Iu5, Word32 IU5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_mask_II __builtin_HEXAGON_S2_mask
+#endif /* __HEXAGON_ARCH___ >= 66 */
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=clip(Rs32,#u5)
+   C Intrinsic Prototype: Word32 Q6_R_clip_RI(Word32 Rs, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_R_clip_RI __builtin_HEXAGON_A7_clip
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cround(Rss32,#u6)
+   C Intrinsic Prototype: Word64 Q6_P_cround_PI(Word64 Rss, Word32 Iu6)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cround_PI __builtin_HEXAGON_A7_croundd_ri
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cround(Rss32,Rt32)
+   C Intrinsic Prototype: Word64 Q6_P_cround_PR(Word64 Rss, Word32 Rt)
+   Instruction Type:      S_3op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_cround_PR __builtin_HEXAGON_A7_croundd_rr
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vclip(Rss32,#u5)
+   C Intrinsic Prototype: Word64 Q6_P_vclip_PI(Word64 Rss, Word32 Iu5)
+   Instruction Type:      S_2op
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_vclip_PI __builtin_HEXAGON_A7_vclip
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfmax(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfmax_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmax_PP __builtin_HEXAGON_F2_dfmax
+#endif /* __HEXAGON_ARCH___ >= 67 */
+
+#if __HEXAGON_ARCH__ >= 67
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfmin(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfmin_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmin_PP __builtin_HEXAGON_F2_dfmin
+#endif /* __HEXAGON_ARCH___ >= 67 */
+
+#if __HEXAGON_ARCH__ >= 67
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfmpyfix(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfmpyfix_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmpyfix_PP __builtin_HEXAGON_F2_dfmpyfix
+#endif /* __HEXAGON_ARCH___ >= 67 */
+
+#if __HEXAGON_ARCH__ >= 67
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=dfmpyhh(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmpyhhacc_PP __builtin_HEXAGON_F2_dfmpyhh
+#endif /* __HEXAGON_ARCH___ >= 67 */
+
+#if __HEXAGON_ARCH__ >= 67
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=dfmpylh(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmpylhacc_PP __builtin_HEXAGON_F2_dfmpylh
+#endif /* __HEXAGON_ARCH___ >= 67 */
+
+#if __HEXAGON_ARCH__ >= 67
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=dfmpyll(Rss32,Rtt32)
+   C Intrinsic Prototype: Float64 Q6_P_dfmpyll_PP(Float64 Rss, Float64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT23
+   ========================================================================== */
+
+#define Q6_P_dfmpyll_PP __builtin_HEXAGON_F2_dfmpyll
+#endif /* __HEXAGON_ARCH___ >= 67 */
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpyiw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyiw_PP __builtin_HEXAGON_M7_dcmpyiw
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpyiw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyiwacc_PP __builtin_HEXAGON_M7_dcmpyiw_acc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpyiw(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP_conj(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyiw_PP_conj __builtin_HEXAGON_M7_dcmpyiwc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpyiw(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyiwacc_PP_conj __builtin_HEXAGON_M7_dcmpyiwc_acc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpyrw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyrw_PP __builtin_HEXAGON_M7_dcmpyrw
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpyrw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyrwacc_PP __builtin_HEXAGON_M7_dcmpyrw_acc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=cmpyrw(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP_conj(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyrw_PP_conj __builtin_HEXAGON_M7_dcmpyrwc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=cmpyrw(Rss32,Rtt32*)
+   C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_cmpyrwacc_PP_conj __builtin_HEXAGON_M7_dcmpyrwc_acc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rdd32=vdmpyw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vdmpyw_PP(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_vdmpyw_PP __builtin_HEXAGON_M7_vdmpy
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rxx32+=vdmpyw(Rss32,Rtt32)
+   C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_P_vdmpywacc_PP __builtin_HEXAGON_M7_vdmpy_acc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyiw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyiw
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyiw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiw_rnd
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyiw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyiwc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyiw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiwc_rnd
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyrw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyrw
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyrw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrw_rnd
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyrw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyrwc
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
+/* ==========================================================================
+   Assembly Syntax:       Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
+   Instruction Type:      M
+   Execution Slots:       SLOT3
+   ========================================================================== */
+
+#define Q6_R_cmpyrw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrwc_rnd
+#endif /* __HEXAGON_ARCH___ >= 67  && defined __HEXAGON_AUDIO__*/
+
+#if __HEXAGON_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       dmlink(Rs32,Rt32)
+   C Intrinsic Prototype: void Q6_dmlink_AA(Address Rs, Address Rt)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dmlink_AA __builtin_HEXAGON_Y6_dmlink
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HEXAGON_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Rd32=dmpause
+   C Intrinsic Prototype: Word32 Q6_R_dmpause()
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_R_dmpause __builtin_HEXAGON_Y6_dmpause
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HEXAGON_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Rd32=dmpoll
+   C Intrinsic Prototype: Word32 Q6_R_dmpoll()
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_R_dmpoll __builtin_HEXAGON_Y6_dmpoll
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HEXAGON_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       dmresume(Rs32)
+   C Intrinsic Prototype: void Q6_dmresume_A(Address Rs)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dmresume_A __builtin_HEXAGON_Y6_dmresume
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HEXAGON_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       dmstart(Rs32)
+   C Intrinsic Prototype: void Q6_dmstart_A(Address Rs)
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_dmstart_A __builtin_HEXAGON_Y6_dmstart
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#if __HEXAGON_ARCH__ >= 68
+/* ==========================================================================
+   Assembly Syntax:       Rd32=dmwait
+   C Intrinsic Prototype: Word32 Q6_R_dmwait()
+   Instruction Type:      ST
+   Execution Slots:       SLOT0
+   ========================================================================== */
+
+#define Q6_R_dmwait __builtin_HEXAGON_Y6_dmwait
+#endif /* __HEXAGON_ARCH___ >= 68 */
+
+#include <hexagon_circ_brev_intrinsics.h>
+#ifdef __HVX__
+#include <hvx_hexagon_protos.h>
+#endif /* __HVX__ */
+#endif
diff --git a/crates/stdarch-gen-hexagon-scalar/src/main.rs b/crates/stdarch-gen-hexagon-scalar/src/main.rs
new file mode 100644
index 0000000000..bbe28174ff
--- /dev/null
+++ b/crates/stdarch-gen-hexagon-scalar/src/main.rs
@@ -0,0 +1,672 @@
+//! Hexagon Scalar Code Generator
+//!
+//! This generator creates scalar.rs from the LLVM `hexagon_protos.h` header file.
+//! It parses the C intrinsic prototypes and generates Rust wrapper functions
+//! with appropriate attributes for all scalar (non-HVX) Hexagon intrinsics.
+//!
+//! The generated module provides ~901 scalar intrinsic wrappers covering:
+//! - Arithmetic, multiply, shift, saturate operations
+//! - Compare, floating-point, and other scalar operations
+//!
+//! Intrinsics with `void*`/`void**` parameters (circular-addressing) are skipped
+//! because they have no corresponding LLVM intrinsic.
+//!
+//! Usage:
+//!     cd crates/stdarch-gen-hexagon-scalar
+//!     cargo run
+//!     # Output is written to ../core_arch/src/hexagon/scalar.rs
+
+use regex::Regex;
+use std::collections::HashMap;
+use std::fs::File;
+use std::io::Write;
+use std::path::Path;
+
+/// Extract the instruction mnemonic from the assembly syntax string.
+///
+/// Examples:
+/// - `Rd32=abs(Rs32)` → Some("abs")
+/// - `Rd32=add(Rs32,Rt32):sat` → Some("add")
+/// - `Rx32+=mpy(Rs32,Rt32)` → Some("mpy")
+/// - `Rd32=dmpause` → Some("dmpause")
+/// - `dmlink(Rs32,Rt32)` → Some("dmlink")
+/// - `Rd32=Rs32` → None (simple transfer)
+/// - `Rx32.h=#u16` → None (immediate load)
+/// - `Rdd32=#s8` → None (immediate load)
+fn extract_instr_name(asm_syntax: &str) -> Option<String> {
+    // Find the operator: +=, -=, or =
+    let after_op = if let Some(pos) = asm_syntax.find("+=") {
+        &asm_syntax[pos + 2..]
+    } else if let Some(pos) = asm_syntax.find("-=") {
+        &asm_syntax[pos + 2..]
+    } else if let Some(pos) = asm_syntax.find('=') {
+        &asm_syntax[pos + 1..]
+    } else {
+        // No assignment operator: try function-call-style syntax like "dmlink(Rs32,Rt32)".
+        // The mnemonic is the leading lowercase identifier.
+        return extract_leading_mnemonic(asm_syntax);
+    };
+
+    // After the operator, we expect a lowercase letter starting the mnemonic.
+    // Skip if it starts with uppercase (register name like Rs32) or # (immediate).
+    extract_leading_mnemonic(after_op)
+}
+
+/// Extract a leading lowercase mnemonic from the given string.
+///
+/// Returns `Some(mnemonic)` if the string starts with a lowercase ASCII letter,
+/// collecting all subsequent alphanumeric/underscore characters. Returns `None`
+/// if the string is empty or starts with an uppercase letter, `#`, etc.
+fn extract_leading_mnemonic(s: &str) -> Option<String> {
+    let first_char = s.chars().next()?;
+    if !first_char.is_ascii_lowercase() {
+        return None;
+    }
+    let mnemonic: String = s
+        .chars()
+        .take_while(|c| c.is_ascii_alphanumeric() || *c == '_')
+        .collect();
+    if mnemonic.is_empty() {
+        None
+    } else {
+        Some(mnemonic)
+    }
+}
+
+/// The tracking issue number for the stdarch_hexagon feature
+const TRACKING_ISSUE: &str = "151523";
+
+/// LLVM version the header file is from (for reference)
+const LLVM_VERSION: &str = "22.1.0";
+
+/// Local header file path (checked into the repository)
+const HEADER_FILE: &str = "hexagon_protos.h";
+
+/// Rust type representation for scalar intrinsics
+#[derive(Debug, Clone, PartialEq)]
+enum RustType {
+    I32,
+    I64,
+    F32,
+    F64,
+    Unit,
+}
+
+impl RustType {
+    fn from_c_type(c_type: &str) -> Option<Self> {
+        match c_type.trim() {
+            "Word32" | "UWord32" | "Byte" | "Address" => Some(RustType::I32),
+            "Word64" | "UWord64" => Some(RustType::I64),
+            "Float32" => Some(RustType::F32),
+            "Float64" => Some(RustType::F64),
+            "void" => Some(RustType::Unit),
+            _ => None,
+        }
+    }
+
+    fn to_rust_str(&self) -> &'static str {
+        match self {
+            RustType::I32 => "i32",
+            RustType::I64 => "i64",
+            RustType::F32 => "f32",
+            RustType::F64 => "f64",
+            RustType::Unit => "()",
+        }
+    }
+}
+
+/// Information about an immediate operand parameter.
+///
+/// Detected from C prototype parameter names like `Is16` (signed 16-bit),
+/// `Iu5` (unsigned 5-bit), `IU5` (unsigned 5-bit secondary), `Iu6_2`
+/// (unsigned 6-bit with 2-bit alignment).
+#[derive(Debug, Clone)]
+struct ImmediateInfo {
+    /// Whether this is a signed immediate
+    signed: bool,
+    /// Number of bits in the immediate field
+    bits: u32,
+}
+
+/// Arch guard for an intrinsic
+#[derive(Debug, Clone, PartialEq)]
+enum ArchGuard {
+    /// No guard (base v5/v55 intrinsics)
+    None,
+    /// `#if __HEXAGON_ARCH__ >= N`
+    Arch(u32),
+    /// `#if __HEXAGON_ARCH__ >= N && defined __HEXAGON_AUDIO__`
+    ArchAudio(u32),
+}
+
+impl ArchGuard {
+    /// Returns a doc comment describing the required architecture version,
+    /// or None if no specific version is needed.
+    fn requires_doc(&self) -> Option<String> {
+        match self {
+            ArchGuard::None => Option::None,
+            ArchGuard::Arch(ver) => Some(format!("Requires: V{}", ver)),
+            ArchGuard::ArchAudio(ver) => Some(format!("Requires: V{}, Audio", ver)),
+        }
+    }
+
+    /// Returns a `#[cfg_attr(target_arch = "hexagon", target_feature(enable = "..."))]`
+    /// attribute string, or None for base intrinsics that have no user-facing feature gate.
+    fn target_feature_attr(&self) -> Option<String> {
+        match self {
+            ArchGuard::None => None,
+            ArchGuard::Arch(ver) => Some(format!(
+                "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"v{}\"))]",
+                ver
+            )),
+            ArchGuard::ArchAudio(ver) => Some(format!(
+                "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"v{},audio\"))]",
+                ver
+            )),
+        }
+    }
+}
+
+/// Parsed scalar intrinsic information
+#[derive(Debug, Clone)]
+struct ScalarIntrinsic {
+    /// Q6 name (e.g., "Q6_R_add_RR")
+    q6_name: String,
+    /// Builtin suffix (e.g., "A2_add") - from __builtin_HEXAGON_A2_add
+    builtin_name: String,
+    /// Assembly syntax
+    asm_syntax: String,
+    /// Instruction type
+    instr_type: String,
+    /// Execution slots
+    exec_slots: String,
+    /// Return type
+    return_type: RustType,
+    /// Parameters (name, type, optional immediate info)
+    params: Vec<(String, RustType, Option<ImmediateInfo>)>,
+    /// Architecture guard
+    arch_guard: ArchGuard,
+}
+
+impl ScalarIntrinsic {
+    /// Generate the LLVM link name: A2_add -> llvm.hexagon.A2.add
+    fn llvm_link_name(&self) -> String {
+        format!("llvm.hexagon.{}", self.builtin_name.replace('_', "."))
+    }
+
+    /// Generate the Rust function name: Q6_R_add_RR -> Q6_R_add_RR
+    ///
+    /// We preserve the original case because the Q6 naming convention uses
+    /// case to distinguish register types:
+    /// - `P` (uppercase) = 64-bit register pair (Word64)
+    /// - `p` (lowercase) = predicate register (Byte)
+    fn rust_fn_name(&self) -> String {
+        self.q6_name.clone()
+    }
+
+    /// Generate the extern function name: A2_add -> hexagon_A2_add
+    fn extern_fn_name(&self) -> String {
+        format!("hexagon_{}", self.builtin_name)
+    }
+}
+
+/// Read the local header file
+fn read_header(crate_dir: &Path) -> Result<String, String> {
+    let header_path = crate_dir.join(HEADER_FILE);
+    println!("Reading scalar header from: {}", header_path.display());
+    println!("  (LLVM version: {})", LLVM_VERSION);
+
+    std::fs::read_to_string(&header_path).map_err(|e| {
+        format!(
+            "Failed to read header file {}: {}",
+            header_path.display(),
+            e
+        )
+    })
+}
+
+/// Detect whether a C parameter name represents an immediate operand.
+///
+/// C prototype parameter names follow the pattern `I[usUS]\d+` for immediates:
+/// - `Is16` → signed 16-bit
+/// - `Iu5` → unsigned 5-bit
+/// - `IS8` → signed 8-bit (secondary)
+/// - `IU5` → unsigned 5-bit (secondary)
+/// - `Iu6_2` → unsigned 6-bit (with alignment suffix)
+fn detect_immediate(original_name: &str, imm_re: &Regex) -> Option<ImmediateInfo> {
+    imm_re.captures(original_name).map(|caps| {
+        let sign_char = &caps[1];
+        let bits: u32 = caps[2].parse().unwrap();
+        ImmediateInfo {
+            signed: sign_char == "s" || sign_char == "S",
+            bits,
+        }
+    })
+}
+
+/// Parse a C function prototype to extract return type and parameters
+fn parse_prototype(
+    prototype: &str,
+    proto_re: &Regex,
+    param_re: &Regex,
+    imm_re: &Regex,
+) -> Option<(RustType, Vec<(String, RustType, Option<ImmediateInfo>)>)> {
+    if let Some(caps) = proto_re.captures(prototype) {
+        let return_type_str = caps[1].trim();
+        let params_str = &caps[2];
+
+        // Skip if return type is unknown
+        let return_type = RustType::from_c_type(return_type_str)?;
+
+        let mut params = Vec::new();
+        if !params_str.trim().is_empty() {
+            let mut name_counts: HashMap<String, u32> = HashMap::new();
+            for param in params_str.split(',') {
+                let param = param.trim();
+                if let Some(pcaps) = param_re.captures(param) {
+                    let ptype_str = &pcaps[1];
+                    let original_name = &pcaps[2];
+                    let base_name = original_name.to_lowercase();
+
+                    // Skip intrinsics with void* or void** params
+                    if ptype_str.contains("void") {
+                        return None;
+                    }
+
+                    if let Some(ptype) = RustType::from_c_type(ptype_str) {
+                        // Detect immediate operands from the original C name
+                        let imm_info = detect_immediate(original_name, imm_re);
+
+                        // De-duplicate parameter names by appending a suffix
+                        let count = name_counts.entry(base_name.clone()).or_insert(0);
+                        *count += 1;
+                        let pname = if *count > 1 {
+                            format!("{}_{}", base_name, count)
+                        } else {
+                            base_name
+                        };
+                        params.push((pname, ptype, imm_info));
+                    } else {
+                        return None; // Unknown type
+                    }
+                }
+            }
+        }
+
+        Some((return_type, params))
+    } else {
+        None
+    }
+}
+
+/// Parse the header file to extract all scalar intrinsics
+fn parse_header(content: &str) -> Vec<ScalarIntrinsic> {
+    let mut intrinsics = Vec::new();
+
+    // Pre-compile all regexes once
+    let arch_guard_re = Regex::new(r"#if __HEXAGON_ARCH__ >= (\d+)(.*)").unwrap();
+    let q6_define_re = Regex::new(r"#define\s+(Q6_\w+)\s+__builtin_HEXAGON_(\w+)").unwrap();
+    let proto_re = Regex::new(r"(\w+)\s+Q6_\w+\(([^)]*)\)").unwrap();
+    let param_re = Regex::new(r"(\w+\*{0,2})\s+(\w+)").unwrap();
+    let imm_re = Regex::new(r"^I([uUsS])(\d+)").unwrap();
+
+    let lines: Vec<&str> = content.lines().collect();
+    let mut current_guard = ArchGuard::None;
+    let mut i = 0;
+
+    while i < lines.len() {
+        let line = lines[i].trim();
+
+        // Track #if guards
+        if let Some(caps) = arch_guard_re.captures(line) {
+            let arch_ver: u32 = caps[1].parse().unwrap_or(0);
+            let rest = &caps[2];
+            if rest.contains("__HEXAGON_AUDIO__") {
+                current_guard = ArchGuard::ArchAudio(arch_ver);
+            } else {
+                current_guard = ArchGuard::Arch(arch_ver);
+            }
+            i += 1;
+            continue;
+        }
+
+        // Track #endif to reset guard
+        if line.starts_with("#endif")
+            && !line.contains("__HEXAGON_PROTOS_H_")
+            && !line.contains("__HVX__")
+        {
+            current_guard = ArchGuard::None;
+            i += 1;
+            continue;
+        }
+
+        // Look for comment blocks with Assembly Syntax
+        if line.contains("Assembly Syntax:") {
+            let mut asm_syntax = String::new();
+            let mut prototype = String::new();
+            let mut instr_type = String::new();
+            let mut exec_slots = String::new();
+
+            // Parse the comment block
+            let mut j = i;
+            while j < lines.len() && !lines[j].trim().starts_with("#define") {
+                let cline = lines[j];
+                if cline.contains("Assembly Syntax:") {
+                    if let Some(pos) = cline.find("Assembly Syntax:") {
+                        asm_syntax = cline[pos + 16..].trim().to_string();
+                    }
+                } else if cline.contains("C Intrinsic Prototype:") {
+                    if let Some(pos) = cline.find("C Intrinsic Prototype:") {
+                        prototype = cline[pos + 22..].trim().to_string();
+                    }
+                } else if cline.contains("Instruction Type:") {
+                    if let Some(pos) = cline.find("Instruction Type:") {
+                        instr_type = cline[pos + 17..].trim().to_string();
+                    }
+                } else if cline.contains("Execution Slots:") {
+                    if let Some(pos) = cline.find("Execution Slots:") {
+                        exec_slots = cline[pos + 16..].trim().to_string();
+                    }
+                }
+                j += 1;
+            }
+
+            // Find the #define line
+            while j < lines.len() && !lines[j].trim().starts_with("#define") {
+                j += 1;
+            }
+
+            if j < lines.len() {
+                let define_line = lines[j];
+
+                if let Some(caps) = q6_define_re.captures(define_line) {
+                    let q6_name = caps[1].to_string();
+                    let builtin_name = caps[2].to_string();
+
+                    // Parse the C prototype
+                    if let Some((return_type, params)) =
+                        parse_prototype(&prototype, &proto_re, &param_re, &imm_re)
+                    {
+                        intrinsics.push(ScalarIntrinsic {
+                            q6_name,
+                            builtin_name,
+                            asm_syntax,
+                            instr_type,
+                            exec_slots,
+                            return_type,
+                            params,
+                            arch_guard: current_guard.clone(),
+                        });
+                    }
+                }
+            }
+            i = j + 1;
+            continue;
+        }
+
+        i += 1;
+    }
+
+    intrinsics
+}
+
+/// Generate the module documentation
+fn generate_module_doc() -> String {
+    r#"//! Hexagon scalar intrinsics
+//!
+//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations,
+//! including arithmetic, multiply, shift, saturate, compare, and floating-point
+//! operations.
+//!
+//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45)
+//!
+//! ## Naming Convention
+//!
+//! Function names preserve the original Q6 naming case because the convention
+//! uses case to distinguish register types:
+//! - `P` (uppercase) = 64-bit register pair (`Word64`)
+//! - `p` (lowercase) = predicate register (`Byte`)
+//!
+//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp`
+//! operates on predicate registers.
+//!
+//! ## Architecture Versions
+//!
+//! Most scalar intrinsics are available on all Hexagon architectures.
+//! Some intrinsics require specific architecture versions (v60, v62, v65,
+//! v66, v67, v68, or v67+audio) and carry
+//! `#[target_feature(enable = "v68")]` (or the appropriate version).
+//! Enable these with `-C target-feature=+v68` or by setting the target CPU
+//! via `-C target-cpu=hexagonv68`.
+//!
+//! Each version includes all features from previous versions.
+
+#![allow(non_snake_case)]
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+"#
+    .to_string()
+}
+
+/// Generate the extern block with LLVM intrinsic declarations
+fn generate_extern_block(intrinsics: &[ScalarIntrinsic]) -> String {
+    let mut output = String::new();
+
+    output.push_str("// LLVM intrinsic declarations for Hexagon scalar operations\n");
+    output.push_str("#[allow(improper_ctypes)]\n");
+    output.push_str("unsafe extern \"unadjusted\" {\n");
+
+    for info in intrinsics {
+        let link_name = info.llvm_link_name();
+        let fn_name = info.extern_fn_name();
+
+        let params_str = if info.params.is_empty() {
+            String::new()
+        } else {
+            info.params
+                .iter()
+                .map(|(_, t, _)| format!("_: {}", t.to_rust_str()))
+                .collect::<Vec<_>>()
+                .join(", ")
+        };
+
+        let return_str = if info.return_type == RustType::Unit {
+            String::new()
+        } else {
+            format!(" -> {}", info.return_type.to_rust_str())
+        };
+
+        output.push_str(&format!(
+            "    #[link_name = \"{}\"]\n    fn {}({}){return_str};\n",
+            link_name, fn_name, params_str
+        ));
+    }
+
+    output.push_str("}\n");
+    output
+}
+
+/// Generate wrapper functions for all intrinsics
+fn generate_functions(intrinsics: &[ScalarIntrinsic]) -> String {
+    let mut output = String::new();
+
+    for info in intrinsics {
+        let rust_name = info.rust_fn_name();
+        let extern_name = info.extern_fn_name();
+
+        // Collect immediate parameter info: (original_index, const_name, ImmediateInfo)
+        let imm_params: Vec<(usize, String, &ImmediateInfo)> = info
+            .params
+            .iter()
+            .enumerate()
+            .filter_map(|(i, (name, _, imm))| imm.as_ref().map(|im| (i, name.to_uppercase(), im)))
+            .collect();
+
+        // Doc comment
+        output.push_str(&format!("/// `{}`\n", info.asm_syntax));
+        output.push_str("///\n");
+        output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type));
+        output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots));
+        if let Some(req) = info.arch_guard.requires_doc() {
+            output.push_str(&format!("/// {}\n", req));
+        }
+
+        // Attributes
+        output.push_str("#[inline(always)]\n");
+        if let Some(tf_attr) = info.arch_guard.target_feature_attr() {
+            output.push_str(&format!("{}\n", tf_attr));
+        }
+
+        // Immediate parameters become const generics but are passed as positional
+        // arguments at the call site: Q6_R_add_RI(rs, 42) rather than Q6_R_add_RI::<42>(rs).
+        // This matches the assembly syntax where the immediate is an operand.
+        if !imm_params.is_empty() {
+            let indices: Vec<String> = imm_params.iter().map(|(i, _, _)| i.to_string()).collect();
+            output.push_str(&format!(
+                "#[rustc_legacy_const_generics({})]\n",
+                indices.join(", ")
+            ));
+        }
+
+        if let Some(instr) = extract_instr_name(&info.asm_syntax) {
+            if imm_params.is_empty() {
+                output.push_str(&format!("#[cfg_attr(test, assert_instr({}))]\n", instr));
+            } else {
+                // Provide default values for const generics in assert_instr
+                let defaults: Vec<String> = imm_params
+                    .iter()
+                    .map(|(_, name, _)| format!("{} = 0", name))
+                    .collect();
+                output.push_str(&format!(
+                    "#[cfg_attr(test, assert_instr({}, {}))]\n",
+                    instr,
+                    defaults.join(", ")
+                ));
+            }
+        }
+
+        output.push_str(&format!(
+            "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n",
+            TRACKING_ISSUE
+        ));
+
+        // Function signature: regular params exclude immediates, const generics added
+        let regular_params_str = info
+            .params
+            .iter()
+            .filter(|(_, _, imm)| imm.is_none())
+            .map(|(name, ty, _)| format!("{}: {}", name, ty.to_rust_str()))
+            .collect::<Vec<_>>()
+            .join(", ");
+
+        let return_str = if info.return_type == RustType::Unit {
+            String::new()
+        } else {
+            format!(" -> {}", info.return_type.to_rust_str())
+        };
+
+        if imm_params.is_empty() {
+            output.push_str(&format!(
+                "pub unsafe fn {}({}){} {{\n",
+                rust_name, regular_params_str, return_str
+            ));
+        } else {
+            let const_generics: Vec<String> = imm_params
+                .iter()
+                .map(|(_, name, imm)| {
+                    let ty = if imm.signed { "i32" } else { "u32" };
+                    format!("const {}: {}", name, ty)
+                })
+                .collect();
+            output.push_str(&format!(
+                "pub unsafe fn {}<{}>({}){} {{\n",
+                rust_name,
+                const_generics.join(", "),
+                regular_params_str,
+                return_str
+            ));
+        }
+
+        // Function body: static assertions then call
+        for (_, const_name, imm_info) in &imm_params {
+            if imm_info.signed {
+                output.push_str(&format!(
+                    "    static_assert_simm_bits!({}, {});\n",
+                    const_name, imm_info.bits
+                ));
+            } else {
+                output.push_str(&format!(
+                    "    static_assert_uimm_bits!({}, {});\n",
+                    const_name, imm_info.bits
+                ));
+            }
+        }
+
+        // Call args: use original order, using const generic names for immediates.
+        // Unsigned const generics (u32) need a cast to i32 for the extern call.
+        let args_str = info
+            .params
+            .iter()
+            .map(|(name, _, imm)| match imm {
+                Some(info) if !info.signed => format!("{} as i32", name.to_uppercase()),
+                Some(_) => name.to_uppercase(),
+                None => name.clone(),
+            })
+            .collect::<Vec<_>>()
+            .join(", ");
+
+        output.push_str(&format!("    {}({})\n", extern_name, args_str));
+        output.push_str("}\n\n");
+    }
+
+    output
+}
+
+/// Generate the complete scalar.rs file
+fn generate_scalar_file(intrinsics: &[ScalarIntrinsic], output_path: &Path) -> Result<(), String> {
+    let mut output =
+        File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?;
+
+    writeln!(output, "{}", generate_module_doc()).map_err(|e| e.to_string())?;
+    writeln!(output, "").map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_extern_block(intrinsics)).map_err(|e| e.to_string())?;
+    writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?;
+
+    // Flush before running rustfmt
+    drop(output);
+
+    // Run rustfmt on the generated file
+    let status = std::process::Command::new("rustfmt")
+        .arg(output_path)
+        .status()
+        .map_err(|e| format!("Failed to run rustfmt: {}", e))?;
+
+    if !status.success() {
+        return Err("rustfmt failed".to_string());
+    }
+
+    Ok(())
+}
+
+fn main() -> Result<(), String> {
+    println!("=== Hexagon Scalar Code Generator ===\n");
+
+    let crate_dir = std::env::var("CARGO_MANIFEST_DIR")
+        .map(std::path::PathBuf::from)
+        .unwrap_or_else(|_| std::env::current_dir().unwrap());
+
+    let header_content = read_header(&crate_dir)?;
+    println!("Read {} bytes", header_content.len());
+
+    let intrinsics = parse_header(&header_content);
+    println!("Parsed {} scalar intrinsics", intrinsics.len());
+
+    let hexagon_dir = crate_dir.join("../core_arch/src/hexagon");
+    let scalar_path = hexagon_dir.join("scalar.rs");
+
+    generate_scalar_file(&intrinsics, &scalar_path)?;
+    println!("Generated scalar.rs at {}", scalar_path.display());
+
+    Ok(())
+}
diff --git a/examples/gaussian.rs b/examples/gaussian.rs
index a310c24def..f41f753986 100644
--- a/examples/gaussian.rs
+++ b/examples/gaussian.rs
@@ -296,13 +296,14 @@ fn main() {
     // Run reference
     gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref);
 
-    // Verify HVX matches reference (allowing small rounding differences)
+    // Verify HVX matches reference (allowing small rounding differences).
+    use core_arch::arch::hexagon::scalar::{Q6_R_abs_R, Q6_R_max_RR};
     let mut max_diff = 0i32;
     for y in 1..HEIGHT - 1 {
         for x in 1..WIDTH - 1 {
             let idx = y * WIDTH + x;
-            let diff = (dst_hvx.0[idx] as i32 - dst_ref[idx] as i32).abs();
-            max_diff = max_diff.max(diff);
+            let diff = unsafe { Q6_R_abs_R(dst_hvx.0[idx] as i32 - dst_ref[idx] as i32) };
+            max_diff = unsafe { Q6_R_max_RR(max_diff, diff) };
             // Allow up to 1 LSB difference due to rounding
             assert!(
                 diff <= 1,

From b3be472acc14485bc7b3b946b46fce64974b257b Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Thu, 16 Apr 2026 15:22:10 +0100
Subject: [PATCH 252/326] Update arm_intrinsics.json

Most of the changes in the JSON were merged earlier in the SVE
intrinsics PR
---
 crates/intrinsic-test/missing_aarch64.txt    |   67 +-
 crates/intrinsic-test/missing_aarch64_be.txt |   65 +-
 crates/intrinsic-test/missing_arm.txt        |   49 +-
 crates/intrinsic-test/src/arm/compile.rs     |    2 +-
 crates/intrinsic-test/src/arm/config.rs      |    4 +-
 intrinsics_data/arm_intrinsics.json          | 9410 ++----------------
 6 files changed, 948 insertions(+), 8649 deletions(-)

diff --git a/crates/intrinsic-test/missing_aarch64.txt b/crates/intrinsic-test/missing_aarch64.txt
index 3c1ac59e91..f0c9eeb6ce 100644
--- a/crates/intrinsic-test/missing_aarch64.txt
+++ b/crates/intrinsic-test/missing_aarch64.txt
@@ -1,8 +1,14 @@
 # Not supported by qemu (will throw illegal instruction)
-vamax_f16
-vamaxq_f16
 vamin_f16
 vaminq_f16
+vamin_f32
+vaminq_f32
+vaminq_f64
+vamax_f16
+vamaxq_f16
+vamax_f32
+vamaxq_f32
+vamaxq_f64
 vscale_f16
 vscale_f32
 vscaleq_f16
@@ -37,39 +43,6 @@ vluti2q_laneq_s8
 vluti2q_laneq_u16
 vluti2q_laneq_u8
 vluti2q_lane_u8
-
-# Not implemented in stdarch yet
-vbfdot_f32
-vbfdot_lane_f32
-vbfdot_laneq_f32
-vbfdotq_f32
-vbfdotq_lane_f32
-vbfdotq_laneq_f32
-vbfmlalbq_f32
-vbfmlalbq_lane_f32
-vbfmlalbq_laneq_f32
-vbfmlaltq_f32
-vbfmlaltq_lane_f32
-vbfmlaltq_laneq_f32
-vbfmmlaq_f32
-
-
-# Implemented in stdarch, but missing in Clang.
-vrnd32xq_f64
-vrnd32zq_f64
-vrnd64xq_f64
-vrnd64zq_f64
-vamin_f32
-vaminq_f32
-vaminq_f64
-vamax_f32
-vamaxq_f32
-vamaxq_f64
-# LLVM select error, and missing in Clang.
-vrnd32x_f64
-vrnd32z_f64
-vrnd64x_f64
-vrnd64z_f64
 vluti4q_lane_f16_x2
 vluti4q_lane_p16_x2
 vluti4q_lane_p8
@@ -85,5 +58,27 @@ vluti4q_laneq_s8
 vluti4q_laneq_u16_x2
 vluti4q_laneq_u8
 
-# Broken in Clang
+# Not implemented in stdarch yet
+vcvtad_s32_f64
+vcvtad_u32_f64
+vcvtd_s32_f64
+vcvtd_u32_f64
+vcvtmd_s32_f64
+vcvtmd_u32_f64
+vcvtnd_s32_f64
+vcvtnd_u32_f64
+vcvtpd_s32_f64
+vcvtpd_u32_f64
+vcvts_s64_f32
+vcvts_u64_f32
+vcvtas_s64_f32
+vcvtas_u64_f32
+vcvtms_s64_f32
+vcvtms_u64_f32
+vcvtns_s64_f32
+vcvtns_u64_f32
+vcvtps_s64_f32
+vcvtps_u64_f32
+
+# Broken in Clang (fixed in https://github.com/llvm/llvm-project/pull/156029)
 vcvth_s16_f16
diff --git a/crates/intrinsic-test/missing_aarch64_be.txt b/crates/intrinsic-test/missing_aarch64_be.txt
index f3c4ffa3d0..9163aaa1c8 100644
--- a/crates/intrinsic-test/missing_aarch64_be.txt
+++ b/crates/intrinsic-test/missing_aarch64_be.txt
@@ -39,10 +39,16 @@ vusdotq_laneq_s32
 
 # Below are in common to missing_aarch64.txt
 # Not supported by qemu (will throw illegal instruction)
-vamax_f16
-vamaxq_f16
 vamin_f16
 vaminq_f16
+vamin_f32
+vaminq_f32
+vaminq_f64
+vamax_f16
+vamaxq_f16
+vamax_f32
+vamaxq_f32
+vamaxq_f64
 vscale_f16
 vscale_f32
 vscaleq_f16
@@ -77,39 +83,6 @@ vluti2q_laneq_s8
 vluti2q_laneq_u16
 vluti2q_laneq_u8
 vluti2q_lane_u8
-
-# Not implemented in stdarch yet
-vbfdot_f32
-vbfdot_lane_f32
-vbfdot_laneq_f32
-vbfdotq_f32
-vbfdotq_lane_f32
-vbfdotq_laneq_f32
-vbfmlalbq_f32
-vbfmlalbq_lane_f32
-vbfmlalbq_laneq_f32
-vbfmlaltq_f32
-vbfmlaltq_lane_f32
-vbfmlaltq_laneq_f32
-vbfmmlaq_f32
-
-
-# Implemented in stdarch, but missing in Clang.
-vrnd32xq_f64
-vrnd32zq_f64
-vrnd64xq_f64
-vrnd64zq_f64
-vamin_f32
-vaminq_f32
-vaminq_f64
-vamax_f32
-vamaxq_f32
-vamaxq_f64
-# LLVM select error, and missing in Clang.
-vrnd32x_f64
-vrnd32z_f64
-vrnd64x_f64
-vrnd64z_f64
 vluti4q_lane_f16_x2
 vluti4q_lane_p16_x2
 vluti4q_lane_p8
@@ -125,5 +98,27 @@ vluti4q_laneq_s8
 vluti4q_laneq_u16_x2
 vluti4q_laneq_u8
 
+# Not implemented in stdarch yet
+vcvtad_s32_f64
+vcvtad_u32_f64
+vcvtd_s32_f64
+vcvtd_u32_f64
+vcvtmd_s32_f64
+vcvtmd_u32_f64
+vcvtnd_s32_f64
+vcvtnd_u32_f64
+vcvtpd_s32_f64
+vcvtpd_u32_f64
+vcvts_s64_f32
+vcvts_u64_f32
+vcvtas_s64_f32
+vcvtas_u64_f32
+vcvtms_s64_f32
+vcvtms_u64_f32
+vcvtns_s64_f32
+vcvtns_u64_f32
+vcvtps_s64_f32
+vcvtps_u64_f32
+
 # Broken in Clang
 vcvth_s16_f16
diff --git a/crates/intrinsic-test/missing_arm.txt b/crates/intrinsic-test/missing_arm.txt
index 04c09a27d9..165b45d50c 100644
--- a/crates/intrinsic-test/missing_arm.txt
+++ b/crates/intrinsic-test/missing_arm.txt
@@ -1,18 +1,3 @@
-# Not implemented in stdarch yet
-vbfdot_f32
-vbfdot_lane_f32
-vbfdot_laneq_f32
-vbfdotq_f32
-vbfdotq_lane_f32
-vbfdotq_laneq_f32
-vbfmlalbq_f32
-vbfmlalbq_lane_f32
-vbfmlalbq_laneq_f32
-vbfmlaltq_f32
-vbfmlaltq_lane_f32
-vbfmlaltq_laneq_f32
-vbfmmlaq_f32
-
 # Implemented in Clang and stdarch for A64 only even though CSV claims A32 support
 vaddq_p64
 vbsl_p64
@@ -134,18 +119,6 @@ vcvth_f16_u32
 vcvth_u32_f16
 vcvth_n_f16_u32
 vcvth_n_u32_f16
-vcvtah_s32_f16
-vcvtah_u32_f16
-vcvtmh_s32_f16
-vcvtmh_u32_f16
-vcvtpq_s16_f16
-vcvtpq_u16_f16
-vcvtp_s16_f16
-vcvtp_u16_f16
-vcvtph_s32_f16
-vcvtph_u32_f16
-vcvtnh_u32_f16
-vcvtnh_s32_f16
 vfmlsl_low_f16
 vfmlslq_low_f16
 vfmlsl_high_f16
@@ -318,3 +291,25 @@ vcvta_s16_f16
 vcvta_u16_f16
 vceqz_f16
 vceqzq_f16
+vcvtah_s32_f16
+vcvtah_u32_f16
+vcvtmh_s32_f16
+vcvtmh_u32_f16
+vcvtpq_s16_f16
+vcvtpq_u16_f16
+vcvtp_s16_f16
+vcvtp_u16_f16
+vcvtph_s32_f16
+vcvtph_u32_f16
+vcvtnh_u32_f16
+vcvtnh_s32_f16
+
+# Missing in Clang
+vusdot_laneq_s32
+vsudot_laneq_s32
+vusdotq_laneq_s32
+vsudotq_laneq_s32
+vdot_laneq_s32
+vdot_laneq_u32
+vdotq_laneq_s32
+vdotq_laneq_u32
diff --git a/crates/intrinsic-test/src/arm/compile.rs b/crates/intrinsic-test/src/arm/compile.rs
index 7da35f9a11..a672da2cc0 100644
--- a/crates/intrinsic-test/src/arm/compile.rs
+++ b/crates/intrinsic-test/src/arm/compile.rs
@@ -15,7 +15,7 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
         .add_extra_flags(["-ffp-contract=off", "-Wno-narrowing"]);
 
     if !config.target.contains("v7") {
-        command = command.add_arch_flags(["faminmax", "lut", "sha3"]);
+        command = command.add_arch_flags(["faminmax", "lut", "sha3", "fp8"]);
     }
 
     if !cpp_compiler.contains("clang") {
diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index 85cb21c2d6..60bb0ca56c 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -58,7 +58,9 @@ pub const PLATFORM_RUST_CFGS: &str = r#"
 #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))]
 #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))]
 #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))]
-#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_aarch64_jscvt))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_feat_lut))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fp8))]
+#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(faminmax))]
 #![feature(fmt_helpers_for_derive)]
 #![feature(stdarch_neon_f16)]
 
diff --git a/intrinsics_data/arm_intrinsics.json b/intrinsics_data/arm_intrinsics.json
index 3a3b962a48..fab6da7f2c 100644
--- a/intrinsics_data/arm_intrinsics.json
+++ b/intrinsics_data/arm_intrinsics.json
@@ -35103,114 +35103,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svcntp_c16",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "uint64_t"
-    },
-    "Arguments_Preparation": {
-      "pnn": {
-        "register": "PNreg1.H"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "CNTP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svcntp_c32",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "uint64_t"
-    },
-    "Arguments_Preparation": {
-      "pnn": {
-        "register": "PNreg1.S"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "CNTP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svcntp_c64",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "uint64_t"
-    },
-    "Arguments_Preparation": {
-      "pnn": {
-        "register": "PNreg1.D"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "CNTP"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svcntp_c8",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "uint64_t"
-    },
-    "Arguments_Preparation": {
-      "pnn": {
-        "register": "PNreg1.B"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "CNTP"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svcntw",
@@ -35409,20 +35301,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svcreate2[_b]",
-    "arguments": [
-      "svbool_t x",
-      "svbool_t y"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svcreate2[_f16]",
@@ -35742,22 +35620,6 @@
       "A64"
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svcreate4[_b]",
-    "arguments": [
-      "svbool_t x",
-      "svbool_t y",
-      "svbool_t z",
-      "svbool_t w"
-    ],
-    "return_type": {
-      "value": "svboolx4_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svcreate4[_f16]",
@@ -51305,20 +51167,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svget2[_b]",
-    "arguments": [
-      "svboolx2_t tuple",
-      "uint64_t imm_index"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svget2[_f16]",
@@ -51627,20 +51475,6 @@
       "A64"
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svget4[_b]",
-    "arguments": [
-      "svboolx4_t tuple",
-      "uint64_t imm_index"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svget4[_f16]",
@@ -58513,60 +58347,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_f16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_f16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1[_f32]",
@@ -58597,60 +58377,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_f32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_f32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1[_f64]",
@@ -58682,21 +58408,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_f64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s16]",
     "arguments": [
-      "svcount_t png",
-      "float64_t const * rn"
+      "svbool_t pg",
+      "const int16_t *base"
     ],
     "return_type": {
-      "value": "svfloat64x2_t"
+      "value": "svint16_t"
     },
     "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
+      "base": {
+        "register": "Xbase"
       },
-      "rn": {
-        "register": "Xreg1"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
@@ -58704,26 +58430,29 @@
     ],
     "instructions": [
       [
-        "LD1D"
+        "LD1H"
+      ],
+      [
+        "LD1H"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_f64]_x4",
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s32]",
     "arguments": [
-      "svcount_t png",
-      "float64_t const * rn"
+      "svbool_t pg",
+      "const int32_t *base"
     ],
     "return_type": {
-      "value": "svfloat64x4_t"
+      "value": "svint32_t"
     },
     "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
+      "base": {
+        "register": "Xbase"
       },
-      "rn": {
-        "register": "Xreg1"
+      "pg": {
+        "register": "Pg.S"
       }
     },
     "Architectures": [
@@ -58731,26 +58460,29 @@
     ],
     "instructions": [
       [
-        "LD1D"
+        "LD1W"
+      ],
+      [
+        "LD1W"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svld1[_s16]",
+    "name": "svld1[_s64]",
     "arguments": [
       "svbool_t pg",
-      "const int16_t *base"
+      "const int64_t *base"
     ],
     "return_type": {
-      "value": "svint16_t"
+      "value": "svint64_t"
     },
     "Arguments_Preparation": {
       "base": {
         "register": "Xbase"
       },
       "pg": {
-        "register": "Pg.H"
+        "register": "Pg.D"
       }
     },
     "Architectures": [
@@ -58758,29 +58490,29 @@
     ],
     "instructions": [
       [
-        "LD1H"
+        "LD1D"
       ],
       [
-        "LD1H"
+        "LD1D"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s16]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_s8]",
     "arguments": [
-      "svcount_t png",
-      "int16_t const * rn"
+      "svbool_t pg",
+      "const int8_t *base"
     ],
     "return_type": {
-      "value": "svint16x2_t"
+      "value": "svint8_t"
     },
     "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
+      "base": {
+        "register": "Xbase"
       },
-      "rn": {
-        "register": "Xreg1"
+      "pg": {
+        "register": "Pg.B"
       }
     },
     "Architectures": [
@@ -58788,32 +58520,38 @@
     ],
     "instructions": [
       [
-        "LD1H"
+        "LD1B"
+      ],
+      [
+        "LD1B"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s16]_x4",
+    "SIMD_ISA": "SVE",
+    "name": "svld1[_u16]",
     "arguments": [
-      "svcount_t png",
-      "int16_t const * rn"
+      "svbool_t pg",
+      "const uint16_t *base"
     ],
     "return_type": {
-      "value": "svint16x4_t"
+      "value": "svuint16_t"
     },
     "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
+      "base": {
+        "register": "Xbase"
       },
-      "rn": {
-        "register": "Xreg1"
+      "pg": {
+        "register": "Pg.H"
       }
     },
     "Architectures": [
       "A64"
     ],
     "instructions": [
+      [
+        "LD1H"
+      ],
       [
         "LD1H"
       ]
@@ -58821,13 +58559,13 @@
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svld1[_s32]",
+    "name": "svld1[_u32]",
     "arguments": [
       "svbool_t pg",
-      "const int32_t *base"
+      "const uint32_t *base"
     ],
     "return_type": {
-      "value": "svint32_t"
+      "value": "svuint32_t"
     },
     "Arguments_Preparation": {
       "base": {
@@ -58849,396 +58587,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svld1[_s64]",
-    "arguments": [
-      "svbool_t pg",
-      "const int64_t *base"
-    ],
-    "return_type": {
-      "value": "svint64_t"
-    },
-    "Arguments_Preparation": {
-      "base": {
-        "register": "Xbase"
-      },
-      "pg": {
-        "register": "Pg.D"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1D"
-      ],
-      [
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svld1[_s8]",
-    "arguments": [
-      "svbool_t pg",
-      "const int8_t *base"
-    ],
-    "return_type": {
-      "value": "svint8_t"
-    },
-    "Arguments_Preparation": {
-      "base": {
-        "register": "Xbase"
-      },
-      "pg": {
-        "register": "Pg.B"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1B"
-      ],
-      [
-        "LD1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_s8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svld1[_u16]",
-    "arguments": [
-      "svbool_t pg",
-      "const uint16_t *base"
-    ],
-    "return_type": {
-      "value": "svuint16_t"
-    },
-    "Arguments_Preparation": {
-      "base": {
-        "register": "Xbase"
-      },
-      "pg": {
-        "register": "Pg.H"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1H"
-      ],
-      [
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svld1[_u32]",
-    "arguments": [
-      "svbool_t pg",
-      "const uint32_t *base"
-    ],
-    "return_type": {
-      "value": "svuint32_t"
-    },
-    "Arguments_Preparation": {
-      "base": {
-        "register": "Xbase"
-      },
-      "pg": {
-        "register": "Pg.S"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ],
-      [
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1[_u64]",
@@ -59269,60 +58617,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1[_u8]",
@@ -59353,60 +58647,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1[_u8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LD1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_gather[_u32base]_f32",
@@ -60755,72 +59995,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_f16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_f16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_f32]",
@@ -60855,72 +60029,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_f32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_f32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_f64]",
@@ -60955,72 +60063,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_f64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_f64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_s16]",
@@ -61055,72 +60097,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_s32]",
@@ -61155,72 +60131,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_s64]",
@@ -61255,72 +60165,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_s8]",
@@ -61355,72 +60199,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LD1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_s8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LD1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_u16]",
@@ -61455,72 +60233,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_u32]",
@@ -61555,72 +60267,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_u64]",
@@ -61655,72 +60301,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LD1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1_vnum[_u8]",
@@ -61755,72 +60335,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LD1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svld1_vnum[_u8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LD1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svld1ro[_f16]",
@@ -79033,60 +77547,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_f16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_f16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_f32]",
@@ -79117,60 +77577,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_f32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_f32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_f64]",
@@ -79201,60 +77607,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_f64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_f64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svfloat64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_s16]",
@@ -79285,60 +77637,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_s32]",
@@ -79369,60 +77667,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_s64]",
@@ -79453,60 +77697,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_s8]",
@@ -79537,60 +77727,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_s8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_u16]",
@@ -79621,60 +77757,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_u32]",
@@ -79705,60 +77787,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_u64]",
@@ -79789,60 +77817,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1[_u8]",
@@ -79873,60 +77847,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1[_u8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn"
-    ],
-    "return_type": {
-      "value": "svuint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "LDNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svldnt1_gather[_u32base]_f32",
@@ -80960,72 +78880,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_f16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_f16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_f32]",
@@ -81060,72 +78914,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_f32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_f32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_f64]",
@@ -81160,72 +78948,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_f64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "float64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_f64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "float64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svfloat64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_s16]",
@@ -81260,72 +78982,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_s32]",
@@ -81360,72 +79016,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_s64]",
@@ -81460,72 +79050,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_s8]",
@@ -81560,72 +79084,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LDNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_s8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "int8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LDNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_u16]",
@@ -81660,72 +79118,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u16]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint16x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u16]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint16x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_u32]",
@@ -81760,72 +79152,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u32]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint32x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u32]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint32x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_u64]",
@@ -81860,72 +79186,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u64]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint64x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u64]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint64x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "LDNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svldnt1_vnum[_u8]",
@@ -81960,72 +79220,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u8]_x2",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint8x2_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LDNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svldnt1_vnum[_u8]_x4",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t const * rn",
-      "int64_t vnum"
-    ],
-    "return_type": {
-      "value": "svuint8x4_t"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MUL",
-        "LDNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svldnt1sb_gather[_u32base]_offset_s32",
@@ -127681,222 +124875,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c16",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c16_x2",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c32",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c32_x2",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c64",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c64_x2",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c8",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpext_lane_c8_x2",
-    "arguments": [
-      "svcount_t pnn",
-      "uint64_t imm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "imm": {
-        "immediate": "imm1"
-      },
-      "pnn": {
-        "register": "PNreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PEXT"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svpfalse[_b]",
@@ -127914,23 +124892,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpfalse_c",
-    "arguments": [],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {},
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PFALSE"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svpfirst[_b]",
@@ -130064,130 +127025,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpsel_lane_c16",
-    "arguments": [
-      "svcount_t pn",
-      "svbool_t pm",
-      "uint32_t idx"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "idx": {
-        "index": "[Wreg1, imm1]"
-      },
-      "pm": {
-        "register": "Preg3"
-      },
-      "pn": {
-        "register": "Preg2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PSEL"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpsel_lane_c32",
-    "arguments": [
-      "svcount_t pn",
-      "svbool_t pm",
-      "uint32_t idx"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "idx": {
-        "index": "[Wreg1, imm1]"
-      },
-      "pm": {
-        "register": "Preg3"
-      },
-      "pn": {
-        "register": "Preg2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PSEL"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpsel_lane_c64",
-    "arguments": [
-      "svcount_t pn",
-      "svbool_t pm",
-      "uint32_t idx"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "idx": {
-        "index": "[Wreg1, imm1]"
-      },
-      "pm": {
-        "register": "Preg3"
-      },
-      "pn": {
-        "register": "Preg2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PSEL"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svpsel_lane_c8",
-    "arguments": [
-      "svcount_t pn",
-      "svbool_t pm",
-      "uint32_t idx"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "idx": {
-        "index": "[Wreg1, imm1]"
-      },
-      "pm": {
-        "register": "Preg3"
-      },
-      "pn": {
-        "register": "Preg2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PSEL"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svptest_any",
@@ -130298,74 +127135,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svptrue_c16",
-    "arguments": [],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {},
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PTRUE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svptrue_c32",
-    "arguments": [],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {},
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PTRUE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svptrue_c64",
-    "arguments": [],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {},
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PTRUE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svptrue_c8",
-    "arguments": [],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {},
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "PTRUE"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svptrue_pat_b16",
@@ -152948,32 +149717,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svreinterpret[_b]",
-    "arguments": [
-      "svcount_t count"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svreinterpret[_c]",
-    "arguments": [
-      "svbool_t pg"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svreinterpret_f16[_f16]",
@@ -166248,21 +162991,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svset2[_b]",
-    "arguments": [
-      "svboolx2_t tuple",
-      "uint64_t imm_index",
-      "svbool_t x"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svset2[_f16]",
@@ -166593,21 +163321,6 @@
       "A64"
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svset4[_b]",
-    "arguments": [
-      "svboolx4_t tuple",
-      "uint64_t imm_index",
-      "svbool_t x"
-    ],
-    "return_type": {
-      "value": "svboolx4_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svset4[_f16]",
@@ -169853,68 +166566,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_f16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "svfloat16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_f16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "svfloat16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_f32]",
@@ -169949,68 +166600,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_f32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "svfloat32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_f32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "svfloat32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_f64]",
@@ -170045,68 +166634,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_f64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "svfloat64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_f64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "svfloat64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_s16]",
@@ -170141,68 +166668,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "svint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "svint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_s32]",
@@ -170237,68 +166702,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "svint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "svint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_s64]",
@@ -170333,68 +166736,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "svint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "svint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_s8]",
@@ -170429,68 +166770,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "svint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_s8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "svint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_u16]",
@@ -170525,68 +166804,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "svuint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "svuint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_u32]",
@@ -170621,68 +166838,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "svuint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "svuint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_u64]",
@@ -170717,68 +166872,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "svuint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "svuint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1[_u8]",
@@ -170813,68 +166906,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "svuint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1[_u8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "svuint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "ST1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_scatter[_u32base]_index[_f32]",
@@ -172395,80 +168426,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_f16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "int64_t vnum",
-      "svfloat16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_f16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "int64_t vnum",
-      "svfloat16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_f32]",
@@ -172507,80 +168464,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_f32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "int64_t vnum",
-      "svfloat32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_f32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "int64_t vnum",
-      "svfloat32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_f64]",
@@ -172619,80 +168502,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_f64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "int64_t vnum",
-      "svfloat64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_f64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "int64_t vnum",
-      "svfloat64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_s16]",
@@ -172731,80 +168540,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "int64_t vnum",
-      "svint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "int64_t vnum",
-      "svint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_s32]",
@@ -172843,80 +168578,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "int64_t vnum",
-      "svint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "int64_t vnum",
-      "svint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_s64]",
@@ -172955,80 +168616,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "int64_t vnum",
-      "svint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "int64_t vnum",
-      "svint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_s8]",
@@ -173067,80 +168654,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "int64_t vnum",
-      "svint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_s8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "int64_t vnum",
-      "svint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_u16]",
@@ -173179,80 +168692,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "int64_t vnum",
-      "svuint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "int64_t vnum",
-      "svuint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_u32]",
@@ -173291,80 +168730,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "int64_t vnum",
-      "svuint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "int64_t vnum",
-      "svuint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_u64]",
@@ -173403,80 +168768,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "int64_t vnum",
-      "svuint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "int64_t vnum",
-      "svuint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1_vnum[_u8]",
@@ -173515,80 +168806,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "int64_t vnum",
-      "svuint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svst1_vnum[_u8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "int64_t vnum",
-      "svuint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "ST1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svst1b[_s16]",
@@ -178901,68 +174118,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_f16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "svfloat16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_f16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "svfloat16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_f32]",
@@ -178997,68 +174152,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_f32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "svfloat32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_f32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "svfloat32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_f64]",
@@ -179093,68 +174186,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_f64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "svfloat64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_f64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "svfloat64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_s16]",
@@ -179189,68 +174220,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "svint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "svint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_s32]",
@@ -179285,68 +174254,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "svint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "svint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_s64]",
@@ -179381,68 +174288,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "svint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "svint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_s8]",
@@ -179477,68 +174322,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "svint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_s8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "svint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_u16]",
@@ -179573,68 +174356,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "svuint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "svuint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_u32]",
@@ -179669,68 +174390,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "svuint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "svuint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_u64]",
@@ -179765,68 +174424,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "svuint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "svuint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1[_u8]",
@@ -179861,68 +174458,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "svuint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1[_u8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "svuint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "STNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svstnt1_scatter[_u32base]_index[_f32]",
@@ -181092,80 +175627,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_f16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "int64_t vnum",
-      "svfloat16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_f16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float16_t * rn",
-      "int64_t vnum",
-      "svfloat16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_f32]",
@@ -181204,80 +175665,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_f32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "int64_t vnum",
-      "svfloat32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_f32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float32_t * rn",
-      "int64_t vnum",
-      "svfloat32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_f64]",
@@ -181316,80 +175703,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_f64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "int64_t vnum",
-      "svfloat64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_f64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "float64_t * rn",
-      "int64_t vnum",
-      "svfloat64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_s16]",
@@ -181428,80 +175741,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "int64_t vnum",
-      "svint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int16_t * rn",
-      "int64_t vnum",
-      "svint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_s32]",
@@ -181540,80 +175779,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "int64_t vnum",
-      "svint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int32_t * rn",
-      "int64_t vnum",
-      "svint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_s64]",
@@ -181652,80 +175817,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "int64_t vnum",
-      "svint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int64_t * rn",
-      "int64_t vnum",
-      "svint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_s8]",
@@ -181764,80 +175855,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "int64_t vnum",
-      "svint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_s8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "int8_t * rn",
-      "int64_t vnum",
-      "svint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_u16]",
@@ -181876,80 +175893,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u16_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "int64_t vnum",
-      "svuint16x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H, Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1H"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u16_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint16_t * rn",
-      "int64_t vnum",
-      "svuint16x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.H - Zreg2.H }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1H"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_u32]",
@@ -181988,80 +175931,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u32_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "int64_t vnum",
-      "svuint32x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S, Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1W"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u32_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint32_t * rn",
-      "int64_t vnum",
-      "svuint32x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.S - Zreg2.S }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1W"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_u64]",
@@ -182100,80 +175969,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u64_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "int64_t vnum",
-      "svuint64x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D, Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1D"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u64_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint64_t * rn",
-      "int64_t vnum",
-      "svuint64x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.D - Zreg2.D }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1D"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svstnt1_vnum[_u8]",
@@ -182212,80 +176007,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u8_x2]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "int64_t vnum",
-      "svuint8x2_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B, Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1B"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svstnt1_vnum[_u8_x4]",
-    "arguments": [
-      "svcount_t png",
-      "uint8_t * rn",
-      "int64_t vnum",
-      "svuint8x4_t zt"
-    ],
-    "return_type": {
-      "value": "void"
-    },
-    "Arguments_Preparation": {
-      "png": {
-        "register": "PNreg1"
-      },
-      "rn": {
-        "register": "Xreg2"
-      },
-      "vnum": {
-        "register": "Xreg3"
-      },
-      "zt": {
-        "Z multi-vector": "{ Zreg1.B - Zreg2.B }"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "RDVL",
-        "MADD",
-        "STNT1B"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svstnt1b_scatter[_u32base]_offset[_s32]",
@@ -193969,17 +187690,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svundef2_b",
-    "arguments": [],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svundef2_f16",
@@ -194222,17 +187932,6 @@
       "A64"
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svundef4_b",
-    "arguments": [],
-    "return_type": {
-      "value": "svboolx4_t"
-    },
-    "Architectures": [
-      "A64"
-    ]
-  },
   {
     "SIMD_ISA": "SVE",
     "name": "svundef4_f16",
@@ -197212,33 +190911,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b16[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGE"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b16[_u32]",
@@ -197293,33 +190965,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b16[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHS"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b32[_s32]",
@@ -197374,33 +191019,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b32[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGE"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b32[_u32]",
@@ -197455,33 +191073,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b32[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHS"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b64[_s32]",
@@ -197536,33 +191127,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b64[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGE"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b64[_u32]",
@@ -197617,33 +191181,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b64[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHS"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b8[_s32]",
@@ -197698,33 +191235,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b8[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGE"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilege_b8[_u32]",
@@ -197781,175 +191291,20 @@
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilege_b8[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c16[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c16[_u64]",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c32[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c32[_u64]",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c64[_s64]",
+    "name": "svwhilegt_b16[_s32]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -197957,30 +191312,26 @@
     ],
     "instructions": [
       [
-        "WHILEGE"
+        "WHILEGT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c64[_u64]",
+    "name": "svwhilegt_b16[_s64]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -197988,30 +191339,26 @@
     ],
     "instructions": [
       [
-        "WHILEHS"
+        "WHILEGT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c8[_s64]",
+    "name": "svwhilegt_b16[_u32]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -198019,30 +191366,26 @@
     ],
     "instructions": [
       [
-        "WHILEGE"
+        "WHILEHI"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilege_c8[_u64]",
+    "name": "svwhilegt_b16[_u64]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -198050,175 +191393,13 @@
     ],
     "instructions": [
       [
-        "WHILEHS"
+        "WHILEHI"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b16[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b16[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b16[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b16[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b16[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b16[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b32[_s32]",
+    "name": "svwhilegt_b32[_s32]",
     "arguments": [
       "int32_t op1",
       "int32_t op2"
@@ -198270,33 +191451,6 @@
       ]
     ]
   },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b32[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
   {
     "SIMD_ISA": "SVE2",
     "name": "svwhilegt_b32[_u32]",
@@ -198347,1246 +191501,26 @@
     ],
     "instructions": [
       [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b32[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b64[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b64[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b64[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b64[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b64[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b64[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b8[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b8[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b8[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b8[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b8[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_b8[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c16[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c16[_u64]",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c32[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c32[_u64]",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c64[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c64[_u64]",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c8[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEGT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilegt_c8[_u64]",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILEHI"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b16[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b16[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b16[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b16[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b16[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b16[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b32[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b32[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b32[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b32[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b32[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b32[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b64[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b64[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b64[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b64[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b64[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b64[_u64]_x2",
-    "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b8[_s32]",
-    "arguments": [
-      "int32_t op1",
-      "int32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b8[_s64]",
-    "arguments": [
-      "int64_t op1",
-      "int64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b8[_s64]_x2",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm"
-    ],
-    "return_type": {
-      "value": "svboolx2_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELE"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b8[_u32]",
-    "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Wop1"
-      },
-      "op2": {
-        "register": "Wop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE",
-    "name": "svwhilele_b8[_u64]",
-    "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
-    ],
-    "return_type": {
-      "value": "svbool_t"
-    },
-    "Arguments_Preparation": {
-      "op1": {
-        "register": "Xop1"
-      },
-      "op2": {
-        "register": "Xop2"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELS"
+        "WHILEHI"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_b8[_u64]_x2",
+    "name": "svwhilegt_b64[_s32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Wop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -199594,30 +191528,26 @@
     ],
     "instructions": [
       [
-        "WHILELS"
+        "WHILEGT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c16[_s64]",
+    "name": "svwhilegt_b64[_s64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -199625,30 +191555,26 @@
     ],
     "instructions": [
       [
-        "WHILELE"
+        "WHILEGT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c16[_u64]",
+    "name": "svwhilegt_b64[_u32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -199656,30 +191582,26 @@
     ],
     "instructions": [
       [
-        "WHILELS"
+        "WHILEHI"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c32[_s64]",
+    "name": "svwhilegt_b64[_u64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -199687,30 +191609,26 @@
     ],
     "instructions": [
       [
-        "WHILELE"
+        "WHILEHI"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c32[_u64]",
+    "name": "svwhilegt_b8[_s32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -199718,30 +191636,26 @@
     ],
     "instructions": [
       [
-        "WHILELS"
+        "WHILEGT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c64[_s64]",
+    "name": "svwhilegt_b8[_s64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -199749,30 +191663,26 @@
     ],
     "instructions": [
       [
-        "WHILELE"
+        "WHILEGT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c64[_u64]",
+    "name": "svwhilegt_b8[_u32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -199780,30 +191690,26 @@
     ],
     "instructions": [
       [
-        "WHILELS"
+        "WHILEHI"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c8[_s64]",
+    "name": "svwhilegt_b8[_u64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -199811,30 +191717,26 @@
     ],
     "instructions": [
       [
-        "WHILELE"
+        "WHILEHI"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilele_c8[_u64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b16[_s32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -199842,26 +191744,26 @@
     ],
     "instructions": [
       [
-        "WHILELS"
+        "WHILELE"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b16[_s32]",
+    "name": "svwhilele_b16[_s64]",
     "arguments": [
-      "int32_t op1",
-      "int32_t op2"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Wop1"
+        "register": "Xop1"
       },
       "op2": {
-        "register": "Wop2"
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -199869,26 +191771,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELE"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b16[_s64]",
+    "name": "svwhilele_b16[_u32]",
     "arguments": [
-      "int64_t op1",
-      "int64_t op2"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Xop1"
+        "register": "Wop1"
       },
       "op2": {
-        "register": "Xop2"
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -199896,26 +191798,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b16[_s64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b16[_u64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Xop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -199923,16 +191825,16 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELS"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b16[_u32]",
+    "name": "svwhilele_b32[_s32]",
     "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
@@ -199950,16 +191852,16 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELE"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b16[_u64]",
+    "name": "svwhilele_b32[_s64]",
     "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
@@ -199977,26 +191879,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b16[_u64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b32[_u32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Wop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200004,26 +191906,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELS"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b32[_s32]",
+    "name": "svwhilele_b32[_u64]",
     "arguments": [
-      "int32_t op1",
-      "int32_t op2"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Wop1"
+        "register": "Xop1"
       },
       "op2": {
-        "register": "Wop2"
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200031,26 +191933,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELS"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b32[_s64]",
+    "name": "svwhilele_b64[_s32]",
     "arguments": [
-      "int64_t op1",
-      "int64_t op2"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Xop1"
+        "register": "Wop1"
       },
       "op2": {
-        "register": "Xop2"
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200058,26 +191960,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELE"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b32[_s64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b64[_s64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Xop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200085,13 +191987,13 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELE"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b32[_u32]",
+    "name": "svwhilele_b64[_u32]",
     "arguments": [
       "uint32_t op1",
       "uint32_t op2"
@@ -200112,13 +192014,13 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELS"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b32[_u64]",
+    "name": "svwhilele_b64[_u64]",
     "arguments": [
       "uint64_t op1",
       "uint64_t op2"
@@ -200139,26 +192041,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b32[_u64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b8[_s32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Wop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200166,26 +192068,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELE"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b64[_s32]",
+    "name": "svwhilele_b8[_s64]",
     "arguments": [
-      "int32_t op1",
-      "int32_t op2"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Wop1"
+        "register": "Xop1"
       },
       "op2": {
-        "register": "Wop2"
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200193,26 +192095,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELE"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b64[_s64]",
+    "name": "svwhilele_b8[_u32]",
     "arguments": [
-      "int64_t op1",
-      "int64_t op2"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Xop1"
+        "register": "Wop1"
       },
       "op2": {
-        "register": "Xop2"
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200220,26 +192122,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELS"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b64[_s64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilele_b8[_u64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Xop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200247,16 +192149,16 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELS"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b64[_u32]",
+    "name": "svwhilelt_b16[_s32]",
     "arguments": [
-      "uint32_t op1",
-      "uint32_t op2"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
@@ -200274,16 +192176,16 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELT"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b64[_u64]",
+    "name": "svwhilelt_b16[_s64]",
     "arguments": [
-      "uint64_t op1",
-      "uint64_t op2"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
@@ -200301,26 +192203,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b64[_u64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b16[_u32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Wop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200334,20 +192236,20 @@
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b8[_s32]",
+    "name": "svwhilelt_b16[_u64]",
     "arguments": [
-      "int32_t op1",
-      "int32_t op2"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Wop1"
+        "register": "Xop1"
       },
       "op2": {
-        "register": "Wop2"
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200355,26 +192257,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELO"
       ]
     ]
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b8[_s64]",
+    "name": "svwhilelt_b32[_s32]",
     "arguments": [
-      "int64_t op1",
-      "int64_t op2"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
       "value": "svbool_t"
     },
     "Arguments_Preparation": {
       "op1": {
-        "register": "Xop1"
+        "register": "Wop1"
       },
       "op2": {
-        "register": "Xop2"
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200387,21 +192289,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b8[_s64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b32[_s64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Xop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200415,7 +192317,7 @@
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b8[_u32]",
+    "name": "svwhilelt_b32[_u32]",
     "arguments": [
       "uint32_t op1",
       "uint32_t op2"
@@ -200442,7 +192344,7 @@
   },
   {
     "SIMD_ISA": "SVE",
-    "name": "svwhilelt_b8[_u64]",
+    "name": "svwhilelt_b32[_u64]",
     "arguments": [
       "uint64_t op1",
       "uint64_t op2"
@@ -200468,21 +192370,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_b8[_u64]_x2",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_s32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svboolx2_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
+      "op1": {
+        "register": "Wop1"
       },
-      "rn": {
-        "register": "Xreg1"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200490,30 +192392,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c16[_s64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_s64]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200526,25 +192424,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c16[_u64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_u32]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200557,56 +192451,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c32[_s64]",
-    "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
-    ],
-    "return_type": {
-      "value": "svcount_t"
-    },
-    "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
-      },
-      "vl": {
-        "immediate": "<VL>"
-      }
-    },
-    "Architectures": [
-      "A64"
-    ],
-    "instructions": [
-      [
-        "WHILELT"
-      ]
-    ]
-  },
-  {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c32[_u64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b64[_u64]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200619,25 +192478,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c64[_s64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_s32]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "int32_t op1",
+      "int32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200650,25 +192505,21 @@
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c64[_u64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_s64]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "int64_t op1",
+      "int64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -200676,30 +192527,26 @@
     ],
     "instructions": [
       [
-        "WHILELO"
+        "WHILELT"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c8[_s64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_u32]",
     "arguments": [
-      "int64_t rn",
-      "int64_t rm",
-      "uint64_t vl"
+      "uint32_t op1",
+      "uint32_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Wop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Wop2"
       }
     },
     "Architectures": [
@@ -200707,30 +192554,26 @@
     ],
     "instructions": [
       [
-        "WHILELT"
+        "WHILELO"
       ]
     ]
   },
   {
-    "SIMD_ISA": "SVE2",
-    "name": "svwhilelt_c8[_u64]",
+    "SIMD_ISA": "SVE",
+    "name": "svwhilelt_b8[_u64]",
     "arguments": [
-      "uint64_t rn",
-      "uint64_t rm",
-      "uint64_t vl"
+      "uint64_t op1",
+      "uint64_t op2"
     ],
     "return_type": {
-      "value": "svcount_t"
+      "value": "svbool_t"
     },
     "Arguments_Preparation": {
-      "rm": {
-        "register": "Xreg2"
-      },
-      "rn": {
-        "register": "Xreg1"
+      "op1": {
+        "register": "Xop1"
       },
-      "vl": {
-        "immediate": "<VL>"
+      "op2": {
+        "register": "Xop2"
       }
     },
     "Architectures": [
@@ -224064,6 +215907,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtad_s32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtad_s64_f64",
@@ -224087,6 +215953,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtad_u32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtad_u64_f64",
@@ -224413,6 +216302,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtas_s64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtas_u32_f32",
@@ -224436,6 +216348,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtas_u64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTAU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtd_f64_s64",
@@ -224594,6 +216529,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_s32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtd_s64_f64",
@@ -224617,6 +216575,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtd_u32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtd_u64_f64",
@@ -225400,6 +217381,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmd_s32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtmd_s64_f64",
@@ -225423,6 +217427,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtmd_u32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtmd_u64_f64",
@@ -225749,6 +217776,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtms_s64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtms_u32_f32",
@@ -225772,6 +217822,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtms_u64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTMU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtn_s16_f16",
@@ -225914,6 +217987,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnd_s32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtnd_s64_f64",
@@ -225937,6 +218033,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtnd_u32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtnd_u64_f64",
@@ -226263,6 +218382,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtns_s64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtns_u32_f32",
@@ -226286,6 +218428,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtns_u64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTNU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtp_s16_f16",
@@ -226428,6 +218593,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpd_s32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "int32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtpd_s64_f64",
@@ -226451,6 +218639,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtpd_u32_f64",
+    "arguments": [
+      "float64_t a"
+    ],
+    "return_type": {
+      "value": "uint32_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Dn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtpd_u64_f64",
@@ -226777,6 +218988,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtps_s64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtps_u32_f32",
@@ -226800,6 +219034,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvtps_u64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTPU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtq_f16_s16",
@@ -227617,6 +219874,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_s64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "int64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZS"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvts_u32_f32",
@@ -227640,6 +219920,29 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vcvts_u64_f32",
+    "arguments": [
+      "float32_t a"
+    ],
+    "return_type": {
+      "value": "uint64_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Sn"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FCVTZU"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vcvtx_f32_f64",
@@ -228005,6 +220308,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -228041,6 +220345,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -228215,6 +220520,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -228251,6 +220557,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -318819,6 +311126,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -318855,6 +311163,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -318891,6 +311200,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -322606,6 +314916,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [
@@ -322711,6 +315022,7 @@
       }
     },
     "Architectures": [
+      "A32",
       "A64"
     ],
     "instructions": [

From ffe700ceb86f86ac38c6ed0b820cf7f4eb3e30cb Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Mon, 30 Mar 2026 12:16:49 +0100
Subject: [PATCH 253/326] Fix duplicate const specifier

---
 crates/intrinsic-test/src/arm/types.rs       | 3 +--
 crates/intrinsic-test/src/common/argument.rs | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/types.rs b/crates/intrinsic-test/src/arm/types.rs
index 4be8d1e48b..18468bd558 100644
--- a/crates/intrinsic-test/src/arm/types.rs
+++ b/crates/intrinsic-test/src/arm/types.rs
@@ -7,11 +7,10 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
     /// Gets a string containing the typename for this type in C format.
     fn c_type(&self) -> String {
         let prefix = self.kind.c_prefix();
-        let const_prefix = if self.constant { "const " } else { "" };
 
         if let (Some(bit_len), simd_len, vec_len) = (self.bit_len, self.simd_len, self.vec_len) {
             match (simd_len, vec_len) {
-                (None, None) => format!("{const_prefix}{prefix}{bit_len}_t"),
+                (None, None) => format!("{prefix}{bit_len}_t"),
                 (Some(simd), None) => format!("{prefix}{bit_len}x{simd}_t"),
                 (Some(simd), Some(vec)) => format!("{prefix}{bit_len}x{simd}x{vec}_t"),
                 (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case
diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 385cf32d3b..3c4a07c51a 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -30,8 +30,7 @@ where
     }
 
     pub fn to_c_type(&self) -> String {
-        let prefix = if self.ty.constant { "const " } else { "" };
-        format!("{prefix}{}", self.ty.c_type())
+        self.ty.c_type()
     }
 
     pub fn generate_name(&self) -> String {

From 1a4002aa2deddfe933f7f97d188a1a905b2431aa Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Wed, 1 Apr 2026 11:41:12 +0100
Subject: [PATCH 254/326] Detect and fix lane-swapping on big endian vectors

---
 .../src/arm_shared/neon/generated.rs          | 84 -------------------
 crates/intrinsic-test/src/common/argument.rs  | 10 ++-
 crates/intrinsic-test/src/common/gen_c.rs     |  7 ++
 crates/intrinsic-test/src/common/gen_rust.rs  |  6 ++
 .../spec/neon/arm_shared.spec.yml             |  1 +
 5 files changed, 20 insertions(+), 88 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index cf4d10162e..106c814749 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -33834,7 +33834,6 @@ pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33854,36 +33853,8 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) }
 }
 #[doc = "Add pairwise."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(addp)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33903,36 +33874,8 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) }
 }
 #[doc = "Add pairwise."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(addp)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
-    unsafe {
-        let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
 #[inline(always)]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33951,33 +33894,6 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) }
 }
-#[doc = "Add pairwise."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
-#[inline(always)]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(addp)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
-    unsafe {
-        let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
 #[inline(always)]
diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 3c4a07c51a..413d5314d3 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -175,9 +175,10 @@ where
     pub fn load_values_c(&self, indentation: Indentation) -> String {
         self.iter()
             .filter(|&arg| !arg.has_constraint())
-            .map(|arg| {
+            .enumerate()
+            .map(|(idx, arg)| {
                 format!(
-                    "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[i]));\n",
+                    "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[i+{idx}]));\n",
                     ty = arg.to_c_type(),
                     name = arg.generate_name(),
                     load = if arg.is_simd() {
@@ -196,7 +197,8 @@ where
     pub fn load_values_rust(&self, indentation: Indentation) -> String {
         self.iter()
             .filter(|&arg| !arg.has_constraint())
-            .map(|arg| {
+            .enumerate()
+            .map(|(idx, arg)| {
                 let load = if arg.is_simd() {
                     arg.ty.get_load_function(Language::Rust)
                 } else {
@@ -204,7 +206,7 @@ where
                 };
                 let typecast = if load.len() > 2 { "as _" } else { "" };
                 format!(
-                    "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i){typecast});\n",
+                    "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i+{idx}){typecast});\n",
                     name = arg.generate_name(),
                     vals_name = arg.rust_vals_array_name(),
                 )
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index a95b4c36b7..12b5a600d5 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -25,6 +25,13 @@ pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(
     passes: u32,
 ) -> std::io::Result<()> {
     let body_indentation = indentation.nested();
+    // Successive arguments are offset increasingly from their value array start
+    let passes = passes + 1
+        - intrinsic
+            .arguments
+            .iter()
+            .filter(|&arg| !arg.has_constraint())
+            .count() as u32;
     writeln!(
         w,
         "{indentation}for (int i=0; i<{passes}; i++) {{\n\
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index 82b97701bb..5a0bc7b4d4 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -214,6 +214,12 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
     passes: u32,
 ) -> std::io::Result<()> {
     let intrinsic_name = &intrinsic.name;
+    let passes = passes + 1
+        - intrinsic
+            .arguments
+            .iter()
+            .filter(|&arg| !arg.has_constraint())
+            .count() as u32;
 
     // Each function (and each specialization) has its own type. Erase that type with a cast.
     let mut coerce = String::from("unsafe fn(");
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index f6ef7f17d7..7902381fa2 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -13298,6 +13298,7 @@ intrinsics:
     doc: "Add pairwise."
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[0]}"
+    big_endian_inverse: false
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vpadd]]}]]

From 9b2717a367cd02813aba10cb911ab2d2ec9608e1 Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Wed, 1 Apr 2026 12:02:57 +0100
Subject: [PATCH 255/326] Add sanity check that intrinsic output isn't empty

---
 crates/intrinsic-test/src/common/compare.rs | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index c22d7fd4ec..c1438d1bbf 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -78,6 +78,8 @@ pub fn compare_outputs(
         .filter_map(|output| output.trim().split_once("\n"))
         .collect::<HashMap<&str, &str>>();
 
+    assert!(!c_output_map.is_empty(), "No C intrinsic output found!");
+
     let intrinsics = c_output_map
         .keys()
         .chain(rust_output_map.keys())

From f0e32856547feb7ac53e93e8bd50043d7c19c688 Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Thu, 2 Apr 2026 17:32:29 +0100
Subject: [PATCH 256/326] Add round trip tests for v{ld,st}{2,3,4} &
 v{ld,st}{2,3,4} lane intrinsics

---
 .github/workflows/main.yml                    |   1 +
 .../core_arch/src/aarch64/neon/generated.rs   |   4 +-
 crates/core_arch/src/aarch64/neon/mod.rs      | 205 +++++++++++-------
 .../src/arm_shared/neon/generated.rs          |   2 +-
 .../src/arm_shared/neon/load_tests.rs         |  18 ++
 crates/core_arch/src/arm_shared/neon/mod.rs   | 129 ++++++++++-
 .../src/arm_shared/neon/store_tests.rs        |  38 ++++
 .../spec/neon/aarch64.spec.yml                |   4 +-
 .../spec/neon/arm_shared.spec.yml             |   2 +-
 9 files changed, 317 insertions(+), 86 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 1f598f6e20..0bbd772b0e 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -348,6 +348,7 @@ jobs:
     - name: Run miri tests
       env:
         TARGET: "aarch64-unknown-linux-gnu"
+        RUSTFLAGS: "-Ctarget-cpu=neoverse-v3"
       run: |
         # read filters and join them with a space.
         FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ')
diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index c9ce7a69a6..d749ccbe66 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12189,7 +12189,7 @@ pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) ->
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> int8x16x3_t {
-    static_assert_uimm_bits!(LANE, 3);
+    static_assert_uimm_bits!(LANE, 4);
     unsafe extern "unadjusted" {
         #[cfg_attr(
             any(target_arch = "aarch64", target_arch = "arm64ec"),
@@ -12571,7 +12571,7 @@ pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> int8x16x4_t {
-    static_assert_uimm_bits!(LANE, 3);
+    static_assert_uimm_bits!(LANE, 4);
     unsafe extern "unadjusted" {
         #[cfg_attr(
             any(target_arch = "aarch64", target_arch = "arm64ec"),
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 29a278b80d..cab36b9b4b 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -1037,6 +1037,7 @@ mod tests {
     macro_rules! wide_store_load_roundtrip_fp16 {
         ($( $name:ident $args:tt);* $(;)?) => {
             $(
+                #[cfg_attr(miri, ignore)]
                 #[simd_test(enable = "neon,fp16")]
                 #[cfg(not(target_arch = "arm64ec"))]
                 unsafe fn $name() {
@@ -1055,13 +1056,13 @@ mod tests {
         test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3);
         test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4);
 
-        test_vld2_f16_x2(f16, 8, float16x4x2_t, vst2_f16, vld2_f16);
-        test_vld2_f16_x3(f16, 12, float16x4x3_t, vst3_f16, vld3_f16);
-        test_vld2_f16_x4(f16, 16, float16x4x4_t, vst4_f16, vld4_f16);
+        test_vld2_f16(f16, 8, float16x4x2_t, vst2_f16, vld2_f16);
+        test_vld3_f16(f16, 12, float16x4x3_t, vst3_f16, vld3_f16);
+        test_vld4_f16(f16, 16, float16x4x4_t, vst4_f16, vld4_f16);
 
-        test_vld2q_f16_x2(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16);
-        test_vld3q_f16_x3(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16);
-        test_vld4q_f16_x4(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16);
+        test_vld2q_f16(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16);
+        test_vld3q_f16(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16);
+        test_vld4q_f16(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16);
     }
 
     macro_rules! wide_store_load_roundtrip_aes {
@@ -1195,101 +1196,149 @@ mod tests {
     }
 
     wide_store_load_roundtrip_neon! {
-        test_vld2_f32_x2(f32, 4, float32x2x2_t, vst2_f32, vld2_f32);
-        test_vld2_f32_x3(f32, 6, float32x2x3_t, vst3_f32, vld3_f32);
-        test_vld2_f32_x4(f32, 8, float32x2x4_t, vst4_f32, vld4_f32);
+        test_vld2_f32(f32, 4, float32x2x2_t, vst2_f32, vld2_f32);
+        test_vld3_f32(f32, 6, float32x2x3_t, vst3_f32, vld3_f32);
+        test_vld4_f32(f32, 8, float32x2x4_t, vst4_f32, vld4_f32);
 
-        test_vld2q_f32_x2(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32);
-        test_vld3q_f32_x3(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32);
-        test_vld4q_f32_x4(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32);
+        test_vld2q_f32(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32);
+        test_vld3q_f32(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32);
+        test_vld4q_f32(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32);
 
-        test_vld2_f64_x2(f64, 2, float64x1x2_t, vst2_f64, vld2_f64);
-        test_vld2_f64_x3(f64, 3, float64x1x3_t, vst3_f64, vld3_f64);
-        test_vld2_f64_x4(f64, 4, float64x1x4_t, vst4_f64, vld4_f64);
+        test_vld2_f64(f64, 2, float64x1x2_t, vst2_f64, vld2_f64);
+        test_vld3_f64(f64, 3, float64x1x3_t, vst3_f64, vld3_f64);
+        test_vld4_f64(f64, 4, float64x1x4_t, vst4_f64, vld4_f64);
 
-        test_vld2q_f64_x2(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64);
-        test_vld3q_f64_x3(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64);
-        test_vld4q_f64_x4(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64);
+        test_vld2q_f64(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64);
+        test_vld3q_f64(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64);
+        test_vld4q_f64(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64);
 
-        test_vld2_s8_x2(i8, 16, int8x8x2_t, vst2_s8, vld2_s8);
-        test_vld2_s8_x3(i8, 24, int8x8x3_t, vst3_s8, vld3_s8);
-        test_vld2_s8_x4(i8, 32, int8x8x4_t, vst4_s8, vld4_s8);
+        test_vld2_s8(i8, 16, int8x8x2_t, vst2_s8, vld2_s8);
+        test_vld3_s8(i8, 24, int8x8x3_t, vst3_s8, vld3_s8);
+        test_vld4_s8(i8, 32, int8x8x4_t, vst4_s8, vld4_s8);
 
-        test_vld2q_s8_x2(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8);
-        test_vld3q_s8_x3(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8);
-        test_vld4q_s8_x4(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8);
+        test_vld2q_s8(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8);
+        test_vld3q_s8(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8);
+        test_vld4q_s8(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8);
 
-        test_vld2_s16_x2(i16, 8, int16x4x2_t, vst2_s16, vld2_s16);
-        test_vld2_s16_x3(i16, 12, int16x4x3_t, vst3_s16, vld3_s16);
-        test_vld2_s16_x4(i16, 16, int16x4x4_t, vst4_s16, vld4_s16);
+        test_vld2_s16(i16, 8, int16x4x2_t, vst2_s16, vld2_s16);
+        test_vld3_s16(i16, 12, int16x4x3_t, vst3_s16, vld3_s16);
+        test_vld4_s16(i16, 16, int16x4x4_t, vst4_s16, vld4_s16);
 
-        test_vld2q_s16_x2(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16);
-        test_vld3q_s16_x3(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16);
-        test_vld4q_s16_x4(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16);
+        test_vld2q_s16(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16);
+        test_vld3q_s16(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16);
+        test_vld4q_s16(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16);
 
-        test_vld2_s32_x2(i32, 4, int32x2x2_t, vst2_s32, vld2_s32);
-        test_vld2_s32_x3(i32, 6, int32x2x3_t, vst3_s32, vld3_s32);
-        test_vld2_s32_x4(i32, 8, int32x2x4_t, vst4_s32, vld4_s32);
+        test_vld2_s32(i32, 4, int32x2x2_t, vst2_s32, vld2_s32);
+        test_vld3_s32(i32, 6, int32x2x3_t, vst3_s32, vld3_s32);
+        test_vld4_s32(i32, 8, int32x2x4_t, vst4_s32, vld4_s32);
 
-        test_vld2q_s32_x2(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32);
-        test_vld3q_s32_x3(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32);
-        test_vld4q_s32_x4(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32);
+        test_vld2q_s32(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32);
+        test_vld3q_s32(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32);
+        test_vld4q_s32(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32);
 
-        test_vld2_s64_x2(i64, 2, int64x1x2_t, vst2_s64, vld2_s64);
-        test_vld2_s64_x3(i64, 3, int64x1x3_t, vst3_s64, vld3_s64);
-        test_vld2_s64_x4(i64, 4, int64x1x4_t, vst4_s64, vld4_s64);
+        test_vld2_s64(i64, 2, int64x1x2_t, vst2_s64, vld2_s64);
+        test_vld3_s64(i64, 3, int64x1x3_t, vst3_s64, vld3_s64);
+        test_vld4_s64(i64, 4, int64x1x4_t, vst4_s64, vld4_s64);
 
-        test_vld2q_s64_x2(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64);
-        test_vld3q_s64_x3(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64);
-        test_vld4q_s64_x4(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64);
+        test_vld2q_s64(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64);
+        test_vld3q_s64(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64);
+        test_vld4q_s64(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64);
 
-        test_vld2_u8_x2(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8);
-        test_vld2_u8_x3(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8);
-        test_vld2_u8_x4(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8);
+        test_vld2_u8(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8);
+        test_vld3_u8(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8);
+        test_vld4_u8(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8);
 
-        test_vld2q_u8_x2(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8);
-        test_vld3q_u8_x3(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8);
-        test_vld4q_u8_x4(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8);
+        test_vld2q_u8(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8);
+        test_vld3q_u8(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8);
+        test_vld4q_u8(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8);
 
-        test_vld2_u16_x2(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16);
-        test_vld2_u16_x3(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16);
-        test_vld2_u16_x4(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16);
+        test_vld2_u16(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16);
+        test_vld3_u16(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16);
+        test_vld4_u16(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16);
 
-        test_vld2q_u16_x2(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16);
-        test_vld3q_u16_x3(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16);
-        test_vld4q_u16_x4(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16);
+        test_vld2q_u16(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16);
+        test_vld3q_u16(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16);
+        test_vld4q_u16(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16);
 
-        test_vld2_u32_x2(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32);
-        test_vld2_u32_x3(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32);
-        test_vld2_u32_x4(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32);
+        test_vld2_u32(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32);
+        test_vld3_u32(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32);
+        test_vld4_u32(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32);
 
-        test_vld2q_u32_x2(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32);
-        test_vld3q_u32_x3(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32);
-        test_vld4q_u32_x4(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32);
+        test_vld2q_u32(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32);
+        test_vld3q_u32(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32);
+        test_vld4q_u32(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32);
 
-        test_vld2_u64_x2(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64);
-        test_vld2_u64_x3(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64);
-        test_vld2_u64_x4(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64);
+        test_vld2_u64(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64);
+        test_vld3_u64(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64);
+        test_vld4_u64(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64);
 
-        test_vld2q_u64_x2(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64);
-        test_vld3q_u64_x3(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64);
-        test_vld4q_u64_x4(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64);
+        test_vld2q_u64(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64);
+        test_vld3q_u64(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64);
+        test_vld4q_u64(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64);
 
-        test_vld2_p8_x2(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8);
-        test_vld2_p8_x3(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8);
-        test_vld2_p8_x4(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8);
+        test_vld2_p8(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8);
+        test_vld3_p8(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8);
+        test_vld4_p8(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8);
 
-        test_vld2q_p8_x2(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8);
-        test_vld3q_p8_x3(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8);
-        test_vld4q_p8_x4(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8);
+        test_vld2q_p8(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8);
+        test_vld3q_p8(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8);
+        test_vld4q_p8(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8);
 
-        test_vld2_p16_x2(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16);
-        test_vld2_p16_x3(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16);
-        test_vld2_p16_x4(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16);
+        test_vld2_p16(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16);
+        test_vld3_p16(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16);
+        test_vld4_p16(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16);
 
-        test_vld2q_p16_x2(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16);
-        test_vld3q_p16_x3(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16);
-        test_vld4q_p16_x4(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16);
+        test_vld2q_p16(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16);
+        test_vld3q_p16(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16);
+        test_vld4q_p16(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16);
+    }
+
+    macro_rules! lane_wide_store_load_roundtrip {
+        ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => {
+            let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty);
+            let a: $vec_ty = transmute(vals);
+            let mut tmp = [0 as $elem_ty; 4];
+            $store::<$idx>(tmp.as_mut_ptr().cast(), a);
+            let r: $vec_ty = $load::<$idx>(tmp.as_ptr().cast(), a);
+            let out: [$elem_ty; $len] = transmute(r);
+            assert_eq!(out, vals);
+        };
+    }
+
+    macro_rules! lane_wide_store_load_roundtrip_neon {
+        ($( $name:ident $args:tt);* $(;)?) => {
+            $(
+                #[cfg_attr(miri, ignore)]
+                #[simd_test(enable = "neon")]
+                unsafe fn $name() {
+                    lane_wide_store_load_roundtrip! $args;
+                }
+            )*
+        };
+    }
+
+    lane_wide_store_load_roundtrip_neon! {
+        test_vld2q_lane_s8(i8, 32, 15, int8x16x2_t, vst2q_lane_s8, vld2q_lane_s8);
+        test_vld3q_lane_s8(i8, 48, 15, int8x16x3_t, vst3q_lane_s8, vld3q_lane_s8);
+        test_vld4q_lane_s8(i8, 64, 15, int8x16x4_t, vst4q_lane_s8, vld4q_lane_s8);
+
+        test_vld2q_lane_u8(u8, 32, 15, uint8x16x2_t, vst2q_lane_u8, vld2q_lane_u8);
+        test_vld3q_lane_u8(u8, 48, 15, uint8x16x3_t, vst3q_lane_u8, vld3q_lane_u8);
+        test_vld4q_lane_u8(u8, 64, 15, uint8x16x4_t, vst4q_lane_u8, vld4q_lane_u8);
+
+        test_vld2_lane_s64(i64, 2, 0, int64x1x2_t, vst2_lane_s64, vld2_lane_s64);
+        test_vld3_lane_s64(i64, 3, 0, int64x1x3_t, vst3_lane_s64, vld3_lane_s64);
+        test_vld4_lane_s64(i64, 4, 0, int64x1x4_t, vst4_lane_s64, vld4_lane_s64);
+        test_vld2q_lane_s64(i64, 4, 1, int64x2x2_t, vst2q_lane_s64, vld2q_lane_s64);
+        test_vld3q_lane_s64(i64, 6, 1, int64x2x3_t, vst3q_lane_s64, vld3q_lane_s64);
+        test_vld4q_lane_s64(i64, 8, 1, int64x2x4_t, vst4q_lane_s64, vld4q_lane_s64);
+
+        test_vld2_lane_u64(u64, 2, 0, uint64x1x2_t, vst2_lane_u64, vld2_lane_u64);
+        test_vld3_lane_u64(u64, 3, 0, uint64x1x3_t, vst3_lane_u64, vld3_lane_u64);
+        test_vld4_lane_u64(u64, 4, 0, uint64x1x4_t, vst4_lane_u64, vld4_lane_u64);
+        test_vld2q_lane_u64(u64, 4, 1, uint64x2x2_t, vst2q_lane_u64, vld2q_lane_u64);
+        test_vld3q_lane_u64(u64, 6, 1, uint64x2x3_t, vst3q_lane_u64, vld3q_lane_u64);
+        test_vld4q_lane_u64(u64, 8, 1, uint64x2x4_t, vst4q_lane_u64, vld4q_lane_u64);
     }
 }
 
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index cf4d10162e..663cba151e 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -66192,7 +66192,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
-    static_assert_uimm_bits!(LANE, 1);
+    static_assert_uimm_bits!(LANE, 3);
     unsafe extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v8f16")]
         fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32);
diff --git a/crates/core_arch/src/arm_shared/neon/load_tests.rs b/crates/core_arch/src/arm_shared/neon/load_tests.rs
index cc821b4af2..70a37f7c05 100644
--- a/crates/core_arch/src/arm_shared/neon/load_tests.rs
+++ b/crates/core_arch/src/arm_shared/neon/load_tests.rs
@@ -190,6 +190,24 @@ fn test_vld1q_p64() {
     assert_eq!(r, e)
 }
 
+#[cfg(not(target_arch = "arm64ec"))]
+#[simd_test(enable = "neon,fp16")]
+fn test_vld1_f16() {
+    let a: [f16; 5] = [0., 1., 2., 3., 4.];
+    let e = f16x4::new(1., 2., 3., 4.);
+    let r = unsafe { f16x4::from(vld1_f16(a[1..].as_ptr())) };
+    assert_eq!(r, e)
+}
+
+#[cfg(not(target_arch = "arm64ec"))]
+#[simd_test(enable = "neon,fp16")]
+fn test_vld1q_f16() {
+    let a: [f16; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.];
+    let e = f16x8::new(1., 2., 3., 4., 5., 6., 7., 8.);
+    let r = unsafe { f16x8::from(vld1q_f16(a[1..].as_ptr())) };
+    assert_eq!(r, e)
+}
+
 #[simd_test(enable = "neon")]
 fn test_vld1_f32() {
     let a: [f32; 3] = [0., 1., 2.];
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index 8a4a6e9228..ed65de2b89 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -5793,8 +5793,7 @@ mod tests {
     #[cfg(not(target_arch = "arm64ec"))]
     mod fp16 {
         use super::*;
-        #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,fp16"))]
-        #[cfg_attr(not(target_arch = "arm"), simd_test(enable = "neon"))]
+        #[simd_test(enable = "neon,fp16")]
         fn test_vcombine_f16() {
             let a = f16x4::from_array([3_f16, 4., 5., 6.]);
             let b = f16x4::from_array([13_f16, 14., 15., 16.]);
@@ -5802,6 +5801,40 @@ mod tests {
             let c = f16x8::from(vcombine_f16(a.into(), b.into()));
             assert_eq!(c, e);
         }
+
+        #[simd_test(enable = "neon,fp16")]
+        fn test_vld1_lane_f16() {
+            let a = f16x4::new(0., 1., 2., 3.);
+            let elem: f16 = 42.;
+            let e = f16x4::new(0., 1., 2., 42.);
+            let r = unsafe { f16x4::from(vld1_lane_f16::<3>(&elem, a.into())) };
+            assert_eq!(r, e)
+        }
+
+        #[simd_test(enable = "neon,fp16")]
+        fn test_vld1q_lane_f16() {
+            let a = f16x8::new(0., 1., 2., 3., 4., 5., 6., 7.);
+            let elem: f16 = 42.;
+            let e = f16x8::new(0., 1., 2., 3., 4., 5., 6., 42.);
+            let r = unsafe { f16x8::from(vld1q_lane_f16::<7>(&elem, a.into())) };
+            assert_eq!(r, e)
+        }
+
+        #[simd_test(enable = "neon,fp16")]
+        fn test_vld1_dup_f16() {
+            let elem: f16 = 42.;
+            let e = f16x4::new(42., 42., 42., 42.);
+            let r = unsafe { f16x4::from(vld1_dup_f16(&elem)) };
+            assert_eq!(r, e)
+        }
+
+        #[simd_test(enable = "neon,fp16")]
+        fn test_vld1q_dup_f16() {
+            let elem: f16 = 42.;
+            let e = f16x8::new(42., 42., 42., 42., 42., 42., 42., 42.);
+            let r = unsafe { f16x8::from(vld1q_dup_f16(&elem)) };
+            assert_eq!(r, e)
+        }
     }
 
     test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14]));
@@ -5814,6 +5847,98 @@ mod tests {
     test_vcombine!(test_vcombine_p64 => vcombine_p64([3_u64], [13_u64]));
     #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
     test_vcombine!(test_vcombine_f64 => vcombine_f64([-3_f64], [13_f64]));
+
+    macro_rules! lane_wide_store_load_roundtrip {
+        ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => {
+            let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty);
+            let a: $vec_ty = transmute(vals);
+            let mut tmp = [0 as $elem_ty; 4];
+            $store::<$idx>(tmp.as_mut_ptr().cast(), a);
+            let r: $vec_ty = $load::<$idx>(tmp.as_ptr().cast(), a);
+            let out: [$elem_ty; $len] = transmute(r);
+            assert_eq!(out, vals);
+        };
+    }
+
+    // Most of these are implemented with builtins, which miri can't handle
+    macro_rules! lane_wide_store_load_roundtrip_neon {
+        ($( $name:ident $args:tt);* $(;)?) => {
+            $(
+                #[cfg_attr(miri, ignore)]
+                #[simd_test(enable = "neon")]
+                unsafe fn $name() {
+                    lane_wide_store_load_roundtrip! $args;
+                }
+            )*
+        };
+    }
+
+    macro_rules! lane_wide_store_load_roundtrip_fp16 {
+        ($( $name:ident $args:tt);* $(;)?) => {
+            $(
+                #[cfg_attr(miri, ignore)]
+                #[simd_test(enable = "neon,fp16")]
+                #[cfg(not(target_arch = "arm64ec"))]
+                unsafe fn $name() {
+                    lane_wide_store_load_roundtrip! $args;
+                }
+            )*
+        };
+    }
+
+    lane_wide_store_load_roundtrip_neon! {
+        test_vld2_lane_s8(i8, 16, 7, int8x8x2_t, vst2_lane_s8, vld2_lane_s8);
+        test_vld3_lane_s8(i8, 24, 7, int8x8x3_t, vst3_lane_s8, vld3_lane_s8);
+        test_vld4_lane_s8(i8, 32, 7, int8x8x4_t, vst4_lane_s8, vld4_lane_s8);
+
+        test_vld2_lane_u8(u8, 16, 7, uint8x8x2_t, vst2_lane_u8, vld2_lane_u8);
+        test_vld3_lane_u8(u8, 24, 7, uint8x8x3_t, vst3_lane_u8, vld3_lane_u8);
+        test_vld4_lane_u8(u8, 32, 7, uint8x8x4_t, vst4_lane_u8, vld4_lane_u8);
+
+        test_vld2_lane_s16(i16, 8, 3, int16x4x2_t, vst2_lane_s16, vld2_lane_s16);
+        test_vld3_lane_s16(i16, 12, 3, int16x4x3_t, vst3_lane_s16, vld3_lane_s16);
+        test_vld4_lane_s16(i16, 16, 3, int16x4x4_t, vst4_lane_s16, vld4_lane_s16);
+        test_vld2q_lane_s16(i16, 16, 7, int16x8x2_t, vst2q_lane_s16, vld2q_lane_s16);
+        test_vld3q_lane_s16(i16, 24, 7, int16x8x3_t, vst3q_lane_s16, vld3q_lane_s16);
+        test_vld4q_lane_s16(i16, 32, 7, int16x8x4_t, vst4q_lane_s16, vld4q_lane_s16);
+
+        test_vld2_lane_u16(u16, 8, 3, uint16x4x2_t, vst2_lane_u16, vld2_lane_u16);
+        test_vld3_lane_u16(u16, 12, 3, uint16x4x3_t, vst3_lane_u16, vld3_lane_u16);
+        test_vld4_lane_u16(u16, 16, 3, uint16x4x4_t, vst4_lane_u16, vld4_lane_u16);
+        test_vld2q_lane_u16(u16, 16, 7, uint16x8x2_t, vst2q_lane_u16, vld2q_lane_u16);
+        test_vld3q_lane_u16(u16, 24, 7, uint16x8x3_t, vst3q_lane_u16, vld3q_lane_u16);
+        test_vld4q_lane_u16(u16, 32, 7, uint16x8x4_t, vst4q_lane_u16, vld4q_lane_u16);
+
+        test_vld2_lane_s32(i32, 4, 1, int32x2x2_t, vst2_lane_s32, vld2_lane_s32);
+        test_vld3_lane_s32(i32, 6, 1, int32x2x3_t, vst3_lane_s32, vld3_lane_s32);
+        test_vld4_lane_s32(i32, 8, 1, int32x2x4_t, vst4_lane_s32, vld4_lane_s32);
+        test_vld2q_lane_s32(i32, 8, 3, int32x4x2_t, vst2q_lane_s32, vld2q_lane_s32);
+        test_vld3q_lane_s32(i32, 12, 3, int32x4x3_t, vst3q_lane_s32, vld3q_lane_s32);
+        test_vld4q_lane_s32(i32, 16, 3, int32x4x4_t, vst4q_lane_s32, vld4q_lane_s32);
+
+        test_vld2_lane_u32(u32, 4, 1, uint32x2x2_t, vst2_lane_u32, vld2_lane_u32);
+        test_vld3_lane_u32(u32, 6, 1, uint32x2x3_t, vst3_lane_u32, vld3_lane_u32);
+        test_vld4_lane_u32(u32, 8, 1, uint32x2x4_t, vst4_lane_u32, vld4_lane_u32);
+        test_vld2q_lane_u32(u32, 8, 3, uint32x4x2_t, vst2q_lane_u32, vld2q_lane_u32);
+        test_vld3q_lane_u32(u32, 12, 3, uint32x4x3_t, vst3q_lane_u32, vld3q_lane_u32);
+        test_vld4q_lane_u32(u32, 16, 3, uint32x4x4_t, vst4q_lane_u32, vld4q_lane_u32);
+
+        test_vld2_lane_f32(f32, 4, 1, float32x2x2_t, vst2_lane_f32, vld2_lane_f32);
+        test_vld3_lane_f32(f32, 6, 1, float32x2x3_t, vst3_lane_f32, vld3_lane_f32);
+        test_vld4_lane_f32(f32, 8, 1, float32x2x4_t, vst4_lane_f32, vld4_lane_f32);
+        test_vld2q_lane_f32(f32, 8, 3, float32x4x2_t, vst2q_lane_f32, vld2q_lane_f32);
+        test_vld3q_lane_f32(f32, 12, 3, float32x4x3_t, vst3q_lane_f32, vld3q_lane_f32);
+        test_vld4q_lane_f32(f32, 16, 3, float32x4x4_t, vst4q_lane_f32, vld4q_lane_f32);
+    }
+
+    lane_wide_store_load_roundtrip_fp16! {
+        test_vld2_lane_f16(f16, 8, 3, float16x4x2_t, vst2_lane_f16, vld2_lane_f16);
+        test_vld3_lane_f16(f16, 12, 3, float16x4x3_t, vst3_lane_f16, vld3_lane_f16);
+        test_vld4_lane_f16(f16, 16, 3, float16x4x4_t, vst4_lane_f16, vld4_lane_f16);
+        test_vld2q_lane_f16(f16, 16, 7, float16x8x2_t, vst2q_lane_f16, vld2q_lane_f16);
+        test_vld3q_lane_f16(f16, 24, 7, float16x8x3_t, vst3q_lane_f16, vld3q_lane_f16);
+        test_vld4q_lane_f16(f16, 32, 7, float16x8x4_t, vst4q_lane_f16, vld4q_lane_f16);
+    }
 }
 
 #[cfg(all(test, target_arch = "arm"))]
diff --git a/crates/core_arch/src/arm_shared/neon/store_tests.rs b/crates/core_arch/src/arm_shared/neon/store_tests.rs
index 2b10b38f2d..6eb60e4c78 100644
--- a/crates/core_arch/src/arm_shared/neon/store_tests.rs
+++ b/crates/core_arch/src/arm_shared/neon/store_tests.rs
@@ -406,6 +406,44 @@ fn test_vst1q_p64() {
     assert_eq!(vals[2], 2);
 }
 
+#[cfg(not(target_arch = "arm64ec"))]
+#[simd_test(enable = "neon,fp16")]
+fn test_vst1_f16() {
+    let mut vals = [0_f16; 5];
+    let a = f16x4::new(1., 2., 3., 4.);
+
+    unsafe {
+        vst1_f16(vals[1..].as_mut_ptr(), a.into());
+    }
+
+    assert_eq!(vals[0], 0.);
+    assert_eq!(vals[1], 1.);
+    assert_eq!(vals[2], 2.);
+    assert_eq!(vals[3], 3.);
+    assert_eq!(vals[4], 4.);
+}
+
+#[cfg(not(target_arch = "arm64ec"))]
+#[simd_test(enable = "neon,fp16")]
+fn test_vst1q_f16() {
+    let mut vals = [0_f16; 9];
+    let a = f16x8::new(1., 2., 3., 4., 5., 6., 7., 8.);
+
+    unsafe {
+        vst1q_f16(vals[1..].as_mut_ptr(), a.into());
+    }
+
+    assert_eq!(vals[0], 0.);
+    assert_eq!(vals[1], 1.);
+    assert_eq!(vals[2], 2.);
+    assert_eq!(vals[3], 3.);
+    assert_eq!(vals[4], 4.);
+    assert_eq!(vals[5], 5.);
+    assert_eq!(vals[6], 6.);
+    assert_eq!(vals[7], 7.);
+    assert_eq!(vals[8], 8.);
+}
+
 #[simd_test(enable = "neon")]
 fn test_vst1_f32() {
     let mut vals = [0_f32; 3];
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a769d35264..990fd7d498 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -3822,7 +3822,7 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ['*const i8', int8x16x3_t, int8x16_t, i8, '3']
+      - ['*const i8', int8x16x3_t, int8x16_t, i8, '4']
       - ['*const i64', int64x2x3_t, int64x2_t, i64, '1']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']]
@@ -4246,7 +4246,7 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ['*const i8', int8x16x4_t, int8x16_t, i8, '3']
+      - ['*const i8', int8x16x4_t, int8x16_t, i8, '4']
       - ['*const i64', int64x2x4_t, int64x2_t, i64, '1']
       - ['*const f64', float64x2x4_t, float64x2_t, f64, '1']
     compose:
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index f6ef7f17d7..2d29d95f0a 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -5368,7 +5368,7 @@ intrinsics:
       unsafe: [neon]
     types:
       - [f16, float16x4x2_t, '2', float16x4_t, '2']
-      - [f16, float16x8x2_t, '1', float16x8_t, '2']
+      - [f16, float16x8x2_t, '3', float16x8_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]]
       - LLVMLink:

From 2d49c7b69aaaf2647558348a2d74ff2c894c3420 Mon Sep 17 00:00:00 2001
From: Adam Gemmell <adam.gemmell@arm.com>
Date: Wed, 15 Apr 2026 16:52:13 +0100
Subject: [PATCH 257/326] Generate some svldff1 tests now that the qemu bug has
 been fixed

---
 .../src/aarch64/sve/ld_st_tests_aarch64.rs    | 2348 +++++++++++++++--
 .../stdarch-gen-arm/src/load_store_tests.rs   |    7 -
 2 files changed, 2119 insertions(+), 236 deletions(-)

diff --git a/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs b/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
index 973b7e9fa3..3007ba4ee6 100644
--- a/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
+++ b/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
@@ -7067,304 +7067,606 @@ unsafe fn test_svldff1_u64() {
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_f32() {
+unsafe fn test_svldff1_gather_s32index_f32() {
+    let indices = svindex_s32(0, 1);
     svsetffr();
-    let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
-    let len = svcntw() as usize;
+    let _ = svld1_gather_s32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_s32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices);
     assert_vector_matches_f32(
         loaded,
         svcvt_f32_s32_x(
             svptrue_b32(),
-            svindex_s32(
-                (len + 0usize).try_into().unwrap(),
-                1usize.try_into().unwrap(),
-            ),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
         ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_f64() {
+unsafe fn test_svldff1_gather_s32index_s32() {
+    let indices = svindex_s32(0, 1);
     svsetffr();
-    let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
+    let _ = svld1_gather_s32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_s32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_s32index_u32() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let _ = svld1_gather_s32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_s32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_s64index_f64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1_gather_s64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_s64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices);
     assert_vector_matches_f64(
         loaded,
         svcvt_f64_s64_x(
             svptrue_b64(),
-            svindex_s64(
-                (len + 0usize).try_into().unwrap(),
-                1usize.try_into().unwrap(),
-            ),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
         ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_s8() {
+unsafe fn test_svldff1_gather_s64index_s64() {
+    let indices = svindex_s64(0, 1);
     svsetffr();
-    let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let len = svcntb() as usize;
-    assert_vector_matches_i8(
+    let _ = svld1_gather_s64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_s64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
         loaded,
-        svindex_s8(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_s16() {
+unsafe fn test_svldff1_gather_s64index_u64() {
+    let indices = svindex_s64(0, 1);
     svsetffr();
-    let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let len = svcnth() as usize;
-    assert_vector_matches_i16(
+    let _ = svld1_gather_s64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_s64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
         loaded,
-        svindex_s16(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_s32() {
+unsafe fn test_svldff1_gather_u32index_f32() {
+    let indices = svindex_u32(0, 1);
     svsetffr();
-    let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
-    let len = svcntw() as usize;
-    assert_vector_matches_i32(
+    let _ = svld1_gather_u32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_u32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices);
+    assert_vector_matches_f32(
         loaded,
-        svindex_s32(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
         ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_s64() {
+unsafe fn test_svldff1_gather_u32index_s32() {
+    let indices = svindex_u32(0, 1);
     svsetffr();
-    let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
-    assert_vector_matches_i64(
+    let _ = svld1_gather_u32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_u32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    assert_vector_matches_i32(
         loaded,
-        svindex_s64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_u8() {
+unsafe fn test_svldff1_gather_u32index_u32() {
+    let indices = svindex_u32(0, 1);
     svsetffr();
-    let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
-    let len = svcntb() as usize;
-    assert_vector_matches_u8(
+    let _ = svld1_gather_u32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_u32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    assert_vector_matches_u32(
         loaded,
-        svindex_u8(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_u16() {
+unsafe fn test_svldff1_gather_u64index_f64() {
+    let indices = svindex_u64(0, 1);
     svsetffr();
-    let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
-    let len = svcnth() as usize;
-    assert_vector_matches_u16(
+    let _ = svld1_gather_u64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_u64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices);
+    assert_vector_matches_f64(
         loaded,
-        svindex_u16(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
         ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_u32() {
+unsafe fn test_svldff1_gather_u64index_s64() {
+    let indices = svindex_u64(0, 1);
     svsetffr();
-    let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
-    let len = svcntw() as usize;
-    assert_vector_matches_u32(
+    let _ = svld1_gather_u64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_u64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
         loaded,
-        svindex_u32(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1_vnum_u64() {
+unsafe fn test_svldff1_gather_u64index_u64() {
+    let indices = svindex_u64(0, 1);
     svsetffr();
-    let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
-    let loaded = svldff1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
+    let _ = svld1_gather_u64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices);
+    let loaded = svldff1_gather_u64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices);
     assert_vector_matches_u64(
         loaded,
-        svindex_u64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_s16() {
+unsafe fn test_svldff1_gather_s32offset_f32() {
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
-    let loaded = svldff1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
-    assert_vector_matches_i16(
+    let _ = svld1_gather_s32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_s32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets);
+    assert_vector_matches_f32(
         loaded,
-        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_s32() {
+unsafe fn test_svldff1_gather_s32offset_s32() {
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
-    let loaded = svldff1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    let _ = svld1_gather_s32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_s32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets);
     assert_vector_matches_i32(
         loaded,
         svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_s32() {
+unsafe fn test_svldff1_gather_s32offset_u32() {
+    let offsets = svindex_s32(0, 4u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
-    let loaded = svldff1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
-    assert_vector_matches_i32(
+    let _ = svld1_gather_s32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_s32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
         loaded,
-        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_s64() {
+unsafe fn test_svldff1_gather_s64offset_f64() {
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
-    let loaded = svldff1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
-    assert_vector_matches_i64(
+    let _ = svld1_gather_s64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_s64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets);
+    assert_vector_matches_f64(
         loaded,
-        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_s64() {
+unsafe fn test_svldff1_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
-    let loaded = svldff1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    let _ = svld1_gather_s64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_s64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets);
     assert_vector_matches_i64(
         loaded,
         svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sw_s64() {
+unsafe fn test_svldff1_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 8u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
-    let loaded = svldff1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
-    assert_vector_matches_i64(
+    let _ = svld1_gather_s64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_s64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
         loaded,
-        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_u16() {
+unsafe fn test_svldff1_gather_u32offset_f32() {
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
-    let loaded = svldff1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
-    assert_vector_matches_u16(
+    let _ = svld1_gather_u32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_u32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets);
+    assert_vector_matches_f32(
         loaded,
-        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_u32() {
+unsafe fn test_svldff1_gather_u32offset_s32() {
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
-    let loaded = svldff1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
-    assert_vector_matches_u32(
+    let _ = svld1_gather_u32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_u32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
         loaded,
-        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_u32() {
+unsafe fn test_svldff1_gather_u32offset_u32() {
+    let offsets = svindex_u32(0, 4u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
-    let loaded = svldff1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    let _ = svld1_gather_u32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_u32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets);
     assert_vector_matches_u32(
         loaded,
         svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_u64() {
+unsafe fn test_svldff1_gather_u64offset_f64() {
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
-    let loaded = svldff1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
-    assert_vector_matches_u64(
+    let _ = svld1_gather_u64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_u64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets);
+    assert_vector_matches_f64(
         loaded,
-        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_u64() {
+unsafe fn test_svldff1_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
-    let loaded = svldff1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
-    assert_vector_matches_u64(
+    let _ = svld1_gather_u64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_u64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
         loaded,
-        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sw_u64() {
+unsafe fn test_svldff1_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
     svsetffr();
-    let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
-    let loaded = svldff1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    let _ = svld1_gather_u64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets);
+    let loaded = svldff1_gather_u64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets);
     assert_vector_matches_u64(
         loaded,
         svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_vnum_s16() {
+unsafe fn test_svldff1_gather_u64base_f64() {
+    let bases = svdup_n_u64(F64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
     svsetffr();
-    let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let len = svcnth() as usize;
-    assert_vector_matches_i16(
+    let _ = svld1_gather_u64base_f64(svptrue_b64(), bases);
+    let loaded = svldff1_gather_u64base_f64(svptrue_b64(), bases);
+    assert_vector_matches_f64(
         loaded,
-        svindex_s16(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
         ),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_vnum_s32() {
+unsafe fn test_svldff1_gather_u64base_s64() {
+    let bases = svdup_n_u64(I64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
     svsetffr();
-    let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let len = svcntw() as usize;
-    assert_vector_matches_i32(
+    let _ = svld1_gather_u64base_s64(svptrue_b64(), bases);
+    let loaded = svldff1_gather_u64base_s64(svptrue_b64(), bases);
+    assert_vector_matches_i64(
         loaded,
-        svindex_s32(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_vnum_s32() {
+unsafe fn test_svldff1_gather_u64base_u64() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
     svsetffr();
-    let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let loaded = svldff1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let _ = svld1_gather_u64base_u64(svptrue_b64(), bases);
+    let loaded = svldff1_gather_u64base_u64(svptrue_b64(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u32base_index_f32() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1_gather_u32base_index_f32(
+        svptrue_b32(),
+        bases,
+        F32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    let loaded = svldff1_gather_u32base_index_f32(
+        svptrue_b32(),
+        bases,
+        F32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u32base_index_s32() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1_gather_u32base_index_s32(
+        svptrue_b32(),
+        bases,
+        I32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    let loaded = svldff1_gather_u32base_index_s32(
+        svptrue_b32(),
+        bases,
+        I32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u32base_index_u32() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1_gather_u32base_index_u32(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    let loaded = svldff1_gather_u32base_index_u32(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u64base_index_f64() {
+    let bases = svdup_n_u64(F64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let _ = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap());
+    let loaded = svldff1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u64base_index_s64() {
+    let bases = svdup_n_u64(I64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let _ = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap());
+    let loaded = svldff1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u64base_index_u64() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let _ = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap());
+    let loaded = svldff1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u32base_offset_f32() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1_gather_u32base_offset_f32(
+        svptrue_b32(),
+        bases,
+        F32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+    let loaded = svldff1_gather_u32base_offset_f32(
+        svptrue_b32(),
+        bases,
+        F32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u32base_offset_s32() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1_gather_u32base_offset_s32(
+        svptrue_b32(),
+        bases,
+        I32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+    let loaded = svldff1_gather_u32base_offset_s32(
+        svptrue_b32(),
+        bases,
+        I32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u32base_offset_u32() {
+    let bases = svindex_u32(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1_gather_u32base_offset_u32(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+    let loaded = svldff1_gather_u32base_offset_u32(
+        svptrue_b32(),
+        bases,
+        U32_DATA.as_ptr() as i64 + 4u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u64base_offset_f64() {
+    let bases = svdup_n_u64(F64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let _ = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    let loaded = svldff1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(I64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let _ = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    let loaded = svldff1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(U64_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 8u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b64(), bases, offsets);
+    svsetffr();
+    let _ = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    let loaded = svldff1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_f32() {
+    svsetffr();
+    let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_f32(
+        loaded,
+        svcvt_f32_s32_x(
+            svptrue_b32(),
+            svindex_s32(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_f64() {
+    svsetffr();
+    let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_f64(
+        loaded,
+        svcvt_f64_s64_x(
+            svptrue_b64(),
+            svindex_s64(
+                (len + 0usize).try_into().unwrap(),
+                1usize.try_into().unwrap(),
+            ),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s8() {
+    svsetffr();
+    let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntb() as usize;
+    assert_vector_matches_i8(
+        loaded,
+        svindex_s8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s16() {
+    svsetffr();
+    let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_s32() {
+    svsetffr();
+    let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1);
     let len = svcntw() as usize;
     assert_vector_matches_i32(
         loaded,
@@ -7375,10 +7677,10 @@ unsafe fn test_svldff1sh_vnum_s32() {
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_vnum_s64() {
+unsafe fn test_svldff1_vnum_s64() {
     svsetffr();
-    let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1);
     let len = svcntd() as usize;
     assert_vector_matches_i64(
         loaded,
@@ -7389,115 +7691,1481 @@ unsafe fn test_svldff1sb_vnum_s64() {
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_vnum_s64() {
+unsafe fn test_svldff1_vnum_u8() {
     svsetffr();
-    let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let loaded = svldff1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
-    assert_vector_matches_i64(
+    let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1);
+    let len = svcntb() as usize;
+    assert_vector_matches_u8(
+        loaded,
+        svindex_u8(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u16() {
+    svsetffr();
+    let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u32() {
+    svsetffr();
+    let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1_vnum_u64() {
+    svsetffr();
+    let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
+    let loaded = svldff1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_s32offset_s32() {
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_s32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_s32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s32offset_s32() {
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_s32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_s32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_s32offset_u32() {
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_s32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_s32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s32offset_u32() {
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_s32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_s32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_s64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_s64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_s64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_s64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sw_gather_s64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    let loaded = svldff1sw_gather_s64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_s64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_s64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_s64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_s64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sw_gather_s64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    let loaded = svldff1sw_gather_s64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u32offset_s32() {
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_u32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_u32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32offset_s32() {
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_u32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u32offset_u32() {
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_u32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_u32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32offset_u32() {
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_u32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_u64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_u64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_u64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sw_gather_u64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    let loaded = svldff1sw_gather_u64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_u64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    let loaded = svldff1sb_gather_u64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    let loaded = svldff1sh_gather_u64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sw_gather_u64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    let loaded = svldff1sw_gather_u64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u32base_offset_s32() {
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        I8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    let loaded = svldff1sb_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        I8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32base_offset_s32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    let loaded = svldff1sh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u32base_offset_u32() {
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sb_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        I8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    let loaded = svldff1sb_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        I8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32base_offset_u32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    let loaded = svldff1sh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(I8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svsetffr();
+    let _ = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    let loaded = svldff1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(I16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    let loaded =
+        svldff1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(I32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    let loaded =
+        svldff1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(I8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svsetffr();
+    let _ = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    let loaded = svldff1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(I16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    let loaded =
+        svldff1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(I32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    let loaded =
+        svldff1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u64base_s64() {
+    let bases = svdup_n_u64(I8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svsetffr();
+    let _ = svld1sb_gather_u64base_s64(svptrue_b8(), bases);
+    let loaded = svldff1sb_gather_u64base_s64(svptrue_b8(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64base_s64() {
+    let bases = svdup_n_u64(I16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1sh_gather_u64base_s64(svptrue_b16(), bases);
+    let loaded = svldff1sh_gather_u64base_s64(svptrue_b16(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64base_s64() {
+    let bases = svdup_n_u64(I32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1sw_gather_u64base_s64(svptrue_b32(), bases);
+    let loaded = svldff1sw_gather_u64base_s64(svptrue_b32(), bases);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_gather_u64base_u64() {
+    let bases = svdup_n_u64(I8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svsetffr();
+    let _ = svld1sb_gather_u64base_u64(svptrue_b8(), bases);
+    let loaded = svldff1sb_gather_u64base_u64(svptrue_b8(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64base_u64() {
+    let bases = svdup_n_u64(I16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1sh_gather_u64base_u64(svptrue_b16(), bases);
+    let loaded = svldff1sh_gather_u64base_u64(svptrue_b16(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64base_u64() {
+    let bases = svdup_n_u64(I32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1sw_gather_u64base_u64(svptrue_b32(), bases);
+    let loaded = svldff1sw_gather_u64base_u64(svptrue_b32(), bases);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_s16() {
+    svsetffr();
+    let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_s16(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_s32() {
+    svsetffr();
+    let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_s32(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_s32() {
+    svsetffr();
+    let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_s32(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_s64() {
+    svsetffr();
+    let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_s64(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_s64() {
+    svsetffr();
+    let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_s64(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_s64() {
+    svsetffr();
+    let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldff1sw_s64(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_u16() {
+    svsetffr();
+    let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_u16(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_u32() {
+    svsetffr();
+    let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_u32(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_u32() {
+    svsetffr();
+    let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_u32(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_u64() {
+    svsetffr();
+    let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
+    let loaded = svldff1sb_u64(svptrue_b8(), I8_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_u64() {
+    svsetffr();
+    let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
+    let loaded = svldff1sh_u64(svptrue_b16(), I16_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_u64() {
+    svsetffr();
+    let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    let loaded = svldff1sw_u64(svptrue_b32(), I32_DATA.as_ptr());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_s16() {
+    svsetffr();
+    let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_i16(
+        loaded,
+        svindex_s16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_s32() {
+    svsetffr();
+    let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_s32() {
+    svsetffr();
+    let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_s64() {
+    svsetffr();
+    let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_s64() {
+    svsetffr();
+    let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_vnum_s64() {
+    svsetffr();
+    let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldff1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_u16() {
+    svsetffr();
+    let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcnth() as usize;
+    assert_vector_matches_u16(
+        loaded,
+        svindex_u16(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_u32() {
+    svsetffr();
+    let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_u32() {
+    svsetffr();
+    let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntw() as usize;
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sb_vnum_u64() {
+    svsetffr();
+    let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let loaded = svldff1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_vnum_u64() {
+    svsetffr();
+    let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let loaded = svldff1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_vnum_u64() {
+    svsetffr();
+    let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let loaded = svldff1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
+    let len = svcntd() as usize;
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64(
+            (len + 0usize).try_into().unwrap(),
+            1usize.try_into().unwrap(),
+        ),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s32index_s32() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_s32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_s32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s32index_u32() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_s32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_s32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s64index_s64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_s64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_s64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_s64index_s64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1sw_gather_s64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    let loaded = svldff1sw_gather_s64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_s64index_u64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_s64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_s64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_s64index_u64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1sw_gather_s64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    let loaded = svldff1sw_gather_s64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32index_s32() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_u32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_u32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32index_u32() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_u32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_u32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64index_s64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_u64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_u64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64index_s64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1sw_gather_u64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    let loaded = svldff1sw_gather_u64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64index_u64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1sh_gather_u64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    let loaded = svldff1sh_gather_u64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64index_u64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1sw_gather_u64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    let loaded = svldff1sw_gather_u64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32base_index_s32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    let loaded = svldff1sh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u32base_index_u32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1sh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    let loaded = svldff1sh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64base_index_s64() {
+    let bases = svdup_n_u64(I16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    let loaded = svldff1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64base_index_s64() {
+    let bases = svdup_n_u64(I32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    let loaded = svldff1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sh_gather_u64base_index_u64() {
+    let bases = svdup_n_u64(I16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    let loaded = svldff1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1sw_gather_u64base_index_u64() {
+    let bases = svdup_n_u64(I32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    let loaded = svldff1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_s32offset_s32() {
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_s32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_s32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s32offset_s32() {
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_s32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_s32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_s32offset_u32() {
+    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_s32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_s32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s32offset_u32() {
+    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_s32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_s32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_s64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_s64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_s64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_s64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_s64offset_s64() {
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uw_gather_s64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    let loaded = svldff1uw_gather_s64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_s64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_s64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_s64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_s64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_s64offset_u64() {
+    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uw_gather_s64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    let loaded = svldff1uw_gather_s64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u32offset_s32() {
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_u32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_u32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32offset_s32() {
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_u32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u32offset_u32() {
+    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_u32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_u32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32offset_u32() {
+    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_u32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_u64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_u64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_u64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64offset_s64() {
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uw_gather_u64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    let loaded = svldff1uw_gather_u64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_u64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    let loaded = svldff1ub_gather_u64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    let loaded = svldff1uh_gather_u64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64offset_u64() {
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uw_gather_u64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    let loaded = svldff1uw_gather_u64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u32base_offset_s32() {
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        U8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    let loaded = svldff1ub_gather_u32base_offset_s32(
+        svptrue_b8(),
+        bases,
+        U8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32base_offset_s32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    let loaded = svldff1uh_gather_u32base_offset_s32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u32base_offset_u32() {
+    let bases = svindex_u32(0, 1u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1ub_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        U8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    let loaded = svldff1ub_gather_u32base_offset_u32(
+        svptrue_b8(),
+        bases,
+        U8_DATA.as_ptr() as i64 + 1u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32base_offset_u32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    let loaded = svldff1uh_gather_u32base_offset_u32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 + 2u32 as i64,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(U8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svsetffr();
+    let _ = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    let loaded = svldff1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(U16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    let loaded =
+        svldff1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64base_offset_s64() {
+    let bases = svdup_n_u64(U32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    let loaded =
+        svldff1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1ub_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(U8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
+    svsetffr();
+    let _ = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    let loaded = svldff1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(U16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    let loaded =
+        svldff1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap());
+    assert_vector_matches_u64(
         loaded,
-        svindex_s64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sw_vnum_s64() {
+unsafe fn test_svldff1uw_gather_u64base_offset_u64() {
+    let bases = svdup_n_u64(U32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
     svsetffr();
-    let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
-    let loaded = svldff1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
-    assert_vector_matches_i64(
+    let _ = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    let loaded =
+        svldff1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap());
+    assert_vector_matches_u64(
         loaded,
-        svindex_s64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_vnum_u16() {
+unsafe fn test_svldff1ub_gather_u64base_s64() {
+    let bases = svdup_n_u64(U8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
     svsetffr();
-    let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let len = svcnth() as usize;
-    assert_vector_matches_u16(
+    let _ = svld1ub_gather_u64base_s64(svptrue_b8(), bases);
+    let loaded = svldff1ub_gather_u64base_s64(svptrue_b8(), bases);
+    assert_vector_matches_i64(
         loaded,
-        svindex_u16(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_vnum_u32() {
+unsafe fn test_svldff1uh_gather_u64base_s64() {
+    let bases = svdup_n_u64(U16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
     svsetffr();
-    let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let len = svcntw() as usize;
-    assert_vector_matches_u32(
+    let _ = svld1uh_gather_u64base_s64(svptrue_b16(), bases);
+    let loaded = svldff1uh_gather_u64base_s64(svptrue_b16(), bases);
+    assert_vector_matches_i64(
         loaded,
-        svindex_u32(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_vnum_u32() {
+unsafe fn test_svldff1uw_gather_u64base_s64() {
+    let bases = svdup_n_u64(U32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
     svsetffr();
-    let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let loaded = svldff1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let len = svcntw() as usize;
-    assert_vector_matches_u32(
+    let _ = svld1uw_gather_u64base_s64(svptrue_b32(), bases);
+    let loaded = svldff1uw_gather_u64base_s64(svptrue_b32(), bases);
+    assert_vector_matches_i64(
         loaded,
-        svindex_u32(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sb_vnum_u64() {
+unsafe fn test_svldff1ub_gather_u64base_u64() {
+    let bases = svdup_n_u64(U8_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
     svsetffr();
-    let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let loaded = svldff1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
+    let _ = svld1ub_gather_u64base_u64(svptrue_b8(), bases);
+    let loaded = svldff1ub_gather_u64base_u64(svptrue_b8(), bases);
     assert_vector_matches_u64(
         loaded,
-        svindex_u64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sh_vnum_u64() {
+unsafe fn test_svldff1uh_gather_u64base_u64() {
+    let bases = svdup_n_u64(U16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
     svsetffr();
-    let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let loaded = svldff1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
+    let _ = svld1uh_gather_u64base_u64(svptrue_b16(), bases);
+    let loaded = svldff1uh_gather_u64base_u64(svptrue_b16(), bases);
     assert_vector_matches_u64(
         loaded,
-        svindex_u64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
-unsafe fn test_svldff1sw_vnum_u64() {
+unsafe fn test_svldff1uw_gather_u64base_u64() {
+    let bases = svdup_n_u64(U32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
     svsetffr();
-    let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
-    let loaded = svldff1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1);
-    let len = svcntd() as usize;
+    let _ = svld1uw_gather_u64base_u64(svptrue_b32(), bases);
+    let loaded = svldff1uw_gather_u64base_u64(svptrue_b32(), bases);
     assert_vector_matches_u64(
         loaded,
-        svindex_u64(
-            (len + 0usize).try_into().unwrap(),
-            1usize.try_into().unwrap(),
-        ),
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
     );
 }
 #[simd_test(enable = "sve")]
@@ -7789,6 +9457,228 @@ unsafe fn test_svldff1uw_vnum_u64() {
     );
 }
 #[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s32index_s32() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_s32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_s32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s32index_u32() {
+    let indices = svindex_s32(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_s32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_s32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s64index_s64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_s64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_s64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_s64index_s64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1uw_gather_s64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    let loaded = svldff1uw_gather_s64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_s64index_u64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_s64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_s64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_s64index_u64() {
+    let indices = svindex_s64(0, 1);
+    svsetffr();
+    let _ = svld1uw_gather_s64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    let loaded = svldff1uw_gather_s64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32index_s32() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_u32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_u32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32index_u32() {
+    let indices = svindex_u32(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_u32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_u32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64index_s64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_u64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_u64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64index_s64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1uw_gather_u64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    let loaded = svldff1uw_gather_u64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64index_u64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1uh_gather_u64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    let loaded = svldff1uh_gather_u64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64index_u64() {
+    let indices = svindex_u64(0, 1);
+    svsetffr();
+    let _ = svld1uw_gather_u64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    let loaded = svldff1uw_gather_u64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices);
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32base_index_s32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    let loaded = svldff1uh_gather_u32base_index_s32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_i32(
+        loaded,
+        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u32base_index_u32() {
+    let bases = svindex_u32(0, 2u32.try_into().unwrap());
+    svsetffr();
+    let _ = svld1uh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    let loaded = svldff1uh_gather_u32base_index_u32(
+        svptrue_b16(),
+        bases,
+        U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1,
+    );
+    assert_vector_matches_u32(
+        loaded,
+        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64base_index_s64() {
+    let bases = svdup_n_u64(U16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    let loaded = svldff1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64base_index_s64() {
+    let bases = svdup_n_u64(U32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    let loaded = svldff1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_i64(
+        loaded,
+        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uh_gather_u64base_index_u64() {
+    let bases = svdup_n_u64(U16_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
+    svsetffr();
+    let _ = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    let loaded = svldff1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
+unsafe fn test_svldff1uw_gather_u64base_index_u64() {
+    let bases = svdup_n_u64(U32_DATA.as_ptr() as u64);
+    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
+    let bases = svadd_u64_x(svptrue_b32(), bases, offsets);
+    svsetffr();
+    let _ = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    let loaded = svldff1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap());
+    assert_vector_matches_u64(
+        loaded,
+        svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
+    );
+}
+#[simd_test(enable = "sve")]
 unsafe fn test_svldnf1_f32() {
     svsetffr();
     let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr());
diff --git a/crates/stdarch-gen-arm/src/load_store_tests.rs b/crates/stdarch-gen-arm/src/load_store_tests.rs
index 0f4de83dac..cbd5df50de 100644
--- a/crates/stdarch-gen-arm/src/load_store_tests.rs
+++ b/crates/stdarch-gen-arm/src/load_store_tests.rs
@@ -141,13 +141,6 @@ fn generate_single_test(
         }
     }
 
-    if fn_name.starts_with("svldff1") && fn_name.contains("gather") {
-        // TODO: We can remove this check when first-faulting gathers are fixed in CI's QEMU
-        // https://gitlab.com/qemu-project/qemu/-/issues/1612
-        println!("Skipping test for {fn_name}");
-        return Ok(quote!());
-    }
-
     let fn_ident = format_ident!("{fn_name}");
     let test_name = format_ident!(
         "test_{fn_name}{}",

From eb8250b7e347bcd5bdcada8b0a003cf9d2b75f0a Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 14 Apr 2026 14:38:28 +0530
Subject: [PATCH 258/326] Remove uses of asm

---
 crates/core_arch/src/x86/avx512bf16.rs   |  38 +-----
 crates/core_arch/src/x86/avx512fp16.rs   | 154 +++++------------------
 crates/core_arch/src/x86/avxneconvert.rs |  28 ++---
 3 files changed, 43 insertions(+), 177 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512bf16.rs b/crates/core_arch/src/x86/avx512bf16.rs
index 66eef063ee..8d944f5ba8 100644
--- a/crates/core_arch/src/x86/avx512bf16.rs
+++ b/crates/core_arch/src/x86/avx512bf16.rs
@@ -2,7 +2,6 @@
 //!
 //! [AVX512BF16 intrinsics]: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769&avx512techs=AVX512_BF16
 
-use crate::arch::asm;
 use crate::core_arch::{simd::*, x86::*};
 use crate::intrinsics::simd::*;
 
@@ -17,6 +16,8 @@ unsafe extern "C" {
     fn cvtne2ps2bf16_256(a: f32x8, b: f32x8) -> i16x16;
     #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.512"]
     fn cvtne2ps2bf16_512(a: f32x16, b: f32x16) -> i16x32;
+    #[link_name = "llvm.x86.avx512bf16.mask.cvtneps2bf16.128"]
+    fn cvtneps2bf16_128(a: f32x4, src: i16x8, k: __mmask8) -> i16x8;
     #[link_name = "llvm.x86.avx512bf16.cvtneps2bf16.256"]
     fn cvtneps2bf16_256(a: f32x8) -> i16x8;
     #[link_name = "llvm.x86.avx512bf16.cvtneps2bf16.512"]
@@ -519,16 +520,7 @@ pub fn _mm_cvtsbh_ss(a: bf16) -> f32 {
 #[cfg_attr(test, assert_instr("vcvtneps2bf16"))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh {
-    unsafe {
-        let mut dst: __m128bh;
-        asm!(
-            "vcvtneps2bf16 {dst}, {src}",
-            dst = lateout(xmm_reg) dst,
-            src = in(xmm_reg) a,
-            options(pure, nomem, nostack, preserves_flags)
-        );
-        dst
-    }
+    _mm_mask_cvtneps_pbh(__m128bh::splat(0), !0, a)
 }
 
 /// Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit)
@@ -541,17 +533,7 @@ pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh {
 #[cfg_attr(test, assert_instr("vcvtneps2bf16"))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh {
-    unsafe {
-        let mut dst = src;
-        asm!(
-            "vcvtneps2bf16 {dst}{{{k}}},{src}",
-            dst = inlateout(xmm_reg) dst,
-            src = in(xmm_reg) a,
-            k = in(kreg) k,
-            options(pure, nomem, nostack, preserves_flags)
-        );
-        dst
-    }
+    unsafe { cvtneps2bf16_128(a.as_f32x4(), src.as_i16x8(), k).as_m128bh() }
 }
 
 /// Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit)
@@ -564,17 +546,7 @@ pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh {
 #[cfg_attr(test, assert_instr("vcvtneps2bf16"))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_maskz_cvtneps_pbh(k: __mmask8, a: __m128) -> __m128bh {
-    unsafe {
-        let mut dst: __m128bh;
-        asm!(
-            "vcvtneps2bf16 {dst}{{{k}}}{{z}},{src}",
-            dst = lateout(xmm_reg) dst,
-            src = in(xmm_reg) a,
-            k = in(kreg) k,
-            options(pure, nomem, nostack, preserves_flags)
-        );
-        dst
-    }
+    _mm_mask_cvtneps_pbh(__m128bh::splat(0), k, a)
 }
 
 /// Converts a single-precision (32-bit) floating-point element in a to a BF16 (16-bit) floating-point
diff --git a/crates/core_arch/src/x86/avx512fp16.rs b/crates/core_arch/src/x86/avx512fp16.rs
index 8ddc3d29a3..6523e98d0c 100644
--- a/crates/core_arch/src/x86/avx512fp16.rs
+++ b/crates/core_arch/src/x86/avx512fp16.rs
@@ -695,34 +695,6 @@ pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h {
     }
 }
 
-macro_rules! cmp_asm { // FIXME: use LLVM intrinsics
-    ($mask_type: ty, $reg: ident, $a: expr, $b: expr) => {{
-        let dst: $mask_type;
-        asm!(
-            "vcmpph {k}, {a}, {b}, {imm8}",
-            k = lateout(kreg) dst,
-            a = in($reg) $a,
-            b = in($reg) $b,
-            imm8 = const IMM5,
-            options(pure, nomem, nostack)
-        );
-        dst
-    }};
-    ($mask_type: ty, $mask: expr, $reg: ident, $a: expr, $b: expr) => {{
-        let dst: $mask_type;
-        asm!(
-            "vcmpph {k} {{ {mask} }}, {a}, {b}, {imm8}",
-            k = lateout(kreg) dst,
-            mask = in(kreg) $mask,
-            a = in($reg) $a,
-            b = in($reg) $b,
-            imm8 = const IMM5,
-            options(pure, nomem, nostack)
-        );
-        dst
-    }};
-}
-
 /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
 /// operand specified by imm8, and store the results in mask vector k.
 ///
@@ -732,10 +704,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM5, 5);
-        cmp_asm!(__mmask8, xmm_reg, a, b)
-    }
+    _mm_mask_cmp_ph_mask::<IMM5>(!0, a, b)
 }
 
 /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
@@ -750,7 +719,7 @@ pub fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
 pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
-        cmp_asm!(__mmask8, k1, xmm_reg, a, b)
+        vcmpph_128(a, b, IMM5, k1)
     }
 }
 
@@ -763,10 +732,7 @@ pub fn _mm_mask_cmp_ph_mask<const IMM5: i32>(k1: __mmask8, a: __m128h, b: __m128
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16 {
-    unsafe {
-        static_assert_uimm_bits!(IMM5, 5);
-        cmp_asm!(__mmask16, ymm_reg, a, b)
-    }
+    _mm256_mask_cmp_ph_mask::<IMM5>(!0, a, b)
 }
 
 /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
@@ -785,7 +751,7 @@ pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
 ) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
-        cmp_asm!(__mmask16, k1, ymm_reg, a, b)
+        vcmpph_256(a, b, IMM5, k1)
     }
 }
 
@@ -798,10 +764,7 @@ pub fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32 {
-    unsafe {
-        static_assert_uimm_bits!(IMM5, 5);
-        cmp_asm!(__mmask32, zmm_reg, a, b)
-    }
+    _mm512_mask_cmp_ph_mask::<IMM5>(!0, a, b)
 }
 
 /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
@@ -818,10 +781,7 @@ pub fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
     a: __m512h,
     b: __m512h,
 ) -> __mmask32 {
-    unsafe {
-        static_assert_uimm_bits!(IMM5, 5);
-        cmp_asm!(__mmask32, k1, zmm_reg, a, b)
-    }
+    _mm512_mask_cmp_round_ph_mask::<IMM5, _MM_FROUND_CUR_DIRECTION>(k1, a, b)
 }
 
 /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
@@ -838,24 +798,7 @@ pub fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
     a: __m512h,
     b: __m512h,
 ) -> __mmask32 {
-    unsafe {
-        static_assert_uimm_bits!(IMM5, 5);
-        static_assert_sae!(SAE);
-        if SAE == _MM_FROUND_NO_EXC {
-            let dst: __mmask32;
-            asm!(
-                "vcmpph {k}, {a}, {b}, {{sae}}, {imm8}",
-                k = lateout(kreg) dst,
-                a = in(zmm_reg) a,
-                b = in(zmm_reg) b,
-                imm8 = const IMM5,
-                options(pure, nomem, nostack)
-            );
-            dst
-        } else {
-            cmp_asm!(__mmask32, zmm_reg, a, b)
-        }
-    }
+    _mm512_mask_cmp_round_ph_mask::<IMM5, SAE>(!0, a, b)
 }
 
 /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison
@@ -877,21 +820,7 @@ pub fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
     unsafe {
         static_assert_uimm_bits!(IMM5, 5);
         static_assert_sae!(SAE);
-        if SAE == _MM_FROUND_NO_EXC {
-            let dst: __mmask32;
-            asm!(
-                "vcmpph {k} {{{k1}}}, {a}, {b}, {{sae}}, {imm8}",
-                k = lateout(kreg) dst,
-                k1 = in(kreg) k1,
-                a = in(zmm_reg) a,
-                b = in(zmm_reg) b,
-                imm8 = const IMM5,
-                options(pure, nomem, nostack)
-            );
-            dst
-        } else {
-            cmp_asm!(__mmask32, k1, zmm_reg, a, b)
-        }
+        vcmpph_512(a, b, IMM5, k1, SAE)
     }
 }
 
@@ -11538,32 +11467,6 @@ pub fn _mm512_reduce_max_ph(a: __m512h) -> f16 {
     }
 }
 
-macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics
-    ($mask_type: ty, $reg: ident, $a: expr) => {{
-        let dst: $mask_type;
-        asm!(
-            "vfpclassph {k}, {src}, {imm8}",
-            k = lateout(kreg) dst,
-            src = in($reg) $a,
-            imm8 = const IMM8,
-            options(pure, nomem, nostack)
-        );
-        dst
-    }};
-    ($mask_type: ty, $mask: expr, $reg: ident, $a: expr) => {{
-        let dst: $mask_type;
-        asm!(
-            "vfpclassph {k} {{ {mask} }}, {src}, {imm8}",
-            k = lateout(kreg) dst,
-            mask = in(kreg) $mask,
-            src = in($reg) $a,
-            imm8 = const IMM8,
-            options(pure, nomem, nostack)
-        );
-        dst
-    }};
-}
-
 /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
 /// by imm8, and store the results in mask vector k.
 /// imm can be a combination of:
@@ -11586,7 +11489,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics
 pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
-        fpclass_asm!(__mmask8, xmm_reg, a)
+        vfpclassph_128(a, IMM8)
     }
 }
 
@@ -11611,10 +11514,7 @@ pub fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        fpclass_asm!(__mmask8, k1, xmm_reg, a)
-    }
+    _mm_fpclass_ph_mask::<IMM8>(a) & k1
 }
 
 /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
@@ -11639,7 +11539,7 @@ pub fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h) -> __
 pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
-        fpclass_asm!(__mmask16, ymm_reg, a)
+        vfpclassph_256(a, IMM8)
     }
 }
 
@@ -11664,10 +11564,7 @@ pub fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -> __mmask16 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        fpclass_asm!(__mmask16, k1, ymm_reg, a)
-    }
+    _mm256_fpclass_ph_mask::<IMM8>(a) & k1
 }
 
 /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified
@@ -11692,7 +11589,7 @@ pub fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m256h) -
 pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
     unsafe {
         static_assert_uimm_bits!(IMM8, 8);
-        fpclass_asm!(__mmask32, zmm_reg, a)
+        vfpclassph_512(a, IMM8)
     }
 }
 
@@ -11717,10 +11614,7 @@ pub fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")]
 pub fn _mm512_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask32, a: __m512h) -> __mmask32 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        fpclass_asm!(__mmask32, k1, zmm_reg, a)
-    }
+    _mm512_fpclass_ph_mask::<IMM8>(a) & k1
 }
 
 /// Test the lower half-precision (16-bit) floating-point element in a for special categories specified
@@ -16571,11 +16465,18 @@ pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i {
 }
 
 #[allow(improper_ctypes)]
-unsafe extern "C" {
+unsafe extern "unadjusted" {
+    #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.128"]
+    fn vcmpph_128(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8) -> __mmask8;
+    #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.256"]
+    fn vcmpph_256(a: __m256h, b: __m256h, imm5: i32, mask: __mmask16) -> __mmask16;
+    #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.512"]
+    fn vcmpph_512(a: __m512h, b: __m512h, imm5: i32, mask: __mmask32, sae: i32) -> __mmask32;
+
     #[link_name = "llvm.x86.avx512fp16.mask.cmp.sh"]
-    fn vcmpsh(a: __m128h, b: __m128h, imm8: i32, mask: __mmask8, sae: i32) -> __mmask8;
+    fn vcmpsh(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8, sae: i32) -> __mmask8;
     #[link_name = "llvm.x86.avx512fp16.vcomi.sh"]
-    fn vcomish(a: __m128h, b: __m128h, imm8: i32, sae: i32) -> i32;
+    fn vcomish(a: __m128h, b: __m128h, imm5: i32, sae: i32) -> i32;
 
     #[link_name = "llvm.x86.avx512fp16.add.ph.512"]
     fn vaddph(a: __m512h, b: __m512h, rounding: i32) -> __m512h;
@@ -16758,6 +16659,13 @@ unsafe extern "C" {
     fn vreducesh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, imm8: i32, sae: i32)
     -> __m128h;
 
+    #[link_name = "llvm.x86.avx512fp16.fpclass.ph.128"]
+    fn vfpclassph_128(a: __m128h, imm8: i32) -> __mmask8;
+    #[link_name = "llvm.x86.avx512fp16.fpclass.ph.256"]
+    fn vfpclassph_256(a: __m256h, imm8: i32) -> __mmask16;
+    #[link_name = "llvm.x86.avx512fp16.fpclass.ph.512"]
+    fn vfpclassph_512(a: __m512h, imm8: i32) -> __mmask32;
+
     #[link_name = "llvm.x86.avx512fp16.mask.fpclass.sh"]
     fn vfpclasssh(a: __m128h, imm8: i32, k: __mmask8) -> __mmask8;
 
diff --git a/crates/core_arch/src/x86/avxneconvert.rs b/crates/core_arch/src/x86/avxneconvert.rs
index b8a3b9473a..861213eb42 100644
--- a/crates/core_arch/src/x86/avxneconvert.rs
+++ b/crates/core_arch/src/x86/avxneconvert.rs
@@ -1,4 +1,3 @@
-use crate::arch::asm;
 use crate::core_arch::x86::*;
 
 #[cfg(test)]
@@ -161,16 +160,7 @@ pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 {
 #[cfg_attr(test, assert_instr(vcvtneps2bf16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh {
-    unsafe {
-        let mut dst: __m128bh;
-        asm!(
-            "{{vex}}vcvtneps2bf16 {dst},{src}",
-            dst = lateout(xmm_reg) dst,
-            src = in(xmm_reg) a,
-            options(pure, nomem, nostack, preserves_flags)
-        );
-        dst
-    }
+    unsafe { vcvtneps2bf16_128(a) }
 }
 
 /// Convert packed single precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point
@@ -182,16 +172,7 @@ pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh {
 #[cfg_attr(test, assert_instr(vcvtneps2bf16))]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_cvtneps_avx_pbh(a: __m256) -> __m128bh {
-    unsafe {
-        let mut dst: __m128bh;
-        asm!(
-            "{{vex}}vcvtneps2bf16 {dst},{src}",
-            dst = lateout(xmm_reg) dst,
-            src = in(ymm_reg) a,
-            options(pure, nomem, nostack, preserves_flags)
-        );
-        dst
-    }
+    unsafe { vcvtneps2bf16_256(a) }
 }
 
 #[allow(improper_ctypes)]
@@ -222,6 +203,11 @@ unsafe extern "C" {
     fn cvtneoph2ps_128(a: *const __m128h) -> __m128;
     #[link_name = "llvm.x86.vcvtneoph2ps256"]
     fn cvtneoph2ps_256(a: *const __m256h) -> __m256;
+
+    #[link_name = "llvm.x86.vcvtneps2bf16128"]
+    fn vcvtneps2bf16_128(a: __m128) -> __m128bh;
+    #[link_name = "llvm.x86.vcvtneps2bf16256"]
+    fn vcvtneps2bf16_256(a: __m256) -> __m128bh;
 }
 
 #[cfg(test)]

From 84ed8350fc967d19a7bd1ff28e801c7508984b22 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 16 Apr 2026 11:23:54 +0530
Subject: [PATCH 259/326] Remove uses of deprecated intrinsics

---
 crates/core_arch/src/aarch64/sve/generated.rs | 32 ++++-----
 crates/core_arch/src/x86/avx512bitalg.rs      | 24 +++----
 crates/core_arch/src/x86/avx512dq.rs          | 68 +++++++------------
 crates/core_arch/src/x86/avx512f.rs           | 18 ++---
 .../stdarch-gen-arm/spec/sve/aarch64.spec.yml | 12 ++--
 5 files changed, 65 insertions(+), 89 deletions(-)

diff --git a/crates/core_arch/src/aarch64/sve/generated.rs b/crates/core_arch/src/aarch64/sve/generated.rs
index ed28e98a81..5f26d61e7c 100644
--- a/crates/core_arch/src/aarch64/sve/generated.rs
+++ b/crates/core_arch/src/aarch64/sve/generated.rs
@@ -9799,7 +9799,7 @@ pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.experimental.vector.insert.nxv4f32.v4f32"
+            link_name = "llvm.vector.insert.nxv4f32.v4f32"
         )]
         fn _svdupq_n_f32(op0: svfloat32_t, op1: float32x4_t, idx: i64) -> svfloat32_t;
     }
@@ -9817,7 +9817,7 @@ pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.experimental.vector.insert.nxv4i32.v4i32"
+            link_name = "llvm.vector.insert.nxv4i32.v4i32"
         )]
         fn _svdupq_n_s32(op0: svint32_t, op1: int32x4_t, idx: i64) -> svint32_t;
     }
@@ -9851,7 +9851,7 @@ pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.experimental.vector.insert.nxv2f64.v2f64"
+            link_name = "llvm.vector.insert.nxv2f64.v2f64"
         )]
         fn _svdupq_n_f64(op0: svfloat64_t, op1: float64x2_t, idx: i64) -> svfloat64_t;
     }
@@ -9869,7 +9869,7 @@ pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.experimental.vector.insert.nxv2i64.v2i64"
+            link_name = "llvm.vector.insert.nxv2i64.v2i64"
         )]
         fn _svdupq_n_s64(op0: svint64_t, op1: int64x2_t, idx: i64) -> svint64_t;
     }
@@ -9904,7 +9904,7 @@ pub fn svdupq_n_s16(
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.experimental.vector.insert.nxv8i16.v8i16"
+            link_name = "llvm.vector.insert.nxv8i16.v8i16"
         )]
         fn _svdupq_n_s16(op0: svint16_t, op1: int16x8_t, idx: i64) -> svint16_t;
     }
@@ -9972,7 +9972,7 @@ pub fn svdupq_n_s8(
     unsafe extern "unadjusted" {
         #[cfg_attr(
             target_arch = "aarch64",
-            link_name = "llvm.experimental.vector.insert.nxv16i8.v16i8"
+            link_name = "llvm.vector.insert.nxv16i8.v16i8"
         )]
         fn _svdupq_n_s8(op0: svint8_t, op1: int8x16_t, idx: i64) -> svint8_t;
     }
@@ -35208,7 +35208,7 @@ pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b8(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv16i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i1")]
         fn _svrev_b8(op: svbool_t) -> svbool_t;
     }
     unsafe { _svrev_b8(op) }
@@ -35221,7 +35221,7 @@ pub fn svrev_b8(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b16(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv8i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv8i1")]
         fn _svrev_b16(op: svbool8_t) -> svbool8_t;
     }
     unsafe { _svrev_b16(op.sve_into()).sve_into() }
@@ -35234,7 +35234,7 @@ pub fn svrev_b16(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b32(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4i1")]
         fn _svrev_b32(op: svbool4_t) -> svbool4_t;
     }
     unsafe { _svrev_b32(op.sve_into()).sve_into() }
@@ -35247,7 +35247,7 @@ pub fn svrev_b32(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_b64(op: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2i1")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2i1")]
         fn _svrev_b64(op: svbool2_t) -> svbool2_t;
     }
     unsafe { _svrev_b64(op.sve_into()).sve_into() }
@@ -35260,7 +35260,7 @@ pub fn svrev_b64(op: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4f32")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4f32")]
         fn _svrev_f32(op: svfloat32_t) -> svfloat32_t;
     }
     unsafe { _svrev_f32(op) }
@@ -35273,7 +35273,7 @@ pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2f64")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2f64")]
         fn _svrev_f64(op: svfloat64_t) -> svfloat64_t;
     }
     unsafe { _svrev_f64(op) }
@@ -35286,7 +35286,7 @@ pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_s8(op: svint8_t) -> svint8_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv16i8")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i8")]
         fn _svrev_s8(op: svint8_t) -> svint8_t;
     }
     unsafe { _svrev_s8(op) }
@@ -35299,7 +35299,7 @@ pub fn svrev_s8(op: svint8_t) -> svint8_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_s16(op: svint16_t) -> svint16_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv8i16")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv8i16")]
         fn _svrev_s16(op: svint16_t) -> svint16_t;
     }
     unsafe { _svrev_s16(op) }
@@ -35312,7 +35312,7 @@ pub fn svrev_s16(op: svint16_t) -> svint16_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_s32(op: svint32_t) -> svint32_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4i32")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4i32")]
         fn _svrev_s32(op: svint32_t) -> svint32_t;
     }
     unsafe { _svrev_s32(op) }
@@ -35325,7 +35325,7 @@ pub fn svrev_s32(op: svint32_t) -> svint32_t {
 #[cfg_attr(test, assert_instr(rev))]
 pub fn svrev_s64(op: svint64_t) -> svint64_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2i64")]
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2i64")]
         fn _svrev_s64(op: svint64_t) -> svint64_t;
     }
     unsafe { _svrev_s64(op) }
diff --git a/crates/core_arch/src/x86/avx512bitalg.rs b/crates/core_arch/src/x86/avx512bitalg.rs
index 6dd4e6b33a..dd211854af 100644
--- a/crates/core_arch/src/x86/avx512bitalg.rs
+++ b/crates/core_arch/src/x86/avx512bitalg.rs
@@ -28,12 +28,12 @@ use stdarch_test::assert_instr;
 
 #[allow(improper_ctypes)]
 unsafe extern "C" {
-    #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.512"]
-    fn bitshuffle_512(data: i8x64, indices: i8x64, mask: __mmask64) -> __mmask64;
-    #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.256"]
-    fn bitshuffle_256(data: i8x32, indices: i8x32, mask: __mmask32) -> __mmask32;
-    #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.128"]
-    fn bitshuffle_128(data: i8x16, indices: i8x16, mask: __mmask16) -> __mmask16;
+    #[link_name = "llvm.x86.avx512.vpshufbitqmb.512"]
+    fn bitshuffle_512(data: i8x64, indices: i8x64) -> __mmask64;
+    #[link_name = "llvm.x86.avx512.vpshufbitqmb.256"]
+    fn bitshuffle_256(data: i8x32, indices: i8x32) -> __mmask32;
+    #[link_name = "llvm.x86.avx512.vpshufbitqmb.128"]
+    fn bitshuffle_128(data: i8x16, indices: i8x16) -> __mmask16;
 }
 
 /// For each packed 16-bit integer maps the value to the number of logical 1 bits.
@@ -370,7 +370,7 @@ pub const fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufbitqmb))]
 pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 {
-    unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), !0) }
+    unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64()) }
 }
 
 /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers.
@@ -386,7 +386,7 @@ pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufbitqmb))]
 pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) -> __mmask64 {
-    unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), k) }
+    _mm512_bitshuffle_epi64_mask(b, c) & k
 }
 
 /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers.
@@ -399,7 +399,7 @@ pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufbitqmb))]
 pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 {
-    unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), !0) }
+    unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32()) }
 }
 
 /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers.
@@ -415,7 +415,7 @@ pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufbitqmb))]
 pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) -> __mmask32 {
-    unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), k) }
+    _mm256_bitshuffle_epi64_mask(b, c) & k
 }
 
 /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers.
@@ -428,7 +428,7 @@ pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufbitqmb))]
 pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 {
-    unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), !0) }
+    unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16()) }
 }
 
 /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers.
@@ -444,7 +444,7 @@ pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vpshufbitqmb))]
 pub fn _mm_mask_bitshuffle_epi64_mask(k: __mmask16, b: __m128i, c: __m128i) -> __mmask16 {
-    unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), k) }
+    _mm_bitshuffle_epi64_mask(b, c) & k
 }
 
 #[cfg(test)]
diff --git a/crates/core_arch/src/x86/avx512dq.rs b/crates/core_arch/src/x86/avx512dq.rs
index 9e1a4c0b29..0b322c8b83 100644
--- a/crates/core_arch/src/x86/avx512dq.rs
+++ b/crates/core_arch/src/x86/avx512dq.rs
@@ -6865,7 +6865,7 @@ pub fn _mm_maskz_reduce_ss<const IMM8: i32>(k: __mmask8, a: __m128, b: __m128) -
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_fpclass_pd_mask<const IMM8: i32>(a: __m128d) -> __mmask8 {
     static_assert_uimm_bits!(IMM8, 8);
-    _mm_mask_fpclass_pd_mask::<IMM8>(0xff, a)
+    unsafe { vfpclasspd_128(a.as_f64x2(), IMM8) }
 }
 
 /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified
@@ -6889,10 +6889,7 @@ pub fn _mm_fpclass_pd_mask<const IMM8: i32>(a: __m128d) -> __mmask8 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_fpclass_pd_mask<const IMM8: i32>(k1: __mmask8, a: __m128d) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        transmute(vfpclasspd_128(a.as_f64x2(), IMM8, k1))
-    }
+    _mm_fpclass_pd_mask::<IMM8>(a) & k1
 }
 
 /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified
@@ -6916,7 +6913,7 @@ pub fn _mm_mask_fpclass_pd_mask<const IMM8: i32>(k1: __mmask8, a: __m128d) -> __
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_fpclass_pd_mask<const IMM8: i32>(a: __m256d) -> __mmask8 {
     static_assert_uimm_bits!(IMM8, 8);
-    _mm256_mask_fpclass_pd_mask::<IMM8>(0xff, a)
+    unsafe { vfpclasspd_256(a.as_f64x4(), IMM8) }
 }
 
 /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified
@@ -6940,10 +6937,7 @@ pub fn _mm256_fpclass_pd_mask<const IMM8: i32>(a: __m256d) -> __mmask8 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_mask_fpclass_pd_mask<const IMM8: i32>(k1: __mmask8, a: __m256d) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        transmute(vfpclasspd_256(a.as_f64x4(), IMM8, k1))
-    }
+    _mm256_fpclass_pd_mask::<IMM8>(a) & k1
 }
 
 /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified
@@ -6967,7 +6961,7 @@ pub fn _mm256_mask_fpclass_pd_mask<const IMM8: i32>(k1: __mmask8, a: __m256d) ->
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_fpclass_pd_mask<const IMM8: i32>(a: __m512d) -> __mmask8 {
     static_assert_uimm_bits!(IMM8, 8);
-    _mm512_mask_fpclass_pd_mask::<IMM8>(0xff, a)
+    unsafe { vfpclasspd_512(a.as_f64x8(), IMM8) }
 }
 
 /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified
@@ -6991,10 +6985,7 @@ pub fn _mm512_fpclass_pd_mask<const IMM8: i32>(a: __m512d) -> __mmask8 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_mask_fpclass_pd_mask<const IMM8: i32>(k1: __mmask8, a: __m512d) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        transmute(vfpclasspd_512(a.as_f64x8(), IMM8, k1))
-    }
+    _mm512_fpclass_pd_mask::<IMM8>(a) & k1
 }
 
 /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified
@@ -7018,7 +7009,7 @@ pub fn _mm512_mask_fpclass_pd_mask<const IMM8: i32>(k1: __mmask8, a: __m512d) ->
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_fpclass_ps_mask<const IMM8: i32>(a: __m128) -> __mmask8 {
     static_assert_uimm_bits!(IMM8, 8);
-    _mm_mask_fpclass_ps_mask::<IMM8>(0xff, a)
+    unsafe { vfpclassps_128(a.as_f32x4(), IMM8) }
 }
 
 /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified
@@ -7042,10 +7033,7 @@ pub fn _mm_fpclass_ps_mask<const IMM8: i32>(a: __m128) -> __mmask8 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm_mask_fpclass_ps_mask<const IMM8: i32>(k1: __mmask8, a: __m128) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        transmute(vfpclassps_128(a.as_f32x4(), IMM8, k1))
-    }
+    _mm_fpclass_ps_mask::<IMM8>(a) & k1
 }
 
 /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified
@@ -7069,7 +7057,7 @@ pub fn _mm_mask_fpclass_ps_mask<const IMM8: i32>(k1: __mmask8, a: __m128) -> __m
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_fpclass_ps_mask<const IMM8: i32>(a: __m256) -> __mmask8 {
     static_assert_uimm_bits!(IMM8, 8);
-    _mm256_mask_fpclass_ps_mask::<IMM8>(0xff, a)
+    unsafe { vfpclassps_256(a.as_f32x8(), IMM8) }
 }
 
 /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified
@@ -7093,10 +7081,7 @@ pub fn _mm256_fpclass_ps_mask<const IMM8: i32>(a: __m256) -> __mmask8 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm256_mask_fpclass_ps_mask<const IMM8: i32>(k1: __mmask8, a: __m256) -> __mmask8 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        transmute(vfpclassps_256(a.as_f32x8(), IMM8, k1))
-    }
+    _mm256_fpclass_ps_mask::<IMM8>(a) & k1
 }
 
 /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified
@@ -7120,7 +7105,7 @@ pub fn _mm256_mask_fpclass_ps_mask<const IMM8: i32>(k1: __mmask8, a: __m256) ->
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_fpclass_ps_mask<const IMM8: i32>(a: __m512) -> __mmask16 {
     static_assert_uimm_bits!(IMM8, 8);
-    _mm512_mask_fpclass_ps_mask::<IMM8>(0xffff, a)
+    unsafe { vfpclassps_512(a.as_f32x16(), IMM8) }
 }
 
 /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified
@@ -7144,10 +7129,7 @@ pub fn _mm512_fpclass_ps_mask<const IMM8: i32>(a: __m512) -> __mmask16 {
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 pub fn _mm512_mask_fpclass_ps_mask<const IMM8: i32>(k1: __mmask16, a: __m512) -> __mmask16 {
-    unsafe {
-        static_assert_uimm_bits!(IMM8, 8);
-        transmute(vfpclassps_512(a.as_f32x16(), IMM8, k1))
-    }
+    _mm512_fpclass_ps_mask::<IMM8>(a) & k1
 }
 
 /// Test the lower double-precision (64-bit) floating-point element in a for special categories specified
@@ -7377,19 +7359,19 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx512.mask.reduce.ss"]
     fn vreducess(a: f32x4, b: f32x4, src: f32x4, k: __mmask8, imm8: i32, sae: i32) -> f32x4;
 
-    #[link_name = "llvm.x86.avx512.mask.fpclass.pd.128"]
-    fn vfpclasspd_128(a: f64x2, imm8: i32, k: __mmask8) -> __mmask8;
-    #[link_name = "llvm.x86.avx512.mask.fpclass.pd.256"]
-    fn vfpclasspd_256(a: f64x4, imm8: i32, k: __mmask8) -> __mmask8;
-    #[link_name = "llvm.x86.avx512.mask.fpclass.pd.512"]
-    fn vfpclasspd_512(a: f64x8, imm8: i32, k: __mmask8) -> __mmask8;
-
-    #[link_name = "llvm.x86.avx512.mask.fpclass.ps.128"]
-    fn vfpclassps_128(a: f32x4, imm8: i32, k: __mmask8) -> __mmask8;
-    #[link_name = "llvm.x86.avx512.mask.fpclass.ps.256"]
-    fn vfpclassps_256(a: f32x8, imm8: i32, k: __mmask8) -> __mmask8;
-    #[link_name = "llvm.x86.avx512.mask.fpclass.ps.512"]
-    fn vfpclassps_512(a: f32x16, imm8: i32, k: __mmask16) -> __mmask16;
+    #[link_name = "llvm.x86.avx512.fpclass.pd.128"]
+    fn vfpclasspd_128(a: f64x2, imm8: i32) -> __mmask8;
+    #[link_name = "llvm.x86.avx512.fpclass.pd.256"]
+    fn vfpclasspd_256(a: f64x4, imm8: i32) -> __mmask8;
+    #[link_name = "llvm.x86.avx512.fpclass.pd.512"]
+    fn vfpclasspd_512(a: f64x8, imm8: i32) -> __mmask8;
+
+    #[link_name = "llvm.x86.avx512.fpclass.ps.128"]
+    fn vfpclassps_128(a: f32x4, imm8: i32) -> __mmask8;
+    #[link_name = "llvm.x86.avx512.fpclass.ps.256"]
+    fn vfpclassps_256(a: f32x8, imm8: i32) -> __mmask8;
+    #[link_name = "llvm.x86.avx512.fpclass.ps.512"]
+    fn vfpclassps_512(a: f32x16, imm8: i32) -> __mmask16;
 
     #[link_name = "llvm.x86.avx512.mask.fpclass.sd"]
     fn vfpclasssd(a: f64x2, imm8: i32, k: __mmask8) -> __mmask8;
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 0c725402a9..2c5002a2d0 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -16242,7 +16242,7 @@ pub fn _mm512_maskz_cvttps_epi32(k: __mmask16, a: __m512) -> __m512i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvttps2dq))]
 pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i {
-    unsafe { transmute(vcvttps2dq256(a.as_f32x8(), src.as_i32x8(), k)) }
+    unsafe { simd_select_bitmask(k, _mm256_cvttps_epi32(a).as_i32x8(), src.as_i32x8()).as_m256i() }
 }
 
 /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -16253,7 +16253,7 @@ pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvttps2dq))]
 pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i {
-    unsafe { transmute(vcvttps2dq256(a.as_f32x8(), i32x8::ZERO, k)) }
+    _mm256_mask_cvttps_epi32(_mm256_setzero_si256(), k, a)
 }
 
 /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -16264,7 +16264,7 @@ pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvttps2dq))]
 pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i {
-    unsafe { transmute(vcvttps2dq128(a.as_f32x4(), src.as_i32x4(), k)) }
+    unsafe { simd_select_bitmask(k, _mm_cvttps_epi32(a).as_i32x4(), src.as_i32x4()).as_m128i() }
 }
 
 /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -16275,7 +16275,7 @@ pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvttps2dq))]
 pub fn _mm_maskz_cvttps_epi32(k: __mmask8, a: __m128) -> __m128i {
-    unsafe { transmute(vcvttps2dq128(a.as_f32x4(), i32x4::ZERO, k)) }
+    _mm_mask_cvttps_epi32(_mm_setzero_si128(), k, a)
 }
 
 /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst.
@@ -16478,7 +16478,7 @@ pub fn _mm512_maskz_cvttpd_epi32(k: __mmask8, a: __m512d) -> __m256i {
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvttpd2dq))]
 pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i {
-    unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), src.as_i32x4(), k)) }
+    unsafe { simd_select_bitmask(k, _mm256_cvttpd_epi32(a).as_i32x4(), src.as_i32x4()).as_m128i() }
 }
 
 /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
@@ -16489,7 +16489,7 @@ pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128
 #[stable(feature = "stdarch_x86_avx512", since = "1.89")]
 #[cfg_attr(test, assert_instr(vcvttpd2dq))]
 pub fn _mm256_maskz_cvttpd_epi32(k: __mmask8, a: __m256d) -> __m128i {
-    unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), i32x4::ZERO, k)) }
+    _mm256_mask_cvttpd_epi32(_mm_setzero_si128(), k, a)
 }
 
 /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
@@ -44430,10 +44430,6 @@ unsafe extern "C" {
 
     #[link_name = "llvm.x86.avx512.mask.cvttps2dq.512"]
     fn vcvttps2dq(a: f32x16, src: i32x16, mask: u16, rounding: i32) -> i32x16;
-    #[link_name = "llvm.x86.avx512.mask.cvttps2dq.256"]
-    fn vcvttps2dq256(a: f32x8, src: i32x8, mask: u8) -> i32x8;
-    #[link_name = "llvm.x86.avx512.mask.cvttps2dq.128"]
-    fn vcvttps2dq128(a: f32x4, src: i32x4, mask: u8) -> i32x4;
 
     #[link_name = "llvm.x86.avx512.mask.cvttps2udq.512"]
     fn vcvttps2udq(a: f32x16, src: u32x16, mask: u16, rounding: i32) -> u32x16;
@@ -44444,8 +44440,6 @@ unsafe extern "C" {
 
     #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.512"]
     fn vcvttpd2dq(a: f64x8, src: i32x8, mask: u8, rounding: i32) -> i32x8;
-    #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.256"]
-    fn vcvttpd2dq256(a: f64x4, src: i32x4, mask: u8) -> i32x4;
     #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.128"]
     fn vcvttpd2dq128(a: f64x2, src: i32x4, mask: u8) -> i32x4;
 
diff --git a/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
index 383e50b7cc..29dd3a095d 100644
--- a/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml
@@ -562,7 +562,7 @@ intrinsics:
     assert_instr: []
     compose:
       - LLVMLink:
-          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          name: llvm.vector.insert.{sve_type}.{neon_type}
           arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
       - Let:
           - op
@@ -657,7 +657,7 @@ intrinsics:
     assert_instr: []
     compose:
       - LLVMLink:
-          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          name: llvm.vector.insert.{sve_type}.{neon_type}
           arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
       - Let:
           - op
@@ -713,7 +713,7 @@ intrinsics:
     assert_instr: []
     compose:
       - LLVMLink:
-          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          name: llvm.vector.insert.{sve_type}.{neon_type}
           arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
       - Let:
           - op
@@ -755,7 +755,7 @@ intrinsics:
     assert_instr: []
     compose:
       - LLVMLink:
-          name: llvm.experimental.vector.insert.{sve_type}.{neon_type}
+          name: llvm.vector.insert.{sve_type}.{neon_type}
           arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"]
       - Let:
           - op
@@ -1210,7 +1210,7 @@ intrinsics:
     types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [rev]
     compose:
-      - LLVMLink: { name: "rev.{sve_type}" }
+      - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" }
 
   - name: svrev_{type}
     attr: [*sve-unstable]
@@ -1220,7 +1220,7 @@ intrinsics:
     types: [b8, b16, b32, b64]
     assert_instr: [rev]
     compose:
-      - LLVMLink: { name: "rev.{sve_type}" }
+      - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" }
 
   - name: svrevb[_{type}]{_mxz}
     attr: [*sve-unstable]

From 10936fdfbb6d3f0a171ecd027b4aa7ede9287124 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 14 Apr 2026 04:38:51 +0530
Subject: [PATCH 260/326] Implement AVX512-VP2INTERSECT intrinsics

---
 crates/core_arch/missing-x86.md               |  16 --
 .../core_arch/src/x86/avx512vp2intersect.rs   | 244 ++++++++++++++++++
 crates/core_arch/src/x86/mod.rs               |   4 +
 3 files changed, 248 insertions(+), 16 deletions(-)
 create mode 100644 crates/core_arch/src/x86/avx512vp2intersect.rs

diff --git a/crates/core_arch/missing-x86.md b/crates/core_arch/missing-x86.md
index 640ec7d0fe..e9f68eb9e6 100644
--- a/crates/core_arch/missing-x86.md
+++ b/crates/core_arch/missing-x86.md
@@ -44,22 +44,6 @@
 </p></details>
 
 
-<details><summary>["AVX512_VP2INTERSECT", "AVX512F"]</summary><p>
-
-  * [ ] [`_mm512_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi32)
-  * [ ] [`_mm512_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi64)
-</p></details>
-
-
-<details><summary>["AVX512_VP2INTERSECT", "AVX512VL"]</summary><p>
-
-  * [ ] [`_mm256_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi32)
-  * [ ] [`_mm256_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi64)
-  * [ ] [`_mm_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi32)
-  * [ ] [`_mm_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi64)
-</p></details>
-
-
 <details><summary>["CET_SS"]</summary><p>
 
   * [ ] [`_clrssbsy`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_clrssbsy)
diff --git a/crates/core_arch/src/x86/avx512vp2intersect.rs b/crates/core_arch/src/x86/avx512vp2intersect.rs
new file mode 100644
index 0000000000..4dd7412e9e
--- /dev/null
+++ b/crates/core_arch/src/x86/avx512vp2intersect.rs
@@ -0,0 +1,244 @@
+//! Vector Pair Intersection to a Pair of Mask Registers (VP2INTERSECT)
+
+use crate::core_arch::{simd::*, x86::*};
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+/// Compute intersection of packed 32-bit integer vectors a and b,
+/// and store indication of match in the corresponding bit of two mask registers
+/// specified by k1 and k2. A match in corresponding elements of a and b is
+/// indicated by a set bit in the corresponding bit of the mask registers.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi32&expand=0)
+#[inline]
+#[target_feature(enable = "avx512vp2intersect,avx512vl")]
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+#[cfg_attr(test, assert_instr(vp2intersectd))]
+pub unsafe fn _mm_2intersect_epi32(a: __m128i, b: __m128i, k1: *mut __mmask8, k2: *mut __mmask8) {
+    (*k1, *k2) = vp2intersectd_128(a.as_i32x4(), b.as_i32x4());
+}
+
+/// Compute intersection of packed 64-bit integer vectors a and b,
+/// and store indication of match in the corresponding bit of two mask registers
+/// specified by k1 and k2. A match in corresponding elements of a and b is
+/// indicated by a set bit in the corresponding bit of the mask registers.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi64&expand=0)
+#[inline]
+#[target_feature(enable = "avx512vp2intersect,avx512vl")]
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+#[cfg_attr(test, assert_instr(vp2intersectq))]
+pub unsafe fn _mm_2intersect_epi64(a: __m128i, b: __m128i, k1: *mut __mmask8, k2: *mut __mmask8) {
+    (*k1, *k2) = vp2intersectq_128(a.as_i64x2(), b.as_i64x2());
+}
+
+/// Compute intersection of packed 32-bit integer vectors a and b,
+/// and store indication of match in the corresponding bit of two mask registers
+/// specified by k1 and k2. A match in corresponding elements of a and b is
+/// indicated by a set bit in the corresponding bit of the mask registers.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi32&expand=0)
+#[inline]
+#[target_feature(enable = "avx512vp2intersect,avx512vl")]
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+#[cfg_attr(test, assert_instr(vp2intersectd))]
+pub unsafe fn _mm256_2intersect_epi32(
+    a: __m256i,
+    b: __m256i,
+    k1: *mut __mmask8,
+    k2: *mut __mmask8,
+) {
+    (*k1, *k2) = vp2intersectd_256(a.as_i32x8(), b.as_i32x8());
+}
+
+/// Compute intersection of packed 64-bit integer vectors a and b,
+/// and store indication of match in the corresponding bit of two mask registers
+/// specified by k1 and k2. A match in corresponding elements of a and b is
+/// indicated by a set bit in the corresponding bit of the mask registers.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi64&expand=0)
+#[inline]
+#[target_feature(enable = "avx512vp2intersect,avx512vl")]
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+#[cfg_attr(test, assert_instr(vp2intersectq))]
+pub unsafe fn _mm256_2intersect_epi64(
+    a: __m256i,
+    b: __m256i,
+    k1: *mut __mmask8,
+    k2: *mut __mmask8,
+) {
+    (*k1, *k2) = vp2intersectq_256(a.as_i64x4(), b.as_i64x4());
+}
+
+/// Compute intersection of packed 32-bit integer vectors a and b,
+/// and store indication of match in the corresponding bit of two mask registers
+/// specified by k1 and k2. A match in corresponding elements of a and b is
+/// indicated by a set bit in the corresponding bit of the mask registers.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi32&expand=0)
+#[inline]
+#[target_feature(enable = "avx512vp2intersect,avx512f")]
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+#[cfg_attr(test, assert_instr(vp2intersectd))]
+pub unsafe fn _mm512_2intersect_epi32(
+    a: __m512i,
+    b: __m512i,
+    k1: *mut __mmask16,
+    k2: *mut __mmask16,
+) {
+    (*k1, *k2) = vp2intersectd_512(a.as_i32x16(), b.as_i32x16());
+}
+
+/// Compute intersection of packed 64-bit integer vectors a and b,
+/// and store indication of match in the corresponding bit of two mask registers
+/// specified by k1 and k2. A match in corresponding elements of a and b is
+/// indicated by a set bit in the corresponding bit of the mask registers.
+///
+/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi64&expand=0)
+#[inline]
+#[target_feature(enable = "avx512vp2intersect,avx512f")]
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+#[cfg_attr(test, assert_instr(vp2intersectq))]
+pub unsafe fn _mm512_2intersect_epi64(
+    a: __m512i,
+    b: __m512i,
+    k1: *mut __mmask8,
+    k2: *mut __mmask8,
+) {
+    (*k1, *k2) = vp2intersectq_512(a.as_i64x8(), b.as_i64x8());
+}
+
+#[allow(improper_ctypes)]
+unsafe extern "C" {
+    #[link_name = "llvm.x86.avx512.vp2intersect.d.128"]
+    fn vp2intersectd_128(a: i32x4, b: i32x4) -> (u8, u8);
+    #[link_name = "llvm.x86.avx512.vp2intersect.q.128"]
+    fn vp2intersectq_128(a: i64x2, b: i64x2) -> (u8, u8);
+
+    #[link_name = "llvm.x86.avx512.vp2intersect.d.256"]
+    fn vp2intersectd_256(a: i32x8, b: i32x8) -> (u8, u8);
+    #[link_name = "llvm.x86.avx512.vp2intersect.q.256"]
+    fn vp2intersectq_256(a: i64x4, b: i64x4) -> (u8, u8);
+
+    #[link_name = "llvm.x86.avx512.vp2intersect.d.512"]
+    fn vp2intersectd_512(a: i32x16, b: i32x16) -> (u16, u16);
+    #[link_name = "llvm.x86.avx512.vp2intersect.q.512"]
+    fn vp2intersectq_512(a: i64x8, b: i64x8) -> (u8, u8);
+}
+
+#[cfg(test)]
+mod tests {
+    use crate::core_arch::x86::*;
+    use stdarch_test::simd_test;
+
+    #[simd_test(enable = "avx512vp2intersect,avx512vl")]
+    unsafe fn test_mm_2intersect_epi32() {
+        let mut k1 = 0;
+        let mut k2 = 0;
+
+        let a = _mm_set_epi32(1, 2, 3, 4);
+        let b = _mm_set_epi32(3, 4, 5, 6);
+        _mm_2intersect_epi32(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b0011);
+        assert_eq!(k2, 0b1100);
+
+        let a = _mm_set_epi32(1, 2, 3, 4);
+        let b = _mm_set_epi32(2, 3, 4, 5);
+        _mm_2intersect_epi32(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b0111);
+        assert_eq!(k2, 0b1110);
+    }
+
+    #[simd_test(enable = "avx512vp2intersect,avx512vl")]
+    unsafe fn test_mm_2intersect_epi64() {
+        let mut k1 = 0;
+        let mut k2 = 0;
+
+        let a = _mm_set_epi64x(1, 2);
+        let b = _mm_set_epi64x(2, 3);
+        _mm_2intersect_epi64(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b01);
+        assert_eq!(k2, 0b10);
+
+        let a = _mm_set_epi64x(1, 2);
+        let b = _mm_set_epi64x(2, 2);
+        _mm_2intersect_epi64(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b01);
+        assert_eq!(k2, 0b11);
+    }
+
+    #[simd_test(enable = "avx512vp2intersect,avx512vl")]
+    unsafe fn test_mm256_2intersect_epi32() {
+        let mut k1 = 0;
+        let mut k2 = 0;
+
+        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+        let b = _mm256_set_epi32(5, 6, 7, 8, 9, 10, 11, 12);
+        _mm256_2intersect_epi32(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b00001111);
+        assert_eq!(k2, 0b11110000);
+
+        let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+        let b = _mm256_set_epi32(2, 3, 4, 5, 6, 7, 8, 9);
+        _mm256_2intersect_epi32(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b01111111);
+        assert_eq!(k2, 0b11111110);
+    }
+
+    #[simd_test(enable = "avx512vp2intersect,avx512vl")]
+    unsafe fn test_mm256_2intersect_epi64() {
+        let mut k1 = 0;
+        let mut k2 = 0;
+
+        let a = _mm256_set_epi64x(1, 2, 3, 4);
+        let b = _mm256_set_epi64x(3, 4, 5, 6);
+        _mm256_2intersect_epi64(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b0011);
+        assert_eq!(k2, 0b1100);
+
+        let a = _mm256_set_epi64x(1, 2, 3, 4);
+        let b = _mm256_set_epi64x(2, 3, 4, 5);
+        _mm256_2intersect_epi64(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b0111);
+        assert_eq!(k2, 0b1110);
+    }
+
+    #[simd_test(enable = "avx512vp2intersect,avx512f")]
+    unsafe fn test_mm512_2intersect_epi32() {
+        let mut k1 = 0;
+        let mut k2 = 0;
+
+        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+        let b = _mm512_set_epi32(
+            9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+        );
+        _mm512_2intersect_epi32(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b0000000011111111);
+        assert_eq!(k2, 0b1111111100000000);
+
+        let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+        let b = _mm512_set_epi32(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17);
+        _mm512_2intersect_epi32(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b0111111111111111);
+        assert_eq!(k2, 0b1111111111111110);
+    }
+
+    #[simd_test(enable = "avx512vp2intersect,avx512f")]
+    unsafe fn test_mm512_2intersect_epi64() {
+        let mut k1 = 0;
+        let mut k2 = 0;
+
+        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+        let b = _mm512_set_epi64(5, 6, 7, 8, 9, 10, 11, 12);
+        _mm512_2intersect_epi64(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b00001111);
+        assert_eq!(k2, 0b11110000);
+
+        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+        let b = _mm512_set_epi64(2, 3, 4, 5, 6, 7, 8, 9);
+        _mm512_2intersect_epi64(a, b, &mut k1, &mut k2);
+        assert_eq!(k1, 0b01111111);
+        assert_eq!(k2, 0b11111110);
+    }
+}
diff --git a/crates/core_arch/src/x86/mod.rs b/crates/core_arch/src/x86/mod.rs
index 68a963f65b..f5a8acbd8f 100644
--- a/crates/core_arch/src/x86/mod.rs
+++ b/crates/core_arch/src/x86/mod.rs
@@ -778,3 +778,7 @@ pub use self::kl::*;
 mod movrs;
 #[unstable(feature = "movrs_target_feature", issue = "137976")]
 pub use self::movrs::*;
+
+mod avx512vp2intersect;
+#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")]
+pub use self::avx512vp2intersect::*;

From 0d61ee304df41d9d0c82ba2dcaf0edfd39253238 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sun, 19 Apr 2026 22:53:43 +0530
Subject: [PATCH 261/326] Add AMX-AVX512 BF16 intrinsics

---
 crates/core_arch/src/x86_64/amx.rs | 178 +++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index 03bbe3e449..62e46097e6 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -480,6 +480,72 @@ pub unsafe fn _tile_cvtrowps2phli<const TILE: i32, const ROW: i32>() -> __m512h
     tcvtrowps2phli(TILE as i8, ROW as u32).as_m512h()
 }
 
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2bf16h, TILE = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2bf16h<const TILE: i32>(row: u32) -> __m512bh {
+    static_assert_uimm_bits!(TILE, 3);
+    tcvtrowps2bf16h(TILE as i8, row).as_m512bh()
+}
+
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0, 1)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2bf16h, TILE = 0, ROW = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2bf16hi<const TILE: i32, const ROW: i32>() -> __m512bh {
+    static_assert_uimm_bits!(TILE, 3);
+    static_assert_uimm_bits!(ROW, 6);
+    tcvtrowps2bf16hi(TILE as i8, ROW as u32).as_m512bh()
+}
+
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2bf16l, TILE = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2bf16l<const TILE: i32>(row: u32) -> __m512bh {
+    static_assert_uimm_bits!(TILE, 3);
+    tcvtrowps2bf16l(TILE as i8, row).as_m512bh()
+}
+
+/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit)
+/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting
+/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector.
+#[inline]
+#[rustc_legacy_const_generics(0, 1)]
+#[target_feature(enable = "amx-avx512,avx10.2")]
+#[cfg_attr(
+    all(test, any(target_os = "linux", target_env = "msvc")),
+    assert_instr(tcvtrowps2bf16l, TILE = 0, ROW = 0)
+)]
+#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
+pub unsafe fn _tile_cvtrowps2bf16li<const TILE: i32, const ROW: i32>() -> __m512bh {
+    static_assert_uimm_bits!(TILE, 3);
+    static_assert_uimm_bits!(ROW, 6);
+    tcvtrowps2bf16li(TILE as i8, ROW as u32).as_m512bh()
+}
+
 /// Moves one row of tile data into a zmm vector register
 #[inline]
 #[rustc_legacy_const_generics(0)]
@@ -567,6 +633,14 @@ unsafe extern "C" {
     fn tcvtrowps2phl(tile: i8, row: u32) -> f16x32;
     #[link_name = "llvm.x86.tcvtrowps2phli"]
     fn tcvtrowps2phli(tile: i8, row: u32) -> f16x32;
+    #[link_name = "llvm.x86.tcvtrowps2bf16h"]
+    fn tcvtrowps2bf16h(tile: i8, row: u32) -> u16x32;
+    #[link_name = "llvm.x86.tcvtrowps2bf16hi"]
+    fn tcvtrowps2bf16hi(tile: i8, row: u32) -> u16x32;
+    #[link_name = "llvm.x86.tcvtrowps2bf16l"]
+    fn tcvtrowps2bf16l(tile: i8, row: u32) -> u16x32;
+    #[link_name = "llvm.x86.tcvtrowps2bf16li"]
+    fn tcvtrowps2bf16li(tile: i8, row: u32) -> u16x32;
     #[link_name = "llvm.x86.tilemovrow"]
     fn tilemovrow(tile: i8, row: u32) -> i32x16;
     #[link_name = "llvm.x86.tilemovrowi"]
@@ -1276,6 +1350,110 @@ mod tests {
         }
     }
 
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2bf16h() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowps2bf16h::<0>(i);
+                assert_eq!(
+                    *row.as_u16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 {
+                        0
+                    } else {
+                        _mm_cvtness_sbh(i as _).to_bits()
+                    })
+                );
+            }
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2bf16hi() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = wrap_imm4!(_tile_cvtrowps2bf16hi::<0>, i);
+                assert_eq!(
+                    *row.as_u16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 {
+                        0
+                    } else {
+                        _mm_cvtness_sbh(i as _).to_bits()
+                    })
+                );
+            }
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2bf16l() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowps2bf16l::<0>(i);
+                assert_eq!(
+                    *row.as_u16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 {
+                        _mm_cvtness_sbh(i as _).to_bits()
+                    } else {
+                        0
+                    })
+                );
+            }
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2bf16li() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = wrap_imm4!(_tile_cvtrowps2bf16li::<0>, i);
+                assert_eq!(
+                    *row.as_u16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 {
+                        _mm_cvtness_sbh(i as _).to_bits()
+                    } else {
+                        0
+                    })
+                );
+            }
+        }
+    }
+
     #[simd_test(enable = "amx-tf32")]
     fn test_tile_mmultf32ps() {
         unsafe {

From 7ebb9e9b257a55ad43963130c1d41f66319454e0 Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 20 Apr 2026 05:09:37 +0000
Subject: [PATCH 262/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to e22c616e4e87914135c1db261a03e0437255335e.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index a8efb5c477..e9fc6c4cd0 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-e4fdb554ad2c0270473181438e338c42b5b30b0c
+e22c616e4e87914135c1db261a03e0437255335e

From 7eca5b6dd97d7a71b50d5ee8ee3a7ff374d9a69a Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Tue, 21 Apr 2026 16:49:09 +0530
Subject: [PATCH 263/326] enable AMX instruction tests in windows-gnu

---
 crates/core_arch/src/x86_64/amx.rs | 38 +++++++++++++++---------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/crates/core_arch/src/x86_64/amx.rs b/crates/core_arch/src/x86_64/amx.rs
index 62e46097e6..b3b3e86750 100644
--- a/crates/core_arch/src/x86_64/amx.rs
+++ b/crates/core_arch/src/x86_64/amx.rs
@@ -252,7 +252,7 @@ pub unsafe fn _tile_cmmrlfp16ps<const DST: i32, const A: i32, const B: i32>() {
 #[rustc_legacy_const_generics(0, 1, 2)]
 #[target_feature(enable = "amx-fp8")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tdpbf8ps, DST = 0, A = 1, B = 2)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -271,7 +271,7 @@ pub unsafe fn _tile_dpbf8ps<const DST: i32, const A: i32, const B: i32>() {
 #[rustc_legacy_const_generics(0, 1, 2)]
 #[target_feature(enable = "amx-fp8")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tdpbhf8ps, DST = 0, A = 1, B = 2)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -290,7 +290,7 @@ pub unsafe fn _tile_dpbhf8ps<const DST: i32, const A: i32, const B: i32>() {
 #[rustc_legacy_const_generics(0, 1, 2)]
 #[target_feature(enable = "amx-fp8")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tdphbf8ps, DST = 0, A = 1, B = 2)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -309,7 +309,7 @@ pub unsafe fn _tile_dphbf8ps<const DST: i32, const A: i32, const B: i32>() {
 #[rustc_legacy_const_generics(0, 1, 2)]
 #[target_feature(enable = "amx-fp8")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tdphf8ps, DST = 0, A = 1, B = 2)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -329,7 +329,7 @@ pub unsafe fn _tile_dphf8ps<const DST: i32, const A: i32, const B: i32>() {
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-movrs")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tileloaddrs, DST = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -349,7 +349,7 @@ pub unsafe fn _tile_loaddrs<const DST: i32>(base: *const u8, stride: usize) {
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-movrs")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tileloaddrst1, DST = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -372,7 +372,7 @@ pub unsafe fn _tile_stream_loaddrs<const DST: i32>(base: *const u8, stride: usiz
 #[rustc_legacy_const_generics(0, 1, 2)]
 #[target_feature(enable = "amx-tf32")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tmmultf32ps, DST = 0, A = 1, B = 2)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -389,7 +389,7 @@ pub unsafe fn _tile_mmultf32ps<const DST: i32, const A: i32, const B: i32>() {
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowd2ps, TILE = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -404,7 +404,7 @@ pub unsafe fn _tile_cvtrowd2ps<const TILE: i32>(row: u32) -> __m512 {
 #[rustc_legacy_const_generics(0, 1)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowd2ps, TILE = 0, ROW = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -421,7 +421,7 @@ pub unsafe fn _tile_cvtrowd2psi<const TILE: i32, const ROW: i32>() -> __m512 {
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2phh, TILE = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -437,7 +437,7 @@ pub unsafe fn _tile_cvtrowps2phh<const TILE: i32>(row: u32) -> __m512h {
 #[rustc_legacy_const_generics(0, 1)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2phh, TILE = 0, ROW = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -454,7 +454,7 @@ pub unsafe fn _tile_cvtrowps2phhi<const TILE: i32, const ROW: i32>() -> __m512h
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2phl, TILE = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -470,7 +470,7 @@ pub unsafe fn _tile_cvtrowps2phl<const TILE: i32>(row: u32) -> __m512h {
 #[rustc_legacy_const_generics(0, 1)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2phl, TILE = 0, ROW = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -487,7 +487,7 @@ pub unsafe fn _tile_cvtrowps2phli<const TILE: i32, const ROW: i32>() -> __m512h
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2bf16h, TILE = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -503,7 +503,7 @@ pub unsafe fn _tile_cvtrowps2bf16h<const TILE: i32>(row: u32) -> __m512bh {
 #[rustc_legacy_const_generics(0, 1)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2bf16h, TILE = 0, ROW = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -520,7 +520,7 @@ pub unsafe fn _tile_cvtrowps2bf16hi<const TILE: i32, const ROW: i32>() -> __m512
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2bf16l, TILE = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -536,7 +536,7 @@ pub unsafe fn _tile_cvtrowps2bf16l<const TILE: i32>(row: u32) -> __m512bh {
 #[rustc_legacy_const_generics(0, 1)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tcvtrowps2bf16l, TILE = 0, ROW = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -551,7 +551,7 @@ pub unsafe fn _tile_cvtrowps2bf16li<const TILE: i32, const ROW: i32>() -> __m512
 #[rustc_legacy_const_generics(0)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tilemovrow, TILE = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
@@ -565,7 +565,7 @@ pub unsafe fn _tile_movrow<const TILE: i32>(row: u32) -> __m512i {
 #[rustc_legacy_const_generics(0, 1)]
 #[target_feature(enable = "amx-avx512,avx10.2")]
 #[cfg_attr(
-    all(test, any(target_os = "linux", target_env = "msvc")),
+    all(test, not(target_vendor = "apple")),
     assert_instr(tilemovrow, TILE = 0, ROW = 0)
 )]
 #[unstable(feature = "x86_amx_intrinsics", issue = "126622")]

From b0dcc0033ffc49e3b82bf9e2b7a07fe66c7f2824 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Thu, 9 Apr 2026 19:45:07 +0800
Subject: [PATCH 264/326] loongarch: Use `intrinsics::simd` for selected
 LSX/LASX intrinsics

This change migrates a subset of LSX/LASX intrinsics to the portable
`intrinsics::simd` interface.

Only straightforward mappings are converted in this patch. Intrinsics
that require more complex transformations or currently result in
suboptimal code generation are intentionally left unchanged and will be
migrated incrementally in follow-up patches.
---
 .../src/loongarch64/lasx/generated.rs         | 2204 ++-------------
 crates/core_arch/src/loongarch64/lasx/mod.rs  |    7 +
 .../src/loongarch64/lasx/portable.rs          |  201 ++
 .../src/loongarch64/lsx/generated.rs          | 2396 ++---------------
 crates/core_arch/src/loongarch64/lsx/mod.rs   |    7 +
 .../core_arch/src/loongarch64/lsx/portable.rs |  207 ++
 crates/core_arch/src/loongarch64/mod.rs       |    1 +
 crates/core_arch/src/loongarch64/simd.rs      |  302 +++
 crates/stdarch-gen-loongarch/lasx.spec        |  186 ++
 crates/stdarch-gen-loongarch/lsx.spec         |  192 ++
 .../src/portable-intrinsics.txt               |  379 +++
 11 files changed, 1951 insertions(+), 4131 deletions(-)
 create mode 100644 crates/core_arch/src/loongarch64/lasx/portable.rs
 create mode 100644 crates/core_arch/src/loongarch64/lsx/portable.rs
 create mode 100644 crates/core_arch/src/loongarch64/simd.rs

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index 5559c6ad4d..de629914ab 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -11,38 +11,6 @@ use super::super::*;
 
 #[allow(improper_ctypes)]
 unsafe extern "unadjusted" {
-    #[link_name = "llvm.loongarch.lasx.xvsll.b"]
-    fn __lasx_xvsll_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsll.h"]
-    fn __lasx_xvsll_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsll.w"]
-    fn __lasx_xvsll_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsll.d"]
-    fn __lasx_xvsll_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslli.b"]
-    fn __lasx_xvslli_b(a: __v32i8, b: u32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslli.h"]
-    fn __lasx_xvslli_h(a: __v16i16, b: u32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslli.w"]
-    fn __lasx_xvslli_w(a: __v8i32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslli.d"]
-    fn __lasx_xvslli_d(a: __v4i64, b: u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsra.b"]
-    fn __lasx_xvsra_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsra.h"]
-    fn __lasx_xvsra_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsra.w"]
-    fn __lasx_xvsra_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsra.d"]
-    fn __lasx_xvsra_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsrai.b"]
-    fn __lasx_xvsrai_b(a: __v32i8, b: u32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsrai.h"]
-    fn __lasx_xvsrai_h(a: __v16i16, b: u32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsrai.w"]
-    fn __lasx_xvsrai_w(a: __v8i32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsrai.d"]
-    fn __lasx_xvsrai_d(a: __v4i64, b: u32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvsrar.b"]
     fn __lasx_xvsrar_b(a: __v32i8, b: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvsrar.h"]
@@ -59,22 +27,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvsrari_w(a: __v8i32, b: u32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvsrari.d"]
     fn __lasx_xvsrari_d(a: __v4i64, b: u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsrl.b"]
-    fn __lasx_xvsrl_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsrl.h"]
-    fn __lasx_xvsrl_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsrl.w"]
-    fn __lasx_xvsrl_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsrl.d"]
-    fn __lasx_xvsrl_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsrli.b"]
-    fn __lasx_xvsrli_b(a: __v32i8, b: u32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsrli.h"]
-    fn __lasx_xvsrli_h(a: __v16i16, b: u32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsrli.w"]
-    fn __lasx_xvsrli_w(a: __v8i32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsrli.d"]
-    fn __lasx_xvsrli_d(a: __v4i64, b: u32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvsrlr.b"]
     fn __lasx_xvsrlr_b(a: __v32i8, b: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvsrlr.h"]
@@ -139,30 +91,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvbitrevi_w(a: __v8u32, b: u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvbitrevi.d"]
     fn __lasx_xvbitrevi_d(a: __v4u64, b: u32) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvadd.b"]
-    fn __lasx_xvadd_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvadd.h"]
-    fn __lasx_xvadd_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvadd.w"]
-    fn __lasx_xvadd_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvadd.d"]
-    fn __lasx_xvadd_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvaddi.bu"]
-    fn __lasx_xvaddi_bu(a: __v32i8, b: u32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvaddi.hu"]
-    fn __lasx_xvaddi_hu(a: __v16i16, b: u32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvaddi.wu"]
-    fn __lasx_xvaddi_wu(a: __v8i32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvaddi.du"]
-    fn __lasx_xvaddi_du(a: __v4i64, b: u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsub.b"]
-    fn __lasx_xvsub_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsub.h"]
-    fn __lasx_xvsub_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsub.w"]
-    fn __lasx_xvsub_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsub.d"]
-    fn __lasx_xvsub_d(a: __v4i64, b: __v4i64) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvsubi.bu"]
     fn __lasx_xvsubi_bu(a: __v32i8, b: u32) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvsubi.hu"]
@@ -171,150 +99,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvsubi_wu(a: __v8i32, b: u32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvsubi.du"]
     fn __lasx_xvsubi_du(a: __v4i64, b: u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmax.b"]
-    fn __lasx_xvmax_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmax.h"]
-    fn __lasx_xvmax_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmax.w"]
-    fn __lasx_xvmax_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmax.d"]
-    fn __lasx_xvmax_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.b"]
-    fn __lasx_xvmaxi_b(a: __v32i8, b: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.h"]
-    fn __lasx_xvmaxi_h(a: __v16i16, b: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.w"]
-    fn __lasx_xvmaxi_w(a: __v8i32, b: i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.d"]
-    fn __lasx_xvmaxi_d(a: __v4i64, b: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmax.bu"]
-    fn __lasx_xvmax_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvmax.hu"]
-    fn __lasx_xvmax_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvmax.wu"]
-    fn __lasx_xvmax_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvmax.du"]
-    fn __lasx_xvmax_du(a: __v4u64, b: __v4u64) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.bu"]
-    fn __lasx_xvmaxi_bu(a: __v32u8, b: u32) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.hu"]
-    fn __lasx_xvmaxi_hu(a: __v16u16, b: u32) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.wu"]
-    fn __lasx_xvmaxi_wu(a: __v8u32, b: u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvmaxi.du"]
-    fn __lasx_xvmaxi_du(a: __v4u64, b: u32) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvmin.b"]
-    fn __lasx_xvmin_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmin.h"]
-    fn __lasx_xvmin_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmin.w"]
-    fn __lasx_xvmin_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmin.d"]
-    fn __lasx_xvmin_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmini.b"]
-    fn __lasx_xvmini_b(a: __v32i8, b: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmini.h"]
-    fn __lasx_xvmini_h(a: __v16i16, b: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmini.w"]
-    fn __lasx_xvmini_w(a: __v8i32, b: i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmini.d"]
-    fn __lasx_xvmini_d(a: __v4i64, b: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmin.bu"]
-    fn __lasx_xvmin_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvmin.hu"]
-    fn __lasx_xvmin_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvmin.wu"]
-    fn __lasx_xvmin_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvmin.du"]
-    fn __lasx_xvmin_du(a: __v4u64, b: __v4u64) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvmini.bu"]
-    fn __lasx_xvmini_bu(a: __v32u8, b: u32) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvmini.hu"]
-    fn __lasx_xvmini_hu(a: __v16u16, b: u32) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvmini.wu"]
-    fn __lasx_xvmini_wu(a: __v8u32, b: u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvmini.du"]
-    fn __lasx_xvmini_du(a: __v4u64, b: u32) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvseq.b"]
-    fn __lasx_xvseq_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvseq.h"]
-    fn __lasx_xvseq_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvseq.w"]
-    fn __lasx_xvseq_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvseq.d"]
-    fn __lasx_xvseq_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvseqi.b"]
-    fn __lasx_xvseqi_b(a: __v32i8, b: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvseqi.h"]
-    fn __lasx_xvseqi_h(a: __v16i16, b: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvseqi.w"]
-    fn __lasx_xvseqi_w(a: __v8i32, b: i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvseqi.d"]
-    fn __lasx_xvseqi_d(a: __v4i64, b: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslt.b"]
-    fn __lasx_xvslt_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslt.h"]
-    fn __lasx_xvslt_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslt.w"]
-    fn __lasx_xvslt_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslt.d"]
-    fn __lasx_xvslt_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslti.b"]
-    fn __lasx_xvslti_b(a: __v32i8, b: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslti.h"]
-    fn __lasx_xvslti_h(a: __v16i16, b: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslti.w"]
-    fn __lasx_xvslti_w(a: __v8i32, b: i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslti.d"]
-    fn __lasx_xvslti_d(a: __v4i64, b: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslt.bu"]
-    fn __lasx_xvslt_bu(a: __v32u8, b: __v32u8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslt.hu"]
-    fn __lasx_xvslt_hu(a: __v16u16, b: __v16u16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslt.wu"]
-    fn __lasx_xvslt_wu(a: __v8u32, b: __v8u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslt.du"]
-    fn __lasx_xvslt_du(a: __v4u64, b: __v4u64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslti.bu"]
-    fn __lasx_xvslti_bu(a: __v32u8, b: u32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslti.hu"]
-    fn __lasx_xvslti_hu(a: __v16u16, b: u32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslti.wu"]
-    fn __lasx_xvslti_wu(a: __v8u32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslti.du"]
-    fn __lasx_xvslti_du(a: __v4u64, b: u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsle.b"]
-    fn __lasx_xvsle_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsle.h"]
-    fn __lasx_xvsle_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsle.w"]
-    fn __lasx_xvsle_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsle.d"]
-    fn __lasx_xvsle_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslei.b"]
-    fn __lasx_xvslei_b(a: __v32i8, b: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslei.h"]
-    fn __lasx_xvslei_h(a: __v16i16, b: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslei.w"]
-    fn __lasx_xvslei_w(a: __v8i32, b: i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslei.d"]
-    fn __lasx_xvslei_d(a: __v4i64, b: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsle.bu"]
-    fn __lasx_xvsle_bu(a: __v32u8, b: __v32u8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsle.hu"]
-    fn __lasx_xvsle_hu(a: __v16u16, b: __v16u16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsle.wu"]
-    fn __lasx_xvsle_wu(a: __v8u32, b: __v8u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsle.du"]
-    fn __lasx_xvsle_du(a: __v4u64, b: __v4u64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvslei.bu"]
-    fn __lasx_xvslei_bu(a: __v32u8, b: u32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvslei.hu"]
-    fn __lasx_xvslei_hu(a: __v16u16, b: u32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvslei.wu"]
-    fn __lasx_xvslei_wu(a: __v8u32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvslei.du"]
-    fn __lasx_xvslei_du(a: __v4u64, b: u32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvsat.b"]
     fn __lasx_xvsat_b(a: __v32i8, b: u32) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvsat.h"]
@@ -419,46 +203,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvabsd_wu(a: __v8u32, b: __v8u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvabsd.du"]
     fn __lasx_xvabsd_du(a: __v4u64, b: __v4u64) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvmul.b"]
-    fn __lasx_xvmul_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmul.h"]
-    fn __lasx_xvmul_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmul.w"]
-    fn __lasx_xvmul_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmul.d"]
-    fn __lasx_xvmul_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmadd.b"]
-    fn __lasx_xvmadd_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmadd.h"]
-    fn __lasx_xvmadd_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmadd.w"]
-    fn __lasx_xvmadd_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmadd.d"]
-    fn __lasx_xvmadd_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmsub.b"]
-    fn __lasx_xvmsub_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmsub.h"]
-    fn __lasx_xvmsub_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmsub.w"]
-    fn __lasx_xvmsub_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmsub.d"]
-    fn __lasx_xvmsub_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.b"]
-    fn __lasx_xvdiv_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.h"]
-    fn __lasx_xvdiv_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.w"]
-    fn __lasx_xvdiv_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.d"]
-    fn __lasx_xvdiv_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.bu"]
-    fn __lasx_xvdiv_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.hu"]
-    fn __lasx_xvdiv_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.wu"]
-    fn __lasx_xvdiv_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvdiv.du"]
-    fn __lasx_xvdiv_du(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvhaddw.h.b"]
     fn __lasx_xvhaddw_h_b(a: __v32i8, b: __v32i8) -> __v16i16;
     #[link_name = "llvm.loongarch.lasx.xvhaddw.w.h"]
@@ -483,22 +227,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvhsubw_wu_hu(a: __v16u16, b: __v16u16) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvhsubw.du.wu"]
     fn __lasx_xvhsubw_du_wu(a: __v8u32, b: __v8u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmod.b"]
-    fn __lasx_xvmod_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvmod.h"]
-    fn __lasx_xvmod_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvmod.w"]
-    fn __lasx_xvmod_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvmod.d"]
-    fn __lasx_xvmod_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvmod.bu"]
-    fn __lasx_xvmod_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvmod.hu"]
-    fn __lasx_xvmod_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvmod.wu"]
-    fn __lasx_xvmod_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvmod.du"]
-    fn __lasx_xvmod_du(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvrepl128vei.b"]
     fn __lasx_xvrepl128vei_b(a: __v32i8, b: u32) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvrepl128vei.h"]
@@ -563,20 +291,12 @@ unsafe extern "unadjusted" {
     fn __lasx_xvshuf_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvshuf.d"]
     fn __lasx_xvshuf_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvand.v"]
-    fn __lasx_xvand_v(a: __v32u8, b: __v32u8) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvandi.b"]
     fn __lasx_xvandi_b(a: __v32u8, b: u32) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvor.v"]
-    fn __lasx_xvor_v(a: __v32u8, b: __v32u8) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvori.b"]
     fn __lasx_xvori_b(a: __v32u8, b: u32) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvnor.v"]
-    fn __lasx_xvnor_v(a: __v32u8, b: __v32u8) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvnori.b"]
     fn __lasx_xvnori_b(a: __v32u8, b: u32) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvxor.v"]
-    fn __lasx_xvxor_v(a: __v32u8, b: __v32u8) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvxori.b"]
     fn __lasx_xvxori_b(a: __v32u8, b: u32) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvbitsel.v"]
@@ -589,22 +309,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvshuf4i_h(a: __v16i16, b: u32) -> __v16i16;
     #[link_name = "llvm.loongarch.lasx.xvshuf4i.w"]
     fn __lasx_xvshuf4i_w(a: __v8i32, b: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.b"]
-    fn __lasx_xvreplgr2vr_b(a: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.h"]
-    fn __lasx_xvreplgr2vr_h(a: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.w"]
-    fn __lasx_xvreplgr2vr_w(a: i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.d"]
-    fn __lasx_xvreplgr2vr_d(a: i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvpcnt.b"]
-    fn __lasx_xvpcnt_b(a: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvpcnt.h"]
-    fn __lasx_xvpcnt_h(a: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvpcnt.w"]
-    fn __lasx_xvpcnt_w(a: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvpcnt.d"]
-    fn __lasx_xvpcnt_d(a: __v4i64) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvclo.b"]
     fn __lasx_xvclo_b(a: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvclo.h"]
@@ -613,30 +317,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvclo_w(a: __v8i32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvclo.d"]
     fn __lasx_xvclo_d(a: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvclz.b"]
-    fn __lasx_xvclz_b(a: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvclz.h"]
-    fn __lasx_xvclz_h(a: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvclz.w"]
-    fn __lasx_xvclz_w(a: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvclz.d"]
-    fn __lasx_xvclz_d(a: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvfadd.s"]
-    fn __lasx_xvfadd_s(a: __v8f32, b: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfadd.d"]
-    fn __lasx_xvfadd_d(a: __v4f64, b: __v4f64) -> __v4f64;
-    #[link_name = "llvm.loongarch.lasx.xvfsub.s"]
-    fn __lasx_xvfsub_s(a: __v8f32, b: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfsub.d"]
-    fn __lasx_xvfsub_d(a: __v4f64, b: __v4f64) -> __v4f64;
-    #[link_name = "llvm.loongarch.lasx.xvfmul.s"]
-    fn __lasx_xvfmul_s(a: __v8f32, b: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfmul.d"]
-    fn __lasx_xvfmul_d(a: __v4f64, b: __v4f64) -> __v4f64;
-    #[link_name = "llvm.loongarch.lasx.xvfdiv.s"]
-    fn __lasx_xvfdiv_s(a: __v8f32, b: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfdiv.d"]
-    fn __lasx_xvfdiv_d(a: __v4f64, b: __v4f64) -> __v4f64;
     #[link_name = "llvm.loongarch.lasx.xvfcvt.h.s"]
     fn __lasx_xvfcvt_h_s(a: __v8f32, b: __v8f32) -> __v16i16;
     #[link_name = "llvm.loongarch.lasx.xvfcvt.s.d"]
@@ -661,10 +341,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvfclass_s(a: __v8f32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvfclass.d"]
     fn __lasx_xvfclass_d(a: __v4f64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvfsqrt.s"]
-    fn __lasx_xvfsqrt_s(a: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfsqrt.d"]
-    fn __lasx_xvfsqrt_d(a: __v4f64) -> __v4f64;
     #[link_name = "llvm.loongarch.lasx.xvfrecip.s"]
     fn __lasx_xvfrecip_s(a: __v8f32) -> __v8f32;
     #[link_name = "llvm.loongarch.lasx.xvfrecip.d"]
@@ -731,16 +407,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvreplve_d(a: __v4i64, b: i32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvpermi.w"]
     fn __lasx_xvpermi_w(a: __v8i32, b: __v8i32, c: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvandn.v"]
-    fn __lasx_xvandn_v(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvneg.b"]
-    fn __lasx_xvneg_b(a: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvneg.h"]
-    fn __lasx_xvneg_h(a: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvneg.w"]
-    fn __lasx_xvneg_w(a: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvneg.d"]
-    fn __lasx_xvneg_d(a: __v4i64) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvmuh.b"]
     fn __lasx_xvmuh_b(a: __v32i8, b: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvmuh.h"]
@@ -867,22 +533,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvsigncov_w(a: __v8i32, b: __v8i32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvsigncov.d"]
     fn __lasx_xvsigncov_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvfmadd.s"]
-    fn __lasx_xvfmadd_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfmadd.d"]
-    fn __lasx_xvfmadd_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64;
-    #[link_name = "llvm.loongarch.lasx.xvfmsub.s"]
-    fn __lasx_xvfmsub_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfmsub.d"]
-    fn __lasx_xvfmsub_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64;
-    #[link_name = "llvm.loongarch.lasx.xvfnmadd.s"]
-    fn __lasx_xvfnmadd_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfnmadd.d"]
-    fn __lasx_xvfnmadd_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64;
-    #[link_name = "llvm.loongarch.lasx.xvfnmsub.s"]
-    fn __lasx_xvfnmsub_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvfnmsub.d"]
-    fn __lasx_xvfnmsub_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64;
     #[link_name = "llvm.loongarch.lasx.xvftintrne.w.s"]
     fn __lasx_xvftintrne_w_s(a: __v8f32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvftintrne.l.d"]
@@ -979,8 +629,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvssrln_h_w(a: __v8i32, b: __v8i32) -> __v16i16;
     #[link_name = "llvm.loongarch.lasx.xvssrln.w.d"]
     fn __lasx_xvssrln_w_d(a: __v4i64, b: __v4i64) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvorn.v"]
-    fn __lasx_xvorn_v(a: __v32u8, b: __v32u8) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvldi"]
     fn __lasx_xvldi(a: i32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvldx"]
@@ -989,10 +637,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvstx(a: __v32i8, b: *mut i8, c: i64);
     #[link_name = "llvm.loongarch.lasx.xvextl.qu.du"]
     fn __lasx_xvextl_qu_du(a: __v4u64) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvinsgr2vr.w"]
-    fn __lasx_xvinsgr2vr_w(a: __v8i32, b: i32, c: u32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvinsgr2vr.d"]
-    fn __lasx_xvinsgr2vr_d(a: __v4i64, b: i64, c: u32) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvreplve0.b"]
     fn __lasx_xvreplve0_b(a: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvreplve0.h"]
@@ -1041,14 +685,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvldrepl_w(a: *const i8, b: i32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvldrepl.d"]
     fn __lasx_xvldrepl_d(a: *const i8, b: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvpickve2gr.w"]
-    fn __lasx_xvpickve2gr_w(a: __v8i32, b: u32) -> i32;
-    #[link_name = "llvm.loongarch.lasx.xvpickve2gr.wu"]
-    fn __lasx_xvpickve2gr_wu(a: __v8i32, b: u32) -> u32;
-    #[link_name = "llvm.loongarch.lasx.xvpickve2gr.d"]
-    fn __lasx_xvpickve2gr_d(a: __v4i64, b: u32) -> i64;
-    #[link_name = "llvm.loongarch.lasx.xvpickve2gr.du"]
-    fn __lasx_xvpickve2gr_du(a: __v4i64, b: u32) -> u64;
     #[link_name = "llvm.loongarch.lasx.xvaddwev.q.d"]
     fn __lasx_xvaddwev_q_d(a: __v4i64, b: __v4i64) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvaddwev.d.w"]
@@ -1483,14 +1119,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvpickve_d_f(a: __v4f64, b: u32) -> __v4f64;
     #[link_name = "llvm.loongarch.lasx.xvpickve.w.f"]
     fn __lasx_xvpickve_w_f(a: __v8f32, b: u32) -> __v8f32;
-    #[link_name = "llvm.loongarch.lasx.xvrepli.b"]
-    fn __lasx_xvrepli_b(a: i32) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvrepli.d"]
-    fn __lasx_xvrepli_d(a: i32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvrepli.h"]
-    fn __lasx_xvrepli_h(a: i32) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvrepli.w"]
-    fn __lasx_xvrepli_w(a: i32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.cast.128.s"]
     fn __lasx_cast_128_s(a: __v4f32) -> __v8f32;
     #[link_name = "llvm.loongarch.lasx.cast.128.d"]
@@ -1529,134 +1157,6 @@ unsafe extern "unadjusted" {
     fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64;
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsll_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsll_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsll_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsll_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsll_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsll_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsll_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsll_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslli_b<const IMM3: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvslli_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslli_h<const IMM4: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lasx_xvslli_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslli_w<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslli_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslli_d<const IMM6: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lasx_xvslli_d(transmute(a), IMM6)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsra_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsra_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsra_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsra_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsra_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsra_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsra_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsra_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrai_b<const IMM3: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvsrai_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrai_h<const IMM4: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lasx_xvsrai_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrai_w<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsrai_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrai_d<const IMM6: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lasx_xvsrai_d(transmute(a), IMM6)) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1721,70 +1221,6 @@ pub fn lasx_xvsrari_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrl_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsrl_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrl_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsrl_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrl_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsrl_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrl_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsrl_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrli_b<const IMM3: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvsrli_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrli_h<const IMM4: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lasx_xvsrli_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrli_w<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsrli_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsrli_d<const IMM6: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lasx_xvsrli_d(transmute(a), IMM6)) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2043,911 +1479,243 @@ pub fn lasx_xvbitrevi_d<const IMM6: u32>(a: m256i) -> m256i {
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadd_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadd_b(transmute(a), transmute(b))) }
+pub fn lasx_xvsubi_bu<const IMM5: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadd_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadd_h(transmute(a), transmute(b))) }
+pub fn lasx_xvsubi_hu<const IMM5: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadd_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadd_w(transmute(a), transmute(b))) }
+pub fn lasx_xvsubi_wu<const IMM5: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadd_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadd_d(transmute(a), transmute(b))) }
+pub fn lasx_xvsubi_du<const IMM5: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvaddi_bu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvaddi_bu(transmute(a), IMM5)) }
+pub fn lasx_xvsat_b<const IMM3: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM3, 3);
+    unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvaddi_hu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvaddi_hu(transmute(a), IMM5)) }
+pub fn lasx_xvsat_h<const IMM4: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM4, 4);
+    unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvaddi_wu<const IMM5: u32>(a: m256i) -> m256i {
+pub fn lasx_xvsat_w<const IMM5: u32>(a: m256i) -> m256i {
     static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvaddi_wu(transmute(a), IMM5)) }
+    unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvaddi_du<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvaddi_du(transmute(a), IMM5)) }
+pub fn lasx_xvsat_d<const IMM6: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM6, 6);
+    unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsub_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsub_b(transmute(a), transmute(b))) }
+pub fn lasx_xvsat_bu<const IMM3: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM3, 3);
+    unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsub_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsub_h(transmute(a), transmute(b))) }
+pub fn lasx_xvsat_hu<const IMM4: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM4, 4);
+    unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsub_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsub_w(transmute(a), transmute(b))) }
+pub fn lasx_xvsat_wu<const IMM5: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsub_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsub_d(transmute(a), transmute(b))) }
+pub fn lasx_xvsat_du<const IMM6: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM6, 6);
+    unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsubi_bu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) }
+pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsubi_hu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) }
+pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsubi_wu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) }
+pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsubi_du<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) }
+pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_b(transmute(a), transmute(b))) }
+pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_h(transmute(a), transmute(b))) }
+pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_w(transmute(a), transmute(b))) }
+pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_d(transmute(a), transmute(b))) }
+pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_b<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmaxi_b(transmute(a), IMM_S5)) }
+pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_h<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmaxi_h(transmute(a), IMM_S5)) }
+pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_w<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmaxi_w(transmute(a), IMM_S5)) }
+pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_d<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmaxi_d(transmute(a), IMM_S5)) }
+pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_bu(transmute(a), transmute(b))) }
+pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_hu(transmute(a), transmute(b))) }
+pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_wu(transmute(a), transmute(b))) }
+pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmax_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmax_du(transmute(a), transmute(b))) }
+pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_bu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmaxi_bu(transmute(a), IMM5)) }
+pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_hu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmaxi_hu(transmute(a), IMM5)) }
+pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_wu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmaxi_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmaxi_du<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmaxi_du(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_b<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmini_b(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_h<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmini_h(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_w<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmini_w(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_d<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvmini_d(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmin_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmin_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_bu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmini_bu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_hu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmini_hu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_wu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmini_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmini_du<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvmini_du(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseq_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvseq_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseq_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvseq_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseq_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvseq_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseq_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvseq_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseqi_b<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvseqi_b(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseqi_h<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvseqi_h(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseqi_w<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvseqi_w(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvseqi_d<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvseqi_d(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_b<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslti_b(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_h<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslti_h(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_w<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslti_w(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_d<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslti_d(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslt_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvslt_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_bu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslti_bu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_hu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslti_hu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_wu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslti_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslti_du<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslti_du(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_b<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslei_b(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_h<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslei_h(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_w<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslei_w(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_d<const IMM_S5: i32>(a: m256i) -> m256i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lasx_xvslei_d(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsle_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsle_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_bu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslei_bu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_hu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslei_hu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_wu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslei_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvslei_du<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvslei_du(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_b<const IMM3: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_h<const IMM4: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_w<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_d<const IMM6: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_bu<const IMM3: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_hu<const IMM4: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_wu<const IMM5: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsat_du<const IMM6: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) }
+pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
@@ -2967,302 +1735,162 @@ pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i {
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmul_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmul_b(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmul_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmul_h(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmul_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmul_w(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmul_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmul_d(transmute(a), transmute(b))) }
+pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmadd_b(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmadd_h(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmadd_w(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmadd_d(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmsub_b(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmsub_h(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmsub_w(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmsub_d(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_b(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_h(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_w(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_d(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_bu(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_hu(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_wu(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvdiv_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvdiv_du(transmute(a), transmute(b))) }
+pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
@@ -3349,62 +1977,6 @@ pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvmod_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvmod_du(transmute(a), transmute(b))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
@@ -3521,395 +2093,227 @@ pub fn lasx_xvilvh_w(a: m256i, b: m256i) -> m256i {
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvand_v(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvand_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvandi_b<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvor_v(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvor_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvori_b<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvnor_v(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvnor_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvnori_b<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvxor_v(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvxor_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvxori_b<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) }
+pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) }
+pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitseli_b<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) }
+pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf4i_b<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) }
+pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf4i_h<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) }
+pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvshuf4i_w<const IMM8: u32>(a: m256i) -> m256i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) }
+pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvreplgr2vr_b(a: i32) -> m256i {
-    unsafe { transmute(__lasx_xvreplgr2vr_b(transmute(a))) }
+pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvreplgr2vr_h(a: i32) -> m256i {
-    unsafe { transmute(__lasx_xvreplgr2vr_h(transmute(a))) }
+pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvreplgr2vr_w(a: i32) -> m256i {
-    unsafe { transmute(__lasx_xvreplgr2vr_w(transmute(a))) }
+pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvreplgr2vr_d(a: i64) -> m256i {
-    unsafe { transmute(__lasx_xvreplgr2vr_d(transmute(a))) }
+pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpcnt_b(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpcnt_b(transmute(a))) }
+pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpcnt_h(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpcnt_h(transmute(a))) }
+pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpcnt_w(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpcnt_w(transmute(a))) }
+pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpcnt_d(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvpcnt_d(transmute(a))) }
+pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclo_b(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclo_b(transmute(a))) }
+pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclo_h(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclo_h(transmute(a))) }
+pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclo_w(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclo_w(transmute(a))) }
+pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclo_d(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclo_d(transmute(a))) }
+pub fn lasx_xvandi_b<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclz_b(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclz_b(transmute(a))) }
+pub fn lasx_xvori_b<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclz_h(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclz_h(transmute(a))) }
+pub fn lasx_xvnori_b<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclz_w(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclz_w(transmute(a))) }
+pub fn lasx_xvxori_b<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvclz_d(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvclz_d(transmute(a))) }
+pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfadd_s(a: m256, b: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfadd_s(transmute(a), transmute(b))) }
+pub fn lasx_xvbitseli_b<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfadd_d(a: m256d, b: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfadd_d(transmute(a), transmute(b))) }
+pub fn lasx_xvshuf4i_b<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfsub_s(a: m256, b: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfsub_s(transmute(a), transmute(b))) }
+pub fn lasx_xvshuf4i_h<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfsub_d(a: m256d, b: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfsub_d(transmute(a), transmute(b))) }
+pub fn lasx_xvshuf4i_w<const IMM8: u32>(a: m256i) -> m256i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfmul_s(a: m256, b: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfmul_s(transmute(a), transmute(b))) }
+pub fn lasx_xvclo_b(a: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvclo_b(transmute(a))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfmul_d(a: m256d, b: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfmul_d(transmute(a), transmute(b))) }
+pub fn lasx_xvclo_h(a: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvclo_h(transmute(a))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfdiv_s(a: m256, b: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfdiv_s(transmute(a), transmute(b))) }
+pub fn lasx_xvclo_w(a: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvclo_w(transmute(a))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfdiv_d(a: m256d, b: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfdiv_d(transmute(a), transmute(b))) }
+pub fn lasx_xvclo_d(a: m256i) -> m256i {
+    unsafe { transmute(__lasx_xvclo_d(transmute(a))) }
 }
 
 #[inline(always)]
@@ -3996,20 +2400,6 @@ pub fn lasx_xvfclass_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfclass_d(transmute(a))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfsqrt_s(a: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfsqrt_s(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfsqrt_d(a: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfsqrt_d(transmute(a))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4243,41 +2633,6 @@ pub fn lasx_xvpermi_w<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvandn_v(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvandn_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvneg_b(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvneg_b(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvneg_h(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvneg_h(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvneg_w(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvneg_w(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvneg_d(a: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvneg_d(transmute(a))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4749,62 +3104,6 @@ pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfmadd_s(a: m256, b: m256, c: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfmadd_d(a: m256d, b: m256d, c: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfmsub_s(a: m256, b: m256, c: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfmsub_d(a: m256d, b: m256d, c: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfnmadd_s(a: m256, b: m256, c: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfnmadd_d(a: m256d, b: m256d, c: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfnmsub_s(a: m256, b: m256, c: m256) -> m256 {
-    unsafe { transmute(__lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvfnmsub_d(a: m256d, b: m256d, c: m256d) -> m256d {
-    unsafe { transmute(__lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5165,13 +3464,6 @@ pub fn lasx_xvssrln_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvorn_v(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvorn_v(transmute(a), transmute(b))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
@@ -5202,24 +3494,6 @@ pub fn lasx_xvextl_qu_du(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextl_qu_du(transmute(a))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvinsgr2vr_w<const IMM3: u32>(a: m256i, b: i32) -> m256i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvinsgr2vr_w(transmute(a), transmute(b), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(2)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvinsgr2vr_d<const IMM2: u32>(a: m256i, b: i64) -> m256i {
-    static_assert_uimm_bits!(IMM2, 2);
-    unsafe { transmute(__lasx_xvinsgr2vr_d(transmute(a), transmute(b), IMM2)) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5400,42 +3674,6 @@ pub unsafe fn lasx_xvldrepl_d<const IMM_S9: i32>(mem_addr: *const i8) -> m256i {
     transmute(__lasx_xvldrepl_d(mem_addr, IMM_S9))
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpickve2gr_w<const IMM3: u32>(a: m256i) -> i32 {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvpickve2gr_w(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpickve2gr_wu<const IMM3: u32>(a: m256i) -> u32 {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lasx_xvpickve2gr_wu(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpickve2gr_d<const IMM2: u32>(a: m256i) -> i64 {
-    static_assert_uimm_bits!(IMM2, 2);
-    unsafe { transmute(__lasx_xvpickve2gr_d(transmute(a), IMM2)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvpickve2gr_du<const IMM2: u32>(a: m256i) -> u64 {
-    static_assert_uimm_bits!(IMM2, 2);
-    unsafe { transmute(__lasx_xvpickve2gr_du(transmute(a), IMM2)) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -7063,42 +5301,6 @@ pub fn lasx_xvpickve_w_f<const IMM3: u32>(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvpickve_w_f(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvrepli_b<const IMM_S10: i32>() -> m256i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lasx_xvrepli_b(IMM_S10)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvrepli_d<const IMM_S10: i32>() -> m256i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lasx_xvrepli_d(IMM_S10)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvrepli_h<const IMM_S10: i32>() -> m256i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lasx_xvrepli_h(IMM_S10)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lasx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvrepli_w<const IMM_S10: i32>() -> m256i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lasx/mod.rs b/crates/core_arch/src/loongarch64/lasx/mod.rs
index c3a244e740..cc449e9492 100644
--- a/crates/core_arch/src/loongarch64/lasx/mod.rs
+++ b/crates/core_arch/src/loongarch64/lasx/mod.rs
@@ -16,6 +16,13 @@ mod generated;
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub use self::generated::*;
 
+#[rustfmt::skip]
+mod portable;
+
+#[rustfmt::skip]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub use self::portable::*;
+
 #[rustfmt::skip]
 #[cfg(test)]
 mod tests;
diff --git a/crates/core_arch/src/loongarch64/lasx/portable.rs b/crates/core_arch/src/loongarch64/lasx/portable.rs
new file mode 100644
index 0000000000..0021d7605f
--- /dev/null
+++ b/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -0,0 +1,201 @@
+//! LoongArch64 LASX intrinsics - intrinsics::simd implementation
+
+use super::super::{simd::*, *};
+use crate::core_arch::simd::*;
+use crate::intrinsics::simd::*;
+use crate::mem::transmute;
+
+impl_vv!("lasx", lasx_xvpcnt_b, simd_ctpop, m256i, i8x32);
+impl_vv!("lasx", lasx_xvpcnt_h, simd_ctpop, m256i, i16x16);
+impl_vv!("lasx", lasx_xvpcnt_w, simd_ctpop, m256i, i32x8);
+impl_vv!("lasx", lasx_xvpcnt_d, simd_ctpop, m256i, i64x4);
+impl_vv!("lasx", lasx_xvclz_b, simd_ctlz, m256i, i8x32);
+impl_vv!("lasx", lasx_xvclz_h, simd_ctlz, m256i, i16x16);
+impl_vv!("lasx", lasx_xvclz_w, simd_ctlz, m256i, i32x8);
+impl_vv!("lasx", lasx_xvclz_d, simd_ctlz, m256i, i64x4);
+impl_vv!("lasx", lasx_xvneg_b, simd_neg, m256i, i8x32);
+impl_vv!("lasx", lasx_xvneg_h, simd_neg, m256i, i16x16);
+impl_vv!("lasx", lasx_xvneg_w, simd_neg, m256i, i32x8);
+impl_vv!("lasx", lasx_xvneg_d, simd_neg, m256i, i64x4);
+impl_vv!("lasx", lasx_xvfsqrt_s, simd_fsqrt, m256, f32x8);
+impl_vv!("lasx", lasx_xvfsqrt_d, simd_fsqrt, m256d, f64x4);
+
+impl_gv!("lasx", lasx_xvreplgr2vr_b, simdl_splat, m256i, i8x32, i32);
+impl_gv!("lasx", lasx_xvreplgr2vr_h, simdl_splat, m256i, i16x16, i32);
+impl_gv!("lasx", lasx_xvreplgr2vr_w, simdl_splat, m256i, i32x8, i32);
+impl_gv!("lasx", lasx_xvreplgr2vr_d, simdl_splat, m256i, i64x4, i64);
+
+impl_sv!("lasx", lasx_xvrepli_b, simdl_splat, m256i, i8x32, 10);
+impl_sv!("lasx", lasx_xvrepli_h, simdl_splat, m256i, i16x16, 10);
+impl_sv!("lasx", lasx_xvrepli_w, simdl_splat, m256i, i32x8, 10);
+impl_sv!("lasx", lasx_xvrepli_d, simdl_splat, m256i, i64x4, 10);
+
+impl_vvv!("lasx", lasx_xvadd_b, simd_add, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvadd_h, simd_add, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvadd_w, simd_add, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvadd_d, simd_add, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsub_b, simd_sub, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsub_h, simd_sub, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsub_w, simd_sub, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsub_d, simd_sub, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmax_b, simd_imax, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmax_h, simd_imax, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmax_w, simd_imax, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmax_d, simd_imax, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmax_bu, simd_imax, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvmax_hu, simd_imax, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvmax_wu, simd_imax, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvmax_du, simd_imax, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvmin_b, simd_imin, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmin_h, simd_imin, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmin_w, simd_imin, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmin_d, simd_imin, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmin_bu, simd_imin, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvmin_hu, simd_imin, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvmin_wu, simd_imin, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvmin_du, simd_imin, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvseq_b, simd_eq, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvseq_h, simd_eq, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvseq_w, simd_eq, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvseq_d, simd_eq, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvslt_b, simd_lt, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvslt_h, simd_lt, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvslt_w, simd_lt, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvslt_d, simd_lt, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvslt_bu, simd_lt, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvslt_hu, simd_lt, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvslt_wu, simd_lt, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvslt_du, simd_lt, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvsle_b, simd_le, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsle_h, simd_le, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsle_w, simd_le, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsle_d, simd_le, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsle_bu, simd_le, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvsle_hu, simd_le, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvsle_wu, simd_le, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvsle_du, simd_le, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvmul_b, simd_mul, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmul_h, simd_mul, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmul_w, simd_mul, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmul_d, simd_mul, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvdiv_b, simd_div, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvdiv_h, simd_div, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvdiv_w, simd_div, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvdiv_d, simd_div, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvdiv_bu, simd_div, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvdiv_hu, simd_div, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvdiv_wu, simd_div, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvdiv_du, simd_div, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvmod_b, simd_rem, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmod_h, simd_rem, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmod_w, simd_rem, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmod_d, simd_rem, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmod_bu, simd_rem, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvmod_hu, simd_rem, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvmod_wu, simd_rem, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvmod_du, simd_rem, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvand_v, simd_and, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvandn_v, simdl_andn, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvor_v, simd_or, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvorn_v, simdl_orn, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvnor_v, simdl_nor, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvxor_v, simd_xor, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvfadd_s, simd_add, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfadd_d, simd_add, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvfsub_s, simd_sub, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfsub_d, simd_sub, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvfmul_s, simd_mul, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfmul_d, simd_mul, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvfdiv_s, simd_div, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfdiv_d, simd_div, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvsll_b, simdl_shl, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsll_h, simdl_shl, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsll_w, simdl_shl, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsll_d, simdl_shl, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsra_b, simdl_shr, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsra_h, simdl_shr, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsra_w, simdl_shr, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsra_d, simdl_shr, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsrl_b, simdl_shr, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvsrl_h, simdl_shr, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvsrl_w, simdl_shr, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvsrl_d, simdl_shr, m256i, u64x4);
+
+impl_vuv!("lasx", lasx_xvslli_b, simd_shl, m256i, i8x32);
+impl_vuv!("lasx", lasx_xvslli_h, simd_shl, m256i, i16x16);
+impl_vuv!("lasx", lasx_xvslli_w, simd_shl, m256i, i32x8);
+impl_vuv!("lasx", lasx_xvslli_d, simd_shl, m256i, i64x4);
+impl_vuv!("lasx", lasx_xvsrai_b, simd_shr, m256i, i8x32);
+impl_vuv!("lasx", lasx_xvsrai_h, simd_shr, m256i, i16x16);
+impl_vuv!("lasx", lasx_xvsrai_w, simd_shr, m256i, i32x8);
+impl_vuv!("lasx", lasx_xvsrai_d, simd_shr, m256i, i64x4);
+impl_vuv!("lasx", lasx_xvsrli_b, simd_shr, m256i, u8x32);
+impl_vuv!("lasx", lasx_xvsrli_h, simd_shr, m256i, u16x16);
+impl_vuv!("lasx", lasx_xvsrli_w, simd_shr, m256i, u32x8);
+impl_vuv!("lasx", lasx_xvsrli_d, simd_shr, m256i, u64x4);
+impl_vuv!("lasx", lasx_xvaddi_bu, simd_add, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvaddi_hu, simd_add, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvaddi_wu, simd_add, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvaddi_du, simd_add, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvslti_bu, simd_lt, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvslti_hu, simd_lt, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvslti_wu, simd_lt, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvslti_du, simd_lt, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvslei_bu, simd_le, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvslei_hu, simd_le, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvslei_wu, simd_le, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvslei_du, simd_le, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvmaxi_bu, simd_imax, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvmaxi_hu, simd_imax, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvmaxi_wu, simd_imax, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvmaxi_du, simd_imax, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvmini_bu, simd_imin, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvmini_hu, simd_imin, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvmini_wu, simd_imin, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvmini_du, simd_imin, m256i, u64x4, 5);
+
+impl_vug!("lasx", lasx_xvpickve2gr_w, simd_extract, m256i, i32x8, i32, 3);
+impl_vug!("lasx", lasx_xvpickve2gr_d, simd_extract, m256i, i64x4, i64, 2);
+impl_vug!("lasx", lasx_xvpickve2gr_wu, simd_extract, m256i, u32x8, u32, 3);
+impl_vug!("lasx", lasx_xvpickve2gr_du, simd_extract, m256i, u64x4, u64, 2);
+
+impl_vsv!("lasx", lasx_xvseqi_b, simd_eq, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvseqi_h, simd_eq, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvseqi_w, simd_eq, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvseqi_d, simd_eq, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvslti_b, simd_lt, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvslti_h, simd_lt, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvslti_w, simd_lt, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvslti_d, simd_lt, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvslei_b, simd_le, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvslei_h, simd_le, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvslei_w, simd_le, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvslei_d, simd_le, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvmaxi_b, simd_imax, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvmaxi_h, simd_imax, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvmaxi_w, simd_imax, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvmaxi_d, simd_imax, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvmini_b, simd_imin, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvmini_h, simd_imin, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvmini_w, simd_imin, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvmini_d, simd_imin, m256i, i64x4, 5);
+
+impl_vvvv!("lasx", lasx_xvmadd_b, simdl_madd, m256i, i8x32);
+impl_vvvv!("lasx", lasx_xvmadd_h, simdl_madd, m256i, i16x16);
+impl_vvvv!("lasx", lasx_xvmadd_w, simdl_madd, m256i, i32x8);
+impl_vvvv!("lasx", lasx_xvmadd_d, simdl_madd, m256i, i64x4);
+impl_vvvv!("lasx", lasx_xvmsub_b, simdl_msub, m256i, i8x32);
+impl_vvvv!("lasx", lasx_xvmsub_h, simdl_msub, m256i, i16x16);
+impl_vvvv!("lasx", lasx_xvmsub_w, simdl_msub, m256i, i32x8);
+impl_vvvv!("lasx", lasx_xvmsub_d, simdl_msub, m256i, i64x4);
+impl_vvvv!("lasx", lasx_xvfmadd_s, simd_fma, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfmadd_d, simd_fma, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvfmsub_s, simdl_fms, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfmsub_d, simdl_fms, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvfnmadd_s, simdl_nfma, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfnmadd_d, simdl_nfma, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvfnmsub_s, simdl_nfms, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfnmsub_d, simdl_nfms, m256d, f64x4);
+
+impl_vugv!("lasx", lasx_xvinsgr2vr_w, simd_insert, m256i, i32x8, i32, 3);
+impl_vugv!("lasx", lasx_xvinsgr2vr_d, simd_insert, m256i, i64x4, i64, 2);
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index faa8859eba..d2d77e2f3e 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -11,38 +11,6 @@ use super::super::*;
 
 #[allow(improper_ctypes)]
 unsafe extern "unadjusted" {
-    #[link_name = "llvm.loongarch.lsx.vsll.b"]
-    fn __lsx_vsll_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsll.h"]
-    fn __lsx_vsll_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsll.w"]
-    fn __lsx_vsll_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsll.d"]
-    fn __lsx_vsll_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslli.b"]
-    fn __lsx_vslli_b(a: __v16i8, b: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslli.h"]
-    fn __lsx_vslli_h(a: __v8i16, b: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslli.w"]
-    fn __lsx_vslli_w(a: __v4i32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslli.d"]
-    fn __lsx_vslli_d(a: __v2i64, b: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsra.b"]
-    fn __lsx_vsra_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsra.h"]
-    fn __lsx_vsra_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsra.w"]
-    fn __lsx_vsra_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsra.d"]
-    fn __lsx_vsra_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsrai.b"]
-    fn __lsx_vsrai_b(a: __v16i8, b: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsrai.h"]
-    fn __lsx_vsrai_h(a: __v8i16, b: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsrai.w"]
-    fn __lsx_vsrai_w(a: __v4i32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsrai.d"]
-    fn __lsx_vsrai_d(a: __v2i64, b: u32) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vsrar.b"]
     fn __lsx_vsrar_b(a: __v16i8, b: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vsrar.h"]
@@ -59,22 +27,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vsrari_w(a: __v4i32, b: u32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vsrari.d"]
     fn __lsx_vsrari_d(a: __v2i64, b: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsrl.b"]
-    fn __lsx_vsrl_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsrl.h"]
-    fn __lsx_vsrl_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsrl.w"]
-    fn __lsx_vsrl_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsrl.d"]
-    fn __lsx_vsrl_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsrli.b"]
-    fn __lsx_vsrli_b(a: __v16i8, b: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsrli.h"]
-    fn __lsx_vsrli_h(a: __v8i16, b: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsrli.w"]
-    fn __lsx_vsrli_w(a: __v4i32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsrli.d"]
-    fn __lsx_vsrli_d(a: __v2i64, b: u32) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vsrlr.b"]
     fn __lsx_vsrlr_b(a: __v16i8, b: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vsrlr.h"]
@@ -139,30 +91,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vbitrevi_w(a: __v4u32, b: u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vbitrevi.d"]
     fn __lsx_vbitrevi_d(a: __v2u64, b: u32) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vadd.b"]
-    fn __lsx_vadd_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vadd.h"]
-    fn __lsx_vadd_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vadd.w"]
-    fn __lsx_vadd_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vadd.d"]
-    fn __lsx_vadd_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vaddi.bu"]
-    fn __lsx_vaddi_bu(a: __v16i8, b: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vaddi.hu"]
-    fn __lsx_vaddi_hu(a: __v8i16, b: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vaddi.wu"]
-    fn __lsx_vaddi_wu(a: __v4i32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vaddi.du"]
-    fn __lsx_vaddi_du(a: __v2i64, b: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsub.b"]
-    fn __lsx_vsub_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsub.h"]
-    fn __lsx_vsub_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsub.w"]
-    fn __lsx_vsub_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsub.d"]
-    fn __lsx_vsub_d(a: __v2i64, b: __v2i64) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vsubi.bu"]
     fn __lsx_vsubi_bu(a: __v16i8, b: u32) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vsubi.hu"]
@@ -171,150 +99,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vsubi_wu(a: __v4i32, b: u32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vsubi.du"]
     fn __lsx_vsubi_du(a: __v2i64, b: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmax.b"]
-    fn __lsx_vmax_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmax.h"]
-    fn __lsx_vmax_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmax.w"]
-    fn __lsx_vmax_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmax.d"]
-    fn __lsx_vmax_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.b"]
-    fn __lsx_vmaxi_b(a: __v16i8, b: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.h"]
-    fn __lsx_vmaxi_h(a: __v8i16, b: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.w"]
-    fn __lsx_vmaxi_w(a: __v4i32, b: i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.d"]
-    fn __lsx_vmaxi_d(a: __v2i64, b: i32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmax.bu"]
-    fn __lsx_vmax_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vmax.hu"]
-    fn __lsx_vmax_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vmax.wu"]
-    fn __lsx_vmax_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vmax.du"]
-    fn __lsx_vmax_du(a: __v2u64, b: __v2u64) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.bu"]
-    fn __lsx_vmaxi_bu(a: __v16u8, b: u32) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.hu"]
-    fn __lsx_vmaxi_hu(a: __v8u16, b: u32) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.wu"]
-    fn __lsx_vmaxi_wu(a: __v4u32, b: u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vmaxi.du"]
-    fn __lsx_vmaxi_du(a: __v2u64, b: u32) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vmin.b"]
-    fn __lsx_vmin_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmin.h"]
-    fn __lsx_vmin_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmin.w"]
-    fn __lsx_vmin_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmin.d"]
-    fn __lsx_vmin_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmini.b"]
-    fn __lsx_vmini_b(a: __v16i8, b: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmini.h"]
-    fn __lsx_vmini_h(a: __v8i16, b: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmini.w"]
-    fn __lsx_vmini_w(a: __v4i32, b: i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmini.d"]
-    fn __lsx_vmini_d(a: __v2i64, b: i32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmin.bu"]
-    fn __lsx_vmin_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vmin.hu"]
-    fn __lsx_vmin_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vmin.wu"]
-    fn __lsx_vmin_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vmin.du"]
-    fn __lsx_vmin_du(a: __v2u64, b: __v2u64) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vmini.bu"]
-    fn __lsx_vmini_bu(a: __v16u8, b: u32) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vmini.hu"]
-    fn __lsx_vmini_hu(a: __v8u16, b: u32) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vmini.wu"]
-    fn __lsx_vmini_wu(a: __v4u32, b: u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vmini.du"]
-    fn __lsx_vmini_du(a: __v2u64, b: u32) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vseq.b"]
-    fn __lsx_vseq_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vseq.h"]
-    fn __lsx_vseq_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vseq.w"]
-    fn __lsx_vseq_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vseq.d"]
-    fn __lsx_vseq_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vseqi.b"]
-    fn __lsx_vseqi_b(a: __v16i8, b: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vseqi.h"]
-    fn __lsx_vseqi_h(a: __v8i16, b: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vseqi.w"]
-    fn __lsx_vseqi_w(a: __v4i32, b: i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vseqi.d"]
-    fn __lsx_vseqi_d(a: __v2i64, b: i32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslti.b"]
-    fn __lsx_vslti_b(a: __v16i8, b: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslt.b"]
-    fn __lsx_vslt_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslt.h"]
-    fn __lsx_vslt_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslt.w"]
-    fn __lsx_vslt_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslt.d"]
-    fn __lsx_vslt_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslti.h"]
-    fn __lsx_vslti_h(a: __v8i16, b: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslti.w"]
-    fn __lsx_vslti_w(a: __v4i32, b: i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslti.d"]
-    fn __lsx_vslti_d(a: __v2i64, b: i32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslt.bu"]
-    fn __lsx_vslt_bu(a: __v16u8, b: __v16u8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslt.hu"]
-    fn __lsx_vslt_hu(a: __v8u16, b: __v8u16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslt.wu"]
-    fn __lsx_vslt_wu(a: __v4u32, b: __v4u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslt.du"]
-    fn __lsx_vslt_du(a: __v2u64, b: __v2u64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslti.bu"]
-    fn __lsx_vslti_bu(a: __v16u8, b: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslti.hu"]
-    fn __lsx_vslti_hu(a: __v8u16, b: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslti.wu"]
-    fn __lsx_vslti_wu(a: __v4u32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslti.du"]
-    fn __lsx_vslti_du(a: __v2u64, b: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsle.b"]
-    fn __lsx_vsle_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsle.h"]
-    fn __lsx_vsle_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsle.w"]
-    fn __lsx_vsle_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsle.d"]
-    fn __lsx_vsle_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslei.b"]
-    fn __lsx_vslei_b(a: __v16i8, b: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslei.h"]
-    fn __lsx_vslei_h(a: __v8i16, b: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslei.w"]
-    fn __lsx_vslei_w(a: __v4i32, b: i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslei.d"]
-    fn __lsx_vslei_d(a: __v2i64, b: i32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsle.bu"]
-    fn __lsx_vsle_bu(a: __v16u8, b: __v16u8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsle.hu"]
-    fn __lsx_vsle_hu(a: __v8u16, b: __v8u16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsle.wu"]
-    fn __lsx_vsle_wu(a: __v4u32, b: __v4u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsle.du"]
-    fn __lsx_vsle_du(a: __v2u64, b: __v2u64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vslei.bu"]
-    fn __lsx_vslei_bu(a: __v16u8, b: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vslei.hu"]
-    fn __lsx_vslei_hu(a: __v8u16, b: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vslei.wu"]
-    fn __lsx_vslei_wu(a: __v4u32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vslei.du"]
-    fn __lsx_vslei_du(a: __v2u64, b: u32) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vsat.b"]
     fn __lsx_vsat_b(a: __v16i8, b: u32) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vsat.h"]
@@ -419,46 +203,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vabsd_wu(a: __v4u32, b: __v4u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vabsd.du"]
     fn __lsx_vabsd_du(a: __v2u64, b: __v2u64) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vmul.b"]
-    fn __lsx_vmul_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmul.h"]
-    fn __lsx_vmul_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmul.w"]
-    fn __lsx_vmul_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmul.d"]
-    fn __lsx_vmul_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmadd.b"]
-    fn __lsx_vmadd_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmadd.h"]
-    fn __lsx_vmadd_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmadd.w"]
-    fn __lsx_vmadd_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmadd.d"]
-    fn __lsx_vmadd_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmsub.b"]
-    fn __lsx_vmsub_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmsub.h"]
-    fn __lsx_vmsub_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmsub.w"]
-    fn __lsx_vmsub_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmsub.d"]
-    fn __lsx_vmsub_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vdiv.b"]
-    fn __lsx_vdiv_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vdiv.h"]
-    fn __lsx_vdiv_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vdiv.w"]
-    fn __lsx_vdiv_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vdiv.d"]
-    fn __lsx_vdiv_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vdiv.bu"]
-    fn __lsx_vdiv_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vdiv.hu"]
-    fn __lsx_vdiv_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vdiv.wu"]
-    fn __lsx_vdiv_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vdiv.du"]
-    fn __lsx_vdiv_du(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vhaddw.h.b"]
     fn __lsx_vhaddw_h_b(a: __v16i8, b: __v16i8) -> __v8i16;
     #[link_name = "llvm.loongarch.lsx.vhaddw.w.h"]
@@ -483,22 +227,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vhsubw_wu_hu(a: __v8u16, b: __v8u16) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vhsubw.du.wu"]
     fn __lsx_vhsubw_du_wu(a: __v4u32, b: __v4u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmod.b"]
-    fn __lsx_vmod_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vmod.h"]
-    fn __lsx_vmod_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vmod.w"]
-    fn __lsx_vmod_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vmod.d"]
-    fn __lsx_vmod_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vmod.bu"]
-    fn __lsx_vmod_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vmod.hu"]
-    fn __lsx_vmod_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vmod.wu"]
-    fn __lsx_vmod_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vmod.du"]
-    fn __lsx_vmod_du(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vreplve.b"]
     fn __lsx_vreplve_b(a: __v16i8, b: i32) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vreplve.h"]
@@ -569,20 +297,12 @@ unsafe extern "unadjusted" {
     fn __lsx_vshuf_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vshuf.d"]
     fn __lsx_vshuf_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vand.v"]
-    fn __lsx_vand_v(a: __v16u8, b: __v16u8) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vandi.b"]
     fn __lsx_vandi_b(a: __v16u8, b: u32) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vor.v"]
-    fn __lsx_vor_v(a: __v16u8, b: __v16u8) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vori.b"]
     fn __lsx_vori_b(a: __v16u8, b: u32) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vnor.v"]
-    fn __lsx_vnor_v(a: __v16u8, b: __v16u8) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vnori.b"]
     fn __lsx_vnori_b(a: __v16u8, b: u32) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vxor.v"]
-    fn __lsx_vxor_v(a: __v16u8, b: __v16u8) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vxori.b"]
     fn __lsx_vxori_b(a: __v16u8, b: u32) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vbitsel.v"]
@@ -595,22 +315,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vshuf4i_h(a: __v8i16, b: u32) -> __v8i16;
     #[link_name = "llvm.loongarch.lsx.vshuf4i.w"]
     fn __lsx_vshuf4i_w(a: __v4i32, b: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vreplgr2vr.b"]
-    fn __lsx_vreplgr2vr_b(a: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vreplgr2vr.h"]
-    fn __lsx_vreplgr2vr_h(a: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vreplgr2vr.w"]
-    fn __lsx_vreplgr2vr_w(a: i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vreplgr2vr.d"]
-    fn __lsx_vreplgr2vr_d(a: i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vpcnt.b"]
-    fn __lsx_vpcnt_b(a: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vpcnt.h"]
-    fn __lsx_vpcnt_h(a: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vpcnt.w"]
-    fn __lsx_vpcnt_w(a: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vpcnt.d"]
-    fn __lsx_vpcnt_d(a: __v2i64) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vclo.b"]
     fn __lsx_vclo_b(a: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vclo.h"]
@@ -619,54 +323,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vclo_w(a: __v4i32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vclo.d"]
     fn __lsx_vclo_d(a: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vclz.b"]
-    fn __lsx_vclz_b(a: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vclz.h"]
-    fn __lsx_vclz_h(a: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vclz.w"]
-    fn __lsx_vclz_w(a: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vclz.d"]
-    fn __lsx_vclz_d(a: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.b"]
-    fn __lsx_vpickve2gr_b(a: __v16i8, b: u32) -> i32;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.h"]
-    fn __lsx_vpickve2gr_h(a: __v8i16, b: u32) -> i32;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.w"]
-    fn __lsx_vpickve2gr_w(a: __v4i32, b: u32) -> i32;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.d"]
-    fn __lsx_vpickve2gr_d(a: __v2i64, b: u32) -> i64;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.bu"]
-    fn __lsx_vpickve2gr_bu(a: __v16i8, b: u32) -> u32;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.hu"]
-    fn __lsx_vpickve2gr_hu(a: __v8i16, b: u32) -> u32;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.wu"]
-    fn __lsx_vpickve2gr_wu(a: __v4i32, b: u32) -> u32;
-    #[link_name = "llvm.loongarch.lsx.vpickve2gr.du"]
-    fn __lsx_vpickve2gr_du(a: __v2i64, b: u32) -> u64;
-    #[link_name = "llvm.loongarch.lsx.vinsgr2vr.b"]
-    fn __lsx_vinsgr2vr_b(a: __v16i8, b: i32, c: u32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vinsgr2vr.h"]
-    fn __lsx_vinsgr2vr_h(a: __v8i16, b: i32, c: u32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vinsgr2vr.w"]
-    fn __lsx_vinsgr2vr_w(a: __v4i32, b: i32, c: u32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vinsgr2vr.d"]
-    fn __lsx_vinsgr2vr_d(a: __v2i64, b: i64, c: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vfadd.s"]
-    fn __lsx_vfadd_s(a: __v4f32, b: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfadd.d"]
-    fn __lsx_vfadd_d(a: __v2f64, b: __v2f64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vfsub.s"]
-    fn __lsx_vfsub_s(a: __v4f32, b: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfsub.d"]
-    fn __lsx_vfsub_d(a: __v2f64, b: __v2f64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vfmul.s"]
-    fn __lsx_vfmul_s(a: __v4f32, b: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfmul.d"]
-    fn __lsx_vfmul_d(a: __v2f64, b: __v2f64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vfdiv.s"]
-    fn __lsx_vfdiv_s(a: __v4f32, b: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfdiv.d"]
-    fn __lsx_vfdiv_d(a: __v2f64, b: __v2f64) -> __v2f64;
     #[link_name = "llvm.loongarch.lsx.vfcvt.h.s"]
     fn __lsx_vfcvt_h_s(a: __v4f32, b: __v4f32) -> __v8i16;
     #[link_name = "llvm.loongarch.lsx.vfcvt.s.d"]
@@ -691,10 +347,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vfclass_s(a: __v4f32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vfclass.d"]
     fn __lsx_vfclass_d(a: __v2f64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vfsqrt.s"]
-    fn __lsx_vfsqrt_s(a: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfsqrt.d"]
-    fn __lsx_vfsqrt_d(a: __v2f64) -> __v2f64;
     #[link_name = "llvm.loongarch.lsx.vfrecip.s"]
     fn __lsx_vfrecip_s(a: __v4f32) -> __v4f32;
     #[link_name = "llvm.loongarch.lsx.vfrecip.d"]
@@ -751,16 +403,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vffint_s_wu(a: __v4u32) -> __v4f32;
     #[link_name = "llvm.loongarch.lsx.vffint.d.lu"]
     fn __lsx_vffint_d_lu(a: __v2u64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vandn.v"]
-    fn __lsx_vandn_v(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vneg.b"]
-    fn __lsx_vneg_b(a: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vneg.h"]
-    fn __lsx_vneg_h(a: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vneg.w"]
-    fn __lsx_vneg_w(a: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vneg.d"]
-    fn __lsx_vneg_d(a: __v2i64) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vmuh.b"]
     fn __lsx_vmuh_b(a: __v16i8, b: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vmuh.h"]
@@ -887,22 +529,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vsigncov_w(a: __v4i32, b: __v4i32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vsigncov.d"]
     fn __lsx_vsigncov_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vfmadd.s"]
-    fn __lsx_vfmadd_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfmadd.d"]
-    fn __lsx_vfmadd_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vfmsub.s"]
-    fn __lsx_vfmsub_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfmsub.d"]
-    fn __lsx_vfmsub_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vfnmadd.s"]
-    fn __lsx_vfnmadd_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfnmadd.d"]
-    fn __lsx_vfnmadd_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64;
-    #[link_name = "llvm.loongarch.lsx.vfnmsub.s"]
-    fn __lsx_vfnmsub_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32;
-    #[link_name = "llvm.loongarch.lsx.vfnmsub.d"]
-    fn __lsx_vfnmsub_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64;
     #[link_name = "llvm.loongarch.lsx.vftintrne.w.s"]
     fn __lsx_vftintrne_w_s(a: __v4f32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vftintrne.l.d"]
@@ -1323,8 +949,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vssrln_h_w(a: __v4i32, b: __v4i32) -> __v8i16;
     #[link_name = "llvm.loongarch.lsx.vssrln.w.d"]
     fn __lsx_vssrln_w_d(a: __v2i64, b: __v2i64) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vorn.v"]
-    fn __lsx_vorn_v(a: __v16u8, b: __v16u8) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vldi"]
     fn __lsx_vldi(a: i32) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vshuf.b"]
@@ -1443,142 +1067,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vfcmp_sune_s(a: __v4f32, b: __v4f32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vfcmp.sun.s"]
     fn __lsx_vfcmp_sun_s(a: __v4f32, b: __v4f32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vrepli.b"]
-    fn __lsx_vrepli_b(a: i32) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vrepli.d"]
-    fn __lsx_vrepli_d(a: i32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vrepli.h"]
-    fn __lsx_vrepli_h(a: i32) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vrepli.w"]
-    fn __lsx_vrepli_w(a: i32) -> __v4i32;
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsll_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsll_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsll_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsll_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsll_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsll_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsll_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsll_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslli_b<const IMM3: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vslli_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslli_h<const IMM4: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vslli_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslli_w<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslli_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslli_d<const IMM6: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lsx_vslli_d(transmute(a), IMM6)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsra_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsra_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsra_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsra_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsra_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsra_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsra_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsra_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrai_b<const IMM3: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vsrai_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrai_h<const IMM4: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vsrai_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrai_w<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsrai_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrai_d<const IMM6: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lsx_vsrai_d(transmute(a), IMM6)) }
 }
 
 #[inline(always)]
@@ -1645,70 +1133,6 @@ pub fn lsx_vsrari_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrl_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsrl_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrl_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsrl_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrl_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsrl_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrl_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsrl_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrli_b<const IMM3: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vsrli_b(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrli_h<const IMM4: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vsrli_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrli_w<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsrli_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsrli_d<const IMM6: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lsx_vsrli_d(transmute(a), IMM6)) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1967,1412 +1391,548 @@ pub fn lsx_vbitrevi_d<const IMM6: u32>(a: m128i) -> m128i {
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadd_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadd_b(transmute(a), transmute(b))) }
+pub fn lsx_vsubi_bu<const IMM5: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadd_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadd_h(transmute(a), transmute(b))) }
+pub fn lsx_vsubi_hu<const IMM5: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadd_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadd_w(transmute(a), transmute(b))) }
+pub fn lsx_vsubi_wu<const IMM5: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadd_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadd_d(transmute(a), transmute(b))) }
+pub fn lsx_vsubi_du<const IMM5: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vaddi_bu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vaddi_bu(transmute(a), IMM5)) }
+pub fn lsx_vsat_b<const IMM3: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM3, 3);
+    unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vaddi_hu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vaddi_hu(transmute(a), IMM5)) }
+pub fn lsx_vsat_h<const IMM4: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM4, 4);
+    unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vaddi_wu<const IMM5: u32>(a: m128i) -> m128i {
+pub fn lsx_vsat_w<const IMM5: u32>(a: m128i) -> m128i {
     static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vaddi_wu(transmute(a), IMM5)) }
+    unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vaddi_du<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vaddi_du(transmute(a), IMM5)) }
+pub fn lsx_vsat_d<const IMM6: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM6, 6);
+    unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsub_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsub_b(transmute(a), transmute(b))) }
+pub fn lsx_vsat_bu<const IMM3: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM3, 3);
+    unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsub_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsub_h(transmute(a), transmute(b))) }
+pub fn lsx_vsat_hu<const IMM4: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM4, 4);
+    unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsub_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsub_w(transmute(a), transmute(b))) }
+pub fn lsx_vsat_wu<const IMM5: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM5, 5);
+    unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsub_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsub_d(transmute(a), transmute(b))) }
+pub fn lsx_vsat_du<const IMM6: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM6, 6);
+    unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsubi_bu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) }
+pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsubi_hu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) }
+pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsubi_wu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) }
+pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsubi_du<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) }
+pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_b(transmute(a), transmute(b))) }
+pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_h(transmute(a), transmute(b))) }
+pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_w(transmute(a), transmute(b))) }
+pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_d(transmute(a), transmute(b))) }
+pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_b<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmaxi_b(transmute(a), IMM_S5)) }
+pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_h<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmaxi_h(transmute(a), IMM_S5)) }
+pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_w<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmaxi_w(transmute(a), IMM_S5)) }
+pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_d<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmaxi_d(transmute(a), IMM_S5)) }
+pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_bu(transmute(a), transmute(b))) }
+pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_hu(transmute(a), transmute(b))) }
+pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_wu(transmute(a), transmute(b))) }
+pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmax_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmax_du(transmute(a), transmute(b))) }
+pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_bu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmaxi_bu(transmute(a), IMM5)) }
+pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_hu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmaxi_hu(transmute(a), IMM5)) }
+pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_wu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmaxi_wu(transmute(a), IMM5)) }
+pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmaxi_du<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmaxi_du(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_b<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmini_b(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_h<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmini_h(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_w<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmini_w(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_d<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vmini_d(transmute(a), IMM_S5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmin_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmin_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_bu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmini_bu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_hu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmini_hu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_wu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmini_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmini_du<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vmini_du(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseq_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vseq_b(transmute(a), transmute(b))) }
+pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseq_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vseq_h(transmute(a), transmute(b))) }
+pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseq_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vseq_w(transmute(a), transmute(b))) }
+pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseq_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vseq_d(transmute(a), transmute(b))) }
+pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseqi_b<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vseqi_b(transmute(a), IMM_S5)) }
+pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseqi_h<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vseqi_h(transmute(a), IMM_S5)) }
+pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseqi_w<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vseqi_w(transmute(a), IMM_S5)) }
+pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vseqi_d<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vseqi_d(transmute(a), IMM_S5)) }
+pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_b<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslti_b(transmute(a), IMM_S5)) }
+pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_b(transmute(a), transmute(b))) }
+pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_h(transmute(a), transmute(b))) }
+pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_w(transmute(a), transmute(b))) }
+pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_d(transmute(a), transmute(b))) }
+pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_h<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslti_h(transmute(a), IMM_S5)) }
+pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_w<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslti_w(transmute(a), IMM_S5)) }
+pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_d<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslti_d(transmute(a), IMM_S5)) }
+pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_bu(transmute(a), transmute(b))) }
+pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_hu(transmute(a), transmute(b))) }
+pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_wu(transmute(a), transmute(b))) }
+pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslt_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vslt_du(transmute(a), transmute(b))) }
+pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_bu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslti_bu(transmute(a), IMM5)) }
+pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_hu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslti_hu(transmute(a), IMM5)) }
+pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_wu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslti_wu(transmute(a), IMM5)) }
+pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslti_du<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslti_du(transmute(a), IMM5)) }
+pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_b(transmute(a), transmute(b))) }
+pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_h(transmute(a), transmute(b))) }
+pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_w(transmute(a), transmute(b))) }
+pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_d(transmute(a), transmute(b))) }
+pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_b<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslei_b(transmute(a), IMM_S5)) }
+pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_h<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslei_h(transmute(a), IMM_S5)) }
+pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_w<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslei_w(transmute(a), IMM_S5)) }
+pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_d<const IMM_S5: i32>(a: m128i) -> m128i {
-    static_assert_simm_bits!(IMM_S5, 5);
-    unsafe { transmute(__lsx_vslei_d(transmute(a), IMM_S5)) }
+pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_bu(transmute(a), transmute(b))) }
+pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_hu(transmute(a), transmute(b))) }
+pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_wu(transmute(a), transmute(b))) }
+pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsle_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsle_du(transmute(a), transmute(b))) }
+pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_bu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslei_bu(transmute(a), IMM5)) }
+pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_hu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslei_hu(transmute(a), IMM5)) }
+pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i {
+    unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_wu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslei_wu(transmute(a), IMM5)) }
+pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i {
+    unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vslei_du<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vslei_du(transmute(a), IMM5)) }
+pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i {
+    unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_b<const IMM3: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) }
+pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i {
+    unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_h<const IMM4: u32>(a: m128i) -> m128i {
+pub fn lsx_vreplvei_b<const IMM4: u32>(a: m128i) -> m128i {
     static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_w<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_d<const IMM6: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) }
+    unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_bu<const IMM3: u32>(a: m128i) -> m128i {
+pub fn lsx_vreplvei_h<const IMM3: u32>(a: m128i) -> m128i {
     static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_hu<const IMM4: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_wu<const IMM5: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM5, 5);
-    unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsat_du<const IMM6: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM6, 6);
-    unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmul_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmul_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmul_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmul_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmul_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmul_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmul_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmul_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmadd_b(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmadd_h(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmadd_w(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmadd_d(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmsub_b(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmsub_h(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmsub_w(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmsub_d(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vdiv_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vdiv_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_bu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_hu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_wu(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vmod_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vmod_du(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplvei_b<const IMM4: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplvei_h<const IMM3: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) }
+    unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) }
 }
 
 #[inline(always)]
@@ -3386,583 +1946,307 @@ pub fn lsx_vreplvei_w<const IMM2: u32>(a: m128i) -> m128i {
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplvei_d<const IMM1: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM1, 1);
-    unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vand_v(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vand_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vandi_b<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vor_v(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vor_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vori_b<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vnor_v(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vnor_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vnori_b<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vxor_v(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vxor_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vxori_b<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) }
+pub fn lsx_vreplvei_d<const IMM1: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM1, 1);
+    unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitseli_b<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) }
+pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vshuf4i_b<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) }
+pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vshuf4i_h<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) }
+pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vshuf4i_w<const IMM8: u32>(a: m128i) -> m128i {
-    static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) }
+pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplgr2vr_b(a: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplgr2vr_b(transmute(a))) }
+pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplgr2vr_h(a: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplgr2vr_h(transmute(a))) }
+pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplgr2vr_w(a: i32) -> m128i {
-    unsafe { transmute(__lsx_vreplgr2vr_w(transmute(a))) }
+pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vreplgr2vr_d(a: i64) -> m128i {
-    unsafe { transmute(__lsx_vreplgr2vr_d(transmute(a))) }
+pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpcnt_b(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpcnt_b(transmute(a))) }
+pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpcnt_h(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpcnt_h(transmute(a))) }
+pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpcnt_w(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpcnt_w(transmute(a))) }
+pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpcnt_d(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vpcnt_d(transmute(a))) }
+pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclo_b(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclo_b(transmute(a))) }
+pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclo_h(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclo_h(transmute(a))) }
+pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclo_w(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclo_w(transmute(a))) }
+pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclo_d(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclo_d(transmute(a))) }
+pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclz_b(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclz_b(transmute(a))) }
+pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclz_h(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclz_h(transmute(a))) }
+pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclz_w(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclz_w(transmute(a))) }
+pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vclz_d(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vclz_d(transmute(a))) }
+pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_b<const IMM4: u32>(a: m128i) -> i32 {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vpickve2gr_b(transmute(a), IMM4)) }
+pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_h<const IMM3: u32>(a: m128i) -> i32 {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vpickve2gr_h(transmute(a), IMM3)) }
+pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_w<const IMM2: u32>(a: m128i) -> i32 {
-    static_assert_uimm_bits!(IMM2, 2);
-    unsafe { transmute(__lsx_vpickve2gr_w(transmute(a), IMM2)) }
+pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_d<const IMM1: u32>(a: m128i) -> i64 {
-    static_assert_uimm_bits!(IMM1, 1);
-    unsafe { transmute(__lsx_vpickve2gr_d(transmute(a), IMM1)) }
+pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i {
+    unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_bu<const IMM4: u32>(a: m128i) -> u32 {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vpickve2gr_bu(transmute(a), IMM4)) }
+pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i {
+    unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_hu<const IMM3: u32>(a: m128i) -> u32 {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vpickve2gr_hu(transmute(a), IMM3)) }
+pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i {
+    unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_wu<const IMM2: u32>(a: m128i) -> u32 {
-    static_assert_uimm_bits!(IMM2, 2);
-    unsafe { transmute(__lsx_vpickve2gr_wu(transmute(a), IMM2)) }
+pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i {
+    unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vpickve2gr_du<const IMM1: u32>(a: m128i) -> u64 {
-    static_assert_uimm_bits!(IMM1, 1);
-    unsafe { transmute(__lsx_vpickve2gr_du(transmute(a), IMM1)) }
+pub fn lsx_vandi_b<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(2)]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vinsgr2vr_b<const IMM4: u32>(a: m128i, b: i32) -> m128i {
-    static_assert_uimm_bits!(IMM4, 4);
-    unsafe { transmute(__lsx_vinsgr2vr_b(transmute(a), transmute(b), IMM4)) }
+pub fn lsx_vori_b<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(2)]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vinsgr2vr_h<const IMM3: u32>(a: m128i, b: i32) -> m128i {
-    static_assert_uimm_bits!(IMM3, 3);
-    unsafe { transmute(__lsx_vinsgr2vr_h(transmute(a), transmute(b), IMM3)) }
+pub fn lsx_vnori_b<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(2)]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vinsgr2vr_w<const IMM2: u32>(a: m128i, b: i32) -> m128i {
-    static_assert_uimm_bits!(IMM2, 2);
-    unsafe { transmute(__lsx_vinsgr2vr_w(transmute(a), transmute(b), IMM2)) }
+pub fn lsx_vxori_b<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vinsgr2vr_d<const IMM1: u32>(a: m128i, b: i64) -> m128i {
-    static_assert_uimm_bits!(IMM1, 1);
-    unsafe { transmute(__lsx_vinsgr2vr_d(transmute(a), transmute(b), IMM1)) }
+pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i {
+    unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfadd_s(a: m128, b: m128) -> m128 {
-    unsafe { transmute(__lsx_vfadd_s(transmute(a), transmute(b))) }
+pub fn lsx_vbitseli_b<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfadd_d(a: m128d, b: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfadd_d(transmute(a), transmute(b))) }
+pub fn lsx_vshuf4i_b<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfsub_s(a: m128, b: m128) -> m128 {
-    unsafe { transmute(__lsx_vfsub_s(transmute(a), transmute(b))) }
+pub fn lsx_vshuf4i_h<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfsub_d(a: m128d, b: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfsub_d(transmute(a), transmute(b))) }
+pub fn lsx_vshuf4i_w<const IMM8: u32>(a: m128i) -> m128i {
+    static_assert_uimm_bits!(IMM8, 8);
+    unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfmul_s(a: m128, b: m128) -> m128 {
-    unsafe { transmute(__lsx_vfmul_s(transmute(a), transmute(b))) }
+pub fn lsx_vclo_b(a: m128i) -> m128i {
+    unsafe { transmute(__lsx_vclo_b(transmute(a))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfmul_d(a: m128d, b: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfmul_d(transmute(a), transmute(b))) }
+pub fn lsx_vclo_h(a: m128i) -> m128i {
+    unsafe { transmute(__lsx_vclo_h(transmute(a))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfdiv_s(a: m128, b: m128) -> m128 {
-    unsafe { transmute(__lsx_vfdiv_s(transmute(a), transmute(b))) }
+pub fn lsx_vclo_w(a: m128i) -> m128i {
+    unsafe { transmute(__lsx_vclo_w(transmute(a))) }
 }
 
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfdiv_d(a: m128d, b: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfdiv_d(transmute(a), transmute(b))) }
+pub fn lsx_vclo_d(a: m128i) -> m128i {
+    unsafe { transmute(__lsx_vclo_d(transmute(a))) }
 }
 
 #[inline(always)]
@@ -4049,20 +2333,6 @@ pub fn lsx_vfclass_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vfclass_d(transmute(a))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfsqrt_s(a: m128) -> m128 {
-    unsafe { transmute(__lsx_vfsqrt_s(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfsqrt_d(a: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfsqrt_d(transmute(a))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4259,41 +2529,6 @@ pub fn lsx_vffint_d_lu(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vandn_v(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vandn_v(transmute(a), transmute(b))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vneg_b(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vneg_b(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vneg_h(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vneg_h(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vneg_w(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vneg_w(transmute(a))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vneg_d(a: m128i) -> m128i {
-    unsafe { transmute(__lsx_vneg_d(transmute(a))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4765,62 +3000,6 @@ pub fn lsx_vsigncov_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfmadd_s(a: m128, b: m128, c: m128) -> m128 {
-    unsafe { transmute(__lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfmadd_d(a: m128d, b: m128d, c: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfmsub_s(a: m128, b: m128, c: m128) -> m128 {
-    unsafe { transmute(__lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfmsub_d(a: m128d, b: m128d, c: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfnmadd_s(a: m128, b: m128, c: m128) -> m128 {
-    unsafe { transmute(__lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfnmadd_d(a: m128d, b: m128d, c: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfnmsub_s(a: m128, b: m128, c: m128) -> m128 {
-    unsafe { transmute(__lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vfnmsub_d(a: m128d, b: m128d, c: m128d) -> m128d {
-    unsafe { transmute(__lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -6421,13 +4600,6 @@ pub fn lsx_vssrln_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vorn_v(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vorn_v(transmute(a), transmute(b))) }
-}
-
 #[inline(always)]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
@@ -6842,39 +5014,3 @@ pub fn lsx_vfcmp_sune_s(a: m128, b: m128) -> m128i {
 pub fn lsx_vfcmp_sun_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sun_s(transmute(a), transmute(b))) }
 }
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vrepli_b<const IMM_S10: i32>() -> m128i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lsx_vrepli_b(IMM_S10)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vrepli_d<const IMM_S10: i32>() -> m128i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lsx_vrepli_d(IMM_S10)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vrepli_h<const IMM_S10: i32>() -> m128i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lsx_vrepli_h(IMM_S10)) }
-}
-
-#[inline(always)]
-#[target_feature(enable = "lsx")]
-#[rustc_legacy_const_generics(0)]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vrepli_w<const IMM_S10: i32>() -> m128i {
-    static_assert_simm_bits!(IMM_S10, 10);
-    unsafe { transmute(__lsx_vrepli_w(IMM_S10)) }
-}
diff --git a/crates/core_arch/src/loongarch64/lsx/mod.rs b/crates/core_arch/src/loongarch64/lsx/mod.rs
index 67a08985a9..0d353746ea 100644
--- a/crates/core_arch/src/loongarch64/lsx/mod.rs
+++ b/crates/core_arch/src/loongarch64/lsx/mod.rs
@@ -16,6 +16,13 @@ mod generated;
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub use self::generated::*;
 
+#[rustfmt::skip]
+mod portable;
+
+#[rustfmt::skip]
+#[unstable(feature = "stdarch_loongarch", issue = "117427")]
+pub use self::portable::*;
+
 #[rustfmt::skip]
 #[cfg(test)]
 mod tests;
diff --git a/crates/core_arch/src/loongarch64/lsx/portable.rs b/crates/core_arch/src/loongarch64/lsx/portable.rs
new file mode 100644
index 0000000000..e33b1758f3
--- /dev/null
+++ b/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -0,0 +1,207 @@
+//! LoongArch64 LSX intrinsics - intrinsics::simd implementation
+
+use super::super::{simd::*, *};
+use crate::core_arch::simd::*;
+use crate::intrinsics::simd::*;
+use crate::mem::transmute;
+
+impl_vv!("lsx", lsx_vpcnt_b, simd_ctpop, m128i, i8x16);
+impl_vv!("lsx", lsx_vpcnt_h, simd_ctpop, m128i, i16x8);
+impl_vv!("lsx", lsx_vpcnt_w, simd_ctpop, m128i, i32x4);
+impl_vv!("lsx", lsx_vpcnt_d, simd_ctpop, m128i, i64x2);
+impl_vv!("lsx", lsx_vclz_b, simd_ctlz, m128i, i8x16);
+impl_vv!("lsx", lsx_vclz_h, simd_ctlz, m128i, i16x8);
+impl_vv!("lsx", lsx_vclz_w, simd_ctlz, m128i, i32x4);
+impl_vv!("lsx", lsx_vclz_d, simd_ctlz, m128i, i64x2);
+impl_vv!("lsx", lsx_vneg_b, simd_neg, m128i, i8x16);
+impl_vv!("lsx", lsx_vneg_h, simd_neg, m128i, i16x8);
+impl_vv!("lsx", lsx_vneg_w, simd_neg, m128i, i32x4);
+impl_vv!("lsx", lsx_vneg_d, simd_neg, m128i, i64x2);
+impl_vv!("lsx", lsx_vfsqrt_s, simd_fsqrt, m128, f32x4);
+impl_vv!("lsx", lsx_vfsqrt_d, simd_fsqrt, m128d, f64x2);
+
+impl_gv!("lsx", lsx_vreplgr2vr_b, simdl_splat, m128i, i8x16, i32);
+impl_gv!("lsx", lsx_vreplgr2vr_h, simdl_splat, m128i, i16x8, i32);
+impl_gv!("lsx", lsx_vreplgr2vr_w, simdl_splat, m128i, i32x4, i32);
+impl_gv!("lsx", lsx_vreplgr2vr_d, simdl_splat, m128i, i64x2, i64);
+
+impl_sv!("lsx", lsx_vrepli_b, simdl_splat, m128i, i8x16, 10);
+impl_sv!("lsx", lsx_vrepli_h, simdl_splat, m128i, i16x8, 10);
+impl_sv!("lsx", lsx_vrepli_w, simdl_splat, m128i, i32x4, 10);
+impl_sv!("lsx", lsx_vrepli_d, simdl_splat, m128i, i64x2, 10);
+
+impl_vvv!("lsx", lsx_vadd_b, simd_add, m128i, i8x16);
+impl_vvv!("lsx", lsx_vadd_h, simd_add, m128i, i16x8);
+impl_vvv!("lsx", lsx_vadd_w, simd_add, m128i, i32x4);
+impl_vvv!("lsx", lsx_vadd_d, simd_add, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsub_b, simd_sub, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsub_h, simd_sub, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsub_w, simd_sub, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsub_d, simd_sub, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmax_b, simd_imax, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmax_h, simd_imax, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmax_w, simd_imax, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmax_d, simd_imax, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmax_bu, simd_imax, m128i, u8x16);
+impl_vvv!("lsx", lsx_vmax_hu, simd_imax, m128i, u16x8);
+impl_vvv!("lsx", lsx_vmax_wu, simd_imax, m128i, u32x4);
+impl_vvv!("lsx", lsx_vmax_du, simd_imax, m128i, u64x2);
+impl_vvv!("lsx", lsx_vmin_b, simd_imin, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmin_h, simd_imin, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmin_w, simd_imin, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmin_d, simd_imin, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmin_bu, simd_imin, m128i, u8x16);
+impl_vvv!("lsx", lsx_vmin_hu, simd_imin, m128i, u16x8);
+impl_vvv!("lsx", lsx_vmin_wu, simd_imin, m128i, u32x4);
+impl_vvv!("lsx", lsx_vmin_du, simd_imin, m128i, u64x2);
+impl_vvv!("lsx", lsx_vseq_b, simd_eq, m128i, i8x16);
+impl_vvv!("lsx", lsx_vseq_h, simd_eq, m128i, i16x8);
+impl_vvv!("lsx", lsx_vseq_w, simd_eq, m128i, i32x4);
+impl_vvv!("lsx", lsx_vseq_d, simd_eq, m128i, i64x2);
+impl_vvv!("lsx", lsx_vslt_b, simd_lt, m128i, i8x16);
+impl_vvv!("lsx", lsx_vslt_h, simd_lt, m128i, i16x8);
+impl_vvv!("lsx", lsx_vslt_w, simd_lt, m128i, i32x4);
+impl_vvv!("lsx", lsx_vslt_d, simd_lt, m128i, i64x2);
+impl_vvv!("lsx", lsx_vslt_bu, simd_lt, m128i, u8x16);
+impl_vvv!("lsx", lsx_vslt_hu, simd_lt, m128i, u16x8);
+impl_vvv!("lsx", lsx_vslt_wu, simd_lt, m128i, u32x4);
+impl_vvv!("lsx", lsx_vslt_du, simd_lt, m128i, u64x2);
+impl_vvv!("lsx", lsx_vsle_b, simd_le, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsle_h, simd_le, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsle_w, simd_le, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsle_d, simd_le, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsle_bu, simd_le, m128i, u8x16);
+impl_vvv!("lsx", lsx_vsle_hu, simd_le, m128i, u16x8);
+impl_vvv!("lsx", lsx_vsle_wu, simd_le, m128i, u32x4);
+impl_vvv!("lsx", lsx_vsle_du, simd_le, m128i, u64x2);
+impl_vvv!("lsx", lsx_vmul_b, simd_mul, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmul_h, simd_mul, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmul_w, simd_mul, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmul_d, simd_mul, m128i, i64x2);
+impl_vvv!("lsx", lsx_vdiv_b, simd_div, m128i, i8x16);
+impl_vvv!("lsx", lsx_vdiv_h, simd_div, m128i, i16x8);
+impl_vvv!("lsx", lsx_vdiv_w, simd_div, m128i, i32x4);
+impl_vvv!("lsx", lsx_vdiv_d, simd_div, m128i, i64x2);
+impl_vvv!("lsx", lsx_vdiv_bu, simd_div, m128i, u8x16);
+impl_vvv!("lsx", lsx_vdiv_hu, simd_div, m128i, u16x8);
+impl_vvv!("lsx", lsx_vdiv_wu, simd_div, m128i, u32x4);
+impl_vvv!("lsx", lsx_vdiv_du, simd_div, m128i, u64x2);
+impl_vvv!("lsx", lsx_vmod_b, simd_rem, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmod_h, simd_rem, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmod_w, simd_rem, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmod_d, simd_rem, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmod_bu, simd_rem, m128i, u8x16);
+impl_vvv!("lsx", lsx_vmod_hu, simd_rem, m128i, u16x8);
+impl_vvv!("lsx", lsx_vmod_wu, simd_rem, m128i, u32x4);
+impl_vvv!("lsx", lsx_vmod_du, simd_rem, m128i, u64x2);
+impl_vvv!("lsx", lsx_vand_v, simd_and, m128i, u8x16);
+impl_vvv!("lsx", lsx_vandn_v, simdl_andn, m128i, u8x16);
+impl_vvv!("lsx", lsx_vor_v, simd_or, m128i, u8x16);
+impl_vvv!("lsx", lsx_vorn_v, simdl_orn, m128i, u8x16);
+impl_vvv!("lsx", lsx_vnor_v, simdl_nor, m128i, u8x16);
+impl_vvv!("lsx", lsx_vxor_v, simd_xor, m128i, u8x16);
+impl_vvv!("lsx", lsx_vfadd_s, simd_add, m128, f32x4);
+impl_vvv!("lsx", lsx_vfadd_d, simd_add, m128d, f64x2);
+impl_vvv!("lsx", lsx_vfsub_s, simd_sub, m128, f32x4);
+impl_vvv!("lsx", lsx_vfsub_d, simd_sub, m128d, f64x2);
+impl_vvv!("lsx", lsx_vfmul_s, simd_mul, m128, f32x4);
+impl_vvv!("lsx", lsx_vfmul_d, simd_mul, m128d, f64x2);
+impl_vvv!("lsx", lsx_vfdiv_s, simd_div, m128, f32x4);
+impl_vvv!("lsx", lsx_vfdiv_d, simd_div, m128d, f64x2);
+impl_vvv!("lsx", lsx_vsll_b, simdl_shl, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsll_h, simdl_shl, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsll_w, simdl_shl, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsll_d, simdl_shl, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsra_b, simdl_shr, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsra_h, simdl_shr, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsra_w, simdl_shr, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsra_d, simdl_shr, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsrl_b, simdl_shr, m128i, u8x16);
+impl_vvv!("lsx", lsx_vsrl_h, simdl_shr, m128i, u16x8);
+impl_vvv!("lsx", lsx_vsrl_w, simdl_shr, m128i, u32x4);
+impl_vvv!("lsx", lsx_vsrl_d, simdl_shr, m128i, u64x2);
+
+impl_vuv!("lsx", lsx_vslli_b, simd_shl, m128i, i8x16);
+impl_vuv!("lsx", lsx_vslli_h, simd_shl, m128i, i16x8);
+impl_vuv!("lsx", lsx_vslli_w, simd_shl, m128i, i32x4);
+impl_vuv!("lsx", lsx_vslli_d, simd_shl, m128i, i64x2);
+impl_vuv!("lsx", lsx_vsrai_b, simd_shr, m128i, i8x16);
+impl_vuv!("lsx", lsx_vsrai_h, simd_shr, m128i, i16x8);
+impl_vuv!("lsx", lsx_vsrai_w, simd_shr, m128i, i32x4);
+impl_vuv!("lsx", lsx_vsrai_d, simd_shr, m128i, i64x2);
+impl_vuv!("lsx", lsx_vsrli_b, simd_shr, m128i, u8x16);
+impl_vuv!("lsx", lsx_vsrli_h, simd_shr, m128i, u16x8);
+impl_vuv!("lsx", lsx_vsrli_w, simd_shr, m128i, u32x4);
+impl_vuv!("lsx", lsx_vsrli_d, simd_shr, m128i, u64x2);
+impl_vuv!("lsx", lsx_vaddi_bu, simd_add, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vaddi_hu, simd_add, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vaddi_wu, simd_add, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vaddi_du, simd_add, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vslti_bu, simd_lt, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vslti_hu, simd_lt, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vslti_wu, simd_lt, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vslti_du, simd_lt, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vslei_bu, simd_le, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vslei_hu, simd_le, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vslei_wu, simd_le, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vslei_du, simd_le, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vmaxi_bu, simd_imax, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vmaxi_hu, simd_imax, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vmaxi_wu, simd_imax, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vmaxi_du, simd_imax, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vmini_bu, simd_imin, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vmini_hu, simd_imin, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vmini_wu, simd_imin, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vmini_du, simd_imin, m128i, u64x2, 5);
+
+impl_vug!("lsx", lsx_vpickve2gr_b, simd_extract, m128i, i8x16, i32, 4);
+impl_vug!("lsx", lsx_vpickve2gr_h, simd_extract, m128i, i16x8, i32, 3);
+impl_vug!("lsx", lsx_vpickve2gr_w, simd_extract, m128i, i32x4, i32, 2);
+impl_vug!("lsx", lsx_vpickve2gr_d, simd_extract, m128i, i64x2, i64, 1);
+impl_vug!("lsx", lsx_vpickve2gr_bu, simd_extract, m128i, u8x16, u32, 4);
+impl_vug!("lsx", lsx_vpickve2gr_hu, simd_extract, m128i, u16x8, u32, 3);
+impl_vug!("lsx", lsx_vpickve2gr_wu, simd_extract, m128i, u32x4, u32, 2);
+impl_vug!("lsx", lsx_vpickve2gr_du, simd_extract, m128i, u64x2, u64, 1);
+
+impl_vsv!("lsx", lsx_vseqi_b, simd_eq, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vseqi_h, simd_eq, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vseqi_w, simd_eq, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vseqi_d, simd_eq, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vslti_b, simd_lt, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vslti_h, simd_lt, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vslti_w, simd_lt, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vslti_d, simd_lt, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vslei_b, simd_le, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vslei_h, simd_le, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vslei_w, simd_le, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vslei_d, simd_le, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vmaxi_b, simd_imax, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vmaxi_h, simd_imax, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vmaxi_w, simd_imax, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vmaxi_d, simd_imax, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vmini_b, simd_imin, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vmini_h, simd_imin, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vmini_w, simd_imin, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vmini_d, simd_imin, m128i, i64x2, 5);
+
+impl_vvvv!("lsx", lsx_vmadd_b, simdl_madd, m128i, i8x16);
+impl_vvvv!("lsx", lsx_vmadd_h, simdl_madd, m128i, i16x8);
+impl_vvvv!("lsx", lsx_vmadd_w, simdl_madd, m128i, i32x4);
+impl_vvvv!("lsx", lsx_vmadd_d, simdl_madd, m128i, i64x2);
+impl_vvvv!("lsx", lsx_vmsub_b, simdl_msub, m128i, i8x16);
+impl_vvvv!("lsx", lsx_vmsub_h, simdl_msub, m128i, i16x8);
+impl_vvvv!("lsx", lsx_vmsub_w, simdl_msub, m128i, i32x4);
+impl_vvvv!("lsx", lsx_vmsub_d, simdl_msub, m128i, i64x2);
+impl_vvvv!("lsx", lsx_vfmadd_s, simd_fma, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfmadd_d, simd_fma, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vfmsub_s, simdl_fms, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfmsub_d, simdl_fms, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vfnmadd_s, simdl_nfma, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfnmadd_d, simdl_nfma, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vfnmsub_s, simdl_nfms, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfnmsub_d, simdl_nfms, m128d, f64x2);
+
+impl_vugv!("lsx", lsx_vinsgr2vr_b, simd_insert, m128i, i8x16, i32, 4);
+impl_vugv!("lsx", lsx_vinsgr2vr_h, simd_insert, m128i, i16x8, i32, 3);
+impl_vugv!("lsx", lsx_vinsgr2vr_w, simd_insert, m128i, i32x4, i32, 2);
+impl_vugv!("lsx", lsx_vinsgr2vr_d, simd_insert, m128i, i64x2, i64, 1);
diff --git a/crates/core_arch/src/loongarch64/mod.rs b/crates/core_arch/src/loongarch64/mod.rs
index 41c21aac2a..f464dbd356 100644
--- a/crates/core_arch/src/loongarch64/mod.rs
+++ b/crates/core_arch/src/loongarch64/mod.rs
@@ -2,6 +2,7 @@
 
 mod lasx;
 mod lsx;
+mod simd;
 
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub use self::lasx::*;
diff --git a/crates/core_arch/src/loongarch64/simd.rs b/crates/core_arch/src/loongarch64/simd.rs
new file mode 100644
index 0000000000..ac98d6ac5d
--- /dev/null
+++ b/crates/core_arch/src/loongarch64/simd.rs
@@ -0,0 +1,302 @@
+//! LoongArch64 SIMD helpers
+
+pub(super) const trait SimdL: Sized {
+    type Elem;
+
+    unsafe fn splat(v: i64) -> Self;
+}
+
+macro_rules! impl_simdl {
+    ($v:ident, $e:ty) => {
+        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+        impl const SimdL for crate::core_arch::simd::$v {
+            type Elem = $e;
+
+            #[inline(always)]
+            unsafe fn splat(v: i64) -> Self {
+                crate::intrinsics::simd::simd_splat(v as Self::Elem)
+            }
+        }
+    };
+}
+
+impl_simdl!(i8x16, i8);
+impl_simdl!(i8x32, i8);
+impl_simdl!(u8x16, u8);
+impl_simdl!(u8x32, u8);
+impl_simdl!(i16x8, i16);
+impl_simdl!(i16x16, i16);
+impl_simdl!(u16x8, u16);
+impl_simdl!(u16x16, u16);
+impl_simdl!(i32x4, i32);
+impl_simdl!(i32x8, i32);
+impl_simdl!(u32x4, u32);
+impl_simdl!(u32x8, u32);
+impl_simdl!(i64x2, i64);
+impl_simdl!(i64x4, i64);
+impl_simdl!(u64x2, u64);
+impl_simdl!(u64x4, u64);
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_andn<T: Copy + const SimdL>(a: T, b: T) -> T {
+    crate::intrinsics::simd::simd_and(simdl_not(a), b)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_fms<T: Copy>(a: T, b: T, c: T) -> T {
+    let c: T = crate::intrinsics::simd::simd_neg(c);
+    crate::intrinsics::simd::simd_fma(a, b, c)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_madd<T: Copy>(a: T, b: T, c: T) -> T {
+    let mul: T = crate::intrinsics::simd::simd_mul(b, c);
+    crate::intrinsics::simd::simd_add(mul, a)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_msub<T: Copy>(a: T, b: T, c: T) -> T {
+    let mul: T = crate::intrinsics::simd::simd_mul(b, c);
+    crate::intrinsics::simd::simd_sub(a, mul)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_nfma<T: Copy>(a: T, b: T, c: T) -> T {
+    let fma: T = crate::intrinsics::simd::simd_fma(a, b, c);
+    crate::intrinsics::simd::simd_neg(fma)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_nfms<T: Copy>(a: T, b: T, c: T) -> T {
+    let fma: T = simdl_fms(a, b, c);
+    crate::intrinsics::simd::simd_neg(fma)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_nor<T: Copy + const SimdL>(a: T, b: T) -> T {
+    let or: T = crate::intrinsics::simd::simd_or(a, b);
+    simdl_not(or)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_not<T: Copy + const SimdL>(a: T) -> T {
+    let not: T = simdl_splat(!0);
+    crate::intrinsics::simd::simd_xor(a, not)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_orn<T: Copy + const SimdL>(a: T, b: T) -> T {
+    crate::intrinsics::simd::simd_or(a, simdl_not(b))
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_shl<T: Copy + const SimdL>(a: T, b: T) -> T {
+    let m: T = simdl_splat((size_of::<T::Elem>() * 8 - 1) as i64);
+    let b: T = crate::intrinsics::simd::simd_and(b, m);
+    crate::intrinsics::simd::simd_shl(a, b)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_shr<T: Copy + const SimdL>(a: T, b: T) -> T {
+    let m: T = simdl_splat((size_of::<T::Elem>() * 8 - 1) as i64);
+    let b: T = crate::intrinsics::simd::simd_and(b, m);
+    crate::intrinsics::simd::simd_shr(a, b)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simdl_splat<T: Copy + const SimdL>(a: i64) -> T {
+    T::splat(a)
+}
+
+macro_rules! impl_vv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name(a: $oty) -> $oty {
+            unsafe {
+                let a: $ity = transmute(a);
+                let r: $ity = $op(a);
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_vv;
+
+macro_rules! impl_gv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name(a: $gty) -> $oty {
+            unsafe {
+                let r: $ity = $op(a.into());
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_gv;
+
+macro_rules! impl_sv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[rustc_legacy_const_generics(0)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name<const IMM: i32>() -> $oty {
+            static_assert_simm_bits!(IMM, $ibs);
+            unsafe {
+                let r: $ity = $op(IMM.into());
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_sv;
+
+macro_rules! impl_vvv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name(a: $oty, b: $oty) -> $oty {
+            unsafe {
+                let a: $ity = transmute(a);
+                let b: $ity = transmute(b);
+                let r: $ity = $op(a, b);
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_vvv;
+
+macro_rules! impl_vuv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[rustc_legacy_const_generics(1)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name<const IMM: u32>(a: $oty) -> $oty {
+            static_assert_uimm_bits!(IMM, (size_of::<<$ity as SimdL>::Elem>() * 8).ilog2());
+            unsafe {
+                let a: $ity = transmute(a);
+                let b: $ity = simdl_splat(IMM.into());
+                let r: $ity = $op(a, b);
+                transmute(r)
+            }
+        }
+    };
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[rustc_legacy_const_generics(1)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name<const IMM: u32>(a: $oty) -> $oty {
+            static_assert_uimm_bits!(IMM, $ibs);
+            unsafe {
+                let a: $ity = transmute(a);
+                let b: $ity = simdl_splat(IMM.into());
+                let r: $ity = $op(a, b);
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_vuv;
+
+macro_rules! impl_vug {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[rustc_legacy_const_generics(1)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name<const IMM: u32>(a: $oty) -> $gty {
+            static_assert_uimm_bits!(IMM, $ibs);
+            unsafe {
+                let a: $ity = transmute(a);
+                let r: <$ity as SimdL>::Elem = $op(a, IMM);
+                r as $gty
+            }
+        }
+    };
+}
+
+pub(super) use impl_vug;
+
+macro_rules! impl_vsv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[rustc_legacy_const_generics(1)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name<const IMM: i32>(a: $oty) -> $oty {
+            static_assert_simm_bits!(IMM, $ibs);
+            unsafe {
+                let a: $ity = transmute(a);
+                let b: $ity = simdl_splat(IMM.into());
+                let r: $ity = $op(a, b);
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_vsv;
+
+macro_rules! impl_vvvv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name(a: $oty, b: $oty, c: $oty) -> $oty {
+            unsafe {
+                let a: $ity = transmute(a);
+                let b: $ity = transmute(b);
+                let c: $ity = transmute(c);
+                let r: $ity = $op(a, b, c);
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_vvvv;
+
+macro_rules! impl_vugv {
+    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
+        #[inline(always)]
+        #[target_feature(enable = $ft)]
+        #[rustc_legacy_const_generics(1)]
+        #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+        pub fn $name<const IMM: u32>(a: $oty, b: $gty) -> $oty {
+            static_assert_uimm_bits!(IMM, $ibs);
+            unsafe {
+                let a: $ity = transmute(a);
+                let r: $ity = $op(a, IMM, b as <$ity as SimdL>::Elem);
+                transmute(r)
+            }
+        }
+    };
+}
+
+pub(super) use impl_vugv;
diff --git a/crates/stdarch-gen-loongarch/lasx.spec b/crates/stdarch-gen-loongarch/lasx.spec
index ac4203a03f..9a9b1a143e 100644
--- a/crates/stdarch-gen-loongarch/lasx.spec
+++ b/crates/stdarch-gen-loongarch/lasx.spec
@@ -4,81 +4,97 @@
 // ```
 
 /// lasx_xvsll_b
+impl = portable
 name = lasx_xvsll_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvsll_h
+impl = portable
 name = lasx_xvsll_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvsll_w
+impl = portable
 name = lasx_xvsll_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvsll_d
+impl = portable
 name = lasx_xvsll_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvslli_b
+impl = portable
 name = lasx_xvslli_b
 asm-fmts = xd, xj, ui3
 data-types = V32QI, V32QI, UQI
 
 /// lasx_xvslli_h
+impl = portable
 name = lasx_xvslli_h
 asm-fmts = xd, xj, ui4
 data-types = V16HI, V16HI, UQI
 
 /// lasx_xvslli_w
+impl = portable
 name = lasx_xvslli_w
 asm-fmts = xd, xj, ui5
 data-types = V8SI, V8SI, UQI
 
 /// lasx_xvslli_d
+impl = portable
 name = lasx_xvslli_d
 asm-fmts = xd, xj, ui6
 data-types = V4DI, V4DI, UQI
 
 /// lasx_xvsra_b
+impl = portable
 name = lasx_xvsra_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvsra_h
+impl = portable
 name = lasx_xvsra_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvsra_w
+impl = portable
 name = lasx_xvsra_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvsra_d
+impl = portable
 name = lasx_xvsra_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvsrai_b
+impl = portable
 name = lasx_xvsrai_b
 asm-fmts = xd, xj, ui3
 data-types = V32QI, V32QI, UQI
 
 /// lasx_xvsrai_h
+impl = portable
 name = lasx_xvsrai_h
 asm-fmts = xd, xj, ui4
 data-types = V16HI, V16HI, UQI
 
 /// lasx_xvsrai_w
+impl = portable
 name = lasx_xvsrai_w
 asm-fmts = xd, xj, ui5
 data-types = V8SI, V8SI, UQI
 
 /// lasx_xvsrai_d
+impl = portable
 name = lasx_xvsrai_d
 asm-fmts = xd, xj, ui6
 data-types = V4DI, V4DI, UQI
@@ -124,41 +140,49 @@ asm-fmts = xd, xj, ui6
 data-types = V4DI, V4DI, UQI
 
 /// lasx_xvsrl_b
+impl = portable
 name = lasx_xvsrl_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvsrl_h
+impl = portable
 name = lasx_xvsrl_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvsrl_w
+impl = portable
 name = lasx_xvsrl_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvsrl_d
+impl = portable
 name = lasx_xvsrl_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvsrli_b
+impl = portable
 name = lasx_xvsrli_b
 asm-fmts = xd, xj, ui3
 data-types = V32QI, V32QI, UQI
 
 /// lasx_xvsrli_h
+impl = portable
 name = lasx_xvsrli_h
 asm-fmts = xd, xj, ui4
 data-types = V16HI, V16HI, UQI
 
 /// lasx_xvsrli_w
+impl = portable
 name = lasx_xvsrli_w
 asm-fmts = xd, xj, ui5
 data-types = V8SI, V8SI, UQI
 
 /// lasx_xvsrli_d
+impl = portable
 name = lasx_xvsrli_d
 asm-fmts = xd, xj, ui6
 data-types = V4DI, V4DI, UQI
@@ -324,61 +348,73 @@ asm-fmts = xd, xj, ui6
 data-types = UV4DI, UV4DI, UQI
 
 /// lasx_xvadd_b
+impl = portable
 name = lasx_xvadd_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvadd_h
+impl = portable
 name = lasx_xvadd_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvadd_w
+impl = portable
 name = lasx_xvadd_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvadd_d
+impl = portable
 name = lasx_xvadd_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvaddi_bu
+impl = portable
 name = lasx_xvaddi_bu
 asm-fmts = xd, xj, ui5
 data-types = V32QI, V32QI, UQI
 
 /// lasx_xvaddi_hu
+impl = portable
 name = lasx_xvaddi_hu
 asm-fmts = xd, xj, ui5
 data-types = V16HI, V16HI, UQI
 
 /// lasx_xvaddi_wu
+impl = portable
 name = lasx_xvaddi_wu
 asm-fmts = xd, xj, ui5
 data-types = V8SI, V8SI, UQI
 
 /// lasx_xvaddi_du
+impl = portable
 name = lasx_xvaddi_du
 asm-fmts = xd, xj, ui5
 data-types = V4DI, V4DI, UQI
 
 /// lasx_xvsub_b
+impl = portable
 name = lasx_xvsub_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvsub_h
+impl = portable
 name = lasx_xvsub_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvsub_w
+impl = portable
 name = lasx_xvsub_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvsub_d
+impl = portable
 name = lasx_xvsub_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
@@ -404,361 +440,433 @@ asm-fmts = xd, xj, ui5
 data-types = V4DI, V4DI, UQI
 
 /// lasx_xvmax_b
+impl = portable
 name = lasx_xvmax_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvmax_h
+impl = portable
 name = lasx_xvmax_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvmax_w
+impl = portable
 name = lasx_xvmax_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvmax_d
+impl = portable
 name = lasx_xvmax_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvmaxi_b
+impl = portable
 name = lasx_xvmaxi_b
 asm-fmts = xd, xj, si5
 data-types = V32QI, V32QI, QI
 
 /// lasx_xvmaxi_h
+impl = portable
 name = lasx_xvmaxi_h
 asm-fmts = xd, xj, si5
 data-types = V16HI, V16HI, QI
 
 /// lasx_xvmaxi_w
+impl = portable
 name = lasx_xvmaxi_w
 asm-fmts = xd, xj, si5
 data-types = V8SI, V8SI, QI
 
 /// lasx_xvmaxi_d
+impl = portable
 name = lasx_xvmaxi_d
 asm-fmts = xd, xj, si5
 data-types = V4DI, V4DI, QI
 
 /// lasx_xvmax_bu
+impl = portable
 name = lasx_xvmax_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvmax_hu
+impl = portable
 name = lasx_xvmax_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvmax_wu
+impl = portable
 name = lasx_xvmax_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvmax_du
+impl = portable
 name = lasx_xvmax_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
 
 /// lasx_xvmaxi_bu
+impl = portable
 name = lasx_xvmaxi_bu
 asm-fmts = xd, xj, ui5
 data-types = UV32QI, UV32QI, UQI
 
 /// lasx_xvmaxi_hu
+impl = portable
 name = lasx_xvmaxi_hu
 asm-fmts = xd, xj, ui5
 data-types = UV16HI, UV16HI, UQI
 
 /// lasx_xvmaxi_wu
+impl = portable
 name = lasx_xvmaxi_wu
 asm-fmts = xd, xj, ui5
 data-types = UV8SI, UV8SI, UQI
 
 /// lasx_xvmaxi_du
+impl = portable
 name = lasx_xvmaxi_du
 asm-fmts = xd, xj, ui5
 data-types = UV4DI, UV4DI, UQI
 
 /// lasx_xvmin_b
+impl = portable
 name = lasx_xvmin_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvmin_h
+impl = portable
 name = lasx_xvmin_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvmin_w
+impl = portable
 name = lasx_xvmin_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvmin_d
+impl = portable
 name = lasx_xvmin_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvmini_b
+impl = portable
 name = lasx_xvmini_b
 asm-fmts = xd, xj, si5
 data-types = V32QI, V32QI, QI
 
 /// lasx_xvmini_h
+impl = portable
 name = lasx_xvmini_h
 asm-fmts = xd, xj, si5
 data-types = V16HI, V16HI, QI
 
 /// lasx_xvmini_w
+impl = portable
 name = lasx_xvmini_w
 asm-fmts = xd, xj, si5
 data-types = V8SI, V8SI, QI
 
 /// lasx_xvmini_d
+impl = portable
 name = lasx_xvmini_d
 asm-fmts = xd, xj, si5
 data-types = V4DI, V4DI, QI
 
 /// lasx_xvmin_bu
+impl = portable
 name = lasx_xvmin_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvmin_hu
+impl = portable
 name = lasx_xvmin_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvmin_wu
+impl = portable
 name = lasx_xvmin_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvmin_du
+impl = portable
 name = lasx_xvmin_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
 
 /// lasx_xvmini_bu
+impl = portable
 name = lasx_xvmini_bu
 asm-fmts = xd, xj, ui5
 data-types = UV32QI, UV32QI, UQI
 
 /// lasx_xvmini_hu
+impl = portable
 name = lasx_xvmini_hu
 asm-fmts = xd, xj, ui5
 data-types = UV16HI, UV16HI, UQI
 
 /// lasx_xvmini_wu
+impl = portable
 name = lasx_xvmini_wu
 asm-fmts = xd, xj, ui5
 data-types = UV8SI, UV8SI, UQI
 
 /// lasx_xvmini_du
+impl = portable
 name = lasx_xvmini_du
 asm-fmts = xd, xj, ui5
 data-types = UV4DI, UV4DI, UQI
 
 /// lasx_xvseq_b
+impl = portable
 name = lasx_xvseq_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvseq_h
+impl = portable
 name = lasx_xvseq_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvseq_w
+impl = portable
 name = lasx_xvseq_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvseq_d
+impl = portable
 name = lasx_xvseq_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvseqi_b
+impl = portable
 name = lasx_xvseqi_b
 asm-fmts = xd, xj, si5
 data-types = V32QI, V32QI, QI
 
 /// lasx_xvseqi_h
+impl = portable
 name = lasx_xvseqi_h
 asm-fmts = xd, xj, si5
 data-types = V16HI, V16HI, QI
 
 /// lasx_xvseqi_w
+impl = portable
 name = lasx_xvseqi_w
 asm-fmts = xd, xj, si5
 data-types = V8SI, V8SI, QI
 
 /// lasx_xvseqi_d
+impl = portable
 name = lasx_xvseqi_d
 asm-fmts = xd, xj, si5
 data-types = V4DI, V4DI, QI
 
 /// lasx_xvslt_b
+impl = portable
 name = lasx_xvslt_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvslt_h
+impl = portable
 name = lasx_xvslt_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvslt_w
+impl = portable
 name = lasx_xvslt_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvslt_d
+impl = portable
 name = lasx_xvslt_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvslti_b
+impl = portable
 name = lasx_xvslti_b
 asm-fmts = xd, xj, si5
 data-types = V32QI, V32QI, QI
 
 /// lasx_xvslti_h
+impl = portable
 name = lasx_xvslti_h
 asm-fmts = xd, xj, si5
 data-types = V16HI, V16HI, QI
 
 /// lasx_xvslti_w
+impl = portable
 name = lasx_xvslti_w
 asm-fmts = xd, xj, si5
 data-types = V8SI, V8SI, QI
 
 /// lasx_xvslti_d
+impl = portable
 name = lasx_xvslti_d
 asm-fmts = xd, xj, si5
 data-types = V4DI, V4DI, QI
 
 /// lasx_xvslt_bu
+impl = portable
 name = lasx_xvslt_bu
 asm-fmts = xd, xj, xk
 data-types = V32QI, UV32QI, UV32QI
 
 /// lasx_xvslt_hu
+impl = portable
 name = lasx_xvslt_hu
 asm-fmts = xd, xj, xk
 data-types = V16HI, UV16HI, UV16HI
 
 /// lasx_xvslt_wu
+impl = portable
 name = lasx_xvslt_wu
 asm-fmts = xd, xj, xk
 data-types = V8SI, UV8SI, UV8SI
 
 /// lasx_xvslt_du
+impl = portable
 name = lasx_xvslt_du
 asm-fmts = xd, xj, xk
 data-types = V4DI, UV4DI, UV4DI
 
 /// lasx_xvslti_bu
+impl = portable
 name = lasx_xvslti_bu
 asm-fmts = xd, xj, ui5
 data-types = V32QI, UV32QI, UQI
 
 /// lasx_xvslti_hu
+impl = portable
 name = lasx_xvslti_hu
 asm-fmts = xd, xj, ui5
 data-types = V16HI, UV16HI, UQI
 
 /// lasx_xvslti_wu
+impl = portable
 name = lasx_xvslti_wu
 asm-fmts = xd, xj, ui5
 data-types = V8SI, UV8SI, UQI
 
 /// lasx_xvslti_du
+impl = portable
 name = lasx_xvslti_du
 asm-fmts = xd, xj, ui5
 data-types = V4DI, UV4DI, UQI
 
 /// lasx_xvsle_b
+impl = portable
 name = lasx_xvsle_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvsle_h
+impl = portable
 name = lasx_xvsle_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvsle_w
+impl = portable
 name = lasx_xvsle_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvsle_d
+impl = portable
 name = lasx_xvsle_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvslei_b
+impl = portable
 name = lasx_xvslei_b
 asm-fmts = xd, xj, si5
 data-types = V32QI, V32QI, QI
 
 /// lasx_xvslei_h
+impl = portable
 name = lasx_xvslei_h
 asm-fmts = xd, xj, si5
 data-types = V16HI, V16HI, QI
 
 /// lasx_xvslei_w
+impl = portable
 name = lasx_xvslei_w
 asm-fmts = xd, xj, si5
 data-types = V8SI, V8SI, QI
 
 /// lasx_xvslei_d
+impl = portable
 name = lasx_xvslei_d
 asm-fmts = xd, xj, si5
 data-types = V4DI, V4DI, QI
 
 /// lasx_xvsle_bu
+impl = portable
 name = lasx_xvsle_bu
 asm-fmts = xd, xj, xk
 data-types = V32QI, UV32QI, UV32QI
 
 /// lasx_xvsle_hu
+impl = portable
 name = lasx_xvsle_hu
 asm-fmts = xd, xj, xk
 data-types = V16HI, UV16HI, UV16HI
 
 /// lasx_xvsle_wu
+impl = portable
 name = lasx_xvsle_wu
 asm-fmts = xd, xj, xk
 data-types = V8SI, UV8SI, UV8SI
 
 /// lasx_xvsle_du
+impl = portable
 name = lasx_xvsle_du
 asm-fmts = xd, xj, xk
 data-types = V4DI, UV4DI, UV4DI
 
 /// lasx_xvslei_bu
+impl = portable
 name = lasx_xvslei_bu
 asm-fmts = xd, xj, ui5
 data-types = V32QI, UV32QI, UQI
 
 /// lasx_xvslei_hu
+impl = portable
 name = lasx_xvslei_hu
 asm-fmts = xd, xj, ui5
 data-types = V16HI, UV16HI, UQI
 
 /// lasx_xvslei_wu
+impl = portable
 name = lasx_xvslei_wu
 asm-fmts = xd, xj, ui5
 data-types = V8SI, UV8SI, UQI
 
 /// lasx_xvslei_du
+impl = portable
 name = lasx_xvslei_du
 asm-fmts = xd, xj, ui5
 data-types = V4DI, UV4DI, UQI
@@ -1024,101 +1132,121 @@ asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
 
 /// lasx_xvmul_b
+impl = portable
 name = lasx_xvmul_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvmul_h
+impl = portable
 name = lasx_xvmul_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvmul_w
+impl = portable
 name = lasx_xvmul_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvmul_d
+impl = portable
 name = lasx_xvmul_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvmadd_b
+impl = portable
 name = lasx_xvmadd_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI, V32QI
 
 /// lasx_xvmadd_h
+impl = portable
 name = lasx_xvmadd_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI, V16HI
 
 /// lasx_xvmadd_w
+impl = portable
 name = lasx_xvmadd_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI, V8SI
 
 /// lasx_xvmadd_d
+impl = portable
 name = lasx_xvmadd_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI, V4DI
 
 /// lasx_xvmsub_b
+impl = portable
 name = lasx_xvmsub_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI, V32QI
 
 /// lasx_xvmsub_h
+impl = portable
 name = lasx_xvmsub_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI, V16HI
 
 /// lasx_xvmsub_w
+impl = portable
 name = lasx_xvmsub_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI, V8SI
 
 /// lasx_xvmsub_d
+impl = portable
 name = lasx_xvmsub_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI, V4DI
 
 /// lasx_xvdiv_b
+impl = portable
 name = lasx_xvdiv_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvdiv_h
+impl = portable
 name = lasx_xvdiv_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvdiv_w
+impl = portable
 name = lasx_xvdiv_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvdiv_d
+impl = portable
 name = lasx_xvdiv_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvdiv_bu
+impl = portable
 name = lasx_xvdiv_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvdiv_hu
+impl = portable
 name = lasx_xvdiv_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvdiv_wu
+impl = portable
 name = lasx_xvdiv_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvdiv_du
+impl = portable
 name = lasx_xvdiv_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
@@ -1184,41 +1312,49 @@ asm-fmts = xd, xj, xk
 data-types = V4DI, UV8SI, UV8SI
 
 /// lasx_xvmod_b
+impl = portable
 name = lasx_xvmod_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvmod_h
+impl = portable
 name = lasx_xvmod_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvmod_w
+impl = portable
 name = lasx_xvmod_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvmod_d
+impl = portable
 name = lasx_xvmod_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvmod_bu
+impl = portable
 name = lasx_xvmod_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvmod_hu
+impl = portable
 name = lasx_xvmod_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvmod_wu
+impl = portable
 name = lasx_xvmod_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvmod_du
+impl = portable
 name = lasx_xvmod_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
@@ -1384,6 +1520,7 @@ asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI, V4DI
 
 /// lasx_xvand_v
+impl = portable
 name = lasx_xvand_v
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
@@ -1394,6 +1531,7 @@ asm-fmts = xd, xj, ui8
 data-types = UV32QI, UV32QI, UQI
 
 /// lasx_xvor_v
+impl = portable
 name = lasx_xvor_v
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
@@ -1404,6 +1542,7 @@ asm-fmts = xd, xj, ui8
 data-types = UV32QI, UV32QI, UQI
 
 /// lasx_xvnor_v
+impl = portable
 name = lasx_xvnor_v
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
@@ -1414,6 +1553,7 @@ asm-fmts = xd, xj, ui8
 data-types = UV32QI, UV32QI, UQI
 
 /// lasx_xvxor_v
+impl = portable
 name = lasx_xvxor_v
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
@@ -1449,41 +1589,49 @@ asm-fmts = xd, xj, ui8
 data-types = V8SI, V8SI, USI
 
 /// lasx_xvreplgr2vr_b
+impl = portable
 name = lasx_xvreplgr2vr_b
 asm-fmts = xd, rj
 data-types = V32QI, SI
 
 /// lasx_xvreplgr2vr_h
+impl = portable
 name = lasx_xvreplgr2vr_h
 asm-fmts = xd, rj
 data-types = V16HI, SI
 
 /// lasx_xvreplgr2vr_w
+impl = portable
 name = lasx_xvreplgr2vr_w
 asm-fmts = xd, rj
 data-types = V8SI, SI
 
 /// lasx_xvreplgr2vr_d
+impl = portable
 name = lasx_xvreplgr2vr_d
 asm-fmts = xd, rj
 data-types = V4DI, DI
 
 /// lasx_xvpcnt_b
+impl = portable
 name = lasx_xvpcnt_b
 asm-fmts = xd, xj
 data-types = V32QI, V32QI
 
 /// lasx_xvpcnt_h
+impl = portable
 name = lasx_xvpcnt_h
 asm-fmts = xd, xj
 data-types = V16HI, V16HI
 
 /// lasx_xvpcnt_w
+impl = portable
 name = lasx_xvpcnt_w
 asm-fmts = xd, xj
 data-types = V8SI, V8SI
 
 /// lasx_xvpcnt_d
+impl = portable
 name = lasx_xvpcnt_d
 asm-fmts = xd, xj
 data-types = V4DI, V4DI
@@ -1509,61 +1657,73 @@ asm-fmts = xd, xj
 data-types = V4DI, V4DI
 
 /// lasx_xvclz_b
+impl = portable
 name = lasx_xvclz_b
 asm-fmts = xd, xj
 data-types = V32QI, V32QI
 
 /// lasx_xvclz_h
+impl = portable
 name = lasx_xvclz_h
 asm-fmts = xd, xj
 data-types = V16HI, V16HI
 
 /// lasx_xvclz_w
+impl = portable
 name = lasx_xvclz_w
 asm-fmts = xd, xj
 data-types = V8SI, V8SI
 
 /// lasx_xvclz_d
+impl = portable
 name = lasx_xvclz_d
 asm-fmts = xd, xj
 data-types = V4DI, V4DI
 
 /// lasx_xvfadd_s
+impl = portable
 name = lasx_xvfadd_s
 asm-fmts = xd, xj, xk
 data-types = V8SF, V8SF, V8SF
 
 /// lasx_xvfadd_d
+impl = portable
 name = lasx_xvfadd_d
 asm-fmts = xd, xj, xk
 data-types = V4DF, V4DF, V4DF
 
 /// lasx_xvfsub_s
+impl = portable
 name = lasx_xvfsub_s
 asm-fmts = xd, xj, xk
 data-types = V8SF, V8SF, V8SF
 
 /// lasx_xvfsub_d
+impl = portable
 name = lasx_xvfsub_d
 asm-fmts = xd, xj, xk
 data-types = V4DF, V4DF, V4DF
 
 /// lasx_xvfmul_s
+impl = portable
 name = lasx_xvfmul_s
 asm-fmts = xd, xj, xk
 data-types = V8SF, V8SF, V8SF
 
 /// lasx_xvfmul_d
+impl = portable
 name = lasx_xvfmul_d
 asm-fmts = xd, xj, xk
 data-types = V4DF, V4DF, V4DF
 
 /// lasx_xvfdiv_s
+impl = portable
 name = lasx_xvfdiv_s
 asm-fmts = xd, xj, xk
 data-types = V8SF, V8SF, V8SF
 
 /// lasx_xvfdiv_d
+impl = portable
 name = lasx_xvfdiv_d
 asm-fmts = xd, xj, xk
 data-types = V4DF, V4DF, V4DF
@@ -1629,11 +1789,13 @@ asm-fmts = xd, xj
 data-types = V4DI, V4DF
 
 /// lasx_xvfsqrt_s
+impl = portable
 name = lasx_xvfsqrt_s
 asm-fmts = xd, xj
 data-types = V8SF, V8SF
 
 /// lasx_xvfsqrt_d
+impl = portable
 name = lasx_xvfsqrt_d
 asm-fmts = xd, xj
 data-types = V4DF, V4DF
@@ -1804,26 +1966,31 @@ asm-fmts = xd, xj, ui8
 data-types = V8SI, V8SI, V8SI, USI
 
 /// lasx_xvandn_v
+impl = portable
 name = lasx_xvandn_v
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvneg_b
+impl = portable
 name = lasx_xvneg_b
 asm-fmts = xd, xj
 data-types = V32QI, V32QI
 
 /// lasx_xvneg_h
+impl = portable
 name = lasx_xvneg_h
 asm-fmts = xd, xj
 data-types = V16HI, V16HI
 
 /// lasx_xvneg_w
+impl = portable
 name = lasx_xvneg_w
 asm-fmts = xd, xj
 data-types = V8SI, V8SI
 
 /// lasx_xvneg_d
+impl = portable
 name = lasx_xvneg_d
 asm-fmts = xd, xj
 data-types = V4DI, V4DI
@@ -2144,41 +2311,49 @@ asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvfmadd_s
+impl = portable
 name = lasx_xvfmadd_s
 asm-fmts = xd, xj, xk, xa
 data-types = V8SF, V8SF, V8SF, V8SF
 
 /// lasx_xvfmadd_d
+impl = portable
 name = lasx_xvfmadd_d
 asm-fmts = xd, xj, xk, xa
 data-types = V4DF, V4DF, V4DF, V4DF
 
 /// lasx_xvfmsub_s
+impl = portable
 name = lasx_xvfmsub_s
 asm-fmts = xd, xj, xk, xa
 data-types = V8SF, V8SF, V8SF, V8SF
 
 /// lasx_xvfmsub_d
+impl = portable
 name = lasx_xvfmsub_d
 asm-fmts = xd, xj, xk, xa
 data-types = V4DF, V4DF, V4DF, V4DF
 
 /// lasx_xvfnmadd_s
+impl = portable
 name = lasx_xvfnmadd_s
 asm-fmts = xd, xj, xk, xa
 data-types = V8SF, V8SF, V8SF, V8SF
 
 /// lasx_xvfnmadd_d
+impl = portable
 name = lasx_xvfnmadd_d
 asm-fmts = xd, xj, xk, xa
 data-types = V4DF, V4DF, V4DF, V4DF
 
 /// lasx_xvfnmsub_s
+impl = portable
 name = lasx_xvfnmsub_s
 asm-fmts = xd, xj, xk, xa
 data-types = V8SF, V8SF, V8SF, V8SF
 
 /// lasx_xvfnmsub_d
+impl = portable
 name = lasx_xvfnmsub_d
 asm-fmts = xd, xj, xk, xa
 data-types = V4DF, V4DF, V4DF, V4DF
@@ -2424,6 +2599,7 @@ asm-fmts = xd, xj, xk
 data-types = V8SI, V4DI, V4DI
 
 /// lasx_xvorn_v
+impl = portable
 name = lasx_xvorn_v
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
@@ -2449,11 +2625,13 @@ asm-fmts = xd, xj
 data-types = UV4DI, UV4DI
 
 /// lasx_xvinsgr2vr_w
+impl = portable
 name = lasx_xvinsgr2vr_w
 asm-fmts = xd, rj, ui3
 data-types = V8SI, V8SI, SI, UQI
 
 /// lasx_xvinsgr2vr_d
+impl = portable
 name = lasx_xvinsgr2vr_d
 asm-fmts = xd, rj, ui2
 data-types = V4DI, V4DI, DI, UQI
@@ -2579,21 +2757,25 @@ asm-fmts = xd, rj, si9
 data-types = V4DI, CVPOINTER, SI
 
 /// lasx_xvpickve2gr_w
+impl = portable
 name = lasx_xvpickve2gr_w
 asm-fmts = rd, xj, ui3
 data-types = SI, V8SI, UQI
 
 /// lasx_xvpickve2gr_wu
+impl = portable
 name = lasx_xvpickve2gr_wu
 asm-fmts = rd, xj, ui3
 data-types = USI, V8SI, UQI
 
 /// lasx_xvpickve2gr_d
+impl = portable
 name = lasx_xvpickve2gr_d
 asm-fmts = rd, xj, ui2
 data-types = DI, V4DI, UQI
 
 /// lasx_xvpickve2gr_du
+impl = portable
 name = lasx_xvpickve2gr_du
 asm-fmts = rd, xj, ui2
 data-types = UDI, V4DI, UQI
@@ -3684,21 +3866,25 @@ asm-fmts = xd, xj, ui3
 data-types = V8SF, V8SF, UQI
 
 /// lasx_xvrepli_b
+impl = portable
 name = lasx_xvrepli_b
 asm-fmts = xd, si10
 data-types = V32QI, HI
 
 /// lasx_xvrepli_d
+impl = portable
 name = lasx_xvrepli_d
 asm-fmts = xd, si10
 data-types = V4DI, HI
 
 /// lasx_xvrepli_h
+impl = portable
 name = lasx_xvrepli_h
 asm-fmts = xd, si10
 data-types = V16HI, HI
 
 /// lasx_xvrepli_w
+impl = portable
 name = lasx_xvrepli_w
 asm-fmts = xd, si10
 data-types = V8SI, HI
diff --git a/crates/stdarch-gen-loongarch/lsx.spec b/crates/stdarch-gen-loongarch/lsx.spec
index b5497b6e62..8fd2678899 100644
--- a/crates/stdarch-gen-loongarch/lsx.spec
+++ b/crates/stdarch-gen-loongarch/lsx.spec
@@ -4,81 +4,97 @@
 // ```
 
 /// lsx_vsll_b
+impl = portable
 name = lsx_vsll_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vsll_h
+impl = portable
 name = lsx_vsll_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vsll_w
+impl = portable
 name = lsx_vsll_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vsll_d
+impl = portable
 name = lsx_vsll_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vslli_b
+impl = portable
 name = lsx_vslli_b
 asm-fmts = vd, vj, ui3
 data-types = V16QI, V16QI, UQI
 
 /// lsx_vslli_h
+impl = portable
 name = lsx_vslli_h
 asm-fmts = vd, vj, ui4
 data-types = V8HI, V8HI, UQI
 
 /// lsx_vslli_w
+impl = portable
 name = lsx_vslli_w
 asm-fmts = vd, vj, ui5
 data-types = V4SI, V4SI, UQI
 
 /// lsx_vslli_d
+impl = portable
 name = lsx_vslli_d
 asm-fmts = vd, vj, ui6
 data-types = V2DI, V2DI, UQI
 
 /// lsx_vsra_b
+impl = portable
 name = lsx_vsra_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vsra_h
+impl = portable
 name = lsx_vsra_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vsra_w
+impl = portable
 name = lsx_vsra_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vsra_d
+impl = portable
 name = lsx_vsra_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vsrai_b
+impl = portable
 name = lsx_vsrai_b
 asm-fmts = vd, vj, ui3
 data-types = V16QI, V16QI, UQI
 
 /// lsx_vsrai_h
+impl = portable
 name = lsx_vsrai_h
 asm-fmts = vd, vj, ui4
 data-types = V8HI, V8HI, UQI
 
 /// lsx_vsrai_w
+impl = portable
 name = lsx_vsrai_w
 asm-fmts = vd, vj, ui5
 data-types = V4SI, V4SI, UQI
 
 /// lsx_vsrai_d
+impl = portable
 name = lsx_vsrai_d
 asm-fmts = vd, vj, ui6
 data-types = V2DI, V2DI, UQI
@@ -124,41 +140,49 @@ asm-fmts = vd, vj, ui6
 data-types = V2DI, V2DI, UQI
 
 /// lsx_vsrl_b
+impl = portable
 name = lsx_vsrl_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vsrl_h
+impl = portable
 name = lsx_vsrl_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vsrl_w
+impl = portable
 name = lsx_vsrl_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vsrl_d
+impl = portable
 name = lsx_vsrl_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vsrli_b
+impl = portable
 name = lsx_vsrli_b
 asm-fmts = vd, vj, ui3
 data-types = V16QI, V16QI, UQI
 
 /// lsx_vsrli_h
+impl = portable
 name = lsx_vsrli_h
 asm-fmts = vd, vj, ui4
 data-types = V8HI, V8HI, UQI
 
 /// lsx_vsrli_w
+impl = portable
 name = lsx_vsrli_w
 asm-fmts = vd, vj, ui5
 data-types = V4SI, V4SI, UQI
 
 /// lsx_vsrli_d
+impl = portable
 name = lsx_vsrli_d
 asm-fmts = vd, vj, ui6
 data-types = V2DI, V2DI, UQI
@@ -324,61 +348,73 @@ asm-fmts = vd, vj, ui6
 data-types = UV2DI, UV2DI, UQI
 
 /// lsx_vadd_b
+impl = portable
 name = lsx_vadd_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vadd_h
+impl = portable
 name = lsx_vadd_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vadd_w
+impl = portable
 name = lsx_vadd_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vadd_d
+impl = portable
 name = lsx_vadd_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vaddi_bu
+impl = portable
 name = lsx_vaddi_bu
 asm-fmts = vd, vj, ui5
 data-types = V16QI, V16QI, UQI
 
 /// lsx_vaddi_hu
+impl = portable
 name = lsx_vaddi_hu
 asm-fmts = vd, vj, ui5
 data-types = V8HI, V8HI, UQI
 
 /// lsx_vaddi_wu
+impl = portable
 name = lsx_vaddi_wu
 asm-fmts = vd, vj, ui5
 data-types = V4SI, V4SI, UQI
 
 /// lsx_vaddi_du
+impl = portable
 name = lsx_vaddi_du
 asm-fmts = vd, vj, ui5
 data-types = V2DI, V2DI, UQI
 
 /// lsx_vsub_b
+impl = portable
 name = lsx_vsub_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vsub_h
+impl = portable
 name = lsx_vsub_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vsub_w
+impl = portable
 name = lsx_vsub_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vsub_d
+impl = portable
 name = lsx_vsub_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
@@ -404,361 +440,433 @@ asm-fmts = vd, vj, ui5
 data-types = V2DI, V2DI, UQI
 
 /// lsx_vmax_b
+impl = portable
 name = lsx_vmax_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vmax_h
+impl = portable
 name = lsx_vmax_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vmax_w
+impl = portable
 name = lsx_vmax_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vmax_d
+impl = portable
 name = lsx_vmax_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vmaxi_b
+impl = portable
 name = lsx_vmaxi_b
 asm-fmts = vd, vj, si5
 data-types = V16QI, V16QI, QI
 
 /// lsx_vmaxi_h
+impl = portable
 name = lsx_vmaxi_h
 asm-fmts = vd, vj, si5
 data-types = V8HI, V8HI, QI
 
 /// lsx_vmaxi_w
+impl = portable
 name = lsx_vmaxi_w
 asm-fmts = vd, vj, si5
 data-types = V4SI, V4SI, QI
 
 /// lsx_vmaxi_d
+impl = portable
 name = lsx_vmaxi_d
 asm-fmts = vd, vj, si5
 data-types = V2DI, V2DI, QI
 
 /// lsx_vmax_bu
+impl = portable
 name = lsx_vmax_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vmax_hu
+impl = portable
 name = lsx_vmax_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vmax_wu
+impl = portable
 name = lsx_vmax_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vmax_du
+impl = portable
 name = lsx_vmax_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
 
 /// lsx_vmaxi_bu
+impl = portable
 name = lsx_vmaxi_bu
 asm-fmts = vd, vj, ui5
 data-types = UV16QI, UV16QI, UQI
 
 /// lsx_vmaxi_hu
+impl = portable
 name = lsx_vmaxi_hu
 asm-fmts = vd, vj, ui5
 data-types = UV8HI, UV8HI, UQI
 
 /// lsx_vmaxi_wu
+impl = portable
 name = lsx_vmaxi_wu
 asm-fmts = vd, vj, ui5
 data-types = UV4SI, UV4SI, UQI
 
 /// lsx_vmaxi_du
+impl = portable
 name = lsx_vmaxi_du
 asm-fmts = vd, vj, ui5
 data-types = UV2DI, UV2DI, UQI
 
 /// lsx_vmin_b
+impl = portable
 name = lsx_vmin_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vmin_h
+impl = portable
 name = lsx_vmin_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vmin_w
+impl = portable
 name = lsx_vmin_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vmin_d
+impl = portable
 name = lsx_vmin_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vmini_b
+impl = portable
 name = lsx_vmini_b
 asm-fmts = vd, vj, si5
 data-types = V16QI, V16QI, QI
 
 /// lsx_vmini_h
+impl = portable
 name = lsx_vmini_h
 asm-fmts = vd, vj, si5
 data-types = V8HI, V8HI, QI
 
 /// lsx_vmini_w
+impl = portable
 name = lsx_vmini_w
 asm-fmts = vd, vj, si5
 data-types = V4SI, V4SI, QI
 
 /// lsx_vmini_d
+impl = portable
 name = lsx_vmini_d
 asm-fmts = vd, vj, si5
 data-types = V2DI, V2DI, QI
 
 /// lsx_vmin_bu
+impl = portable
 name = lsx_vmin_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vmin_hu
+impl = portable
 name = lsx_vmin_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vmin_wu
+impl = portable
 name = lsx_vmin_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vmin_du
+impl = portable
 name = lsx_vmin_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
 
 /// lsx_vmini_bu
+impl = portable
 name = lsx_vmini_bu
 asm-fmts = vd, vj, ui5
 data-types = UV16QI, UV16QI, UQI
 
 /// lsx_vmini_hu
+impl = portable
 name = lsx_vmini_hu
 asm-fmts = vd, vj, ui5
 data-types = UV8HI, UV8HI, UQI
 
 /// lsx_vmini_wu
+impl = portable
 name = lsx_vmini_wu
 asm-fmts = vd, vj, ui5
 data-types = UV4SI, UV4SI, UQI
 
 /// lsx_vmini_du
+impl = portable
 name = lsx_vmini_du
 asm-fmts = vd, vj, ui5
 data-types = UV2DI, UV2DI, UQI
 
 /// lsx_vseq_b
+impl = portable
 name = lsx_vseq_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vseq_h
+impl = portable
 name = lsx_vseq_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vseq_w
+impl = portable
 name = lsx_vseq_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vseq_d
+impl = portable
 name = lsx_vseq_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vseqi_b
+impl = portable
 name = lsx_vseqi_b
 asm-fmts = vd, vj, si5
 data-types = V16QI, V16QI, QI
 
 /// lsx_vseqi_h
+impl = portable
 name = lsx_vseqi_h
 asm-fmts = vd, vj, si5
 data-types = V8HI, V8HI, QI
 
 /// lsx_vseqi_w
+impl = portable
 name = lsx_vseqi_w
 asm-fmts = vd, vj, si5
 data-types = V4SI, V4SI, QI
 
 /// lsx_vseqi_d
+impl = portable
 name = lsx_vseqi_d
 asm-fmts = vd, vj, si5
 data-types = V2DI, V2DI, QI
 
 /// lsx_vslti_b
+impl = portable
 name = lsx_vslti_b
 asm-fmts = vd, vj, si5
 data-types = V16QI, V16QI, QI
 
 /// lsx_vslt_b
+impl = portable
 name = lsx_vslt_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vslt_h
+impl = portable
 name = lsx_vslt_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vslt_w
+impl = portable
 name = lsx_vslt_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vslt_d
+impl = portable
 name = lsx_vslt_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vslti_h
+impl = portable
 name = lsx_vslti_h
 asm-fmts = vd, vj, si5
 data-types = V8HI, V8HI, QI
 
 /// lsx_vslti_w
+impl = portable
 name = lsx_vslti_w
 asm-fmts = vd, vj, si5
 data-types = V4SI, V4SI, QI
 
 /// lsx_vslti_d
+impl = portable
 name = lsx_vslti_d
 asm-fmts = vd, vj, si5
 data-types = V2DI, V2DI, QI
 
 /// lsx_vslt_bu
+impl = portable
 name = lsx_vslt_bu
 asm-fmts = vd, vj, vk
 data-types = V16QI, UV16QI, UV16QI
 
 /// lsx_vslt_hu
+impl = portable
 name = lsx_vslt_hu
 asm-fmts = vd, vj, vk
 data-types = V8HI, UV8HI, UV8HI
 
 /// lsx_vslt_wu
+impl = portable
 name = lsx_vslt_wu
 asm-fmts = vd, vj, vk
 data-types = V4SI, UV4SI, UV4SI
 
 /// lsx_vslt_du
+impl = portable
 name = lsx_vslt_du
 asm-fmts = vd, vj, vk
 data-types = V2DI, UV2DI, UV2DI
 
 /// lsx_vslti_bu
+impl = portable
 name = lsx_vslti_bu
 asm-fmts = vd, vj, ui5
 data-types = V16QI, UV16QI, UQI
 
 /// lsx_vslti_hu
+impl = portable
 name = lsx_vslti_hu
 asm-fmts = vd, vj, ui5
 data-types = V8HI, UV8HI, UQI
 
 /// lsx_vslti_wu
+impl = portable
 name = lsx_vslti_wu
 asm-fmts = vd, vj, ui5
 data-types = V4SI, UV4SI, UQI
 
 /// lsx_vslti_du
+impl = portable
 name = lsx_vslti_du
 asm-fmts = vd, vj, ui5
 data-types = V2DI, UV2DI, UQI
 
 /// lsx_vsle_b
+impl = portable
 name = lsx_vsle_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vsle_h
+impl = portable
 name = lsx_vsle_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vsle_w
+impl = portable
 name = lsx_vsle_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vsle_d
+impl = portable
 name = lsx_vsle_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vslei_b
+impl = portable
 name = lsx_vslei_b
 asm-fmts = vd, vj, si5
 data-types = V16QI, V16QI, QI
 
 /// lsx_vslei_h
+impl = portable
 name = lsx_vslei_h
 asm-fmts = vd, vj, si5
 data-types = V8HI, V8HI, QI
 
 /// lsx_vslei_w
+impl = portable
 name = lsx_vslei_w
 asm-fmts = vd, vj, si5
 data-types = V4SI, V4SI, QI
 
 /// lsx_vslei_d
+impl = portable
 name = lsx_vslei_d
 asm-fmts = vd, vj, si5
 data-types = V2DI, V2DI, QI
 
 /// lsx_vsle_bu
+impl = portable
 name = lsx_vsle_bu
 asm-fmts = vd, vj, vk
 data-types = V16QI, UV16QI, UV16QI
 
 /// lsx_vsle_hu
+impl = portable
 name = lsx_vsle_hu
 asm-fmts = vd, vj, vk
 data-types = V8HI, UV8HI, UV8HI
 
 /// lsx_vsle_wu
+impl = portable
 name = lsx_vsle_wu
 asm-fmts = vd, vj, vk
 data-types = V4SI, UV4SI, UV4SI
 
 /// lsx_vsle_du
+impl = portable
 name = lsx_vsle_du
 asm-fmts = vd, vj, vk
 data-types = V2DI, UV2DI, UV2DI
 
 /// lsx_vslei_bu
+impl = portable
 name = lsx_vslei_bu
 asm-fmts = vd, vj, ui5
 data-types = V16QI, UV16QI, UQI
 
 /// lsx_vslei_hu
+impl = portable
 name = lsx_vslei_hu
 asm-fmts = vd, vj, ui5
 data-types = V8HI, UV8HI, UQI
 
 /// lsx_vslei_wu
+impl = portable
 name = lsx_vslei_wu
 asm-fmts = vd, vj, ui5
 data-types = V4SI, UV4SI, UQI
 
 /// lsx_vslei_du
+impl = portable
 name = lsx_vslei_du
 asm-fmts = vd, vj, ui5
 data-types = V2DI, UV2DI, UQI
@@ -1024,101 +1132,121 @@ asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
 
 /// lsx_vmul_b
+impl = portable
 name = lsx_vmul_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vmul_h
+impl = portable
 name = lsx_vmul_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vmul_w
+impl = portable
 name = lsx_vmul_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vmul_d
+impl = portable
 name = lsx_vmul_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vmadd_b
+impl = portable
 name = lsx_vmadd_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI, V16QI
 
 /// lsx_vmadd_h
+impl = portable
 name = lsx_vmadd_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI, V8HI
 
 /// lsx_vmadd_w
+impl = portable
 name = lsx_vmadd_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI, V4SI
 
 /// lsx_vmadd_d
+impl = portable
 name = lsx_vmadd_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI, V2DI
 
 /// lsx_vmsub_b
+impl = portable
 name = lsx_vmsub_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI, V16QI
 
 /// lsx_vmsub_h
+impl = portable
 name = lsx_vmsub_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI, V8HI
 
 /// lsx_vmsub_w
+impl = portable
 name = lsx_vmsub_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI, V4SI
 
 /// lsx_vmsub_d
+impl = portable
 name = lsx_vmsub_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI, V2DI
 
 /// lsx_vdiv_b
+impl = portable
 name = lsx_vdiv_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vdiv_h
+impl = portable
 name = lsx_vdiv_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vdiv_w
+impl = portable
 name = lsx_vdiv_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vdiv_d
+impl = portable
 name = lsx_vdiv_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vdiv_bu
+impl = portable
 name = lsx_vdiv_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vdiv_hu
+impl = portable
 name = lsx_vdiv_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vdiv_wu
+impl = portable
 name = lsx_vdiv_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vdiv_du
+impl = portable
 name = lsx_vdiv_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
@@ -1184,41 +1312,49 @@ asm-fmts = vd, vj, vk
 data-types = V2DI, UV4SI, UV4SI
 
 /// lsx_vmod_b
+impl = portable
 name = lsx_vmod_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vmod_h
+impl = portable
 name = lsx_vmod_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vmod_w
+impl = portable
 name = lsx_vmod_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vmod_d
+impl = portable
 name = lsx_vmod_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vmod_bu
+impl = portable
 name = lsx_vmod_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vmod_hu
+impl = portable
 name = lsx_vmod_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vmod_wu
+impl = portable
 name = lsx_vmod_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vmod_du
+impl = portable
 name = lsx_vmod_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
@@ -1399,6 +1535,7 @@ asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI, V2DI
 
 /// lsx_vand_v
+impl = portable
 name = lsx_vand_v
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
@@ -1409,6 +1546,7 @@ asm-fmts = vd, vj, ui8
 data-types = UV16QI, UV16QI, UQI
 
 /// lsx_vor_v
+impl = portable
 name = lsx_vor_v
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
@@ -1419,6 +1557,7 @@ asm-fmts = vd, vj, ui8
 data-types = UV16QI, UV16QI, UQI
 
 /// lsx_vnor_v
+impl = portable
 name = lsx_vnor_v
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
@@ -1429,6 +1568,7 @@ asm-fmts = vd, vj, ui8
 data-types = UV16QI, UV16QI, UQI
 
 /// lsx_vxor_v
+impl = portable
 name = lsx_vxor_v
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
@@ -1464,41 +1604,49 @@ asm-fmts = vd, vj, ui8
 data-types = V4SI, V4SI, USI
 
 /// lsx_vreplgr2vr_b
+impl = portable
 name = lsx_vreplgr2vr_b
 asm-fmts = vd, rj
 data-types = V16QI, SI
 
 /// lsx_vreplgr2vr_h
+impl = portable
 name = lsx_vreplgr2vr_h
 asm-fmts = vd, rj
 data-types = V8HI, SI
 
 /// lsx_vreplgr2vr_w
+impl = portable
 name = lsx_vreplgr2vr_w
 asm-fmts = vd, rj
 data-types = V4SI, SI
 
 /// lsx_vreplgr2vr_d
+impl = portable
 name = lsx_vreplgr2vr_d
 asm-fmts = vd, rj
 data-types = V2DI, DI
 
 /// lsx_vpcnt_b
+impl = portable
 name = lsx_vpcnt_b
 asm-fmts = vd, vj
 data-types = V16QI, V16QI
 
 /// lsx_vpcnt_h
+impl = portable
 name = lsx_vpcnt_h
 asm-fmts = vd, vj
 data-types = V8HI, V8HI
 
 /// lsx_vpcnt_w
+impl = portable
 name = lsx_vpcnt_w
 asm-fmts = vd, vj
 data-types = V4SI, V4SI
 
 /// lsx_vpcnt_d
+impl = portable
 name = lsx_vpcnt_d
 asm-fmts = vd, vj
 data-types = V2DI, V2DI
@@ -1524,121 +1672,145 @@ asm-fmts = vd, vj
 data-types = V2DI, V2DI
 
 /// lsx_vclz_b
+impl = portable
 name = lsx_vclz_b
 asm-fmts = vd, vj
 data-types = V16QI, V16QI
 
 /// lsx_vclz_h
+impl = portable
 name = lsx_vclz_h
 asm-fmts = vd, vj
 data-types = V8HI, V8HI
 
 /// lsx_vclz_w
+impl = portable
 name = lsx_vclz_w
 asm-fmts = vd, vj
 data-types = V4SI, V4SI
 
 /// lsx_vclz_d
+impl = portable
 name = lsx_vclz_d
 asm-fmts = vd, vj
 data-types = V2DI, V2DI
 
 /// lsx_vpickve2gr_b
+impl = portable
 name = lsx_vpickve2gr_b
 asm-fmts = rd, vj, ui4
 data-types = SI, V16QI, UQI
 
 /// lsx_vpickve2gr_h
+impl = portable
 name = lsx_vpickve2gr_h
 asm-fmts = rd, vj, ui3
 data-types = SI, V8HI, UQI
 
 /// lsx_vpickve2gr_w
+impl = portable
 name = lsx_vpickve2gr_w
 asm-fmts = rd, vj, ui2
 data-types = SI, V4SI, UQI
 
 /// lsx_vpickve2gr_d
+impl = portable
 name = lsx_vpickve2gr_d
 asm-fmts = rd, vj, ui1
 data-types = DI, V2DI, UQI
 
 /// lsx_vpickve2gr_bu
+impl = portable
 name = lsx_vpickve2gr_bu
 asm-fmts = rd, vj, ui4
 data-types = USI, V16QI, UQI
 
 /// lsx_vpickve2gr_hu
+impl = portable
 name = lsx_vpickve2gr_hu
 asm-fmts = rd, vj, ui3
 data-types = USI, V8HI, UQI
 
 /// lsx_vpickve2gr_wu
+impl = portable
 name = lsx_vpickve2gr_wu
 asm-fmts = rd, vj, ui2
 data-types = USI, V4SI, UQI
 
 /// lsx_vpickve2gr_du
+impl = portable
 name = lsx_vpickve2gr_du
 asm-fmts = rd, vj, ui1
 data-types = UDI, V2DI, UQI
 
 /// lsx_vinsgr2vr_b
+impl = portable
 name = lsx_vinsgr2vr_b
 asm-fmts = vd, rj, ui4
 data-types = V16QI, V16QI, SI, UQI
 
 /// lsx_vinsgr2vr_h
+impl = portable
 name = lsx_vinsgr2vr_h
 asm-fmts = vd, rj, ui3
 data-types = V8HI, V8HI, SI, UQI
 
 /// lsx_vinsgr2vr_w
+impl = portable
 name = lsx_vinsgr2vr_w
 asm-fmts = vd, rj, ui2
 data-types = V4SI, V4SI, SI, UQI
 
 /// lsx_vinsgr2vr_d
+impl = portable
 name = lsx_vinsgr2vr_d
 asm-fmts = vd, rj, ui1
 data-types = V2DI, V2DI, DI, UQI
 
 /// lsx_vfadd_s
+impl = portable
 name = lsx_vfadd_s
 asm-fmts = vd, vj, vk
 data-types = V4SF, V4SF, V4SF
 
 /// lsx_vfadd_d
+impl = portable
 name = lsx_vfadd_d
 asm-fmts = vd, vj, vk
 data-types = V2DF, V2DF, V2DF
 
 /// lsx_vfsub_s
+impl = portable
 name = lsx_vfsub_s
 asm-fmts = vd, vj, vk
 data-types = V4SF, V4SF, V4SF
 
 /// lsx_vfsub_d
+impl = portable
 name = lsx_vfsub_d
 asm-fmts = vd, vj, vk
 data-types = V2DF, V2DF, V2DF
 
 /// lsx_vfmul_s
+impl = portable
 name = lsx_vfmul_s
 asm-fmts = vd, vj, vk
 data-types = V4SF, V4SF, V4SF
 
 /// lsx_vfmul_d
+impl = portable
 name = lsx_vfmul_d
 asm-fmts = vd, vj, vk
 data-types = V2DF, V2DF, V2DF
 
 /// lsx_vfdiv_s
+impl = portable
 name = lsx_vfdiv_s
 asm-fmts = vd, vj, vk
 data-types = V4SF, V4SF, V4SF
 
 /// lsx_vfdiv_d
+impl = portable
 name = lsx_vfdiv_d
 asm-fmts = vd, vj, vk
 data-types = V2DF, V2DF, V2DF
@@ -1704,11 +1876,13 @@ asm-fmts = vd, vj
 data-types = V2DI, V2DF
 
 /// lsx_vfsqrt_s
+impl = portable
 name = lsx_vfsqrt_s
 asm-fmts = vd, vj
 data-types = V4SF, V4SF
 
 /// lsx_vfsqrt_d
+impl = portable
 name = lsx_vfsqrt_d
 asm-fmts = vd, vj
 data-types = V2DF, V2DF
@@ -1854,26 +2028,31 @@ asm-fmts = vd, vj
 data-types = V2DF, UV2DI
 
 /// lsx_vandn_v
+impl = portable
 name = lsx_vandn_v
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vneg_b
+impl = portable
 name = lsx_vneg_b
 asm-fmts = vd, vj
 data-types = V16QI, V16QI
 
 /// lsx_vneg_h
+impl = portable
 name = lsx_vneg_h
 asm-fmts = vd, vj
 data-types = V8HI, V8HI
 
 /// lsx_vneg_w
+impl = portable
 name = lsx_vneg_w
 asm-fmts = vd, vj
 data-types = V4SI, V4SI
 
 /// lsx_vneg_d
+impl = portable
 name = lsx_vneg_d
 asm-fmts = vd, vj
 data-types = V2DI, V2DI
@@ -2194,41 +2373,49 @@ asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vfmadd_s
+impl = portable
 name = lsx_vfmadd_s
 asm-fmts = vd, vj, vk, va
 data-types = V4SF, V4SF, V4SF, V4SF
 
 /// lsx_vfmadd_d
+impl = portable
 name = lsx_vfmadd_d
 asm-fmts = vd, vj, vk, va
 data-types = V2DF, V2DF, V2DF, V2DF
 
 /// lsx_vfmsub_s
+impl = portable
 name = lsx_vfmsub_s
 asm-fmts = vd, vj, vk, va
 data-types = V4SF, V4SF, V4SF, V4SF
 
 /// lsx_vfmsub_d
+impl = portable
 name = lsx_vfmsub_d
 asm-fmts = vd, vj, vk, va
 data-types = V2DF, V2DF, V2DF, V2DF
 
 /// lsx_vfnmadd_s
+impl = portable
 name = lsx_vfnmadd_s
 asm-fmts = vd, vj, vk, va
 data-types = V4SF, V4SF, V4SF, V4SF
 
 /// lsx_vfnmadd_d
+impl = portable
 name = lsx_vfnmadd_d
 asm-fmts = vd, vj, vk, va
 data-types = V2DF, V2DF, V2DF, V2DF
 
 /// lsx_vfnmsub_s
+impl = portable
 name = lsx_vfnmsub_s
 asm-fmts = vd, vj, vk, va
 data-types = V4SF, V4SF, V4SF, V4SF
 
 /// lsx_vfnmsub_d
+impl = portable
 name = lsx_vfnmsub_d
 asm-fmts = vd, vj, vk, va
 data-types = V2DF, V2DF, V2DF, V2DF
@@ -3284,6 +3471,7 @@ asm-fmts = vd, vj, vk
 data-types = V4SI, V2DI, V2DI
 
 /// lsx_vorn_v
+impl = portable
 name = lsx_vorn_v
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
@@ -3584,21 +3772,25 @@ asm-fmts = vd, vj, vk
 data-types = V4SI, V4SF, V4SF
 
 /// lsx_vrepli_b
+impl = portable
 name = lsx_vrepli_b
 asm-fmts = vd, si10
 data-types = V16QI, HI
 
 /// lsx_vrepli_d
+impl = portable
 name = lsx_vrepli_d
 asm-fmts = vd, si10
 data-types = V2DI, HI
 
 /// lsx_vrepli_h
+impl = portable
 name = lsx_vrepli_h
 asm-fmts = vd, si10
 data-types = V8HI, HI
 
 /// lsx_vrepli_w
+impl = portable
 name = lsx_vrepli_w
 asm-fmts = vd, si10
 data-types = V4SI, HI
diff --git a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
index b62f7f5f8f..2d5e9817a3 100644
--- a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
+++ b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -1,2 +1,381 @@
 # LSX intrinsics
+lsx_vsll_b
+lsx_vsll_h
+lsx_vsll_w
+lsx_vsll_d
+lsx_vslli_b
+lsx_vslli_h
+lsx_vslli_w
+lsx_vslli_d
+lsx_vsra_b
+lsx_vsra_h
+lsx_vsra_w
+lsx_vsra_d
+lsx_vsrai_b
+lsx_vsrai_h
+lsx_vsrai_w
+lsx_vsrai_d
+lsx_vsrl_b
+lsx_vsrl_h
+lsx_vsrl_w
+lsx_vsrl_d
+lsx_vsrli_b
+lsx_vsrli_h
+lsx_vsrli_w
+lsx_vsrli_d
+lsx_vadd_b
+lsx_vadd_h
+lsx_vadd_w
+lsx_vadd_d
+lsx_vaddi_bu
+lsx_vaddi_hu
+lsx_vaddi_wu
+lsx_vaddi_du
+lsx_vsub_b
+lsx_vsub_h
+lsx_vsub_w
+lsx_vsub_d
+lsx_vmax_b
+lsx_vmax_h
+lsx_vmax_w
+lsx_vmax_d
+lsx_vmaxi_b
+lsx_vmaxi_h
+lsx_vmaxi_w
+lsx_vmaxi_d
+lsx_vmax_bu
+lsx_vmax_hu
+lsx_vmax_wu
+lsx_vmax_du
+lsx_vmaxi_bu
+lsx_vmaxi_hu
+lsx_vmaxi_wu
+lsx_vmaxi_du
+lsx_vmin_b
+lsx_vmin_h
+lsx_vmin_w
+lsx_vmin_d
+lsx_vmini_b
+lsx_vmini_h
+lsx_vmini_w
+lsx_vmini_d
+lsx_vmin_bu
+lsx_vmin_hu
+lsx_vmin_wu
+lsx_vmin_du
+lsx_vmini_bu
+lsx_vmini_hu
+lsx_vmini_wu
+lsx_vmini_du
+lsx_vseq_b
+lsx_vseq_h
+lsx_vseq_w
+lsx_vseq_d
+lsx_vseqi_b
+lsx_vseqi_h
+lsx_vseqi_w
+lsx_vseqi_d
+lsx_vslt_b
+lsx_vslt_h
+lsx_vslt_w
+lsx_vslt_d
+lsx_vslti_b
+lsx_vslti_h
+lsx_vslti_w
+lsx_vslti_d
+lsx_vslt_bu
+lsx_vslt_hu
+lsx_vslt_wu
+lsx_vslt_du
+lsx_vslti_bu
+lsx_vslti_hu
+lsx_vslti_wu
+lsx_vslti_du
+lsx_vsle_b
+lsx_vsle_h
+lsx_vsle_w
+lsx_vsle_d
+lsx_vslei_b
+lsx_vslei_h
+lsx_vslei_w
+lsx_vslei_d
+lsx_vsle_bu
+lsx_vsle_hu
+lsx_vsle_wu
+lsx_vsle_du
+lsx_vslei_bu
+lsx_vslei_hu
+lsx_vslei_wu
+lsx_vslei_du
+lsx_vmul_b
+lsx_vmul_h
+lsx_vmul_w
+lsx_vmul_d
+lsx_vdiv_b
+lsx_vdiv_h
+lsx_vdiv_w
+lsx_vdiv_d
+lsx_vdiv_bu
+lsx_vdiv_hu
+lsx_vdiv_wu
+lsx_vdiv_du
+lsx_vmod_b
+lsx_vmod_h
+lsx_vmod_w
+lsx_vmod_d
+lsx_vmod_bu
+lsx_vmod_hu
+lsx_vmod_wu
+lsx_vmod_du
+lsx_vmadd_b
+lsx_vmadd_h
+lsx_vmadd_w
+lsx_vmadd_d
+lsx_vmsub_b
+lsx_vmsub_h
+lsx_vmsub_w
+lsx_vmsub_d
+lsx_vand_v
+lsx_vor_v
+lsx_vnor_v
+lsx_vxor_v
+lsx_vpcnt_b
+lsx_vpcnt_h
+lsx_vpcnt_w
+lsx_vpcnt_d
+lsx_vclz_b
+lsx_vclz_h
+lsx_vclz_w
+lsx_vclz_d
+lsx_vreplgr2vr_b
+lsx_vreplgr2vr_h
+lsx_vreplgr2vr_w
+lsx_vreplgr2vr_d
+lsx_vpickve2gr_b
+lsx_vpickve2gr_h
+lsx_vpickve2gr_w
+lsx_vpickve2gr_d
+lsx_vpickve2gr_bu
+lsx_vpickve2gr_hu
+lsx_vpickve2gr_wu
+lsx_vpickve2gr_du
+lsx_vinsgr2vr_b
+lsx_vinsgr2vr_h
+lsx_vinsgr2vr_w
+lsx_vinsgr2vr_d
+lsx_vfadd_s
+lsx_vfadd_d
+lsx_vfsub_s
+lsx_vfsub_d
+lsx_vfmul_s
+lsx_vfmul_d
+lsx_vfdiv_s
+lsx_vfdiv_d
+lsx_vfsqrt_s
+lsx_vfsqrt_d
+lsx_vandn_v
+lsx_vneg_b
+lsx_vneg_h
+lsx_vneg_w
+lsx_vneg_d
+lsx_vfmadd_s
+lsx_vfmadd_d
+lsx_vfmsub_s
+lsx_vfmsub_d
+lsx_vfnmadd_s
+lsx_vfnmadd_d
+lsx_vfnmsub_s
+lsx_vfnmsub_d
+lsx_vorn_v
+lsx_vrepli_b
+lsx_vrepli_h
+lsx_vrepli_w
+lsx_vrepli_d
+
 # LASX intrinsics
+lasx_xvsll_b
+lasx_xvsll_h
+lasx_xvsll_w
+lasx_xvsll_d
+lasx_xvslli_b
+lasx_xvslli_h
+lasx_xvslli_w
+lasx_xvslli_d
+lasx_xvsra_b
+lasx_xvsra_h
+lasx_xvsra_w
+lasx_xvsra_d
+lasx_xvsrai_b
+lasx_xvsrai_h
+lasx_xvsrai_w
+lasx_xvsrai_d
+lasx_xvsrl_b
+lasx_xvsrl_h
+lasx_xvsrl_w
+lasx_xvsrl_d
+lasx_xvsrli_b
+lasx_xvsrli_h
+lasx_xvsrli_w
+lasx_xvsrli_d
+lasx_xvadd_b
+lasx_xvadd_h
+lasx_xvadd_w
+lasx_xvadd_d
+lasx_xvaddi_bu
+lasx_xvaddi_hu
+lasx_xvaddi_wu
+lasx_xvaddi_du
+lasx_xvsub_b
+lasx_xvsub_h
+lasx_xvsub_w
+lasx_xvsub_d
+lasx_xvmax_b
+lasx_xvmax_h
+lasx_xvmax_w
+lasx_xvmax_d
+lasx_xvmaxi_b
+lasx_xvmaxi_h
+lasx_xvmaxi_w
+lasx_xvmaxi_d
+lasx_xvmax_bu
+lasx_xvmax_hu
+lasx_xvmax_wu
+lasx_xvmax_du
+lasx_xvmaxi_bu
+lasx_xvmaxi_hu
+lasx_xvmaxi_wu
+lasx_xvmaxi_du
+lasx_xvmin_b
+lasx_xvmin_h
+lasx_xvmin_w
+lasx_xvmin_d
+lasx_xvmini_b
+lasx_xvmini_h
+lasx_xvmini_w
+lasx_xvmini_d
+lasx_xvmin_bu
+lasx_xvmin_hu
+lasx_xvmin_wu
+lasx_xvmin_du
+lasx_xvmini_bu
+lasx_xvmini_hu
+lasx_xvmini_wu
+lasx_xvmini_du
+lasx_xvseq_b
+lasx_xvseq_h
+lasx_xvseq_w
+lasx_xvseq_d
+lasx_xvseqi_b
+lasx_xvseqi_h
+lasx_xvseqi_w
+lasx_xvseqi_d
+lasx_xvslt_b
+lasx_xvslt_h
+lasx_xvslt_w
+lasx_xvslt_d
+lasx_xvslti_b
+lasx_xvslti_h
+lasx_xvslti_w
+lasx_xvslti_d
+lasx_xvslt_bu
+lasx_xvslt_hu
+lasx_xvslt_wu
+lasx_xvslt_du
+lasx_xvslti_bu
+lasx_xvslti_hu
+lasx_xvslti_wu
+lasx_xvslti_du
+lasx_xvsle_b
+lasx_xvsle_h
+lasx_xvsle_w
+lasx_xvsle_d
+lasx_xvslei_b
+lasx_xvslei_h
+lasx_xvslei_w
+lasx_xvslei_d
+lasx_xvsle_bu
+lasx_xvsle_hu
+lasx_xvsle_wu
+lasx_xvsle_du
+lasx_xvslei_bu
+lasx_xvslei_hu
+lasx_xvslei_wu
+lasx_xvslei_du
+lasx_xvmul_b
+lasx_xvmul_h
+lasx_xvmul_w
+lasx_xvmul_d
+lasx_xvdiv_b
+lasx_xvdiv_h
+lasx_xvdiv_w
+lasx_xvdiv_d
+lasx_xvdiv_bu
+lasx_xvdiv_hu
+lasx_xvdiv_wu
+lasx_xvdiv_du
+lasx_xvmod_b
+lasx_xvmod_h
+lasx_xvmod_w
+lasx_xvmod_d
+lasx_xvmod_bu
+lasx_xvmod_hu
+lasx_xvmod_wu
+lasx_xvmod_du
+lasx_xvmadd_b
+lasx_xvmadd_h
+lasx_xvmadd_w
+lasx_xvmadd_d
+lasx_xvmsub_b
+lasx_xvmsub_h
+lasx_xvmsub_w
+lasx_xvmsub_d
+lasx_xvand_v
+lasx_xvor_v
+lasx_xvnor_v
+lasx_xvxor_v
+lasx_xvpcnt_b
+lasx_xvpcnt_h
+lasx_xvpcnt_w
+lasx_xvpcnt_d
+lasx_xvclz_b
+lasx_xvclz_h
+lasx_xvclz_w
+lasx_xvclz_d
+lasx_xvreplgr2vr_b
+lasx_xvreplgr2vr_h
+lasx_xvreplgr2vr_w
+lasx_xvreplgr2vr_d
+lasx_xvpickve2gr_w
+lasx_xvpickve2gr_d
+lasx_xvpickve2gr_wu
+lasx_xvpickve2gr_du
+lasx_xvinsgr2vr_w
+lasx_xvinsgr2vr_d
+lasx_xvfadd_s
+lasx_xvfadd_d
+lasx_xvfsub_s
+lasx_xvfsub_d
+lasx_xvfmul_s
+lasx_xvfmul_d
+lasx_xvfdiv_s
+lasx_xvfdiv_d
+lasx_xvfsqrt_s
+lasx_xvfsqrt_d
+lasx_xvandn_v
+lasx_xvneg_b
+lasx_xvneg_h
+lasx_xvneg_w
+lasx_xvneg_d
+lasx_xvfmadd_s
+lasx_xvfmadd_d
+lasx_xvfmsub_s
+lasx_xvfmsub_d
+lasx_xvfnmadd_s
+lasx_xvfnmadd_d
+lasx_xvfnmsub_s
+lasx_xvfnmsub_d
+lasx_xvorn_v
+lasx_xvrepli_b
+lasx_xvrepli_h
+lasx_xvrepli_w
+lasx_xvrepli_d

From e850a3ba1e9749cf503d70fa862619cb5538daff Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 25 Apr 2026 01:01:21 +0200
Subject: [PATCH 265/326] mark `vstl1_*` functions as unsafe

these functions write to a raw pointer, and so are clearly unsafe to use
---
 .../core_arch/src/aarch64/neon/generated.rs   | 56 +++++++++++--------
 .../spec/neon/aarch64.spec.yml                |  8 ++-
 crates/stdarch-gen-arm/src/intrinsic.rs       |  5 ++
 3 files changed, 45 insertions(+), 24 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index c9ce7a69a6..6958fee50a 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -25421,107 +25421,119 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
+pub unsafe fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
     static_assert!(LANE == 0);
-    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+    vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
+pub unsafe fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+    vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
+pub unsafe fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
     static_assert!(LANE == 0);
-    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+    vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
+pub unsafe fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+    vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
+pub unsafe fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
     static_assert!(LANE == 0);
-    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+    vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
+pub unsafe fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+    vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
+pub unsafe fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
     static_assert!(LANE == 0);
     let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
-    unsafe {
-        let lane: i64 = simd_extract!(val, LANE as u32);
-        (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
-    }
+    let lane: i64 = simd_extract!(val, LANE as u32);
+    (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 #[cfg(target_has_atomic = "64")]
-pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
+pub unsafe fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
     let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
-    unsafe {
-        let lane: i64 = simd_extract!(val, LANE as u32);
-        (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
-    }
+    let lane: i64 = simd_extract!(val, LANE as u32);
+    (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a769d35264..04a78f1868 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -4459,7 +4459,9 @@ intrinsics:
     doc: "Store-Release a single-element structure from one lane of one register."
     arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
     static_defs: ["const LANE: i32"]
-    safety: safe
+    safety:
+      unsafe:
+        - pointer_write: ptr
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
@@ -4488,7 +4490,9 @@ intrinsics:
     doc: "Store-Release a single-element structure from one lane of one register."
     arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
     static_defs: ["const LANE: i32"]
-    safety: safe
+    safety:
+      unsafe:
+        - pointer_write: ptr
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index 5d38d45ca6..aadff82928 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -806,6 +806,7 @@ pub enum UnsafetyComment {
     NonTemporal,
     Neon,
     NoProvenance(String),
+    PointerWrite(String),
 }
 
 #[derive(Debug, Clone, Default, Serialize, Deserialize)]
@@ -874,6 +875,10 @@ impl fmt::Display for UnsafetyComment {
                 `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane \
                 before  using it."
             ),
+            Self::PointerWrite(arg) => write!(
+                f,
+                "The pointer in `{arg}` must satisfy the requirements of [`core::ptr::write`]."
+            ),
             Self::UnpredictableOnFault => write!(
                 f,
                 "Result lanes corresponding to inactive FFR lanes (either before or as a result \

From b5ae0dc88cd8f129a4e95012afc6d103be3ed079 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Tue, 28 Apr 2026 23:57:40 +0800
Subject: [PATCH 266/326] loongarch: Refactor portable SIMD helper naming and
 intrinsic paths

Rename `SimdL` to `SimdExt`, `impl_simdl!` to `impl_simd_ext!`,
and the helper functions in `loongarch64/simd.rs` from `simdl_*`
to `simd_*`.

Also qualify intrinsic and helper calls explicitly with aliases:
- `is::` for `crate::intrinsics::simd`
- `cs::` for `crate::core_arch::simd`
- `ls::` for local LoongArch SIMD helpers
---
 .../src/loongarch64/lasx/portable.rs          | 378 ++++++++---------
 .../core_arch/src/loongarch64/lsx/portable.rs | 390 +++++++++---------
 crates/core_arch/src/loongarch64/simd.rs      | 139 ++++---
 3 files changed, 453 insertions(+), 454 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/portable.rs b/crates/core_arch/src/loongarch64/lasx/portable.rs
index 0021d7605f..f2a7254d79 100644
--- a/crates/core_arch/src/loongarch64/lasx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -1,201 +1,201 @@
 //! LoongArch64 LASX intrinsics - intrinsics::simd implementation
 
-use super::super::{simd::*, *};
-use crate::core_arch::simd::*;
-use crate::intrinsics::simd::*;
+use super::super::{simd as ls, simd::*, *};
+use crate::core_arch::simd::{self as cs, *};
+use crate::intrinsics::simd as is;
 use crate::mem::transmute;
 
-impl_vv!("lasx", lasx_xvpcnt_b, simd_ctpop, m256i, i8x32);
-impl_vv!("lasx", lasx_xvpcnt_h, simd_ctpop, m256i, i16x16);
-impl_vv!("lasx", lasx_xvpcnt_w, simd_ctpop, m256i, i32x8);
-impl_vv!("lasx", lasx_xvpcnt_d, simd_ctpop, m256i, i64x4);
-impl_vv!("lasx", lasx_xvclz_b, simd_ctlz, m256i, i8x32);
-impl_vv!("lasx", lasx_xvclz_h, simd_ctlz, m256i, i16x16);
-impl_vv!("lasx", lasx_xvclz_w, simd_ctlz, m256i, i32x8);
-impl_vv!("lasx", lasx_xvclz_d, simd_ctlz, m256i, i64x4);
-impl_vv!("lasx", lasx_xvneg_b, simd_neg, m256i, i8x32);
-impl_vv!("lasx", lasx_xvneg_h, simd_neg, m256i, i16x16);
-impl_vv!("lasx", lasx_xvneg_w, simd_neg, m256i, i32x8);
-impl_vv!("lasx", lasx_xvneg_d, simd_neg, m256i, i64x4);
-impl_vv!("lasx", lasx_xvfsqrt_s, simd_fsqrt, m256, f32x8);
-impl_vv!("lasx", lasx_xvfsqrt_d, simd_fsqrt, m256d, f64x4);
+impl_vv!("lasx", lasx_xvpcnt_b, is::simd_ctpop, m256i, i8x32);
+impl_vv!("lasx", lasx_xvpcnt_h, is::simd_ctpop, m256i, i16x16);
+impl_vv!("lasx", lasx_xvpcnt_w, is::simd_ctpop, m256i, i32x8);
+impl_vv!("lasx", lasx_xvpcnt_d, is::simd_ctpop, m256i, i64x4);
+impl_vv!("lasx", lasx_xvclz_b, is::simd_ctlz, m256i, i8x32);
+impl_vv!("lasx", lasx_xvclz_h, is::simd_ctlz, m256i, i16x16);
+impl_vv!("lasx", lasx_xvclz_w, is::simd_ctlz, m256i, i32x8);
+impl_vv!("lasx", lasx_xvclz_d, is::simd_ctlz, m256i, i64x4);
+impl_vv!("lasx", lasx_xvneg_b, is::simd_neg, m256i, i8x32);
+impl_vv!("lasx", lasx_xvneg_h, is::simd_neg, m256i, i16x16);
+impl_vv!("lasx", lasx_xvneg_w, is::simd_neg, m256i, i32x8);
+impl_vv!("lasx", lasx_xvneg_d, is::simd_neg, m256i, i64x4);
+impl_vv!("lasx", lasx_xvfsqrt_s, is::simd_fsqrt, m256, f32x8);
+impl_vv!("lasx", lasx_xvfsqrt_d, is::simd_fsqrt, m256d, f64x4);
 
-impl_gv!("lasx", lasx_xvreplgr2vr_b, simdl_splat, m256i, i8x32, i32);
-impl_gv!("lasx", lasx_xvreplgr2vr_h, simdl_splat, m256i, i16x16, i32);
-impl_gv!("lasx", lasx_xvreplgr2vr_w, simdl_splat, m256i, i32x8, i32);
-impl_gv!("lasx", lasx_xvreplgr2vr_d, simdl_splat, m256i, i64x4, i64);
+impl_gv!("lasx", lasx_xvreplgr2vr_b, ls::simd_splat, m256i, i8x32, i32);
+impl_gv!("lasx", lasx_xvreplgr2vr_h, ls::simd_splat, m256i, i16x16, i32);
+impl_gv!("lasx", lasx_xvreplgr2vr_w, ls::simd_splat, m256i, i32x8, i32);
+impl_gv!("lasx", lasx_xvreplgr2vr_d, ls::simd_splat, m256i, i64x4, i64);
 
-impl_sv!("lasx", lasx_xvrepli_b, simdl_splat, m256i, i8x32, 10);
-impl_sv!("lasx", lasx_xvrepli_h, simdl_splat, m256i, i16x16, 10);
-impl_sv!("lasx", lasx_xvrepli_w, simdl_splat, m256i, i32x8, 10);
-impl_sv!("lasx", lasx_xvrepli_d, simdl_splat, m256i, i64x4, 10);
+impl_sv!("lasx", lasx_xvrepli_b, ls::simd_splat, m256i, i8x32, 10);
+impl_sv!("lasx", lasx_xvrepli_h, ls::simd_splat, m256i, i16x16, 10);
+impl_sv!("lasx", lasx_xvrepli_w, ls::simd_splat, m256i, i32x8, 10);
+impl_sv!("lasx", lasx_xvrepli_d, ls::simd_splat, m256i, i64x4, 10);
 
-impl_vvv!("lasx", lasx_xvadd_b, simd_add, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvadd_h, simd_add, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvadd_w, simd_add, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvadd_d, simd_add, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvsub_b, simd_sub, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvsub_h, simd_sub, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvsub_w, simd_sub, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvsub_d, simd_sub, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvmax_b, simd_imax, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvmax_h, simd_imax, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvmax_w, simd_imax, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvmax_d, simd_imax, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvmax_bu, simd_imax, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvmax_hu, simd_imax, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvmax_wu, simd_imax, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvmax_du, simd_imax, m256i, u64x4);
-impl_vvv!("lasx", lasx_xvmin_b, simd_imin, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvmin_h, simd_imin, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvmin_w, simd_imin, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvmin_d, simd_imin, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvmin_bu, simd_imin, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvmin_hu, simd_imin, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvmin_wu, simd_imin, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvmin_du, simd_imin, m256i, u64x4);
-impl_vvv!("lasx", lasx_xvseq_b, simd_eq, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvseq_h, simd_eq, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvseq_w, simd_eq, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvseq_d, simd_eq, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvslt_b, simd_lt, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvslt_h, simd_lt, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvslt_w, simd_lt, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvslt_d, simd_lt, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvslt_bu, simd_lt, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvslt_hu, simd_lt, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvslt_wu, simd_lt, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvslt_du, simd_lt, m256i, u64x4);
-impl_vvv!("lasx", lasx_xvsle_b, simd_le, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvsle_h, simd_le, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvsle_w, simd_le, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvsle_d, simd_le, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvsle_bu, simd_le, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvsle_hu, simd_le, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvsle_wu, simd_le, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvsle_du, simd_le, m256i, u64x4);
-impl_vvv!("lasx", lasx_xvmul_b, simd_mul, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvmul_h, simd_mul, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvmul_w, simd_mul, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvmul_d, simd_mul, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvdiv_b, simd_div, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvdiv_h, simd_div, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvdiv_w, simd_div, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvdiv_d, simd_div, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvdiv_bu, simd_div, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvdiv_hu, simd_div, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvdiv_wu, simd_div, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvdiv_du, simd_div, m256i, u64x4);
-impl_vvv!("lasx", lasx_xvmod_b, simd_rem, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvmod_h, simd_rem, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvmod_w, simd_rem, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvmod_d, simd_rem, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvmod_bu, simd_rem, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvmod_hu, simd_rem, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvmod_wu, simd_rem, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvmod_du, simd_rem, m256i, u64x4);
-impl_vvv!("lasx", lasx_xvand_v, simd_and, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvandn_v, simdl_andn, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvor_v, simd_or, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvorn_v, simdl_orn, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvnor_v, simdl_nor, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvxor_v, simd_xor, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvfadd_s, simd_add, m256, f32x8);
-impl_vvv!("lasx", lasx_xvfadd_d, simd_add, m256d, f64x4);
-impl_vvv!("lasx", lasx_xvfsub_s, simd_sub, m256, f32x8);
-impl_vvv!("lasx", lasx_xvfsub_d, simd_sub, m256d, f64x4);
-impl_vvv!("lasx", lasx_xvfmul_s, simd_mul, m256, f32x8);
-impl_vvv!("lasx", lasx_xvfmul_d, simd_mul, m256d, f64x4);
-impl_vvv!("lasx", lasx_xvfdiv_s, simd_div, m256, f32x8);
-impl_vvv!("lasx", lasx_xvfdiv_d, simd_div, m256d, f64x4);
-impl_vvv!("lasx", lasx_xvsll_b, simdl_shl, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvsll_h, simdl_shl, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvsll_w, simdl_shl, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvsll_d, simdl_shl, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvsra_b, simdl_shr, m256i, i8x32);
-impl_vvv!("lasx", lasx_xvsra_h, simdl_shr, m256i, i16x16);
-impl_vvv!("lasx", lasx_xvsra_w, simdl_shr, m256i, i32x8);
-impl_vvv!("lasx", lasx_xvsra_d, simdl_shr, m256i, i64x4);
-impl_vvv!("lasx", lasx_xvsrl_b, simdl_shr, m256i, u8x32);
-impl_vvv!("lasx", lasx_xvsrl_h, simdl_shr, m256i, u16x16);
-impl_vvv!("lasx", lasx_xvsrl_w, simdl_shr, m256i, u32x8);
-impl_vvv!("lasx", lasx_xvsrl_d, simdl_shr, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvadd_b, is::simd_add, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvadd_h, is::simd_add, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvadd_w, is::simd_add, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvadd_d, is::simd_add, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsub_b, is::simd_sub, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsub_h, is::simd_sub, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsub_w, is::simd_sub, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsub_d, is::simd_sub, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmax_b, cs::simd_imax, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmax_h, cs::simd_imax, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmax_w, cs::simd_imax, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmax_d, cs::simd_imax, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmax_bu, cs::simd_imax, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvmax_hu, cs::simd_imax, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvmax_wu, cs::simd_imax, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvmax_du, cs::simd_imax, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvmin_b, cs::simd_imin, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmin_h, cs::simd_imin, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmin_w, cs::simd_imin, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmin_d, cs::simd_imin, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmin_bu, cs::simd_imin, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvmin_hu, cs::simd_imin, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvmin_wu, cs::simd_imin, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvmin_du, cs::simd_imin, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvseq_b, is::simd_eq, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvseq_h, is::simd_eq, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvseq_w, is::simd_eq, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvseq_d, is::simd_eq, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvslt_b, is::simd_lt, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvslt_h, is::simd_lt, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvslt_w, is::simd_lt, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvslt_d, is::simd_lt, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvslt_bu, is::simd_lt, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvslt_hu, is::simd_lt, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvslt_wu, is::simd_lt, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvslt_du, is::simd_lt, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvsle_b, is::simd_le, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsle_h, is::simd_le, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsle_w, is::simd_le, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsle_d, is::simd_le, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsle_bu, is::simd_le, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvsle_hu, is::simd_le, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvsle_wu, is::simd_le, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvsle_du, is::simd_le, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvmul_b, is::simd_mul, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmul_h, is::simd_mul, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmul_w, is::simd_mul, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmul_d, is::simd_mul, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvdiv_b, is::simd_div, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvdiv_h, is::simd_div, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvdiv_w, is::simd_div, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvdiv_d, is::simd_div, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvdiv_bu, is::simd_div, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvdiv_hu, is::simd_div, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvdiv_wu, is::simd_div, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvdiv_du, is::simd_div, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvmod_b, is::simd_rem, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvmod_h, is::simd_rem, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvmod_w, is::simd_rem, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvmod_d, is::simd_rem, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvmod_bu, is::simd_rem, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvmod_hu, is::simd_rem, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvmod_wu, is::simd_rem, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvmod_du, is::simd_rem, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvand_v, is::simd_and, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvandn_v, ls::simd_andn, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvor_v, is::simd_or, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvorn_v, ls::simd_orn, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvnor_v, ls::simd_nor, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvxor_v, is::simd_xor, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvfadd_s, is::simd_add, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfadd_d, is::simd_add, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvfsub_s, is::simd_sub, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfsub_d, is::simd_sub, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvfmul_s, is::simd_mul, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfmul_d, is::simd_mul, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvfdiv_s, is::simd_div, m256, f32x8);
+impl_vvv!("lasx", lasx_xvfdiv_d, is::simd_div, m256d, f64x4);
+impl_vvv!("lasx", lasx_xvsll_b, ls::simd_shl, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsll_h, ls::simd_shl, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsll_w, ls::simd_shl, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsll_d, ls::simd_shl, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsra_b, ls::simd_shr, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsra_h, ls::simd_shr, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsra_w, ls::simd_shr, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsra_d, ls::simd_shr, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsrl_b, ls::simd_shr, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvsrl_h, ls::simd_shr, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvsrl_w, ls::simd_shr, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvsrl_d, ls::simd_shr, m256i, u64x4);
 
-impl_vuv!("lasx", lasx_xvslli_b, simd_shl, m256i, i8x32);
-impl_vuv!("lasx", lasx_xvslli_h, simd_shl, m256i, i16x16);
-impl_vuv!("lasx", lasx_xvslli_w, simd_shl, m256i, i32x8);
-impl_vuv!("lasx", lasx_xvslli_d, simd_shl, m256i, i64x4);
-impl_vuv!("lasx", lasx_xvsrai_b, simd_shr, m256i, i8x32);
-impl_vuv!("lasx", lasx_xvsrai_h, simd_shr, m256i, i16x16);
-impl_vuv!("lasx", lasx_xvsrai_w, simd_shr, m256i, i32x8);
-impl_vuv!("lasx", lasx_xvsrai_d, simd_shr, m256i, i64x4);
-impl_vuv!("lasx", lasx_xvsrli_b, simd_shr, m256i, u8x32);
-impl_vuv!("lasx", lasx_xvsrli_h, simd_shr, m256i, u16x16);
-impl_vuv!("lasx", lasx_xvsrli_w, simd_shr, m256i, u32x8);
-impl_vuv!("lasx", lasx_xvsrli_d, simd_shr, m256i, u64x4);
-impl_vuv!("lasx", lasx_xvaddi_bu, simd_add, m256i, u8x32, 5);
-impl_vuv!("lasx", lasx_xvaddi_hu, simd_add, m256i, u16x16, 5);
-impl_vuv!("lasx", lasx_xvaddi_wu, simd_add, m256i, u32x8, 5);
-impl_vuv!("lasx", lasx_xvaddi_du, simd_add, m256i, u64x4, 5);
-impl_vuv!("lasx", lasx_xvslti_bu, simd_lt, m256i, u8x32, 5);
-impl_vuv!("lasx", lasx_xvslti_hu, simd_lt, m256i, u16x16, 5);
-impl_vuv!("lasx", lasx_xvslti_wu, simd_lt, m256i, u32x8, 5);
-impl_vuv!("lasx", lasx_xvslti_du, simd_lt, m256i, u64x4, 5);
-impl_vuv!("lasx", lasx_xvslei_bu, simd_le, m256i, u8x32, 5);
-impl_vuv!("lasx", lasx_xvslei_hu, simd_le, m256i, u16x16, 5);
-impl_vuv!("lasx", lasx_xvslei_wu, simd_le, m256i, u32x8, 5);
-impl_vuv!("lasx", lasx_xvslei_du, simd_le, m256i, u64x4, 5);
-impl_vuv!("lasx", lasx_xvmaxi_bu, simd_imax, m256i, u8x32, 5);
-impl_vuv!("lasx", lasx_xvmaxi_hu, simd_imax, m256i, u16x16, 5);
-impl_vuv!("lasx", lasx_xvmaxi_wu, simd_imax, m256i, u32x8, 5);
-impl_vuv!("lasx", lasx_xvmaxi_du, simd_imax, m256i, u64x4, 5);
-impl_vuv!("lasx", lasx_xvmini_bu, simd_imin, m256i, u8x32, 5);
-impl_vuv!("lasx", lasx_xvmini_hu, simd_imin, m256i, u16x16, 5);
-impl_vuv!("lasx", lasx_xvmini_wu, simd_imin, m256i, u32x8, 5);
-impl_vuv!("lasx", lasx_xvmini_du, simd_imin, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvslli_b, is::simd_shl, m256i, i8x32);
+impl_vuv!("lasx", lasx_xvslli_h, is::simd_shl, m256i, i16x16);
+impl_vuv!("lasx", lasx_xvslli_w, is::simd_shl, m256i, i32x8);
+impl_vuv!("lasx", lasx_xvslli_d, is::simd_shl, m256i, i64x4);
+impl_vuv!("lasx", lasx_xvsrai_b, is::simd_shr, m256i, i8x32);
+impl_vuv!("lasx", lasx_xvsrai_h, is::simd_shr, m256i, i16x16);
+impl_vuv!("lasx", lasx_xvsrai_w, is::simd_shr, m256i, i32x8);
+impl_vuv!("lasx", lasx_xvsrai_d, is::simd_shr, m256i, i64x4);
+impl_vuv!("lasx", lasx_xvsrli_b, is::simd_shr, m256i, u8x32);
+impl_vuv!("lasx", lasx_xvsrli_h, is::simd_shr, m256i, u16x16);
+impl_vuv!("lasx", lasx_xvsrli_w, is::simd_shr, m256i, u32x8);
+impl_vuv!("lasx", lasx_xvsrli_d, is::simd_shr, m256i, u64x4);
+impl_vuv!("lasx", lasx_xvaddi_bu, is::simd_add, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvaddi_hu, is::simd_add, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvaddi_wu, is::simd_add, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvaddi_du, is::simd_add, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvslti_bu, is::simd_lt, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvslti_hu, is::simd_lt, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvslti_wu, is::simd_lt, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvslti_du, is::simd_lt, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvslei_bu, is::simd_le, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvslei_hu, is::simd_le, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvslei_wu, is::simd_le, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvslei_du, is::simd_le, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvmaxi_bu, cs::simd_imax, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvmaxi_hu, cs::simd_imax, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvmaxi_wu, cs::simd_imax, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvmaxi_du, cs::simd_imax, m256i, u64x4, 5);
+impl_vuv!("lasx", lasx_xvmini_bu, cs::simd_imin, m256i, u8x32, 5);
+impl_vuv!("lasx", lasx_xvmini_hu, cs::simd_imin, m256i, u16x16, 5);
+impl_vuv!("lasx", lasx_xvmini_wu, cs::simd_imin, m256i, u32x8, 5);
+impl_vuv!("lasx", lasx_xvmini_du, cs::simd_imin, m256i, u64x4, 5);
 
-impl_vug!("lasx", lasx_xvpickve2gr_w, simd_extract, m256i, i32x8, i32, 3);
-impl_vug!("lasx", lasx_xvpickve2gr_d, simd_extract, m256i, i64x4, i64, 2);
-impl_vug!("lasx", lasx_xvpickve2gr_wu, simd_extract, m256i, u32x8, u32, 3);
-impl_vug!("lasx", lasx_xvpickve2gr_du, simd_extract, m256i, u64x4, u64, 2);
+impl_vug!("lasx", lasx_xvpickve2gr_w, is::simd_extract, m256i, i32x8, i32, 3);
+impl_vug!("lasx", lasx_xvpickve2gr_d, is::simd_extract, m256i, i64x4, i64, 2);
+impl_vug!("lasx", lasx_xvpickve2gr_wu, is::simd_extract, m256i, u32x8, u32, 3);
+impl_vug!("lasx", lasx_xvpickve2gr_du, is::simd_extract, m256i, u64x4, u64, 2);
 
-impl_vsv!("lasx", lasx_xvseqi_b, simd_eq, m256i, i8x32, 5);
-impl_vsv!("lasx", lasx_xvseqi_h, simd_eq, m256i, i16x16, 5);
-impl_vsv!("lasx", lasx_xvseqi_w, simd_eq, m256i, i32x8, 5);
-impl_vsv!("lasx", lasx_xvseqi_d, simd_eq, m256i, i64x4, 5);
-impl_vsv!("lasx", lasx_xvslti_b, simd_lt, m256i, i8x32, 5);
-impl_vsv!("lasx", lasx_xvslti_h, simd_lt, m256i, i16x16, 5);
-impl_vsv!("lasx", lasx_xvslti_w, simd_lt, m256i, i32x8, 5);
-impl_vsv!("lasx", lasx_xvslti_d, simd_lt, m256i, i64x4, 5);
-impl_vsv!("lasx", lasx_xvslei_b, simd_le, m256i, i8x32, 5);
-impl_vsv!("lasx", lasx_xvslei_h, simd_le, m256i, i16x16, 5);
-impl_vsv!("lasx", lasx_xvslei_w, simd_le, m256i, i32x8, 5);
-impl_vsv!("lasx", lasx_xvslei_d, simd_le, m256i, i64x4, 5);
-impl_vsv!("lasx", lasx_xvmaxi_b, simd_imax, m256i, i8x32, 5);
-impl_vsv!("lasx", lasx_xvmaxi_h, simd_imax, m256i, i16x16, 5);
-impl_vsv!("lasx", lasx_xvmaxi_w, simd_imax, m256i, i32x8, 5);
-impl_vsv!("lasx", lasx_xvmaxi_d, simd_imax, m256i, i64x4, 5);
-impl_vsv!("lasx", lasx_xvmini_b, simd_imin, m256i, i8x32, 5);
-impl_vsv!("lasx", lasx_xvmini_h, simd_imin, m256i, i16x16, 5);
-impl_vsv!("lasx", lasx_xvmini_w, simd_imin, m256i, i32x8, 5);
-impl_vsv!("lasx", lasx_xvmini_d, simd_imin, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvseqi_b, is::simd_eq, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvseqi_h, is::simd_eq, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvseqi_w, is::simd_eq, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvseqi_d, is::simd_eq, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvslti_b, is::simd_lt, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvslti_h, is::simd_lt, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvslti_w, is::simd_lt, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvslti_d, is::simd_lt, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvslei_b, is::simd_le, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvslei_h, is::simd_le, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvslei_w, is::simd_le, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvslei_d, is::simd_le, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvmaxi_b, cs::simd_imax, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvmaxi_h, cs::simd_imax, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvmaxi_w, cs::simd_imax, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvmaxi_d, cs::simd_imax, m256i, i64x4, 5);
+impl_vsv!("lasx", lasx_xvmini_b, cs::simd_imin, m256i, i8x32, 5);
+impl_vsv!("lasx", lasx_xvmini_h, cs::simd_imin, m256i, i16x16, 5);
+impl_vsv!("lasx", lasx_xvmini_w, cs::simd_imin, m256i, i32x8, 5);
+impl_vsv!("lasx", lasx_xvmini_d, cs::simd_imin, m256i, i64x4, 5);
 
-impl_vvvv!("lasx", lasx_xvmadd_b, simdl_madd, m256i, i8x32);
-impl_vvvv!("lasx", lasx_xvmadd_h, simdl_madd, m256i, i16x16);
-impl_vvvv!("lasx", lasx_xvmadd_w, simdl_madd, m256i, i32x8);
-impl_vvvv!("lasx", lasx_xvmadd_d, simdl_madd, m256i, i64x4);
-impl_vvvv!("lasx", lasx_xvmsub_b, simdl_msub, m256i, i8x32);
-impl_vvvv!("lasx", lasx_xvmsub_h, simdl_msub, m256i, i16x16);
-impl_vvvv!("lasx", lasx_xvmsub_w, simdl_msub, m256i, i32x8);
-impl_vvvv!("lasx", lasx_xvmsub_d, simdl_msub, m256i, i64x4);
-impl_vvvv!("lasx", lasx_xvfmadd_s, simd_fma, m256, f32x8);
-impl_vvvv!("lasx", lasx_xvfmadd_d, simd_fma, m256d, f64x4);
-impl_vvvv!("lasx", lasx_xvfmsub_s, simdl_fms, m256, f32x8);
-impl_vvvv!("lasx", lasx_xvfmsub_d, simdl_fms, m256d, f64x4);
-impl_vvvv!("lasx", lasx_xvfnmadd_s, simdl_nfma, m256, f32x8);
-impl_vvvv!("lasx", lasx_xvfnmadd_d, simdl_nfma, m256d, f64x4);
-impl_vvvv!("lasx", lasx_xvfnmsub_s, simdl_nfms, m256, f32x8);
-impl_vvvv!("lasx", lasx_xvfnmsub_d, simdl_nfms, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvmadd_b, ls::simd_madd, m256i, i8x32);
+impl_vvvv!("lasx", lasx_xvmadd_h, ls::simd_madd, m256i, i16x16);
+impl_vvvv!("lasx", lasx_xvmadd_w, ls::simd_madd, m256i, i32x8);
+impl_vvvv!("lasx", lasx_xvmadd_d, ls::simd_madd, m256i, i64x4);
+impl_vvvv!("lasx", lasx_xvmsub_b, ls::simd_msub, m256i, i8x32);
+impl_vvvv!("lasx", lasx_xvmsub_h, ls::simd_msub, m256i, i16x16);
+impl_vvvv!("lasx", lasx_xvmsub_w, ls::simd_msub, m256i, i32x8);
+impl_vvvv!("lasx", lasx_xvmsub_d, ls::simd_msub, m256i, i64x4);
+impl_vvvv!("lasx", lasx_xvfmadd_s, is::simd_fma, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfmadd_d, is::simd_fma, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvfmsub_s, ls::simd_fmsub, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfmsub_d, ls::simd_fmsub, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvfnmadd_s, ls::simd_fnmadd, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfnmadd_d, ls::simd_fnmadd, m256d, f64x4);
+impl_vvvv!("lasx", lasx_xvfnmsub_s, ls::simd_fnmsub, m256, f32x8);
+impl_vvvv!("lasx", lasx_xvfnmsub_d, ls::simd_fnmsub, m256d, f64x4);
 
-impl_vugv!("lasx", lasx_xvinsgr2vr_w, simd_insert, m256i, i32x8, i32, 3);
-impl_vugv!("lasx", lasx_xvinsgr2vr_d, simd_insert, m256i, i64x4, i64, 2);
+impl_vugv!("lasx", lasx_xvinsgr2vr_w, is::simd_insert, m256i, i32x8, i32, 3);
+impl_vugv!("lasx", lasx_xvinsgr2vr_d, is::simd_insert, m256i, i64x4, i64, 2);
diff --git a/crates/core_arch/src/loongarch64/lsx/portable.rs b/crates/core_arch/src/loongarch64/lsx/portable.rs
index e33b1758f3..1980000c3d 100644
--- a/crates/core_arch/src/loongarch64/lsx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -1,207 +1,207 @@
 //! LoongArch64 LSX intrinsics - intrinsics::simd implementation
 
-use super::super::{simd::*, *};
-use crate::core_arch::simd::*;
-use crate::intrinsics::simd::*;
+use super::super::{simd as ls, simd::*, *};
+use crate::core_arch::simd::{self as cs, *};
+use crate::intrinsics::simd as is;
 use crate::mem::transmute;
 
-impl_vv!("lsx", lsx_vpcnt_b, simd_ctpop, m128i, i8x16);
-impl_vv!("lsx", lsx_vpcnt_h, simd_ctpop, m128i, i16x8);
-impl_vv!("lsx", lsx_vpcnt_w, simd_ctpop, m128i, i32x4);
-impl_vv!("lsx", lsx_vpcnt_d, simd_ctpop, m128i, i64x2);
-impl_vv!("lsx", lsx_vclz_b, simd_ctlz, m128i, i8x16);
-impl_vv!("lsx", lsx_vclz_h, simd_ctlz, m128i, i16x8);
-impl_vv!("lsx", lsx_vclz_w, simd_ctlz, m128i, i32x4);
-impl_vv!("lsx", lsx_vclz_d, simd_ctlz, m128i, i64x2);
-impl_vv!("lsx", lsx_vneg_b, simd_neg, m128i, i8x16);
-impl_vv!("lsx", lsx_vneg_h, simd_neg, m128i, i16x8);
-impl_vv!("lsx", lsx_vneg_w, simd_neg, m128i, i32x4);
-impl_vv!("lsx", lsx_vneg_d, simd_neg, m128i, i64x2);
-impl_vv!("lsx", lsx_vfsqrt_s, simd_fsqrt, m128, f32x4);
-impl_vv!("lsx", lsx_vfsqrt_d, simd_fsqrt, m128d, f64x2);
+impl_vv!("lsx", lsx_vpcnt_b, is::simd_ctpop, m128i, i8x16);
+impl_vv!("lsx", lsx_vpcnt_h, is::simd_ctpop, m128i, i16x8);
+impl_vv!("lsx", lsx_vpcnt_w, is::simd_ctpop, m128i, i32x4);
+impl_vv!("lsx", lsx_vpcnt_d, is::simd_ctpop, m128i, i64x2);
+impl_vv!("lsx", lsx_vclz_b, is::simd_ctlz, m128i, i8x16);
+impl_vv!("lsx", lsx_vclz_h, is::simd_ctlz, m128i, i16x8);
+impl_vv!("lsx", lsx_vclz_w, is::simd_ctlz, m128i, i32x4);
+impl_vv!("lsx", lsx_vclz_d, is::simd_ctlz, m128i, i64x2);
+impl_vv!("lsx", lsx_vneg_b, is::simd_neg, m128i, i8x16);
+impl_vv!("lsx", lsx_vneg_h, is::simd_neg, m128i, i16x8);
+impl_vv!("lsx", lsx_vneg_w, is::simd_neg, m128i, i32x4);
+impl_vv!("lsx", lsx_vneg_d, is::simd_neg, m128i, i64x2);
+impl_vv!("lsx", lsx_vfsqrt_s, is::simd_fsqrt, m128, f32x4);
+impl_vv!("lsx", lsx_vfsqrt_d, is::simd_fsqrt, m128d, f64x2);
 
-impl_gv!("lsx", lsx_vreplgr2vr_b, simdl_splat, m128i, i8x16, i32);
-impl_gv!("lsx", lsx_vreplgr2vr_h, simdl_splat, m128i, i16x8, i32);
-impl_gv!("lsx", lsx_vreplgr2vr_w, simdl_splat, m128i, i32x4, i32);
-impl_gv!("lsx", lsx_vreplgr2vr_d, simdl_splat, m128i, i64x2, i64);
+impl_gv!("lsx", lsx_vreplgr2vr_b, ls::simd_splat, m128i, i8x16, i32);
+impl_gv!("lsx", lsx_vreplgr2vr_h, ls::simd_splat, m128i, i16x8, i32);
+impl_gv!("lsx", lsx_vreplgr2vr_w, ls::simd_splat, m128i, i32x4, i32);
+impl_gv!("lsx", lsx_vreplgr2vr_d, ls::simd_splat, m128i, i64x2, i64);
 
-impl_sv!("lsx", lsx_vrepli_b, simdl_splat, m128i, i8x16, 10);
-impl_sv!("lsx", lsx_vrepli_h, simdl_splat, m128i, i16x8, 10);
-impl_sv!("lsx", lsx_vrepli_w, simdl_splat, m128i, i32x4, 10);
-impl_sv!("lsx", lsx_vrepli_d, simdl_splat, m128i, i64x2, 10);
+impl_sv!("lsx", lsx_vrepli_b, ls::simd_splat, m128i, i8x16, 10);
+impl_sv!("lsx", lsx_vrepli_h, ls::simd_splat, m128i, i16x8, 10);
+impl_sv!("lsx", lsx_vrepli_w, ls::simd_splat, m128i, i32x4, 10);
+impl_sv!("lsx", lsx_vrepli_d, ls::simd_splat, m128i, i64x2, 10);
 
-impl_vvv!("lsx", lsx_vadd_b, simd_add, m128i, i8x16);
-impl_vvv!("lsx", lsx_vadd_h, simd_add, m128i, i16x8);
-impl_vvv!("lsx", lsx_vadd_w, simd_add, m128i, i32x4);
-impl_vvv!("lsx", lsx_vadd_d, simd_add, m128i, i64x2);
-impl_vvv!("lsx", lsx_vsub_b, simd_sub, m128i, i8x16);
-impl_vvv!("lsx", lsx_vsub_h, simd_sub, m128i, i16x8);
-impl_vvv!("lsx", lsx_vsub_w, simd_sub, m128i, i32x4);
-impl_vvv!("lsx", lsx_vsub_d, simd_sub, m128i, i64x2);
-impl_vvv!("lsx", lsx_vmax_b, simd_imax, m128i, i8x16);
-impl_vvv!("lsx", lsx_vmax_h, simd_imax, m128i, i16x8);
-impl_vvv!("lsx", lsx_vmax_w, simd_imax, m128i, i32x4);
-impl_vvv!("lsx", lsx_vmax_d, simd_imax, m128i, i64x2);
-impl_vvv!("lsx", lsx_vmax_bu, simd_imax, m128i, u8x16);
-impl_vvv!("lsx", lsx_vmax_hu, simd_imax, m128i, u16x8);
-impl_vvv!("lsx", lsx_vmax_wu, simd_imax, m128i, u32x4);
-impl_vvv!("lsx", lsx_vmax_du, simd_imax, m128i, u64x2);
-impl_vvv!("lsx", lsx_vmin_b, simd_imin, m128i, i8x16);
-impl_vvv!("lsx", lsx_vmin_h, simd_imin, m128i, i16x8);
-impl_vvv!("lsx", lsx_vmin_w, simd_imin, m128i, i32x4);
-impl_vvv!("lsx", lsx_vmin_d, simd_imin, m128i, i64x2);
-impl_vvv!("lsx", lsx_vmin_bu, simd_imin, m128i, u8x16);
-impl_vvv!("lsx", lsx_vmin_hu, simd_imin, m128i, u16x8);
-impl_vvv!("lsx", lsx_vmin_wu, simd_imin, m128i, u32x4);
-impl_vvv!("lsx", lsx_vmin_du, simd_imin, m128i, u64x2);
-impl_vvv!("lsx", lsx_vseq_b, simd_eq, m128i, i8x16);
-impl_vvv!("lsx", lsx_vseq_h, simd_eq, m128i, i16x8);
-impl_vvv!("lsx", lsx_vseq_w, simd_eq, m128i, i32x4);
-impl_vvv!("lsx", lsx_vseq_d, simd_eq, m128i, i64x2);
-impl_vvv!("lsx", lsx_vslt_b, simd_lt, m128i, i8x16);
-impl_vvv!("lsx", lsx_vslt_h, simd_lt, m128i, i16x8);
-impl_vvv!("lsx", lsx_vslt_w, simd_lt, m128i, i32x4);
-impl_vvv!("lsx", lsx_vslt_d, simd_lt, m128i, i64x2);
-impl_vvv!("lsx", lsx_vslt_bu, simd_lt, m128i, u8x16);
-impl_vvv!("lsx", lsx_vslt_hu, simd_lt, m128i, u16x8);
-impl_vvv!("lsx", lsx_vslt_wu, simd_lt, m128i, u32x4);
-impl_vvv!("lsx", lsx_vslt_du, simd_lt, m128i, u64x2);
-impl_vvv!("lsx", lsx_vsle_b, simd_le, m128i, i8x16);
-impl_vvv!("lsx", lsx_vsle_h, simd_le, m128i, i16x8);
-impl_vvv!("lsx", lsx_vsle_w, simd_le, m128i, i32x4);
-impl_vvv!("lsx", lsx_vsle_d, simd_le, m128i, i64x2);
-impl_vvv!("lsx", lsx_vsle_bu, simd_le, m128i, u8x16);
-impl_vvv!("lsx", lsx_vsle_hu, simd_le, m128i, u16x8);
-impl_vvv!("lsx", lsx_vsle_wu, simd_le, m128i, u32x4);
-impl_vvv!("lsx", lsx_vsle_du, simd_le, m128i, u64x2);
-impl_vvv!("lsx", lsx_vmul_b, simd_mul, m128i, i8x16);
-impl_vvv!("lsx", lsx_vmul_h, simd_mul, m128i, i16x8);
-impl_vvv!("lsx", lsx_vmul_w, simd_mul, m128i, i32x4);
-impl_vvv!("lsx", lsx_vmul_d, simd_mul, m128i, i64x2);
-impl_vvv!("lsx", lsx_vdiv_b, simd_div, m128i, i8x16);
-impl_vvv!("lsx", lsx_vdiv_h, simd_div, m128i, i16x8);
-impl_vvv!("lsx", lsx_vdiv_w, simd_div, m128i, i32x4);
-impl_vvv!("lsx", lsx_vdiv_d, simd_div, m128i, i64x2);
-impl_vvv!("lsx", lsx_vdiv_bu, simd_div, m128i, u8x16);
-impl_vvv!("lsx", lsx_vdiv_hu, simd_div, m128i, u16x8);
-impl_vvv!("lsx", lsx_vdiv_wu, simd_div, m128i, u32x4);
-impl_vvv!("lsx", lsx_vdiv_du, simd_div, m128i, u64x2);
-impl_vvv!("lsx", lsx_vmod_b, simd_rem, m128i, i8x16);
-impl_vvv!("lsx", lsx_vmod_h, simd_rem, m128i, i16x8);
-impl_vvv!("lsx", lsx_vmod_w, simd_rem, m128i, i32x4);
-impl_vvv!("lsx", lsx_vmod_d, simd_rem, m128i, i64x2);
-impl_vvv!("lsx", lsx_vmod_bu, simd_rem, m128i, u8x16);
-impl_vvv!("lsx", lsx_vmod_hu, simd_rem, m128i, u16x8);
-impl_vvv!("lsx", lsx_vmod_wu, simd_rem, m128i, u32x4);
-impl_vvv!("lsx", lsx_vmod_du, simd_rem, m128i, u64x2);
-impl_vvv!("lsx", lsx_vand_v, simd_and, m128i, u8x16);
-impl_vvv!("lsx", lsx_vandn_v, simdl_andn, m128i, u8x16);
-impl_vvv!("lsx", lsx_vor_v, simd_or, m128i, u8x16);
-impl_vvv!("lsx", lsx_vorn_v, simdl_orn, m128i, u8x16);
-impl_vvv!("lsx", lsx_vnor_v, simdl_nor, m128i, u8x16);
-impl_vvv!("lsx", lsx_vxor_v, simd_xor, m128i, u8x16);
-impl_vvv!("lsx", lsx_vfadd_s, simd_add, m128, f32x4);
-impl_vvv!("lsx", lsx_vfadd_d, simd_add, m128d, f64x2);
-impl_vvv!("lsx", lsx_vfsub_s, simd_sub, m128, f32x4);
-impl_vvv!("lsx", lsx_vfsub_d, simd_sub, m128d, f64x2);
-impl_vvv!("lsx", lsx_vfmul_s, simd_mul, m128, f32x4);
-impl_vvv!("lsx", lsx_vfmul_d, simd_mul, m128d, f64x2);
-impl_vvv!("lsx", lsx_vfdiv_s, simd_div, m128, f32x4);
-impl_vvv!("lsx", lsx_vfdiv_d, simd_div, m128d, f64x2);
-impl_vvv!("lsx", lsx_vsll_b, simdl_shl, m128i, i8x16);
-impl_vvv!("lsx", lsx_vsll_h, simdl_shl, m128i, i16x8);
-impl_vvv!("lsx", lsx_vsll_w, simdl_shl, m128i, i32x4);
-impl_vvv!("lsx", lsx_vsll_d, simdl_shl, m128i, i64x2);
-impl_vvv!("lsx", lsx_vsra_b, simdl_shr, m128i, i8x16);
-impl_vvv!("lsx", lsx_vsra_h, simdl_shr, m128i, i16x8);
-impl_vvv!("lsx", lsx_vsra_w, simdl_shr, m128i, i32x4);
-impl_vvv!("lsx", lsx_vsra_d, simdl_shr, m128i, i64x2);
-impl_vvv!("lsx", lsx_vsrl_b, simdl_shr, m128i, u8x16);
-impl_vvv!("lsx", lsx_vsrl_h, simdl_shr, m128i, u16x8);
-impl_vvv!("lsx", lsx_vsrl_w, simdl_shr, m128i, u32x4);
-impl_vvv!("lsx", lsx_vsrl_d, simdl_shr, m128i, u64x2);
+impl_vvv!("lsx", lsx_vadd_b, is::simd_add, m128i, i8x16);
+impl_vvv!("lsx", lsx_vadd_h, is::simd_add, m128i, i16x8);
+impl_vvv!("lsx", lsx_vadd_w, is::simd_add, m128i, i32x4);
+impl_vvv!("lsx", lsx_vadd_d, is::simd_add, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsub_b, is::simd_sub, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsub_h, is::simd_sub, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsub_w, is::simd_sub, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsub_d, is::simd_sub, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmax_b, cs::simd_imax, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmax_h, cs::simd_imax, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmax_w, cs::simd_imax, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmax_d, cs::simd_imax, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmax_bu, cs::simd_imax, m128i, u8x16);
+impl_vvv!("lsx", lsx_vmax_hu, cs::simd_imax, m128i, u16x8);
+impl_vvv!("lsx", lsx_vmax_wu, cs::simd_imax, m128i, u32x4);
+impl_vvv!("lsx", lsx_vmax_du, cs::simd_imax, m128i, u64x2);
+impl_vvv!("lsx", lsx_vmin_b, cs::simd_imin, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmin_h, cs::simd_imin, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmin_w, cs::simd_imin, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmin_d, cs::simd_imin, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmin_bu, cs::simd_imin, m128i, u8x16);
+impl_vvv!("lsx", lsx_vmin_hu, cs::simd_imin, m128i, u16x8);
+impl_vvv!("lsx", lsx_vmin_wu, cs::simd_imin, m128i, u32x4);
+impl_vvv!("lsx", lsx_vmin_du, cs::simd_imin, m128i, u64x2);
+impl_vvv!("lsx", lsx_vseq_b, is::simd_eq, m128i, i8x16);
+impl_vvv!("lsx", lsx_vseq_h, is::simd_eq, m128i, i16x8);
+impl_vvv!("lsx", lsx_vseq_w, is::simd_eq, m128i, i32x4);
+impl_vvv!("lsx", lsx_vseq_d, is::simd_eq, m128i, i64x2);
+impl_vvv!("lsx", lsx_vslt_b, is::simd_lt, m128i, i8x16);
+impl_vvv!("lsx", lsx_vslt_h, is::simd_lt, m128i, i16x8);
+impl_vvv!("lsx", lsx_vslt_w, is::simd_lt, m128i, i32x4);
+impl_vvv!("lsx", lsx_vslt_d, is::simd_lt, m128i, i64x2);
+impl_vvv!("lsx", lsx_vslt_bu, is::simd_lt, m128i, u8x16);
+impl_vvv!("lsx", lsx_vslt_hu, is::simd_lt, m128i, u16x8);
+impl_vvv!("lsx", lsx_vslt_wu, is::simd_lt, m128i, u32x4);
+impl_vvv!("lsx", lsx_vslt_du, is::simd_lt, m128i, u64x2);
+impl_vvv!("lsx", lsx_vsle_b, is::simd_le, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsle_h, is::simd_le, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsle_w, is::simd_le, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsle_d, is::simd_le, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsle_bu, is::simd_le, m128i, u8x16);
+impl_vvv!("lsx", lsx_vsle_hu, is::simd_le, m128i, u16x8);
+impl_vvv!("lsx", lsx_vsle_wu, is::simd_le, m128i, u32x4);
+impl_vvv!("lsx", lsx_vsle_du, is::simd_le, m128i, u64x2);
+impl_vvv!("lsx", lsx_vmul_b, is::simd_mul, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmul_h, is::simd_mul, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmul_w, is::simd_mul, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmul_d, is::simd_mul, m128i, i64x2);
+impl_vvv!("lsx", lsx_vdiv_b, is::simd_div, m128i, i8x16);
+impl_vvv!("lsx", lsx_vdiv_h, is::simd_div, m128i, i16x8);
+impl_vvv!("lsx", lsx_vdiv_w, is::simd_div, m128i, i32x4);
+impl_vvv!("lsx", lsx_vdiv_d, is::simd_div, m128i, i64x2);
+impl_vvv!("lsx", lsx_vdiv_bu, is::simd_div, m128i, u8x16);
+impl_vvv!("lsx", lsx_vdiv_hu, is::simd_div, m128i, u16x8);
+impl_vvv!("lsx", lsx_vdiv_wu, is::simd_div, m128i, u32x4);
+impl_vvv!("lsx", lsx_vdiv_du, is::simd_div, m128i, u64x2);
+impl_vvv!("lsx", lsx_vmod_b, is::simd_rem, m128i, i8x16);
+impl_vvv!("lsx", lsx_vmod_h, is::simd_rem, m128i, i16x8);
+impl_vvv!("lsx", lsx_vmod_w, is::simd_rem, m128i, i32x4);
+impl_vvv!("lsx", lsx_vmod_d, is::simd_rem, m128i, i64x2);
+impl_vvv!("lsx", lsx_vmod_bu, is::simd_rem, m128i, u8x16);
+impl_vvv!("lsx", lsx_vmod_hu, is::simd_rem, m128i, u16x8);
+impl_vvv!("lsx", lsx_vmod_wu, is::simd_rem, m128i, u32x4);
+impl_vvv!("lsx", lsx_vmod_du, is::simd_rem, m128i, u64x2);
+impl_vvv!("lsx", lsx_vand_v, is::simd_and, m128i, u8x16);
+impl_vvv!("lsx", lsx_vandn_v, ls::simd_andn, m128i, u8x16);
+impl_vvv!("lsx", lsx_vor_v, is::simd_or, m128i, u8x16);
+impl_vvv!("lsx", lsx_vorn_v, ls::simd_orn, m128i, u8x16);
+impl_vvv!("lsx", lsx_vnor_v, ls::simd_nor, m128i, u8x16);
+impl_vvv!("lsx", lsx_vxor_v, is::simd_xor, m128i, u8x16);
+impl_vvv!("lsx", lsx_vfadd_s, is::simd_add, m128, f32x4);
+impl_vvv!("lsx", lsx_vfadd_d, is::simd_add, m128d, f64x2);
+impl_vvv!("lsx", lsx_vfsub_s, is::simd_sub, m128, f32x4);
+impl_vvv!("lsx", lsx_vfsub_d, is::simd_sub, m128d, f64x2);
+impl_vvv!("lsx", lsx_vfmul_s, is::simd_mul, m128, f32x4);
+impl_vvv!("lsx", lsx_vfmul_d, is::simd_mul, m128d, f64x2);
+impl_vvv!("lsx", lsx_vfdiv_s, is::simd_div, m128, f32x4);
+impl_vvv!("lsx", lsx_vfdiv_d, is::simd_div, m128d, f64x2);
+impl_vvv!("lsx", lsx_vsll_b, ls::simd_shl, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsll_h, ls::simd_shl, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsll_w, ls::simd_shl, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsll_d, ls::simd_shl, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsra_b, ls::simd_shr, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsra_h, ls::simd_shr, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsra_w, ls::simd_shr, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsra_d, ls::simd_shr, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsrl_b, ls::simd_shr, m128i, u8x16);
+impl_vvv!("lsx", lsx_vsrl_h, ls::simd_shr, m128i, u16x8);
+impl_vvv!("lsx", lsx_vsrl_w, ls::simd_shr, m128i, u32x4);
+impl_vvv!("lsx", lsx_vsrl_d, ls::simd_shr, m128i, u64x2);
 
-impl_vuv!("lsx", lsx_vslli_b, simd_shl, m128i, i8x16);
-impl_vuv!("lsx", lsx_vslli_h, simd_shl, m128i, i16x8);
-impl_vuv!("lsx", lsx_vslli_w, simd_shl, m128i, i32x4);
-impl_vuv!("lsx", lsx_vslli_d, simd_shl, m128i, i64x2);
-impl_vuv!("lsx", lsx_vsrai_b, simd_shr, m128i, i8x16);
-impl_vuv!("lsx", lsx_vsrai_h, simd_shr, m128i, i16x8);
-impl_vuv!("lsx", lsx_vsrai_w, simd_shr, m128i, i32x4);
-impl_vuv!("lsx", lsx_vsrai_d, simd_shr, m128i, i64x2);
-impl_vuv!("lsx", lsx_vsrli_b, simd_shr, m128i, u8x16);
-impl_vuv!("lsx", lsx_vsrli_h, simd_shr, m128i, u16x8);
-impl_vuv!("lsx", lsx_vsrli_w, simd_shr, m128i, u32x4);
-impl_vuv!("lsx", lsx_vsrli_d, simd_shr, m128i, u64x2);
-impl_vuv!("lsx", lsx_vaddi_bu, simd_add, m128i, u8x16, 5);
-impl_vuv!("lsx", lsx_vaddi_hu, simd_add, m128i, u16x8, 5);
-impl_vuv!("lsx", lsx_vaddi_wu, simd_add, m128i, u32x4, 5);
-impl_vuv!("lsx", lsx_vaddi_du, simd_add, m128i, u64x2, 5);
-impl_vuv!("lsx", lsx_vslti_bu, simd_lt, m128i, u8x16, 5);
-impl_vuv!("lsx", lsx_vslti_hu, simd_lt, m128i, u16x8, 5);
-impl_vuv!("lsx", lsx_vslti_wu, simd_lt, m128i, u32x4, 5);
-impl_vuv!("lsx", lsx_vslti_du, simd_lt, m128i, u64x2, 5);
-impl_vuv!("lsx", lsx_vslei_bu, simd_le, m128i, u8x16, 5);
-impl_vuv!("lsx", lsx_vslei_hu, simd_le, m128i, u16x8, 5);
-impl_vuv!("lsx", lsx_vslei_wu, simd_le, m128i, u32x4, 5);
-impl_vuv!("lsx", lsx_vslei_du, simd_le, m128i, u64x2, 5);
-impl_vuv!("lsx", lsx_vmaxi_bu, simd_imax, m128i, u8x16, 5);
-impl_vuv!("lsx", lsx_vmaxi_hu, simd_imax, m128i, u16x8, 5);
-impl_vuv!("lsx", lsx_vmaxi_wu, simd_imax, m128i, u32x4, 5);
-impl_vuv!("lsx", lsx_vmaxi_du, simd_imax, m128i, u64x2, 5);
-impl_vuv!("lsx", lsx_vmini_bu, simd_imin, m128i, u8x16, 5);
-impl_vuv!("lsx", lsx_vmini_hu, simd_imin, m128i, u16x8, 5);
-impl_vuv!("lsx", lsx_vmini_wu, simd_imin, m128i, u32x4, 5);
-impl_vuv!("lsx", lsx_vmini_du, simd_imin, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vslli_b, is::simd_shl, m128i, i8x16);
+impl_vuv!("lsx", lsx_vslli_h, is::simd_shl, m128i, i16x8);
+impl_vuv!("lsx", lsx_vslli_w, is::simd_shl, m128i, i32x4);
+impl_vuv!("lsx", lsx_vslli_d, is::simd_shl, m128i, i64x2);
+impl_vuv!("lsx", lsx_vsrai_b, is::simd_shr, m128i, i8x16);
+impl_vuv!("lsx", lsx_vsrai_h, is::simd_shr, m128i, i16x8);
+impl_vuv!("lsx", lsx_vsrai_w, is::simd_shr, m128i, i32x4);
+impl_vuv!("lsx", lsx_vsrai_d, is::simd_shr, m128i, i64x2);
+impl_vuv!("lsx", lsx_vsrli_b, is::simd_shr, m128i, u8x16);
+impl_vuv!("lsx", lsx_vsrli_h, is::simd_shr, m128i, u16x8);
+impl_vuv!("lsx", lsx_vsrli_w, is::simd_shr, m128i, u32x4);
+impl_vuv!("lsx", lsx_vsrli_d, is::simd_shr, m128i, u64x2);
+impl_vuv!("lsx", lsx_vaddi_bu, is::simd_add, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vaddi_hu, is::simd_add, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vaddi_wu, is::simd_add, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vaddi_du, is::simd_add, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vslti_bu, is::simd_lt, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vslti_hu, is::simd_lt, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vslti_wu, is::simd_lt, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vslti_du, is::simd_lt, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vslei_bu, is::simd_le, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vslei_hu, is::simd_le, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vslei_wu, is::simd_le, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vslei_du, is::simd_le, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vmaxi_bu, cs::simd_imax, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vmaxi_hu, cs::simd_imax, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vmaxi_wu, cs::simd_imax, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vmaxi_du, cs::simd_imax, m128i, u64x2, 5);
+impl_vuv!("lsx", lsx_vmini_bu, cs::simd_imin, m128i, u8x16, 5);
+impl_vuv!("lsx", lsx_vmini_hu, cs::simd_imin, m128i, u16x8, 5);
+impl_vuv!("lsx", lsx_vmini_wu, cs::simd_imin, m128i, u32x4, 5);
+impl_vuv!("lsx", lsx_vmini_du, cs::simd_imin, m128i, u64x2, 5);
 
-impl_vug!("lsx", lsx_vpickve2gr_b, simd_extract, m128i, i8x16, i32, 4);
-impl_vug!("lsx", lsx_vpickve2gr_h, simd_extract, m128i, i16x8, i32, 3);
-impl_vug!("lsx", lsx_vpickve2gr_w, simd_extract, m128i, i32x4, i32, 2);
-impl_vug!("lsx", lsx_vpickve2gr_d, simd_extract, m128i, i64x2, i64, 1);
-impl_vug!("lsx", lsx_vpickve2gr_bu, simd_extract, m128i, u8x16, u32, 4);
-impl_vug!("lsx", lsx_vpickve2gr_hu, simd_extract, m128i, u16x8, u32, 3);
-impl_vug!("lsx", lsx_vpickve2gr_wu, simd_extract, m128i, u32x4, u32, 2);
-impl_vug!("lsx", lsx_vpickve2gr_du, simd_extract, m128i, u64x2, u64, 1);
+impl_vug!("lsx", lsx_vpickve2gr_b, is::simd_extract, m128i, i8x16, i32, 4);
+impl_vug!("lsx", lsx_vpickve2gr_h, is::simd_extract, m128i, i16x8, i32, 3);
+impl_vug!("lsx", lsx_vpickve2gr_w, is::simd_extract, m128i, i32x4, i32, 2);
+impl_vug!("lsx", lsx_vpickve2gr_d, is::simd_extract, m128i, i64x2, i64, 1);
+impl_vug!("lsx", lsx_vpickve2gr_bu, is::simd_extract, m128i, u8x16, u32, 4);
+impl_vug!("lsx", lsx_vpickve2gr_hu, is::simd_extract, m128i, u16x8, u32, 3);
+impl_vug!("lsx", lsx_vpickve2gr_wu, is::simd_extract, m128i, u32x4, u32, 2);
+impl_vug!("lsx", lsx_vpickve2gr_du, is::simd_extract, m128i, u64x2, u64, 1);
 
-impl_vsv!("lsx", lsx_vseqi_b, simd_eq, m128i, i8x16, 5);
-impl_vsv!("lsx", lsx_vseqi_h, simd_eq, m128i, i16x8, 5);
-impl_vsv!("lsx", lsx_vseqi_w, simd_eq, m128i, i32x4, 5);
-impl_vsv!("lsx", lsx_vseqi_d, simd_eq, m128i, i64x2, 5);
-impl_vsv!("lsx", lsx_vslti_b, simd_lt, m128i, i8x16, 5);
-impl_vsv!("lsx", lsx_vslti_h, simd_lt, m128i, i16x8, 5);
-impl_vsv!("lsx", lsx_vslti_w, simd_lt, m128i, i32x4, 5);
-impl_vsv!("lsx", lsx_vslti_d, simd_lt, m128i, i64x2, 5);
-impl_vsv!("lsx", lsx_vslei_b, simd_le, m128i, i8x16, 5);
-impl_vsv!("lsx", lsx_vslei_h, simd_le, m128i, i16x8, 5);
-impl_vsv!("lsx", lsx_vslei_w, simd_le, m128i, i32x4, 5);
-impl_vsv!("lsx", lsx_vslei_d, simd_le, m128i, i64x2, 5);
-impl_vsv!("lsx", lsx_vmaxi_b, simd_imax, m128i, i8x16, 5);
-impl_vsv!("lsx", lsx_vmaxi_h, simd_imax, m128i, i16x8, 5);
-impl_vsv!("lsx", lsx_vmaxi_w, simd_imax, m128i, i32x4, 5);
-impl_vsv!("lsx", lsx_vmaxi_d, simd_imax, m128i, i64x2, 5);
-impl_vsv!("lsx", lsx_vmini_b, simd_imin, m128i, i8x16, 5);
-impl_vsv!("lsx", lsx_vmini_h, simd_imin, m128i, i16x8, 5);
-impl_vsv!("lsx", lsx_vmini_w, simd_imin, m128i, i32x4, 5);
-impl_vsv!("lsx", lsx_vmini_d, simd_imin, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vseqi_b, is::simd_eq, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vseqi_h, is::simd_eq, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vseqi_w, is::simd_eq, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vseqi_d, is::simd_eq, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vslti_b, is::simd_lt, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vslti_h, is::simd_lt, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vslti_w, is::simd_lt, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vslti_d, is::simd_lt, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vslei_b, is::simd_le, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vslei_h, is::simd_le, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vslei_w, is::simd_le, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vslei_d, is::simd_le, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vmaxi_b, cs::simd_imax, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vmaxi_h, cs::simd_imax, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vmaxi_w, cs::simd_imax, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vmaxi_d, cs::simd_imax, m128i, i64x2, 5);
+impl_vsv!("lsx", lsx_vmini_b, cs::simd_imin, m128i, i8x16, 5);
+impl_vsv!("lsx", lsx_vmini_h, cs::simd_imin, m128i, i16x8, 5);
+impl_vsv!("lsx", lsx_vmini_w, cs::simd_imin, m128i, i32x4, 5);
+impl_vsv!("lsx", lsx_vmini_d, cs::simd_imin, m128i, i64x2, 5);
 
-impl_vvvv!("lsx", lsx_vmadd_b, simdl_madd, m128i, i8x16);
-impl_vvvv!("lsx", lsx_vmadd_h, simdl_madd, m128i, i16x8);
-impl_vvvv!("lsx", lsx_vmadd_w, simdl_madd, m128i, i32x4);
-impl_vvvv!("lsx", lsx_vmadd_d, simdl_madd, m128i, i64x2);
-impl_vvvv!("lsx", lsx_vmsub_b, simdl_msub, m128i, i8x16);
-impl_vvvv!("lsx", lsx_vmsub_h, simdl_msub, m128i, i16x8);
-impl_vvvv!("lsx", lsx_vmsub_w, simdl_msub, m128i, i32x4);
-impl_vvvv!("lsx", lsx_vmsub_d, simdl_msub, m128i, i64x2);
-impl_vvvv!("lsx", lsx_vfmadd_s, simd_fma, m128, f32x4);
-impl_vvvv!("lsx", lsx_vfmadd_d, simd_fma, m128d, f64x2);
-impl_vvvv!("lsx", lsx_vfmsub_s, simdl_fms, m128, f32x4);
-impl_vvvv!("lsx", lsx_vfmsub_d, simdl_fms, m128d, f64x2);
-impl_vvvv!("lsx", lsx_vfnmadd_s, simdl_nfma, m128, f32x4);
-impl_vvvv!("lsx", lsx_vfnmadd_d, simdl_nfma, m128d, f64x2);
-impl_vvvv!("lsx", lsx_vfnmsub_s, simdl_nfms, m128, f32x4);
-impl_vvvv!("lsx", lsx_vfnmsub_d, simdl_nfms, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vmadd_b, ls::simd_madd, m128i, i8x16);
+impl_vvvv!("lsx", lsx_vmadd_h, ls::simd_madd, m128i, i16x8);
+impl_vvvv!("lsx", lsx_vmadd_w, ls::simd_madd, m128i, i32x4);
+impl_vvvv!("lsx", lsx_vmadd_d, ls::simd_madd, m128i, i64x2);
+impl_vvvv!("lsx", lsx_vmsub_b, ls::simd_msub, m128i, i8x16);
+impl_vvvv!("lsx", lsx_vmsub_h, ls::simd_msub, m128i, i16x8);
+impl_vvvv!("lsx", lsx_vmsub_w, ls::simd_msub, m128i, i32x4);
+impl_vvvv!("lsx", lsx_vmsub_d, ls::simd_msub, m128i, i64x2);
+impl_vvvv!("lsx", lsx_vfmadd_s, is::simd_fma, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfmadd_d, is::simd_fma, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vfmsub_s, ls::simd_fmsub, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfmsub_d, ls::simd_fmsub, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vfnmadd_s, ls::simd_fnmadd, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfnmadd_d, ls::simd_fnmadd, m128d, f64x2);
+impl_vvvv!("lsx", lsx_vfnmsub_s, ls::simd_fnmsub, m128, f32x4);
+impl_vvvv!("lsx", lsx_vfnmsub_d, ls::simd_fnmsub, m128d, f64x2);
 
-impl_vugv!("lsx", lsx_vinsgr2vr_b, simd_insert, m128i, i8x16, i32, 4);
-impl_vugv!("lsx", lsx_vinsgr2vr_h, simd_insert, m128i, i16x8, i32, 3);
-impl_vugv!("lsx", lsx_vinsgr2vr_w, simd_insert, m128i, i32x4, i32, 2);
-impl_vugv!("lsx", lsx_vinsgr2vr_d, simd_insert, m128i, i64x2, i64, 1);
+impl_vugv!("lsx", lsx_vinsgr2vr_b, is::simd_insert, m128i, i8x16, i32, 4);
+impl_vugv!("lsx", lsx_vinsgr2vr_h, is::simd_insert, m128i, i16x8, i32, 3);
+impl_vugv!("lsx", lsx_vinsgr2vr_w, is::simd_insert, m128i, i32x4, i32, 2);
+impl_vugv!("lsx", lsx_vinsgr2vr_d, is::simd_insert, m128i, i64x2, i64, 1);
diff --git a/crates/core_arch/src/loongarch64/simd.rs b/crates/core_arch/src/loongarch64/simd.rs
index ac98d6ac5d..2dedfa7eb9 100644
--- a/crates/core_arch/src/loongarch64/simd.rs
+++ b/crates/core_arch/src/loongarch64/simd.rs
@@ -1,127 +1,126 @@
 //! LoongArch64 SIMD helpers
 
-pub(super) const trait SimdL: Sized {
+use self as ls;
+use crate::intrinsics::simd as is;
+
+// Internal extension trait for concrete `Simd<T, N>` types.
+//
+// Provides a small set of helper functionality (`Elem` and `splat`)
+// so generic and macro-based code can operate on different SIMD
+// vector types in a uniform way.
+pub(super) const trait SimdExt: Sized {
     type Elem;
 
     unsafe fn splat(v: i64) -> Self;
 }
 
-macro_rules! impl_simdl {
+macro_rules! impl_simd_ext {
     ($v:ident, $e:ty) => {
         #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-        impl const SimdL for crate::core_arch::simd::$v {
+        impl const SimdExt for crate::core_arch::simd::$v {
             type Elem = $e;
 
             #[inline(always)]
             unsafe fn splat(v: i64) -> Self {
-                crate::intrinsics::simd::simd_splat(v as Self::Elem)
+                is::simd_splat(v as Self::Elem)
             }
         }
     };
 }
 
-impl_simdl!(i8x16, i8);
-impl_simdl!(i8x32, i8);
-impl_simdl!(u8x16, u8);
-impl_simdl!(u8x32, u8);
-impl_simdl!(i16x8, i16);
-impl_simdl!(i16x16, i16);
-impl_simdl!(u16x8, u16);
-impl_simdl!(u16x16, u16);
-impl_simdl!(i32x4, i32);
-impl_simdl!(i32x8, i32);
-impl_simdl!(u32x4, u32);
-impl_simdl!(u32x8, u32);
-impl_simdl!(i64x2, i64);
-impl_simdl!(i64x4, i64);
-impl_simdl!(u64x2, u64);
-impl_simdl!(u64x4, u64);
+impl_simd_ext!(i8x16, i8);
+impl_simd_ext!(i8x32, i8);
+impl_simd_ext!(u8x16, u8);
+impl_simd_ext!(u8x32, u8);
+impl_simd_ext!(i16x8, i16);
+impl_simd_ext!(i16x16, i16);
+impl_simd_ext!(u16x8, u16);
+impl_simd_ext!(u16x16, u16);
+impl_simd_ext!(i32x4, i32);
+impl_simd_ext!(i32x8, i32);
+impl_simd_ext!(u32x4, u32);
+impl_simd_ext!(u32x8, u32);
+impl_simd_ext!(i64x2, i64);
+impl_simd_ext!(i64x4, i64);
+impl_simd_ext!(u64x2, u64);
+impl_simd_ext!(u64x4, u64);
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_andn<T: Copy + const SimdL>(a: T, b: T) -> T {
-    crate::intrinsics::simd::simd_and(simdl_not(a), b)
+pub(super) const unsafe fn simd_andn<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    is::simd_and(ls::simd_not(a), b)
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_fms<T: Copy>(a: T, b: T, c: T) -> T {
-    let c: T = crate::intrinsics::simd::simd_neg(c);
-    crate::intrinsics::simd::simd_fma(a, b, c)
+pub(super) const unsafe fn simd_fmsub<T: Copy>(a: T, b: T, c: T) -> T {
+    is::simd_fma(a, b, is::simd_neg(c))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_madd<T: Copy>(a: T, b: T, c: T) -> T {
-    let mul: T = crate::intrinsics::simd::simd_mul(b, c);
-    crate::intrinsics::simd::simd_add(mul, a)
+pub(super) const unsafe fn simd_fnmadd<T: Copy>(a: T, b: T, c: T) -> T {
+    is::simd_neg(is::simd_fma(a, b, c))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_msub<T: Copy>(a: T, b: T, c: T) -> T {
-    let mul: T = crate::intrinsics::simd::simd_mul(b, c);
-    crate::intrinsics::simd::simd_sub(a, mul)
+pub(super) const unsafe fn simd_fnmsub<T: Copy>(a: T, b: T, c: T) -> T {
+    is::simd_neg(ls::simd_fmsub(a, b, c))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_nfma<T: Copy>(a: T, b: T, c: T) -> T {
-    let fma: T = crate::intrinsics::simd::simd_fma(a, b, c);
-    crate::intrinsics::simd::simd_neg(fma)
+pub(super) const unsafe fn simd_madd<T: Copy>(a: T, b: T, c: T) -> T {
+    is::simd_add(a, is::simd_mul(b, c))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_nfms<T: Copy>(a: T, b: T, c: T) -> T {
-    let fma: T = simdl_fms(a, b, c);
-    crate::intrinsics::simd::simd_neg(fma)
+pub(super) const unsafe fn simd_msub<T: Copy>(a: T, b: T, c: T) -> T {
+    is::simd_sub(a, is::simd_mul(b, c))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_nor<T: Copy + const SimdL>(a: T, b: T) -> T {
-    let or: T = crate::intrinsics::simd::simd_or(a, b);
-    simdl_not(or)
+pub(super) const unsafe fn simd_nor<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    ls::simd_not(is::simd_or(a, b))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_not<T: Copy + const SimdL>(a: T) -> T {
-    let not: T = simdl_splat(!0);
-    crate::intrinsics::simd::simd_xor(a, not)
+pub(super) const unsafe fn simd_not<T: Copy + const SimdExt>(a: T) -> T {
+    is::simd_xor(a, ls::simd_splat(!0))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_orn<T: Copy + const SimdL>(a: T, b: T) -> T {
-    crate::intrinsics::simd::simd_or(a, simdl_not(b))
+pub(super) const unsafe fn simd_orn<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    is::simd_or(a, ls::simd_not(b))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_shl<T: Copy + const SimdL>(a: T, b: T) -> T {
-    let m: T = simdl_splat((size_of::<T::Elem>() * 8 - 1) as i64);
-    let b: T = crate::intrinsics::simd::simd_and(b, m);
-    crate::intrinsics::simd::simd_shl(a, b)
+pub(super) const unsafe fn simd_shl<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    let m = (size_of::<T::Elem>() * 8 - 1) as i64;
+    is::simd_shl(a, is::simd_and(b, ls::simd_splat(m)))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_shr<T: Copy + const SimdL>(a: T, b: T) -> T {
-    let m: T = simdl_splat((size_of::<T::Elem>() * 8 - 1) as i64);
-    let b: T = crate::intrinsics::simd::simd_and(b, m);
-    crate::intrinsics::simd::simd_shr(a, b)
+pub(super) const unsafe fn simd_shr<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    let m = (size_of::<T::Elem>() * 8 - 1) as i64;
+    is::simd_shr(a, is::simd_and(b, ls::simd_splat(m)))
 }
 
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-pub(super) const unsafe fn simdl_splat<T: Copy + const SimdL>(a: i64) -> T {
+pub(super) const unsafe fn simd_splat<T: Copy + const SimdExt>(a: i64) -> T {
     T::splat(a)
 }
 
 macro_rules! impl_vv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -138,7 +137,7 @@ macro_rules! impl_vv {
 pub(super) use impl_vv;
 
 macro_rules! impl_gv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -154,7 +153,7 @@ macro_rules! impl_gv {
 pub(super) use impl_gv;
 
 macro_rules! impl_sv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(0)]
@@ -172,7 +171,7 @@ macro_rules! impl_sv {
 pub(super) use impl_sv;
 
 macro_rules! impl_vvv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -190,22 +189,22 @@ macro_rules! impl_vvv {
 pub(super) use impl_vvv;
 
 macro_rules! impl_vuv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
         pub fn $name<const IMM: u32>(a: $oty) -> $oty {
-            static_assert_uimm_bits!(IMM, (size_of::<<$ity as SimdL>::Elem>() * 8).ilog2());
+            static_assert_uimm_bits!(IMM, (size_of::<<$ity as SimdExt>::Elem>() * 8).ilog2());
             unsafe {
                 let a: $ity = transmute(a);
-                let b: $ity = simdl_splat(IMM.into());
+                let b: $ity = ls::simd_splat(IMM.into());
                 let r: $ity = $op(a, b);
                 transmute(r)
             }
         }
     };
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
@@ -214,7 +213,7 @@ macro_rules! impl_vuv {
             static_assert_uimm_bits!(IMM, $ibs);
             unsafe {
                 let a: $ity = transmute(a);
-                let b: $ity = simdl_splat(IMM.into());
+                let b: $ity = ls::simd_splat(IMM.into());
                 let r: $ity = $op(a, b);
                 transmute(r)
             }
@@ -225,7 +224,7 @@ macro_rules! impl_vuv {
 pub(super) use impl_vuv;
 
 macro_rules! impl_vug {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
@@ -234,7 +233,7 @@ macro_rules! impl_vug {
             static_assert_uimm_bits!(IMM, $ibs);
             unsafe {
                 let a: $ity = transmute(a);
-                let r: <$ity as SimdL>::Elem = $op(a, IMM);
+                let r: <$ity as SimdExt>::Elem = $op(a, IMM);
                 r as $gty
             }
         }
@@ -244,7 +243,7 @@ macro_rules! impl_vug {
 pub(super) use impl_vug;
 
 macro_rules! impl_vsv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
@@ -253,7 +252,7 @@ macro_rules! impl_vsv {
             static_assert_simm_bits!(IMM, $ibs);
             unsafe {
                 let a: $ity = transmute(a);
-                let b: $ity = simdl_splat(IMM.into());
+                let b: $ity = ls::simd_splat(IMM.into());
                 let r: $ity = $op(a, b);
                 transmute(r)
             }
@@ -264,7 +263,7 @@ macro_rules! impl_vsv {
 pub(super) use impl_vsv;
 
 macro_rules! impl_vvvv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ty) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -283,7 +282,7 @@ macro_rules! impl_vvvv {
 pub(super) use impl_vvvv;
 
 macro_rules! impl_vugv {
-    ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
+    ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
         #[inline(always)]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
@@ -292,7 +291,7 @@ macro_rules! impl_vugv {
             static_assert_uimm_bits!(IMM, $ibs);
             unsafe {
                 let a: $ity = transmute(a);
-                let r: $ity = $op(a, IMM, b as <$ity as SimdL>::Elem);
+                let r: $ity = $op(a, IMM, b as <$ity as SimdExt>::Elem);
                 transmute(r)
             }
         }

From af2d3b958645bdb3df0e9142f674f18da579787d Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 30 Apr 2026 08:39:24 +0530
Subject: [PATCH 267/326] Handle `Identifier` unsafety in stdarch-gen-arm

---
 crates/stdarch-gen-arm/src/big_endian.rs | 36 +++++++++++-------------
 crates/stdarch-gen-arm/src/expression.rs | 13 +++++++--
 crates/stdarch-gen-arm/src/intrinsic.rs  |  7 +++--
 3 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/crates/stdarch-gen-arm/src/big_endian.rs b/crates/stdarch-gen-arm/src/big_endian.rs
index b982ff53ec..f024ca074e 100644
--- a/crates/stdarch-gen-arm/src/big_endian.rs
+++ b/crates/stdarch-gen-arm/src/big_endian.rs
@@ -15,9 +15,9 @@ fn create_single_wild_string(name: &str) -> WildString {
 /// Creates an Identifier with name `name` with no wildcards. This, for example,
 /// can be used to create variables, function names or arbitrary input. Is is
 /// extremely flexible.
-pub fn create_symbol_identifier(arbitrary_string: &str) -> Expression {
+pub fn create_symbol_identifier(arbitrary_string: &str, kind: IdentifierType) -> Expression {
     let identifier_name = create_single_wild_string(arbitrary_string);
-    Expression::Identifier(identifier_name, IdentifierType::Symbol)
+    Expression::Identifier(identifier_name, kind)
 }
 
 /// To compose the simd_shuffle! call we need:
@@ -101,7 +101,6 @@ pub fn make_variable_mutable(variable_name: &str, type_kind: &TypeKind) -> Expre
 fn create_shuffle_internal(
     variable_name: &String,
     type_kind: &TypeKind,
-    fmt_tuple: fn(variable_name: &String, idx: u32, array_lanes: &String) -> String,
     fmt: fn(variable_name: &String, type_kind: &TypeKind, array_lanes: &String) -> String,
 ) -> Option<Expression> {
     let TypeKind::Vector(vector_type) = type_kind else {
@@ -120,14 +119,21 @@ fn create_shuffle_internal(
 
         /* <var_name>.idx = simd_shuffle!(<var_name>.idx, <var_name>.idx, [<indexes>]) */
         for idx in 0..tuple_count {
-            let formatted = fmt_tuple(variable_name, idx, &array_lanes);
+            let formatted =
+                create_assigned_tuple_shuffle_call_fmt(variable_name, idx, &array_lanes);
             string_builder += formatted.as_str();
         }
-        Some(create_symbol_identifier(&string_builder))
+        Some(create_symbol_identifier(
+            &string_builder,
+            IdentifierType::UnsafeSymbol,
+        ))
     } else {
         /* Generate a list of shuffles for each tuple */
         let expression = fmt(variable_name, type_kind, &array_lanes);
-        Some(create_symbol_identifier(&expression))
+        Some(create_symbol_identifier(
+            &expression,
+            IdentifierType::UnsafeSymbol,
+        ))
     }
 }
 
@@ -137,7 +143,7 @@ fn create_assigned_tuple_shuffle_call_fmt(
     array_lanes: &String,
 ) -> String {
     format!(
-        "{variable_name}.{idx} = unsafe {{ simd_shuffle!({variable_name}.{idx}, {variable_name}.{idx}, {array_lanes}) }};\n"
+        "{variable_name}.{idx} = simd_shuffle!({variable_name}.{idx}, {variable_name}.{idx}, {array_lanes});\n"
     )
 }
 
@@ -147,7 +153,7 @@ fn create_assigned_shuffle_call_fmt(
     array_lanes: &String,
 ) -> String {
     format!(
-        "let {variable_name}: {type_kind} = unsafe {{ simd_shuffle!({variable_name}, {variable_name}, {array_lanes}) }}"
+        "let {variable_name}: {type_kind} = simd_shuffle!({variable_name}, {variable_name}, {array_lanes})"
     )
 }
 
@@ -165,20 +171,10 @@ pub fn create_assigned_shuffle_call(
     variable_name: &String,
     type_kind: &TypeKind,
 ) -> Option<Expression> {
-    create_shuffle_internal(
-        variable_name,
-        type_kind,
-        create_assigned_tuple_shuffle_call_fmt,
-        create_assigned_shuffle_call_fmt,
-    )
+    create_shuffle_internal(variable_name, type_kind, create_assigned_shuffle_call_fmt)
 }
 
 /// Create a `simd_shuffle!(<...>, [...])` call
 pub fn create_shuffle_call(variable_name: &String, type_kind: &TypeKind) -> Option<Expression> {
-    create_shuffle_internal(
-        variable_name,
-        type_kind,
-        create_assigned_tuple_shuffle_call_fmt,
-        create_shuffle_call_fmt,
-    )
+    create_shuffle_internal(variable_name, type_kind, create_shuffle_call_fmt)
 }
diff --git a/crates/stdarch-gen-arm/src/expression.rs b/crates/stdarch-gen-arm/src/expression.rs
index 0b6ffef9d8..daaf7ee689 100644
--- a/crates/stdarch-gen-arm/src/expression.rs
+++ b/crates/stdarch-gen-arm/src/expression.rs
@@ -23,6 +23,7 @@ use crate::{
 pub enum IdentifierType {
     Variable,
     Symbol,
+    UnsafeSymbol,
 }
 
 #[derive(Debug, Clone, Serialize, Deserialize)]
@@ -65,7 +66,11 @@ impl FnCall {
     }
 
     pub fn is_expected_call(&self, fn_call_name: &str) -> bool {
-        if let Expression::Identifier(fn_name, IdentifierType::Symbol) = self.0.as_ref() {
+        if let Expression::Identifier(
+            fn_name,
+            IdentifierType::Symbol | IdentifierType::UnsafeSymbol,
+        ) = self.0.as_ref()
+        {
             fn_name.to_string() == fn_call_name
         } else {
             false
@@ -298,13 +303,15 @@ impl Expression {
         match self {
             // The call will need to be unsafe, but the declaration does not.
             Self::LLVMLink(..) => false,
-            // Identifiers, literals and type names are never unsafe.
-            Self::Identifier(..) => false,
+            // literals and type names are never unsafe.
             Self::IntConstant(..) => false,
             Self::FloatConstant(..) => false,
             Self::BoolConstant(..) => false,
             Self::Type(..) => false,
             Self::ConvertConst(..) => false,
+            // Only unsafe `Symbol` identifiers are unsafe
+            Self::Identifier(_, IdentifierType::UnsafeSymbol) => true,
+            Self::Identifier(..) => false,
             // Nested structures that aren't inherently unsafe, but could contain other expressions
             // that might be.
             Self::Assign(_var, exp) => exp.requires_unsafe_wrapper(ctx_fn),
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index 612c913d26..ab80b499b0 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1191,9 +1191,10 @@ impl Intrinsic {
                      * re-assigning each tuple however those generated calls do
                      * not make the parent function return. So we add the return
                      * value here */
-                    variant
-                        .big_endian_compose
-                        .push(create_symbol_identifier(&ret_val_name));
+                    variant.big_endian_compose.push(create_symbol_identifier(
+                        &ret_val_name,
+                        IdentifierType::Symbol,
+                    ));
                 }
             }
         }

From 8dc0c0e363e9e6ad17ef78566cca39e6b85a8d6b Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 30 Apr 2026 08:39:51 +0530
Subject: [PATCH 268/326] Remove all unneeded `unsafe` from stdarch-gen-arm

---
 .../core_arch/src/aarch64/neon/generated.rs   |  264 +--
 .../src/arm_shared/neon/generated.rs          | 1470 +++++++++--------
 .../spec/neon/aarch64.spec.yml                |  120 +-
 .../spec/neon/arm_shared.spec.yml             |   82 +-
 4 files changed, 1005 insertions(+), 931 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 9c27dbdacf..fd7a04146b 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4299,8 +4299,8 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 2);
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]),
@@ -4318,9 +4318,9 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 4);
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         match LANE1 & 0b111 {
             0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
             1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
@@ -4347,8 +4347,8 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 ) -> int16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 3);
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
         match LANE1 & 0b11 {
             0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]),
             1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]),
@@ -4371,8 +4371,8 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 ) -> int32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 2);
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]),
@@ -4393,9 +4393,9 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 ) -> uint8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 4);
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         match LANE1 & 0b111 {
             0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
             1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
@@ -4422,8 +4422,8 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 ) -> uint16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 3);
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
         match LANE1 & 0b11 {
             0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]),
             1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]),
@@ -4446,8 +4446,8 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 ) -> uint32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 2);
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]),
@@ -4468,9 +4468,9 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 ) -> poly8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 4);
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         match LANE1 & 0b111 {
             0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
             1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
@@ -4497,8 +4497,8 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
 ) -> poly16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 3);
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
         match LANE1 & 0b11 {
             0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]),
             1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]),
@@ -4521,8 +4521,8 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 1);
-    let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };
     unsafe {
+        let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
         match LANE1 & 0b11 {
             0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
             1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
@@ -4545,8 +4545,8 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
 ) -> float64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };
     unsafe {
+        let b: float64x2_t = simd_shuffle!(b, b, [0, 1]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
@@ -4567,8 +4567,8 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };
     unsafe {
+        let b: int64x2_t = simd_shuffle!(b, b, [0, 1]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
@@ -4589,8 +4589,8 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };
     unsafe {
+        let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
@@ -4611,8 +4611,8 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 ) -> poly64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };
     unsafe {
+        let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]);
         match LANE1 & 0b1 {
             0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
             1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
@@ -4630,9 +4630,9 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 3);
-    let b: int8x16_t =
-        unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };
     unsafe {
+        let b: int8x16_t =
+            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         match LANE1 & 0b1111 {
             0 => simd_shuffle!(
                 a,
@@ -5003,8 +5003,8 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 ) -> int16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 2);
-    let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };
     unsafe {
+        let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
         match LANE1 & 0b111 {
             0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
             1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
@@ -5031,8 +5031,8 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 1);
-    let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };
     unsafe {
+        let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
         match LANE1 & 0b11 {
             0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
             1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
@@ -5055,9 +5055,9 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 ) -> uint8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 3);
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };
     unsafe {
+        let b: uint8x16_t =
+            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         match LANE1 & 0b1111 {
             0 => simd_shuffle!(
                 a,
@@ -5428,8 +5428,8 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 ) -> uint16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 2);
-    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };
     unsafe {
+        let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
         match LANE1 & 0b111 {
             0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
             1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
@@ -5456,8 +5456,8 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 1);
-    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };
     unsafe {
+        let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
         match LANE1 & 0b11 {
             0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
             1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
@@ -5480,9 +5480,9 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 ) -> poly8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 3);
-    let b: poly8x16_t =
-        unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };
     unsafe {
+        let b: poly8x16_t =
+            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
         match LANE1 & 0b1111 {
             0 => simd_shuffle!(
                 a,
@@ -5853,8 +5853,8 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 ) -> poly16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 2);
-    let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };
     unsafe {
+        let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
         match LANE1 & 0b111 {
             0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
             1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
@@ -11701,8 +11701,8 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[cfg_attr(test, assert_instr(ld2r))]
 pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
     let mut ret_val: poly64x2x2_t = transmute(vld2q_dup_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -11728,8 +11728,8 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[cfg_attr(test, assert_instr(ld2r))]
 pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
     let mut ret_val: uint64x2x2_t = transmute(vld2q_dup_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
     ret_val
 }
 #[doc = "Load multiple 2-element structures to two registers"]
@@ -11904,8 +11904,8 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[cfg_attr(test, assert_instr(ld2))]
 pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
     let mut ret_val: poly64x2x2_t = transmute(vld2q_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
     ret_val
 }
 #[doc = "Load multiple 2-element structures to two registers"]
@@ -12085,9 +12085,9 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[cfg_attr(test, assert_instr(ld3r))]
 pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
     let mut ret_val: poly64x2x3_t = transmute(vld3q_dup_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -12113,9 +12113,9 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[cfg_attr(test, assert_instr(ld3r))]
 pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
     let mut ret_val: uint64x2x3_t = transmute(vld3q_dup_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
     ret_val
 }
 #[doc = "Load multiple 3-element structures to three registers"]
@@ -12293,9 +12293,9 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[cfg_attr(test, assert_instr(ld3))]
 pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
     let mut ret_val: poly64x2x3_t = transmute(vld3q_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
     ret_val
 }
 #[doc = "Load multiple 3-element structures to three registers"]
@@ -12477,10 +12477,10 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
     let mut ret_val: poly64x2x4_t = transmute(vld4q_dup_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -12506,10 +12506,10 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
     let mut ret_val: uint64x2x4_t = transmute(vld4q_dup_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
     ret_val
 }
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -12690,10 +12690,10 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[cfg_attr(test, assert_instr(ld4))]
 pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
     let mut ret_val: poly64x2x4_t = transmute(vld4q_s64(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
     ret_val
 }
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -19951,8 +19951,8 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
 pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vrbit_s8(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -19975,9 +19975,9 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
 pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(vrbitq_s8(transmute(a)));
         simd_shuffle!(
             ret_val,
@@ -20004,8 +20004,8 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
 pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vrbit_s8(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -20028,9 +20028,9 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
 pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(vrbitq_s8(transmute(a)));
         simd_shuffle!(
             ret_val,
@@ -20270,8 +20270,10 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
@@ -20293,8 +20295,8 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -20344,8 +20346,8 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -20391,8 +20393,10 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
@@ -20412,8 +20416,10 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
@@ -20433,8 +20439,8 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -20457,8 +20463,8 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -20715,8 +20721,10 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
@@ -20736,8 +20744,8 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -20760,8 +20768,8 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -20788,8 +20796,8 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -20812,8 +20820,8 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -20836,8 +20844,8 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -20860,8 +20868,8 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -20888,8 +20896,8 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -20912,8 +20920,8 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -20936,8 +20944,8 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -20960,8 +20968,8 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -20988,8 +20996,8 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -21012,8 +21020,8 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
-    let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21036,8 +21044,10 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
@@ -21057,9 +21067,9 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21082,8 +21092,10 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
@@ -21103,8 +21115,8 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21127,8 +21139,10 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
@@ -21148,8 +21162,8 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21190,8 +21204,8 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21214,8 +21228,8 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21238,8 +21252,10 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
@@ -21259,9 +21275,9 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21284,8 +21300,10 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
@@ -21305,8 +21323,8 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21329,8 +21347,10 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
@@ -21350,8 +21370,8 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21392,8 +21412,8 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21416,8 +21436,8 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21440,8 +21460,10 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
@@ -21461,9 +21483,9 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21486,8 +21508,10 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
@@ -21507,8 +21531,8 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21581,8 +21605,8 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -21605,8 +21629,8 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21629,8 +21653,8 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -21653,8 +21677,8 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index d31451c4a7..28a978fdbb 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -7309,8 +7309,8 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -7357,8 +7357,8 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -7405,8 +7405,8 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -7453,8 +7453,8 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -7501,8 +7501,8 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -7549,9 +7549,9 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
         simd_shuffle!(
             ret_val,
@@ -7644,8 +7644,8 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -7692,9 +7692,9 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
         simd_shuffle!(
             ret_val,
@@ -7745,8 +7745,8 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -7793,9 +7793,9 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
         simd_shuffle!(
             ret_val,
@@ -9620,10 +9620,10 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 )]
 pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
@@ -9681,11 +9681,11 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 )]
 pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: int8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: int8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
@@ -9743,10 +9743,10 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 )]
 pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
@@ -9804,11 +9804,11 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 )]
 pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: uint8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
@@ -9852,11 +9852,11 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x16_t =
+            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x4_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
@@ -9900,12 +9900,12 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: int8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: int8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x16_t =
+            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x4_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
@@ -9949,11 +9949,11 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x16_t =
+            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: uint32x4_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
@@ -9997,12 +9997,12 @@ pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x1
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: uint8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x16_t =
+            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: uint32x4_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
@@ -19057,8 +19057,8 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 )]
 pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
     let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19108,20 +19108,16 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 )]
 pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
     let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
+    ret_val.0 = simd_shuffle!(
+        ret_val.0,
+        ret_val.0,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.1 = simd_shuffle!(
+        ret_val.1,
+        ret_val.1,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19171,8 +19167,8 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 )]
 pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
     let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19222,8 +19218,8 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 )]
 pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
     let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19273,8 +19269,8 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 )]
 pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
     let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19324,8 +19320,8 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 )]
 pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
     let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19375,8 +19371,8 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 )]
 pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
     let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19426,20 +19422,16 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 )]
 pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
     let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
+    ret_val.0 = simd_shuffle!(
+        ret_val.0,
+        ret_val.0,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.1 = simd_shuffle!(
+        ret_val.1,
+        ret_val.1,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19489,8 +19481,8 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 )]
 pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
     let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -19540,8 +19532,8 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 )]
 pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
     let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
@@ -21336,9 +21328,9 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 )]
 pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
     let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21388,27 +21380,21 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 )]
 pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
     let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
+    ret_val.0 = simd_shuffle!(
+        ret_val.0,
+        ret_val.0,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.1 = simd_shuffle!(
+        ret_val.1,
+        ret_val.1,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.2 = simd_shuffle!(
+        ret_val.2,
+        ret_val.2,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21458,9 +21444,9 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 )]
 pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
     let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21510,9 +21496,9 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 )]
 pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
     let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21562,9 +21548,9 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 )]
 pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
     let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21614,9 +21600,9 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 )]
 pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
     let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21666,9 +21652,9 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 )]
 pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
     let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21718,27 +21704,21 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 )]
 pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
     let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
+    ret_val.0 = simd_shuffle!(
+        ret_val.0,
+        ret_val.0,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.1 = simd_shuffle!(
+        ret_val.1,
+        ret_val.1,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.2 = simd_shuffle!(
+        ret_val.2,
+        ret_val.2,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21788,9 +21768,9 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 )]
 pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
     let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
@@ -21840,9 +21820,9 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 )]
 pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
     let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
@@ -23617,10 +23597,10 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 )]
 pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
     let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -23670,34 +23650,26 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 )]
 pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
     let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.3 = unsafe {
-        simd_shuffle!(
-            ret_val.3,
-            ret_val.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
+    ret_val.0 = simd_shuffle!(
+        ret_val.0,
+        ret_val.0,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.1 = simd_shuffle!(
+        ret_val.1,
+        ret_val.1,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.2 = simd_shuffle!(
+        ret_val.2,
+        ret_val.2,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.3 = simd_shuffle!(
+        ret_val.3,
+        ret_val.3,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -23747,10 +23719,10 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 )]
 pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
     let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -23800,10 +23772,10 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 )]
 pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
     let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -23853,10 +23825,10 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 )]
 pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
     let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -23906,10 +23878,10 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 )]
 pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
     let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -23959,10 +23931,10 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 )]
 pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
     let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -24012,34 +23984,26 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 )]
 pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
     let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
-    ret_val.0 = unsafe {
-        simd_shuffle!(
-            ret_val.0,
-            ret_val.0,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.1 = unsafe {
-        simd_shuffle!(
-            ret_val.1,
-            ret_val.1,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.2 = unsafe {
-        simd_shuffle!(
-            ret_val.2,
-            ret_val.2,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
-    ret_val.3 = unsafe {
-        simd_shuffle!(
-            ret_val.3,
-            ret_val.3,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    };
+    ret_val.0 = simd_shuffle!(
+        ret_val.0,
+        ret_val.0,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.1 = simd_shuffle!(
+        ret_val.1,
+        ret_val.1,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.2 = simd_shuffle!(
+        ret_val.2,
+        ret_val.2,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
+    ret_val.3 = simd_shuffle!(
+        ret_val.3,
+        ret_val.3,
+        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+    );
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -24089,10 +24053,10 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 )]
 pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
     let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
@@ -24142,10 +24106,10 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 )]
 pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
     let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
-    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
     ret_val
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
@@ -39548,9 +39512,9 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -39597,9 +39561,9 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -39646,9 +39610,9 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
         let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -39991,8 +39955,8 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -40041,8 +40005,8 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -40091,8 +40055,8 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -40141,8 +40105,8 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -40191,8 +40155,10 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
@@ -40238,8 +40204,8 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -40288,8 +40254,8 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -40338,8 +40304,8 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -40388,8 +40354,10 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
@@ -40435,8 +40403,8 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -40485,8 +40453,8 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -40535,8 +40503,8 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -40585,8 +40553,8 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -40639,8 +40607,8 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -40689,8 +40657,8 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -40739,8 +40707,8 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -40789,8 +40757,8 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -40843,8 +40811,8 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -40893,8 +40861,8 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -40943,8 +40911,8 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -40993,8 +40961,8 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -41047,8 +41015,8 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41097,8 +41065,8 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41147,8 +41115,8 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41197,8 +41165,8 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41247,9 +41215,9 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41298,8 +41266,8 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41348,8 +41316,8 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41398,8 +41366,8 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41448,8 +41416,8 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41547,8 +41515,8 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41597,8 +41565,8 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41647,9 +41615,9 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41698,8 +41666,8 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41748,8 +41716,8 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41798,8 +41766,8 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -41848,8 +41816,8 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41947,8 +41915,8 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -41997,8 +41965,8 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -42047,9 +42015,9 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -42098,8 +42066,8 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -42148,8 +42116,8 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -42247,8 +42215,10 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
-    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
@@ -42294,8 +42264,10 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
@@ -42341,8 +42313,8 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
-    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -42440,8 +42412,8 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 )]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -42535,8 +42507,8 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -42583,8 +42555,8 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -42631,8 +42603,8 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -42679,8 +42651,10 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
@@ -42724,8 +42698,8 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -42772,8 +42746,8 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -42820,8 +42794,8 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -42868,8 +42842,10 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
@@ -42913,8 +42889,8 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -42961,8 +42937,8 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
-    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -43009,8 +42985,10 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
@@ -43054,8 +43032,8 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -43106,8 +43084,8 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -43154,8 +43132,8 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -43202,8 +43180,8 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -43250,8 +43228,8 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -43302,8 +43280,8 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -43350,8 +43328,8 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -43398,8 +43376,8 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -43446,8 +43424,8 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -43498,8 +43476,8 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
-    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -43546,8 +43524,8 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -43594,8 +43572,8 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -43642,8 +43620,8 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -43690,8 +43668,10 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
@@ -43735,8 +43715,8 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -43783,8 +43763,8 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -43831,8 +43811,8 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -43879,8 +43859,10 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
@@ -43924,8 +43906,8 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -43972,8 +43954,8 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -44020,9 +44002,9 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -44069,9 +44051,9 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -44118,9 +44100,9 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -44167,9 +44149,9 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -44216,9 +44198,9 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -44269,9 +44251,9 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -44318,9 +44300,9 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -44367,9 +44349,9 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -44416,9 +44398,9 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -44469,9 +44451,9 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -44518,8 +44500,8 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -44566,8 +44548,8 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -44614,8 +44596,8 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -44662,8 +44644,10 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
@@ -44707,8 +44691,8 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -44755,8 +44739,8 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -44803,8 +44787,8 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -44851,8 +44835,10 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
@@ -44896,8 +44882,8 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -44944,8 +44930,8 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -44992,8 +44978,8 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -45040,8 +45026,8 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -45092,8 +45078,8 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -45140,8 +45126,8 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -45188,8 +45174,8 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -45240,8 +45226,8 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -45288,8 +45274,8 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -45336,8 +45322,8 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -45384,8 +45370,8 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -45436,8 +45422,8 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -45484,8 +45470,8 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -45532,8 +45518,8 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -45580,8 +45566,8 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -45628,8 +45614,10 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
@@ -45673,8 +45661,8 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -45721,8 +45709,8 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -45769,8 +45757,8 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -45817,8 +45805,10 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
@@ -45862,8 +45852,8 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -45910,8 +45900,8 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -45958,8 +45948,8 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -46006,8 +45996,8 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -46058,8 +46048,8 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -46106,8 +46096,8 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -46154,8 +46144,8 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -46206,8 +46196,8 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -46254,8 +46244,8 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -46302,8 +46292,8 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -46350,8 +46340,8 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -46402,8 +46392,8 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -46894,8 +46884,8 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -46942,8 +46932,8 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -46994,8 +46984,8 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -47042,8 +47032,8 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -47090,8 +47080,8 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -47142,8 +47132,8 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -47190,8 +47180,8 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -47238,8 +47228,8 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -47286,8 +47276,8 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -47338,8 +47328,8 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -47386,8 +47376,8 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -47434,8 +47424,8 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -47482,8 +47472,8 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -47530,8 +47520,8 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -47578,8 +47568,10 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
@@ -47623,8 +47615,8 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -47671,8 +47663,8 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -47719,8 +47711,10 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
@@ -47764,8 +47758,8 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -47812,8 +47806,8 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -47860,9 +47854,9 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -47909,9 +47903,9 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -47962,9 +47956,9 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48011,9 +48005,9 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -48060,9 +48054,9 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -48109,9 +48103,9 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48158,9 +48152,9 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -48207,9 +48201,9 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -48256,9 +48250,9 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -48309,9 +48303,9 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48358,8 +48352,8 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -48406,8 +48400,8 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48454,8 +48448,8 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -48502,8 +48496,8 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -48550,8 +48544,10 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
@@ -48595,8 +48591,8 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48643,8 +48639,8 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -48691,8 +48687,10 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
@@ -48736,8 +48734,8 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48784,8 +48782,8 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -48832,8 +48830,8 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -48880,8 +48878,8 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -48932,8 +48930,8 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -48980,8 +48978,8 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49028,8 +49026,8 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -49076,8 +49074,8 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -49128,8 +49126,8 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49176,8 +49174,8 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -49224,8 +49222,8 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -49276,8 +49274,8 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -49324,8 +49322,8 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -49372,8 +49370,8 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -49420,8 +49418,8 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49468,8 +49466,8 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -49516,8 +49514,10 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
@@ -49561,8 +49561,8 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -49609,8 +49609,8 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49657,8 +49657,10 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
@@ -49702,8 +49704,8 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -49750,8 +49752,8 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49798,8 +49800,8 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49846,8 +49848,8 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -49898,8 +49900,8 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -49946,8 +49948,8 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -49994,8 +49996,8 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -50042,8 +50044,8 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -50094,8 +50096,8 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -50142,8 +50144,8 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -50190,8 +50192,8 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -50242,8 +50244,8 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -50734,8 +50736,8 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -50782,8 +50784,8 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -50834,8 +50836,8 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -50882,8 +50884,8 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -50930,8 +50932,8 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -50978,8 +50980,8 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -51030,8 +51032,8 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -51078,8 +51080,8 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -51126,8 +51128,8 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -51178,8 +51180,8 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -51226,8 +51228,8 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -51274,8 +51276,8 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -51322,8 +51324,8 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -51370,8 +51372,8 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -51418,8 +51420,10 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
@@ -51463,8 +51467,8 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -51511,8 +51515,8 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -51559,8 +51563,8 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -51607,8 +51611,10 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
@@ -51652,8 +51658,8 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -51700,9 +51706,9 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -51749,9 +51755,9 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -51802,9 +51808,9 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -51851,9 +51857,9 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -51900,9 +51906,9 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -51949,9 +51955,9 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -52002,9 +52008,9 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -52051,9 +52057,9 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -52100,9 +52106,9 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -52149,9 +52155,9 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -52198,8 +52204,8 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -52246,8 +52252,8 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -52294,8 +52300,8 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -52342,8 +52348,8 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -52390,8 +52396,10 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
@@ -52435,8 +52443,8 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -52483,8 +52491,8 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -52531,8 +52539,8 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -52579,8 +52587,10 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
@@ -52624,8 +52634,8 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -52672,8 +52682,8 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -52720,8 +52730,8 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -52772,8 +52782,8 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -52820,8 +52830,8 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -52868,8 +52878,8 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -52916,8 +52926,8 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -52968,8 +52978,8 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -53016,8 +53026,8 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -53064,8 +53074,8 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -53112,8 +53122,8 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -53693,8 +53703,10 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
@@ -53738,9 +53750,11 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
@@ -53784,9 +53798,9 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
-    let a: int8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -53833,8 +53847,10 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
-    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
@@ -53878,8 +53894,10 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
@@ -53923,8 +53941,8 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
-    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -53971,8 +53989,10 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
@@ -54016,8 +54036,10 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
@@ -54061,8 +54083,8 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -54109,8 +54131,10 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
@@ -54154,8 +54178,10 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
@@ -54199,9 +54225,11 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
@@ -54245,9 +54273,9 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
-    let a: uint8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -54294,8 +54322,10 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
-    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
@@ -54339,8 +54369,10 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
@@ -54384,8 +54416,8 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -54432,8 +54464,10 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
-    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
@@ -54477,8 +54511,10 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
@@ -54522,8 +54558,8 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -54570,8 +54606,10 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
@@ -54615,8 +54653,10 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
@@ -54660,9 +54700,11 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
@@ -54706,9 +54748,9 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
-    let a: poly8x16_t =
-        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -54755,8 +54797,10 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
-    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
@@ -54800,8 +54844,10 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
@@ -54845,8 +54891,8 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
-    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -55269,8 +55315,10 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(a) }
+    unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
+    }
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
@@ -55314,8 +55362,8 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -55366,8 +55414,8 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -55414,8 +55462,8 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -55462,8 +55510,8 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -55514,8 +55562,8 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -55562,8 +55610,8 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -55610,8 +55658,8 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -55662,8 +55710,8 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
-    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
     unsafe {
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -58727,9 +58775,9 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
-    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -58776,9 +58824,9 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
-    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
     unsafe {
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
         let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
@@ -58825,9 +58873,9 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
-    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
     unsafe {
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
         let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
@@ -70468,10 +70516,10 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 )]
 pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: int32x2_t = vusdot_s32(a, transmute(c), b);
@@ -70529,11 +70577,11 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 )]
 pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: int8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: int8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
@@ -70630,9 +70678,9 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -70659,9 +70707,9 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -70715,10 +70763,10 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
     let mut a: uint8x8x2_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -70746,10 +70794,10 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
     let mut a: poly8x8x2_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -70810,11 +70858,11 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
     let mut a: uint8x8x3_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbl3(
             transmute(a.0),
             transmute(a.1),
@@ -70854,11 +70902,11 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
     let mut a: poly8x8x3_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbl3(
             transmute(a.0),
             transmute(a.1),
@@ -70925,12 +70973,12 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
     let mut a: uint8x8x4_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbl4(
             transmute(a.0),
             transmute(a.1),
@@ -70972,12 +71020,12 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(vtbl))]
 pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
     let mut a: poly8x8x4_t = a;
-    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbl4(
             transmute(a.0),
             transmute(a.1),
@@ -71032,10 +71080,10 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -71060,10 +71108,10 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
@@ -71120,11 +71168,11 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
     let mut b: uint8x8x2_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbx2(
             transmute(a),
             transmute(b.0),
@@ -71162,11 +71210,11 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
     let mut b: poly8x8x2_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbx2(
             transmute(a),
             transmute(b.0),
@@ -71229,12 +71277,12 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
     let mut b: uint8x8x3_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbx3(
             transmute(a),
             transmute(b.0),
@@ -71274,12 +71322,12 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
     let mut b: poly8x8x3_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbx3(
             transmute(a),
             transmute(b.0),
@@ -71341,13 +71389,13 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
     let mut b: int8x8x4_t = b;
-    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: int8x8_t = vtbx4(
             a,
             transmute(b.0),
@@ -71389,13 +71437,13 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
     let mut b: uint8x8x4_t = b;
-    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: uint8x8_t = transmute(vtbx4(
             transmute(a),
             transmute(b.0),
@@ -71437,13 +71485,13 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(vtbx))]
 pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
     let mut b: poly8x8x4_t = b;
-    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
+        b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly8x8_t = transmute(vtbx4(
             transmute(a),
             transmute(b.0),
@@ -72511,10 +72559,10 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 )]
 pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
@@ -72572,11 +72620,11 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 )]
 pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: uint8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
@@ -72620,11 +72668,11 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x16_t =
+            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x4_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
@@ -72668,12 +72716,12 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
-    let b: uint8x16_t =
-        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
-    let c: int8x16_t =
-        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
     unsafe {
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let b: uint8x16_t =
+            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let c: int8x16_t =
+            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x4_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index d55ea0b770..e37f9f124b 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -2670,11 +2670,11 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [poly64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
-      - [float64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
+      - [poly64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - [float64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
-      - Identifier: ["{type[2]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 1]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
   - name: "vmla{neon_type.no}"
     doc: "Floating-point multiply-add to accumulator"
@@ -8944,19 +8944,19 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
+      - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", Symbol]
+      - Identifier: ["{type[5]}", UnsafeSymbol]
 
   - name: "vcopy{neon_type[0].lane_nox}"
     doc: "Insert vector element from another vector element"
@@ -8969,19 +8969,19 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
+      - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", Symbol]
-      - Identifier: ["{type[6]}", Symbol]
+      - Identifier: ["{type[5]}", UnsafeSymbol]
+      - Identifier: ["{type[6]}", UnsafeSymbol]
 
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
@@ -8994,23 +8994,23 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
+      - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", Symbol]
+      - Identifier: ["{type[5]}", UnsafeSymbol]
 
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
@@ -9023,20 +9023,20 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
+      - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", Symbol]
-      - Identifier: ["{type[6]}", Symbol]
+      - Identifier: ["{type[5]}", UnsafeSymbol]
+      - Identifier: ["{type[6]}", UnsafeSymbol]
 
   - name: "vcopyq_lane_{neon_type[0]}"
     doc: "Insert vector element from another vector element"
@@ -9049,15 +9049,15 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int64x2_t, int64x1_t, ' let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [uint64x2_t, uint64x1_t, ' let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [poly64x2_t, poly64x1_t, ' let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
-      - [float64x2_t, float64x1_t, ' let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
+      - [int64x2_t, int64x1_t, ' let b: int64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [uint64x2_t, uint64x1_t, ' let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [poly64x2_t, poly64x1_t, ' let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [float64x2_t, float64x1_t, ' let b: float64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '1']]
       - FnCall: [static_assert!, ['LANE2 == 0']]
-      - Identifier: ['{type[2]}', Symbol]
-      - Identifier: ['{type[3]}', Symbol]
+      - Identifier: ['{type[2]}', UnsafeSymbol]
+      - Identifier: ['{type[3]}', UnsafeSymbol]
 
   - name: "vcopyq_lane_f32"
     doc: "Insert vector element from another vector element"
@@ -9070,12 +9070,12 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [float32x4_t, float32x2_t, ' let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }']
+      - [float32x4_t, float32x2_t, ' let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, 2]]
       - FnCall: [static_assert_uimm_bits!, [LANE2, 1]]
-      - Identifier: ["{type[2]}", Symbol]
-      - Identifier: ["{type[3]}", Symbol]
+      - Identifier: ["{type[2]}", UnsafeSymbol]
+      - Identifier: ["{type[3]}", UnsafeSymbol]
 
   - name: "vcreate_f64"
     doc: "Insert vector element from another vector element"
@@ -13366,7 +13366,7 @@ intrinsics:
           links:
             - link: "llvm.aarch64.neon.saddlv.i32.{neon_type[0]}"
               arch: aarch64,arm64ec
-      - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as i16 }}", Symbol]
+      - Identifier: ["_vaddlv{neon_type[0].no}(a) as i16", UnsafeSymbol]
 
   - name: "vaddlv{neon_type[0].no}"
     doc: "Unsigned Add Long across Vector"
@@ -13386,7 +13386,7 @@ intrinsics:
           links:
             - link: "llvm.aarch64.neon.uaddlv.i32.{neon_type[0]}"
               arch: aarch64,arm64ec
-      - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as u16 }}", Symbol]
+      - Identifier: ["_vaddlv{neon_type[0].no}(a) as u16", UnsafeSymbol]
 
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 60fa830e5d..7b8ddf4374 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -1729,15 +1729,15 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
-      - [int16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
-      - [uint8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
-      - [uint16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
-      - [poly8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
-      - [poly16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
+      - [int8x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - [int16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - [uint8x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - [uint16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - [poly8x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - [poly16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
-      - Identifier: ["{type[2]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 3]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
   - name: "vext{neon_type[0].no}"
     doc: "Extract vector from pair of vectors"
@@ -1753,12 +1753,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }']
-      - [uint8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }']
-      - [poly8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }']
+      - [int8x16_t, 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }']
+      - [uint8x16_t, 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }']
+      - [poly8x16_t, 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
-      - Identifier: ["{type[2]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 4]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
   - name: "vext{neon_type[0].no}"
     doc: "Extract vector from pair of vectors"
@@ -1774,15 +1774,15 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x4_t, 'static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
-      - [int32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
-      - [uint16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
-      - [uint32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
-      - [poly16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
-      - [float32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
+      - [int16x4_t,'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - [int32x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - [uint16x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - [uint32x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - [poly16x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - [float32x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
-      - Identifier: ["{type[2]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 2]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
 
   - name: "vext{neon_type[0].no}"
@@ -1801,9 +1801,10 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [float16x4_t, ' static_assert_uimm_bits!(N, 2); unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }']
+      - [float16x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 2]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
   - name: "vext{neon_type[0].no}"
     doc: "Extract vector from pair of vectors"
@@ -1821,9 +1822,10 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [float16x8_t, ' static_assert_uimm_bits!(N, 3); unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }']
+      - [float16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 3]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
 
 
@@ -1841,12 +1843,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
-      - [uint32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
-      - [float32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
+      - [int32x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - [uint32x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - [float32x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
-      - Identifier: ["{type[2]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 1]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
   - name: "vext{neon_type[0].no}"
     doc: "Extract vector from pair of vectors"
@@ -1862,11 +1864,11 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
-      - [uint64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }']
+      - [int64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - [uint64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
     compose:
-      - Identifier: ["{type[1]}", Symbol]
-      - Identifier: ["{type[2]}", Symbol]
+      - FnCall: [static_assert_uimm_bits!, [N, 1]]
+      - Identifier: ["{type[1]}", UnsafeSymbol]
 
   - name: "vmla{neon_type[0].no}"
     doc: "Multiply-add to accumulator"
@@ -15007,10 +15009,10 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'vmov', 'ext', 'unsafe { int64x1_t([simd_extract!(a, 1)]) }']
-      - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'vmov', 'ext', 'unsafe { uint64x1_t([simd_extract!(a, 1)]) }']
+      - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'vmov', 'ext', 'int64x1_t([simd_extract!(a, 1)])']
+      - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'vmov', 'ext', 'uint64x1_t([simd_extract!(a, 1)])']
     compose:
-      - Identifier: ['{type[5]}', Symbol]
+      - Identifier: ['{type[5]}', UnsafeSymbol]
 
   - name: "{type[0]}"
     doc: "Duplicate vector element to vector or scalar"
@@ -15023,10 +15025,10 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'unsafe { int64x1_t([simd_extract!(a, 0)]) }']
-      - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'unsafe { uint64x1_t([simd_extract!(a, 0)]) }']
+      - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'int64x1_t([simd_extract!(a, 0)])']
+      - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'uint64x1_t([simd_extract!(a, 0)])']
     compose:
-      - Identifier: ['{type[3]}', Symbol]
+      - Identifier: ['{type[3]}', UnsafeSymbol]
 
   - name: "{type[0]}"
     doc: "Duplicate vector element to vector or scalar"

From 6d7929aa4e5acf8f7aa7bf9c16794f980e28fdd4 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 30 Apr 2026 06:54:09 +0530
Subject: [PATCH 269/326] Fix `fixupimm`

---
 crates/core_arch/src/x86/avx512f.rs | 80 ++++++++++++++---------------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 2c5002a2d0..94c4269c8f 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -42633,7 +42633,7 @@ pub fn _mm_mask3_fnmsub_round_sd<const ROUNDING: i32>(
     }
 }
 
-/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.
+/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_ss&expand=2517)
 #[inline]
@@ -42649,12 +42649,12 @@ pub fn _mm_fixupimm_ss<const IMM8: i32>(a: __m128, b: __m128, c: __m128i) -> __m
         let c = c.as_i32x4();
         let r = vfixupimmss(a, b, c, IMM8, 0b11111111, _MM_FROUND_CUR_DIRECTION);
         let fixupimm: f32 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.
+/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_ss&expand=2518)
 #[inline]
@@ -42675,12 +42675,12 @@ pub fn _mm_mask_fixupimm_ss<const IMM8: i32>(
         let c = c.as_i32x4();
         let fixupimm = vfixupimmss(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION);
         let fixupimm: f32 = simd_extract!(fixupimm, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.
+/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_ss&expand=2519)
 #[inline]
@@ -42701,12 +42701,12 @@ pub fn _mm_maskz_fixupimm_ss<const IMM8: i32>(
         let c = c.as_i32x4();
         let fixupimm = vfixupimmssz(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION);
         let fixupimm: f32 = simd_extract!(fixupimm, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.
+/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_sd&expand=2514)
 #[inline]
@@ -42722,12 +42722,12 @@ pub fn _mm_fixupimm_sd<const IMM8: i32>(a: __m128d, b: __m128d, c: __m128i) -> _
         let c = c.as_i64x2();
         let fixupimm = vfixupimmsd(a, b, c, IMM8, 0b11111111, _MM_FROUND_CUR_DIRECTION);
         let fixupimm: f64 = simd_extract!(fixupimm, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.
+/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_sd&expand=2515)
 #[inline]
@@ -42748,12 +42748,12 @@ pub fn _mm_mask_fixupimm_sd<const IMM8: i32>(
         let c = c.as_i64x2();
         let fixupimm = vfixupimmsd(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION);
         let fixupimm: f64 = simd_extract!(fixupimm, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.
+/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_sd&expand=2516)
 #[inline]
@@ -42774,12 +42774,12 @@ pub fn _mm_maskz_fixupimm_sd<const IMM8: i32>(
         let c = c.as_i64x2();
         let fixupimm = vfixupimmsdz(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION);
         let fixupimm: f64 = simd_extract!(fixupimm, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\
+/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\
 /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_ss&expand=2511)
@@ -42801,12 +42801,12 @@ pub fn _mm_fixupimm_round_ss<const IMM8: i32, const SAE: i32>(
         let c = c.as_i32x4();
         let r = vfixupimmss(a, b, c, IMM8, 0b11111111, SAE);
         let fixupimm: f32 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\
+/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\
 /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_ss&expand=2512)
@@ -42829,12 +42829,12 @@ pub fn _mm_mask_fixupimm_round_ss<const IMM8: i32, const SAE: i32>(
         let c = c.as_i32x4();
         let r = vfixupimmss(a, b, c, IMM8, k, SAE);
         let fixupimm: f32 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\
+/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\
 /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_ss&expand=2513)
@@ -42857,12 +42857,12 @@ pub fn _mm_maskz_fixupimm_round_ss<const IMM8: i32, const SAE: i32>(
         let c = c.as_i32x4();
         let r = vfixupimmssz(a, b, c, IMM8, k, SAE);
         let fixupimm: f32 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\
+/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\
 /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_sd&expand=2508)
@@ -42884,12 +42884,12 @@ pub fn _mm_fixupimm_round_sd<const IMM8: i32, const SAE: i32>(
         let c = c.as_i64x2();
         let r = vfixupimmsd(a, b, c, IMM8, 0b11111111, SAE);
         let fixupimm: f64 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\
+/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\
 /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_sd&expand=2509)
@@ -42912,12 +42912,12 @@ pub fn _mm_mask_fixupimm_round_sd<const IMM8: i32, const SAE: i32>(
         let c = c.as_i64x2();
         let r = vfixupimmsd(a, b, c, IMM8, k, SAE);
         let fixupimm: f64 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
 
-/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\
+/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\
 /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_sd&expand=2510)
@@ -42940,7 +42940,7 @@ pub fn _mm_maskz_fixupimm_round_sd<const IMM8: i32, const SAE: i32>(
         let c = c.as_i64x2();
         let r = vfixupimmsdz(a, b, c, IMM8, k, SAE);
         let fixupimm: f64 = simd_extract!(r, 0);
-        let r = simd_insert!(a, 0, fixupimm);
+        let r = simd_insert!(b, 0, fixupimm);
         transmute(r)
     }
 }
@@ -61830,7 +61830,7 @@ mod tests {
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
         let r = _mm_fixupimm_ss::<5>(a, b, c);
-        let e = _mm_set_ps(0., 0., 0., -0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0);
         assert_eq_m128(r, e);
     }
 
@@ -61840,7 +61840,7 @@ mod tests {
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
         let r = _mm_mask_fixupimm_ss::<5>(a, 0b11111111, b, c);
-        let e = _mm_set_ps(0., 0., 0., -0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0);
         assert_eq_m128(r, e);
     }
 
@@ -61850,10 +61850,10 @@ mod tests {
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
         let r = _mm_maskz_fixupimm_ss::<5>(0b00000000, a, b, c);
-        let e = _mm_set_ps(0., 0., 0., 0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, 0.0);
         assert_eq_m128(r, e);
         let r = _mm_maskz_fixupimm_ss::<5>(0b11111111, a, b, c);
-        let e = _mm_set_ps(0., 0., 0., -0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0);
         assert_eq_m128(r, e);
     }
 
@@ -61863,7 +61863,7 @@ mod tests {
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
         let r = _mm_fixupimm_sd::<5>(a, b, c);
-        let e = _mm_set_pd(0., -0.0);
+        let e = _mm_set_pd(f64::MAX, -0.0);
         assert_eq_m128d(r, e);
     }
 
@@ -61873,7 +61873,7 @@ mod tests {
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
         let r = _mm_mask_fixupimm_sd::<5>(a, 0b11111111, b, c);
-        let e = _mm_set_pd(0., -0.0);
+        let e = _mm_set_pd(f64::MAX, -0.0);
         assert_eq_m128d(r, e);
     }
 
@@ -61883,10 +61883,10 @@ mod tests {
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
         let r = _mm_maskz_fixupimm_sd::<5>(0b00000000, a, b, c);
-        let e = _mm_set_pd(0., 0.0);
+        let e = _mm_set_pd(f64::MAX, 0.0);
         assert_eq_m128d(r, e);
         let r = _mm_maskz_fixupimm_sd::<5>(0b11111111, a, b, c);
-        let e = _mm_set_pd(0., -0.0);
+        let e = _mm_set_pd(f64::MAX, -0.0);
         assert_eq_m128d(r, e);
     }
 
@@ -61896,7 +61896,7 @@ mod tests {
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
         let r = _mm_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
-        let e = _mm_set_ps(1., 0., 0., -0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0);
         assert_eq_m128(r, e);
     }
 
@@ -61906,7 +61906,7 @@ mod tests {
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
         let r = _mm_mask_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c);
-        let e = _mm_set_ps(0., 0., 0., -0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0);
         assert_eq_m128(r, e);
     }
 
@@ -61916,10 +61916,10 @@ mod tests {
         let b = _mm_set1_ps(f32::MAX);
         let c = _mm_set1_epi32(i32::MAX);
         let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c);
-        let e = _mm_set_ps(0., 0., 0., 0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, 0.0);
         assert_eq_m128(r, e);
         let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c);
-        let e = _mm_set_ps(0., 0., 0., -0.0);
+        let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0);
         assert_eq_m128(r, e);
     }
 
@@ -61929,7 +61929,7 @@ mod tests {
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
         let r = _mm_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
-        let e = _mm_set_pd(0., -0.0);
+        let e = _mm_set_pd(f64::MAX, -0.0);
         assert_eq_m128d(r, e);
     }
 
@@ -61939,7 +61939,7 @@ mod tests {
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
         let r = _mm_mask_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c);
-        let e = _mm_set_pd(0., -0.0);
+        let e = _mm_set_pd(f64::MAX, -0.0);
         assert_eq_m128d(r, e);
     }
 
@@ -61949,10 +61949,10 @@ mod tests {
         let b = _mm_set1_pd(f64::MAX);
         let c = _mm_set1_epi64x(i32::MAX as i64);
         let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c);
-        let e = _mm_set_pd(0., 0.0);
+        let e = _mm_set_pd(f64::MAX, 0.0);
         assert_eq_m128d(r, e);
         let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c);
-        let e = _mm_set_pd(0., -0.0);
+        let e = _mm_set_pd(f64::MAX, -0.0);
         assert_eq_m128d(r, e);
     }
 

From 4ba4f077b8f306b21aa10d78fc0f1359d745bc6f Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 4 May 2026 05:12:53 +0000
Subject: [PATCH 270/326] Prepare for merging from rust-lang/rust

This updates the rust-version file to 045b17737dab5fcc28e4cbee0cfe2ce4ed363b32.
---
 rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-version b/rust-version
index e9fc6c4cd0..59e9e5a0e6 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-e22c616e4e87914135c1db261a03e0437255335e
+045b17737dab5fcc28e4cbee0cfe2ce4ed363b32

From 324f2fd91111270ebf844cdf2a295cb62b6c3c76 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 30 Apr 2026 03:49:51 +0530
Subject: [PATCH 271/326] some changes in argument loading in intrinsic-test

revert the offset loading, instead load in a wrapping fashion
---
 crates/intrinsic-test/src/common/argument.rs | 26 +++++++++++---------
 crates/intrinsic-test/src/common/gen_c.rs    |  7 ------
 crates/intrinsic-test/src/common/gen_rust.rs |  6 -----
 3 files changed, 15 insertions(+), 24 deletions(-)

diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 413d5314d3..8ae9869db0 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -1,5 +1,6 @@
 use super::cli::Language;
 use super::constraint::Constraint;
+use super::gen_rust::PASSES;
 use super::indentation::Indentation;
 use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
@@ -178,7 +179,7 @@ where
             .enumerate()
             .map(|(idx, arg)| {
                 format!(
-                    "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[i+{idx}]));\n",
+                    "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[(i+{idx}) % {PASSES}]));\n",
                     ty = arg.to_c_type(),
                     name = arg.generate_name(),
                     load = if arg.is_simd() {
@@ -199,17 +200,20 @@ where
             .filter(|&arg| !arg.has_constraint())
             .enumerate()
             .map(|(idx, arg)| {
-                let load = if arg.is_simd() {
-                    arg.ty.get_load_function(Language::Rust)
+                if arg.is_simd() {
+                    format!(
+                        "{indentation}let {name} = {load}({vals_name}.as_ptr().add((i+{idx}) % {PASSES}) as _);\n",
+                        name = arg.generate_name(),
+                        vals_name = arg.rust_vals_array_name(),
+                        load = arg.ty.get_load_function(Language::Rust),
+                    )
                 } else {
-                    "*".to_string()
-                };
-                let typecast = if load.len() > 2 { "as _" } else { "" };
-                format!(
-                    "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i+{idx}){typecast});\n",
-                    name = arg.generate_name(),
-                    vals_name = arg.rust_vals_array_name(),
-                )
+                    format!(
+                        "{indentation}let {name} = {vals_name}[(i+{idx}) % {PASSES}];\n",
+                        name = arg.generate_name(),
+                        vals_name = arg.rust_vals_array_name(),
+                    )
+                }
             })
             .collect()
     }
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index 12b5a600d5..a95b4c36b7 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -25,13 +25,6 @@ pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(
     passes: u32,
 ) -> std::io::Result<()> {
     let body_indentation = indentation.nested();
-    // Successive arguments are offset increasingly from their value array start
-    let passes = passes + 1
-        - intrinsic
-            .arguments
-            .iter()
-            .filter(|&arg| !arg.has_constraint())
-            .count() as u32;
     writeln!(
         w,
         "{indentation}for (int i=0; i<{passes}; i++) {{\n\
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index 5a0bc7b4d4..82b97701bb 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -214,12 +214,6 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
     passes: u32,
 ) -> std::io::Result<()> {
     let intrinsic_name = &intrinsic.name;
-    let passes = passes + 1
-        - intrinsic
-            .arguments
-            .iter()
-            .filter(|&arg| !arg.has_constraint())
-            .count() as u32;
 
     // Each function (and each specialization) has its own type. Erase that type with a cast.
     let mut coerce = String::from("unsafe fn(");

From 192eb41910fd4f03ce1f955bff15e7f649290ac6 Mon Sep 17 00:00:00 2001
From: James Barford-Evans <james.barford-evans@arm.com>
Date: Wed, 6 May 2026 16:27:55 +0100
Subject: [PATCH 272/326] Remove #[inline(always)] from Arm intrinsic generator
 & re-generate intrinsics

---
 .../core_arch/src/aarch64/neon/generated.rs   | 3870 ++++-----
 crates/core_arch/src/aarch64/sve/generated.rs | 7328 ++++++++---------
 .../core_arch/src/aarch64/sve2/generated.rs   | 3774 ++++-----
 .../src/arm_shared/neon/generated.rs          | 6420 +++++++--------
 crates/stdarch-gen-arm/src/intrinsic.rs       |    2 +-
 5 files changed, 10697 insertions(+), 10697 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index fd7a04146b..898ccfc9ed 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "CRC32-C single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32cx))]
 #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
@@ -30,7 +30,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32 single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32x))]
 #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
@@ -46,7 +46,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 }
 #[doc = "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__jcvt)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "jsconv")]
 #[cfg_attr(test, assert_instr(fjcvtzs))]
 #[stable(feature = "stdarch_aarch64_jscvt", since = "1.95.0")]
@@ -62,7 +62,7 @@ pub fn __jcvt(a: f64) -> i32 {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -77,7 +77,7 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -92,7 +92,7 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -107,7 +107,7 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -121,7 +121,7 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -135,7 +135,7 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -149,7 +149,7 @@ pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -165,7 +165,7 @@ pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -181,7 +181,7 @@ pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -190,7 +190,7 @@ pub fn vabdd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -199,7 +199,7 @@ pub fn vabds_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -209,7 +209,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -223,7 +223,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -237,7 +237,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -251,7 +251,7 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -264,7 +264,7 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -277,7 +277,7 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -290,7 +290,7 @@ pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fabs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -299,7 +299,7 @@ pub fn vabs_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fabs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -308,7 +308,7 @@ pub fn vabsq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -321,7 +321,7 @@ pub fn vabs_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -334,7 +334,7 @@ pub fn vabsq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -350,7 +350,7 @@ pub fn vabsd_s64(a: i64) -> i64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -359,7 +359,7 @@ pub fn vaddd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -368,7 +368,7 @@ pub fn vaddd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -384,7 +384,7 @@ pub fn vaddlv_s16(a: int16x4_t) -> i32 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -400,7 +400,7 @@ pub fn vaddlvq_s16(a: int16x8_t) -> i32 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -416,7 +416,7 @@ pub fn vaddlvq_s32(a: int32x4_t) -> i64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlp))]
@@ -432,7 +432,7 @@ pub fn vaddlv_s32(a: int32x2_t) -> i64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -448,7 +448,7 @@ pub fn vaddlv_s8(a: int8x8_t) -> i16 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -464,7 +464,7 @@ pub fn vaddlvq_s8(a: int8x16_t) -> i16 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -480,7 +480,7 @@ pub fn vaddlv_u16(a: uint16x4_t) -> u32 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -496,7 +496,7 @@ pub fn vaddlvq_u16(a: uint16x8_t) -> u32 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -512,7 +512,7 @@ pub fn vaddlvq_u32(a: uint32x4_t) -> u64 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlp))]
@@ -528,7 +528,7 @@ pub fn vaddlv_u32(a: uint32x2_t) -> u64 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -544,7 +544,7 @@ pub fn vaddlv_u8(a: uint8x8_t) -> u16 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -560,7 +560,7 @@ pub fn vaddlvq_u8(a: uint8x16_t) -> u16 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -576,7 +576,7 @@ pub fn vaddv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -592,7 +592,7 @@ pub fn vaddvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -608,7 +608,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -617,7 +617,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -626,7 +626,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -635,7 +635,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -644,7 +644,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -653,7 +653,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -662,7 +662,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -671,7 +671,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -680,7 +680,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -689,7 +689,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -698,7 +698,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -707,7 +707,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -716,7 +716,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -725,7 +725,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -734,7 +734,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -750,7 +750,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -766,7 +766,7 @@ pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -782,7 +782,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -798,7 +798,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -814,7 +814,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -830,7 +830,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -846,7 +846,7 @@ pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -862,7 +862,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -878,7 +878,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -894,7 +894,7 @@ pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -910,7 +910,7 @@ pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -926,7 +926,7 @@ pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -942,7 +942,7 @@ pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -958,7 +958,7 @@ pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -974,7 +974,7 @@ pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -990,7 +990,7 @@ pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -1006,7 +1006,7 @@ pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -1022,7 +1022,7 @@ pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1040,7 +1040,7 @@ pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1058,7 +1058,7 @@ pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1074,7 +1074,7 @@ pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1090,7 +1090,7 @@ pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1106,7 +1106,7 @@ pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1124,7 +1124,7 @@ pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1142,7 +1142,7 @@ pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1158,7 +1158,7 @@ pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1174,7 +1174,7 @@ pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1190,7 +1190,7 @@ pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1206,7 +1206,7 @@ pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1222,7 +1222,7 @@ pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1238,7 +1238,7 @@ pub fn vcaged_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1254,7 +1254,7 @@ pub fn vcages_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(facge))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1271,7 +1271,7 @@ pub fn vcageh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1287,7 +1287,7 @@ pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1303,7 +1303,7 @@ pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1319,7 +1319,7 @@ pub fn vcagtd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1335,7 +1335,7 @@ pub fn vcagts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(facgt))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1352,7 +1352,7 @@ pub fn vcagth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1361,7 +1361,7 @@ pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1370,7 +1370,7 @@ pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1379,7 +1379,7 @@ pub fn vcaled_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1388,7 +1388,7 @@ pub fn vcales_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(facge))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1398,7 +1398,7 @@ pub fn vcaleh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1407,7 +1407,7 @@ pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1416,7 +1416,7 @@ pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1425,7 +1425,7 @@ pub fn vcaltd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1434,7 +1434,7 @@ pub fn vcalts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(facgt))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1444,7 +1444,7 @@ pub fn vcalth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1453,7 +1453,7 @@ pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1462,7 +1462,7 @@ pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1471,7 +1471,7 @@ pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1480,7 +1480,7 @@ pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1489,7 +1489,7 @@ pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1498,7 +1498,7 @@ pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1507,7 +1507,7 @@ pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1516,7 +1516,7 @@ pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1525,7 +1525,7 @@ pub fn vceqd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1534,7 +1534,7 @@ pub fn vceqs_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1543,7 +1543,7 @@ pub fn vceqd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1552,7 +1552,7 @@ pub fn vceqd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1562,7 +1562,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -1573,7 +1573,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -1584,7 +1584,7 @@ pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1594,7 +1594,7 @@ pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1604,7 +1604,7 @@ pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1614,7 +1614,7 @@ pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1624,7 +1624,7 @@ pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1634,7 +1634,7 @@ pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1644,7 +1644,7 @@ pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1654,7 +1654,7 @@ pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1664,7 +1664,7 @@ pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1674,7 +1674,7 @@ pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1684,7 +1684,7 @@ pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1694,7 +1694,7 @@ pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1704,7 +1704,7 @@ pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1714,7 +1714,7 @@ pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1724,7 +1724,7 @@ pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1734,7 +1734,7 @@ pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1744,7 +1744,7 @@ pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1754,7 +1754,7 @@ pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1764,7 +1764,7 @@ pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1774,7 +1774,7 @@ pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1784,7 +1784,7 @@ pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1794,7 +1794,7 @@ pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1804,7 +1804,7 @@ pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1814,7 +1814,7 @@ pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1824,7 +1824,7 @@ pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1833,7 +1833,7 @@ pub fn vceqzd_s64(a: i64) -> u64 {
 }
 #[doc = "Compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1842,7 +1842,7 @@ pub fn vceqzd_u64(a: u64) -> u64 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1852,7 +1852,7 @@ pub fn vceqzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1861,7 +1861,7 @@ pub fn vceqzs_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1870,7 +1870,7 @@ pub fn vceqzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1879,7 +1879,7 @@ pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1888,7 +1888,7 @@ pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1897,7 +1897,7 @@ pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1906,7 +1906,7 @@ pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1915,7 +1915,7 @@ pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1924,7 +1924,7 @@ pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1933,7 +1933,7 @@ pub fn vcged_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1942,7 +1942,7 @@ pub fn vcges_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1951,7 +1951,7 @@ pub fn vcged_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1960,7 +1960,7 @@ pub fn vcged_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1970,7 +1970,7 @@ pub fn vcgeh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1980,7 +1980,7 @@ pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1990,7 +1990,7 @@ pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2000,7 +2000,7 @@ pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2010,7 +2010,7 @@ pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2020,7 +2020,7 @@ pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2030,7 +2030,7 @@ pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2040,7 +2040,7 @@ pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2050,7 +2050,7 @@ pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2060,7 +2060,7 @@ pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2070,7 +2070,7 @@ pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2080,7 +2080,7 @@ pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2090,7 +2090,7 @@ pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2099,7 +2099,7 @@ pub fn vcgezd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2108,7 +2108,7 @@ pub fn vcgezs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2117,7 +2117,7 @@ pub fn vcgezd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2127,7 +2127,7 @@ pub fn vcgezh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2136,7 +2136,7 @@ pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2145,7 +2145,7 @@ pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2154,7 +2154,7 @@ pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2163,7 +2163,7 @@ pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2172,7 +2172,7 @@ pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2181,7 +2181,7 @@ pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2190,7 +2190,7 @@ pub fn vcgtd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2199,7 +2199,7 @@ pub fn vcgts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2208,7 +2208,7 @@ pub fn vcgtd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2217,7 +2217,7 @@ pub fn vcgtd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2227,7 +2227,7 @@ pub fn vcgth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2237,7 +2237,7 @@ pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2247,7 +2247,7 @@ pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2257,7 +2257,7 @@ pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2267,7 +2267,7 @@ pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2277,7 +2277,7 @@ pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2287,7 +2287,7 @@ pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2297,7 +2297,7 @@ pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2307,7 +2307,7 @@ pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2317,7 +2317,7 @@ pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2327,7 +2327,7 @@ pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2337,7 +2337,7 @@ pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2347,7 +2347,7 @@ pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2356,7 +2356,7 @@ pub fn vcgtzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2365,7 +2365,7 @@ pub fn vcgtzs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2374,7 +2374,7 @@ pub fn vcgtzd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2384,7 +2384,7 @@ pub fn vcgtzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2393,7 +2393,7 @@ pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2402,7 +2402,7 @@ pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2411,7 +2411,7 @@ pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2420,7 +2420,7 @@ pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2429,7 +2429,7 @@ pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2438,7 +2438,7 @@ pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2447,7 +2447,7 @@ pub fn vcled_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2456,7 +2456,7 @@ pub fn vcles_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2465,7 +2465,7 @@ pub fn vcled_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2474,7 +2474,7 @@ pub fn vcled_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2484,7 +2484,7 @@ pub fn vcleh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2494,7 +2494,7 @@ pub fn vclez_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2504,7 +2504,7 @@ pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2514,7 +2514,7 @@ pub fn vclez_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2524,7 +2524,7 @@ pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2534,7 +2534,7 @@ pub fn vclez_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2544,7 +2544,7 @@ pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2554,7 +2554,7 @@ pub fn vclez_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2564,7 +2564,7 @@ pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2574,7 +2574,7 @@ pub fn vclez_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2584,7 +2584,7 @@ pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2594,7 +2594,7 @@ pub fn vclez_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2604,7 +2604,7 @@ pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2613,7 +2613,7 @@ pub fn vclezd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2622,7 +2622,7 @@ pub fn vclezs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2631,7 +2631,7 @@ pub fn vclezd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2641,7 +2641,7 @@ pub fn vclezh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2650,7 +2650,7 @@ pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2659,7 +2659,7 @@ pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2668,7 +2668,7 @@ pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2677,7 +2677,7 @@ pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2686,7 +2686,7 @@ pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2695,7 +2695,7 @@ pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2704,7 +2704,7 @@ pub fn vcltd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2713,7 +2713,7 @@ pub fn vcltd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2723,7 +2723,7 @@ pub fn vclth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2732,7 +2732,7 @@ pub fn vclts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2741,7 +2741,7 @@ pub fn vcltd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2751,7 +2751,7 @@ pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2761,7 +2761,7 @@ pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2771,7 +2771,7 @@ pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2781,7 +2781,7 @@ pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2791,7 +2791,7 @@ pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2801,7 +2801,7 @@ pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2811,7 +2811,7 @@ pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2821,7 +2821,7 @@ pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2831,7 +2831,7 @@ pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2841,7 +2841,7 @@ pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2851,7 +2851,7 @@ pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2861,7 +2861,7 @@ pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2870,7 +2870,7 @@ pub fn vcltzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2879,7 +2879,7 @@ pub fn vcltzs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(asr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2888,7 +2888,7 @@ pub fn vcltzd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2898,7 +2898,7 @@ pub fn vcltzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -2916,7 +2916,7 @@ pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -2934,7 +2934,7 @@ pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2950,7 +2950,7 @@ pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2966,7 +2966,7 @@ pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2982,7 +2982,7 @@ pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3011,7 +3011,7 @@ pub fn vcmla_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3044,7 +3044,7 @@ pub fn vcmlaq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3062,7 +3062,7 @@ pub fn vcmla_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3089,7 +3089,7 @@ pub fn vcmlaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3118,7 +3118,7 @@ pub fn vcmla_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3151,7 +3151,7 @@ pub fn vcmlaq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3169,7 +3169,7 @@ pub fn vcmla_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3196,7 +3196,7 @@ pub fn vcmlaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3214,7 +3214,7 @@ pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3232,7 +3232,7 @@ pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3248,7 +3248,7 @@ pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3264,7 +3264,7 @@ pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3280,7 +3280,7 @@ pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3309,7 +3309,7 @@ pub fn vcmla_rot180_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3342,7 +3342,7 @@ pub fn vcmlaq_rot180_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3360,7 +3360,7 @@ pub fn vcmla_rot180_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3387,7 +3387,7 @@ pub fn vcmlaq_rot180_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3416,7 +3416,7 @@ pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3449,7 +3449,7 @@ pub fn vcmlaq_rot180_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3467,7 +3467,7 @@ pub fn vcmla_rot180_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3494,7 +3494,7 @@ pub fn vcmlaq_rot180_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3512,7 +3512,7 @@ pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3530,7 +3530,7 @@ pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3546,7 +3546,7 @@ pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3562,7 +3562,7 @@ pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3578,7 +3578,7 @@ pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3607,7 +3607,7 @@ pub fn vcmla_rot270_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3640,7 +3640,7 @@ pub fn vcmlaq_rot270_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3658,7 +3658,7 @@ pub fn vcmla_rot270_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3685,7 +3685,7 @@ pub fn vcmlaq_rot270_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3714,7 +3714,7 @@ pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3747,7 +3747,7 @@ pub fn vcmlaq_rot270_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3765,7 +3765,7 @@ pub fn vcmla_rot270_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3792,7 +3792,7 @@ pub fn vcmlaq_rot270_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3810,7 +3810,7 @@ pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3828,7 +3828,7 @@ pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3844,7 +3844,7 @@ pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3860,7 +3860,7 @@ pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3876,7 +3876,7 @@ pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3905,7 +3905,7 @@ pub fn vcmla_rot90_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3938,7 +3938,7 @@ pub fn vcmlaq_rot90_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3956,7 +3956,7 @@ pub fn vcmla_rot90_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3983,7 +3983,7 @@ pub fn vcmlaq_rot90_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -4012,7 +4012,7 @@ pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -4045,7 +4045,7 @@ pub fn vcmlaq_rot90_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -4063,7 +4063,7 @@ pub fn vcmla_rot90_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -4090,7 +4090,7 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4111,7 +4111,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4135,7 +4135,7 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4155,7 +4155,7 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4173,7 +4173,7 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4197,7 +4197,7 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4220,7 +4220,7 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4241,7 +4241,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4265,7 +4265,7 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4288,7 +4288,7 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4310,7 +4310,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4336,7 +4336,7 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4360,7 +4360,7 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4382,7 +4382,7 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4411,7 +4411,7 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4435,7 +4435,7 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4457,7 +4457,7 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4486,7 +4486,7 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4510,7 +4510,7 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4534,7 +4534,7 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4556,7 +4556,7 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4578,7 +4578,7 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4600,7 +4600,7 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4622,7 +4622,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4992,7 +4992,7 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5020,7 +5020,7 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5044,7 +5044,7 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5417,7 +5417,7 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5445,7 +5445,7 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5469,7 +5469,7 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5842,7 +5842,7 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5870,7 +5870,7 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5893,7 +5893,7 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5914,7 +5914,7 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6285,7 +6285,7 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6312,7 +6312,7 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6335,7 +6335,7 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6356,7 +6356,7 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6727,7 +6727,7 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6754,7 +6754,7 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6777,7 +6777,7 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6798,7 +6798,7 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7169,7 +7169,7 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7196,7 +7196,7 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7217,7 +7217,7 @@ pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7226,7 +7226,7 @@ pub fn vcreate_f64(a: u64) -> float64x1_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7235,7 +7235,7 @@ pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7244,7 +7244,7 @@ pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7253,7 +7253,7 @@ pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7262,7 +7262,7 @@ pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7271,7 +7271,7 @@ pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7280,7 +7280,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point convert to lower precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -7290,7 +7290,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 }
 #[doc = "Floating-point convert to higher precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -7300,7 +7300,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7309,7 +7309,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7321,7 +7321,7 @@ pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7339,7 +7339,7 @@ pub fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7357,7 +7357,7 @@ pub fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7375,7 +7375,7 @@ pub fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7393,7 +7393,7 @@ pub fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7411,7 +7411,7 @@ pub fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7429,7 +7429,7 @@ pub fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7447,7 +7447,7 @@ pub fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7465,7 +7465,7 @@ pub fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7481,7 +7481,7 @@ pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7497,7 +7497,7 @@ pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7513,7 +7513,7 @@ pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7529,7 +7529,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -7546,7 +7546,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -7563,7 +7563,7 @@ pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7579,7 +7579,7 @@ pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7595,7 +7595,7 @@ pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7611,7 +7611,7 @@ pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7627,7 +7627,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -7644,7 +7644,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -7661,7 +7661,7 @@ pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7677,7 +7677,7 @@ pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7693,7 +7693,7 @@ pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7709,7 +7709,7 @@ pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7725,7 +7725,7 @@ pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7735,7 +7735,7 @@ pub fn vcvtah_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7752,7 +7752,7 @@ pub fn vcvtah_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7769,7 +7769,7 @@ pub fn vcvtah_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7779,7 +7779,7 @@ pub fn vcvtah_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7796,7 +7796,7 @@ pub fn vcvtah_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7813,7 +7813,7 @@ pub fn vcvtah_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7829,7 +7829,7 @@ pub fn vcvtas_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7845,7 +7845,7 @@ pub fn vcvtad_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7861,7 +7861,7 @@ pub fn vcvtas_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7877,7 +7877,7 @@ pub fn vcvtad_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7886,7 +7886,7 @@ pub fn vcvtd_f64_s64(a: i64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7895,7 +7895,7 @@ pub fn vcvts_f32_s32(a: i32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7905,7 +7905,7 @@ pub fn vcvth_f16_s16(a: i16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7915,7 +7915,7 @@ pub fn vcvth_f16_s32(a: i32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7925,7 +7925,7 @@ pub fn vcvth_f16_s64(a: i64) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7935,7 +7935,7 @@ pub fn vcvth_f16_u16(a: u16) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7945,7 +7945,7 @@ pub fn vcvth_f16_u32(a: u32) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7955,7 +7955,7 @@ pub fn vcvth_f16_u64(a: u64) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7967,7 +7967,7 @@ pub fn vcvth_n_f16_s16<const N: i32>(a: i16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7986,7 +7986,7 @@ pub fn vcvth_n_f16_s32<const N: i32>(a: i32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8005,7 +8005,7 @@ pub fn vcvth_n_f16_s64<const N: i32>(a: i64) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8017,7 +8017,7 @@ pub fn vcvth_n_f16_u16<const N: i32>(a: u16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8036,7 +8036,7 @@ pub fn vcvth_n_f16_u32<const N: i32>(a: u32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8055,7 +8055,7 @@ pub fn vcvth_n_f16_u64<const N: i32>(a: u64) -> f16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8067,7 +8067,7 @@ pub fn vcvth_n_s16_f16<const N: i32>(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8086,7 +8086,7 @@ pub fn vcvth_n_s32_f16<const N: i32>(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8105,7 +8105,7 @@ pub fn vcvth_n_s64_f16<const N: i32>(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8117,7 +8117,7 @@ pub fn vcvth_n_u16_f16<const N: i32>(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8136,7 +8136,7 @@ pub fn vcvth_n_u32_f16<const N: i32>(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8155,7 +8155,7 @@ pub fn vcvth_n_u64_f16<const N: i32>(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8165,7 +8165,7 @@ pub fn vcvth_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8175,7 +8175,7 @@ pub fn vcvth_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8185,7 +8185,7 @@ pub fn vcvth_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8195,7 +8195,7 @@ pub fn vcvth_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8205,7 +8205,7 @@ pub fn vcvth_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8215,7 +8215,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8232,7 +8232,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8249,7 +8249,7 @@ pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8265,7 +8265,7 @@ pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8281,7 +8281,7 @@ pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8297,7 +8297,7 @@ pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8313,7 +8313,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8330,7 +8330,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8347,7 +8347,7 @@ pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8363,7 +8363,7 @@ pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8379,7 +8379,7 @@ pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8395,7 +8395,7 @@ pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8411,7 +8411,7 @@ pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8421,7 +8421,7 @@ pub fn vcvtmh_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8438,7 +8438,7 @@ pub fn vcvtmh_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8455,7 +8455,7 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8465,7 +8465,7 @@ pub fn vcvtmh_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8482,7 +8482,7 @@ pub fn vcvtmh_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8499,7 +8499,7 @@ pub fn vcvtmh_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8515,7 +8515,7 @@ pub fn vcvtms_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8531,7 +8531,7 @@ pub fn vcvtmd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8547,7 +8547,7 @@ pub fn vcvtms_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8563,7 +8563,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8580,7 +8580,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8597,7 +8597,7 @@ pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8613,7 +8613,7 @@ pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8629,7 +8629,7 @@ pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8645,7 +8645,7 @@ pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8661,7 +8661,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8678,7 +8678,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8695,7 +8695,7 @@ pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8711,7 +8711,7 @@ pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8727,7 +8727,7 @@ pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8743,7 +8743,7 @@ pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8759,7 +8759,7 @@ pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8769,7 +8769,7 @@ pub fn vcvtnh_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8786,7 +8786,7 @@ pub fn vcvtnh_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8803,7 +8803,7 @@ pub fn vcvtnh_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8813,7 +8813,7 @@ pub fn vcvtnh_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8830,7 +8830,7 @@ pub fn vcvtnh_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8847,7 +8847,7 @@ pub fn vcvtnh_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8863,7 +8863,7 @@ pub fn vcvtns_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8879,7 +8879,7 @@ pub fn vcvtnd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8895,7 +8895,7 @@ pub fn vcvtns_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8911,7 +8911,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8928,7 +8928,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -8945,7 +8945,7 @@ pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8961,7 +8961,7 @@ pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8977,7 +8977,7 @@ pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8993,7 +8993,7 @@ pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9009,7 +9009,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -9026,7 +9026,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -9043,7 +9043,7 @@ pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9059,7 +9059,7 @@ pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9075,7 +9075,7 @@ pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9091,7 +9091,7 @@ pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9107,7 +9107,7 @@ pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9117,7 +9117,7 @@ pub fn vcvtph_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9134,7 +9134,7 @@ pub fn vcvtph_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9151,7 +9151,7 @@ pub fn vcvtph_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9161,7 +9161,7 @@ pub fn vcvtph_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9178,7 +9178,7 @@ pub fn vcvtph_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9195,7 +9195,7 @@ pub fn vcvtph_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9211,7 +9211,7 @@ pub fn vcvtps_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9227,7 +9227,7 @@ pub fn vcvtpd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9243,7 +9243,7 @@ pub fn vcvtps_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9259,7 +9259,7 @@ pub fn vcvtpd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9268,7 +9268,7 @@ pub fn vcvts_f32_u32(a: u32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9277,7 +9277,7 @@ pub fn vcvtd_f64_u64(a: u64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9295,7 +9295,7 @@ pub fn vcvts_n_f32_s32<const N: i32>(a: i32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9313,7 +9313,7 @@ pub fn vcvtd_n_f64_s64<const N: i32>(a: i64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9331,7 +9331,7 @@ pub fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9349,7 +9349,7 @@ pub fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9367,7 +9367,7 @@ pub fn vcvts_n_s32_f32<const N: i32>(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9385,7 +9385,7 @@ pub fn vcvtd_n_s64_f64<const N: i32>(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9403,7 +9403,7 @@ pub fn vcvts_n_u32_f32<const N: i32>(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9421,7 +9421,7 @@ pub fn vcvtd_n_u64_f64<const N: i32>(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9430,7 +9430,7 @@ pub fn vcvts_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9439,7 +9439,7 @@ pub fn vcvtd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9448,7 +9448,7 @@ pub fn vcvts_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9457,7 +9457,7 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9473,7 +9473,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9482,7 +9482,7 @@ pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9491,7 +9491,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9501,7 +9501,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9511,7 +9511,7 @@ pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9520,7 +9520,7 @@ pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9529,7 +9529,7 @@ pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9538,7 +9538,7 @@ pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9547,7 +9547,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9557,7 +9557,7 @@ pub fn vdivh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9568,7 +9568,7 @@ pub fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9579,7 +9579,7 @@ pub fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9590,7 +9590,7 @@ pub fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9601,7 +9601,7 @@ pub fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9612,7 +9612,7 @@ pub fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9623,7 +9623,7 @@ pub fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9634,7 +9634,7 @@ pub fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9645,7 +9645,7 @@ pub fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9656,7 +9656,7 @@ pub fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9667,7 +9667,7 @@ pub fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9678,7 +9678,7 @@ pub fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9689,7 +9689,7 @@ pub fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9700,7 +9700,7 @@ pub fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9711,7 +9711,7 @@ pub fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9722,7 +9722,7 @@ pub fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9733,7 +9733,7 @@ pub fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -9745,7 +9745,7 @@ pub fn vduph_lane_f16<const N: i32>(a: float16x4_t) -> f16 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -9757,7 +9757,7 @@ pub fn vduph_laneq_f16<const N: i32>(a: float16x8_t) -> f16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9768,7 +9768,7 @@ pub fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9779,7 +9779,7 @@ pub fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9790,7 +9790,7 @@ pub fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9801,7 +9801,7 @@ pub fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9812,7 +9812,7 @@ pub fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9823,7 +9823,7 @@ pub fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9834,7 +9834,7 @@ pub fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9845,7 +9845,7 @@ pub fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9856,7 +9856,7 @@ pub fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9867,7 +9867,7 @@ pub fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9878,7 +9878,7 @@ pub fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9889,7 +9889,7 @@ pub fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9900,7 +9900,7 @@ pub fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9911,7 +9911,7 @@ pub fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9922,7 +9922,7 @@ pub fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9933,7 +9933,7 @@ pub fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9949,7 +9949,7 @@ pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9965,7 +9965,7 @@ pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9981,7 +9981,7 @@ pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9997,7 +9997,7 @@ pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10013,7 +10013,7 @@ pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10029,7 +10029,7 @@ pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10045,7 +10045,7 @@ pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10061,7 +10061,7 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ext, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -10078,7 +10078,7 @@ pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ext, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -10095,7 +10095,7 @@ pub fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmadd))]
@@ -10104,7 +10104,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10120,7 +10120,7 @@ pub fn vfma_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10136,7 +10136,7 @@ pub fn vfma_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10152,7 +10152,7 @@ pub fn vfmaq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10168,7 +10168,7 @@ pub fn vfmaq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10183,7 +10183,7 @@ pub fn vfma_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10198,7 +10198,7 @@ pub fn vfma_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10213,7 +10213,7 @@ pub fn vfmaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10228,7 +10228,7 @@ pub fn vfmaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10243,7 +10243,7 @@ pub fn vfmaq_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10258,7 +10258,7 @@ pub fn vfma_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10273,7 +10273,7 @@ pub fn vfma_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -10283,7 +10283,7 @@ pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -10293,7 +10293,7 @@ pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmadd))]
@@ -10302,7 +10302,7 @@ pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10316,7 +10316,7 @@ pub fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmadd))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10326,7 +10326,7 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10341,7 +10341,7 @@ pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10356,7 +10356,7 @@ pub fn vfmah_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -10365,7 +10365,7 @@ pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10380,7 +10380,7 @@ pub fn vfmaq_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -10389,7 +10389,7 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10403,7 +10403,7 @@ pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10417,7 +10417,7 @@ pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10431,7 +10431,7 @@ pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10449,7 +10449,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10467,7 +10467,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10484,7 +10484,7 @@ pub fn vfmlal_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10501,7 +10501,7 @@ pub fn vfmlal_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10518,7 +10518,7 @@ pub fn vfmlalq_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10535,7 +10535,7 @@ pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10552,7 +10552,7 @@ pub fn vfmlal_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10569,7 +10569,7 @@ pub fn vfmlal_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10586,7 +10586,7 @@ pub fn vfmlalq_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10603,7 +10603,7 @@ pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10621,7 +10621,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10639,7 +10639,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10657,7 +10657,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10675,7 +10675,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10692,7 +10692,7 @@ pub fn vfmlsl_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10709,7 +10709,7 @@ pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10726,7 +10726,7 @@ pub fn vfmlslq_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10743,7 +10743,7 @@ pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10760,7 +10760,7 @@ pub fn vfmlsl_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10777,7 +10777,7 @@ pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10794,7 +10794,7 @@ pub fn vfmlslq_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10811,7 +10811,7 @@ pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10829,7 +10829,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -10847,7 +10847,7 @@ pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -10859,7 +10859,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10875,7 +10875,7 @@ pub fn vfms_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10891,7 +10891,7 @@ pub fn vfms_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10907,7 +10907,7 @@ pub fn vfmsq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10923,7 +10923,7 @@ pub fn vfmsq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10938,7 +10938,7 @@ pub fn vfms_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10953,7 +10953,7 @@ pub fn vfms_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10968,7 +10968,7 @@ pub fn vfmsq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10983,7 +10983,7 @@ pub fn vfmsq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10998,7 +10998,7 @@ pub fn vfmsq_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11013,7 +11013,7 @@ pub fn vfms_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11028,7 +11028,7 @@ pub fn vfms_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -11038,7 +11038,7 @@ pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -11048,7 +11048,7 @@ pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11057,7 +11057,7 @@ pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11067,7 +11067,7 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -11082,7 +11082,7 @@ pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -11097,7 +11097,7 @@ pub fn vfmsh_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11109,7 +11109,7 @@ pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11124,7 +11124,7 @@ pub fn vfmsq_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11133,7 +11133,7 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11143,7 +11143,7 @@ pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11153,7 +11153,7 @@ pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11163,7 +11163,7 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11175,7 +11175,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11187,7 +11187,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11199,7 +11199,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11210,7 +11210,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11221,7 +11221,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11232,7 +11232,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11243,7 +11243,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11254,7 +11254,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11265,7 +11265,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11276,7 +11276,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11287,7 +11287,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11298,7 +11298,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11309,7 +11309,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11320,7 +11320,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11331,7 +11331,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11342,7 +11342,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11353,7 +11353,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11364,7 +11364,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11375,7 +11375,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11386,7 +11386,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11397,7 +11397,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11408,7 +11408,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11419,7 +11419,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11430,7 +11430,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11441,7 +11441,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11452,7 +11452,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11463,7 +11463,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11474,7 +11474,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11485,7 +11485,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld))]
@@ -11496,7 +11496,7 @@ pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld))]
@@ -11507,7 +11507,7 @@ pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld))]
@@ -11518,7 +11518,7 @@ pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld))]
@@ -11529,7 +11529,7 @@ pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld))]
@@ -11540,7 +11540,7 @@ pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld))]
@@ -11551,7 +11551,7 @@ pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11569,7 +11569,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11587,7 +11587,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11605,7 +11605,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -11616,7 +11616,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11636,7 +11636,7 @@ pub unsafe fn vld2_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11656,7 +11656,7 @@ pub unsafe fn vld2_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11669,7 +11669,7 @@ pub unsafe fn vld2_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11682,7 +11682,7 @@ pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11694,7 +11694,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11709,7 +11709,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11721,7 +11721,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11736,7 +11736,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11754,7 +11754,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11772,7 +11772,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11793,7 +11793,7 @@ pub unsafe fn vld2q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11813,7 +11813,7 @@ pub unsafe fn vld2q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x2_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11833,7 +11833,7 @@ pub unsafe fn vld2q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11846,7 +11846,7 @@ pub unsafe fn vld2q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11859,7 +11859,7 @@ pub unsafe fn vld2q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x2_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11872,7 +11872,7 @@ pub unsafe fn vld2q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11885,7 +11885,7 @@ pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11897,7 +11897,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11912,7 +11912,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11923,7 +11923,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -11941,7 +11941,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -11959,7 +11959,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -11977,7 +11977,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -11988,7 +11988,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12014,7 +12014,7 @@ pub unsafe fn vld3_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12027,7 +12027,7 @@ pub unsafe fn vld3_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12053,7 +12053,7 @@ pub unsafe fn vld3_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12066,7 +12066,7 @@ pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12078,7 +12078,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12094,7 +12094,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12106,7 +12106,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12122,7 +12122,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12133,7 +12133,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12144,7 +12144,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12170,7 +12170,7 @@ pub unsafe fn vld3q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12183,7 +12183,7 @@ pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12209,7 +12209,7 @@ pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12235,7 +12235,7 @@ pub unsafe fn vld3q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12248,7 +12248,7 @@ pub unsafe fn vld3q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x3_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12261,7 +12261,7 @@ pub unsafe fn vld3q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12274,7 +12274,7 @@ pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12286,7 +12286,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12302,7 +12302,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12313,7 +12313,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12331,7 +12331,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12349,7 +12349,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12367,7 +12367,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -12378,7 +12378,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12405,7 +12405,7 @@ pub unsafe fn vld4_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12432,7 +12432,7 @@ pub unsafe fn vld4_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12445,7 +12445,7 @@ pub unsafe fn vld4_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12458,7 +12458,7 @@ pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12470,7 +12470,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12487,7 +12487,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12499,7 +12499,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12516,7 +12516,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12527,7 +12527,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12538,7 +12538,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12565,7 +12565,7 @@ pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12592,7 +12592,7 @@ pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12619,7 +12619,7 @@ pub unsafe fn vld4q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12632,7 +12632,7 @@ pub unsafe fn vld4q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12645,7 +12645,7 @@ pub unsafe fn vld4q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x4_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12658,7 +12658,7 @@ pub unsafe fn vld4q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12671,7 +12671,7 @@ pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -12683,7 +12683,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -12700,7 +12700,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12711,7 +12711,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12730,7 +12730,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12749,7 +12749,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12763,7 +12763,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12777,7 +12777,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12791,7 +12791,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12805,7 +12805,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12819,7 +12819,7 @@ pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12832,7 +12832,7 @@ pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12845,7 +12845,7 @@ pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12858,7 +12858,7 @@ pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> ui
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12871,7 +12871,7 @@ pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12884,7 +12884,7 @@ pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12897,7 +12897,7 @@ pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12910,7 +12910,7 @@ pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> po
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12923,7 +12923,7 @@ pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12936,7 +12936,7 @@ pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12949,7 +12949,7 @@ pub unsafe fn vluti2q_lane_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12969,7 +12969,7 @@ pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12989,7 +12989,7 @@ pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13009,7 +13009,7 @@ pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13029,7 +13029,7 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13042,7 +13042,7 @@ pub unsafe fn vluti2_laneq_f16<const INDEX: i32>(a: float16x4_t, b: uint8x16_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13055,7 +13055,7 @@ pub unsafe fn vluti2q_laneq_f16<const INDEX: i32>(a: float16x8_t, b: uint8x16_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13068,7 +13068,7 @@ pub unsafe fn vluti2_laneq_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13081,7 +13081,7 @@ pub unsafe fn vluti2q_laneq_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13094,7 +13094,7 @@ pub unsafe fn vluti2_laneq_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13107,7 +13107,7 @@ pub unsafe fn vluti2q_laneq_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x16_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13120,7 +13120,7 @@ pub unsafe fn vluti2_laneq_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13133,7 +13133,7 @@ pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13146,7 +13146,7 @@ pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13159,7 +13159,7 @@ pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13179,7 +13179,7 @@ pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13199,7 +13199,7 @@ pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13219,7 +13219,7 @@ pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13239,7 +13239,7 @@ pub unsafe fn vluti2q_laneq_s16<const INDEX: i32>(a: int16x8_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13252,7 +13252,7 @@ pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13265,7 +13265,7 @@ pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13278,7 +13278,7 @@ pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13298,7 +13298,7 @@ pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13318,7 +13318,7 @@ pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13331,7 +13331,7 @@ pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13344,7 +13344,7 @@ pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13360,7 +13360,7 @@ pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13373,7 +13373,7 @@ pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13386,7 +13386,7 @@ pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13406,7 +13406,7 @@ pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13426,7 +13426,7 @@ pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13439,7 +13439,7 @@ pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13450,7 +13450,7 @@ pub unsafe fn vluti4q_laneq_p8<const LANE: i32>(a: poly8x16_t, b: uint8x16_t) ->
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -13466,7 +13466,7 @@ pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -13482,7 +13482,7 @@ pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13499,7 +13499,7 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -13515,7 +13515,7 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -13531,7 +13531,7 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point Maximum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13548,7 +13548,7 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13565,7 +13565,7 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13582,7 +13582,7 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -13598,7 +13598,7 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -13614,7 +13614,7 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
@@ -13630,7 +13630,7 @@ pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13647,7 +13647,7 @@ pub fn vmaxv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13664,7 +13664,7 @@ pub fn vmaxvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -13680,7 +13680,7 @@ pub fn vmaxv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxv))]
@@ -13696,7 +13696,7 @@ pub fn vmaxvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -13712,7 +13712,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13721,7 +13721,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13730,7 +13730,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13739,7 +13739,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13748,7 +13748,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -13757,7 +13757,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13766,7 +13766,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13775,7 +13775,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13784,7 +13784,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13793,7 +13793,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13802,7 +13802,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -13811,7 +13811,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13820,7 +13820,7 @@ pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -13836,7 +13836,7 @@ pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -13852,7 +13852,7 @@ pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13869,7 +13869,7 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -13885,7 +13885,7 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -13901,7 +13901,7 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point Minimum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13918,7 +13918,7 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13935,7 +13935,7 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13952,7 +13952,7 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13968,7 +13968,7 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13984,7 +13984,7 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmv))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14000,7 +14000,7 @@ pub fn vminnmvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -14017,7 +14017,7 @@ pub fn vminv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -14034,7 +14034,7 @@ pub fn vminvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -14050,7 +14050,7 @@ pub fn vminv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminv))]
@@ -14066,7 +14066,7 @@ pub fn vminvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -14082,7 +14082,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -14091,7 +14091,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -14100,7 +14100,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -14109,7 +14109,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -14118,7 +14118,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -14127,7 +14127,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -14136,7 +14136,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -14145,7 +14145,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -14154,7 +14154,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -14163,7 +14163,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -14172,7 +14172,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -14181,7 +14181,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -14190,7 +14190,7 @@ pub fn vminvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14199,7 +14199,7 @@ pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14208,7 +14208,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14219,7 +14219,7 @@ pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14234,7 +14234,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14245,7 +14245,7 @@ pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14260,7 +14260,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14275,7 +14275,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14290,7 +14290,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14305,7 +14305,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14320,7 +14320,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14329,7 +14329,7 @@ pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14338,7 +14338,7 @@ pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14347,7 +14347,7 @@ pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14356,7 +14356,7 @@ pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14369,7 +14369,7 @@ pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14382,7 +14382,7 @@ pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14395,7 +14395,7 @@ pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14408,7 +14408,7 @@ pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14421,7 +14421,7 @@ pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14434,7 +14434,7 @@ pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14443,7 +14443,7 @@ pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14452,7 +14452,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14463,7 +14463,7 @@ pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14478,7 +14478,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14489,7 +14489,7 @@ pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14504,7 +14504,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14519,7 +14519,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14534,7 +14534,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14549,7 +14549,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14564,7 +14564,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14573,7 +14573,7 @@ pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14582,7 +14582,7 @@ pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14591,7 +14591,7 @@ pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14600,7 +14600,7 @@ pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14613,7 +14613,7 @@ pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14626,7 +14626,7 @@ pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14639,7 +14639,7 @@ pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14652,7 +14652,7 @@ pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14665,7 +14665,7 @@ pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14678,7 +14678,7 @@ pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14690,7 +14690,7 @@ pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14702,7 +14702,7 @@ pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14714,7 +14714,7 @@ pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14726,7 +14726,7 @@ pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14738,7 +14738,7 @@ pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14750,7 +14750,7 @@ pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14762,7 +14762,7 @@ pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14774,7 +14774,7 @@ pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14786,7 +14786,7 @@ pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14798,7 +14798,7 @@ pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14810,7 +14810,7 @@ pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14822,7 +14822,7 @@ pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -14831,7 +14831,7 @@ pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -14840,7 +14840,7 @@ pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14851,7 +14851,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14863,7 +14863,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14875,7 +14875,7 @@ pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14886,7 +14886,7 @@ pub fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float6
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14895,7 +14895,7 @@ pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14904,7 +14904,7 @@ pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14918,7 +14918,7 @@ pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -14928,7 +14928,7 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14943,7 +14943,7 @@ pub fn vmulh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14958,7 +14958,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14969,7 +14969,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14980,7 +14980,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14991,7 +14991,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15002,7 +15002,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15013,7 +15013,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15024,7 +15024,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15035,7 +15035,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15046,7 +15046,7 @@ pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> ui
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15055,7 +15055,7 @@ pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15064,7 +15064,7 @@ pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15073,7 +15073,7 @@ pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15082,7 +15082,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull2))]
@@ -15091,7 +15091,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull2))]
@@ -15104,7 +15104,7 @@ pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15117,7 +15117,7 @@ pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15130,7 +15130,7 @@ pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15143,7 +15143,7 @@ pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15156,7 +15156,7 @@ pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15169,7 +15169,7 @@ pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15182,7 +15182,7 @@ pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull))]
@@ -15198,7 +15198,7 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15209,7 +15209,7 @@ pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float6
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15220,7 +15220,7 @@ pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15234,7 +15234,7 @@ pub fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15248,7 +15248,7 @@ pub fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15262,7 +15262,7 @@ pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15279,7 +15279,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15296,7 +15296,7 @@ pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15312,7 +15312,7 @@ pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15328,7 +15328,7 @@ pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15344,7 +15344,7 @@ pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15360,7 +15360,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15372,7 +15372,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15384,7 +15384,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15396,7 +15396,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15408,7 +15408,7 @@ pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15419,7 +15419,7 @@ pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float3
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15430,7 +15430,7 @@ pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15441,7 +15441,7 @@ pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15452,7 +15452,7 @@ pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15463,7 +15463,7 @@ pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15474,7 +15474,7 @@ pub fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float6
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15485,7 +15485,7 @@ pub fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -15495,7 +15495,7 @@ pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -15505,7 +15505,7 @@ pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15521,7 +15521,7 @@ pub fn vmulxd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15537,7 +15537,7 @@ pub fn vmulxs_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15548,7 +15548,7 @@ pub fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15559,7 +15559,7 @@ pub fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15570,7 +15570,7 @@ pub fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15581,7 +15581,7 @@ pub fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15598,7 +15598,7 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15610,7 +15610,7 @@ pub fn vmulxh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15622,7 +15622,7 @@ pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15633,7 +15633,7 @@ pub fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -15642,7 +15642,7 @@ pub fn vneg_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -15651,7 +15651,7 @@ pub fn vnegq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15660,7 +15660,7 @@ pub fn vneg_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15669,7 +15669,7 @@ pub fn vnegq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15678,7 +15678,7 @@ pub fn vnegd_s64(a: i64) -> i64 {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15688,7 +15688,7 @@ pub fn vnegh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -15701,7 +15701,7 @@ pub fn vpaddd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -15714,7 +15714,7 @@ pub fn vpadds_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15723,7 +15723,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15732,7 +15732,7 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15746,7 +15746,7 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -15759,7 +15759,7 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -15772,7 +15772,7 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15785,7 +15785,7 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15798,7 +15798,7 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15811,7 +15811,7 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15824,7 +15824,7 @@ pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15837,7 +15837,7 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15850,7 +15850,7 @@ pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15863,7 +15863,7 @@ pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15876,7 +15876,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15893,7 +15893,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15910,7 +15910,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15927,7 +15927,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15944,7 +15944,7 @@ pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15960,7 +15960,7 @@ pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15976,7 +15976,7 @@ pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15992,7 +15992,7 @@ pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16008,7 +16008,7 @@ pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16024,7 +16024,7 @@ pub fn vpmaxnms_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16040,7 +16040,7 @@ pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16056,7 +16056,7 @@ pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16072,7 +16072,7 @@ pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16088,7 +16088,7 @@ pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16104,7 +16104,7 @@ pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16120,7 +16120,7 @@ pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16136,7 +16136,7 @@ pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16152,7 +16152,7 @@ pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16168,7 +16168,7 @@ pub fn vpmaxqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16184,7 +16184,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16201,7 +16201,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16218,7 +16218,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16235,7 +16235,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16252,7 +16252,7 @@ pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16268,7 +16268,7 @@ pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16284,7 +16284,7 @@ pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16300,7 +16300,7 @@ pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16316,7 +16316,7 @@ pub fn vpminnmqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16332,7 +16332,7 @@ pub fn vpminnms_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16348,7 +16348,7 @@ pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16364,7 +16364,7 @@ pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16380,7 +16380,7 @@ pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16396,7 +16396,7 @@ pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16412,7 +16412,7 @@ pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16428,7 +16428,7 @@ pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16444,7 +16444,7 @@ pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16460,7 +16460,7 @@ pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16476,7 +16476,7 @@ pub fn vpminqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16492,7 +16492,7 @@ pub fn vpmins_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16508,7 +16508,7 @@ pub fn vqabs_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16524,7 +16524,7 @@ pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16533,7 +16533,7 @@ pub fn vqabsb_s8(a: i8) -> i8 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16542,7 +16542,7 @@ pub fn vqabsh_s16(a: i16) -> i16 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16558,7 +16558,7 @@ pub fn vqabss_s32(a: i32) -> i32 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16574,7 +16574,7 @@ pub fn vqabsd_s64(a: i64) -> i64 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16585,7 +16585,7 @@ pub fn vqaddb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16596,7 +16596,7 @@ pub fn vqaddh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16607,7 +16607,7 @@ pub fn vqaddb_u8(a: u8, b: u8) -> u8 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16618,7 +16618,7 @@ pub fn vqaddh_u16(a: u16, b: u16) -> u16 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16634,7 +16634,7 @@ pub fn vqadds_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16650,7 +16650,7 @@ pub fn vqaddd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16666,7 +16666,7 @@ pub fn vqadds_u32(a: u32, b: u32) -> u32 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16682,7 +16682,7 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16693,7 +16693,7 @@ pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16704,7 +16704,7 @@ pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16715,7 +16715,7 @@ pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16726,7 +16726,7 @@ pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16735,7 +16735,7 @@ pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16744,7 +16744,7 @@ pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16753,7 +16753,7 @@ pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16762,7 +16762,7 @@ pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, N = 2))]
 #[rustc_legacy_const_generics(3)]
@@ -16773,7 +16773,7 @@ pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16784,7 +16784,7 @@ pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16795,7 +16795,7 @@ pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16806,7 +16806,7 @@ pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16817,7 +16817,7 @@ pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16828,7 +16828,7 @@ pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16838,7 +16838,7 @@ pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16848,7 +16848,7 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16859,7 +16859,7 @@ pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16870,7 +16870,7 @@ pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16881,7 +16881,7 @@ pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16892,7 +16892,7 @@ pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16901,7 +16901,7 @@ pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16910,7 +16910,7 @@ pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16919,7 +16919,7 @@ pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16928,7 +16928,7 @@ pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, N = 2))]
 #[rustc_legacy_const_generics(3)]
@@ -16939,7 +16939,7 @@ pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16950,7 +16950,7 @@ pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16961,7 +16961,7 @@ pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16972,7 +16972,7 @@ pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16983,7 +16983,7 @@ pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16994,7 +16994,7 @@ pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17004,7 +17004,7 @@ pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17014,7 +17014,7 @@ pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 {
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17025,7 +17025,7 @@ pub fn vqdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17036,7 +17036,7 @@ pub fn vqdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17047,7 +17047,7 @@ pub fn vqdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17058,7 +17058,7 @@ pub fn vqdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17072,7 +17072,7 @@ pub fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17086,7 +17086,7 @@ pub fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17097,7 +17097,7 @@ pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17108,7 +17108,7 @@ pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17122,7 +17122,7 @@ pub fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17136,7 +17136,7 @@ pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17151,7 +17151,7 @@ pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17166,7 +17166,7 @@ pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17181,7 +17181,7 @@ pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17196,7 +17196,7 @@ pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17209,7 +17209,7 @@ pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17222,7 +17222,7 @@ pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17235,7 +17235,7 @@ pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17248,7 +17248,7 @@ pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17262,7 +17262,7 @@ pub fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17276,7 +17276,7 @@ pub fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17290,7 +17290,7 @@ pub fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17304,7 +17304,7 @@ pub fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17318,7 +17318,7 @@ pub fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17329,7 +17329,7 @@ pub fn vqdmullh_s16(a: i16, b: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17343,7 +17343,7 @@ pub fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17359,7 +17359,7 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17374,7 +17374,7 @@ pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17383,7 +17383,7 @@ pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17392,7 +17392,7 @@ pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17407,7 +17407,7 @@ pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17416,7 +17416,7 @@ pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17425,7 +17425,7 @@ pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17441,7 +17441,7 @@ pub fn vqmovnd_s64(a: i64) -> i32 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17457,7 +17457,7 @@ pub fn vqmovnd_u64(a: u64) -> u32 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17466,7 +17466,7 @@ pub fn vqmovnh_s16(a: i16) -> i8 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17475,7 +17475,7 @@ pub fn vqmovns_s32(a: i32) -> i16 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17484,7 +17484,7 @@ pub fn vqmovnh_u16(a: u16) -> u8 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17493,7 +17493,7 @@ pub fn vqmovns_u32(a: u32) -> u16 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17508,7 +17508,7 @@ pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17517,7 +17517,7 @@ pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17526,7 +17526,7 @@ pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17535,7 +17535,7 @@ pub fn vqmovunh_s16(a: i16) -> u8 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17544,7 +17544,7 @@ pub fn vqmovuns_s32(a: i32) -> u16 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17553,7 +17553,7 @@ pub fn vqmovund_s64(a: i64) -> u32 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17569,7 +17569,7 @@ pub fn vqneg_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17585,7 +17585,7 @@ pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17594,7 +17594,7 @@ pub fn vqnegb_s8(a: i8) -> i8 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17603,7 +17603,7 @@ pub fn vqnegh_s16(a: i16) -> i16 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17612,7 +17612,7 @@ pub fn vqnegs_s32(a: i32) -> i32 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17621,7 +17621,7 @@ pub fn vqnegd_s64(a: i64) -> i64 {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17635,7 +17635,7 @@ pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17649,7 +17649,7 @@ pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17663,7 +17663,7 @@ pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17677,7 +17677,7 @@ pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17691,7 +17691,7 @@ pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17705,7 +17705,7 @@ pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17719,7 +17719,7 @@ pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17733,7 +17733,7 @@ pub fn vqrdmlahq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17749,7 +17749,7 @@ pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17765,7 +17765,7 @@ pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17781,7 +17781,7 @@ pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17797,7 +17797,7 @@ pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17808,7 +17808,7 @@ pub fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17819,7 +17819,7 @@ pub fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17830,7 +17830,7 @@ pub fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17841,7 +17841,7 @@ pub fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17853,7 +17853,7 @@ pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17865,7 +17865,7 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17879,7 +17879,7 @@ pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17893,7 +17893,7 @@ pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17907,7 +17907,7 @@ pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17921,7 +17921,7 @@ pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17935,7 +17935,7 @@ pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17949,7 +17949,7 @@ pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17963,7 +17963,7 @@ pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17977,7 +17977,7 @@ pub fn vqrdmlshq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17993,7 +17993,7 @@ pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18009,7 +18009,7 @@ pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18025,7 +18025,7 @@ pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18041,7 +18041,7 @@ pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18052,7 +18052,7 @@ pub fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18063,7 +18063,7 @@ pub fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18074,7 +18074,7 @@ pub fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18085,7 +18085,7 @@ pub fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18097,7 +18097,7 @@ pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18109,7 +18109,7 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18120,7 +18120,7 @@ pub fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18131,7 +18131,7 @@ pub fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18142,7 +18142,7 @@ pub fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18153,7 +18153,7 @@ pub fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18162,7 +18162,7 @@ pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18171,7 +18171,7 @@ pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18182,7 +18182,7 @@ pub fn vqrshlb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18193,7 +18193,7 @@ pub fn vqrshlh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18204,7 +18204,7 @@ pub fn vqrshlb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18215,7 +18215,7 @@ pub fn vqrshlh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18231,7 +18231,7 @@ pub fn vqrshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18247,7 +18247,7 @@ pub fn vqrshls_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18263,7 +18263,7 @@ pub fn vqrshls_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18279,7 +18279,7 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18296,7 +18296,7 @@ pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18307,7 +18307,7 @@ pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18318,7 +18318,7 @@ pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18335,7 +18335,7 @@ pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18346,7 +18346,7 @@ pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18357,7 +18357,7 @@ pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18369,7 +18369,7 @@ pub fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18381,7 +18381,7 @@ pub fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18393,7 +18393,7 @@ pub fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18405,7 +18405,7 @@ pub fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18417,7 +18417,7 @@ pub fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18429,7 +18429,7 @@ pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18446,7 +18446,7 @@ pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18457,7 +18457,7 @@ pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18468,7 +18468,7 @@ pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18480,7 +18480,7 @@ pub fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18492,7 +18492,7 @@ pub fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18504,7 +18504,7 @@ pub fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18515,7 +18515,7 @@ pub fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18526,7 +18526,7 @@ pub fn vqshld_n_s64<const N: i32>(a: i64) -> i64 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18537,7 +18537,7 @@ pub fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18548,7 +18548,7 @@ pub fn vqshls_n_s32<const N: i32>(a: i32) -> i32 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18559,7 +18559,7 @@ pub fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18570,7 +18570,7 @@ pub fn vqshld_n_u64<const N: i32>(a: u64) -> u64 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18581,7 +18581,7 @@ pub fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18592,7 +18592,7 @@ pub fn vqshls_n_u32<const N: i32>(a: u32) -> u32 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18602,7 +18602,7 @@ pub fn vqshlb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18612,7 +18612,7 @@ pub fn vqshlh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18622,7 +18622,7 @@ pub fn vqshls_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18632,7 +18632,7 @@ pub fn vqshlb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18642,7 +18642,7 @@ pub fn vqshlh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18652,7 +18652,7 @@ pub fn vqshls_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18668,7 +18668,7 @@ pub fn vqshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18684,7 +18684,7 @@ pub fn vqshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18695,7 +18695,7 @@ pub fn vqshlub_n_s8<const N: i32>(a: i8) -> u8 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18706,7 +18706,7 @@ pub fn vqshlud_n_s64<const N: i32>(a: i64) -> u64 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18717,7 +18717,7 @@ pub fn vqshluh_n_s16<const N: i32>(a: i16) -> u16 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18728,7 +18728,7 @@ pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18745,7 +18745,7 @@ pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18756,7 +18756,7 @@ pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18767,7 +18767,7 @@ pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18784,7 +18784,7 @@ pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18795,7 +18795,7 @@ pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18806,7 +18806,7 @@ pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18824,7 +18824,7 @@ pub fn vqshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18842,7 +18842,7 @@ pub fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18853,7 +18853,7 @@ pub fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18864,7 +18864,7 @@ pub fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18875,7 +18875,7 @@ pub fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18886,7 +18886,7 @@ pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18903,7 +18903,7 @@ pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18914,7 +18914,7 @@ pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18925,7 +18925,7 @@ pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18936,7 +18936,7 @@ pub fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18947,7 +18947,7 @@ pub fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18958,7 +18958,7 @@ pub fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -18969,7 +18969,7 @@ pub fn vqsubb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -18980,7 +18980,7 @@ pub fn vqsubh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -18991,7 +18991,7 @@ pub fn vqsubb_u8(a: u8, b: u8) -> u8 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19002,7 +19002,7 @@ pub fn vqsubh_u16(a: u16, b: u16) -> u16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19018,7 +19018,7 @@ pub fn vqsubs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19034,7 +19034,7 @@ pub fn vqsubd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19050,7 +19050,7 @@ pub fn vqsubs_u32(a: u32, b: u32) -> u32 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19066,7 +19066,7 @@ pub fn vqsubd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19082,7 +19082,7 @@ fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19098,7 +19098,7 @@ fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19107,7 +19107,7 @@ pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19116,7 +19116,7 @@ pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19125,7 +19125,7 @@ pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19134,7 +19134,7 @@ pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19143,7 +19143,7 @@ pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19152,7 +19152,7 @@ pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19168,7 +19168,7 @@ fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19184,7 +19184,7 @@ fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19193,7 +19193,7 @@ pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19202,7 +19202,7 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19211,7 +19211,7 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19220,7 +19220,7 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19229,7 +19229,7 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19238,7 +19238,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19254,7 +19254,7 @@ fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19270,7 +19270,7 @@ fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19279,7 +19279,7 @@ pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19288,7 +19288,7 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19297,7 +19297,7 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19306,7 +19306,7 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19315,7 +19315,7 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19324,7 +19324,7 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19346,7 +19346,7 @@ fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19368,7 +19368,7 @@ fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19377,7 +19377,7 @@ pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19386,7 +19386,7 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19403,7 +19403,7 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19420,7 +19420,7 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19437,7 +19437,7 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19454,7 +19454,7 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19470,7 +19470,7 @@ fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19486,7 +19486,7 @@ fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19495,7 +19495,7 @@ pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19504,7 +19504,7 @@ pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19513,7 +19513,7 @@ pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19522,7 +19522,7 @@ pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19531,7 +19531,7 @@ pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19540,7 +19540,7 @@ pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19556,7 +19556,7 @@ fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19572,7 +19572,7 @@ fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19581,7 +19581,7 @@ pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19590,7 +19590,7 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19599,7 +19599,7 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19608,7 +19608,7 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19617,7 +19617,7 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19626,7 +19626,7 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19643,7 +19643,7 @@ fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19665,7 +19665,7 @@ fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19674,7 +19674,7 @@ pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19683,7 +19683,7 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19700,7 +19700,7 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19717,7 +19717,7 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19734,7 +19734,7 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19751,7 +19751,7 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19781,7 +19781,7 @@ fn vqtbx4(
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19811,7 +19811,7 @@ fn vqtbx4q(
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19820,7 +19820,7 @@ pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19829,7 +19829,7 @@ pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19847,7 +19847,7 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19865,7 +19865,7 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19883,7 +19883,7 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19901,7 +19901,7 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Rotate and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(rax1))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -19917,7 +19917,7 @@ pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -19926,7 +19926,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -19935,7 +19935,7 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19945,7 +19945,7 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19959,7 +19959,7 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19969,7 +19969,7 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19988,7 +19988,7 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19998,7 +19998,7 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20012,7 +20012,7 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20022,7 +20022,7 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20041,7 +20041,7 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20057,7 +20057,7 @@ pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20073,7 +20073,7 @@ pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20089,7 +20089,7 @@ pub fn vrecped_f64(a: f64) -> f64 {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20105,7 +20105,7 @@ pub fn vrecpes_f32(a: f32) -> f32 {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -20122,7 +20122,7 @@ pub fn vrecpeh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20138,7 +20138,7 @@ pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20154,7 +20154,7 @@ pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20170,7 +20170,7 @@ pub fn vrecpsd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20186,7 +20186,7 @@ pub fn vrecpss_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(frecps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -20203,7 +20203,7 @@ pub fn vrecpsh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20219,7 +20219,7 @@ pub fn vrecpxd_f64(a: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20235,7 +20235,7 @@ pub fn vrecpxs_f32(a: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -20252,7 +20252,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20263,7 +20263,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20277,7 +20277,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20288,7 +20288,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20303,7 +20303,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20314,7 +20314,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20328,7 +20328,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20339,7 +20339,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -20354,7 +20354,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20364,7 +20364,7 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20377,7 +20377,7 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20387,7 +20387,7 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20400,7 +20400,7 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20410,7 +20410,7 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20423,7 +20423,7 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20433,7 +20433,7 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20447,7 +20447,7 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20457,7 +20457,7 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20471,7 +20471,7 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20481,7 +20481,7 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20494,7 +20494,7 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20504,7 +20504,7 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20517,7 +20517,7 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20527,7 +20527,7 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20540,7 +20540,7 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20550,7 +20550,7 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20563,7 +20563,7 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -20572,7 +20572,7 @@ pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20582,7 +20582,7 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20595,7 +20595,7 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20605,7 +20605,7 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20618,7 +20618,7 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20628,7 +20628,7 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20641,7 +20641,7 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -20650,7 +20650,7 @@ pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20660,7 +20660,7 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20673,7 +20673,7 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20683,7 +20683,7 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20696,7 +20696,7 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -20705,7 +20705,7 @@ pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20715,7 +20715,7 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20728,7 +20728,7 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20738,7 +20738,7 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20752,7 +20752,7 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20762,7 +20762,7 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20780,7 +20780,7 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20790,7 +20790,7 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20804,7 +20804,7 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20814,7 +20814,7 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20828,7 +20828,7 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20838,7 +20838,7 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20852,7 +20852,7 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20862,7 +20862,7 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20880,7 +20880,7 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20890,7 +20890,7 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20904,7 +20904,7 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20914,7 +20914,7 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20928,7 +20928,7 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20938,7 +20938,7 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20952,7 +20952,7 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20962,7 +20962,7 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20980,7 +20980,7 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20990,7 +20990,7 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21004,7 +21004,7 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21014,7 +21014,7 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21028,7 +21028,7 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21038,7 +21038,7 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21051,7 +21051,7 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21061,7 +21061,7 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21076,7 +21076,7 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21086,7 +21086,7 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21099,7 +21099,7 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21109,7 +21109,7 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21123,7 +21123,7 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21133,7 +21133,7 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21146,7 +21146,7 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21156,7 +21156,7 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21170,7 +21170,7 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21179,7 +21179,7 @@ pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21188,7 +21188,7 @@ pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21198,7 +21198,7 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21212,7 +21212,7 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21222,7 +21222,7 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21236,7 +21236,7 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21246,7 +21246,7 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21259,7 +21259,7 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21269,7 +21269,7 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21284,7 +21284,7 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21294,7 +21294,7 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21307,7 +21307,7 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21317,7 +21317,7 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21331,7 +21331,7 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21341,7 +21341,7 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21354,7 +21354,7 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21364,7 +21364,7 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21378,7 +21378,7 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21387,7 +21387,7 @@ pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21396,7 +21396,7 @@ pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21406,7 +21406,7 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21420,7 +21420,7 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21430,7 +21430,7 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21444,7 +21444,7 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21454,7 +21454,7 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21467,7 +21467,7 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21477,7 +21477,7 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21492,7 +21492,7 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21502,7 +21502,7 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21515,7 +21515,7 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21525,7 +21525,7 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21539,7 +21539,7 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21549,7 +21549,7 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21562,7 +21562,7 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21571,7 +21571,7 @@ pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21580,7 +21580,7 @@ pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21589,7 +21589,7 @@ pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21599,7 +21599,7 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21613,7 +21613,7 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21623,7 +21623,7 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21637,7 +21637,7 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21647,7 +21647,7 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21661,7 +21661,7 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21671,7 +21671,7 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21685,7 +21685,7 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -21701,7 +21701,7 @@ pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -21717,7 +21717,7 @@ pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -21733,7 +21733,7 @@ pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -21749,7 +21749,7 @@ pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -21765,7 +21765,7 @@ pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -21781,7 +21781,7 @@ pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -21797,7 +21797,7 @@ pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -21813,7 +21813,7 @@ pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -21829,7 +21829,7 @@ pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -21845,7 +21845,7 @@ pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -21861,7 +21861,7 @@ pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -21877,7 +21877,7 @@ pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -21893,7 +21893,7 @@ pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -21909,7 +21909,7 @@ pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -21925,7 +21925,7 @@ pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -21941,7 +21941,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -21951,7 +21951,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -21961,7 +21961,7 @@ pub fn vrndq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -21970,7 +21970,7 @@ pub fn vrnd_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -21979,7 +21979,7 @@ pub fn vrndq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -21988,7 +21988,7 @@ pub fn vrnd_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -21997,7 +21997,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22007,7 +22007,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22017,7 +22017,7 @@ pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -22026,7 +22026,7 @@ pub fn vrnda_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -22035,7 +22035,7 @@ pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -22044,7 +22044,7 @@ pub fn vrnda_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -22053,7 +22053,7 @@ pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22063,7 +22063,7 @@ pub fn vrndah_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22073,7 +22073,7 @@ pub fn vrndh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22090,7 +22090,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22107,7 +22107,7 @@ pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -22123,7 +22123,7 @@ pub fn vrndi_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -22139,7 +22139,7 @@ pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -22155,7 +22155,7 @@ pub fn vrndi_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -22171,7 +22171,7 @@ pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22188,7 +22188,7 @@ pub fn vrndih_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22198,7 +22198,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22208,7 +22208,7 @@ pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -22217,7 +22217,7 @@ pub fn vrndm_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -22226,7 +22226,7 @@ pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -22235,7 +22235,7 @@ pub fn vrndm_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -22244,7 +22244,7 @@ pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22254,7 +22254,7 @@ pub fn vrndmh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -22270,7 +22270,7 @@ pub fn vrndn_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -22286,7 +22286,7 @@ pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22303,7 +22303,7 @@ pub fn vrndnh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -22319,7 +22319,7 @@ pub fn vrndns_f32(a: f32) -> f32 {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22329,7 +22329,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22339,7 +22339,7 @@ pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -22348,7 +22348,7 @@ pub fn vrndp_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -22357,7 +22357,7 @@ pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -22366,7 +22366,7 @@ pub fn vrndp_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -22375,7 +22375,7 @@ pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22385,7 +22385,7 @@ pub fn vrndph_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22395,7 +22395,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22405,7 +22405,7 @@ pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -22414,7 +22414,7 @@ pub fn vrndx_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -22423,7 +22423,7 @@ pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -22432,7 +22432,7 @@ pub fn vrndx_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -22441,7 +22441,7 @@ pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -22451,7 +22451,7 @@ pub fn vrndxh_f16(a: f16) -> f16 {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22467,7 +22467,7 @@ pub fn vrshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22483,7 +22483,7 @@ pub fn vrshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshr, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -22494,7 +22494,7 @@ pub fn vrshrd_n_s64<const N: i32>(a: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshr, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -22505,7 +22505,7 @@ pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22522,7 +22522,7 @@ pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22533,7 +22533,7 @@ pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22544,7 +22544,7 @@ pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22561,7 +22561,7 @@ pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22572,7 +22572,7 @@ pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22583,7 +22583,7 @@ pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22599,7 +22599,7 @@ pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22615,7 +22615,7 @@ pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22631,7 +22631,7 @@ pub fn vrsqrted_f64(a: f64) -> f64 {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22647,7 +22647,7 @@ pub fn vrsqrtes_f32(a: f32) -> f32 {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -22664,7 +22664,7 @@ pub fn vrsqrteh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22680,7 +22680,7 @@ pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22696,7 +22696,7 @@ pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22712,7 +22712,7 @@ pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22728,7 +22728,7 @@ pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -22745,7 +22745,7 @@ pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed rounding shift right and accumulate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshr, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22757,7 +22757,7 @@ pub fn vrsrad_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift right and accumulate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshr, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -22769,7 +22769,7 @@ pub fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -22780,7 +22780,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -22791,7 +22791,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -22802,7 +22802,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -22813,7 +22813,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -22824,7 +22824,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -22835,7 +22835,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -22846,7 +22846,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -22857,7 +22857,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -22868,7 +22868,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -22879,7 +22879,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -22890,7 +22890,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -22901,7 +22901,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
-#[inline(always)]
+#[inline]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
@@ -22917,7 +22917,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"]
-#[inline(always)]
+#[inline]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
@@ -22933,7 +22933,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"]
-#[inline(always)]
+#[inline]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
@@ -22949,7 +22949,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"]
-#[inline(always)]
+#[inline]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
@@ -22965,7 +22965,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"]
-#[inline(always)]
+#[inline]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
@@ -22981,7 +22981,7 @@ pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -22992,7 +22992,7 @@ pub fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -23003,7 +23003,7 @@ pub fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "SHA512 hash update part 2"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h2))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -23019,7 +23019,7 @@ pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t
 }
 #[doc = "SHA512 hash update part 1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -23035,7 +23035,7 @@ pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t
 }
 #[doc = "SHA512 schedule update 0"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su0))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -23051,7 +23051,7 @@ pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "SHA512 schedule update 1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su1))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -23067,7 +23067,7 @@ pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23076,7 +23076,7 @@ pub fn vshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23085,7 +23085,7 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23099,7 +23099,7 @@ pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23113,7 +23113,7 @@ pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23127,7 +23127,7 @@ pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23141,7 +23141,7 @@ pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23155,7 +23155,7 @@ pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23169,7 +23169,7 @@ pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23186,7 +23186,7 @@ pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23197,7 +23197,7 @@ pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23208,7 +23208,7 @@ pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23225,7 +23225,7 @@ pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23236,7 +23236,7 @@ pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23247,7 +23247,7 @@ pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23265,7 +23265,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23283,7 +23283,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23301,7 +23301,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23319,7 +23319,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23337,7 +23337,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23355,7 +23355,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23373,7 +23373,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23391,7 +23391,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23402,7 +23402,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23413,7 +23413,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23424,7 +23424,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23435,7 +23435,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23446,7 +23446,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23457,7 +23457,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23468,7 +23468,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23479,7 +23479,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23490,7 +23490,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23501,7 +23501,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23512,7 +23512,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23523,7 +23523,7 @@ pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23534,7 +23534,7 @@ pub fn vsli_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23545,7 +23545,7 @@ pub fn vsliq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -23556,7 +23556,7 @@ pub fn vslid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -23567,7 +23567,7 @@ pub fn vslid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 }
 #[doc = "SM3PARTW1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3partw1))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -23583,7 +23583,7 @@ pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_
 }
 #[doc = "SM3PARTW2"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3partw2))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -23599,7 +23599,7 @@ pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_
 }
 #[doc = "SM3SS1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3ss1))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -23615,7 +23615,7 @@ pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SM3TT1A"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -23633,7 +23633,7 @@ pub fn vsm3tt1aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT1B"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -23651,7 +23651,7 @@ pub fn vsm3tt1bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT2A"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -23669,7 +23669,7 @@ pub fn vsm3tt2aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT2B"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -23687,7 +23687,7 @@ pub fn vsm3tt2bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM4 key"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm4ekey))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -23703,7 +23703,7 @@ pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SM4 encode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm4e))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -23719,7 +23719,7 @@ pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23735,7 +23735,7 @@ pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23751,7 +23751,7 @@ pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23767,7 +23767,7 @@ pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23783,7 +23783,7 @@ pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23799,7 +23799,7 @@ pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23815,7 +23815,7 @@ pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23831,7 +23831,7 @@ pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -23847,7 +23847,7 @@ pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23856,7 +23856,7 @@ pub fn vsqaddb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23865,7 +23865,7 @@ pub fn vsqaddh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23881,7 +23881,7 @@ pub fn vsqaddd_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23897,7 +23897,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -23907,7 +23907,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
@@ -23917,7 +23917,7 @@ pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23926,7 +23926,7 @@ pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23935,7 +23935,7 @@ pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23944,7 +23944,7 @@ pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23953,7 +23953,7 @@ pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23963,7 +23963,7 @@ pub fn vsqrth_f16(a: f16) -> f16 {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23974,7 +23974,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23985,7 +23985,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -23996,7 +23996,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24007,7 +24007,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24018,7 +24018,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24029,7 +24029,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24040,7 +24040,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24051,7 +24051,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24062,7 +24062,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24073,7 +24073,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24084,7 +24084,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24095,7 +24095,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24106,7 +24106,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24117,7 +24117,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24128,7 +24128,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24139,7 +24139,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24150,7 +24150,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24161,7 +24161,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24172,7 +24172,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24183,7 +24183,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24194,7 +24194,7 @@ pub fn vsri_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24205,7 +24205,7 @@ pub fn vsriq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -24216,7 +24216,7 @@ pub fn vsrid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -24229,7 +24229,7 @@ pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24242,7 +24242,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24255,7 +24255,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24267,7 +24267,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24279,7 +24279,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24291,7 +24291,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24303,7 +24303,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24315,7 +24315,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24327,7 +24327,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24339,7 +24339,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24351,7 +24351,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24363,7 +24363,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24375,7 +24375,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24387,7 +24387,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24399,7 +24399,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24411,7 +24411,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24423,7 +24423,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24435,7 +24435,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24447,7 +24447,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24459,7 +24459,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24471,7 +24471,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24483,7 +24483,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24495,7 +24495,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24507,7 +24507,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24519,7 +24519,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24531,7 +24531,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24543,7 +24543,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24555,7 +24555,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -24567,7 +24567,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24585,7 +24585,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24603,7 +24603,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24621,7 +24621,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24639,7 +24639,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24663,7 +24663,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24687,7 +24687,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24700,7 +24700,7 @@ pub unsafe fn vst1_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24713,7 +24713,7 @@ pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(stp))]
@@ -24724,7 +24724,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24744,7 +24744,7 @@ pub unsafe fn vst2_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24764,7 +24764,7 @@ pub unsafe fn vst2_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24777,7 +24777,7 @@ pub unsafe fn vst2_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24790,7 +24790,7 @@ pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -24801,7 +24801,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -24812,7 +24812,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24832,7 +24832,7 @@ pub unsafe fn vst2q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24852,7 +24852,7 @@ pub unsafe fn vst2q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24872,7 +24872,7 @@ pub unsafe fn vst2q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24885,7 +24885,7 @@ pub unsafe fn vst2q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24898,7 +24898,7 @@ pub unsafe fn vst2q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24911,7 +24911,7 @@ pub unsafe fn vst2q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24924,7 +24924,7 @@ pub unsafe fn vst2q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24935,7 +24935,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -24946,7 +24946,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -24957,7 +24957,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24977,7 +24977,7 @@ pub unsafe fn vst3_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24997,7 +24997,7 @@ pub unsafe fn vst3_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -25010,7 +25010,7 @@ pub unsafe fn vst3_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -25023,7 +25023,7 @@ pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -25034,7 +25034,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -25045,7 +25045,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25065,7 +25065,7 @@ pub unsafe fn vst3q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25085,7 +25085,7 @@ pub unsafe fn vst3q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25105,7 +25105,7 @@ pub unsafe fn vst3q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -25118,7 +25118,7 @@ pub unsafe fn vst3q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -25131,7 +25131,7 @@ pub unsafe fn vst3q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -25144,7 +25144,7 @@ pub unsafe fn vst3q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -25157,7 +25157,7 @@ pub unsafe fn vst3q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -25168,7 +25168,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -25179,7 +25179,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -25190,7 +25190,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25217,7 +25217,7 @@ pub unsafe fn vst4_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25244,7 +25244,7 @@ pub unsafe fn vst4_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -25257,7 +25257,7 @@ pub unsafe fn vst4_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -25270,7 +25270,7 @@ pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -25281,7 +25281,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -25292,7 +25292,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25319,7 +25319,7 @@ pub unsafe fn vst4q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25346,7 +25346,7 @@ pub unsafe fn vst4q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25373,7 +25373,7 @@ pub unsafe fn vst4q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -25386,7 +25386,7 @@ pub unsafe fn vst4q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -25399,7 +25399,7 @@ pub unsafe fn vst4q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -25412,7 +25412,7 @@ pub unsafe fn vst4q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -25425,7 +25425,7 @@ pub unsafe fn vst4q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -25436,7 +25436,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -25447,7 +25447,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25461,7 +25461,7 @@ pub unsafe fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25475,7 +25475,7 @@ pub unsafe fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25489,7 +25489,7 @@ pub unsafe fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25503,7 +25503,7 @@ pub unsafe fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25517,7 +25517,7 @@ pub unsafe fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25531,7 +25531,7 @@ pub unsafe fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25547,7 +25547,7 @@ pub unsafe fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25561,7 +25561,7 @@ pub unsafe fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -25570,7 +25570,7 @@ pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -25579,7 +25579,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -25588,7 +25588,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -25597,7 +25597,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -25607,7 +25607,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -25622,7 +25622,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -25637,7 +25637,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -25652,7 +25652,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -25667,7 +25667,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -25682,7 +25682,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -25697,7 +25697,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -25709,7 +25709,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -25721,7 +25721,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -25733,7 +25733,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -25745,7 +25745,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -25757,7 +25757,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -25769,7 +25769,7 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25782,7 +25782,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25791,7 +25791,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25800,7 +25800,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25809,7 +25809,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25818,7 +25818,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25827,7 +25827,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25840,7 +25840,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25853,7 +25853,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25866,7 +25866,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25876,7 +25876,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25886,7 +25886,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25896,7 +25896,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25915,7 +25915,7 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25934,7 +25934,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25953,7 +25953,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25962,7 +25962,7 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25971,7 +25971,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25980,7 +25980,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26004,7 +26004,7 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26023,7 +26023,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26042,7 +26042,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26058,7 +26058,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26074,7 +26074,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26090,7 +26090,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26100,7 +26100,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26110,7 +26110,7 @@ pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26119,7 +26119,7 @@ pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26128,7 +26128,7 @@ pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26137,7 +26137,7 @@ pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26146,7 +26146,7 @@ pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26155,7 +26155,7 @@ pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26164,7 +26164,7 @@ pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26173,7 +26173,7 @@ pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26182,7 +26182,7 @@ pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26191,7 +26191,7 @@ pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26206,7 +26206,7 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26215,7 +26215,7 @@ pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26224,7 +26224,7 @@ pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26233,7 +26233,7 @@ pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26242,7 +26242,7 @@ pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26257,7 +26257,7 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26266,7 +26266,7 @@ pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26275,7 +26275,7 @@ pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26284,7 +26284,7 @@ pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26293,7 +26293,7 @@ pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26308,7 +26308,7 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26317,7 +26317,7 @@ pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -26326,7 +26326,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26336,7 +26336,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26346,7 +26346,7 @@ pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26355,7 +26355,7 @@ pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26364,7 +26364,7 @@ pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26373,7 +26373,7 @@ pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26382,7 +26382,7 @@ pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26391,7 +26391,7 @@ pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26400,7 +26400,7 @@ pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -26409,7 +26409,7 @@ pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26418,7 +26418,7 @@ pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26427,7 +26427,7 @@ pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26442,7 +26442,7 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26451,7 +26451,7 @@ pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26460,7 +26460,7 @@ pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26469,7 +26469,7 @@ pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26478,7 +26478,7 @@ pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26493,7 +26493,7 @@ pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26502,7 +26502,7 @@ pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26511,7 +26511,7 @@ pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26520,7 +26520,7 @@ pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26529,7 +26529,7 @@ pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26544,7 +26544,7 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26553,7 +26553,7 @@ pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -26562,7 +26562,7 @@ pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26575,7 +26575,7 @@ pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26588,7 +26588,7 @@ pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26601,7 +26601,7 @@ pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26614,7 +26614,7 @@ pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26627,7 +26627,7 @@ pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26640,7 +26640,7 @@ pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26649,7 +26649,7 @@ pub fn vtstd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare bitwise test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26658,7 +26658,7 @@ pub fn vtstd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26674,7 +26674,7 @@ pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26690,7 +26690,7 @@ pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26706,7 +26706,7 @@ pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26722,7 +26722,7 @@ pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26738,7 +26738,7 @@ pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26754,7 +26754,7 @@ pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26770,7 +26770,7 @@ pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -26786,7 +26786,7 @@ pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26795,7 +26795,7 @@ pub fn vuqaddb_s8(a: i8, b: u8) -> i8 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26804,7 +26804,7 @@ pub fn vuqaddh_s16(a: i16, b: u16) -> i16 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26820,7 +26820,7 @@ pub fn vuqaddd_s64(a: i64, b: u64) -> i64 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26836,7 +26836,7 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26846,7 +26846,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26856,7 +26856,7 @@ pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26865,7 +26865,7 @@ pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26874,7 +26874,7 @@ pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26883,7 +26883,7 @@ pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26892,7 +26892,7 @@ pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26901,7 +26901,7 @@ pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26910,7 +26910,7 @@ pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -26919,7 +26919,7 @@ pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26928,7 +26928,7 @@ pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26937,7 +26937,7 @@ pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26952,7 +26952,7 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26961,7 +26961,7 @@ pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26970,7 +26970,7 @@ pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26979,7 +26979,7 @@ pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -26988,7 +26988,7 @@ pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27003,7 +27003,7 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27012,7 +27012,7 @@ pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27021,7 +27021,7 @@ pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27030,7 +27030,7 @@ pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27039,7 +27039,7 @@ pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27054,7 +27054,7 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27063,7 +27063,7 @@ pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -27072,7 +27072,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27082,7 +27082,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27092,7 +27092,7 @@ pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27101,7 +27101,7 @@ pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27110,7 +27110,7 @@ pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27119,7 +27119,7 @@ pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27128,7 +27128,7 @@ pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27137,7 +27137,7 @@ pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27146,7 +27146,7 @@ pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27155,7 +27155,7 @@ pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27164,7 +27164,7 @@ pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27173,7 +27173,7 @@ pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27188,7 +27188,7 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27197,7 +27197,7 @@ pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27206,7 +27206,7 @@ pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27215,7 +27215,7 @@ pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27224,7 +27224,7 @@ pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27239,7 +27239,7 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27248,7 +27248,7 @@ pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27257,7 +27257,7 @@ pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27266,7 +27266,7 @@ pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27275,7 +27275,7 @@ pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27290,7 +27290,7 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27299,7 +27299,7 @@ pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -27308,7 +27308,7 @@ pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Exclusive OR and rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(xar, IMM6 = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27326,7 +27326,7 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27336,7 +27336,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27346,7 +27346,7 @@ pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27355,7 +27355,7 @@ pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27364,7 +27364,7 @@ pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27373,7 +27373,7 @@ pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27382,7 +27382,7 @@ pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27397,7 +27397,7 @@ pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27406,7 +27406,7 @@ pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27415,7 +27415,7 @@ pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27424,7 +27424,7 @@ pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27433,7 +27433,7 @@ pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27442,7 +27442,7 @@ pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27451,7 +27451,7 @@ pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27466,7 +27466,7 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27475,7 +27475,7 @@ pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27484,7 +27484,7 @@ pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27493,7 +27493,7 @@ pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27502,7 +27502,7 @@ pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27511,7 +27511,7 @@ pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27520,7 +27520,7 @@ pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27535,7 +27535,7 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27544,7 +27544,7 @@ pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27553,7 +27553,7 @@ pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27562,7 +27562,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27572,7 +27572,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27582,7 +27582,7 @@ pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27591,7 +27591,7 @@ pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27600,7 +27600,7 @@ pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27609,7 +27609,7 @@ pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27618,7 +27618,7 @@ pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27633,7 +27633,7 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27642,7 +27642,7 @@ pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27651,7 +27651,7 @@ pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27660,7 +27660,7 @@ pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27669,7 +27669,7 @@ pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27678,7 +27678,7 @@ pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27687,7 +27687,7 @@ pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27702,7 +27702,7 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27711,7 +27711,7 @@ pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27720,7 +27720,7 @@ pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27729,7 +27729,7 @@ pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27738,7 +27738,7 @@ pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27747,7 +27747,7 @@ pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27756,7 +27756,7 @@ pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27771,7 +27771,7 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27780,7 +27780,7 @@ pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27789,7 +27789,7 @@ pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
diff --git a/crates/core_arch/src/aarch64/sve/generated.rs b/crates/core_arch/src/aarch64/sve/generated.rs
index 5f26d61e7c..6c6a2476a4 100644
--- a/crates/core_arch/src/aarch64/sve/generated.rs
+++ b/crates/core_arch/src/aarch64/sve/generated.rs
@@ -15,7 +15,7 @@ use crate::core_arch::arch::aarch64::*;
 
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -28,7 +28,7 @@ pub fn svabd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -37,7 +37,7 @@ pub fn svabd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -46,7 +46,7 @@ pub fn svabd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -55,7 +55,7 @@ pub fn svabd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -64,7 +64,7 @@ pub fn svabd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -73,7 +73,7 @@ pub fn svabd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -86,7 +86,7 @@ pub fn svabd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -95,7 +95,7 @@ pub fn svabd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -104,7 +104,7 @@ pub fn svabd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -113,7 +113,7 @@ pub fn svabd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -122,7 +122,7 @@ pub fn svabd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -131,7 +131,7 @@ pub fn svabd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -144,7 +144,7 @@ pub fn svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -153,7 +153,7 @@ pub fn svabd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -162,7 +162,7 @@ pub fn svabd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -171,7 +171,7 @@ pub fn svabd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -180,7 +180,7 @@ pub fn svabd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -189,7 +189,7 @@ pub fn svabd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -202,7 +202,7 @@ pub fn svabd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -211,7 +211,7 @@ pub fn svabd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -220,7 +220,7 @@ pub fn svabd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -229,7 +229,7 @@ pub fn svabd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -238,7 +238,7 @@ pub fn svabd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -247,7 +247,7 @@ pub fn svabd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -260,7 +260,7 @@ pub fn svabd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -269,7 +269,7 @@ pub fn svabd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -278,7 +278,7 @@ pub fn svabd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -287,7 +287,7 @@ pub fn svabd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -296,7 +296,7 @@ pub fn svabd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -305,7 +305,7 @@ pub fn svabd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -318,7 +318,7 @@ pub fn svabd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -327,7 +327,7 @@ pub fn svabd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -336,7 +336,7 @@ pub fn svabd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -345,7 +345,7 @@ pub fn svabd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -354,7 +354,7 @@ pub fn svabd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabd))]
@@ -363,7 +363,7 @@ pub fn svabd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -376,7 +376,7 @@ pub fn svabd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -385,7 +385,7 @@ pub fn svabd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -394,7 +394,7 @@ pub fn svabd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -403,7 +403,7 @@ pub fn svabd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -412,7 +412,7 @@ pub fn svabd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -421,7 +421,7 @@ pub fn svabd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -434,7 +434,7 @@ pub fn svabd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -443,7 +443,7 @@ pub fn svabd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -452,7 +452,7 @@ pub fn svabd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -461,7 +461,7 @@ pub fn svabd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -470,7 +470,7 @@ pub fn svabd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -479,7 +479,7 @@ pub fn svabd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -492,7 +492,7 @@ pub fn svabd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -501,7 +501,7 @@ pub fn svabd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -510,7 +510,7 @@ pub fn svabd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -519,7 +519,7 @@ pub fn svabd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -528,7 +528,7 @@ pub fn svabd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -537,7 +537,7 @@ pub fn svabd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -550,7 +550,7 @@ pub fn svabd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -559,7 +559,7 @@ pub fn svabd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -568,7 +568,7 @@ pub fn svabd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -577,7 +577,7 @@ pub fn svabd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -586,7 +586,7 @@ pub fn svabd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabd))]
@@ -595,7 +595,7 @@ pub fn svabd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabs))]
@@ -608,7 +608,7 @@ pub fn svabs_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfl
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabs))]
@@ -617,7 +617,7 @@ pub fn svabs_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabs))]
@@ -626,7 +626,7 @@ pub fn svabs_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabs))]
@@ -639,7 +639,7 @@ pub fn svabs_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfl
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabs))]
@@ -648,7 +648,7 @@ pub fn svabs_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fabs))]
@@ -657,7 +657,7 @@ pub fn svabs_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -670,7 +670,7 @@ pub fn svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -679,7 +679,7 @@ pub fn svabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -688,7 +688,7 @@ pub fn svabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -701,7 +701,7 @@ pub fn svabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -710,7 +710,7 @@ pub fn svabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -719,7 +719,7 @@ pub fn svabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -732,7 +732,7 @@ pub fn svabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -741,7 +741,7 @@ pub fn svabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -750,7 +750,7 @@ pub fn svabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -763,7 +763,7 @@ pub fn svabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -772,7 +772,7 @@ pub fn svabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -781,7 +781,7 @@ pub fn svabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Absolute compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -794,7 +794,7 @@ pub fn svacge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Absolute compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -803,7 +803,7 @@ pub fn svacge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Absolute compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -816,7 +816,7 @@ pub fn svacge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Absolute compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -825,7 +825,7 @@ pub fn svacge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -838,7 +838,7 @@ pub fn svacgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -847,7 +847,7 @@ pub fn svacgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -860,7 +860,7 @@ pub fn svacgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -869,7 +869,7 @@ pub fn svacgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Absolute compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -878,7 +878,7 @@ pub fn svacle_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Absolute compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -887,7 +887,7 @@ pub fn svacle_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Absolute compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -896,7 +896,7 @@ pub fn svacle_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Absolute compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facge))]
@@ -905,7 +905,7 @@ pub fn svacle_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -914,7 +914,7 @@ pub fn svaclt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -923,7 +923,7 @@ pub fn svaclt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -932,7 +932,7 @@ pub fn svaclt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(facgt))]
@@ -941,7 +941,7 @@ pub fn svaclt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -954,7 +954,7 @@ pub fn svadd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -963,7 +963,7 @@ pub fn svadd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -972,7 +972,7 @@ pub fn svadd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -981,7 +981,7 @@ pub fn svadd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -990,7 +990,7 @@ pub fn svadd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -999,7 +999,7 @@ pub fn svadd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -1012,7 +1012,7 @@ pub fn svadd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -1021,7 +1021,7 @@ pub fn svadd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -1030,7 +1030,7 @@ pub fn svadd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -1039,7 +1039,7 @@ pub fn svadd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -1048,7 +1048,7 @@ pub fn svadd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadd))]
@@ -1057,7 +1057,7 @@ pub fn svadd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1070,7 +1070,7 @@ pub fn svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1079,7 +1079,7 @@ pub fn svadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1088,7 +1088,7 @@ pub fn svadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1097,7 +1097,7 @@ pub fn svadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1106,7 +1106,7 @@ pub fn svadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1115,7 +1115,7 @@ pub fn svadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1128,7 +1128,7 @@ pub fn svadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1137,7 +1137,7 @@ pub fn svadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1146,7 +1146,7 @@ pub fn svadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1155,7 +1155,7 @@ pub fn svadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1164,7 +1164,7 @@ pub fn svadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1173,7 +1173,7 @@ pub fn svadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1186,7 +1186,7 @@ pub fn svadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1195,7 +1195,7 @@ pub fn svadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1204,7 +1204,7 @@ pub fn svadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1213,7 +1213,7 @@ pub fn svadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1222,7 +1222,7 @@ pub fn svadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1231,7 +1231,7 @@ pub fn svadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1244,7 +1244,7 @@ pub fn svadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1253,7 +1253,7 @@ pub fn svadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1262,7 +1262,7 @@ pub fn svadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1271,7 +1271,7 @@ pub fn svadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1280,7 +1280,7 @@ pub fn svadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1289,7 +1289,7 @@ pub fn svadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1298,7 +1298,7 @@ pub fn svadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1307,7 +1307,7 @@ pub fn svadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1316,7 +1316,7 @@ pub fn svadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1325,7 +1325,7 @@ pub fn svadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1334,7 +1334,7 @@ pub fn svadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1343,7 +1343,7 @@ pub fn svadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1352,7 +1352,7 @@ pub fn svadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1361,7 +1361,7 @@ pub fn svadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1370,7 +1370,7 @@ pub fn svadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1379,7 +1379,7 @@ pub fn svadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1388,7 +1388,7 @@ pub fn svadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1397,7 +1397,7 @@ pub fn svadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1406,7 +1406,7 @@ pub fn svadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1415,7 +1415,7 @@ pub fn svadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1424,7 +1424,7 @@ pub fn svadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1433,7 +1433,7 @@ pub fn svadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1442,7 +1442,7 @@ pub fn svadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1451,7 +1451,7 @@ pub fn svadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1460,7 +1460,7 @@ pub fn svadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1469,7 +1469,7 @@ pub fn svadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1478,7 +1478,7 @@ pub fn svadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1487,7 +1487,7 @@ pub fn svadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1496,7 +1496,7 @@ pub fn svadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(add))]
@@ -1505,7 +1505,7 @@ pub fn svadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Add reduction (strictly-ordered)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadda))]
@@ -1518,7 +1518,7 @@ pub fn svadda_f32(pg: svbool_t, initial: f32, op: svfloat32_t) -> f32 {
 }
 #[doc = "Add reduction (strictly-ordered)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fadda))]
@@ -1531,7 +1531,7 @@ pub fn svadda_f64(pg: svbool_t, initial: f64, op: svfloat64_t) -> f64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(faddv))]
@@ -1544,7 +1544,7 @@ pub fn svaddv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(faddv))]
@@ -1557,7 +1557,7 @@ pub fn svaddv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddv))]
@@ -1570,7 +1570,7 @@ pub fn svaddv_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddv))]
@@ -1583,7 +1583,7 @@ pub fn svaddv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddv))]
@@ -1596,7 +1596,7 @@ pub fn svaddv_s8(pg: svbool_t, op: svint8_t) -> i64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddv))]
@@ -1609,7 +1609,7 @@ pub fn svaddv_s16(pg: svbool_t, op: svint16_t) -> i64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddv))]
@@ -1622,7 +1622,7 @@ pub fn svaddv_s32(pg: svbool_t, op: svint32_t) -> i64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddv))]
@@ -1635,7 +1635,7 @@ pub fn svaddv_u8(pg: svbool_t, op: svuint8_t) -> u64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddv))]
@@ -1648,7 +1648,7 @@ pub fn svaddv_u16(pg: svbool_t, op: svuint16_t) -> u64 {
 }
 #[doc = "Add reduction"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddv))]
@@ -1661,7 +1661,7 @@ pub fn svaddv_u32(pg: svbool_t, op: svuint32_t) -> u64 {
 }
 #[doc = "Compute vector addresses for 8-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[s32]offset)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1674,7 +1674,7 @@ pub fn svadrb_u32base_s32offset(bases: svuint32_t, offsets: svint32_t) -> svuint
 }
 #[doc = "Compute vector addresses for 16-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[s32]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1687,7 +1687,7 @@ pub fn svadrh_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint3
 }
 #[doc = "Compute vector addresses for 32-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[s32]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1700,7 +1700,7 @@ pub fn svadrw_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint3
 }
 #[doc = "Compute vector addresses for 64-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[s32]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1713,7 +1713,7 @@ pub fn svadrd_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint3
 }
 #[doc = "Compute vector addresses for 8-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[u32]offset)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1722,7 +1722,7 @@ pub fn svadrb_u32base_u32offset(bases: svuint32_t, offsets: svuint32_t) -> svuin
 }
 #[doc = "Compute vector addresses for 16-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[u32]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1731,7 +1731,7 @@ pub fn svadrh_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint
 }
 #[doc = "Compute vector addresses for 32-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[u32]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1740,7 +1740,7 @@ pub fn svadrw_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint
 }
 #[doc = "Compute vector addresses for 64-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[u32]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1749,7 +1749,7 @@ pub fn svadrd_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint
 }
 #[doc = "Compute vector addresses for 8-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[s64]offset)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1762,7 +1762,7 @@ pub fn svadrb_u64base_s64offset(bases: svuint64_t, offsets: svint64_t) -> svuint
 }
 #[doc = "Compute vector addresses for 16-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[s64]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1775,7 +1775,7 @@ pub fn svadrh_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint6
 }
 #[doc = "Compute vector addresses for 32-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[s64]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1788,7 +1788,7 @@ pub fn svadrw_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint6
 }
 #[doc = "Compute vector addresses for 64-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[s64]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1801,7 +1801,7 @@ pub fn svadrd_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint6
 }
 #[doc = "Compute vector addresses for 8-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[u64]offset)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1810,7 +1810,7 @@ pub fn svadrb_u64base_u64offset(bases: svuint64_t, offsets: svuint64_t) -> svuin
 }
 #[doc = "Compute vector addresses for 16-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[u64]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1819,7 +1819,7 @@ pub fn svadrh_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint
 }
 #[doc = "Compute vector addresses for 32-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[u64]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1828,7 +1828,7 @@ pub fn svadrw_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint
 }
 #[doc = "Compute vector addresses for 64-bit data"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[u64]index)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adr))]
@@ -1837,7 +1837,7 @@ pub fn svadrd_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1850,7 +1850,7 @@ pub fn svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1863,7 +1863,7 @@ pub fn svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1872,7 +1872,7 @@ pub fn svand_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1881,7 +1881,7 @@ pub fn svand_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1890,7 +1890,7 @@ pub fn svand_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1899,7 +1899,7 @@ pub fn svand_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1908,7 +1908,7 @@ pub fn svand_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1921,7 +1921,7 @@ pub fn svand_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1930,7 +1930,7 @@ pub fn svand_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1939,7 +1939,7 @@ pub fn svand_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1948,7 +1948,7 @@ pub fn svand_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1957,7 +1957,7 @@ pub fn svand_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1966,7 +1966,7 @@ pub fn svand_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1979,7 +1979,7 @@ pub fn svand_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1988,7 +1988,7 @@ pub fn svand_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -1997,7 +1997,7 @@ pub fn svand_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2006,7 +2006,7 @@ pub fn svand_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2015,7 +2015,7 @@ pub fn svand_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2024,7 +2024,7 @@ pub fn svand_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2037,7 +2037,7 @@ pub fn svand_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2046,7 +2046,7 @@ pub fn svand_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2055,7 +2055,7 @@ pub fn svand_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2064,7 +2064,7 @@ pub fn svand_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2073,7 +2073,7 @@ pub fn svand_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2082,7 +2082,7 @@ pub fn svand_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2091,7 +2091,7 @@ pub fn svand_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2100,7 +2100,7 @@ pub fn svand_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2109,7 +2109,7 @@ pub fn svand_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2118,7 +2118,7 @@ pub fn svand_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2127,7 +2127,7 @@ pub fn svand_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2136,7 +2136,7 @@ pub fn svand_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2145,7 +2145,7 @@ pub fn svand_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2154,7 +2154,7 @@ pub fn svand_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2163,7 +2163,7 @@ pub fn svand_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2172,7 +2172,7 @@ pub fn svand_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2181,7 +2181,7 @@ pub fn svand_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2190,7 +2190,7 @@ pub fn svand_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2199,7 +2199,7 @@ pub fn svand_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2208,7 +2208,7 @@ pub fn svand_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2217,7 +2217,7 @@ pub fn svand_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2226,7 +2226,7 @@ pub fn svand_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2235,7 +2235,7 @@ pub fn svand_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2244,7 +2244,7 @@ pub fn svand_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2253,7 +2253,7 @@ pub fn svand_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2262,7 +2262,7 @@ pub fn svand_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2271,7 +2271,7 @@ pub fn svand_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2280,7 +2280,7 @@ pub fn svand_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2289,7 +2289,7 @@ pub fn svand_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise AND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(and))]
@@ -2298,7 +2298,7 @@ pub fn svand_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2311,7 +2311,7 @@ pub fn svandv_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2324,7 +2324,7 @@ pub fn svandv_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2337,7 +2337,7 @@ pub fn svandv_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2350,7 +2350,7 @@ pub fn svandv_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2359,7 +2359,7 @@ pub fn svandv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2368,7 +2368,7 @@ pub fn svandv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2377,7 +2377,7 @@ pub fn svandv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Bitwise AND reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(andv))]
@@ -2386,7 +2386,7 @@ pub fn svandv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2399,7 +2399,7 @@ pub fn svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2408,7 +2408,7 @@ pub fn svasr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2417,7 +2417,7 @@ pub fn svasr_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2426,7 +2426,7 @@ pub fn svasr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2435,7 +2435,7 @@ pub fn svasr_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2444,7 +2444,7 @@ pub fn svasr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2457,7 +2457,7 @@ pub fn svasr_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2466,7 +2466,7 @@ pub fn svasr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2475,7 +2475,7 @@ pub fn svasr_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2484,7 +2484,7 @@ pub fn svasr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2493,7 +2493,7 @@ pub fn svasr_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2502,7 +2502,7 @@ pub fn svasr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2515,7 +2515,7 @@ pub fn svasr_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2524,7 +2524,7 @@ pub fn svasr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2533,7 +2533,7 @@ pub fn svasr_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2542,7 +2542,7 @@ pub fn svasr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2551,7 +2551,7 @@ pub fn svasr_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2560,7 +2560,7 @@ pub fn svasr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2573,7 +2573,7 @@ pub fn svasr_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2582,7 +2582,7 @@ pub fn svasr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2591,7 +2591,7 @@ pub fn svasr_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2600,7 +2600,7 @@ pub fn svasr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2609,7 +2609,7 @@ pub fn svasr_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2618,7 +2618,7 @@ pub fn svasr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2634,7 +2634,7 @@ pub fn svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2643,7 +2643,7 @@ pub fn svasr_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2652,7 +2652,7 @@ pub fn svasr_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2661,7 +2661,7 @@ pub fn svasr_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2670,7 +2670,7 @@ pub fn svasr_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2679,7 +2679,7 @@ pub fn svasr_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2695,7 +2695,7 @@ pub fn svasr_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint1
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2704,7 +2704,7 @@ pub fn svasr_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2713,7 +2713,7 @@ pub fn svasr_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint1
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2722,7 +2722,7 @@ pub fn svasr_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2731,7 +2731,7 @@ pub fn svasr_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint1
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2740,7 +2740,7 @@ pub fn svasr_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2756,7 +2756,7 @@ pub fn svasr_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint3
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2765,7 +2765,7 @@ pub fn svasr_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2774,7 +2774,7 @@ pub fn svasr_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint3
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2783,7 +2783,7 @@ pub fn svasr_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2792,7 +2792,7 @@ pub fn svasr_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint3
 }
 #[doc = "Arithmetic shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asr))]
@@ -2801,7 +2801,7 @@ pub fn svasr_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2815,7 +2815,7 @@ pub fn svasrd_n_s8_m<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2824,7 +2824,7 @@ pub fn svasrd_n_s8_x<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2833,7 +2833,7 @@ pub fn svasrd_n_s8_z<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2847,7 +2847,7 @@ pub fn svasrd_n_s16_m<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2856,7 +2856,7 @@ pub fn svasrd_n_s16_x<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2865,7 +2865,7 @@ pub fn svasrd_n_s16_z<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2879,7 +2879,7 @@ pub fn svasrd_n_s32_m<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2888,7 +2888,7 @@ pub fn svasrd_n_s32_x<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2897,7 +2897,7 @@ pub fn svasrd_n_s32_z<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2911,7 +2911,7 @@ pub fn svasrd_n_s64_m<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2920,7 +2920,7 @@ pub fn svasrd_n_s64_x<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 }
 #[doc = "Arithmetic shift right for divide by immediate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(asrd, IMM2 = 1))]
@@ -2929,7 +2929,7 @@ pub fn svasrd_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -2942,7 +2942,7 @@ pub fn svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -2955,7 +2955,7 @@ pub fn svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -2964,7 +2964,7 @@ pub fn svbic_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -2973,7 +2973,7 @@ pub fn svbic_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -2982,7 +2982,7 @@ pub fn svbic_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -2991,7 +2991,7 @@ pub fn svbic_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3000,7 +3000,7 @@ pub fn svbic_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3013,7 +3013,7 @@ pub fn svbic_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3022,7 +3022,7 @@ pub fn svbic_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3031,7 +3031,7 @@ pub fn svbic_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3040,7 +3040,7 @@ pub fn svbic_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3049,7 +3049,7 @@ pub fn svbic_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3058,7 +3058,7 @@ pub fn svbic_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3071,7 +3071,7 @@ pub fn svbic_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3080,7 +3080,7 @@ pub fn svbic_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3089,7 +3089,7 @@ pub fn svbic_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3098,7 +3098,7 @@ pub fn svbic_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3107,7 +3107,7 @@ pub fn svbic_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3116,7 +3116,7 @@ pub fn svbic_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3129,7 +3129,7 @@ pub fn svbic_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3138,7 +3138,7 @@ pub fn svbic_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3147,7 +3147,7 @@ pub fn svbic_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3156,7 +3156,7 @@ pub fn svbic_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3165,7 +3165,7 @@ pub fn svbic_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3174,7 +3174,7 @@ pub fn svbic_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3183,7 +3183,7 @@ pub fn svbic_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3192,7 +3192,7 @@ pub fn svbic_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3201,7 +3201,7 @@ pub fn svbic_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3210,7 +3210,7 @@ pub fn svbic_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3219,7 +3219,7 @@ pub fn svbic_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3228,7 +3228,7 @@ pub fn svbic_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3237,7 +3237,7 @@ pub fn svbic_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3246,7 +3246,7 @@ pub fn svbic_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3255,7 +3255,7 @@ pub fn svbic_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3264,7 +3264,7 @@ pub fn svbic_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3273,7 +3273,7 @@ pub fn svbic_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3282,7 +3282,7 @@ pub fn svbic_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3291,7 +3291,7 @@ pub fn svbic_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3300,7 +3300,7 @@ pub fn svbic_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3309,7 +3309,7 @@ pub fn svbic_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3318,7 +3318,7 @@ pub fn svbic_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3327,7 +3327,7 @@ pub fn svbic_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3336,7 +3336,7 @@ pub fn svbic_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3345,7 +3345,7 @@ pub fn svbic_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3354,7 +3354,7 @@ pub fn svbic_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3363,7 +3363,7 @@ pub fn svbic_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3372,7 +3372,7 @@ pub fn svbic_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3381,7 +3381,7 @@ pub fn svbic_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise clear"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bic))]
@@ -3390,7 +3390,7 @@ pub fn svbic_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Break after first true condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brka))]
@@ -3403,7 +3403,7 @@ pub fn svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Break after first true condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brka))]
@@ -3416,7 +3416,7 @@ pub fn svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Break before first true condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brkb))]
@@ -3429,7 +3429,7 @@ pub fn svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Break before first true condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brkb))]
@@ -3442,7 +3442,7 @@ pub fn svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Propagate break to next partition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkn[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brkn))]
@@ -3455,7 +3455,7 @@ pub fn svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Break after first true condition, propagating from previous partition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpa[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brkpa))]
@@ -3471,7 +3471,7 @@ pub fn svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Break before first true condition, propagating from previous partition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpb[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(brkpb))]
@@ -3487,7 +3487,7 @@ pub fn svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
@@ -3510,7 +3510,7 @@ pub fn svcadd_f32_m<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
@@ -3523,7 +3523,7 @@ pub fn svcadd_f32_x<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
@@ -3536,7 +3536,7 @@ pub fn svcadd_f32_z<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
@@ -3559,7 +3559,7 @@ pub fn svcadd_f64_m<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
@@ -3572,7 +3572,7 @@ pub fn svcadd_f64_x<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))]
@@ -3585,7 +3585,7 @@ pub fn svcadd_f64_z<const IMM_ROTATION: i32>(
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3598,7 +3598,7 @@ pub fn svclasta_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> s
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3611,7 +3611,7 @@ pub fn svclasta_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> s
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3624,7 +3624,7 @@ pub fn svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3637,7 +3637,7 @@ pub fn svclasta_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3650,7 +3650,7 @@ pub fn svclasta_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3663,7 +3663,7 @@ pub fn svclasta_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3672,7 +3672,7 @@ pub fn svclasta_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3681,7 +3681,7 @@ pub fn svclasta_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svu
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3690,7 +3690,7 @@ pub fn svclasta_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svu
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3699,7 +3699,7 @@ pub fn svclasta_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svu
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3715,7 +3715,7 @@ pub fn svclasta_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3731,7 +3731,7 @@ pub fn svclasta_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3747,7 +3747,7 @@ pub fn svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3763,7 +3763,7 @@ pub fn svclasta_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3779,7 +3779,7 @@ pub fn svclasta_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3795,7 +3795,7 @@ pub fn svclasta_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3804,7 +3804,7 @@ pub fn svclasta_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3813,7 +3813,7 @@ pub fn svclasta_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3822,7 +3822,7 @@ pub fn svclasta_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 {
 }
 #[doc = "Conditionally extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clasta))]
@@ -3831,7 +3831,7 @@ pub fn svclasta_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3844,7 +3844,7 @@ pub fn svclastb_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> s
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3857,7 +3857,7 @@ pub fn svclastb_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> s
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3870,7 +3870,7 @@ pub fn svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3883,7 +3883,7 @@ pub fn svclastb_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3896,7 +3896,7 @@ pub fn svclastb_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3909,7 +3909,7 @@ pub fn svclastb_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3918,7 +3918,7 @@ pub fn svclastb_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3927,7 +3927,7 @@ pub fn svclastb_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svu
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3936,7 +3936,7 @@ pub fn svclastb_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svu
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3945,7 +3945,7 @@ pub fn svclastb_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svu
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3961,7 +3961,7 @@ pub fn svclastb_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3977,7 +3977,7 @@ pub fn svclastb_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -3993,7 +3993,7 @@ pub fn svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4009,7 +4009,7 @@ pub fn svclastb_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4025,7 +4025,7 @@ pub fn svclastb_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4041,7 +4041,7 @@ pub fn svclastb_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4050,7 +4050,7 @@ pub fn svclastb_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4059,7 +4059,7 @@ pub fn svclastb_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4068,7 +4068,7 @@ pub fn svclastb_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 {
 }
 #[doc = "Conditionally extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clastb))]
@@ -4077,7 +4077,7 @@ pub fn svclastb_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4090,7 +4090,7 @@ pub fn svcls_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4099,7 +4099,7 @@ pub fn svcls_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4108,7 +4108,7 @@ pub fn svcls_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4121,7 +4121,7 @@ pub fn svcls_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint1
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4130,7 +4130,7 @@ pub fn svcls_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4139,7 +4139,7 @@ pub fn svcls_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4152,7 +4152,7 @@ pub fn svcls_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint3
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4161,7 +4161,7 @@ pub fn svcls_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4170,7 +4170,7 @@ pub fn svcls_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4183,7 +4183,7 @@ pub fn svcls_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint6
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4192,7 +4192,7 @@ pub fn svcls_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cls))]
@@ -4201,7 +4201,7 @@ pub fn svcls_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4214,7 +4214,7 @@ pub fn svclz_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4223,7 +4223,7 @@ pub fn svclz_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4232,7 +4232,7 @@ pub fn svclz_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4245,7 +4245,7 @@ pub fn svclz_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint1
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4254,7 +4254,7 @@ pub fn svclz_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4263,7 +4263,7 @@ pub fn svclz_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4276,7 +4276,7 @@ pub fn svclz_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint3
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4285,7 +4285,7 @@ pub fn svclz_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4294,7 +4294,7 @@ pub fn svclz_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4307,7 +4307,7 @@ pub fn svclz_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint6
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4316,7 +4316,7 @@ pub fn svclz_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4325,7 +4325,7 @@ pub fn svclz_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4334,7 +4334,7 @@ pub fn svclz_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4343,7 +4343,7 @@ pub fn svclz_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4352,7 +4352,7 @@ pub fn svclz_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4361,7 +4361,7 @@ pub fn svclz_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4370,7 +4370,7 @@ pub fn svclz_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4379,7 +4379,7 @@ pub fn svclz_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4388,7 +4388,7 @@ pub fn svclz_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4397,7 +4397,7 @@ pub fn svclz_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4406,7 +4406,7 @@ pub fn svclz_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4415,7 +4415,7 @@ pub fn svclz_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4424,7 +4424,7 @@ pub fn svclz_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(clz))]
@@ -4433,7 +4433,7 @@ pub fn svclz_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
@@ -4460,7 +4460,7 @@ pub fn svcmla_f32_m<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
@@ -4474,7 +4474,7 @@ pub fn svcmla_f32_x<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
@@ -4488,7 +4488,7 @@ pub fn svcmla_f32_z<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
@@ -4515,7 +4515,7 @@ pub fn svcmla_f64_m<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
@@ -4529,7 +4529,7 @@ pub fn svcmla_f64_x<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))]
@@ -4543,7 +4543,7 @@ pub fn svcmla_f64_z<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -4573,7 +4573,7 @@ pub fn svcmla_lane_f32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmeq))]
@@ -4586,7 +4586,7 @@ pub fn svcmpeq_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmeq))]
@@ -4595,7 +4595,7 @@ pub fn svcmpeq_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmeq))]
@@ -4608,7 +4608,7 @@ pub fn svcmpeq_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmeq))]
@@ -4617,7 +4617,7 @@ pub fn svcmpeq_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4630,7 +4630,7 @@ pub fn svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4639,7 +4639,7 @@ pub fn svcmpeq_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4652,7 +4652,7 @@ pub fn svcmpeq_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4661,7 +4661,7 @@ pub fn svcmpeq_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4674,7 +4674,7 @@ pub fn svcmpeq_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4683,7 +4683,7 @@ pub fn svcmpeq_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4696,7 +4696,7 @@ pub fn svcmpeq_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4705,7 +4705,7 @@ pub fn svcmpeq_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4714,7 +4714,7 @@ pub fn svcmpeq_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4723,7 +4723,7 @@ pub fn svcmpeq_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4732,7 +4732,7 @@ pub fn svcmpeq_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4741,7 +4741,7 @@ pub fn svcmpeq_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4750,7 +4750,7 @@ pub fn svcmpeq_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4759,7 +4759,7 @@ pub fn svcmpeq_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4768,7 +4768,7 @@ pub fn svcmpeq_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4777,7 +4777,7 @@ pub fn svcmpeq_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4793,7 +4793,7 @@ pub fn svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4802,7 +4802,7 @@ pub fn svcmpeq_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4818,7 +4818,7 @@ pub fn svcmpeq_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4827,7 +4827,7 @@ pub fn svcmpeq_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4843,7 +4843,7 @@ pub fn svcmpeq_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpeq))]
@@ -4852,7 +4852,7 @@ pub fn svcmpeq_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -4865,7 +4865,7 @@ pub fn svcmpge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -4874,7 +4874,7 @@ pub fn svcmpge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -4887,7 +4887,7 @@ pub fn svcmpge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -4896,7 +4896,7 @@ pub fn svcmpge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4909,7 +4909,7 @@ pub fn svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4918,7 +4918,7 @@ pub fn svcmpge_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4931,7 +4931,7 @@ pub fn svcmpge_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4940,7 +4940,7 @@ pub fn svcmpge_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4953,7 +4953,7 @@ pub fn svcmpge_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4962,7 +4962,7 @@ pub fn svcmpge_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4975,7 +4975,7 @@ pub fn svcmpge_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -4984,7 +4984,7 @@ pub fn svcmpge_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -4997,7 +4997,7 @@ pub fn svcmpge_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5006,7 +5006,7 @@ pub fn svcmpge_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5019,7 +5019,7 @@ pub fn svcmpge_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5028,7 +5028,7 @@ pub fn svcmpge_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5041,7 +5041,7 @@ pub fn svcmpge_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5050,7 +5050,7 @@ pub fn svcmpge_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5063,7 +5063,7 @@ pub fn svcmpge_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5072,7 +5072,7 @@ pub fn svcmpge_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5088,7 +5088,7 @@ pub fn svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5097,7 +5097,7 @@ pub fn svcmpge_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5113,7 +5113,7 @@ pub fn svcmpge_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5122,7 +5122,7 @@ pub fn svcmpge_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5138,7 +5138,7 @@ pub fn svcmpge_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5147,7 +5147,7 @@ pub fn svcmpge_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5163,7 +5163,7 @@ pub fn svcmpge_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5172,7 +5172,7 @@ pub fn svcmpge_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5188,7 +5188,7 @@ pub fn svcmpge_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5197,7 +5197,7 @@ pub fn svcmpge_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5213,7 +5213,7 @@ pub fn svcmpge_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5222,7 +5222,7 @@ pub fn svcmpge_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5235,7 +5235,7 @@ pub fn svcmpgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5244,7 +5244,7 @@ pub fn svcmpgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5257,7 +5257,7 @@ pub fn svcmpgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5266,7 +5266,7 @@ pub fn svcmpgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5279,7 +5279,7 @@ pub fn svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5288,7 +5288,7 @@ pub fn svcmpgt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5301,7 +5301,7 @@ pub fn svcmpgt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5310,7 +5310,7 @@ pub fn svcmpgt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5323,7 +5323,7 @@ pub fn svcmpgt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5332,7 +5332,7 @@ pub fn svcmpgt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5345,7 +5345,7 @@ pub fn svcmpgt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5354,7 +5354,7 @@ pub fn svcmpgt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5367,7 +5367,7 @@ pub fn svcmpgt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5376,7 +5376,7 @@ pub fn svcmpgt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5389,7 +5389,7 @@ pub fn svcmpgt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5398,7 +5398,7 @@ pub fn svcmpgt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5411,7 +5411,7 @@ pub fn svcmpgt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5420,7 +5420,7 @@ pub fn svcmpgt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5433,7 +5433,7 @@ pub fn svcmpgt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5442,7 +5442,7 @@ pub fn svcmpgt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5458,7 +5458,7 @@ pub fn svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5467,7 +5467,7 @@ pub fn svcmpgt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5483,7 +5483,7 @@ pub fn svcmpgt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5492,7 +5492,7 @@ pub fn svcmpgt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5508,7 +5508,7 @@ pub fn svcmpgt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5517,7 +5517,7 @@ pub fn svcmpgt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5533,7 +5533,7 @@ pub fn svcmpgt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5542,7 +5542,7 @@ pub fn svcmpgt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5558,7 +5558,7 @@ pub fn svcmpgt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5567,7 +5567,7 @@ pub fn svcmpgt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5583,7 +5583,7 @@ pub fn svcmpgt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -5592,7 +5592,7 @@ pub fn svcmpgt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -5601,7 +5601,7 @@ pub fn svcmple_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -5610,7 +5610,7 @@ pub fn svcmple_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -5619,7 +5619,7 @@ pub fn svcmple_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmge))]
@@ -5628,7 +5628,7 @@ pub fn svcmple_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5637,7 +5637,7 @@ pub fn svcmple_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5646,7 +5646,7 @@ pub fn svcmple_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5655,7 +5655,7 @@ pub fn svcmple_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5664,7 +5664,7 @@ pub fn svcmple_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5673,7 +5673,7 @@ pub fn svcmple_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5682,7 +5682,7 @@ pub fn svcmple_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5691,7 +5691,7 @@ pub fn svcmple_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpge))]
@@ -5700,7 +5700,7 @@ pub fn svcmple_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5709,7 +5709,7 @@ pub fn svcmple_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5718,7 +5718,7 @@ pub fn svcmple_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5727,7 +5727,7 @@ pub fn svcmple_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5736,7 +5736,7 @@ pub fn svcmple_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5745,7 +5745,7 @@ pub fn svcmple_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5754,7 +5754,7 @@ pub fn svcmple_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5763,7 +5763,7 @@ pub fn svcmple_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphs))]
@@ -5772,7 +5772,7 @@ pub fn svcmple_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmple))]
@@ -5788,7 +5788,7 @@ pub fn svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmple))]
@@ -5797,7 +5797,7 @@ pub fn svcmple_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmple))]
@@ -5813,7 +5813,7 @@ pub fn svcmple_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmple))]
@@ -5822,7 +5822,7 @@ pub fn svcmple_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmple))]
@@ -5838,7 +5838,7 @@ pub fn svcmple_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmple))]
@@ -5847,7 +5847,7 @@ pub fn svcmple_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpls))]
@@ -5863,7 +5863,7 @@ pub fn svcmple_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpls))]
@@ -5872,7 +5872,7 @@ pub fn svcmple_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpls))]
@@ -5888,7 +5888,7 @@ pub fn svcmple_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpls))]
@@ -5897,7 +5897,7 @@ pub fn svcmple_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpls))]
@@ -5913,7 +5913,7 @@ pub fn svcmple_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpls))]
@@ -5922,7 +5922,7 @@ pub fn svcmple_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5931,7 +5931,7 @@ pub fn svcmplt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5940,7 +5940,7 @@ pub fn svcmplt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5949,7 +5949,7 @@ pub fn svcmplt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmgt))]
@@ -5958,7 +5958,7 @@ pub fn svcmplt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5967,7 +5967,7 @@ pub fn svcmplt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5976,7 +5976,7 @@ pub fn svcmplt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5985,7 +5985,7 @@ pub fn svcmplt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -5994,7 +5994,7 @@ pub fn svcmplt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -6003,7 +6003,7 @@ pub fn svcmplt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -6012,7 +6012,7 @@ pub fn svcmplt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -6021,7 +6021,7 @@ pub fn svcmplt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpgt))]
@@ -6030,7 +6030,7 @@ pub fn svcmplt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6039,7 +6039,7 @@ pub fn svcmplt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6048,7 +6048,7 @@ pub fn svcmplt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6057,7 +6057,7 @@ pub fn svcmplt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6066,7 +6066,7 @@ pub fn svcmplt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6075,7 +6075,7 @@ pub fn svcmplt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6084,7 +6084,7 @@ pub fn svcmplt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6093,7 +6093,7 @@ pub fn svcmplt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmphi))]
@@ -6102,7 +6102,7 @@ pub fn svcmplt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplt))]
@@ -6118,7 +6118,7 @@ pub fn svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplt))]
@@ -6127,7 +6127,7 @@ pub fn svcmplt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplt))]
@@ -6143,7 +6143,7 @@ pub fn svcmplt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplt))]
@@ -6152,7 +6152,7 @@ pub fn svcmplt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplt))]
@@ -6168,7 +6168,7 @@ pub fn svcmplt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplt))]
@@ -6177,7 +6177,7 @@ pub fn svcmplt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplo))]
@@ -6193,7 +6193,7 @@ pub fn svcmplt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplo))]
@@ -6202,7 +6202,7 @@ pub fn svcmplt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplo))]
@@ -6218,7 +6218,7 @@ pub fn svcmplt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplo))]
@@ -6227,7 +6227,7 @@ pub fn svcmplt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplo))]
@@ -6243,7 +6243,7 @@ pub fn svcmplt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svboo
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmplo))]
@@ -6252,7 +6252,7 @@ pub fn svcmplt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmne))]
@@ -6265,7 +6265,7 @@ pub fn svcmpne_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmne))]
@@ -6274,7 +6274,7 @@ pub fn svcmpne_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmne))]
@@ -6287,7 +6287,7 @@ pub fn svcmpne_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmne))]
@@ -6296,7 +6296,7 @@ pub fn svcmpne_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6309,7 +6309,7 @@ pub fn svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6318,7 +6318,7 @@ pub fn svcmpne_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6331,7 +6331,7 @@ pub fn svcmpne_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6340,7 +6340,7 @@ pub fn svcmpne_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6353,7 +6353,7 @@ pub fn svcmpne_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6362,7 +6362,7 @@ pub fn svcmpne_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6375,7 +6375,7 @@ pub fn svcmpne_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6384,7 +6384,7 @@ pub fn svcmpne_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6393,7 +6393,7 @@ pub fn svcmpne_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6402,7 +6402,7 @@ pub fn svcmpne_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6411,7 +6411,7 @@ pub fn svcmpne_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6420,7 +6420,7 @@ pub fn svcmpne_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6429,7 +6429,7 @@ pub fn svcmpne_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6438,7 +6438,7 @@ pub fn svcmpne_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6447,7 +6447,7 @@ pub fn svcmpne_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6456,7 +6456,7 @@ pub fn svcmpne_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6472,7 +6472,7 @@ pub fn svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6481,7 +6481,7 @@ pub fn svcmpne_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6497,7 +6497,7 @@ pub fn svcmpne_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6506,7 +6506,7 @@ pub fn svcmpne_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6522,7 +6522,7 @@ pub fn svcmpne_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_
 }
 #[doc = "Compare not equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmpne))]
@@ -6531,7 +6531,7 @@ pub fn svcmpne_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t {
 }
 #[doc = "Compare unordered with"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmuo))]
@@ -6544,7 +6544,7 @@ pub fn svcmpuo_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t
 }
 #[doc = "Compare unordered with"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmuo))]
@@ -6553,7 +6553,7 @@ pub fn svcmpuo_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t {
 }
 #[doc = "Compare unordered with"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmuo))]
@@ -6566,7 +6566,7 @@ pub fn svcmpuo_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t
 }
 #[doc = "Compare unordered with"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcmuo))]
@@ -6575,7 +6575,7 @@ pub fn svcmpuo_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6588,7 +6588,7 @@ pub fn svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6597,7 +6597,7 @@ pub fn svcnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6606,7 +6606,7 @@ pub fn svcnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6619,7 +6619,7 @@ pub fn svcnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6628,7 +6628,7 @@ pub fn svcnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6637,7 +6637,7 @@ pub fn svcnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6650,7 +6650,7 @@ pub fn svcnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6659,7 +6659,7 @@ pub fn svcnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6668,7 +6668,7 @@ pub fn svcnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6681,7 +6681,7 @@ pub fn svcnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6690,7 +6690,7 @@ pub fn svcnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6699,7 +6699,7 @@ pub fn svcnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6708,7 +6708,7 @@ pub fn svcnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6717,7 +6717,7 @@ pub fn svcnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6726,7 +6726,7 @@ pub fn svcnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6735,7 +6735,7 @@ pub fn svcnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuin
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6744,7 +6744,7 @@ pub fn svcnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6753,7 +6753,7 @@ pub fn svcnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6762,7 +6762,7 @@ pub fn svcnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuin
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6771,7 +6771,7 @@ pub fn svcnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6780,7 +6780,7 @@ pub fn svcnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6789,7 +6789,7 @@ pub fn svcnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6798,7 +6798,7 @@ pub fn svcnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Logically invert boolean condition"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnot))]
@@ -6807,7 +6807,7 @@ pub fn svcnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6820,7 +6820,7 @@ pub fn svcnt_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuin
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6829,7 +6829,7 @@ pub fn svcnt_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6838,7 +6838,7 @@ pub fn svcnt_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6851,7 +6851,7 @@ pub fn svcnt_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuin
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6860,7 +6860,7 @@ pub fn svcnt_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6869,7 +6869,7 @@ pub fn svcnt_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6882,7 +6882,7 @@ pub fn svcnt_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6891,7 +6891,7 @@ pub fn svcnt_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6900,7 +6900,7 @@ pub fn svcnt_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6913,7 +6913,7 @@ pub fn svcnt_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint1
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6922,7 +6922,7 @@ pub fn svcnt_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6931,7 +6931,7 @@ pub fn svcnt_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6944,7 +6944,7 @@ pub fn svcnt_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint3
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6953,7 +6953,7 @@ pub fn svcnt_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6962,7 +6962,7 @@ pub fn svcnt_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6975,7 +6975,7 @@ pub fn svcnt_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint6
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6984,7 +6984,7 @@ pub fn svcnt_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -6993,7 +6993,7 @@ pub fn svcnt_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7002,7 +7002,7 @@ pub fn svcnt_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7011,7 +7011,7 @@ pub fn svcnt_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7020,7 +7020,7 @@ pub fn svcnt_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7029,7 +7029,7 @@ pub fn svcnt_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7038,7 +7038,7 @@ pub fn svcnt_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7047,7 +7047,7 @@ pub fn svcnt_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7056,7 +7056,7 @@ pub fn svcnt_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7065,7 +7065,7 @@ pub fn svcnt_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7074,7 +7074,7 @@ pub fn svcnt_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7083,7 +7083,7 @@ pub fn svcnt_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7092,7 +7092,7 @@ pub fn svcnt_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Count nonzero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnt))]
@@ -7101,7 +7101,7 @@ pub fn svcnt_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Count the number of 8-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rdvl))]
@@ -7110,7 +7110,7 @@ pub fn svcntb() -> u64 {
 }
 #[doc = "Count the number of 16-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnth))]
@@ -7119,7 +7119,7 @@ pub fn svcnth() -> u64 {
 }
 #[doc = "Count the number of 32-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntw))]
@@ -7128,7 +7128,7 @@ pub fn svcntw() -> u64 {
 }
 #[doc = "Count the number of 64-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntd))]
@@ -7137,7 +7137,7 @@ pub fn svcntd() -> u64 {
 }
 #[doc = "Count the number of 8-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb_pat)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (rdvl , PATTERN = { svpattern :: SV_ALL }))]
@@ -7151,7 +7151,7 @@ pub fn svcntb_pat<const PATTERN: svpattern>() -> u64 {
 }
 #[doc = "Count the number of 16-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth_pat)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (cnth , PATTERN = { svpattern :: SV_ALL }))]
@@ -7164,7 +7164,7 @@ pub fn svcnth_pat<const PATTERN: svpattern>() -> u64 {
 }
 #[doc = "Count the number of 32-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw_pat)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (cntw , PATTERN = { svpattern :: SV_ALL }))]
@@ -7177,7 +7177,7 @@ pub fn svcntw_pat<const PATTERN: svpattern>() -> u64 {
 }
 #[doc = "Count the number of 64-bit elements in a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd_pat)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (cntd , PATTERN = { svpattern :: SV_ALL }))]
@@ -7190,7 +7190,7 @@ pub fn svcntd_pat<const PATTERN: svpattern>() -> u64 {
 }
 #[doc = "Count set predicate bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntp))]
@@ -7203,7 +7203,7 @@ pub fn svcntp_b8(pg: svbool_t, op: svbool_t) -> u64 {
 }
 #[doc = "Count set predicate bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntp))]
@@ -7216,7 +7216,7 @@ pub fn svcntp_b16(pg: svbool_t, op: svbool_t) -> u64 {
 }
 #[doc = "Count set predicate bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntp))]
@@ -7229,7 +7229,7 @@ pub fn svcntp_b32(pg: svbool_t, op: svbool_t) -> u64 {
 }
 #[doc = "Count set predicate bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntp))]
@@ -7242,7 +7242,7 @@ pub fn svcntp_b64(pg: svbool_t, op: svbool_t) -> u64 {
 }
 #[doc = "Shuffle active elements of vector to the right and fill with zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(compact))]
@@ -7258,7 +7258,7 @@ pub fn svcompact_f32(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Shuffle active elements of vector to the right and fill with zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(compact))]
@@ -7274,7 +7274,7 @@ pub fn svcompact_f64(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Shuffle active elements of vector to the right and fill with zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(compact))]
@@ -7290,7 +7290,7 @@ pub fn svcompact_s32(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Shuffle active elements of vector to the right and fill with zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(compact))]
@@ -7306,7 +7306,7 @@ pub fn svcompact_s64(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Shuffle active elements of vector to the right and fill with zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(compact))]
@@ -7315,7 +7315,7 @@ pub fn svcompact_u32(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Shuffle active elements of vector to the right and fill with zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(compact))]
@@ -7324,7 +7324,7 @@ pub fn svcompact_u64(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_f32(x0: svfloat32_t, x1: svfloat32_t) -> svfloat32x2_t {
@@ -7332,7 +7332,7 @@ pub fn svcreate2_f32(x0: svfloat32_t, x1: svfloat32_t) -> svfloat32x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_f64(x0: svfloat64_t, x1: svfloat64_t) -> svfloat64x2_t {
@@ -7340,7 +7340,7 @@ pub fn svcreate2_f64(x0: svfloat64_t, x1: svfloat64_t) -> svfloat64x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_s8(x0: svint8_t, x1: svint8_t) -> svint8x2_t {
@@ -7348,7 +7348,7 @@ pub fn svcreate2_s8(x0: svint8_t, x1: svint8_t) -> svint8x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_s16(x0: svint16_t, x1: svint16_t) -> svint16x2_t {
@@ -7356,7 +7356,7 @@ pub fn svcreate2_s16(x0: svint16_t, x1: svint16_t) -> svint16x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_s32(x0: svint32_t, x1: svint32_t) -> svint32x2_t {
@@ -7364,7 +7364,7 @@ pub fn svcreate2_s32(x0: svint32_t, x1: svint32_t) -> svint32x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_s64(x0: svint64_t, x1: svint64_t) -> svint64x2_t {
@@ -7372,7 +7372,7 @@ pub fn svcreate2_s64(x0: svint64_t, x1: svint64_t) -> svint64x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_u8(x0: svuint8_t, x1: svuint8_t) -> svuint8x2_t {
@@ -7380,7 +7380,7 @@ pub fn svcreate2_u8(x0: svuint8_t, x1: svuint8_t) -> svuint8x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_u16(x0: svuint16_t, x1: svuint16_t) -> svuint16x2_t {
@@ -7388,7 +7388,7 @@ pub fn svcreate2_u16(x0: svuint16_t, x1: svuint16_t) -> svuint16x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_u32(x0: svuint32_t, x1: svuint32_t) -> svuint32x2_t {
@@ -7396,7 +7396,7 @@ pub fn svcreate2_u32(x0: svuint32_t, x1: svuint32_t) -> svuint32x2_t {
 }
 #[doc = "Create a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate2_u64(x0: svuint64_t, x1: svuint64_t) -> svuint64x2_t {
@@ -7404,7 +7404,7 @@ pub fn svcreate2_u64(x0: svuint64_t, x1: svuint64_t) -> svuint64x2_t {
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_f32(x0: svfloat32_t, x1: svfloat32_t, x2: svfloat32_t) -> svfloat32x3_t {
@@ -7412,7 +7412,7 @@ pub fn svcreate3_f32(x0: svfloat32_t, x1: svfloat32_t, x2: svfloat32_t) -> svflo
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_f64(x0: svfloat64_t, x1: svfloat64_t, x2: svfloat64_t) -> svfloat64x3_t {
@@ -7420,7 +7420,7 @@ pub fn svcreate3_f64(x0: svfloat64_t, x1: svfloat64_t, x2: svfloat64_t) -> svflo
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t) -> svint8x3_t {
@@ -7428,7 +7428,7 @@ pub fn svcreate3_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t) -> svint8x3_t {
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t) -> svint16x3_t {
@@ -7436,7 +7436,7 @@ pub fn svcreate3_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t) -> svint16x3_t
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t) -> svint32x3_t {
@@ -7444,7 +7444,7 @@ pub fn svcreate3_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t) -> svint32x3_t
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t) -> svint64x3_t {
@@ -7452,7 +7452,7 @@ pub fn svcreate3_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t) -> svint64x3_t
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t) -> svuint8x3_t {
@@ -7460,7 +7460,7 @@ pub fn svcreate3_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t) -> svuint8x3_t
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_u16(x0: svuint16_t, x1: svuint16_t, x2: svuint16_t) -> svuint16x3_t {
@@ -7468,7 +7468,7 @@ pub fn svcreate3_u16(x0: svuint16_t, x1: svuint16_t, x2: svuint16_t) -> svuint16
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_u32(x0: svuint32_t, x1: svuint32_t, x2: svuint32_t) -> svuint32x3_t {
@@ -7476,7 +7476,7 @@ pub fn svcreate3_u32(x0: svuint32_t, x1: svuint32_t, x2: svuint32_t) -> svuint32
 }
 #[doc = "Create a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate3_u64(x0: svuint64_t, x1: svuint64_t, x2: svuint64_t) -> svuint64x3_t {
@@ -7484,7 +7484,7 @@ pub fn svcreate3_u64(x0: svuint64_t, x1: svuint64_t, x2: svuint64_t) -> svuint64
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_f32(
@@ -7497,7 +7497,7 @@ pub fn svcreate4_f32(
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_f64(
@@ -7510,7 +7510,7 @@ pub fn svcreate4_f64(
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t, x3: svint8_t) -> svint8x4_t {
@@ -7518,7 +7518,7 @@ pub fn svcreate4_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t, x3: svint8_t) -> s
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t, x3: svint16_t) -> svint16x4_t {
@@ -7526,7 +7526,7 @@ pub fn svcreate4_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t, x3: svint16_t)
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t, x3: svint32_t) -> svint32x4_t {
@@ -7534,7 +7534,7 @@ pub fn svcreate4_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t, x3: svint32_t)
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t, x3: svint64_t) -> svint64x4_t {
@@ -7542,7 +7542,7 @@ pub fn svcreate4_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t, x3: svint64_t)
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t, x3: svuint8_t) -> svuint8x4_t {
@@ -7550,7 +7550,7 @@ pub fn svcreate4_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t, x3: svuint8_t)
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_u16(
@@ -7563,7 +7563,7 @@ pub fn svcreate4_u16(
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_u32(
@@ -7576,7 +7576,7 @@ pub fn svcreate4_u32(
 }
 #[doc = "Create a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svcreate4_u64(
@@ -7589,7 +7589,7 @@ pub fn svcreate4_u64(
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvt))]
@@ -7602,7 +7602,7 @@ pub fn svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) ->
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvt))]
@@ -7611,7 +7611,7 @@ pub fn svcvt_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvt))]
@@ -7620,7 +7620,7 @@ pub fn svcvt_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvt))]
@@ -7633,7 +7633,7 @@ pub fn svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) ->
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvt))]
@@ -7642,7 +7642,7 @@ pub fn svcvt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvt))]
@@ -7651,7 +7651,7 @@ pub fn svcvt_f64_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7664,7 +7664,7 @@ pub fn svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool_t, op: svint32_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7673,7 +7673,7 @@ pub fn svcvt_f32_s32_x(pg: svbool_t, op: svint32_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7682,7 +7682,7 @@ pub fn svcvt_f32_s32_z(pg: svbool_t, op: svint32_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7695,7 +7695,7 @@ pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7704,7 +7704,7 @@ pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7713,7 +7713,7 @@ pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7726,7 +7726,7 @@ pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7735,7 +7735,7 @@ pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7744,7 +7744,7 @@ pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7757,7 +7757,7 @@ pub fn svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool_t, op: svuint64_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7766,7 +7766,7 @@ pub fn svcvt_f32_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7775,7 +7775,7 @@ pub fn svcvt_f32_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7788,7 +7788,7 @@ pub fn svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool_t, op: svint32_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7797,7 +7797,7 @@ pub fn svcvt_f64_s32_x(pg: svbool_t, op: svint32_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7806,7 +7806,7 @@ pub fn svcvt_f64_s32_z(pg: svbool_t, op: svint32_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7819,7 +7819,7 @@ pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7828,7 +7828,7 @@ pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(scvtf))]
@@ -7837,7 +7837,7 @@ pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7850,7 +7850,7 @@ pub fn svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool_t, op: svuint32_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7859,7 +7859,7 @@ pub fn svcvt_f64_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7868,7 +7868,7 @@ pub fn svcvt_f64_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7881,7 +7881,7 @@ pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7890,7 +7890,7 @@ pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ucvtf))]
@@ -7899,7 +7899,7 @@ pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7912,7 +7912,7 @@ pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7921,7 +7921,7 @@ pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7930,7 +7930,7 @@ pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7943,7 +7943,7 @@ pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7952,7 +7952,7 @@ pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7961,7 +7961,7 @@ pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7974,7 +7974,7 @@ pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7983,7 +7983,7 @@ pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -7992,7 +7992,7 @@ pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -8005,7 +8005,7 @@ pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -8014,7 +8014,7 @@ pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
@@ -8023,7 +8023,7 @@ pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8036,7 +8036,7 @@ pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8045,7 +8045,7 @@ pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8054,7 +8054,7 @@ pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8067,7 +8067,7 @@ pub fn svcvt_u32_f64_m(inactive: svuint32_t, pg: svbool_t, op: svfloat64_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8076,7 +8076,7 @@ pub fn svcvt_u32_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8085,7 +8085,7 @@ pub fn svcvt_u32_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint32_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8098,7 +8098,7 @@ pub fn svcvt_u64_f32_m(inactive: svuint64_t, pg: svbool_t, op: svfloat32_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8107,7 +8107,7 @@ pub fn svcvt_u64_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8116,7 +8116,7 @@ pub fn svcvt_u64_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8129,7 +8129,7 @@ pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> s
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8138,7 +8138,7 @@ pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
@@ -8147,7 +8147,7 @@ pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8160,7 +8160,7 @@ pub fn svdiv_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8169,7 +8169,7 @@ pub fn svdiv_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8178,7 +8178,7 @@ pub fn svdiv_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8187,7 +8187,7 @@ pub fn svdiv_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8196,7 +8196,7 @@ pub fn svdiv_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8205,7 +8205,7 @@ pub fn svdiv_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8218,7 +8218,7 @@ pub fn svdiv_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8227,7 +8227,7 @@ pub fn svdiv_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8236,7 +8236,7 @@ pub fn svdiv_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8245,7 +8245,7 @@ pub fn svdiv_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8254,7 +8254,7 @@ pub fn svdiv_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -8263,7 +8263,7 @@ pub fn svdiv_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8276,7 +8276,7 @@ pub fn svdiv_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8285,7 +8285,7 @@ pub fn svdiv_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8294,7 +8294,7 @@ pub fn svdiv_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8303,7 +8303,7 @@ pub fn svdiv_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8312,7 +8312,7 @@ pub fn svdiv_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8321,7 +8321,7 @@ pub fn svdiv_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8334,7 +8334,7 @@ pub fn svdiv_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8343,7 +8343,7 @@ pub fn svdiv_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8352,7 +8352,7 @@ pub fn svdiv_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8361,7 +8361,7 @@ pub fn svdiv_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8370,7 +8370,7 @@ pub fn svdiv_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdiv))]
@@ -8379,7 +8379,7 @@ pub fn svdiv_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8392,7 +8392,7 @@ pub fn svdiv_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8401,7 +8401,7 @@ pub fn svdiv_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8410,7 +8410,7 @@ pub fn svdiv_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8419,7 +8419,7 @@ pub fn svdiv_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8428,7 +8428,7 @@ pub fn svdiv_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8437,7 +8437,7 @@ pub fn svdiv_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8450,7 +8450,7 @@ pub fn svdiv_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8459,7 +8459,7 @@ pub fn svdiv_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8468,7 +8468,7 @@ pub fn svdiv_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8477,7 +8477,7 @@ pub fn svdiv_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8486,7 +8486,7 @@ pub fn svdiv_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udiv))]
@@ -8495,7 +8495,7 @@ pub fn svdiv_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8508,7 +8508,7 @@ pub fn svdivr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8517,7 +8517,7 @@ pub fn svdivr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8526,7 +8526,7 @@ pub fn svdivr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8535,7 +8535,7 @@ pub fn svdivr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8544,7 +8544,7 @@ pub fn svdivr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8553,7 +8553,7 @@ pub fn svdivr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8566,7 +8566,7 @@ pub fn svdivr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8575,7 +8575,7 @@ pub fn svdivr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8584,7 +8584,7 @@ pub fn svdivr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8593,7 +8593,7 @@ pub fn svdivr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8602,7 +8602,7 @@ pub fn svdivr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fdivr))]
@@ -8611,7 +8611,7 @@ pub fn svdivr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8624,7 +8624,7 @@ pub fn svdivr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8633,7 +8633,7 @@ pub fn svdivr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8642,7 +8642,7 @@ pub fn svdivr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8651,7 +8651,7 @@ pub fn svdivr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8660,7 +8660,7 @@ pub fn svdivr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8669,7 +8669,7 @@ pub fn svdivr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8682,7 +8682,7 @@ pub fn svdivr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8691,7 +8691,7 @@ pub fn svdivr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8700,7 +8700,7 @@ pub fn svdivr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8709,7 +8709,7 @@ pub fn svdivr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8718,7 +8718,7 @@ pub fn svdivr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdivr))]
@@ -8727,7 +8727,7 @@ pub fn svdivr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8740,7 +8740,7 @@ pub fn svdivr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8749,7 +8749,7 @@ pub fn svdivr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8758,7 +8758,7 @@ pub fn svdivr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8767,7 +8767,7 @@ pub fn svdivr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8776,7 +8776,7 @@ pub fn svdivr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8785,7 +8785,7 @@ pub fn svdivr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8798,7 +8798,7 @@ pub fn svdivr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8807,7 +8807,7 @@ pub fn svdivr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8816,7 +8816,7 @@ pub fn svdivr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8825,7 +8825,7 @@ pub fn svdivr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8834,7 +8834,7 @@ pub fn svdivr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Divide reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udivr))]
@@ -8843,7 +8843,7 @@ pub fn svdivr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))]
@@ -8869,7 +8869,7 @@ pub fn svdot_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))]
@@ -8895,7 +8895,7 @@ pub fn svdot_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))]
@@ -8923,7 +8923,7 @@ pub fn svdot_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))]
@@ -8951,7 +8951,7 @@ pub fn svdot_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdot))]
@@ -8964,7 +8964,7 @@ pub fn svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t {
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdot))]
@@ -8973,7 +8973,7 @@ pub fn svdot_n_s32(op1: svint32_t, op2: svint8_t, op3: i8) -> svint32_t {
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdot))]
@@ -8986,7 +8986,7 @@ pub fn svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t {
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sdot))]
@@ -8995,7 +8995,7 @@ pub fn svdot_n_s64(op1: svint64_t, op2: svint16_t, op3: i16) -> svint64_t {
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udot))]
@@ -9008,7 +9008,7 @@ pub fn svdot_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udot))]
@@ -9017,7 +9017,7 @@ pub fn svdot_n_u32(op1: svuint32_t, op2: svuint8_t, op3: u8) -> svuint32_t {
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udot))]
@@ -9030,7 +9030,7 @@ pub fn svdot_u64(op1: svuint64_t, op2: svuint16_t, op3: svuint16_t) -> svuint64_
 }
 #[doc = "Dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(udot))]
@@ -9039,7 +9039,7 @@ pub fn svdot_n_u64(op1: svuint64_t, op2: svuint16_t, op3: u16) -> svuint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9048,7 +9048,7 @@ pub fn svdup_lane_f32(data: svfloat32_t, index: u32) -> svfloat32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9057,7 +9057,7 @@ pub fn svdup_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9066,7 +9066,7 @@ pub fn svdup_lane_s8(data: svint8_t, index: u8) -> svint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9075,7 +9075,7 @@ pub fn svdup_lane_s16(data: svint16_t, index: u16) -> svint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9084,7 +9084,7 @@ pub fn svdup_lane_s32(data: svint32_t, index: u32) -> svint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9093,7 +9093,7 @@ pub fn svdup_lane_s64(data: svint64_t, index: u64) -> svint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9102,7 +9102,7 @@ pub fn svdup_lane_u8(data: svuint8_t, index: u8) -> svuint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9111,7 +9111,7 @@ pub fn svdup_lane_u16(data: svuint16_t, index: u16) -> svuint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9120,7 +9120,7 @@ pub fn svdup_lane_u32(data: svuint32_t, index: u32) -> svuint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9129,7 +9129,7 @@ pub fn svdup_lane_u64(data: svuint64_t, index: u64) -> svuint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbfx))]
@@ -9143,7 +9143,7 @@ pub fn svdup_n_b8(op: bool) -> svbool_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbfx))]
@@ -9157,7 +9157,7 @@ pub fn svdup_n_b16(op: bool) -> svbool_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbfx))]
@@ -9171,7 +9171,7 @@ pub fn svdup_n_b32(op: bool) -> svbool_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbfx))]
@@ -9185,7 +9185,7 @@ pub fn svdup_n_b64(op: bool) -> svbool_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9198,7 +9198,7 @@ pub fn svdup_n_f32(op: f32) -> svfloat32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9211,7 +9211,7 @@ pub fn svdup_n_f64(op: f64) -> svfloat64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9224,7 +9224,7 @@ pub fn svdup_n_s8(op: i8) -> svint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9237,7 +9237,7 @@ pub fn svdup_n_s16(op: i16) -> svint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9250,7 +9250,7 @@ pub fn svdup_n_s32(op: i32) -> svint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9263,7 +9263,7 @@ pub fn svdup_n_s64(op: i64) -> svint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9272,7 +9272,7 @@ pub fn svdup_n_u8(op: u8) -> svuint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9281,7 +9281,7 @@ pub fn svdup_n_u16(op: u16) -> svuint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9290,7 +9290,7 @@ pub fn svdup_n_u32(op: u32) -> svuint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9299,7 +9299,7 @@ pub fn svdup_n_u64(op: u64) -> svuint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9312,7 +9312,7 @@ pub fn svdup_n_f32_m(inactive: svfloat32_t, pg: svbool_t, op: f32) -> svfloat32_
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9321,7 +9321,7 @@ pub fn svdup_n_f32_x(pg: svbool_t, op: f32) -> svfloat32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9330,7 +9330,7 @@ pub fn svdup_n_f32_z(pg: svbool_t, op: f32) -> svfloat32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9343,7 +9343,7 @@ pub fn svdup_n_f64_m(inactive: svfloat64_t, pg: svbool_t, op: f64) -> svfloat64_
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9352,7 +9352,7 @@ pub fn svdup_n_f64_x(pg: svbool_t, op: f64) -> svfloat64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9361,7 +9361,7 @@ pub fn svdup_n_f64_z(pg: svbool_t, op: f64) -> svfloat64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9374,7 +9374,7 @@ pub fn svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9383,7 +9383,7 @@ pub fn svdup_n_s8_x(pg: svbool_t, op: i8) -> svint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9392,7 +9392,7 @@ pub fn svdup_n_s8_z(pg: svbool_t, op: i8) -> svint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9405,7 +9405,7 @@ pub fn svdup_n_s16_m(inactive: svint16_t, pg: svbool_t, op: i16) -> svint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9414,7 +9414,7 @@ pub fn svdup_n_s16_x(pg: svbool_t, op: i16) -> svint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9423,7 +9423,7 @@ pub fn svdup_n_s16_z(pg: svbool_t, op: i16) -> svint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9436,7 +9436,7 @@ pub fn svdup_n_s32_m(inactive: svint32_t, pg: svbool_t, op: i32) -> svint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9445,7 +9445,7 @@ pub fn svdup_n_s32_x(pg: svbool_t, op: i32) -> svint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9454,7 +9454,7 @@ pub fn svdup_n_s32_z(pg: svbool_t, op: i32) -> svint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9467,7 +9467,7 @@ pub fn svdup_n_s64_m(inactive: svint64_t, pg: svbool_t, op: i64) -> svint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9476,7 +9476,7 @@ pub fn svdup_n_s64_x(pg: svbool_t, op: i64) -> svint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9485,7 +9485,7 @@ pub fn svdup_n_s64_z(pg: svbool_t, op: i64) -> svint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9494,7 +9494,7 @@ pub fn svdup_n_u8_m(inactive: svuint8_t, pg: svbool_t, op: u8) -> svuint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9503,7 +9503,7 @@ pub fn svdup_n_u8_x(pg: svbool_t, op: u8) -> svuint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9512,7 +9512,7 @@ pub fn svdup_n_u8_z(pg: svbool_t, op: u8) -> svuint8_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9521,7 +9521,7 @@ pub fn svdup_n_u16_m(inactive: svuint16_t, pg: svbool_t, op: u16) -> svuint16_t
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9530,7 +9530,7 @@ pub fn svdup_n_u16_x(pg: svbool_t, op: u16) -> svuint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9539,7 +9539,7 @@ pub fn svdup_n_u16_z(pg: svbool_t, op: u16) -> svuint16_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9548,7 +9548,7 @@ pub fn svdup_n_u32_m(inactive: svuint32_t, pg: svbool_t, op: u32) -> svuint32_t
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9557,7 +9557,7 @@ pub fn svdup_n_u32_x(pg: svbool_t, op: u32) -> svuint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9566,7 +9566,7 @@ pub fn svdup_n_u32_z(pg: svbool_t, op: u32) -> svuint32_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9575,7 +9575,7 @@ pub fn svdup_n_u64_m(inactive: svuint64_t, pg: svbool_t, op: u64) -> svuint64_t
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9584,7 +9584,7 @@ pub fn svdup_n_u64_x(pg: svbool_t, op: u64) -> svuint64_t {
 }
 #[doc = "Broadcast a scalar value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -9593,7 +9593,7 @@ pub fn svdup_n_u64_z(pg: svbool_t, op: u64) -> svuint64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9609,7 +9609,7 @@ pub fn svdupq_lane_f32(data: svfloat32_t, index: u64) -> svfloat32_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9625,7 +9625,7 @@ pub fn svdupq_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9641,7 +9641,7 @@ pub fn svdupq_lane_s8(data: svint8_t, index: u64) -> svint8_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9657,7 +9657,7 @@ pub fn svdupq_lane_s16(data: svint16_t, index: u64) -> svint16_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9673,7 +9673,7 @@ pub fn svdupq_lane_s32(data: svint32_t, index: u64) -> svint32_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9689,7 +9689,7 @@ pub fn svdupq_lane_s64(data: svint64_t, index: u64) -> svint64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9698,7 +9698,7 @@ pub fn svdupq_lane_u8(data: svuint8_t, index: u64) -> svuint8_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9707,7 +9707,7 @@ pub fn svdupq_lane_u16(data: svuint16_t, index: u64) -> svuint16_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9716,7 +9716,7 @@ pub fn svdupq_lane_u32(data: svuint32_t, index: u64) -> svuint32_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -9725,7 +9725,7 @@ pub fn svdupq_lane_u64(data: svuint64_t, index: u64) -> svuint64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_b16(
@@ -9745,7 +9745,7 @@ pub fn svdupq_n_b16(
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_b32(x0: bool, x1: bool, x2: bool, x3: bool) -> svbool_t {
@@ -9754,7 +9754,7 @@ pub fn svdupq_n_b32(x0: bool, x1: bool, x2: bool, x3: bool) -> svbool_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_b64(x0: bool, x1: bool) -> svbool_t {
@@ -9763,7 +9763,7 @@ pub fn svdupq_n_b64(x0: bool, x1: bool) -> svbool_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_b8(
@@ -9792,7 +9792,7 @@ pub fn svdupq_n_b8(
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t {
@@ -9810,7 +9810,7 @@ pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t {
@@ -9828,7 +9828,7 @@ pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t {
@@ -9844,7 +9844,7 @@ pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t {
@@ -9862,7 +9862,7 @@ pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t {
@@ -9880,7 +9880,7 @@ pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t {
@@ -9888,7 +9888,7 @@ pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t {
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_s16(
@@ -9919,7 +9919,7 @@ pub fn svdupq_n_s16(
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_u16(
@@ -9948,7 +9948,7 @@ pub fn svdupq_n_u16(
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_s8(
@@ -9989,7 +9989,7 @@ pub fn svdupq_n_s8(
 }
 #[doc = "Broadcast a quadword of scalars"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svdupq_n_u8(
@@ -10034,7 +10034,7 @@ pub fn svdupq_n_u8(
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10047,7 +10047,7 @@ pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10060,7 +10060,7 @@ pub fn sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10069,7 +10069,7 @@ pub fn sveor_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10078,7 +10078,7 @@ pub fn sveor_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10087,7 +10087,7 @@ pub fn sveor_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10096,7 +10096,7 @@ pub fn sveor_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10105,7 +10105,7 @@ pub fn sveor_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10118,7 +10118,7 @@ pub fn sveor_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10127,7 +10127,7 @@ pub fn sveor_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10136,7 +10136,7 @@ pub fn sveor_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10145,7 +10145,7 @@ pub fn sveor_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10154,7 +10154,7 @@ pub fn sveor_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10163,7 +10163,7 @@ pub fn sveor_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10176,7 +10176,7 @@ pub fn sveor_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10185,7 +10185,7 @@ pub fn sveor_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10194,7 +10194,7 @@ pub fn sveor_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10203,7 +10203,7 @@ pub fn sveor_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10212,7 +10212,7 @@ pub fn sveor_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10221,7 +10221,7 @@ pub fn sveor_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10234,7 +10234,7 @@ pub fn sveor_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10243,7 +10243,7 @@ pub fn sveor_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10252,7 +10252,7 @@ pub fn sveor_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10261,7 +10261,7 @@ pub fn sveor_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10270,7 +10270,7 @@ pub fn sveor_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10279,7 +10279,7 @@ pub fn sveor_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10288,7 +10288,7 @@ pub fn sveor_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10297,7 +10297,7 @@ pub fn sveor_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10306,7 +10306,7 @@ pub fn sveor_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10315,7 +10315,7 @@ pub fn sveor_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10324,7 +10324,7 @@ pub fn sveor_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10333,7 +10333,7 @@ pub fn sveor_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10342,7 +10342,7 @@ pub fn sveor_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10351,7 +10351,7 @@ pub fn sveor_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10360,7 +10360,7 @@ pub fn sveor_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10369,7 +10369,7 @@ pub fn sveor_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10378,7 +10378,7 @@ pub fn sveor_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10387,7 +10387,7 @@ pub fn sveor_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10396,7 +10396,7 @@ pub fn sveor_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10405,7 +10405,7 @@ pub fn sveor_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10414,7 +10414,7 @@ pub fn sveor_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10423,7 +10423,7 @@ pub fn sveor_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10432,7 +10432,7 @@ pub fn sveor_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10441,7 +10441,7 @@ pub fn sveor_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10450,7 +10450,7 @@ pub fn sveor_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10459,7 +10459,7 @@ pub fn sveor_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10468,7 +10468,7 @@ pub fn sveor_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10477,7 +10477,7 @@ pub fn sveor_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10486,7 +10486,7 @@ pub fn sveor_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor))]
@@ -10495,7 +10495,7 @@ pub fn sveor_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10508,7 +10508,7 @@ pub fn sveorv_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10521,7 +10521,7 @@ pub fn sveorv_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10534,7 +10534,7 @@ pub fn sveorv_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10547,7 +10547,7 @@ pub fn sveorv_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10556,7 +10556,7 @@ pub fn sveorv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10565,7 +10565,7 @@ pub fn sveorv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10574,7 +10574,7 @@ pub fn sveorv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Bitwise exclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorv))]
@@ -10583,7 +10583,7 @@ pub fn sveorv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Floating-point exponential accelerator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fexpa))]
@@ -10599,7 +10599,7 @@ pub fn svexpa_f32(op: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Floating-point exponential accelerator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fexpa))]
@@ -10615,7 +10615,7 @@ pub fn svexpa_f64(op: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10629,7 +10629,7 @@ pub fn svext_f32<const IMM3: i32>(op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10643,7 +10643,7 @@ pub fn svext_f64<const IMM3: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10657,7 +10657,7 @@ pub fn svext_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10671,7 +10671,7 @@ pub fn svext_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10685,7 +10685,7 @@ pub fn svext_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10699,7 +10699,7 @@ pub fn svext_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10709,7 +10709,7 @@ pub fn svext_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10719,7 +10719,7 @@ pub fn svext_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10729,7 +10729,7 @@ pub fn svext_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ext, IMM3 = 1))]
@@ -10739,7 +10739,7 @@ pub fn svext_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10752,7 +10752,7 @@ pub fn svextb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10761,7 +10761,7 @@ pub fn svextb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10770,7 +10770,7 @@ pub fn svextb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10783,7 +10783,7 @@ pub fn svextb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10792,7 +10792,7 @@ pub fn svextb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10801,7 +10801,7 @@ pub fn svextb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Sign-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxth))]
@@ -10814,7 +10814,7 @@ pub fn svexth_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Sign-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxth))]
@@ -10823,7 +10823,7 @@ pub fn svexth_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Sign-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxth))]
@@ -10832,7 +10832,7 @@ pub fn svexth_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10845,7 +10845,7 @@ pub fn svextb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10854,7 +10854,7 @@ pub fn svextb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Sign-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtb))]
@@ -10863,7 +10863,7 @@ pub fn svextb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Sign-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxth))]
@@ -10876,7 +10876,7 @@ pub fn svexth_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Sign-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxth))]
@@ -10885,7 +10885,7 @@ pub fn svexth_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Sign-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxth))]
@@ -10894,7 +10894,7 @@ pub fn svexth_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Sign-extend the low 32 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtw))]
@@ -10907,7 +10907,7 @@ pub fn svextw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Sign-extend the low 32 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtw))]
@@ -10916,7 +10916,7 @@ pub fn svextw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Sign-extend the low 32 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sxtw))]
@@ -10925,7 +10925,7 @@ pub fn svextw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -10938,7 +10938,7 @@ pub fn svextb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuin
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -10947,7 +10947,7 @@ pub fn svextb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -10956,7 +10956,7 @@ pub fn svextb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -10969,7 +10969,7 @@ pub fn svextb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuin
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -10978,7 +10978,7 @@ pub fn svextb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -10987,7 +10987,7 @@ pub fn svextb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Zero-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxth))]
@@ -11000,7 +11000,7 @@ pub fn svexth_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuin
 }
 #[doc = "Zero-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxth))]
@@ -11009,7 +11009,7 @@ pub fn svexth_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Zero-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxth))]
@@ -11018,7 +11018,7 @@ pub fn svexth_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -11031,7 +11031,7 @@ pub fn svextb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -11040,7 +11040,7 @@ pub fn svextb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Zero-extend the low 8 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtb))]
@@ -11049,7 +11049,7 @@ pub fn svextb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Zero-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxth))]
@@ -11062,7 +11062,7 @@ pub fn svexth_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Zero-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxth))]
@@ -11071,7 +11071,7 @@ pub fn svexth_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Zero-extend the low 16 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxth))]
@@ -11080,7 +11080,7 @@ pub fn svexth_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Zero-extend the low 32 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtw))]
@@ -11093,7 +11093,7 @@ pub fn svextw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Zero-extend the low 32 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtw))]
@@ -11102,7 +11102,7 @@ pub fn svextw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Zero-extend the low 32 bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uxtw))]
@@ -11111,7 +11111,7 @@ pub fn svextw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_f32<const IMM_INDEX: i32>(tuple: svfloat32x2_t) -> svfloat32_t {
@@ -11120,7 +11120,7 @@ pub fn svget2_f32<const IMM_INDEX: i32>(tuple: svfloat32x2_t) -> svfloat32_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_f64<const IMM_INDEX: i32>(tuple: svfloat64x2_t) -> svfloat64_t {
@@ -11129,7 +11129,7 @@ pub fn svget2_f64<const IMM_INDEX: i32>(tuple: svfloat64x2_t) -> svfloat64_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_s8<const IMM_INDEX: i32>(tuple: svint8x2_t) -> svint8_t {
@@ -11138,7 +11138,7 @@ pub fn svget2_s8<const IMM_INDEX: i32>(tuple: svint8x2_t) -> svint8_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_s16<const IMM_INDEX: i32>(tuple: svint16x2_t) -> svint16_t {
@@ -11147,7 +11147,7 @@ pub fn svget2_s16<const IMM_INDEX: i32>(tuple: svint16x2_t) -> svint16_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_s32<const IMM_INDEX: i32>(tuple: svint32x2_t) -> svint32_t {
@@ -11156,7 +11156,7 @@ pub fn svget2_s32<const IMM_INDEX: i32>(tuple: svint32x2_t) -> svint32_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_s64<const IMM_INDEX: i32>(tuple: svint64x2_t) -> svint64_t {
@@ -11165,7 +11165,7 @@ pub fn svget2_s64<const IMM_INDEX: i32>(tuple: svint64x2_t) -> svint64_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_u8<const IMM_INDEX: i32>(tuple: svuint8x2_t) -> svuint8_t {
@@ -11174,7 +11174,7 @@ pub fn svget2_u8<const IMM_INDEX: i32>(tuple: svuint8x2_t) -> svuint8_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_u16<const IMM_INDEX: i32>(tuple: svuint16x2_t) -> svuint16_t {
@@ -11183,7 +11183,7 @@ pub fn svget2_u16<const IMM_INDEX: i32>(tuple: svuint16x2_t) -> svuint16_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_u32<const IMM_INDEX: i32>(tuple: svuint32x2_t) -> svuint32_t {
@@ -11192,7 +11192,7 @@ pub fn svget2_u32<const IMM_INDEX: i32>(tuple: svuint32x2_t) -> svuint32_t {
 }
 #[doc = "Extract one vector from a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget2_u64<const IMM_INDEX: i32>(tuple: svuint64x2_t) -> svuint64_t {
@@ -11201,7 +11201,7 @@ pub fn svget2_u64<const IMM_INDEX: i32>(tuple: svuint64x2_t) -> svuint64_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_f32<const IMM_INDEX: i32>(tuple: svfloat32x3_t) -> svfloat32_t {
@@ -11210,7 +11210,7 @@ pub fn svget3_f32<const IMM_INDEX: i32>(tuple: svfloat32x3_t) -> svfloat32_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_f64<const IMM_INDEX: i32>(tuple: svfloat64x3_t) -> svfloat64_t {
@@ -11219,7 +11219,7 @@ pub fn svget3_f64<const IMM_INDEX: i32>(tuple: svfloat64x3_t) -> svfloat64_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_s8<const IMM_INDEX: i32>(tuple: svint8x3_t) -> svint8_t {
@@ -11228,7 +11228,7 @@ pub fn svget3_s8<const IMM_INDEX: i32>(tuple: svint8x3_t) -> svint8_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_s16<const IMM_INDEX: i32>(tuple: svint16x3_t) -> svint16_t {
@@ -11237,7 +11237,7 @@ pub fn svget3_s16<const IMM_INDEX: i32>(tuple: svint16x3_t) -> svint16_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_s32<const IMM_INDEX: i32>(tuple: svint32x3_t) -> svint32_t {
@@ -11246,7 +11246,7 @@ pub fn svget3_s32<const IMM_INDEX: i32>(tuple: svint32x3_t) -> svint32_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_s64<const IMM_INDEX: i32>(tuple: svint64x3_t) -> svint64_t {
@@ -11255,7 +11255,7 @@ pub fn svget3_s64<const IMM_INDEX: i32>(tuple: svint64x3_t) -> svint64_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_u8<const IMM_INDEX: i32>(tuple: svuint8x3_t) -> svuint8_t {
@@ -11264,7 +11264,7 @@ pub fn svget3_u8<const IMM_INDEX: i32>(tuple: svuint8x3_t) -> svuint8_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_u16<const IMM_INDEX: i32>(tuple: svuint16x3_t) -> svuint16_t {
@@ -11273,7 +11273,7 @@ pub fn svget3_u16<const IMM_INDEX: i32>(tuple: svuint16x3_t) -> svuint16_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_u32<const IMM_INDEX: i32>(tuple: svuint32x3_t) -> svuint32_t {
@@ -11282,7 +11282,7 @@ pub fn svget3_u32<const IMM_INDEX: i32>(tuple: svuint32x3_t) -> svuint32_t {
 }
 #[doc = "Extract one vector from a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget3_u64<const IMM_INDEX: i32>(tuple: svuint64x3_t) -> svuint64_t {
@@ -11291,7 +11291,7 @@ pub fn svget3_u64<const IMM_INDEX: i32>(tuple: svuint64x3_t) -> svuint64_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_f32<const IMM_INDEX: i32>(tuple: svfloat32x4_t) -> svfloat32_t {
@@ -11300,7 +11300,7 @@ pub fn svget4_f32<const IMM_INDEX: i32>(tuple: svfloat32x4_t) -> svfloat32_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_f64<const IMM_INDEX: i32>(tuple: svfloat64x4_t) -> svfloat64_t {
@@ -11309,7 +11309,7 @@ pub fn svget4_f64<const IMM_INDEX: i32>(tuple: svfloat64x4_t) -> svfloat64_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_s8<const IMM_INDEX: i32>(tuple: svint8x4_t) -> svint8_t {
@@ -11318,7 +11318,7 @@ pub fn svget4_s8<const IMM_INDEX: i32>(tuple: svint8x4_t) -> svint8_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_s16<const IMM_INDEX: i32>(tuple: svint16x4_t) -> svint16_t {
@@ -11327,7 +11327,7 @@ pub fn svget4_s16<const IMM_INDEX: i32>(tuple: svint16x4_t) -> svint16_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_s32<const IMM_INDEX: i32>(tuple: svint32x4_t) -> svint32_t {
@@ -11336,7 +11336,7 @@ pub fn svget4_s32<const IMM_INDEX: i32>(tuple: svint32x4_t) -> svint32_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_s64<const IMM_INDEX: i32>(tuple: svint64x4_t) -> svint64_t {
@@ -11345,7 +11345,7 @@ pub fn svget4_s64<const IMM_INDEX: i32>(tuple: svint64x4_t) -> svint64_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_u8<const IMM_INDEX: i32>(tuple: svuint8x4_t) -> svuint8_t {
@@ -11354,7 +11354,7 @@ pub fn svget4_u8<const IMM_INDEX: i32>(tuple: svuint8x4_t) -> svuint8_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_u16<const IMM_INDEX: i32>(tuple: svuint16x4_t) -> svuint16_t {
@@ -11363,7 +11363,7 @@ pub fn svget4_u16<const IMM_INDEX: i32>(tuple: svuint16x4_t) -> svuint16_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_u32<const IMM_INDEX: i32>(tuple: svuint32x4_t) -> svuint32_t {
@@ -11372,7 +11372,7 @@ pub fn svget4_u32<const IMM_INDEX: i32>(tuple: svuint32x4_t) -> svuint32_t {
 }
 #[doc = "Extract one vector from a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svget4_u64<const IMM_INDEX: i32>(tuple: svuint64x4_t) -> svuint64_t {
@@ -11381,7 +11381,7 @@ pub fn svget4_u64<const IMM_INDEX: i32>(tuple: svuint64x4_t) -> svuint64_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11394,7 +11394,7 @@ pub fn svindex_s8(base: i8, step: i8) -> svint8_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11407,7 +11407,7 @@ pub fn svindex_s16(base: i16, step: i16) -> svint16_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11420,7 +11420,7 @@ pub fn svindex_s32(base: i32, step: i32) -> svint32_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11433,7 +11433,7 @@ pub fn svindex_s64(base: i64, step: i64) -> svint64_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11442,7 +11442,7 @@ pub fn svindex_u8(base: u8, step: u8) -> svuint8_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11451,7 +11451,7 @@ pub fn svindex_u16(base: u16, step: u16) -> svuint16_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11460,7 +11460,7 @@ pub fn svindex_u32(base: u32, step: u32) -> svuint32_t {
 }
 #[doc = "Create linear series"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(index))]
@@ -11469,7 +11469,7 @@ pub fn svindex_u64(base: u64, step: u64) -> svuint64_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11482,7 +11482,7 @@ pub fn svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11495,7 +11495,7 @@ pub fn svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11508,7 +11508,7 @@ pub fn svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11521,7 +11521,7 @@ pub fn svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11534,7 +11534,7 @@ pub fn svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11547,7 +11547,7 @@ pub fn svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11556,7 +11556,7 @@ pub fn svinsr_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11565,7 +11565,7 @@ pub fn svinsr_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11574,7 +11574,7 @@ pub fn svinsr_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Insert scalar in shifted vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(insr))]
@@ -11583,7 +11583,7 @@ pub fn svinsr_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11596,7 +11596,7 @@ pub fn svlasta_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11609,7 +11609,7 @@ pub fn svlasta_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11622,7 +11622,7 @@ pub fn svlasta_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11635,7 +11635,7 @@ pub fn svlasta_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11648,7 +11648,7 @@ pub fn svlasta_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11661,7 +11661,7 @@ pub fn svlasta_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11670,7 +11670,7 @@ pub fn svlasta_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11679,7 +11679,7 @@ pub fn svlasta_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11688,7 +11688,7 @@ pub fn svlasta_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Extract element after last"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lasta))]
@@ -11697,7 +11697,7 @@ pub fn svlasta_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11710,7 +11710,7 @@ pub fn svlastb_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11723,7 +11723,7 @@ pub fn svlastb_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11736,7 +11736,7 @@ pub fn svlastb_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11749,7 +11749,7 @@ pub fn svlastb_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11762,7 +11762,7 @@ pub fn svlastb_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11775,7 +11775,7 @@ pub fn svlastb_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11784,7 +11784,7 @@ pub fn svlastb_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11793,7 +11793,7 @@ pub fn svlastb_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11802,7 +11802,7 @@ pub fn svlastb_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Extract last element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lastb))]
@@ -11814,7 +11814,7 @@ pub fn svlastb_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -11830,7 +11830,7 @@ pub unsafe fn svld1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -11846,7 +11846,7 @@ pub unsafe fn svld1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -11862,7 +11862,7 @@ pub unsafe fn svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -11878,7 +11878,7 @@ pub unsafe fn svld1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -11894,7 +11894,7 @@ pub unsafe fn svld1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -11910,7 +11910,7 @@ pub unsafe fn svld1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -11922,7 +11922,7 @@ pub unsafe fn svld1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -11934,7 +11934,7 @@ pub unsafe fn svld1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -11946,7 +11946,7 @@ pub unsafe fn svld1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -11958,7 +11958,7 @@ pub unsafe fn svld1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -11985,7 +11985,7 @@ pub unsafe fn svld1_gather_s32index_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12012,7 +12012,7 @@ pub unsafe fn svld1_gather_s32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12028,7 +12028,7 @@ pub unsafe fn svld1_gather_s32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12055,7 +12055,7 @@ pub unsafe fn svld1_gather_s64index_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12082,7 +12082,7 @@ pub unsafe fn svld1_gather_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12098,7 +12098,7 @@ pub unsafe fn svld1_gather_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12125,7 +12125,7 @@ pub unsafe fn svld1_gather_u32index_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12152,7 +12152,7 @@ pub unsafe fn svld1_gather_u32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12168,7 +12168,7 @@ pub unsafe fn svld1_gather_u32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12184,7 +12184,7 @@ pub unsafe fn svld1_gather_u64index_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12200,7 +12200,7 @@ pub unsafe fn svld1_gather_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12216,7 +12216,7 @@ pub unsafe fn svld1_gather_u64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12243,7 +12243,7 @@ pub unsafe fn svld1_gather_s32offset_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12270,7 +12270,7 @@ pub unsafe fn svld1_gather_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12286,7 +12286,7 @@ pub unsafe fn svld1_gather_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12313,7 +12313,7 @@ pub unsafe fn svld1_gather_s64offset_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12340,7 +12340,7 @@ pub unsafe fn svld1_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12356,7 +12356,7 @@ pub unsafe fn svld1_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12383,7 +12383,7 @@ pub unsafe fn svld1_gather_u32offset_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12410,7 +12410,7 @@ pub unsafe fn svld1_gather_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12426,7 +12426,7 @@ pub unsafe fn svld1_gather_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12442,7 +12442,7 @@ pub unsafe fn svld1_gather_u64offset_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12458,7 +12458,7 @@ pub unsafe fn svld1_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12475,7 +12475,7 @@ pub unsafe fn svld1_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12488,7 +12488,7 @@ pub unsafe fn svld1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svflo
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12501,7 +12501,7 @@ pub unsafe fn svld1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12514,7 +12514,7 @@ pub unsafe fn svld1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12527,7 +12527,7 @@ pub unsafe fn svld1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svflo
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12540,7 +12540,7 @@ pub unsafe fn svld1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12553,7 +12553,7 @@ pub unsafe fn svld1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12570,7 +12570,7 @@ pub unsafe fn svld1_gather_u32base_index_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12587,7 +12587,7 @@ pub unsafe fn svld1_gather_u32base_index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12604,7 +12604,7 @@ pub unsafe fn svld1_gather_u32base_index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12621,7 +12621,7 @@ pub unsafe fn svld1_gather_u64base_index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12638,7 +12638,7 @@ pub unsafe fn svld1_gather_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12655,7 +12655,7 @@ pub unsafe fn svld1_gather_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12683,7 +12683,7 @@ pub unsafe fn svld1_gather_u32base_offset_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12711,7 +12711,7 @@ pub unsafe fn svld1_gather_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12728,7 +12728,7 @@ pub unsafe fn svld1_gather_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12756,7 +12756,7 @@ pub unsafe fn svld1_gather_u64base_offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12784,7 +12784,7 @@ pub unsafe fn svld1_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12800,7 +12800,7 @@ pub unsafe fn svld1_gather_u64base_offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12812,7 +12812,7 @@ pub unsafe fn svld1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12824,7 +12824,7 @@ pub unsafe fn svld1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -12836,7 +12836,7 @@ pub unsafe fn svld1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -12848,7 +12848,7 @@ pub unsafe fn svld1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12860,7 +12860,7 @@ pub unsafe fn svld1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12872,7 +12872,7 @@ pub unsafe fn svld1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -12884,7 +12884,7 @@ pub unsafe fn svld1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -12896,7 +12896,7 @@ pub unsafe fn svld1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -12908,7 +12908,7 @@ pub unsafe fn svld1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1d))]
@@ -12920,7 +12920,7 @@ pub unsafe fn svld1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1row))]
@@ -12936,7 +12936,7 @@ pub unsafe fn svld1ro_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rod))]
@@ -12952,7 +12952,7 @@ pub unsafe fn svld1ro_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rob))]
@@ -12968,7 +12968,7 @@ pub unsafe fn svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1roh))]
@@ -12984,7 +12984,7 @@ pub unsafe fn svld1ro_s16(pg: svbool_t, base: *const i16) -> svint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1row))]
@@ -13000,7 +13000,7 @@ pub unsafe fn svld1ro_s32(pg: svbool_t, base: *const i32) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rod))]
@@ -13016,7 +13016,7 @@ pub unsafe fn svld1ro_s64(pg: svbool_t, base: *const i64) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rob))]
@@ -13028,7 +13028,7 @@ pub unsafe fn svld1ro_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1roh))]
@@ -13040,7 +13040,7 @@ pub unsafe fn svld1ro_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1row))]
@@ -13052,7 +13052,7 @@ pub unsafe fn svld1ro_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rod))]
@@ -13064,7 +13064,7 @@ pub unsafe fn svld1ro_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqw))]
@@ -13080,7 +13080,7 @@ pub unsafe fn svld1rq_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqd))]
@@ -13096,7 +13096,7 @@ pub unsafe fn svld1rq_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqb))]
@@ -13112,7 +13112,7 @@ pub unsafe fn svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqh))]
@@ -13128,7 +13128,7 @@ pub unsafe fn svld1rq_s16(pg: svbool_t, base: *const i16) -> svint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqw))]
@@ -13144,7 +13144,7 @@ pub unsafe fn svld1rq_s32(pg: svbool_t, base: *const i32) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqd))]
@@ -13160,7 +13160,7 @@ pub unsafe fn svld1rq_s64(pg: svbool_t, base: *const i64) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqb))]
@@ -13172,7 +13172,7 @@ pub unsafe fn svld1rq_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqh))]
@@ -13184,7 +13184,7 @@ pub unsafe fn svld1rq_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqw))]
@@ -13196,7 +13196,7 @@ pub unsafe fn svld1rq_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1rqd))]
@@ -13208,7 +13208,7 @@ pub unsafe fn svld1rq_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13235,7 +13235,7 @@ pub unsafe fn svld1sb_gather_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13262,7 +13262,7 @@ pub unsafe fn svld1sh_gather_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13278,7 +13278,7 @@ pub unsafe fn svld1sb_gather_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13294,7 +13294,7 @@ pub unsafe fn svld1sh_gather_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13321,7 +13321,7 @@ pub unsafe fn svld1sb_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13348,7 +13348,7 @@ pub unsafe fn svld1sh_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13375,7 +13375,7 @@ pub unsafe fn svld1sw_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13391,7 +13391,7 @@ pub unsafe fn svld1sb_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13407,7 +13407,7 @@ pub unsafe fn svld1sh_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13423,7 +13423,7 @@ pub unsafe fn svld1sw_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13454,7 +13454,7 @@ pub unsafe fn svld1sb_gather_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13485,7 +13485,7 @@ pub unsafe fn svld1sh_gather_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13501,7 +13501,7 @@ pub unsafe fn svld1sb_gather_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13517,7 +13517,7 @@ pub unsafe fn svld1sh_gather_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13533,7 +13533,7 @@ pub unsafe fn svld1sb_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13549,7 +13549,7 @@ pub unsafe fn svld1sh_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13565,7 +13565,7 @@ pub unsafe fn svld1sw_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13581,7 +13581,7 @@ pub unsafe fn svld1sb_gather_u64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13597,7 +13597,7 @@ pub unsafe fn svld1sh_gather_u64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13614,7 +13614,7 @@ pub unsafe fn svld1sw_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13646,7 +13646,7 @@ pub unsafe fn svld1sb_gather_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13678,7 +13678,7 @@ pub unsafe fn svld1sh_gather_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13695,7 +13695,7 @@ pub unsafe fn svld1sb_gather_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13712,7 +13712,7 @@ pub unsafe fn svld1sh_gather_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13744,7 +13744,7 @@ pub unsafe fn svld1sb_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13776,7 +13776,7 @@ pub unsafe fn svld1sh_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13808,7 +13808,7 @@ pub unsafe fn svld1sw_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13825,7 +13825,7 @@ pub unsafe fn svld1sb_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13842,7 +13842,7 @@ pub unsafe fn svld1sh_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13859,7 +13859,7 @@ pub unsafe fn svld1sw_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13872,7 +13872,7 @@ pub unsafe fn svld1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13885,7 +13885,7 @@ pub unsafe fn svld1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13898,7 +13898,7 @@ pub unsafe fn svld1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13911,7 +13911,7 @@ pub unsafe fn svld1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13924,7 +13924,7 @@ pub unsafe fn svld1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13937,7 +13937,7 @@ pub unsafe fn svld1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13950,7 +13950,7 @@ pub unsafe fn svld1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -13963,7 +13963,7 @@ pub unsafe fn svld1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -13976,7 +13976,7 @@ pub unsafe fn svld1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -13988,7 +13988,7 @@ pub unsafe fn svld1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14004,7 +14004,7 @@ pub unsafe fn svld1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14020,7 +14020,7 @@ pub unsafe fn svld1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14036,7 +14036,7 @@ pub unsafe fn svld1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14052,7 +14052,7 @@ pub unsafe fn svld1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14068,7 +14068,7 @@ pub unsafe fn svld1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14084,7 +14084,7 @@ pub unsafe fn svld1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14096,7 +14096,7 @@ pub unsafe fn svld1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14108,7 +14108,7 @@ pub unsafe fn svld1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14120,7 +14120,7 @@ pub unsafe fn svld1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14132,7 +14132,7 @@ pub unsafe fn svld1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14144,7 +14144,7 @@ pub unsafe fn svld1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14156,7 +14156,7 @@ pub unsafe fn svld1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14168,7 +14168,7 @@ pub unsafe fn svld1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14180,7 +14180,7 @@ pub unsafe fn svld1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14192,7 +14192,7 @@ pub unsafe fn svld1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14204,7 +14204,7 @@ pub unsafe fn svld1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14216,7 +14216,7 @@ pub unsafe fn svld1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14228,7 +14228,7 @@ pub unsafe fn svld1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14240,7 +14240,7 @@ pub unsafe fn svld1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14252,7 +14252,7 @@ pub unsafe fn svld1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14264,7 +14264,7 @@ pub unsafe fn svld1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sb))]
@@ -14276,7 +14276,7 @@ pub unsafe fn svld1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14288,7 +14288,7 @@ pub unsafe fn svld1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14300,7 +14300,7 @@ pub unsafe fn svld1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14327,7 +14327,7 @@ pub unsafe fn svld1sh_gather_s32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14343,7 +14343,7 @@ pub unsafe fn svld1sh_gather_s32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14370,7 +14370,7 @@ pub unsafe fn svld1sh_gather_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14397,7 +14397,7 @@ pub unsafe fn svld1sw_gather_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14413,7 +14413,7 @@ pub unsafe fn svld1sh_gather_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14429,7 +14429,7 @@ pub unsafe fn svld1sw_gather_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14460,7 +14460,7 @@ pub unsafe fn svld1sh_gather_u32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14476,7 +14476,7 @@ pub unsafe fn svld1sh_gather_u32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14492,7 +14492,7 @@ pub unsafe fn svld1sh_gather_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14508,7 +14508,7 @@ pub unsafe fn svld1sw_gather_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14524,7 +14524,7 @@ pub unsafe fn svld1sh_gather_u64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14541,7 +14541,7 @@ pub unsafe fn svld1sw_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14558,7 +14558,7 @@ pub unsafe fn svld1sh_gather_u32base_index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14575,7 +14575,7 @@ pub unsafe fn svld1sh_gather_u32base_index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14592,7 +14592,7 @@ pub unsafe fn svld1sh_gather_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14609,7 +14609,7 @@ pub unsafe fn svld1sw_gather_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sh))]
@@ -14626,7 +14626,7 @@ pub unsafe fn svld1sh_gather_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1sw))]
@@ -14642,7 +14642,7 @@ pub unsafe fn svld1sw_gather_u64base_index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14658,7 +14658,7 @@ pub unsafe fn svld1ub_gather_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14674,7 +14674,7 @@ pub unsafe fn svld1uh_gather_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14703,7 +14703,7 @@ pub unsafe fn svld1ub_gather_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14732,7 +14732,7 @@ pub unsafe fn svld1uh_gather_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14748,7 +14748,7 @@ pub unsafe fn svld1ub_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14764,7 +14764,7 @@ pub unsafe fn svld1uh_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -14780,7 +14780,7 @@ pub unsafe fn svld1uw_gather_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14809,7 +14809,7 @@ pub unsafe fn svld1ub_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14838,7 +14838,7 @@ pub unsafe fn svld1uh_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -14867,7 +14867,7 @@ pub unsafe fn svld1uw_gather_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14883,7 +14883,7 @@ pub unsafe fn svld1ub_gather_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14899,7 +14899,7 @@ pub unsafe fn svld1uh_gather_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14929,7 +14929,7 @@ pub unsafe fn svld1ub_gather_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14959,7 +14959,7 @@ pub unsafe fn svld1uh_gather_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -14975,7 +14975,7 @@ pub unsafe fn svld1ub_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -14991,7 +14991,7 @@ pub unsafe fn svld1uh_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15007,7 +15007,7 @@ pub unsafe fn svld1uw_gather_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15023,7 +15023,7 @@ pub unsafe fn svld1ub_gather_u64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15039,7 +15039,7 @@ pub unsafe fn svld1uh_gather_u64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15056,7 +15056,7 @@ pub unsafe fn svld1uw_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15073,7 +15073,7 @@ pub unsafe fn svld1ub_gather_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15090,7 +15090,7 @@ pub unsafe fn svld1uh_gather_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15120,7 +15120,7 @@ pub unsafe fn svld1ub_gather_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15150,7 +15150,7 @@ pub unsafe fn svld1uh_gather_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15167,7 +15167,7 @@ pub unsafe fn svld1ub_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15184,7 +15184,7 @@ pub unsafe fn svld1uh_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15201,7 +15201,7 @@ pub unsafe fn svld1uw_gather_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15231,7 +15231,7 @@ pub unsafe fn svld1ub_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15261,7 +15261,7 @@ pub unsafe fn svld1uh_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15291,7 +15291,7 @@ pub unsafe fn svld1uw_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15304,7 +15304,7 @@ pub unsafe fn svld1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15317,7 +15317,7 @@ pub unsafe fn svld1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15330,7 +15330,7 @@ pub unsafe fn svld1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15343,7 +15343,7 @@ pub unsafe fn svld1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15356,7 +15356,7 @@ pub unsafe fn svld1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15369,7 +15369,7 @@ pub unsafe fn svld1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15382,7 +15382,7 @@ pub unsafe fn svld1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15395,7 +15395,7 @@ pub unsafe fn svld1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15408,7 +15408,7 @@ pub unsafe fn svld1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15420,7 +15420,7 @@ pub unsafe fn svld1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15438,7 +15438,7 @@ pub unsafe fn svld1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15456,7 +15456,7 @@ pub unsafe fn svld1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15474,7 +15474,7 @@ pub unsafe fn svld1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15492,7 +15492,7 @@ pub unsafe fn svld1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15510,7 +15510,7 @@ pub unsafe fn svld1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15528,7 +15528,7 @@ pub unsafe fn svld1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15540,7 +15540,7 @@ pub unsafe fn svld1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15552,7 +15552,7 @@ pub unsafe fn svld1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15564,7 +15564,7 @@ pub unsafe fn svld1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15576,7 +15576,7 @@ pub unsafe fn svld1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15588,7 +15588,7 @@ pub unsafe fn svld1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15600,7 +15600,7 @@ pub unsafe fn svld1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15612,7 +15612,7 @@ pub unsafe fn svld1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15624,7 +15624,7 @@ pub unsafe fn svld1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15636,7 +15636,7 @@ pub unsafe fn svld1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15648,7 +15648,7 @@ pub unsafe fn svld1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15660,7 +15660,7 @@ pub unsafe fn svld1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15672,7 +15672,7 @@ pub unsafe fn svld1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15684,7 +15684,7 @@ pub unsafe fn svld1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15696,7 +15696,7 @@ pub unsafe fn svld1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15708,7 +15708,7 @@ pub unsafe fn svld1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1b))]
@@ -15720,7 +15720,7 @@ pub unsafe fn svld1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15732,7 +15732,7 @@ pub unsafe fn svld1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15744,7 +15744,7 @@ pub unsafe fn svld1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15760,7 +15760,7 @@ pub unsafe fn svld1uh_gather_s32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15789,7 +15789,7 @@ pub unsafe fn svld1uh_gather_s32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15805,7 +15805,7 @@ pub unsafe fn svld1uh_gather_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15821,7 +15821,7 @@ pub unsafe fn svld1uw_gather_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15850,7 +15850,7 @@ pub unsafe fn svld1uh_gather_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15879,7 +15879,7 @@ pub unsafe fn svld1uw_gather_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15895,7 +15895,7 @@ pub unsafe fn svld1uh_gather_u32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15925,7 +15925,7 @@ pub unsafe fn svld1uh_gather_u32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15941,7 +15941,7 @@ pub unsafe fn svld1uh_gather_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15957,7 +15957,7 @@ pub unsafe fn svld1uw_gather_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -15973,7 +15973,7 @@ pub unsafe fn svld1uh_gather_u64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -15990,7 +15990,7 @@ pub unsafe fn svld1uw_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -16007,7 +16007,7 @@ pub unsafe fn svld1uh_gather_u32base_index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -16024,7 +16024,7 @@ pub unsafe fn svld1uh_gather_u32base_index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -16041,7 +16041,7 @@ pub unsafe fn svld1uh_gather_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -16058,7 +16058,7 @@ pub unsafe fn svld1uw_gather_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1h))]
@@ -16075,7 +16075,7 @@ pub unsafe fn svld1uh_gather_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld1w))]
@@ -16091,7 +16091,7 @@ pub unsafe fn svld1uw_gather_u64base_index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2w))]
@@ -16110,7 +16110,7 @@ pub unsafe fn svld2_f32(pg: svbool_t, base: *const f32) -> svfloat32x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2d))]
@@ -16129,7 +16129,7 @@ pub unsafe fn svld2_f64(pg: svbool_t, base: *const f64) -> svfloat64x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2b))]
@@ -16148,7 +16148,7 @@ pub unsafe fn svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2h))]
@@ -16167,7 +16167,7 @@ pub unsafe fn svld2_s16(pg: svbool_t, base: *const i16) -> svint16x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2w))]
@@ -16186,7 +16186,7 @@ pub unsafe fn svld2_s32(pg: svbool_t, base: *const i32) -> svint32x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2d))]
@@ -16205,7 +16205,7 @@ pub unsafe fn svld2_s64(pg: svbool_t, base: *const i64) -> svint64x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2b))]
@@ -16217,7 +16217,7 @@ pub unsafe fn svld2_u8(pg: svbool_t, base: *const u8) -> svuint8x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2h))]
@@ -16229,7 +16229,7 @@ pub unsafe fn svld2_u16(pg: svbool_t, base: *const u16) -> svuint16x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2w))]
@@ -16241,7 +16241,7 @@ pub unsafe fn svld2_u32(pg: svbool_t, base: *const u32) -> svuint32x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2d))]
@@ -16253,7 +16253,7 @@ pub unsafe fn svld2_u64(pg: svbool_t, base: *const u64) -> svuint64x2_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2w))]
@@ -16265,7 +16265,7 @@ pub unsafe fn svld2_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2d))]
@@ -16277,7 +16277,7 @@ pub unsafe fn svld2_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2b))]
@@ -16289,7 +16289,7 @@ pub unsafe fn svld2_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2h))]
@@ -16301,7 +16301,7 @@ pub unsafe fn svld2_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2w))]
@@ -16313,7 +16313,7 @@ pub unsafe fn svld2_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2d))]
@@ -16325,7 +16325,7 @@ pub unsafe fn svld2_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2b))]
@@ -16337,7 +16337,7 @@ pub unsafe fn svld2_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2h))]
@@ -16349,7 +16349,7 @@ pub unsafe fn svld2_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2w))]
@@ -16361,7 +16361,7 @@ pub unsafe fn svld2_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld2d))]
@@ -16373,7 +16373,7 @@ pub unsafe fn svld2_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3w))]
@@ -16392,7 +16392,7 @@ pub unsafe fn svld3_f32(pg: svbool_t, base: *const f32) -> svfloat32x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3d))]
@@ -16411,7 +16411,7 @@ pub unsafe fn svld3_f64(pg: svbool_t, base: *const f64) -> svfloat64x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3b))]
@@ -16430,7 +16430,7 @@ pub unsafe fn svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3h))]
@@ -16449,7 +16449,7 @@ pub unsafe fn svld3_s16(pg: svbool_t, base: *const i16) -> svint16x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3w))]
@@ -16468,7 +16468,7 @@ pub unsafe fn svld3_s32(pg: svbool_t, base: *const i32) -> svint32x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3d))]
@@ -16487,7 +16487,7 @@ pub unsafe fn svld3_s64(pg: svbool_t, base: *const i64) -> svint64x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3b))]
@@ -16499,7 +16499,7 @@ pub unsafe fn svld3_u8(pg: svbool_t, base: *const u8) -> svuint8x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3h))]
@@ -16511,7 +16511,7 @@ pub unsafe fn svld3_u16(pg: svbool_t, base: *const u16) -> svuint16x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3w))]
@@ -16523,7 +16523,7 @@ pub unsafe fn svld3_u32(pg: svbool_t, base: *const u32) -> svuint32x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3d))]
@@ -16535,7 +16535,7 @@ pub unsafe fn svld3_u64(pg: svbool_t, base: *const u64) -> svuint64x3_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3w))]
@@ -16547,7 +16547,7 @@ pub unsafe fn svld3_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3d))]
@@ -16559,7 +16559,7 @@ pub unsafe fn svld3_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3b))]
@@ -16571,7 +16571,7 @@ pub unsafe fn svld3_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3h))]
@@ -16583,7 +16583,7 @@ pub unsafe fn svld3_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3w))]
@@ -16595,7 +16595,7 @@ pub unsafe fn svld3_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3d))]
@@ -16607,7 +16607,7 @@ pub unsafe fn svld3_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3b))]
@@ -16619,7 +16619,7 @@ pub unsafe fn svld3_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3h))]
@@ -16631,7 +16631,7 @@ pub unsafe fn svld3_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3w))]
@@ -16643,7 +16643,7 @@ pub unsafe fn svld3_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld3d))]
@@ -16655,7 +16655,7 @@ pub unsafe fn svld3_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4w))]
@@ -16674,7 +16674,7 @@ pub unsafe fn svld4_f32(pg: svbool_t, base: *const f32) -> svfloat32x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4d))]
@@ -16693,7 +16693,7 @@ pub unsafe fn svld4_f64(pg: svbool_t, base: *const f64) -> svfloat64x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4b))]
@@ -16712,7 +16712,7 @@ pub unsafe fn svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4h))]
@@ -16731,7 +16731,7 @@ pub unsafe fn svld4_s16(pg: svbool_t, base: *const i16) -> svint16x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4w))]
@@ -16750,7 +16750,7 @@ pub unsafe fn svld4_s32(pg: svbool_t, base: *const i32) -> svint32x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4d))]
@@ -16769,7 +16769,7 @@ pub unsafe fn svld4_s64(pg: svbool_t, base: *const i64) -> svint64x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4b))]
@@ -16781,7 +16781,7 @@ pub unsafe fn svld4_u8(pg: svbool_t, base: *const u8) -> svuint8x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4h))]
@@ -16793,7 +16793,7 @@ pub unsafe fn svld4_u16(pg: svbool_t, base: *const u16) -> svuint16x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4w))]
@@ -16805,7 +16805,7 @@ pub unsafe fn svld4_u32(pg: svbool_t, base: *const u32) -> svuint32x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4d))]
@@ -16817,7 +16817,7 @@ pub unsafe fn svld4_u64(pg: svbool_t, base: *const u64) -> svuint64x4_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4w))]
@@ -16829,7 +16829,7 @@ pub unsafe fn svld4_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4d))]
@@ -16841,7 +16841,7 @@ pub unsafe fn svld4_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svflo
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4b))]
@@ -16853,7 +16853,7 @@ pub unsafe fn svld4_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4h))]
@@ -16865,7 +16865,7 @@ pub unsafe fn svld4_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4w))]
@@ -16877,7 +16877,7 @@ pub unsafe fn svld4_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4d))]
@@ -16889,7 +16889,7 @@ pub unsafe fn svld4_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4b))]
@@ -16901,7 +16901,7 @@ pub unsafe fn svld4_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4h))]
@@ -16913,7 +16913,7 @@ pub unsafe fn svld4_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4w))]
@@ -16925,7 +16925,7 @@ pub unsafe fn svld4_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ld4d))]
@@ -16938,7 +16938,7 @@ pub unsafe fn svld4_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -16955,7 +16955,7 @@ pub unsafe fn svldff1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -16972,7 +16972,7 @@ pub unsafe fn svldff1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -16989,7 +16989,7 @@ pub unsafe fn svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -17006,7 +17006,7 @@ pub unsafe fn svldff1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17023,7 +17023,7 @@ pub unsafe fn svldff1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17040,7 +17040,7 @@ pub unsafe fn svldff1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -17053,7 +17053,7 @@ pub unsafe fn svldff1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -17066,7 +17066,7 @@ pub unsafe fn svldff1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17079,7 +17079,7 @@ pub unsafe fn svldff1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17092,7 +17092,7 @@ pub unsafe fn svldff1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17120,7 +17120,7 @@ pub unsafe fn svldff1_gather_s32index_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17148,7 +17148,7 @@ pub unsafe fn svldff1_gather_s32index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17165,7 +17165,7 @@ pub unsafe fn svldff1_gather_s32index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17193,7 +17193,7 @@ pub unsafe fn svldff1_gather_s64index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17221,7 +17221,7 @@ pub unsafe fn svldff1_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17238,7 +17238,7 @@ pub unsafe fn svldff1_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17266,7 +17266,7 @@ pub unsafe fn svldff1_gather_u32index_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17294,7 +17294,7 @@ pub unsafe fn svldff1_gather_u32index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17311,7 +17311,7 @@ pub unsafe fn svldff1_gather_u32index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17328,7 +17328,7 @@ pub unsafe fn svldff1_gather_u64index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17345,7 +17345,7 @@ pub unsafe fn svldff1_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17362,7 +17362,7 @@ pub unsafe fn svldff1_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17390,7 +17390,7 @@ pub unsafe fn svldff1_gather_s32offset_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17418,7 +17418,7 @@ pub unsafe fn svldff1_gather_s32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17435,7 +17435,7 @@ pub unsafe fn svldff1_gather_s32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17463,7 +17463,7 @@ pub unsafe fn svldff1_gather_s64offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17491,7 +17491,7 @@ pub unsafe fn svldff1_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17508,7 +17508,7 @@ pub unsafe fn svldff1_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17536,7 +17536,7 @@ pub unsafe fn svldff1_gather_u32offset_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17564,7 +17564,7 @@ pub unsafe fn svldff1_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17581,7 +17581,7 @@ pub unsafe fn svldff1_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17598,7 +17598,7 @@ pub unsafe fn svldff1_gather_u64offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17615,7 +17615,7 @@ pub unsafe fn svldff1_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17633,7 +17633,7 @@ pub unsafe fn svldff1_gather_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17647,7 +17647,7 @@ pub unsafe fn svldff1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svf
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17661,7 +17661,7 @@ pub unsafe fn svldff1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svi
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17675,7 +17675,7 @@ pub unsafe fn svldff1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svu
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17689,7 +17689,7 @@ pub unsafe fn svldff1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svf
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17703,7 +17703,7 @@ pub unsafe fn svldff1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17717,7 +17717,7 @@ pub unsafe fn svldff1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17735,7 +17735,7 @@ pub unsafe fn svldff1_gather_u32base_index_f32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17753,7 +17753,7 @@ pub unsafe fn svldff1_gather_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17771,7 +17771,7 @@ pub unsafe fn svldff1_gather_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17789,7 +17789,7 @@ pub unsafe fn svldff1_gather_u64base_index_f64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17807,7 +17807,7 @@ pub unsafe fn svldff1_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17825,7 +17825,7 @@ pub unsafe fn svldff1_gather_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17854,7 +17854,7 @@ pub unsafe fn svldff1_gather_u32base_offset_f32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17883,7 +17883,7 @@ pub unsafe fn svldff1_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17901,7 +17901,7 @@ pub unsafe fn svldff1_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17930,7 +17930,7 @@ pub unsafe fn svldff1_gather_u64base_offset_f64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17959,7 +17959,7 @@ pub unsafe fn svldff1_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -17976,7 +17976,7 @@ pub unsafe fn svldff1_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -17989,7 +17989,7 @@ pub unsafe fn svldff1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svf
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -18002,7 +18002,7 @@ pub unsafe fn svldff1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svf
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -18015,7 +18015,7 @@ pub unsafe fn svldff1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -18028,7 +18028,7 @@ pub unsafe fn svldff1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -18041,7 +18041,7 @@ pub unsafe fn svldff1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -18054,7 +18054,7 @@ pub unsafe fn svldff1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -18067,7 +18067,7 @@ pub unsafe fn svldff1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -18080,7 +18080,7 @@ pub unsafe fn svldff1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -18093,7 +18093,7 @@ pub unsafe fn svldff1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1d))]
@@ -18106,7 +18106,7 @@ pub unsafe fn svldff1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18138,7 +18138,7 @@ pub unsafe fn svldff1sb_gather_s32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18170,7 +18170,7 @@ pub unsafe fn svldff1sh_gather_s32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18187,7 +18187,7 @@ pub unsafe fn svldff1sb_gather_s32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18204,7 +18204,7 @@ pub unsafe fn svldff1sh_gather_s32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18236,7 +18236,7 @@ pub unsafe fn svldff1sb_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18268,7 +18268,7 @@ pub unsafe fn svldff1sh_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18300,7 +18300,7 @@ pub unsafe fn svldff1sw_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18317,7 +18317,7 @@ pub unsafe fn svldff1sb_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18334,7 +18334,7 @@ pub unsafe fn svldff1sh_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18351,7 +18351,7 @@ pub unsafe fn svldff1sw_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18383,7 +18383,7 @@ pub unsafe fn svldff1sb_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18415,7 +18415,7 @@ pub unsafe fn svldff1sh_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18432,7 +18432,7 @@ pub unsafe fn svldff1sb_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18449,7 +18449,7 @@ pub unsafe fn svldff1sh_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18466,7 +18466,7 @@ pub unsafe fn svldff1sb_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18483,7 +18483,7 @@ pub unsafe fn svldff1sh_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18500,7 +18500,7 @@ pub unsafe fn svldff1sw_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18517,7 +18517,7 @@ pub unsafe fn svldff1sb_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18534,7 +18534,7 @@ pub unsafe fn svldff1sh_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18552,7 +18552,7 @@ pub unsafe fn svldff1sw_gather_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18585,7 +18585,7 @@ pub unsafe fn svldff1sb_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18618,7 +18618,7 @@ pub unsafe fn svldff1sh_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18636,7 +18636,7 @@ pub unsafe fn svldff1sb_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18654,7 +18654,7 @@ pub unsafe fn svldff1sh_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18687,7 +18687,7 @@ pub unsafe fn svldff1sb_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18720,7 +18720,7 @@ pub unsafe fn svldff1sh_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18753,7 +18753,7 @@ pub unsafe fn svldff1sw_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18771,7 +18771,7 @@ pub unsafe fn svldff1sb_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18789,7 +18789,7 @@ pub unsafe fn svldff1sh_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18807,7 +18807,7 @@ pub unsafe fn svldff1sw_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18821,7 +18821,7 @@ pub unsafe fn svldff1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18835,7 +18835,7 @@ pub unsafe fn svldff1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18849,7 +18849,7 @@ pub unsafe fn svldff1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18863,7 +18863,7 @@ pub unsafe fn svldff1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18877,7 +18877,7 @@ pub unsafe fn svldff1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18891,7 +18891,7 @@ pub unsafe fn svldff1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18905,7 +18905,7 @@ pub unsafe fn svldff1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18919,7 +18919,7 @@ pub unsafe fn svldff1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18933,7 +18933,7 @@ pub unsafe fn svldff1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -18946,7 +18946,7 @@ pub unsafe fn svldff1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18963,7 +18963,7 @@ pub unsafe fn svldff1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -18980,7 +18980,7 @@ pub unsafe fn svldff1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -18997,7 +18997,7 @@ pub unsafe fn svldff1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19014,7 +19014,7 @@ pub unsafe fn svldff1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19031,7 +19031,7 @@ pub unsafe fn svldff1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19048,7 +19048,7 @@ pub unsafe fn svldff1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19061,7 +19061,7 @@ pub unsafe fn svldff1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19074,7 +19074,7 @@ pub unsafe fn svldff1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19087,7 +19087,7 @@ pub unsafe fn svldff1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19100,7 +19100,7 @@ pub unsafe fn svldff1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19113,7 +19113,7 @@ pub unsafe fn svldff1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19126,7 +19126,7 @@ pub unsafe fn svldff1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19139,7 +19139,7 @@ pub unsafe fn svldff1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19152,7 +19152,7 @@ pub unsafe fn svldff1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19165,7 +19165,7 @@ pub unsafe fn svldff1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19178,7 +19178,7 @@ pub unsafe fn svldff1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19191,7 +19191,7 @@ pub unsafe fn svldff1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19204,7 +19204,7 @@ pub unsafe fn svldff1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19217,7 +19217,7 @@ pub unsafe fn svldff1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19230,7 +19230,7 @@ pub unsafe fn svldff1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19243,7 +19243,7 @@ pub unsafe fn svldff1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sb))]
@@ -19256,7 +19256,7 @@ pub unsafe fn svldff1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19269,7 +19269,7 @@ pub unsafe fn svldff1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19282,7 +19282,7 @@ pub unsafe fn svldff1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19310,7 +19310,7 @@ pub unsafe fn svldff1sh_gather_s32index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19327,7 +19327,7 @@ pub unsafe fn svldff1sh_gather_s32index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19355,7 +19355,7 @@ pub unsafe fn svldff1sh_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19383,7 +19383,7 @@ pub unsafe fn svldff1sw_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19400,7 +19400,7 @@ pub unsafe fn svldff1sh_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19417,7 +19417,7 @@ pub unsafe fn svldff1sw_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19449,7 +19449,7 @@ pub unsafe fn svldff1sh_gather_u32index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19466,7 +19466,7 @@ pub unsafe fn svldff1sh_gather_u32index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19483,7 +19483,7 @@ pub unsafe fn svldff1sh_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19500,7 +19500,7 @@ pub unsafe fn svldff1sw_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19517,7 +19517,7 @@ pub unsafe fn svldff1sh_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19535,7 +19535,7 @@ pub unsafe fn svldff1sw_gather_u64index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19553,7 +19553,7 @@ pub unsafe fn svldff1sh_gather_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19571,7 +19571,7 @@ pub unsafe fn svldff1sh_gather_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19589,7 +19589,7 @@ pub unsafe fn svldff1sh_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19607,7 +19607,7 @@ pub unsafe fn svldff1sw_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sh))]
@@ -19625,7 +19625,7 @@ pub unsafe fn svldff1sh_gather_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1sw))]
@@ -19642,7 +19642,7 @@ pub unsafe fn svldff1sw_gather_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19659,7 +19659,7 @@ pub unsafe fn svldff1ub_gather_s32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -19676,7 +19676,7 @@ pub unsafe fn svldff1uh_gather_s32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19706,7 +19706,7 @@ pub unsafe fn svldff1ub_gather_s32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -19736,7 +19736,7 @@ pub unsafe fn svldff1uh_gather_s32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19753,7 +19753,7 @@ pub unsafe fn svldff1ub_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -19770,7 +19770,7 @@ pub unsafe fn svldff1uh_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -19787,7 +19787,7 @@ pub unsafe fn svldff1uw_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19817,7 +19817,7 @@ pub unsafe fn svldff1ub_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -19847,7 +19847,7 @@ pub unsafe fn svldff1uh_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -19877,7 +19877,7 @@ pub unsafe fn svldff1uw_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19894,7 +19894,7 @@ pub unsafe fn svldff1ub_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -19911,7 +19911,7 @@ pub unsafe fn svldff1uh_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19942,7 +19942,7 @@ pub unsafe fn svldff1ub_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -19973,7 +19973,7 @@ pub unsafe fn svldff1uh_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -19990,7 +19990,7 @@ pub unsafe fn svldff1ub_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20007,7 +20007,7 @@ pub unsafe fn svldff1uh_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20024,7 +20024,7 @@ pub unsafe fn svldff1uw_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20041,7 +20041,7 @@ pub unsafe fn svldff1ub_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20058,7 +20058,7 @@ pub unsafe fn svldff1uh_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20076,7 +20076,7 @@ pub unsafe fn svldff1uw_gather_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20094,7 +20094,7 @@ pub unsafe fn svldff1ub_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20112,7 +20112,7 @@ pub unsafe fn svldff1uh_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20144,7 +20144,7 @@ pub unsafe fn svldff1ub_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20176,7 +20176,7 @@ pub unsafe fn svldff1uh_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20194,7 +20194,7 @@ pub unsafe fn svldff1ub_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20212,7 +20212,7 @@ pub unsafe fn svldff1uh_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20230,7 +20230,7 @@ pub unsafe fn svldff1uw_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20262,7 +20262,7 @@ pub unsafe fn svldff1ub_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20294,7 +20294,7 @@ pub unsafe fn svldff1uh_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20326,7 +20326,7 @@ pub unsafe fn svldff1uw_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20340,7 +20340,7 @@ pub unsafe fn svldff1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20354,7 +20354,7 @@ pub unsafe fn svldff1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20368,7 +20368,7 @@ pub unsafe fn svldff1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20382,7 +20382,7 @@ pub unsafe fn svldff1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20396,7 +20396,7 @@ pub unsafe fn svldff1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20410,7 +20410,7 @@ pub unsafe fn svldff1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20424,7 +20424,7 @@ pub unsafe fn svldff1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20438,7 +20438,7 @@ pub unsafe fn svldff1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20452,7 +20452,7 @@ pub unsafe fn svldff1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20465,7 +20465,7 @@ pub unsafe fn svldff1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20484,7 +20484,7 @@ pub unsafe fn svldff1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20503,7 +20503,7 @@ pub unsafe fn svldff1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20522,7 +20522,7 @@ pub unsafe fn svldff1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20541,7 +20541,7 @@ pub unsafe fn svldff1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20560,7 +20560,7 @@ pub unsafe fn svldff1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20579,7 +20579,7 @@ pub unsafe fn svldff1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20592,7 +20592,7 @@ pub unsafe fn svldff1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20605,7 +20605,7 @@ pub unsafe fn svldff1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20618,7 +20618,7 @@ pub unsafe fn svldff1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20631,7 +20631,7 @@ pub unsafe fn svldff1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20644,7 +20644,7 @@ pub unsafe fn svldff1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20657,7 +20657,7 @@ pub unsafe fn svldff1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20670,7 +20670,7 @@ pub unsafe fn svldff1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20683,7 +20683,7 @@ pub unsafe fn svldff1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20696,7 +20696,7 @@ pub unsafe fn svldff1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20709,7 +20709,7 @@ pub unsafe fn svldff1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20722,7 +20722,7 @@ pub unsafe fn svldff1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20735,7 +20735,7 @@ pub unsafe fn svldff1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20748,7 +20748,7 @@ pub unsafe fn svldff1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20761,7 +20761,7 @@ pub unsafe fn svldff1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20774,7 +20774,7 @@ pub unsafe fn svldff1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1b))]
@@ -20787,7 +20787,7 @@ pub unsafe fn svldff1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20800,7 +20800,7 @@ pub unsafe fn svldff1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20813,7 +20813,7 @@ pub unsafe fn svldff1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20830,7 +20830,7 @@ pub unsafe fn svldff1uh_gather_s32index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20860,7 +20860,7 @@ pub unsafe fn svldff1uh_gather_s32index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20877,7 +20877,7 @@ pub unsafe fn svldff1uh_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20894,7 +20894,7 @@ pub unsafe fn svldff1uw_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20924,7 +20924,7 @@ pub unsafe fn svldff1uh_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -20954,7 +20954,7 @@ pub unsafe fn svldff1uw_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -20971,7 +20971,7 @@ pub unsafe fn svldff1uh_gather_u32index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21002,7 +21002,7 @@ pub unsafe fn svldff1uh_gather_u32index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21019,7 +21019,7 @@ pub unsafe fn svldff1uh_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -21036,7 +21036,7 @@ pub unsafe fn svldff1uw_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21053,7 +21053,7 @@ pub unsafe fn svldff1uh_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -21071,7 +21071,7 @@ pub unsafe fn svldff1uw_gather_u64index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21089,7 +21089,7 @@ pub unsafe fn svldff1uh_gather_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21107,7 +21107,7 @@ pub unsafe fn svldff1uh_gather_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21125,7 +21125,7 @@ pub unsafe fn svldff1uh_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -21143,7 +21143,7 @@ pub unsafe fn svldff1uw_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1h))]
@@ -21161,7 +21161,7 @@ pub unsafe fn svldff1uh_gather_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldff1w))]
@@ -21178,7 +21178,7 @@ pub unsafe fn svldff1uw_gather_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21195,7 +21195,7 @@ pub unsafe fn svldnf1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1d))]
@@ -21212,7 +21212,7 @@ pub unsafe fn svldnf1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21229,7 +21229,7 @@ pub unsafe fn svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21246,7 +21246,7 @@ pub unsafe fn svldnf1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21263,7 +21263,7 @@ pub unsafe fn svldnf1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1d))]
@@ -21280,7 +21280,7 @@ pub unsafe fn svldnf1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21293,7 +21293,7 @@ pub unsafe fn svldnf1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21306,7 +21306,7 @@ pub unsafe fn svldnf1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21319,7 +21319,7 @@ pub unsafe fn svldnf1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1d))]
@@ -21332,7 +21332,7 @@ pub unsafe fn svldnf1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21345,7 +21345,7 @@ pub unsafe fn svldnf1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svf
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1d))]
@@ -21358,7 +21358,7 @@ pub unsafe fn svldnf1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svf
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21371,7 +21371,7 @@ pub unsafe fn svldnf1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21384,7 +21384,7 @@ pub unsafe fn svldnf1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21397,7 +21397,7 @@ pub unsafe fn svldnf1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1d))]
@@ -21410,7 +21410,7 @@ pub unsafe fn svldnf1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21423,7 +21423,7 @@ pub unsafe fn svldnf1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21436,7 +21436,7 @@ pub unsafe fn svldnf1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21449,7 +21449,7 @@ pub unsafe fn svldnf1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1d))]
@@ -21462,7 +21462,7 @@ pub unsafe fn svldnf1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21479,7 +21479,7 @@ pub unsafe fn svldnf1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21496,7 +21496,7 @@ pub unsafe fn svldnf1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21513,7 +21513,7 @@ pub unsafe fn svldnf1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21530,7 +21530,7 @@ pub unsafe fn svldnf1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21547,7 +21547,7 @@ pub unsafe fn svldnf1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sw))]
@@ -21564,7 +21564,7 @@ pub unsafe fn svldnf1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21577,7 +21577,7 @@ pub unsafe fn svldnf1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21590,7 +21590,7 @@ pub unsafe fn svldnf1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21603,7 +21603,7 @@ pub unsafe fn svldnf1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21616,7 +21616,7 @@ pub unsafe fn svldnf1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21629,7 +21629,7 @@ pub unsafe fn svldnf1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sw))]
@@ -21642,7 +21642,7 @@ pub unsafe fn svldnf1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21655,7 +21655,7 @@ pub unsafe fn svldnf1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21668,7 +21668,7 @@ pub unsafe fn svldnf1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21681,7 +21681,7 @@ pub unsafe fn svldnf1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21694,7 +21694,7 @@ pub unsafe fn svldnf1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21707,7 +21707,7 @@ pub unsafe fn svldnf1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sw))]
@@ -21720,7 +21720,7 @@ pub unsafe fn svldnf1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21733,7 +21733,7 @@ pub unsafe fn svldnf1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21746,7 +21746,7 @@ pub unsafe fn svldnf1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21759,7 +21759,7 @@ pub unsafe fn svldnf1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sb))]
@@ -21772,7 +21772,7 @@ pub unsafe fn svldnf1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sh))]
@@ -21785,7 +21785,7 @@ pub unsafe fn svldnf1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1sw))]
@@ -21798,7 +21798,7 @@ pub unsafe fn svldnf1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21817,7 +21817,7 @@ pub unsafe fn svldnf1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21836,7 +21836,7 @@ pub unsafe fn svldnf1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21855,7 +21855,7 @@ pub unsafe fn svldnf1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21874,7 +21874,7 @@ pub unsafe fn svldnf1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21893,7 +21893,7 @@ pub unsafe fn svldnf1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21912,7 +21912,7 @@ pub unsafe fn svldnf1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21925,7 +21925,7 @@ pub unsafe fn svldnf1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21938,7 +21938,7 @@ pub unsafe fn svldnf1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21951,7 +21951,7 @@ pub unsafe fn svldnf1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -21964,7 +21964,7 @@ pub unsafe fn svldnf1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -21977,7 +21977,7 @@ pub unsafe fn svldnf1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -21990,7 +21990,7 @@ pub unsafe fn svldnf1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -22003,7 +22003,7 @@ pub unsafe fn svldnf1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -22016,7 +22016,7 @@ pub unsafe fn svldnf1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -22029,7 +22029,7 @@ pub unsafe fn svldnf1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -22042,7 +22042,7 @@ pub unsafe fn svldnf1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -22055,7 +22055,7 @@ pub unsafe fn svldnf1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -22068,7 +22068,7 @@ pub unsafe fn svldnf1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -22081,7 +22081,7 @@ pub unsafe fn svldnf1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -22094,7 +22094,7 @@ pub unsafe fn svldnf1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -22107,7 +22107,7 @@ pub unsafe fn svldnf1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1b))]
@@ -22120,7 +22120,7 @@ pub unsafe fn svldnf1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1h))]
@@ -22133,7 +22133,7 @@ pub unsafe fn svldnf1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."]
 #[doc = "  * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnf1w))]
@@ -22146,7 +22146,7 @@ pub unsafe fn svldnf1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -22163,7 +22163,7 @@ pub unsafe fn svldnt1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -22180,7 +22180,7 @@ pub unsafe fn svldnt1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -22197,7 +22197,7 @@ pub unsafe fn svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -22214,7 +22214,7 @@ pub unsafe fn svldnt1_s16(pg: svbool_t, base: *const i16) -> svint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -22231,7 +22231,7 @@ pub unsafe fn svldnt1_s32(pg: svbool_t, base: *const i32) -> svint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -22248,7 +22248,7 @@ pub unsafe fn svldnt1_s64(pg: svbool_t, base: *const i64) -> svint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -22261,7 +22261,7 @@ pub unsafe fn svldnt1_u8(pg: svbool_t, base: *const u8) -> svuint8_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -22274,7 +22274,7 @@ pub unsafe fn svldnt1_u16(pg: svbool_t, base: *const u16) -> svuint16_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -22287,7 +22287,7 @@ pub unsafe fn svldnt1_u32(pg: svbool_t, base: *const u32) -> svuint32_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -22300,7 +22300,7 @@ pub unsafe fn svldnt1_u64(pg: svbool_t, base: *const u64) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -22313,7 +22313,7 @@ pub unsafe fn svldnt1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svf
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -22326,7 +22326,7 @@ pub unsafe fn svldnt1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svf
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -22339,7 +22339,7 @@ pub unsafe fn svldnt1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -22352,7 +22352,7 @@ pub unsafe fn svldnt1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -22365,7 +22365,7 @@ pub unsafe fn svldnt1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -22378,7 +22378,7 @@ pub unsafe fn svldnt1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svi
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -22391,7 +22391,7 @@ pub unsafe fn svldnt1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -22404,7 +22404,7 @@ pub unsafe fn svldnt1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -22417,7 +22417,7 @@ pub unsafe fn svldnt1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svu
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -22426,7 +22426,7 @@ pub unsafe fn svldnt1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svu
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntw))]
@@ -22435,7 +22435,7 @@ pub fn svlen_f32(_op: svfloat32_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntd))]
@@ -22444,7 +22444,7 @@ pub fn svlen_f64(_op: svfloat64_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rdvl))]
@@ -22453,7 +22453,7 @@ pub fn svlen_s8(_op: svint8_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnth))]
@@ -22462,7 +22462,7 @@ pub fn svlen_s16(_op: svint16_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntw))]
@@ -22471,7 +22471,7 @@ pub fn svlen_s32(_op: svint32_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntd))]
@@ -22480,7 +22480,7 @@ pub fn svlen_s64(_op: svint64_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rdvl))]
@@ -22489,7 +22489,7 @@ pub fn svlen_u8(_op: svuint8_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cnth))]
@@ -22498,7 +22498,7 @@ pub fn svlen_u16(_op: svuint16_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntw))]
@@ -22507,7 +22507,7 @@ pub fn svlen_u32(_op: svuint32_t) -> u64 {
 }
 #[doc = "Count the number of elements in a full vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cntd))]
@@ -22516,7 +22516,7 @@ pub fn svlen_u64(_op: svuint64_t) -> u64 {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22529,7 +22529,7 @@ pub fn svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22538,7 +22538,7 @@ pub fn svlsl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22547,7 +22547,7 @@ pub fn svlsl_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22556,7 +22556,7 @@ pub fn svlsl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22565,7 +22565,7 @@ pub fn svlsl_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22574,7 +22574,7 @@ pub fn svlsl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22587,7 +22587,7 @@ pub fn svlsl_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22596,7 +22596,7 @@ pub fn svlsl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22605,7 +22605,7 @@ pub fn svlsl_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22614,7 +22614,7 @@ pub fn svlsl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22623,7 +22623,7 @@ pub fn svlsl_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22632,7 +22632,7 @@ pub fn svlsl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22645,7 +22645,7 @@ pub fn svlsl_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22654,7 +22654,7 @@ pub fn svlsl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22663,7 +22663,7 @@ pub fn svlsl_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22672,7 +22672,7 @@ pub fn svlsl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22681,7 +22681,7 @@ pub fn svlsl_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22690,7 +22690,7 @@ pub fn svlsl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22703,7 +22703,7 @@ pub fn svlsl_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22712,7 +22712,7 @@ pub fn svlsl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22721,7 +22721,7 @@ pub fn svlsl_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22730,7 +22730,7 @@ pub fn svlsl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22739,7 +22739,7 @@ pub fn svlsl_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22748,7 +22748,7 @@ pub fn svlsl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22757,7 +22757,7 @@ pub fn svlsl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22766,7 +22766,7 @@ pub fn svlsl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22775,7 +22775,7 @@ pub fn svlsl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22784,7 +22784,7 @@ pub fn svlsl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22793,7 +22793,7 @@ pub fn svlsl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22802,7 +22802,7 @@ pub fn svlsl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22811,7 +22811,7 @@ pub fn svlsl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22820,7 +22820,7 @@ pub fn svlsl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22829,7 +22829,7 @@ pub fn svlsl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22838,7 +22838,7 @@ pub fn svlsl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22847,7 +22847,7 @@ pub fn svlsl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22856,7 +22856,7 @@ pub fn svlsl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22865,7 +22865,7 @@ pub fn svlsl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22874,7 +22874,7 @@ pub fn svlsl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22883,7 +22883,7 @@ pub fn svlsl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22892,7 +22892,7 @@ pub fn svlsl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22901,7 +22901,7 @@ pub fn svlsl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22910,7 +22910,7 @@ pub fn svlsl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22919,7 +22919,7 @@ pub fn svlsl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22928,7 +22928,7 @@ pub fn svlsl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22937,7 +22937,7 @@ pub fn svlsl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22946,7 +22946,7 @@ pub fn svlsl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22955,7 +22955,7 @@ pub fn svlsl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22964,7 +22964,7 @@ pub fn svlsl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22980,7 +22980,7 @@ pub fn svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22989,7 +22989,7 @@ pub fn svlsl_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -22998,7 +22998,7 @@ pub fn svlsl_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23007,7 +23007,7 @@ pub fn svlsl_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23016,7 +23016,7 @@ pub fn svlsl_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23025,7 +23025,7 @@ pub fn svlsl_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23041,7 +23041,7 @@ pub fn svlsl_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint1
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23050,7 +23050,7 @@ pub fn svlsl_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23059,7 +23059,7 @@ pub fn svlsl_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint1
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23068,7 +23068,7 @@ pub fn svlsl_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23077,7 +23077,7 @@ pub fn svlsl_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint1
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23086,7 +23086,7 @@ pub fn svlsl_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23102,7 +23102,7 @@ pub fn svlsl_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint3
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23111,7 +23111,7 @@ pub fn svlsl_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23120,7 +23120,7 @@ pub fn svlsl_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint3
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23129,7 +23129,7 @@ pub fn svlsl_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23138,7 +23138,7 @@ pub fn svlsl_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint3
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23147,7 +23147,7 @@ pub fn svlsl_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23156,7 +23156,7 @@ pub fn svlsl_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23165,7 +23165,7 @@ pub fn svlsl_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23174,7 +23174,7 @@ pub fn svlsl_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23183,7 +23183,7 @@ pub fn svlsl_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23192,7 +23192,7 @@ pub fn svlsl_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23201,7 +23201,7 @@ pub fn svlsl_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23210,7 +23210,7 @@ pub fn svlsl_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23219,7 +23219,7 @@ pub fn svlsl_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23228,7 +23228,7 @@ pub fn svlsl_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23237,7 +23237,7 @@ pub fn svlsl_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23246,7 +23246,7 @@ pub fn svlsl_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23255,7 +23255,7 @@ pub fn svlsl_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23264,7 +23264,7 @@ pub fn svlsl_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23273,7 +23273,7 @@ pub fn svlsl_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23282,7 +23282,7 @@ pub fn svlsl_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23291,7 +23291,7 @@ pub fn svlsl_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23300,7 +23300,7 @@ pub fn svlsl_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsl))]
@@ -23309,7 +23309,7 @@ pub fn svlsl_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23322,7 +23322,7 @@ pub fn svlsr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23331,7 +23331,7 @@ pub fn svlsr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23340,7 +23340,7 @@ pub fn svlsr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23349,7 +23349,7 @@ pub fn svlsr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23358,7 +23358,7 @@ pub fn svlsr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23367,7 +23367,7 @@ pub fn svlsr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23380,7 +23380,7 @@ pub fn svlsr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23389,7 +23389,7 @@ pub fn svlsr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23398,7 +23398,7 @@ pub fn svlsr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23407,7 +23407,7 @@ pub fn svlsr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23416,7 +23416,7 @@ pub fn svlsr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23425,7 +23425,7 @@ pub fn svlsr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23438,7 +23438,7 @@ pub fn svlsr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23447,7 +23447,7 @@ pub fn svlsr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23456,7 +23456,7 @@ pub fn svlsr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23465,7 +23465,7 @@ pub fn svlsr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23474,7 +23474,7 @@ pub fn svlsr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23483,7 +23483,7 @@ pub fn svlsr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23496,7 +23496,7 @@ pub fn svlsr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23505,7 +23505,7 @@ pub fn svlsr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23514,7 +23514,7 @@ pub fn svlsr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23523,7 +23523,7 @@ pub fn svlsr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23532,7 +23532,7 @@ pub fn svlsr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23541,7 +23541,7 @@ pub fn svlsr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23557,7 +23557,7 @@ pub fn svlsr_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23566,7 +23566,7 @@ pub fn svlsr_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23575,7 +23575,7 @@ pub fn svlsr_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23584,7 +23584,7 @@ pub fn svlsr_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23593,7 +23593,7 @@ pub fn svlsr_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23602,7 +23602,7 @@ pub fn svlsr_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t {
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23618,7 +23618,7 @@ pub fn svlsr_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23627,7 +23627,7 @@ pub fn svlsr_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23636,7 +23636,7 @@ pub fn svlsr_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23645,7 +23645,7 @@ pub fn svlsr_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23654,7 +23654,7 @@ pub fn svlsr_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23663,7 +23663,7 @@ pub fn svlsr_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23679,7 +23679,7 @@ pub fn svlsr_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23688,7 +23688,7 @@ pub fn svlsr_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23697,7 +23697,7 @@ pub fn svlsr_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23706,7 +23706,7 @@ pub fn svlsr_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23715,7 +23715,7 @@ pub fn svlsr_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Logical shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(lsr))]
@@ -23724,7 +23724,7 @@ pub fn svlsr_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23747,7 +23747,7 @@ pub fn svmad_f32_m(
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23756,7 +23756,7 @@ pub fn svmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23770,7 +23770,7 @@ pub fn svmad_f32_x(
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23779,7 +23779,7 @@ pub fn svmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23793,7 +23793,7 @@ pub fn svmad_f32_z(
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23802,7 +23802,7 @@ pub fn svmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23825,7 +23825,7 @@ pub fn svmad_f64_m(
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23834,7 +23834,7 @@ pub fn svmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23848,7 +23848,7 @@ pub fn svmad_f64_x(
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23857,7 +23857,7 @@ pub fn svmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23871,7 +23871,7 @@ pub fn svmad_f64_z(
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmad))]
@@ -23880,7 +23880,7 @@ pub fn svmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23893,7 +23893,7 @@ pub fn svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23902,7 +23902,7 @@ pub fn svmad_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23911,7 +23911,7 @@ pub fn svmad_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23920,7 +23920,7 @@ pub fn svmad_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23929,7 +23929,7 @@ pub fn svmad_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23938,7 +23938,7 @@ pub fn svmad_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23952,7 +23952,7 @@ pub fn svmad_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23961,7 +23961,7 @@ pub fn svmad_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23970,7 +23970,7 @@ pub fn svmad_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23979,7 +23979,7 @@ pub fn svmad_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23988,7 +23988,7 @@ pub fn svmad_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -23997,7 +23997,7 @@ pub fn svmad_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24011,7 +24011,7 @@ pub fn svmad_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24020,7 +24020,7 @@ pub fn svmad_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24029,7 +24029,7 @@ pub fn svmad_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24038,7 +24038,7 @@ pub fn svmad_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24047,7 +24047,7 @@ pub fn svmad_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24056,7 +24056,7 @@ pub fn svmad_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24070,7 +24070,7 @@ pub fn svmad_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24079,7 +24079,7 @@ pub fn svmad_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24088,7 +24088,7 @@ pub fn svmad_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24097,7 +24097,7 @@ pub fn svmad_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24106,7 +24106,7 @@ pub fn svmad_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24115,7 +24115,7 @@ pub fn svmad_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24124,7 +24124,7 @@ pub fn svmad_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24133,7 +24133,7 @@ pub fn svmad_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24142,7 +24142,7 @@ pub fn svmad_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24151,7 +24151,7 @@ pub fn svmad_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24160,7 +24160,7 @@ pub fn svmad_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24169,7 +24169,7 @@ pub fn svmad_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24178,7 +24178,7 @@ pub fn svmad_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24187,7 +24187,7 @@ pub fn svmad_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24196,7 +24196,7 @@ pub fn svmad_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24205,7 +24205,7 @@ pub fn svmad_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24214,7 +24214,7 @@ pub fn svmad_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24223,7 +24223,7 @@ pub fn svmad_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24232,7 +24232,7 @@ pub fn svmad_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24241,7 +24241,7 @@ pub fn svmad_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24250,7 +24250,7 @@ pub fn svmad_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24259,7 +24259,7 @@ pub fn svmad_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24268,7 +24268,7 @@ pub fn svmad_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24277,7 +24277,7 @@ pub fn svmad_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24286,7 +24286,7 @@ pub fn svmad_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24295,7 +24295,7 @@ pub fn svmad_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24304,7 +24304,7 @@ pub fn svmad_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24313,7 +24313,7 @@ pub fn svmad_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24322,7 +24322,7 @@ pub fn svmad_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mad))]
@@ -24331,7 +24331,7 @@ pub fn svmad_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24344,7 +24344,7 @@ pub fn svmax_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24353,7 +24353,7 @@ pub fn svmax_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24362,7 +24362,7 @@ pub fn svmax_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24371,7 +24371,7 @@ pub fn svmax_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24380,7 +24380,7 @@ pub fn svmax_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24389,7 +24389,7 @@ pub fn svmax_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24402,7 +24402,7 @@ pub fn svmax_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24411,7 +24411,7 @@ pub fn svmax_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24420,7 +24420,7 @@ pub fn svmax_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24429,7 +24429,7 @@ pub fn svmax_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24438,7 +24438,7 @@ pub fn svmax_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -24447,7 +24447,7 @@ pub fn svmax_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24460,7 +24460,7 @@ pub fn svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24469,7 +24469,7 @@ pub fn svmax_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24478,7 +24478,7 @@ pub fn svmax_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24487,7 +24487,7 @@ pub fn svmax_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24496,7 +24496,7 @@ pub fn svmax_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24505,7 +24505,7 @@ pub fn svmax_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24518,7 +24518,7 @@ pub fn svmax_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24527,7 +24527,7 @@ pub fn svmax_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24536,7 +24536,7 @@ pub fn svmax_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24545,7 +24545,7 @@ pub fn svmax_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24554,7 +24554,7 @@ pub fn svmax_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24563,7 +24563,7 @@ pub fn svmax_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24576,7 +24576,7 @@ pub fn svmax_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24585,7 +24585,7 @@ pub fn svmax_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24594,7 +24594,7 @@ pub fn svmax_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24603,7 +24603,7 @@ pub fn svmax_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24612,7 +24612,7 @@ pub fn svmax_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24621,7 +24621,7 @@ pub fn svmax_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24634,7 +24634,7 @@ pub fn svmax_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24643,7 +24643,7 @@ pub fn svmax_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24652,7 +24652,7 @@ pub fn svmax_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24661,7 +24661,7 @@ pub fn svmax_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24670,7 +24670,7 @@ pub fn svmax_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smax))]
@@ -24679,7 +24679,7 @@ pub fn svmax_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24692,7 +24692,7 @@ pub fn svmax_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24701,7 +24701,7 @@ pub fn svmax_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24710,7 +24710,7 @@ pub fn svmax_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24719,7 +24719,7 @@ pub fn svmax_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24728,7 +24728,7 @@ pub fn svmax_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24737,7 +24737,7 @@ pub fn svmax_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24750,7 +24750,7 @@ pub fn svmax_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24759,7 +24759,7 @@ pub fn svmax_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24768,7 +24768,7 @@ pub fn svmax_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24777,7 +24777,7 @@ pub fn svmax_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24786,7 +24786,7 @@ pub fn svmax_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24795,7 +24795,7 @@ pub fn svmax_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24808,7 +24808,7 @@ pub fn svmax_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24817,7 +24817,7 @@ pub fn svmax_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24826,7 +24826,7 @@ pub fn svmax_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24835,7 +24835,7 @@ pub fn svmax_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24844,7 +24844,7 @@ pub fn svmax_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24853,7 +24853,7 @@ pub fn svmax_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24866,7 +24866,7 @@ pub fn svmax_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24875,7 +24875,7 @@ pub fn svmax_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24884,7 +24884,7 @@ pub fn svmax_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24893,7 +24893,7 @@ pub fn svmax_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24902,7 +24902,7 @@ pub fn svmax_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umax))]
@@ -24911,7 +24911,7 @@ pub fn svmax_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24924,7 +24924,7 @@ pub fn svmaxnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24933,7 +24933,7 @@ pub fn svmaxnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24942,7 +24942,7 @@ pub fn svmaxnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24951,7 +24951,7 @@ pub fn svmaxnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24960,7 +24960,7 @@ pub fn svmaxnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24969,7 +24969,7 @@ pub fn svmaxnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24982,7 +24982,7 @@ pub fn svmaxnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -24991,7 +24991,7 @@ pub fn svmaxnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -25000,7 +25000,7 @@ pub fn svmaxnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -25009,7 +25009,7 @@ pub fn svmaxnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -25018,7 +25018,7 @@ pub fn svmaxnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Maximum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -25027,7 +25027,7 @@ pub fn svmaxnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t
 }
 #[doc = "Maximum number reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
@@ -25043,7 +25043,7 @@ pub fn svmaxnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Maximum number reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
@@ -25059,7 +25059,7 @@ pub fn svmaxnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxv))]
@@ -25072,7 +25072,7 @@ pub fn svmaxv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxv))]
@@ -25085,7 +25085,7 @@ pub fn svmaxv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -25098,7 +25098,7 @@ pub fn svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -25111,7 +25111,7 @@ pub fn svmaxv_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -25124,7 +25124,7 @@ pub fn svmaxv_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -25137,7 +25137,7 @@ pub fn svmaxv_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -25150,7 +25150,7 @@ pub fn svmaxv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -25163,7 +25163,7 @@ pub fn svmaxv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -25176,7 +25176,7 @@ pub fn svmaxv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Maximum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -25189,7 +25189,7 @@ pub fn svmaxv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25202,7 +25202,7 @@ pub fn svmin_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25211,7 +25211,7 @@ pub fn svmin_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25220,7 +25220,7 @@ pub fn svmin_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25229,7 +25229,7 @@ pub fn svmin_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25238,7 +25238,7 @@ pub fn svmin_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25247,7 +25247,7 @@ pub fn svmin_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25260,7 +25260,7 @@ pub fn svmin_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25269,7 +25269,7 @@ pub fn svmin_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25278,7 +25278,7 @@ pub fn svmin_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25287,7 +25287,7 @@ pub fn svmin_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25296,7 +25296,7 @@ pub fn svmin_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -25305,7 +25305,7 @@ pub fn svmin_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25318,7 +25318,7 @@ pub fn svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25327,7 +25327,7 @@ pub fn svmin_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25336,7 +25336,7 @@ pub fn svmin_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25345,7 +25345,7 @@ pub fn svmin_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25354,7 +25354,7 @@ pub fn svmin_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25363,7 +25363,7 @@ pub fn svmin_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25376,7 +25376,7 @@ pub fn svmin_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25385,7 +25385,7 @@ pub fn svmin_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25394,7 +25394,7 @@ pub fn svmin_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25403,7 +25403,7 @@ pub fn svmin_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25412,7 +25412,7 @@ pub fn svmin_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25421,7 +25421,7 @@ pub fn svmin_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25434,7 +25434,7 @@ pub fn svmin_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25443,7 +25443,7 @@ pub fn svmin_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25452,7 +25452,7 @@ pub fn svmin_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25461,7 +25461,7 @@ pub fn svmin_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25470,7 +25470,7 @@ pub fn svmin_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25479,7 +25479,7 @@ pub fn svmin_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25492,7 +25492,7 @@ pub fn svmin_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25501,7 +25501,7 @@ pub fn svmin_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25510,7 +25510,7 @@ pub fn svmin_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25519,7 +25519,7 @@ pub fn svmin_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25528,7 +25528,7 @@ pub fn svmin_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smin))]
@@ -25537,7 +25537,7 @@ pub fn svmin_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25550,7 +25550,7 @@ pub fn svmin_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25559,7 +25559,7 @@ pub fn svmin_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25568,7 +25568,7 @@ pub fn svmin_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25577,7 +25577,7 @@ pub fn svmin_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25586,7 +25586,7 @@ pub fn svmin_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25595,7 +25595,7 @@ pub fn svmin_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25608,7 +25608,7 @@ pub fn svmin_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25617,7 +25617,7 @@ pub fn svmin_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25626,7 +25626,7 @@ pub fn svmin_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25635,7 +25635,7 @@ pub fn svmin_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25644,7 +25644,7 @@ pub fn svmin_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25653,7 +25653,7 @@ pub fn svmin_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25666,7 +25666,7 @@ pub fn svmin_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25675,7 +25675,7 @@ pub fn svmin_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25684,7 +25684,7 @@ pub fn svmin_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25693,7 +25693,7 @@ pub fn svmin_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25702,7 +25702,7 @@ pub fn svmin_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25711,7 +25711,7 @@ pub fn svmin_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25724,7 +25724,7 @@ pub fn svmin_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25733,7 +25733,7 @@ pub fn svmin_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25742,7 +25742,7 @@ pub fn svmin_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25751,7 +25751,7 @@ pub fn svmin_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25760,7 +25760,7 @@ pub fn svmin_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umin))]
@@ -25769,7 +25769,7 @@ pub fn svmin_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25782,7 +25782,7 @@ pub fn svminnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25791,7 +25791,7 @@ pub fn svminnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25800,7 +25800,7 @@ pub fn svminnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25809,7 +25809,7 @@ pub fn svminnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25818,7 +25818,7 @@ pub fn svminnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25827,7 +25827,7 @@ pub fn svminnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25840,7 +25840,7 @@ pub fn svminnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25849,7 +25849,7 @@ pub fn svminnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25858,7 +25858,7 @@ pub fn svminnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25867,7 +25867,7 @@ pub fn svminnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25876,7 +25876,7 @@ pub fn svminnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Minimum number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -25885,7 +25885,7 @@ pub fn svminnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t
 }
 #[doc = "Minimum number reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnmv))]
@@ -25901,7 +25901,7 @@ pub fn svminnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Minimum number reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnmv))]
@@ -25917,7 +25917,7 @@ pub fn svminnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminv))]
@@ -25930,7 +25930,7 @@ pub fn svminv_f32(pg: svbool_t, op: svfloat32_t) -> f32 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminv))]
@@ -25943,7 +25943,7 @@ pub fn svminv_f64(pg: svbool_t, op: svfloat64_t) -> f64 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -25956,7 +25956,7 @@ pub fn svminv_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -25969,7 +25969,7 @@ pub fn svminv_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -25982,7 +25982,7 @@ pub fn svminv_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -25995,7 +25995,7 @@ pub fn svminv_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -26008,7 +26008,7 @@ pub fn svminv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -26021,7 +26021,7 @@ pub fn svminv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -26034,7 +26034,7 @@ pub fn svminv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Minimum reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -26047,7 +26047,7 @@ pub fn svminv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26070,7 +26070,7 @@ pub fn svmla_f32_m(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26079,7 +26079,7 @@ pub fn svmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26093,7 +26093,7 @@ pub fn svmla_f32_x(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26102,7 +26102,7 @@ pub fn svmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26116,7 +26116,7 @@ pub fn svmla_f32_z(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26125,7 +26125,7 @@ pub fn svmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26148,7 +26148,7 @@ pub fn svmla_f64_m(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26157,7 +26157,7 @@ pub fn svmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26171,7 +26171,7 @@ pub fn svmla_f64_x(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26180,7 +26180,7 @@ pub fn svmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26194,7 +26194,7 @@ pub fn svmla_f64_z(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -26203,7 +26203,7 @@ pub fn svmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26216,7 +26216,7 @@ pub fn svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26225,7 +26225,7 @@ pub fn svmla_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26234,7 +26234,7 @@ pub fn svmla_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26243,7 +26243,7 @@ pub fn svmla_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26252,7 +26252,7 @@ pub fn svmla_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26261,7 +26261,7 @@ pub fn svmla_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26275,7 +26275,7 @@ pub fn svmla_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26284,7 +26284,7 @@ pub fn svmla_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26293,7 +26293,7 @@ pub fn svmla_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26302,7 +26302,7 @@ pub fn svmla_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26311,7 +26311,7 @@ pub fn svmla_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26320,7 +26320,7 @@ pub fn svmla_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26334,7 +26334,7 @@ pub fn svmla_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26343,7 +26343,7 @@ pub fn svmla_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26352,7 +26352,7 @@ pub fn svmla_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26361,7 +26361,7 @@ pub fn svmla_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26370,7 +26370,7 @@ pub fn svmla_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26379,7 +26379,7 @@ pub fn svmla_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26393,7 +26393,7 @@ pub fn svmla_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26402,7 +26402,7 @@ pub fn svmla_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26411,7 +26411,7 @@ pub fn svmla_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26420,7 +26420,7 @@ pub fn svmla_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26429,7 +26429,7 @@ pub fn svmla_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26438,7 +26438,7 @@ pub fn svmla_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26447,7 +26447,7 @@ pub fn svmla_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26456,7 +26456,7 @@ pub fn svmla_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26465,7 +26465,7 @@ pub fn svmla_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26474,7 +26474,7 @@ pub fn svmla_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26483,7 +26483,7 @@ pub fn svmla_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26492,7 +26492,7 @@ pub fn svmla_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26501,7 +26501,7 @@ pub fn svmla_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26510,7 +26510,7 @@ pub fn svmla_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26519,7 +26519,7 @@ pub fn svmla_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26528,7 +26528,7 @@ pub fn svmla_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26537,7 +26537,7 @@ pub fn svmla_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26546,7 +26546,7 @@ pub fn svmla_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26555,7 +26555,7 @@ pub fn svmla_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26564,7 +26564,7 @@ pub fn svmla_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26573,7 +26573,7 @@ pub fn svmla_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26582,7 +26582,7 @@ pub fn svmla_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26591,7 +26591,7 @@ pub fn svmla_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26600,7 +26600,7 @@ pub fn svmla_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26609,7 +26609,7 @@ pub fn svmla_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26618,7 +26618,7 @@ pub fn svmla_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26627,7 +26627,7 @@ pub fn svmla_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26636,7 +26636,7 @@ pub fn svmla_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26645,7 +26645,7 @@ pub fn svmla_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla))]
@@ -26654,7 +26654,7 @@ pub fn svmla_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))]
@@ -26680,7 +26680,7 @@ pub fn svmla_lane_f32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))]
@@ -26706,7 +26706,7 @@ pub fn svmla_lane_f64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26729,7 +26729,7 @@ pub fn svmls_f32_m(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26738,7 +26738,7 @@ pub fn svmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26752,7 +26752,7 @@ pub fn svmls_f32_x(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26761,7 +26761,7 @@ pub fn svmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26775,7 +26775,7 @@ pub fn svmls_f32_z(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26784,7 +26784,7 @@ pub fn svmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26807,7 +26807,7 @@ pub fn svmls_f64_m(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26816,7 +26816,7 @@ pub fn svmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26830,7 +26830,7 @@ pub fn svmls_f64_x(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26839,7 +26839,7 @@ pub fn svmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26853,7 +26853,7 @@ pub fn svmls_f64_z(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls))]
@@ -26862,7 +26862,7 @@ pub fn svmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26875,7 +26875,7 @@ pub fn svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26884,7 +26884,7 @@ pub fn svmls_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26893,7 +26893,7 @@ pub fn svmls_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26902,7 +26902,7 @@ pub fn svmls_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26911,7 +26911,7 @@ pub fn svmls_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26920,7 +26920,7 @@ pub fn svmls_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26934,7 +26934,7 @@ pub fn svmls_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26943,7 +26943,7 @@ pub fn svmls_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26952,7 +26952,7 @@ pub fn svmls_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26961,7 +26961,7 @@ pub fn svmls_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26970,7 +26970,7 @@ pub fn svmls_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26979,7 +26979,7 @@ pub fn svmls_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -26993,7 +26993,7 @@ pub fn svmls_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27002,7 +27002,7 @@ pub fn svmls_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27011,7 +27011,7 @@ pub fn svmls_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27020,7 +27020,7 @@ pub fn svmls_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27029,7 +27029,7 @@ pub fn svmls_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27038,7 +27038,7 @@ pub fn svmls_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27052,7 +27052,7 @@ pub fn svmls_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27061,7 +27061,7 @@ pub fn svmls_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27070,7 +27070,7 @@ pub fn svmls_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27079,7 +27079,7 @@ pub fn svmls_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27088,7 +27088,7 @@ pub fn svmls_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27097,7 +27097,7 @@ pub fn svmls_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27106,7 +27106,7 @@ pub fn svmls_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27115,7 +27115,7 @@ pub fn svmls_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27124,7 +27124,7 @@ pub fn svmls_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27133,7 +27133,7 @@ pub fn svmls_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27142,7 +27142,7 @@ pub fn svmls_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27151,7 +27151,7 @@ pub fn svmls_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27160,7 +27160,7 @@ pub fn svmls_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27169,7 +27169,7 @@ pub fn svmls_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27178,7 +27178,7 @@ pub fn svmls_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27187,7 +27187,7 @@ pub fn svmls_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27196,7 +27196,7 @@ pub fn svmls_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27205,7 +27205,7 @@ pub fn svmls_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27214,7 +27214,7 @@ pub fn svmls_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27223,7 +27223,7 @@ pub fn svmls_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27232,7 +27232,7 @@ pub fn svmls_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27241,7 +27241,7 @@ pub fn svmls_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27250,7 +27250,7 @@ pub fn svmls_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27259,7 +27259,7 @@ pub fn svmls_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27268,7 +27268,7 @@ pub fn svmls_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27277,7 +27277,7 @@ pub fn svmls_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27286,7 +27286,7 @@ pub fn svmls_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27295,7 +27295,7 @@ pub fn svmls_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27304,7 +27304,7 @@ pub fn svmls_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls))]
@@ -27313,7 +27313,7 @@ pub fn svmls_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))]
@@ -27339,7 +27339,7 @@ pub fn svmls_lane_f32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))]
@@ -27365,7 +27365,7 @@ pub fn svmls_lane_f64<const IMM_INDEX: i32>(
 }
 #[doc = "Matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f32mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmmla))]
@@ -27378,7 +27378,7 @@ pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svflo
 }
 #[doc = "Matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmmla))]
@@ -27391,7 +27391,7 @@ pub fn svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svflo
 }
 #[doc = "Matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smmla))]
@@ -27404,7 +27404,7 @@ pub fn svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t {
 }
 #[doc = "Matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ummla))]
@@ -27417,7 +27417,7 @@ pub fn svmmla_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t
 }
 #[doc = "Move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmov[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mov))]
@@ -27426,7 +27426,7 @@ pub fn svmov_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27449,7 +27449,7 @@ pub fn svmsb_f32_m(
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27458,7 +27458,7 @@ pub fn svmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27472,7 +27472,7 @@ pub fn svmsb_f32_x(
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27481,7 +27481,7 @@ pub fn svmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27495,7 +27495,7 @@ pub fn svmsb_f32_z(
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27504,7 +27504,7 @@ pub fn svmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27527,7 +27527,7 @@ pub fn svmsb_f64_m(
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27536,7 +27536,7 @@ pub fn svmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27550,7 +27550,7 @@ pub fn svmsb_f64_x(
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27559,7 +27559,7 @@ pub fn svmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27573,7 +27573,7 @@ pub fn svmsb_f64_z(
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmsb))]
@@ -27582,7 +27582,7 @@ pub fn svmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27595,7 +27595,7 @@ pub fn svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27604,7 +27604,7 @@ pub fn svmsb_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27613,7 +27613,7 @@ pub fn svmsb_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27622,7 +27622,7 @@ pub fn svmsb_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27631,7 +27631,7 @@ pub fn svmsb_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27640,7 +27640,7 @@ pub fn svmsb_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svin
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27654,7 +27654,7 @@ pub fn svmsb_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27663,7 +27663,7 @@ pub fn svmsb_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27672,7 +27672,7 @@ pub fn svmsb_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27681,7 +27681,7 @@ pub fn svmsb_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27690,7 +27690,7 @@ pub fn svmsb_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27699,7 +27699,7 @@ pub fn svmsb_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27713,7 +27713,7 @@ pub fn svmsb_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27722,7 +27722,7 @@ pub fn svmsb_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27731,7 +27731,7 @@ pub fn svmsb_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27740,7 +27740,7 @@ pub fn svmsb_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27749,7 +27749,7 @@ pub fn svmsb_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27758,7 +27758,7 @@ pub fn svmsb_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27772,7 +27772,7 @@ pub fn svmsb_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27781,7 +27781,7 @@ pub fn svmsb_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27790,7 +27790,7 @@ pub fn svmsb_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27799,7 +27799,7 @@ pub fn svmsb_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27808,7 +27808,7 @@ pub fn svmsb_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27817,7 +27817,7 @@ pub fn svmsb_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) ->
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27826,7 +27826,7 @@ pub fn svmsb_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27835,7 +27835,7 @@ pub fn svmsb_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27844,7 +27844,7 @@ pub fn svmsb_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27853,7 +27853,7 @@ pub fn svmsb_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27862,7 +27862,7 @@ pub fn svmsb_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t)
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27871,7 +27871,7 @@ pub fn svmsb_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> sv
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27880,7 +27880,7 @@ pub fn svmsb_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27889,7 +27889,7 @@ pub fn svmsb_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27898,7 +27898,7 @@ pub fn svmsb_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27907,7 +27907,7 @@ pub fn svmsb_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27916,7 +27916,7 @@ pub fn svmsb_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27925,7 +27925,7 @@ pub fn svmsb_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27934,7 +27934,7 @@ pub fn svmsb_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27943,7 +27943,7 @@ pub fn svmsb_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27952,7 +27952,7 @@ pub fn svmsb_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27961,7 +27961,7 @@ pub fn svmsb_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27970,7 +27970,7 @@ pub fn svmsb_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27979,7 +27979,7 @@ pub fn svmsb_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27988,7 +27988,7 @@ pub fn svmsb_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -27997,7 +27997,7 @@ pub fn svmsb_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -28006,7 +28006,7 @@ pub fn svmsb_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -28015,7 +28015,7 @@ pub fn svmsb_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -28024,7 +28024,7 @@ pub fn svmsb_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64
 }
 #[doc = "Multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(msb))]
@@ -28033,7 +28033,7 @@ pub fn svmsb_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28046,7 +28046,7 @@ pub fn svmul_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28055,7 +28055,7 @@ pub fn svmul_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28064,7 +28064,7 @@ pub fn svmul_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28073,7 +28073,7 @@ pub fn svmul_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28082,7 +28082,7 @@ pub fn svmul_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28091,7 +28091,7 @@ pub fn svmul_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28104,7 +28104,7 @@ pub fn svmul_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28113,7 +28113,7 @@ pub fn svmul_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28122,7 +28122,7 @@ pub fn svmul_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28131,7 +28131,7 @@ pub fn svmul_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28140,7 +28140,7 @@ pub fn svmul_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -28149,7 +28149,7 @@ pub fn svmul_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28162,7 +28162,7 @@ pub fn svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28171,7 +28171,7 @@ pub fn svmul_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28180,7 +28180,7 @@ pub fn svmul_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28189,7 +28189,7 @@ pub fn svmul_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28198,7 +28198,7 @@ pub fn svmul_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28207,7 +28207,7 @@ pub fn svmul_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28220,7 +28220,7 @@ pub fn svmul_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28229,7 +28229,7 @@ pub fn svmul_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28238,7 +28238,7 @@ pub fn svmul_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28247,7 +28247,7 @@ pub fn svmul_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28256,7 +28256,7 @@ pub fn svmul_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28265,7 +28265,7 @@ pub fn svmul_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28278,7 +28278,7 @@ pub fn svmul_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28287,7 +28287,7 @@ pub fn svmul_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28296,7 +28296,7 @@ pub fn svmul_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28305,7 +28305,7 @@ pub fn svmul_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28314,7 +28314,7 @@ pub fn svmul_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28323,7 +28323,7 @@ pub fn svmul_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28336,7 +28336,7 @@ pub fn svmul_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28345,7 +28345,7 @@ pub fn svmul_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28354,7 +28354,7 @@ pub fn svmul_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28363,7 +28363,7 @@ pub fn svmul_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28372,7 +28372,7 @@ pub fn svmul_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28381,7 +28381,7 @@ pub fn svmul_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28390,7 +28390,7 @@ pub fn svmul_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28399,7 +28399,7 @@ pub fn svmul_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28408,7 +28408,7 @@ pub fn svmul_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28417,7 +28417,7 @@ pub fn svmul_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28426,7 +28426,7 @@ pub fn svmul_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28435,7 +28435,7 @@ pub fn svmul_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28444,7 +28444,7 @@ pub fn svmul_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28453,7 +28453,7 @@ pub fn svmul_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28462,7 +28462,7 @@ pub fn svmul_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28471,7 +28471,7 @@ pub fn svmul_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28480,7 +28480,7 @@ pub fn svmul_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28489,7 +28489,7 @@ pub fn svmul_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28498,7 +28498,7 @@ pub fn svmul_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28507,7 +28507,7 @@ pub fn svmul_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28516,7 +28516,7 @@ pub fn svmul_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28525,7 +28525,7 @@ pub fn svmul_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28534,7 +28534,7 @@ pub fn svmul_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28543,7 +28543,7 @@ pub fn svmul_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28552,7 +28552,7 @@ pub fn svmul_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28561,7 +28561,7 @@ pub fn svmul_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28570,7 +28570,7 @@ pub fn svmul_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28579,7 +28579,7 @@ pub fn svmul_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28588,7 +28588,7 @@ pub fn svmul_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul))]
@@ -28597,7 +28597,7 @@ pub fn svmul_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28610,7 +28610,7 @@ pub fn svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28619,7 +28619,7 @@ pub fn svmulh_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28628,7 +28628,7 @@ pub fn svmulh_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28637,7 +28637,7 @@ pub fn svmulh_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28646,7 +28646,7 @@ pub fn svmulh_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28655,7 +28655,7 @@ pub fn svmulh_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28668,7 +28668,7 @@ pub fn svmulh_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28677,7 +28677,7 @@ pub fn svmulh_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28686,7 +28686,7 @@ pub fn svmulh_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28695,7 +28695,7 @@ pub fn svmulh_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28704,7 +28704,7 @@ pub fn svmulh_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28713,7 +28713,7 @@ pub fn svmulh_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28726,7 +28726,7 @@ pub fn svmulh_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28735,7 +28735,7 @@ pub fn svmulh_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28744,7 +28744,7 @@ pub fn svmulh_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28753,7 +28753,7 @@ pub fn svmulh_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28762,7 +28762,7 @@ pub fn svmulh_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28771,7 +28771,7 @@ pub fn svmulh_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28784,7 +28784,7 @@ pub fn svmulh_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28793,7 +28793,7 @@ pub fn svmulh_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28802,7 +28802,7 @@ pub fn svmulh_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28811,7 +28811,7 @@ pub fn svmulh_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28820,7 +28820,7 @@ pub fn svmulh_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smulh))]
@@ -28829,7 +28829,7 @@ pub fn svmulh_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28842,7 +28842,7 @@ pub fn svmulh_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28851,7 +28851,7 @@ pub fn svmulh_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28860,7 +28860,7 @@ pub fn svmulh_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28869,7 +28869,7 @@ pub fn svmulh_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28878,7 +28878,7 @@ pub fn svmulh_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28887,7 +28887,7 @@ pub fn svmulh_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28900,7 +28900,7 @@ pub fn svmulh_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28909,7 +28909,7 @@ pub fn svmulh_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28918,7 +28918,7 @@ pub fn svmulh_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28927,7 +28927,7 @@ pub fn svmulh_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28936,7 +28936,7 @@ pub fn svmulh_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28945,7 +28945,7 @@ pub fn svmulh_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28958,7 +28958,7 @@ pub fn svmulh_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28967,7 +28967,7 @@ pub fn svmulh_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28976,7 +28976,7 @@ pub fn svmulh_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28985,7 +28985,7 @@ pub fn svmulh_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -28994,7 +28994,7 @@ pub fn svmulh_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29003,7 +29003,7 @@ pub fn svmulh_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29016,7 +29016,7 @@ pub fn svmulh_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29025,7 +29025,7 @@ pub fn svmulh_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29034,7 +29034,7 @@ pub fn svmulh_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29043,7 +29043,7 @@ pub fn svmulh_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29052,7 +29052,7 @@ pub fn svmulh_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Multiply, returning high-half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umulh))]
@@ -29061,7 +29061,7 @@ pub fn svmulh_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29074,7 +29074,7 @@ pub fn svmulx_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29083,7 +29083,7 @@ pub fn svmulx_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29092,7 +29092,7 @@ pub fn svmulx_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29101,7 +29101,7 @@ pub fn svmulx_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29110,7 +29110,7 @@ pub fn svmulx_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29119,7 +29119,7 @@ pub fn svmulx_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29132,7 +29132,7 @@ pub fn svmulx_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29141,7 +29141,7 @@ pub fn svmulx_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29150,7 +29150,7 @@ pub fn svmulx_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29159,7 +29159,7 @@ pub fn svmulx_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29168,7 +29168,7 @@ pub fn svmulx_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Multiply extended (∞×0=2)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -29177,7 +29177,7 @@ pub fn svmulx_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Bitwise NAND"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnand[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nand))]
@@ -29190,7 +29190,7 @@ pub fn svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -29203,7 +29203,7 @@ pub fn svneg_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfl
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -29212,7 +29212,7 @@ pub fn svneg_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -29221,7 +29221,7 @@ pub fn svneg_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -29234,7 +29234,7 @@ pub fn svneg_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfl
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -29243,7 +29243,7 @@ pub fn svneg_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -29252,7 +29252,7 @@ pub fn svneg_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29265,7 +29265,7 @@ pub fn svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29274,7 +29274,7 @@ pub fn svneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29283,7 +29283,7 @@ pub fn svneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29296,7 +29296,7 @@ pub fn svneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29305,7 +29305,7 @@ pub fn svneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29314,7 +29314,7 @@ pub fn svneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29327,7 +29327,7 @@ pub fn svneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29336,7 +29336,7 @@ pub fn svneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29345,7 +29345,7 @@ pub fn svneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29358,7 +29358,7 @@ pub fn svneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29367,7 +29367,7 @@ pub fn svneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -29376,7 +29376,7 @@ pub fn svneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29399,7 +29399,7 @@ pub fn svnmad_f32_m(
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29408,7 +29408,7 @@ pub fn svnmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29422,7 +29422,7 @@ pub fn svnmad_f32_x(
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29431,7 +29431,7 @@ pub fn svnmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29445,7 +29445,7 @@ pub fn svnmad_f32_z(
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29454,7 +29454,7 @@ pub fn svnmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29477,7 +29477,7 @@ pub fn svnmad_f64_m(
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29486,7 +29486,7 @@ pub fn svnmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29500,7 +29500,7 @@ pub fn svnmad_f64_x(
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29509,7 +29509,7 @@ pub fn svnmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29523,7 +29523,7 @@ pub fn svnmad_f64_z(
 }
 #[doc = "Negated multiply-add, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmad))]
@@ -29532,7 +29532,7 @@ pub fn svnmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29555,7 +29555,7 @@ pub fn svnmla_f32_m(
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29564,7 +29564,7 @@ pub fn svnmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29578,7 +29578,7 @@ pub fn svnmla_f32_x(
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29587,7 +29587,7 @@ pub fn svnmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29601,7 +29601,7 @@ pub fn svnmla_f32_z(
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29610,7 +29610,7 @@ pub fn svnmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29633,7 +29633,7 @@ pub fn svnmla_f64_m(
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29642,7 +29642,7 @@ pub fn svnmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29656,7 +29656,7 @@ pub fn svnmla_f64_x(
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29665,7 +29665,7 @@ pub fn svnmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29679,7 +29679,7 @@ pub fn svnmla_f64_z(
 }
 #[doc = "Negated multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmla))]
@@ -29688,7 +29688,7 @@ pub fn svnmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29711,7 +29711,7 @@ pub fn svnmls_f32_m(
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29720,7 +29720,7 @@ pub fn svnmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29734,7 +29734,7 @@ pub fn svnmls_f32_x(
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29743,7 +29743,7 @@ pub fn svnmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29757,7 +29757,7 @@ pub fn svnmls_f32_z(
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29766,7 +29766,7 @@ pub fn svnmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29789,7 +29789,7 @@ pub fn svnmls_f64_m(
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29798,7 +29798,7 @@ pub fn svnmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29812,7 +29812,7 @@ pub fn svnmls_f64_x(
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29821,7 +29821,7 @@ pub fn svnmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29835,7 +29835,7 @@ pub fn svnmls_f64_z(
 }
 #[doc = "Negated multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmls))]
@@ -29844,7 +29844,7 @@ pub fn svnmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29867,7 +29867,7 @@ pub fn svnmsb_f32_m(
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29876,7 +29876,7 @@ pub fn svnmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29890,7 +29890,7 @@ pub fn svnmsb_f32_x(
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29899,7 +29899,7 @@ pub fn svnmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29913,7 +29913,7 @@ pub fn svnmsb_f32_z(
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29922,7 +29922,7 @@ pub fn svnmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29945,7 +29945,7 @@ pub fn svnmsb_f64_m(
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29954,7 +29954,7 @@ pub fn svnmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29968,7 +29968,7 @@ pub fn svnmsb_f64_x(
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29977,7 +29977,7 @@ pub fn svnmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -29991,7 +29991,7 @@ pub fn svnmsb_f64_z(
 }
 #[doc = "Negated multiply-subtract, multiplicand first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fnmsb))]
@@ -30000,7 +30000,7 @@ pub fn svnmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64
 }
 #[doc = "Bitwise NOR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnor[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nor))]
@@ -30013,7 +30013,7 @@ pub fn svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30022,7 +30022,7 @@ pub fn svnot_b_z(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30035,7 +30035,7 @@ pub fn svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30044,7 +30044,7 @@ pub fn svnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30053,7 +30053,7 @@ pub fn svnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30066,7 +30066,7 @@ pub fn svnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30075,7 +30075,7 @@ pub fn svnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30084,7 +30084,7 @@ pub fn svnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30097,7 +30097,7 @@ pub fn svnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30106,7 +30106,7 @@ pub fn svnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30115,7 +30115,7 @@ pub fn svnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30128,7 +30128,7 @@ pub fn svnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30137,7 +30137,7 @@ pub fn svnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30146,7 +30146,7 @@ pub fn svnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30155,7 +30155,7 @@ pub fn svnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30164,7 +30164,7 @@ pub fn svnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30173,7 +30173,7 @@ pub fn svnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30182,7 +30182,7 @@ pub fn svnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30191,7 +30191,7 @@ pub fn svnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30200,7 +30200,7 @@ pub fn svnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30209,7 +30209,7 @@ pub fn svnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30218,7 +30218,7 @@ pub fn svnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30227,7 +30227,7 @@ pub fn svnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30236,7 +30236,7 @@ pub fn svnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30245,7 +30245,7 @@ pub fn svnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Bitwise invert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(not))]
@@ -30254,7 +30254,7 @@ pub fn svnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Bitwise inclusive OR, inverting second argument"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorn[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orn))]
@@ -30267,7 +30267,7 @@ pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_b]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30280,7 +30280,7 @@ pub fn svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30293,7 +30293,7 @@ pub fn svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30302,7 +30302,7 @@ pub fn svorr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30311,7 +30311,7 @@ pub fn svorr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30320,7 +30320,7 @@ pub fn svorr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30329,7 +30329,7 @@ pub fn svorr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30338,7 +30338,7 @@ pub fn svorr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30351,7 +30351,7 @@ pub fn svorr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30360,7 +30360,7 @@ pub fn svorr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30369,7 +30369,7 @@ pub fn svorr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30378,7 +30378,7 @@ pub fn svorr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30387,7 +30387,7 @@ pub fn svorr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30396,7 +30396,7 @@ pub fn svorr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30409,7 +30409,7 @@ pub fn svorr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30418,7 +30418,7 @@ pub fn svorr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30427,7 +30427,7 @@ pub fn svorr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30436,7 +30436,7 @@ pub fn svorr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30445,7 +30445,7 @@ pub fn svorr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30454,7 +30454,7 @@ pub fn svorr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30467,7 +30467,7 @@ pub fn svorr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30476,7 +30476,7 @@ pub fn svorr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30485,7 +30485,7 @@ pub fn svorr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30494,7 +30494,7 @@ pub fn svorr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30503,7 +30503,7 @@ pub fn svorr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30512,7 +30512,7 @@ pub fn svorr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30521,7 +30521,7 @@ pub fn svorr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30530,7 +30530,7 @@ pub fn svorr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30539,7 +30539,7 @@ pub fn svorr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30548,7 +30548,7 @@ pub fn svorr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30557,7 +30557,7 @@ pub fn svorr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30566,7 +30566,7 @@ pub fn svorr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30575,7 +30575,7 @@ pub fn svorr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30584,7 +30584,7 @@ pub fn svorr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30593,7 +30593,7 @@ pub fn svorr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30602,7 +30602,7 @@ pub fn svorr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30611,7 +30611,7 @@ pub fn svorr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30620,7 +30620,7 @@ pub fn svorr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30629,7 +30629,7 @@ pub fn svorr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30638,7 +30638,7 @@ pub fn svorr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30647,7 +30647,7 @@ pub fn svorr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30656,7 +30656,7 @@ pub fn svorr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30665,7 +30665,7 @@ pub fn svorr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30674,7 +30674,7 @@ pub fn svorr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30683,7 +30683,7 @@ pub fn svorr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30692,7 +30692,7 @@ pub fn svorr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30701,7 +30701,7 @@ pub fn svorr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30710,7 +30710,7 @@ pub fn svorr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30719,7 +30719,7 @@ pub fn svorr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Bitwise inclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orr))]
@@ -30728,7 +30728,7 @@ pub fn svorr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30741,7 +30741,7 @@ pub fn svorv_s8(pg: svbool_t, op: svint8_t) -> i8 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30754,7 +30754,7 @@ pub fn svorv_s16(pg: svbool_t, op: svint16_t) -> i16 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30767,7 +30767,7 @@ pub fn svorv_s32(pg: svbool_t, op: svint32_t) -> i32 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30780,7 +30780,7 @@ pub fn svorv_s64(pg: svbool_t, op: svint64_t) -> i64 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30789,7 +30789,7 @@ pub fn svorv_u8(pg: svbool_t, op: svuint8_t) -> u8 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30798,7 +30798,7 @@ pub fn svorv_u16(pg: svbool_t, op: svuint16_t) -> u16 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30807,7 +30807,7 @@ pub fn svorv_u32(pg: svbool_t, op: svuint32_t) -> u32 {
 }
 #[doc = "Bitwise inclusive OR reduction to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(orv))]
@@ -30816,7 +30816,7 @@ pub fn svorv_u64(pg: svbool_t, op: svuint64_t) -> u64 {
 }
 #[doc = "Set all predicate elements to false"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfalse[_b])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svpfalse_b() -> svbool_t {
@@ -30827,7 +30827,7 @@ pub fn svpfalse_b() -> svbool_t {
 }
 #[doc = "Set the first active predicate element to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfirst[_b])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pfirst))]
@@ -30840,7 +30840,7 @@ pub fn svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Find next active predicate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pnext))]
@@ -30853,7 +30853,7 @@ pub fn svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Find next active predicate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pnext))]
@@ -30866,7 +30866,7 @@ pub fn svpnext_b16(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Find next active predicate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pnext))]
@@ -30879,7 +30879,7 @@ pub fn svpnext_b32(pg: svbool_t, op: svbool_t) -> svbool_t {
 }
 #[doc = "Find next active predicate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pnext))]
@@ -30894,7 +30894,7 @@ pub fn svpnext_b64(pg: svbool_t, op: svbool_t) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -30909,7 +30909,7 @@ pub unsafe fn svprfb<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -30924,7 +30924,7 @@ pub unsafe fn svprfh<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -30939,7 +30939,7 @@ pub unsafe fn svprfw<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -30954,7 +30954,7 @@ pub unsafe fn svprfd<const OP: svprfop, T>(pg: svbool_t, base: *const T) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s32]offset)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -30986,7 +30986,7 @@ pub unsafe fn svprfb_gather_s32offset<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s32]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31018,7 +31018,7 @@ pub unsafe fn svprfh_gather_s32index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s32]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31050,7 +31050,7 @@ pub unsafe fn svprfw_gather_s32index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s32]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31082,7 +31082,7 @@ pub unsafe fn svprfd_gather_s32index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s64]offset)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31114,7 +31114,7 @@ pub unsafe fn svprfb_gather_s64offset<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s64]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31146,7 +31146,7 @@ pub unsafe fn svprfh_gather_s64index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s64]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31178,7 +31178,7 @@ pub unsafe fn svprfw_gather_s64index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s64]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31210,7 +31210,7 @@ pub unsafe fn svprfd_gather_s64index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u32]offset)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31242,7 +31242,7 @@ pub unsafe fn svprfb_gather_u32offset<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u32]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31274,7 +31274,7 @@ pub unsafe fn svprfh_gather_u32index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u32]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31306,7 +31306,7 @@ pub unsafe fn svprfw_gather_u32index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u32]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31338,7 +31338,7 @@ pub unsafe fn svprfd_gather_u32index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u64]offset)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31353,7 +31353,7 @@ pub unsafe fn svprfb_gather_u64offset<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u64]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31368,7 +31368,7 @@ pub unsafe fn svprfh_gather_u64index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u64]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31383,7 +31383,7 @@ pub unsafe fn svprfw_gather_u64index<const OP: svprfop, T>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u64]index)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31399,7 +31399,7 @@ pub unsafe fn svprfd_gather_u64index<const OP: svprfop, T>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31418,7 +31418,7 @@ pub unsafe fn svprfb_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31437,7 +31437,7 @@ pub unsafe fn svprfh_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31456,7 +31456,7 @@ pub unsafe fn svprfw_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31475,7 +31475,7 @@ pub unsafe fn svprfd_gather_u32base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31494,7 +31494,7 @@ pub unsafe fn svprfb_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31513,7 +31513,7 @@ pub unsafe fn svprfh_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31532,7 +31532,7 @@ pub unsafe fn svprfw_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31551,7 +31551,7 @@ pub unsafe fn svprfd_gather_u64base<const OP: svprfop>(pg: svbool_t, bases: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31574,7 +31574,7 @@ pub unsafe fn svprfb_gather_u32base_offset<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31597,7 +31597,7 @@ pub unsafe fn svprfh_gather_u32base_index<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31620,7 +31620,7 @@ pub unsafe fn svprfw_gather_u32base_index<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31643,7 +31643,7 @@ pub unsafe fn svprfd_gather_u32base_index<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31666,7 +31666,7 @@ pub unsafe fn svprfb_gather_u64base_offset<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31689,7 +31689,7 @@ pub unsafe fn svprfh_gather_u64base_index<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31712,7 +31712,7 @@ pub unsafe fn svprfw_gather_u64base_index<const OP: svprfop>(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))]
@@ -31734,7 +31734,7 @@ pub unsafe fn svprfd_gather_u64base_index<const OP: svprfop>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_vnum)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31745,7 +31745,7 @@ pub unsafe fn svprfb_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vn
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_vnum)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31756,7 +31756,7 @@ pub unsafe fn svprfh_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vn
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_vnum)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31767,7 +31767,7 @@ pub unsafe fn svprfw_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vn
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_vnum)"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))]
@@ -31776,7 +31776,7 @@ pub unsafe fn svprfd_vnum<const OP: svprfop, T>(pg: svbool_t, base: *const T, vn
 }
 #[doc = "Test whether any active element is true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_any)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptest))]
@@ -31792,7 +31792,7 @@ pub fn svptest_any(pg: svbool_t, op: svbool_t) -> bool {
 }
 #[doc = "Test whether first active element is true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_first)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptest))]
@@ -31808,7 +31808,7 @@ pub fn svptest_first(pg: svbool_t, op: svbool_t) -> bool {
 }
 #[doc = "Test whether last active element is true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_last)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptest))]
@@ -31824,7 +31824,7 @@ pub fn svptest_last(pg: svbool_t, op: svbool_t) -> bool {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptrue))]
@@ -31833,7 +31833,7 @@ pub fn svptrue_b8() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptrue))]
@@ -31842,7 +31842,7 @@ pub fn svptrue_b16() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptrue))]
@@ -31851,7 +31851,7 @@ pub fn svptrue_b32() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ptrue))]
@@ -31860,7 +31860,7 @@ pub fn svptrue_b64() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
@@ -31873,7 +31873,7 @@ pub fn svptrue_pat_b8<const PATTERN: svpattern>() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
@@ -31886,7 +31886,7 @@ pub fn svptrue_pat_b16<const PATTERN: svpattern>() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
@@ -31899,7 +31899,7 @@ pub fn svptrue_pat_b32<const PATTERN: svpattern>() -> svbool_t {
 }
 #[doc = "Set predicate elements to true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))]
@@ -31912,7 +31912,7 @@ pub fn svptrue_pat_b64<const PATTERN: svpattern>() -> svbool_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -31928,7 +31928,7 @@ pub fn svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -31937,7 +31937,7 @@ pub fn svqadd_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -31953,7 +31953,7 @@ pub fn svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -31962,7 +31962,7 @@ pub fn svqadd_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -31978,7 +31978,7 @@ pub fn svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -31987,7 +31987,7 @@ pub fn svqadd_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -32003,7 +32003,7 @@ pub fn svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -32012,7 +32012,7 @@ pub fn svqadd_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32028,7 +32028,7 @@ pub fn svqadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32037,7 +32037,7 @@ pub fn svqadd_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32053,7 +32053,7 @@ pub fn svqadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32062,7 +32062,7 @@ pub fn svqadd_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32078,7 +32078,7 @@ pub fn svqadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32087,7 +32087,7 @@ pub fn svqadd_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32103,7 +32103,7 @@ pub fn svqadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -32112,7 +32112,7 @@ pub fn svqadd_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))]
@@ -32121,7 +32121,7 @@ pub fn svqdecb_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))]
@@ -32130,7 +32130,7 @@ pub fn svqdech_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))]
@@ -32139,7 +32139,7 @@ pub fn svqdecw_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))]
@@ -32148,7 +32148,7 @@ pub fn svqdecd_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))]
@@ -32157,7 +32157,7 @@ pub fn svqdecb_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))]
@@ -32166,7 +32166,7 @@ pub fn svqdech_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))]
@@ -32175,7 +32175,7 @@ pub fn svqdecw_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))]
@@ -32184,7 +32184,7 @@ pub fn svqdecd_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))]
@@ -32193,7 +32193,7 @@ pub fn svqdecb_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))]
@@ -32202,7 +32202,7 @@ pub fn svqdech_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))]
@@ -32211,7 +32211,7 @@ pub fn svqdecw_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))]
@@ -32220,7 +32220,7 @@ pub fn svqdecd_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))]
@@ -32229,7 +32229,7 @@ pub fn svqdecb_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))]
@@ -32238,7 +32238,7 @@ pub fn svqdech_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))]
@@ -32247,7 +32247,7 @@ pub fn svqdecw_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))]
@@ -32256,7 +32256,7 @@ pub fn svqdecd_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32270,7 +32270,7 @@ pub fn svqdecb_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32284,7 +32284,7 @@ pub fn svqdech_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32298,7 +32298,7 @@ pub fn svqdecw_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32312,7 +32312,7 @@ pub fn svqdecd_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32326,7 +32326,7 @@ pub fn svqdecb_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32340,7 +32340,7 @@ pub fn svqdech_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32354,7 +32354,7 @@ pub fn svqdecw_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32368,7 +32368,7 @@ pub fn svqdecd_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32382,7 +32382,7 @@ pub fn svqdecb_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32396,7 +32396,7 @@ pub fn svqdech_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32410,7 +32410,7 @@ pub fn svqdecw_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32424,7 +32424,7 @@ pub fn svqdecd_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating decrement by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32438,7 +32438,7 @@ pub fn svqdecb_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32452,7 +32452,7 @@ pub fn svqdech_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32466,7 +32466,7 @@ pub fn svqdecw_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32480,7 +32480,7 @@ pub fn svqdecd_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32496,7 +32496,7 @@ pub fn svqdech_pat_s16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32512,7 +32512,7 @@ pub fn svqdecw_pat_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32528,7 +32528,7 @@ pub fn svqdecd_pat_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32544,7 +32544,7 @@ pub fn svqdech_pat_u16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32560,7 +32560,7 @@ pub fn svqdecw_pat_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -32576,7 +32576,7 @@ pub fn svqdecd_pat_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))]
@@ -32585,7 +32585,7 @@ pub fn svqdech_s16<const IMM_FACTOR: i32>(op: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))]
@@ -32594,7 +32594,7 @@ pub fn svqdecw_s32<const IMM_FACTOR: i32>(op: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))]
@@ -32603,7 +32603,7 @@ pub fn svqdecd_s64<const IMM_FACTOR: i32>(op: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating decrement by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))]
@@ -32612,7 +32612,7 @@ pub fn svqdech_u16<const IMM_FACTOR: i32>(op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Saturating decrement by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))]
@@ -32621,7 +32621,7 @@ pub fn svqdecw_u32<const IMM_FACTOR: i32>(op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Saturating decrement by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))]
@@ -32630,7 +32630,7 @@ pub fn svqdecd_u64<const IMM_FACTOR: i32>(op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32646,7 +32646,7 @@ pub fn svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32662,7 +32662,7 @@ pub fn svqdecp_n_s32_b16(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32678,7 +32678,7 @@ pub fn svqdecp_n_s32_b32(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32694,7 +32694,7 @@ pub fn svqdecp_n_s32_b64(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32710,7 +32710,7 @@ pub fn svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32726,7 +32726,7 @@ pub fn svqdecp_n_s64_b16(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32742,7 +32742,7 @@ pub fn svqdecp_n_s64_b32(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32758,7 +32758,7 @@ pub fn svqdecp_n_s64_b64(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32774,7 +32774,7 @@ pub fn svqdecp_n_u32_b8(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32790,7 +32790,7 @@ pub fn svqdecp_n_u32_b16(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32806,7 +32806,7 @@ pub fn svqdecp_n_u32_b32(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32822,7 +32822,7 @@ pub fn svqdecp_n_u32_b64(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32838,7 +32838,7 @@ pub fn svqdecp_n_u64_b8(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32854,7 +32854,7 @@ pub fn svqdecp_n_u64_b16(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32870,7 +32870,7 @@ pub fn svqdecp_n_u64_b32(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32886,7 +32886,7 @@ pub fn svqdecp_n_u64_b64(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32899,7 +32899,7 @@ pub fn svqdecp_s16(op: svint16_t, pg: svbool_t) -> svint16_t {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32912,7 +32912,7 @@ pub fn svqdecp_s32(op: svint32_t, pg: svbool_t) -> svint32_t {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdecp))]
@@ -32925,7 +32925,7 @@ pub fn svqdecp_s64(op: svint64_t, pg: svbool_t) -> svint64_t {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32938,7 +32938,7 @@ pub fn svqdecp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32951,7 +32951,7 @@ pub fn svqdecp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t {
 }
 #[doc = "Saturating decrement by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqdecp))]
@@ -32964,7 +32964,7 @@ pub fn svqdecp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t {
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))]
@@ -32973,7 +32973,7 @@ pub fn svqincb_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))]
@@ -32982,7 +32982,7 @@ pub fn svqinch_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))]
@@ -32991,7 +32991,7 @@ pub fn svqincw_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))]
@@ -33000,7 +33000,7 @@ pub fn svqincd_n_s32<const IMM_FACTOR: i32>(op: i32) -> i32 {
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))]
@@ -33009,7 +33009,7 @@ pub fn svqincb_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))]
@@ -33018,7 +33018,7 @@ pub fn svqinch_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))]
@@ -33027,7 +33027,7 @@ pub fn svqincw_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))]
@@ -33036,7 +33036,7 @@ pub fn svqincd_n_s64<const IMM_FACTOR: i32>(op: i64) -> i64 {
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))]
@@ -33045,7 +33045,7 @@ pub fn svqincb_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))]
@@ -33054,7 +33054,7 @@ pub fn svqinch_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))]
@@ -33063,7 +33063,7 @@ pub fn svqincw_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))]
@@ -33072,7 +33072,7 @@ pub fn svqincd_n_u32<const IMM_FACTOR: i32>(op: u32) -> u32 {
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))]
@@ -33081,7 +33081,7 @@ pub fn svqincb_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))]
@@ -33090,7 +33090,7 @@ pub fn svqinch_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))]
@@ -33099,7 +33099,7 @@ pub fn svqincw_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))]
@@ -33108,7 +33108,7 @@ pub fn svqincd_n_u64<const IMM_FACTOR: i32>(op: u64) -> u64 {
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33122,7 +33122,7 @@ pub fn svqincb_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33136,7 +33136,7 @@ pub fn svqinch_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33150,7 +33150,7 @@ pub fn svqincw_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33164,7 +33164,7 @@ pub fn svqincd_pat_n_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i3
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33178,7 +33178,7 @@ pub fn svqincb_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33192,7 +33192,7 @@ pub fn svqinch_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33206,7 +33206,7 @@ pub fn svqincw_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33220,7 +33220,7 @@ pub fn svqincd_pat_n_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: i6
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33234,7 +33234,7 @@ pub fn svqincb_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33248,7 +33248,7 @@ pub fn svqinch_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33262,7 +33262,7 @@ pub fn svqincw_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33276,7 +33276,7 @@ pub fn svqincd_pat_n_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u3
 }
 #[doc = "Saturating increment by number of byte elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33290,7 +33290,7 @@ pub fn svqincb_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33304,7 +33304,7 @@ pub fn svqinch_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33318,7 +33318,7 @@ pub fn svqincw_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33332,7 +33332,7 @@ pub fn svqincd_pat_n_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(op: u6
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33348,7 +33348,7 @@ pub fn svqinch_pat_s16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33364,7 +33364,7 @@ pub fn svqincw_pat_s32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33380,7 +33380,7 @@ pub fn svqincd_pat_s64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33396,7 +33396,7 @@ pub fn svqinch_pat_u16<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33412,7 +33412,7 @@ pub fn svqincw_pat_u32<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 # [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))]
@@ -33428,7 +33428,7 @@ pub fn svqincd_pat_u64<const PATTERN: svpattern, const IMM_FACTOR: i32>(
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))]
@@ -33437,7 +33437,7 @@ pub fn svqinch_s16<const IMM_FACTOR: i32>(op: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))]
@@ -33446,7 +33446,7 @@ pub fn svqincw_s32<const IMM_FACTOR: i32>(op: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))]
@@ -33455,7 +33455,7 @@ pub fn svqincd_s64<const IMM_FACTOR: i32>(op: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating increment by number of halfword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))]
@@ -33464,7 +33464,7 @@ pub fn svqinch_u16<const IMM_FACTOR: i32>(op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Saturating increment by number of word elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))]
@@ -33473,7 +33473,7 @@ pub fn svqincw_u32<const IMM_FACTOR: i32>(op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Saturating increment by number of doubleword elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))]
@@ -33482,7 +33482,7 @@ pub fn svqincd_u64<const IMM_FACTOR: i32>(op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33498,7 +33498,7 @@ pub fn svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33514,7 +33514,7 @@ pub fn svqincp_n_s32_b16(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33530,7 +33530,7 @@ pub fn svqincp_n_s32_b32(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33546,7 +33546,7 @@ pub fn svqincp_n_s32_b64(op: i32, pg: svbool_t) -> i32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33562,7 +33562,7 @@ pub fn svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33578,7 +33578,7 @@ pub fn svqincp_n_s64_b16(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33594,7 +33594,7 @@ pub fn svqincp_n_s64_b32(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33610,7 +33610,7 @@ pub fn svqincp_n_s64_b64(op: i64, pg: svbool_t) -> i64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33626,7 +33626,7 @@ pub fn svqincp_n_u32_b8(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33642,7 +33642,7 @@ pub fn svqincp_n_u32_b16(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33658,7 +33658,7 @@ pub fn svqincp_n_u32_b32(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33674,7 +33674,7 @@ pub fn svqincp_n_u32_b64(op: u32, pg: svbool_t) -> u32 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33690,7 +33690,7 @@ pub fn svqincp_n_u64_b8(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33706,7 +33706,7 @@ pub fn svqincp_n_u64_b16(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33722,7 +33722,7 @@ pub fn svqincp_n_u64_b32(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33738,7 +33738,7 @@ pub fn svqincp_n_u64_b64(op: u64, pg: svbool_t) -> u64 {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33751,7 +33751,7 @@ pub fn svqincp_s16(op: svint16_t, pg: svbool_t) -> svint16_t {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33764,7 +33764,7 @@ pub fn svqincp_s32(op: svint32_t, pg: svbool_t) -> svint32_t {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqincp))]
@@ -33777,7 +33777,7 @@ pub fn svqincp_s64(op: svint64_t, pg: svbool_t) -> svint64_t {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33790,7 +33790,7 @@ pub fn svqincp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33803,7 +33803,7 @@ pub fn svqincp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t {
 }
 #[doc = "Saturating increment by active element count"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqincp))]
@@ -33816,7 +33816,7 @@ pub fn svqincp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33832,7 +33832,7 @@ pub fn svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33841,7 +33841,7 @@ pub fn svqsub_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33857,7 +33857,7 @@ pub fn svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33866,7 +33866,7 @@ pub fn svqsub_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33882,7 +33882,7 @@ pub fn svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33891,7 +33891,7 @@ pub fn svqsub_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33907,7 +33907,7 @@ pub fn svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -33916,7 +33916,7 @@ pub fn svqsub_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -33932,7 +33932,7 @@ pub fn svqsub_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -33941,7 +33941,7 @@ pub fn svqsub_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -33957,7 +33957,7 @@ pub fn svqsub_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -33966,7 +33966,7 @@ pub fn svqsub_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -33982,7 +33982,7 @@ pub fn svqsub_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -33991,7 +33991,7 @@ pub fn svqsub_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -34007,7 +34007,7 @@ pub fn svqsub_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -34016,7 +34016,7 @@ pub fn svqsub_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34029,7 +34029,7 @@ pub fn svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34038,7 +34038,7 @@ pub fn svrbit_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34047,7 +34047,7 @@ pub fn svrbit_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34060,7 +34060,7 @@ pub fn svrbit_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34069,7 +34069,7 @@ pub fn svrbit_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34078,7 +34078,7 @@ pub fn svrbit_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34091,7 +34091,7 @@ pub fn svrbit_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34100,7 +34100,7 @@ pub fn svrbit_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34109,7 +34109,7 @@ pub fn svrbit_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34122,7 +34122,7 @@ pub fn svrbit_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34131,7 +34131,7 @@ pub fn svrbit_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34140,7 +34140,7 @@ pub fn svrbit_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34149,7 +34149,7 @@ pub fn svrbit_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34158,7 +34158,7 @@ pub fn svrbit_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34167,7 +34167,7 @@ pub fn svrbit_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34176,7 +34176,7 @@ pub fn svrbit_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuin
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34185,7 +34185,7 @@ pub fn svrbit_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34194,7 +34194,7 @@ pub fn svrbit_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34203,7 +34203,7 @@ pub fn svrbit_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuin
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34212,7 +34212,7 @@ pub fn svrbit_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34221,7 +34221,7 @@ pub fn svrbit_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34230,7 +34230,7 @@ pub fn svrbit_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34239,7 +34239,7 @@ pub fn svrbit_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -34248,7 +34248,7 @@ pub fn svrbit_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Read FFR, returning predicate of succesfully loaded elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rdffr))]
@@ -34257,7 +34257,7 @@ pub fn svrdffr() -> svbool_t {
 }
 #[doc = "Read FFR, returning predicate of succesfully loaded elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rdffr))]
@@ -34270,7 +34270,7 @@ pub fn svrdffr_z(pg: svbool_t) -> svbool_t {
 }
 #[doc = "Reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpe))]
@@ -34286,7 +34286,7 @@ pub fn svrecpe_f32(op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpe))]
@@ -34302,7 +34302,7 @@ pub fn svrecpe_f64(op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecps))]
@@ -34318,7 +34318,7 @@ pub fn svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecps))]
@@ -34334,7 +34334,7 @@ pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpx))]
@@ -34350,7 +34350,7 @@ pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpx))]
@@ -34359,7 +34359,7 @@ pub fn svrecpx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpx))]
@@ -34368,7 +34368,7 @@ pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpx))]
@@ -34384,7 +34384,7 @@ pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpx))]
@@ -34393,7 +34393,7 @@ pub fn svrecpx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frecpx))]
@@ -34402,7 +34402,7 @@ pub fn svrecpx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_f32(op: svfloat32_t) -> svfloat32_t {
@@ -34410,7 +34410,7 @@ pub fn svreinterpret_f32_f32(op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_f64(op: svfloat64_t) -> svfloat32_t {
@@ -34418,7 +34418,7 @@ pub fn svreinterpret_f32_f64(op: svfloat64_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_s8(op: svint8_t) -> svfloat32_t {
@@ -34426,7 +34426,7 @@ pub fn svreinterpret_f32_s8(op: svint8_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_s16(op: svint16_t) -> svfloat32_t {
@@ -34434,7 +34434,7 @@ pub fn svreinterpret_f32_s16(op: svint16_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_s32(op: svint32_t) -> svfloat32_t {
@@ -34442,7 +34442,7 @@ pub fn svreinterpret_f32_s32(op: svint32_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_s64(op: svint64_t) -> svfloat32_t {
@@ -34450,7 +34450,7 @@ pub fn svreinterpret_f32_s64(op: svint64_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_u8(op: svuint8_t) -> svfloat32_t {
@@ -34458,7 +34458,7 @@ pub fn svreinterpret_f32_u8(op: svuint8_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_u16(op: svuint16_t) -> svfloat32_t {
@@ -34466,7 +34466,7 @@ pub fn svreinterpret_f32_u16(op: svuint16_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_u32(op: svuint32_t) -> svfloat32_t {
@@ -34474,7 +34474,7 @@ pub fn svreinterpret_f32_u32(op: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f32_u64(op: svuint64_t) -> svfloat32_t {
@@ -34482,7 +34482,7 @@ pub fn svreinterpret_f32_u64(op: svuint64_t) -> svfloat32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_f32(op: svfloat32_t) -> svfloat64_t {
@@ -34490,7 +34490,7 @@ pub fn svreinterpret_f64_f32(op: svfloat32_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_f64(op: svfloat64_t) -> svfloat64_t {
@@ -34498,7 +34498,7 @@ pub fn svreinterpret_f64_f64(op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_s8(op: svint8_t) -> svfloat64_t {
@@ -34506,7 +34506,7 @@ pub fn svreinterpret_f64_s8(op: svint8_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_s16(op: svint16_t) -> svfloat64_t {
@@ -34514,7 +34514,7 @@ pub fn svreinterpret_f64_s16(op: svint16_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_s32(op: svint32_t) -> svfloat64_t {
@@ -34522,7 +34522,7 @@ pub fn svreinterpret_f64_s32(op: svint32_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_s64(op: svint64_t) -> svfloat64_t {
@@ -34530,7 +34530,7 @@ pub fn svreinterpret_f64_s64(op: svint64_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_u8(op: svuint8_t) -> svfloat64_t {
@@ -34538,7 +34538,7 @@ pub fn svreinterpret_f64_u8(op: svuint8_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_u16(op: svuint16_t) -> svfloat64_t {
@@ -34546,7 +34546,7 @@ pub fn svreinterpret_f64_u16(op: svuint16_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_u32(op: svuint32_t) -> svfloat64_t {
@@ -34554,7 +34554,7 @@ pub fn svreinterpret_f64_u32(op: svuint32_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_f64_u64(op: svuint64_t) -> svfloat64_t {
@@ -34562,7 +34562,7 @@ pub fn svreinterpret_f64_u64(op: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_f32(op: svfloat32_t) -> svint8_t {
@@ -34570,7 +34570,7 @@ pub fn svreinterpret_s8_f32(op: svfloat32_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_f64(op: svfloat64_t) -> svint8_t {
@@ -34578,7 +34578,7 @@ pub fn svreinterpret_s8_f64(op: svfloat64_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_s8(op: svint8_t) -> svint8_t {
@@ -34586,7 +34586,7 @@ pub fn svreinterpret_s8_s8(op: svint8_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_s16(op: svint16_t) -> svint8_t {
@@ -34594,7 +34594,7 @@ pub fn svreinterpret_s8_s16(op: svint16_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_s32(op: svint32_t) -> svint8_t {
@@ -34602,7 +34602,7 @@ pub fn svreinterpret_s8_s32(op: svint32_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_s64(op: svint64_t) -> svint8_t {
@@ -34610,7 +34610,7 @@ pub fn svreinterpret_s8_s64(op: svint64_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_u8(op: svuint8_t) -> svint8_t {
@@ -34618,7 +34618,7 @@ pub fn svreinterpret_s8_u8(op: svuint8_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_u16(op: svuint16_t) -> svint8_t {
@@ -34626,7 +34626,7 @@ pub fn svreinterpret_s8_u16(op: svuint16_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_u32(op: svuint32_t) -> svint8_t {
@@ -34634,7 +34634,7 @@ pub fn svreinterpret_s8_u32(op: svuint32_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s8_u64(op: svuint64_t) -> svint8_t {
@@ -34642,7 +34642,7 @@ pub fn svreinterpret_s8_u64(op: svuint64_t) -> svint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_f32(op: svfloat32_t) -> svint16_t {
@@ -34650,7 +34650,7 @@ pub fn svreinterpret_s16_f32(op: svfloat32_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_f64(op: svfloat64_t) -> svint16_t {
@@ -34658,7 +34658,7 @@ pub fn svreinterpret_s16_f64(op: svfloat64_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_s8(op: svint8_t) -> svint16_t {
@@ -34666,7 +34666,7 @@ pub fn svreinterpret_s16_s8(op: svint8_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_s16(op: svint16_t) -> svint16_t {
@@ -34674,7 +34674,7 @@ pub fn svreinterpret_s16_s16(op: svint16_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_s32(op: svint32_t) -> svint16_t {
@@ -34682,7 +34682,7 @@ pub fn svreinterpret_s16_s32(op: svint32_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_s64(op: svint64_t) -> svint16_t {
@@ -34690,7 +34690,7 @@ pub fn svreinterpret_s16_s64(op: svint64_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_u8(op: svuint8_t) -> svint16_t {
@@ -34698,7 +34698,7 @@ pub fn svreinterpret_s16_u8(op: svuint8_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_u16(op: svuint16_t) -> svint16_t {
@@ -34706,7 +34706,7 @@ pub fn svreinterpret_s16_u16(op: svuint16_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_u32(op: svuint32_t) -> svint16_t {
@@ -34714,7 +34714,7 @@ pub fn svreinterpret_s16_u32(op: svuint32_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s16_u64(op: svuint64_t) -> svint16_t {
@@ -34722,7 +34722,7 @@ pub fn svreinterpret_s16_u64(op: svuint64_t) -> svint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_f32(op: svfloat32_t) -> svint32_t {
@@ -34730,7 +34730,7 @@ pub fn svreinterpret_s32_f32(op: svfloat32_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_f64(op: svfloat64_t) -> svint32_t {
@@ -34738,7 +34738,7 @@ pub fn svreinterpret_s32_f64(op: svfloat64_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_s8(op: svint8_t) -> svint32_t {
@@ -34746,7 +34746,7 @@ pub fn svreinterpret_s32_s8(op: svint8_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_s16(op: svint16_t) -> svint32_t {
@@ -34754,7 +34754,7 @@ pub fn svreinterpret_s32_s16(op: svint16_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_s32(op: svint32_t) -> svint32_t {
@@ -34762,7 +34762,7 @@ pub fn svreinterpret_s32_s32(op: svint32_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_s64(op: svint64_t) -> svint32_t {
@@ -34770,7 +34770,7 @@ pub fn svreinterpret_s32_s64(op: svint64_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_u8(op: svuint8_t) -> svint32_t {
@@ -34778,7 +34778,7 @@ pub fn svreinterpret_s32_u8(op: svuint8_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_u16(op: svuint16_t) -> svint32_t {
@@ -34786,7 +34786,7 @@ pub fn svreinterpret_s32_u16(op: svuint16_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_u32(op: svuint32_t) -> svint32_t {
@@ -34794,7 +34794,7 @@ pub fn svreinterpret_s32_u32(op: svuint32_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s32_u64(op: svuint64_t) -> svint32_t {
@@ -34802,7 +34802,7 @@ pub fn svreinterpret_s32_u64(op: svuint64_t) -> svint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_f32(op: svfloat32_t) -> svint64_t {
@@ -34810,7 +34810,7 @@ pub fn svreinterpret_s64_f32(op: svfloat32_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_f64(op: svfloat64_t) -> svint64_t {
@@ -34818,7 +34818,7 @@ pub fn svreinterpret_s64_f64(op: svfloat64_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_s8(op: svint8_t) -> svint64_t {
@@ -34826,7 +34826,7 @@ pub fn svreinterpret_s64_s8(op: svint8_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_s16(op: svint16_t) -> svint64_t {
@@ -34834,7 +34834,7 @@ pub fn svreinterpret_s64_s16(op: svint16_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_s32(op: svint32_t) -> svint64_t {
@@ -34842,7 +34842,7 @@ pub fn svreinterpret_s64_s32(op: svint32_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_s64(op: svint64_t) -> svint64_t {
@@ -34850,7 +34850,7 @@ pub fn svreinterpret_s64_s64(op: svint64_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_u8(op: svuint8_t) -> svint64_t {
@@ -34858,7 +34858,7 @@ pub fn svreinterpret_s64_u8(op: svuint8_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_u16(op: svuint16_t) -> svint64_t {
@@ -34866,7 +34866,7 @@ pub fn svreinterpret_s64_u16(op: svuint16_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_u32(op: svuint32_t) -> svint64_t {
@@ -34874,7 +34874,7 @@ pub fn svreinterpret_s64_u32(op: svuint32_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_s64_u64(op: svuint64_t) -> svint64_t {
@@ -34882,7 +34882,7 @@ pub fn svreinterpret_s64_u64(op: svuint64_t) -> svint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_f32(op: svfloat32_t) -> svuint8_t {
@@ -34890,7 +34890,7 @@ pub fn svreinterpret_u8_f32(op: svfloat32_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_f64(op: svfloat64_t) -> svuint8_t {
@@ -34898,7 +34898,7 @@ pub fn svreinterpret_u8_f64(op: svfloat64_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_s8(op: svint8_t) -> svuint8_t {
@@ -34906,7 +34906,7 @@ pub fn svreinterpret_u8_s8(op: svint8_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_s16(op: svint16_t) -> svuint8_t {
@@ -34914,7 +34914,7 @@ pub fn svreinterpret_u8_s16(op: svint16_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_s32(op: svint32_t) -> svuint8_t {
@@ -34922,7 +34922,7 @@ pub fn svreinterpret_u8_s32(op: svint32_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_s64(op: svint64_t) -> svuint8_t {
@@ -34930,7 +34930,7 @@ pub fn svreinterpret_u8_s64(op: svint64_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_u8(op: svuint8_t) -> svuint8_t {
@@ -34938,7 +34938,7 @@ pub fn svreinterpret_u8_u8(op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_u16(op: svuint16_t) -> svuint8_t {
@@ -34946,7 +34946,7 @@ pub fn svreinterpret_u8_u16(op: svuint16_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_u32(op: svuint32_t) -> svuint8_t {
@@ -34954,7 +34954,7 @@ pub fn svreinterpret_u8_u32(op: svuint32_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u8_u64(op: svuint64_t) -> svuint8_t {
@@ -34962,7 +34962,7 @@ pub fn svreinterpret_u8_u64(op: svuint64_t) -> svuint8_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_f32(op: svfloat32_t) -> svuint16_t {
@@ -34970,7 +34970,7 @@ pub fn svreinterpret_u16_f32(op: svfloat32_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_f64(op: svfloat64_t) -> svuint16_t {
@@ -34978,7 +34978,7 @@ pub fn svreinterpret_u16_f64(op: svfloat64_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_s8(op: svint8_t) -> svuint16_t {
@@ -34986,7 +34986,7 @@ pub fn svreinterpret_u16_s8(op: svint8_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_s16(op: svint16_t) -> svuint16_t {
@@ -34994,7 +34994,7 @@ pub fn svreinterpret_u16_s16(op: svint16_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_s32(op: svint32_t) -> svuint16_t {
@@ -35002,7 +35002,7 @@ pub fn svreinterpret_u16_s32(op: svint32_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_s64(op: svint64_t) -> svuint16_t {
@@ -35010,7 +35010,7 @@ pub fn svreinterpret_u16_s64(op: svint64_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_u8(op: svuint8_t) -> svuint16_t {
@@ -35018,7 +35018,7 @@ pub fn svreinterpret_u16_u8(op: svuint8_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_u16(op: svuint16_t) -> svuint16_t {
@@ -35026,7 +35026,7 @@ pub fn svreinterpret_u16_u16(op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_u32(op: svuint32_t) -> svuint16_t {
@@ -35034,7 +35034,7 @@ pub fn svreinterpret_u16_u32(op: svuint32_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u16_u64(op: svuint64_t) -> svuint16_t {
@@ -35042,7 +35042,7 @@ pub fn svreinterpret_u16_u64(op: svuint64_t) -> svuint16_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_f32(op: svfloat32_t) -> svuint32_t {
@@ -35050,7 +35050,7 @@ pub fn svreinterpret_u32_f32(op: svfloat32_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_f64(op: svfloat64_t) -> svuint32_t {
@@ -35058,7 +35058,7 @@ pub fn svreinterpret_u32_f64(op: svfloat64_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_s8(op: svint8_t) -> svuint32_t {
@@ -35066,7 +35066,7 @@ pub fn svreinterpret_u32_s8(op: svint8_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_s16(op: svint16_t) -> svuint32_t {
@@ -35074,7 +35074,7 @@ pub fn svreinterpret_u32_s16(op: svint16_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_s32(op: svint32_t) -> svuint32_t {
@@ -35082,7 +35082,7 @@ pub fn svreinterpret_u32_s32(op: svint32_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_s64(op: svint64_t) -> svuint32_t {
@@ -35090,7 +35090,7 @@ pub fn svreinterpret_u32_s64(op: svint64_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_u8(op: svuint8_t) -> svuint32_t {
@@ -35098,7 +35098,7 @@ pub fn svreinterpret_u32_u8(op: svuint8_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_u16(op: svuint16_t) -> svuint32_t {
@@ -35106,7 +35106,7 @@ pub fn svreinterpret_u32_u16(op: svuint16_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_u32(op: svuint32_t) -> svuint32_t {
@@ -35114,7 +35114,7 @@ pub fn svreinterpret_u32_u32(op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u32_u64(op: svuint64_t) -> svuint32_t {
@@ -35122,7 +35122,7 @@ pub fn svreinterpret_u32_u64(op: svuint64_t) -> svuint32_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_f32(op: svfloat32_t) -> svuint64_t {
@@ -35130,7 +35130,7 @@ pub fn svreinterpret_u64_f32(op: svfloat32_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_f64(op: svfloat64_t) -> svuint64_t {
@@ -35138,7 +35138,7 @@ pub fn svreinterpret_u64_f64(op: svfloat64_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_s8(op: svint8_t) -> svuint64_t {
@@ -35146,7 +35146,7 @@ pub fn svreinterpret_u64_s8(op: svint8_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_s16(op: svint16_t) -> svuint64_t {
@@ -35154,7 +35154,7 @@ pub fn svreinterpret_u64_s16(op: svint16_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_s32(op: svint32_t) -> svuint64_t {
@@ -35162,7 +35162,7 @@ pub fn svreinterpret_u64_s32(op: svint32_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_s64(op: svint64_t) -> svuint64_t {
@@ -35170,7 +35170,7 @@ pub fn svreinterpret_u64_s64(op: svint64_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_u8(op: svuint8_t) -> svuint64_t {
@@ -35178,7 +35178,7 @@ pub fn svreinterpret_u64_u8(op: svuint8_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_u16(op: svuint16_t) -> svuint64_t {
@@ -35186,7 +35186,7 @@ pub fn svreinterpret_u64_u16(op: svuint16_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_u32(op: svuint32_t) -> svuint64_t {
@@ -35194,7 +35194,7 @@ pub fn svreinterpret_u64_u32(op: svuint32_t) -> svuint64_t {
 }
 #[doc = "Reinterpret vector contents"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t {
@@ -35202,7 +35202,7 @@ pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35215,7 +35215,7 @@ pub fn svrev_b8(op: svbool_t) -> svbool_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35228,7 +35228,7 @@ pub fn svrev_b16(op: svbool_t) -> svbool_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35241,7 +35241,7 @@ pub fn svrev_b32(op: svbool_t) -> svbool_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35254,7 +35254,7 @@ pub fn svrev_b64(op: svbool_t) -> svbool_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35267,7 +35267,7 @@ pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35280,7 +35280,7 @@ pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35293,7 +35293,7 @@ pub fn svrev_s8(op: svint8_t) -> svint8_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35306,7 +35306,7 @@ pub fn svrev_s16(op: svint16_t) -> svint16_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35319,7 +35319,7 @@ pub fn svrev_s32(op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35332,7 +35332,7 @@ pub fn svrev_s64(op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35341,7 +35341,7 @@ pub fn svrev_u8(op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35350,7 +35350,7 @@ pub fn svrev_u16(op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35359,7 +35359,7 @@ pub fn svrev_u32(op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse all elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rev))]
@@ -35368,7 +35368,7 @@ pub fn svrev_u64(op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35381,7 +35381,7 @@ pub fn svrevb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35390,7 +35390,7 @@ pub fn svrevb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35399,7 +35399,7 @@ pub fn svrevb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35412,7 +35412,7 @@ pub fn svrevb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35421,7 +35421,7 @@ pub fn svrevb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35430,7 +35430,7 @@ pub fn svrevb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35443,7 +35443,7 @@ pub fn svrevb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35452,7 +35452,7 @@ pub fn svrevb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35461,7 +35461,7 @@ pub fn svrevb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35470,7 +35470,7 @@ pub fn svrevb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuin
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35479,7 +35479,7 @@ pub fn svrevb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35488,7 +35488,7 @@ pub fn svrevb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35497,7 +35497,7 @@ pub fn svrevb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuin
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35506,7 +35506,7 @@ pub fn svrevb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35515,7 +35515,7 @@ pub fn svrevb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35524,7 +35524,7 @@ pub fn svrevb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35533,7 +35533,7 @@ pub fn svrevb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse bytes within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revb))]
@@ -35542,7 +35542,7 @@ pub fn svrevb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35555,7 +35555,7 @@ pub fn svrevh_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35564,7 +35564,7 @@ pub fn svrevh_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35573,7 +35573,7 @@ pub fn svrevh_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35586,7 +35586,7 @@ pub fn svrevh_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35595,7 +35595,7 @@ pub fn svrevh_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35604,7 +35604,7 @@ pub fn svrevh_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35613,7 +35613,7 @@ pub fn svrevh_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuin
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35622,7 +35622,7 @@ pub fn svrevh_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35631,7 +35631,7 @@ pub fn svrevh_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35640,7 +35640,7 @@ pub fn svrevh_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35649,7 +35649,7 @@ pub fn svrevh_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse halfwords within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revh))]
@@ -35658,7 +35658,7 @@ pub fn svrevh_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse words within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revw))]
@@ -35671,7 +35671,7 @@ pub fn svrevw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Reverse words within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revw))]
@@ -35680,7 +35680,7 @@ pub fn svrevw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse words within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revw))]
@@ -35689,7 +35689,7 @@ pub fn svrevw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Reverse words within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revw))]
@@ -35698,7 +35698,7 @@ pub fn svrevw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuin
 }
 #[doc = "Reverse words within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revw))]
@@ -35707,7 +35707,7 @@ pub fn svrevw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reverse words within elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(revw))]
@@ -35716,7 +35716,7 @@ pub fn svrevw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t {
 }
 #[doc = "Round to nearest, ties away from zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -35729,7 +35729,7 @@ pub fn svrinta_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round to nearest, ties away from zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -35738,7 +35738,7 @@ pub fn svrinta_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round to nearest, ties away from zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -35747,7 +35747,7 @@ pub fn svrinta_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round to nearest, ties away from zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -35760,7 +35760,7 @@ pub fn svrinta_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round to nearest, ties away from zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -35769,7 +35769,7 @@ pub fn svrinta_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round to nearest, ties away from zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -35778,7 +35778,7 @@ pub fn svrinta_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round using current rounding mode (inexact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -35791,7 +35791,7 @@ pub fn svrinti_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round using current rounding mode (inexact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -35800,7 +35800,7 @@ pub fn svrinti_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round using current rounding mode (inexact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -35809,7 +35809,7 @@ pub fn svrinti_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round using current rounding mode (inexact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -35822,7 +35822,7 @@ pub fn svrinti_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round using current rounding mode (inexact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -35831,7 +35831,7 @@ pub fn svrinti_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round using current rounding mode (inexact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -35840,7 +35840,7 @@ pub fn svrinti_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round towards -∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -35853,7 +35853,7 @@ pub fn svrintm_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round towards -∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -35862,7 +35862,7 @@ pub fn svrintm_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round towards -∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -35871,7 +35871,7 @@ pub fn svrintm_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round towards -∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -35884,7 +35884,7 @@ pub fn svrintm_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round towards -∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -35893,7 +35893,7 @@ pub fn svrintm_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round towards -∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -35902,7 +35902,7 @@ pub fn svrintm_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round to nearest, ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -35915,7 +35915,7 @@ pub fn svrintn_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round to nearest, ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -35924,7 +35924,7 @@ pub fn svrintn_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round to nearest, ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -35933,7 +35933,7 @@ pub fn svrintn_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round to nearest, ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -35946,7 +35946,7 @@ pub fn svrintn_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round to nearest, ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -35955,7 +35955,7 @@ pub fn svrintn_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round to nearest, ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -35964,7 +35964,7 @@ pub fn svrintn_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round towards +∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -35977,7 +35977,7 @@ pub fn svrintp_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round towards +∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -35986,7 +35986,7 @@ pub fn svrintp_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round towards +∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -35995,7 +35995,7 @@ pub fn svrintp_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round towards +∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -36008,7 +36008,7 @@ pub fn svrintp_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round towards +∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -36017,7 +36017,7 @@ pub fn svrintp_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round towards +∞"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -36026,7 +36026,7 @@ pub fn svrintp_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round using current rounding mode (exact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -36039,7 +36039,7 @@ pub fn svrintx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round using current rounding mode (exact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -36048,7 +36048,7 @@ pub fn svrintx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round using current rounding mode (exact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -36057,7 +36057,7 @@ pub fn svrintx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round using current rounding mode (exact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -36070,7 +36070,7 @@ pub fn svrintx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round using current rounding mode (exact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -36079,7 +36079,7 @@ pub fn svrintx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round using current rounding mode (exact)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -36088,7 +36088,7 @@ pub fn svrintx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round towards zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -36101,7 +36101,7 @@ pub fn svrintz_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> sv
 }
 #[doc = "Round towards zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -36110,7 +36110,7 @@ pub fn svrintz_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round towards zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -36119,7 +36119,7 @@ pub fn svrintz_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Round towards zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -36132,7 +36132,7 @@ pub fn svrintz_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Round towards zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -36141,7 +36141,7 @@ pub fn svrintz_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Round towards zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -36150,7 +36150,7 @@ pub fn svrintz_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frsqrte))]
@@ -36166,7 +36166,7 @@ pub fn svrsqrte_f32(op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frsqrte))]
@@ -36182,7 +36182,7 @@ pub fn svrsqrte_f64(op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frsqrts))]
@@ -36198,7 +36198,7 @@ pub fn svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(frsqrts))]
@@ -36214,7 +36214,7 @@ pub fn svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36227,7 +36227,7 @@ pub fn svscale_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat3
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36236,7 +36236,7 @@ pub fn svscale_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36245,7 +36245,7 @@ pub fn svscale_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat3
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36254,7 +36254,7 @@ pub fn svscale_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36263,7 +36263,7 @@ pub fn svscale_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat3
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36272,7 +36272,7 @@ pub fn svscale_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36285,7 +36285,7 @@ pub fn svscale_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat6
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36294,7 +36294,7 @@ pub fn svscale_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36303,7 +36303,7 @@ pub fn svscale_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat6
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36312,7 +36312,7 @@ pub fn svscale_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36321,7 +36321,7 @@ pub fn svscale_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat6
 }
 #[doc = "Adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -36330,7 +36330,7 @@ pub fn svscale_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_b])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36339,7 +36339,7 @@ pub fn svsel_b(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36348,7 +36348,7 @@ pub fn svsel_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36357,7 +36357,7 @@ pub fn svsel_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36366,7 +36366,7 @@ pub fn svsel_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36375,7 +36375,7 @@ pub fn svsel_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36384,7 +36384,7 @@ pub fn svsel_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36393,7 +36393,7 @@ pub fn svsel_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36402,7 +36402,7 @@ pub fn svsel_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36411,7 +36411,7 @@ pub fn svsel_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36420,7 +36420,7 @@ pub fn svsel_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Conditionally select elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sel))]
@@ -36429,7 +36429,7 @@ pub fn svsel_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_f32<const IMM_INDEX: i32>(tuple: svfloat32x2_t, x: svfloat32_t) -> svfloat32x2_t {
@@ -36438,7 +36438,7 @@ pub fn svset2_f32<const IMM_INDEX: i32>(tuple: svfloat32x2_t, x: svfloat32_t) ->
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_f64<const IMM_INDEX: i32>(tuple: svfloat64x2_t, x: svfloat64_t) -> svfloat64x2_t {
@@ -36447,7 +36447,7 @@ pub fn svset2_f64<const IMM_INDEX: i32>(tuple: svfloat64x2_t, x: svfloat64_t) ->
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_s8<const IMM_INDEX: i32>(tuple: svint8x2_t, x: svint8_t) -> svint8x2_t {
@@ -36456,7 +36456,7 @@ pub fn svset2_s8<const IMM_INDEX: i32>(tuple: svint8x2_t, x: svint8_t) -> svint8
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_s16<const IMM_INDEX: i32>(tuple: svint16x2_t, x: svint16_t) -> svint16x2_t {
@@ -36465,7 +36465,7 @@ pub fn svset2_s16<const IMM_INDEX: i32>(tuple: svint16x2_t, x: svint16_t) -> svi
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_s32<const IMM_INDEX: i32>(tuple: svint32x2_t, x: svint32_t) -> svint32x2_t {
@@ -36474,7 +36474,7 @@ pub fn svset2_s32<const IMM_INDEX: i32>(tuple: svint32x2_t, x: svint32_t) -> svi
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_s64<const IMM_INDEX: i32>(tuple: svint64x2_t, x: svint64_t) -> svint64x2_t {
@@ -36483,7 +36483,7 @@ pub fn svset2_s64<const IMM_INDEX: i32>(tuple: svint64x2_t, x: svint64_t) -> svi
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_u8<const IMM_INDEX: i32>(tuple: svuint8x2_t, x: svuint8_t) -> svuint8x2_t {
@@ -36492,7 +36492,7 @@ pub fn svset2_u8<const IMM_INDEX: i32>(tuple: svuint8x2_t, x: svuint8_t) -> svui
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_u16<const IMM_INDEX: i32>(tuple: svuint16x2_t, x: svuint16_t) -> svuint16x2_t {
@@ -36501,7 +36501,7 @@ pub fn svset2_u16<const IMM_INDEX: i32>(tuple: svuint16x2_t, x: svuint16_t) -> s
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_u32<const IMM_INDEX: i32>(tuple: svuint32x2_t, x: svuint32_t) -> svuint32x2_t {
@@ -36510,7 +36510,7 @@ pub fn svset2_u32<const IMM_INDEX: i32>(tuple: svuint32x2_t, x: svuint32_t) -> s
 }
 #[doc = "Change one vector in a tuple of two vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset2_u64<const IMM_INDEX: i32>(tuple: svuint64x2_t, x: svuint64_t) -> svuint64x2_t {
@@ -36519,7 +36519,7 @@ pub fn svset2_u64<const IMM_INDEX: i32>(tuple: svuint64x2_t, x: svuint64_t) -> s
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_f32<const IMM_INDEX: i32>(tuple: svfloat32x3_t, x: svfloat32_t) -> svfloat32x3_t {
@@ -36528,7 +36528,7 @@ pub fn svset3_f32<const IMM_INDEX: i32>(tuple: svfloat32x3_t, x: svfloat32_t) ->
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_f64<const IMM_INDEX: i32>(tuple: svfloat64x3_t, x: svfloat64_t) -> svfloat64x3_t {
@@ -36537,7 +36537,7 @@ pub fn svset3_f64<const IMM_INDEX: i32>(tuple: svfloat64x3_t, x: svfloat64_t) ->
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_s8<const IMM_INDEX: i32>(tuple: svint8x3_t, x: svint8_t) -> svint8x3_t {
@@ -36546,7 +36546,7 @@ pub fn svset3_s8<const IMM_INDEX: i32>(tuple: svint8x3_t, x: svint8_t) -> svint8
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_s16<const IMM_INDEX: i32>(tuple: svint16x3_t, x: svint16_t) -> svint16x3_t {
@@ -36555,7 +36555,7 @@ pub fn svset3_s16<const IMM_INDEX: i32>(tuple: svint16x3_t, x: svint16_t) -> svi
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_s32<const IMM_INDEX: i32>(tuple: svint32x3_t, x: svint32_t) -> svint32x3_t {
@@ -36564,7 +36564,7 @@ pub fn svset3_s32<const IMM_INDEX: i32>(tuple: svint32x3_t, x: svint32_t) -> svi
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_s64<const IMM_INDEX: i32>(tuple: svint64x3_t, x: svint64_t) -> svint64x3_t {
@@ -36573,7 +36573,7 @@ pub fn svset3_s64<const IMM_INDEX: i32>(tuple: svint64x3_t, x: svint64_t) -> svi
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_u8<const IMM_INDEX: i32>(tuple: svuint8x3_t, x: svuint8_t) -> svuint8x3_t {
@@ -36582,7 +36582,7 @@ pub fn svset3_u8<const IMM_INDEX: i32>(tuple: svuint8x3_t, x: svuint8_t) -> svui
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_u16<const IMM_INDEX: i32>(tuple: svuint16x3_t, x: svuint16_t) -> svuint16x3_t {
@@ -36591,7 +36591,7 @@ pub fn svset3_u16<const IMM_INDEX: i32>(tuple: svuint16x3_t, x: svuint16_t) -> s
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_u32<const IMM_INDEX: i32>(tuple: svuint32x3_t, x: svuint32_t) -> svuint32x3_t {
@@ -36600,7 +36600,7 @@ pub fn svset3_u32<const IMM_INDEX: i32>(tuple: svuint32x3_t, x: svuint32_t) -> s
 }
 #[doc = "Change one vector in a tuple of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset3_u64<const IMM_INDEX: i32>(tuple: svuint64x3_t, x: svuint64_t) -> svuint64x3_t {
@@ -36609,7 +36609,7 @@ pub fn svset3_u64<const IMM_INDEX: i32>(tuple: svuint64x3_t, x: svuint64_t) -> s
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_f32<const IMM_INDEX: i32>(tuple: svfloat32x4_t, x: svfloat32_t) -> svfloat32x4_t {
@@ -36618,7 +36618,7 @@ pub fn svset4_f32<const IMM_INDEX: i32>(tuple: svfloat32x4_t, x: svfloat32_t) ->
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_f64<const IMM_INDEX: i32>(tuple: svfloat64x4_t, x: svfloat64_t) -> svfloat64x4_t {
@@ -36627,7 +36627,7 @@ pub fn svset4_f64<const IMM_INDEX: i32>(tuple: svfloat64x4_t, x: svfloat64_t) ->
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_s8<const IMM_INDEX: i32>(tuple: svint8x4_t, x: svint8_t) -> svint8x4_t {
@@ -36636,7 +36636,7 @@ pub fn svset4_s8<const IMM_INDEX: i32>(tuple: svint8x4_t, x: svint8_t) -> svint8
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_s16<const IMM_INDEX: i32>(tuple: svint16x4_t, x: svint16_t) -> svint16x4_t {
@@ -36645,7 +36645,7 @@ pub fn svset4_s16<const IMM_INDEX: i32>(tuple: svint16x4_t, x: svint16_t) -> svi
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_s32<const IMM_INDEX: i32>(tuple: svint32x4_t, x: svint32_t) -> svint32x4_t {
@@ -36654,7 +36654,7 @@ pub fn svset4_s32<const IMM_INDEX: i32>(tuple: svint32x4_t, x: svint32_t) -> svi
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_s64<const IMM_INDEX: i32>(tuple: svint64x4_t, x: svint64_t) -> svint64x4_t {
@@ -36663,7 +36663,7 @@ pub fn svset4_s64<const IMM_INDEX: i32>(tuple: svint64x4_t, x: svint64_t) -> svi
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_u8<const IMM_INDEX: i32>(tuple: svuint8x4_t, x: svuint8_t) -> svuint8x4_t {
@@ -36672,7 +36672,7 @@ pub fn svset4_u8<const IMM_INDEX: i32>(tuple: svuint8x4_t, x: svuint8_t) -> svui
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_u16<const IMM_INDEX: i32>(tuple: svuint16x4_t, x: svuint16_t) -> svuint16x4_t {
@@ -36681,7 +36681,7 @@ pub fn svset4_u16<const IMM_INDEX: i32>(tuple: svuint16x4_t, x: svuint16_t) -> s
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_u32<const IMM_INDEX: i32>(tuple: svuint32x4_t, x: svuint32_t) -> svuint32x4_t {
@@ -36690,7 +36690,7 @@ pub fn svset4_u32<const IMM_INDEX: i32>(tuple: svuint32x4_t, x: svuint32_t) -> s
 }
 #[doc = "Change one vector in a tuple of four vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub fn svset4_u64<const IMM_INDEX: i32>(tuple: svuint64x4_t, x: svuint64_t) -> svuint64x4_t {
@@ -36699,7 +36699,7 @@ pub fn svset4_u64<const IMM_INDEX: i32>(tuple: svuint64x4_t, x: svuint64_t) -> s
 }
 #[doc = "Initialize the first-fault register to all-true"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsetffr)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(setffr))]
@@ -36712,7 +36712,7 @@ pub fn svsetffr() {
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36725,7 +36725,7 @@ pub fn svsplice_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36738,7 +36738,7 @@ pub fn svsplice_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36751,7 +36751,7 @@ pub fn svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36764,7 +36764,7 @@ pub fn svsplice_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36777,7 +36777,7 @@ pub fn svsplice_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36790,7 +36790,7 @@ pub fn svsplice_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36799,7 +36799,7 @@ pub fn svsplice_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36808,7 +36808,7 @@ pub fn svsplice_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36817,7 +36817,7 @@ pub fn svsplice_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Splice two vectors under predicate control"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(splice))]
@@ -36826,7 +36826,7 @@ pub fn svsplice_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Square root"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsqrt))]
@@ -36839,7 +36839,7 @@ pub fn svsqrt_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svf
 }
 #[doc = "Square root"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsqrt))]
@@ -36848,7 +36848,7 @@ pub fn svsqrt_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Square root"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsqrt))]
@@ -36857,7 +36857,7 @@ pub fn svsqrt_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Square root"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsqrt))]
@@ -36870,7 +36870,7 @@ pub fn svsqrt_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svf
 }
 #[doc = "Square root"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsqrt))]
@@ -36879,7 +36879,7 @@ pub fn svsqrt_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Square root"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsqrt))]
@@ -36891,7 +36891,7 @@ pub fn svsqrt_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -36907,7 +36907,7 @@ pub unsafe fn svst1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -36923,7 +36923,7 @@ pub unsafe fn svst1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -36939,7 +36939,7 @@ pub unsafe fn svst1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -36955,7 +36955,7 @@ pub unsafe fn svst1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -36971,7 +36971,7 @@ pub unsafe fn svst1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -36987,7 +36987,7 @@ pub unsafe fn svst1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -36999,7 +36999,7 @@ pub unsafe fn svst1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -37011,7 +37011,7 @@ pub unsafe fn svst1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37023,7 +37023,7 @@ pub unsafe fn svst1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37035,7 +37035,7 @@ pub unsafe fn svst1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37064,7 +37064,7 @@ pub unsafe fn svst1_scatter_s32index_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37093,7 +37093,7 @@ pub unsafe fn svst1_scatter_s32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37110,7 +37110,7 @@ pub unsafe fn svst1_scatter_s32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37139,7 +37139,7 @@ pub unsafe fn svst1_scatter_s64index_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37168,7 +37168,7 @@ pub unsafe fn svst1_scatter_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37185,7 +37185,7 @@ pub unsafe fn svst1_scatter_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37214,7 +37214,7 @@ pub unsafe fn svst1_scatter_u32index_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37243,7 +37243,7 @@ pub unsafe fn svst1_scatter_u32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37260,7 +37260,7 @@ pub unsafe fn svst1_scatter_u32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37277,7 +37277,7 @@ pub unsafe fn svst1_scatter_u64index_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37294,7 +37294,7 @@ pub unsafe fn svst1_scatter_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37311,7 +37311,7 @@ pub unsafe fn svst1_scatter_u64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37340,7 +37340,7 @@ pub unsafe fn svst1_scatter_s32offset_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37369,7 +37369,7 @@ pub unsafe fn svst1_scatter_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37386,7 +37386,7 @@ pub unsafe fn svst1_scatter_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37415,7 +37415,7 @@ pub unsafe fn svst1_scatter_s64offset_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37444,7 +37444,7 @@ pub unsafe fn svst1_scatter_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37461,7 +37461,7 @@ pub unsafe fn svst1_scatter_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37490,7 +37490,7 @@ pub unsafe fn svst1_scatter_u32offset_f32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37519,7 +37519,7 @@ pub unsafe fn svst1_scatter_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37536,7 +37536,7 @@ pub unsafe fn svst1_scatter_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37553,7 +37553,7 @@ pub unsafe fn svst1_scatter_u64offset_f64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37570,7 +37570,7 @@ pub unsafe fn svst1_scatter_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37588,7 +37588,7 @@ pub unsafe fn svst1_scatter_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37601,7 +37601,7 @@ pub unsafe fn svst1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37614,7 +37614,7 @@ pub unsafe fn svst1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37627,7 +37627,7 @@ pub unsafe fn svst1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37640,7 +37640,7 @@ pub unsafe fn svst1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37653,7 +37653,7 @@ pub unsafe fn svst1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37666,7 +37666,7 @@ pub unsafe fn svst1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37684,7 +37684,7 @@ pub unsafe fn svst1_scatter_u32base_index_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37702,7 +37702,7 @@ pub unsafe fn svst1_scatter_u32base_index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37720,7 +37720,7 @@ pub unsafe fn svst1_scatter_u32base_index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37738,7 +37738,7 @@ pub unsafe fn svst1_scatter_u64base_index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37756,7 +37756,7 @@ pub unsafe fn svst1_scatter_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37774,7 +37774,7 @@ pub unsafe fn svst1_scatter_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37804,7 +37804,7 @@ pub unsafe fn svst1_scatter_u32base_offset_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37834,7 +37834,7 @@ pub unsafe fn svst1_scatter_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37852,7 +37852,7 @@ pub unsafe fn svst1_scatter_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37882,7 +37882,7 @@ pub unsafe fn svst1_scatter_u64base_offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37912,7 +37912,7 @@ pub unsafe fn svst1_scatter_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37929,7 +37929,7 @@ pub unsafe fn svst1_scatter_u64base_offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37941,7 +37941,7 @@ pub unsafe fn svst1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -37953,7 +37953,7 @@ pub unsafe fn svst1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -37965,7 +37965,7 @@ pub unsafe fn svst1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -37977,7 +37977,7 @@ pub unsafe fn svst1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -37989,7 +37989,7 @@ pub unsafe fn svst1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -38001,7 +38001,7 @@ pub unsafe fn svst1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38013,7 +38013,7 @@ pub unsafe fn svst1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38025,7 +38025,7 @@ pub unsafe fn svst1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38037,7 +38037,7 @@ pub unsafe fn svst1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1d))]
@@ -38049,7 +38049,7 @@ pub unsafe fn svst1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38069,7 +38069,7 @@ pub unsafe fn svst1b_s16(pg: svbool_t, base: *mut i8, data: svint16_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38089,7 +38089,7 @@ pub unsafe fn svst1b_s32(pg: svbool_t, base: *mut i8, data: svint32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38109,7 +38109,7 @@ pub unsafe fn svst1h_s32(pg: svbool_t, base: *mut i16, data: svint32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38129,7 +38129,7 @@ pub unsafe fn svst1b_s64(pg: svbool_t, base: *mut i8, data: svint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38149,7 +38149,7 @@ pub unsafe fn svst1h_s64(pg: svbool_t, base: *mut i16, data: svint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38169,7 +38169,7 @@ pub unsafe fn svst1w_s64(pg: svbool_t, base: *mut i32, data: svint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38181,7 +38181,7 @@ pub unsafe fn svst1b_u16(pg: svbool_t, base: *mut u8, data: svuint16_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38193,7 +38193,7 @@ pub unsafe fn svst1b_u32(pg: svbool_t, base: *mut u8, data: svuint32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38205,7 +38205,7 @@ pub unsafe fn svst1h_u32(pg: svbool_t, base: *mut u16, data: svuint32_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38217,7 +38217,7 @@ pub unsafe fn svst1b_u64(pg: svbool_t, base: *mut u8, data: svuint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38229,7 +38229,7 @@ pub unsafe fn svst1h_u64(pg: svbool_t, base: *mut u16, data: svuint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38241,7 +38241,7 @@ pub unsafe fn svst1w_u64(pg: svbool_t, base: *mut u32, data: svuint64_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38275,7 +38275,7 @@ pub unsafe fn svst1b_scatter_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38309,7 +38309,7 @@ pub unsafe fn svst1h_scatter_s32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38326,7 +38326,7 @@ pub unsafe fn svst1b_scatter_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38343,7 +38343,7 @@ pub unsafe fn svst1h_scatter_s32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38377,7 +38377,7 @@ pub unsafe fn svst1b_scatter_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38411,7 +38411,7 @@ pub unsafe fn svst1h_scatter_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38445,7 +38445,7 @@ pub unsafe fn svst1w_scatter_s64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38462,7 +38462,7 @@ pub unsafe fn svst1b_scatter_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38479,7 +38479,7 @@ pub unsafe fn svst1h_scatter_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38496,7 +38496,7 @@ pub unsafe fn svst1w_scatter_s64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38530,7 +38530,7 @@ pub unsafe fn svst1b_scatter_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38564,7 +38564,7 @@ pub unsafe fn svst1h_scatter_u32offset_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38581,7 +38581,7 @@ pub unsafe fn svst1b_scatter_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38598,7 +38598,7 @@ pub unsafe fn svst1h_scatter_u32offset_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38615,7 +38615,7 @@ pub unsafe fn svst1b_scatter_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38632,7 +38632,7 @@ pub unsafe fn svst1h_scatter_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38649,7 +38649,7 @@ pub unsafe fn svst1w_scatter_u64offset_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38666,7 +38666,7 @@ pub unsafe fn svst1b_scatter_u64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38683,7 +38683,7 @@ pub unsafe fn svst1h_scatter_u64offset_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38701,7 +38701,7 @@ pub unsafe fn svst1w_scatter_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38736,7 +38736,7 @@ pub unsafe fn svst1b_scatter_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38771,7 +38771,7 @@ pub unsafe fn svst1h_scatter_u32base_offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38789,7 +38789,7 @@ pub unsafe fn svst1b_scatter_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38807,7 +38807,7 @@ pub unsafe fn svst1h_scatter_u32base_offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38842,7 +38842,7 @@ pub unsafe fn svst1b_scatter_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38877,7 +38877,7 @@ pub unsafe fn svst1h_scatter_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38912,7 +38912,7 @@ pub unsafe fn svst1w_scatter_u64base_offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38930,7 +38930,7 @@ pub unsafe fn svst1b_scatter_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38948,7 +38948,7 @@ pub unsafe fn svst1h_scatter_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -38966,7 +38966,7 @@ pub unsafe fn svst1w_scatter_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -38979,7 +38979,7 @@ pub unsafe fn svst1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -38992,7 +38992,7 @@ pub unsafe fn svst1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39005,7 +39005,7 @@ pub unsafe fn svst1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39018,7 +39018,7 @@ pub unsafe fn svst1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39031,7 +39031,7 @@ pub unsafe fn svst1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39044,7 +39044,7 @@ pub unsafe fn svst1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39057,7 +39057,7 @@ pub unsafe fn svst1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39070,7 +39070,7 @@ pub unsafe fn svst1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39083,7 +39083,7 @@ pub unsafe fn svst1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39095,7 +39095,7 @@ pub unsafe fn svst1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39107,7 +39107,7 @@ pub unsafe fn svst1b_vnum_s16(pg: svbool_t, base: *mut i8, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39119,7 +39119,7 @@ pub unsafe fn svst1b_vnum_s32(pg: svbool_t, base: *mut i8, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39131,7 +39131,7 @@ pub unsafe fn svst1h_vnum_s32(pg: svbool_t, base: *mut i16, vnum: i64, data: svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39143,7 +39143,7 @@ pub unsafe fn svst1b_vnum_s64(pg: svbool_t, base: *mut i8, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39155,7 +39155,7 @@ pub unsafe fn svst1h_vnum_s64(pg: svbool_t, base: *mut i16, vnum: i64, data: svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39167,7 +39167,7 @@ pub unsafe fn svst1w_vnum_s64(pg: svbool_t, base: *mut i32, vnum: i64, data: svi
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39179,7 +39179,7 @@ pub unsafe fn svst1b_vnum_u16(pg: svbool_t, base: *mut u8, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39191,7 +39191,7 @@ pub unsafe fn svst1b_vnum_u32(pg: svbool_t, base: *mut u8, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39203,7 +39203,7 @@ pub unsafe fn svst1h_vnum_u32(pg: svbool_t, base: *mut u16, vnum: i64, data: svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1b))]
@@ -39215,7 +39215,7 @@ pub unsafe fn svst1b_vnum_u64(pg: svbool_t, base: *mut u8, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39227,7 +39227,7 @@ pub unsafe fn svst1h_vnum_u64(pg: svbool_t, base: *mut u16, vnum: i64, data: svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39239,7 +39239,7 @@ pub unsafe fn svst1w_vnum_u64(pg: svbool_t, base: *mut u32, vnum: i64, data: svu
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39273,7 +39273,7 @@ pub unsafe fn svst1h_scatter_s32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39290,7 +39290,7 @@ pub unsafe fn svst1h_scatter_s32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39324,7 +39324,7 @@ pub unsafe fn svst1h_scatter_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39358,7 +39358,7 @@ pub unsafe fn svst1w_scatter_s64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39375,7 +39375,7 @@ pub unsafe fn svst1h_scatter_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39392,7 +39392,7 @@ pub unsafe fn svst1w_scatter_s64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39426,7 +39426,7 @@ pub unsafe fn svst1h_scatter_u32index_s32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39443,7 +39443,7 @@ pub unsafe fn svst1h_scatter_u32index_u32(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39460,7 +39460,7 @@ pub unsafe fn svst1h_scatter_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39477,7 +39477,7 @@ pub unsafe fn svst1w_scatter_u64index_s64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39494,7 +39494,7 @@ pub unsafe fn svst1h_scatter_u64index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39512,7 +39512,7 @@ pub unsafe fn svst1w_scatter_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39530,7 +39530,7 @@ pub unsafe fn svst1h_scatter_u32base_index_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39548,7 +39548,7 @@ pub unsafe fn svst1h_scatter_u32base_index_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39566,7 +39566,7 @@ pub unsafe fn svst1h_scatter_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39584,7 +39584,7 @@ pub unsafe fn svst1w_scatter_u64base_index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1h))]
@@ -39602,7 +39602,7 @@ pub unsafe fn svst1h_scatter_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st1w))]
@@ -39619,7 +39619,7 @@ pub unsafe fn svst1w_scatter_u64base_index_u64(
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2w))]
@@ -39640,7 +39640,7 @@ pub unsafe fn svst2_f32(pg: svbool_t, base: *mut f32, data: svfloat32x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2d))]
@@ -39661,7 +39661,7 @@ pub unsafe fn svst2_f64(pg: svbool_t, base: *mut f64, data: svfloat64x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2b))]
@@ -39677,7 +39677,7 @@ pub unsafe fn svst2_s8(pg: svbool_t, base: *mut i8, data: svint8x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2h))]
@@ -39698,7 +39698,7 @@ pub unsafe fn svst2_s16(pg: svbool_t, base: *mut i16, data: svint16x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2w))]
@@ -39719,7 +39719,7 @@ pub unsafe fn svst2_s32(pg: svbool_t, base: *mut i32, data: svint32x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2d))]
@@ -39740,7 +39740,7 @@ pub unsafe fn svst2_s64(pg: svbool_t, base: *mut i64, data: svint64x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2b))]
@@ -39752,7 +39752,7 @@ pub unsafe fn svst2_u8(pg: svbool_t, base: *mut u8, data: svuint8x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2h))]
@@ -39764,7 +39764,7 @@ pub unsafe fn svst2_u16(pg: svbool_t, base: *mut u16, data: svuint16x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2w))]
@@ -39776,7 +39776,7 @@ pub unsafe fn svst2_u32(pg: svbool_t, base: *mut u32, data: svuint32x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2d))]
@@ -39788,7 +39788,7 @@ pub unsafe fn svst2_u64(pg: svbool_t, base: *mut u64, data: svuint64x2_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2w))]
@@ -39800,7 +39800,7 @@ pub unsafe fn svst2_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2d))]
@@ -39812,7 +39812,7 @@ pub unsafe fn svst2_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2b))]
@@ -39824,7 +39824,7 @@ pub unsafe fn svst2_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2h))]
@@ -39836,7 +39836,7 @@ pub unsafe fn svst2_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2w))]
@@ -39848,7 +39848,7 @@ pub unsafe fn svst2_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2d))]
@@ -39860,7 +39860,7 @@ pub unsafe fn svst2_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2b))]
@@ -39872,7 +39872,7 @@ pub unsafe fn svst2_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2h))]
@@ -39884,7 +39884,7 @@ pub unsafe fn svst2_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2w))]
@@ -39896,7 +39896,7 @@ pub unsafe fn svst2_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st2d))]
@@ -39908,7 +39908,7 @@ pub unsafe fn svst2_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3w))]
@@ -39936,7 +39936,7 @@ pub unsafe fn svst3_f32(pg: svbool_t, base: *mut f32, data: svfloat32x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3d))]
@@ -39964,7 +39964,7 @@ pub unsafe fn svst3_f64(pg: svbool_t, base: *mut f64, data: svfloat64x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3b))]
@@ -39986,7 +39986,7 @@ pub unsafe fn svst3_s8(pg: svbool_t, base: *mut i8, data: svint8x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3h))]
@@ -40014,7 +40014,7 @@ pub unsafe fn svst3_s16(pg: svbool_t, base: *mut i16, data: svint16x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3w))]
@@ -40042,7 +40042,7 @@ pub unsafe fn svst3_s32(pg: svbool_t, base: *mut i32, data: svint32x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3d))]
@@ -40070,7 +40070,7 @@ pub unsafe fn svst3_s64(pg: svbool_t, base: *mut i64, data: svint64x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3b))]
@@ -40082,7 +40082,7 @@ pub unsafe fn svst3_u8(pg: svbool_t, base: *mut u8, data: svuint8x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3h))]
@@ -40094,7 +40094,7 @@ pub unsafe fn svst3_u16(pg: svbool_t, base: *mut u16, data: svuint16x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3w))]
@@ -40106,7 +40106,7 @@ pub unsafe fn svst3_u32(pg: svbool_t, base: *mut u32, data: svuint32x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3d))]
@@ -40118,7 +40118,7 @@ pub unsafe fn svst3_u64(pg: svbool_t, base: *mut u64, data: svuint64x3_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3w))]
@@ -40130,7 +40130,7 @@ pub unsafe fn svst3_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3d))]
@@ -40142,7 +40142,7 @@ pub unsafe fn svst3_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3b))]
@@ -40154,7 +40154,7 @@ pub unsafe fn svst3_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3h))]
@@ -40166,7 +40166,7 @@ pub unsafe fn svst3_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3w))]
@@ -40178,7 +40178,7 @@ pub unsafe fn svst3_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3d))]
@@ -40190,7 +40190,7 @@ pub unsafe fn svst3_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3b))]
@@ -40202,7 +40202,7 @@ pub unsafe fn svst3_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3h))]
@@ -40214,7 +40214,7 @@ pub unsafe fn svst3_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3w))]
@@ -40226,7 +40226,7 @@ pub unsafe fn svst3_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st3d))]
@@ -40238,7 +40238,7 @@ pub unsafe fn svst3_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4w))]
@@ -40268,7 +40268,7 @@ pub unsafe fn svst4_f32(pg: svbool_t, base: *mut f32, data: svfloat32x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4d))]
@@ -40298,7 +40298,7 @@ pub unsafe fn svst4_f64(pg: svbool_t, base: *mut f64, data: svfloat64x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4b))]
@@ -40328,7 +40328,7 @@ pub unsafe fn svst4_s8(pg: svbool_t, base: *mut i8, data: svint8x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4h))]
@@ -40358,7 +40358,7 @@ pub unsafe fn svst4_s16(pg: svbool_t, base: *mut i16, data: svint16x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4w))]
@@ -40388,7 +40388,7 @@ pub unsafe fn svst4_s32(pg: svbool_t, base: *mut i32, data: svint32x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4d))]
@@ -40418,7 +40418,7 @@ pub unsafe fn svst4_s64(pg: svbool_t, base: *mut i64, data: svint64x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4b))]
@@ -40430,7 +40430,7 @@ pub unsafe fn svst4_u8(pg: svbool_t, base: *mut u8, data: svuint8x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4h))]
@@ -40442,7 +40442,7 @@ pub unsafe fn svst4_u16(pg: svbool_t, base: *mut u16, data: svuint16x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4w))]
@@ -40454,7 +40454,7 @@ pub unsafe fn svst4_u32(pg: svbool_t, base: *mut u32, data: svuint32x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4d))]
@@ -40466,7 +40466,7 @@ pub unsafe fn svst4_u64(pg: svbool_t, base: *mut u64, data: svuint64x4_t) {
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4w))]
@@ -40478,7 +40478,7 @@ pub unsafe fn svst4_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4d))]
@@ -40490,7 +40490,7 @@ pub unsafe fn svst4_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfl
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4b))]
@@ -40502,7 +40502,7 @@ pub unsafe fn svst4_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4h))]
@@ -40514,7 +40514,7 @@ pub unsafe fn svst4_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4w))]
@@ -40526,7 +40526,7 @@ pub unsafe fn svst4_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4d))]
@@ -40538,7 +40538,7 @@ pub unsafe fn svst4_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svin
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4b))]
@@ -40550,7 +40550,7 @@ pub unsafe fn svst4_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4h))]
@@ -40562,7 +40562,7 @@ pub unsafe fn svst4_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4w))]
@@ -40574,7 +40574,7 @@ pub unsafe fn svst4_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svui
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(st4d))]
@@ -40587,7 +40587,7 @@ pub unsafe fn svst4_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svui
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -40604,7 +40604,7 @@ pub unsafe fn svstnt1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -40621,7 +40621,7 @@ pub unsafe fn svstnt1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -40638,7 +40638,7 @@ pub unsafe fn svstnt1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -40655,7 +40655,7 @@ pub unsafe fn svstnt1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -40672,7 +40672,7 @@ pub unsafe fn svstnt1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -40689,7 +40689,7 @@ pub unsafe fn svstnt1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -40702,7 +40702,7 @@ pub unsafe fn svstnt1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -40715,7 +40715,7 @@ pub unsafe fn svstnt1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -40728,7 +40728,7 @@ pub unsafe fn svstnt1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -40741,7 +40741,7 @@ pub unsafe fn svstnt1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -40754,7 +40754,7 @@ pub unsafe fn svstnt1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -40767,7 +40767,7 @@ pub unsafe fn svstnt1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -40780,7 +40780,7 @@ pub unsafe fn svstnt1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svin
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -40793,7 +40793,7 @@ pub unsafe fn svstnt1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -40806,7 +40806,7 @@ pub unsafe fn svstnt1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -40819,7 +40819,7 @@ pub unsafe fn svstnt1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -40832,7 +40832,7 @@ pub unsafe fn svstnt1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svui
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -40845,7 +40845,7 @@ pub unsafe fn svstnt1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -40858,7 +40858,7 @@ pub unsafe fn svstnt1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: sv
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -40867,7 +40867,7 @@ pub unsafe fn svstnt1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: sv
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40880,7 +40880,7 @@ pub fn svsub_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40889,7 +40889,7 @@ pub fn svsub_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40898,7 +40898,7 @@ pub fn svsub_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40907,7 +40907,7 @@ pub fn svsub_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40916,7 +40916,7 @@ pub fn svsub_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat3
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40925,7 +40925,7 @@ pub fn svsub_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40938,7 +40938,7 @@ pub fn svsub_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40947,7 +40947,7 @@ pub fn svsub_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40956,7 +40956,7 @@ pub fn svsub_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40965,7 +40965,7 @@ pub fn svsub_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40974,7 +40974,7 @@ pub fn svsub_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat6
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -40983,7 +40983,7 @@ pub fn svsub_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -40996,7 +40996,7 @@ pub fn svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41005,7 +41005,7 @@ pub fn svsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41014,7 +41014,7 @@ pub fn svsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41023,7 +41023,7 @@ pub fn svsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41032,7 +41032,7 @@ pub fn svsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41041,7 +41041,7 @@ pub fn svsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41054,7 +41054,7 @@ pub fn svsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41063,7 +41063,7 @@ pub fn svsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41072,7 +41072,7 @@ pub fn svsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41081,7 +41081,7 @@ pub fn svsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41090,7 +41090,7 @@ pub fn svsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41099,7 +41099,7 @@ pub fn svsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41112,7 +41112,7 @@ pub fn svsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41121,7 +41121,7 @@ pub fn svsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41130,7 +41130,7 @@ pub fn svsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41139,7 +41139,7 @@ pub fn svsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41148,7 +41148,7 @@ pub fn svsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41157,7 +41157,7 @@ pub fn svsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41170,7 +41170,7 @@ pub fn svsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41179,7 +41179,7 @@ pub fn svsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41188,7 +41188,7 @@ pub fn svsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41197,7 +41197,7 @@ pub fn svsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41206,7 +41206,7 @@ pub fn svsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41215,7 +41215,7 @@ pub fn svsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41224,7 +41224,7 @@ pub fn svsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41233,7 +41233,7 @@ pub fn svsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41242,7 +41242,7 @@ pub fn svsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41251,7 +41251,7 @@ pub fn svsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41260,7 +41260,7 @@ pub fn svsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41269,7 +41269,7 @@ pub fn svsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41278,7 +41278,7 @@ pub fn svsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41287,7 +41287,7 @@ pub fn svsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41296,7 +41296,7 @@ pub fn svsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41305,7 +41305,7 @@ pub fn svsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41314,7 +41314,7 @@ pub fn svsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41323,7 +41323,7 @@ pub fn svsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41332,7 +41332,7 @@ pub fn svsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41341,7 +41341,7 @@ pub fn svsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41350,7 +41350,7 @@ pub fn svsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41359,7 +41359,7 @@ pub fn svsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41368,7 +41368,7 @@ pub fn svsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41377,7 +41377,7 @@ pub fn svsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41386,7 +41386,7 @@ pub fn svsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41395,7 +41395,7 @@ pub fn svsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41404,7 +41404,7 @@ pub fn svsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41413,7 +41413,7 @@ pub fn svsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41422,7 +41422,7 @@ pub fn svsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -41431,7 +41431,7 @@ pub fn svsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41444,7 +41444,7 @@ pub fn svsubr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41453,7 +41453,7 @@ pub fn svsubr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41462,7 +41462,7 @@ pub fn svsubr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41471,7 +41471,7 @@ pub fn svsubr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41480,7 +41480,7 @@ pub fn svsubr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41489,7 +41489,7 @@ pub fn svsubr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41502,7 +41502,7 @@ pub fn svsubr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41511,7 +41511,7 @@ pub fn svsubr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41520,7 +41520,7 @@ pub fn svsubr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41529,7 +41529,7 @@ pub fn svsubr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41538,7 +41538,7 @@ pub fn svsubr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fsubr))]
@@ -41547,7 +41547,7 @@ pub fn svsubr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41560,7 +41560,7 @@ pub fn svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41569,7 +41569,7 @@ pub fn svsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41578,7 +41578,7 @@ pub fn svsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41587,7 +41587,7 @@ pub fn svsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41596,7 +41596,7 @@ pub fn svsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41605,7 +41605,7 @@ pub fn svsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41618,7 +41618,7 @@ pub fn svsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41627,7 +41627,7 @@ pub fn svsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41636,7 +41636,7 @@ pub fn svsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41645,7 +41645,7 @@ pub fn svsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41654,7 +41654,7 @@ pub fn svsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41663,7 +41663,7 @@ pub fn svsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41676,7 +41676,7 @@ pub fn svsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41685,7 +41685,7 @@ pub fn svsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41694,7 +41694,7 @@ pub fn svsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41703,7 +41703,7 @@ pub fn svsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41712,7 +41712,7 @@ pub fn svsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41721,7 +41721,7 @@ pub fn svsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41734,7 +41734,7 @@ pub fn svsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41743,7 +41743,7 @@ pub fn svsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41752,7 +41752,7 @@ pub fn svsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41761,7 +41761,7 @@ pub fn svsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41770,7 +41770,7 @@ pub fn svsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41779,7 +41779,7 @@ pub fn svsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41788,7 +41788,7 @@ pub fn svsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41797,7 +41797,7 @@ pub fn svsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41806,7 +41806,7 @@ pub fn svsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41815,7 +41815,7 @@ pub fn svsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41824,7 +41824,7 @@ pub fn svsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41833,7 +41833,7 @@ pub fn svsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41842,7 +41842,7 @@ pub fn svsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41851,7 +41851,7 @@ pub fn svsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41860,7 +41860,7 @@ pub fn svsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41869,7 +41869,7 @@ pub fn svsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41878,7 +41878,7 @@ pub fn svsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41887,7 +41887,7 @@ pub fn svsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41896,7 +41896,7 @@ pub fn svsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41905,7 +41905,7 @@ pub fn svsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41914,7 +41914,7 @@ pub fn svsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41923,7 +41923,7 @@ pub fn svsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41932,7 +41932,7 @@ pub fn svsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41941,7 +41941,7 @@ pub fn svsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41950,7 +41950,7 @@ pub fn svsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41959,7 +41959,7 @@ pub fn svsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41968,7 +41968,7 @@ pub fn svsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41977,7 +41977,7 @@ pub fn svsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41986,7 +41986,7 @@ pub fn svsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subr))]
@@ -41995,7 +41995,7 @@ pub fn svsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Dot product (signed × unsigned)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sudot, IMM_INDEX = 0))]
@@ -42021,7 +42021,7 @@ pub fn svsudot_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Dot product (signed × unsigned)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usdot))]
@@ -42030,7 +42030,7 @@ pub fn svsudot_s32(op1: svint32_t, op2: svint8_t, op3: svuint8_t) -> svint32_t {
 }
 #[doc = "Dot product (signed × unsigned)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usdot))]
@@ -42039,7 +42039,7 @@ pub fn svsudot_n_s32(op1: svint32_t, op2: svint8_t, op3: u8) -> svint32_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42052,7 +42052,7 @@ pub fn svtbl_f32(data: svfloat32_t, indices: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42065,7 +42065,7 @@ pub fn svtbl_f64(data: svfloat64_t, indices: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42078,7 +42078,7 @@ pub fn svtbl_s8(data: svint8_t, indices: svuint8_t) -> svint8_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42091,7 +42091,7 @@ pub fn svtbl_s16(data: svint16_t, indices: svuint16_t) -> svint16_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42104,7 +42104,7 @@ pub fn svtbl_s32(data: svint32_t, indices: svuint32_t) -> svint32_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42117,7 +42117,7 @@ pub fn svtbl_s64(data: svint64_t, indices: svuint64_t) -> svint64_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42126,7 +42126,7 @@ pub fn svtbl_u8(data: svuint8_t, indices: svuint8_t) -> svuint8_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42135,7 +42135,7 @@ pub fn svtbl_u16(data: svuint16_t, indices: svuint16_t) -> svuint16_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42144,7 +42144,7 @@ pub fn svtbl_u32(data: svuint32_t, indices: svuint32_t) -> svuint32_t {
 }
 #[doc = "Table lookup in single-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -42153,7 +42153,7 @@ pub fn svtbl_u64(data: svuint64_t, indices: svuint64_t) -> svuint64_t {
 }
 #[doc = "Trigonometric multiply-add coefficient"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))]
@@ -42170,7 +42170,7 @@ pub fn svtmad_f32<const IMM3: i32>(op1: svfloat32_t, op2: svfloat32_t) -> svfloa
 }
 #[doc = "Trigonometric multiply-add coefficient"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))]
@@ -42187,7 +42187,7 @@ pub fn svtmad_f64<const IMM3: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloa
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42200,7 +42200,7 @@ pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42213,7 +42213,7 @@ pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42226,7 +42226,7 @@ pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42239,7 +42239,7 @@ pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42252,7 +42252,7 @@ pub fn svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42265,7 +42265,7 @@ pub fn svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42278,7 +42278,7 @@ pub fn svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42291,7 +42291,7 @@ pub fn svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42304,7 +42304,7 @@ pub fn svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42317,7 +42317,7 @@ pub fn svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42326,7 +42326,7 @@ pub fn svtrn1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42335,7 +42335,7 @@ pub fn svtrn1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42344,7 +42344,7 @@ pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42353,7 +42353,7 @@ pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42366,7 +42366,7 @@ pub fn svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42379,7 +42379,7 @@ pub fn svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42392,7 +42392,7 @@ pub fn svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42405,7 +42405,7 @@ pub fn svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42418,7 +42418,7 @@ pub fn svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42431,7 +42431,7 @@ pub fn svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42440,7 +42440,7 @@ pub fn svtrn1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42449,7 +42449,7 @@ pub fn svtrn1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42458,7 +42458,7 @@ pub fn svtrn1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
@@ -42467,7 +42467,7 @@ pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42480,7 +42480,7 @@ pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42493,7 +42493,7 @@ pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42506,7 +42506,7 @@ pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42519,7 +42519,7 @@ pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42532,7 +42532,7 @@ pub fn svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42545,7 +42545,7 @@ pub fn svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42558,7 +42558,7 @@ pub fn svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42571,7 +42571,7 @@ pub fn svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42584,7 +42584,7 @@ pub fn svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42597,7 +42597,7 @@ pub fn svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42606,7 +42606,7 @@ pub fn svtrn2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42615,7 +42615,7 @@ pub fn svtrn2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42624,7 +42624,7 @@ pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42633,7 +42633,7 @@ pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42646,7 +42646,7 @@ pub fn svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42659,7 +42659,7 @@ pub fn svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42672,7 +42672,7 @@ pub fn svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42685,7 +42685,7 @@ pub fn svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42698,7 +42698,7 @@ pub fn svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42711,7 +42711,7 @@ pub fn svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42720,7 +42720,7 @@ pub fn svtrn2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42729,7 +42729,7 @@ pub fn svtrn2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42738,7 +42738,7 @@ pub fn svtrn2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
@@ -42747,7 +42747,7 @@ pub fn svtrn2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Trigonometric starting value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ftsmul))]
@@ -42763,7 +42763,7 @@ pub fn svtsmul_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Trigonometric starting value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ftsmul))]
@@ -42779,7 +42779,7 @@ pub fn svtsmul_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Trigonometric select coefficient"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ftssel))]
@@ -42795,7 +42795,7 @@ pub fn svtssel_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Trigonometric select coefficient"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ftssel))]
@@ -42813,7 +42813,7 @@ pub fn svtssel_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_f32() -> svfloat32x2_t {
@@ -42823,7 +42823,7 @@ pub unsafe fn svundef2_f32() -> svfloat32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_f64() -> svfloat64x2_t {
@@ -42833,7 +42833,7 @@ pub unsafe fn svundef2_f64() -> svfloat64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_s8() -> svint8x2_t {
@@ -42843,7 +42843,7 @@ pub unsafe fn svundef2_s8() -> svint8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_s16() -> svint16x2_t {
@@ -42853,7 +42853,7 @@ pub unsafe fn svundef2_s16() -> svint16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_s32() -> svint32x2_t {
@@ -42863,7 +42863,7 @@ pub unsafe fn svundef2_s32() -> svint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_s64() -> svint64x2_t {
@@ -42873,7 +42873,7 @@ pub unsafe fn svundef2_s64() -> svint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_u8() -> svuint8x2_t {
@@ -42883,7 +42883,7 @@ pub unsafe fn svundef2_u8() -> svuint8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_u16() -> svuint16x2_t {
@@ -42893,7 +42893,7 @@ pub unsafe fn svundef2_u16() -> svuint16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_u32() -> svuint32x2_t {
@@ -42903,7 +42903,7 @@ pub unsafe fn svundef2_u32() -> svuint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef2_u64() -> svuint64x2_t {
@@ -42913,7 +42913,7 @@ pub unsafe fn svundef2_u64() -> svuint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_f32() -> svfloat32x3_t {
@@ -42923,7 +42923,7 @@ pub unsafe fn svundef3_f32() -> svfloat32x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_f64() -> svfloat64x3_t {
@@ -42933,7 +42933,7 @@ pub unsafe fn svundef3_f64() -> svfloat64x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_s8() -> svint8x3_t {
@@ -42943,7 +42943,7 @@ pub unsafe fn svundef3_s8() -> svint8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_s16() -> svint16x3_t {
@@ -42953,7 +42953,7 @@ pub unsafe fn svundef3_s16() -> svint16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_s32() -> svint32x3_t {
@@ -42963,7 +42963,7 @@ pub unsafe fn svundef3_s32() -> svint32x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_s64() -> svint64x3_t {
@@ -42973,7 +42973,7 @@ pub unsafe fn svundef3_s64() -> svint64x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_u8() -> svuint8x3_t {
@@ -42983,7 +42983,7 @@ pub unsafe fn svundef3_u8() -> svuint8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_u16() -> svuint16x3_t {
@@ -42993,7 +42993,7 @@ pub unsafe fn svundef3_u16() -> svuint16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_u32() -> svuint32x3_t {
@@ -43003,7 +43003,7 @@ pub unsafe fn svundef3_u32() -> svuint32x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef3_u64() -> svuint64x3_t {
@@ -43013,7 +43013,7 @@ pub unsafe fn svundef3_u64() -> svuint64x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_f32() -> svfloat32x4_t {
@@ -43028,7 +43028,7 @@ pub unsafe fn svundef4_f32() -> svfloat32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_f64() -> svfloat64x4_t {
@@ -43043,7 +43043,7 @@ pub unsafe fn svundef4_f64() -> svfloat64x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_s8() -> svint8x4_t {
@@ -43053,7 +43053,7 @@ pub unsafe fn svundef4_s8() -> svint8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_s16() -> svint16x4_t {
@@ -43068,7 +43068,7 @@ pub unsafe fn svundef4_s16() -> svint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_s32() -> svint32x4_t {
@@ -43083,7 +43083,7 @@ pub unsafe fn svundef4_s32() -> svint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_s64() -> svint64x4_t {
@@ -43098,7 +43098,7 @@ pub unsafe fn svundef4_s64() -> svint64x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_u8() -> svuint8x4_t {
@@ -43108,7 +43108,7 @@ pub unsafe fn svundef4_u8() -> svuint8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_u16() -> svuint16x4_t {
@@ -43123,7 +43123,7 @@ pub unsafe fn svundef4_u16() -> svuint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_u32() -> svuint32x4_t {
@@ -43138,7 +43138,7 @@ pub unsafe fn svundef4_u32() -> svuint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef4_u64() -> svuint64x4_t {
@@ -43153,7 +43153,7 @@ pub unsafe fn svundef4_u64() -> svuint64x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_f32() -> svfloat32_t {
@@ -43163,7 +43163,7 @@ pub unsafe fn svundef_f32() -> svfloat32_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_f64() -> svfloat64_t {
@@ -43173,7 +43173,7 @@ pub unsafe fn svundef_f64() -> svfloat64_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_s8() -> svint8_t {
@@ -43183,7 +43183,7 @@ pub unsafe fn svundef_s8() -> svint8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_s16() -> svint16_t {
@@ -43193,7 +43193,7 @@ pub unsafe fn svundef_s16() -> svint16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_s32() -> svint32_t {
@@ -43203,7 +43203,7 @@ pub unsafe fn svundef_s32() -> svint32_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_s64() -> svint64_t {
@@ -43213,7 +43213,7 @@ pub unsafe fn svundef_s64() -> svint64_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_u8() -> svuint8_t {
@@ -43223,7 +43223,7 @@ pub unsafe fn svundef_u8() -> svuint8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_u16() -> svuint16_t {
@@ -43233,7 +43233,7 @@ pub unsafe fn svundef_u16() -> svuint16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_u32() -> svuint32_t {
@@ -43243,7 +43243,7 @@ pub unsafe fn svundef_u32() -> svuint32_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub unsafe fn svundef_u64() -> svuint64_t {
@@ -43251,7 +43251,7 @@ pub unsafe fn svundef_u64() -> svuint64_t {
 }
 #[doc = "Dot product (unsigned × signed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usdot, IMM_INDEX = 0))]
@@ -43277,7 +43277,7 @@ pub fn svusdot_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Dot product (unsigned × signed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usdot))]
@@ -43290,7 +43290,7 @@ pub fn svusdot_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t {
 }
 #[doc = "Dot product (unsigned × signed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usdot))]
@@ -43299,7 +43299,7 @@ pub fn svusdot_n_s32(op1: svint32_t, op2: svuint8_t, op3: i8) -> svint32_t {
 }
 #[doc = "Matrix multiply-accumulate (unsigned × signed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusmmla[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,i8mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usmmla))]
@@ -43312,7 +43312,7 @@ pub fn svusmmla_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43325,7 +43325,7 @@ pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43338,7 +43338,7 @@ pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43351,7 +43351,7 @@ pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43364,7 +43364,7 @@ pub fn svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43377,7 +43377,7 @@ pub fn svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43390,7 +43390,7 @@ pub fn svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43403,7 +43403,7 @@ pub fn svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43416,7 +43416,7 @@ pub fn svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43429,7 +43429,7 @@ pub fn svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43442,7 +43442,7 @@ pub fn svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43451,7 +43451,7 @@ pub fn svuzp1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43460,7 +43460,7 @@ pub fn svuzp1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43469,7 +43469,7 @@ pub fn svuzp1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Concatenate even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43478,7 +43478,7 @@ pub fn svuzp1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43491,7 +43491,7 @@ pub fn svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43504,7 +43504,7 @@ pub fn svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43517,7 +43517,7 @@ pub fn svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43530,7 +43530,7 @@ pub fn svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43543,7 +43543,7 @@ pub fn svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43556,7 +43556,7 @@ pub fn svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43565,7 +43565,7 @@ pub fn svuzp1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43574,7 +43574,7 @@ pub fn svuzp1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43583,7 +43583,7 @@ pub fn svuzp1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Concatenate even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp1))]
@@ -43592,7 +43592,7 @@ pub fn svuzp1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43605,7 +43605,7 @@ pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43618,7 +43618,7 @@ pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43631,7 +43631,7 @@ pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43644,7 +43644,7 @@ pub fn svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43657,7 +43657,7 @@ pub fn svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43670,7 +43670,7 @@ pub fn svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43683,7 +43683,7 @@ pub fn svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43696,7 +43696,7 @@ pub fn svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43709,7 +43709,7 @@ pub fn svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43722,7 +43722,7 @@ pub fn svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43731,7 +43731,7 @@ pub fn svuzp2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43740,7 +43740,7 @@ pub fn svuzp2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43749,7 +43749,7 @@ pub fn svuzp2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Concatenate odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43758,7 +43758,7 @@ pub fn svuzp2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43771,7 +43771,7 @@ pub fn svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43784,7 +43784,7 @@ pub fn svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43797,7 +43797,7 @@ pub fn svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43810,7 +43810,7 @@ pub fn svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43823,7 +43823,7 @@ pub fn svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43836,7 +43836,7 @@ pub fn svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43845,7 +43845,7 @@ pub fn svuzp2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43854,7 +43854,7 @@ pub fn svuzp2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43863,7 +43863,7 @@ pub fn svuzp2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Concatenate odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uzp2))]
@@ -43872,7 +43872,7 @@ pub fn svuzp2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43888,7 +43888,7 @@ pub fn svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43904,7 +43904,7 @@ pub fn svwhilele_b16_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43920,7 +43920,7 @@ pub fn svwhilele_b32_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43936,7 +43936,7 @@ pub fn svwhilele_b64_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43952,7 +43952,7 @@ pub fn svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43968,7 +43968,7 @@ pub fn svwhilele_b16_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -43984,7 +43984,7 @@ pub fn svwhilele_b32_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilele))]
@@ -44000,7 +44000,7 @@ pub fn svwhilele_b64_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44016,7 +44016,7 @@ pub fn svwhilele_b8_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44032,7 +44032,7 @@ pub fn svwhilele_b16_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44048,7 +44048,7 @@ pub fn svwhilele_b32_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44064,7 +44064,7 @@ pub fn svwhilele_b64_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44080,7 +44080,7 @@ pub fn svwhilele_b8_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44096,7 +44096,7 @@ pub fn svwhilele_b16_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44112,7 +44112,7 @@ pub fn svwhilele_b32_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilels))]
@@ -44128,7 +44128,7 @@ pub fn svwhilele_b64_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44144,7 +44144,7 @@ pub fn svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44160,7 +44160,7 @@ pub fn svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44176,7 +44176,7 @@ pub fn svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44192,7 +44192,7 @@ pub fn svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44208,7 +44208,7 @@ pub fn svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44224,7 +44224,7 @@ pub fn svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44240,7 +44240,7 @@ pub fn svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelt))]
@@ -44256,7 +44256,7 @@ pub fn svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44272,7 +44272,7 @@ pub fn svwhilelt_b8_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44288,7 +44288,7 @@ pub fn svwhilelt_b16_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44304,7 +44304,7 @@ pub fn svwhilelt_b32_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44320,7 +44320,7 @@ pub fn svwhilelt_b64_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44336,7 +44336,7 @@ pub fn svwhilelt_b8_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44352,7 +44352,7 @@ pub fn svwhilelt_b16_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44368,7 +44368,7 @@ pub fn svwhilelt_b32_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While incrementing scalar is less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilelo))]
@@ -44384,7 +44384,7 @@ pub fn svwhilelt_b64_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "Write to the first-fault register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwrffr)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(wrffr))]
@@ -44397,7 +44397,7 @@ pub fn svwrffr(op: svbool_t) {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44410,7 +44410,7 @@ pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44423,7 +44423,7 @@ pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44436,7 +44436,7 @@ pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44449,7 +44449,7 @@ pub fn svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44462,7 +44462,7 @@ pub fn svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44475,7 +44475,7 @@ pub fn svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44488,7 +44488,7 @@ pub fn svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44501,7 +44501,7 @@ pub fn svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44514,7 +44514,7 @@ pub fn svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44527,7 +44527,7 @@ pub fn svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44536,7 +44536,7 @@ pub fn svzip1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44545,7 +44545,7 @@ pub fn svzip1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44554,7 +44554,7 @@ pub fn svzip1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave elements from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44563,7 +44563,7 @@ pub fn svzip1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44576,7 +44576,7 @@ pub fn svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44589,7 +44589,7 @@ pub fn svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44602,7 +44602,7 @@ pub fn svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44615,7 +44615,7 @@ pub fn svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44628,7 +44628,7 @@ pub fn svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44641,7 +44641,7 @@ pub fn svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44650,7 +44650,7 @@ pub fn svzip1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44659,7 +44659,7 @@ pub fn svzip1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44668,7 +44668,7 @@ pub fn svzip1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave quadwords from low halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip1))]
@@ -44677,7 +44677,7 @@ pub fn svzip1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44690,7 +44690,7 @@ pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44703,7 +44703,7 @@ pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44716,7 +44716,7 @@ pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44729,7 +44729,7 @@ pub fn svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44742,7 +44742,7 @@ pub fn svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44755,7 +44755,7 @@ pub fn svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44768,7 +44768,7 @@ pub fn svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44781,7 +44781,7 @@ pub fn svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44794,7 +44794,7 @@ pub fn svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44807,7 +44807,7 @@ pub fn svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44816,7 +44816,7 @@ pub fn svzip2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44825,7 +44825,7 @@ pub fn svzip2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44834,7 +44834,7 @@ pub fn svzip2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave elements from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44843,7 +44843,7 @@ pub fn svzip2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44856,7 +44856,7 @@ pub fn svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44869,7 +44869,7 @@ pub fn svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44882,7 +44882,7 @@ pub fn svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44895,7 +44895,7 @@ pub fn svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44908,7 +44908,7 @@ pub fn svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44921,7 +44921,7 @@ pub fn svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44930,7 +44930,7 @@ pub fn svzip2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44939,7 +44939,7 @@ pub fn svzip2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
@@ -44948,7 +44948,7 @@ pub fn svzip2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Interleave quadwords from high halves of two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,f64mm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(zip2))]
diff --git a/crates/core_arch/src/aarch64/sve2/generated.rs b/crates/core_arch/src/aarch64/sve2/generated.rs
index c5b0149c9c..e11c20e5dd 100644
--- a/crates/core_arch/src/aarch64/sve2/generated.rs
+++ b/crates/core_arch/src/aarch64/sve2/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -27,7 +27,7 @@ pub fn svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -36,7 +36,7 @@ pub fn svaba_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -49,7 +49,7 @@ pub fn svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -58,7 +58,7 @@ pub fn svaba_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -71,7 +71,7 @@ pub fn svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -80,7 +80,7 @@ pub fn svaba_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -93,7 +93,7 @@ pub fn svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saba))]
@@ -102,7 +102,7 @@ pub fn svaba_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -115,7 +115,7 @@ pub fn svaba_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -124,7 +124,7 @@ pub fn svaba_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -137,7 +137,7 @@ pub fn svaba_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -146,7 +146,7 @@ pub fn svaba_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -159,7 +159,7 @@ pub fn svaba_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -168,7 +168,7 @@ pub fn svaba_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -181,7 +181,7 @@ pub fn svaba_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_
 }
 #[doc = "Absolute difference and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaba))]
@@ -190,7 +190,7 @@ pub fn svaba_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalb))]
@@ -203,7 +203,7 @@ pub fn svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalb))]
@@ -212,7 +212,7 @@ pub fn svabalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalb))]
@@ -225,7 +225,7 @@ pub fn svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalb))]
@@ -234,7 +234,7 @@ pub fn svabalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalb))]
@@ -247,7 +247,7 @@ pub fn svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalb))]
@@ -256,7 +256,7 @@ pub fn svabalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalb))]
@@ -269,7 +269,7 @@ pub fn svabalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalb))]
@@ -278,7 +278,7 @@ pub fn svabalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalb))]
@@ -291,7 +291,7 @@ pub fn svabalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint3
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalb))]
@@ -300,7 +300,7 @@ pub fn svabalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalb))]
@@ -313,7 +313,7 @@ pub fn svabalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint6
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalb))]
@@ -322,7 +322,7 @@ pub fn svabalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalt))]
@@ -335,7 +335,7 @@ pub fn svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalt))]
@@ -344,7 +344,7 @@ pub fn svabalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalt))]
@@ -357,7 +357,7 @@ pub fn svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalt))]
@@ -366,7 +366,7 @@ pub fn svabalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalt))]
@@ -379,7 +379,7 @@ pub fn svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabalt))]
@@ -388,7 +388,7 @@ pub fn svabalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalt))]
@@ -401,7 +401,7 @@ pub fn svabalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalt))]
@@ -410,7 +410,7 @@ pub fn svabalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalt))]
@@ -423,7 +423,7 @@ pub fn svabalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint3
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalt))]
@@ -432,7 +432,7 @@ pub fn svabalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalt))]
@@ -445,7 +445,7 @@ pub fn svabalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint6
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabalt))]
@@ -454,7 +454,7 @@ pub fn svabalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlb))]
@@ -467,7 +467,7 @@ pub fn svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlb))]
@@ -476,7 +476,7 @@ pub fn svabdlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlb))]
@@ -489,7 +489,7 @@ pub fn svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlb))]
@@ -498,7 +498,7 @@ pub fn svabdlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlb))]
@@ -511,7 +511,7 @@ pub fn svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlb))]
@@ -520,7 +520,7 @@ pub fn svabdlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlb))]
@@ -533,7 +533,7 @@ pub fn svabdlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlb))]
@@ -542,7 +542,7 @@ pub fn svabdlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlb))]
@@ -555,7 +555,7 @@ pub fn svabdlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlb))]
@@ -564,7 +564,7 @@ pub fn svabdlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlb))]
@@ -577,7 +577,7 @@ pub fn svabdlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Absolute difference long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlb))]
@@ -586,7 +586,7 @@ pub fn svabdlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlt))]
@@ -599,7 +599,7 @@ pub fn svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlt))]
@@ -608,7 +608,7 @@ pub fn svabdlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlt))]
@@ -621,7 +621,7 @@ pub fn svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlt))]
@@ -630,7 +630,7 @@ pub fn svabdlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlt))]
@@ -643,7 +643,7 @@ pub fn svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sabdlt))]
@@ -652,7 +652,7 @@ pub fn svabdlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlt))]
@@ -665,7 +665,7 @@ pub fn svabdlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlt))]
@@ -674,7 +674,7 @@ pub fn svabdlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlt))]
@@ -687,7 +687,7 @@ pub fn svabdlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlt))]
@@ -696,7 +696,7 @@ pub fn svabdlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlt))]
@@ -709,7 +709,7 @@ pub fn svabdlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Absolute difference long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uabdlt))]
@@ -718,7 +718,7 @@ pub fn svabdlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -731,7 +731,7 @@ pub fn svadalp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -740,7 +740,7 @@ pub fn svadalp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -749,7 +749,7 @@ pub fn svadalp_s16_z(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -762,7 +762,7 @@ pub fn svadalp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -771,7 +771,7 @@ pub fn svadalp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -780,7 +780,7 @@ pub fn svadalp_s32_z(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -793,7 +793,7 @@ pub fn svadalp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -802,7 +802,7 @@ pub fn svadalp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sadalp))]
@@ -811,7 +811,7 @@ pub fn svadalp_s64_z(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -824,7 +824,7 @@ pub fn svadalp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -833,7 +833,7 @@ pub fn svadalp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -842,7 +842,7 @@ pub fn svadalp_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -855,7 +855,7 @@ pub fn svadalp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -864,7 +864,7 @@ pub fn svadalp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -873,7 +873,7 @@ pub fn svadalp_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -886,7 +886,7 @@ pub fn svadalp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -895,7 +895,7 @@ pub fn svadalp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64
 }
 #[doc = "Add and accumulate long pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uadalp))]
@@ -904,7 +904,7 @@ pub fn svadalp_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64
 }
 #[doc = "Add with carry long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclb))]
@@ -917,7 +917,7 @@ pub fn svadclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint3
 }
 #[doc = "Add with carry long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclb))]
@@ -926,7 +926,7 @@ pub fn svadclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Add with carry long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclb))]
@@ -939,7 +939,7 @@ pub fn svadclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint6
 }
 #[doc = "Add with carry long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclb))]
@@ -948,7 +948,7 @@ pub fn svadclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Add with carry long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclt))]
@@ -961,7 +961,7 @@ pub fn svadclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint3
 }
 #[doc = "Add with carry long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclt))]
@@ -970,7 +970,7 @@ pub fn svadclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Add with carry long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclt))]
@@ -983,7 +983,7 @@ pub fn svadclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint6
 }
 #[doc = "Add with carry long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(adclt))]
@@ -992,7 +992,7 @@ pub fn svadclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1005,7 +1005,7 @@ pub fn svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1014,7 +1014,7 @@ pub fn svaddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1027,7 +1027,7 @@ pub fn svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1036,7 +1036,7 @@ pub fn svaddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1049,7 +1049,7 @@ pub fn svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1058,7 +1058,7 @@ pub fn svaddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1067,7 +1067,7 @@ pub fn svaddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1076,7 +1076,7 @@ pub fn svaddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1085,7 +1085,7 @@ pub fn svaddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1094,7 +1094,7 @@ pub fn svaddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1103,7 +1103,7 @@ pub fn svaddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
 }
 #[doc = "Add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnb))]
@@ -1112,7 +1112,7 @@ pub fn svaddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1125,7 +1125,7 @@ pub fn svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1134,7 +1134,7 @@ pub fn svaddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1147,7 +1147,7 @@ pub fn svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1156,7 +1156,7 @@ pub fn svaddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1169,7 +1169,7 @@ pub fn svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1178,7 +1178,7 @@ pub fn svaddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1187,7 +1187,7 @@ pub fn svaddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1196,7 +1196,7 @@ pub fn svaddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t {
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1205,7 +1205,7 @@ pub fn svaddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuin
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1214,7 +1214,7 @@ pub fn svaddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1223,7 +1223,7 @@ pub fn svaddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addhnt))]
@@ -1232,7 +1232,7 @@ pub fn svaddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlb))]
@@ -1245,7 +1245,7 @@ pub fn svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlb))]
@@ -1254,7 +1254,7 @@ pub fn svaddlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlb))]
@@ -1267,7 +1267,7 @@ pub fn svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlb))]
@@ -1276,7 +1276,7 @@ pub fn svaddlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlb))]
@@ -1289,7 +1289,7 @@ pub fn svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlb))]
@@ -1298,7 +1298,7 @@ pub fn svaddlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlb))]
@@ -1311,7 +1311,7 @@ pub fn svaddlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlb))]
@@ -1320,7 +1320,7 @@ pub fn svaddlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlb))]
@@ -1333,7 +1333,7 @@ pub fn svaddlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlb))]
@@ -1342,7 +1342,7 @@ pub fn svaddlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlb))]
@@ -1355,7 +1355,7 @@ pub fn svaddlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlb))]
@@ -1364,7 +1364,7 @@ pub fn svaddlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Add long (bottom + top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlbt))]
@@ -1380,7 +1380,7 @@ pub fn svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add long (bottom + top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlbt))]
@@ -1389,7 +1389,7 @@ pub fn svaddlbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Add long (bottom + top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlbt))]
@@ -1405,7 +1405,7 @@ pub fn svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Add long (bottom + top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlbt))]
@@ -1414,7 +1414,7 @@ pub fn svaddlbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Add long (bottom + top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlbt))]
@@ -1430,7 +1430,7 @@ pub fn svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Add long (bottom + top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlbt))]
@@ -1439,7 +1439,7 @@ pub fn svaddlbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlt))]
@@ -1452,7 +1452,7 @@ pub fn svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlt))]
@@ -1461,7 +1461,7 @@ pub fn svaddlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlt))]
@@ -1474,7 +1474,7 @@ pub fn svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlt))]
@@ -1483,7 +1483,7 @@ pub fn svaddlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlt))]
@@ -1496,7 +1496,7 @@ pub fn svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddlt))]
@@ -1505,7 +1505,7 @@ pub fn svaddlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlt))]
@@ -1518,7 +1518,7 @@ pub fn svaddlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlt))]
@@ -1527,7 +1527,7 @@ pub fn svaddlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlt))]
@@ -1540,7 +1540,7 @@ pub fn svaddlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlt))]
@@ -1549,7 +1549,7 @@ pub fn svaddlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlt))]
@@ -1562,7 +1562,7 @@ pub fn svaddlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddlt))]
@@ -1571,7 +1571,7 @@ pub fn svaddlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -1584,7 +1584,7 @@ pub fn svaddp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -1593,7 +1593,7 @@ pub fn svaddp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -1606,7 +1606,7 @@ pub fn svaddp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -1615,7 +1615,7 @@ pub fn svaddp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1628,7 +1628,7 @@ pub fn svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1637,7 +1637,7 @@ pub fn svaddp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1650,7 +1650,7 @@ pub fn svaddp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1659,7 +1659,7 @@ pub fn svaddp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1672,7 +1672,7 @@ pub fn svaddp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1681,7 +1681,7 @@ pub fn svaddp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1694,7 +1694,7 @@ pub fn svaddp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1703,7 +1703,7 @@ pub fn svaddp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1712,7 +1712,7 @@ pub fn svaddp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1721,7 +1721,7 @@ pub fn svaddp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1730,7 +1730,7 @@ pub fn svaddp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1739,7 +1739,7 @@ pub fn svaddp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1748,7 +1748,7 @@ pub fn svaddp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1757,7 +1757,7 @@ pub fn svaddp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1766,7 +1766,7 @@ pub fn svaddp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -1775,7 +1775,7 @@ pub fn svaddp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwb))]
@@ -1788,7 +1788,7 @@ pub fn svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwb))]
@@ -1797,7 +1797,7 @@ pub fn svaddwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwb))]
@@ -1810,7 +1810,7 @@ pub fn svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwb))]
@@ -1819,7 +1819,7 @@ pub fn svaddwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwb))]
@@ -1832,7 +1832,7 @@ pub fn svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwb))]
@@ -1841,7 +1841,7 @@ pub fn svaddwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwb))]
@@ -1854,7 +1854,7 @@ pub fn svaddwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwb))]
@@ -1863,7 +1863,7 @@ pub fn svaddwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwb))]
@@ -1876,7 +1876,7 @@ pub fn svaddwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwb))]
@@ -1885,7 +1885,7 @@ pub fn svaddwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwb))]
@@ -1898,7 +1898,7 @@ pub fn svaddwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Add wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwb))]
@@ -1907,7 +1907,7 @@ pub fn svaddwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwt))]
@@ -1920,7 +1920,7 @@ pub fn svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwt))]
@@ -1929,7 +1929,7 @@ pub fn svaddwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwt))]
@@ -1942,7 +1942,7 @@ pub fn svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwt))]
@@ -1951,7 +1951,7 @@ pub fn svaddwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwt))]
@@ -1964,7 +1964,7 @@ pub fn svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(saddwt))]
@@ -1973,7 +1973,7 @@ pub fn svaddwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwt))]
@@ -1986,7 +1986,7 @@ pub fn svaddwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwt))]
@@ -1995,7 +1995,7 @@ pub fn svaddwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwt))]
@@ -2008,7 +2008,7 @@ pub fn svaddwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwt))]
@@ -2017,7 +2017,7 @@ pub fn svaddwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwt))]
@@ -2030,7 +2030,7 @@ pub fn svaddwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Add wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uaddwt))]
@@ -2039,7 +2039,7 @@ pub fn svaddwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
 }
 #[doc = "AES single round decryption"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesd[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(aesd))]
@@ -2052,7 +2052,7 @@ pub fn svaesd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "AES single round encryption"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaese[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(aese))]
@@ -2065,7 +2065,7 @@ pub fn svaese_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "AES inverse mix columns"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesimc[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(aesimc))]
@@ -2078,7 +2078,7 @@ pub fn svaesimc_u8(op: svuint8_t) -> svuint8_t {
 }
 #[doc = "AES mix columns"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesmc[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(aesmc))]
@@ -2091,7 +2091,7 @@ pub fn svaesmc_u8(op: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2104,7 +2104,7 @@ pub fn svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2113,7 +2113,7 @@ pub fn svbcax_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2126,7 +2126,7 @@ pub fn svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2135,7 +2135,7 @@ pub fn svbcax_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2148,7 +2148,7 @@ pub fn svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2157,7 +2157,7 @@ pub fn svbcax_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2170,7 +2170,7 @@ pub fn svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2179,7 +2179,7 @@ pub fn svbcax_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2188,7 +2188,7 @@ pub fn svbcax_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2197,7 +2197,7 @@ pub fn svbcax_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2206,7 +2206,7 @@ pub fn svbcax_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2215,7 +2215,7 @@ pub fn svbcax_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2224,7 +2224,7 @@ pub fn svbcax_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2233,7 +2233,7 @@ pub fn svbcax_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2242,7 +2242,7 @@ pub fn svbcax_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64
 }
 #[doc = "Bitwise clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -2251,7 +2251,7 @@ pub fn svbcax_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2264,7 +2264,7 @@ pub fn svbdep_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2273,7 +2273,7 @@ pub fn svbdep_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2286,7 +2286,7 @@ pub fn svbdep_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2295,7 +2295,7 @@ pub fn svbdep_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2308,7 +2308,7 @@ pub fn svbdep_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2317,7 +2317,7 @@ pub fn svbdep_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2330,7 +2330,7 @@ pub fn svbdep_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Scatter lower bits into positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bdep))]
@@ -2339,7 +2339,7 @@ pub fn svbdep_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2352,7 +2352,7 @@ pub fn svbext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2361,7 +2361,7 @@ pub fn svbext_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2374,7 +2374,7 @@ pub fn svbext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2383,7 +2383,7 @@ pub fn svbext_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2396,7 +2396,7 @@ pub fn svbext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2405,7 +2405,7 @@ pub fn svbext_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2418,7 +2418,7 @@ pub fn svbext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Gather lower bits from positions selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bext))]
@@ -2427,7 +2427,7 @@ pub fn svbext_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2440,7 +2440,7 @@ pub fn svbgrp_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2449,7 +2449,7 @@ pub fn svbgrp_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2462,7 +2462,7 @@ pub fn svbgrp_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2471,7 +2471,7 @@ pub fn svbgrp_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2484,7 +2484,7 @@ pub fn svbgrp_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2493,7 +2493,7 @@ pub fn svbgrp_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2506,7 +2506,7 @@ pub fn svbgrp_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Group bits to right or left as selected by bitmask"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-bitperm")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bgrp))]
@@ -2515,7 +2515,7 @@ pub fn svbgrp_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2528,7 +2528,7 @@ pub fn svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2537,7 +2537,7 @@ pub fn svbsl1n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2550,7 +2550,7 @@ pub fn svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2559,7 +2559,7 @@ pub fn svbsl1n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2572,7 +2572,7 @@ pub fn svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2581,7 +2581,7 @@ pub fn svbsl1n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2594,7 +2594,7 @@ pub fn svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2603,7 +2603,7 @@ pub fn svbsl1n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2612,7 +2612,7 @@ pub fn svbsl1n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2621,7 +2621,7 @@ pub fn svbsl1n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2630,7 +2630,7 @@ pub fn svbsl1n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint1
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2639,7 +2639,7 @@ pub fn svbsl1n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2648,7 +2648,7 @@ pub fn svbsl1n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint3
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2657,7 +2657,7 @@ pub fn svbsl1n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2666,7 +2666,7 @@ pub fn svbsl1n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint6
 }
 #[doc = "Bitwise select with first input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl1n))]
@@ -2675,7 +2675,7 @@ pub fn svbsl1n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2688,7 +2688,7 @@ pub fn svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2697,7 +2697,7 @@ pub fn svbsl2n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2710,7 +2710,7 @@ pub fn svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2719,7 +2719,7 @@ pub fn svbsl2n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2732,7 +2732,7 @@ pub fn svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2741,7 +2741,7 @@ pub fn svbsl2n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2754,7 +2754,7 @@ pub fn svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2763,7 +2763,7 @@ pub fn svbsl2n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2772,7 +2772,7 @@ pub fn svbsl2n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2781,7 +2781,7 @@ pub fn svbsl2n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2790,7 +2790,7 @@ pub fn svbsl2n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint1
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2799,7 +2799,7 @@ pub fn svbsl2n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2808,7 +2808,7 @@ pub fn svbsl2n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint3
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2817,7 +2817,7 @@ pub fn svbsl2n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2826,7 +2826,7 @@ pub fn svbsl2n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint6
 }
 #[doc = "Bitwise select with second input inverted"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl2n))]
@@ -2835,7 +2835,7 @@ pub fn svbsl2n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2848,7 +2848,7 @@ pub fn svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2857,7 +2857,7 @@ pub fn svbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2870,7 +2870,7 @@ pub fn svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2879,7 +2879,7 @@ pub fn svbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2892,7 +2892,7 @@ pub fn svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2901,7 +2901,7 @@ pub fn svbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2914,7 +2914,7 @@ pub fn svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2923,7 +2923,7 @@ pub fn svbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2932,7 +2932,7 @@ pub fn svbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2941,7 +2941,7 @@ pub fn svbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2950,7 +2950,7 @@ pub fn svbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2959,7 +2959,7 @@ pub fn svbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2968,7 +2968,7 @@ pub fn svbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2977,7 +2977,7 @@ pub fn svbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2986,7 +2986,7 @@ pub fn svbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(bsl))]
@@ -2995,7 +2995,7 @@ pub fn svbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3009,7 +3009,7 @@ pub fn svcadd_s8<const IMM_ROTATION: i32>(op1: svint8_t, op2: svint8_t) -> svint
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3023,7 +3023,7 @@ pub fn svcadd_s16<const IMM_ROTATION: i32>(op1: svint16_t, op2: svint16_t) -> sv
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3037,7 +3037,7 @@ pub fn svcadd_s32<const IMM_ROTATION: i32>(op1: svint32_t, op2: svint32_t) -> sv
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3051,7 +3051,7 @@ pub fn svcadd_s64<const IMM_ROTATION: i32>(op1: svint64_t, op2: svint64_t) -> sv
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3061,7 +3061,7 @@ pub fn svcadd_u8<const IMM_ROTATION: i32>(op1: svuint8_t, op2: svuint8_t) -> svu
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3071,7 +3071,7 @@ pub fn svcadd_u16<const IMM_ROTATION: i32>(op1: svuint16_t, op2: svuint16_t) ->
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3081,7 +3081,7 @@ pub fn svcadd_u32<const IMM_ROTATION: i32>(op1: svuint32_t, op2: svuint32_t) ->
 }
 #[doc = "Complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))]
@@ -3091,7 +3091,7 @@ pub fn svcadd_u64<const IMM_ROTATION: i32>(op1: svuint64_t, op2: svuint64_t) ->
 }
 #[doc = "Complex dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -3121,7 +3121,7 @@ pub fn svcdot_lane_s32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Complex dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -3151,7 +3151,7 @@ pub fn svcdot_lane_s64<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Complex dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))]
@@ -3176,7 +3176,7 @@ pub fn svcdot_s32<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex dot product"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))]
@@ -3201,7 +3201,7 @@ pub fn svcdot_s64<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -3231,7 +3231,7 @@ pub fn svcmla_lane_s16<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -3261,7 +3261,7 @@ pub fn svcmla_lane_s32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -3285,7 +3285,7 @@ pub fn svcmla_lane_u16<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -3309,7 +3309,7 @@ pub fn svcmla_lane_u32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3325,7 +3325,7 @@ pub fn svcmla_s8<const IMM_ROTATION: i32>(op1: svint8_t, op2: svint8_t, op3: svi
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3350,7 +3350,7 @@ pub fn svcmla_s16<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3375,7 +3375,7 @@ pub fn svcmla_s32<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3400,7 +3400,7 @@ pub fn svcmla_s64<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3418,7 +3418,7 @@ pub fn svcmla_u8<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3436,7 +3436,7 @@ pub fn svcmla_u16<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3454,7 +3454,7 @@ pub fn svcmla_u32<const IMM_ROTATION: i32>(
 }
 #[doc = "Complex multiply-add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))]
@@ -3472,7 +3472,7 @@ pub fn svcmla_u64<const IMM_ROTATION: i32>(
 }
 #[doc = "Up convert long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtlt))]
@@ -3486,7 +3486,7 @@ pub fn svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -
 }
 #[doc = "Up convert long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtlt))]
@@ -3495,7 +3495,7 @@ pub fn svcvtlt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t {
 }
 #[doc = "Down convert and narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtnt))]
@@ -3508,7 +3508,7 @@ pub fn svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Down convert and narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtnt))]
@@ -3517,7 +3517,7 @@ pub fn svcvtnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> sv
 }
 #[doc = "Down convert, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtx))]
@@ -3530,7 +3530,7 @@ pub fn svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) ->
 }
 #[doc = "Down convert, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtx))]
@@ -3539,7 +3539,7 @@ pub fn svcvtx_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
 }
 #[doc = "Down convert, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtx))]
@@ -3548,7 +3548,7 @@ pub fn svcvtx_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t {
 }
 #[doc = "Down convert, rounding to odd (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtxnt))]
@@ -3561,7 +3561,7 @@ pub fn svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> s
 }
 #[doc = "Down convert, rounding to odd (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fcvtxnt))]
@@ -3570,7 +3570,7 @@ pub fn svcvtxnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> s
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3583,7 +3583,7 @@ pub fn sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3592,7 +3592,7 @@ pub fn sveor3_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3605,7 +3605,7 @@ pub fn sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3614,7 +3614,7 @@ pub fn sveor3_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3627,7 +3627,7 @@ pub fn sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3636,7 +3636,7 @@ pub fn sveor3_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3649,7 +3649,7 @@ pub fn sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3658,7 +3658,7 @@ pub fn sveor3_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3667,7 +3667,7 @@ pub fn sveor3_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3676,7 +3676,7 @@ pub fn sveor3_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3685,7 +3685,7 @@ pub fn sveor3_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3694,7 +3694,7 @@ pub fn sveor3_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3703,7 +3703,7 @@ pub fn sveor3_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3712,7 +3712,7 @@ pub fn sveor3_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3721,7 +3721,7 @@ pub fn sveor3_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64
 }
 #[doc = "Bitwise exclusive OR of three vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -3730,7 +3730,7 @@ pub fn sveor3_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3743,7 +3743,7 @@ pub fn sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3752,7 +3752,7 @@ pub fn sveorbt_n_s8(odd: svint8_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3765,7 +3765,7 @@ pub fn sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3774,7 +3774,7 @@ pub fn sveorbt_n_s16(odd: svint16_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3787,7 +3787,7 @@ pub fn sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3796,7 +3796,7 @@ pub fn sveorbt_n_s32(odd: svint32_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3809,7 +3809,7 @@ pub fn sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3818,7 +3818,7 @@ pub fn sveorbt_n_s64(odd: svint64_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3827,7 +3827,7 @@ pub fn sveorbt_u8(odd: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3836,7 +3836,7 @@ pub fn sveorbt_n_u8(odd: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3845,7 +3845,7 @@ pub fn sveorbt_u16(odd: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint1
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3854,7 +3854,7 @@ pub fn sveorbt_n_u16(odd: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3863,7 +3863,7 @@ pub fn sveorbt_u32(odd: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint3
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3872,7 +3872,7 @@ pub fn sveorbt_n_u32(odd: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3881,7 +3881,7 @@ pub fn sveorbt_u64(odd: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint6
 }
 #[doc = "Interleaving exclusive OR (bottom, top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eorbt))]
@@ -3890,7 +3890,7 @@ pub fn sveorbt_n_u64(odd: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3903,7 +3903,7 @@ pub fn sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3912,7 +3912,7 @@ pub fn sveortb_n_s8(even: svint8_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3925,7 +3925,7 @@ pub fn sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3934,7 +3934,7 @@ pub fn sveortb_n_s16(even: svint16_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3947,7 +3947,7 @@ pub fn sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3956,7 +3956,7 @@ pub fn sveortb_n_s32(even: svint32_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3969,7 +3969,7 @@ pub fn sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3978,7 +3978,7 @@ pub fn sveortb_n_s64(even: svint64_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3987,7 +3987,7 @@ pub fn sveortb_u8(even: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -3996,7 +3996,7 @@ pub fn sveortb_n_u8(even: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -4005,7 +4005,7 @@ pub fn sveortb_u16(even: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -4014,7 +4014,7 @@ pub fn sveortb_n_u16(even: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -4023,7 +4023,7 @@ pub fn sveortb_u32(even: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -4032,7 +4032,7 @@ pub fn sveortb_n_u32(even: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -4041,7 +4041,7 @@ pub fn sveortb_u64(even: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint
 }
 #[doc = "Interleaving exclusive OR (top, bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(eortb))]
@@ -4050,7 +4050,7 @@ pub fn sveortb_n_u64(even: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4063,7 +4063,7 @@ pub fn svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4072,7 +4072,7 @@ pub fn svhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4081,7 +4081,7 @@ pub fn svhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4090,7 +4090,7 @@ pub fn svhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4099,7 +4099,7 @@ pub fn svhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4108,7 +4108,7 @@ pub fn svhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4121,7 +4121,7 @@ pub fn svhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4130,7 +4130,7 @@ pub fn svhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4139,7 +4139,7 @@ pub fn svhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4148,7 +4148,7 @@ pub fn svhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4157,7 +4157,7 @@ pub fn svhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4166,7 +4166,7 @@ pub fn svhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4179,7 +4179,7 @@ pub fn svhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4188,7 +4188,7 @@ pub fn svhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4197,7 +4197,7 @@ pub fn svhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4206,7 +4206,7 @@ pub fn svhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4215,7 +4215,7 @@ pub fn svhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4224,7 +4224,7 @@ pub fn svhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4237,7 +4237,7 @@ pub fn svhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4246,7 +4246,7 @@ pub fn svhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4255,7 +4255,7 @@ pub fn svhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4264,7 +4264,7 @@ pub fn svhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4273,7 +4273,7 @@ pub fn svhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shadd))]
@@ -4282,7 +4282,7 @@ pub fn svhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4295,7 +4295,7 @@ pub fn svhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4304,7 +4304,7 @@ pub fn svhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4313,7 +4313,7 @@ pub fn svhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4322,7 +4322,7 @@ pub fn svhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4331,7 +4331,7 @@ pub fn svhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4340,7 +4340,7 @@ pub fn svhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4353,7 +4353,7 @@ pub fn svhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4362,7 +4362,7 @@ pub fn svhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4371,7 +4371,7 @@ pub fn svhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4380,7 +4380,7 @@ pub fn svhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4389,7 +4389,7 @@ pub fn svhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4398,7 +4398,7 @@ pub fn svhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4411,7 +4411,7 @@ pub fn svhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4420,7 +4420,7 @@ pub fn svhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4429,7 +4429,7 @@ pub fn svhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4438,7 +4438,7 @@ pub fn svhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4447,7 +4447,7 @@ pub fn svhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4456,7 +4456,7 @@ pub fn svhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4469,7 +4469,7 @@ pub fn svhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4478,7 +4478,7 @@ pub fn svhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4487,7 +4487,7 @@ pub fn svhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4496,7 +4496,7 @@ pub fn svhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4505,7 +4505,7 @@ pub fn svhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhadd))]
@@ -4514,7 +4514,7 @@ pub fn svhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Count matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(histcnt))]
@@ -4530,7 +4530,7 @@ pub fn svhistcnt_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svuint32
 }
 #[doc = "Count matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(histcnt))]
@@ -4546,7 +4546,7 @@ pub fn svhistcnt_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svuint64
 }
 #[doc = "Count matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(histcnt))]
@@ -4555,7 +4555,7 @@ pub fn svhistcnt_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint
 }
 #[doc = "Count matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(histcnt))]
@@ -4564,7 +4564,7 @@ pub fn svhistcnt_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint
 }
 #[doc = "Count matching elements in 128-bit segments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(histseg))]
@@ -4580,7 +4580,7 @@ pub fn svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Count matching elements in 128-bit segments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(histseg))]
@@ -4589,7 +4589,7 @@ pub fn svhistseg_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4602,7 +4602,7 @@ pub fn svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4611,7 +4611,7 @@ pub fn svhsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4620,7 +4620,7 @@ pub fn svhsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4629,7 +4629,7 @@ pub fn svhsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4638,7 +4638,7 @@ pub fn svhsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4647,7 +4647,7 @@ pub fn svhsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4660,7 +4660,7 @@ pub fn svhsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4669,7 +4669,7 @@ pub fn svhsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4678,7 +4678,7 @@ pub fn svhsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4687,7 +4687,7 @@ pub fn svhsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4696,7 +4696,7 @@ pub fn svhsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4705,7 +4705,7 @@ pub fn svhsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4718,7 +4718,7 @@ pub fn svhsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4727,7 +4727,7 @@ pub fn svhsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4736,7 +4736,7 @@ pub fn svhsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4745,7 +4745,7 @@ pub fn svhsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4754,7 +4754,7 @@ pub fn svhsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4763,7 +4763,7 @@ pub fn svhsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4776,7 +4776,7 @@ pub fn svhsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4785,7 +4785,7 @@ pub fn svhsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4794,7 +4794,7 @@ pub fn svhsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4803,7 +4803,7 @@ pub fn svhsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4812,7 +4812,7 @@ pub fn svhsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -4821,7 +4821,7 @@ pub fn svhsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4834,7 +4834,7 @@ pub fn svhsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4843,7 +4843,7 @@ pub fn svhsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4852,7 +4852,7 @@ pub fn svhsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4861,7 +4861,7 @@ pub fn svhsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4870,7 +4870,7 @@ pub fn svhsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4879,7 +4879,7 @@ pub fn svhsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4892,7 +4892,7 @@ pub fn svhsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4901,7 +4901,7 @@ pub fn svhsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4910,7 +4910,7 @@ pub fn svhsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4919,7 +4919,7 @@ pub fn svhsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4928,7 +4928,7 @@ pub fn svhsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4937,7 +4937,7 @@ pub fn svhsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4950,7 +4950,7 @@ pub fn svhsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4959,7 +4959,7 @@ pub fn svhsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4968,7 +4968,7 @@ pub fn svhsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4977,7 +4977,7 @@ pub fn svhsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4986,7 +4986,7 @@ pub fn svhsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -4995,7 +4995,7 @@ pub fn svhsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5008,7 +5008,7 @@ pub fn svhsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5017,7 +5017,7 @@ pub fn svhsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5026,7 +5026,7 @@ pub fn svhsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5035,7 +5035,7 @@ pub fn svhsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5044,7 +5044,7 @@ pub fn svhsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5053,7 +5053,7 @@ pub fn svhsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5066,7 +5066,7 @@ pub fn svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5075,7 +5075,7 @@ pub fn svhsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5084,7 +5084,7 @@ pub fn svhsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5093,7 +5093,7 @@ pub fn svhsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5102,7 +5102,7 @@ pub fn svhsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5111,7 +5111,7 @@ pub fn svhsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5124,7 +5124,7 @@ pub fn svhsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5133,7 +5133,7 @@ pub fn svhsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5142,7 +5142,7 @@ pub fn svhsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5151,7 +5151,7 @@ pub fn svhsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5160,7 +5160,7 @@ pub fn svhsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5169,7 +5169,7 @@ pub fn svhsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5182,7 +5182,7 @@ pub fn svhsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5191,7 +5191,7 @@ pub fn svhsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5200,7 +5200,7 @@ pub fn svhsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5209,7 +5209,7 @@ pub fn svhsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5218,7 +5218,7 @@ pub fn svhsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5227,7 +5227,7 @@ pub fn svhsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5240,7 +5240,7 @@ pub fn svhsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5249,7 +5249,7 @@ pub fn svhsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5258,7 +5258,7 @@ pub fn svhsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5267,7 +5267,7 @@ pub fn svhsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5276,7 +5276,7 @@ pub fn svhsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shsub))]
@@ -5285,7 +5285,7 @@ pub fn svhsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5298,7 +5298,7 @@ pub fn svhsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5307,7 +5307,7 @@ pub fn svhsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5316,7 +5316,7 @@ pub fn svhsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5325,7 +5325,7 @@ pub fn svhsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5334,7 +5334,7 @@ pub fn svhsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5343,7 +5343,7 @@ pub fn svhsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5356,7 +5356,7 @@ pub fn svhsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5365,7 +5365,7 @@ pub fn svhsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5374,7 +5374,7 @@ pub fn svhsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5383,7 +5383,7 @@ pub fn svhsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5392,7 +5392,7 @@ pub fn svhsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5401,7 +5401,7 @@ pub fn svhsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5414,7 +5414,7 @@ pub fn svhsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5423,7 +5423,7 @@ pub fn svhsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5432,7 +5432,7 @@ pub fn svhsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5441,7 +5441,7 @@ pub fn svhsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5450,7 +5450,7 @@ pub fn svhsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5459,7 +5459,7 @@ pub fn svhsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5472,7 +5472,7 @@ pub fn svhsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5481,7 +5481,7 @@ pub fn svhsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5490,7 +5490,7 @@ pub fn svhsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5499,7 +5499,7 @@ pub fn svhsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5508,7 +5508,7 @@ pub fn svhsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Halving subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uhsub))]
@@ -5521,7 +5521,7 @@ pub fn svhsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5549,7 +5549,7 @@ pub unsafe fn svldnt1_gather_s64index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5577,7 +5577,7 @@ pub unsafe fn svldnt1_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5594,7 +5594,7 @@ pub unsafe fn svldnt1_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5611,7 +5611,7 @@ pub unsafe fn svldnt1_gather_u64index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5628,7 +5628,7 @@ pub unsafe fn svldnt1_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5645,7 +5645,7 @@ pub unsafe fn svldnt1_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5673,7 +5673,7 @@ pub unsafe fn svldnt1_gather_s64offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5701,7 +5701,7 @@ pub unsafe fn svldnt1_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5718,7 +5718,7 @@ pub unsafe fn svldnt1_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5746,7 +5746,7 @@ pub unsafe fn svldnt1_gather_u32offset_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5774,7 +5774,7 @@ pub unsafe fn svldnt1_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5791,7 +5791,7 @@ pub unsafe fn svldnt1_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5808,7 +5808,7 @@ pub unsafe fn svldnt1_gather_u64offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5825,7 +5825,7 @@ pub unsafe fn svldnt1_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5843,7 +5843,7 @@ pub unsafe fn svldnt1_gather_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5857,7 +5857,7 @@ pub unsafe fn svldnt1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svf
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5871,7 +5871,7 @@ pub unsafe fn svldnt1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svi
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5885,7 +5885,7 @@ pub unsafe fn svldnt1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svu
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5899,7 +5899,7 @@ pub unsafe fn svldnt1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svf
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5913,7 +5913,7 @@ pub unsafe fn svldnt1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svi
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5927,7 +5927,7 @@ pub unsafe fn svldnt1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svu
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5945,7 +5945,7 @@ pub unsafe fn svldnt1_gather_u32base_index_f32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5963,7 +5963,7 @@ pub unsafe fn svldnt1_gather_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -5981,7 +5981,7 @@ pub unsafe fn svldnt1_gather_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -5999,7 +5999,7 @@ pub unsafe fn svldnt1_gather_u64base_index_f64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -6017,7 +6017,7 @@ pub unsafe fn svldnt1_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -6035,7 +6035,7 @@ pub unsafe fn svldnt1_gather_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -6064,7 +6064,7 @@ pub unsafe fn svldnt1_gather_u32base_offset_f32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -6093,7 +6093,7 @@ pub unsafe fn svldnt1_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -6111,7 +6111,7 @@ pub unsafe fn svldnt1_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -6140,7 +6140,7 @@ pub unsafe fn svldnt1_gather_u64base_offset_f64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -6169,7 +6169,7 @@ pub unsafe fn svldnt1_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1d))]
@@ -6186,7 +6186,7 @@ pub unsafe fn svldnt1_gather_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6218,7 +6218,7 @@ pub unsafe fn svldnt1sb_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6250,7 +6250,7 @@ pub unsafe fn svldnt1sh_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6282,7 +6282,7 @@ pub unsafe fn svldnt1sw_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6299,7 +6299,7 @@ pub unsafe fn svldnt1sb_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6316,7 +6316,7 @@ pub unsafe fn svldnt1sh_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6333,7 +6333,7 @@ pub unsafe fn svldnt1sw_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6365,7 +6365,7 @@ pub unsafe fn svldnt1sb_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6397,7 +6397,7 @@ pub unsafe fn svldnt1sh_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6414,7 +6414,7 @@ pub unsafe fn svldnt1sb_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6431,7 +6431,7 @@ pub unsafe fn svldnt1sh_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6448,7 +6448,7 @@ pub unsafe fn svldnt1sb_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6465,7 +6465,7 @@ pub unsafe fn svldnt1sh_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6482,7 +6482,7 @@ pub unsafe fn svldnt1sw_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6499,7 +6499,7 @@ pub unsafe fn svldnt1sb_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6516,7 +6516,7 @@ pub unsafe fn svldnt1sh_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6534,7 +6534,7 @@ pub unsafe fn svldnt1sw_gather_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6567,7 +6567,7 @@ pub unsafe fn svldnt1sb_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6600,7 +6600,7 @@ pub unsafe fn svldnt1sh_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6618,7 +6618,7 @@ pub unsafe fn svldnt1sb_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6636,7 +6636,7 @@ pub unsafe fn svldnt1sh_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6669,7 +6669,7 @@ pub unsafe fn svldnt1sb_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6702,7 +6702,7 @@ pub unsafe fn svldnt1sh_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6735,7 +6735,7 @@ pub unsafe fn svldnt1sw_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6753,7 +6753,7 @@ pub unsafe fn svldnt1sb_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6771,7 +6771,7 @@ pub unsafe fn svldnt1sh_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6789,7 +6789,7 @@ pub unsafe fn svldnt1sw_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6803,7 +6803,7 @@ pub unsafe fn svldnt1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6817,7 +6817,7 @@ pub unsafe fn svldnt1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6831,7 +6831,7 @@ pub unsafe fn svldnt1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6845,7 +6845,7 @@ pub unsafe fn svldnt1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6859,7 +6859,7 @@ pub unsafe fn svldnt1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6873,7 +6873,7 @@ pub unsafe fn svldnt1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6887,7 +6887,7 @@ pub unsafe fn svldnt1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sb))]
@@ -6901,7 +6901,7 @@ pub unsafe fn svldnt1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6915,7 +6915,7 @@ pub unsafe fn svldnt1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6928,7 +6928,7 @@ pub unsafe fn svldnt1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -6956,7 +6956,7 @@ pub unsafe fn svldnt1sh_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -6984,7 +6984,7 @@ pub unsafe fn svldnt1sw_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7001,7 +7001,7 @@ pub unsafe fn svldnt1sh_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -7018,7 +7018,7 @@ pub unsafe fn svldnt1sw_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7035,7 +7035,7 @@ pub unsafe fn svldnt1sh_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -7052,7 +7052,7 @@ pub unsafe fn svldnt1sw_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7069,7 +7069,7 @@ pub unsafe fn svldnt1sh_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -7087,7 +7087,7 @@ pub unsafe fn svldnt1sw_gather_u64index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7105,7 +7105,7 @@ pub unsafe fn svldnt1sh_gather_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7123,7 +7123,7 @@ pub unsafe fn svldnt1sh_gather_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7141,7 +7141,7 @@ pub unsafe fn svldnt1sh_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -7159,7 +7159,7 @@ pub unsafe fn svldnt1sw_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sh))]
@@ -7177,7 +7177,7 @@ pub unsafe fn svldnt1sh_gather_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1sw))]
@@ -7194,7 +7194,7 @@ pub unsafe fn svldnt1sw_gather_u64base_index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7211,7 +7211,7 @@ pub unsafe fn svldnt1ub_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7228,7 +7228,7 @@ pub unsafe fn svldnt1uh_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7245,7 +7245,7 @@ pub unsafe fn svldnt1uw_gather_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7275,7 +7275,7 @@ pub unsafe fn svldnt1ub_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7305,7 +7305,7 @@ pub unsafe fn svldnt1uh_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7335,7 +7335,7 @@ pub unsafe fn svldnt1uw_gather_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7352,7 +7352,7 @@ pub unsafe fn svldnt1ub_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7369,7 +7369,7 @@ pub unsafe fn svldnt1uh_gather_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7400,7 +7400,7 @@ pub unsafe fn svldnt1ub_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7431,7 +7431,7 @@ pub unsafe fn svldnt1uh_gather_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7448,7 +7448,7 @@ pub unsafe fn svldnt1ub_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7465,7 +7465,7 @@ pub unsafe fn svldnt1uh_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7482,7 +7482,7 @@ pub unsafe fn svldnt1uw_gather_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7499,7 +7499,7 @@ pub unsafe fn svldnt1ub_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7516,7 +7516,7 @@ pub unsafe fn svldnt1uh_gather_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7534,7 +7534,7 @@ pub unsafe fn svldnt1uw_gather_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7552,7 +7552,7 @@ pub unsafe fn svldnt1ub_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7570,7 +7570,7 @@ pub unsafe fn svldnt1uh_gather_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7602,7 +7602,7 @@ pub unsafe fn svldnt1ub_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7634,7 +7634,7 @@ pub unsafe fn svldnt1uh_gather_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7652,7 +7652,7 @@ pub unsafe fn svldnt1ub_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7670,7 +7670,7 @@ pub unsafe fn svldnt1uh_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7688,7 +7688,7 @@ pub unsafe fn svldnt1uw_gather_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7720,7 +7720,7 @@ pub unsafe fn svldnt1ub_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7752,7 +7752,7 @@ pub unsafe fn svldnt1uh_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7784,7 +7784,7 @@ pub unsafe fn svldnt1uw_gather_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7798,7 +7798,7 @@ pub unsafe fn svldnt1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7812,7 +7812,7 @@ pub unsafe fn svldnt1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7826,7 +7826,7 @@ pub unsafe fn svldnt1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7840,7 +7840,7 @@ pub unsafe fn svldnt1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7854,7 +7854,7 @@ pub unsafe fn svldnt1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7868,7 +7868,7 @@ pub unsafe fn svldnt1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7882,7 +7882,7 @@ pub unsafe fn svldnt1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1b))]
@@ -7896,7 +7896,7 @@ pub unsafe fn svldnt1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7910,7 +7910,7 @@ pub unsafe fn svldnt1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7923,7 +7923,7 @@ pub unsafe fn svldnt1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> s
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7940,7 +7940,7 @@ pub unsafe fn svldnt1uh_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -7957,7 +7957,7 @@ pub unsafe fn svldnt1uw_gather_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -7987,7 +7987,7 @@ pub unsafe fn svldnt1uh_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -8017,7 +8017,7 @@ pub unsafe fn svldnt1uw_gather_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -8034,7 +8034,7 @@ pub unsafe fn svldnt1uh_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -8051,7 +8051,7 @@ pub unsafe fn svldnt1uw_gather_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -8068,7 +8068,7 @@ pub unsafe fn svldnt1uh_gather_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -8086,7 +8086,7 @@ pub unsafe fn svldnt1uw_gather_u64index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -8104,7 +8104,7 @@ pub unsafe fn svldnt1uh_gather_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -8122,7 +8122,7 @@ pub unsafe fn svldnt1uh_gather_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -8140,7 +8140,7 @@ pub unsafe fn svldnt1uh_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -8158,7 +8158,7 @@ pub unsafe fn svldnt1uw_gather_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1h))]
@@ -8176,7 +8176,7 @@ pub unsafe fn svldnt1uh_gather_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ldnt1w))]
@@ -8189,7 +8189,7 @@ pub unsafe fn svldnt1uw_gather_u64base_index_u64(
 }
 #[doc = "Base 2 logarithm as integer"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(flogb))]
@@ -8202,7 +8202,7 @@ pub fn svlogb_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint
 }
 #[doc = "Base 2 logarithm as integer"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(flogb))]
@@ -8211,7 +8211,7 @@ pub fn svlogb_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t {
 }
 #[doc = "Base 2 logarithm as integer"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(flogb))]
@@ -8220,7 +8220,7 @@ pub fn svlogb_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t {
 }
 #[doc = "Base 2 logarithm as integer"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(flogb))]
@@ -8233,7 +8233,7 @@ pub fn svlogb_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint
 }
 #[doc = "Base 2 logarithm as integer"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(flogb))]
@@ -8242,7 +8242,7 @@ pub fn svlogb_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t {
 }
 #[doc = "Base 2 logarithm as integer"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(flogb))]
@@ -8251,7 +8251,7 @@ pub fn svlogb_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t {
 }
 #[doc = "Detect any matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(match))]
@@ -8264,7 +8264,7 @@ pub fn svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Detect any matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(match))]
@@ -8277,7 +8277,7 @@ pub fn svmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Detect any matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(match))]
@@ -8286,7 +8286,7 @@ pub fn svmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Detect any matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(match))]
@@ -8295,7 +8295,7 @@ pub fn svmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t {
 }
 #[doc = "Maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -8311,7 +8311,7 @@ pub fn svmaxnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svflo
 }
 #[doc = "Maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -8320,7 +8320,7 @@ pub fn svmaxnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svflo
 }
 #[doc = "Maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -8336,7 +8336,7 @@ pub fn svmaxnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svflo
 }
 #[doc = "Maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -8345,7 +8345,7 @@ pub fn svmaxnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svflo
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -8358,7 +8358,7 @@ pub fn svmaxp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -8367,7 +8367,7 @@ pub fn svmaxp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -8380,7 +8380,7 @@ pub fn svmaxp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -8389,7 +8389,7 @@ pub fn svmaxp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8402,7 +8402,7 @@ pub fn svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8411,7 +8411,7 @@ pub fn svmaxp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8424,7 +8424,7 @@ pub fn svmaxp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8433,7 +8433,7 @@ pub fn svmaxp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8446,7 +8446,7 @@ pub fn svmaxp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8455,7 +8455,7 @@ pub fn svmaxp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8468,7 +8468,7 @@ pub fn svmaxp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -8477,7 +8477,7 @@ pub fn svmaxp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8490,7 +8490,7 @@ pub fn svmaxp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8499,7 +8499,7 @@ pub fn svmaxp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8512,7 +8512,7 @@ pub fn svmaxp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8521,7 +8521,7 @@ pub fn svmaxp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8534,7 +8534,7 @@ pub fn svmaxp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8543,7 +8543,7 @@ pub fn svmaxp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8556,7 +8556,7 @@ pub fn svmaxp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -8565,7 +8565,7 @@ pub fn svmaxp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnmp))]
@@ -8581,7 +8581,7 @@ pub fn svminnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svflo
 }
 #[doc = "Minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnmp))]
@@ -8590,7 +8590,7 @@ pub fn svminnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svflo
 }
 #[doc = "Minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnmp))]
@@ -8606,7 +8606,7 @@ pub fn svminnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svflo
 }
 #[doc = "Minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminnmp))]
@@ -8615,7 +8615,7 @@ pub fn svminnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svflo
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -8628,7 +8628,7 @@ pub fn svminp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -8637,7 +8637,7 @@ pub fn svminp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -8650,7 +8650,7 @@ pub fn svminp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -8659,7 +8659,7 @@ pub fn svminp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8672,7 +8672,7 @@ pub fn svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8681,7 +8681,7 @@ pub fn svminp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8694,7 +8694,7 @@ pub fn svminp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8703,7 +8703,7 @@ pub fn svminp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8716,7 +8716,7 @@ pub fn svminp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8725,7 +8725,7 @@ pub fn svminp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8738,7 +8738,7 @@ pub fn svminp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -8747,7 +8747,7 @@ pub fn svminp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8760,7 +8760,7 @@ pub fn svminp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8769,7 +8769,7 @@ pub fn svminp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8782,7 +8782,7 @@ pub fn svminp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8791,7 +8791,7 @@ pub fn svminp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8804,7 +8804,7 @@ pub fn svminp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8813,7 +8813,7 @@ pub fn svminp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8826,7 +8826,7 @@ pub fn svminp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -8835,7 +8835,7 @@ pub fn svminp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
@@ -8861,7 +8861,7 @@ pub fn svmla_lane_s16<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
@@ -8887,7 +8887,7 @@ pub fn svmla_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
@@ -8913,7 +8913,7 @@ pub fn svmla_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
@@ -8929,7 +8929,7 @@ pub fn svmla_lane_u16<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
@@ -8945,7 +8945,7 @@ pub fn svmla_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add, addend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))]
@@ -8961,7 +8961,7 @@ pub fn svmla_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))]
@@ -8987,7 +8987,7 @@ pub fn svmlalb_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))]
@@ -9013,7 +9013,7 @@ pub fn svmlalb_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))]
@@ -9042,7 +9042,7 @@ pub fn svmlalb_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))]
@@ -9071,7 +9071,7 @@ pub fn svmlalb_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb))]
@@ -9084,7 +9084,7 @@ pub fn svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb))]
@@ -9093,7 +9093,7 @@ pub fn svmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb))]
@@ -9106,7 +9106,7 @@ pub fn svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb))]
@@ -9115,7 +9115,7 @@ pub fn svmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb))]
@@ -9128,7 +9128,7 @@ pub fn svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalb))]
@@ -9137,7 +9137,7 @@ pub fn svmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb))]
@@ -9150,7 +9150,7 @@ pub fn svmlalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb))]
@@ -9159,7 +9159,7 @@ pub fn svmlalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb))]
@@ -9172,7 +9172,7 @@ pub fn svmlalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint3
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb))]
@@ -9181,7 +9181,7 @@ pub fn svmlalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb))]
@@ -9194,7 +9194,7 @@ pub fn svmlalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint6
 }
 #[doc = "Multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalb))]
@@ -9203,7 +9203,7 @@ pub fn svmlalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))]
@@ -9229,7 +9229,7 @@ pub fn svmlalt_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))]
@@ -9255,7 +9255,7 @@ pub fn svmlalt_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))]
@@ -9284,7 +9284,7 @@ pub fn svmlalt_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))]
@@ -9313,7 +9313,7 @@ pub fn svmlalt_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt))]
@@ -9326,7 +9326,7 @@ pub fn svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt))]
@@ -9335,7 +9335,7 @@ pub fn svmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt))]
@@ -9348,7 +9348,7 @@ pub fn svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt))]
@@ -9357,7 +9357,7 @@ pub fn svmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt))]
@@ -9370,7 +9370,7 @@ pub fn svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlalt))]
@@ -9379,7 +9379,7 @@ pub fn svmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt))]
@@ -9392,7 +9392,7 @@ pub fn svmlalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt))]
@@ -9401,7 +9401,7 @@ pub fn svmlalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt))]
@@ -9414,7 +9414,7 @@ pub fn svmlalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint3
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt))]
@@ -9423,7 +9423,7 @@ pub fn svmlalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt))]
@@ -9436,7 +9436,7 @@ pub fn svmlalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint6
 }
 #[doc = "Multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlalt))]
@@ -9445,7 +9445,7 @@ pub fn svmlalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
@@ -9471,7 +9471,7 @@ pub fn svmls_lane_s16<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
@@ -9497,7 +9497,7 @@ pub fn svmls_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
@@ -9523,7 +9523,7 @@ pub fn svmls_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
@@ -9539,7 +9539,7 @@ pub fn svmls_lane_u16<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
@@ -9555,7 +9555,7 @@ pub fn svmls_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract, minuend first"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))]
@@ -9571,7 +9571,7 @@ pub fn svmls_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))]
@@ -9597,7 +9597,7 @@ pub fn svmlslb_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))]
@@ -9623,7 +9623,7 @@ pub fn svmlslb_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))]
@@ -9652,7 +9652,7 @@ pub fn svmlslb_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))]
@@ -9681,7 +9681,7 @@ pub fn svmlslb_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb))]
@@ -9694,7 +9694,7 @@ pub fn svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb))]
@@ -9703,7 +9703,7 @@ pub fn svmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb))]
@@ -9716,7 +9716,7 @@ pub fn svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb))]
@@ -9725,7 +9725,7 @@ pub fn svmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb))]
@@ -9738,7 +9738,7 @@ pub fn svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslb))]
@@ -9747,7 +9747,7 @@ pub fn svmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb))]
@@ -9760,7 +9760,7 @@ pub fn svmlslb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb))]
@@ -9769,7 +9769,7 @@ pub fn svmlslb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb))]
@@ -9782,7 +9782,7 @@ pub fn svmlslb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint3
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb))]
@@ -9791,7 +9791,7 @@ pub fn svmlslb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb))]
@@ -9804,7 +9804,7 @@ pub fn svmlslb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint6
 }
 #[doc = "Multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslb))]
@@ -9813,7 +9813,7 @@ pub fn svmlslb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))]
@@ -9839,7 +9839,7 @@ pub fn svmlslt_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))]
@@ -9865,7 +9865,7 @@ pub fn svmlslt_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))]
@@ -9894,7 +9894,7 @@ pub fn svmlslt_lane_u32<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))]
@@ -9923,7 +9923,7 @@ pub fn svmlslt_lane_u64<const IMM_INDEX: i32>(
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt))]
@@ -9936,7 +9936,7 @@ pub fn svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt))]
@@ -9945,7 +9945,7 @@ pub fn svmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt))]
@@ -9958,7 +9958,7 @@ pub fn svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt))]
@@ -9967,7 +9967,7 @@ pub fn svmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt))]
@@ -9980,7 +9980,7 @@ pub fn svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smlslt))]
@@ -9989,7 +9989,7 @@ pub fn svmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt))]
@@ -10002,7 +10002,7 @@ pub fn svmlslt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt))]
@@ -10011,7 +10011,7 @@ pub fn svmlslt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt))]
@@ -10024,7 +10024,7 @@ pub fn svmlslt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint3
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt))]
@@ -10033,7 +10033,7 @@ pub fn svmlslt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t {
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt))]
@@ -10046,7 +10046,7 @@ pub fn svmlslt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint6
 }
 #[doc = "Multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umlslt))]
@@ -10055,7 +10055,7 @@ pub fn svmlslt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t {
 }
 #[doc = "Move long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllb))]
@@ -10064,7 +10064,7 @@ pub fn svmovlb_s16(op: svint8_t) -> svint16_t {
 }
 #[doc = "Move long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllb))]
@@ -10073,7 +10073,7 @@ pub fn svmovlb_s32(op: svint16_t) -> svint32_t {
 }
 #[doc = "Move long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllb))]
@@ -10082,7 +10082,7 @@ pub fn svmovlb_s64(op: svint32_t) -> svint64_t {
 }
 #[doc = "Move long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllb))]
@@ -10091,7 +10091,7 @@ pub fn svmovlb_u16(op: svuint8_t) -> svuint16_t {
 }
 #[doc = "Move long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllb))]
@@ -10100,7 +10100,7 @@ pub fn svmovlb_u32(op: svuint16_t) -> svuint32_t {
 }
 #[doc = "Move long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllb))]
@@ -10109,7 +10109,7 @@ pub fn svmovlb_u64(op: svuint32_t) -> svuint64_t {
 }
 #[doc = "Move long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllt))]
@@ -10118,7 +10118,7 @@ pub fn svmovlt_s16(op: svint8_t) -> svint16_t {
 }
 #[doc = "Move long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllt))]
@@ -10127,7 +10127,7 @@ pub fn svmovlt_s32(op: svint16_t) -> svint32_t {
 }
 #[doc = "Move long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllt))]
@@ -10136,7 +10136,7 @@ pub fn svmovlt_s64(op: svint32_t) -> svint64_t {
 }
 #[doc = "Move long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllt))]
@@ -10145,7 +10145,7 @@ pub fn svmovlt_u16(op: svuint8_t) -> svuint16_t {
 }
 #[doc = "Move long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllt))]
@@ -10154,7 +10154,7 @@ pub fn svmovlt_u32(op: svuint16_t) -> svuint32_t {
 }
 #[doc = "Move long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllt))]
@@ -10163,7 +10163,7 @@ pub fn svmovlt_u64(op: svuint32_t) -> svuint64_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))]
@@ -10180,7 +10180,7 @@ pub fn svmul_lane_f32<const IMM_INDEX: i32>(op1: svfloat32_t, op2: svfloat32_t)
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))]
@@ -10197,7 +10197,7 @@ pub fn svmul_lane_f64<const IMM_INDEX: i32>(op1: svfloat64_t, op2: svfloat64_t)
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
@@ -10214,7 +10214,7 @@ pub fn svmul_lane_s16<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -> s
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
@@ -10231,7 +10231,7 @@ pub fn svmul_lane_s32<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -> s
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
@@ -10248,7 +10248,7 @@ pub fn svmul_lane_s64<const IMM_INDEX: i32>(op1: svint64_t, op2: svint64_t) -> s
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
@@ -10258,7 +10258,7 @@ pub fn svmul_lane_u16<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t) ->
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
@@ -10268,7 +10268,7 @@ pub fn svmul_lane_u32<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t) ->
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))]
@@ -10278,7 +10278,7 @@ pub fn svmul_lane_u64<const IMM_INDEX: i32>(op1: svuint64_t, op2: svuint64_t) ->
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10298,7 +10298,7 @@ pub fn svmullb_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) ->
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10318,7 +10318,7 @@ pub fn svmullb_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) ->
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10338,7 +10338,7 @@ pub fn svmullb_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t)
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10358,7 +10358,7 @@ pub fn svmullb_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t)
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smullb))]
@@ -10371,7 +10371,7 @@ pub fn svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smullb))]
@@ -10380,7 +10380,7 @@ pub fn svmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smullb))]
@@ -10393,7 +10393,7 @@ pub fn svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smullb))]
@@ -10402,7 +10402,7 @@ pub fn svmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smullb))]
@@ -10415,7 +10415,7 @@ pub fn svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(smullb))]
@@ -10424,7 +10424,7 @@ pub fn svmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umullb))]
@@ -10437,7 +10437,7 @@ pub fn svmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umullb))]
@@ -10446,7 +10446,7 @@ pub fn svmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umullb))]
@@ -10459,7 +10459,7 @@ pub fn svmullb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umullb))]
@@ -10468,7 +10468,7 @@ pub fn svmullb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umullb))]
@@ -10481,7 +10481,7 @@ pub fn svmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(umullb))]
@@ -10490,7 +10490,7 @@ pub fn svmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10510,7 +10510,7 @@ pub fn svmullt_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) ->
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10530,7 +10530,7 @@ pub fn svmullt_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) ->
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10550,7 +10550,7 @@ pub fn svmullt_lane_u32<const IMM_INDEX: i32>(op1: svuint16_t, op2: svuint16_t)
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(
@@ -10570,7 +10570,7 @@ pub fn svmullt_lane_u64<const IMM_INDEX: i32>(op1: svuint32_t, op2: svuint32_t)
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
@@ -10583,7 +10583,7 @@ pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
@@ -10592,7 +10592,7 @@ pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
@@ -10605,7 +10605,7 @@ pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
@@ -10614,7 +10614,7 @@ pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
@@ -10627,7 +10627,7 @@ pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))]
@@ -10636,7 +10636,7 @@ pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
@@ -10649,7 +10649,7 @@ pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
@@ -10658,7 +10658,7 @@ pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
@@ -10671,7 +10671,7 @@ pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
@@ -10680,7 +10680,7 @@ pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
@@ -10693,7 +10693,7 @@ pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))]
@@ -10702,7 +10702,7 @@ pub fn svmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10715,7 +10715,7 @@ pub fn svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10724,7 +10724,7 @@ pub fn svnbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10737,7 +10737,7 @@ pub fn svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10746,7 +10746,7 @@ pub fn svnbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10759,7 +10759,7 @@ pub fn svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10768,7 +10768,7 @@ pub fn svnbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10781,7 +10781,7 @@ pub fn svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10790,7 +10790,7 @@ pub fn svnbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10799,7 +10799,7 @@ pub fn svnbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10808,7 +10808,7 @@ pub fn svnbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10817,7 +10817,7 @@ pub fn svnbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10826,7 +10826,7 @@ pub fn svnbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10835,7 +10835,7 @@ pub fn svnbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10844,7 +10844,7 @@ pub fn svnbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10853,7 +10853,7 @@ pub fn svnbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64
 }
 #[doc = "Bitwise select"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nbsl))]
@@ -10862,7 +10862,7 @@ pub fn svnbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Detect no matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nmatch))]
@@ -10875,7 +10875,7 @@ pub fn svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t {
 }
 #[doc = "Detect no matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nmatch))]
@@ -10888,7 +10888,7 @@ pub fn svnmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t {
 }
 #[doc = "Detect no matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nmatch))]
@@ -10897,7 +10897,7 @@ pub fn svnmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t {
 }
 #[doc = "Detect no matching elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(nmatch))]
@@ -10906,7 +10906,7 @@ pub fn svnmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmul))]
@@ -10919,7 +10919,7 @@ pub fn svpmul_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmul))]
@@ -10928,7 +10928,7 @@ pub fn svpmul_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -10944,7 +10944,7 @@ pub fn svpmullb_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -10953,7 +10953,7 @@ pub fn svpmullb_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -10969,7 +10969,7 @@ pub fn svpmullb_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -10978,7 +10978,7 @@ pub fn svpmullb_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -10994,7 +10994,7 @@ pub fn svpmullb_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -11003,7 +11003,7 @@ pub fn svpmullb_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -11012,7 +11012,7 @@ pub fn svpmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -11021,7 +11021,7 @@ pub fn svpmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -11030,7 +11030,7 @@ pub fn svpmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullb))]
@@ -11039,7 +11039,7 @@ pub fn svpmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11055,7 +11055,7 @@ pub fn svpmullt_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11064,7 +11064,7 @@ pub fn svpmullt_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11080,7 +11080,7 @@ pub fn svpmullt_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11089,7 +11089,7 @@ pub fn svpmullt_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11105,7 +11105,7 @@ pub fn svpmullt_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11114,7 +11114,7 @@ pub fn svpmullt_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11123,7 +11123,7 @@ pub fn svpmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11132,7 +11132,7 @@ pub fn svpmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11141,7 +11141,7 @@ pub fn svpmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Polynomial multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-aes")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(pmullt))]
@@ -11150,7 +11150,7 @@ pub fn svpmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11163,7 +11163,7 @@ pub fn svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11172,7 +11172,7 @@ pub fn svqabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11181,7 +11181,7 @@ pub fn svqabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11194,7 +11194,7 @@ pub fn svqabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11203,7 +11203,7 @@ pub fn svqabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11212,7 +11212,7 @@ pub fn svqabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11225,7 +11225,7 @@ pub fn svqabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11234,7 +11234,7 @@ pub fn svqabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11243,7 +11243,7 @@ pub fn svqabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11256,7 +11256,7 @@ pub fn svqabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11265,7 +11265,7 @@ pub fn svqabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqabs))]
@@ -11274,7 +11274,7 @@ pub fn svqabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11287,7 +11287,7 @@ pub fn svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11296,7 +11296,7 @@ pub fn svqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11305,7 +11305,7 @@ pub fn svqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11314,7 +11314,7 @@ pub fn svqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11323,7 +11323,7 @@ pub fn svqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11332,7 +11332,7 @@ pub fn svqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11345,7 +11345,7 @@ pub fn svqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11354,7 +11354,7 @@ pub fn svqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11363,7 +11363,7 @@ pub fn svqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11372,7 +11372,7 @@ pub fn svqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11381,7 +11381,7 @@ pub fn svqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11390,7 +11390,7 @@ pub fn svqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11403,7 +11403,7 @@ pub fn svqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11412,7 +11412,7 @@ pub fn svqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11421,7 +11421,7 @@ pub fn svqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11430,7 +11430,7 @@ pub fn svqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11439,7 +11439,7 @@ pub fn svqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11448,7 +11448,7 @@ pub fn svqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11461,7 +11461,7 @@ pub fn svqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11470,7 +11470,7 @@ pub fn svqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11479,7 +11479,7 @@ pub fn svqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11488,7 +11488,7 @@ pub fn svqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11497,7 +11497,7 @@ pub fn svqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -11506,7 +11506,7 @@ pub fn svqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11519,7 +11519,7 @@ pub fn svqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11528,7 +11528,7 @@ pub fn svqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11537,7 +11537,7 @@ pub fn svqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11546,7 +11546,7 @@ pub fn svqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11555,7 +11555,7 @@ pub fn svqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11564,7 +11564,7 @@ pub fn svqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11577,7 +11577,7 @@ pub fn svqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11586,7 +11586,7 @@ pub fn svqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11595,7 +11595,7 @@ pub fn svqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11604,7 +11604,7 @@ pub fn svqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11613,7 +11613,7 @@ pub fn svqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11622,7 +11622,7 @@ pub fn svqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11635,7 +11635,7 @@ pub fn svqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11644,7 +11644,7 @@ pub fn svqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11653,7 +11653,7 @@ pub fn svqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11662,7 +11662,7 @@ pub fn svqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11671,7 +11671,7 @@ pub fn svqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11680,7 +11680,7 @@ pub fn svqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11693,7 +11693,7 @@ pub fn svqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11702,7 +11702,7 @@ pub fn svqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11711,7 +11711,7 @@ pub fn svqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11720,7 +11720,7 @@ pub fn svqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11729,7 +11729,7 @@ pub fn svqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -11738,7 +11738,7 @@ pub fn svqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
@@ -11755,7 +11755,7 @@ pub fn svqcadd_s8<const IMM_ROTATION: i32>(op1: svint8_t, op2: svint8_t) -> svin
 }
 #[doc = "Saturating complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
@@ -11772,7 +11772,7 @@ pub fn svqcadd_s16<const IMM_ROTATION: i32>(op1: svint16_t, op2: svint16_t) -> s
 }
 #[doc = "Saturating complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
@@ -11789,7 +11789,7 @@ pub fn svqcadd_s32<const IMM_ROTATION: i32>(op1: svint32_t, op2: svint32_t) -> s
 }
 #[doc = "Saturating complex add with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))]
@@ -11806,7 +11806,7 @@ pub fn svqcadd_s64<const IMM_ROTATION: i32>(op1: svint64_t, op2: svint64_t) -> s
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))]
@@ -11832,7 +11832,7 @@ pub fn svqdmlalb_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))]
@@ -11858,7 +11858,7 @@ pub fn svqdmlalb_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb))]
@@ -11874,7 +11874,7 @@ pub fn svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb))]
@@ -11883,7 +11883,7 @@ pub fn svqdmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb))]
@@ -11899,7 +11899,7 @@ pub fn svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb))]
@@ -11908,7 +11908,7 @@ pub fn svqdmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb))]
@@ -11924,7 +11924,7 @@ pub fn svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_
 }
 #[doc = "Saturating doubling multiply-add long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalb))]
@@ -11933,7 +11933,7 @@ pub fn svqdmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply-add long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalbt))]
@@ -11949,7 +11949,7 @@ pub fn svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t
 }
 #[doc = "Saturating doubling multiply-add long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalbt))]
@@ -11958,7 +11958,7 @@ pub fn svqdmlalbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply-add long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalbt))]
@@ -11974,7 +11974,7 @@ pub fn svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32
 }
 #[doc = "Saturating doubling multiply-add long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalbt))]
@@ -11983,7 +11983,7 @@ pub fn svqdmlalbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply-add long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalbt))]
@@ -11999,7 +11999,7 @@ pub fn svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64
 }
 #[doc = "Saturating doubling multiply-add long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalbt))]
@@ -12008,7 +12008,7 @@ pub fn svqdmlalbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))]
@@ -12034,7 +12034,7 @@ pub fn svqdmlalt_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))]
@@ -12060,7 +12060,7 @@ pub fn svqdmlalt_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt))]
@@ -12076,7 +12076,7 @@ pub fn svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt))]
@@ -12085,7 +12085,7 @@ pub fn svqdmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt))]
@@ -12101,7 +12101,7 @@ pub fn svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt))]
@@ -12110,7 +12110,7 @@ pub fn svqdmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt))]
@@ -12126,7 +12126,7 @@ pub fn svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_
 }
 #[doc = "Saturating doubling multiply-add long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlalt))]
@@ -12135,7 +12135,7 @@ pub fn svqdmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))]
@@ -12161,7 +12161,7 @@ pub fn svqdmlslb_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))]
@@ -12187,7 +12187,7 @@ pub fn svqdmlslb_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb))]
@@ -12203,7 +12203,7 @@ pub fn svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb))]
@@ -12212,7 +12212,7 @@ pub fn svqdmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb))]
@@ -12228,7 +12228,7 @@ pub fn svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb))]
@@ -12237,7 +12237,7 @@ pub fn svqdmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb))]
@@ -12253,7 +12253,7 @@ pub fn svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslb))]
@@ -12262,7 +12262,7 @@ pub fn svqdmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslbt))]
@@ -12278,7 +12278,7 @@ pub fn svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslbt))]
@@ -12287,7 +12287,7 @@ pub fn svqdmlslbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslbt))]
@@ -12303,7 +12303,7 @@ pub fn svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslbt))]
@@ -12312,7 +12312,7 @@ pub fn svqdmlslbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslbt))]
@@ -12328,7 +12328,7 @@ pub fn svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64
 }
 #[doc = "Saturating doubling multiply-subtract long (bottom × top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslbt))]
@@ -12337,7 +12337,7 @@ pub fn svqdmlslbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))]
@@ -12363,7 +12363,7 @@ pub fn svqdmlslt_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))]
@@ -12389,7 +12389,7 @@ pub fn svqdmlslt_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt))]
@@ -12405,7 +12405,7 @@ pub fn svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt))]
@@ -12414,7 +12414,7 @@ pub fn svqdmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt))]
@@ -12430,7 +12430,7 @@ pub fn svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt))]
@@ -12439,7 +12439,7 @@ pub fn svqdmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt))]
@@ -12455,7 +12455,7 @@ pub fn svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_
 }
 #[doc = "Saturating doubling multiply-subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmlslt))]
@@ -12464,7 +12464,7 @@ pub fn svqdmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))]
@@ -12481,7 +12481,7 @@ pub fn svqdmulh_lane_s16<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t) -
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))]
@@ -12498,7 +12498,7 @@ pub fn svqdmulh_lane_s32<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t) -
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))]
@@ -12515,7 +12515,7 @@ pub fn svqdmulh_lane_s64<const IMM_INDEX: i32>(op1: svint64_t, op2: svint64_t) -
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12531,7 +12531,7 @@ pub fn svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12540,7 +12540,7 @@ pub fn svqdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12556,7 +12556,7 @@ pub fn svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12565,7 +12565,7 @@ pub fn svqdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12581,7 +12581,7 @@ pub fn svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12590,7 +12590,7 @@ pub fn svqdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12606,7 +12606,7 @@ pub fn svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
@@ -12615,7 +12615,7 @@ pub fn svqdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))]
@@ -12632,7 +12632,7 @@ pub fn svqdmullb_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t)
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))]
@@ -12649,7 +12649,7 @@ pub fn svqdmullb_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t)
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb))]
@@ -12665,7 +12665,7 @@ pub fn svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb))]
@@ -12674,7 +12674,7 @@ pub fn svqdmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb))]
@@ -12690,7 +12690,7 @@ pub fn svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb))]
@@ -12699,7 +12699,7 @@ pub fn svqdmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb))]
@@ -12715,7 +12715,7 @@ pub fn svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullb))]
@@ -12724,7 +12724,7 @@ pub fn svqdmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))]
@@ -12741,7 +12741,7 @@ pub fn svqdmullt_lane_s32<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t)
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))]
@@ -12758,7 +12758,7 @@ pub fn svqdmullt_lane_s64<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t)
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt))]
@@ -12774,7 +12774,7 @@ pub fn svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt))]
@@ -12783,7 +12783,7 @@ pub fn svqdmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt))]
@@ -12799,7 +12799,7 @@ pub fn svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt))]
@@ -12808,7 +12808,7 @@ pub fn svqdmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt))]
@@ -12824,7 +12824,7 @@ pub fn svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Saturating doubling multiply long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqdmullt))]
@@ -12833,7 +12833,7 @@ pub fn svqdmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12846,7 +12846,7 @@ pub fn svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12855,7 +12855,7 @@ pub fn svqneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12864,7 +12864,7 @@ pub fn svqneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12877,7 +12877,7 @@ pub fn svqneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12886,7 +12886,7 @@ pub fn svqneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12895,7 +12895,7 @@ pub fn svqneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12908,7 +12908,7 @@ pub fn svqneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12917,7 +12917,7 @@ pub fn svqneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12926,7 +12926,7 @@ pub fn svqneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12939,7 +12939,7 @@ pub fn svqneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12948,7 +12948,7 @@ pub fn svqneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -12957,7 +12957,7 @@ pub fn svqneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -12987,7 +12987,7 @@ pub fn svqrdcmlah_lane_s16<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))]
@@ -13017,7 +13017,7 @@ pub fn svqrdcmlah_lane_s32<const IMM_INDEX: i32, const IMM_ROTATION: i32>(
 }
 #[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
@@ -13045,7 +13045,7 @@ pub fn svqrdcmlah_s8<const IMM_ROTATION: i32>(
 }
 #[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
@@ -13073,7 +13073,7 @@ pub fn svqrdcmlah_s16<const IMM_ROTATION: i32>(
 }
 #[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
@@ -13101,7 +13101,7 @@ pub fn svqrdcmlah_s32<const IMM_ROTATION: i32>(
 }
 #[doc = "Saturating rounding doubling complex multiply-add high with rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))]
@@ -13129,7 +13129,7 @@ pub fn svqrdcmlah_s64<const IMM_ROTATION: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))]
@@ -13155,7 +13155,7 @@ pub fn svqrdmlah_lane_s16<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))]
@@ -13181,7 +13181,7 @@ pub fn svqrdmlah_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))]
@@ -13207,7 +13207,7 @@ pub fn svqrdmlah_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13223,7 +13223,7 @@ pub fn svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13232,7 +13232,7 @@ pub fn svqrdmlah_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13248,7 +13248,7 @@ pub fn svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13257,7 +13257,7 @@ pub fn svqrdmlah_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13273,7 +13273,7 @@ pub fn svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13282,7 +13282,7 @@ pub fn svqrdmlah_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13298,7 +13298,7 @@ pub fn svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_
 }
 #[doc = "Saturating rounding doubling multiply-add high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
@@ -13307,7 +13307,7 @@ pub fn svqrdmlah_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))]
@@ -13333,7 +13333,7 @@ pub fn svqrdmlsh_lane_s16<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))]
@@ -13359,7 +13359,7 @@ pub fn svqrdmlsh_lane_s32<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))]
@@ -13385,7 +13385,7 @@ pub fn svqrdmlsh_lane_s64<const IMM_INDEX: i32>(
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13401,7 +13401,7 @@ pub fn svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13410,7 +13410,7 @@ pub fn svqrdmlsh_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t {
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13426,7 +13426,7 @@ pub fn svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13435,7 +13435,7 @@ pub fn svqrdmlsh_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t {
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13451,7 +13451,7 @@ pub fn svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13460,7 +13460,7 @@ pub fn svqrdmlsh_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t {
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13476,7 +13476,7 @@ pub fn svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_
 }
 #[doc = "Saturating rounding doubling multiply-subtract high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
@@ -13485,7 +13485,7 @@ pub fn svqrdmlsh_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))]
@@ -13502,7 +13502,7 @@ pub fn svqrdmulh_lane_s16<const IMM_INDEX: i32>(op1: svint16_t, op2: svint16_t)
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))]
@@ -13519,7 +13519,7 @@ pub fn svqrdmulh_lane_s32<const IMM_INDEX: i32>(op1: svint32_t, op2: svint32_t)
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))]
@@ -13536,7 +13536,7 @@ pub fn svqrdmulh_lane_s64<const IMM_INDEX: i32>(op1: svint64_t, op2: svint64_t)
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13552,7 +13552,7 @@ pub fn svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13561,7 +13561,7 @@ pub fn svqrdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13577,7 +13577,7 @@ pub fn svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13586,7 +13586,7 @@ pub fn svqrdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13602,7 +13602,7 @@ pub fn svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13611,7 +13611,7 @@ pub fn svqrdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13627,7 +13627,7 @@ pub fn svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating rounding doubling multiply high"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
@@ -13636,7 +13636,7 @@ pub fn svqrdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13649,7 +13649,7 @@ pub fn svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13658,7 +13658,7 @@ pub fn svqrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13667,7 +13667,7 @@ pub fn svqrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13676,7 +13676,7 @@ pub fn svqrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13685,7 +13685,7 @@ pub fn svqrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13694,7 +13694,7 @@ pub fn svqrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13707,7 +13707,7 @@ pub fn svqrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13716,7 +13716,7 @@ pub fn svqrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13725,7 +13725,7 @@ pub fn svqrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13734,7 +13734,7 @@ pub fn svqrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13743,7 +13743,7 @@ pub fn svqrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13752,7 +13752,7 @@ pub fn svqrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13765,7 +13765,7 @@ pub fn svqrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13774,7 +13774,7 @@ pub fn svqrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13783,7 +13783,7 @@ pub fn svqrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13792,7 +13792,7 @@ pub fn svqrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13801,7 +13801,7 @@ pub fn svqrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13810,7 +13810,7 @@ pub fn svqrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13823,7 +13823,7 @@ pub fn svqrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13832,7 +13832,7 @@ pub fn svqrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13841,7 +13841,7 @@ pub fn svqrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13850,7 +13850,7 @@ pub fn svqrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13859,7 +13859,7 @@ pub fn svqrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshl))]
@@ -13868,7 +13868,7 @@ pub fn svqrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13881,7 +13881,7 @@ pub fn svqrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13890,7 +13890,7 @@ pub fn svqrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13899,7 +13899,7 @@ pub fn svqrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13908,7 +13908,7 @@ pub fn svqrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13917,7 +13917,7 @@ pub fn svqrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13926,7 +13926,7 @@ pub fn svqrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13939,7 +13939,7 @@ pub fn svqrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13948,7 +13948,7 @@ pub fn svqrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13957,7 +13957,7 @@ pub fn svqrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13966,7 +13966,7 @@ pub fn svqrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13975,7 +13975,7 @@ pub fn svqrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13984,7 +13984,7 @@ pub fn svqrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -13997,7 +13997,7 @@ pub fn svqrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14006,7 +14006,7 @@ pub fn svqrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14015,7 +14015,7 @@ pub fn svqrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14024,7 +14024,7 @@ pub fn svqrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14033,7 +14033,7 @@ pub fn svqrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14042,7 +14042,7 @@ pub fn svqrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14055,7 +14055,7 @@ pub fn svqrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14064,7 +14064,7 @@ pub fn svqrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14073,7 +14073,7 @@ pub fn svqrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14082,7 +14082,7 @@ pub fn svqrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14091,7 +14091,7 @@ pub fn svqrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_
 }
 #[doc = "Saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshl))]
@@ -14100,7 +14100,7 @@ pub fn svqrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))]
@@ -14117,7 +14117,7 @@ pub fn svqrshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
 }
 #[doc = "Saturating rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))]
@@ -14134,7 +14134,7 @@ pub fn svqrshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
 }
 #[doc = "Saturating rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))]
@@ -14151,7 +14151,7 @@ pub fn svqrshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
 }
 #[doc = "Saturating rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))]
@@ -14168,7 +14168,7 @@ pub fn svqrshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))]
@@ -14185,7 +14185,7 @@ pub fn svqrshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
 }
 #[doc = "Saturating rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))]
@@ -14202,7 +14202,7 @@ pub fn svqrshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
 }
 #[doc = "Saturating rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))]
@@ -14219,7 +14219,7 @@ pub fn svqrshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint
 }
 #[doc = "Saturating rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))]
@@ -14236,7 +14236,7 @@ pub fn svqrshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svin
 }
 #[doc = "Saturating rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))]
@@ -14253,7 +14253,7 @@ pub fn svqrshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svin
 }
 #[doc = "Saturating rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))]
@@ -14270,7 +14270,7 @@ pub fn svqrshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svu
 }
 #[doc = "Saturating rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))]
@@ -14287,7 +14287,7 @@ pub fn svqrshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> sv
 }
 #[doc = "Saturating rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))]
@@ -14304,7 +14304,7 @@ pub fn svqrshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> sv
 }
 #[doc = "Saturating rounding shift right unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))]
@@ -14321,7 +14321,7 @@ pub fn svqrshrunb_n_s16<const IMM2: i32>(op1: svint16_t) -> svuint8_t {
 }
 #[doc = "Saturating rounding shift right unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))]
@@ -14338,7 +14338,7 @@ pub fn svqrshrunb_n_s32<const IMM2: i32>(op1: svint32_t) -> svuint16_t {
 }
 #[doc = "Saturating rounding shift right unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))]
@@ -14355,7 +14355,7 @@ pub fn svqrshrunb_n_s64<const IMM2: i32>(op1: svint64_t) -> svuint32_t {
 }
 #[doc = "Saturating rounding shift right unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))]
@@ -14372,7 +14372,7 @@ pub fn svqrshrunt_n_s16<const IMM2: i32>(even: svuint8_t, op1: svint16_t) -> svu
 }
 #[doc = "Saturating rounding shift right unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))]
@@ -14389,7 +14389,7 @@ pub fn svqrshrunt_n_s32<const IMM2: i32>(even: svuint16_t, op1: svint32_t) -> sv
 }
 #[doc = "Saturating rounding shift right unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))]
@@ -14406,7 +14406,7 @@ pub fn svqrshrunt_n_s64<const IMM2: i32>(even: svuint32_t, op1: svint64_t) -> sv
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14419,7 +14419,7 @@ pub fn svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14428,7 +14428,7 @@ pub fn svqshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14437,7 +14437,7 @@ pub fn svqshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14446,7 +14446,7 @@ pub fn svqshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14455,7 +14455,7 @@ pub fn svqshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14464,7 +14464,7 @@ pub fn svqshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14477,7 +14477,7 @@ pub fn svqshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14486,7 +14486,7 @@ pub fn svqshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14495,7 +14495,7 @@ pub fn svqshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14504,7 +14504,7 @@ pub fn svqshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14513,7 +14513,7 @@ pub fn svqshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14522,7 +14522,7 @@ pub fn svqshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14535,7 +14535,7 @@ pub fn svqshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14544,7 +14544,7 @@ pub fn svqshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14553,7 +14553,7 @@ pub fn svqshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14562,7 +14562,7 @@ pub fn svqshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14571,7 +14571,7 @@ pub fn svqshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14580,7 +14580,7 @@ pub fn svqshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14593,7 +14593,7 @@ pub fn svqshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14602,7 +14602,7 @@ pub fn svqshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14611,7 +14611,7 @@ pub fn svqshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14620,7 +14620,7 @@ pub fn svqshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14629,7 +14629,7 @@ pub fn svqshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshl))]
@@ -14638,7 +14638,7 @@ pub fn svqshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14651,7 +14651,7 @@ pub fn svqshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14660,7 +14660,7 @@ pub fn svqshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14669,7 +14669,7 @@ pub fn svqshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14678,7 +14678,7 @@ pub fn svqshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14687,7 +14687,7 @@ pub fn svqshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14696,7 +14696,7 @@ pub fn svqshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14709,7 +14709,7 @@ pub fn svqshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14718,7 +14718,7 @@ pub fn svqshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14727,7 +14727,7 @@ pub fn svqshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14736,7 +14736,7 @@ pub fn svqshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14745,7 +14745,7 @@ pub fn svqshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14754,7 +14754,7 @@ pub fn svqshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14767,7 +14767,7 @@ pub fn svqshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14776,7 +14776,7 @@ pub fn svqshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14785,7 +14785,7 @@ pub fn svqshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14794,7 +14794,7 @@ pub fn svqshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14803,7 +14803,7 @@ pub fn svqshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14812,7 +14812,7 @@ pub fn svqshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14825,7 +14825,7 @@ pub fn svqshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14834,7 +14834,7 @@ pub fn svqshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14843,7 +14843,7 @@ pub fn svqshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14852,7 +14852,7 @@ pub fn svqshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14861,7 +14861,7 @@ pub fn svqshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t
 }
 #[doc = "Saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshl))]
@@ -14870,7 +14870,7 @@ pub fn svqshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14884,7 +14884,7 @@ pub fn svqshlu_n_s8_m<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svuint8_t
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14893,7 +14893,7 @@ pub fn svqshlu_n_s8_x<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svuint8_t
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14902,7 +14902,7 @@ pub fn svqshlu_n_s8_z<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svuint8_t
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14916,7 +14916,7 @@ pub fn svqshlu_n_s16_m<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svuint1
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14925,7 +14925,7 @@ pub fn svqshlu_n_s16_x<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svuint1
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14934,7 +14934,7 @@ pub fn svqshlu_n_s16_z<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svuint1
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14948,7 +14948,7 @@ pub fn svqshlu_n_s32_m<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svuint3
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14957,7 +14957,7 @@ pub fn svqshlu_n_s32_x<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svuint3
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14966,7 +14966,7 @@ pub fn svqshlu_n_s32_z<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svuint3
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14980,7 +14980,7 @@ pub fn svqshlu_n_s64_m<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svuint6
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14989,7 +14989,7 @@ pub fn svqshlu_n_s64_x<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svuint6
 }
 #[doc = "Saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))]
@@ -14998,7 +14998,7 @@ pub fn svqshlu_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svuint6
 }
 #[doc = "Saturating shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))]
@@ -15015,7 +15015,7 @@ pub fn svqshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
 }
 #[doc = "Saturating shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))]
@@ -15032,7 +15032,7 @@ pub fn svqshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
 }
 #[doc = "Saturating shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))]
@@ -15049,7 +15049,7 @@ pub fn svqshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
 }
 #[doc = "Saturating shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))]
@@ -15066,7 +15066,7 @@ pub fn svqshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
 }
 #[doc = "Saturating shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))]
@@ -15083,7 +15083,7 @@ pub fn svqshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
 }
 #[doc = "Saturating shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))]
@@ -15100,7 +15100,7 @@ pub fn svqshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
 }
 #[doc = "Saturating shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))]
@@ -15117,7 +15117,7 @@ pub fn svqshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8
 }
 #[doc = "Saturating shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))]
@@ -15134,7 +15134,7 @@ pub fn svqshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint
 }
 #[doc = "Saturating shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))]
@@ -15151,7 +15151,7 @@ pub fn svqshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint
 }
 #[doc = "Saturating shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))]
@@ -15168,7 +15168,7 @@ pub fn svqshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svui
 }
 #[doc = "Saturating shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))]
@@ -15185,7 +15185,7 @@ pub fn svqshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svu
 }
 #[doc = "Saturating shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))]
@@ -15202,7 +15202,7 @@ pub fn svqshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svu
 }
 #[doc = "Saturating shift right unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))]
@@ -15219,7 +15219,7 @@ pub fn svqshrunb_n_s16<const IMM2: i32>(op1: svint16_t) -> svuint8_t {
 }
 #[doc = "Saturating shift right unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))]
@@ -15236,7 +15236,7 @@ pub fn svqshrunb_n_s32<const IMM2: i32>(op1: svint32_t) -> svuint16_t {
 }
 #[doc = "Saturating shift right unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))]
@@ -15253,7 +15253,7 @@ pub fn svqshrunb_n_s64<const IMM2: i32>(op1: svint64_t) -> svuint32_t {
 }
 #[doc = "Saturating shift right unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))]
@@ -15270,7 +15270,7 @@ pub fn svqshrunt_n_s16<const IMM2: i32>(even: svuint8_t, op1: svint16_t) -> svui
 }
 #[doc = "Saturating shift right unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))]
@@ -15287,7 +15287,7 @@ pub fn svqshrunt_n_s32<const IMM2: i32>(even: svuint16_t, op1: svint32_t) -> svu
 }
 #[doc = "Saturating shift right unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))]
@@ -15304,7 +15304,7 @@ pub fn svqshrunt_n_s64<const IMM2: i32>(even: svuint32_t, op1: svint64_t) -> svu
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15317,7 +15317,7 @@ pub fn svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15326,7 +15326,7 @@ pub fn svqsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15335,7 +15335,7 @@ pub fn svqsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15344,7 +15344,7 @@ pub fn svqsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15353,7 +15353,7 @@ pub fn svqsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15362,7 +15362,7 @@ pub fn svqsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15375,7 +15375,7 @@ pub fn svqsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15384,7 +15384,7 @@ pub fn svqsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15393,7 +15393,7 @@ pub fn svqsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15402,7 +15402,7 @@ pub fn svqsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15411,7 +15411,7 @@ pub fn svqsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15420,7 +15420,7 @@ pub fn svqsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15433,7 +15433,7 @@ pub fn svqsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15442,7 +15442,7 @@ pub fn svqsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15451,7 +15451,7 @@ pub fn svqsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15460,7 +15460,7 @@ pub fn svqsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15469,7 +15469,7 @@ pub fn svqsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15478,7 +15478,7 @@ pub fn svqsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15491,7 +15491,7 @@ pub fn svqsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15500,7 +15500,7 @@ pub fn svqsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15509,7 +15509,7 @@ pub fn svqsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15518,7 +15518,7 @@ pub fn svqsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15527,7 +15527,7 @@ pub fn svqsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -15536,7 +15536,7 @@ pub fn svqsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15549,7 +15549,7 @@ pub fn svqsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15558,7 +15558,7 @@ pub fn svqsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15567,7 +15567,7 @@ pub fn svqsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15576,7 +15576,7 @@ pub fn svqsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15585,7 +15585,7 @@ pub fn svqsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15594,7 +15594,7 @@ pub fn svqsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15607,7 +15607,7 @@ pub fn svqsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15616,7 +15616,7 @@ pub fn svqsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15625,7 +15625,7 @@ pub fn svqsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15634,7 +15634,7 @@ pub fn svqsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15643,7 +15643,7 @@ pub fn svqsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15652,7 +15652,7 @@ pub fn svqsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15665,7 +15665,7 @@ pub fn svqsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15674,7 +15674,7 @@ pub fn svqsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15683,7 +15683,7 @@ pub fn svqsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15692,7 +15692,7 @@ pub fn svqsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15701,7 +15701,7 @@ pub fn svqsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15710,7 +15710,7 @@ pub fn svqsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15723,7 +15723,7 @@ pub fn svqsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15732,7 +15732,7 @@ pub fn svqsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15741,7 +15741,7 @@ pub fn svqsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15750,7 +15750,7 @@ pub fn svqsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15759,7 +15759,7 @@ pub fn svqsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -15768,7 +15768,7 @@ pub fn svqsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15781,7 +15781,7 @@ pub fn svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15790,7 +15790,7 @@ pub fn svqsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15799,7 +15799,7 @@ pub fn svqsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15808,7 +15808,7 @@ pub fn svqsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15817,7 +15817,7 @@ pub fn svqsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15826,7 +15826,7 @@ pub fn svqsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15839,7 +15839,7 @@ pub fn svqsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15848,7 +15848,7 @@ pub fn svqsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15857,7 +15857,7 @@ pub fn svqsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15866,7 +15866,7 @@ pub fn svqsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15875,7 +15875,7 @@ pub fn svqsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15884,7 +15884,7 @@ pub fn svqsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15897,7 +15897,7 @@ pub fn svqsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15906,7 +15906,7 @@ pub fn svqsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15915,7 +15915,7 @@ pub fn svqsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15924,7 +15924,7 @@ pub fn svqsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15933,7 +15933,7 @@ pub fn svqsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15942,7 +15942,7 @@ pub fn svqsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15955,7 +15955,7 @@ pub fn svqsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15964,7 +15964,7 @@ pub fn svqsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15973,7 +15973,7 @@ pub fn svqsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15982,7 +15982,7 @@ pub fn svqsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -15991,7 +15991,7 @@ pub fn svqsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqsubr))]
@@ -16000,7 +16000,7 @@ pub fn svqsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16013,7 +16013,7 @@ pub fn svqsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16022,7 +16022,7 @@ pub fn svqsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16031,7 +16031,7 @@ pub fn svqsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16040,7 +16040,7 @@ pub fn svqsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16049,7 +16049,7 @@ pub fn svqsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16058,7 +16058,7 @@ pub fn svqsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16071,7 +16071,7 @@ pub fn svqsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16080,7 +16080,7 @@ pub fn svqsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16089,7 +16089,7 @@ pub fn svqsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16098,7 +16098,7 @@ pub fn svqsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16107,7 +16107,7 @@ pub fn svqsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16116,7 +16116,7 @@ pub fn svqsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16129,7 +16129,7 @@ pub fn svqsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16138,7 +16138,7 @@ pub fn svqsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16147,7 +16147,7 @@ pub fn svqsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16156,7 +16156,7 @@ pub fn svqsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16165,7 +16165,7 @@ pub fn svqsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16174,7 +16174,7 @@ pub fn svqsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16187,7 +16187,7 @@ pub fn svqsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16196,7 +16196,7 @@ pub fn svqsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16205,7 +16205,7 @@ pub fn svqsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16214,7 +16214,7 @@ pub fn svqsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16223,7 +16223,7 @@ pub fn svqsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Saturating subtract reversed"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqsubr))]
@@ -16232,7 +16232,7 @@ pub fn svqsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Saturating extract narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtnb))]
@@ -16245,7 +16245,7 @@ pub fn svqxtnb_s16(op: svint16_t) -> svint8_t {
 }
 #[doc = "Saturating extract narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtnb))]
@@ -16258,7 +16258,7 @@ pub fn svqxtnb_s32(op: svint32_t) -> svint16_t {
 }
 #[doc = "Saturating extract narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtnb))]
@@ -16271,7 +16271,7 @@ pub fn svqxtnb_s64(op: svint64_t) -> svint32_t {
 }
 #[doc = "Saturating extract narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqxtnb))]
@@ -16284,7 +16284,7 @@ pub fn svqxtnb_u16(op: svuint16_t) -> svuint8_t {
 }
 #[doc = "Saturating extract narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqxtnb))]
@@ -16297,7 +16297,7 @@ pub fn svqxtnb_u32(op: svuint32_t) -> svuint16_t {
 }
 #[doc = "Saturating extract narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqxtnb))]
@@ -16310,7 +16310,7 @@ pub fn svqxtnb_u64(op: svuint64_t) -> svuint32_t {
 }
 #[doc = "Saturating extract narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtnt))]
@@ -16323,7 +16323,7 @@ pub fn svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t {
 }
 #[doc = "Saturating extract narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtnt))]
@@ -16336,7 +16336,7 @@ pub fn svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t {
 }
 #[doc = "Saturating extract narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtnt))]
@@ -16349,7 +16349,7 @@ pub fn svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t {
 }
 #[doc = "Saturating extract narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqxtnt))]
@@ -16362,7 +16362,7 @@ pub fn svqxtnt_u16(even: svuint8_t, op: svuint16_t) -> svuint8_t {
 }
 #[doc = "Saturating extract narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqxtnt))]
@@ -16375,7 +16375,7 @@ pub fn svqxtnt_u32(even: svuint16_t, op: svuint32_t) -> svuint16_t {
 }
 #[doc = "Saturating extract narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uqxtnt))]
@@ -16388,7 +16388,7 @@ pub fn svqxtnt_u64(even: svuint32_t, op: svuint64_t) -> svuint32_t {
 }
 #[doc = "Saturating extract unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtunb))]
@@ -16404,7 +16404,7 @@ pub fn svqxtunb_s16(op: svint16_t) -> svuint8_t {
 }
 #[doc = "Saturating extract unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtunb))]
@@ -16420,7 +16420,7 @@ pub fn svqxtunb_s32(op: svint32_t) -> svuint16_t {
 }
 #[doc = "Saturating extract unsigned narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtunb))]
@@ -16436,7 +16436,7 @@ pub fn svqxtunb_s64(op: svint64_t) -> svuint32_t {
 }
 #[doc = "Saturating extract unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtunt))]
@@ -16452,7 +16452,7 @@ pub fn svqxtunt_s16(even: svuint8_t, op: svint16_t) -> svuint8_t {
 }
 #[doc = "Saturating extract unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtunt))]
@@ -16468,7 +16468,7 @@ pub fn svqxtunt_s32(even: svuint16_t, op: svint32_t) -> svuint16_t {
 }
 #[doc = "Saturating extract unsigned narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sqxtunt))]
@@ -16484,7 +16484,7 @@ pub fn svqxtunt_s64(even: svuint32_t, op: svint64_t) -> svuint32_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16500,7 +16500,7 @@ pub fn svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16509,7 +16509,7 @@ pub fn svraddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16525,7 +16525,7 @@ pub fn svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16534,7 +16534,7 @@ pub fn svraddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16550,7 +16550,7 @@ pub fn svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16559,7 +16559,7 @@ pub fn svraddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16568,7 +16568,7 @@ pub fn svraddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16577,7 +16577,7 @@ pub fn svraddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16586,7 +16586,7 @@ pub fn svraddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16595,7 +16595,7 @@ pub fn svraddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16604,7 +16604,7 @@ pub fn svraddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
 }
 #[doc = "Rounding add narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnb))]
@@ -16613,7 +16613,7 @@ pub fn svraddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16629,7 +16629,7 @@ pub fn svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16638,7 +16638,7 @@ pub fn svraddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16654,7 +16654,7 @@ pub fn svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16663,7 +16663,7 @@ pub fn svraddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16679,7 +16679,7 @@ pub fn svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16688,7 +16688,7 @@ pub fn svraddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16697,7 +16697,7 @@ pub fn svraddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuin
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16706,7 +16706,7 @@ pub fn svraddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16715,7 +16715,7 @@ pub fn svraddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svui
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16724,7 +16724,7 @@ pub fn svraddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16733,7 +16733,7 @@ pub fn svraddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svui
 }
 #[doc = "Rounding add narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(raddhnt))]
@@ -16742,7 +16742,7 @@ pub fn svraddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_
 }
 #[doc = "Bitwise rotate left by 1 and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-sha3")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rax1))]
@@ -16755,7 +16755,7 @@ pub fn svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Bitwise rotate left by 1 and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-sha3")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rax1))]
@@ -16764,7 +16764,7 @@ pub fn svrax1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
 }
 #[doc = "Reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urecpe))]
@@ -16777,7 +16777,7 @@ pub fn svrecpe_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svui
 }
 #[doc = "Reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urecpe))]
@@ -16786,7 +16786,7 @@ pub fn svrecpe_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urecpe))]
@@ -16795,7 +16795,7 @@ pub fn svrecpe_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16808,7 +16808,7 @@ pub fn svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16817,7 +16817,7 @@ pub fn svrhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16826,7 +16826,7 @@ pub fn svrhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16835,7 +16835,7 @@ pub fn svrhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16844,7 +16844,7 @@ pub fn svrhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16853,7 +16853,7 @@ pub fn svrhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16866,7 +16866,7 @@ pub fn svrhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16875,7 +16875,7 @@ pub fn svrhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16884,7 +16884,7 @@ pub fn svrhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16893,7 +16893,7 @@ pub fn svrhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16902,7 +16902,7 @@ pub fn svrhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16911,7 +16911,7 @@ pub fn svrhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16924,7 +16924,7 @@ pub fn svrhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16933,7 +16933,7 @@ pub fn svrhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16942,7 +16942,7 @@ pub fn svrhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16951,7 +16951,7 @@ pub fn svrhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16960,7 +16960,7 @@ pub fn svrhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16969,7 +16969,7 @@ pub fn svrhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16982,7 +16982,7 @@ pub fn svrhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -16991,7 +16991,7 @@ pub fn svrhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -17000,7 +17000,7 @@ pub fn svrhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -17009,7 +17009,7 @@ pub fn svrhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -17018,7 +17018,7 @@ pub fn svrhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srhadd))]
@@ -17027,7 +17027,7 @@ pub fn svrhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17040,7 +17040,7 @@ pub fn svrhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17049,7 +17049,7 @@ pub fn svrhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17058,7 +17058,7 @@ pub fn svrhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17067,7 +17067,7 @@ pub fn svrhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17076,7 +17076,7 @@ pub fn svrhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17085,7 +17085,7 @@ pub fn svrhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17098,7 +17098,7 @@ pub fn svrhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17107,7 +17107,7 @@ pub fn svrhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17116,7 +17116,7 @@ pub fn svrhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17125,7 +17125,7 @@ pub fn svrhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17134,7 +17134,7 @@ pub fn svrhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17143,7 +17143,7 @@ pub fn svrhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17156,7 +17156,7 @@ pub fn svrhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17165,7 +17165,7 @@ pub fn svrhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17174,7 +17174,7 @@ pub fn svrhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17183,7 +17183,7 @@ pub fn svrhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17192,7 +17192,7 @@ pub fn svrhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17201,7 +17201,7 @@ pub fn svrhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17214,7 +17214,7 @@ pub fn svrhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17223,7 +17223,7 @@ pub fn svrhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17232,7 +17232,7 @@ pub fn svrhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17241,7 +17241,7 @@ pub fn svrhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17250,7 +17250,7 @@ pub fn svrhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urhadd))]
@@ -17259,7 +17259,7 @@ pub fn svrhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17272,7 +17272,7 @@ pub fn svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17281,7 +17281,7 @@ pub fn svrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17290,7 +17290,7 @@ pub fn svrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17299,7 +17299,7 @@ pub fn svrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17308,7 +17308,7 @@ pub fn svrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17317,7 +17317,7 @@ pub fn svrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17330,7 +17330,7 @@ pub fn svrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17339,7 +17339,7 @@ pub fn svrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17348,7 +17348,7 @@ pub fn svrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17357,7 +17357,7 @@ pub fn svrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17366,7 +17366,7 @@ pub fn svrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17375,7 +17375,7 @@ pub fn svrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17388,7 +17388,7 @@ pub fn svrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17397,7 +17397,7 @@ pub fn svrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17406,7 +17406,7 @@ pub fn svrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17415,7 +17415,7 @@ pub fn svrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17424,7 +17424,7 @@ pub fn svrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17433,7 +17433,7 @@ pub fn svrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17446,7 +17446,7 @@ pub fn svrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17455,7 +17455,7 @@ pub fn svrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17464,7 +17464,7 @@ pub fn svrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17473,7 +17473,7 @@ pub fn svrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17482,7 +17482,7 @@ pub fn svrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshl))]
@@ -17491,7 +17491,7 @@ pub fn svrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17504,7 +17504,7 @@ pub fn svrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17513,7 +17513,7 @@ pub fn svrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17522,7 +17522,7 @@ pub fn svrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17531,7 +17531,7 @@ pub fn svrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17540,7 +17540,7 @@ pub fn svrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17549,7 +17549,7 @@ pub fn svrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17562,7 +17562,7 @@ pub fn svrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17571,7 +17571,7 @@ pub fn svrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17580,7 +17580,7 @@ pub fn svrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17589,7 +17589,7 @@ pub fn svrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17598,7 +17598,7 @@ pub fn svrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17607,7 +17607,7 @@ pub fn svrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17620,7 +17620,7 @@ pub fn svrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17629,7 +17629,7 @@ pub fn svrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17638,7 +17638,7 @@ pub fn svrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17647,7 +17647,7 @@ pub fn svrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17656,7 +17656,7 @@ pub fn svrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17665,7 +17665,7 @@ pub fn svrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17678,7 +17678,7 @@ pub fn svrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17687,7 +17687,7 @@ pub fn svrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17696,7 +17696,7 @@ pub fn svrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17705,7 +17705,7 @@ pub fn svrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17714,7 +17714,7 @@ pub fn svrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t
 }
 #[doc = "Rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshl))]
@@ -17723,7 +17723,7 @@ pub fn svrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17737,7 +17737,7 @@ pub fn svrshr_n_s8_m<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17746,7 +17746,7 @@ pub fn svrshr_n_s8_x<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17755,7 +17755,7 @@ pub fn svrshr_n_s8_z<const IMM2: i32>(pg: svbool_t, op1: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17769,7 +17769,7 @@ pub fn svrshr_n_s16_m<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17778,7 +17778,7 @@ pub fn svrshr_n_s16_x<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17787,7 +17787,7 @@ pub fn svrshr_n_s16_z<const IMM2: i32>(pg: svbool_t, op1: svint16_t) -> svint16_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17801,7 +17801,7 @@ pub fn svrshr_n_s32_m<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17810,7 +17810,7 @@ pub fn svrshr_n_s32_x<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17819,7 +17819,7 @@ pub fn svrshr_n_s32_z<const IMM2: i32>(pg: svbool_t, op1: svint32_t) -> svint32_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17833,7 +17833,7 @@ pub fn svrshr_n_s64_m<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17842,7 +17842,7 @@ pub fn svrshr_n_s64_x<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srshr, IMM2 = 1))]
@@ -17851,7 +17851,7 @@ pub fn svrshr_n_s64_z<const IMM2: i32>(pg: svbool_t, op1: svint64_t) -> svint64_
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17865,7 +17865,7 @@ pub fn svrshr_n_u8_m<const IMM2: i32>(pg: svbool_t, op1: svuint8_t) -> svuint8_t
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17874,7 +17874,7 @@ pub fn svrshr_n_u8_x<const IMM2: i32>(pg: svbool_t, op1: svuint8_t) -> svuint8_t
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17883,7 +17883,7 @@ pub fn svrshr_n_u8_z<const IMM2: i32>(pg: svbool_t, op1: svuint8_t) -> svuint8_t
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17897,7 +17897,7 @@ pub fn svrshr_n_u16_m<const IMM2: i32>(pg: svbool_t, op1: svuint16_t) -> svuint1
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17906,7 +17906,7 @@ pub fn svrshr_n_u16_x<const IMM2: i32>(pg: svbool_t, op1: svuint16_t) -> svuint1
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17915,7 +17915,7 @@ pub fn svrshr_n_u16_z<const IMM2: i32>(pg: svbool_t, op1: svuint16_t) -> svuint1
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17929,7 +17929,7 @@ pub fn svrshr_n_u32_m<const IMM2: i32>(pg: svbool_t, op1: svuint32_t) -> svuint3
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17938,7 +17938,7 @@ pub fn svrshr_n_u32_x<const IMM2: i32>(pg: svbool_t, op1: svuint32_t) -> svuint3
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17947,7 +17947,7 @@ pub fn svrshr_n_u32_z<const IMM2: i32>(pg: svbool_t, op1: svuint32_t) -> svuint3
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17961,7 +17961,7 @@ pub fn svrshr_n_u64_m<const IMM2: i32>(pg: svbool_t, op1: svuint64_t) -> svuint6
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17970,7 +17970,7 @@ pub fn svrshr_n_u64_x<const IMM2: i32>(pg: svbool_t, op1: svuint64_t) -> svuint6
 }
 #[doc = "Rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(urshr, IMM2 = 1))]
@@ -17979,7 +17979,7 @@ pub fn svrshr_n_u64_z<const IMM2: i32>(pg: svbool_t, op1: svuint64_t) -> svuint6
 }
 #[doc = "Rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
@@ -17993,7 +17993,7 @@ pub fn svrshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
 }
 #[doc = "Rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
@@ -18007,7 +18007,7 @@ pub fn svrshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
 }
 #[doc = "Rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
@@ -18021,7 +18021,7 @@ pub fn svrshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
 }
 #[doc = "Rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
@@ -18031,7 +18031,7 @@ pub fn svrshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
 }
 #[doc = "Rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
@@ -18041,7 +18041,7 @@ pub fn svrshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
 }
 #[doc = "Rounding shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))]
@@ -18051,7 +18051,7 @@ pub fn svrshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
 }
 #[doc = "Rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
@@ -18065,7 +18065,7 @@ pub fn svrshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8
 }
 #[doc = "Rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
@@ -18079,7 +18079,7 @@ pub fn svrshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint
 }
 #[doc = "Rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
@@ -18093,7 +18093,7 @@ pub fn svrshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint
 }
 #[doc = "Rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
@@ -18103,7 +18103,7 @@ pub fn svrshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svui
 }
 #[doc = "Rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
@@ -18113,7 +18113,7 @@ pub fn svrshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svu
 }
 #[doc = "Rounding shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))]
@@ -18123,7 +18123,7 @@ pub fn svrshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svu
 }
 #[doc = "Reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursqrte))]
@@ -18139,7 +18139,7 @@ pub fn svrsqrte_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svu
 }
 #[doc = "Reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursqrte))]
@@ -18148,7 +18148,7 @@ pub fn svrsqrte_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursqrte))]
@@ -18157,7 +18157,7 @@ pub fn svrsqrte_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t {
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
@@ -18171,7 +18171,7 @@ pub fn svrsra_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
@@ -18185,7 +18185,7 @@ pub fn svrsra_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
@@ -18199,7 +18199,7 @@ pub fn svrsra_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(srsra, IMM3 = 1))]
@@ -18213,7 +18213,7 @@ pub fn svrsra_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
@@ -18227,7 +18227,7 @@ pub fn svrsra_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
@@ -18241,7 +18241,7 @@ pub fn svrsra_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
@@ -18255,7 +18255,7 @@ pub fn svrsra_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint
 }
 #[doc = "Rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ursra, IMM3 = 1))]
@@ -18269,7 +18269,7 @@ pub fn svrsra_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18285,7 +18285,7 @@ pub fn svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18294,7 +18294,7 @@ pub fn svrsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18310,7 +18310,7 @@ pub fn svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18319,7 +18319,7 @@ pub fn svrsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18335,7 +18335,7 @@ pub fn svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18344,7 +18344,7 @@ pub fn svrsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18353,7 +18353,7 @@ pub fn svrsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18362,7 +18362,7 @@ pub fn svrsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18371,7 +18371,7 @@ pub fn svrsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18380,7 +18380,7 @@ pub fn svrsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18389,7 +18389,7 @@ pub fn svrsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
 }
 #[doc = "Rounding subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnb))]
@@ -18398,7 +18398,7 @@ pub fn svrsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18414,7 +18414,7 @@ pub fn svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18423,7 +18423,7 @@ pub fn svrsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18439,7 +18439,7 @@ pub fn svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18448,7 +18448,7 @@ pub fn svrsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18464,7 +18464,7 @@ pub fn svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18473,7 +18473,7 @@ pub fn svrsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18482,7 +18482,7 @@ pub fn svrsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuin
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18491,7 +18491,7 @@ pub fn svrsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18500,7 +18500,7 @@ pub fn svrsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svui
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18509,7 +18509,7 @@ pub fn svrsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18518,7 +18518,7 @@ pub fn svrsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svui
 }
 #[doc = "Rounding subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(rsubhnt))]
@@ -18527,7 +18527,7 @@ pub fn svrsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_
 }
 #[doc = "Subtract with borrow long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclb))]
@@ -18540,7 +18540,7 @@ pub fn svsbclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint3
 }
 #[doc = "Subtract with borrow long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclb))]
@@ -18549,7 +18549,7 @@ pub fn svsbclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Subtract with borrow long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclb))]
@@ -18562,7 +18562,7 @@ pub fn svsbclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint6
 }
 #[doc = "Subtract with borrow long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclb))]
@@ -18571,7 +18571,7 @@ pub fn svsbclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Subtract with borrow long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclt))]
@@ -18584,7 +18584,7 @@ pub fn svsbclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint3
 }
 #[doc = "Subtract with borrow long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclt))]
@@ -18593,7 +18593,7 @@ pub fn svsbclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t {
 }
 #[doc = "Subtract with borrow long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclt))]
@@ -18606,7 +18606,7 @@ pub fn svsbclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint6
 }
 #[doc = "Subtract with borrow long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sbclt))]
@@ -18615,7 +18615,7 @@ pub fn svsbclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t {
 }
 #[doc = "Shift left long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))]
@@ -18629,7 +18629,7 @@ pub fn svshllb_n_s16<const IMM2: i32>(op1: svint8_t) -> svint16_t {
 }
 #[doc = "Shift left long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))]
@@ -18643,7 +18643,7 @@ pub fn svshllb_n_s32<const IMM2: i32>(op1: svint16_t) -> svint32_t {
 }
 #[doc = "Shift left long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))]
@@ -18657,7 +18657,7 @@ pub fn svshllb_n_s64<const IMM2: i32>(op1: svint32_t) -> svint64_t {
 }
 #[doc = "Shift left long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))]
@@ -18671,7 +18671,7 @@ pub fn svshllb_n_u16<const IMM2: i32>(op1: svuint8_t) -> svuint16_t {
 }
 #[doc = "Shift left long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))]
@@ -18685,7 +18685,7 @@ pub fn svshllb_n_u32<const IMM2: i32>(op1: svuint16_t) -> svuint32_t {
 }
 #[doc = "Shift left long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))]
@@ -18699,7 +18699,7 @@ pub fn svshllb_n_u64<const IMM2: i32>(op1: svuint32_t) -> svuint64_t {
 }
 #[doc = "Shift left long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))]
@@ -18713,7 +18713,7 @@ pub fn svshllt_n_s16<const IMM2: i32>(op1: svint8_t) -> svint16_t {
 }
 #[doc = "Shift left long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))]
@@ -18727,7 +18727,7 @@ pub fn svshllt_n_s32<const IMM2: i32>(op1: svint16_t) -> svint32_t {
 }
 #[doc = "Shift left long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))]
@@ -18741,7 +18741,7 @@ pub fn svshllt_n_s64<const IMM2: i32>(op1: svint32_t) -> svint64_t {
 }
 #[doc = "Shift left long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))]
@@ -18755,7 +18755,7 @@ pub fn svshllt_n_u16<const IMM2: i32>(op1: svuint8_t) -> svuint16_t {
 }
 #[doc = "Shift left long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))]
@@ -18769,7 +18769,7 @@ pub fn svshllt_n_u32<const IMM2: i32>(op1: svuint16_t) -> svuint32_t {
 }
 #[doc = "Shift left long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))]
@@ -18783,7 +18783,7 @@ pub fn svshllt_n_u64<const IMM2: i32>(op1: svuint32_t) -> svuint64_t {
 }
 #[doc = "Shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
@@ -18797,7 +18797,7 @@ pub fn svshrnb_n_s16<const IMM2: i32>(op1: svint16_t) -> svint8_t {
 }
 #[doc = "Shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
@@ -18811,7 +18811,7 @@ pub fn svshrnb_n_s32<const IMM2: i32>(op1: svint32_t) -> svint16_t {
 }
 #[doc = "Shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
@@ -18825,7 +18825,7 @@ pub fn svshrnb_n_s64<const IMM2: i32>(op1: svint64_t) -> svint32_t {
 }
 #[doc = "Shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
@@ -18835,7 +18835,7 @@ pub fn svshrnb_n_u16<const IMM2: i32>(op1: svuint16_t) -> svuint8_t {
 }
 #[doc = "Shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
@@ -18845,7 +18845,7 @@ pub fn svshrnb_n_u32<const IMM2: i32>(op1: svuint32_t) -> svuint16_t {
 }
 #[doc = "Shift right narrow (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))]
@@ -18855,7 +18855,7 @@ pub fn svshrnb_n_u64<const IMM2: i32>(op1: svuint64_t) -> svuint32_t {
 }
 #[doc = "Shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
@@ -18869,7 +18869,7 @@ pub fn svshrnt_n_s16<const IMM2: i32>(even: svint8_t, op1: svint16_t) -> svint8_
 }
 #[doc = "Shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
@@ -18883,7 +18883,7 @@ pub fn svshrnt_n_s32<const IMM2: i32>(even: svint16_t, op1: svint32_t) -> svint1
 }
 #[doc = "Shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
@@ -18897,7 +18897,7 @@ pub fn svshrnt_n_s64<const IMM2: i32>(even: svint32_t, op1: svint64_t) -> svint3
 }
 #[doc = "Shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
@@ -18907,7 +18907,7 @@ pub fn svshrnt_n_u16<const IMM2: i32>(even: svuint8_t, op1: svuint16_t) -> svuin
 }
 #[doc = "Shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
@@ -18917,7 +18917,7 @@ pub fn svshrnt_n_u32<const IMM2: i32>(even: svuint16_t, op1: svuint32_t) -> svui
 }
 #[doc = "Shift right narrow (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))]
@@ -18927,7 +18927,7 @@ pub fn svshrnt_n_u64<const IMM2: i32>(even: svuint32_t, op1: svuint64_t) -> svui
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -18941,7 +18941,7 @@ pub fn svsli_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -18955,7 +18955,7 @@ pub fn svsli_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -18969,7 +18969,7 @@ pub fn svsli_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -18983,7 +18983,7 @@ pub fn svsli_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -18993,7 +18993,7 @@ pub fn svsli_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -19003,7 +19003,7 @@ pub fn svsli_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint1
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -19013,7 +19013,7 @@ pub fn svsli_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint3
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sli, IMM3 = 0))]
@@ -19023,7 +19023,7 @@ pub fn svsli_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint6
 }
 #[doc = "SM4 encryption and decryption"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4e[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-sm4")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sm4e))]
@@ -19036,7 +19036,7 @@ pub fn svsm4e_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "SM4 key updates"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4ekey[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2,sve2-sm4")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sm4ekey))]
@@ -19049,7 +19049,7 @@ pub fn svsm4ekey_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19062,7 +19062,7 @@ pub fn svsqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19071,7 +19071,7 @@ pub fn svsqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19080,7 +19080,7 @@ pub fn svsqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19089,7 +19089,7 @@ pub fn svsqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19098,7 +19098,7 @@ pub fn svsqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19107,7 +19107,7 @@ pub fn svsqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19120,7 +19120,7 @@ pub fn svsqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19129,7 +19129,7 @@ pub fn svsqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19138,7 +19138,7 @@ pub fn svsqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19147,7 +19147,7 @@ pub fn svsqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19156,7 +19156,7 @@ pub fn svsqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19165,7 +19165,7 @@ pub fn svsqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19178,7 +19178,7 @@ pub fn svsqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19187,7 +19187,7 @@ pub fn svsqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19196,7 +19196,7 @@ pub fn svsqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19205,7 +19205,7 @@ pub fn svsqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19214,7 +19214,7 @@ pub fn svsqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19223,7 +19223,7 @@ pub fn svsqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19236,7 +19236,7 @@ pub fn svsqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19245,7 +19245,7 @@ pub fn svsqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19254,7 +19254,7 @@ pub fn svsqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19263,7 +19263,7 @@ pub fn svsqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19272,7 +19272,7 @@ pub fn svsqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_
 }
 #[doc = "Saturating add with signed addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -19281,7 +19281,7 @@ pub fn svsqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t {
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
@@ -19295,7 +19295,7 @@ pub fn svsra_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
@@ -19309,7 +19309,7 @@ pub fn svsra_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
@@ -19323,7 +19323,7 @@ pub fn svsra_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssra, IMM3 = 1))]
@@ -19337,7 +19337,7 @@ pub fn svsra_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
@@ -19351,7 +19351,7 @@ pub fn svsra_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
@@ -19365,7 +19365,7 @@ pub fn svsra_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint1
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
@@ -19379,7 +19379,7 @@ pub fn svsra_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint3
 }
 #[doc = "Shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usra, IMM3 = 1))]
@@ -19393,7 +19393,7 @@ pub fn svsra_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint6
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19407,7 +19407,7 @@ pub fn svsri_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19421,7 +19421,7 @@ pub fn svsri_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19435,7 +19435,7 @@ pub fn svsri_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19449,7 +19449,7 @@ pub fn svsri_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19459,7 +19459,7 @@ pub fn svsri_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19469,7 +19469,7 @@ pub fn svsri_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint1
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19479,7 +19479,7 @@ pub fn svsri_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint3
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sri, IMM3 = 1))]
@@ -19493,7 +19493,7 @@ pub fn svsri_n_u64<const IMM3: i32>(op1: svuint64_t, op2: svuint64_t) -> svuint6
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19523,7 +19523,7 @@ pub unsafe fn svstnt1_scatter_s64index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19553,7 +19553,7 @@ pub unsafe fn svstnt1_scatter_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19571,7 +19571,7 @@ pub unsafe fn svstnt1_scatter_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19589,7 +19589,7 @@ pub unsafe fn svstnt1_scatter_u64index_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19607,7 +19607,7 @@ pub unsafe fn svstnt1_scatter_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19625,7 +19625,7 @@ pub unsafe fn svstnt1_scatter_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19655,7 +19655,7 @@ pub unsafe fn svstnt1_scatter_s64offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19685,7 +19685,7 @@ pub unsafe fn svstnt1_scatter_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19703,7 +19703,7 @@ pub unsafe fn svstnt1_scatter_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19733,7 +19733,7 @@ pub unsafe fn svstnt1_scatter_u32offset_f32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19763,7 +19763,7 @@ pub unsafe fn svstnt1_scatter_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19781,7 +19781,7 @@ pub unsafe fn svstnt1_scatter_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19799,7 +19799,7 @@ pub unsafe fn svstnt1_scatter_u64offset_f64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19817,7 +19817,7 @@ pub unsafe fn svstnt1_scatter_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19836,7 +19836,7 @@ pub unsafe fn svstnt1_scatter_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19850,7 +19850,7 @@ pub unsafe fn svstnt1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19864,7 +19864,7 @@ pub unsafe fn svstnt1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19878,7 +19878,7 @@ pub unsafe fn svstnt1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data:
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19892,7 +19892,7 @@ pub unsafe fn svstnt1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19906,7 +19906,7 @@ pub unsafe fn svstnt1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19920,7 +19920,7 @@ pub unsafe fn svstnt1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data:
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19939,7 +19939,7 @@ pub unsafe fn svstnt1_scatter_u32base_index_f32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19958,7 +19958,7 @@ pub unsafe fn svstnt1_scatter_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -19977,7 +19977,7 @@ pub unsafe fn svstnt1_scatter_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -19996,7 +19996,7 @@ pub unsafe fn svstnt1_scatter_u64base_index_f64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -20015,7 +20015,7 @@ pub unsafe fn svstnt1_scatter_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -20034,7 +20034,7 @@ pub unsafe fn svstnt1_scatter_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20065,7 +20065,7 @@ pub unsafe fn svstnt1_scatter_u32base_offset_f32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20096,7 +20096,7 @@ pub unsafe fn svstnt1_scatter_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20115,7 +20115,7 @@ pub unsafe fn svstnt1_scatter_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -20146,7 +20146,7 @@ pub unsafe fn svstnt1_scatter_u64base_offset_f64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -20177,7 +20177,7 @@ pub unsafe fn svstnt1_scatter_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1d))]
@@ -20195,7 +20195,7 @@ pub unsafe fn svstnt1_scatter_u64base_offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20230,7 +20230,7 @@ pub unsafe fn svstnt1b_scatter_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20265,7 +20265,7 @@ pub unsafe fn svstnt1h_scatter_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20300,7 +20300,7 @@ pub unsafe fn svstnt1w_scatter_s64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20318,7 +20318,7 @@ pub unsafe fn svstnt1b_scatter_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20336,7 +20336,7 @@ pub unsafe fn svstnt1h_scatter_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20354,7 +20354,7 @@ pub unsafe fn svstnt1w_scatter_s64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20389,7 +20389,7 @@ pub unsafe fn svstnt1b_scatter_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20424,7 +20424,7 @@ pub unsafe fn svstnt1h_scatter_u32offset_s32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20442,7 +20442,7 @@ pub unsafe fn svstnt1b_scatter_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20460,7 +20460,7 @@ pub unsafe fn svstnt1h_scatter_u32offset_u32(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20478,7 +20478,7 @@ pub unsafe fn svstnt1b_scatter_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20496,7 +20496,7 @@ pub unsafe fn svstnt1h_scatter_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20514,7 +20514,7 @@ pub unsafe fn svstnt1w_scatter_u64offset_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20532,7 +20532,7 @@ pub unsafe fn svstnt1b_scatter_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20550,7 +20550,7 @@ pub unsafe fn svstnt1h_scatter_u64offset_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20569,7 +20569,7 @@ pub unsafe fn svstnt1w_scatter_u64offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20605,7 +20605,7 @@ pub unsafe fn svstnt1b_scatter_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20641,7 +20641,7 @@ pub unsafe fn svstnt1h_scatter_u32base_offset_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20660,7 +20660,7 @@ pub unsafe fn svstnt1b_scatter_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20679,7 +20679,7 @@ pub unsafe fn svstnt1h_scatter_u32base_offset_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20715,7 +20715,7 @@ pub unsafe fn svstnt1b_scatter_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20751,7 +20751,7 @@ pub unsafe fn svstnt1h_scatter_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20787,7 +20787,7 @@ pub unsafe fn svstnt1w_scatter_u64base_offset_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20806,7 +20806,7 @@ pub unsafe fn svstnt1b_scatter_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20825,7 +20825,7 @@ pub unsafe fn svstnt1h_scatter_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20844,7 +20844,7 @@ pub unsafe fn svstnt1w_scatter_u64base_offset_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20858,7 +20858,7 @@ pub unsafe fn svstnt1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20872,7 +20872,7 @@ pub unsafe fn svstnt1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20886,7 +20886,7 @@ pub unsafe fn svstnt1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20900,7 +20900,7 @@ pub unsafe fn svstnt1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20914,7 +20914,7 @@ pub unsafe fn svstnt1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20928,7 +20928,7 @@ pub unsafe fn svstnt1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20942,7 +20942,7 @@ pub unsafe fn svstnt1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1b))]
@@ -20956,7 +20956,7 @@ pub unsafe fn svstnt1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -20970,7 +20970,7 @@ pub unsafe fn svstnt1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -20983,7 +20983,7 @@ pub unsafe fn svstnt1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21018,7 +21018,7 @@ pub unsafe fn svstnt1h_scatter_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -21053,7 +21053,7 @@ pub unsafe fn svstnt1w_scatter_s64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21071,7 +21071,7 @@ pub unsafe fn svstnt1h_scatter_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -21089,7 +21089,7 @@ pub unsafe fn svstnt1w_scatter_s64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21107,7 +21107,7 @@ pub unsafe fn svstnt1h_scatter_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -21125,7 +21125,7 @@ pub unsafe fn svstnt1w_scatter_u64index_s64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21143,7 +21143,7 @@ pub unsafe fn svstnt1h_scatter_u64index_u64(
 #[doc = "  * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."]
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -21162,7 +21162,7 @@ pub unsafe fn svstnt1w_scatter_u64index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21181,7 +21181,7 @@ pub unsafe fn svstnt1h_scatter_u32base_index_s32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21200,7 +21200,7 @@ pub unsafe fn svstnt1h_scatter_u32base_index_u32(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21219,7 +21219,7 @@ pub unsafe fn svstnt1h_scatter_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -21238,7 +21238,7 @@ pub unsafe fn svstnt1w_scatter_u64base_index_s64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1h))]
@@ -21257,7 +21257,7 @@ pub unsafe fn svstnt1h_scatter_u64base_index_u64(
 #[doc = "  * This dereferences and accesses the calculated address for each active element (governed by `pg`)."]
 #[doc = "  * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before  using it."]
 #[doc = "  * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(stnt1w))]
@@ -21271,7 +21271,7 @@ pub unsafe fn svstnt1w_scatter_u64base_index_u64(
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21284,7 +21284,7 @@ pub fn svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21293,7 +21293,7 @@ pub fn svsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21306,7 +21306,7 @@ pub fn svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21315,7 +21315,7 @@ pub fn svsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21328,7 +21328,7 @@ pub fn svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21337,7 +21337,7 @@ pub fn svsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21346,7 +21346,7 @@ pub fn svsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21355,7 +21355,7 @@ pub fn svsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21364,7 +21364,7 @@ pub fn svsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21373,7 +21373,7 @@ pub fn svsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21382,7 +21382,7 @@ pub fn svsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t {
 }
 #[doc = "Subtract narrow high part (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnb))]
@@ -21391,7 +21391,7 @@ pub fn svsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t {
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21404,7 +21404,7 @@ pub fn svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21413,7 +21413,7 @@ pub fn svsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t {
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21426,7 +21426,7 @@ pub fn svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21435,7 +21435,7 @@ pub fn svsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t {
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21448,7 +21448,7 @@ pub fn svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21457,7 +21457,7 @@ pub fn svsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t {
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21466,7 +21466,7 @@ pub fn svsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21475,7 +21475,7 @@ pub fn svsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t {
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21484,7 +21484,7 @@ pub fn svsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuin
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21493,7 +21493,7 @@ pub fn svsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21502,7 +21502,7 @@ pub fn svsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuin
 }
 #[doc = "Subtract narrow high part (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(subhnt))]
@@ -21511,7 +21511,7 @@ pub fn svsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublb))]
@@ -21524,7 +21524,7 @@ pub fn svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublb))]
@@ -21533,7 +21533,7 @@ pub fn svsublb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublb))]
@@ -21546,7 +21546,7 @@ pub fn svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublb))]
@@ -21555,7 +21555,7 @@ pub fn svsublb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublb))]
@@ -21568,7 +21568,7 @@ pub fn svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublb))]
@@ -21577,7 +21577,7 @@ pub fn svsublb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublb))]
@@ -21590,7 +21590,7 @@ pub fn svsublb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublb))]
@@ -21599,7 +21599,7 @@ pub fn svsublb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublb))]
@@ -21612,7 +21612,7 @@ pub fn svsublb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublb))]
@@ -21621,7 +21621,7 @@ pub fn svsublb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublb))]
@@ -21634,7 +21634,7 @@ pub fn svsublb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Subtract long (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublb))]
@@ -21643,7 +21643,7 @@ pub fn svsublb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Subtract long (bottom - top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublbt))]
@@ -21659,7 +21659,7 @@ pub fn svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Subtract long (bottom - top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublbt))]
@@ -21668,7 +21668,7 @@ pub fn svsublbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Subtract long (bottom - top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublbt))]
@@ -21684,7 +21684,7 @@ pub fn svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Subtract long (bottom - top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublbt))]
@@ -21693,7 +21693,7 @@ pub fn svsublbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Subtract long (bottom - top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublbt))]
@@ -21709,7 +21709,7 @@ pub fn svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Subtract long (bottom - top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublbt))]
@@ -21718,7 +21718,7 @@ pub fn svsublbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublt))]
@@ -21731,7 +21731,7 @@ pub fn svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublt))]
@@ -21740,7 +21740,7 @@ pub fn svsublt_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublt))]
@@ -21753,7 +21753,7 @@ pub fn svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublt))]
@@ -21762,7 +21762,7 @@ pub fn svsublt_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublt))]
@@ -21775,7 +21775,7 @@ pub fn svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssublt))]
@@ -21784,7 +21784,7 @@ pub fn svsublt_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublt))]
@@ -21797,7 +21797,7 @@ pub fn svsublt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublt))]
@@ -21806,7 +21806,7 @@ pub fn svsublt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublt))]
@@ -21819,7 +21819,7 @@ pub fn svsublt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublt))]
@@ -21828,7 +21828,7 @@ pub fn svsublt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublt))]
@@ -21841,7 +21841,7 @@ pub fn svsublt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Subtract long (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usublt))]
@@ -21850,7 +21850,7 @@ pub fn svsublt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Subtract long (top - bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubltb))]
@@ -21866,7 +21866,7 @@ pub fn svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Subtract long (top - bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubltb))]
@@ -21875,7 +21875,7 @@ pub fn svsubltb_n_s16(op1: svint8_t, op2: i8) -> svint16_t {
 }
 #[doc = "Subtract long (top - bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubltb))]
@@ -21891,7 +21891,7 @@ pub fn svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Subtract long (top - bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubltb))]
@@ -21900,7 +21900,7 @@ pub fn svsubltb_n_s32(op1: svint16_t, op2: i16) -> svint32_t {
 }
 #[doc = "Subtract long (top - bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubltb))]
@@ -21916,7 +21916,7 @@ pub fn svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Subtract long (top - bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubltb))]
@@ -21925,7 +21925,7 @@ pub fn svsubltb_n_s64(op1: svint32_t, op2: i32) -> svint64_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwb))]
@@ -21938,7 +21938,7 @@ pub fn svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwb))]
@@ -21947,7 +21947,7 @@ pub fn svsubwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwb))]
@@ -21960,7 +21960,7 @@ pub fn svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwb))]
@@ -21969,7 +21969,7 @@ pub fn svsubwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwb))]
@@ -21982,7 +21982,7 @@ pub fn svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwb))]
@@ -21991,7 +21991,7 @@ pub fn svsubwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwb))]
@@ -22004,7 +22004,7 @@ pub fn svsubwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwb))]
@@ -22013,7 +22013,7 @@ pub fn svsubwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwb))]
@@ -22026,7 +22026,7 @@ pub fn svsubwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwb))]
@@ -22035,7 +22035,7 @@ pub fn svsubwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwb))]
@@ -22048,7 +22048,7 @@ pub fn svsubwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Subtract wide (bottom)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwb))]
@@ -22057,7 +22057,7 @@ pub fn svsubwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwt))]
@@ -22070,7 +22070,7 @@ pub fn svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwt))]
@@ -22079,7 +22079,7 @@ pub fn svsubwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwt))]
@@ -22092,7 +22092,7 @@ pub fn svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwt))]
@@ -22101,7 +22101,7 @@ pub fn svsubwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwt))]
@@ -22114,7 +22114,7 @@ pub fn svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(ssubwt))]
@@ -22123,7 +22123,7 @@ pub fn svsubwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwt))]
@@ -22136,7 +22136,7 @@ pub fn svsubwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwt))]
@@ -22145,7 +22145,7 @@ pub fn svsubwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwt))]
@@ -22158,7 +22158,7 @@ pub fn svsubwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwt))]
@@ -22167,7 +22167,7 @@ pub fn svsubwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwt))]
@@ -22180,7 +22180,7 @@ pub fn svsubwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t {
 }
 #[doc = "Subtract wide (top)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(usubwt))]
@@ -22189,7 +22189,7 @@ pub fn svsubwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22208,7 +22208,7 @@ pub fn svtbl2_f32(data: svfloat32x2_t, indices: svuint32_t) -> svfloat32_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22227,7 +22227,7 @@ pub fn svtbl2_f64(data: svfloat64x2_t, indices: svuint64_t) -> svfloat64_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22246,7 +22246,7 @@ pub fn svtbl2_s8(data: svint8x2_t, indices: svuint8_t) -> svint8_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22265,7 +22265,7 @@ pub fn svtbl2_s16(data: svint16x2_t, indices: svuint16_t) -> svint16_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22284,7 +22284,7 @@ pub fn svtbl2_s32(data: svint32x2_t, indices: svuint32_t) -> svint32_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22303,7 +22303,7 @@ pub fn svtbl2_s64(data: svint64x2_t, indices: svuint64_t) -> svint64_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22312,7 +22312,7 @@ pub fn svtbl2_u8(data: svuint8x2_t, indices: svuint8_t) -> svuint8_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22321,7 +22321,7 @@ pub fn svtbl2_u16(data: svuint16x2_t, indices: svuint16_t) -> svuint16_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22330,7 +22330,7 @@ pub fn svtbl2_u32(data: svuint32x2_t, indices: svuint32_t) -> svuint32_t {
 }
 #[doc = "Table lookup in two-vector table"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -22339,7 +22339,7 @@ pub fn svtbl2_u64(data: svuint64x2_t, indices: svuint64_t) -> svuint64_t {
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22352,7 +22352,7 @@ pub fn svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svuint32_t)
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22365,7 +22365,7 @@ pub fn svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svuint64_t)
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22378,7 +22378,7 @@ pub fn svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svuint8_t) -> svint
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22391,7 +22391,7 @@ pub fn svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svuint16_t) -> s
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22404,7 +22404,7 @@ pub fn svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svuint32_t) -> s
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22417,7 +22417,7 @@ pub fn svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svuint64_t) -> s
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22426,7 +22426,7 @@ pub fn svtbx_u8(fallback: svuint8_t, data: svuint8_t, indices: svuint8_t) -> svu
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22435,7 +22435,7 @@ pub fn svtbx_u16(fallback: svuint16_t, data: svuint16_t, indices: svuint16_t) ->
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22444,7 +22444,7 @@ pub fn svtbx_u32(fallback: svuint32_t, data: svuint32_t, indices: svuint32_t) ->
 }
 #[doc = "Table lookup in single-vector table (merging)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -22453,7 +22453,7 @@ pub fn svtbx_u64(fallback: svuint64_t, data: svuint64_t, indices: svuint64_t) ->
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_b])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(punpkhi))]
@@ -22469,7 +22469,7 @@ pub fn svunpkhi_b(op: svbool_t) -> svbool_t {
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sunpkhi))]
@@ -22485,7 +22485,7 @@ pub fn svunpkhi_s16(op: svint8_t) -> svint16_t {
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sunpkhi))]
@@ -22501,7 +22501,7 @@ pub fn svunpkhi_s32(op: svint16_t) -> svint32_t {
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sunpkhi))]
@@ -22517,7 +22517,7 @@ pub fn svunpkhi_s64(op: svint32_t) -> svint64_t {
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uunpkhi))]
@@ -22533,7 +22533,7 @@ pub fn svunpkhi_u16(op: svuint8_t) -> svuint16_t {
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uunpkhi))]
@@ -22549,7 +22549,7 @@ pub fn svunpkhi_u32(op: svuint16_t) -> svuint32_t {
 }
 #[doc = "Unpack and extend high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uunpkhi))]
@@ -22565,7 +22565,7 @@ pub fn svunpkhi_u64(op: svuint32_t) -> svuint64_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_b])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(punpklo))]
@@ -22581,7 +22581,7 @@ pub fn svunpklo_b(op: svbool_t) -> svbool_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sunpklo))]
@@ -22597,7 +22597,7 @@ pub fn svunpklo_s16(op: svint8_t) -> svint16_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sunpklo))]
@@ -22613,7 +22613,7 @@ pub fn svunpklo_s32(op: svint16_t) -> svint32_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(sunpklo))]
@@ -22629,7 +22629,7 @@ pub fn svunpklo_s64(op: svint32_t) -> svint64_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uunpklo))]
@@ -22645,7 +22645,7 @@ pub fn svunpklo_u16(op: svuint8_t) -> svuint16_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uunpklo))]
@@ -22661,7 +22661,7 @@ pub fn svunpklo_u32(op: svuint16_t) -> svuint32_t {
 }
 #[doc = "Unpack and extend low half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(uunpklo))]
@@ -22677,7 +22677,7 @@ pub fn svunpklo_u64(op: svuint32_t) -> svuint64_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22690,7 +22690,7 @@ pub fn svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22699,7 +22699,7 @@ pub fn svuqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22708,7 +22708,7 @@ pub fn svuqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22717,7 +22717,7 @@ pub fn svuqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22726,7 +22726,7 @@ pub fn svuqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22735,7 +22735,7 @@ pub fn svuqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22748,7 +22748,7 @@ pub fn svuqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22757,7 +22757,7 @@ pub fn svuqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22766,7 +22766,7 @@ pub fn svuqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22775,7 +22775,7 @@ pub fn svuqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22784,7 +22784,7 @@ pub fn svuqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22793,7 +22793,7 @@ pub fn svuqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22806,7 +22806,7 @@ pub fn svuqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22815,7 +22815,7 @@ pub fn svuqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22824,7 +22824,7 @@ pub fn svuqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22833,7 +22833,7 @@ pub fn svuqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22842,7 +22842,7 @@ pub fn svuqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22851,7 +22851,7 @@ pub fn svuqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22864,7 +22864,7 @@ pub fn svuqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_m)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22873,7 +22873,7 @@ pub fn svuqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22882,7 +22882,7 @@ pub fn svuqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_x)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22891,7 +22891,7 @@ pub fn svuqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22900,7 +22900,7 @@ pub fn svuqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t
 }
 #[doc = "Saturating add with unsigned addend"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_z)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -22909,7 +22909,7 @@ pub fn svuqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -22925,7 +22925,7 @@ pub fn svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -22941,7 +22941,7 @@ pub fn svwhilege_b16_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -22957,7 +22957,7 @@ pub fn svwhilege_b32_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -22973,7 +22973,7 @@ pub fn svwhilege_b64_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -22989,7 +22989,7 @@ pub fn svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -23005,7 +23005,7 @@ pub fn svwhilege_b16_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -23021,7 +23021,7 @@ pub fn svwhilege_b32_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilege))]
@@ -23037,7 +23037,7 @@ pub fn svwhilege_b64_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23053,7 +23053,7 @@ pub fn svwhilege_b8_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23069,7 +23069,7 @@ pub fn svwhilege_b16_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23085,7 +23085,7 @@ pub fn svwhilege_b32_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23101,7 +23101,7 @@ pub fn svwhilege_b64_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23117,7 +23117,7 @@ pub fn svwhilege_b8_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23133,7 +23133,7 @@ pub fn svwhilege_b16_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23149,7 +23149,7 @@ pub fn svwhilege_b32_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than or equal to"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehs))]
@@ -23165,7 +23165,7 @@ pub fn svwhilege_b64_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23181,7 +23181,7 @@ pub fn svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23197,7 +23197,7 @@ pub fn svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23213,7 +23213,7 @@ pub fn svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23229,7 +23229,7 @@ pub fn svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23245,7 +23245,7 @@ pub fn svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23261,7 +23261,7 @@ pub fn svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23277,7 +23277,7 @@ pub fn svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilegt))]
@@ -23293,7 +23293,7 @@ pub fn svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23309,7 +23309,7 @@ pub fn svwhilegt_b8_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23325,7 +23325,7 @@ pub fn svwhilegt_b16_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23341,7 +23341,7 @@ pub fn svwhilegt_b32_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23357,7 +23357,7 @@ pub fn svwhilegt_b64_u32(op1: u32, op2: u32) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23373,7 +23373,7 @@ pub fn svwhilegt_b8_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23389,7 +23389,7 @@ pub fn svwhilegt_b16_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23405,7 +23405,7 @@ pub fn svwhilegt_b32_u64(op1: u64, op2: u64) -> svbool_t {
 }
 #[doc = "While decrementing scalar is greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilehi))]
@@ -23419,7 +23419,7 @@ pub fn svwhilegt_b64_u64(op1: u64, op2: u64) -> svbool_t {
     }
     unsafe { _svwhilegt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilerw_8ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23437,7 +23437,7 @@ unsafe fn svwhilerw_8ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
     }
     _svwhilerw_8ptr(op1, op2)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilerw_16ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23455,7 +23455,7 @@ unsafe fn svwhilerw_16ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
     }
     _svwhilerw_16ptr(op1, op2).sve_into()
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilerw_32ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23473,7 +23473,7 @@ unsafe fn svwhilerw_32ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
     }
     _svwhilerw_32ptr(op1, op2).sve_into()
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilerw_64ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23495,7 +23495,7 @@ unsafe fn svwhilerw_64ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f32])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23506,7 +23506,7 @@ pub unsafe fn svwhilerw_f32(op1: *const f32, op2: *const f32) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f64])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23517,7 +23517,7 @@ pub unsafe fn svwhilerw_f64(op1: *const f64, op2: *const f64) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s8])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23528,7 +23528,7 @@ pub unsafe fn svwhilerw_s8(op1: *const i8, op2: *const i8) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s16])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23539,7 +23539,7 @@ pub unsafe fn svwhilerw_s16(op1: *const i16, op2: *const i16) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s32])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23550,7 +23550,7 @@ pub unsafe fn svwhilerw_s32(op1: *const i32, op2: *const i32) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s64])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23561,7 +23561,7 @@ pub unsafe fn svwhilerw_s64(op1: *const i64, op2: *const i64) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u8])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23572,7 +23572,7 @@ pub unsafe fn svwhilerw_u8(op1: *const u8, op2: *const u8) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u16])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23583,7 +23583,7 @@ pub unsafe fn svwhilerw_u16(op1: *const u16, op2: *const u16) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u32])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
@@ -23594,14 +23594,14 @@ pub unsafe fn svwhilerw_u32(op1: *const u32, op2: *const u32) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u64])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilerw))]
 pub unsafe fn svwhilerw_u64(op1: *const u64, op2: *const u64) -> svbool_t {
     svwhilerw_64ptr::<u64>(op1, op2)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilewr_8ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23619,7 +23619,7 @@ unsafe fn svwhilewr_8ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
     }
     _svwhilewr_8ptr(op1, op2)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilewr_16ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23637,7 +23637,7 @@ unsafe fn svwhilewr_16ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
     }
     _svwhilewr_16ptr(op1, op2).sve_into()
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilewr_32ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23655,7 +23655,7 @@ unsafe fn svwhilewr_32ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
     }
     _svwhilewr_32ptr(op1, op2).sve_into()
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 unsafe fn svwhilewr_64ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
@@ -23677,7 +23677,7 @@ unsafe fn svwhilewr_64ptr<T>(op1: *const T, op2: *const T) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f32])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23688,7 +23688,7 @@ pub unsafe fn svwhilewr_f32(op1: *const f32, op2: *const f32) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f64])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23699,7 +23699,7 @@ pub unsafe fn svwhilewr_f64(op1: *const f64, op2: *const f64) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s8])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23710,7 +23710,7 @@ pub unsafe fn svwhilewr_s8(op1: *const i8, op2: *const i8) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s16])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23721,7 +23721,7 @@ pub unsafe fn svwhilewr_s16(op1: *const i16, op2: *const i16) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s32])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23732,7 +23732,7 @@ pub unsafe fn svwhilewr_s32(op1: *const i32, op2: *const i32) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s64])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23743,7 +23743,7 @@ pub unsafe fn svwhilewr_s64(op1: *const i64, op2: *const i64) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u8])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23754,7 +23754,7 @@ pub unsafe fn svwhilewr_u8(op1: *const u8, op2: *const u8) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u16])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23765,7 +23765,7 @@ pub unsafe fn svwhilewr_u16(op1: *const u16, op2: *const u16) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u32])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23776,7 +23776,7 @@ pub unsafe fn svwhilewr_u32(op1: *const u32, op2: *const u32) -> svbool_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u64])"]
 #[doc = "## Safety"]
 #[doc = "  * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(whilewr))]
@@ -23785,7 +23785,7 @@ pub unsafe fn svwhilewr_u64(op1: *const u64, op2: *const u64) -> svbool_t {
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23799,7 +23799,7 @@ pub fn svxar_n_s8<const IMM3: i32>(op1: svint8_t, op2: svint8_t) -> svint8_t {
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23813,7 +23813,7 @@ pub fn svxar_n_s16<const IMM3: i32>(op1: svint16_t, op2: svint16_t) -> svint16_t
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23827,7 +23827,7 @@ pub fn svxar_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23841,7 +23841,7 @@ pub fn svxar_n_s64<const IMM3: i32>(op1: svint64_t, op2: svint64_t) -> svint64_t
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u8])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23851,7 +23851,7 @@ pub fn svxar_n_u8<const IMM3: i32>(op1: svuint8_t, op2: svuint8_t) -> svuint8_t
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u16])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23861,7 +23861,7 @@ pub fn svxar_n_u16<const IMM3: i32>(op1: svuint16_t, op2: svuint16_t) -> svuint1
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u32])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
@@ -23871,7 +23871,7 @@ pub fn svxar_n_u32<const IMM3: i32>(op1: svuint32_t, op2: svuint32_t) -> svuint3
 }
 #[doc = "Bitwise exclusive OR and rotate right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u64])"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sve,sve2")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(xar, IMM3 = 1))]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 28a978fdbb..84c1a91adf 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "CRC32 single round checksum for bytes (8 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32b))]
@@ -39,7 +39,7 @@ pub fn __crc32b(crc: u32, data: u8) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (8 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32cb))]
@@ -64,7 +64,7 @@ pub fn __crc32cb(crc: u32, data: u8) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(crc32cw))]
@@ -83,7 +83,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (16 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32ch))]
@@ -108,7 +108,7 @@ pub fn __crc32ch(crc: u32, data: u16) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (32 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32cw))]
@@ -133,7 +133,7 @@ pub fn __crc32cw(crc: u32, data: u32) -> u32 {
 }
 #[doc = "CRC32 single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(crc32w))]
@@ -152,7 +152,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32 single round checksum for bytes (16 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32h))]
@@ -177,7 +177,7 @@ pub fn __crc32h(crc: u32, data: u16) -> u32 {
 }
 #[doc = "CRC32 single round checksum for bytes (32 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32w))]
@@ -202,7 +202,7 @@ pub fn __crc32w(crc: u32, data: u32) -> u32 {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -220,7 +220,7 @@ fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -238,7 +238,7 @@ fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -256,7 +256,7 @@ fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -274,7 +274,7 @@ fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -292,7 +292,7 @@ fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -310,7 +310,7 @@ fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -328,7 +328,7 @@ fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -346,7 +346,7 @@ fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -364,7 +364,7 @@ fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -382,7 +382,7 @@ fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -400,7 +400,7 @@ fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -418,7 +418,7 @@ fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
@@ -439,7 +439,7 @@ pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
@@ -460,7 +460,7 @@ pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
@@ -481,7 +481,7 @@ pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
@@ -502,7 +502,7 @@ pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
@@ -523,7 +523,7 @@ pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
@@ -544,7 +544,7 @@ pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
@@ -569,7 +569,7 @@ pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
@@ -594,7 +594,7 @@ pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
@@ -619,7 +619,7 @@ pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
@@ -641,7 +641,7 @@ pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
@@ -663,7 +663,7 @@ pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
@@ -685,7 +685,7 @@ pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
@@ -706,7 +706,7 @@ pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
@@ -727,7 +727,7 @@ pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
@@ -748,7 +748,7 @@ pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
@@ -769,7 +769,7 @@ pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
@@ -790,7 +790,7 @@ pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
@@ -811,7 +811,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
 #[cfg_attr(
@@ -841,7 +841,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
 #[cfg_attr(
@@ -871,7 +871,7 @@ pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
@@ -900,7 +900,7 @@ pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
@@ -929,7 +929,7 @@ pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
@@ -958,7 +958,7 @@ pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
@@ -987,7 +987,7 @@ pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
@@ -1016,7 +1016,7 @@ pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
@@ -1045,7 +1045,7 @@ pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
@@ -1074,7 +1074,7 @@ pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
@@ -1103,7 +1103,7 @@ pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
@@ -1132,7 +1132,7 @@ pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
@@ -1161,7 +1161,7 @@ pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
@@ -1190,7 +1190,7 @@ pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
@@ -1219,7 +1219,7 @@ pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
@@ -1248,7 +1248,7 @@ pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
@@ -1277,7 +1277,7 @@ pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
@@ -1301,7 +1301,7 @@ pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
@@ -1325,7 +1325,7 @@ pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
@@ -1349,7 +1349,7 @@ pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
@@ -1370,7 +1370,7 @@ pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
@@ -1391,7 +1391,7 @@ pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
@@ -1412,7 +1412,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1434,7 +1434,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1456,7 +1456,7 @@ pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1477,7 +1477,7 @@ pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1498,7 +1498,7 @@ pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1523,7 +1523,7 @@ pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1548,7 +1548,7 @@ pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1573,7 +1573,7 @@ pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1598,7 +1598,7 @@ pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1623,7 +1623,7 @@ pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1648,7 +1648,7 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1663,7 +1663,7 @@ pub fn vabsh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -1685,7 +1685,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -1707,7 +1707,7 @@ pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1728,7 +1728,7 @@ pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1749,7 +1749,7 @@ pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1770,7 +1770,7 @@ pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1791,7 +1791,7 @@ pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1812,7 +1812,7 @@ pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1833,7 +1833,7 @@ pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1854,7 +1854,7 @@ pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1875,7 +1875,7 @@ pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1896,7 +1896,7 @@ pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1917,7 +1917,7 @@ pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1938,7 +1938,7 @@ pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1959,7 +1959,7 @@ pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1980,7 +1980,7 @@ pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2001,7 +2001,7 @@ pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2022,7 +2022,7 @@ pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2043,7 +2043,7 @@ pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2064,7 +2064,7 @@ pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2085,7 +2085,7 @@ pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2106,7 +2106,7 @@ pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2127,7 +2127,7 @@ pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2148,7 +2148,7 @@ pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2169,7 +2169,7 @@ pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -2184,7 +2184,7 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2208,7 +2208,7 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2232,7 +2232,7 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2256,7 +2256,7 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2280,7 +2280,7 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2304,7 +2304,7 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2328,7 +2328,7 @@ pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2349,7 +2349,7 @@ pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2370,7 +2370,7 @@ pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2391,7 +2391,7 @@ pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2412,7 +2412,7 @@ pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2433,7 +2433,7 @@ pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2454,7 +2454,7 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2481,7 +2481,7 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2508,7 +2508,7 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2535,7 +2535,7 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2562,7 +2562,7 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2589,7 +2589,7 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2616,7 +2616,7 @@ pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2641,7 +2641,7 @@ pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2666,7 +2666,7 @@ pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2691,7 +2691,7 @@ pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2716,7 +2716,7 @@ pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2741,7 +2741,7 @@ pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2766,7 +2766,7 @@ pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2787,7 +2787,7 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2812,7 +2812,7 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2837,7 +2837,7 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2862,7 +2862,7 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2887,7 +2887,7 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2912,7 +2912,7 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2937,7 +2937,7 @@ pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2961,7 +2961,7 @@ pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2985,7 +2985,7 @@ pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3009,7 +3009,7 @@ pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3033,7 +3033,7 @@ pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3057,7 +3057,7 @@ pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3081,7 +3081,7 @@ pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "AES single round encryption."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesd))]
@@ -3106,7 +3106,7 @@ pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES single round encryption."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aese))]
@@ -3131,7 +3131,7 @@ pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES inverse mix columns."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesimc))]
@@ -3156,7 +3156,7 @@ pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES mix columns."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesmc))]
@@ -3181,7 +3181,7 @@ pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3202,7 +3202,7 @@ pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3223,7 +3223,7 @@ pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3244,7 +3244,7 @@ pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3265,7 +3265,7 @@ pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3286,7 +3286,7 @@ pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3307,7 +3307,7 @@ pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3328,7 +3328,7 @@ pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3349,7 +3349,7 @@ pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3370,7 +3370,7 @@ pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3391,7 +3391,7 @@ pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3412,7 +3412,7 @@ pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3433,7 +3433,7 @@ pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3454,7 +3454,7 @@ pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3475,7 +3475,7 @@ pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3496,7 +3496,7 @@ pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3517,7 +3517,7 @@ pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3539,7 +3539,7 @@ pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3561,7 +3561,7 @@ pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3583,7 +3583,7 @@ pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3605,7 +3605,7 @@ pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3627,7 +3627,7 @@ pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3649,7 +3649,7 @@ pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3671,7 +3671,7 @@ pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3693,7 +3693,7 @@ pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3715,7 +3715,7 @@ pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3737,7 +3737,7 @@ pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3759,7 +3759,7 @@ pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3781,7 +3781,7 @@ pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3803,7 +3803,7 @@ pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3825,7 +3825,7 @@ pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3847,7 +3847,7 @@ pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3869,7 +3869,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3897,7 +3897,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3925,7 +3925,7 @@ pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3952,7 +3952,7 @@ pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3979,7 +3979,7 @@ pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4006,7 +4006,7 @@ pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4033,7 +4033,7 @@ pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4060,7 +4060,7 @@ pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4087,7 +4087,7 @@ pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4114,7 +4114,7 @@ pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4141,7 +4141,7 @@ pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4168,7 +4168,7 @@ pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4195,7 +4195,7 @@ pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4222,7 +4222,7 @@ pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4249,7 +4249,7 @@ pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4276,7 +4276,7 @@ pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4303,7 +4303,7 @@ pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4330,7 +4330,7 @@ pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4357,7 +4357,7 @@ pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4384,7 +4384,7 @@ pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4411,7 +4411,7 @@ pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4438,7 +4438,7 @@ pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4465,7 +4465,7 @@ pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4492,7 +4492,7 @@ pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4519,7 +4519,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4549,7 +4549,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4579,7 +4579,7 @@ pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4608,7 +4608,7 @@ pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4637,7 +4637,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4667,7 +4667,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4697,7 +4697,7 @@ pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4726,7 +4726,7 @@ pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4755,7 +4755,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4777,7 +4777,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4799,7 +4799,7 @@ pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4820,7 +4820,7 @@ pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4841,7 +4841,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4863,7 +4863,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4885,7 +4885,7 @@ pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4906,7 +4906,7 @@ pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4927,7 +4927,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
 #[cfg_attr(
@@ -4949,7 +4949,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
 #[cfg_attr(
@@ -4971,7 +4971,7 @@ pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
@@ -4992,7 +4992,7 @@ pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
@@ -5013,7 +5013,7 @@ pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5034,7 +5034,7 @@ pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5055,7 +5055,7 @@ pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5076,7 +5076,7 @@ pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5097,7 +5097,7 @@ pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5118,7 +5118,7 @@ pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5139,7 +5139,7 @@ pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5160,7 +5160,7 @@ pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5181,7 +5181,7 @@ pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5202,7 +5202,7 @@ pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5223,7 +5223,7 @@ pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5244,7 +5244,7 @@ pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5265,7 +5265,7 @@ pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5286,7 +5286,7 @@ pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5307,7 +5307,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5329,7 +5329,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5351,7 +5351,7 @@ pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -5372,7 +5372,7 @@ pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -5393,7 +5393,7 @@ pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -5414,7 +5414,7 @@ pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -5435,7 +5435,7 @@ pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -5456,7 +5456,7 @@ pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -5477,7 +5477,7 @@ pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -5498,7 +5498,7 @@ pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -5519,7 +5519,7 @@ pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -5540,7 +5540,7 @@ pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -5561,7 +5561,7 @@ pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -5582,7 +5582,7 @@ pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -5603,7 +5603,7 @@ pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -5624,7 +5624,7 @@ pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -5645,7 +5645,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5668,7 +5668,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5691,7 +5691,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -5713,7 +5713,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -5735,7 +5735,7 @@ pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -5756,7 +5756,7 @@ pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -5777,7 +5777,7 @@ pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -5798,7 +5798,7 @@ pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -5819,7 +5819,7 @@ pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -5840,7 +5840,7 @@ pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -5861,7 +5861,7 @@ pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -5882,7 +5882,7 @@ pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -5903,7 +5903,7 @@ pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -5924,7 +5924,7 @@ pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -5945,7 +5945,7 @@ pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -5966,7 +5966,7 @@ pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -5987,7 +5987,7 @@ pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -6008,7 +6008,7 @@ pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -6029,7 +6029,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6052,7 +6052,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6075,7 +6075,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -6097,7 +6097,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -6119,7 +6119,7 @@ pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -6140,7 +6140,7 @@ pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -6161,7 +6161,7 @@ pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -6182,7 +6182,7 @@ pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -6203,7 +6203,7 @@ pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -6224,7 +6224,7 @@ pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -6245,7 +6245,7 @@ pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -6266,7 +6266,7 @@ pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -6287,7 +6287,7 @@ pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -6308,7 +6308,7 @@ pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -6329,7 +6329,7 @@ pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -6350,7 +6350,7 @@ pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -6371,7 +6371,7 @@ pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -6392,7 +6392,7 @@ pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -6413,7 +6413,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
 #[cfg_attr(
@@ -6436,7 +6436,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
 #[cfg_attr(
@@ -6459,7 +6459,7 @@ pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
@@ -6488,7 +6488,7 @@ pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
@@ -6517,7 +6517,7 @@ pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
@@ -6546,7 +6546,7 @@ pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
@@ -6575,7 +6575,7 @@ pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
@@ -6604,7 +6604,7 @@ pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
@@ -6633,7 +6633,7 @@ pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6654,7 +6654,7 @@ pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6675,7 +6675,7 @@ pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6696,7 +6696,7 @@ pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6717,7 +6717,7 @@ pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6738,7 +6738,7 @@ pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6759,7 +6759,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6781,7 +6781,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6803,7 +6803,7 @@ pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -6824,7 +6824,7 @@ pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -6845,7 +6845,7 @@ pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -6866,7 +6866,7 @@ pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -6887,7 +6887,7 @@ pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -6908,7 +6908,7 @@ pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -6929,7 +6929,7 @@ pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -6950,7 +6950,7 @@ pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -6971,7 +6971,7 @@ pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -6992,7 +6992,7 @@ pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -7013,7 +7013,7 @@ pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -7034,7 +7034,7 @@ pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -7055,7 +7055,7 @@ pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -7076,7 +7076,7 @@ pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -7097,7 +7097,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
 #[cfg_attr(
@@ -7120,7 +7120,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
 #[cfg_attr(
@@ -7143,7 +7143,7 @@ pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7164,7 +7164,7 @@ pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7185,7 +7185,7 @@ pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7206,7 +7206,7 @@ pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7227,7 +7227,7 @@ pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7248,7 +7248,7 @@ pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7269,7 +7269,7 @@ pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7291,7 +7291,7 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7317,7 +7317,7 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7339,7 +7339,7 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7365,7 +7365,7 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7387,7 +7387,7 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7413,7 +7413,7 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7435,7 +7435,7 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7461,7 +7461,7 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7483,7 +7483,7 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7509,7 +7509,7 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7531,7 +7531,7 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7562,7 +7562,7 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7583,7 +7583,7 @@ pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7604,7 +7604,7 @@ pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7626,7 +7626,7 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7652,7 +7652,7 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7674,7 +7674,7 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7705,7 +7705,7 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7727,7 +7727,7 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7753,7 +7753,7 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7775,7 +7775,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7806,7 +7806,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -7825,7 +7825,7 @@ pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7842,7 +7842,7 @@ pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7859,7 +7859,7 @@ pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7876,7 +7876,7 @@ pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7893,7 +7893,7 @@ pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7910,7 +7910,7 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7927,7 +7927,7 @@ pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7944,7 +7944,7 @@ pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7961,7 +7961,7 @@ pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7978,7 +7978,7 @@ pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7995,7 +7995,7 @@ pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8012,7 +8012,7 @@ pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8029,7 +8029,7 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8053,7 +8053,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8080,7 +8080,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8102,7 +8102,7 @@ pub fn vcreate_f32(a: u64) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8127,7 +8127,7 @@ pub fn vcreate_f32(a: u64) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8149,7 +8149,7 @@ pub fn vcreate_s8(a: u64) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8174,7 +8174,7 @@ pub fn vcreate_s8(a: u64) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8196,7 +8196,7 @@ pub fn vcreate_s16(a: u64) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8221,7 +8221,7 @@ pub fn vcreate_s16(a: u64) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8243,7 +8243,7 @@ pub fn vcreate_s32(a: u64) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8268,7 +8268,7 @@ pub fn vcreate_s32(a: u64) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8289,7 +8289,7 @@ pub fn vcreate_s64(a: u64) -> int64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8311,7 +8311,7 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8336,7 +8336,7 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8358,7 +8358,7 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8383,7 +8383,7 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8405,7 +8405,7 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8430,7 +8430,7 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8451,7 +8451,7 @@ pub fn vcreate_u64(a: u64) -> uint64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8473,7 +8473,7 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8498,7 +8498,7 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8520,7 +8520,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8545,7 +8545,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8566,7 +8566,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
 }
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8589,7 +8589,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8611,7 +8611,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8633,7 +8633,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8655,7 +8655,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8677,7 +8677,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8700,7 +8700,7 @@ pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8721,7 +8721,7 @@ pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8742,7 +8742,7 @@ pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8763,7 +8763,7 @@ pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8784,7 +8784,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8819,7 +8819,7 @@ pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8854,7 +8854,7 @@ pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8889,7 +8889,7 @@ pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8924,7 +8924,7 @@ pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -8943,7 +8943,7 @@ pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -8962,7 +8962,7 @@ pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
@@ -8981,7 +8981,7 @@ pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
@@ -9000,7 +9000,7 @@ pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9019,7 +9019,7 @@ pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9038,7 +9038,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
@@ -9057,7 +9057,7 @@ pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
@@ -9076,7 +9076,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9111,7 +9111,7 @@ pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9146,7 +9146,7 @@ pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9165,7 +9165,7 @@ pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9184,7 +9184,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
@@ -9203,7 +9203,7 @@ pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
@@ -9222,7 +9222,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9257,7 +9257,7 @@ pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9292,7 +9292,7 @@ pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9311,7 +9311,7 @@ pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9330,7 +9330,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
@@ -9349,7 +9349,7 @@ pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
@@ -9368,7 +9368,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9390,7 +9390,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9412,7 +9412,7 @@ pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9441,7 +9441,7 @@ pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9470,7 +9470,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9492,7 +9492,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9514,7 +9514,7 @@ pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9543,7 +9543,7 @@ pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9572,7 +9572,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9600,7 +9600,7 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9632,7 +9632,7 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9661,7 +9661,7 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9695,7 +9695,7 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9723,7 +9723,7 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9755,7 +9755,7 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9784,7 +9784,7 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9818,7 +9818,7 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9839,7 +9839,7 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9865,7 +9865,7 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9887,7 +9887,7 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9915,7 +9915,7 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9936,7 +9936,7 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9962,7 +9962,7 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9984,7 +9984,7 @@ pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x1
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -10012,7 +10012,7 @@ pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x1
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
@@ -10041,7 +10041,7 @@ pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
@@ -10070,7 +10070,7 @@ pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
@@ -10099,7 +10099,7 @@ pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
@@ -10128,7 +10128,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10153,7 +10153,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10178,7 +10178,7 @@ pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10201,7 +10201,7 @@ pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10224,7 +10224,7 @@ pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10247,7 +10247,7 @@ pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10270,7 +10270,7 @@ pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10293,7 +10293,7 @@ pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10316,7 +10316,7 @@ pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10339,7 +10339,7 @@ pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10362,7 +10362,7 @@ pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10385,7 +10385,7 @@ pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10408,7 +10408,7 @@ pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10431,7 +10431,7 @@ pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10454,7 +10454,7 @@ pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10477,7 +10477,7 @@ pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10500,7 +10500,7 @@ pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10523,7 +10523,7 @@ pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10546,7 +10546,7 @@ pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10569,7 +10569,7 @@ pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10592,7 +10592,7 @@ pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -10615,7 +10615,7 @@ pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -10638,7 +10638,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10663,7 +10663,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10688,7 +10688,7 @@ pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10711,7 +10711,7 @@ pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10734,7 +10734,7 @@ pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10757,7 +10757,7 @@ pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10780,7 +10780,7 @@ pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10803,7 +10803,7 @@ pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10826,7 +10826,7 @@ pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10849,7 +10849,7 @@ pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10872,7 +10872,7 @@ pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10895,7 +10895,7 @@ pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10918,7 +10918,7 @@ pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10941,7 +10941,7 @@ pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10964,7 +10964,7 @@ pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10987,7 +10987,7 @@ pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11010,7 +11010,7 @@ pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11033,7 +11033,7 @@ pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11056,7 +11056,7 @@ pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11079,7 +11079,7 @@ pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11102,7 +11102,7 @@ pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11125,7 +11125,7 @@ pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11148,7 +11148,7 @@ pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11164,7 +11164,7 @@ pub fn vdup_n_f16(a: f16) -> float16x4_t {
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11180,7 +11180,7 @@ pub fn vdupq_n_f16(a: f16) -> float16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11201,7 +11201,7 @@ pub fn vdup_n_f32(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11222,7 +11222,7 @@ pub fn vdup_n_p16(value: p16) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11243,7 +11243,7 @@ pub fn vdup_n_p8(value: p8) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11264,7 +11264,7 @@ pub fn vdup_n_s16(value: i16) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11285,7 +11285,7 @@ pub fn vdup_n_s32(value: i32) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11306,7 +11306,7 @@ pub fn vdup_n_s64(value: i64) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11327,7 +11327,7 @@ pub fn vdup_n_s8(value: i8) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11348,7 +11348,7 @@ pub fn vdup_n_u16(value: u16) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11369,7 +11369,7 @@ pub fn vdup_n_u32(value: u32) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11390,7 +11390,7 @@ pub fn vdup_n_u64(value: u64) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11411,7 +11411,7 @@ pub fn vdup_n_u8(value: u8) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11432,7 +11432,7 @@ pub fn vdupq_n_f32(value: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11453,7 +11453,7 @@ pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11474,7 +11474,7 @@ pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11495,7 +11495,7 @@ pub fn vdupq_n_s16(value: i16) -> int16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11516,7 +11516,7 @@ pub fn vdupq_n_s32(value: i32) -> int32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11537,7 +11537,7 @@ pub fn vdupq_n_s64(value: i64) -> int64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11558,7 +11558,7 @@ pub fn vdupq_n_s8(value: i8) -> int8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11579,7 +11579,7 @@ pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11600,7 +11600,7 @@ pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11621,7 +11621,7 @@ pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11642,7 +11642,7 @@ pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11663,7 +11663,7 @@ fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11684,7 +11684,7 @@ fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
@@ -11707,7 +11707,7 @@ pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
@@ -11730,7 +11730,7 @@ pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11753,7 +11753,7 @@ pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11776,7 +11776,7 @@ pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11797,7 +11797,7 @@ pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11818,7 +11818,7 @@ pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11839,7 +11839,7 @@ pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11860,7 +11860,7 @@ pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11881,7 +11881,7 @@ pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11902,7 +11902,7 @@ pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11923,7 +11923,7 @@ pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11944,7 +11944,7 @@ pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11965,7 +11965,7 @@ pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11986,7 +11986,7 @@ pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12007,7 +12007,7 @@ pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12028,7 +12028,7 @@ pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12049,7 +12049,7 @@ pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12070,7 +12070,7 @@ pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12091,7 +12091,7 @@ pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12112,7 +12112,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
 #[cfg_attr(
@@ -12144,7 +12144,7 @@ pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12173,7 +12173,7 @@ pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12202,7 +12202,7 @@ pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12233,7 +12233,7 @@ pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -12258,7 +12258,7 @@ pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -12281,7 +12281,7 @@ pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12316,7 +12316,7 @@ pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12351,7 +12351,7 @@ pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12386,7 +12386,7 @@ pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12421,7 +12421,7 @@ pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12456,7 +12456,7 @@ pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12491,7 +12491,7 @@ pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
 #[cfg_attr(
@@ -12527,7 +12527,7 @@ pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12558,7 +12558,7 @@ pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12589,7 +12589,7 @@ pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12620,7 +12620,7 @@ pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12651,7 +12651,7 @@ pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12682,7 +12682,7 @@ pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12713,7 +12713,7 @@ pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -12742,7 +12742,7 @@ pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -12771,7 +12771,7 @@ pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -12874,7 +12874,7 @@ pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -12977,7 +12977,7 @@ pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -13080,7 +13080,7 @@ pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
 #[cfg_attr(
@@ -13102,7 +13102,7 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
 #[cfg_attr(
@@ -13124,7 +13124,7 @@ pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13145,7 +13145,7 @@ pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13166,7 +13166,7 @@ pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13187,7 +13187,7 @@ pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13208,7 +13208,7 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -13234,7 +13234,7 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -13260,7 +13260,7 @@ pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13284,7 +13284,7 @@ pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13308,7 +13308,7 @@ pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13329,7 +13329,7 @@ pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13350,7 +13350,7 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -13369,7 +13369,7 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -13388,7 +13388,7 @@ pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13409,7 +13409,7 @@ pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13430,7 +13430,7 @@ pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13451,7 +13451,7 @@ pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13472,7 +13472,7 @@ pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13493,7 +13493,7 @@ pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13514,7 +13514,7 @@ pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13535,7 +13535,7 @@ pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13556,7 +13556,7 @@ pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13577,7 +13577,7 @@ pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13598,7 +13598,7 @@ pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13619,7 +13619,7 @@ pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -13637,7 +13637,7 @@ pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
 }
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -13655,7 +13655,7 @@ pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13674,7 +13674,7 @@ pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13693,7 +13693,7 @@ pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13712,7 +13712,7 @@ pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13731,7 +13731,7 @@ pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13750,7 +13750,7 @@ pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13769,7 +13769,7 @@ pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13788,7 +13788,7 @@ pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13807,7 +13807,7 @@ pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13826,7 +13826,7 @@ pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13845,7 +13845,7 @@ pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13864,7 +13864,7 @@ pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13883,7 +13883,7 @@ pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13902,7 +13902,7 @@ pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13921,7 +13921,7 @@ pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13940,7 +13940,7 @@ pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13959,7 +13959,7 @@ pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13978,7 +13978,7 @@ pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13997,7 +13997,7 @@ pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14016,7 +14016,7 @@ pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14035,7 +14035,7 @@ pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14054,7 +14054,7 @@ pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14073,7 +14073,7 @@ pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14092,7 +14092,7 @@ pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14111,7 +14111,7 @@ pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14128,7 +14128,7 @@ pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14145,7 +14145,7 @@ pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14162,7 +14162,7 @@ pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14179,7 +14179,7 @@ pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14196,7 +14196,7 @@ pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14213,7 +14213,7 @@ pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14230,7 +14230,7 @@ pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14247,7 +14247,7 @@ pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14264,7 +14264,7 @@ pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14281,7 +14281,7 @@ pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14298,7 +14298,7 @@ pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
@@ -14327,7 +14327,7 @@ pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
@@ -14356,7 +14356,7 @@ pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
@@ -14385,7 +14385,7 @@ pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
@@ -14414,7 +14414,7 @@ pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
@@ -14443,7 +14443,7 @@ pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
@@ -14472,7 +14472,7 @@ pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
@@ -14501,7 +14501,7 @@ pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
@@ -14530,7 +14530,7 @@ pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
@@ -14559,7 +14559,7 @@ pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
@@ -14588,7 +14588,7 @@ pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
@@ -14617,7 +14617,7 @@ pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
@@ -14646,7 +14646,7 @@ pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
@@ -14675,7 +14675,7 @@ pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
@@ -14704,7 +14704,7 @@ pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
@@ -14733,7 +14733,7 @@ pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
@@ -14762,7 +14762,7 @@ pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
@@ -14791,7 +14791,7 @@ pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
@@ -14820,7 +14820,7 @@ pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
@@ -14849,7 +14849,7 @@ pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
@@ -14878,7 +14878,7 @@ pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
@@ -14907,7 +14907,7 @@ pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
@@ -14936,7 +14936,7 @@ pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
@@ -14965,7 +14965,7 @@ pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
@@ -14996,7 +14996,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15015,7 +15015,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15034,7 +15034,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15057,7 +15057,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15080,7 +15080,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15103,7 +15103,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15126,7 +15126,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15149,7 +15149,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15172,7 +15172,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15195,7 +15195,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15218,7 +15218,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15241,7 +15241,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15264,7 +15264,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15287,7 +15287,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15310,7 +15310,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15333,7 +15333,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15356,7 +15356,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
@@ -15379,7 +15379,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15402,7 +15402,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15425,7 +15425,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15448,7 +15448,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
@@ -15471,7 +15471,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15494,7 +15494,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15526,7 +15526,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15558,7 +15558,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15590,7 +15590,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15608,7 +15608,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15627,7 +15627,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15645,7 +15645,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15664,7 +15664,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15682,7 +15682,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15700,7 +15700,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15718,7 +15718,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15736,7 +15736,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15754,7 +15754,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15772,7 +15772,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15785,7 +15785,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15798,7 +15798,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15811,7 +15811,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15824,7 +15824,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15837,7 +15837,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15850,7 +15850,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15863,7 +15863,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15876,7 +15876,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15889,7 +15889,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15902,7 +15902,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15915,7 +15915,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15928,7 +15928,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15941,7 +15941,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15954,7 +15954,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15967,7 +15967,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -15990,7 +15990,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -16013,7 +16013,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -16036,7 +16036,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -16059,7 +16059,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -16082,7 +16082,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -16105,7 +16105,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
@@ -16125,7 +16125,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
@@ -16145,7 +16145,7 @@ pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16170,7 +16170,7 @@ pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16195,7 +16195,7 @@ pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16220,7 +16220,7 @@ pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16245,7 +16245,7 @@ pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16270,7 +16270,7 @@ pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16295,7 +16295,7 @@ pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16320,7 +16320,7 @@ pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16345,7 +16345,7 @@ pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16370,7 +16370,7 @@ pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16395,7 +16395,7 @@ pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16420,7 +16420,7 @@ pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16445,7 +16445,7 @@ pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16470,7 +16470,7 @@ pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16495,7 +16495,7 @@ pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16520,7 +16520,7 @@ pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16545,7 +16545,7 @@ pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16570,7 +16570,7 @@ pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16595,7 +16595,7 @@ pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16620,7 +16620,7 @@ pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16645,7 +16645,7 @@ pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16670,7 +16670,7 @@ pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16695,7 +16695,7 @@ pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16720,7 +16720,7 @@ pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16745,7 +16745,7 @@ pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16763,7 +16763,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -16786,7 +16786,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16809,7 +16809,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16832,7 +16832,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16855,7 +16855,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16878,7 +16878,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16901,7 +16901,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16914,7 +16914,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16927,7 +16927,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16940,7 +16940,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16953,7 +16953,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16966,7 +16966,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16979,7 +16979,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16992,7 +16992,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17005,7 +17005,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17028,7 +17028,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17051,7 +17051,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17074,7 +17074,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17097,7 +17097,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17120,7 +17120,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17143,7 +17143,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17166,7 +17166,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17189,7 +17189,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17212,7 +17212,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17235,7 +17235,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17258,7 +17258,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17281,7 +17281,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17304,7 +17304,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17327,7 +17327,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17350,7 +17350,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17373,7 +17373,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17396,7 +17396,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17419,7 +17419,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17442,7 +17442,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17465,7 +17465,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17488,7 +17488,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17511,7 +17511,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17534,7 +17534,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17557,7 +17557,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17580,7 +17580,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17603,7 +17603,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17626,7 +17626,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17649,7 +17649,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17672,7 +17672,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17695,7 +17695,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17718,7 +17718,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17741,7 +17741,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17764,7 +17764,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17787,7 +17787,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17810,7 +17810,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17833,7 +17833,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17856,7 +17856,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17879,7 +17879,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17902,7 +17902,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17925,7 +17925,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17948,7 +17948,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17971,7 +17971,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -17994,7 +17994,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18017,7 +18017,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18040,7 +18040,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18063,7 +18063,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18086,7 +18086,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18109,7 +18109,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18132,7 +18132,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18155,7 +18155,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18178,7 +18178,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18201,7 +18201,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18224,7 +18224,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18247,7 +18247,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18270,7 +18270,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18293,7 +18293,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18316,7 +18316,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18339,7 +18339,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18362,7 +18362,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))]
@@ -18381,7 +18381,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
     crate::ptr::read_unaligned(a.cast())
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18394,7 +18394,7 @@ unsafe fn vld1_v1i64<const ALIGN: i32>(a: *const i8) -> int64x1_t {
     }
     _vld1_v1i64(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18407,7 +18407,7 @@ unsafe fn vld1_v2f32<const ALIGN: i32>(a: *const i8) -> float32x2_t {
     }
     _vld1_v2f32(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18420,7 +18420,7 @@ unsafe fn vld1_v2i32<const ALIGN: i32>(a: *const i8) -> int32x2_t {
     }
     _vld1_v2i32(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18433,7 +18433,7 @@ unsafe fn vld1_v4i16<const ALIGN: i32>(a: *const i8) -> int16x4_t {
     }
     _vld1_v4i16(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18446,7 +18446,7 @@ unsafe fn vld1_v8i8<const ALIGN: i32>(a: *const i8) -> int8x8_t {
     }
     _vld1_v8i8(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18459,7 +18459,7 @@ unsafe fn vld1q_v16i8<const ALIGN: i32>(a: *const i8) -> int8x16_t {
     }
     _vld1q_v16i8(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18472,7 +18472,7 @@ unsafe fn vld1q_v2i64<const ALIGN: i32>(a: *const i8) -> int64x2_t {
     }
     _vld1q_v2i64(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18485,7 +18485,7 @@ unsafe fn vld1q_v4f32<const ALIGN: i32>(a: *const i8) -> float32x4_t {
     }
     _vld1q_v4f32(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18498,7 +18498,7 @@ unsafe fn vld1q_v4i32<const ALIGN: i32>(a: *const i8) -> int32x4_t {
     }
     _vld1q_v4i32(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -18511,7 +18511,7 @@ unsafe fn vld1q_v8i16<const ALIGN: i32>(a: *const i8) -> int16x8_t {
     }
     _vld1q_v8i16(a, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -18525,7 +18525,7 @@ unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
     }
     _vld1_v4f16(a, b)
 }
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -18543,7 +18543,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -18567,7 +18567,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -18586,7 +18586,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -18605,7 +18605,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -18629,7 +18629,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -18653,7 +18653,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18669,7 +18669,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18685,7 +18685,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18701,7 +18701,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18717,7 +18717,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18733,7 +18733,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18749,7 +18749,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18765,7 +18765,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18781,7 +18781,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18800,7 +18800,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18819,7 +18819,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18838,7 +18838,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18857,7 +18857,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18876,7 +18876,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18895,7 +18895,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18914,7 +18914,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18933,7 +18933,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -18956,7 +18956,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -18972,7 +18972,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18991,7 +18991,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -19014,7 +19014,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19038,7 +19038,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19065,7 +19065,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19089,7 +19089,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19124,7 +19124,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19148,7 +19148,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19175,7 +19175,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19199,7 +19199,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19226,7 +19226,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19250,7 +19250,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19277,7 +19277,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19301,7 +19301,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19328,7 +19328,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19352,7 +19352,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19379,7 +19379,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19403,7 +19403,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19438,7 +19438,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19462,7 +19462,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19489,7 +19489,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19513,7 +19513,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19540,7 +19540,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -19559,7 +19559,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -19578,7 +19578,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -19602,7 +19602,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -19626,7 +19626,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19642,7 +19642,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19658,7 +19658,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19674,7 +19674,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19690,7 +19690,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19706,7 +19706,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19722,7 +19722,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19738,7 +19738,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -19754,7 +19754,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19773,7 +19773,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19792,7 +19792,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19811,7 +19811,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19830,7 +19830,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19849,7 +19849,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19868,7 +19868,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19887,7 +19887,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19906,7 +19906,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -19932,7 +19932,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -19958,7 +19958,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -19985,7 +19985,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20016,7 +20016,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20037,7 +20037,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20059,7 +20059,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20080,7 +20080,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20101,7 +20101,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20122,7 +20122,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20143,7 +20143,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -20164,7 +20164,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20188,7 +20188,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20212,7 +20212,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20236,7 +20236,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20260,7 +20260,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20279,7 +20279,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20303,7 +20303,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -20327,7 +20327,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20352,7 +20352,7 @@ pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20377,7 +20377,7 @@ pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20402,7 +20402,7 @@ pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20427,7 +20427,7 @@ pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20452,7 +20452,7 @@ pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20477,7 +20477,7 @@ pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20502,7 +20502,7 @@ pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -20527,7 +20527,7 @@ pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -20550,7 +20550,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20566,7 +20566,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20585,7 +20585,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -20608,7 +20608,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20631,7 +20631,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20654,7 +20654,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20677,7 +20677,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20700,7 +20700,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20723,7 +20723,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20746,7 +20746,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20769,7 +20769,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20792,7 +20792,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20815,7 +20815,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -20838,7 +20838,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -20857,7 +20857,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -20876,7 +20876,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20900,7 +20900,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20924,7 +20924,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20943,7 +20943,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20962,7 +20962,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20981,7 +20981,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21000,7 +21000,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21019,7 +21019,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21038,7 +21038,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21057,7 +21057,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21076,7 +21076,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21095,7 +21095,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21111,7 +21111,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21127,7 +21127,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21143,7 +21143,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21159,7 +21159,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21175,7 +21175,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21191,7 +21191,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21207,7 +21207,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21223,7 +21223,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -21246,7 +21246,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21262,7 +21262,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -21285,7 +21285,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21309,7 +21309,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21337,7 +21337,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21361,7 +21361,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21401,7 +21401,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21425,7 +21425,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21453,7 +21453,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21477,7 +21477,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21505,7 +21505,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21529,7 +21529,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21557,7 +21557,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21581,7 +21581,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21609,7 +21609,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21633,7 +21633,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21661,7 +21661,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21685,7 +21685,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21725,7 +21725,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21749,7 +21749,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21777,7 +21777,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21801,7 +21801,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21829,7 +21829,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -21848,7 +21848,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -21867,7 +21867,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21884,7 +21884,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21901,7 +21901,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21913,7 +21913,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21925,7 +21925,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21937,7 +21937,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21949,7 +21949,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21961,7 +21961,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21973,7 +21973,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21985,7 +21985,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -21997,7 +21997,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22013,7 +22013,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22029,7 +22029,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22045,7 +22045,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22061,7 +22061,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22077,7 +22077,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22093,7 +22093,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22109,7 +22109,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22125,7 +22125,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22152,7 +22152,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22179,7 +22179,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -22211,7 +22211,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -22243,7 +22243,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22270,7 +22270,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22297,7 +22297,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -22322,7 +22322,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22349,7 +22349,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22376,7 +22376,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22403,7 +22403,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22430,7 +22430,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -22457,7 +22457,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -22482,7 +22482,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -22507,7 +22507,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -22532,7 +22532,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -22557,7 +22557,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -22582,7 +22582,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22607,7 +22607,7 @@ pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22632,7 +22632,7 @@ pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22657,7 +22657,7 @@ pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22682,7 +22682,7 @@ pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22707,7 +22707,7 @@ pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22732,7 +22732,7 @@ pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22757,7 +22757,7 @@ pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -22782,7 +22782,7 @@ pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22805,7 +22805,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -22817,7 +22817,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22833,7 +22833,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22856,7 +22856,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -22879,7 +22879,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -22902,7 +22902,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -22925,7 +22925,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -22948,7 +22948,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -22971,7 +22971,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -22994,7 +22994,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23017,7 +23017,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23040,7 +23040,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23063,7 +23063,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -23086,7 +23086,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -23111,7 +23111,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23129,7 +23129,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23147,7 +23147,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -23170,7 +23170,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -23193,7 +23193,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23209,7 +23209,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23225,7 +23225,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23241,7 +23241,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23257,7 +23257,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23273,7 +23273,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23289,7 +23289,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23305,7 +23305,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -23321,7 +23321,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23340,7 +23340,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23359,7 +23359,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23378,7 +23378,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23397,7 +23397,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23416,7 +23416,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23435,7 +23435,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23454,7 +23454,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23473,7 +23473,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -23492,7 +23492,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -23515,7 +23515,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -23531,7 +23531,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -23554,7 +23554,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23578,7 +23578,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23607,7 +23607,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23631,7 +23631,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23676,7 +23676,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23700,7 +23700,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23729,7 +23729,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23753,7 +23753,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23782,7 +23782,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23806,7 +23806,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23835,7 +23835,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23859,7 +23859,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23888,7 +23888,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23912,7 +23912,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23941,7 +23941,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23965,7 +23965,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24010,7 +24010,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24034,7 +24034,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24063,7 +24063,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24087,7 +24087,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24116,7 +24116,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -24134,7 +24134,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -24152,7 +24152,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -24168,7 +24168,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -24184,7 +24184,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24196,7 +24196,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24208,7 +24208,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24220,7 +24220,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24232,7 +24232,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24244,7 +24244,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24256,7 +24256,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24268,7 +24268,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24280,7 +24280,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24296,7 +24296,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24312,7 +24312,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24328,7 +24328,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24344,7 +24344,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24360,7 +24360,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24376,7 +24376,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24392,7 +24392,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24408,7 +24408,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -24436,7 +24436,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -24464,7 +24464,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -24496,7 +24496,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -24528,7 +24528,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24556,7 +24556,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24584,7 +24584,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24612,7 +24612,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24640,7 +24640,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24668,7 +24668,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24696,7 +24696,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -24724,7 +24724,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24750,7 +24750,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24776,7 +24776,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24802,7 +24802,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24828,7 +24828,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24854,7 +24854,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24880,7 +24880,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -24906,7 +24906,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -24931,7 +24931,7 @@ pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -24956,7 +24956,7 @@ pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -24981,7 +24981,7 @@ pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -25006,7 +25006,7 @@ pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -25031,7 +25031,7 @@ pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -25056,7 +25056,7 @@ pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -25081,7 +25081,7 @@ pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -25106,7 +25106,7 @@ pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25129,7 +25129,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25141,7 +25141,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -25157,7 +25157,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25180,7 +25180,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25203,7 +25203,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25226,7 +25226,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25249,7 +25249,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25272,7 +25272,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25295,7 +25295,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25318,7 +25318,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25341,7 +25341,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25364,7 +25364,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25387,7 +25387,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25410,7 +25410,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25431,7 +25431,7 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
 #[cfg_attr(
@@ -25461,7 +25461,7 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
 #[cfg_attr(
@@ -25491,7 +25491,7 @@ pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25520,7 +25520,7 @@ pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25549,7 +25549,7 @@ pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25573,7 +25573,7 @@ pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25597,7 +25597,7 @@ pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25621,7 +25621,7 @@ pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25645,7 +25645,7 @@ pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25669,7 +25669,7 @@ pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25693,7 +25693,7 @@ pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25717,7 +25717,7 @@ pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25741,7 +25741,7 @@ pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25765,7 +25765,7 @@ pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25789,7 +25789,7 @@ pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25813,7 +25813,7 @@ pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -25837,7 +25837,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
 #[cfg_attr(
@@ -25867,7 +25867,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
 #[cfg_attr(
@@ -25897,7 +25897,7 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
@@ -25926,7 +25926,7 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
@@ -25955,7 +25955,7 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
 #[cfg_attr(
@@ -25985,7 +25985,7 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
 #[cfg_attr(
@@ -26015,7 +26015,7 @@ pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26044,7 +26044,7 @@ pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26073,7 +26073,7 @@ pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26097,7 +26097,7 @@ pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26121,7 +26121,7 @@ pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26145,7 +26145,7 @@ pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26169,7 +26169,7 @@ pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26193,7 +26193,7 @@ pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26217,7 +26217,7 @@ pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26241,7 +26241,7 @@ pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26265,7 +26265,7 @@ pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26289,7 +26289,7 @@ pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26313,7 +26313,7 @@ pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26337,7 +26337,7 @@ pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -26361,7 +26361,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
 #[cfg_attr(
@@ -26391,7 +26391,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
 #[cfg_attr(
@@ -26421,7 +26421,7 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
@@ -26450,7 +26450,7 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
@@ -26479,7 +26479,7 @@ pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -26500,7 +26500,7 @@ pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -26521,7 +26521,7 @@ pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -26548,7 +26548,7 @@ pub fn vmla_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -26575,7 +26575,7 @@ pub fn vmla_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -26608,7 +26608,7 @@ pub fn vmlaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -26641,7 +26641,7 @@ pub fn vmlaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26670,7 +26670,7 @@ pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26699,7 +26699,7 @@ pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26728,7 +26728,7 @@ pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26757,7 +26757,7 @@ pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26799,7 +26799,7 @@ pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26841,7 +26841,7 @@ pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26883,7 +26883,7 @@ pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -26925,7 +26925,7 @@ pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -26948,7 +26948,7 @@ pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -26971,7 +26971,7 @@ pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -26994,7 +26994,7 @@ pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -27017,7 +27017,7 @@ pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -27046,7 +27046,7 @@ pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -27075,7 +27075,7 @@ pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -27104,7 +27104,7 @@ pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -27133,7 +27133,7 @@ pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -27154,7 +27154,7 @@ pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -27175,7 +27175,7 @@ pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27196,7 +27196,7 @@ pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27217,7 +27217,7 @@ pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27238,7 +27238,7 @@ pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27259,7 +27259,7 @@ pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27280,7 +27280,7 @@ pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27301,7 +27301,7 @@ pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27322,7 +27322,7 @@ pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27343,7 +27343,7 @@ pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -27364,7 +27364,7 @@ pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -27385,7 +27385,7 @@ pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27406,7 +27406,7 @@ pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27427,7 +27427,7 @@ pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27448,7 +27448,7 @@ pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27469,7 +27469,7 @@ pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -27490,7 +27490,7 @@ pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -27511,7 +27511,7 @@ pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27532,7 +27532,7 @@ pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -27553,7 +27553,7 @@ pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27574,7 +27574,7 @@ pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -27595,7 +27595,7 @@ pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
@@ -27624,7 +27624,7 @@ pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
@@ -27653,7 +27653,7 @@ pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
@@ -27676,7 +27676,7 @@ pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
@@ -27699,7 +27699,7 @@ pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
@@ -27728,7 +27728,7 @@ pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
@@ -27757,7 +27757,7 @@ pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
@@ -27780,7 +27780,7 @@ pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
@@ -27803,7 +27803,7 @@ pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
@@ -27824,7 +27824,7 @@ pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
@@ -27845,7 +27845,7 @@ pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
@@ -27866,7 +27866,7 @@ pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
@@ -27887,7 +27887,7 @@ pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
@@ -27908,7 +27908,7 @@ pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
@@ -27929,7 +27929,7 @@ pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
@@ -27950,7 +27950,7 @@ pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
@@ -27971,7 +27971,7 @@ pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
@@ -27992,7 +27992,7 @@ pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
@@ -28013,7 +28013,7 @@ pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -28034,7 +28034,7 @@ pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -28055,7 +28055,7 @@ pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -28082,7 +28082,7 @@ pub fn vmls_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -28109,7 +28109,7 @@ pub fn vmls_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -28142,7 +28142,7 @@ pub fn vmlsq_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -28175,7 +28175,7 @@ pub fn vmlsq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28204,7 +28204,7 @@ pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28233,7 +28233,7 @@ pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28262,7 +28262,7 @@ pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28291,7 +28291,7 @@ pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28333,7 +28333,7 @@ pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28375,7 +28375,7 @@ pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28417,7 +28417,7 @@ pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -28459,7 +28459,7 @@ pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28482,7 +28482,7 @@ pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28505,7 +28505,7 @@ pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28528,7 +28528,7 @@ pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28551,7 +28551,7 @@ pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28580,7 +28580,7 @@ pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28609,7 +28609,7 @@ pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28638,7 +28638,7 @@ pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -28667,7 +28667,7 @@ pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -28688,7 +28688,7 @@ pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -28709,7 +28709,7 @@ pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -28730,7 +28730,7 @@ pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -28751,7 +28751,7 @@ pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -28772,7 +28772,7 @@ pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -28793,7 +28793,7 @@ pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -28814,7 +28814,7 @@ pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -28835,7 +28835,7 @@ pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -28856,7 +28856,7 @@ pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -28877,7 +28877,7 @@ pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -28898,7 +28898,7 @@ pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -28919,7 +28919,7 @@ pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -28940,7 +28940,7 @@ pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -28961,7 +28961,7 @@ pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -28982,7 +28982,7 @@ pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -29003,7 +29003,7 @@ pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -29024,7 +29024,7 @@ pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -29045,7 +29045,7 @@ pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -29066,7 +29066,7 @@ pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -29087,7 +29087,7 @@ pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -29108,7 +29108,7 @@ pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -29129,7 +29129,7 @@ pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
@@ -29158,7 +29158,7 @@ pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
@@ -29187,7 +29187,7 @@ pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
@@ -29210,7 +29210,7 @@ pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
@@ -29233,7 +29233,7 @@ pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
@@ -29262,7 +29262,7 @@ pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
@@ -29291,7 +29291,7 @@ pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
@@ -29314,7 +29314,7 @@ pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
@@ -29337,7 +29337,7 @@ pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
@@ -29358,7 +29358,7 @@ pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
@@ -29379,7 +29379,7 @@ pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
@@ -29400,7 +29400,7 @@ pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
@@ -29421,7 +29421,7 @@ pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
@@ -29442,7 +29442,7 @@ pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
@@ -29463,7 +29463,7 @@ pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
@@ -29484,7 +29484,7 @@ pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
@@ -29505,7 +29505,7 @@ pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
@@ -29526,7 +29526,7 @@ pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
@@ -29547,7 +29547,7 @@ pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -29576,7 +29576,7 @@ pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -29605,7 +29605,7 @@ pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29621,7 +29621,7 @@ pub fn vmov_n_f16(a: f16) -> float16x4_t {
 }
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29637,7 +29637,7 @@ pub fn vmovq_n_f16(a: f16) -> float16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -29658,7 +29658,7 @@ pub fn vmov_n_f32(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29679,7 +29679,7 @@ pub fn vmov_n_p16(value: p16) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -29700,7 +29700,7 @@ pub fn vmov_n_p8(value: p8) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29721,7 +29721,7 @@ pub fn vmov_n_s16(value: i16) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -29742,7 +29742,7 @@ pub fn vmov_n_s32(value: i32) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -29763,7 +29763,7 @@ pub fn vmov_n_s64(value: i64) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -29784,7 +29784,7 @@ pub fn vmov_n_s8(value: i8) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29805,7 +29805,7 @@ pub fn vmov_n_u16(value: u16) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -29826,7 +29826,7 @@ pub fn vmov_n_u32(value: u32) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -29847,7 +29847,7 @@ pub fn vmov_n_u64(value: u64) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -29868,7 +29868,7 @@ pub fn vmov_n_u8(value: u8) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -29889,7 +29889,7 @@ pub fn vmovq_n_f32(value: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29910,7 +29910,7 @@ pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -29931,7 +29931,7 @@ pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -29952,7 +29952,7 @@ pub fn vmovq_n_s16(value: i16) -> int16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -29973,7 +29973,7 @@ pub fn vmovq_n_s32(value: i32) -> int32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -29994,7 +29994,7 @@ pub fn vmovq_n_s64(value: i64) -> int64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -30015,7 +30015,7 @@ pub fn vmovq_n_s8(value: i8) -> int8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -30036,7 +30036,7 @@ pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -30057,7 +30057,7 @@ pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -30078,7 +30078,7 @@ pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -30099,7 +30099,7 @@ pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -30120,7 +30120,7 @@ pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -30141,7 +30141,7 @@ pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -30162,7 +30162,7 @@ pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -30183,7 +30183,7 @@ pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -30204,7 +30204,7 @@ pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -30225,7 +30225,7 @@ pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -30246,7 +30246,7 @@ pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -30267,7 +30267,7 @@ pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -30288,7 +30288,7 @@ pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -30309,7 +30309,7 @@ pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -30330,7 +30330,7 @@ pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -30351,7 +30351,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
 #[cfg_attr(
@@ -30373,7 +30373,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
 #[cfg_attr(
@@ -30395,7 +30395,7 @@ pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
@@ -30416,7 +30416,7 @@ pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
@@ -30437,7 +30437,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
 #[cfg_attr(
@@ -30466,7 +30466,7 @@ pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
 #[cfg_attr(
@@ -30508,7 +30508,7 @@ pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float1
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -30531,7 +30531,7 @@ pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -30554,7 +30554,7 @@ pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float3
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -30582,7 +30582,7 @@ pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float3
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -30610,7 +30610,7 @@ pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30638,7 +30638,7 @@ pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30679,7 +30679,7 @@ pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30702,7 +30702,7 @@ pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30730,7 +30730,7 @@ pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30758,7 +30758,7 @@ pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30799,7 +30799,7 @@ pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30822,7 +30822,7 @@ pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30850,7 +30850,7 @@ pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30878,7 +30878,7 @@ pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30919,7 +30919,7 @@ pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30942,7 +30942,7 @@ pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30970,7 +30970,7 @@ pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -30998,7 +30998,7 @@ pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -31039,7 +31039,7 @@ pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -31062,7 +31062,7 @@ pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -31090,7 +31090,7 @@ pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
 #[cfg_attr(
@@ -31105,7 +31105,7 @@ pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
 #[cfg_attr(
@@ -31120,7 +31120,7 @@ pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31141,7 +31141,7 @@ pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31162,7 +31162,7 @@ pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31183,7 +31183,7 @@ pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31204,7 +31204,7 @@ pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31225,7 +31225,7 @@ pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31246,7 +31246,7 @@ pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31267,7 +31267,7 @@ pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31288,7 +31288,7 @@ pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31309,7 +31309,7 @@ pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31330,7 +31330,7 @@ pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31359,7 +31359,7 @@ pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -31388,7 +31388,7 @@ pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -31409,7 +31409,7 @@ pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -31430,7 +31430,7 @@ pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -31451,7 +31451,7 @@ pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -31472,7 +31472,7 @@ pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -31493,7 +31493,7 @@ pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -31514,7 +31514,7 @@ pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -31535,7 +31535,7 @@ pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -31556,7 +31556,7 @@ pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -31577,7 +31577,7 @@ pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -31598,7 +31598,7 @@ pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -31619,7 +31619,7 @@ pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -31640,7 +31640,7 @@ pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31668,7 +31668,7 @@ pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31696,7 +31696,7 @@ pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31719,7 +31719,7 @@ pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31742,7 +31742,7 @@ pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31770,7 +31770,7 @@ pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31798,7 +31798,7 @@ pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31821,7 +31821,7 @@ pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -31844,7 +31844,7 @@ pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -31865,7 +31865,7 @@ pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -31886,7 +31886,7 @@ pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -31907,7 +31907,7 @@ pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -31928,7 +31928,7 @@ pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
@@ -31957,7 +31957,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
@@ -31978,7 +31978,7 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
@@ -31999,7 +31999,7 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
@@ -32020,7 +32020,7 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
@@ -32041,7 +32041,7 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
@@ -32062,7 +32062,7 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
@@ -32083,7 +32083,7 @@ pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32105,7 +32105,7 @@ pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32127,7 +32127,7 @@ pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32149,7 +32149,7 @@ pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32171,7 +32171,7 @@ pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32193,7 +32193,7 @@ pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32215,7 +32215,7 @@ pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32237,7 +32237,7 @@ pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32259,7 +32259,7 @@ pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32281,7 +32281,7 @@ pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32303,7 +32303,7 @@ pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32325,7 +32325,7 @@ pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32347,7 +32347,7 @@ pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32369,7 +32369,7 @@ pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -32391,7 +32391,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
 #[cfg_attr(
@@ -32413,7 +32413,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
 #[cfg_attr(
@@ -32435,7 +32435,7 @@ pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
@@ -32456,7 +32456,7 @@ pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
@@ -32477,7 +32477,7 @@ pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
@@ -32498,7 +32498,7 @@ pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
@@ -32519,7 +32519,7 @@ pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
@@ -32540,7 +32540,7 @@ pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
@@ -32561,7 +32561,7 @@ pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
@@ -32582,7 +32582,7 @@ pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
@@ -32603,7 +32603,7 @@ pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32625,7 +32625,7 @@ pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32647,7 +32647,7 @@ pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32669,7 +32669,7 @@ pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32691,7 +32691,7 @@ pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32713,7 +32713,7 @@ pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32735,7 +32735,7 @@ pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32757,7 +32757,7 @@ pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32779,7 +32779,7 @@ pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32801,7 +32801,7 @@ pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32823,7 +32823,7 @@ pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32845,7 +32845,7 @@ pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32867,7 +32867,7 @@ pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32889,7 +32889,7 @@ pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32911,7 +32911,7 @@ pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32933,7 +32933,7 @@ pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -32955,7 +32955,7 @@ pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -32976,7 +32976,7 @@ pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -32997,7 +32997,7 @@ pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33018,7 +33018,7 @@ pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33039,7 +33039,7 @@ pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33060,7 +33060,7 @@ pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33081,7 +33081,7 @@ pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33102,7 +33102,7 @@ pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33123,7 +33123,7 @@ pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33144,7 +33144,7 @@ pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33165,7 +33165,7 @@ pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33186,7 +33186,7 @@ pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33207,7 +33207,7 @@ pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33228,7 +33228,7 @@ pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33249,7 +33249,7 @@ pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33270,7 +33270,7 @@ pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -33291,7 +33291,7 @@ pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
@@ -33321,7 +33321,7 @@ pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
@@ -33351,7 +33351,7 @@ pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
@@ -33381,7 +33381,7 @@ pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
@@ -33411,7 +33411,7 @@ pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
@@ -33441,7 +33441,7 @@ pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
@@ -33471,7 +33471,7 @@ pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
@@ -33501,7 +33501,7 @@ pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
@@ -33531,7 +33531,7 @@ pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
@@ -33561,7 +33561,7 @@ pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
@@ -33591,7 +33591,7 @@ pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
@@ -33621,7 +33621,7 @@ pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
@@ -33651,7 +33651,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
 #[cfg_attr(
@@ -33681,7 +33681,7 @@ pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33710,7 +33710,7 @@ pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33739,7 +33739,7 @@ pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33768,7 +33768,7 @@ pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33797,7 +33797,7 @@ pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33818,7 +33818,7 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33839,7 +33839,7 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -33860,7 +33860,7 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
@@ -33889,7 +33889,7 @@ pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
@@ -33918,7 +33918,7 @@ pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
@@ -33947,7 +33947,7 @@ pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
@@ -33976,7 +33976,7 @@ pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
@@ -34005,7 +34005,7 @@ pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
@@ -34034,7 +34034,7 @@ pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
@@ -34063,7 +34063,7 @@ pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
@@ -34092,7 +34092,7 @@ pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
@@ -34121,7 +34121,7 @@ pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
@@ -34150,7 +34150,7 @@ pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
@@ -34179,7 +34179,7 @@ pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
@@ -34208,7 +34208,7 @@ pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34237,7 +34237,7 @@ pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34266,7 +34266,7 @@ pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34295,7 +34295,7 @@ pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34324,7 +34324,7 @@ pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34353,7 +34353,7 @@ pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34382,7 +34382,7 @@ pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -34411,7 +34411,7 @@ pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34440,7 +34440,7 @@ pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34469,7 +34469,7 @@ pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34498,7 +34498,7 @@ pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34527,7 +34527,7 @@ pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34556,7 +34556,7 @@ pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34585,7 +34585,7 @@ pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -34614,7 +34614,7 @@ pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
@@ -34643,7 +34643,7 @@ pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
@@ -34672,7 +34672,7 @@ pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
@@ -34701,7 +34701,7 @@ pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
@@ -34730,7 +34730,7 @@ pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
@@ -34759,7 +34759,7 @@ pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
@@ -34788,7 +34788,7 @@ pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
@@ -34809,7 +34809,7 @@ pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
@@ -34830,7 +34830,7 @@ pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
@@ -34851,7 +34851,7 @@ pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
@@ -34872,7 +34872,7 @@ pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
@@ -34893,7 +34893,7 @@ pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
@@ -34914,7 +34914,7 @@ pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
@@ -34935,7 +34935,7 @@ pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
@@ -34956,7 +34956,7 @@ pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
@@ -34977,7 +34977,7 @@ pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
@@ -34998,7 +34998,7 @@ pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
@@ -35019,7 +35019,7 @@ pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
@@ -35040,7 +35040,7 @@ pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
@@ -35061,7 +35061,7 @@ pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
@@ -35082,7 +35082,7 @@ pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
@@ -35103,7 +35103,7 @@ pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
@@ -35124,7 +35124,7 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
@@ -35147,7 +35147,7 @@ pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
@@ -35170,7 +35170,7 @@ pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -35191,7 +35191,7 @@ pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -35212,7 +35212,7 @@ pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -35233,7 +35233,7 @@ pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -35254,7 +35254,7 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
@@ -35277,7 +35277,7 @@ pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
@@ -35300,7 +35300,7 @@ pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -35321,7 +35321,7 @@ pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -35342,7 +35342,7 @@ pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -35363,7 +35363,7 @@ pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -35384,7 +35384,7 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -35407,7 +35407,7 @@ pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -35430,7 +35430,7 @@ pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -35453,7 +35453,7 @@ pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -35476,7 +35476,7 @@ pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35498,7 +35498,7 @@ pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35520,7 +35520,7 @@ pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35542,7 +35542,7 @@ pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35564,7 +35564,7 @@ pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35593,7 +35593,7 @@ pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35622,7 +35622,7 @@ pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35651,7 +35651,7 @@ pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -35680,7 +35680,7 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
@@ -35706,7 +35706,7 @@ pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
@@ -35732,7 +35732,7 @@ pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -35753,7 +35753,7 @@ pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -35774,7 +35774,7 @@ pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -35803,7 +35803,7 @@ pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -35832,7 +35832,7 @@ pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -35861,7 +35861,7 @@ pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -35890,7 +35890,7 @@ pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -35919,7 +35919,7 @@ pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -35948,7 +35948,7 @@ pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -35977,7 +35977,7 @@ pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -36006,7 +36006,7 @@ pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -36035,7 +36035,7 @@ pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -36064,7 +36064,7 @@ pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -36093,7 +36093,7 @@ pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
@@ -36122,7 +36122,7 @@ pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
@@ -36151,7 +36151,7 @@ pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
@@ -36180,7 +36180,7 @@ pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
@@ -36209,7 +36209,7 @@ pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
@@ -36238,7 +36238,7 @@ pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
@@ -36267,7 +36267,7 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36294,7 +36294,7 @@ pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36320,7 +36320,7 @@ pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36347,7 +36347,7 @@ pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36373,7 +36373,7 @@ pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36412,7 +36412,7 @@ pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36439,7 +36439,7 @@ pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36478,7 +36478,7 @@ pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -36505,7 +36505,7 @@ pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36526,7 +36526,7 @@ pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36547,7 +36547,7 @@ pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36568,7 +36568,7 @@ pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36589,7 +36589,7 @@ pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36618,7 +36618,7 @@ pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36647,7 +36647,7 @@ pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36676,7 +36676,7 @@ pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -36705,7 +36705,7 @@ pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36734,7 +36734,7 @@ pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36763,7 +36763,7 @@ pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36792,7 +36792,7 @@ pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36821,7 +36821,7 @@ pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36850,7 +36850,7 @@ pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36879,7 +36879,7 @@ pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36908,7 +36908,7 @@ pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36937,7 +36937,7 @@ pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36966,7 +36966,7 @@ pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -36995,7 +36995,7 @@ pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -37024,7 +37024,7 @@ pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -37053,7 +37053,7 @@ pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -37082,7 +37082,7 @@ pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -37111,7 +37111,7 @@ pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -37140,7 +37140,7 @@ pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -37169,7 +37169,7 @@ pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -37185,7 +37185,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -37201,7 +37201,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -37217,7 +37217,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -37236,7 +37236,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -37255,7 +37255,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -37274,7 +37274,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -37290,7 +37290,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -37306,7 +37306,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -37322,7 +37322,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -37341,7 +37341,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -37360,7 +37360,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -37379,7 +37379,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -37395,7 +37395,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -37411,7 +37411,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -37427,7 +37427,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -37446,7 +37446,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -37465,7 +37465,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -37484,7 +37484,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37507,7 +37507,7 @@ pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37530,7 +37530,7 @@ pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37553,7 +37553,7 @@ pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37576,7 +37576,7 @@ pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37599,7 +37599,7 @@ pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37622,7 +37622,7 @@ pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37645,7 +37645,7 @@ pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37668,7 +37668,7 @@ pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37691,7 +37691,7 @@ pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37714,7 +37714,7 @@ pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37737,7 +37737,7 @@ pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37760,7 +37760,7 @@ pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37783,7 +37783,7 @@ pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37806,7 +37806,7 @@ pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37829,7 +37829,7 @@ pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -37852,7 +37852,7 @@ pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -37881,7 +37881,7 @@ pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -37910,7 +37910,7 @@ pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -37939,7 +37939,7 @@ pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -37968,7 +37968,7 @@ pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -37997,7 +37997,7 @@ pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38026,7 +38026,7 @@ pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38055,7 +38055,7 @@ pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38084,7 +38084,7 @@ pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38113,7 +38113,7 @@ pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38142,7 +38142,7 @@ pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38171,7 +38171,7 @@ pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38200,7 +38200,7 @@ pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38229,7 +38229,7 @@ pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38258,7 +38258,7 @@ pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38287,7 +38287,7 @@ pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -38316,7 +38316,7 @@ pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38332,7 +38332,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38348,7 +38348,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38364,7 +38364,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38380,7 +38380,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38396,7 +38396,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38412,7 +38412,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38428,7 +38428,7 @@ pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -38444,7 +38444,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38463,7 +38463,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38482,7 +38482,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38501,7 +38501,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38520,7 +38520,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38539,7 +38539,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38558,7 +38558,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38577,7 +38577,7 @@ pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -38596,7 +38596,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -38612,7 +38612,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -38628,7 +38628,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -38644,7 +38644,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -38663,7 +38663,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -38682,7 +38682,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -38701,7 +38701,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -38717,7 +38717,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -38733,7 +38733,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -38749,7 +38749,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -38768,7 +38768,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -38787,7 +38787,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -38806,7 +38806,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -38822,7 +38822,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -38838,7 +38838,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -38854,7 +38854,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -38873,7 +38873,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -38892,7 +38892,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -38911,7 +38911,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
@@ -38932,7 +38932,7 @@ pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
@@ -38953,7 +38953,7 @@ pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
@@ -38974,7 +38974,7 @@ pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
@@ -38995,7 +38995,7 @@ pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
@@ -39016,7 +39016,7 @@ pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
@@ -39037,7 +39037,7 @@ pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
@@ -39058,7 +39058,7 @@ pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
@@ -39079,7 +39079,7 @@ pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
@@ -39100,7 +39100,7 @@ pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
@@ -39121,7 +39121,7 @@ pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
@@ -39142,7 +39142,7 @@ pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
@@ -39163,7 +39163,7 @@ pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
@@ -39184,7 +39184,7 @@ pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
@@ -39205,7 +39205,7 @@ pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
@@ -39226,7 +39226,7 @@ pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
@@ -39247,7 +39247,7 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -39269,7 +39269,7 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -39291,7 +39291,7 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -39313,7 +39313,7 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -39337,7 +39337,7 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -39361,7 +39361,7 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -39385,7 +39385,7 @@ pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -39414,7 +39414,7 @@ pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -39443,7 +39443,7 @@ pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -39472,7 +39472,7 @@ pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39494,7 +39494,7 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39521,7 +39521,7 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39543,7 +39543,7 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39570,7 +39570,7 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39592,7 +39592,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39619,7 +39619,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
 #[cfg_attr(
@@ -39649,7 +39649,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
 #[cfg_attr(
@@ -39679,7 +39679,7 @@ pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -39708,7 +39708,7 @@ pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -39737,7 +39737,7 @@ pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unsigned reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -39766,7 +39766,7 @@ pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -39795,7 +39795,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
 #[cfg_attr(
@@ -39825,7 +39825,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
 #[cfg_attr(
@@ -39855,7 +39855,7 @@ pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
@@ -39884,7 +39884,7 @@ pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
@@ -39913,7 +39913,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39936,7 +39936,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39963,7 +39963,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -39986,7 +39986,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40013,7 +40013,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40036,7 +40036,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40063,7 +40063,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40086,7 +40086,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40113,7 +40113,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40136,7 +40136,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40162,7 +40162,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40185,7 +40185,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40212,7 +40212,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40235,7 +40235,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40262,7 +40262,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40285,7 +40285,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40312,7 +40312,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40335,7 +40335,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40361,7 +40361,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40384,7 +40384,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40411,7 +40411,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40434,7 +40434,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40461,7 +40461,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40484,7 +40484,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40511,7 +40511,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40534,7 +40534,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40565,7 +40565,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40588,7 +40588,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40615,7 +40615,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40638,7 +40638,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40665,7 +40665,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40688,7 +40688,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40715,7 +40715,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40738,7 +40738,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40769,7 +40769,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40792,7 +40792,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40819,7 +40819,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40842,7 +40842,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40869,7 +40869,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40892,7 +40892,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40919,7 +40919,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40942,7 +40942,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40973,7 +40973,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -40996,7 +40996,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41023,7 +41023,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41046,7 +41046,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41073,7 +41073,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41096,7 +41096,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41123,7 +41123,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41146,7 +41146,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41173,7 +41173,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41196,7 +41196,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41224,7 +41224,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41247,7 +41247,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41274,7 +41274,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41297,7 +41297,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41324,7 +41324,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41347,7 +41347,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41374,7 +41374,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41397,7 +41397,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41424,7 +41424,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41447,7 +41447,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41473,7 +41473,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41496,7 +41496,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41523,7 +41523,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41546,7 +41546,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41573,7 +41573,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41596,7 +41596,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41624,7 +41624,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41647,7 +41647,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41674,7 +41674,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41697,7 +41697,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41724,7 +41724,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41747,7 +41747,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41774,7 +41774,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41797,7 +41797,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41824,7 +41824,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41847,7 +41847,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41873,7 +41873,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41896,7 +41896,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41923,7 +41923,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41946,7 +41946,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41973,7 +41973,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -41996,7 +41996,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42024,7 +42024,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42047,7 +42047,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42074,7 +42074,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42097,7 +42097,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42124,7 +42124,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42147,7 +42147,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42173,7 +42173,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42196,7 +42196,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42222,7 +42222,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42245,7 +42245,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42271,7 +42271,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42294,7 +42294,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42321,7 +42321,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42344,7 +42344,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42370,7 +42370,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42393,7 +42393,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -42420,7 +42420,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42442,7 +42442,7 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42467,7 +42467,7 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42489,7 +42489,7 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42515,7 +42515,7 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42537,7 +42537,7 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42563,7 +42563,7 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42585,7 +42585,7 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42611,7 +42611,7 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42633,7 +42633,7 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42658,7 +42658,7 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42680,7 +42680,7 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42706,7 +42706,7 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42728,7 +42728,7 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42754,7 +42754,7 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42776,7 +42776,7 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42802,7 +42802,7 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42824,7 +42824,7 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42849,7 +42849,7 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42871,7 +42871,7 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42897,7 +42897,7 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42919,7 +42919,7 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42945,7 +42945,7 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42967,7 +42967,7 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42992,7 +42992,7 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43014,7 +43014,7 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43044,7 +43044,7 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43066,7 +43066,7 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43092,7 +43092,7 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43114,7 +43114,7 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43140,7 +43140,7 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43162,7 +43162,7 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43188,7 +43188,7 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43210,7 +43210,7 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43240,7 +43240,7 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43262,7 +43262,7 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43288,7 +43288,7 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43310,7 +43310,7 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43336,7 +43336,7 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43358,7 +43358,7 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43384,7 +43384,7 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43406,7 +43406,7 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43436,7 +43436,7 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43458,7 +43458,7 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43484,7 +43484,7 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43506,7 +43506,7 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43532,7 +43532,7 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43554,7 +43554,7 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43580,7 +43580,7 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43602,7 +43602,7 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43628,7 +43628,7 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43650,7 +43650,7 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43675,7 +43675,7 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43697,7 +43697,7 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43723,7 +43723,7 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43745,7 +43745,7 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43771,7 +43771,7 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43793,7 +43793,7 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43819,7 +43819,7 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43841,7 +43841,7 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43866,7 +43866,7 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43888,7 +43888,7 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43914,7 +43914,7 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43936,7 +43936,7 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43962,7 +43962,7 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -43984,7 +43984,7 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44011,7 +44011,7 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44033,7 +44033,7 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44060,7 +44060,7 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44082,7 +44082,7 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44109,7 +44109,7 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44131,7 +44131,7 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44158,7 +44158,7 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44180,7 +44180,7 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44211,7 +44211,7 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44233,7 +44233,7 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44260,7 +44260,7 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44282,7 +44282,7 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44309,7 +44309,7 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44331,7 +44331,7 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44358,7 +44358,7 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44380,7 +44380,7 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44411,7 +44411,7 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44433,7 +44433,7 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44460,7 +44460,7 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44482,7 +44482,7 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44508,7 +44508,7 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44530,7 +44530,7 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44556,7 +44556,7 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44578,7 +44578,7 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44604,7 +44604,7 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44626,7 +44626,7 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44651,7 +44651,7 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44673,7 +44673,7 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44699,7 +44699,7 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44721,7 +44721,7 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44747,7 +44747,7 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44769,7 +44769,7 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44795,7 +44795,7 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44817,7 +44817,7 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44842,7 +44842,7 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44864,7 +44864,7 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44890,7 +44890,7 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44912,7 +44912,7 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44938,7 +44938,7 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44960,7 +44960,7 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -44986,7 +44986,7 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45008,7 +45008,7 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45038,7 +45038,7 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45060,7 +45060,7 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45086,7 +45086,7 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45108,7 +45108,7 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45134,7 +45134,7 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45156,7 +45156,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45186,7 +45186,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45208,7 +45208,7 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45234,7 +45234,7 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45256,7 +45256,7 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45282,7 +45282,7 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45304,7 +45304,7 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45330,7 +45330,7 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45352,7 +45352,7 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45382,7 +45382,7 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45404,7 +45404,7 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45430,7 +45430,7 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45452,7 +45452,7 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45478,7 +45478,7 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45500,7 +45500,7 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45526,7 +45526,7 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45548,7 +45548,7 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45574,7 +45574,7 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45596,7 +45596,7 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45621,7 +45621,7 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45643,7 +45643,7 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45669,7 +45669,7 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45691,7 +45691,7 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45717,7 +45717,7 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45739,7 +45739,7 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45765,7 +45765,7 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45787,7 +45787,7 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45812,7 +45812,7 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45834,7 +45834,7 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45860,7 +45860,7 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45882,7 +45882,7 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45908,7 +45908,7 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45930,7 +45930,7 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45956,7 +45956,7 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45978,7 +45978,7 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46008,7 +46008,7 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46030,7 +46030,7 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46056,7 +46056,7 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46078,7 +46078,7 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46104,7 +46104,7 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46126,7 +46126,7 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46156,7 +46156,7 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46178,7 +46178,7 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46204,7 +46204,7 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46226,7 +46226,7 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46252,7 +46252,7 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46274,7 +46274,7 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46300,7 +46300,7 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46322,7 +46322,7 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46352,7 +46352,7 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46374,7 +46374,7 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46400,7 +46400,7 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46422,7 +46422,7 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46447,7 +46447,7 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46469,7 +46469,7 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46494,7 +46494,7 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46516,7 +46516,7 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46541,7 +46541,7 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46563,7 +46563,7 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46588,7 +46588,7 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46610,7 +46610,7 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46635,7 +46635,7 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46657,7 +46657,7 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46682,7 +46682,7 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46704,7 +46704,7 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46729,7 +46729,7 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46750,7 +46750,7 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46772,7 +46772,7 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46797,7 +46797,7 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46819,7 +46819,7 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46844,7 +46844,7 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46866,7 +46866,7 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46892,7 +46892,7 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46914,7 +46914,7 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46944,7 +46944,7 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46966,7 +46966,7 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46992,7 +46992,7 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47014,7 +47014,7 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47040,7 +47040,7 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47062,7 +47062,7 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47092,7 +47092,7 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47114,7 +47114,7 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47140,7 +47140,7 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47162,7 +47162,7 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47188,7 +47188,7 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47210,7 +47210,7 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47236,7 +47236,7 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47258,7 +47258,7 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47288,7 +47288,7 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47310,7 +47310,7 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47336,7 +47336,7 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47358,7 +47358,7 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47384,7 +47384,7 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47406,7 +47406,7 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47432,7 +47432,7 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47454,7 +47454,7 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47480,7 +47480,7 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47502,7 +47502,7 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47528,7 +47528,7 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47550,7 +47550,7 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47575,7 +47575,7 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47597,7 +47597,7 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47623,7 +47623,7 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47645,7 +47645,7 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47671,7 +47671,7 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47693,7 +47693,7 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47718,7 +47718,7 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47740,7 +47740,7 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47766,7 +47766,7 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47788,7 +47788,7 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47814,7 +47814,7 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47836,7 +47836,7 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47863,7 +47863,7 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47885,7 +47885,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47916,7 +47916,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47938,7 +47938,7 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47965,7 +47965,7 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47987,7 +47987,7 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48014,7 +48014,7 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48036,7 +48036,7 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48063,7 +48063,7 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48085,7 +48085,7 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48112,7 +48112,7 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48134,7 +48134,7 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48161,7 +48161,7 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48183,7 +48183,7 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48210,7 +48210,7 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48232,7 +48232,7 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48263,7 +48263,7 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48285,7 +48285,7 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48312,7 +48312,7 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48334,7 +48334,7 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48360,7 +48360,7 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48382,7 +48382,7 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48408,7 +48408,7 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48430,7 +48430,7 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48456,7 +48456,7 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48478,7 +48478,7 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48504,7 +48504,7 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48526,7 +48526,7 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48551,7 +48551,7 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48573,7 +48573,7 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48599,7 +48599,7 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48621,7 +48621,7 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48647,7 +48647,7 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48669,7 +48669,7 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48694,7 +48694,7 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48716,7 +48716,7 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48742,7 +48742,7 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48764,7 +48764,7 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48790,7 +48790,7 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48812,7 +48812,7 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48838,7 +48838,7 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48860,7 +48860,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48890,7 +48890,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48912,7 +48912,7 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48938,7 +48938,7 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48960,7 +48960,7 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48986,7 +48986,7 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49008,7 +49008,7 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49034,7 +49034,7 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49056,7 +49056,7 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49086,7 +49086,7 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49108,7 +49108,7 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49134,7 +49134,7 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49156,7 +49156,7 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49182,7 +49182,7 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49204,7 +49204,7 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49234,7 +49234,7 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49256,7 +49256,7 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49282,7 +49282,7 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49304,7 +49304,7 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49330,7 +49330,7 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49352,7 +49352,7 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49378,7 +49378,7 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49400,7 +49400,7 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49426,7 +49426,7 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49448,7 +49448,7 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49474,7 +49474,7 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49496,7 +49496,7 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49521,7 +49521,7 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49543,7 +49543,7 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49569,7 +49569,7 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49591,7 +49591,7 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49617,7 +49617,7 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49639,7 +49639,7 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49664,7 +49664,7 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49686,7 +49686,7 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49712,7 +49712,7 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49734,7 +49734,7 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49760,7 +49760,7 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49782,7 +49782,7 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49808,7 +49808,7 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49830,7 +49830,7 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49860,7 +49860,7 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49882,7 +49882,7 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49908,7 +49908,7 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49930,7 +49930,7 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49956,7 +49956,7 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49978,7 +49978,7 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50004,7 +50004,7 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50026,7 +50026,7 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50056,7 +50056,7 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50078,7 +50078,7 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50104,7 +50104,7 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50126,7 +50126,7 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50152,7 +50152,7 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50174,7 +50174,7 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50204,7 +50204,7 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50226,7 +50226,7 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50252,7 +50252,7 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50274,7 +50274,7 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50299,7 +50299,7 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50321,7 +50321,7 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50346,7 +50346,7 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50368,7 +50368,7 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50393,7 +50393,7 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50415,7 +50415,7 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50440,7 +50440,7 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50461,7 +50461,7 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50483,7 +50483,7 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50508,7 +50508,7 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50530,7 +50530,7 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50555,7 +50555,7 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50577,7 +50577,7 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50602,7 +50602,7 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50624,7 +50624,7 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50649,7 +50649,7 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50671,7 +50671,7 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50696,7 +50696,7 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50718,7 +50718,7 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50744,7 +50744,7 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50766,7 +50766,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50796,7 +50796,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50818,7 +50818,7 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50844,7 +50844,7 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50866,7 +50866,7 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50892,7 +50892,7 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50914,7 +50914,7 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50940,7 +50940,7 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50962,7 +50962,7 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50992,7 +50992,7 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51014,7 +51014,7 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51040,7 +51040,7 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51062,7 +51062,7 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51088,7 +51088,7 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51110,7 +51110,7 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51140,7 +51140,7 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51162,7 +51162,7 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51188,7 +51188,7 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51210,7 +51210,7 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51236,7 +51236,7 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51258,7 +51258,7 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51284,7 +51284,7 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51306,7 +51306,7 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51332,7 +51332,7 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51354,7 +51354,7 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51380,7 +51380,7 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51402,7 +51402,7 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51427,7 +51427,7 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51449,7 +51449,7 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51475,7 +51475,7 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51497,7 +51497,7 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51523,7 +51523,7 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51545,7 +51545,7 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51571,7 +51571,7 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51593,7 +51593,7 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51618,7 +51618,7 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51640,7 +51640,7 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51666,7 +51666,7 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51688,7 +51688,7 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51715,7 +51715,7 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51737,7 +51737,7 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51768,7 +51768,7 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51790,7 +51790,7 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51817,7 +51817,7 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51839,7 +51839,7 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51866,7 +51866,7 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51888,7 +51888,7 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51915,7 +51915,7 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51937,7 +51937,7 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51968,7 +51968,7 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51990,7 +51990,7 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52017,7 +52017,7 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52039,7 +52039,7 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52066,7 +52066,7 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52088,7 +52088,7 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52115,7 +52115,7 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52137,7 +52137,7 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52164,7 +52164,7 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52186,7 +52186,7 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52212,7 +52212,7 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52234,7 +52234,7 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52260,7 +52260,7 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52282,7 +52282,7 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52308,7 +52308,7 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52330,7 +52330,7 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52356,7 +52356,7 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52378,7 +52378,7 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52403,7 +52403,7 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52425,7 +52425,7 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52451,7 +52451,7 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52473,7 +52473,7 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52499,7 +52499,7 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52521,7 +52521,7 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52547,7 +52547,7 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52569,7 +52569,7 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52594,7 +52594,7 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52616,7 +52616,7 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52642,7 +52642,7 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52664,7 +52664,7 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52690,7 +52690,7 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52712,7 +52712,7 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52742,7 +52742,7 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52764,7 +52764,7 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52790,7 +52790,7 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52812,7 +52812,7 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52838,7 +52838,7 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52860,7 +52860,7 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52886,7 +52886,7 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52908,7 +52908,7 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52938,7 +52938,7 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52960,7 +52960,7 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52986,7 +52986,7 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53008,7 +53008,7 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53034,7 +53034,7 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53056,7 +53056,7 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53082,7 +53082,7 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53104,7 +53104,7 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53134,7 +53134,7 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53156,7 +53156,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53185,7 +53185,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53207,7 +53207,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53232,7 +53232,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53254,7 +53254,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53279,7 +53279,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53301,7 +53301,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53326,7 +53326,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53348,7 +53348,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53377,7 +53377,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53399,7 +53399,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53424,7 +53424,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53446,7 +53446,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53471,7 +53471,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53493,7 +53493,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53518,7 +53518,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53540,7 +53540,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53569,7 +53569,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53591,7 +53591,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53616,7 +53616,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53638,7 +53638,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53663,7 +53663,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53685,7 +53685,7 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53710,7 +53710,7 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53732,7 +53732,7 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53758,7 +53758,7 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53780,7 +53780,7 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53807,7 +53807,7 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53829,7 +53829,7 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53854,7 +53854,7 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53876,7 +53876,7 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53901,7 +53901,7 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53923,7 +53923,7 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53949,7 +53949,7 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53971,7 +53971,7 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -53996,7 +53996,7 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54018,7 +54018,7 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54043,7 +54043,7 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54065,7 +54065,7 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54091,7 +54091,7 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54113,7 +54113,7 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54138,7 +54138,7 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54160,7 +54160,7 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54185,7 +54185,7 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54207,7 +54207,7 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54233,7 +54233,7 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54255,7 +54255,7 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54282,7 +54282,7 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54304,7 +54304,7 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54329,7 +54329,7 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54351,7 +54351,7 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54376,7 +54376,7 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54398,7 +54398,7 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54424,7 +54424,7 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54446,7 +54446,7 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54471,7 +54471,7 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54493,7 +54493,7 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54518,7 +54518,7 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54540,7 +54540,7 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54566,7 +54566,7 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54588,7 +54588,7 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54613,7 +54613,7 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54635,7 +54635,7 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54660,7 +54660,7 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54682,7 +54682,7 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54708,7 +54708,7 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54730,7 +54730,7 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54757,7 +54757,7 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54779,7 +54779,7 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54804,7 +54804,7 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54826,7 +54826,7 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54851,7 +54851,7 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54873,7 +54873,7 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54899,7 +54899,7 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54921,7 +54921,7 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54946,7 +54946,7 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54968,7 +54968,7 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -54993,7 +54993,7 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55015,7 +55015,7 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55040,7 +55040,7 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55062,7 +55062,7 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55087,7 +55087,7 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55109,7 +55109,7 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55134,7 +55134,7 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55156,7 +55156,7 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55181,7 +55181,7 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55203,7 +55203,7 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55228,7 +55228,7 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55250,7 +55250,7 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55275,7 +55275,7 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55297,7 +55297,7 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55322,7 +55322,7 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55344,7 +55344,7 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55374,7 +55374,7 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55396,7 +55396,7 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55422,7 +55422,7 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55444,7 +55444,7 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55470,7 +55470,7 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55492,7 +55492,7 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55522,7 +55522,7 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55544,7 +55544,7 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55570,7 +55570,7 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55592,7 +55592,7 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55618,7 +55618,7 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55640,7 +55640,7 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55670,7 +55670,7 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55692,7 +55692,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55718,7 +55718,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -55739,7 +55739,7 @@ pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -55760,7 +55760,7 @@ pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -55781,7 +55781,7 @@ pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -55802,7 +55802,7 @@ pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -55823,7 +55823,7 @@ pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -55844,7 +55844,7 @@ pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -55865,7 +55865,7 @@ pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -55886,7 +55886,7 @@ pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -55907,7 +55907,7 @@ pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -55928,7 +55928,7 @@ pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -55949,7 +55949,7 @@ pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -55970,7 +55970,7 @@ pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -55991,7 +55991,7 @@ pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -56012,7 +56012,7 @@ pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -56033,7 +56033,7 @@ pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -56054,7 +56054,7 @@ pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -56075,7 +56075,7 @@ pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -56096,7 +56096,7 @@ pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -56117,7 +56117,7 @@ pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -56138,7 +56138,7 @@ pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -56159,7 +56159,7 @@ pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -56180,7 +56180,7 @@ pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -56201,7 +56201,7 @@ pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -56222,7 +56222,7 @@ pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -56243,7 +56243,7 @@ pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -56264,7 +56264,7 @@ pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -56285,7 +56285,7 @@ pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -56306,7 +56306,7 @@ pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -56327,7 +56327,7 @@ pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -56348,7 +56348,7 @@ pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -56369,7 +56369,7 @@ pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -56390,7 +56390,7 @@ pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -56411,7 +56411,7 @@ pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -56432,7 +56432,7 @@ pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -56453,7 +56453,7 @@ pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -56474,7 +56474,7 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse elements in 64-bit doublewords"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
 #[cfg_attr(
@@ -56496,7 +56496,7 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reverse elements in 64-bit doublewords"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
 #[cfg_attr(
@@ -56518,7 +56518,7 @@ pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
@@ -56547,7 +56547,7 @@ pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
@@ -56576,7 +56576,7 @@ pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
@@ -56605,7 +56605,7 @@ pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
@@ -56634,7 +56634,7 @@ pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
@@ -56663,7 +56663,7 @@ pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
@@ -56692,7 +56692,7 @@ pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
@@ -56721,7 +56721,7 @@ pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
@@ -56750,7 +56750,7 @@ pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
@@ -56779,7 +56779,7 @@ pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
@@ -56808,7 +56808,7 @@ pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
@@ -56837,7 +56837,7 @@ pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
@@ -56866,7 +56866,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
 #[cfg_attr(
@@ -56895,7 +56895,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
 #[cfg_attr(
@@ -56924,7 +56924,7 @@ pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
@@ -56952,7 +56952,7 @@ pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
@@ -56980,7 +56980,7 @@ pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57009,7 +57009,7 @@ pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57038,7 +57038,7 @@ pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57067,7 +57067,7 @@ pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57096,7 +57096,7 @@ pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57125,7 +57125,7 @@ pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57154,7 +57154,7 @@ pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57183,7 +57183,7 @@ pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57212,7 +57212,7 @@ pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57241,7 +57241,7 @@ pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57270,7 +57270,7 @@ pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57299,7 +57299,7 @@ pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57328,7 +57328,7 @@ pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57357,7 +57357,7 @@ pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57386,7 +57386,7 @@ pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57415,7 +57415,7 @@ pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -57444,7 +57444,7 @@ pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57467,7 +57467,7 @@ pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57490,7 +57490,7 @@ pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57513,7 +57513,7 @@ pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57536,7 +57536,7 @@ pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57559,7 +57559,7 @@ pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57582,7 +57582,7 @@ pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57605,7 +57605,7 @@ pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57628,7 +57628,7 @@ pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57651,7 +57651,7 @@ pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57674,7 +57674,7 @@ pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57697,7 +57697,7 @@ pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57720,7 +57720,7 @@ pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57743,7 +57743,7 @@ pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57766,7 +57766,7 @@ pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57789,7 +57789,7 @@ pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -57812,7 +57812,7 @@ pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -57828,7 +57828,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -57844,7 +57844,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -57860,7 +57860,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -57879,7 +57879,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -57898,7 +57898,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -57917,7 +57917,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -57940,7 +57940,7 @@ pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -57963,7 +57963,7 @@ pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -57986,7 +57986,7 @@ pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -58016,7 +58016,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -58046,7 +58046,7 @@ pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -58075,7 +58075,7 @@ pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -58104,7 +58104,7 @@ pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unsigned reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -58133,7 +58133,7 @@ pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -58162,7 +58162,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -58192,7 +58192,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -58222,7 +58222,7 @@ pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -58251,7 +58251,7 @@ pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -58280,7 +58280,7 @@ pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58303,7 +58303,7 @@ pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58326,7 +58326,7 @@ pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58349,7 +58349,7 @@ pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58372,7 +58372,7 @@ pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58395,7 +58395,7 @@ pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58418,7 +58418,7 @@ pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58441,7 +58441,7 @@ pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58464,7 +58464,7 @@ pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58487,7 +58487,7 @@ pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58510,7 +58510,7 @@ pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58533,7 +58533,7 @@ pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58556,7 +58556,7 @@ pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58579,7 +58579,7 @@ pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58602,7 +58602,7 @@ pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58625,7 +58625,7 @@ pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -58648,7 +58648,7 @@ pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -58677,7 +58677,7 @@ pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -58706,7 +58706,7 @@ pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -58735,7 +58735,7 @@ pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -58757,7 +58757,7 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -58784,7 +58784,7 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -58806,7 +58806,7 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -58833,7 +58833,7 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -58855,7 +58855,7 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -58882,7 +58882,7 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -58899,7 +58899,7 @@ pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -58916,7 +58916,7 @@ pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -58939,7 +58939,7 @@ pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -58962,7 +58962,7 @@ pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -58985,7 +58985,7 @@ pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59008,7 +59008,7 @@ pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59031,7 +59031,7 @@ pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59054,7 +59054,7 @@ pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59077,7 +59077,7 @@ pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59100,7 +59100,7 @@ pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59123,7 +59123,7 @@ pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59146,7 +59146,7 @@ pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59169,7 +59169,7 @@ pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59192,7 +59192,7 @@ pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59215,7 +59215,7 @@ pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59238,7 +59238,7 @@ pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59261,7 +59261,7 @@ pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59284,7 +59284,7 @@ pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59307,7 +59307,7 @@ pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59330,7 +59330,7 @@ pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59353,7 +59353,7 @@ pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59376,7 +59376,7 @@ pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59399,7 +59399,7 @@ pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59422,7 +59422,7 @@ pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59445,7 +59445,7 @@ pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -59468,7 +59468,7 @@ pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "SHA1 hash update accelerator, choose."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1c))]
@@ -59493,7 +59493,7 @@ pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 fixed rotate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1h))]
@@ -59518,7 +59518,7 @@ pub fn vsha1h_u32(hash_e: u32) -> u32 {
 }
 #[doc = "SHA1 hash update accelerator, majority"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1m))]
@@ -59543,7 +59543,7 @@ pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 hash update accelerator, parity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1p))]
@@ -59568,7 +59568,7 @@ pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1su0))]
@@ -59593,7 +59593,7 @@ pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> u
 }
 #[doc = "SHA1 schedule update accelerator, second part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1su1))]
@@ -59618,7 +59618,7 @@ pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SHA1 schedule update accelerator, upper part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256h2))]
@@ -59647,7 +59647,7 @@ pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4
 }
 #[doc = "SHA1 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256h))]
@@ -59676,7 +59676,7 @@ pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_
 }
 #[doc = "SHA256 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256su0))]
@@ -59701,7 +59701,7 @@ pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SHA256 schedule update accelerator, second part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256su1))]
@@ -59725,7 +59725,7 @@ pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
     }
     unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59738,7 +59738,7 @@ fn vshiftlins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     }
     unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59751,7 +59751,7 @@ fn vshiftlins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     }
     unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59764,7 +59764,7 @@ fn vshiftlins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     }
     unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59777,7 +59777,7 @@ fn vshiftlins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     }
     unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59790,7 +59790,7 @@ fn vshiftlins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     }
     unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59803,7 +59803,7 @@ fn vshiftlins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     }
     unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59816,7 +59816,7 @@ fn vshiftlins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     }
     unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) }
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59831,7 +59831,7 @@ fn vshiftlins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59846,7 +59846,7 @@ fn vshiftrins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59861,7 +59861,7 @@ fn vshiftrins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59876,7 +59876,7 @@ fn vshiftrins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59891,7 +59891,7 @@ fn vshiftrins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59906,7 +59906,7 @@ fn vshiftrins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59921,7 +59921,7 @@ fn vshiftrins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59936,7 +59936,7 @@ fn vshiftrins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -59951,7 +59951,7 @@ fn vshiftrins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -59974,7 +59974,7 @@ pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -59997,7 +59997,7 @@ pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60020,7 +60020,7 @@ pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60043,7 +60043,7 @@ pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60066,7 +60066,7 @@ pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60089,7 +60089,7 @@ pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60112,7 +60112,7 @@ pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60135,7 +60135,7 @@ pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60158,7 +60158,7 @@ pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60181,7 +60181,7 @@ pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60204,7 +60204,7 @@ pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60227,7 +60227,7 @@ pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60250,7 +60250,7 @@ pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60273,7 +60273,7 @@ pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60296,7 +60296,7 @@ pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -60319,7 +60319,7 @@ pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60348,7 +60348,7 @@ pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60377,7 +60377,7 @@ pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60406,7 +60406,7 @@ pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60435,7 +60435,7 @@ pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60464,7 +60464,7 @@ pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60493,7 +60493,7 @@ pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60522,7 +60522,7 @@ pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60551,7 +60551,7 @@ pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60580,7 +60580,7 @@ pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60609,7 +60609,7 @@ pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60638,7 +60638,7 @@ pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60667,7 +60667,7 @@ pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60696,7 +60696,7 @@ pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60725,7 +60725,7 @@ pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60754,7 +60754,7 @@ pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -60783,7 +60783,7 @@ pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
@@ -60806,7 +60806,7 @@ pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
@@ -60829,7 +60829,7 @@ pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
@@ -60852,7 +60852,7 @@ pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
@@ -60875,7 +60875,7 @@ pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
@@ -60898,7 +60898,7 @@ pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
@@ -60921,7 +60921,7 @@ pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
@@ -60945,7 +60945,7 @@ pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
@@ -60969,7 +60969,7 @@ pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
@@ -60993,7 +60993,7 @@ pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
@@ -61017,7 +61017,7 @@ pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
@@ -61041,7 +61041,7 @@ pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
@@ -61065,7 +61065,7 @@ pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
@@ -61089,7 +61089,7 @@ pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
@@ -61113,7 +61113,7 @@ pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
@@ -61141,7 +61141,7 @@ pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
@@ -61169,7 +61169,7 @@ pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
@@ -61197,7 +61197,7 @@ pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
@@ -61225,7 +61225,7 @@ pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
@@ -61253,7 +61253,7 @@ pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
@@ -61281,7 +61281,7 @@ pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
@@ -61309,7 +61309,7 @@ pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
@@ -61337,7 +61337,7 @@ pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
@@ -61360,7 +61360,7 @@ pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
@@ -61383,7 +61383,7 @@ pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
@@ -61406,7 +61406,7 @@ pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
@@ -61429,7 +61429,7 @@ pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
@@ -61452,7 +61452,7 @@ pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
@@ -61475,7 +61475,7 @@ pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61487,7 +61487,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61499,7 +61499,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61511,7 +61511,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61523,7 +61523,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61535,7 +61535,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61547,7 +61547,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61559,7 +61559,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61571,7 +61571,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61583,7 +61583,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61595,7 +61595,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61607,7 +61607,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61619,7 +61619,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61631,7 +61631,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61643,7 +61643,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61655,7 +61655,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61667,7 +61667,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61679,7 +61679,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61691,7 +61691,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61703,7 +61703,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -61715,7 +61715,7 @@ pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61738,7 +61738,7 @@ pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61761,7 +61761,7 @@ pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61784,7 +61784,7 @@ pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61807,7 +61807,7 @@ pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61830,7 +61830,7 @@ pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61853,7 +61853,7 @@ pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61876,7 +61876,7 @@ pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61899,7 +61899,7 @@ pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61922,7 +61922,7 @@ pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61945,7 +61945,7 @@ pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61968,7 +61968,7 @@ pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -61991,7 +61991,7 @@ pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -62014,7 +62014,7 @@ pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -62037,7 +62037,7 @@ pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -62060,7 +62060,7 @@ pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -62083,7 +62083,7 @@ pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62095,7 +62095,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62107,7 +62107,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62119,7 +62119,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62131,7 +62131,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62143,7 +62143,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62155,7 +62155,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62167,7 +62167,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62179,7 +62179,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62191,7 +62191,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62203,7 +62203,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62215,7 +62215,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62227,7 +62227,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62239,7 +62239,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62251,7 +62251,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62263,7 +62263,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62275,7 +62275,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62287,7 +62287,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62299,7 +62299,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62311,7 +62311,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -62325,7 +62325,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -62343,7 +62343,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -62361,7 +62361,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -62379,7 +62379,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -62397,7 +62397,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -62417,7 +62417,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -62437,7 +62437,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -62455,7 +62455,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -62473,7 +62473,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -62493,7 +62493,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -62513,7 +62513,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62538,7 +62538,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62563,7 +62563,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -62589,7 +62589,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -62615,7 +62615,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62629,7 +62629,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62643,7 +62643,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62657,7 +62657,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62671,7 +62671,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62685,7 +62685,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62699,7 +62699,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62713,7 +62713,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62727,7 +62727,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62741,7 +62741,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62755,7 +62755,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62769,7 +62769,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62783,7 +62783,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62797,7 +62797,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62811,7 +62811,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62825,7 +62825,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62839,7 +62839,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62853,7 +62853,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62867,7 +62867,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62881,7 +62881,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62895,7 +62895,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62909,7 +62909,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62923,7 +62923,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62937,7 +62937,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62951,7 +62951,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -62967,7 +62967,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -62983,7 +62983,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -63002,7 +63002,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -63021,7 +63021,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -63040,7 +63040,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -63059,7 +63059,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -63081,7 +63081,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -63103,7 +63103,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -63128,7 +63128,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -63153,7 +63153,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63173,7 +63173,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63193,7 +63193,7 @@ pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63218,7 +63218,7 @@ pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63243,7 +63243,7 @@ pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63268,7 +63268,7 @@ pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63293,7 +63293,7 @@ pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63318,7 +63318,7 @@ pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63343,7 +63343,7 @@ pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63368,7 +63368,7 @@ pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63393,7 +63393,7 @@ pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63418,7 +63418,7 @@ pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63443,7 +63443,7 @@ pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63468,7 +63468,7 @@ pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63493,7 +63493,7 @@ pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63518,7 +63518,7 @@ pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63543,7 +63543,7 @@ pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63568,7 +63568,7 @@ pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63593,7 +63593,7 @@ pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63618,7 +63618,7 @@ pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63643,7 +63643,7 @@ pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63668,7 +63668,7 @@ pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63693,7 +63693,7 @@ pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63718,7 +63718,7 @@ pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63743,7 +63743,7 @@ pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -63768,7 +63768,7 @@ pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -63791,7 +63791,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -63814,7 +63814,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -63837,7 +63837,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -63860,7 +63860,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -63883,7 +63883,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -63906,7 +63906,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -63925,7 +63925,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -63944,7 +63944,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -63963,7 +63963,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -63982,7 +63982,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64001,7 +64001,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64020,7 +64020,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64039,7 +64039,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64058,7 +64058,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64074,7 +64074,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64090,7 +64090,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64106,7 +64106,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64122,7 +64122,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64138,7 +64138,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64154,7 +64154,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64170,7 +64170,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64186,7 +64186,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64205,7 +64205,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64224,7 +64224,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64243,7 +64243,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64262,7 +64262,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64281,7 +64281,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64300,7 +64300,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64319,7 +64319,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64338,7 +64338,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64354,7 +64354,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64370,7 +64370,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64386,7 +64386,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64402,7 +64402,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64418,7 +64418,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64434,7 +64434,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64450,7 +64450,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64466,7 +64466,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64485,7 +64485,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64504,7 +64504,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64523,7 +64523,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64542,7 +64542,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64561,7 +64561,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64580,7 +64580,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64599,7 +64599,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -64618,7 +64618,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64634,7 +64634,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64650,7 +64650,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64666,7 +64666,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64682,7 +64682,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64698,7 +64698,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64714,7 +64714,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64730,7 +64730,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64746,7 +64746,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64769,7 +64769,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64792,7 +64792,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64815,7 +64815,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64838,7 +64838,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64861,7 +64861,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64884,7 +64884,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64907,7 +64907,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64930,7 +64930,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64953,7 +64953,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64976,7 +64976,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -64999,7 +64999,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65022,7 +65022,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65045,7 +65045,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65068,7 +65068,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65091,7 +65091,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65114,7 +65114,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65137,7 +65137,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65160,7 +65160,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65183,7 +65183,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65206,7 +65206,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65229,7 +65229,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65252,7 +65252,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65275,7 +65275,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65298,7 +65298,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65321,7 +65321,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65344,7 +65344,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65367,7 +65367,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65390,7 +65390,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65413,7 +65413,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65436,7 +65436,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65459,7 +65459,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65482,7 +65482,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65505,7 +65505,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65528,7 +65528,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65551,7 +65551,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -65570,7 +65570,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
     vst1q_s16_x4(transmute(a), transmute(b))
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65584,7 +65584,7 @@ unsafe fn vst1_v1i64<const ALIGN: i32>(addr: *const i8, val: int64x1_t) {
     }
     _vst1_v1i64(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65598,7 +65598,7 @@ unsafe fn vst1_v2f32<const ALIGN: i32>(addr: *const i8, val: float32x2_t) {
     }
     _vst1_v2f32(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65612,7 +65612,7 @@ unsafe fn vst1_v2i32<const ALIGN: i32>(addr: *const i8, val: int32x2_t) {
     }
     _vst1_v2i32(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65626,7 +65626,7 @@ unsafe fn vst1_v4i16<const ALIGN: i32>(addr: *const i8, val: int16x4_t) {
     }
     _vst1_v4i16(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65640,7 +65640,7 @@ unsafe fn vst1_v8i8<const ALIGN: i32>(addr: *const i8, val: int8x8_t) {
     }
     _vst1_v8i8(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65654,7 +65654,7 @@ unsafe fn vst1q_v16i8<const ALIGN: i32>(addr: *const i8, val: int8x16_t) {
     }
     _vst1q_v16i8(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65668,7 +65668,7 @@ unsafe fn vst1q_v2i64<const ALIGN: i32>(addr: *const i8, val: int64x2_t) {
     }
     _vst1q_v2i64(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65682,7 +65682,7 @@ unsafe fn vst1q_v4f32<const ALIGN: i32>(addr: *const i8, val: float32x4_t) {
     }
     _vst1q_v4f32(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65696,7 +65696,7 @@ unsafe fn vst1q_v4i32<const ALIGN: i32>(addr: *const i8, val: int32x4_t) {
     }
     _vst1q_v4i32(addr, val, ALIGN)
 }
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65714,7 +65714,7 @@ unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -65732,7 +65732,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -65750,7 +65750,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65775,7 +65775,7 @@ pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -65796,7 +65796,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -65817,7 +65817,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65836,7 +65836,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65855,7 +65855,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65867,7 +65867,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65879,7 +65879,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65891,7 +65891,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65903,7 +65903,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65915,7 +65915,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65927,7 +65927,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65939,7 +65939,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -65951,7 +65951,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65967,7 +65967,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65983,7 +65983,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65999,7 +65999,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66015,7 +66015,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66031,7 +66031,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66047,7 +66047,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66063,7 +66063,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66079,7 +66079,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66102,7 +66102,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66125,7 +66125,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66146,7 +66146,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66167,7 +66167,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66188,7 +66188,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66209,7 +66209,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66230,7 +66230,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66251,7 +66251,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66272,7 +66272,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66293,7 +66293,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -66314,7 +66314,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66332,7 +66332,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66350,7 +66350,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66368,7 +66368,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66386,7 +66386,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66404,7 +66404,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66422,7 +66422,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -66440,7 +66440,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66465,7 +66465,7 @@ pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66490,7 +66490,7 @@ pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66515,7 +66515,7 @@ pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66540,7 +66540,7 @@ pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66565,7 +66565,7 @@ pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66590,7 +66590,7 @@ pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66615,7 +66615,7 @@ pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -66640,7 +66640,7 @@ pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66663,7 +66663,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66675,7 +66675,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66687,7 +66687,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66710,7 +66710,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66733,7 +66733,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66756,7 +66756,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66779,7 +66779,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66802,7 +66802,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66825,7 +66825,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66848,7 +66848,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66871,7 +66871,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66894,7 +66894,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66917,7 +66917,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -66940,7 +66940,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66959,7 +66959,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66978,7 +66978,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -66999,7 +66999,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -67020,7 +67020,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67032,7 +67032,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67044,7 +67044,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67056,7 +67056,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67068,7 +67068,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67080,7 +67080,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67092,7 +67092,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67104,7 +67104,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67116,7 +67116,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67128,7 +67128,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67140,7 +67140,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67152,7 +67152,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67164,7 +67164,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67176,7 +67176,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67188,7 +67188,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67200,7 +67200,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67212,7 +67212,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67240,7 +67240,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67268,7 +67268,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67291,7 +67291,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67314,7 +67314,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67339,7 +67339,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67364,7 +67364,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67382,7 +67382,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67407,7 +67407,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67432,7 +67432,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67457,7 +67457,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -67482,7 +67482,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67503,7 +67503,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67524,7 +67524,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67545,7 +67545,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67566,7 +67566,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67587,7 +67587,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67608,7 +67608,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -67629,7 +67629,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67654,7 +67654,7 @@ pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67679,7 +67679,7 @@ pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67704,7 +67704,7 @@ pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67729,7 +67729,7 @@ pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67754,7 +67754,7 @@ pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67779,7 +67779,7 @@ pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67804,7 +67804,7 @@ pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -67829,7 +67829,7 @@ pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -67852,7 +67852,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67864,7 +67864,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67876,7 +67876,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -67899,7 +67899,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -67922,7 +67922,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -67945,7 +67945,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -67968,7 +67968,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -67991,7 +67991,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -68014,7 +68014,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -68037,7 +68037,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -68060,7 +68060,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -68083,7 +68083,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -68106,7 +68106,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -68129,7 +68129,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68155,7 +68155,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68181,7 +68181,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -68202,7 +68202,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -68223,7 +68223,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68246,7 +68246,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68269,7 +68269,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68285,7 +68285,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68308,7 +68308,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68331,7 +68331,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68354,7 +68354,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68377,7 +68377,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68400,7 +68400,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68412,7 +68412,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68424,7 +68424,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68436,7 +68436,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68448,7 +68448,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68460,7 +68460,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68472,7 +68472,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68484,7 +68484,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68496,7 +68496,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68525,7 +68525,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68554,7 +68554,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68584,7 +68584,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68614,7 +68614,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68640,7 +68640,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68666,7 +68666,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68692,7 +68692,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68718,7 +68718,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68744,7 +68744,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68770,7 +68770,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -68796,7 +68796,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68824,7 +68824,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68852,7 +68852,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68873,7 +68873,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68901,7 +68901,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68929,7 +68929,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68957,7 +68957,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68985,7 +68985,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69010,7 +69010,7 @@ pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69035,7 +69035,7 @@ pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69060,7 +69060,7 @@ pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69085,7 +69085,7 @@ pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69110,7 +69110,7 @@ pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69135,7 +69135,7 @@ pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69160,7 +69160,7 @@ pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -69185,7 +69185,7 @@ pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69208,7 +69208,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69220,7 +69220,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69232,7 +69232,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69255,7 +69255,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69278,7 +69278,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69301,7 +69301,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69324,7 +69324,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69347,7 +69347,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69370,7 +69370,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69393,7 +69393,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69416,7 +69416,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69439,7 +69439,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69462,7 +69462,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -69485,7 +69485,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69506,7 +69506,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
 #[cfg_attr(
@@ -69528,7 +69528,7 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
 #[cfg_attr(
@@ -69550,7 +69550,7 @@ pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
@@ -69571,7 +69571,7 @@ pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
@@ -69592,7 +69592,7 @@ pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -69613,7 +69613,7 @@ pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -69634,7 +69634,7 @@ pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -69655,7 +69655,7 @@ pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -69676,7 +69676,7 @@ pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -69697,7 +69697,7 @@ pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -69718,7 +69718,7 @@ pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -69739,7 +69739,7 @@ pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -69760,7 +69760,7 @@ pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -69781,7 +69781,7 @@ pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -69802,7 +69802,7 @@ pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -69823,7 +69823,7 @@ pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -69844,7 +69844,7 @@ pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -69865,7 +69865,7 @@ pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -69886,7 +69886,7 @@ pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -69907,7 +69907,7 @@ pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -69928,7 +69928,7 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -69950,7 +69950,7 @@ pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -69972,7 +69972,7 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -69994,7 +69994,7 @@ pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70016,7 +70016,7 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70038,7 +70038,7 @@ pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70060,7 +70060,7 @@ pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70082,7 +70082,7 @@ pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70104,7 +70104,7 @@ pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70126,7 +70126,7 @@ pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70148,7 +70148,7 @@ pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70170,7 +70170,7 @@ pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -70192,7 +70192,7 @@ pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -70217,7 +70217,7 @@ pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -70242,7 +70242,7 @@ pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -70267,7 +70267,7 @@ pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -70292,7 +70292,7 @@ pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -70317,7 +70317,7 @@ pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -70342,7 +70342,7 @@ pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -70363,7 +70363,7 @@ pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -70384,7 +70384,7 @@ pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -70405,7 +70405,7 @@ pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -70426,7 +70426,7 @@ pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -70447,7 +70447,7 @@ pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -70468,7 +70468,7 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -70496,7 +70496,7 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -70528,7 +70528,7 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -70557,7 +70557,7 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -70591,7 +70591,7 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
@@ -70611,7 +70611,7 @@ pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
@@ -70632,7 +70632,7 @@ pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x1
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70647,7 +70647,7 @@ fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70658,7 +70658,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70670,7 +70670,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70687,7 +70687,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70699,7 +70699,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70716,7 +70716,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70731,7 +70731,7 @@ fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70742,7 +70742,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70754,7 +70754,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70773,7 +70773,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70785,7 +70785,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70804,7 +70804,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70819,7 +70819,7 @@ fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70830,7 +70830,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70849,7 +70849,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70874,7 +70874,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70893,7 +70893,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70918,7 +70918,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70933,7 +70933,7 @@ fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70944,7 +70944,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70964,7 +70964,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70991,7 +70991,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71011,7 +71011,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71038,7 +71038,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71052,7 +71052,7 @@ fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71062,7 +71062,7 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71073,7 +71073,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71090,7 +71090,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71101,7 +71101,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71118,7 +71118,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71132,7 +71132,7 @@ fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71142,7 +71142,7 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71160,7 +71160,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71184,7 +71184,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71202,7 +71202,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71226,7 +71226,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71240,7 +71240,7 @@ fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71250,7 +71250,7 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71269,7 +71269,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71295,7 +71295,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71314,7 +71314,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71340,7 +71340,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71361,7 +71361,7 @@ fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71381,7 +71381,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71409,7 +71409,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71429,7 +71429,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71457,7 +71457,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71477,7 +71477,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -71505,7 +71505,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
@@ -71535,7 +71535,7 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
@@ -71565,7 +71565,7 @@ pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71594,7 +71594,7 @@ pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71623,7 +71623,7 @@ pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71652,7 +71652,7 @@ pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71681,7 +71681,7 @@ pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71710,7 +71710,7 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71747,7 +71747,7 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71776,7 +71776,7 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71805,7 +71805,7 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71834,7 +71834,7 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71863,7 +71863,7 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71900,7 +71900,7 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71929,7 +71929,7 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71958,7 +71958,7 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -71987,7 +71987,7 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72016,7 +72016,7 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72053,7 +72053,7 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72082,7 +72082,7 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72111,7 +72111,7 @@ pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72136,7 +72136,7 @@ pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72161,7 +72161,7 @@ pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72186,7 +72186,7 @@ pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72211,7 +72211,7 @@ pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72236,7 +72236,7 @@ pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72261,7 +72261,7 @@ pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72286,7 +72286,7 @@ pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72311,7 +72311,7 @@ pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72336,7 +72336,7 @@ pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72361,7 +72361,7 @@ pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72386,7 +72386,7 @@ pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72411,7 +72411,7 @@ pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72436,7 +72436,7 @@ pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72461,7 +72461,7 @@ pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72486,7 +72486,7 @@ pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -72511,7 +72511,7 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -72539,7 +72539,7 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -72571,7 +72571,7 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -72600,7 +72600,7 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -72634,7 +72634,7 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
@@ -72655,7 +72655,7 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
@@ -72681,7 +72681,7 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
@@ -72703,7 +72703,7 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline(always)]
+#[inline]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
@@ -72731,7 +72731,7 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
@@ -72760,7 +72760,7 @@ pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
@@ -72789,7 +72789,7 @@ pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -72818,7 +72818,7 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
@@ -72848,7 +72848,7 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
@@ -72878,7 +72878,7 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72907,7 +72907,7 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72936,7 +72936,7 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -72965,7 +72965,7 @@ pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -72994,7 +72994,7 @@ pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73023,7 +73023,7 @@ pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73060,7 +73060,7 @@ pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73089,7 +73089,7 @@ pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73118,7 +73118,7 @@ pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73147,7 +73147,7 @@ pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73176,7 +73176,7 @@ pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73213,7 +73213,7 @@ pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73242,7 +73242,7 @@ pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73271,7 +73271,7 @@ pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73300,7 +73300,7 @@ pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73329,7 +73329,7 @@ pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73366,7 +73366,7 @@ pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73395,7 +73395,7 @@ pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -73424,7 +73424,7 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
@@ -73454,7 +73454,7 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
@@ -73484,7 +73484,7 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -73513,7 +73513,7 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -73542,7 +73542,7 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -73571,7 +73571,7 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -73600,7 +73600,7 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -73629,7 +73629,7 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -73658,7 +73658,7 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -73687,7 +73687,7 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -73716,7 +73716,7 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -73745,7 +73745,7 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73774,7 +73774,7 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73811,7 +73811,7 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73840,7 +73840,7 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73869,7 +73869,7 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73906,7 +73906,7 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73935,7 +73935,7 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -73964,7 +73964,7 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -74001,7 +74001,7 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index ab80b499b0..dc467fd307 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1741,7 +1741,7 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok
         );
     }
 
-    tokens.append_all(quote! { #[inline(always)] });
+    tokens.append_all(quote! { #[inline] });
 
     match endianness {
         Endianness::Little => tokens.append_all(quote! { #[cfg(target_endian = "little")] }),

From e78a84618422efc3cd039729f3d601590daa9fb1 Mon Sep 17 00:00:00 2001
From: James Barford-Evans <james.barford-evans@arm.com>
Date: Wed, 6 May 2026 16:28:26 +0100
Subject: [PATCH 273/326] Remove #[inline(always)] from hexagon intrinsic
 generator & re-generate intrinsics

---
 crates/core_arch/src/hexagon/v128.rs   | 952 ++++++++++++-------------
 crates/core_arch/src/hexagon/v64.rs    | 952 ++++++++++++-------------
 crates/stdarch-gen-hexagon/src/main.rs |   4 +-
 3 files changed, 954 insertions(+), 954 deletions(-)

diff --git a/crates/core_arch/src/hexagon/v128.rs b/crates/core_arch/src/hexagon/v128.rs
index 1026338293..1f0566af78 100644
--- a/crates/core_arch/src/hexagon/v128.rs
+++ b/crates/core_arch/src/hexagon/v128.rs
@@ -1043,7 +1043,7 @@ unsafe extern "unadjusted" {
 ///
 /// Instruction Type: LD
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(extractw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1055,7 +1055,7 @@ pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(hi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1067,7 +1067,7 @@ pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lo))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1079,7 +1079,7 @@ pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lvsplatw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1091,7 +1091,7 @@ pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1103,7 +1103,7 @@ pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1115,7 +1115,7 @@ pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1127,7 +1127,7 @@ pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1139,7 +1139,7 @@ pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1151,7 +1151,7 @@ pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1163,7 +1163,7 @@ pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1175,7 +1175,7 @@ pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1187,7 +1187,7 @@ pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1199,7 +1199,7 @@ pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1211,7 +1211,7 @@ pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1223,7 +1223,7 @@ pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1235,7 +1235,7 @@ pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1247,7 +1247,7 @@ pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1259,7 +1259,7 @@ pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1271,7 +1271,7 @@ pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1283,7 +1283,7 @@ pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1295,7 +1295,7 @@ pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1307,7 +1307,7 @@ pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1319,7 +1319,7 @@ pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1331,7 +1331,7 @@ pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1343,7 +1343,7 @@ pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1355,7 +1355,7 @@ pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1367,7 +1367,7 @@ pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1379,7 +1379,7 @@ pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1391,7 +1391,7 @@ pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1403,7 +1403,7 @@ pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1415,7 +1415,7 @@ pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vand))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1427,7 +1427,7 @@ pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1439,7 +1439,7 @@ pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1451,7 +1451,7 @@ pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1463,7 +1463,7 @@ pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1475,7 +1475,7 @@ pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1487,7 +1487,7 @@ pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1499,7 +1499,7 @@ pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhbrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1511,7 +1511,7 @@ pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1523,7 +1523,7 @@ pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1535,7 +1535,7 @@ pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1547,7 +1547,7 @@ pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1559,7 +1559,7 @@ pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1571,7 +1571,7 @@ pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1583,7 +1583,7 @@ pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1595,7 +1595,7 @@ pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1607,7 +1607,7 @@ pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1619,7 +1619,7 @@ pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1631,7 +1631,7 @@ pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassign))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1643,7 +1643,7 @@ pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassignp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1655,7 +1655,7 @@ pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1667,7 +1667,7 @@ pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavghrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1679,7 +1679,7 @@ pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1691,7 +1691,7 @@ pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgubrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1703,7 +1703,7 @@ pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1715,7 +1715,7 @@ pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguhrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1727,7 +1727,7 @@ pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1739,7 +1739,7 @@ pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1751,7 +1751,7 @@ pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1763,7 +1763,7 @@ pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1775,7 +1775,7 @@ pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcombine))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1787,7 +1787,7 @@ pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1799,7 +1799,7 @@ pub unsafe fn Q6_V_vzero() -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1811,7 +1811,7 @@ pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb4w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1823,7 +1823,7 @@ pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1835,7 +1835,7 @@ pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1847,7 +1847,7 @@ pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1859,7 +1859,7 @@ pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1871,7 +1871,7 @@ pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1883,7 +1883,7 @@ pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1895,7 +1895,7 @@ pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1911,7 +1911,7 @@ pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1923,7 +1923,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1935,7 +1935,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1947,7 +1947,7 @@ pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1963,7 +1963,7 @@ pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1975,7 +1975,7 @@ pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1987,7 +1987,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1999,7 +1999,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2011,7 +2011,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2023,7 +2023,7 @@ pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2035,7 +2035,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt:
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2047,7 +2047,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2059,7 +2059,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2071,7 +2071,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2083,7 +2083,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2095,7 +2095,7 @@ pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2111,7 +2111,7 @@ pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh(
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vinsertwr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2123,7 +2123,7 @@ pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2135,7 +2135,7 @@ pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2147,7 +2147,7 @@ pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2159,7 +2159,7 @@ pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2171,7 +2171,7 @@ pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2183,7 +2183,7 @@ pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2195,7 +2195,7 @@ pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2207,7 +2207,7 @@ pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2224,7 +2224,7 @@ pub unsafe fn Q6_Vb_vlut32or_VbVbVbR(
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2236,7 +2236,7 @@ pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2253,7 +2253,7 @@ pub unsafe fn Q6_Wh_vlut16or_WhVbVhR(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2265,7 +2265,7 @@ pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2277,7 +2277,7 @@ pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2289,7 +2289,7 @@ pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2301,7 +2301,7 @@ pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2313,7 +2313,7 @@ pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2325,7 +2325,7 @@ pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2337,7 +2337,7 @@ pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2349,7 +2349,7 @@ pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2361,7 +2361,7 @@ pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2377,7 +2377,7 @@ pub unsafe fn Q6_Wh_vmpaacc_WhWubRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2389,7 +2389,7 @@ pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabuuv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2401,7 +2401,7 @@ pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2413,7 +2413,7 @@ pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2429,7 +2429,7 @@ pub unsafe fn Q6_Ww_vmpaacc_WwWhRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2441,7 +2441,7 @@ pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2453,7 +2453,7 @@ pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2465,7 +2465,7 @@ pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2481,7 +2481,7 @@ pub unsafe fn Q6_Wh_vmpyacc_WhVubVb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2493,7 +2493,7 @@ pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2509,7 +2509,7 @@ pub unsafe fn Q6_Wh_vmpyacc_WhVbVb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2521,7 +2521,7 @@ pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2533,7 +2533,7 @@ pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2549,7 +2549,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2561,7 +2561,7 @@ pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhss))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2573,7 +2573,7 @@ pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2585,7 +2585,7 @@ pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2601,7 +2601,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2613,7 +2613,7 @@ pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2629,7 +2629,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhVh(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhvsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2641,7 +2641,7 @@ pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyieoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2653,7 +2653,7 @@ pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2665,7 +2665,7 @@ pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2677,7 +2677,7 @@ pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2689,7 +2689,7 @@ pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2701,7 +2701,7 @@ pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2713,7 +2713,7 @@ pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2725,7 +2725,7 @@ pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2737,7 +2737,7 @@ pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2749,7 +2749,7 @@ pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2761,7 +2761,7 @@ pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2773,7 +2773,7 @@ pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2785,7 +2785,7 @@ pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2797,7 +2797,7 @@ pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2809,7 +2809,7 @@ pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2821,7 +2821,7 @@ pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2837,7 +2837,7 @@ pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2853,7 +2853,7 @@ pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2865,7 +2865,7 @@ pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2881,7 +2881,7 @@ pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2893,7 +2893,7 @@ pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2909,7 +2909,7 @@ pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2921,7 +2921,7 @@ pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2937,7 +2937,7 @@ pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2949,7 +2949,7 @@ pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2965,7 +2965,7 @@ pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2977,7 +2977,7 @@ pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2989,7 +2989,7 @@ pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3001,7 +3001,7 @@ pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3013,7 +3013,7 @@ pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamtw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3025,7 +3025,7 @@ pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnot))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3037,7 +3037,7 @@ pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3049,7 +3049,7 @@ pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3061,7 +3061,7 @@ pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3073,7 +3073,7 @@ pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3085,7 +3085,7 @@ pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhub_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3097,7 +3097,7 @@ pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3109,7 +3109,7 @@ pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3121,7 +3121,7 @@ pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3133,7 +3133,7 @@ pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwuh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3145,7 +3145,7 @@ pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpopcounth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3157,7 +3157,7 @@ pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3169,7 +3169,7 @@ pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3181,7 +3181,7 @@ pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3193,7 +3193,7 @@ pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3205,7 +3205,7 @@ pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3222,7 +3222,7 @@ pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3234,7 +3234,7 @@ pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3246,7 +3246,7 @@ pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3258,7 +3258,7 @@ pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3270,7 +3270,7 @@ pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3282,7 +3282,7 @@ pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3294,7 +3294,7 @@ pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3306,7 +3306,7 @@ pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3323,7 +3323,7 @@ pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3335,7 +3335,7 @@ pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3347,7 +3347,7 @@ pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVec
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vror))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3359,7 +3359,7 @@ pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3371,7 +3371,7 @@ pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3383,7 +3383,7 @@ pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3395,7 +3395,7 @@ pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3407,7 +3407,7 @@ pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3419,7 +3419,7 @@ pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3436,7 +3436,7 @@ pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsathub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3448,7 +3448,7 @@ pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsatwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3460,7 +3460,7 @@ pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3472,7 +3472,7 @@ pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3484,7 +3484,7 @@ pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3496,7 +3496,7 @@ pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3508,7 +3508,7 @@ pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3520,7 +3520,7 @@ pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3532,7 +3532,7 @@ pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3544,7 +3544,7 @@ pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3556,7 +3556,7 @@ pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3568,7 +3568,7 @@ pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3580,7 +3580,7 @@ pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3592,7 +3592,7 @@ pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3604,7 +3604,7 @@ pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3616,7 +3616,7 @@ pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3628,7 +3628,7 @@ pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3640,7 +3640,7 @@ pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3652,7 +3652,7 @@ pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3664,7 +3664,7 @@ pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3676,7 +3676,7 @@ pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3688,7 +3688,7 @@ pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3700,7 +3700,7 @@ pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3712,7 +3712,7 @@ pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3724,7 +3724,7 @@ pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3736,7 +3736,7 @@ pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3748,7 +3748,7 @@ pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3760,7 +3760,7 @@ pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3772,7 +3772,7 @@ pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3784,7 +3784,7 @@ pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3796,7 +3796,7 @@ pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3808,7 +3808,7 @@ pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3824,7 +3824,7 @@ pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3836,7 +3836,7 @@ pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3852,7 +3852,7 @@ pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3864,7 +3864,7 @@ pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3880,7 +3880,7 @@ pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb(
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3892,7 +3892,7 @@ pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3904,7 +3904,7 @@ pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3916,7 +3916,7 @@ pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3928,7 +3928,7 @@ pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3940,7 +3940,7 @@ pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3952,7 +3952,7 @@ pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vxor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3964,7 +3964,7 @@ pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3976,7 +3976,7 @@ pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3988,7 +3988,7 @@ pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplatb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4000,7 +4000,7 @@ pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplath))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4012,7 +4012,7 @@ pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4024,7 +4024,7 @@ pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4036,7 +4036,7 @@ pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4048,7 +4048,7 @@ pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4060,7 +4060,7 @@ pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4076,7 +4076,7 @@ pub unsafe fn Q6_Ww_vaddacc_WwVhVh(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddubh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4092,7 +4092,7 @@ pub unsafe fn Q6_Wh_vaddacc_WhVubVub(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4104,7 +4104,7 @@ pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4120,7 +4120,7 @@ pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4132,7 +4132,7 @@ pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4144,7 +4144,7 @@ pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrhbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4156,7 +4156,7 @@ pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasruwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4168,7 +4168,7 @@ pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4180,7 +4180,7 @@ pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlsrb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4192,7 +4192,7 @@ pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4204,7 +4204,7 @@ pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4221,7 +4221,7 @@ pub unsafe fn Q6_Vb_vlut32or_VbVbVbI(
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4233,7 +4233,7 @@ pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4245,7 +4245,7 @@ pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4262,7 +4262,7 @@ pub unsafe fn Q6_Wh_vlut16or_WhVbVhI(
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwhi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4274,7 +4274,7 @@ pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmaxb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4286,7 +4286,7 @@ pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vminb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4298,7 +4298,7 @@ pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4310,7 +4310,7 @@ pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4326,7 +4326,7 @@ pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyewuh_64))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4338,7 +4338,7 @@ pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4350,7 +4350,7 @@ pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4362,7 +4362,7 @@ pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4378,7 +4378,7 @@ pub unsafe fn Q6_W_vmpyoacc_WVwVh(
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4390,7 +4390,7 @@ pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4402,7 +4402,7 @@ pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsatuwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4414,7 +4414,7 @@ pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4426,7 +4426,7 @@ pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4438,7 +4438,7 @@ pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4450,7 +4450,7 @@ pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4462,7 +4462,7 @@ pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4474,7 +4474,7 @@ pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4486,7 +4486,7 @@ pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4498,7 +4498,7 @@ pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vaslh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4510,7 +4510,7 @@ pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasrh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4522,7 +4522,7 @@ pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4534,7 +4534,7 @@ pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4546,7 +4546,7 @@ pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4558,7 +4558,7 @@ pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4570,7 +4570,7 @@ pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgbrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4582,7 +4582,7 @@ pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4594,7 +4594,7 @@ pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4606,7 +4606,7 @@ pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: MAPPING
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vdd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4618,7 +4618,7 @@ pub unsafe fn Q6_W_vzero() -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4630,7 +4630,7 @@ pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 ///
 /// Instruction Type: CVI_GATHER_DV
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4642,7 +4642,7 @@ pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec
 ///
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4654,7 +4654,7 @@ pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4666,7 +4666,7 @@ pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4682,7 +4682,7 @@ pub unsafe fn Q6_Wh_vmpaacc_WhWubRub(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4694,7 +4694,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4706,7 +4706,7 @@ pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4718,7 +4718,7 @@ pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vnavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4730,7 +4730,7 @@ pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4742,7 +4742,7 @@ pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4754,7 +4754,7 @@ pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 ///
 /// Instruction Type: CVI_SCATTER_DV
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4766,7 +4766,7 @@ pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec
 ///
 /// Instruction Type: CVI_SCATTER_DV
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4778,7 +4778,7 @@ pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4790,7 +4790,7 @@ pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4802,7 +4802,7 @@ pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vasr_into))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4818,7 +4818,7 @@ pub unsafe fn Q6_Ww_vasrinto_WwVwVw(
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vrotr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4830,7 +4830,7 @@ pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vsatdw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4842,7 +4842,7 @@ pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4858,7 +4858,7 @@ pub unsafe fn Q6_Ww_v6mpy_WubWbI_h(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4875,7 +4875,7 @@ pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4891,7 +4891,7 @@ pub unsafe fn Q6_Ww_v6mpy_WubWbI_v(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4908,7 +4908,7 @@ pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v(
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4920,7 +4920,7 @@ pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4932,7 +4932,7 @@ pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4944,7 +4944,7 @@ pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4956,7 +4956,7 @@ pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4968,7 +4968,7 @@ pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4980,7 +4980,7 @@ pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4992,7 +4992,7 @@ pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5004,7 +5004,7 @@ pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5016,7 +5016,7 @@ pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5028,7 +5028,7 @@ pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5040,7 +5040,7 @@ pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vassign_fp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5052,7 +5052,7 @@ pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5064,7 +5064,7 @@ pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5076,7 +5076,7 @@ pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_sf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5088,7 +5088,7 @@ pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_b_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5100,7 +5100,7 @@ pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5112,7 +5112,7 @@ pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5124,7 +5124,7 @@ pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5136,7 +5136,7 @@ pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5148,7 +5148,7 @@ pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5160,7 +5160,7 @@ pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_uh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5172,7 +5172,7 @@ pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5184,7 +5184,7 @@ pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_ub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5196,7 +5196,7 @@ pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_uh_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5208,7 +5208,7 @@ pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5220,7 +5220,7 @@ pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5232,7 +5232,7 @@ pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVec
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5244,7 +5244,7 @@ pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5256,7 +5256,7 @@ pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5268,7 +5268,7 @@ pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5280,7 +5280,7 @@ pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5292,7 +5292,7 @@ pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5304,7 +5304,7 @@ pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5316,7 +5316,7 @@ pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5328,7 +5328,7 @@ pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5340,7 +5340,7 @@ pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5352,7 +5352,7 @@ pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5364,7 +5364,7 @@ pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5376,7 +5376,7 @@ pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVect
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5388,7 +5388,7 @@ pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5400,7 +5400,7 @@ pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5412,7 +5412,7 @@ pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5424,7 +5424,7 @@ pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5436,7 +5436,7 @@ pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5448,7 +5448,7 @@ pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5460,7 +5460,7 @@ pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5472,7 +5472,7 @@ pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5484,7 +5484,7 @@ pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5500,7 +5500,7 @@ pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5512,7 +5512,7 @@ pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5524,7 +5524,7 @@ pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5536,7 +5536,7 @@ pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5548,7 +5548,7 @@ pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5560,7 +5560,7 @@ pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5572,7 +5572,7 @@ pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5584,7 +5584,7 @@ pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5596,7 +5596,7 @@ pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5608,7 +5608,7 @@ pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5620,7 +5620,7 @@ pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5632,7 +5632,7 @@ pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5644,7 +5644,7 @@ pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5656,7 +5656,7 @@ pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5668,7 +5668,7 @@ pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vmpyuhvs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5680,7 +5680,7 @@ pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5692,7 +5692,7 @@ pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5704,7 +5704,7 @@ pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_sf_w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5716,7 +5716,7 @@ pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_w_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5728,7 +5728,7 @@ pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(get_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5740,7 +5740,7 @@ pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(set_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5752,7 +5752,7 @@ pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vabs_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5764,7 +5764,7 @@ pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5776,7 +5776,7 @@ pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5788,7 +5788,7 @@ pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5800,7 +5800,7 @@ pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmax_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5812,7 +5812,7 @@ pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmin_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5824,7 +5824,7 @@ pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfneg_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5837,7 +5837,7 @@ pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5855,7 +5855,7 @@ pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5873,7 +5873,7 @@ pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
@@ -5891,7 +5891,7 @@ pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5909,7 +5909,7 @@ pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5927,7 +5927,7 @@ pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
@@ -5939,7 +5939,7 @@ pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5957,7 +5957,7 @@ pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -5973,7 +5973,7 @@ pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -5989,7 +5989,7 @@ pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -6005,7 +6005,7 @@ pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -6021,7 +6021,7 @@ pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector)
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6037,7 +6037,7 @@ pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6053,7 +6053,7 @@ pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6069,7 +6069,7 @@ pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6085,7 +6085,7 @@ pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6101,7 +6101,7 @@ pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6117,7 +6117,7 @@ pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -6129,7 +6129,7 @@ pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -6141,7 +6141,7 @@ pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
@@ -6153,7 +6153,7 @@ pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
@@ -6169,7 +6169,7 @@ pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6181,7 +6181,7 @@ pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
@@ -6204,7 +6204,7 @@ pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
@@ -6227,7 +6227,7 @@ pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
@@ -6250,7 +6250,7 @@ pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6262,7 +6262,7 @@ pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
@@ -6285,7 +6285,7 @@ pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
@@ -6308,7 +6308,7 @@ pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
@@ -6331,7 +6331,7 @@ pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6343,7 +6343,7 @@ pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
@@ -6366,7 +6366,7 @@ pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
@@ -6389,7 +6389,7 @@ pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
@@ -6412,7 +6412,7 @@ pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6424,7 +6424,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
@@ -6447,7 +6447,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
@@ -6470,7 +6470,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
@@ -6493,7 +6493,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6505,7 +6505,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
@@ -6528,7 +6528,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
@@ -6551,7 +6551,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
@@ -6574,7 +6574,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6586,7 +6586,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
@@ -6609,7 +6609,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
@@ -6632,7 +6632,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
@@ -6655,7 +6655,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6667,7 +6667,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
@@ -6690,7 +6690,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
@@ -6713,7 +6713,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
@@ -6736,7 +6736,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6748,7 +6748,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
@@ -6771,7 +6771,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
@@ -6794,7 +6794,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
@@ -6817,7 +6817,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6829,7 +6829,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
@@ -6852,7 +6852,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
@@ -6875,7 +6875,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
@@ -6898,7 +6898,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
@@ -6914,7 +6914,7 @@ pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6930,7 +6930,7 @@ pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6946,7 +6946,7 @@ pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6962,7 +6962,7 @@ pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6978,7 +6978,7 @@ pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6994,7 +6994,7 @@ pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -7010,7 +7010,7 @@ pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
@@ -7026,7 +7026,7 @@ pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
@@ -7038,7 +7038,7 @@ pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -7056,7 +7056,7 @@ pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -7074,7 +7074,7 @@ pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -7089,7 +7089,7 @@ pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -7105,7 +7105,7 @@ pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
@@ -7120,7 +7120,7 @@ pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
@@ -7135,7 +7135,7 @@ pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vgather_AQRMVh(
@@ -7159,7 +7159,7 @@ pub unsafe fn Q6_vgather_AQRMVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_GATHER_DV
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vgather_AQRMWw(
@@ -7183,7 +7183,7 @@ pub unsafe fn Q6_vgather_AQRMWw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vgather_AQRMVw(
@@ -7207,7 +7207,7 @@ pub unsafe fn Q6_vgather_AQRMVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
@@ -7222,7 +7222,7 @@ pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
@@ -7237,7 +7237,7 @@ pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
@@ -7252,7 +7252,7 @@ pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vscatter_QRMVhV(
@@ -7276,7 +7276,7 @@ pub unsafe fn Q6_vscatter_QRMVhV(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_SCATTER_DV
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vscatter_QRMWwV(
@@ -7300,7 +7300,7 @@ pub unsafe fn Q6_vscatter_QRMWwV(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vscatter_QRMVwV(
@@ -7324,7 +7324,7 @@ pub unsafe fn Q6_vscatter_QRMVwV(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
@@ -7344,7 +7344,7 @@ pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -7356,7 +7356,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
@@ -7379,7 +7379,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
@@ -7402,7 +7402,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
@@ -7425,7 +7425,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -7437,7 +7437,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
@@ -7460,7 +7460,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
@@ -7483,7 +7483,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf(
diff --git a/crates/core_arch/src/hexagon/v64.rs b/crates/core_arch/src/hexagon/v64.rs
index 517a807db4..e9b18b2fd8 100644
--- a/crates/core_arch/src/hexagon/v64.rs
+++ b/crates/core_arch/src/hexagon/v64.rs
@@ -1043,7 +1043,7 @@ unsafe extern "unadjusted" {
 ///
 /// Instruction Type: LD
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(extractw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1055,7 +1055,7 @@ pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(hi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1067,7 +1067,7 @@ pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lo))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1079,7 +1079,7 @@ pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(lvsplatw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1091,7 +1091,7 @@ pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1103,7 +1103,7 @@ pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1115,7 +1115,7 @@ pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1127,7 +1127,7 @@ pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsdiffw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1139,7 +1139,7 @@ pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1151,7 +1151,7 @@ pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1163,7 +1163,7 @@ pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1175,7 +1175,7 @@ pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vabsw_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1187,7 +1187,7 @@ pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1199,7 +1199,7 @@ pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1211,7 +1211,7 @@ pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1223,7 +1223,7 @@ pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1235,7 +1235,7 @@ pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1247,7 +1247,7 @@ pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1259,7 +1259,7 @@ pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1271,7 +1271,7 @@ pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1283,7 +1283,7 @@ pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1295,7 +1295,7 @@ pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddubsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1307,7 +1307,7 @@ pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1319,7 +1319,7 @@ pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1331,7 +1331,7 @@ pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vadduhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1343,7 +1343,7 @@ pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1355,7 +1355,7 @@ pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1367,7 +1367,7 @@ pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1379,7 +1379,7 @@ pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaddwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1391,7 +1391,7 @@ pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1403,7 +1403,7 @@ pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(valignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1415,7 +1415,7 @@ pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vand))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1427,7 +1427,7 @@ pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1439,7 +1439,7 @@ pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1451,7 +1451,7 @@ pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1463,7 +1463,7 @@ pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1475,7 +1475,7 @@ pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vaslwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1487,7 +1487,7 @@ pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1499,7 +1499,7 @@ pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhbrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1511,7 +1511,7 @@ pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1523,7 +1523,7 @@ pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1535,7 +1535,7 @@ pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1547,7 +1547,7 @@ pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1559,7 +1559,7 @@ pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1571,7 +1571,7 @@ pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1583,7 +1583,7 @@ pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1595,7 +1595,7 @@ pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1607,7 +1607,7 @@ pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1619,7 +1619,7 @@ pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vasrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1631,7 +1631,7 @@ pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassign))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1643,7 +1643,7 @@ pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vassignp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1655,7 +1655,7 @@ pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1667,7 +1667,7 @@ pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavghrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1679,7 +1679,7 @@ pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1691,7 +1691,7 @@ pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgubrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1703,7 +1703,7 @@ pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1715,7 +1715,7 @@ pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavguhrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1727,7 +1727,7 @@ pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1739,7 +1739,7 @@ pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vavgwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1751,7 +1751,7 @@ pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1763,7 +1763,7 @@ pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcl0w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1775,7 +1775,7 @@ pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vcombine))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1787,7 +1787,7 @@ pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1799,7 +1799,7 @@ pub unsafe fn Q6_V_vzero() -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1811,7 +1811,7 @@ pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealb4w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1823,7 +1823,7 @@ pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1835,7 +1835,7 @@ pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdealvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1847,7 +1847,7 @@ pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1859,7 +1859,7 @@ pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1871,7 +1871,7 @@ pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1883,7 +1883,7 @@ pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1895,7 +1895,7 @@ pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1911,7 +1911,7 @@ pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1923,7 +1923,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1935,7 +1935,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1947,7 +1947,7 @@ pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1963,7 +1963,7 @@ pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1975,7 +1975,7 @@ pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1987,7 +1987,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -1999,7 +1999,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2011,7 +2011,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2023,7 +2023,7 @@ pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2035,7 +2035,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt:
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2047,7 +2047,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2059,7 +2059,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2071,7 +2071,7 @@ pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2083,7 +2083,7 @@ pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2095,7 +2095,7 @@ pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vdsaduh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2111,7 +2111,7 @@ pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh(
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vinsertwr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2123,7 +2123,7 @@ pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2135,7 +2135,7 @@ pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlalignbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2147,7 +2147,7 @@ pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2159,7 +2159,7 @@ pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2171,7 +2171,7 @@ pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2183,7 +2183,7 @@ pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlsrwv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2195,7 +2195,7 @@ pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2207,7 +2207,7 @@ pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2224,7 +2224,7 @@ pub unsafe fn Q6_Vb_vlut32or_VbVbVbR(
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2236,7 +2236,7 @@ pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2253,7 +2253,7 @@ pub unsafe fn Q6_Wh_vlut16or_WhVbVhR(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2265,7 +2265,7 @@ pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2277,7 +2277,7 @@ pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2289,7 +2289,7 @@ pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmaxw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2301,7 +2301,7 @@ pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2313,7 +2313,7 @@ pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2325,7 +2325,7 @@ pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2337,7 +2337,7 @@ pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vminw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2349,7 +2349,7 @@ pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2361,7 +2361,7 @@ pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2377,7 +2377,7 @@ pub unsafe fn Q6_Wh_vmpaacc_WhWubRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2389,7 +2389,7 @@ pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpabuuv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2401,7 +2401,7 @@ pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2413,7 +2413,7 @@ pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpahb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2429,7 +2429,7 @@ pub unsafe fn Q6_Ww_vmpaacc_WwWhRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2441,7 +2441,7 @@ pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2453,7 +2453,7 @@ pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2465,7 +2465,7 @@ pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2481,7 +2481,7 @@ pub unsafe fn Q6_Wh_vmpyacc_WhVubVb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2493,7 +2493,7 @@ pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2509,7 +2509,7 @@ pub unsafe fn Q6_Wh_vmpyacc_WhVbVb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2521,7 +2521,7 @@ pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2533,7 +2533,7 @@ pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsat_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2549,7 +2549,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2561,7 +2561,7 @@ pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhss))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2573,7 +2573,7 @@ pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2585,7 +2585,7 @@ pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2601,7 +2601,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2613,7 +2613,7 @@ pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2629,7 +2629,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhVh(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyhvsrs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2641,7 +2641,7 @@ pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyieoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2653,7 +2653,7 @@ pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2665,7 +2665,7 @@ pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2677,7 +2677,7 @@ pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiewuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2689,7 +2689,7 @@ pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2701,7 +2701,7 @@ pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyih_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2713,7 +2713,7 @@ pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2725,7 +2725,7 @@ pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyihb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2737,7 +2737,7 @@ pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2749,7 +2749,7 @@ pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2761,7 +2761,7 @@ pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2773,7 +2773,7 @@ pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2785,7 +2785,7 @@ pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyiwh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2797,7 +2797,7 @@ pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2809,7 +2809,7 @@ pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2821,7 +2821,7 @@ pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2837,7 +2837,7 @@ pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyowh_sacc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2853,7 +2853,7 @@ pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2865,7 +2865,7 @@ pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2881,7 +2881,7 @@ pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2893,7 +2893,7 @@ pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2909,7 +2909,7 @@ pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2921,7 +2921,7 @@ pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2937,7 +2937,7 @@ pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2949,7 +2949,7 @@ pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vmpyuhv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2965,7 +2965,7 @@ pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2977,7 +2977,7 @@ pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -2989,7 +2989,7 @@ pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnavgw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3001,7 +3001,7 @@ pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3013,7 +3013,7 @@ pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnormamtw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3025,7 +3025,7 @@ pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vnot))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3037,7 +3037,7 @@ pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3049,7 +3049,7 @@ pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3061,7 +3061,7 @@ pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3073,7 +3073,7 @@ pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3085,7 +3085,7 @@ pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackhub_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3097,7 +3097,7 @@ pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3109,7 +3109,7 @@ pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3121,7 +3121,7 @@ pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3133,7 +3133,7 @@ pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpackwuh_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3145,7 +3145,7 @@ pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vpopcounth))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3157,7 +3157,7 @@ pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrdelta))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3169,7 +3169,7 @@ pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3181,7 +3181,7 @@ pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3193,7 +3193,7 @@ pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3205,7 +3205,7 @@ pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3222,7 +3222,7 @@ pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3234,7 +3234,7 @@ pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybusv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3246,7 +3246,7 @@ pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3258,7 +3258,7 @@ pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpybv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3270,7 +3270,7 @@ pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector)
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3282,7 +3282,7 @@ pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3294,7 +3294,7 @@ pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3306,7 +3306,7 @@ pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3323,7 +3323,7 @@ pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI(
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3335,7 +3335,7 @@ pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrmpyubv_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3347,7 +3347,7 @@ pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVec
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vror))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3359,7 +3359,7 @@ pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3371,7 +3371,7 @@ pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3383,7 +3383,7 @@ pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3395,7 +3395,7 @@ pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vroundwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3407,7 +3407,7 @@ pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3419,7 +3419,7 @@ pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vrsadubi_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3436,7 +3436,7 @@ pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsathub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3448,7 +3448,7 @@ pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsatwh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3460,7 +3460,7 @@ pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3472,7 +3472,7 @@ pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3484,7 +3484,7 @@ pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3496,7 +3496,7 @@ pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3508,7 +3508,7 @@ pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3520,7 +3520,7 @@ pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3532,7 +3532,7 @@ pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3544,7 +3544,7 @@ pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshuffvdd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3556,7 +3556,7 @@ pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3568,7 +3568,7 @@ pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoeh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3580,7 +3580,7 @@ pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vshufoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3592,7 +3592,7 @@ pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3604,7 +3604,7 @@ pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubb_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3616,7 +3616,7 @@ pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3628,7 +3628,7 @@ pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubh_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3640,7 +3640,7 @@ pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3652,7 +3652,7 @@ pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3664,7 +3664,7 @@ pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3676,7 +3676,7 @@ pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3688,7 +3688,7 @@ pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3700,7 +3700,7 @@ pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsububsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3712,7 +3712,7 @@ pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3724,7 +3724,7 @@ pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3736,7 +3736,7 @@ pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubuhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3748,7 +3748,7 @@ pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3760,7 +3760,7 @@ pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubw_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3772,7 +3772,7 @@ pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3784,7 +3784,7 @@ pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vsubwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3796,7 +3796,7 @@ pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3808,7 +3808,7 @@ pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3824,7 +3824,7 @@ pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3836,7 +3836,7 @@ pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpybus_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3852,7 +3852,7 @@ pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3864,7 +3864,7 @@ pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vtmpyhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3880,7 +3880,7 @@ pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb(
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3892,7 +3892,7 @@ pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3904,7 +3904,7 @@ pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackob))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3916,7 +3916,7 @@ pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackoh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3928,7 +3928,7 @@ pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3940,7 +3940,7 @@ pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vunpackuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3952,7 +3952,7 @@ pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vxor))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3964,7 +3964,7 @@ pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3976,7 +3976,7 @@ pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[cfg_attr(test, assert_instr(vzh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -3988,7 +3988,7 @@ pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplatb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4000,7 +4000,7 @@ pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(lvsplath))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4012,7 +4012,7 @@ pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4024,7 +4024,7 @@ pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4036,7 +4036,7 @@ pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4048,7 +4048,7 @@ pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddclbw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4060,7 +4060,7 @@ pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4076,7 +4076,7 @@ pub unsafe fn Q6_Ww_vaddacc_WwVhVh(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddubh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4092,7 +4092,7 @@ pub unsafe fn Q6_Wh_vaddacc_WhVubVub(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vaddububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4104,7 +4104,7 @@ pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduhw_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4120,7 +4120,7 @@ pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh(
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4132,7 +4132,7 @@ pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vadduwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4144,7 +4144,7 @@ pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrhbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4156,7 +4156,7 @@ pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasruwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4168,7 +4168,7 @@ pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vasrwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4180,7 +4180,7 @@ pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlsrb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4192,7 +4192,7 @@ pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4204,7 +4204,7 @@ pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvb_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4221,7 +4221,7 @@ pub unsafe fn Q6_Vb_vlut32or_VbVbVbI(
 ///
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvvbi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4233,7 +4233,7 @@ pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_nm))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4245,7 +4245,7 @@ pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwh_oracci))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4262,7 +4262,7 @@ pub unsafe fn Q6_Wh_vlut16or_WhVbVhI(
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vlutvwhi))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4274,7 +4274,7 @@ pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmaxb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4286,7 +4286,7 @@ pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vminb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4298,7 +4298,7 @@ pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4310,7 +4310,7 @@ pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpauhb_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4326,7 +4326,7 @@ pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyewuh_64))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4338,7 +4338,7 @@ pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4350,7 +4350,7 @@ pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyiwub_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4362,7 +4362,7 @@ pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> H
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vmpyowh_64_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4378,7 +4378,7 @@ pub unsafe fn Q6_W_vmpyoacc_WVwVh(
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduhub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4390,7 +4390,7 @@ pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vrounduwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4402,7 +4402,7 @@ pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsatuwuh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4414,7 +4414,7 @@ pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4426,7 +4426,7 @@ pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubbsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4438,7 +4438,7 @@ pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubububb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4450,7 +4450,7 @@ pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4462,7 +4462,7 @@ pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[cfg_attr(test, assert_instr(vsubuwsat_dv))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4474,7 +4474,7 @@ pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4486,7 +4486,7 @@ pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vabsb_sat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4498,7 +4498,7 @@ pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vaslh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4510,7 +4510,7 @@ pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasrh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4522,7 +4522,7 @@ pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4534,7 +4534,7 @@ pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32)
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4546,7 +4546,7 @@ pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vasruwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4558,7 +4558,7 @@ pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) ->
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4570,7 +4570,7 @@ pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavgbrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4582,7 +4582,7 @@ pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4594,7 +4594,7 @@ pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vavguwrnd))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4606,7 +4606,7 @@ pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: MAPPING
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vdd0))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4618,7 +4618,7 @@ pub unsafe fn Q6_W_vzero() -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4630,7 +4630,7 @@ pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 ///
 /// Instruction Type: CVI_GATHER_DV
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4642,7 +4642,7 @@ pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec
 ///
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vgathermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4654,7 +4654,7 @@ pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4666,7 +4666,7 @@ pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpabuu_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4682,7 +4682,7 @@ pub unsafe fn Q6_Wh_vmpaacc_WhWubRub(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyh_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4694,7 +4694,7 @@ pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4706,7 +4706,7 @@ pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vmpyuhe_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4718,7 +4718,7 @@ pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vnavgb))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4730,7 +4730,7 @@ pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4742,7 +4742,7 @@ pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermh_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4754,7 +4754,7 @@ pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 ///
 /// Instruction Type: CVI_SCATTER_DV
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4766,7 +4766,7 @@ pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec
 ///
 /// Instruction Type: CVI_SCATTER_DV
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermhw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4778,7 +4778,7 @@ pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4790,7 +4790,7 @@ pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector)
 ///
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[cfg_attr(test, assert_instr(vscattermw_add))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4802,7 +4802,7 @@ pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto
 ///
 /// Instruction Type: CVI_VP_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vasr_into))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4818,7 +4818,7 @@ pub unsafe fn Q6_Ww_vasrinto_WwVwVw(
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vrotr))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4830,7 +4830,7 @@ pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[cfg_attr(test, assert_instr(vsatdw))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4842,7 +4842,7 @@ pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4858,7 +4858,7 @@ pub unsafe fn Q6_Ww_v6mpy_WubWbI_h(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4875,7 +4875,7 @@ pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4891,7 +4891,7 @@ pub unsafe fn Q6_Ww_v6mpy_WubWbI_v(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4908,7 +4908,7 @@ pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v(
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4920,7 +4920,7 @@ pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vabs_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4932,7 +4932,7 @@ pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4944,7 +4944,7 @@ pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4956,7 +4956,7 @@ pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4968,7 +4968,7 @@ pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4980,7 +4980,7 @@ pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -4992,7 +4992,7 @@ pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5004,7 +5004,7 @@ pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5016,7 +5016,7 @@ pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5028,7 +5028,7 @@ pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vadd_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5040,7 +5040,7 @@ pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vassign_fp))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5052,7 +5052,7 @@ pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5064,7 +5064,7 @@ pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_hf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5076,7 +5076,7 @@ pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vconv_sf_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5088,7 +5088,7 @@ pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_b_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5100,7 +5100,7 @@ pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5112,7 +5112,7 @@ pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5124,7 +5124,7 @@ pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5136,7 +5136,7 @@ pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5148,7 +5148,7 @@ pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5160,7 +5160,7 @@ pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_uh))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5172,7 +5172,7 @@ pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5184,7 +5184,7 @@ pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_ub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5196,7 +5196,7 @@ pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vcvt_uh_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5208,7 +5208,7 @@ pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5220,7 +5220,7 @@ pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5232,7 +5232,7 @@ pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVec
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5244,7 +5244,7 @@ pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5256,7 +5256,7 @@ pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5268,7 +5268,7 @@ pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5280,7 +5280,7 @@ pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5292,7 +5292,7 @@ pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vfneg_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5304,7 +5304,7 @@ pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5316,7 +5316,7 @@ pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmax_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5328,7 +5328,7 @@ pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5340,7 +5340,7 @@ pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmin_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5352,7 +5352,7 @@ pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5364,7 +5364,7 @@ pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5376,7 +5376,7 @@ pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVect
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5388,7 +5388,7 @@ pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5400,7 +5400,7 @@ pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5412,7 +5412,7 @@ pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5424,7 +5424,7 @@ pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5436,7 +5436,7 @@ pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5448,7 +5448,7 @@ pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5460,7 +5460,7 @@ pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_qf32_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5472,7 +5472,7 @@ pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5484,7 +5484,7 @@ pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5500,7 +5500,7 @@ pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf(
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vmpy_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5512,7 +5512,7 @@ pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5524,7 +5524,7 @@ pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_hf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5536,7 +5536,7 @@ pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5548,7 +5548,7 @@ pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf16_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5560,7 +5560,7 @@ pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5572,7 +5572,7 @@ pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_qf32_mix))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5584,7 +5584,7 @@ pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5596,7 +5596,7 @@ pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5608,7 +5608,7 @@ pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[cfg_attr(test, assert_instr(vsub_sf_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5620,7 +5620,7 @@ pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5632,7 +5632,7 @@ pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvuhubsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5644,7 +5644,7 @@ pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhrndsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5656,7 +5656,7 @@ pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vasrvwuhsat))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5668,7 +5668,7 @@ pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))]
 #[cfg_attr(test, assert_instr(vmpyuhvs))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5680,7 +5680,7 @@ pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_h_hf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5692,7 +5692,7 @@ pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_hf_h))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5704,7 +5704,7 @@ pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_sf_w))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5716,7 +5716,7 @@ pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))]
 #[cfg_attr(test, assert_instr(vconv_w_sf))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5728,7 +5728,7 @@ pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(get_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5740,7 +5740,7 @@ pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(set_qfext))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5752,7 +5752,7 @@ pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vabs_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5764,7 +5764,7 @@ pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_b))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5776,7 +5776,7 @@ pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt2_hf_ub))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5788,7 +5788,7 @@ pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_DV
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vcvt_hf_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5800,7 +5800,7 @@ pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmax_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5812,7 +5812,7 @@ pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfmin_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5824,7 +5824,7 @@ pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector {
 ///
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))]
 #[cfg_attr(test, assert_instr(vfneg_f8))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
@@ -5837,7 +5837,7 @@ pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5855,7 +5855,7 @@ pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5873,7 +5873,7 @@ pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
@@ -5891,7 +5891,7 @@ pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5909,7 +5909,7 @@ pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5927,7 +5927,7 @@ pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
@@ -5939,7 +5939,7 @@ pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -5957,7 +5957,7 @@ pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -5973,7 +5973,7 @@ pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -5989,7 +5989,7 @@ pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -6005,7 +6005,7 @@ pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VM_ST
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) {
@@ -6021,7 +6021,7 @@ pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector)
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6037,7 +6037,7 @@ pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6053,7 +6053,7 @@ pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6069,7 +6069,7 @@ pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6085,7 +6085,7 @@ pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6101,7 +6101,7 @@ pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6117,7 +6117,7 @@ pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -6129,7 +6129,7 @@ pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -6141,7 +6141,7 @@ pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
@@ -6153,7 +6153,7 @@ pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred {
@@ -6169,7 +6169,7 @@ pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6181,7 +6181,7 @@ pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
@@ -6204,7 +6204,7 @@ pub unsafe fn Q6_Q_vcmp_eqand_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
@@ -6227,7 +6227,7 @@ pub unsafe fn Q6_Q_vcmp_eqor_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
@@ -6250,7 +6250,7 @@ pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6262,7 +6262,7 @@ pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
@@ -6285,7 +6285,7 @@ pub unsafe fn Q6_Q_vcmp_eqand_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
@@ -6308,7 +6308,7 @@ pub unsafe fn Q6_Q_vcmp_eqor_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
@@ -6331,7 +6331,7 @@ pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6343,7 +6343,7 @@ pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
@@ -6366,7 +6366,7 @@ pub unsafe fn Q6_Q_vcmp_eqand_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
@@ -6389,7 +6389,7 @@ pub unsafe fn Q6_Q_vcmp_eqor_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
@@ -6412,7 +6412,7 @@ pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6424,7 +6424,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
@@ -6447,7 +6447,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
@@ -6470,7 +6470,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
@@ -6493,7 +6493,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6505,7 +6505,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
@@ -6528,7 +6528,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
@@ -6551,7 +6551,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
@@ -6574,7 +6574,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6586,7 +6586,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
@@ -6609,7 +6609,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVubVub(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
@@ -6632,7 +6632,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVubVub(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
@@ -6655,7 +6655,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6667,7 +6667,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
@@ -6690,7 +6690,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
@@ -6713,7 +6713,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
@@ -6736,7 +6736,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6748,7 +6748,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
@@ -6771,7 +6771,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
@@ -6794,7 +6794,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
@@ -6817,7 +6817,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -6829,7 +6829,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
@@ -6852,7 +6852,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
@@ -6875,7 +6875,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
@@ -6898,7 +6898,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector {
@@ -6914,7 +6914,7 @@ pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6930,7 +6930,7 @@ pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6946,7 +6946,7 @@ pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6962,7 +6962,7 @@ pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6978,7 +6978,7 @@ pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -6994,7 +6994,7 @@ pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector {
@@ -7010,7 +7010,7 @@ pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair {
@@ -7026,7 +7026,7 @@ pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) ->
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VP
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
@@ -7038,7 +7038,7 @@ pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -7056,7 +7056,7 @@ pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA_DV
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred {
@@ -7074,7 +7074,7 @@ pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -7089,7 +7089,7 @@ pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VX_LATE
 /// Execution Slots: SLOT23
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector {
@@ -7105,7 +7105,7 @@ pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
@@ -7120,7 +7120,7 @@ pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
@@ -7135,7 +7135,7 @@ pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vgather_AQRMVh(
@@ -7159,7 +7159,7 @@ pub unsafe fn Q6_vgather_AQRMVh(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_GATHER_DV
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vgather_AQRMWw(
@@ -7183,7 +7183,7 @@ pub unsafe fn Q6_vgather_AQRMWw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_GATHER
 /// Execution Slots: SLOT01
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vgather_AQRMVw(
@@ -7207,7 +7207,7 @@ pub unsafe fn Q6_vgather_AQRMVw(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
@@ -7222,7 +7222,7 @@ pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
@@ -7237,7 +7237,7 @@ pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VS
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
@@ -7252,7 +7252,7 @@ pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector {
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vscatter_QRMVhV(
@@ -7276,7 +7276,7 @@ pub unsafe fn Q6_vscatter_QRMVhV(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_SCATTER_DV
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vscatter_QRMWwV(
@@ -7300,7 +7300,7 @@ pub unsafe fn Q6_vscatter_QRMWwV(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_SCATTER
 /// Execution Slots: SLOT0
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_vscatter_QRMVwV(
@@ -7324,7 +7324,7 @@ pub unsafe fn Q6_vscatter_QRMVwV(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
@@ -7344,7 +7344,7 @@ pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -7356,7 +7356,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
@@ -7379,7 +7379,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
@@ -7402,7 +7402,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
@@ -7425,7 +7425,7 @@ pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred {
@@ -7437,7 +7437,7 @@ pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
@@ -7460,7 +7460,7 @@ pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
@@ -7483,7 +7483,7 @@ pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf(
 /// This is a compound operation composed of multiple HVX instructions.
 /// Instruction Type: CVI_VA
 /// Execution Slots: SLOT0123
-#[inline(always)]
+#[inline]
 #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))]
 #[unstable(feature = "stdarch_hexagon", issue = "151523")]
 pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf(
diff --git a/crates/stdarch-gen-hexagon/src/main.rs b/crates/stdarch-gen-hexagon/src/main.rs
index 79837e2224..8a58c66313 100644
--- a/crates/stdarch-gen-hexagon/src/main.rs
+++ b/crates/stdarch-gen-hexagon/src/main.rs
@@ -1449,7 +1449,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String {
         output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots));
 
         // Generate attributes
-        output.push_str("#[inline(always)]\n");
+        output.push_str("#[inline]\n");
         output.push_str(&format!(
             "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n",
             info.min_arch
@@ -1532,7 +1532,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String {
             }
 
             // Generate attributes
-            output.push_str("#[inline(always)]\n");
+            output.push_str("#[inline]\n");
             output.push_str(&format!(
                 "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n",
                 info.min_arch

From 224cae0fc6c9b2e4b7f7f18f214adf5c5c0b5a51 Mon Sep 17 00:00:00 2001
From: James Barford-Evans <james.barford-evans@arm.com>
Date: Wed, 6 May 2026 16:28:46 +0100
Subject: [PATCH 274/326] Remove #[inline(always)] from loongarch intrinsic
 generator & re-generate intrinsics

---
 .../src/loongarch64/lasx/generated.rs         | 1144 ++++++++---------
 .../src/loongarch64/lsx/generated.rs          | 1056 +++++++--------
 crates/core_arch/src/loongarch_shared/mod.rs  |    8 +-
 crates/stdarch-gen-loongarch/src/main.rs      |    4 +-
 4 files changed, 1106 insertions(+), 1106 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index de629914ab..c7dbd46480 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -1157,35 +1157,35 @@ unsafe extern "unadjusted" {
     fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64;
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrar_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrar_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1194,7 +1194,7 @@ pub fn lasx_xvsrari_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1203,7 +1203,7 @@ pub fn lasx_xvsrari_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1212,7 +1212,7 @@ pub fn lasx_xvsrari_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1221,35 +1221,35 @@ pub fn lasx_xvsrari_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1258,7 +1258,7 @@ pub fn lasx_xvsrlri_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1267,7 +1267,7 @@ pub fn lasx_xvsrlri_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1276,7 +1276,7 @@ pub fn lasx_xvsrlri_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1285,35 +1285,35 @@ pub fn lasx_xvsrlri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitclr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1322,7 +1322,7 @@ pub fn lasx_xvbitclri_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1331,7 +1331,7 @@ pub fn lasx_xvbitclri_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1340,7 +1340,7 @@ pub fn lasx_xvbitclri_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1349,35 +1349,35 @@ pub fn lasx_xvbitclri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitset_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitset_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1386,7 +1386,7 @@ pub fn lasx_xvbitseti_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1395,7 +1395,7 @@ pub fn lasx_xvbitseti_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1404,7 +1404,7 @@ pub fn lasx_xvbitseti_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1413,35 +1413,35 @@ pub fn lasx_xvbitseti_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitrev_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrev_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1450,7 +1450,7 @@ pub fn lasx_xvbitrevi_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1459,7 +1459,7 @@ pub fn lasx_xvbitrevi_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1468,7 +1468,7 @@ pub fn lasx_xvbitrevi_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1477,7 +1477,7 @@ pub fn lasx_xvbitrevi_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitrevi_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1486,7 +1486,7 @@ pub fn lasx_xvsubi_bu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1495,7 +1495,7 @@ pub fn lasx_xvsubi_hu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1504,7 +1504,7 @@ pub fn lasx_xvsubi_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1513,7 +1513,7 @@ pub fn lasx_xvsubi_du<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1522,7 +1522,7 @@ pub fn lasx_xvsat_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1531,7 +1531,7 @@ pub fn lasx_xvsat_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1540,7 +1540,7 @@ pub fn lasx_xvsat_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1549,7 +1549,7 @@ pub fn lasx_xvsat_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1558,7 +1558,7 @@ pub fn lasx_xvsat_bu<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1567,7 +1567,7 @@ pub fn lasx_xvsat_hu<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1576,7 +1576,7 @@ pub fn lasx_xvsat_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1585,399 +1585,399 @@ pub fn lasx_xvsat_du<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1986,7 +1986,7 @@ pub fn lasx_xvrepl128vei_b<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_b(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1995,7 +1995,7 @@ pub fn lasx_xvrepl128vei_h<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_h(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2004,7 +2004,7 @@ pub fn lasx_xvrepl128vei_w<const IMM2: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_w(transmute(a), IMM2)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2013,203 +2013,203 @@ pub fn lasx_xvrepl128vei_d<const IMM1: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrepl128vei_d(transmute(a), IMM1)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickev_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickev_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpickod_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickod_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2218,7 +2218,7 @@ pub fn lasx_xvandi_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2227,7 +2227,7 @@ pub fn lasx_xvori_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2236,7 +2236,7 @@ pub fn lasx_xvnori_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2245,14 +2245,14 @@ pub fn lasx_xvxori_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2261,7 +2261,7 @@ pub fn lasx_xvbitseli_b<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2270,7 +2270,7 @@ pub fn lasx_xvshuf4i_b<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2279,7 +2279,7 @@ pub fn lasx_xvshuf4i_h<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2288,343 +2288,343 @@ pub fn lasx_xvshuf4i_w<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvclo_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvclo_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvt_h_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcvt_h_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvt_s_d(a: m256d, b: m256d) -> m256 {
     unsafe { transmute(__lasx_xvfcvt_s_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmin_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmin_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmin_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmin_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmina_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmina_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmina_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmina_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmax_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmax_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmax_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmax_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmaxa_s(a: m256, b: m256) -> m256 {
     unsafe { transmute(__lasx_xvfmaxa_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfmaxa_d(a: m256d, b: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfmaxa_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfclass_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvfclass_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfclass_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfclass_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecip_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrecip_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecip_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrecip_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecipe_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrecipe_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrecipe_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrecipe_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrte_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrsqrte_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrte_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrsqrte_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrint_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrint_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrint_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrint_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrt_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrsqrt_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrsqrt_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrsqrt_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvflogb_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvflogb_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvflogb_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvflogb_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvth_s_h(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvfcvth_s_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvth_d_s(a: m256) -> m256d {
     unsafe { transmute(__lasx_xvfcvth_d_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvtl_s_h(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvfcvtl_s_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcvtl_d_s(a: m256) -> m256d {
     unsafe { transmute(__lasx_xvfcvtl_d_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftint_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftint_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_wu_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftint_wu_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_lu_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftint_lu_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_wu_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_wu_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_lu_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_lu_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_s_w(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvffint_s_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_d_l(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffint_d_l(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_s_wu(a: m256i) -> m256 {
     unsafe { transmute(__lasx_xvffint_s_wu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_d_lu(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffint_d_lu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_b(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_h(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_w(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve_d(a: m256i, b: i32) -> m256i {
     unsafe { transmute(__lasx_xvreplve_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2633,63 +2633,63 @@ pub fn lasx_xvpermi_w<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmuh_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmuh_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2698,7 +2698,7 @@ pub fn lasx_xvsllwil_h_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_h_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2707,7 +2707,7 @@ pub fn lasx_xvsllwil_w_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_w_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2716,7 +2716,7 @@ pub fn lasx_xvsllwil_d_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_d_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2725,7 +2725,7 @@ pub fn lasx_xvsllwil_hu_bu<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_hu_bu(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2734,7 +2734,7 @@ pub fn lasx_xvsllwil_wu_hu<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_wu_hu(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2743,217 +2743,217 @@ pub fn lasx_xvsllwil_du_wu<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsllwil_du_wu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsran_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsran_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsran_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssran_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssran_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrarn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrarn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrarn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrarn_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrln_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrln_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrln_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlrn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlrn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsrlrn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_bu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_hu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_wu_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2962,7 +2962,7 @@ pub fn lasx_xvfrstpi_b<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstpi_b(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2971,21 +2971,21 @@ pub fn lasx_xvfrstpi_h<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstpi_h(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrstp_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrstp_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2994,7 +2994,7 @@ pub fn lasx_xvshuf4i_d<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvshuf4i_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3003,7 +3003,7 @@ pub fn lasx_xvbsrl_v<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbsrl_v(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3012,7 +3012,7 @@ pub fn lasx_xvbsll_v<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbsll_v(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3021,7 +3021,7 @@ pub fn lasx_xvextrins_b<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3030,7 +3030,7 @@ pub fn lasx_xvextrins_h<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_h(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3039,7 +3039,7 @@ pub fn lasx_xvextrins_w<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3048,287 +3048,287 @@ pub fn lasx_xvextrins_d<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextrins_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskltz_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskltz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrne_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrne_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrne_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrne_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrp_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrp_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrp_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrp_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrm_w_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrm_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrm_l_d(a: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrm_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftint_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftint_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffint_s_l(a: m256i, b: m256i) -> m256 {
     unsafe { transmute(__lasx_xvffint_s_l(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrz_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrz_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrp_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrp_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrm_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrm_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrne_w_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvftintrne_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftinth_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftinth_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintl_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintl_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffinth_d_w(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffinth_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvffintl_d_w(a: m256i) -> m256d {
     unsafe { transmute(__lasx_xvffintl_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrzh_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrzh_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrzl_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrzl_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrph_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrph_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrpl_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrpl_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrmh_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrmh_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrml_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrml_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrneh_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrneh_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvftintrnel_l_s(a: m256) -> m256i {
     unsafe { transmute(__lasx_xvftintrnel_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrne_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrne_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrne_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrne_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrz_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrz_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrz_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrp_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrp_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrp_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrp_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrm_s(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvfrintrm_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfrintrm_d(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvfrintrm_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3337,7 +3337,7 @@ pub unsafe fn lasx_xvld<const IMM_S12: i32>(mem_addr: *const i8) -> m256i {
     transmute(__lasx_xvld(mem_addr, IMM_S12))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3346,7 +3346,7 @@ pub unsafe fn lasx_xvst<const IMM_S12: i32>(a: m256i, mem_addr: *mut i8) {
     __lasx_xvst(transmute(a), mem_addr, IMM_S12)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3356,7 +3356,7 @@ pub unsafe fn lasx_xvstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m256i, mem_a
     __lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3366,7 +3366,7 @@ pub unsafe fn lasx_xvstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m256i, mem_a
     __lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3376,7 +3376,7 @@ pub unsafe fn lasx_xvstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m256i, mem_a
     __lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3386,7 +3386,7 @@ pub unsafe fn lasx_xvstelm_d<const IMM_S8: i32, const IMM1: u32>(a: m256i, mem_a
     __lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3395,7 +3395,7 @@ pub fn lasx_xvinsve0_w<const IMM3: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvinsve0_w(transmute(a), transmute(b), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3404,7 +3404,7 @@ pub fn lasx_xvinsve0_d<const IMM2: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvinsve0_d(transmute(a), transmute(b), IMM2)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3413,7 +3413,7 @@ pub fn lasx_xvpickve_w<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickve_w(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3422,49 +3422,49 @@ pub fn lasx_xvpickve_d<const IMM2: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpickve_d(transmute(a), IMM2)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrlrn_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_b_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_h_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvssrln_w_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3473,147 +3473,147 @@ pub fn lasx_xvldi<const IMM_S13: i32>() -> m256i {
     unsafe { transmute(__lasx_xvldi(IMM_S13)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lasx_xvldx(mem_addr: *const i8, b: i64) -> m256i {
     transmute(__lasx_xvldx(mem_addr, transmute(b)))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lasx_xvstx(a: m256i, mem_addr: *mut i8, b: i64) {
     __lasx_xvstx(transmute(a), mem_addr, transmute(b))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvextl_qu_du(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextl_qu_du(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvreplve0_q(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvreplve0_q(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_h_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_h_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_w_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_w_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_d_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_w_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_w_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_d_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_d_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_d_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_d_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_hu_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_hu_bu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_wu_hu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_wu_hu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_du_wu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_du_wu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_wu_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_wu_bu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_du_hu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_du_hu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_vext2xv_du_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_vext2xv_du_bu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3622,7 +3622,7 @@ pub fn lasx_xvpermi_q<const IMM8: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_q(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3631,14 +3631,14 @@ pub fn lasx_xvpermi_d<const IMM8: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvpermi_d(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvperm_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvperm_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3647,7 +3647,7 @@ pub unsafe fn lasx_xvldrepl_b<const IMM_S12: i32>(mem_addr: *const i8) -> m256i
     transmute(__lasx_xvldrepl_b(mem_addr, IMM_S12))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3656,7 +3656,7 @@ pub unsafe fn lasx_xvldrepl_h<const IMM_S11: i32>(mem_addr: *const i8) -> m256i
     transmute(__lasx_xvldrepl_h(mem_addr, IMM_S11))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3665,7 +3665,7 @@ pub unsafe fn lasx_xvldrepl_w<const IMM_S10: i32>(mem_addr: *const i8) -> m256i
     transmute(__lasx_xvldrepl_w(mem_addr, IMM_S10))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3674,763 +3674,763 @@ pub unsafe fn lasx_xvldrepl_d<const IMM_S9: i32>(mem_addr: *const i8) -> m256i {
     transmute(__lasx_xvldrepl_d(mem_addr, IMM_S9))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwev_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsubwod_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsubwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_d_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_w_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_h_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_q_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_d_wu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_w_hu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_h_bu(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_d_wu_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_w_hu_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_h_bu_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhaddw_qu_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhaddw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_q_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvhsubw_qu_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvhsubw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_q_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_d_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_w_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_h_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_q_du(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_d_wu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_w_hu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_h_bu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_q_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_d_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_w_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_h_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_q_du(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_d_wu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_w_hu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_h_bu(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_q_du_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_d_wu_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_w_hu_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwev_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwev_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_q_du_d(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_d_wu_w(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_w_hu_h(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmaddwod_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_b(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_h(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_w(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvrotr_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvadd_q(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadd_q(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvsub_q(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsub_q(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwev_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvaddwod_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvaddwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwev_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmulwod_q_du_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmulwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmskgez_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmskgez_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvmsknz_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvmsknz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_h_b(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_h_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_w_h(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_w_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_d_w(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_q_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_q_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_hu_bu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_hu_bu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_wu_hu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_wu_hu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_du_wu(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_du_wu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvexth_qu_du(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvexth_qu_du(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4439,7 +4439,7 @@ pub fn lasx_xvrotri_b<const IMM3: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4448,7 +4448,7 @@ pub fn lasx_xvrotri_h<const IMM4: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4457,7 +4457,7 @@ pub fn lasx_xvrotri_w<const IMM5: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4466,14 +4466,14 @@ pub fn lasx_xvrotri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvrotri_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvextl_q_d(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvextl_q_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4482,7 +4482,7 @@ pub fn lasx_xvsrlni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4491,7 +4491,7 @@ pub fn lasx_xvsrlni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4500,7 +4500,7 @@ pub fn lasx_xvsrlni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4509,7 +4509,7 @@ pub fn lasx_xvsrlni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4518,7 +4518,7 @@ pub fn lasx_xvsrlrni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4527,7 +4527,7 @@ pub fn lasx_xvsrlrni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4536,7 +4536,7 @@ pub fn lasx_xvsrlrni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4545,7 +4545,7 @@ pub fn lasx_xvsrlrni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4554,7 +4554,7 @@ pub fn lasx_xvssrlni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4563,7 +4563,7 @@ pub fn lasx_xvssrlni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4572,7 +4572,7 @@ pub fn lasx_xvssrlni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4581,7 +4581,7 @@ pub fn lasx_xvssrlni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4590,7 +4590,7 @@ pub fn lasx_xvssrlni_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4599,7 +4599,7 @@ pub fn lasx_xvssrlni_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4608,7 +4608,7 @@ pub fn lasx_xvssrlni_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4617,7 +4617,7 @@ pub fn lasx_xvssrlni_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4626,7 +4626,7 @@ pub fn lasx_xvssrlrni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4635,7 +4635,7 @@ pub fn lasx_xvssrlrni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4644,7 +4644,7 @@ pub fn lasx_xvssrlrni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4653,7 +4653,7 @@ pub fn lasx_xvssrlrni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4662,7 +4662,7 @@ pub fn lasx_xvssrlrni_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4671,7 +4671,7 @@ pub fn lasx_xvssrlrni_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4680,7 +4680,7 @@ pub fn lasx_xvssrlrni_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4689,7 +4689,7 @@ pub fn lasx_xvssrlrni_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrlrni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4698,7 +4698,7 @@ pub fn lasx_xvsrani_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4707,7 +4707,7 @@ pub fn lasx_xvsrani_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4716,7 +4716,7 @@ pub fn lasx_xvsrani_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4725,7 +4725,7 @@ pub fn lasx_xvsrani_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4734,7 +4734,7 @@ pub fn lasx_xvsrarni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4743,7 +4743,7 @@ pub fn lasx_xvsrarni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4752,7 +4752,7 @@ pub fn lasx_xvsrarni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4761,7 +4761,7 @@ pub fn lasx_xvsrarni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4770,7 +4770,7 @@ pub fn lasx_xvssrani_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4779,7 +4779,7 @@ pub fn lasx_xvssrani_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4788,7 +4788,7 @@ pub fn lasx_xvssrani_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4797,7 +4797,7 @@ pub fn lasx_xvssrani_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4806,7 +4806,7 @@ pub fn lasx_xvssrani_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4815,7 +4815,7 @@ pub fn lasx_xvssrani_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4824,7 +4824,7 @@ pub fn lasx_xvssrani_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4833,7 +4833,7 @@ pub fn lasx_xvssrani_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrani_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4842,7 +4842,7 @@ pub fn lasx_xvssrarni_b_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4851,7 +4851,7 @@ pub fn lasx_xvssrarni_h_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4860,7 +4860,7 @@ pub fn lasx_xvssrarni_w_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4869,7 +4869,7 @@ pub fn lasx_xvssrarni_d_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4878,7 +4878,7 @@ pub fn lasx_xvssrarni_bu_h<const IMM4: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4887,7 +4887,7 @@ pub fn lasx_xvssrarni_hu_w<const IMM5: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4896,7 +4896,7 @@ pub fn lasx_xvssrarni_wu_d<const IMM6: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4905,385 +4905,385 @@ pub fn lasx_xvssrarni_du_q<const IMM7: u32>(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvssrarni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_b(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_d(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_h(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_v(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_v(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbnz_w(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbnz_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_b(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_d(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_h(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_v(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_v(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xbz_w(a: m256i) -> i32 {
     unsafe { transmute(__lasx_xbz_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_caf_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_caf_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_caf_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_caf_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_ceq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_ceq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_ceq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_ceq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cle_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cle_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cle_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cle_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_clt_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_clt_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_clt_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_clt_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cne_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cne_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cne_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cne_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cor_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cor_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cor_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cor_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cueq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cueq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cule_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cule_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cule_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cule_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cult_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cult_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cult_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cult_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cun_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cun_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cune_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cune_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cune_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cune_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_cun_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_cun_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_saf_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_saf_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_saf_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_saf_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_seq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_seq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_seq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_seq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sle_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sle_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sle_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sle_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_slt_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_slt_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_slt_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_slt_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sne_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sne_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sne_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sne_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sor_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sor_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sor_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sor_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sueq_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sueq_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sule_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sule_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sule_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sule_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sult_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sult_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sult_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sult_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sun_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sun_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sune_d(a: m256d, b: m256d) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sune_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sune_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sune_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_xvfcmp_sun_s(a: m256, b: m256) -> m256i {
     unsafe { transmute(__lasx_xvfcmp_sun_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5292,7 +5292,7 @@ pub fn lasx_xvpickve_d_f<const IMM2: u32>(a: m256d) -> m256d {
     unsafe { transmute(__lasx_xvpickve_d_f(transmute(a), IMM2)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -5301,126 +5301,126 @@ pub fn lasx_xvpickve_w_f<const IMM3: u32>(a: m256) -> m256 {
     unsafe { transmute(__lasx_xvpickve_w_f(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_cast_128_s(a: m128) -> m256 {
     unsafe { transmute(__lasx_cast_128_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_cast_128_d(a: m128d) -> m256d {
     unsafe { transmute(__lasx_cast_128_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_cast_128(a: m128i) -> m256i {
     unsafe { transmute(__lasx_cast_128(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 {
     unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d {
     unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i {
     unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_lo_s(a: m256) -> m128 {
     unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_hi_s(a: m256) -> m128 {
     unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_lo_d(a: m256d) -> m128d {
     unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_hi_d(a: m256d) -> m128d {
     unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_lo(a: m256i) -> m128i {
     unsafe { transmute(__lasx_extract_128_lo(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_extract_128_hi(a: m256i) -> m128i {
     unsafe { transmute(__lasx_extract_128_hi(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 {
     unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 {
     unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d {
     unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d {
     unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i {
     unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i {
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index d2d77e2f3e..4ec3cdf0c5 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -1069,35 +1069,35 @@ unsafe extern "unadjusted" {
     fn __lsx_vfcmp_sun_s(a: __v4f32, b: __v4f32) -> __v4i32;
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1106,7 +1106,7 @@ pub fn lsx_vsrari_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1115,7 +1115,7 @@ pub fn lsx_vsrari_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1124,7 +1124,7 @@ pub fn lsx_vsrari_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1133,35 +1133,35 @@ pub fn lsx_vsrari_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1170,7 +1170,7 @@ pub fn lsx_vsrlri_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1179,7 +1179,7 @@ pub fn lsx_vsrlri_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1188,7 +1188,7 @@ pub fn lsx_vsrlri_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1197,35 +1197,35 @@ pub fn lsx_vsrlri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitclr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1234,7 +1234,7 @@ pub fn lsx_vbitclri_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1243,7 +1243,7 @@ pub fn lsx_vbitclri_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1252,7 +1252,7 @@ pub fn lsx_vbitclri_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1261,35 +1261,35 @@ pub fn lsx_vbitclri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitset_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitset_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1298,7 +1298,7 @@ pub fn lsx_vbitseti_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1307,7 +1307,7 @@ pub fn lsx_vbitseti_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1316,7 +1316,7 @@ pub fn lsx_vbitseti_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1325,35 +1325,35 @@ pub fn lsx_vbitseti_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitrev_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrev_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1362,7 +1362,7 @@ pub fn lsx_vbitrevi_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1371,7 +1371,7 @@ pub fn lsx_vbitrevi_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1380,7 +1380,7 @@ pub fn lsx_vbitrevi_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1389,7 +1389,7 @@ pub fn lsx_vbitrevi_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1398,7 +1398,7 @@ pub fn lsx_vsubi_bu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1407,7 +1407,7 @@ pub fn lsx_vsubi_hu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1416,7 +1416,7 @@ pub fn lsx_vsubi_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1425,7 +1425,7 @@ pub fn lsx_vsubi_du<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1434,7 +1434,7 @@ pub fn lsx_vsat_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1443,7 +1443,7 @@ pub fn lsx_vsat_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1452,7 +1452,7 @@ pub fn lsx_vsat_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1461,7 +1461,7 @@ pub fn lsx_vsat_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1470,7 +1470,7 @@ pub fn lsx_vsat_bu<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1479,7 +1479,7 @@ pub fn lsx_vsat_hu<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1488,7 +1488,7 @@ pub fn lsx_vsat_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1497,427 +1497,427 @@ pub fn lsx_vsat_du<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i {
     unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1926,7 +1926,7 @@ pub fn lsx_vreplvei_b<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1935,7 +1935,7 @@ pub fn lsx_vreplvei_h<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1944,7 +1944,7 @@ pub fn lsx_vreplvei_w<const IMM2: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_w(transmute(a), IMM2)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1953,196 +1953,196 @@ pub fn lsx_vreplvei_d<const IMM1: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2151,7 +2151,7 @@ pub fn lsx_vandi_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2160,7 +2160,7 @@ pub fn lsx_vori_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2169,7 +2169,7 @@ pub fn lsx_vnori_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2178,14 +2178,14 @@ pub fn lsx_vxori_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2194,7 +2194,7 @@ pub fn lsx_vbitseli_b<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2203,7 +2203,7 @@ pub fn lsx_vshuf4i_b<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2212,7 +2212,7 @@ pub fn lsx_vshuf4i_h<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2221,371 +2221,371 @@ pub fn lsx_vshuf4i_w<const IMM8: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vclo_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vclo_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvt_h_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcvt_h_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvt_s_d(a: m128d, b: m128d) -> m128 {
     unsafe { transmute(__lsx_vfcvt_s_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmin_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmin_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmin_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmin_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmina_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmina_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmina_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmina_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmax_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmax_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmax_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmax_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmaxa_s(a: m128, b: m128) -> m128 {
     unsafe { transmute(__lsx_vfmaxa_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfmaxa_d(a: m128d, b: m128d) -> m128d {
     unsafe { transmute(__lsx_vfmaxa_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfclass_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vfclass_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfclass_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vfclass_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecip_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrecip_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecip_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrecip_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecipe_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrecipe_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrecipe_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrecipe_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrte_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrsqrte_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx,frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrte_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrsqrte_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrint_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrint_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrint_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrint_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrt_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrsqrt_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrsqrt_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrsqrt_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vflogb_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vflogb_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vflogb_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vflogb_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvth_s_h(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vfcvth_s_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvth_d_s(a: m128) -> m128d {
     unsafe { transmute(__lsx_vfcvth_d_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvtl_s_h(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vfcvtl_s_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcvtl_d_s(a: m128) -> m128d {
     unsafe { transmute(__lsx_vfcvtl_d_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftint_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftint_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_wu_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftint_wu_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_lu_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftint_lu_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrz_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrz_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_wu_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrz_wu_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_lu_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrz_lu_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_s_w(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vffint_s_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_d_l(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffint_d_l(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_s_wu(a: m128i) -> m128 {
     unsafe { transmute(__lsx_vffint_s_wu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_d_lu(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmuh_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmuh_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2594,7 +2594,7 @@ pub fn lsx_vsllwil_h_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_h_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2603,7 +2603,7 @@ pub fn lsx_vsllwil_w_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_w_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2612,7 +2612,7 @@ pub fn lsx_vsllwil_d_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_d_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2621,7 +2621,7 @@ pub fn lsx_vsllwil_hu_bu<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_hu_bu(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2630,7 +2630,7 @@ pub fn lsx_vsllwil_wu_hu<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_wu_hu(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2639,217 +2639,217 @@ pub fn lsx_vsllwil_du_wu<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsllwil_du_wu(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsran_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsran_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsran_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssran_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssran_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrarn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrarn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrarn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrarn_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrln_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrln_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrln_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlrn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlrn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsrlrn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_bu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_bu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_hu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_hu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_wu_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_wu_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2858,7 +2858,7 @@ pub fn lsx_vfrstpi_b<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstpi_b(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2867,21 +2867,21 @@ pub fn lsx_vfrstpi_h<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstpi_h(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrstp_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstp_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrstp_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2890,7 +2890,7 @@ pub fn lsx_vshuf4i_d<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf4i_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2899,7 +2899,7 @@ pub fn lsx_vbsrl_v<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbsrl_v(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2908,7 +2908,7 @@ pub fn lsx_vbsll_v<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbsll_v(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2917,7 +2917,7 @@ pub fn lsx_vextrins_b<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_b(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2926,7 +2926,7 @@ pub fn lsx_vextrins_h<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_h(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2935,7 +2935,7 @@ pub fn lsx_vextrins_w<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -2944,287 +2944,287 @@ pub fn lsx_vextrins_d<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vextrins_d(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskltz_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskltz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsigncov_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsigncov_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrne_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrne_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrne_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrne_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrp_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrp_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrp_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrp_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrm_w_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrm_w_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrm_l_d(a: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrm_l_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftint_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftint_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffint_s_l(a: m128i, b: m128i) -> m128 {
     unsafe { transmute(__lsx_vffint_s_l(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrz_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrz_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrp_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrp_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrm_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrm_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrne_w_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vftintrne_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintl_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintl_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftinth_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftinth_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffinth_d_w(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffinth_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vffintl_d_w(a: m128i) -> m128d {
     unsafe { transmute(__lsx_vffintl_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrzl_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrzl_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrzh_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrzh_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrpl_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrpl_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrph_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrph_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrml_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrml_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrmh_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrmh_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrnel_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrnel_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vftintrneh_l_s(a: m128) -> m128i {
     unsafe { transmute(__lsx_vftintrneh_l_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrne_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrne_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrne_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrne_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrz_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrz_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrz_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrp_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrp_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrp_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrp_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrm_s(a: m128) -> m128 {
     unsafe { transmute(__lsx_vfrintrm_s(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfrintrm_d(a: m128d) -> m128d {
     unsafe { transmute(__lsx_vfrintrm_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3234,7 +3234,7 @@ pub unsafe fn lsx_vstelm_b<const IMM_S8: i32, const IMM4: u32>(a: m128i, mem_add
     __lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3244,7 +3244,7 @@ pub unsafe fn lsx_vstelm_h<const IMM_S8: i32, const IMM3: u32>(a: m128i, mem_add
     __lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3254,7 +3254,7 @@ pub unsafe fn lsx_vstelm_w<const IMM_S8: i32, const IMM2: u32>(a: m128i, mem_add
     __lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2, 3)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3264,693 +3264,693 @@ pub unsafe fn lsx_vstelm_d<const IMM_S8: i32, const IMM1: u32>(a: m128i, mem_add
     __lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwev_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsubwod_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsubwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwev_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vaddwod_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vaddwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_d_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_d_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_w_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_w_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_h_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_h_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_d_wu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_d_wu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_w_hu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_w_hu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_h_bu(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_h_bu(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_d_wu_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_d_wu_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_w_hu_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_w_hu_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_h_bu_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_h_bu_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_q_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_q_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwev_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwev_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmulwod_q_du_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vmulwod_q_du_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhaddw_qu_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhaddw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_q_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_q_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vhsubw_qu_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vhsubw_qu_du(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_d_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_w_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_h_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_d_wu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_w_hu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_h_bu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_d_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_w_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_h_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_d_wu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_w_hu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_h_bu(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_d_wu_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_w_hu_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_h_bu_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_d_wu_w(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_d_wu_w(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_w_hu_h(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_w_hu_h(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_h_bu_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_q_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_q_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_q_du(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_q_du(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwev_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwev_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmaddwod_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_b(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_b(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vrotr_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotr_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vadd_q(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadd_q(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vsub_q(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsub_q(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3959,7 +3959,7 @@ pub unsafe fn lsx_vldrepl_b<const IMM_S12: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_b(mem_addr, IMM_S12))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3968,7 +3968,7 @@ pub unsafe fn lsx_vldrepl_h<const IMM_S11: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_h(mem_addr, IMM_S11))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3977,7 +3977,7 @@ pub unsafe fn lsx_vldrepl_w<const IMM_S10: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_w(mem_addr, IMM_S10))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -3986,77 +3986,77 @@ pub unsafe fn lsx_vldrepl_d<const IMM_S9: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vldrepl_d(mem_addr, IMM_S9))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmskgez_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmskgez_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vmsknz_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vmsknz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_h_b(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_h_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_w_h(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_w_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_d_w(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_d_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_q_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_q_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_hu_bu(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_hu_bu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_wu_hu(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_wu_hu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_du_wu(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_du_wu(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vexth_qu_du(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vexth_qu_du(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4065,7 +4065,7 @@ pub fn lsx_vrotri_b<const IMM3: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_b(transmute(a), IMM3)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4074,7 +4074,7 @@ pub fn lsx_vrotri_h<const IMM4: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_h(transmute(a), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4083,7 +4083,7 @@ pub fn lsx_vrotri_w<const IMM5: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_w(transmute(a), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4092,14 +4092,14 @@ pub fn lsx_vrotri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vrotri_d(transmute(a), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vextl_q_d(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vextl_q_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4108,7 +4108,7 @@ pub fn lsx_vsrlni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4117,7 +4117,7 @@ pub fn lsx_vsrlni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4126,7 +4126,7 @@ pub fn lsx_vsrlni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4135,7 +4135,7 @@ pub fn lsx_vsrlni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4144,7 +4144,7 @@ pub fn lsx_vsrlrni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4153,7 +4153,7 @@ pub fn lsx_vsrlrni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4162,7 +4162,7 @@ pub fn lsx_vsrlrni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4171,7 +4171,7 @@ pub fn lsx_vsrlrni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4180,7 +4180,7 @@ pub fn lsx_vssrlni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4189,7 +4189,7 @@ pub fn lsx_vssrlni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4198,7 +4198,7 @@ pub fn lsx_vssrlni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4207,7 +4207,7 @@ pub fn lsx_vssrlni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4216,7 +4216,7 @@ pub fn lsx_vssrlni_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4225,7 +4225,7 @@ pub fn lsx_vssrlni_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4234,7 +4234,7 @@ pub fn lsx_vssrlni_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4243,7 +4243,7 @@ pub fn lsx_vssrlni_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4252,7 +4252,7 @@ pub fn lsx_vssrlrni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4261,7 +4261,7 @@ pub fn lsx_vssrlrni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4270,7 +4270,7 @@ pub fn lsx_vssrlrni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4279,7 +4279,7 @@ pub fn lsx_vssrlrni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4288,7 +4288,7 @@ pub fn lsx_vssrlrni_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4297,7 +4297,7 @@ pub fn lsx_vssrlrni_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4306,7 +4306,7 @@ pub fn lsx_vssrlrni_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4315,7 +4315,7 @@ pub fn lsx_vssrlrni_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4324,7 +4324,7 @@ pub fn lsx_vsrani_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4333,7 +4333,7 @@ pub fn lsx_vsrani_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4342,7 +4342,7 @@ pub fn lsx_vsrani_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4351,7 +4351,7 @@ pub fn lsx_vsrani_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4360,7 +4360,7 @@ pub fn lsx_vsrarni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4369,7 +4369,7 @@ pub fn lsx_vsrarni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4378,7 +4378,7 @@ pub fn lsx_vsrarni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4387,7 +4387,7 @@ pub fn lsx_vsrarni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4396,7 +4396,7 @@ pub fn lsx_vssrani_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4405,7 +4405,7 @@ pub fn lsx_vssrani_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4414,7 +4414,7 @@ pub fn lsx_vssrani_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4423,7 +4423,7 @@ pub fn lsx_vssrani_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4432,7 +4432,7 @@ pub fn lsx_vssrani_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4441,7 +4441,7 @@ pub fn lsx_vssrani_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4450,7 +4450,7 @@ pub fn lsx_vssrani_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4459,7 +4459,7 @@ pub fn lsx_vssrani_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrani_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4468,7 +4468,7 @@ pub fn lsx_vssrarni_b_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_b_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4477,7 +4477,7 @@ pub fn lsx_vssrarni_h_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_h_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4486,7 +4486,7 @@ pub fn lsx_vssrarni_w_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_w_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4495,7 +4495,7 @@ pub fn lsx_vssrarni_d_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_d_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4504,7 +4504,7 @@ pub fn lsx_vssrarni_bu_h<const IMM4: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_bu_h(transmute(a), transmute(b), IMM4)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4513,7 +4513,7 @@ pub fn lsx_vssrarni_hu_w<const IMM5: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_hu_w(transmute(a), transmute(b), IMM5)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4522,7 +4522,7 @@ pub fn lsx_vssrarni_wu_d<const IMM6: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_wu_d(transmute(a), transmute(b), IMM6)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4531,7 +4531,7 @@ pub fn lsx_vssrarni_du_q<const IMM7: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrarni_du_q(transmute(a), transmute(b), IMM7)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4540,7 +4540,7 @@ pub fn lsx_vpermi_w<const IMM8: u32>(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vpermi_w(transmute(a), transmute(b), IMM8)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4549,7 +4549,7 @@ pub unsafe fn lsx_vld<const IMM_S12: i32>(mem_addr: *const i8) -> m128i {
     transmute(__lsx_vld(mem_addr, IMM_S12))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4558,49 +4558,49 @@ pub unsafe fn lsx_vst<const IMM_S12: i32>(a: m128i, mem_addr: *mut i8) {
     __lsx_vst(transmute(a), mem_addr, IMM_S12)
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrlrn_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrlrn_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_b_h(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_b_h(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_h_w(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_h_w(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vssrln_w_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vssrln_w_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -4609,406 +4609,406 @@ pub fn lsx_vldi<const IMM_S13: i32>() -> m128i {
     unsafe { transmute(__lsx_vldi(IMM_S13)) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vshuf_b(a: m128i, b: m128i, c: m128i) -> m128i {
     unsafe { transmute(__lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lsx_vldx(mem_addr: *const i8, b: i64) -> m128i {
     transmute(__lsx_vldx(mem_addr, transmute(b)))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn lsx_vstx(a: m128i, mem_addr: *mut i8, b: i64) {
     __lsx_vstx(transmute(a), mem_addr, transmute(b))
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vextl_qu_du(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vextl_qu_du(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_b(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_d(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_h(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_v(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_v(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bnz_w(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bnz_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_b(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_b(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_d(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_d(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_h(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_h(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_v(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_v(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_bz_w(a: m128i) -> i32 {
     unsafe { transmute(__lsx_bz_w(transmute(a))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_caf_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_caf_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_caf_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_caf_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_ceq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_ceq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_ceq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_ceq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cle_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cle_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cle_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cle_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_clt_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_clt_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_clt_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_clt_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cne_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cne_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cne_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cne_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cor_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cor_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cor_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cor_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cueq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cueq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cule_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cule_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cule_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cule_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cult_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cult_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cult_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cult_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cun_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cun_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cune_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cune_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cune_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cune_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_cun_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_cun_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_saf_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_saf_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_saf_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_saf_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_seq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_seq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_seq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_seq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sle_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sle_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sle_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sle_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_slt_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_slt_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_slt_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_slt_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sne_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sne_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sne_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sne_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sor_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sor_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sor_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sor_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sueq_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sueq_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sueq_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sueq_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sule_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sule_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sule_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sule_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sult_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sult_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sult_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sult_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sun_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sun_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sune_d(a: m128d, b: m128d) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sune_d(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sune_s(a: m128, b: m128) -> m128i {
     unsafe { transmute(__lsx_vfcmp_sune_s(transmute(a), transmute(b))) }
 }
 
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn lsx_vfcmp_sun_s(a: m128, b: m128) -> m128i {
diff --git a/crates/core_arch/src/loongarch_shared/mod.rs b/crates/core_arch/src/loongarch_shared/mod.rs
index b2a67fb609..948c98df61 100644
--- a/crates/core_arch/src/loongarch_shared/mod.rs
+++ b/crates/core_arch/src/loongarch_shared/mod.rs
@@ -210,7 +210,7 @@ pub unsafe fn syscall<const IMM15: i32>() {
 }
 
 /// Calculate the approximate single-precision result of 1.0 divided
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frecipe_s(a: f32) -> f32 {
@@ -218,7 +218,7 @@ pub fn frecipe_s(a: f32) -> f32 {
 }
 
 /// Calculate the approximate double-precision result of 1.0 divided
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frecipe_d(a: f64) -> f64 {
@@ -226,7 +226,7 @@ pub fn frecipe_d(a: f64) -> f64 {
 }
 
 /// Calculate the approximate single-precision result of dividing 1.0 by the square root
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frsqrte_s(a: f32) -> f32 {
@@ -234,7 +234,7 @@ pub fn frsqrte_s(a: f32) -> f32 {
 }
 
 /// Calculate the approximate double-precision result of dividing 1.0 by the square root
-#[inline(always)]
+#[inline]
 #[target_feature(enable = "frecipe")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn frsqrte_d(a: f64) -> f64 {
diff --git a/crates/stdarch-gen-loongarch/src/main.rs b/crates/stdarch-gen-loongarch/src/main.rs
index 8bdee521a3..8c4d4e13ec 100644
--- a/crates/stdarch-gen-loongarch/src/main.rs
+++ b/crates/stdarch-gen-loongarch/src/main.rs
@@ -618,7 +618,7 @@ fn gen_bind_body(
     let function = if !rustc_legacy_const_generics.is_empty() {
         format!(
             r#"
-#[inline(always)]{target_feature}
+#[inline]{target_feature}
 #[{rustc_legacy_const_generics}]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 {fn_decl}{{
@@ -630,7 +630,7 @@ fn gen_bind_body(
     } else {
         format!(
             r#"
-#[inline(always)]{target_feature}
+#[inline]{target_feature}
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 {fn_decl}{{
     {call_params}

From 122a23467e0fe33c64c8a68996616db49f4805a6 Mon Sep 17 00:00:00 2001
From: James Barford-Evans <james.barford-evans@arm.com>
Date: Wed, 6 May 2026 16:39:21 +0100
Subject: [PATCH 275/326] remove `target_feature_inline_always` from lib.rs

---
 crates/core_arch/src/lib.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/crates/core_arch/src/lib.rs b/crates/core_arch/src/lib.rs
index 58a6849ad5..b9d63b4497 100644
--- a/crates/core_arch/src/lib.rs
+++ b/crates/core_arch/src/lib.rs
@@ -33,7 +33,6 @@
     x86_amx_intrinsics,
     f16,
     aarch64_unstable_target_feature,
-    target_feature_inline_always,
     funnel_shifts,
     avx10_target_feature,
     const_trait_impl,

From ed16937694fcd5c8b0ead6b7ead0c06411b3760a Mon Sep 17 00:00:00 2001
From: James Barford-Evans <james.barford-evans@arm.com>
Date: Wed, 6 May 2026 16:53:04 +0100
Subject: [PATCH 276/326] replace more instances of `#[inline(always)]`

---
 crates/core_arch/src/loongarch64/simd.rs | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/simd.rs b/crates/core_arch/src/loongarch64/simd.rs
index 2dedfa7eb9..959e2d0cb6 100644
--- a/crates/core_arch/src/loongarch64/simd.rs
+++ b/crates/core_arch/src/loongarch64/simd.rs
@@ -121,7 +121,7 @@ pub(super) const unsafe fn simd_splat<T: Copy + const SimdExt>(a: i64) -> T {
 
 macro_rules! impl_vv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
         pub fn $name(a: $oty) -> $oty {
@@ -138,7 +138,7 @@ pub(super) use impl_vv;
 
 macro_rules! impl_gv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
         pub fn $name(a: $gty) -> $oty {
@@ -154,7 +154,7 @@ pub(super) use impl_gv;
 
 macro_rules! impl_sv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(0)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -172,7 +172,7 @@ pub(super) use impl_sv;
 
 macro_rules! impl_vvv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
         pub fn $name(a: $oty, b: $oty) -> $oty {
@@ -190,7 +190,7 @@ pub(super) use impl_vvv;
 
 macro_rules! impl_vuv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -205,7 +205,7 @@ macro_rules! impl_vuv {
         }
     };
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -225,7 +225,7 @@ pub(super) use impl_vuv;
 
 macro_rules! impl_vug {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -244,7 +244,7 @@ pub(super) use impl_vug;
 
 macro_rules! impl_vsv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -264,7 +264,7 @@ pub(super) use impl_vsv;
 
 macro_rules! impl_vvvv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]
         pub fn $name(a: $oty, b: $oty, c: $oty) -> $oty {
@@ -283,7 +283,7 @@ pub(super) use impl_vvvv;
 
 macro_rules! impl_vugv {
     ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => {
-        #[inline(always)]
+        #[inline]
         #[target_feature(enable = $ft)]
         #[rustc_legacy_const_generics(1)]
         #[unstable(feature = "stdarch_loongarch", issue = "117427")]

From 1c81407752de2f2c721949eb8e2a297605d7f5ff Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 16:41:06 +0100
Subject: [PATCH 277/326] gen-arm: resolve outdated `big_endian_inverse` todo

Earlier patches added `big_endian_inverse` and used `transmute` instead
of using `vreinterpret` due to an LLVM bug that has since been resolved
---
 .../src/arm_shared/neon/generated.rs          | 488 +-----------------
 .../spec/neon/arm_shared.spec.yml             |  36 +-
 2 files changed, 36 insertions(+), 488 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 84c1a91adf..ce9b236ff5 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -9573,35 +9573,6 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(sdot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x2_t = transmute(c);
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
@@ -9620,49 +9591,15 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 )]
 pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(sdot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x2_t = transmute(c);
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, transmute(c))
+        vdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
@@ -9681,50 +9618,16 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 )]
 pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: int8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(udot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: uint32x2_t = transmute(c);
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, transmute(c))
+        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
@@ -9743,20 +9646,15 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 )]
 pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        vdot_u32(a, b, vreinterpret_u8_u32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
@@ -9775,51 +9673,16 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 )]
 pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(udot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: uint8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint32x2_t = transmute(c);
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
@@ -9831,42 +9694,15 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: int32x4_t = vreinterpretq_s32_s8(c);
     unsafe {
-        let c: int32x4_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(sdot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x16_t =
-            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x4_t = transmute(c);
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        vdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
@@ -9878,45 +9714,16 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: int32x4_t = vreinterpretq_s32_s8(c);
     unsafe {
-        let c: int32x4_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(sdot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: int8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x16_t =
-            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x4_t = transmute(c);
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
@@ -9928,42 +9735,15 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: uint32x4_t = vreinterpretq_u32_u8(c);
     unsafe {
-        let c: uint32x4_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
         vdot_u32(a, b, transmute(c))
     }
 }
 #[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(udot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x16_t =
-            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
@@ -9975,41 +9755,13 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
+    let c: uint32x4_t = vreinterpretq_u32_u8(c);
     unsafe {
-        let c: uint32x4_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
         vdotq_u32(a, b, transmute(c))
     }
 }
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(udot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: uint8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x16_t =
-            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
 #[inline]
@@ -70469,7 +70221,6 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
@@ -70488,48 +70239,15 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 )]
 pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, transmute(c), b)
-    }
-}
-#[doc = "Dot product index form with signed and unsigned integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(sudot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint32x2_t = transmute(c);
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: int32x2_t = vusdot_s32(a, transmute(c), b);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        vusdot_s32(a, vreinterpret_u8_u32(c), b)
     }
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
@@ -70548,45 +70266,11 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 )]
 pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: uint32x2_t = vreinterpret_u32_u8(c);
     unsafe {
-        let c: uint32x2_t = transmute(c);
         let c: uint32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, transmute(c), b)
-    }
-}
-#[doc = "Dot product index form with signed and unsigned integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(sudot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: int8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint32x2_t = transmute(c);
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: int32x4_t = vusdotq_s32(a, transmute(c), b);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        vusdotq_s32(a, vreinterpretq_u8_u32(c), b)
     }
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
@@ -72512,35 +72196,6 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(usdot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x2_t = transmute(c);
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
@@ -72559,20 +72214,15 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 )]
 pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x2_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        vusdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
@@ -72591,51 +72241,16 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 )]
 pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
+    let c: int32x2_t = vreinterpret_s32_s8(c);
     unsafe {
-        let c: int32x2_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(usdot, LANE = 0)
-)]
-#[rustc_legacy_const_generics(3)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: uint8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x2_t = transmute(c);
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
@@ -72650,61 +72265,12 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
     unsafe {
         let c: int32x4_t = transmute(c);
         let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(usdot, LANE = 3)
-)]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x16_t =
-            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int32x4_t = transmute(c);
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        vusdot_s32(a, b, vreinterpret_s8_s32(c))
     }
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(usdot, LANE = 3)
-)]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x4_t = transmute(c);
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, transmute(c))
-    }
-}
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline]
-#[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
@@ -72717,16 +72283,10 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: uint8x16_t =
-            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: int8x16_t =
-            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let c: int32x4_t = transmute(c);
         let c: int32x4_t =
             simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
     }
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 7b8ddf4374..bfc8033fdd 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6168,7 +6168,6 @@ intrinsics:
       - *neon-unstable-i8mm
       - *neon-cfg-arm-unstable
     static_defs: ["const LANE: i32"]
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     safety: safe
     types:
       - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]','']
@@ -6178,12 +6177,12 @@ intrinsics:
       - Let:
           - c
           - int32x2_t
-          - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_s32_s8', [c]]
+          - FnCall: ['vreinterpret_s32_s8', [c]]
       - Let:
           - c
           - "{type[1]}"
           - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: [transmute, [c]]}]] #'vreinterpret{type[4]}_s8_s32'
+      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
 
   - name: "vsudot{neon_type[0].lane_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -6198,7 +6197,6 @@ intrinsics:
       - *neon-unstable-i8mm
       - *neon-cfg-arm-unstable
     static_defs: ["const LANE: i32"]
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     safety: safe
     types:
       - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t,'']
@@ -6208,7 +6206,7 @@ intrinsics:
       - Let:
           - c
           - uint32x2_t
-          - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_u32_u8', [c]]
+          - FnCall: ['vreinterpret_u32_u8', [c]]
       - Let:
           - c
           - "{type[4]}"
@@ -6216,7 +6214,7 @@ intrinsics:
       - FnCall: 
           - "vusdot{neon_type[0].no}"
           - - a
-            - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_u8_u32', [c]]
+            - FnCall: ['vreinterpret{type[5]}_u8_u32', [c]]
             - b
 
   - name: "vmul{neon_type[1].no}"
@@ -6968,7 +6966,6 @@ intrinsics:
     doc: "Dot product index form with unsigned and signed integers"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     attr:
       - *neon-v8
       - *neon-i8mm
@@ -6985,8 +6982,7 @@ intrinsics:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
       - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}]
       - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]]
-      #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] 
+      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] 
 
   - name: "vsudot{neon_type[0].laneq_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -7025,7 +7021,6 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     static_defs: ["const LANE: i32"]
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     attr:
       - *neon-v8
       - FnCall: [target_feature, ['enable = "neon,dotprod"']]
@@ -7042,8 +7037,7 @@ intrinsics:
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
-          #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7052,15 +7046,13 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
-            #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vdot{neon_type[0].laneq_nox}"
     doc: Dot product arithmetic (indexed)
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     static_defs: ["const LANE: i32"]
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     attr:
       - *neon-v8
       - FnCall: [target_feature, ['enable = "neon,dotprod"']]
@@ -7077,8 +7069,7 @@ intrinsics:
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
-          #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7088,7 +7079,6 @@ intrinsics:
           - - a
             - b
             - FnCall: [transmute, [c]]
-            #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vdot{neon_type[0].no}"
     doc: Dot product arithmetic (vector)
@@ -7151,7 +7141,6 @@ intrinsics:
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]]
       - *neon-cfg-arm-unstable
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     safety: safe
     types:
       - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]','']
@@ -7161,7 +7150,7 @@ intrinsics:
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]]
+          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7170,7 +7159,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vdot{neon_type[0].lane_nox}"
     doc: Dot product arithmetic (indexed)
@@ -7186,7 +7175,6 @@ intrinsics:
       - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]]
       - *neon-cfg-arm-unstable
     safety: safe
-    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
     types:
       - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]','']
       - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
@@ -7195,7 +7183,7 @@ intrinsics:
       - Let:
           - c
           - "{neon_type[3]}"
-          - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
       - Let:
           - c
           - "{neon_type[0]}"
@@ -7204,7 +7192,7 @@ intrinsics:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
 
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)

From 6654a2626be997f124befff4fda5bcffd319d8be Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 278/326] gen-arm: use `neon-stable` anchor throughout

Instead of duplicating the stability attribute, re-use the `neon-stable`
anchor through
---
 .../spec/neon/aarch64.spec.yml                | 620 +++++++++---------
 1 file changed, 306 insertions(+), 314 deletions(-)

diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index e37f9f124b..e40775d68a 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -245,11 +245,7 @@ intrinsics:
     doc: Signed Absolute difference Long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr:
-      - FnCall:
-          - stable
-          - - 'feature = "neon_intrinsics"'
-            - 'since = "1.59.0"'
+    attr: [*neon-stable]
     assert_instr: [sabdl2]
     safety: safe
     types:
@@ -288,11 +284,7 @@ intrinsics:
     doc: Signed Absolute difference Long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr:
-      - FnCall:
-          - stable
-          - - 'feature = "neon_intrinsics"'
-            - 'since = "1.59.0"'
+    attr: [*neon-stable]
     assert_instr: [sabdl2]
     safety: safe
     types:
@@ -333,7 +325,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint64x1_t, uint64x1_t]
@@ -351,7 +343,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -365,7 +357,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -407,7 +399,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64", "s64"]
@@ -426,7 +418,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)']
@@ -444,7 +436,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tst]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64", "s64"]
@@ -463,7 +455,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_s32", "i32", "u32"]
@@ -481,7 +473,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["b_s8", "i8", "u8", "s8"]
@@ -501,7 +493,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fabs]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float64x1_t
@@ -515,7 +507,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int64x1_t, uint64x1_t]
@@ -529,7 +521,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - uint64x1_t
@@ -543,7 +535,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -557,7 +549,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -599,7 +591,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int64x1_t, uint64x1_t]
@@ -613,7 +605,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int64x1_t, uint64x1_t]
@@ -627,7 +619,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -641,7 +633,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -683,7 +675,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int64x1_t, uint64x1_t]
@@ -697,7 +689,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)']
@@ -718,7 +710,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64"]
@@ -735,7 +727,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmle]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)']
@@ -759,7 +751,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmle]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)']
@@ -779,7 +771,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -818,7 +810,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmlt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)']
@@ -842,7 +834,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmlt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)']
@@ -862,7 +854,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -901,7 +893,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [asr]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64"]
@@ -918,7 +910,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -936,7 +928,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32", i32]
@@ -975,7 +967,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -993,7 +985,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32", i32]
@@ -1033,7 +1025,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -1047,7 +1039,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -1076,7 +1068,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -1090,7 +1082,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -1119,7 +1111,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int64x1_t, float64x1_t]
@@ -1133,7 +1125,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "i32", "f32", s32]
@@ -1147,7 +1139,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint64x1_t, float64x1_t]
@@ -1161,7 +1153,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u32", "f32", "s_f32"]
@@ -1176,7 +1168,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1314,7 +1306,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1340,7 +1332,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1365,7 +1357,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1389,7 +1381,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "i32", "s_s32_f32", "32"]
@@ -1403,7 +1395,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", "s_u32_f32"]
@@ -1488,7 +1480,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, float64x2_t]
@@ -1501,7 +1493,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x4_t, float64x2_t]
@@ -1556,7 +1548,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x2_t, float32x2_t]
@@ -1569,7 +1561,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, float64x2_t, float32x4_t]
@@ -1586,7 +1578,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x2_t, float32x2_t]
@@ -1603,7 +1595,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f64", "f32"]
@@ -1621,7 +1613,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, float64x2_t, float32x4_t]
@@ -1639,7 +1631,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1662,7 +1654,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1756,7 +1748,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1779,7 +1771,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -1801,7 +1793,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, int32x2_t, _s32_f32]
@@ -1842,7 +1834,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "i32", 's_s32_f32']
@@ -1935,7 +1927,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", 's_u32_f32']
@@ -1953,7 +1945,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, int32x2_t]
@@ -1973,7 +1965,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "i32", 's_s32_f32']
@@ -2106,7 +2098,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, int32x2_t]
@@ -2169,7 +2161,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "i32", 's_s32_f32']
@@ -2187,7 +2179,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, int32x2_t]
@@ -2207,7 +2199,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "i32", 's_s32_f32']
@@ -2225,7 +2217,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t]
@@ -2245,7 +2237,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", 's_u32_f32']
@@ -2263,7 +2255,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t]
@@ -2283,7 +2275,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", s_u32_f32]
@@ -2301,7 +2293,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t]
@@ -2321,7 +2313,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", s_u32_f32, 'i32']
@@ -2458,7 +2450,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2475,7 +2467,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2492,7 +2484,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2509,7 +2501,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2527,7 +2519,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2546,7 +2538,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2567,7 +2559,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 4']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2627,7 +2619,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 8']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2645,7 +2637,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2666,7 +2658,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ext, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -2682,7 +2674,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float64x1_t
@@ -2696,7 +2688,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -2713,7 +2705,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -2736,7 +2728,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -2759,7 +2751,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -6869,7 +6861,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, "f32"]
@@ -6887,7 +6879,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmv]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x4_t, "f32"]
@@ -7102,7 +7094,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i16", "i32"]
@@ -7117,7 +7109,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i32", "i64"]
@@ -7134,7 +7126,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]']
@@ -7150,7 +7142,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int16x8_t, "i16", int32x4_t, int16x4_t, '[4, 5, 6, 7]']
@@ -7167,7 +7159,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7185,7 +7177,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, N = 4]]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7202,7 +7194,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7219,7 +7211,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7238,7 +7230,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7256,7 +7248,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7274,7 +7266,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 4']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7291,7 +7283,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7307,7 +7299,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16]
@@ -7324,7 +7316,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7342,7 +7334,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i32", "i16", "s16"]
@@ -7356,7 +7348,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "i32", "i32", "i64"]
@@ -7371,7 +7363,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -7390,7 +7382,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7406,7 +7398,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7421,7 +7413,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16]
@@ -7438,7 +7430,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7456,7 +7448,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i32", "i16"]
@@ -7470,7 +7462,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "i32", "i32", "i64"]
@@ -7485,7 +7477,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -7504,7 +7496,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7520,7 +7512,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7535,7 +7527,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i16", "i16", "i16", int16x4_t, 'h_s16']
@@ -7552,7 +7544,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7570,7 +7562,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7587,7 +7579,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -7602,7 +7594,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -7617,7 +7609,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i16", "i8", 'h_s16', s16]
@@ -7631,7 +7623,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u16", "u8", 'h_u16', 'u16']
@@ -7645,7 +7637,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "i32"]
@@ -7662,7 +7654,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u64", "u32"]
@@ -7679,7 +7671,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i16", "u8", 'h_s16', s16]
@@ -7694,7 +7686,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8_t, int16x8_t, uint8x16_t, s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -7709,7 +7701,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i16", 'h_s16', 's16']
@@ -7724,7 +7716,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh, LANE = 1]]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -7910,7 +7902,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ['s_s32', "i32"]
@@ -7928,7 +7920,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i8", 'b_s8', int8x8_t, s8]
@@ -7944,7 +7936,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u32", "i32", 's_u32']
@@ -7962,7 +7954,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u8", "i8", "b_u8", uint8x8_t, int8x8_t, s8]
@@ -7979,7 +7971,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -7998,7 +7990,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8016,7 +8008,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8035,7 +8027,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8059,7 +8051,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8086,7 +8078,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8109,7 +8101,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - i64
@@ -8126,7 +8118,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [b_s8, "i8", int8x8_t]
@@ -8149,7 +8141,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8172,7 +8164,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u64", "i64"]
@@ -8189,7 +8181,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [b_u8, "u8", "i8", uint8x8_t, int8x8_t]
@@ -8212,7 +8204,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8234,7 +8226,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8258,7 +8250,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8280,7 +8272,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8302,7 +8294,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8326,7 +8318,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8348,7 +8340,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8370,7 +8362,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8393,7 +8385,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8414,7 +8406,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [b_u8, "u8", "i8", s8]
@@ -8434,7 +8426,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [s_u32, "u32", "i32"]
@@ -8452,7 +8444,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float32x2_t
@@ -8499,7 +8491,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [_f64, float64x1_t, v1f64]
@@ -8517,7 +8509,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [s_f32, "f32"]
@@ -8556,7 +8548,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [_f64, float64x1_t, v1f64]
@@ -8574,7 +8566,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [s_f32, "f32"]
@@ -8613,7 +8605,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [_f64, float64x1_t, v1f64]
@@ -8631,7 +8623,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [s_f32, "f32"]
@@ -8670,7 +8662,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [s_f32, "f32"]
@@ -8802,7 +8794,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - "i64"
@@ -8819,7 +8811,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u64", "i64"]
@@ -8837,7 +8829,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8853,7 +8845,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8869,7 +8861,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -8894,7 +8886,7 @@ intrinsics:
     attr:
       - *little-endian
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -8917,7 +8909,7 @@ intrinsics:
     attr:
       - *big-endian
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -8940,7 +8932,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
@@ -8965,7 +8957,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
@@ -8990,7 +8982,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
@@ -9019,7 +9011,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
@@ -9045,7 +9037,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
@@ -9066,7 +9058,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
@@ -9083,7 +9075,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u64", float64x1_t]
@@ -9097,7 +9089,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -9113,7 +9105,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -9128,7 +9120,7 @@ intrinsics:
     return_type: "{type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - "i64"
@@ -9146,7 +9138,7 @@ intrinsics:
     return_type: "{type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["u64", "i64"]
@@ -9165,7 +9157,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -9184,7 +9176,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -9203,7 +9195,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -10011,7 +10003,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal2]]}]]
     safety: safe
     types:
@@ -10164,7 +10156,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float32x2_t
@@ -10182,7 +10174,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -10205,7 +10197,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -10229,7 +10221,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -10256,7 +10248,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10350,7 +10342,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10370,7 +10362,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10390,7 +10382,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10410,7 +10402,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10429,7 +10421,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10502,7 +10494,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float64x1_t
@@ -10516,7 +10508,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float64x2_t
@@ -10530,7 +10522,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float64x1_t
@@ -10545,7 +10537,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10565,7 +10557,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10581,7 +10573,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10597,7 +10589,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10613,7 +10605,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -10631,7 +10623,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t, 'f32x2', 'f32x2::new(0.0, 0.0)']
@@ -10665,7 +10657,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", "s_f32"]
@@ -10704,7 +10696,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64", "s64"]
@@ -10722,7 +10714,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)']
@@ -10750,7 +10742,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8_t, uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)']
@@ -10774,7 +10766,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - uint64x1_t
@@ -10788,7 +10780,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -10830,7 +10822,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -10844,7 +10836,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["d_s64", "i64", "u64", s64]
@@ -10863,7 +10855,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - uint64x1_t
@@ -10877,7 +10869,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s64", "i64", "u64"]
@@ -10896,7 +10888,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint64x1_t, u64x1, 'u64x1::new(0)']
@@ -10912,7 +10904,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)']
@@ -10932,7 +10924,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -10972,7 +10964,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64"]
@@ -10987,7 +10979,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64", 's64']
@@ -11006,7 +10998,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)']
@@ -11030,7 +11022,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["i64", "u64"]
@@ -11047,7 +11039,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)']
@@ -11064,7 +11056,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32", "u32"]
@@ -11103,7 +11095,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -11121,7 +11113,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, "f64"]
@@ -11139,7 +11131,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11160,7 +11152,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11179,7 +11171,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11196,7 +11188,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11217,7 +11209,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11277,7 +11269,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11318,7 +11310,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -11334,7 +11326,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int32x4_t, int16x8_t, "i16"]
@@ -11348,7 +11340,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint32x4_t, uint16x8_t, "u16"]
@@ -11363,7 +11355,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11386,7 +11378,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11408,7 +11400,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, uint64x1_t]
@@ -11422,7 +11414,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["f32", "u32", 's_f32']
@@ -11464,7 +11456,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -11481,7 +11473,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, "f64"]
@@ -11498,7 +11490,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x2_t, "f64"]
@@ -11539,7 +11531,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ['s_f32', float32x2_t, "f32"]
@@ -11557,7 +11549,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ['s_f32', float32x2_t, "f32"]
@@ -11575,7 +11567,7 @@ intrinsics:
     return_type: "{type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s64", "i64", "u64"]
@@ -11595,7 +11587,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11617,7 +11609,7 @@ intrinsics:
     arguments: ["a: {type[0]}"]
     return_type: "{type[0]}"
     attr:
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]]
     safety: safe
     types:
@@ -11634,7 +11626,7 @@ intrinsics:
     arguments: ["a: {type[0]}"]
     return_type: "{type[0]}"
     attr:
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
       - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]]
     safety: safe
     types:
@@ -11653,7 +11645,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int16x8_t, "i16", int32x4_t]
@@ -11670,7 +11662,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint16x8_t, "u16", uint32x4_t]
@@ -11688,7 +11680,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11710,7 +11702,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -11731,7 +11723,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float64x1_t
@@ -11749,7 +11741,7 @@ intrinsics:
     return_type: "{type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["s_f32", "f32"]
@@ -11788,7 +11780,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - float32x2_t
@@ -11808,7 +11800,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshlu, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -11831,7 +11823,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float32x2_t, uint32x2_t]
@@ -11873,7 +11865,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [float64x1_t, int64x1_t]
@@ -11964,7 +11956,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int32x4_t, int16x8_t, "i16"]
@@ -11982,7 +11974,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint32x4_t, uint16x8_t, "u16"]
@@ -12001,7 +11993,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -12020,7 +12012,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const LANE: i32']
     safety: safe
     types:
@@ -12039,7 +12031,7 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     static_defs: ['const N: i32']
     safety: safe
     types:
@@ -12055,7 +12047,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - uint64x1_t
@@ -12069,7 +12061,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -12092,7 +12084,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -12109,7 +12101,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "neon,aes"']]
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -12125,7 +12117,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, int8x8x4_t]
@@ -12147,7 +12139,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12173,7 +12165,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, 'int8x8_t', 'unsafe {{ transmute(b) }}']
@@ -12194,7 +12186,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8x2_t, 'int8x8_t']
@@ -12215,7 +12207,7 @@ intrinsics:
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12240,7 +12232,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8x3_t, 'int8x8_t', 'int8x16x2']
@@ -12265,7 +12257,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t']
@@ -12292,7 +12284,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8x4_t, 'int8x8_t', 'int8x16x2']
@@ -12317,7 +12309,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t']
@@ -12344,7 +12336,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, int8x16_t, uint8x8_t, vqtbx1]
@@ -12358,7 +12350,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8_t, "uint8x16_t", uint8x8_t, "vqtbx1", "_u8"]
@@ -12381,7 +12373,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, "int8x8_t", "transmute(c)", "i8x8::splat(8)", "int8x8"]
@@ -12411,7 +12403,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, 'int8x8x2_t']
@@ -12430,7 +12422,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12453,7 +12445,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'i8x8::splat(24)', 'int8x8']
@@ -12488,7 +12480,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8']
@@ -12525,7 +12517,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ['int8x16_t', uint8x8_t, 'vqtbl1', 'int8x8_t']
@@ -12539,7 +12531,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ['uint8x16_t', uint8x8_t, 'vqtbl1', 'uint8x8_t']
@@ -12561,7 +12553,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ['int8x16x2_t', uint8x8_t, 'vqtbl2', 'int8x8_t']
@@ -12575,7 +12567,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12598,7 +12590,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, 'int8x16x2_t', uint8x8_t, 'vqtbx2']
@@ -12612,7 +12604,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12636,7 +12628,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12651,7 +12643,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12675,7 +12667,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, 'int8x16x3_t', uint8x8_t, 'vqtbx3']
@@ -12689,7 +12681,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12714,7 +12706,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12729,7 +12721,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12754,7 +12746,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [int8x8_t, 'int8x16x4_t', uint8x8_t, 'vqtbx4']
@@ -12768,7 +12760,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12795,7 +12787,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["vqtbl1", "int8x16_t", "uint8x8_t", "int8x8_t"]
@@ -12814,7 +12806,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - ["vqtbl2", "int8x16_t", "uint8x8_t", "int8x8_t"]
@@ -12833,7 +12825,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12853,7 +12845,7 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     big_endian_inverse: false
     safety: safe
     types:
@@ -12873,7 +12865,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [vqtbx1, "int8x8_t", "int8x16_t", "uint8x8_t"]
@@ -12892,7 +12884,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [vqtbx2, "int8x8_t", "int8x16_t", "uint8x8_t"]
@@ -12911,7 +12903,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [vqtbx3, "int8x8_t", "int8x16_t", "uint8x8_t"]
@@ -12930,7 +12922,7 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety: safe
     types:
       - [vqtbx4, "int8x8_t", "int8x16_t", "uint8x8_t"]
@@ -12949,7 +12941,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "{type[2]}"']]
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldr]]}]]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:
@@ -13016,7 +13008,7 @@ intrinsics:
       - FnCall: [target_feature, ['enable = "{type[2]}"']]
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [str]]}]]
       - FnCall: [allow, ['clippy::cast_ptr_alignment']]
-      - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      - *neon-stable
     safety:
       unsafe: [neon]
     types:

From 8075df71f7ca3f8b3ba0343313627a22ec979226 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Fri, 1 May 2026 12:26:25 +0100
Subject: [PATCH 279/326] gen-arm: skip `assert_instr` on big-endian

Some intrinsics optimise to different instructions on big endian which
leads to `assert_instr` failing
---
 .../core_arch/src/aarch64/neon/generated.rs   | 1323 ++++++++++++-----
 .../src/arm_shared/neon/generated.rs          |  240 ++-
 .../spec/neon/aarch64.spec.yml                |  238 +--
 .../spec/neon/arm_shared.spec.yml             |   30 +-
 4 files changed, 1297 insertions(+), 534 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 898ccfc9ed..8e3493dfac 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -65,7 +65,10 @@ pub fn __jcvt(a: f64) -> i32 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(sabal2)
+)]
 pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
     unsafe {
         let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -80,7 +83,10 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(sabal2)
+)]
 pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     unsafe {
         let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -95,7 +101,10 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(sabal2)
+)]
 pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     unsafe {
         let d: int32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -110,7 +119,10 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uabal2)
+)]
 pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
     unsafe {
         let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -124,7 +136,10 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uabal2)
+)]
 pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
     unsafe {
         let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -138,7 +153,10 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uabal2)
+)]
 pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
     unsafe {
         let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -212,7 +230,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sabdl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
 pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -226,7 +244,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sabdl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
 pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -240,7 +258,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sabdl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
 pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -253,8 +271,8 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
 pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
         let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -266,8 +284,8 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
 pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
         let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -279,8 +297,8 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
 pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
         let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -4092,7 +4110,10 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
@@ -4113,7 +4134,10 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
@@ -4137,7 +4161,10 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
@@ -4157,7 +4184,10 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
@@ -4175,7 +4205,10 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
@@ -4199,7 +4232,10 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
@@ -4222,7 +4258,10 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
@@ -4243,7 +4282,10 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
@@ -4267,7 +4309,10 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
@@ -4290,7 +4335,10 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
@@ -4312,7 +4360,10 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
@@ -4338,7 +4389,10 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
@@ -4362,7 +4416,10 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
@@ -4384,7 +4441,10 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
@@ -4413,7 +4473,10 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
@@ -4437,7 +4500,10 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
@@ -4459,7 +4525,10 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
@@ -4488,7 +4557,10 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
@@ -4536,7 +4608,10 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 1, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
@@ -4558,7 +4633,10 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 1, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
@@ -4580,7 +4658,10 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 1, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
@@ -4602,7 +4683,10 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 1, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
@@ -4624,7 +4708,10 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
@@ -4994,7 +5081,10 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
@@ -5022,7 +5112,10 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
@@ -5046,7 +5139,10 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
@@ -5419,7 +5515,10 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
@@ -5447,7 +5546,10 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
@@ -5471,7 +5573,10 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
@@ -5844,7 +5949,10 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
@@ -5872,7 +5980,10 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
@@ -5895,7 +6006,10 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
@@ -5916,7 +6030,10 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
@@ -6287,7 +6404,10 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
@@ -6314,7 +6434,10 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
@@ -6337,7 +6460,10 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
@@ -6358,7 +6484,10 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
@@ -6729,7 +6858,10 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
@@ -6756,7 +6888,10 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
@@ -6779,7 +6914,10 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
@@ -6800,7 +6938,10 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
@@ -7171,7 +7312,10 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
@@ -7198,7 +7342,10 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
+#[cfg_attr(
+    all(test, target_endian = "little"),
+    assert_instr(mov, LANE1 = 0, LANE2 = 0)
+)]
 #[rustc_legacy_const_generics(1, 3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
@@ -7228,7 +7375,7 @@ pub fn vcreate_f64(a: u64) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtn))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
     unsafe { simd_cast(a) }
@@ -7282,7 +7429,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
@@ -7292,7 +7439,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
@@ -7302,7 +7449,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) }
@@ -7311,7 +7458,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
     unsafe {
@@ -9459,7 +9606,7 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtxn))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -9475,7 +9622,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtxn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) }
@@ -10260,7 +10407,7 @@ pub fn vfma_lane_f64<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfma_laneq_f64<const LANE: i32>(
@@ -10327,7 +10474,7 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
 #[inline]
-#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10342,7 +10489,7 @@ pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
 #[inline]
-#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10391,7 +10538,7 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
@@ -10405,7 +10552,7 @@ pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
@@ -10419,7 +10566,7 @@ pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
@@ -11015,7 +11162,7 @@ pub fn vfms_lane_f64<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfms_laneq_f64<const LANE: i32>(
@@ -11068,7 +11215,7 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"]
 #[inline]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11083,7 +11230,7 @@ pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
 #[inline]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11135,7 +11282,7 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
@@ -11145,7 +11292,7 @@ pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
@@ -11155,7 +11302,7 @@ pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
@@ -11165,7 +11312,7 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
@@ -14210,7 +14357,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -14221,7 +14368,7 @@ pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_laneq_s16<const LANE: i32>(
@@ -14236,7 +14383,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -14247,7 +14394,7 @@ pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_laneq_s32<const LANE: i32>(
@@ -14262,7 +14409,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_u16<const LANE: i32>(
@@ -14277,7 +14424,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_laneq_u16<const LANE: i32>(
@@ -14292,7 +14439,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_u32<const LANE: i32>(
@@ -14307,7 +14454,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_laneq_u32<const LANE: i32>(
@@ -14322,7 +14469,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
     vmlal_high_s16(a, b, vdupq_n_s16(c))
@@ -14331,7 +14478,7 @@ pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
     vmlal_high_s32(a, b, vdupq_n_s32(c))
@@ -14340,7 +14487,7 @@ pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
     vmlal_high_u16(a, b, vdupq_n_u16(c))
@@ -14349,7 +14496,7 @@ pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
     vmlal_high_u32(a, b, vdupq_n_u32(c))
@@ -14358,7 +14505,7 @@ pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
     unsafe {
@@ -14371,7 +14518,7 @@ pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     unsafe {
@@ -14384,7 +14531,7 @@ pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     unsafe {
@@ -14397,7 +14544,7 @@ pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
     unsafe {
@@ -14410,7 +14557,7 @@ pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
     unsafe {
@@ -14423,7 +14570,7 @@ pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
     unsafe {
@@ -14454,7 +14601,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -14465,7 +14612,7 @@ pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_laneq_s16<const LANE: i32>(
@@ -14480,7 +14627,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -14491,7 +14638,7 @@ pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_laneq_s32<const LANE: i32>(
@@ -14506,7 +14653,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_u16<const LANE: i32>(
@@ -14521,7 +14668,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_laneq_u16<const LANE: i32>(
@@ -14536,7 +14683,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_u32<const LANE: i32>(
@@ -14551,7 +14698,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_laneq_u32<const LANE: i32>(
@@ -14566,7 +14713,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
     vmlsl_high_s16(a, b, vdupq_n_s16(c))
@@ -14575,7 +14722,7 @@ pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
     vmlsl_high_s32(a, b, vdupq_n_s32(c))
@@ -14584,7 +14731,7 @@ pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
     vmlsl_high_u16(a, b, vdupq_n_u16(c))
@@ -14593,7 +14740,7 @@ pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
     vmlsl_high_u32(a, b, vdupq_n_u32(c))
@@ -14602,7 +14749,7 @@ pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
     unsafe {
@@ -14615,7 +14762,7 @@ pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     unsafe {
@@ -14628,7 +14775,7 @@ pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     unsafe {
@@ -14641,7 +14788,7 @@ pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
     unsafe {
@@ -14654,7 +14801,7 @@ pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
     unsafe {
@@ -14667,7 +14814,7 @@ pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
     unsafe {
@@ -14681,7 +14828,7 @@ pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sxtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
 pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
     unsafe {
         let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -14693,7 +14840,7 @@ pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sxtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
 pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
     unsafe {
         let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -14705,7 +14852,7 @@ pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sxtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
 pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
     unsafe {
         let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -14717,7 +14864,7 @@ pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(uxtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
 pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
     unsafe {
         let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -14729,7 +14876,7 @@ pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(uxtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
 pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
     unsafe {
         let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -14741,7 +14888,7 @@ pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(uxtl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
 pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
     unsafe {
         let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -14753,7 +14900,7 @@ pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(xtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
     unsafe {
         let c: int8x8_t = simd_cast(b);
@@ -14765,7 +14912,7 @@ pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(xtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
     unsafe {
         let c: int16x4_t = simd_cast(b);
@@ -14777,7 +14924,7 @@ pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(xtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
     unsafe {
         let c: int32x2_t = simd_cast(b);
@@ -14789,7 +14936,7 @@ pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(xtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
     unsafe {
         let c: uint8x8_t = simd_cast(b);
@@ -14801,7 +14948,7 @@ pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(xtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
     unsafe {
         let c: uint16x4_t = simd_cast(b);
@@ -14813,7 +14960,7 @@ pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(xtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
     unsafe {
         let c: uint32x2_t = simd_cast(b);
@@ -14960,7 +15107,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
@@ -14971,7 +15118,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
@@ -14982,7 +15129,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
@@ -14993,7 +15140,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
@@ -15004,7 +15151,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t {
@@ -15015,7 +15162,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
@@ -15026,7 +15173,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t {
@@ -15037,7 +15184,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
@@ -15048,7 +15195,7 @@ pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> ui
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
     vmull_high_s16(a, vdupq_n_s16(b))
@@ -15057,7 +15204,7 @@ pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(smull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
     vmull_high_s32(a, vdupq_n_s32(b))
@@ -15066,7 +15213,7 @@ pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
     vmull_high_u16(a, vdupq_n_u16(b))
@@ -15075,7 +15222,7 @@ pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(umull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
     vmull_high_u32(a, vdupq_n_u32(b))
@@ -15085,7 +15232,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(pmull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
 pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
     unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) }
 }
@@ -15094,7 +15241,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(pmull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
 pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
     unsafe {
         let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -15107,7 +15254,7 @@ pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(smull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -15120,7 +15267,7 @@ pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(smull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -15133,7 +15280,7 @@ pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(smull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -15146,7 +15293,7 @@ pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(umull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
         let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -15159,7 +15306,7 @@ pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(umull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
         let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -15172,7 +15319,7 @@ pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(umull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
         let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -16684,7 +16831,7 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -16695,7 +16842,7 @@ pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
@@ -16706,7 +16853,7 @@ pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -16717,7 +16864,7 @@ pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
@@ -16728,7 +16875,7 @@ pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
     vqaddq_s32(a, vqdmull_high_n_s16(b, c))
@@ -16737,7 +16884,7 @@ pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     vqaddq_s32(a, vqdmull_high_s16(b, c))
@@ -16746,7 +16893,7 @@ pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
     vqaddq_s64(a, vqdmull_high_n_s32(b, c))
@@ -16755,7 +16902,7 @@ pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     vqaddq_s64(a, vqdmull_high_s32(b, c))
@@ -16764,7 +16911,7 @@ pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 2))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
@@ -16775,7 +16922,7 @@ pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlal, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
@@ -16850,7 +16997,7 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -16861,7 +17008,7 @@ pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
@@ -16872,7 +17019,7 @@ pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -16883,7 +17030,7 @@ pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
@@ -16894,7 +17041,7 @@ pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
     vqsubq_s32(a, vqdmull_high_n_s16(b, c))
@@ -16903,7 +17050,7 @@ pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     vqsubq_s32(a, vqdmull_high_s16(b, c))
@@ -16912,7 +17059,7 @@ pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
     vqsubq_s64(a, vqdmull_high_n_s32(b, c))
@@ -16921,7 +17068,7 @@ pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     vqsubq_s64(a, vqdmull_high_s32(b, c))
@@ -16930,7 +17077,7 @@ pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 2))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
@@ -16941,7 +17088,7 @@ pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmlsl, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 1))]
 #[rustc_legacy_const_generics(3)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
@@ -17138,7 +17285,7 @@ pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
@@ -17153,7 +17300,7 @@ pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
@@ -17168,7 +17315,7 @@ pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2, N = 1))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 1))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
@@ -17183,7 +17330,7 @@ pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2, N = 4))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 4))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
@@ -17198,7 +17345,7 @@ pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
     unsafe {
@@ -17211,7 +17358,7 @@ pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
     unsafe {
@@ -17224,7 +17371,7 @@ pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
@@ -17237,7 +17384,7 @@ pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqdmull2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
@@ -17361,7 +17508,7 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqxtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
     unsafe {
@@ -17376,7 +17523,7 @@ pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqxtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -17385,7 +17532,7 @@ pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqxtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) }
@@ -17394,7 +17541,7 @@ pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqxtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
     unsafe {
@@ -17409,7 +17556,7 @@ pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqxtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -17418,7 +17565,7 @@ pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqxtn2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) }
@@ -17495,7 +17642,7 @@ pub fn vqmovns_u32(a: u32) -> u16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqxtun2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
     unsafe {
@@ -17510,7 +17657,7 @@ pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqxtun2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -17519,7 +17666,7 @@ pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqxtun2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) }
@@ -18281,7 +18428,7 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -18298,7 +18445,7 @@ pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -18309,7 +18456,7 @@ pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -18320,7 +18467,7 @@ pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -18337,7 +18484,7 @@ pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -18348,7 +18495,7 @@ pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -18431,7 +18578,7 @@ pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
@@ -18448,7 +18595,7 @@ pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
@@ -18459,7 +18606,7 @@ pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
@@ -18730,7 +18877,7 @@ pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -18747,7 +18894,7 @@ pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -18758,7 +18905,7 @@ pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -18769,7 +18916,7 @@ pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -18786,7 +18933,7 @@ pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -18797,7 +18944,7 @@ pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -18888,7 +19035,7 @@ pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
@@ -18905,7 +19052,7 @@ pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
@@ -18916,7 +19063,7 @@ pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
@@ -22507,7 +22654,7 @@ pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -22524,7 +22671,7 @@ pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -22535,7 +22682,7 @@ pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -22546,7 +22693,7 @@ pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -22563,7 +22710,7 @@ pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -22574,7 +22721,7 @@ pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -23087,7 +23234,7 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sshll2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
@@ -23101,7 +23248,7 @@ pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sshll2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
@@ -23115,7 +23262,7 @@ pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sshll2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
@@ -23129,7 +23276,7 @@ pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(ushll2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
@@ -23143,7 +23290,7 @@ pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(ushll2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
@@ -23157,7 +23304,7 @@ pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(ushll2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
@@ -23171,7 +23318,7 @@ pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(shrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -23188,7 +23335,7 @@ pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(shrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -23199,7 +23346,7 @@ pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(shrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -23210,7 +23357,7 @@ pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(shrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -23227,7 +23374,7 @@ pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(shrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -23238,7 +23385,7 @@ pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(shrn2, N = 2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -25610,7 +25757,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
 pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25625,7 +25772,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
 pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -25640,7 +25787,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
 pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -25655,7 +25802,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
 pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
         let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25670,7 +25817,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
 pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
         let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -25685,7 +25832,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubl2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
 pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
         let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -25700,7 +25847,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubw2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
 pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25712,7 +25859,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubw2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
 pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -25724,7 +25871,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubw2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
 pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let c: int32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -25736,7 +25883,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubw2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
 pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
         let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25748,7 +25895,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubw2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
 pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
         let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -25760,7 +25907,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubw2))]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
 pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
         let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -26094,7 +26241,10 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26104,7 +26254,10 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26113,7 +26266,10 @@ pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26122,7 +26278,10 @@ pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26131,7 +26290,10 @@ pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26140,7 +26302,10 @@ pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26149,7 +26314,10 @@ pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26158,7 +26326,10 @@ pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26167,7 +26338,10 @@ pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26176,7 +26350,10 @@ pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26185,7 +26362,10 @@ pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26194,7 +26374,10 @@ pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26209,7 +26392,10 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26218,7 +26404,10 @@ pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26227,7 +26416,10 @@ pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26236,7 +26428,10 @@ pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26245,7 +26440,10 @@ pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26260,7 +26458,10 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26269,7 +26470,10 @@ pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26278,7 +26482,10 @@ pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26287,7 +26494,10 @@ pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26296,7 +26506,10 @@ pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26311,7 +26524,10 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
 }
@@ -26320,7 +26536,10 @@ pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn1)
+)]
 pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
 }
@@ -26330,7 +26549,10 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26340,7 +26562,10 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26349,7 +26574,10 @@ pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26358,7 +26586,10 @@ pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26367,7 +26598,10 @@ pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26376,7 +26610,10 @@ pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26385,7 +26622,10 @@ pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26394,7 +26634,10 @@ pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26403,7 +26646,10 @@ pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -26412,7 +26658,10 @@ pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26421,7 +26670,10 @@ pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26430,7 +26682,10 @@ pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26445,7 +26700,10 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26454,7 +26712,10 @@ pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26463,7 +26724,10 @@ pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26472,7 +26736,10 @@ pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26481,7 +26748,10 @@ pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26496,7 +26766,10 @@ pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26505,7 +26778,10 @@ pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26514,7 +26790,10 @@ pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26523,7 +26802,10 @@ pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26532,7 +26814,10 @@ pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26547,7 +26832,10 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
 }
@@ -26556,7 +26844,10 @@ pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(trn2)
+)]
 pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
 }
@@ -26840,7 +27131,10 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -26850,7 +27144,10 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -26859,7 +27156,10 @@ pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26868,7 +27168,10 @@ pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26877,7 +27180,10 @@ pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26886,7 +27192,10 @@ pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26895,7 +27204,10 @@ pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26904,7 +27216,10 @@ pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26913,7 +27228,10 @@ pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -26922,7 +27240,10 @@ pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -26931,7 +27252,10 @@ pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -26940,7 +27264,10 @@ pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe {
         simd_shuffle!(
@@ -26955,7 +27282,10 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -26964,7 +27294,10 @@ pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -26973,7 +27306,10 @@ pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -26982,7 +27318,10 @@ pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -26991,7 +27330,10 @@ pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27006,7 +27348,10 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -27015,7 +27360,10 @@ pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -27024,7 +27372,10 @@ pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -27033,7 +27384,10 @@ pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -27042,7 +27396,10 @@ pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27057,7 +27414,10 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
 }
@@ -27066,7 +27426,10 @@ pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp1)
+)]
 pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
 }
@@ -27076,7 +27439,10 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27086,7 +27452,10 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27095,7 +27464,10 @@ pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27104,7 +27476,10 @@ pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27113,7 +27488,10 @@ pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27122,7 +27500,10 @@ pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27131,7 +27512,10 @@ pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27140,7 +27524,10 @@ pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27149,7 +27536,10 @@ pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27158,7 +27548,10 @@ pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27167,7 +27560,10 @@ pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27176,7 +27572,10 @@ pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27191,7 +27590,10 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27200,7 +27602,10 @@ pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27209,7 +27614,10 @@ pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27218,7 +27626,10 @@ pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27227,7 +27638,10 @@ pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27242,7 +27656,10 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27251,7 +27668,10 @@ pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27260,7 +27680,10 @@ pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27269,7 +27692,10 @@ pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27278,7 +27704,10 @@ pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27293,7 +27722,10 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
 }
@@ -27302,7 +27734,10 @@ pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(uzp2)
+)]
 pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
 }
@@ -27330,7 +27765,10 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27340,7 +27778,10 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27349,7 +27790,10 @@ pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27358,7 +27802,10 @@ pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27367,7 +27814,10 @@ pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27376,7 +27826,10 @@ pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27385,7 +27838,10 @@ pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27400,7 +27856,10 @@ pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27409,7 +27868,10 @@ pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27418,7 +27880,10 @@ pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27427,7 +27892,10 @@ pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27436,7 +27904,10 @@ pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27445,7 +27916,10 @@ pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27454,7 +27928,10 @@ pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27469,7 +27946,10 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27478,7 +27958,10 @@ pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27487,7 +27970,10 @@ pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27496,7 +27982,10 @@ pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27505,7 +27994,10 @@ pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27514,7 +28006,10 @@ pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27523,7 +28018,10 @@ pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27538,7 +28036,10 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
 }
@@ -27547,7 +28048,10 @@ pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
 }
@@ -27556,7 +28060,10 @@ pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip1)
+)]
 pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     unsafe { simd_shuffle!(a, b, [0, 2]) }
 }
@@ -27566,7 +28073,10 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27576,7 +28086,10 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
 #[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27585,7 +28098,10 @@ pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27594,7 +28110,10 @@ pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27603,7 +28122,10 @@ pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27612,7 +28134,10 @@ pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27621,7 +28146,10 @@ pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27636,7 +28164,10 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27645,7 +28176,10 @@ pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27654,7 +28188,10 @@ pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27663,7 +28200,10 @@ pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27672,7 +28212,10 @@ pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27681,7 +28224,10 @@ pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27690,7 +28236,10 @@ pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27705,7 +28254,10 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27714,7 +28266,10 @@ pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27723,7 +28278,10 @@ pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27732,7 +28290,10 @@ pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27741,7 +28302,10 @@ pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
@@ -27750,7 +28314,10 @@ pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27759,7 +28326,10 @@ pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     unsafe {
         simd_shuffle!(
@@ -27774,7 +28344,10 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
 }
@@ -27783,7 +28356,10 @@ pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
 }
@@ -27792,7 +28368,10 @@ pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
+#[cfg_attr(
+    all(test, not(target_env = "msvc"), target_endian = "little"),
+    assert_instr(zip2)
+)]
 pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     unsafe { simd_shuffle!(a, b, [1, 3]) }
 }
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index ce9b236ff5..8b35cb5d33 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -2189,7 +2189,11 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(addhn2)
 )]
 #[cfg_attr(
@@ -2213,7 +2217,11 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(addhn2)
 )]
 #[cfg_attr(
@@ -2237,7 +2245,11 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(addhn2)
 )]
 #[cfg_attr(
@@ -2261,7 +2273,11 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(addhn2)
 )]
 #[cfg_attr(
@@ -2285,7 +2301,11 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(addhn2)
 )]
 #[cfg_attr(
@@ -2309,7 +2329,11 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(addhn2)
 )]
 #[cfg_attr(
@@ -2459,7 +2483,11 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(saddl2)
 )]
 #[cfg_attr(
@@ -2486,7 +2514,11 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(saddl2)
 )]
 #[cfg_attr(
@@ -2513,7 +2545,11 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(saddl2)
 )]
 #[cfg_attr(
@@ -2540,7 +2576,11 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(uaddl2)
 )]
 #[cfg_attr(
@@ -2567,7 +2607,11 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(uaddl2)
 )]
 #[cfg_attr(
@@ -2594,7 +2638,11 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(uaddl2)
 )]
 #[cfg_attr(
@@ -2792,7 +2840,11 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(saddw2)
 )]
 #[cfg_attr(
@@ -2817,7 +2869,11 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(saddw2)
 )]
 #[cfg_attr(
@@ -2842,7 +2898,11 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(saddw2)
 )]
 #[cfg_attr(
@@ -2867,7 +2927,11 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(uaddw2)
 )]
 #[cfg_attr(
@@ -2892,7 +2956,11 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(uaddw2)
 )]
 #[cfg_attr(
@@ -2917,7 +2985,11 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(uaddw2)
 )]
 #[cfg_attr(
@@ -34881,7 +34953,11 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sqdmlal, N = 2)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -34904,7 +34980,11 @@ pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sqdmlal, N = 1)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -35011,7 +35091,11 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sqdmlsl, N = 2)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -35034,7 +35118,11 @@ pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sqdmlsl, N = 1)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -39004,7 +39092,11 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(raddhn2)
 )]
 #[cfg_attr(
@@ -39026,7 +39118,11 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(raddhn2)
 )]
 #[cfg_attr(
@@ -39048,7 +39144,11 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(raddhn2)
 )]
 #[cfg_attr(
@@ -39070,7 +39170,11 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(raddhn2)
 )]
 #[cfg_attr(
@@ -39094,7 +39198,11 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(raddhn2)
 )]
 #[cfg_attr(
@@ -39118,7 +39226,11 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(raddhn2)
 )]
 #[cfg_attr(
@@ -69685,7 +69797,11 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(subhn2)
 )]
 #[cfg_attr(
@@ -69707,7 +69823,11 @@ pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(subhn2)
 )]
 #[cfg_attr(
@@ -69729,7 +69849,11 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(subhn2)
 )]
 #[cfg_attr(
@@ -69751,7 +69875,11 @@ pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(subhn2)
 )]
 #[cfg_attr(
@@ -69773,7 +69901,11 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(subhn2)
 )]
 #[cfg_attr(
@@ -69795,7 +69927,11 @@ pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(subhn2)
 )]
 #[cfg_attr(
@@ -70225,7 +70361,11 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sudot, LANE = 0)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -70252,7 +70392,11 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sudot, LANE = 0)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -70280,7 +70424,11 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sudot, LANE = 3)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -70300,7 +70448,11 @@ pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(sudot, LANE = 3)
 )]
 #[rustc_legacy_const_generics(3)]
@@ -72296,7 +72448,11 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(usdot)
 )]
 #[cfg_attr(
@@ -72325,7 +72481,11 @@ pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
 #[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    all(
+        test,
+        any(target_arch = "aarch64", target_arch = "arm64ec"),
+        target_endian = "little"
+    ),
     assert_instr(usdot)
 )]
 #[cfg_attr(
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index e40775d68a..163145e7ba 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -78,14 +78,22 @@ cfg-target-has-atomic-64: &cfg-target-has-atomic-64
 neon-unstable-fp8: &neon-unstable-fp8
   FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']]
 
+# all(test, target_endian = "little")
+all-test-little-endian: &all-test-little-endian
+  FnCall: [all, [test, 'target_endian = "little"']]
+
 # #[cfg(target_endian = "little")]
-little-endian: &little-endian
+cfg-little-endian: &cfg-little-endian
   FnCall: [cfg, ['target_endian = "little"']]
 
 # #[cfg(target_endian = "big")]
-big-endian: &big-endian
+cfg-big-endian: &cfg-big-endian
   FnCall: [cfg, ['target_endian = "big"']]
 
+# all(test, not(target_env = "msvc"), target_endian = "big")
+cfg-test-not-msvc-little-endian: &cfg-test-not-msvc-little-endian
+  FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}, 'target_endian = "little"']]
+
 intrinsics:
   - name: "vaddd_{type}"
     doc: Add
@@ -206,8 +214,9 @@ intrinsics:
     doc: Signed Absolute difference Long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [sabdl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
     safety: safe
     types:
       - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t]
@@ -245,8 +254,9 @@ intrinsics:
     doc: Signed Absolute difference Long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [sabdl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
     safety: safe
     types:
       - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t]
@@ -284,8 +294,9 @@ intrinsics:
     doc: Signed Absolute difference Long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [sabdl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
     safety: safe
     types:
       - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t]
@@ -1492,7 +1503,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -1513,7 +1524,7 @@ intrinsics:
     arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]]
       - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
@@ -1530,7 +1541,7 @@ intrinsics:
     arguments: ["a: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]]
       - *neon-stable-fp16
       - *target-not-arm64ec
     safety: safe
@@ -1547,7 +1558,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -1560,7 +1571,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -1577,7 +1588,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -1612,7 +1623,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
     return_type: "{type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -2687,7 +2698,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -2704,7 +2715,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -2727,7 +2738,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -2750,7 +2761,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -2766,8 +2777,9 @@ intrinsics:
     doc: Extract narrow
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
-    attr: [*neon-stable]
-    assert_instr: [xtn2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [xtn2]]}]]
     safety: safe
     types:
       - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -5145,8 +5157,9 @@ intrinsics:
     doc: Signed multiply long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[3]}"
-    attr: [*neon-stable]
-    assert_instr: [smull2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]]
     safety: safe
     types:
       - [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t]
@@ -5167,8 +5180,9 @@ intrinsics:
     doc: "Unsigned multiply long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[3]}"
-    attr: [*neon-stable]
-    assert_instr: [umull2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]]
     safety: safe
     types:
       - [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t]
@@ -5211,8 +5225,8 @@ intrinsics:
     return_type: "{neon_type[3]}"
     attr:
       - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]]
     safety: safe
-    assert_instr: [pmull2]
     types:
       - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t]
     compose:
@@ -5233,8 +5247,8 @@ intrinsics:
     attr:
       - *neon-aes
       - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]]
     safety: safe
-    assert_instr: [pmull2]
     types:
       - [poly64x2_t, "p128"]
     compose:
@@ -5814,8 +5828,9 @@ intrinsics:
     doc: Signed Subtract Wide
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
-    attr: [*neon-stable]
-    assert_instr: [ssubw2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubw2]]}]]
     safety: safe
     types:
       - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -5835,8 +5850,9 @@ intrinsics:
     doc: Unsigned Subtract Wide
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
-    attr: [*neon-stable]
-    assert_instr: [usubw2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubw2]]}]]
     safety: safe
     types:
       - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -5856,8 +5872,9 @@ intrinsics:
     doc: "Signed Subtract Long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [ssubl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubl2]]}]]
     safety: safe
     types:
       - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t]
@@ -5886,8 +5903,9 @@ intrinsics:
     doc: "Unsigned Subtract Long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [usubl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubl2]]}]]
     safety: safe
     types:
       - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t]
@@ -6894,8 +6912,9 @@ intrinsics:
     doc: Vector move
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [sxtl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sxtl2]]}]]
     safety: safe
     types:
       - [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -6912,8 +6931,9 @@ intrinsics:
     doc: Vector move
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
-    attr: [*neon-stable]
-    assert_instr: [uxtl2]
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uxtl2]]}]]
     safety: safe
     types:
       - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -7125,7 +7145,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7141,7 +7161,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7209,7 +7229,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7228,7 +7248,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7246,7 +7266,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7298,7 +7318,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7314,7 +7334,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7380,7 +7400,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7396,7 +7416,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7412,7 +7432,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7428,7 +7448,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7494,7 +7514,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7510,7 +7530,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -7578,7 +7598,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtn2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7593,7 +7613,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqxtn2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7685,7 +7705,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtun2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -7988,7 +8008,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8025,7 +8045,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8076,7 +8096,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8270,7 +8290,7 @@ intrinsics:
     arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"]
     return_type: "{neon_type[3]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8338,7 +8358,7 @@ intrinsics:
     arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"]
     return_type: "{neon_type[3]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8383,7 +8403,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8859,7 +8879,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -8884,7 +8904,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[3]}"
     attr:
-      - *little-endian
+      - *cfg-little-endian
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]]
       - *neon-stable
     safety: safe
@@ -8907,7 +8927,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[3]}"
     attr:
-      - *big-endian
+      - *cfg-big-endian
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn]]}]]
       - *neon-stable
     safety: safe
@@ -8930,7 +8950,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -8955,7 +8975,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -8980,7 +9000,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9009,7 +9029,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9035,7 +9055,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1', '3']]
       - *neon-stable
     static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9155,7 +9175,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -9174,7 +9194,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['1']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -9193,7 +9213,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const N: i32']
@@ -9646,7 +9666,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]]
     safety: safe
     types:
       - [int8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]']
@@ -9676,7 +9696,7 @@ intrinsics:
       - *neon-fp16
       - *neon-stable-fp16
       - *target-not-arm64ec
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]]
     safety: safe
     types:
       - [float16x4_t, '[0, 4, 2, 6]']
@@ -9690,7 +9710,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
     safety: safe
     types:
       - [int32x2_t, '[0, 2]']
@@ -9709,7 +9729,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]]
     safety: safe
     types:
       - [int8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]']
@@ -9738,7 +9758,7 @@ intrinsics:
       - *neon-fp16
       - *neon-stable-fp16
       - *target-not-arm64ec
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]]
     safety: safe
     types:
       - [float16x4_t, '[1, 5, 3, 7]']
@@ -9752,7 +9772,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
     safety: safe
     types:
       - [int32x2_t, '[1, 3]']
@@ -9771,7 +9791,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
     safety: safe
     types:
       - [int8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]']
@@ -9807,7 +9827,7 @@ intrinsics:
       - *neon-fp16
       - *neon-stable-fp16
       - *target-not-arm64ec
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
     safety: safe
     types:
       - [float16x4_t, '[2, 6, 3, 7]']
@@ -9821,7 +9841,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
     safety: safe
     types:
       - [int8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]']
@@ -9858,7 +9878,7 @@ intrinsics:
       - *neon-fp16
       - *neon-stable-fp16
       - *target-not-arm64ec
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
     safety: safe
     types:
       - [float16x4_t, '[0, 4, 1, 5]']
@@ -9872,7 +9892,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
     safety: safe
     types:
       - [int32x2_t, '[0, 2]']
@@ -9891,7 +9911,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]]
     safety: safe
     types:
       - [int8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]']
@@ -9920,7 +9940,7 @@ intrinsics:
       - *neon-fp16
       - *neon-stable-fp16
       - *target-not-arm64ec
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]]
     safety: safe
     types:
       - [float16x4_t, '[0, 2, 4, 6]']
@@ -9934,7 +9954,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
     safety: safe
     types:
       - [int32x2_t, '[1, 3]']
@@ -9953,7 +9973,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]]
     safety: safe
     types:
       - [int8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]']
@@ -9986,7 +10006,7 @@ intrinsics:
       - *neon-fp16
       - *neon-stable-fp16
       - *target-not-arm64ec
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]]
     safety: safe
     types:
       - [float16x4_t, '[1, 3, 5, 7]']
@@ -10004,7 +10024,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uabal2]]}]]
     safety: safe
     types:
       - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -10031,7 +10051,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal2]]}]]
+      - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [sabal2]]}]]
     safety: safe
     types:
       - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t]
@@ -10360,7 +10380,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -10400,7 +10420,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"]
     return_type: "{type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -10453,7 +10473,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"]
     return_type: "{type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
       - *neon-unstable-f16
@@ -10473,7 +10493,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"]
     return_type: "{type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-fp16
       - *neon-unstable-f16
@@ -10571,7 +10591,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -10603,7 +10623,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"]
     return_type: "{type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -11325,7 +11345,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -11339,7 +11359,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -11353,7 +11373,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -11376,7 +11396,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -11455,8 +11475,8 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl2]]}]]
       - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
     safety: safe
     types:
       - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -11644,7 +11664,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -11661,7 +11681,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -11678,7 +11698,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -11700,7 +11720,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -11955,7 +11975,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -11973,7 +11993,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]]
       - *neon-stable
     safety: safe
     types:
@@ -11991,7 +12011,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
@@ -12010,7 +12030,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-stable
     static_defs: ['const LANE: i32']
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index bfc8033fdd..5324fbb251 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -104,6 +104,10 @@ aarch64-crc-stable: &aarch64-crc-stable
 neon-unstable-f16: &neon-unstable-f16
   FnCall: [unstable, ['feature = "stdarch_neon_f16"', 'issue = "136306"']]
 
+# all(target_endian = "little")
+all-neon-target-aarch64-arm64ec-little-endian: &all-neon-target-aarch64-arm64ec-little-endian
+  FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}, 'target_endian = "little"']]
+
 intrinsics:
   - name: "vand{neon_type.no}"
     doc: Vector bitwise and
@@ -6139,7 +6143,7 @@ intrinsics:
       - *neon-i8mm
       - *neon-v8
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot]]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [usdot]]}]]
       - *neon-unstable-i8mm
       - *neon-cfg-arm-unstable
     safety: safe
@@ -6192,7 +6196,7 @@ intrinsics:
       - *neon-i8mm
       - *neon-v8
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 0']]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-unstable-i8mm
       - *neon-cfg-arm-unstable
@@ -6796,7 +6800,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vsubhn"]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn2]]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [subhn2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
@@ -6992,7 +6996,7 @@ intrinsics:
       - *neon-v8
       - *neon-i8mm
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
     static_defs: ["const LANE: i32"]
@@ -7650,7 +7654,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 2]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
@@ -7669,7 +7673,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
@@ -7722,7 +7726,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 2]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
@@ -7741,7 +7745,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 1]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['3']]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
@@ -13216,7 +13220,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
@@ -13243,7 +13247,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
@@ -14469,7 +14473,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] }  ]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
@@ -14525,7 +14529,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] }  ]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
@@ -14583,7 +14587,7 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vaddhn']] }  ]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['addhn2']]}] ]
+      - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['addhn2']]}] ]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe

From f51d2850f993ca933168599c24f7a72bb490f87c Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 280/326] gen-arm: port `vcopy_lane_{s,u,p,f}64` to generator

This enables the `big_endian_inverse` transformation to apply to this
intrinsic.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 60 +++++++++++++++++++
 crates/core_arch/src/aarch64/neon/mod.rs      | 50 ----------------
 .../spec/neon/aarch64.spec.yml                | 20 +++++++
 3 files changed, 80 insertions(+), 50 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 8e3493dfac..e0b853c9ef 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4332,6 +4332,66 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
     }
 }
 #[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_lane_f64<const LANE1: i32, const LANE2: i32>(
+    _a: float64x1_t,
+    b: float64x1_t,
+) -> float64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert!(LANE2 == 0);
+    b
+}
+#[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_lane_s64<const LANE1: i32, const LANE2: i32>(
+    _a: int64x1_t,
+    b: int64x1_t,
+) -> int64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert!(LANE2 == 0);
+    b
+}
+#[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_lane_u64<const LANE1: i32, const LANE2: i32>(
+    _a: uint64x1_t,
+    b: uint64x1_t,
+) -> uint64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert!(LANE2 == 0);
+    b
+}
+#[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_lane_p64<const LANE1: i32, const LANE2: i32>(
+    _a: poly64x1_t,
+    b: poly64x1_t,
+) -> poly64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert!(LANE2 == 0);
+    b
+}
+#[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index cab36b9b4b..736baf5ec6 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -94,56 +94,6 @@ macro_rules! shift_right_and_insert {
 
 pub(crate) use shift_right_and_insert;
 
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_lane_s64<const N1: i32, const N2: i32>(_a: int64x1_t, b: int64x1_t) -> int64x1_t {
-    static_assert!(N1 == 0);
-    static_assert!(N2 == 0);
-    b
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_lane_u64<const N1: i32, const N2: i32>(_a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
-    static_assert!(N1 == 0);
-    static_assert!(N2 == 0);
-    b
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_lane_p64<const N1: i32, const N2: i32>(_a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
-    static_assert!(N1 == 0);
-    static_assert!(N2 == 0);
-    b
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_lane_f64<const N1: i32, const N2: i32>(
-    _a: float64x1_t,
-    b: float64x1_t,
-) -> float64x1_t {
-    static_assert!(N1 == 0);
-    static_assert!(N2 == 0);
-    b
-}
 
 /// Duplicate vector element to vector or scalar
 #[inline]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 163145e7ba..e68157bf54 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -8995,6 +8995,26 @@ intrinsics:
       - Identifier: ["{type[5]}", UnsafeSymbol]
       - Identifier: ["{type[6]}", UnsafeSymbol]
 
+  - name: "vcopy_lane_{neon_type[0]}"
+    doc: "Insert vector element from another vector element"
+    arguments: ["_a: {neon_type[0]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[0]}"
+    attr:
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE1 = {type[1]}', 'LANE2 = {type[1]}']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['1', '3']]
+      - *neon-stable
+    static_defs: ['const LANE1: i32, const LANE2: i32']
+    safety: safe
+    types:
+      - [float64x1_t, '0', 'b']
+      - [poly64x1_t, '0', 'b']
+      - [uint64x1_t, '0', 'b']
+      - [int64x1_t, '0', 'b']
+    compose:
+      - FnCall: [static_assert!, ['LANE1 == {type[1]}']]
+      - FnCall: [static_assert!, ['LANE2 == {type[1]}']]
+      - Identifier: ["{type[2]}", Symbol]
+
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]

From c4c2bda54c9b722875ae6c40227fe029e45fd924 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 281/326] gen-arm: port `vcopy_laneq_{f,u,s,p}64` to generator

This enables the `big_endian_inverse` transformation to apply to these
intrinsics.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 60 ++++++++++++++++++
 crates/core_arch/src/aarch64/neon/mod.rs      | 61 -------------------
 .../spec/neon/aarch64.spec.yml                | 20 ++++++
 3 files changed, 80 insertions(+), 61 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index e0b853c9ef..335a79f0ee 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4641,6 +4641,66 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
     }
 }
 #[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_laneq_f64<const LANE1: i32, const LANE2: i32>(
+    _a: float64x1_t,
+    b: float64x2_t,
+) -> float64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert_uimm_bits!(LANE2, 1);
+    unsafe { transmute::<f64, _>(simd_extract!(b, LANE2 as u32)) }
+}
+#[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_laneq_s64<const LANE1: i32, const LANE2: i32>(
+    _a: int64x1_t,
+    b: int64x2_t,
+) -> int64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert_uimm_bits!(LANE2, 1);
+    unsafe { transmute::<i64, _>(simd_extract!(b, LANE2 as u32)) }
+}
+#[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_laneq_u64<const LANE1: i32, const LANE2: i32>(
+    _a: uint64x1_t,
+    b: uint64x2_t,
+) -> uint64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert_uimm_bits!(LANE2, 1);
+    unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
+}
+#[doc = "Insert vector element from another vector element"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
+#[rustc_legacy_const_generics(1, 3)]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+pub fn vcopy_laneq_p64<const LANE1: i32, const LANE2: i32>(
+    _a: poly64x1_t,
+    b: poly64x2_t,
+) -> poly64x1_t {
+    static_assert!(LANE1 == 0);
+    static_assert_uimm_bits!(LANE2, 1);
+    unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
+}
+#[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 736baf5ec6..d232c263f5 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -94,67 +94,6 @@ macro_rules! shift_right_and_insert {
 
 pub(crate) use shift_right_and_insert;
 
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_laneq_s64<const LANE1: i32, const LANE2: i32>(
-    _a: int64x1_t,
-    b: int64x2_t,
-) -> int64x1_t {
-    static_assert!(LANE1 == 0);
-    static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<i64, _>(simd_extract!(b, LANE2 as u32)) }
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_laneq_u64<const LANE1: i32, const LANE2: i32>(
-    _a: uint64x1_t,
-    b: uint64x2_t,
-) -> uint64x1_t {
-    static_assert!(LANE1 == 0);
-    static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_laneq_p64<const LANE1: i32, const LANE2: i32>(
-    _a: poly64x1_t,
-    b: poly64x2_t,
-) -> poly64x1_t {
-    static_assert!(LANE1 == 0);
-    static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
-#[rustc_legacy_const_generics(1, 3)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcopy_laneq_f64<const LANE1: i32, const LANE2: i32>(
-    _a: float64x1_t,
-    b: float64x2_t,
-) -> float64x1_t {
-    static_assert!(LANE1 == 0);
-    static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<f64, _>(simd_extract!(b, LANE2 as u32)) }
-}
-
 /// Load multiple single-element structures to one, two, three, or four registers
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index e68157bf54..dd625ebb22 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -9015,6 +9015,26 @@ intrinsics:
       - FnCall: [static_assert!, ['LANE2 == {type[1]}']]
       - Identifier: ["{type[2]}", Symbol]
 
+  - name: "vcopy_laneq_{neon_type[0]}"
+    doc: "Insert vector element from another vector element"
+    arguments: ["_a: {neon_type[1]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[1]}"
+    attr:
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE1 = {type[2]}', 'LANE2 = {type[3]}']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['1', '3']]
+      - *neon-stable
+    static_defs: ['const LANE1: i32, const LANE2: i32']
+    safety: safe
+    types:
+      - [float64x2_t, float64x1_t, '0', '1', 'transmute::<f64, _>(simd_extract!(b, LANE2 as u32))']
+      - [poly64x2_t, poly64x1_t, '0', '1', 'transmute::<u64, _>(simd_extract!(b, LANE2 as u32))']
+      - [uint64x2_t, uint64x1_t, '0', '1', 'transmute::<u64, _>(simd_extract!(b, LANE2 as u32))']
+      - [int64x2_t, int64x1_t, '0', '1', 'transmute::<i64, _>(simd_extract!(b, LANE2 as u32))']
+    compose:
+      - FnCall: [static_assert!, ['LANE1 == {type[2]}']]
+      - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[3]}']]
+      - Identifier: ["{type[4]}", UnsafeSymbol]
+
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]

From 10efd43da135c8e045227942e065cc2599b34c6d Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 282/326] gen-arm: port `vget_{high,low}_{p,f}64` to generator

This enables the `big_endian_inverse` transform to apply to these
intrinsics.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 18 +++++++++
 crates/core_arch/src/aarch64/neon/mod.rs      | 36 ------------------
 .../src/arm_shared/neon/generated.rs          | 38 +++++++++++++++++++
 .../spec/neon/aarch64.spec.yml                | 14 +++++++
 .../spec/neon/arm_shared.spec.yml             | 10 +++--
 5 files changed, 76 insertions(+), 40 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 335a79f0ee..4baad8fc37 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11438,6 +11438,24 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
     vfmad_laneq_f64::<LANE>(a, -b, c)
 }
+#[doc = "Duplicate vector element to vector or scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(fmov))]
+pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
+    unsafe { float64x1_t([simd_extract!(a, 1)]) }
+}
+#[doc = "Duplicate vector element to vector or scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
+    unsafe { float64x1_t([simd_extract!(a, 0)]) }
+}
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index d232c263f5..07f5a61d77 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -332,42 +332,6 @@ pub fn vmovq_n_f64(value: f64) -> float64x2_t {
     vdupq_n_f64(value)
 }
 
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
-    unsafe { float64x1_t([simd_extract!(a, 1)]) }
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(ext))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t {
-    unsafe { transmute(u64x1::new(simd_extract!(a, 1))) }
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
-    unsafe { float64x1_t([simd_extract!(a, 0)]) }
-}
-
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(nop))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t {
-    unsafe { transmute(u64x1::new(simd_extract!(a, 0))) }
-}
-
 /// Duplicate vector element to vector or scalar
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 8b35cb5d33..f24a12ad40 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -13400,6 +13400,27 @@ pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
 }
 #[doc = "Duplicate vector element to vector or scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(ext)
+)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "neon_intrinsics", since = "1.59.0")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t {
+    unsafe { transmute(u64x1::new(simd_extract!(a, 1))) }
+}
+#[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
@@ -14087,6 +14108,23 @@ pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
     unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
 }
 #[doc = "Duplicate vector element to vector or scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "neon_intrinsics", since = "1.59.0")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t {
+    unsafe { transmute(u64x1::new(simd_extract!(a, 0))) }
+}
+#[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index dd625ebb22..e38b4a508d 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -14404,3 +14404,17 @@ intrinsics:
           links:
             - link: "llvm.aarch64.fjcvtzs"
               arch: aarch64,arm64ec
+
+  - name: "{type[0]}"
+    doc: "Duplicate vector element to vector or scalar"
+    arguments: ["a: {type[1]}"]
+    return_type: "{neon_type[2]}"
+    attr:
+      - *neon-stable
+    assert_instr: ['{type[3]}']
+    safety: safe
+    types:
+      - ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'fmov', 'float64x1_t([simd_extract!(a, 1)])']
+      - ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])']
+    compose:
+      - Identifier: ['{type[4]}', UnsafeSymbol]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 5324fbb251..68c92aa54d 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -15001,8 +15001,9 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'vmov', 'ext', 'int64x1_t([simd_extract!(a, 1)])']
-      - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'vmov', 'ext', 'uint64x1_t([simd_extract!(a, 1)])']
+      - ['vget_high_s64', 'int64x2_t',   'int64x1_t',   'vmov', 'ext',  'int64x1_t([simd_extract!(a, 1)])']
+      - ['vget_high_u64', 'uint64x2_t',  'uint64x1_t',  'vmov', 'ext',  'uint64x1_t([simd_extract!(a, 1)])']
+      - ['vget_high_p64', 'poly64x2_t',  'poly64x1_t',  'vmov', 'ext',  'transmute(u64x1::new(simd_extract!(a, 1)))']
     compose:
       - Identifier: ['{type[5]}', UnsafeSymbol]
 
@@ -15017,8 +15018,9 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'int64x1_t([simd_extract!(a, 0)])']
-      - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'uint64x1_t([simd_extract!(a, 0)])']
+      - ['vget_low_s64', 'int64x2_t',   'int64x1_t',   'int64x1_t([simd_extract!(a, 0)])']
+      - ['vget_low_u64', 'uint64x2_t',  'uint64x1_t',  'uint64x1_t([simd_extract!(a, 0)])']
+      - ['vget_low_p64', 'poly64x2_t',  'poly64x1_t',  'transmute(u64x1::new(simd_extract!(a, 0)))']
     compose:
       - Identifier: ['{type[3]}', UnsafeSymbol]
 

From 5de9dffc506e1d4b0f880446d63d1b2bdfc6c19d Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 283/326] gen-arm: port `vgetq_lane_f64` to generator

This enables the `big_endian_inverse` transform to apply to this
intrinsic.
---
 crates/core_arch/src/aarch64/neon/generated.rs   | 11 +++++++++++
 crates/core_arch/src/aarch64/neon/mod.rs         | 14 --------------
 .../stdarch-gen-arm/spec/neon/aarch64.spec.yml   | 16 ++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 4baad8fc37..c1054f8ff0 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11456,6 +11456,17 @@ pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
 pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
     unsafe { float64x1_t([simd_extract!(a, 0)]) }
 }
+#[doc = "Duplicate vector element to vector or scalar"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[rustc_legacy_const_generics(1)]
+#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
+pub fn vgetq_lane_f64<const IMM5: i32>(a: float64x2_t) -> f64 {
+    static_assert_uimm_bits!(IMM5, 1);
+    unsafe { simd_extract!(a, IMM5 as u32) }
+}
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 07f5a61d77..bc82c980a8 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -346,20 +346,6 @@ pub fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
     unsafe { simd_extract!(v, IMM5 as u32) }
 }
 
-/// Duplicate vector element to vector or scalar
-#[inline]
-#[target_feature(enable = "neon")]
-#[rustc_legacy_const_generics(1)]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop, IMM5 = 0)
-)]
-pub fn vgetq_lane_f64<const IMM5: i32>(v: float64x2_t) -> f64 {
-    static_assert_uimm_bits!(IMM5, 1);
-    unsafe { simd_extract!(v, IMM5 as u32) }
-}
-
 /// Vector combine
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index e38b4a508d..48ce5a5f86 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -14418,3 +14418,19 @@ intrinsics:
       - ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])']
     compose:
       - Identifier: ['{type[4]}', UnsafeSymbol]
+
+  - name: "vgetq_lane_{type[1]}"
+    doc: "Duplicate vector element to vector or scalar"
+    arguments: ["a: {type[0]}"]
+    return_type: "{type[1]}"
+    attr:
+      - *neon-stable
+      - FnCall: [rustc_legacy_const_generics, ['1']]
+    assert_instr: [['nop', 'IMM5 = 0']]
+    safety: safe
+    static_defs: ["const IMM5: i32"]
+    types:
+      - ['float64x2_t', 'f64']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [IMM5, "1"]]
+      - FnCall: ['simd_extract!', [a, 'IMM5 as u32'], [] , true]

From d3c6e0e80d0c0570f842b885edd612fafe2f18d1 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 284/326] gen-arm: port `vcombine_f64` to generator

This enables the `big_endian_inverse` transform to apply to this
intrinsic.
---
 crates/core_arch/src/aarch64/neon/generated.rs    |  9 +++++++++
 crates/core_arch/src/aarch64/neon/mod.rs          |  9 ---------
 crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml | 13 +++++++++++++
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index c1054f8ff0..3c69f9defb 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4106,6 +4106,15 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
         vcmlaq_rot90_f32(a, b, c)
     }
 }
+#[doc = "Join two smaller vectors into a single larger vector"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(mov))]
+pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t {
+    unsafe { simd_shuffle!(a, b, [0, 1]) }
+}
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
 #[inline]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index bc82c980a8..386176874d 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -346,15 +346,6 @@ pub fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
     unsafe { simd_extract!(v, IMM5 as u32) }
 }
 
-/// Vector combine
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mov))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t {
-    unsafe { simd_shuffle!(low, high, [0, 1]) }
-}
-
 /// Shift left
 #[inline]
 #[target_feature(enable = "neon")]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 48ce5a5f86..0f9c8f2a5c 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -14419,6 +14419,19 @@ intrinsics:
     compose:
       - Identifier: ['{type[4]}', UnsafeSymbol]
 
+  - name: "vcombine{neon_type[0].noq}"
+    doc: Join two smaller vectors into a single larger vector
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[1]}"
+    attr:
+      - *neon-stable
+    assert_instr: [mov]
+    safety: safe
+    types:
+      - [float64x1_t, float64x2_t, '[0, 1]']
+    compose:
+      - FnCall: [simd_shuffle!, [a, b, '{type[2]}']]
+
   - name: "vgetq_lane_{type[1]}"
     doc: "Duplicate vector element to vector or scalar"
     arguments: ["a: {type[0]}"]

From efc35fecb8a92471cf51d8085e6d8c2be679ffe5 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Fri, 1 May 2026 11:08:00 +0100
Subject: [PATCH 285/326] core_arch: remove redundant tests

Manually written tests for `vcopy_laneq`, `vget{,q}_{high,low,lane}`,
`vcombine` and `vaddw_high` don't account for the expected differences
in output for big endian intrinsics and given that they duplicate the
testing of `intrinsic-test`, can be removed.
---
 crates/core_arch/src/aarch64/neon/mod.rs    |  77 ---
 crates/core_arch/src/arm_shared/neon/mod.rs | 612 --------------------
 crates/stdarch-verify/tests/arm.rs          | 124 ++++
 3 files changed, 124 insertions(+), 689 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 386176874d..b140131012 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -611,38 +611,6 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_f64() {
-        let a = f64x2::new(1.0, 2.0);
-        let e = f64x1::new(2.0);
-        let r = f64x1::from(vget_high_f64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_p64() {
-        let a = u64x2::new(1, 2);
-        let e = u64x1::new(2);
-        let r = u64x1::from(vget_high_p64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_f64() {
-        let a = f64x2::new(1.0, 2.0);
-        let e = f64x1::new(1.0);
-        let r = f64x1::from(vget_low_f64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_p64() {
-        let a = u64x2::new(1, 2);
-        let e = u64x1::new(1);
-        let r = u64x1::from(vget_low_p64(a.into()));
-        assert_eq!(r, e);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vget_lane_f64() {
         let v = f64x1::new(1.0);
@@ -650,15 +618,6 @@ mod tests {
         assert_eq!(r, 1.0);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_f64() {
-        let v = f64x2::new(0.0, 1.0);
-        let r = vgetq_lane_f64::<1>(v.into());
-        assert_eq!(r, 1.0);
-        let r = vgetq_lane_f64::<0>(v.into());
-        assert_eq!(r, 0.0);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vcopy_lane_s64() {
         let a = i64x1::new(1);
@@ -695,42 +654,6 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vcopy_laneq_s64() {
-        let a = i64x1::new(1);
-        let b = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let r = i64x1::from(vcopy_laneq_s64::<0, 1>(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vcopy_laneq_u64() {
-        let a = u64x1::new(1);
-        let b = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF);
-        let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
-        let r = u64x1::from(vcopy_laneq_u64::<0, 1>(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vcopy_laneq_p64() {
-        let a = u64x1::new(1);
-        let b = u64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
-        let r = u64x1::from(vcopy_laneq_p64::<0, 1>(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vcopy_laneq_f64() {
-        let a = f64x1::from_array([1.]);
-        let b = f64x2::from_array([0., 0.5]);
-        let e = f64x1::from_array([0.5]);
-        let r = f64x1::from(vcopy_laneq_f64::<0, 1>(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vbsl_f64() {
         let a = u64x1::new(0x8000000000000000);
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index ed65de2b89..c4249c2b3c 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -1663,235 +1663,6 @@ mod tests {
         assert_eq!(r, e)
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_u8() {
-        let v = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = vget_lane_u8::<1>(v.into());
-        assert_eq!(r, 2);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_u32() {
-        let v = u32x4::new(1, 2, 3, 4);
-        let r = vgetq_lane_u32::<1>(v.into());
-        assert_eq!(r, 2);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_s32() {
-        let v = i32x4::new(1, 2, 3, 4);
-        let r = vgetq_lane_s32::<1>(v.into());
-        assert_eq!(r, 2);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_u64() {
-        let v = u64x1::new(1);
-        let r = vget_lane_u64::<0>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_u16() {
-        let v = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = vgetq_lane_u16::<1>(v.into());
-        assert_eq!(r, 2);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_s8() {
-        let v = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vget_lane_s8::<2>(v.into());
-        assert_eq!(r, 2);
-        let r = vget_lane_s8::<4>(v.into());
-        assert_eq!(r, 4);
-        let r = vget_lane_s8::<5>(v.into());
-        assert_eq!(r, 5);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_p8() {
-        let v = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vget_lane_p8::<2>(v.into());
-        assert_eq!(r, 2);
-        let r = vget_lane_p8::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vget_lane_p8::<5>(v.into());
-        assert_eq!(r, 5);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_p16() {
-        let v = u16x4::new(0, 1, 2, 3);
-        let r = vget_lane_p16::<2>(v.into());
-        assert_eq!(r, 2);
-        let r = vget_lane_p16::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vget_lane_p16::<0>(v.into());
-        assert_eq!(r, 0);
-        let r = vget_lane_p16::<1>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_s16() {
-        let v = i16x4::new(0, 1, 2, 3);
-        let r = vget_lane_s16::<2>(v.into());
-        assert_eq!(r, 2);
-        let r = vget_lane_s16::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vget_lane_s16::<0>(v.into());
-        assert_eq!(r, 0);
-        let r = vget_lane_s16::<1>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_u16() {
-        let v = u16x4::new(0, 1, 2, 3);
-        let r = vget_lane_u16::<2>(v.into());
-        assert_eq!(r, 2);
-        let r = vget_lane_u16::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vget_lane_u16::<0>(v.into());
-        assert_eq!(r, 0);
-        let r = vget_lane_u16::<1>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_f32() {
-        let v = f32x2::new(0.0, 1.0);
-        let r = vget_lane_f32::<1>(v.into());
-        assert_eq!(r, 1.0);
-        let r = vget_lane_f32::<0>(v.into());
-        assert_eq!(r, 0.0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_s32() {
-        let v = i32x2::new(0, 1);
-        let r = vget_lane_s32::<1>(v.into());
-        assert_eq!(r, 1);
-        let r = vget_lane_s32::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_u32() {
-        let v = u32x2::new(0, 1);
-        let r = vget_lane_u32::<1>(v.into());
-        assert_eq!(r, 1);
-        let r = vget_lane_u32::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_s64() {
-        let v = i64x1::new(1);
-        let r = vget_lane_s64::<0>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_lane_p64() {
-        let v = u64x1::new(1);
-        let r = vget_lane_p64::<0>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_s8() {
-        let v = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_s8::<7>(v.into());
-        assert_eq!(r, 7);
-        let r = vgetq_lane_s8::<13>(v.into());
-        assert_eq!(r, 13);
-        let r = vgetq_lane_s8::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vgetq_lane_s8::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_p8() {
-        let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_p8::<7>(v.into());
-        assert_eq!(r, 7);
-        let r = vgetq_lane_p8::<13>(v.into());
-        assert_eq!(r, 13);
-        let r = vgetq_lane_p8::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vgetq_lane_p8::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_u8() {
-        let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_u8::<7>(v.into());
-        assert_eq!(r, 7);
-        let r = vgetq_lane_u8::<13>(v.into());
-        assert_eq!(r, 13);
-        let r = vgetq_lane_u8::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vgetq_lane_u8::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_s16() {
-        let v = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vgetq_lane_s16::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vgetq_lane_s16::<6>(v.into());
-        assert_eq!(r, 6);
-        let r = vgetq_lane_s16::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_p16() {
-        let v = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vgetq_lane_p16::<3>(v.into());
-        assert_eq!(r, 3);
-        let r = vgetq_lane_p16::<7>(v.into());
-        assert_eq!(r, 7);
-        let r = vgetq_lane_p16::<1>(v.into());
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_f32() {
-        let v = f32x4::new(0.0, 1.0, 2.0, 3.0);
-        let r = vgetq_lane_f32::<3>(v.into());
-        assert_eq!(r, 3.0);
-        let r = vgetq_lane_f32::<0>(v.into());
-        assert_eq!(r, 0.0);
-        let r = vgetq_lane_f32::<2>(v.into());
-        assert_eq!(r, 2.0);
-        let r = vgetq_lane_f32::<1>(v.into());
-        assert_eq!(r, 1.0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_s64() {
-        let v = i64x2::new(0, 1);
-        let r = vgetq_lane_s64::<1>(v.into());
-        assert_eq!(r, 1);
-        let r = vgetq_lane_s64::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_p64() {
-        let v = u64x2::new(0, 1);
-        let r = vgetq_lane_p64::<1>(v.into());
-        assert_eq!(r, 1);
-        let r = vgetq_lane_p64::<0>(v.into());
-        assert_eq!(r, 0);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vext_s64() {
         let a: i64x1 = i64x1::new(0);
@@ -1910,182 +1681,6 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_s8() {
-        let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let e = i8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r = i8x8::from(vget_high_s8(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_s16() {
-        let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let e = i16x4::new(5, 6, 7, 8);
-        let r = i16x4::from(vget_high_s16(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_s32() {
-        let a = i32x4::new(1, 2, 3, 4);
-        let e = i32x2::new(3, 4);
-        let r = i32x2::from(vget_high_s32(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_s64() {
-        let a = i64x2::new(1, 2);
-        let e = i64x1::new(2);
-        let r = i64x1::from(vget_high_s64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_u8() {
-        let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r = u8x8::from(vget_high_u8(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_u16() {
-        let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let e = u16x4::new(5, 6, 7, 8);
-        let r = u16x4::from(vget_high_u16(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_u32() {
-        let a = u32x4::new(1, 2, 3, 4);
-        let e = u32x2::new(3, 4);
-        let r = u32x2::from(vget_high_u32(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_u64() {
-        let a = u64x2::new(1, 2);
-        let e = u64x1::new(2);
-        let r = u64x1::from(vget_high_u64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_p8() {
-        let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r = u8x8::from(vget_high_p8(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_p16() {
-        let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let e = u16x4::new(5, 6, 7, 8);
-        let r = u16x4::from(vget_high_p16(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_high_f32() {
-        let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
-        let e = f32x2::new(3.0, 4.0);
-        let r = f32x2::from(vget_high_f32(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_s8() {
-        let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = i8x8::from(vget_low_s8(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_s16() {
-        let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let e = i16x4::new(1, 2, 3, 4);
-        let r = i16x4::from(vget_low_s16(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_s32() {
-        let a = i32x4::new(1, 2, 3, 4);
-        let e = i32x2::new(1, 2);
-        let r = i32x2::from(vget_low_s32(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_s64() {
-        let a = i64x2::new(1, 2);
-        let e = i64x1::new(1);
-        let r = i64x1::from(vget_low_s64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_u8() {
-        let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = u8x8::from(vget_low_u8(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_u16() {
-        let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let e = u16x4::new(1, 2, 3, 4);
-        let r = u16x4::from(vget_low_u16(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_u32() {
-        let a = u32x4::new(1, 2, 3, 4);
-        let e = u32x2::new(1, 2);
-        let r = u32x2::from(vget_low_u32(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_u64() {
-        let a = u64x2::new(1, 2);
-        let e = u64x1::new(1);
-        let r = u64x1::from(vget_low_u64(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_p8() {
-        let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = u8x8::from(vget_low_p8(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_p16() {
-        let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let e = u16x4::new(1, 2, 3, 4);
-        let r = u16x4::from(vget_low_p16(a.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vget_low_f32() {
-        let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
-        let e = f32x2::new(1.0, 2.0);
-        let r = f32x2::from(vget_low_f32(a.into()));
-        assert_eq!(r, e);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vdupq_n_s8() {
         let v: i8 = 42;
@@ -2469,13 +2064,6 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vgetq_lane_u64() {
-        let v = u64x2::new(1, 2);
-        let r = vgetq_lane_u64::<1>(v.into());
-        assert_eq!(r, 2);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vadd_s8() {
         test_ari_s8(
@@ -2638,72 +2226,6 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vaddl_high_s8() {
-        let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let x = i8::MAX;
-        let b = i8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x);
-        let x = x as i16;
-        let e = i16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15);
-        let r = i16x8::from(vaddl_high_s8(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddl_high_s16() {
-        let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let x = i16::MAX;
-        let b = i16x8::new(x, x, x, x, x, x, x, x);
-        let x = x as i32;
-        let e = i32x4::new(x + 4, x + 5, x + 6, x + 7);
-        let r = i32x4::from(vaddl_high_s16(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddl_high_s32() {
-        let a = i32x4::new(0, 1, 2, 3);
-        let x = i32::MAX;
-        let b = i32x4::new(x, x, x, x);
-        let x = x as i64;
-        let e = i64x2::new(x + 2, x + 3);
-        let r = i64x2::from(vaddl_high_s32(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddl_high_u8() {
-        let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let x = u8::MAX;
-        let b = u8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x);
-        let x = x as u16;
-        let e = u16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15);
-        let r = u16x8::from(vaddl_high_u8(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddl_high_u16() {
-        let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let x = u16::MAX;
-        let b = u16x8::new(x, x, x, x, x, x, x, x);
-        let x = x as u32;
-        let e = u32x4::new(x + 4, x + 5, x + 6, x + 7);
-        let r = u32x4::from(vaddl_high_u16(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddl_high_u32() {
-        let a = u32x4::new(0, 1, 2, 3);
-        let x = u32::MAX;
-        let b = u32x4::new(x, x, x, x);
-        let x = x as u64;
-        let e = u64x2::new(x + 2, x + 3);
-        let r = u64x2::from(vaddl_high_u32(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vaddw_s8() {
         let x = i16::MAX;
@@ -2794,96 +2316,6 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    #[simd_test(enable = "neon")]
-    fn test_vaddw_high_s8() {
-        let x = i16::MAX;
-        let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
-        let y = i8::MAX;
-        let b = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, y, y, y, y, y, y, y, y);
-        let y = y as i16;
-        let e = i16x8::new(
-            x.wrapping_add(y),
-            1 + y,
-            2 + y,
-            3 + y,
-            4 + y,
-            5 + y,
-            6 + y,
-            7 + y,
-        );
-        let r = i16x8::from(vaddw_high_s8(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddw_high_s16() {
-        let x = i32::MAX;
-        let a = i32x4::new(x, 1, 2, 3);
-        let y = i16::MAX;
-        let b = i16x8::new(0, 0, 0, 0, y, y, y, y);
-        let y = y as i32;
-        let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r = i32x4::from(vaddw_high_s16(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddw_high_s32() {
-        let x = i64::MAX;
-        let a = i64x2::new(x, 1);
-        let y = i32::MAX;
-        let b = i32x4::new(0, 0, y, y);
-        let y = y as i64;
-        let e = i64x2::new(x.wrapping_add(y), 1 + y);
-        let r = i64x2::from(vaddw_high_s32(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddw_high_u8() {
-        let x = u16::MAX;
-        let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
-        let y = u8::MAX;
-        let b = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, y, y, y, y, y, y, y, y);
-        let y = y as u16;
-        let e = u16x8::new(
-            x.wrapping_add(y),
-            1 + y,
-            2 + y,
-            3 + y,
-            4 + y,
-            5 + y,
-            6 + y,
-            7 + y,
-        );
-        let r = u16x8::from(vaddw_high_u8(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddw_high_u16() {
-        let x = u32::MAX;
-        let a = u32x4::new(x, 1, 2, 3);
-        let y = u16::MAX;
-        let b = u16x8::new(0, 0, 0, 0, y, y, y, y);
-        let y = y as u32;
-        let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r = u32x4::from(vaddw_high_u16(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    fn test_vaddw_high_u32() {
-        let x = u64::MAX;
-        let a = u64x2::new(x, 1);
-        let y = u32::MAX;
-        let b = u32x4::new(0, 0, y, y);
-        let y = y as u64;
-        let e = u64x2::new(x.wrapping_add(y), 1 + y);
-        let r = u64x2::from(vaddw_high_u32(a.into(), b.into()));
-        assert_eq!(r, e);
-    }
-
     #[simd_test(enable = "neon")]
     fn test_vmvn_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
@@ -5766,42 +5198,9 @@ mod tests {
         assert_eq!(r, e);
     }
 
-    macro_rules! test_vcombine {
-        ($test_id:ident => $fn_id:ident ([$($a:expr),*], [$($b:expr),*])) => {
-            #[allow(unused_assignments)]
-            #[simd_test(enable = "neon")]
-            fn $test_id() {
-                let a = Simd::from_array([$($a),*]);
-                let b = Simd::from_array([$($b),*]);
-                let e = Simd::from_array([$($a),* $(, $b)*]);
-                let c = $fn_id(a.into(), b.into());
-                let mut d = e;
-                d = c.into();
-                assert_eq!(d, e);
-            }
-        }
-    }
-
-    test_vcombine!(test_vcombine_s8 => vcombine_s8([3_i8, -4, 5, -6, 7, 8, 9, 10], [13_i8, -14, 15, -16, 17, 18, 19, 110]));
-    test_vcombine!(test_vcombine_u8 => vcombine_u8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110]));
-    test_vcombine!(test_vcombine_p8 => vcombine_p8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110]));
-
-    test_vcombine!(test_vcombine_s16 => vcombine_s16([3_i16, -4, 5, -6], [13_i16, -14, 15, -16]));
-    test_vcombine!(test_vcombine_u16 => vcombine_u16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
-    test_vcombine!(test_vcombine_p16 => vcombine_p16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
-
     #[cfg(not(target_arch = "arm64ec"))]
     mod fp16 {
         use super::*;
-        #[simd_test(enable = "neon,fp16")]
-        fn test_vcombine_f16() {
-            let a = f16x4::from_array([3_f16, 4., 5., 6.]);
-            let b = f16x4::from_array([13_f16, 14., 15., 16.]);
-            let e = f16x8::from_array([3_f16, 4., 5., 6., 13_f16, 14., 15., 16.]);
-            let c = f16x8::from(vcombine_f16(a.into(), b.into()));
-            assert_eq!(c, e);
-        }
-
         #[simd_test(enable = "neon,fp16")]
         fn test_vld1_lane_f16() {
             let a = f16x4::new(0., 1., 2., 3.);
@@ -5837,17 +5236,6 @@ mod tests {
         }
     }
 
-    test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14]));
-    test_vcombine!(test_vcombine_u32 => vcombine_u32([3_u32, 4], [13_u32, 14]));
-    // note: poly32x4 does not exist, and neither does vcombine_p32
-    test_vcombine!(test_vcombine_f32 => vcombine_f32([3_f32, -4.], [13_f32, -14.]));
-
-    test_vcombine!(test_vcombine_s64 => vcombine_s64([-3_i64], [13_i64]));
-    test_vcombine!(test_vcombine_u64 => vcombine_u64([3_u64], [13_u64]));
-    test_vcombine!(test_vcombine_p64 => vcombine_p64([3_u64], [13_u64]));
-    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
-    test_vcombine!(test_vcombine_f64 => vcombine_f64([-3_f64], [13_f64]));
-
     macro_rules! lane_wide_store_load_roundtrip {
         ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => {
             let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty);
diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs
index 2242bf4264..6ba9c17c48 100644
--- a/crates/stdarch-verify/tests/arm.rs
+++ b/crates/stdarch-verify/tests/arm.rs
@@ -5145,4 +5145,128 @@ static SKIP_RUNTIME_TESTS: &'static [&'static str] = &[
     "vzipq_p16",
     "__rndr",
     "__rndrrs",
+    "vcopy_laneq_f64",
+    "vcopy_laneq_f64",
+    "vcopy_laneq_s64",
+    "vcopy_laneq_s64",
+    "vcopy_laneq_u64",
+    "vcopy_laneq_u64",
+    "vcopy_laneq_p64",
+    "vcopy_laneq_p64",
+    "vget_high_f64",
+    "vget_high_f64",
+    "vget_high_p64",
+    "vget_high_p64",
+    "vget_low_f64",
+    "vget_low_f64",
+    "vget_low_p64",
+    "vget_low_p64",
+    "vgetq_lane_f64",
+    "vgetq_lane_f64",
+    "vaddl_high_s16",
+    "vaddl_high_s16",
+    "vaddl_high_s32",
+    "vaddl_high_s32",
+    "vaddl_high_s8",
+    "vaddl_high_s8",
+    "vaddl_high_u16",
+    "vaddl_high_u16",
+    "vaddl_high_u32",
+    "vaddl_high_u32",
+    "vaddl_high_u8",
+    "vaddl_high_u8",
+    "vget_high_f32",
+    "vget_high_f32",
+    "vget_high_p16",
+    "vget_high_p16",
+    "vget_high_p8",
+    "vget_high_p8",
+    "vget_high_s16",
+    "vget_high_s16",
+    "vget_high_s32",
+    "vget_high_s32",
+    "vget_high_s8",
+    "vget_high_s8",
+    "vget_high_u16",
+    "vget_high_u16",
+    "vget_high_u32",
+    "vget_high_u32",
+    "vget_high_u8",
+    "vget_high_u8",
+    "vget_high_s64",
+    "vget_high_s64",
+    "vget_high_u64",
+    "vget_high_u64",
+    "vget_lane_f32",
+    "vget_lane_f32",
+    "vget_lane_p16",
+    "vget_lane_p16",
+    "vget_lane_p8",
+    "vget_lane_p8",
+    "vget_lane_s16",
+    "vget_lane_s16",
+    "vget_lane_s32",
+    "vget_lane_s32",
+    "vget_lane_s8",
+    "vget_lane_s8",
+    "vget_lane_u16",
+    "vget_lane_u16",
+    "vget_lane_u32",
+    "vget_lane_u32",
+    "vget_lane_u8",
+    "vget_lane_u8",
+    "vgetq_lane_f32",
+    "vgetq_lane_f32",
+    "vgetq_lane_p16",
+    "vgetq_lane_p16",
+    "vgetq_lane_p64",
+    "vgetq_lane_p64",
+    "vgetq_lane_p8",
+    "vgetq_lane_p8",
+    "vgetq_lane_s16",
+    "vgetq_lane_s16",
+    "vgetq_lane_s32",
+    "vgetq_lane_s32",
+    "vgetq_lane_s64",
+    "vgetq_lane_s64",
+    "vgetq_lane_s8",
+    "vgetq_lane_s8",
+    "vgetq_lane_u16",
+    "vgetq_lane_u16",
+    "vgetq_lane_u32",
+    "vgetq_lane_u32",
+    "vgetq_lane_u8",
+    "vgetq_lane_u8",
+    "vget_lane_p64",
+    "vget_lane_s64",
+    "vget_lane_u64",
+    "vget_low_f32",
+    "vget_low_f32",
+    "vget_low_p16",
+    "vget_low_p16",
+    "vget_low_p8",
+    "vget_low_p8",
+    "vget_low_s16",
+    "vget_low_s16",
+    "vget_low_s32",
+    "vget_low_s32",
+    "vget_low_s8",
+    "vget_low_s8",
+    "vget_low_u16",
+    "vget_low_u16",
+    "vget_low_u32",
+    "vget_low_u32",
+    "vget_low_u8",
+    "vget_low_u8",
+    "vget_low_s64",
+    "vget_low_s64",
+    "vget_low_u64",
+    "vget_low_u64",
+    "vaddw_high_s16",
+    "vaddw_high_s32",
+    "vaddw_high_s8",
+    "vaddw_high_u16",
+    "vaddw_high_u32",
+    "vaddw_high_u8",
+    "vgetq_lane_u64",
 ];

From 1892beb2227cffd9373ca8ac36a0b7233ec26dd8 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Tue, 21 Apr 2026 22:34:57 +0800
Subject: [PATCH 286/326] loongarch: Use `intrinsics::simd` for
 vbit{clr,rev,set}

---
 .../src/loongarch64/lasx/generated.rs         | 108 ------------------
 .../src/loongarch64/lasx/portable.rs          |  12 ++
 .../src/loongarch64/lsx/generated.rs          | 108 ------------------
 .../core_arch/src/loongarch64/lsx/portable.rs |  12 ++
 crates/core_arch/src/loongarch64/simd.rs      |  18 +++
 crates/stdarch-gen-loongarch/lasx.spec        |  12 ++
 crates/stdarch-gen-loongarch/lsx.spec         |  12 ++
 .../src/portable-intrinsics.txt               |  24 ++++
 8 files changed, 90 insertions(+), 216 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index c7dbd46480..29aed37e6b 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -43,14 +43,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvsrlri_w(a: __v8i32, b: u32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvsrlri.d"]
     fn __lasx_xvsrlri_d(a: __v4i64, b: u32) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvbitclr.b"]
-    fn __lasx_xvbitclr_b(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvbitclr.h"]
-    fn __lasx_xvbitclr_h(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvbitclr.w"]
-    fn __lasx_xvbitclr_w(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvbitclr.d"]
-    fn __lasx_xvbitclr_d(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvbitclri.b"]
     fn __lasx_xvbitclri_b(a: __v32u8, b: u32) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvbitclri.h"]
@@ -59,14 +51,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvbitclri_w(a: __v8u32, b: u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvbitclri.d"]
     fn __lasx_xvbitclri_d(a: __v4u64, b: u32) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvbitset.b"]
-    fn __lasx_xvbitset_b(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvbitset.h"]
-    fn __lasx_xvbitset_h(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvbitset.w"]
-    fn __lasx_xvbitset_w(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvbitset.d"]
-    fn __lasx_xvbitset_d(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvbitseti.b"]
     fn __lasx_xvbitseti_b(a: __v32u8, b: u32) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvbitseti.h"]
@@ -75,14 +59,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvbitseti_w(a: __v8u32, b: u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvbitseti.d"]
     fn __lasx_xvbitseti_d(a: __v4u64, b: u32) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvbitrev.b"]
-    fn __lasx_xvbitrev_b(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvbitrev.h"]
-    fn __lasx_xvbitrev_h(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvbitrev.w"]
-    fn __lasx_xvbitrev_w(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvbitrev.d"]
-    fn __lasx_xvbitrev_d(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvbitrevi.b"]
     fn __lasx_xvbitrevi_b(a: __v32u8, b: u32) -> __v32u8;
     #[link_name = "llvm.loongarch.lasx.xvbitrevi.h"]
@@ -1285,34 +1261,6 @@ pub fn lasx_xvsrlri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitclr_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitclr_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitclr_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitclr_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitclr_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitclr_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitclr_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitclr_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
@@ -1349,34 +1297,6 @@ pub fn lasx_xvbitclri_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitset_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitset_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitset_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitset_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitset_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitset_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitset_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitset_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
@@ -1413,34 +1333,6 @@ pub fn lasx_xvbitseti_d<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitrev_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitrev_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitrev_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitrev_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitrev_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitrev_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvbitrev_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvbitrev_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[rustc_legacy_const_generics(1)]
diff --git a/crates/core_arch/src/loongarch64/lasx/portable.rs b/crates/core_arch/src/loongarch64/lasx/portable.rs
index f2a7254d79..5f306502d9 100644
--- a/crates/core_arch/src/loongarch64/lasx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -120,6 +120,18 @@ impl_vvv!("lasx", lasx_xvsrl_b, ls::simd_shr, m256i, u8x32);
 impl_vvv!("lasx", lasx_xvsrl_h, ls::simd_shr, m256i, u16x16);
 impl_vvv!("lasx", lasx_xvsrl_w, ls::simd_shr, m256i, u32x8);
 impl_vvv!("lasx", lasx_xvsrl_d, ls::simd_shr, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvbitclr_b, ls::simd_bitclr, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvbitclr_h, ls::simd_bitclr, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvbitclr_w, ls::simd_bitclr, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvbitclr_d, ls::simd_bitclr, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvbitset_b, ls::simd_bitset, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvbitset_h, ls::simd_bitset, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvbitset_w, ls::simd_bitset, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvbitset_d, ls::simd_bitset, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvbitrev_b, ls::simd_bitrev, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvbitrev_h, ls::simd_bitrev, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvbitrev_w, ls::simd_bitrev, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvbitrev_d, ls::simd_bitrev, m256i, u64x4);
 
 impl_vuv!("lasx", lasx_xvslli_b, is::simd_shl, m256i, i8x32);
 impl_vuv!("lasx", lasx_xvslli_h, is::simd_shl, m256i, i16x16);
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 4ec3cdf0c5..529dc605c2 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -43,14 +43,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vsrlri_w(a: __v4i32, b: u32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vsrlri.d"]
     fn __lsx_vsrlri_d(a: __v2i64, b: u32) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vbitclr.b"]
-    fn __lsx_vbitclr_b(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vbitclr.h"]
-    fn __lsx_vbitclr_h(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vbitclr.w"]
-    fn __lsx_vbitclr_w(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vbitclr.d"]
-    fn __lsx_vbitclr_d(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vbitclri.b"]
     fn __lsx_vbitclri_b(a: __v16u8, b: u32) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vbitclri.h"]
@@ -59,14 +51,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vbitclri_w(a: __v4u32, b: u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vbitclri.d"]
     fn __lsx_vbitclri_d(a: __v2u64, b: u32) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vbitset.b"]
-    fn __lsx_vbitset_b(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vbitset.h"]
-    fn __lsx_vbitset_h(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vbitset.w"]
-    fn __lsx_vbitset_w(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vbitset.d"]
-    fn __lsx_vbitset_d(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vbitseti.b"]
     fn __lsx_vbitseti_b(a: __v16u8, b: u32) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vbitseti.h"]
@@ -75,14 +59,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vbitseti_w(a: __v4u32, b: u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vbitseti.d"]
     fn __lsx_vbitseti_d(a: __v2u64, b: u32) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vbitrev.b"]
-    fn __lsx_vbitrev_b(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vbitrev.h"]
-    fn __lsx_vbitrev_h(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vbitrev.w"]
-    fn __lsx_vbitrev_w(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vbitrev.d"]
-    fn __lsx_vbitrev_d(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vbitrevi.b"]
     fn __lsx_vbitrevi_b(a: __v16u8, b: u32) -> __v16u8;
     #[link_name = "llvm.loongarch.lsx.vbitrevi.h"]
@@ -1197,34 +1173,6 @@ pub fn lsx_vsrlri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitclr_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitclr_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitclr_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitclr_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitclr_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitclr_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitclr_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitclr_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
@@ -1261,34 +1209,6 @@ pub fn lsx_vbitclri_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitset_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitset_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitset_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitset_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitset_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitset_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitset_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitset_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
@@ -1325,34 +1245,6 @@ pub fn lsx_vbitseti_d<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitrev_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitrev_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitrev_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitrev_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitrev_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitrev_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vbitrev_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vbitrev_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[rustc_legacy_const_generics(1)]
diff --git a/crates/core_arch/src/loongarch64/lsx/portable.rs b/crates/core_arch/src/loongarch64/lsx/portable.rs
index 1980000c3d..f6b8daae4e 100644
--- a/crates/core_arch/src/loongarch64/lsx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -120,6 +120,18 @@ impl_vvv!("lsx", lsx_vsrl_b, ls::simd_shr, m128i, u8x16);
 impl_vvv!("lsx", lsx_vsrl_h, ls::simd_shr, m128i, u16x8);
 impl_vvv!("lsx", lsx_vsrl_w, ls::simd_shr, m128i, u32x4);
 impl_vvv!("lsx", lsx_vsrl_d, ls::simd_shr, m128i, u64x2);
+impl_vvv!("lsx", lsx_vbitclr_b, ls::simd_bitclr, m128i, u8x16);
+impl_vvv!("lsx", lsx_vbitclr_h, ls::simd_bitclr, m128i, u16x8);
+impl_vvv!("lsx", lsx_vbitclr_w, ls::simd_bitclr, m128i, u32x4);
+impl_vvv!("lsx", lsx_vbitclr_d, ls::simd_bitclr, m128i, u64x2);
+impl_vvv!("lsx", lsx_vbitset_b, ls::simd_bitset, m128i, u8x16);
+impl_vvv!("lsx", lsx_vbitset_h, ls::simd_bitset, m128i, u16x8);
+impl_vvv!("lsx", lsx_vbitset_w, ls::simd_bitset, m128i, u32x4);
+impl_vvv!("lsx", lsx_vbitset_d, ls::simd_bitset, m128i, u64x2);
+impl_vvv!("lsx", lsx_vbitrev_b, ls::simd_bitrev, m128i, u8x16);
+impl_vvv!("lsx", lsx_vbitrev_h, ls::simd_bitrev, m128i, u16x8);
+impl_vvv!("lsx", lsx_vbitrev_w, ls::simd_bitrev, m128i, u32x4);
+impl_vvv!("lsx", lsx_vbitrev_d, ls::simd_bitrev, m128i, u64x2);
 
 impl_vuv!("lsx", lsx_vslli_b, is::simd_shl, m128i, i8x16);
 impl_vuv!("lsx", lsx_vslli_h, is::simd_shl, m128i, i16x8);
diff --git a/crates/core_arch/src/loongarch64/simd.rs b/crates/core_arch/src/loongarch64/simd.rs
index 959e2d0cb6..6f573f56d6 100644
--- a/crates/core_arch/src/loongarch64/simd.rs
+++ b/crates/core_arch/src/loongarch64/simd.rs
@@ -51,6 +51,24 @@ pub(super) const unsafe fn simd_andn<T: Copy + const SimdExt>(a: T, b: T) -> T {
     is::simd_and(ls::simd_not(a), b)
 }
 
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simd_bitclr<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    ls::simd_andn(ls::simd_shl(ls::simd_splat(1), b), a)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simd_bitrev<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    is::simd_xor(ls::simd_shl(ls::simd_splat(1), b), a)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(super) const unsafe fn simd_bitset<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    is::simd_or(ls::simd_shl(ls::simd_splat(1), b), a)
+}
+
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(super) const unsafe fn simd_fmsub<T: Copy>(a: T, b: T, c: T) -> T {
diff --git a/crates/stdarch-gen-loongarch/lasx.spec b/crates/stdarch-gen-loongarch/lasx.spec
index 9a9b1a143e..93317fca6b 100644
--- a/crates/stdarch-gen-loongarch/lasx.spec
+++ b/crates/stdarch-gen-loongarch/lasx.spec
@@ -228,21 +228,25 @@ asm-fmts = xd, xj, ui6
 data-types = V4DI, V4DI, UQI
 
 /// lasx_xvbitclr_b
+impl = portable
 name = lasx_xvbitclr_b
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvbitclr_h
+impl = portable
 name = lasx_xvbitclr_h
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvbitclr_w
+impl = portable
 name = lasx_xvbitclr_w
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvbitclr_d
+impl = portable
 name = lasx_xvbitclr_d
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
@@ -268,21 +272,25 @@ asm-fmts = xd, xj, ui6
 data-types = UV4DI, UV4DI, UQI
 
 /// lasx_xvbitset_b
+impl = portable
 name = lasx_xvbitset_b
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvbitset_h
+impl = portable
 name = lasx_xvbitset_h
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvbitset_w
+impl = portable
 name = lasx_xvbitset_w
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvbitset_d
+impl = portable
 name = lasx_xvbitset_d
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
@@ -308,21 +316,25 @@ asm-fmts = xd, xj, ui6
 data-types = UV4DI, UV4DI, UQI
 
 /// lasx_xvbitrev_b
+impl = portable
 name = lasx_xvbitrev_b
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvbitrev_h
+impl = portable
 name = lasx_xvbitrev_h
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvbitrev_w
+impl = portable
 name = lasx_xvbitrev_w
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvbitrev_d
+impl = portable
 name = lasx_xvbitrev_d
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
diff --git a/crates/stdarch-gen-loongarch/lsx.spec b/crates/stdarch-gen-loongarch/lsx.spec
index 8fd2678899..274ebe4144 100644
--- a/crates/stdarch-gen-loongarch/lsx.spec
+++ b/crates/stdarch-gen-loongarch/lsx.spec
@@ -228,21 +228,25 @@ asm-fmts = vd, vj, ui6
 data-types = V2DI, V2DI, UQI
 
 /// lsx_vbitclr_b
+impl = portable
 name = lsx_vbitclr_b
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vbitclr_h
+impl = portable
 name = lsx_vbitclr_h
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vbitclr_w
+impl = portable
 name = lsx_vbitclr_w
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vbitclr_d
+impl = portable
 name = lsx_vbitclr_d
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
@@ -268,21 +272,25 @@ asm-fmts = vd, vj, ui6
 data-types = UV2DI, UV2DI, UQI
 
 /// lsx_vbitset_b
+impl = portable
 name = lsx_vbitset_b
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vbitset_h
+impl = portable
 name = lsx_vbitset_h
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vbitset_w
+impl = portable
 name = lsx_vbitset_w
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vbitset_d
+impl = portable
 name = lsx_vbitset_d
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
@@ -308,21 +316,25 @@ asm-fmts = vd, vj, ui6
 data-types = UV2DI, UV2DI, UQI
 
 /// lsx_vbitrev_b
+impl = portable
 name = lsx_vbitrev_b
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vbitrev_h
+impl = portable
 name = lsx_vbitrev_h
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vbitrev_w
+impl = portable
 name = lsx_vbitrev_w
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vbitrev_d
+impl = portable
 name = lsx_vbitrev_d
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
diff --git a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
index 2d5e9817a3..f78f594cb9 100644
--- a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
+++ b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -191,6 +191,18 @@ lsx_vrepli_b
 lsx_vrepli_h
 lsx_vrepli_w
 lsx_vrepli_d
+lsx_vbitclr_b
+lsx_vbitclr_h
+lsx_vbitclr_w
+lsx_vbitclr_d
+lsx_vbitset_b
+lsx_vbitset_h
+lsx_vbitset_w
+lsx_vbitset_d
+lsx_vbitrev_b
+lsx_vbitrev_h
+lsx_vbitrev_w
+lsx_vbitrev_d
 
 # LASX intrinsics
 lasx_xvsll_b
@@ -379,3 +391,15 @@ lasx_xvrepli_b
 lasx_xvrepli_h
 lasx_xvrepli_w
 lasx_xvrepli_d
+lasx_xvbitclr_b
+lasx_xvbitclr_h
+lasx_xvbitclr_w
+lasx_xvbitclr_d
+lasx_xvbitset_b
+lasx_xvbitset_h
+lasx_xvbitset_w
+lasx_xvbitset_d
+lasx_xvbitrev_b
+lasx_xvbitrev_h
+lasx_xvbitrev_w
+lasx_xvbitrev_d

From ec40556190452c0d46a0c791cbcbf318ada4e79e Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 287/326] gen-arm: change defn of `vabdl_high_u{8,16,32}`

Changes the definition of `vabdl_high_u{8,16,32}` to match that of
`vabdl_high_s{8,16,32}` so that the `big_endian_inverse` transformation
can apply.
---
 .../core_arch/src/aarch64/neon/generated.rs   |  26 ++---
 .../spec/neon/aarch64.spec.yml                | 102 ++++++++++++++++--
 2 files changed, 107 insertions(+), 21 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 8e3493dfac..3f31996655 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -268,19 +268,6 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     }
 }
 #[doc = "Unsigned Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
-pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        simd_cast(vabd_u8(c, d))
-    }
-}
-#[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
@@ -306,6 +293,19 @@ pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
         simd_cast(vabd_u32(c, d))
     }
 }
+#[doc = "Unsigned Absolute difference Long"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
+pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
+    unsafe {
+        let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
+        let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
+        simd_cast(vabd_u8(c, d))
+    }
+}
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"]
 #[inline]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 163145e7ba..bc71eac8d1 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -11470,8 +11470,8 @@ intrinsics:
                   - FnCall: ["vdup_n_{type[0]}", [b]]
             - '0'
 
-  - name: "vabdl_high_{neon_type[0]}"
-    doc: "Unsigned Absolute difference Long"
+  - name: "vabdl_high{neon_type[0].noq}"
+    doc: Unsigned Absolute difference Long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
@@ -11479,13 +11479,99 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
     safety: safe
     types:
-      - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]']
-      - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]']
+      - [uint8x16_t, uint16x8_t, uint8x8_t]
     compose:
-      - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]}]
-      - Let: [d, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
-      - FnCall: [simd_cast, [{FnCall: ["vabd_{neon_type[0]}", [c, d]]}]]
+      - Let:
+          - c
+          - "{neon_type[2]}"
+          - FnCall:
+              - simd_shuffle!
+              - - a
+                - a
+                - [8, 9, 10, 11, 12, 13, 14, 15]
+      - Let:
+          - d
+          - "{neon_type[2]}"
+          - FnCall:
+              - simd_shuffle!
+              - - b
+                - b
+                - [8, 9, 10, 11, 12, 13, 14, 15]
+      - FnCall:
+          - simd_cast
+          - - FnCall:
+                - "vabd_{neon_type[0]}"
+                - - c
+                  - d
+
+  - name: "vabdl_high{neon_type[0].noq}"
+    doc: Unsigned Absolute difference Long
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[1]}"
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
+    safety: safe
+    types:
+      - [uint16x8_t, uint32x4_t, uint16x4_t]
+    compose:
+      - Let:
+          - c
+          - "{neon_type[2]}"
+          - FnCall:
+              - simd_shuffle!
+              - - a
+                - a
+                - [4, 5, 6, 7]
+      - Let:
+          - d
+          - "{neon_type[2]}"
+          - FnCall:
+              - simd_shuffle!
+              - - b
+                - b
+                - [4, 5, 6, 7]
+
+      - FnCall:
+          - simd_cast
+          - - FnCall:
+                - "vabd_{neon_type[0]}"
+                - - c
+                  - d
+
+  - name: "vabdl_high{neon_type[0].noq}"
+    doc: Unsigned Absolute difference Long
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+    return_type: "{neon_type[1]}"
+    attr:
+      - *neon-stable
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
+    safety: safe
+    types:
+      - [uint32x4_t, uint64x2_t, uint32x2_t, int32x2_t]
+    compose:
+      - Let:
+          - c
+          - "{neon_type[2]}"
+          - FnCall:
+              - simd_shuffle!
+              - - a
+                - a
+                - [2, 3]
+      - Let:
+          - d
+          - "{neon_type[2]}"
+          - FnCall:
+              - simd_shuffle!
+              - - b
+                - b
+                - [2, 3]
+      - FnCall:
+          - simd_cast
+          - - FnCall:
+                - "vabd_{neon_type[0]}"
+                - - c
+                  - d
 
   - name: "vfms_n_f64"
     doc: "Floating-point fused Multiply-subtract to accumulator(vector)"

From b203d651cd1a4a7c6d333f4b0a1e02358fc7c84b Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Wed, 29 Apr 2026 12:55:45 +0100
Subject: [PATCH 288/326] gen-arm: write `vtbl{1,2,3,4}` in terms of `vqtbl`

Writing these intrinsics in terms of the `vqtbl_$ty` functions rather
than the `vqtbl` helper function preserves the behaviour while making
them work in big endian.
---
 .../core_arch/src/aarch64/neon/generated.rs   |  18 +--
 .../spec/neon/aarch64.spec.yml                | 149 ++++++++----------
 2 files changed, 74 insertions(+), 93 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 3f31996655..00008c6ce6 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -25952,7 +25952,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
-    unsafe { vqtbl1(transmute(vcombine_s8(a.0, a.1)), transmute(b)) }
+    vqtbl1_s8(vcombine_s8(a.0, a.1), vreinterpret_u8_s8(b))
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
@@ -25961,7 +25961,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
-    unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) }
+    vqtbl1_u8(vcombine_u8(a.0, a.1), b)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
@@ -25970,7 +25970,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
-    unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) }
+    vqtbl1_p8(vcombine_p8(a.0, a.1), b)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
@@ -25983,7 +25983,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
         vcombine_s8(a.0, a.1),
         vcombine_s8(a.2, unsafe { crate::mem::zeroed() }),
     );
-    unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) }
+    vqtbl2_s8(x, vreinterpret_u8_s8(b))
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
@@ -25996,7 +25996,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
         vcombine_u8(a.0, a.1),
         vcombine_u8(a.2, unsafe { crate::mem::zeroed() }),
     );
-    unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
+    vqtbl2_u8(x, b)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
@@ -26009,7 +26009,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
         vcombine_p8(a.0, a.1),
         vcombine_p8(a.2, unsafe { crate::mem::zeroed() }),
     );
-    unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
+    vqtbl2_p8(x, b)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
@@ -26019,7 +26019,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
     let x = int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, a.3));
-    unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) }
+    vqtbl2_s8(x, vreinterpret_u8_s8(b))
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
@@ -26029,7 +26029,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
     let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3));
-    unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
+    vqtbl2_u8(x, b)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
@@ -26039,7 +26039,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
     let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3));
-    unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) }
+    vqtbl2_p8(x, b)
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index bc71eac8d1..26b31b1e4c 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -12273,6 +12273,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
+    big_endian_inverse: false
     types:
       - [int8x8_t, 'int8x8_t', 'unsafe {{ transmute(b) }}']
       - [uint8x8_t, 'uint8x8_t', 'b']
@@ -12286,26 +12287,22 @@ intrinsics:
                   - 'unsafe {{ crate::mem::zeroed() }}'
             - Identifier: ['{type[2]}', Symbol]
 
-  - name: "vtbl2{neon_type[1].noq}"
+  - name: "vtbl2{neon_type[2].no}"
     doc: "Table look-up"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
-    return_type: "{neon_type[1]}"
+    return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
+    big_endian_inverse: false
     safety: safe
     types:
-      - [int8x8x2_t, 'int8x8_t']
+      - ['int8x8x2_t',  'int8x8_t',  'int8x8_t']
     compose:
       - FnCall:
-          - vqtbl1
-          - - FnCall:
-                - transmute
-                - - FnCall:
-                      - 'vcombine{neon_type[1].noq}'
-                      - - 'a.0'
-                        - 'a.1'
-            - FnCall: [transmute, [b]]
+        - 'vqtbl1{neon_type[2].noq}'
+        - - FnCall: ['vcombine{neon_type[2].noq}', ['a.0', 'a.1']]
+          - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]]
 
   - name: "vtbl2{neon_type[2].no}"
     doc: "Table look-up"
@@ -12317,124 +12314,108 @@ intrinsics:
     big_endian_inverse: false
     safety: safe
     types:
-      - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t']
-      - [poly8x8x2_t, 'uint8x8_t', 'poly8x8_t']
+      - ['uint8x8x2_t', 'uint8x8_t', 'uint8x8_t']
+      - ['poly8x8x2_t', 'uint8x8_t', 'poly8x8_t']
     compose:
       - FnCall:
-          - transmute
-          - - FnCall:
-                - vqtbl1
-                - - FnCall:
-                      - transmute
-                      - - FnCall:
-                            - 'vcombine{neon_type[2].noq}'
-                            - - 'a.0'
-                              - 'a.1'
-                  - b
+          - 'vqtbl1{neon_type[2].noq}'
+          - - FnCall: ['vcombine{neon_type[2].noq}', ['a.0', 'a.1']]
+            - b
 
   - name: "vtbl3{neon_type[1].no}"
     doc: "Table look-up"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
-    return_type: "{neon_type[1]}"
+    return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
+    big_endian_inverse: false
     types:
-      - [int8x8x3_t, 'int8x8_t', 'int8x16x2']
+      - ['int8x8x3_t', 'int8x8_t', 'int8x8_t', 'int8x16x2']
     compose:
       - Let:
-          - x
-          - FnCall:
-              - '{type[2]}_t'
-              - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']]
-                - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']]
+        - x
+        - FnCall:
+          - '{type[3]}_t'
+          - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']]
+            - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']]
       - FnCall:
-          - transmute
-          - - FnCall:
-                - vqtbl2
-                - - FnCall: [transmute, ['x.0']]
-                  - FnCall: [transmute, ['x.1']]
-                  - FnCall: [transmute, [b]]
+        - 'vqtbl2{neon_type[2].no}'
+        - - x
+          - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]]
+
 
-  - name: "vtbl3{neon_type[3].no}"
+  - name: "vtbl3{neon_type[2].no}"
     doc: "Table look-up"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
-    return_type: "{neon_type[3]}"
+    return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    types:
-      - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t']
-      - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t']
     big_endian_inverse: false
+    types:
+      - [uint8x8x3_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2']
+      - [poly8x8x3_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2']
     compose:
       - Let:
-          - x
-          - FnCall:
-              - '{type[2]}_t'
-              - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']]
-                - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']]
-      - FnCall:
-          - transmute
-          - - FnCall:
-                - vqtbl2
-                - - FnCall: [transmute, ['x.0']]
-                  - FnCall: [transmute, ['x.1']]
-                  - b
+        - x
+        - FnCall:
+          - '{type[3]}_t'
+          - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']]
+            - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']]
+      - FnCall:
+        - 'vqtbl2{neon_type[2].no}'
+        - - x
+          - b
 
-  - name: "vtbl4{neon_type[1].no}"
+  - name: "vtbl4{neon_type[2].no}"
     doc: "Table look-up"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
-    return_type: "{neon_type[1]}"
+    return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
+    big_endian_inverse: false
     types:
-      - [int8x8x4_t, 'int8x8_t', 'int8x16x2']
+      - ['int8x8x4_t', 'int8x8_t', 'int8x8_t', 'int8x16x2']
     compose:
       - Let:
-          - x
-          - FnCall:
-              - '{type[2]}_t'
-              - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']]
-                - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'a.3']]
+        - x
+        - FnCall:
+            - '{type[3]}_t'
+            - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']]
+              - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'a.3']]
       - FnCall:
-          - transmute
-          - - FnCall:
-                - 'vqtbl2'
-                - - FnCall: [transmute, ['x.0']]
-                  - FnCall: [transmute, ['x.1']]
-                  - FnCall: [transmute, [b]]
+        - 'vqtbl2{neon_type[2].no}'
+        - - x
+          - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]]
 
-  - name: "vtbl4{neon_type[3].no}"
+  - name: "vtbl4{neon_type[2].no}"
     doc: "Table look-up"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
-    return_type: "{neon_type[3]}"
+    return_type: "{neon_type[2]}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    types:
-      - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t']
-      - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t']
     big_endian_inverse: false
+    types:
+      - [uint8x8x4_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2']
+      - [poly8x8x4_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2']
     compose:
       - Let:
-          - x
-          - FnCall:
-              - '{type[2]}_t'
-              - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']]
-                - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'a.3']]
-      - FnCall:
-          - transmute
-          - - FnCall:
-                - 'vqtbl2'
-                - - FnCall: [transmute, ['x.0']]
-                  - FnCall: [transmute, ['x.1']]
-                  - b
+        - x
+        - FnCall:
+            - '{type[3]}_t'
+            - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']]
+              - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'a.3']]
+      - FnCall:
+        - 'vqtbl2{neon_type[2].no}'
+        - - x
+          - b
 
   - name: "vqtbx1{neon_type[0].no}"
     doc: "Extended table look-up"

From 8f84a30c0d82148f49cf0eeccec268fc233264c1 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Thu, 30 Apr 2026 14:32:12 +0100
Subject: [PATCH 289/326] gen-arm: write `vtbx{1,2,3,4}` in terms of `vqtbx`

Writing these intrinsics in terms of the `vqtbx_$ty` functions rather
than the `vqtbx` helper function preserves the behaviour while making
them work in big endian.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 109 ++++----
 .../spec/neon/aarch64.spec.yml                | 234 ++++++++++--------
 2 files changed, 192 insertions(+), 151 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 00008c6ce6..cca3879571 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -26051,11 +26051,11 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
     unsafe {
         simd_select(
             simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(8))),
-            transmute(vqtbx1(
-                transmute(a),
-                transmute(vcombine_s8(b, crate::mem::zeroed())),
-                transmute(c),
-            )),
+            vqtbx1_s8(
+                a,
+                vcombine_s8(b, crate::mem::zeroed()),
+                vreinterpret_u8_s8(c),
+            ),
             a,
         )
     }
@@ -26070,11 +26070,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
     unsafe {
         simd_select(
             simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(8))),
-            transmute(vqtbx1(
-                transmute(a),
-                transmute(vcombine_u8(b, crate::mem::zeroed())),
-                c,
-            )),
+            vqtbx1_u8(a, vcombine_u8(b, crate::mem::zeroed()), c),
             a,
         )
     }
@@ -26089,11 +26085,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
     unsafe {
         simd_select(
             simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(8))),
-            transmute(vqtbx1(
-                transmute(a),
-                transmute(vcombine_p8(b, crate::mem::zeroed())),
-                c,
-            )),
+            vqtbx1_p8(a, vcombine_p8(b, crate::mem::zeroed()), c),
             a,
         )
     }
@@ -26105,7 +26097,13 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
-    unsafe { vqtbx1(transmute(a), transmute(vcombine_s8(b.0, b.1)), transmute(c)) }
+    unsafe {
+        simd_select(
+            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(16))),
+            vqtbx1_s8(a, vcombine_s8(b.0, b.1), vreinterpret_u8_s8(c)),
+            a,
+        )
+    }
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
@@ -26114,7 +26112,13 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
-    unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) }
+    unsafe {
+        simd_select(
+            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(16))),
+            vqtbx1_u8(a, vcombine_u8(b.0, b.1), c),
+            a,
+        )
+    }
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
@@ -26123,7 +26127,13 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
-    unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) }
+    unsafe {
+        simd_select(
+            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(16))),
+            vqtbx1_p8(a, vcombine_p8(b.0, b.1), c),
+            a,
+        )
+    }
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
@@ -26137,16 +26147,11 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
         vcombine_s8(b.2, unsafe { crate::mem::zeroed() }),
     );
     unsafe {
-        transmute(simd_select(
-            simd_lt::<int8x8_t, int8x8_t>(transmute(c), transmute(i8x8::splat(24))),
-            transmute(vqtbx2(
-                transmute(a),
-                transmute(x.0),
-                transmute(x.1),
-                transmute(c),
-            )),
+        simd_select(
+            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(24))),
+            vqtbx2_s8(a, x, vreinterpret_u8_s8(c)),
             a,
-        ))
+        )
     }
 }
 #[doc = "Extended table look-up"]
@@ -26161,11 +26166,11 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
         vcombine_u8(b.2, unsafe { crate::mem::zeroed() }),
     );
     unsafe {
-        transmute(simd_select(
-            simd_lt::<uint8x8_t, int8x8_t>(transmute(c), transmute(u8x8::splat(24))),
-            transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)),
+        simd_select(
+            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(24))),
+            vqtbx2_u8(a, x, c),
             a,
-        ))
+        )
     }
 }
 #[doc = "Extended table look-up"]
@@ -26180,11 +26185,11 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
         vcombine_p8(b.2, unsafe { crate::mem::zeroed() }),
     );
     unsafe {
-        transmute(simd_select(
-            simd_lt::<poly8x8_t, int8x8_t>(transmute(c), transmute(u8x8::splat(24))),
-            transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)),
+        simd_select(
+            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(24))),
+            vqtbx2_p8(a, x, c),
             a,
-        ))
+        )
     }
 }
 #[doc = "Extended table look-up"]
@@ -26194,12 +26199,12 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
+    let x = int8x16x2_t(vcombine_s8(b.0, b.1), vcombine_s8(b.2, b.3));
     unsafe {
-        vqtbx2(
-            transmute(a),
-            transmute(vcombine_s8(b.0, b.1)),
-            transmute(vcombine_s8(b.2, b.3)),
-            transmute(c),
+        simd_select(
+            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(32))),
+            vqtbx2_s8(a, x, vreinterpret_u8_s8(c)),
+            a,
         )
     }
 }
@@ -26210,13 +26215,13 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
+    let x = uint8x16x2_t(vcombine_u8(b.0, b.1), vcombine_u8(b.2, b.3));
     unsafe {
-        transmute(vqtbx2(
-            transmute(a),
-            transmute(vcombine_u8(b.0, b.1)),
-            transmute(vcombine_u8(b.2, b.3)),
-            c,
-        ))
+        simd_select(
+            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(32))),
+            vqtbx2_u8(a, x, c),
+            a,
+        )
     }
 }
 #[doc = "Extended table look-up"]
@@ -26226,13 +26231,13 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
+    let x = poly8x16x2_t(vcombine_p8(b.0, b.1), vcombine_p8(b.2, b.3));
     unsafe {
-        transmute(vqtbx2(
-            transmute(a),
-            transmute(vcombine_p8(b.0, b.1)),
-            transmute(vcombine_p8(b.2, b.3)),
-            c,
-        ))
+        simd_select(
+            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(32))),
+            vqtbx2_p8(a, x, c),
+            a,
+        )
     }
 }
 #[doc = "Transpose vectors"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 26b31b1e4c..9cceacec9d 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -12224,20 +12224,29 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
+    big_endian_inverse: false
     safety: safe
     types:
-      - [int8x8_t, int8x8x4_t]
+      - [int8x8_t, 'int8x8x4_t', 'int8x16x2', 'int8x8', 'i8x8::splat(32)']
     compose:
+      - Let:
+        - x
+        - FnCall:
+            - '{type[2]}_t'
+            - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']]
+              - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'b.3']]
       - FnCall:
-          - "vqtbx2"
-          - - FnCall: [transmute, [a]]
-            - FnCall:
-                - transmute
-                - - FnCall: ["vcombine{neon_type[0].noq}", ["b.0", "b.1"]]
-            - FnCall:
-                - transmute
-                - - FnCall: ["vcombine{neon_type[0].noq}", ["b.2", "b.3"]]
-            - FnCall: [transmute, [c]]
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[3]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[4]}"]]
+          - FnCall:
+              - 'vqtbx2{neon_type[0].no}'
+              - - a
+                - x
+                - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]]
+          - a
 
   - name: "vtbx4{neon_type[0].no}"
     doc: "Extended table look-up"
@@ -12249,21 +12258,27 @@ intrinsics:
     big_endian_inverse: false
     safety: safe
     types:
-      - [uint8x8_t, uint8x8x4_t, uint8x8_t]
-      - [poly8x8_t, poly8x8x4_t, uint8x8_t]
+      - [uint8x8_t, 'uint8x8x4_t', 'uint8x8_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(32)']
+      - [poly8x8_t, 'poly8x8x4_t', 'uint8x8_t', 'poly8x16x2', 'uint8x8', 'u8x8::splat(32)']
     compose:
+      - Let:
+        - x
+        - FnCall:
+            - '{type[3]}_t'
+            - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']]
+              - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'b.3']]
       - FnCall:
-          - transmute
-          - - FnCall:
-                - "vqtbx2"
-                - - FnCall: [transmute, [a]]
-                  - FnCall:
-                      - transmute
-                      - - FnCall: ["vcombine{neon_type[0].noq}", ["b.0", "b.1"]]
-                  - FnCall:
-                      - transmute
-                      - - FnCall: ["vcombine{neon_type[0].noq}", ["b.2", "b.3"]]
-                  - c
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[4]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[5]}"]]
+          - FnCall:
+              - 'vqtbx2{neon_type[0].no}'
+              - - a
+                - x
+                - c
+          - a
 
   - name: "vtbl1{neon_type[0].no}"
     doc: "Table look-up"
@@ -12461,28 +12476,49 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
+    big_endian_inverse: false
     safety: safe
     types:
-      - [int8x8_t, "int8x8_t", "transmute(c)", "i8x8::splat(8)", "int8x8"]
-      - [uint8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"]
-      - [poly8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"]
+      - [int8x8_t, "int8x8_t", "int8x8", "i8x8::splat(8)"]
     compose:
       - FnCall:
-          - simd_select
-          - - FnCall:
-                - "simd_lt::<{type[4]}_t, int8x8_t>"
-                - - c
-                  - FnCall: [transmute, ["{type[3]}"]]
-            - FnCall:
-                - transmute
-                - - FnCall:
-                      - "vqtbx1"
-                      - - "transmute(a)"
-                        - FnCall:
-                            - transmute
-                            - - FnCall: ["vcombine{neon_type[0].no}", [b, "crate::mem::zeroed()"]]
-                        - "{type[2]}"
-            - a
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[2]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[3]}"]]
+          - FnCall:
+            - 'vqtbx1{neon_type[0].no}'
+            - - a
+              - FnCall: ['vcombine{neon_type[0].no}', [b, 'crate::mem::zeroed()']]
+              - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]]
+          - a
+
+  - name: "vtbx1{neon_type[0].no}"
+    doc: "Extended table look-up"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
+    return_type: "{neon_type[0]}"
+    attr:
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
+      - *neon-stable
+    big_endian_inverse: false
+    safety: safe
+    types:
+      - [uint8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"]
+      - [poly8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"]
+    compose:
+      - FnCall:
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[2]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[3]}"]]
+          - FnCall:
+            - 'vqtbx1{neon_type[0].no}'
+            - - a
+              - FnCall: ['vcombine{neon_type[0].no}', [b, 'crate::mem::zeroed()']]
+              - c
+          - a
 
   - name: "vtbx2{neon_type[0].no}"
     doc: "Extended table look-up"
@@ -12491,17 +12527,23 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
+    big_endian_inverse: false
     safety: safe
     types:
-      - [int8x8_t, 'int8x8x2_t']
+      - [int8x8_t, 'int8x8x2_t', 'int8x8', 'i8x8::splat(16)']
     compose:
       - FnCall:
-          - vqtbx1
-          - - FnCall: [transmute, [a]]
-            - FnCall:
-                - transmute
-                - - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']]
-            - FnCall: [transmute, [c]]
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[2]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[3]}"]]
+          - FnCall:
+              - 'vqtbx1{neon_type[0].no}'
+              - - a
+                - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']]
+                - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]]
+          - a
 
   - name: "vtbx2{neon_type[0].no}"
     doc: "Extended table look-up"
@@ -12513,18 +12555,21 @@ intrinsics:
     big_endian_inverse: false
     safety: safe
     types:
-      - [uint8x8_t, 'uint8x8x2_t', uint8x8_t]
-      - [poly8x8_t, 'poly8x8x2_t', uint8x8_t]
+      - [uint8x8_t, 'uint8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)']
+      - [poly8x8_t, 'poly8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)']
     compose:
       - FnCall:
-          - transmute
-          - - FnCall:
-                - vqtbx1
-                - - FnCall: [transmute, [a]]
-                  - FnCall:
-                      - transmute
-                      - - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']]
-                  - c
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[3]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[4]}"]]
+          - FnCall:
+              - 'vqtbx1{neon_type[0].no}'
+              - - a
+                - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']]
+                - c
+          - a
 
   - name: "vtbx3{neon_type[0].no}"
     doc: "Extended table look-up"
@@ -12533,33 +12578,29 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
+    big_endian_inverse: false
     safety: safe
     types:
-      - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'i8x8::splat(24)', 'int8x8']
+      - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'int8x8', 'i8x8::splat(24)']
     compose:
       - Let:
-         - x
-         - FnCall:
-             - '{type[2]}_t'
-             - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']]
-               - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']]
+        - x
+        - FnCall:
+            - '{type[2]}_t'
+            - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']]
+              - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']]
       - FnCall:
-          - transmute
-          - - FnCall:
-                - simd_select
-                - - FnCall:
-                      - 'simd_lt::<{type[4]}_t, int8x8_t>'
-                      - - FnCall: [transmute, [c]]
-                        - FnCall: [transmute, ['{type[3]}']]
-                  - FnCall:
-                      - transmute
-                      - - FnCall:
-                            - 'vqtbx2'
-                            - - FnCall: [transmute, [a]]
-                              - FnCall: [transmute, ['x.0']]
-                              - FnCall: [transmute, ['x.1']]
-                              - FnCall: [transmute, [c]]
-                  - a
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[3]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[4]}"]]
+          - FnCall:
+              - 'vqtbx2{neon_type[0].no}'
+              - - a
+                - x
+                - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]]
+          - a
 
   - name: "vtbx3{neon_type[0].no}"
     doc: "Extended table look-up"
@@ -12568,11 +12609,11 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
+    big_endian_inverse: false
     safety: safe
     types:
-      - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8']
-      - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8']
-    big_endian_inverse: false
+      - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(24)']
+      - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'uint8x8', 'u8x8::splat(24)']
     compose:
       - Let:
          - x
@@ -12581,22 +12622,17 @@ intrinsics:
              - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']]
                - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']]
       - FnCall:
-          - transmute
-          - - FnCall:
-                - simd_select
-                - - FnCall:
-                      - 'simd_lt::<{type[4]}_t, int8x8_t>'
-                      - - FnCall: [transmute, [c]]
-                        - FnCall: [transmute, ['{type[3]}']]
-                  - FnCall:
-                      - transmute
-                      - - FnCall:
-                            - 'vqtbx2'
-                            - - FnCall: [transmute, [a]]
-                              - FnCall: [transmute, ['x.0']]
-                              - FnCall: [transmute, ['x.1']]
-                              - c
-                  - a
+        - simd_select
+        - - FnCall:
+              - "simd_lt::<{type[3]}_t, int8x8_t>"
+              - - c
+                - FnCall: [transmute, ["{type[4]}"]]
+          - FnCall:
+              - 'vqtbx2{neon_type[0].no}'
+              - - a
+                - x
+                - c
+          - a
 
   - name: "vqtbl1{neon_type[3].no}"
     doc: "Table look-up"

From a2f5209107a7d908d8a7298fe0be90cb03a43cb5 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Fri, 24 Apr 2026 23:59:46 +0800
Subject: [PATCH 290/326] loongarch: Use `intrinsics::simd` for vs{add,sub}

---
 .../src/loongarch64/lasx/generated.rs         | 144 ------------------
 .../src/loongarch64/lasx/portable.rs          |  16 ++
 .../src/loongarch64/lsx/generated.rs          | 144 ------------------
 .../core_arch/src/loongarch64/lsx/portable.rs |  16 ++
 crates/stdarch-gen-loongarch/lasx.spec        |  16 ++
 crates/stdarch-gen-loongarch/lsx.spec         |  16 ++
 .../src/portable-intrinsics.txt               |  32 ++++
 7 files changed, 96 insertions(+), 288 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index 29aed37e6b..387a3e564c 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -99,22 +99,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvadda_w(a: __v8i32, b: __v8i32) -> __v8i32;
     #[link_name = "llvm.loongarch.lasx.xvadda.d"]
     fn __lasx_xvadda_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.b"]
-    fn __lasx_xvsadd_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.h"]
-    fn __lasx_xvsadd_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.w"]
-    fn __lasx_xvsadd_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.d"]
-    fn __lasx_xvsadd_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.bu"]
-    fn __lasx_xvsadd_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.hu"]
-    fn __lasx_xvsadd_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.wu"]
-    fn __lasx_xvsadd_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvsadd.du"]
-    fn __lasx_xvsadd_du(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvavg.b"]
     fn __lasx_xvavg_b(a: __v32i8, b: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvavg.h"]
@@ -147,22 +131,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvavgr_wu(a: __v8u32, b: __v8u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvavgr.du"]
     fn __lasx_xvavgr_du(a: __v4u64, b: __v4u64) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvssub.b"]
-    fn __lasx_xvssub_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvssub.h"]
-    fn __lasx_xvssub_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvssub.w"]
-    fn __lasx_xvssub_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvssub.d"]
-    fn __lasx_xvssub_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvssub.bu"]
-    fn __lasx_xvssub_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvssub.hu"]
-    fn __lasx_xvssub_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvssub.wu"]
-    fn __lasx_xvssub_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvssub.du"]
-    fn __lasx_xvssub_du(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvabsd.b"]
     fn __lasx_xvabsd_b(a: __v32i8, b: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvabsd.h"]
@@ -1505,62 +1473,6 @@ pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1673,62 +1585,6 @@ pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lasx/portable.rs b/crates/core_arch/src/loongarch64/lasx/portable.rs
index 5f306502d9..147d94fe21 100644
--- a/crates/core_arch/src/loongarch64/lasx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -132,6 +132,22 @@ impl_vvv!("lasx", lasx_xvbitrev_b, ls::simd_bitrev, m256i, u8x32);
 impl_vvv!("lasx", lasx_xvbitrev_h, ls::simd_bitrev, m256i, u16x16);
 impl_vvv!("lasx", lasx_xvbitrev_w, ls::simd_bitrev, m256i, u32x8);
 impl_vvv!("lasx", lasx_xvbitrev_d, ls::simd_bitrev, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvsadd_b, is::simd_saturating_add, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvsadd_h, is::simd_saturating_add, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvsadd_w, is::simd_saturating_add, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvsadd_d, is::simd_saturating_add, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvsadd_bu, is::simd_saturating_add, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvsadd_hu, is::simd_saturating_add, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvsadd_wu, is::simd_saturating_add, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvsadd_du, is::simd_saturating_add, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvssub_b, is::simd_saturating_sub, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvssub_h, is::simd_saturating_sub, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvssub_w, is::simd_saturating_sub, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvssub_d, is::simd_saturating_sub, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvssub_bu, is::simd_saturating_sub, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvssub_hu, is::simd_saturating_sub, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvssub_wu, is::simd_saturating_sub, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvssub_du, is::simd_saturating_sub, m256i, u64x4);
 
 impl_vuv!("lasx", lasx_xvslli_b, is::simd_shl, m256i, i8x32);
 impl_vuv!("lasx", lasx_xvslli_h, is::simd_shl, m256i, i16x16);
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 529dc605c2..4f9a022c1d 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -99,22 +99,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vadda_w(a: __v4i32, b: __v4i32) -> __v4i32;
     #[link_name = "llvm.loongarch.lsx.vadda.d"]
     fn __lsx_vadda_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsadd.b"]
-    fn __lsx_vsadd_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vsadd.h"]
-    fn __lsx_vsadd_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vsadd.w"]
-    fn __lsx_vsadd_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vsadd.d"]
-    fn __lsx_vsadd_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vsadd.bu"]
-    fn __lsx_vsadd_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vsadd.hu"]
-    fn __lsx_vsadd_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vsadd.wu"]
-    fn __lsx_vsadd_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vsadd.du"]
-    fn __lsx_vsadd_du(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vavg.b"]
     fn __lsx_vavg_b(a: __v16i8, b: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vavg.h"]
@@ -147,22 +131,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vavgr_wu(a: __v4u32, b: __v4u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vavgr.du"]
     fn __lsx_vavgr_du(a: __v2u64, b: __v2u64) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vssub.b"]
-    fn __lsx_vssub_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vssub.h"]
-    fn __lsx_vssub_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vssub.w"]
-    fn __lsx_vssub_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vssub.d"]
-    fn __lsx_vssub_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vssub.bu"]
-    fn __lsx_vssub_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vssub.hu"]
-    fn __lsx_vssub_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vssub.wu"]
-    fn __lsx_vssub_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vssub.du"]
-    fn __lsx_vssub_du(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vabsd.b"]
     fn __lsx_vabsd_b(a: __v16i8, b: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vabsd.h"]
@@ -1417,62 +1385,6 @@ pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
@@ -1585,62 +1497,6 @@ pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lsx/portable.rs b/crates/core_arch/src/loongarch64/lsx/portable.rs
index f6b8daae4e..e98dcf050f 100644
--- a/crates/core_arch/src/loongarch64/lsx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -132,6 +132,22 @@ impl_vvv!("lsx", lsx_vbitrev_b, ls::simd_bitrev, m128i, u8x16);
 impl_vvv!("lsx", lsx_vbitrev_h, ls::simd_bitrev, m128i, u16x8);
 impl_vvv!("lsx", lsx_vbitrev_w, ls::simd_bitrev, m128i, u32x4);
 impl_vvv!("lsx", lsx_vbitrev_d, ls::simd_bitrev, m128i, u64x2);
+impl_vvv!("lsx", lsx_vsadd_b, is::simd_saturating_add, m128i, i8x16);
+impl_vvv!("lsx", lsx_vsadd_h, is::simd_saturating_add, m128i, i16x8);
+impl_vvv!("lsx", lsx_vsadd_w, is::simd_saturating_add, m128i, i32x4);
+impl_vvv!("lsx", lsx_vsadd_d, is::simd_saturating_add, m128i, i64x2);
+impl_vvv!("lsx", lsx_vsadd_bu, is::simd_saturating_add, m128i, u8x16);
+impl_vvv!("lsx", lsx_vsadd_hu, is::simd_saturating_add, m128i, u16x8);
+impl_vvv!("lsx", lsx_vsadd_wu, is::simd_saturating_add, m128i, u32x4);
+impl_vvv!("lsx", lsx_vsadd_du, is::simd_saturating_add, m128i, u64x2);
+impl_vvv!("lsx", lsx_vssub_b, is::simd_saturating_sub, m128i, i8x16);
+impl_vvv!("lsx", lsx_vssub_h, is::simd_saturating_sub, m128i, i16x8);
+impl_vvv!("lsx", lsx_vssub_w, is::simd_saturating_sub, m128i, i32x4);
+impl_vvv!("lsx", lsx_vssub_d, is::simd_saturating_sub, m128i, i64x2);
+impl_vvv!("lsx", lsx_vssub_bu, is::simd_saturating_sub, m128i, u8x16);
+impl_vvv!("lsx", lsx_vssub_hu, is::simd_saturating_sub, m128i, u16x8);
+impl_vvv!("lsx", lsx_vssub_wu, is::simd_saturating_sub, m128i, u32x4);
+impl_vvv!("lsx", lsx_vssub_du, is::simd_saturating_sub, m128i, u64x2);
 
 impl_vuv!("lsx", lsx_vslli_b, is::simd_shl, m128i, i8x16);
 impl_vuv!("lsx", lsx_vslli_h, is::simd_shl, m128i, i16x8);
diff --git a/crates/stdarch-gen-loongarch/lasx.spec b/crates/stdarch-gen-loongarch/lasx.spec
index 93317fca6b..27362d3259 100644
--- a/crates/stdarch-gen-loongarch/lasx.spec
+++ b/crates/stdarch-gen-loongarch/lasx.spec
@@ -944,41 +944,49 @@ asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvsadd_b
+impl = portable
 name = lasx_xvsadd_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvsadd_h
+impl = portable
 name = lasx_xvsadd_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvsadd_w
+impl = portable
 name = lasx_xvsadd_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvsadd_d
+impl = portable
 name = lasx_xvsadd_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvsadd_bu
+impl = portable
 name = lasx_xvsadd_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvsadd_hu
+impl = portable
 name = lasx_xvsadd_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvsadd_wu
+impl = portable
 name = lasx_xvsadd_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvsadd_du
+impl = portable
 name = lasx_xvsadd_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
@@ -1064,41 +1072,49 @@ asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
 
 /// lasx_xvssub_b
+impl = portable
 name = lasx_xvssub_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvssub_h
+impl = portable
 name = lasx_xvssub_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvssub_w
+impl = portable
 name = lasx_xvssub_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvssub_d
+impl = portable
 name = lasx_xvssub_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvssub_bu
+impl = portable
 name = lasx_xvssub_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvssub_hu
+impl = portable
 name = lasx_xvssub_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvssub_wu
+impl = portable
 name = lasx_xvssub_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvssub_du
+impl = portable
 name = lasx_xvssub_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
diff --git a/crates/stdarch-gen-loongarch/lsx.spec b/crates/stdarch-gen-loongarch/lsx.spec
index 274ebe4144..9b1b7cc245 100644
--- a/crates/stdarch-gen-loongarch/lsx.spec
+++ b/crates/stdarch-gen-loongarch/lsx.spec
@@ -944,41 +944,49 @@ asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vsadd_b
+impl = portable
 name = lsx_vsadd_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vsadd_h
+impl = portable
 name = lsx_vsadd_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vsadd_w
+impl = portable
 name = lsx_vsadd_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vsadd_d
+impl = portable
 name = lsx_vsadd_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vsadd_bu
+impl = portable
 name = lsx_vsadd_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vsadd_hu
+impl = portable
 name = lsx_vsadd_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vsadd_wu
+impl = portable
 name = lsx_vsadd_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vsadd_du
+impl = portable
 name = lsx_vsadd_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
@@ -1064,41 +1072,49 @@ asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
 
 /// lsx_vssub_b
+impl = portable
 name = lsx_vssub_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vssub_h
+impl = portable
 name = lsx_vssub_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vssub_w
+impl = portable
 name = lsx_vssub_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vssub_d
+impl = portable
 name = lsx_vssub_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vssub_bu
+impl = portable
 name = lsx_vssub_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vssub_hu
+impl = portable
 name = lsx_vssub_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vssub_wu
+impl = portable
 name = lsx_vssub_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vssub_du
+impl = portable
 name = lsx_vssub_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
diff --git a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
index f78f594cb9..423af4cd71 100644
--- a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
+++ b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -203,6 +203,22 @@ lsx_vbitrev_b
 lsx_vbitrev_h
 lsx_vbitrev_w
 lsx_vbitrev_d
+lsx_vsadd_b
+lsx_vsadd_h
+lsx_vsadd_w
+lsx_vsadd_d
+lsx_vsadd_bu
+lsx_vsadd_hu
+lsx_vsadd_wu
+lsx_vsadd_du
+lsx_vssub_b
+lsx_vssub_h
+lsx_vssub_w
+lsx_vssub_d
+lsx_vssub_bu
+lsx_vssub_hu
+lsx_vssub_wu
+lsx_vssub_du
 
 # LASX intrinsics
 lasx_xvsll_b
@@ -403,3 +419,19 @@ lasx_xvbitrev_b
 lasx_xvbitrev_h
 lasx_xvbitrev_w
 lasx_xvbitrev_d
+lasx_xvsadd_b
+lasx_xvsadd_h
+lasx_xvsadd_w
+lasx_xvsadd_d
+lasx_xvsadd_bu
+lasx_xvsadd_hu
+lasx_xvsadd_wu
+lasx_xvsadd_du
+lasx_xvssub_b
+lasx_xvssub_h
+lasx_xvssub_w
+lasx_xvssub_d
+lasx_xvssub_bu
+lasx_xvssub_hu
+lasx_xvssub_wu
+lasx_xvssub_du

From 7314bb3bc873b033d9edacc786e5ad57b0acb09b Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Fri, 1 May 2026 01:11:01 +0530
Subject: [PATCH 291/326] gen-arm: fix `vmlal`, `vmlsl` and `vmull`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 48 +++++++--------
 .../spec/neon/aarch64.spec.yml                | 60 +++++++++----------
 2 files changed, 54 insertions(+), 54 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 4bf10926e4..c67c277c7f 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -14520,7 +14520,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlal_high_s16(a, b, vdupq_lane_s16::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
@@ -14535,7 +14535,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
     c: int16x8_t,
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlal_high_s16(a, b, vdupq_laneq_s16::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
@@ -14546,7 +14546,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlal_high_s32(a, b, vdupq_lane_s32::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
@@ -14561,7 +14561,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
     c: int32x4_t,
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlal_high_s32(a, b, vdupq_laneq_s32::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
@@ -14576,7 +14576,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
     c: uint16x4_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlal_high_u16(a, b, vdupq_lane_u16::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
@@ -14591,7 +14591,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
     c: uint16x8_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlal_high_u16(a, b, vdupq_laneq_u16::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
@@ -14606,7 +14606,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
     c: uint32x2_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlal_high_u32(a, b, vdupq_lane_u32::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
@@ -14621,7 +14621,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
     c: uint32x4_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlal_high_u32(a, b, vdupq_laneq_u32::<LANE>(c))
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
@@ -14764,7 +14764,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlsl_high_s16(a, b, vdupq_lane_s16::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
@@ -14779,7 +14779,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
     c: int16x8_t,
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlsl_high_s16(a, b, vdupq_laneq_s16::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
@@ -14790,7 +14790,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlsl_high_s32(a, b, vdupq_lane_s32::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
@@ -14805,7 +14805,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
     c: int32x4_t,
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlsl_high_s32(a, b, vdupq_laneq_s32::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
@@ -14820,7 +14820,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
     c: uint16x4_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlsl_high_u16(a, b, vdupq_lane_u16::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
@@ -14835,7 +14835,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
     c: uint16x8_t,
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) }
+    vmlsl_high_u16(a, b, vdupq_laneq_u16::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
@@ -14850,7 +14850,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
     c: uint32x2_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlsl_high_u32(a, b, vdupq_lane_u32::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
@@ -14865,7 +14865,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
     c: uint32x4_t,
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) }
+    vmlsl_high_u32(a, b, vdupq_laneq_u32::<LANE>(c))
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
@@ -15270,7 +15270,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    vmull_high_s16(a, vdupq_lane_s16::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
@@ -15281,7 +15281,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    vmull_high_s16(a, vdupq_laneq_s16::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
@@ -15292,7 +15292,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmull_high_s32(a, vdupq_lane_s32::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
@@ -15303,7 +15303,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmull_high_s32(a, vdupq_laneq_s32::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
@@ -15314,7 +15314,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    vmull_high_u16(a, vdupq_lane_u16::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
@@ -15325,7 +15325,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    vmull_high_u16(a, vdupq_laneq_u16::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
@@ -15336,7 +15336,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmull_high_u32(a, vdupq_lane_u32::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
@@ -15347,7 +15347,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmull_high_u32(a, vdupq_laneq_u32::<LANE>(b))
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 9c59af1338..64408a4d92 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -11419,17 +11419,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
-      - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
-      - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
-      - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
+      - [int32x4_t, int16x8_t, int16x4_t, '2']
+      - [int32x4_t, int16x8_t, int16x8_t, '3']
+      - [int64x2_t, int32x4_t, int32x2_t, '1']
+      - [int64x2_t, int32x4_t, int32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmlsl_high_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vmlsl_high_lane{neon_type[2].no}"
     doc: "Multiply-subtract long"
@@ -11442,17 +11442,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]']
-      - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]']
-      - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]']
+      - [uint32x4_t, uint16x8_t, uint16x4_t, '2']
+      - [uint32x4_t, uint16x8_t, uint16x8_t, '3']
+      - [uint64x2_t, uint32x4_t, uint32x2_t, '1']
+      - [uint64x2_t, uint32x4_t, uint32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmlsl_high_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vclt{neon_type[0].no}"
     doc: "Floating-point compare less than"
@@ -11830,16 +11830,16 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32; 8]']
-      - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32; 8]']
-      - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32; 4]']
-      - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32; 4]']
+      - [int16x8_t, int16x4_t, int32x4_t, '2']
+      - [int16x8_t, int16x8_t, int32x4_t, '3']
+      - [int32x4_t, int32x2_t, int64x2_t, '1']
+      - [int32x4_t, int32x4_t, int64x2_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmull_high_{neon_type[0]}"
           - - a
-            - FnCall: [simd_shuffle!, [b, b, '{type[4]}']]
+            - FnCall: ['vdupq_lane{neon_type[1].no}', [b], [LANE]]
 
   - name: "vmull_high_lane{neon_type[1].no}"
     doc: "Multiply long"
@@ -11852,16 +11852,16 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32; 8]']
-      - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32; 8]']
-      - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32; 4]']
-      - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32; 4]']
+      - [uint16x8_t, uint16x4_t, uint32x4_t, '2']
+      - [uint16x8_t, uint16x8_t, uint32x4_t, '3']
+      - [uint32x4_t, uint32x2_t, uint64x2_t, '1']
+      - [uint32x4_t, uint32x4_t, uint64x2_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmull_high_{neon_type[0]}"
           - - a
-            - FnCall: [simd_shuffle!, [b, b, '{type[4]}']]
+            - FnCall: ['vdupq_lane{neon_type[1].no}', [b], [LANE]]
 
   - name: "vrsqrte{neon_type.no}"
     doc: "Reciprocal square-root estimate."
@@ -12143,13 +12143,13 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
-      - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
-      - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
-      - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
+      - [int32x4_t, int16x8_t, int16x4_t, '2']
+      - [int32x4_t, int16x8_t, int16x8_t, '3']
+      - [int64x2_t, int32x4_t, int32x2_t, '1']
+      - [int64x2_t, int32x4_t, int32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
-      - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]]
+      - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]}]]
 
   - name: "vmlal_high_lane{neon_type[2].no}"
     doc: "Multiply-add long"
@@ -12162,13 +12162,13 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]']
-      - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]']
-      - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]']
+      - [uint32x4_t, uint16x8_t, uint16x4_t, '2']
+      - [uint32x4_t, uint16x8_t, uint16x8_t, '3']
+      - [uint64x2_t, uint32x4_t, uint32x2_t, '1']
+      - [uint64x2_t, uint32x4_t, uint32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
-      - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]]
+      - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]}]]
 
   - name: "vrsrad_n_u64"
     doc: "Unsigned rounding shift right and accumulate."

From 47563140999f1f3995332cc93e6c25f125db59a3 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Fri, 1 May 2026 01:59:28 +0530
Subject: [PATCH 292/326] gen-arm: fix `vfmlal` and `vfmlsl`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 32 ++++++------
 .../spec/neon/aarch64.spec.yml                | 51 +++++++++----------
 2 files changed, 40 insertions(+), 43 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index c67c277c7f..5a0bbfa095 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -10756,7 +10756,7 @@ pub fn vfmlal_lane_high_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlal_high_f16(r, a, vdup_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"]
@@ -10773,7 +10773,7 @@ pub fn vfmlal_laneq_high_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlal_high_f16(r, a, vdup_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"]
@@ -10790,7 +10790,7 @@ pub fn vfmlalq_lane_high_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlalq_high_f16(r, a, vdupq_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"]
@@ -10807,7 +10807,7 @@ pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlalq_high_f16(r, a, vdupq_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"]
@@ -10824,7 +10824,7 @@ pub fn vfmlal_lane_low_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlal_low_f16(r, a, vdup_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"]
@@ -10841,7 +10841,7 @@ pub fn vfmlal_laneq_low_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlal_low_f16(r, a, vdup_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"]
@@ -10858,7 +10858,7 @@ pub fn vfmlalq_lane_low_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlalq_low_f16(r, a, vdupq_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"]
@@ -10875,7 +10875,7 @@ pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlalq_low_f16(r, a, vdupq_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"]
@@ -10964,7 +10964,7 @@ pub fn vfmlsl_lane_high_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlsl_high_f16(r, a, vdup_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"]
@@ -10981,7 +10981,7 @@ pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlsl_high_f16(r, a, vdup_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"]
@@ -10998,7 +10998,7 @@ pub fn vfmlslq_lane_high_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlslq_high_f16(r, a, vdupq_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"]
@@ -11015,7 +11015,7 @@ pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlslq_high_f16(r, a, vdupq_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"]
@@ -11032,7 +11032,7 @@ pub fn vfmlsl_lane_low_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlsl_low_f16(r, a, vdup_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"]
@@ -11049,7 +11049,7 @@ pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlsl_low_f16(r, a, vdup_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"]
@@ -11066,7 +11066,7 @@ pub fn vfmlslq_lane_low_f16<const LANE: i32>(
     b: float16x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlslq_low_f16(r, a, vdupq_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"]
@@ -11083,7 +11083,7 @@ pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
     b: float16x8_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) }
+    vfmlslq_low_f16(r, a, vdupq_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 64408a4d92..6950f69731 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -13920,7 +13920,7 @@ intrinsics:
               arch: aarch64,arm64ec
 
 
-  - name: "vfmlal{type[3]}{neon_type[1]}"
+  - name: "vfmlal{type[3]}_high_{neon_type[1]}"
     doc: "Floating-point fused Multiply-Add Long to accumulator (by element)."
     arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}",  "b: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
@@ -13934,18 +13934,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2']
-      - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3']
-      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_high_', 'q_high_', '2']
-      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_high_', 'q_high_', '3']
+      - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_high_', '2']
+      - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_high_', '3']
+      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_high_', '2']
+      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_high_', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]]
       - FnCall:
           - "vfmlal{type[4]}{neon_type[1]}"
           - - r
             - a
-            - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]]
-
+            - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]]
 
   - name: "vfmlal{type[2]}{neon_type[1]}"
     doc: "Floating-point fused Multiply-Add Long to accumulator (vector)."
@@ -13969,7 +13968,7 @@ intrinsics:
               arch: aarch64,arm64ec
 
 
-  - name: "vfmlal{type[3]}{neon_type[1]}"
+  - name: "vfmlal{type[3]}_low_{neon_type[1]}"
     doc: "Floating-point fused Multiply-Add Long to accumulator (by element)."
     arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}",  "b: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
@@ -13983,18 +13982,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2']
-      - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3']
-      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_low_', 'q_low_', '2']
-      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_low_', 'q_low_', '3']
+      - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_low_', '2']
+      - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_low_', '3']
+      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_low_', '2']
+      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_low_', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]]
       - FnCall:
           - "vfmlal{type[4]}{neon_type[1]}"
           - - r
             - a
-            - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]]
-
+            - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]]
 
   - name: "vfmlsl{type[2]}{neon_type[1]}"
     doc: "Floating-point fused Multiply-Subtract Long from accumulator (vector)."
@@ -14017,7 +14015,7 @@ intrinsics:
             - link: "llvm.aarch64.neon.fmlsl2.{neon_type[0]}.{neon_type[1]}"
               arch: aarch64,arm64ec
 
-  - name: "vfmlsl{type[3]}{neon_type[1]}"
+  - name: "vfmlsl{type[3]}_high_{neon_type[1]}"
     doc: "Floating-point fused Multiply-Subtract Long from accumulator (by element)."
     arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}",  "b: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
@@ -14031,18 +14029,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2']
-      - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3']
-      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_high_', 'q_high_', '2']
-      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_high_', 'q_high_', '3']
+      - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_high_', '2']
+      - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_high_', '3']
+      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_high_', '2']
+      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_high_', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]]
       - FnCall:
           - "vfmlsl{type[4]}{neon_type[1]}"
           - - r
             - a
-            - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]]
-
+            - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]]
 
   - name: "vfmlsl{type[2]}{neon_type[1]}"
     doc: "Floating-point fused Multiply-Subtract Long from accumulator (vector)."
@@ -14065,7 +14062,7 @@ intrinsics:
             - link: "llvm.aarch64.neon.fmlsl.{neon_type[0]}.{neon_type[1]}"
               arch: aarch64,arm64ec
 
-  - name: "vfmlsl{type[3]}{neon_type[1]}"
+  - name: "vfmlsl{type[3]}_low_{neon_type[1]}"
     doc: "Floating-point fused Multiply-Subtract Long from accumulator (by element)."
     arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}",  "b: {neon_type[2]}"]
     return_type: "{neon_type[0]}"
@@ -14079,17 +14076,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2']
-      - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3']
-      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_low_', 'q_low_', '2']
-      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_low_', 'q_low_', '3']
+      - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_low_', '2']
+      - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_low_', '3']
+      - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_low_', '2']
+      - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_low_', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]]
       - FnCall:
           - "vfmlsl{type[4]}{neon_type[1]}"
           - - r
             - a
-            - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]]
+            - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]]
 
   - name: "vamax{neon_type.no}"
     doc: "Multi-vector floating-point absolute maximum"

From 20be9139d78c637810126bf78060466e5aa2979a Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Fri, 8 May 2026 14:50:34 +0530
Subject: [PATCH 293/326] replace uses of `simd_extract` with `vget_lane`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 558 ++++++++----------
 .../src/arm_shared/neon/generated.rs          |  14 +-
 .../spec/neon/aarch64.spec.yml                | 327 +++++-----
 .../spec/neon/arm_shared.spec.yml             |  10 +-
 4 files changed, 423 insertions(+), 486 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 5a0bbfa095..2624e2f22d 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -204,7 +204,7 @@ pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
 pub fn vabdd_f64(a: f64, b: f64) -> f64 {
-    unsafe { simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) }
+    vget_lane_f64::<0>(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)))
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"]
@@ -213,7 +213,7 @@ pub fn vabdd_f64(a: f64, b: f64) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
 pub fn vabds_f32(a: f32, b: f32) -> f32 {
-    unsafe { simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) }
+    vget_lane_f32::<0>(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)))
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"]
@@ -223,7 +223,7 @@ pub fn vabds_f32(a: f32, b: f32) -> f32 {
 #[cfg(not(target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(fabd))]
 pub fn vabdh_f16(a: f16, b: f16) -> f16 {
-    unsafe { simd_extract!(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) }
+    vget_lane_f16::<0>(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
@@ -1539,7 +1539,7 @@ pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vceqd_f64(a: f64, b: f64) -> u64 {
-    unsafe { simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) }
+    vget_lane_u64::<0>(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)))
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"]
@@ -1548,7 +1548,7 @@ pub fn vceqd_f64(a: f64, b: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vceqs_f32(a: f32, b: f32) -> u32 {
-    unsafe { simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) }
+    vget_lane_u32::<0>(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)))
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"]
@@ -1576,7 +1576,7 @@ pub fn vceqd_u64(a: u64, b: u64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqh_f16(a: f16, b: f16) -> u16 {
-    unsafe { simd_extract!(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) }
+    vget_lane_u16::<0>(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"]
@@ -1866,7 +1866,7 @@ pub fn vceqzd_u64(a: u64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vceqzh_f16(a: f16) -> u16 {
-    unsafe { simd_extract!(vceqz_f16(vdup_n_f16(a)), 0) }
+    vget_lane_u16::<0>(vceqz_f16(vdup_n_f16(a)))
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"]
@@ -1875,7 +1875,7 @@ pub fn vceqzh_f16(a: f16) -> u16 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vceqzs_f32(a: f32) -> u32 {
-    unsafe { simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) }
+    vget_lane_u32::<0>(vceqz_f32(vdup_n_f32(a)))
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"]
@@ -1884,7 +1884,7 @@ pub fn vceqzs_f32(a: f32) -> u32 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vceqzd_f64(a: f64) -> u64 {
-    unsafe { simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) }
+    vget_lane_u64::<0>(vceqz_f64(vdup_n_f64(a)))
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"]
@@ -1947,7 +1947,7 @@ pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcged_f64(a: f64, b: f64) -> u64 {
-    unsafe { simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) }
+    vget_lane_u64::<0>(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)))
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"]
@@ -1956,7 +1956,7 @@ pub fn vcged_f64(a: f64, b: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcges_f32(a: f32, b: f32) -> u32 {
-    unsafe { simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) }
+    vget_lane_u32::<0>(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)))
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"]
@@ -1984,7 +1984,7 @@ pub fn vcged_u64(a: u64, b: u64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgeh_f16(a: f16, b: f16) -> u16 {
-    unsafe { simd_extract!(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) }
+    vget_lane_u16::<0>(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"]
@@ -2113,7 +2113,7 @@ pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcgezd_f64(a: f64) -> u64 {
-    unsafe { simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) }
+    vget_lane_u64::<0>(vcgez_f64(vdup_n_f64(a)))
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"]
@@ -2122,7 +2122,7 @@ pub fn vcgezd_f64(a: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcgezs_f32(a: f32) -> u32 {
-    unsafe { simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) }
+    vget_lane_u32::<0>(vcgez_f32(vdup_n_f32(a)))
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"]
@@ -2141,7 +2141,7 @@ pub fn vcgezd_s64(a: i64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgezh_f16(a: f16) -> u16 {
-    unsafe { simd_extract!(vcgez_f16(vdup_n_f16(a)), 0) }
+    vget_lane_u16::<0>(vcgez_f16(vdup_n_f16(a)))
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"]
@@ -2204,7 +2204,7 @@ pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcgtd_f64(a: f64, b: f64) -> u64 {
-    unsafe { simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) }
+    vget_lane_u64::<0>(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)))
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"]
@@ -2213,7 +2213,7 @@ pub fn vcgtd_f64(a: f64, b: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcgts_f32(a: f32, b: f32) -> u32 {
-    unsafe { simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) }
+    vget_lane_u32::<0>(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)))
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"]
@@ -2241,7 +2241,7 @@ pub fn vcgtd_u64(a: u64, b: u64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgth_f16(a: f16, b: f16) -> u16 {
-    unsafe { simd_extract!(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) }
+    vget_lane_u16::<0>(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"]
@@ -2370,7 +2370,7 @@ pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcgtzd_f64(a: f64) -> u64 {
-    unsafe { simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) }
+    vget_lane_u64::<0>(vcgtz_f64(vdup_n_f64(a)))
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"]
@@ -2379,7 +2379,7 @@ pub fn vcgtzd_f64(a: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcgtzs_f32(a: f32) -> u32 {
-    unsafe { simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) }
+    vget_lane_u32::<0>(vcgtz_f32(vdup_n_f32(a)))
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"]
@@ -2398,7 +2398,7 @@ pub fn vcgtzd_s64(a: i64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcgtzh_f16(a: f16) -> u16 {
-    unsafe { simd_extract!(vcgtz_f16(vdup_n_f16(a)), 0) }
+    vget_lane_u16::<0>(vcgtz_f16(vdup_n_f16(a)))
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"]
@@ -2461,7 +2461,7 @@ pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcled_f64(a: f64, b: f64) -> u64 {
-    unsafe { simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) }
+    vget_lane_u64::<0>(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)))
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"]
@@ -2470,7 +2470,7 @@ pub fn vcled_f64(a: f64, b: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcles_f32(a: f32, b: f32) -> u32 {
-    unsafe { simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) }
+    vget_lane_u32::<0>(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)))
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"]
@@ -2498,7 +2498,7 @@ pub fn vcled_s64(a: i64, b: i64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcleh_f16(a: f16, b: f16) -> u16 {
-    unsafe { simd_extract!(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) }
+    vget_lane_u16::<0>(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"]
@@ -2627,7 +2627,7 @@ pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vclezd_f64(a: f64) -> u64 {
-    unsafe { simd_extract!(vclez_f64(vdup_n_f64(a)), 0) }
+    vget_lane_u64::<0>(vclez_f64(vdup_n_f64(a)))
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"]
@@ -2636,7 +2636,7 @@ pub fn vclezd_f64(a: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vclezs_f32(a: f32) -> u32 {
-    unsafe { simd_extract!(vclez_f32(vdup_n_f32(a)), 0) }
+    vget_lane_u32::<0>(vclez_f32(vdup_n_f32(a)))
 }
 #[doc = "Compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"]
@@ -2655,7 +2655,7 @@ pub fn vclezd_s64(a: i64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vclezh_f16(a: f16) -> u16 {
-    unsafe { simd_extract!(vclez_f16(vdup_n_f16(a)), 0) }
+    vget_lane_u16::<0>(vclez_f16(vdup_n_f16(a)))
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"]
@@ -2737,7 +2737,7 @@ pub fn vcltd_s64(a: i64, b: i64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vclth_f16(a: f16, b: f16) -> u16 {
-    unsafe { simd_extract!(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) }
+    vget_lane_u16::<0>(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"]
@@ -2746,7 +2746,7 @@ pub fn vclth_f16(a: f16, b: f16) -> u16 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vclts_f32(a: f32, b: f32) -> u32 {
-    unsafe { simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) }
+    vget_lane_u32::<0>(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)))
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"]
@@ -2755,7 +2755,7 @@ pub fn vclts_f32(a: f32, b: f32) -> u32 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcltd_f64(a: f64, b: f64) -> u64 {
-    unsafe { simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) }
+    vget_lane_u64::<0>(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)))
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"]
@@ -2884,7 +2884,7 @@ pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcltzd_f64(a: f64) -> u64 {
-    unsafe { simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) }
+    vget_lane_u64::<0>(vcltz_f64(vdup_n_f64(a)))
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"]
@@ -2893,7 +2893,7 @@ pub fn vcltzd_f64(a: f64) -> u64 {
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcltzs_f32(a: f32) -> u32 {
-    unsafe { simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) }
+    vget_lane_u32::<0>(vcltz_f32(vdup_n_f32(a)))
 }
 #[doc = "Compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"]
@@ -2912,7 +2912,7 @@ pub fn vcltzd_s64(a: i64) -> u64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcltzh_f16(a: f16) -> u16 {
-    unsafe { simd_extract!(vcltz_f16(vdup_n_f16(a)), 0) }
+    vget_lane_u16::<0>(vcltz_f16(vdup_n_f16(a)))
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"]
@@ -4662,7 +4662,7 @@ pub fn vcopy_laneq_f64<const LANE1: i32, const LANE2: i32>(
 ) -> float64x1_t {
     static_assert!(LANE1 == 0);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<f64, _>(simd_extract!(b, LANE2 as u32)) }
+    unsafe { transmute(vgetq_lane_f64::<LANE2>(b)) }
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s64)"]
@@ -4677,7 +4677,7 @@ pub fn vcopy_laneq_s64<const LANE1: i32, const LANE2: i32>(
 ) -> int64x1_t {
     static_assert!(LANE1 == 0);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<i64, _>(simd_extract!(b, LANE2 as u32)) }
+    unsafe { transmute(vgetq_lane_s64::<LANE2>(b)) }
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u64)"]
@@ -4692,7 +4692,7 @@ pub fn vcopy_laneq_u64<const LANE1: i32, const LANE2: i32>(
 ) -> uint64x1_t {
     static_assert!(LANE1 == 0);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
+    unsafe { transmute(vgetq_lane_u64::<LANE2>(b)) }
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p64)"]
@@ -4707,7 +4707,7 @@ pub fn vcopy_laneq_p64<const LANE1: i32, const LANE2: i32>(
 ) -> poly64x1_t {
     static_assert!(LANE1 == 0);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
+    unsafe { transmute(vgetq_lane_p64::<LANE2>(b)) }
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
@@ -9763,7 +9763,7 @@ pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvtxd_f32_f64(a: f64) -> f32 {
-    unsafe { simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) }
+    vget_lane_f32::<0>(vcvtx_f32_f64(vdupq_n_f64(a)))
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
@@ -9862,7 +9862,7 @@ pub fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe { transmute::<f64, _>(simd_extract!(a, N as u32)) }
+    unsafe { transmute(vgetq_lane_f64::<N>(a)) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"]
@@ -9873,7 +9873,7 @@ pub fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
+    unsafe { transmute(vgetq_lane_p64::<N>(a)) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"]
@@ -9884,7 +9884,7 @@ pub fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_s8::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"]
@@ -9895,7 +9895,7 @@ pub fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_s16::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"]
@@ -9906,7 +9906,7 @@ pub fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_u8::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"]
@@ -9917,7 +9917,7 @@ pub fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_u16::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"]
@@ -9928,7 +9928,7 @@ pub fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_p8::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"]
@@ -9939,7 +9939,7 @@ pub fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_p16::<N>(a)
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"]
@@ -9950,7 +9950,7 @@ pub fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_s8::<N>(a)
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"]
@@ -9961,7 +9961,7 @@ pub fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_u8::<N>(a)
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"]
@@ -9972,7 +9972,7 @@ pub fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_p8::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"]
@@ -9983,7 +9983,7 @@ pub fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
     static_assert!(N == 0);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_f64::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"]
@@ -9994,7 +9994,7 @@ pub fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
     static_assert!(N == 0);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_s64::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"]
@@ -10005,7 +10005,7 @@ pub fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
     static_assert!(N == 0);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_u64::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"]
@@ -10017,7 +10017,7 @@ pub fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vduph_lane_f16<const N: i32>(a: float16x4_t) -> f16 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_f16::<N>(a)
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"]
@@ -10029,7 +10029,7 @@ pub fn vduph_lane_f16<const N: i32>(a: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vduph_laneq_f16<const N: i32>(a: float16x8_t) -> f16 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_f16::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"]
@@ -10084,7 +10084,7 @@ pub fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
     static_assert_uimm_bits!(N, 1);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_f32::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"]
@@ -10095,7 +10095,7 @@ pub fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
     static_assert_uimm_bits!(N, 1);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_f64::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"]
@@ -10106,7 +10106,7 @@ pub fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
     static_assert_uimm_bits!(N, 1);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_s32::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"]
@@ -10117,7 +10117,7 @@ pub fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
     static_assert_uimm_bits!(N, 1);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_s64::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"]
@@ -10128,7 +10128,7 @@ pub fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
     static_assert_uimm_bits!(N, 1);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_u32::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"]
@@ -10139,7 +10139,7 @@ pub fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
     static_assert_uimm_bits!(N, 1);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_u64::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"]
@@ -10150,7 +10150,7 @@ pub fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_f32::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"]
@@ -10161,7 +10161,7 @@ pub fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_s16::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"]
@@ -10172,7 +10172,7 @@ pub fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_s32::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"]
@@ -10183,7 +10183,7 @@ pub fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_u16::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"]
@@ -10194,7 +10194,7 @@ pub fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vgetq_lane_u32::<N>(a)
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"]
@@ -10205,7 +10205,7 @@ pub fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
     static_assert_uimm_bits!(N, 2);
-    unsafe { simd_extract!(a, N as u32) }
+    vget_lane_p16::<N>(a)
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"]
@@ -10392,7 +10392,7 @@ pub fn vfma_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) }
+    vfma_f16(a, b, vdup_n_f16(vget_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"]
@@ -10408,7 +10408,7 @@ pub fn vfma_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) }
+    vfma_f16(a, b, vdup_n_f16(vgetq_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"]
@@ -10424,7 +10424,7 @@ pub fn vfmaq_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) }
+    vfmaq_f16(a, b, vdupq_n_f16(vget_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"]
@@ -10440,7 +10440,7 @@ pub fn vfmaq_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) }
+    vfmaq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"]
@@ -10455,7 +10455,7 @@ pub fn vfma_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) }
+    vfma_f32(a, b, vdup_n_f32(vget_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"]
@@ -10470,7 +10470,7 @@ pub fn vfma_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) }
+    vfma_f32(a, b, vdup_n_f32(vgetq_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"]
@@ -10485,7 +10485,7 @@ pub fn vfmaq_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) }
+    vfmaq_f32(a, b, vdupq_n_f32(vget_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"]
@@ -10500,7 +10500,7 @@ pub fn vfmaq_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) }
+    vfmaq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"]
@@ -10515,7 +10515,7 @@ pub fn vfmaq_laneq_f64<const LANE: i32>(
     c: float64x2_t,
 ) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) }
+    vfmaq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"]
@@ -10530,7 +10530,7 @@ pub fn vfma_lane_f64<const LANE: i32>(
     c: float64x1_t,
 ) -> float64x1_t {
     static_assert!(LANE == 0);
-    unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) }
+    vfma_f64(a, b, vdup_n_f64(vget_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
@@ -10545,7 +10545,7 @@ pub fn vfma_laneq_f64<const LANE: i32>(
     c: float64x2_t,
 ) -> float64x1_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) }
+    vfma_f64(a, b, vdup_n_f64(vgetq_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"]
@@ -10585,10 +10585,8 @@ pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: f64 = simd_extract!(c, LANE as u32);
-        fmaf64(b, c, a)
-    }
+    let c: f64 = vget_lane_f64::<LANE>(c);
+    fmaf64(b, c, a)
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"]
@@ -10610,10 +10608,8 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: f16 = simd_extract!(v, LANE as u32);
-        vfmah_f16(a, b, c)
-    }
+    let c: f16 = vget_lane_f16::<LANE>(v);
+    vfmah_f16(a, b, c)
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
@@ -10625,10 +10621,8 @@ pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmah_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let c: f16 = simd_extract!(v, LANE as u32);
-        vfmah_f16(a, b, c)
-    }
+    let c: f16 = vgetq_lane_f16::<LANE>(v);
+    vfmah_f16(a, b, c)
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"]
@@ -10652,7 +10646,7 @@ pub fn vfmaq_lane_f64<const LANE: i32>(
     c: float64x1_t,
 ) -> float64x2_t {
     static_assert!(LANE == 0);
-    unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) }
+    vfmaq_f64(a, b, vdupq_n_f64(vget_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"]
@@ -10672,10 +10666,8 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: f32 = simd_extract!(c, LANE as u32);
-        fmaf32(b, c, a)
-    }
+    let c: f32 = vget_lane_f32::<LANE>(c);
+    fmaf32(b, c, a)
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
@@ -10686,10 +10678,8 @@ pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: f32 = simd_extract!(c, LANE as u32);
-        fmaf32(b, c, a)
-    }
+    let c: f32 = vgetq_lane_f32::<LANE>(c);
+    fmaf32(b, c, a)
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
@@ -10700,10 +10690,8 @@ pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: f64 = simd_extract!(c, LANE as u32);
-        fmaf64(b, c, a)
-    }
+    let c: f64 = vgetq_lane_f64::<LANE>(c);
+    fmaf64(b, c, a)
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"]
@@ -11147,7 +11135,7 @@ pub fn vfms_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) }
+    vfms_f16(a, b, vdup_n_f16(vget_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"]
@@ -11163,7 +11151,7 @@ pub fn vfms_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) }
+    vfms_f16(a, b, vdup_n_f16(vgetq_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"]
@@ -11179,7 +11167,7 @@ pub fn vfmsq_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) }
+    vfmsq_f16(a, b, vdupq_n_f16(vget_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"]
@@ -11195,7 +11183,7 @@ pub fn vfmsq_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) }
+    vfmsq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"]
@@ -11210,7 +11198,7 @@ pub fn vfms_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) }
+    vfms_f32(a, b, vdup_n_f32(vget_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"]
@@ -11225,7 +11213,7 @@ pub fn vfms_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) }
+    vfms_f32(a, b, vdup_n_f32(vgetq_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"]
@@ -11240,7 +11228,7 @@ pub fn vfmsq_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) }
+    vfmsq_f32(a, b, vdupq_n_f32(vget_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"]
@@ -11255,7 +11243,7 @@ pub fn vfmsq_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) }
+    vfmsq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"]
@@ -11270,7 +11258,7 @@ pub fn vfmsq_laneq_f64<const LANE: i32>(
     c: float64x2_t,
 ) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) }
+    vfmsq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"]
@@ -11285,7 +11273,7 @@ pub fn vfms_lane_f64<const LANE: i32>(
     c: float64x1_t,
 ) -> float64x1_t {
     static_assert!(LANE == 0);
-    unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) }
+    vfms_f64(a, b, vdup_n_f64(vget_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
@@ -11300,7 +11288,7 @@ pub fn vfms_laneq_f64<const LANE: i32>(
     c: float64x2_t,
 ) -> float64x1_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) }
+    vfms_f64(a, b, vdup_n_f64(vgetq_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"]
@@ -11351,10 +11339,8 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: f16 = simd_extract!(v, LANE as u32);
-        vfmsh_f16(a, b, c)
-    }
+    let c: f16 = vget_lane_f16::<LANE>(v);
+    vfmsh_f16(a, b, c)
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
@@ -11366,10 +11352,8 @@ pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vfmsh_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let c: f16 = simd_extract!(v, LANE as u32);
-        vfmsh_f16(a, b, c)
-    }
+    let c: f16 = vgetq_lane_f16::<LANE>(v);
+    vfmsh_f16(a, b, c)
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"]
@@ -11396,7 +11380,7 @@ pub fn vfmsq_lane_f64<const LANE: i32>(
     c: float64x1_t,
 ) -> float64x2_t {
     static_assert!(LANE == 0);
-    unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) }
+    vfmsq_f64(a, b, vdupq_n_f64(vget_lane_f64::<LANE>(c)))
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"]
@@ -15152,7 +15136,7 @@ pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t {
     static_assert!(LANE == 0);
-    unsafe { simd_mul(a, transmute::<f64, _>(simd_extract!(b, LANE as u32))) }
+    unsafe { simd_mul(a, transmute::<f64, _>(vget_lane_f64::<LANE>(b))) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"]
@@ -15187,7 +15171,7 @@ pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { simd_mul(a, transmute::<f64, _>(simd_extract!(b, LANE as u32))) }
+    unsafe { simd_mul(a, transmute::<f64, _>(vgetq_lane_f64::<LANE>(b))) }
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"]
@@ -15216,10 +15200,8 @@ pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
     static_assert!(LANE == 0);
-    unsafe {
-        let b: f64 = simd_extract!(b, LANE as u32);
-        a * b
-    }
+    let b: f64 = vget_lane_f64::<LANE>(b);
+    a * b
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"]
@@ -15241,10 +15223,8 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let b: f16 = simd_extract!(b, LANE as u32);
-        a * b
-    }
+    let b: f16 = vget_lane_f16::<LANE>(b);
+    a * b
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"]
@@ -15256,10 +15236,8 @@ pub fn vmulh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let b: f16 = simd_extract!(b, LANE as u32);
-        a * b
-    }
+    let b: f16 = vgetq_lane_f16::<LANE>(b);
+    a * b
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
@@ -15392,7 +15370,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
 pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
-    unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) }
+    vmull_p64(vgetq_lane_p64::<1>(a), vgetq_lane_p64::<1>(b))
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"]
@@ -15532,10 +15510,8 @@ pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let b: f32 = simd_extract!(b, LANE as u32);
-        a * b
-    }
+    let b: f32 = vget_lane_f32::<LANE>(b);
+    a * b
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"]
@@ -15546,10 +15522,8 @@ pub fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let b: f32 = simd_extract!(b, LANE as u32);
-        a * b
-    }
+    let b: f32 = vgetq_lane_f32::<LANE>(b);
+    a * b
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"]
@@ -15560,10 +15534,8 @@ pub fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let b: f64 = simd_extract!(b, LANE as u32);
-        a * b
-    }
+    let b: f64 = vgetq_lane_f64::<LANE>(b);
+    a * b
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
@@ -15775,7 +15747,7 @@ pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> floa
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t {
     static_assert!(LANE == 0);
-    unsafe { vmulx_f64(a, transmute::<f64, _>(simd_extract!(b, LANE as u32))) }
+    unsafe { vmulx_f64(a, transmute(vget_lane_f64::<LANE>(b))) }
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"]
@@ -15786,7 +15758,7 @@ pub fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float6
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulx_f64(a, transmute::<f64, _>(simd_extract!(b, LANE as u32))) }
+    unsafe { vmulx_f64(a, transmute(vgetq_lane_f64::<LANE>(b))) }
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"]
@@ -15849,7 +15821,7 @@ pub fn vmulxs_f32(a: f32, b: f32) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
     static_assert!(LANE == 0);
-    unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) }
+    vmulxd_f64(a, vget_lane_f64::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"]
@@ -15860,7 +15832,7 @@ pub fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) }
+    vmulxd_f64(a, vgetq_lane_f64::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"]
@@ -15871,7 +15843,7 @@ pub fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) }
+    vmulxs_f32(a, vget_lane_f32::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"]
@@ -15882,7 +15854,7 @@ pub fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) }
+    vmulxs_f32(a, vgetq_lane_f32::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"]
@@ -15911,7 +15883,7 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) }
+    vmulxh_f16(a, vget_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"]
@@ -15923,7 +15895,7 @@ pub fn vmulxh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) }
+    vmulxh_f16(a, vgetq_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"]
@@ -15998,11 +15970,9 @@ pub fn vnegh_f16(a: f16) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vpaddd_f64(a: float64x2_t) -> f64 {
-    unsafe {
-        let a1: f64 = simd_extract!(a, 0);
-        let a2: f64 = simd_extract!(a, 1);
-        a1 + a2
-    }
+    let a1: f64 = vgetq_lane_f64::<0>(a);
+    let a2: f64 = vgetq_lane_f64::<1>(a);
+    a1 + a2
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"]
@@ -16011,11 +15981,9 @@ pub fn vpaddd_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
 pub fn vpadds_f32(a: float32x2_t) -> f32 {
-    unsafe {
-        let a1: f32 = simd_extract!(a, 0);
-        let a2: f32 = simd_extract!(a, 1);
-        a1 + a2
-    }
+    let a1: f32 = vget_lane_f32::<0>(a);
+    let a2: f32 = vget_lane_f32::<1>(a);
+    a1 + a2
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
@@ -16834,7 +16802,7 @@ pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
 pub fn vqabsb_s8(a: i8) -> i8 {
-    unsafe { simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) }
+    vget_lane_s8::<0>(vqabs_s8(vdup_n_s8(a)))
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"]
@@ -16843,7 +16811,7 @@ pub fn vqabsb_s8(a: i8) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
 pub fn vqabsh_s16(a: i16) -> i16 {
-    unsafe { simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) }
+    vget_lane_s16::<0>(vqabs_s16(vdup_n_s16(a)))
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"]
@@ -16886,7 +16854,7 @@ pub fn vqabsd_s64(a: i64) -> i64 {
 pub fn vqaddb_s8(a: i8, b: i8) -> i8 {
     let a: int8x8_t = vdup_n_s8(a);
     let b: int8x8_t = vdup_n_s8(b);
-    unsafe { simd_extract!(vqadd_s8(a, b), 0) }
+    vget_lane_s8::<0>(vqadd_s8(a, b))
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"]
@@ -16897,7 +16865,7 @@ pub fn vqaddb_s8(a: i8, b: i8) -> i8 {
 pub fn vqaddh_s16(a: i16, b: i16) -> i16 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
-    unsafe { simd_extract!(vqadd_s16(a, b), 0) }
+    vget_lane_s16::<0>(vqadd_s16(a, b))
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"]
@@ -16908,7 +16876,7 @@ pub fn vqaddh_s16(a: i16, b: i16) -> i16 {
 pub fn vqaddb_u8(a: u8, b: u8) -> u8 {
     let a: uint8x8_t = vdup_n_u8(a);
     let b: uint8x8_t = vdup_n_u8(b);
-    unsafe { simd_extract!(vqadd_u8(a, b), 0) }
+    vget_lane_u8::<0>(vqadd_u8(a, b))
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"]
@@ -16919,7 +16887,7 @@ pub fn vqaddb_u8(a: u8, b: u8) -> u8 {
 pub fn vqaddh_u16(a: u16, b: u16) -> u16 {
     let a: uint16x4_t = vdup_n_u16(a);
     let b: uint16x4_t = vdup_n_u16(b);
-    unsafe { simd_extract!(vqadd_u16(a, b), 0) }
+    vget_lane_u16::<0>(vqadd_u16(a, b))
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"]
@@ -17096,7 +17064,7 @@ pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlalh_s16(a, b, vget_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
@@ -17107,7 +17075,7 @@ pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlalh_s16(a, b, vgetq_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
@@ -17118,7 +17086,7 @@ pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlals_s32(a, b, vget_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
@@ -17129,7 +17097,7 @@ pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlals_s32(a, b, vgetq_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
@@ -17139,7 +17107,7 @@ pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
     let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));
-    unsafe { vqadds_s32(a, simd_extract!(x, 0)) }
+    vqadds_s32(a, vgetq_lane_s32::<0>(x))
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"]
@@ -17262,7 +17230,7 @@ pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlslh_s16(a, b, vget_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
@@ -17273,7 +17241,7 @@ pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlslh_s16(a, b, vgetq_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
@@ -17284,7 +17252,7 @@ pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlsls_s32(a, b, vget_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
@@ -17295,7 +17263,7 @@ pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqdmlsls_s32(a, b, vgetq_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
@@ -17305,7 +17273,7 @@ pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
     let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));
-    unsafe { vqsubs_s32(a, simd_extract!(x, 0)) }
+    vqsubs_s32(a, vgetq_lane_s32::<0>(x))
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"]
@@ -17326,7 +17294,7 @@ pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
+    vqdmulh_s16(a, vdup_n_s16(vget_lane_s16::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"]
@@ -17337,7 +17305,7 @@ pub fn vqdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
+    vqdmulhq_s16(a, vdupq_n_s16(vget_lane_s16::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"]
@@ -17348,7 +17316,7 @@ pub fn vqdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
+    vqdmulh_s32(a, vdup_n_s32(vget_lane_s32::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"]
@@ -17359,7 +17327,7 @@ pub fn vqdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
+    vqdmulhq_s32(a, vdupq_n_s32(vget_lane_s32::<LANE>(b)))
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"]
@@ -17370,10 +17338,8 @@ pub fn vqdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let b: i16 = simd_extract!(b, N as u32);
-        vqdmulhh_s16(a, b)
-    }
+    let b: i16 = vget_lane_s16::<N>(b);
+    vqdmulhh_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"]
@@ -17384,10 +17350,8 @@ pub fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        let b: i16 = simd_extract!(b, N as u32);
-        vqdmulhh_s16(a, b)
-    }
+    let b: i16 = vgetq_lane_s16::<N>(b);
+    vqdmulhh_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"]
@@ -17398,7 +17362,7 @@ pub fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 {
 pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
-    unsafe { simd_extract!(vqdmulh_s16(a, b), 0) }
+    vget_lane_s16::<0>(vqdmulh_s16(a, b))
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"]
@@ -17409,7 +17373,7 @@ pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 {
 pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 {
     let a: int32x2_t = vdup_n_s32(a);
     let b: int32x2_t = vdup_n_s32(b);
-    unsafe { simd_extract!(vqdmulh_s32(a, b), 0) }
+    vget_lane_s32::<0>(vqdmulh_s32(a, b))
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"]
@@ -17420,10 +17384,8 @@ pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        let b: i32 = simd_extract!(b, N as u32);
-        vqdmulhs_s32(a, b)
-    }
+    let b: i32 = vget_lane_s32::<N>(b);
+    vqdmulhs_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"]
@@ -17434,10 +17396,8 @@ pub fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let b: i32 = simd_extract!(b, N as u32);
-        vqdmulhs_s32(a, b)
-    }
+    let b: i32 = vgetq_lane_s32::<N>(b);
+    vqdmulhs_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
@@ -17588,10 +17548,8 @@ pub fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let b: i16 = simd_extract!(b, N as u32);
-        vqdmullh_s16(a, b)
-    }
+    let b: i16 = vget_lane_s16::<N>(b);
+    vqdmullh_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"]
@@ -17602,10 +17560,8 @@ pub fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let b: i32 = simd_extract!(b, N as u32);
-        vqdmulls_s32(a, b)
-    }
+    let b: i32 = vgetq_lane_s32::<N>(b);
+    vqdmulls_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"]
@@ -17616,10 +17572,8 @@ pub fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        let b: i16 = simd_extract!(b, N as u32);
-        vqdmullh_s16(a, b)
-    }
+    let b: i16 = vgetq_lane_s16::<N>(b);
+    vqdmullh_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"]
@@ -17630,7 +17584,7 @@ pub fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 {
 pub fn vqdmullh_s16(a: i16, b: i16) -> i32 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
-    unsafe { simd_extract!(vqdmull_s16(a, b), 0) }
+    vgetq_lane_s32::<0>(vqdmull_s16(a, b))
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"]
@@ -17641,10 +17595,8 @@ pub fn vqdmullh_s16(a: i16, b: i16) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        let b: i32 = simd_extract!(b, N as u32);
-        vqdmulls_s32(a, b)
-    }
+    let b: i32 = vget_lane_s32::<N>(b);
+    vqdmulls_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"]
@@ -17767,7 +17719,7 @@ pub fn vqmovnd_u64(a: u64) -> u32 {
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovnh_s16(a: i16) -> i8 {
-    unsafe { simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) }
+    vget_lane_s8::<0>(vqmovn_s16(vdupq_n_s16(a)))
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"]
@@ -17776,7 +17728,7 @@ pub fn vqmovnh_s16(a: i16) -> i8 {
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovns_s32(a: i32) -> i16 {
-    unsafe { simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) }
+    vget_lane_s16::<0>(vqmovn_s32(vdupq_n_s32(a)))
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"]
@@ -17785,7 +17737,7 @@ pub fn vqmovns_s32(a: i32) -> i16 {
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovnh_u16(a: u16) -> u8 {
-    unsafe { simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) }
+    vget_lane_u8::<0>(vqmovn_u16(vdupq_n_u16(a)))
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"]
@@ -17794,7 +17746,7 @@ pub fn vqmovnh_u16(a: u16) -> u8 {
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovns_u32(a: u32) -> u16 {
-    unsafe { simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) }
+    vget_lane_u16::<0>(vqmovn_u32(vdupq_n_u32(a)))
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
@@ -17836,7 +17788,7 @@ pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovunh_s16(a: i16) -> u8 {
-    unsafe { simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) }
+    vget_lane_u8::<0>(vqmovun_s16(vdupq_n_s16(a)))
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"]
@@ -17845,7 +17797,7 @@ pub fn vqmovunh_s16(a: i16) -> u8 {
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovuns_s32(a: i32) -> u16 {
-    unsafe { simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) }
+    vget_lane_u16::<0>(vqmovun_s32(vdupq_n_s32(a)))
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"]
@@ -17854,7 +17806,7 @@ pub fn vqmovuns_s32(a: i32) -> u16 {
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovund_s64(a: i64) -> u32 {
-    unsafe { simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) }
+    vget_lane_u32::<0>(vqmovun_s64(vdupq_n_s64(a)))
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"]
@@ -17895,7 +17847,7 @@ pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
 pub fn vqnegb_s8(a: i8) -> i8 {
-    unsafe { simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) }
+    vget_lane_s8::<0>(vqneg_s8(vdup_n_s8(a)))
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"]
@@ -17904,7 +17856,7 @@ pub fn vqnegb_s8(a: i8) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
 pub fn vqnegh_s16(a: i16) -> i16 {
-    unsafe { simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) }
+    vget_lane_s16::<0>(vqneg_s16(vdup_n_s16(a)))
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"]
@@ -17913,7 +17865,7 @@ pub fn vqnegh_s16(a: i16) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
 pub fn vqnegs_s32(a: i32) -> i32 {
-    unsafe { simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) }
+    vget_lane_s32::<0>(vqneg_s32(vdup_n_s32(a)))
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"]
@@ -17922,7 +17874,7 @@ pub fn vqnegs_s32(a: i32) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
 pub fn vqnegd_s64(a: i64) -> i64 {
-    unsafe { simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) }
+    vget_lane_s64::<0>(vqneg_s64(vdup_n_s64(a)))
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"]
@@ -18109,7 +18061,7 @@ pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlahh_s16(a, b, vget_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"]
@@ -18120,7 +18072,7 @@ pub fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlahh_s16(a, b, vgetq_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"]
@@ -18131,7 +18083,7 @@ pub fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlahs_s32(a, b, vget_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"]
@@ -18142,7 +18094,7 @@ pub fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlahs_s32(a, b, vgetq_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"]
@@ -18154,7 +18106,7 @@ pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
     let c: int16x4_t = vdup_n_s16(c);
-    unsafe { simd_extract!(vqrdmlah_s16(a, b, c), 0) }
+    vget_lane_s16::<0>(vqrdmlah_s16(a, b, c))
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"]
@@ -18166,7 +18118,7 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
     let a: int32x2_t = vdup_n_s32(a);
     let b: int32x2_t = vdup_n_s32(b);
     let c: int32x2_t = vdup_n_s32(c);
-    unsafe { simd_extract!(vqrdmlah_s32(a, b, c), 0) }
+    vget_lane_s32::<0>(vqrdmlah_s32(a, b, c))
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"]
@@ -18353,7 +18305,7 @@ pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlshh_s16(a, b, vget_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"]
@@ -18364,7 +18316,7 @@ pub fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlshh_s16(a, b, vgetq_lane_s16::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"]
@@ -18375,7 +18327,7 @@ pub fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlshs_s32(a, b, vget_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"]
@@ -18386,7 +18338,7 @@ pub fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) }
+    vqrdmlshs_s32(a, b, vgetq_lane_s32::<LANE>(c))
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"]
@@ -18398,7 +18350,7 @@ pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
     let c: int16x4_t = vdup_n_s16(c);
-    unsafe { simd_extract!(vqrdmlsh_s16(a, b, c), 0) }
+    vget_lane_s16::<0>(vqrdmlsh_s16(a, b, c))
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"]
@@ -18410,7 +18362,7 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 {
     let a: int32x2_t = vdup_n_s32(a);
     let b: int32x2_t = vdup_n_s32(b);
     let c: int32x2_t = vdup_n_s32(c);
-    unsafe { simd_extract!(vqrdmlsh_s32(a, b, c), 0) }
+    vget_lane_s32::<0>(vqrdmlsh_s32(a, b, c))
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"]
@@ -18421,7 +18373,7 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) }
+    vqrdmulhh_s16(a, vget_lane_s16::<LANE>(b))
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"]
@@ -18432,7 +18384,7 @@ pub fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) }
+    vqrdmulhh_s16(a, vgetq_lane_s16::<LANE>(b))
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"]
@@ -18443,7 +18395,7 @@ pub fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) }
+    vqrdmulhs_s32(a, vget_lane_s32::<LANE>(b))
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"]
@@ -18454,7 +18406,7 @@ pub fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) }
+    vqrdmulhs_s32(a, vgetq_lane_s32::<LANE>(b))
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"]
@@ -18463,7 +18415,7 @@ pub fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 {
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 {
-    unsafe { simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) }
+    vget_lane_s16::<0>(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)))
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"]
@@ -18472,7 +18424,7 @@ pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 {
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 {
-    unsafe { simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) }
+    vget_lane_s32::<0>(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)))
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"]
@@ -18483,7 +18435,7 @@ pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 {
 pub fn vqrshlb_s8(a: i8, b: i8) -> i8 {
     let a: int8x8_t = vdup_n_s8(a);
     let b: int8x8_t = vdup_n_s8(b);
-    unsafe { simd_extract!(vqrshl_s8(a, b), 0) }
+    vget_lane_s8::<0>(vqrshl_s8(a, b))
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"]
@@ -18494,7 +18446,7 @@ pub fn vqrshlb_s8(a: i8, b: i8) -> i8 {
 pub fn vqrshlh_s16(a: i16, b: i16) -> i16 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
-    unsafe { simd_extract!(vqrshl_s16(a, b), 0) }
+    vget_lane_s16::<0>(vqrshl_s16(a, b))
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"]
@@ -18505,7 +18457,7 @@ pub fn vqrshlh_s16(a: i16, b: i16) -> i16 {
 pub fn vqrshlb_u8(a: u8, b: i8) -> u8 {
     let a: uint8x8_t = vdup_n_u8(a);
     let b: int8x8_t = vdup_n_s8(b);
-    unsafe { simd_extract!(vqrshl_u8(a, b), 0) }
+    vget_lane_u8::<0>(vqrshl_u8(a, b))
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"]
@@ -18516,7 +18468,7 @@ pub fn vqrshlb_u8(a: u8, b: i8) -> u8 {
 pub fn vqrshlh_u16(a: u16, b: i16) -> u16 {
     let a: uint16x4_t = vdup_n_u16(a);
     let b: int16x4_t = vdup_n_s16(b);
-    unsafe { simd_extract!(vqrshl_u16(a, b), 0) }
+    vget_lane_u16::<0>(vqrshl_u16(a, b))
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"]
@@ -18670,7 +18622,7 @@ pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x
 pub fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 {
     static_assert!(N >= 1 && N <= 32);
     let a: uint64x2_t = vdupq_n_u64(a);
-    unsafe { simd_extract!(vqrshrn_n_u64::<N>(a), 0) }
+    vget_lane_u32::<0>(vqrshrn_n_u64::<N>(a))
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"]
@@ -18682,7 +18634,7 @@ pub fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 pub fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 {
     static_assert!(N >= 1 && N <= 8);
     let a: uint16x8_t = vdupq_n_u16(a);
-    unsafe { simd_extract!(vqrshrn_n_u16::<N>(a), 0) }
+    vget_lane_u8::<0>(vqrshrn_n_u16::<N>(a))
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"]
@@ -18694,7 +18646,7 @@ pub fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 pub fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 {
     static_assert!(N >= 1 && N <= 16);
     let a: uint32x4_t = vdupq_n_u32(a);
-    unsafe { simd_extract!(vqrshrn_n_u32::<N>(a), 0) }
+    vget_lane_u16::<0>(vqrshrn_n_u32::<N>(a))
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"]
@@ -18706,7 +18658,7 @@ pub fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 {
 pub fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 {
     static_assert!(N >= 1 && N <= 8);
     let a: int16x8_t = vdupq_n_s16(a);
-    unsafe { simd_extract!(vqrshrn_n_s16::<N>(a), 0) }
+    vget_lane_s8::<0>(vqrshrn_n_s16::<N>(a))
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"]
@@ -18718,7 +18670,7 @@ pub fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 pub fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 {
     static_assert!(N >= 1 && N <= 16);
     let a: int32x4_t = vdupq_n_s32(a);
-    unsafe { simd_extract!(vqrshrn_n_s32::<N>(a), 0) }
+    vget_lane_s16::<0>(vqrshrn_n_s32::<N>(a))
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"]
@@ -18730,7 +18682,7 @@ pub fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 {
 pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
     static_assert!(N >= 1 && N <= 32);
     let a: int64x2_t = vdupq_n_s64(a);
-    unsafe { simd_extract!(vqrshrn_n_s64::<N>(a), 0) }
+    vget_lane_s32::<0>(vqrshrn_n_s64::<N>(a))
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
@@ -18781,7 +18733,7 @@ pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x
 pub fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 {
     static_assert!(N >= 1 && N <= 32);
     let a: int64x2_t = vdupq_n_s64(a);
-    unsafe { simd_extract!(vqrshrun_n_s64::<N>(a), 0) }
+    vget_lane_u32::<0>(vqrshrun_n_s64::<N>(a))
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"]
@@ -18793,7 +18745,7 @@ pub fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 {
 pub fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 {
     static_assert!(N >= 1 && N <= 8);
     let a: int16x8_t = vdupq_n_s16(a);
-    unsafe { simd_extract!(vqrshrun_n_s16::<N>(a), 0) }
+    vget_lane_u8::<0>(vqrshrun_n_s16::<N>(a))
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"]
@@ -18805,7 +18757,7 @@ pub fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 pub fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 {
     static_assert!(N >= 1 && N <= 16);
     let a: int32x4_t = vdupq_n_s32(a);
-    unsafe { simd_extract!(vqrshrun_n_s32::<N>(a), 0) }
+    vget_lane_u16::<0>(vqrshrun_n_s32::<N>(a))
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"]
@@ -18816,7 +18768,7 @@ pub fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(vqshl_n_s8::<N>(vdup_n_s8(a)), 0) }
+    vget_lane_s8::<0>(vqshl_n_s8::<N>(vdup_n_s8(a)))
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"]
@@ -18827,7 +18779,7 @@ pub fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshld_n_s64<const N: i32>(a: i64) -> i64 {
     static_assert_uimm_bits!(N, 6);
-    unsafe { simd_extract!(vqshl_n_s64::<N>(vdup_n_s64(a)), 0) }
+    vget_lane_s64::<0>(vqshl_n_s64::<N>(vdup_n_s64(a)))
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"]
@@ -18838,7 +18790,7 @@ pub fn vqshld_n_s64<const N: i32>(a: i64) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(vqshl_n_s16::<N>(vdup_n_s16(a)), 0) }
+    vget_lane_s16::<0>(vqshl_n_s16::<N>(vdup_n_s16(a)))
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"]
@@ -18849,7 +18801,7 @@ pub fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshls_n_s32<const N: i32>(a: i32) -> i32 {
     static_assert_uimm_bits!(N, 5);
-    unsafe { simd_extract!(vqshl_n_s32::<N>(vdup_n_s32(a)), 0) }
+    vget_lane_s32::<0>(vqshl_n_s32::<N>(vdup_n_s32(a)))
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"]
@@ -18860,7 +18812,7 @@ pub fn vqshls_n_s32<const N: i32>(a: i32) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(vqshl_n_u8::<N>(vdup_n_u8(a)), 0) }
+    vget_lane_u8::<0>(vqshl_n_u8::<N>(vdup_n_u8(a)))
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"]
@@ -18871,7 +18823,7 @@ pub fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshld_n_u64<const N: i32>(a: u64) -> u64 {
     static_assert_uimm_bits!(N, 6);
-    unsafe { simd_extract!(vqshl_n_u64::<N>(vdup_n_u64(a)), 0) }
+    vget_lane_u64::<0>(vqshl_n_u64::<N>(vdup_n_u64(a)))
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"]
@@ -18882,7 +18834,7 @@ pub fn vqshld_n_u64<const N: i32>(a: u64) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(vqshl_n_u16::<N>(vdup_n_u16(a)), 0) }
+    vget_lane_u16::<0>(vqshl_n_u16::<N>(vdup_n_u16(a)))
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"]
@@ -18893,7 +18845,7 @@ pub fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshls_n_u32<const N: i32>(a: u32) -> u32 {
     static_assert_uimm_bits!(N, 5);
-    unsafe { simd_extract!(vqshl_n_u32::<N>(vdup_n_u32(a)), 0) }
+    vget_lane_u32::<0>(vqshl_n_u32::<N>(vdup_n_u32(a)))
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"]
@@ -18903,7 +18855,7 @@ pub fn vqshls_n_u32<const N: i32>(a: u32) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlb_s8(a: i8, b: i8) -> i8 {
     let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b));
-    unsafe { simd_extract!(c, 0) }
+    vget_lane_s8::<0>(c)
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"]
@@ -18913,7 +18865,7 @@ pub fn vqshlb_s8(a: i8, b: i8) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlh_s16(a: i16, b: i16) -> i16 {
     let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b));
-    unsafe { simd_extract!(c, 0) }
+    vget_lane_s16::<0>(c)
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"]
@@ -18923,7 +18875,7 @@ pub fn vqshlh_s16(a: i16, b: i16) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshls_s32(a: i32, b: i32) -> i32 {
     let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b));
-    unsafe { simd_extract!(c, 0) }
+    vget_lane_s32::<0>(c)
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"]
@@ -18933,7 +18885,7 @@ pub fn vqshls_s32(a: i32, b: i32) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlb_u8(a: u8, b: i8) -> u8 {
     let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b));
-    unsafe { simd_extract!(c, 0) }
+    vget_lane_u8::<0>(c)
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"]
@@ -18943,7 +18895,7 @@ pub fn vqshlb_u8(a: u8, b: i8) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlh_u16(a: u16, b: i16) -> u16 {
     let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b));
-    unsafe { simd_extract!(c, 0) }
+    vget_lane_u16::<0>(c)
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"]
@@ -18953,7 +18905,7 @@ pub fn vqshlh_u16(a: u16, b: i16) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshls_u32(a: u32, b: i32) -> u32 {
     let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b));
-    unsafe { simd_extract!(c, 0) }
+    vget_lane_u32::<0>(c)
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"]
@@ -18996,7 +18948,7 @@ pub fn vqshld_u64(a: u64, b: i64) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlub_n_s8<const N: i32>(a: i8) -> u8 {
     static_assert_uimm_bits!(N, 3);
-    unsafe { simd_extract!(vqshlu_n_s8::<N>(vdup_n_s8(a)), 0) }
+    vget_lane_u8::<0>(vqshlu_n_s8::<N>(vdup_n_s8(a)))
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"]
@@ -19007,7 +18959,7 @@ pub fn vqshlub_n_s8<const N: i32>(a: i8) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlud_n_s64<const N: i32>(a: i64) -> u64 {
     static_assert_uimm_bits!(N, 6);
-    unsafe { simd_extract!(vqshlu_n_s64::<N>(vdup_n_s64(a)), 0) }
+    vget_lane_u64::<0>(vqshlu_n_s64::<N>(vdup_n_s64(a)))
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"]
@@ -19018,7 +18970,7 @@ pub fn vqshlud_n_s64<const N: i32>(a: i64) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshluh_n_s16<const N: i32>(a: i16) -> u16 {
     static_assert_uimm_bits!(N, 4);
-    unsafe { simd_extract!(vqshlu_n_s16::<N>(vdup_n_s16(a)), 0) }
+    vget_lane_u16::<0>(vqshlu_n_s16::<N>(vdup_n_s16(a)))
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"]
@@ -19029,7 +18981,7 @@ pub fn vqshluh_n_s16<const N: i32>(a: i16) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
     static_assert_uimm_bits!(N, 5);
-    unsafe { simd_extract!(vqshlu_n_s32::<N>(vdup_n_s32(a)), 0) }
+    vget_lane_u32::<0>(vqshlu_n_s32::<N>(vdup_n_s32(a)))
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
@@ -19154,7 +19106,7 @@ pub fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 {
     static_assert!(N >= 1 && N <= 8);
-    unsafe { simd_extract!(vqshrn_n_s16::<N>(vdupq_n_s16(a)), 0) }
+    vget_lane_s8::<0>(vqshrn_n_s16::<N>(vdupq_n_s16(a)))
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"]
@@ -19165,7 +19117,7 @@ pub fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_extract!(vqshrn_n_s32::<N>(vdupq_n_s32(a)), 0) }
+    vget_lane_s16::<0>(vqshrn_n_s32::<N>(vdupq_n_s32(a)))
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"]
@@ -19176,7 +19128,7 @@ pub fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 {
     static_assert!(N >= 1 && N <= 8);
-    unsafe { simd_extract!(vqshrn_n_u16::<N>(vdupq_n_u16(a)), 0) }
+    vget_lane_u8::<0>(vqshrn_n_u16::<N>(vdupq_n_u16(a)))
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"]
@@ -19187,7 +19139,7 @@ pub fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_extract!(vqshrn_n_u32::<N>(vdupq_n_u32(a)), 0) }
+    vget_lane_u16::<0>(vqshrn_n_u32::<N>(vdupq_n_u32(a)))
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
@@ -19237,7 +19189,7 @@ pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_extract!(vqshrun_n_s64::<N>(vdupq_n_s64(a)), 0) }
+    vget_lane_u32::<0>(vqshrun_n_s64::<N>(vdupq_n_s64(a)))
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"]
@@ -19248,7 +19200,7 @@ pub fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 {
     static_assert!(N >= 1 && N <= 8);
-    unsafe { simd_extract!(vqshrun_n_s16::<N>(vdupq_n_s16(a)), 0) }
+    vget_lane_u8::<0>(vqshrun_n_s16::<N>(vdupq_n_s16(a)))
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"]
@@ -19259,7 +19211,7 @@ pub fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_extract!(vqshrun_n_s32::<N>(vdupq_n_s32(a)), 0) }
+    vget_lane_u16::<0>(vqshrun_n_s32::<N>(vdupq_n_s32(a)))
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"]
@@ -19270,7 +19222,7 @@ pub fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 {
 pub fn vqsubb_s8(a: i8, b: i8) -> i8 {
     let a: int8x8_t = vdup_n_s8(a);
     let b: int8x8_t = vdup_n_s8(b);
-    unsafe { simd_extract!(vqsub_s8(a, b), 0) }
+    vget_lane_s8::<0>(vqsub_s8(a, b))
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"]
@@ -19281,7 +19233,7 @@ pub fn vqsubb_s8(a: i8, b: i8) -> i8 {
 pub fn vqsubh_s16(a: i16, b: i16) -> i16 {
     let a: int16x4_t = vdup_n_s16(a);
     let b: int16x4_t = vdup_n_s16(b);
-    unsafe { simd_extract!(vqsub_s16(a, b), 0) }
+    vget_lane_s16::<0>(vqsub_s16(a, b))
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"]
@@ -19292,7 +19244,7 @@ pub fn vqsubh_s16(a: i16, b: i16) -> i16 {
 pub fn vqsubb_u8(a: u8, b: u8) -> u8 {
     let a: uint8x8_t = vdup_n_u8(a);
     let b: uint8x8_t = vdup_n_u8(b);
-    unsafe { simd_extract!(vqsub_u8(a, b), 0) }
+    vget_lane_u8::<0>(vqsub_u8(a, b))
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"]
@@ -19303,7 +19255,7 @@ pub fn vqsubb_u8(a: u8, b: u8) -> u8 {
 pub fn vqsubh_u16(a: u16, b: u16) -> u16 {
     let a: uint16x4_t = vdup_n_u16(a);
     let b: uint16x4_t = vdup_n_u16(b);
-    unsafe { simd_extract!(vqsub_u16(a, b), 0) }
+    vget_lane_u16::<0>(vqsub_u16(a, b))
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"]
@@ -22050,7 +22002,7 @@ pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t {
         )]
         fn _vrnd32x_f64(a: f64) -> f64;
     }
-    unsafe { transmute(_vrnd32x_f64(simd_extract!(a, 0))) }
+    unsafe { transmute(_vrnd32x_f64(vget_lane_f64::<0>(a))) }
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"]
@@ -22114,7 +22066,7 @@ pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t {
         )]
         fn _vrnd32z_f64(a: f64) -> f64;
     }
-    unsafe { transmute(_vrnd32z_f64(simd_extract!(a, 0))) }
+    unsafe { transmute(_vrnd32z_f64(vget_lane_f64::<0>(a))) }
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"]
@@ -22178,7 +22130,7 @@ pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t {
         )]
         fn _vrnd64x_f64(a: f64) -> f64;
     }
-    unsafe { transmute(_vrnd64x_f64(simd_extract!(a, 0))) }
+    unsafe { transmute(_vrnd64x_f64(vget_lane_f64::<0>(a))) }
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"]
@@ -22242,7 +22194,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
         )]
         fn _vrnd64z_f64(a: f64) -> f64;
     }
-    unsafe { transmute(_vrnd64z_f64(simd_extract!(a, 0))) }
+    unsafe { transmute(_vrnd64z_f64(vget_lane_f64::<0>(a))) }
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
@@ -24157,7 +24109,7 @@ pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsqaddb_u8(a: u8, b: i8) -> u8 {
-    unsafe { simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) }
+    vget_lane_u8::<0>(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)))
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"]
@@ -24166,7 +24118,7 @@ pub fn vsqaddb_u8(a: u8, b: i8) -> u8 {
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vsqaddh_u16(a: u16, b: i16) -> u16 {
-    unsafe { simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) }
+    vget_lane_u16::<0>(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)))
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"]
@@ -25845,7 +25797,7 @@ pub unsafe fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 pub unsafe fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
     static_assert!(LANE == 0);
     let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
-    let lane: i64 = simd_extract!(val, LANE as u32);
+    let lane: i64 = vget_lane_s64::<LANE>(val);
     (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
@@ -25861,7 +25813,7 @@ pub unsafe fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 pub unsafe fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
     static_assert_uimm_bits!(LANE, 1);
     let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
-    let lane: i64 = simd_extract!(val, LANE as u32);
+    let lane: i64 = vgetq_lane_s64::<LANE>(val);
     (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
 }
 #[doc = "Subtract"]
@@ -27245,7 +27197,7 @@ pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t {
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vuqaddb_s8(a: i8, b: u8) -> i8 {
-    unsafe { simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) }
+    vget_lane_s8::<0>(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)))
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"]
@@ -27254,7 +27206,7 @@ pub fn vuqaddb_s8(a: i8, b: u8) -> i8 {
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vuqaddh_s16(a: i16, b: u16) -> i16 {
-    unsafe { simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) }
+    vget_lane_s16::<0>(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)))
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index f24a12ad40..1ae7f3f3b0 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -1659,7 +1659,7 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vabsh_f16(a: f16) -> f16 {
-    unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) }
+    vget_lane_f16::<0>(vabs_f16(vdup_n_f16(a)))
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
@@ -10945,7 +10945,7 @@ pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 )]
 pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe { transmute::<i64, _>(simd_extract!(a, N as u32)) }
+    unsafe { transmute(vgetq_lane_s64::<N>(a)) }
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
@@ -10968,7 +10968,7 @@ pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
 )]
 pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
+    unsafe { transmute(vgetq_lane_u64::<N>(a)) }
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
@@ -35281,7 +35281,7 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 )]
 pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
+    vqdmulh_s16(a, vdup_n_s16(vgetq_lane_s16::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
@@ -35304,7 +35304,7 @@ pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4
 )]
 pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
+    vqdmulhq_s16(a, vdupq_n_s16(vgetq_lane_s16::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
@@ -35327,7 +35327,7 @@ pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x
 )]
 pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
+    vqdmulh_s32(a, vdup_n_s32(vgetq_lane_s32::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
@@ -35350,7 +35350,7 @@ pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2
 )]
 pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
+    vqdmulhq_s32(a, vdupq_n_s32(vgetq_lane_s32::<LANE>(b)))
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 6950f69731..75e7e88362 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -182,12 +182,12 @@ intrinsics:
       - ['d_f64', 'f64']
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vabd_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - 0
+          - - 0
 
   - name: "vabd{type[0]}"
     doc: "Floating-point absolute difference"
@@ -203,12 +203,12 @@ intrinsics:
       - ['h_f16', 'f16']
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vabd_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - 0
+          - - 0
 
   - name: "vabdl_high{neon_type[0].noq}"
     doc: Signed Absolute difference Long
@@ -375,12 +375,12 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vceq_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - 0
 
 
   - name: "vceq{type[0]}"
@@ -397,12 +397,12 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vceq_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - 0
 
   - name: "vceqd_{type[0]}"
     doc: "Compare bitwise equal"
@@ -491,12 +491,12 @@ intrinsics:
       - ["h_s16", "i16", "u16", "s16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[3]}'
           - - FnCall:
                 - "vuqadd_{type[3]}"
                 - - FnCall: ["vdup_n_{type[3]}", [a]]
                   - FnCall: ["vdup_n_{type[2]}", [b]]
-            - '0'
+          - - '0'
 
   - name: "vabs{neon_type.no}"
     doc: "Floating-point absolute value"
@@ -567,12 +567,12 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - 'simd_extract!'
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcgt_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - '0'
 
 
   - name: "vcgt{type[0]}"
@@ -589,12 +589,12 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - 'simd_extract!'
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcgt_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - '0'
 
   - name: "vclt{neon_type[0].no}"
     doc: "Compare signed less than"
@@ -651,12 +651,12 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcle_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - '0'
 
 
   - name: "vcle{type[0]}"
@@ -673,12 +673,12 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcle_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - '0'
 
   - name: "vcge{neon_type[0].no}"
     doc: "Compare signed greater than or equal"
@@ -789,11 +789,11 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vclez_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vclez{type[0]}"
     doc: "Floating-point compare less than or equal to zero"
@@ -809,11 +809,11 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vclez_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vcltz{neon_type[0].no}"
     doc: "Compare signed less than zero"
@@ -872,11 +872,11 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcltz_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vcltz{type[0]}"
     doc: "Floating-point compare less than zero"
@@ -892,11 +892,11 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcltz_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vcltzd_s64"
     doc: "Compare less than zero"
@@ -1612,11 +1612,11 @@ intrinsics:
       - ["f64", "f32"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - vcvtx_f32_f64
                 - - FnCall: [vdupq_n_f64, [a]]
-            - '0'
+          - - '0'
 
   - name: "vcvtx_high_f32_f64"
     doc: "Floating-point convert to lower precision narrow, rounding to odd"
@@ -2521,7 +2521,7 @@ intrinsics:
       - [float64x1_t, "f64"]
     compose:
       - FnCall: [static_assert!, ['N == 0']]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
   - name: "vdup_laneq_{neon_type[0]}"
     doc: "Set all vector lanes to the same value"
@@ -2539,8 +2539,8 @@ intrinsics:
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
       - FnCall:
-          - "transmute::<{type[2]}, _>"
-          - - FnCall: [simd_extract!, [a, 'N as u32']]
+          - transmute
+          - - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
   - name: "vdup{type[2]}"
     doc: "Set all vector lanes to the same value"
@@ -2561,7 +2561,7 @@ intrinsics:
       - [float64x2_t, "f64", d_laneq_f64]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
   - name: "vdup{type[2]}"
     doc: "Set all vector lanes to the same value"
@@ -2582,7 +2582,7 @@ intrinsics:
       - [poly16x8_t, "p16", h_laneq_p16]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 3]]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
 
   - name: "vdup{type[2]}"
@@ -2601,7 +2601,7 @@ intrinsics:
       - [float16x4_t, "f16", h_lane_f16]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 2]]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
 
   - name: "vdup{type[2]}"
@@ -2620,7 +2620,7 @@ intrinsics:
       - [float16x8_t, "f16", h_laneq_f16]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 4]]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
 
   - name: "vdup{type[2]}"
@@ -2639,7 +2639,7 @@ intrinsics:
       - [poly8x16_t, "p8", b_laneq_p8]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 4]]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
   - name: "vdup{type[2]}"
     doc: "Set all vector lanes to the same value"
@@ -2660,7 +2660,7 @@ intrinsics:
       - [float32x4_t, "f32", s_laneq_f32]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 2]]
-      - FnCall: [simd_extract!, [a, 'N as u32']]
+      - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
   - name: "vext{neon_type[0].no}"
     doc: "Extract vector from pair of vectors"
@@ -2877,11 +2877,11 @@ intrinsics:
       - [i64, 'd_s64', 's64']
     compose:
       - FnCall:
-          - 'simd_extract!'
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - 'vqneg_{type[2]}'
                 - - FnCall: ['vdup_n_{type[2]}', [a]]
-            - 0
+          - - 0
 
   - name: "vqneg{neon_type[0].no}"
     doc: Signed saturating negate
@@ -2958,12 +2958,12 @@ intrinsics:
               - "vdup_n_{type[2]}"
               - - b
       - FnCall:
-          - 'simd_extract!'
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqsub_{type[2]}"
                 - - a
                   - b
-            - "0"
+          - - "0"
 
   - name: "vqsub{type[3]}"
     doc: Saturating subtract
@@ -2989,12 +2989,12 @@ intrinsics:
               - "vdup_n_{type[2]}"
               - - b
       - FnCall:
-          - 'simd_extract!'
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqsub_{type[2]}"
                 - - a
                   - b
-            - "0"
+          - - "0"
 
   - name: "vrbit{neon_type.no}"
     doc: Reverse bit order
@@ -3443,12 +3443,12 @@ intrinsics:
               - "vdup_n_{type[0]}"
               - - b
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[0]}'
           - - FnCall:
                 - "vqadd_{type[0]}"
                 - - a
                   - b
-            - "0"
+          - - "0"
 
   - name: "vqadd{type[2]}"
     doc: Saturating add
@@ -3474,12 +3474,12 @@ intrinsics:
               - "vdup_n_{type[0]}"
               - - b
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[0]}'
           - - FnCall:
                 - "vqadd_{type[0]}"
                 - - a
                   - b
-            - "0"
+          - - "0"
 
   - name: "vld1{neon_type[1].no}"
     doc: "Load multiple single-element structures to one, two, three, or four registers"
@@ -4484,7 +4484,7 @@ intrinsics:
       - Let:
         - "lane"
         - i64
-        - FnCall: [simd_extract!, [val, 'LANE as u32']]
+        - FnCall: ['vget{neon_type[1].lane_nox}', [val], [LANE]]
       - MethodCall:
         - "(*atomic_dst)"
         - store
@@ -5254,8 +5254,8 @@ intrinsics:
     compose:
       - FnCall:
           - "vmull_{neon_type[0]}"
-          - - FnCall: [simd_extract!, [a, '1']]
-            - FnCall: [simd_extract!, [b, '1']]
+          - - FnCall: ['vget{neon_type[0].lane_nox}', [a], [1]]
+            - FnCall: ['vget{neon_type[0].lane_nox}', [b], [1]]
 
   - name: "vmulx{neon_type.no}"
     doc: Floating-point multiply extended
@@ -5354,11 +5354,8 @@ intrinsics:
           - vmulx_f64
           - - a
             - FnCall:
-                - 'transmute::<f64, _>'
-                - - FnCall:
-                      - "simd_extract!"
-                      - - b
-                        - 'LANE as u32'
+                - 'transmute'
+                - - FnCall: ['vget{neon_type.lane_nox}', [b], [LANE]]
 
   - name: "vmulx{type[0]}"
     doc: Floating-point multiply extended
@@ -5394,16 +5391,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ["d_lane_f64", "f64", float64x1_t, "d_f64", 'LANE as u32']
+      - ["d_lane_f64", "f64", float64x1_t, "d_f64"]
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
       - FnCall:
           - "vmulx{type[3]}"
           - - a
-            - FnCall:
-                - "simd_extract!"
-                - - b
-                  - "{type[4]}"
+            - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]]
 
   - name: "vmulx_laneq_f64"
     doc: Floating-point multiply extended
@@ -5423,11 +5417,8 @@ intrinsics:
           - vmulx_f64
           - - a
             - FnCall:
-                - 'transmute::<f64, _>'
-                - - FnCall:
-                      - "simd_extract!"
-                      - - b
-                        - 'LANE as u32'
+                - 'transmute'
+                - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]
 
   - name: "vmulx{type[0]}"
     doc: Floating-point multiply extended
@@ -5497,18 +5488,15 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['s_lane_f32', f32, float32x2_t, '1', 's_f32', 'LANE as u32']
-      - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32', 'LANE as u32']
-      - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64', 'LANE as u32']
+      - ['s_lane_f32', f32, float32x2_t, '1', 's_f32']
+      - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32']
+      - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64']
     compose:
       - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]]
       - FnCall:
           - "vmulx{type[4]}"
           - - a
-            - FnCall:
-                - "simd_extract!"
-                - - b
-                  - "{type[5]}"
+            - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]]
 
 
   - name: "vmulx{type[0]}"
@@ -5531,10 +5519,7 @@ intrinsics:
       - FnCall:
           - "vmulx{type[4]}"
           - - a
-            - FnCall:
-                - "simd_extract!"
-                - - b
-                  - "{type[5]}"
+            - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]]
 
 
   - name: "vmulx{neon_type[0].N}"
@@ -7084,11 +7069,11 @@ intrinsics:
       - Let:
           - a1
           - "{type[2]}"
-          - FnCall: [simd_extract!, [a, '0']]
+          - FnCall: ['vget{neon_type[1].lane_nox}', [a], [0]]
       - Let:
           - a2
           - "{type[2]}"
-          - FnCall: [simd_extract!, [a, '1']]
+          - FnCall: ['vget{neon_type[1].lane_nox}', [a], [1]]
       - Identifier: ['a1 + a2', Symbol]
 
   - name: "vpmin{type[0]}"
@@ -7121,7 +7106,7 @@ intrinsics:
     compose:
       - Let: [a, int16x4_t, {FnCall: [vdup_n_s16, [a]]}]
       - Let: [b, int16x4_t, {FnCall: [vdup_n_s16, [b]]}]
-      - FnCall: [simd_extract!, [{FnCall: [vqdmull_s16, [a, b]]}, '0']]
+      - FnCall: ['vgetq_lane_{type[1]}', [{FnCall: [vqdmull_s16, [a, b]]}], ['0']]
 
   - name: "vqdmulls_s32"
     doc: "Signed saturating doubling multiply long"
@@ -7187,7 +7172,7 @@ intrinsics:
       - ["i32", int32x4_t, "i64", 's_laneq_s32', 's_s32']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 2]]
-      - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}]
+      - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}]
       - FnCall: ["vqdmull{type[4]}", [a, b]]
 
   - name: "vqdmullh_laneq_s16"
@@ -7204,7 +7189,7 @@ intrinsics:
       - ["i16", int16x8_t, "i32"]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 3]]
-      - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}]
+      - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}]
       - FnCall: ["vqdmullh_s16", [a, b]]
 
   - name: "vqdmulls_lane_s32"
@@ -7221,7 +7206,7 @@ intrinsics:
       - ["i32", int32x2_t, "i64"]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
-      - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}]
+      - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}]
       - FnCall: ["vqdmulls_s32", [a, b]]
 
   - name: "vqdmull{type[6]}"
@@ -7360,7 +7345,7 @@ intrinsics:
       - ["i32", "i16", "s16"]
     compose:
       - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}]
-      - FnCall: [vqadds_s32, [a, {FnCall: [simd_extract!, [x, 0]]}]]
+      - FnCall: [vqadds_s32, [a, {FnCall: ['vgetq_lane_s32', [x], [0]]}]]
 
   - name: "vqdmlals_s32"
     doc: "Signed saturating doubling multiply-add long"
@@ -7393,7 +7378,7 @@ intrinsics:
       - ["i64", "i32", int32x4_t, "i64", s_laneq_s32, '2', s_s32]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]]
-      - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+      - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: ['vget{neon_type[2].lane_nox}', [c], [LANE]]}]]
 
   - name: "vqdmlal_laneq_s16"
     doc: "Vector widening saturating doubling multiply accumulate with scalar"
@@ -7474,7 +7459,7 @@ intrinsics:
       - ["i32", "i16"]
     compose:
       - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}]
-      - FnCall: [vqsubs_s32, [a, {FnCall: [simd_extract!, [x, '0']]}]]
+      - FnCall: [vqsubs_s32, [a, {FnCall: ['vgetq_lane_s32', [x], [0]]}]]
 
   - name: "vqdmlsls_s32"
     doc: "Signed saturating doubling multiply-subtract long"
@@ -7507,7 +7492,7 @@ intrinsics:
       - ["i64", "i32", int32x4_t, "i64", 's_laneq_s32', '2', 's_s32']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]]
-      - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+      - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: ['vget{neon_type[2].lane_nox}', [c], [LANE]]}]]
 
   - name: "vqdmlsl_laneq_s16"
     doc: "Vector widening saturating doubling multiply subtract with scalar"
@@ -7555,7 +7540,7 @@ intrinsics:
     compose:
       - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [a]]}]
       - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [b]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}, '0']]
+      - FnCall: ['vget{neon_type[3].lane_nox}', [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}], ['0']]
 
   - name: "vqdmulhh{type[3]}"
     doc: "Signed saturating doubling multiply returning high half"
@@ -7572,7 +7557,7 @@ intrinsics:
       - ["i16", int16x8_t, "i16", '_laneq_s16', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]]
-      - Let: [b, 'i16', {FnCall: [simd_extract!, [b, 'N as u32']]}]
+      - Let: [b, 'i16', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}]
       - FnCall: ['vqdmulhh_s16', [a, b]]
 
   - name: "vqdmulhs{type[3]}"
@@ -7590,7 +7575,7 @@ intrinsics:
       - ["i32", int32x4_t, "i32", "_laneq_s32", '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]]
-      - Let: [b, 'i32', {FnCall: [simd_extract!, [b, 'N as u32']]}]
+      - Let: [b, 'i32', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}]
       - FnCall: ['vqdmulhs_s32', [a, b]]
 
   - name: "vqmovn_high{neon_type[1].noq}"
@@ -7635,7 +7620,7 @@ intrinsics:
       - ["i16", "i8", 'h_s16', s16]
       - ["i32", "i16", 's_s32', s32]
     compose:
-      - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']]
+      - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']]
 
   - name: "vqmovn{type[2]}"
     doc: "Saturating extract narrow"
@@ -7649,7 +7634,7 @@ intrinsics:
       - ["u16", "u8", 'h_u16', 'u16']
       - ["u32", "u16", 's_u32', 'u32']
     compose:
-      - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']]
+      - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']]
 
   - name: "vqmovnd_s64"
     doc: "Saturating extract narrow"
@@ -7698,7 +7683,7 @@ intrinsics:
       - ["i32", "u16", 's_s32', s32]
       - ["i64", "u32", 'd_s64', s64]
     compose:
-      - FnCall: [simd_extract!, [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']]
+      - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']]
 
   - name: "vqmovun_high_{neon_type[1]}"
     doc: "Signed saturating extract unsigned narrow"
@@ -7727,7 +7712,7 @@ intrinsics:
       - ["i16", 'h_s16', 's16']
       - ["i32", 's_s32', 's32']
     compose:
-      - FnCall: [simd_extract!, [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}, '0']]
+      - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}], ['0']]
 
   - name: "vqrdmulh{type[2]}"
     doc: "Signed saturating rounding doubling multiply returning high half"
@@ -7746,7 +7731,7 @@ intrinsics:
       - ["i32", int32x4_t, 's_laneq_s32', 's_s32', '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]]
-      - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: [simd_extract!, [b, 'LANE as u32']]}]]
+      - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}]]
 
   - name: "vqrdmlah{neon_type.no}"
     doc: "Signed saturating rounding doubling multiply accumulate returning high half"
@@ -7785,7 +7770,7 @@ intrinsics:
       - Let: [a, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [a]]}]
       - Let: [b, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [b]]}]
       - Let: [c, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [c]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}, '0']]
+      - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}], ['0']]
 
   - name: "vqrdmlah{type[0]}"
     doc: "Signed saturating rounding doubling multiply accumulate returning high half"
@@ -7830,7 +7815,7 @@ intrinsics:
       - ["i32", int32x4_t, '2', "s_s32", s_laneq_s32, s_s32]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]]
-      - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+      - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
   - name: "vqrdmlsh{neon_type.no}"
     doc: "Signed saturating rounding doubling multiply subtract returning high half"
@@ -7869,7 +7854,7 @@ intrinsics:
       - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}]
       - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}]
       - Let: [c, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [c]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}, '0']]
+      - FnCall: ['vget{neon_type[2].lane_nox}', [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}], ['0']]
 
   - name: "vqrdmlsh{type[0]}"
     doc: "Signed saturating rounding doubling multiply subtract returning high half"
@@ -7914,7 +7899,7 @@ intrinsics:
       - ["i32", int32x4_t, '2', s_laneq_s32, s_s32]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]]
-      - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+      - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
   - name: "vqrshl{type[0]}"
     doc: "Signed saturating rounding shift left"
@@ -7948,7 +7933,7 @@ intrinsics:
     compose:
       - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}]
       - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[3]}", [a, b]]}, '0']]
+      - FnCall: ['vget{neon_type[2].lane_nox}', [{FnCall: ["vqrshl_{type[3]}", [a, b]]}], ['0']]
 
   - name: "vqrshl{type[2]}"
     doc: "Unsigned signed saturating rounding shift left"
@@ -7982,7 +7967,7 @@ intrinsics:
     compose:
       - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n_{type[0]}", [a]]}]
       - Let: [b, "{neon_type[4]}", {FnCall: ["vdup_n_{type[5]}", [b]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[0]}", [a, b]]}, '0']]
+      - FnCall: ['vget{neon_type[3].lane_nox}', [{FnCall: ["vqrshl_{type[0]}", [a, b]]}], ['0']]
 
   - name: "vqrshrn{type[2]}"
     doc: "Signed saturating rounded shift right narrow"
@@ -8001,7 +7986,7 @@ intrinsics:
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqrshrn_n{neon_type[4].noq}::<N>", [a]]}, '0']]
+      - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqrshrn_n{neon_type[4].noq}::<N>", [a]]}], ['0']]
 
   - name: "vqrshrn{type[3]}"
     doc: "Signed saturating rounded shift right narrow"
@@ -8038,7 +8023,7 @@ intrinsics:
     compose:
       - FnCall: [static_assert!, ['{type[3]}']]
       - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}]
-      - FnCall: [simd_extract!, [{FnCall: ["vqrshrn{type[6]}::<N>", [a]]}, '0']]
+      - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrshrn{type[6]}::<N>", [a]]}], ['0']]
 
   - name: "vqrshrn_high_n{neon_type[1].noq}"
     doc: "Unsigned saturating rounded shift right narrow"
@@ -8085,11 +8070,11 @@ intrinsics:
           - "{neon_type[4]}"
           - FnCall: ["vdupq_n_{type[5]}", [a]]
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqrshrun_n_{type[5]}::<N>"
                 - - a
-            - '0'
+          - - '0'
 
   - name: "vqrshrun_high_n{neon_type[1].noq}"
     doc: "Signed saturating rounded shift right unsigned narrow"
@@ -8152,7 +8137,7 @@ intrinsics:
               - "vqshl{neon_type[2].noq}"
               - - FnCall: ["vdup_n{neon_type[2].no}", [a]]
                 - FnCall: ["vdup_n{neon_type[2].no}", [b]]
-      - FnCall: [simd_extract!, [c, '0']]
+      - FnCall: ['vget{neon_type[2].lane_nox}', [c], ['0']]
 
   - name: "vqshl{type[0]}"
     doc: "Signed saturating shift left"
@@ -8172,11 +8157,11 @@ intrinsics:
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]]
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vqshl_n_{type[3]}::<N>"
                 - - FnCall: ["vdup_n_{type[3]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vqshld_{type[0]}"
     doc: "Unsigned saturating shift left"
@@ -8215,7 +8200,7 @@ intrinsics:
               - "vqshl{neon_type[3].noq}"
               - - FnCall: ["vdup{neon_type[3].N}", [a]]
                 - FnCall: ["vdup{neon_type[4].N}", [b]]
-      - FnCall: [simd_extract!, [c, '0']]
+      - FnCall: ['vget{neon_type[3].lane_nox}', [c], ['0']]
 
   - name: "vqshl{type[0]}"
     doc: "Unsigned saturating shift left"
@@ -8235,9 +8220,9 @@ intrinsics:
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]]
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall: ["vqshl_n_{type[1]}::<N>", [{FnCall: ["vdup_n_{type[1]}", [a]]}]]
-            - '0'
+          - - '0'
 
   - name: "vqshrnd_n_s64"
     doc: "Signed saturating shift right narrow"
@@ -8279,11 +8264,11 @@ intrinsics:
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqshrn_n_{type[4]}::<N>"
                 - - FnCall: ["vdupq_n_{type[4]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vqshrn{type[0]}"
     doc: "Signed saturating shift right narrow"
@@ -8347,11 +8332,11 @@ intrinsics:
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - "simd_extract!"
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqshrn_n_{type[1]}::<N>"
                 - - FnCall: ["vdupq_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vqshrn{type[0]}"
     doc: "Unsigned saturating shift right narrow"
@@ -8392,11 +8377,11 @@ intrinsics:
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqshrun_n_{type[4]}::<N>"
                 - - FnCall: ["vdupq_n_{type[4]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vqshrun_high_n_{neon_type[1]}"
     doc: "Signed saturating shift right unsigned narrow"
@@ -8433,12 +8418,12 @@ intrinsics:
       - [h_u16, "u16", "i16", s16]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vsqadd_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[2]}", [b]]
-            - '0'
+          - - '0'
 
   - name: "vsqadd{type[0]}"
     doc: "Unsigned saturating accumulate of signed value"
@@ -9026,14 +9011,14 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [float64x2_t, float64x1_t, '0', '1', 'transmute::<f64, _>(simd_extract!(b, LANE2 as u32))']
-      - [poly64x2_t, poly64x1_t, '0', '1', 'transmute::<u64, _>(simd_extract!(b, LANE2 as u32))']
-      - [uint64x2_t, uint64x1_t, '0', '1', 'transmute::<u64, _>(simd_extract!(b, LANE2 as u32))']
-      - [int64x2_t, int64x1_t, '0', '1', 'transmute::<i64, _>(simd_extract!(b, LANE2 as u32))']
+      - [float64x2_t, float64x1_t, '0', '1']
+      - [poly64x2_t, poly64x1_t, '0', '1']
+      - [uint64x2_t, uint64x1_t, '0', '1']
+      - [int64x2_t, int64x1_t, '0', '1']
     compose:
       - FnCall: [static_assert!, ['LANE1 == {type[2]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[3]}']]
-      - Identifier: ["{type[4]}", UnsafeSymbol]
+      - FnCall: [transmute, [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}]]
 
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
@@ -9566,7 +9551,7 @@ intrinsics:
           - transmute
           - - FnCall:
                 - _vrnd32x_f64
-                - - FnCall: [simd_extract!, [a, 0]]
+                - - FnCall: ['vget{neon_type.lane_nox}', [a], [0]]
 
   - name: "vrnd32z{neon_type.no}"
     doc: "Floating-point round to 32-bit integer toward zero"
@@ -9610,7 +9595,7 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall:
           - transmute
-          - - FnCall: [_vrnd32z_f64, [{FnCall: [simd_extract!, [a, 0]]}]]
+          - - FnCall: [_vrnd32z_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]]
 
   - name: "vrnd64x{neon_type.no}"
     doc: "Floating-point round to 64-bit integer, using current rounding mode"
@@ -9654,7 +9639,7 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall:
           - transmute
-          - - FnCall: [_vrnd64x_f64, [{FnCall: [simd_extract!, [a, 0]]}]]
+          - - FnCall: [_vrnd64x_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]]
 
   - name: "vrnd64z{neon_type.no}"
     doc: "Floating-point round to 64-bit integer toward zero"
@@ -9698,7 +9683,7 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall:
           - transmute
-          - - FnCall: [_vrnd64z_f64, [{FnCall: [simd_extract!, [a, 0]]}]]
+          - - FnCall: [_vrnd64z_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]]
 
   - name: "vtrn1{neon_type[0].no}"
     doc: Transpose vectors
@@ -10323,7 +10308,7 @@ intrinsics:
           - "vfma{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
 
   - name: "vfma{type[3]}"
@@ -10349,7 +10334,7 @@ intrinsics:
           - "vfma{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
 
   # vfms lane f16
@@ -10376,7 +10361,7 @@ intrinsics:
           - "vfms{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
 
   - name: "vfms{type[1]}"
@@ -10413,7 +10398,7 @@ intrinsics:
           - "vfma{neon_type.no}"
           - - a
             - b
-            - FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+            - FnCall: ["vdup{neon_type.N}", [{FnCall: ['vget{neon_type.lane_nox}', [c], [LANE]]}]]
 
   - name: "vfma_laneq_f64"
     doc: "Floating-point fused multiply-add to accumulator"
@@ -10433,7 +10418,7 @@ intrinsics:
           - "vfma{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
   - name: "vfmaq_lane_f64"
     doc: "Floating-point fused multiply-add to accumulator"
@@ -10453,7 +10438,7 @@ intrinsics:
           - "vfma{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]
+            - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]
 
   - name: "vfma{type[2]}"
     doc: "Floating-point fused multiply-add to accumulator"
@@ -10471,7 +10456,7 @@ intrinsics:
       - ["f64", float64x2_t, "d_laneq_f64", '1']
     compose:
       - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]]
-      - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}]
+      - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]
       - FnCall: ["fma{type[0]}", [b, c, a]]
 
   - name: "vfmad_lane_f64"
@@ -10488,7 +10473,7 @@ intrinsics:
       - ["f64", float64x1_t]
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}]
+      - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]
       - FnCall: [fmaf64, [b, c, a]]
 
 
@@ -10525,7 +10510,7 @@ intrinsics:
       - ["f16", float16x8_t, 'q_f16', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
-      - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [v, 'LANE as u32']]}]
+      - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [v], [LANE]]}]
       - FnCall: ["vfmah_{type[0]}", [a, b, c]]
 
   - name: "vfmsh_lane{type[2]}"
@@ -10545,7 +10530,7 @@ intrinsics:
       - ["f16", float16x8_t, 'q_f16', '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
-      - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [v, 'LANE as u32']]}]
+      - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [v], [LANE]]}]
       - FnCall: ["vfmsh_{type[0]}", [a, b, c]]
 
   - name: "vfms_f64"
@@ -10608,7 +10593,7 @@ intrinsics:
       - [float64x2_t, float64x2_t, '1', q_laneq_f64]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[2]}']]
-      - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]]
+      - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]]
 
   - name: "vfms_lane_f64"
     doc: "Floating-point fused multiply-subtract to accumulator"
@@ -10624,7 +10609,7 @@ intrinsics:
       - float64x1_t
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]]
+      - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: ['vget{neon_type.lane_nox}', [c], [LANE]]}]]}]]
 
   - name: "vfms_laneq_f64"
     doc: "Floating-point fused multiply-subtract to accumulator"
@@ -10640,7 +10625,7 @@ intrinsics:
       - [float64x1_t, float64x2_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
-      - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]]
+      - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]]
 
   - name: "vfmsq_lane_f64"
     doc: "Floating-point fused multiply-subtract to accumulator"
@@ -10656,7 +10641,7 @@ intrinsics:
       - [float64x2_t, float64x1_t]
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]]
+      - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]]
 
   - name: "vfms{type[2]}"
     doc: "Floating-point fused multiply-subtract to accumulator"
@@ -10724,11 +10709,11 @@ intrinsics:
       - ["f64", "u64", "d_f64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vceqz_{type[0]}"
                 - - FnCall: ["vdup_n_{type[0]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vceqz{type[2]}"
     doc: "Floating-point compare bitwise equal to zero"
@@ -10744,11 +10729,11 @@ intrinsics:
       - ["f16", "u16", "h_f16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vceqz_{type[0]}"
                 - - FnCall: ["vdup_n_{type[0]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vceqzd_{type[2]}"
     doc: "Compare bitwise equal to zero"
@@ -10847,12 +10832,12 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcge_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - '0'
 
 
   - name: "vcge{type[0]}"
@@ -10869,12 +10854,12 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcge_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
                   - FnCall: ["vdup_n_{type[1]}", [b]]
-            - '0'
+          - - '0'
 
   - name: "vcge{neon_type[0].no}"
     doc: "Floating-point compare greater than or equal"
@@ -10991,11 +10976,11 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcgez_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
 
   - name: "vcgez{type[0]}"
@@ -11012,11 +10997,11 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcgez_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vclezd_s64"
     doc: "Compare less than or equal to zero"
@@ -11123,11 +11108,11 @@ intrinsics:
       - ["d_f64", "f64", "u64"]
     compose:
       - FnCall:
-          - "simd_extract!"
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcgtz_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vcgtz{type[0]}"
     doc: "Floating-point compare greater than zero"
@@ -11143,11 +11128,11 @@ intrinsics:
       - ["h_f16", "f16", "u16"]
     compose:
       - FnCall:
-          - "simd_extract!"
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vcgtz_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vcvt{neon_type[1].no}_{neon_type[0]}"
     doc: "Floating-point convert to unsigned fixed-point, rounding toward zero"
@@ -11203,7 +11188,7 @@ intrinsics:
           - - a
             - FnCall:
                 - "transmute::<f64, _>"
-                - - FnCall: [simd_extract!, [b, 'LANE as u32']]
+                - - FnCall: ['vget{neon_type.lane_nox}', [b], [LANE]]
 
   - name: "vmulq_lane_f64"
     doc: "Floating-point multiply"
@@ -11238,7 +11223,7 @@ intrinsics:
       - ["f64", float64x1_t]
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}]
+      - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}]
       - Identifier: ['a * b', Symbol]
 
   - name: "vmul_laneq_f64"
@@ -11260,7 +11245,7 @@ intrinsics:
           - - a
             - FnCall:
                 - "transmute::<f64, _>"
-                - - FnCall: [simd_extract!, [b, 'LANE as u32']]
+                - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]
 
   - name: "vmulq_laneq_f64"
     doc: "Floating-point multiply"
@@ -11338,7 +11323,7 @@ intrinsics:
       - ["f64", float64x2_t, "d_laneq_f64", '1']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
-      - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}]
+      - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}]
       - Identifier: ['a * b', Symbol]
 
 
@@ -11359,7 +11344,7 @@ intrinsics:
       - ["f16", float16x8_t, "h_laneq_f16", '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
-      - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}]
+      - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}]
       - Identifier: ['a * b', Symbol]
 
 
@@ -11481,12 +11466,12 @@ intrinsics:
       - ["f64", "u64", 'd_f64']
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vclt_{type[0]}"
                 - - FnCall: ["vdup_n_{type[0]}", [a]]
                   - FnCall: ["vdup_n_{type[0]}", [b]]
-            - '0'
+          - - '0'
 
 
   - name: "vclt{type[2]}"
@@ -11503,12 +11488,12 @@ intrinsics:
       - ["f16", "u16", 'h_f16']
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vclt_{type[0]}"
                 - - FnCall: ["vdup_n_{type[0]}", [a]]
                   - FnCall: ["vdup_n_{type[0]}", [b]]
-            - '0'
+          - - '0'
 
   - name: "vabdl_high{neon_type[0].noq}"
     doc: Unsigned Absolute difference Long
@@ -11748,7 +11733,7 @@ intrinsics:
           - - a
             - FnCall:
                 - "vdup{neon_type[0].N}"
-                - - FnCall: [simd_extract!, [b, 'LANE as u32']]
+                - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]
 
   - name: "vqabs{type[2]}"
     doc: "Signed saturating absolute value"
@@ -11763,9 +11748,9 @@ intrinsics:
       - ["i16", "s16", 'h_s16']
     compose:
       - FnCall:
-          - "simd_extract!"
+          - 'vget_lane_{type[0]}'
           - - FnCall: ["vqabs_{type[1]}", [{FnCall: ["vdup_n_{type[1]}", [a]]}]]
-            - '0'
+          - - '0'
 
   - name: "vqabs{type[1]}"
     doc: "Signed saturating absolute value"
@@ -11957,11 +11942,11 @@ intrinsics:
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]]
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[2]}'
           - - FnCall:
                 - "vqshlu_n_{type[4]}::<N>"
                 - - FnCall: ["vdup_n_{type[4]}", [a]]
-            - '0'
+          - - '0'
 
   - name: "vcvta{neon_type[1].no}_{neon_type[0]}"
     doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to away"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 68c92aa54d..08a80c3719 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -506,11 +506,11 @@ intrinsics:
       - ['h_f16', 'f16']
     compose:
       - FnCall:
-          - simd_extract!
+          - 'vget_lane_{type[1]}'
           - - FnCall:
                 - "vabs_{type[1]}"
                 - - FnCall: ["vdup_n_{type[1]}", [a]]
-            - 0
+          - - 0
 
   - name: "vcgt{neon_type[0].no}"
     doc: "Compare signed greater than"
@@ -1716,8 +1716,8 @@ intrinsics:
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
       - FnCall:
-          - "transmute{type[3]}"
-          - - FnCall: [simd_extract!, [a, 'N as u32']]
+          - "transmute"
+          - - FnCall: ['vget{neon_type[1].lane_nox}', [a], [N]]
 
   - name: "vext{neon_type[0].no}"
     doc: "Extract vector from pair of vectors"
@@ -11461,7 +11461,7 @@ intrinsics:
           - - a
             - FnCall:
                 - "vdup{neon_type[0].N}"
-                - - FnCall: [simd_extract!, [b, 'LANE as u32']]
+                - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]
 
   - name: "vrecpe{neon_type.no}"
     doc: "Unsigned reciprocal estimate"

From 494f6d4e963ec27af266dfa79420a023707e95bc Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 10:00:45 +0100
Subject: [PATCH 294/326] gen-arm: use LLVM intrinsics for `f16` to `{i,u}16`

Instead of doing an `as {i,u}16` cast, we can use the same LLVM
intrinsics as when converting to `{i,u}{32,64}`, which is what Clang does
and ensures the intrinsic result matches.
---
 .../core_arch/src/aarch64/neon/generated.rs   |  74 ++++++++--
 .../spec/neon/aarch64.spec.yml                | 132 ++----------------
 2 files changed, 73 insertions(+), 133 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 5a0bbfa095..f705954194 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -8007,7 +8007,14 @@ pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtah_s16_f16(a: f16) -> i16 {
-    vcvtah_s32_f16(a) as i16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtas.i16.f16"
+        )]
+        fn _vcvtah_s16_f16(a: f16) -> i16;
+    }
+    unsafe { _vcvtah_s16_f16(a) }
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"]
@@ -8051,7 +8058,14 @@ pub fn vcvtah_s64_f16(a: f16) -> i64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtah_u16_f16(a: f16) -> u16 {
-    vcvtah_u32_f16(a) as u16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtau.i16.f16"
+        )]
+        fn _vcvtah_u16_f16(a: f16) -> u16;
+    }
+    unsafe { _vcvtah_u16_f16(a) }
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"]
@@ -8693,7 +8707,14 @@ pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtmh_s16_f16(a: f16) -> i16 {
-    vcvtmh_s32_f16(a) as i16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtms.i16.f16"
+        )]
+        fn _vcvtmh_s16_f16(a: f16) -> i16;
+    }
+    unsafe { _vcvtmh_s16_f16(a) }
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"]
@@ -8729,7 +8750,7 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 {
     }
     unsafe { _vcvtmh_s64_f16(a) }
 }
-#[doc = "Floating-point convert to integer, rounding towards minus infinity"]
+#[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"]
 #[inline]
 #[cfg_attr(test, assert_instr(fcvtmu))]
@@ -8737,7 +8758,14 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtmh_u16_f16(a: f16) -> u16 {
-    vcvtmh_u32_f16(a) as u16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtmu.i16.f16"
+        )]
+        fn _vcvtmh_u16_f16(a: f16) -> u16;
+    }
+    unsafe { _vcvtmh_u16_f16(a) }
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"]
@@ -9041,7 +9069,14 @@ pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtnh_s16_f16(a: f16) -> i16 {
-    vcvtnh_s32_f16(a) as i16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtns.i16.f16"
+        )]
+        fn _vcvtnh_s16_f16(a: f16) -> i16;
+    }
+    unsafe { _vcvtnh_s16_f16(a) }
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"]
@@ -9085,7 +9120,14 @@ pub fn vcvtnh_s64_f16(a: f16) -> i64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtnh_u16_f16(a: f16) -> u16 {
-    vcvtnh_u32_f16(a) as u16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtnu.i16.f16"
+        )]
+        fn _vcvtnh_u16_f16(a: f16) -> u16;
+    }
+    unsafe { _vcvtnh_u16_f16(a) }
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"]
@@ -9389,7 +9431,14 @@ pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtph_s16_f16(a: f16) -> i16 {
-    vcvtph_s32_f16(a) as i16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtps.i16.f16"
+        )]
+        fn _vcvtph_s16_f16(a: f16) -> i16;
+    }
+    unsafe { _vcvtph_s16_f16(a) }
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"]
@@ -9433,7 +9482,14 @@ pub fn vcvtph_s64_f16(a: f16) -> i64 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vcvtph_u16_f16(a: f16) -> u16 {
-    vcvtph_u32_f16(a) as u16
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fcvtpu.i16.f16"
+        )]
+        fn _vcvtph_u16_f16(a: f16) -> u16;
+    }
+    unsafe { _vcvtph_u16_f16(a) }
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 6950f69731..342e66cab4 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -1869,9 +1869,9 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "u16", 'h_u16_f16']
       - ["f16", "u32", 'h_u32_f16']
       - ["f16", "u64", 'h_u64_f16']
-
     compose:
       - LLVMLink:
           name: "vcvta{type[2]}"
@@ -1891,6 +1891,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "i16", 'h_s16_f16']
       - ["f16", "i32", 'h_s32_f16']
       - ["f16", "i64", 'h_s64_f16']
     compose:
@@ -1901,37 +1902,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtas.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-
-  - name: "vcvta{type[2]}"
-    doc: "Floating-point convert to integer, rounding to nearest with ties to away"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "i16", 'h_s16_f16', 's32']
-    compose:
-      - 'vcvtah_{type[3]}_f16(a) as i16'
-
-  - name: "vcvta{type[2]}"
-    doc: "Floating-point convert to integer, rounding to nearest with ties to away"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "u16", 'h_u16_f16', 'u32']
-    compose:
-      - 'vcvtah_{type[3]}_f16(a) as u16'
-
   - name: "vcvta{type[2]}"
     doc: "Floating-point convert to integer, rounding to nearest with ties to away"
     arguments: ["a: {type[0]}"]
@@ -2041,6 +2011,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "i16", 'h']
       - ["f16", "i32", 'h']
       - ["f16", "i64", 'h']
     compose:
@@ -2051,22 +2022,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtns.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-  - name: "vcvtn{type[2]}_{type[1]}_{type[0]}"
-    doc: "Floating-point convert to integer, rounding to nearest with ties to even"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "i16", 'h', 'i32']
-    compose:
-      - 'vcvtnh_{type[3]}_f16(a) as i16'
-
-
   - name: "vcvtn{type[2]}_{type[1]}_{type[0]}"
     doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even"
     arguments: ["a: {type[0]}"]
@@ -2078,6 +2033,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "u16", 'h']
       - ["f16", "u32", 'h']
       - ["f16", "u64", 'h']
     compose:
@@ -2088,21 +2044,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtnu.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-  - name: "vcvtn{type[2]}_{type[1]}_{type[0]}"
-    doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "u16", 'h', 'u32']
-    compose:
-      - 'vcvtnh_{type[3]}_f16(a) as u16'
-
   - name: "vcvtm{neon_type[1].no}_{neon_type[0]}"
     doc: "Floating-point convert to signed integer, rounding toward minus infinity"
     arguments: ["a: {neon_type[0]}"]
@@ -2393,6 +2334,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "i16", 'h']
       - ["f16", "i32", 'h']
       - ["f16", "i64", 'h']
     compose:
@@ -2403,21 +2345,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtps.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-  - name: "vcvtp{type[2]}_{type[1]}_{type[0]}"
-    doc: "Floating-point convert to integer, rounding to plus infinity"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "i16", 'h', 'i32']
-    compose:
-      - 'vcvtph_{type[3]}_f16(a) as i16'
-
   - name: "vcvtp{type[2]}_{type[1]}_{type[0]}"
     doc: "Floating-point convert to unsigned integer, rounding to plus infinity"
     arguments: ["a: {type[0]}"]
@@ -2429,6 +2356,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "u16", 'h']
       - ["f16", "u32", 'h']
       - ["f16", "u64", 'h']
     compose:
@@ -2439,21 +2367,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtpu.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-  - name: "vcvtp{type[2]}_{type[1]}_{type[0]}"
-    doc: "Floating-point convert to unsigned integer, rounding to plus infinity"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "u16", 'h', 'u32']
-    compose:
-      - 'vcvtph_{type[3]}_f16(a) as u16'
-
   - name: "vdup{neon_type.laneq_nox}"
     doc: "Set all vector lanes to the same value"
     arguments: ["a: {neon_type}"]
@@ -12034,6 +11947,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "i16", 'h']
       - ["f16", "i32", 'h']
       - ["f16", "i64", 'h']
     compose:
@@ -12044,22 +11958,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtms.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-  - name: "vcvtm{type[2]}_{type[1]}_{type[0]}"
-    doc: "Floating-point convert to integer, rounding towards minus infinity"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "i16", 'h', 'i32']
-    compose:
-      - 'vcvtmh_{type[3]}_f16(a) as i16'
-
-
   - name: "vcvtm{type[2]}_{type[1]}_{type[0]}"
     doc: "Floating-point convert to unsigned integer, rounding towards minus infinity"
     arguments: ["a: {type[0]}"]
@@ -12071,6 +11969,7 @@ intrinsics:
       - *target-not-arm64ec
     safety: safe
     types:
+      - ["f16", "u16", 'h']
       - ["f16", "u32", 'h']
       - ["f16", "u64", 'h']
     compose:
@@ -12081,21 +11980,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.fcvtmu.{type[1]}.{type[0]}"
               arch: aarch64,arm64ec
 
-  - name: "vcvtm{type[2]}_{type[1]}_{type[0]}"
-    doc: "Floating-point convert to integer, rounding towards minus infinity"
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]]
-      - *neon-fp16
-      - *neon-unstable-f16
-      - *target-not-arm64ec
-    safety: safe
-    types:
-      - ["f16", "u16", 'h', 'u32']
-    compose:
-      - 'vcvtmh_{type[3]}_f16(a) as u16'
-
   - name: "vmlal_high_n_{neon_type[1]}"
     doc: "Multiply-add long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]

From f8df4ea0bd329c2584b3f4e056ffcb489d9d9fa5 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Thu, 30 Apr 2026 06:12:54 +0530
Subject: [PATCH 295/326] Use latest clang versions from kernel.org

---
 ci/docker/aarch64-unknown-linux-gnu/Dockerfile     | 10 ++++++++--
 ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile  |  9 +++++++--
 ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile | 10 ++++++++--
 ci/docker/x86_64-unknown-linux-gnu/Dockerfile      |  7 +++++++
 4 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
index 2768c521eb..8435dd3ded 100644
--- a/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
@@ -10,8 +10,14 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   qemu-user \
   make \
   file \
-  clang \
-  lld
+  xz-utils \
+  wget
+
+RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN mkdir llvm
+RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
+
+ENV PATH="/llvm/bin:$PATH"
 
 ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \
     CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max -L /usr/aarch64-linux-gnu" \
diff --git a/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile b/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile
index f85c6a2592..0e8efc64bb 100644
--- a/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile
@@ -9,10 +9,9 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   qemu-user \
   make \
   file \
-  clang \
   curl \
   xz-utils \
-  lld
+  wget
 
 ENV TOOLCHAIN="arm-gnu-toolchain-14.3.rel1-x86_64-aarch64_be-none-linux-gnu"
 
@@ -21,6 +20,12 @@ RUN curl -L "https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/bin
 RUN tar -xvf "${TOOLCHAIN}.tar.xz"
 RUN mkdir /toolchains && mv "./${TOOLCHAIN}" /toolchains
 
+RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN mkdir llvm
+RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
+
+ENV PATH="/llvm/bin:$PATH"
+
 ENV AARCH64_BE_TOOLCHAIN="/toolchains/${TOOLCHAIN}"
 ENV AARCH64_BE_LIBC="${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc"
 
diff --git a/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile
index 602249c0ec..c0a4ed3e70 100644
--- a/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile
+++ b/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile
@@ -10,8 +10,14 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   qemu-user \
   make \
   file \
-  clang \
-  lld
+  wget
+
+RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN mkdir llvm
+RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
+
+ENV PATH="/llvm/bin:$PATH"
+
 ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \
     CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \
     OBJDUMP=arm-linux-gnueabihf-objdump
diff --git a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
index 17c6d25215..ca6192a38d 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
@@ -15,6 +15,13 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
 RUN wget http://ci-mirrors.rust-lang.org/sde-external-10.8.0-2026-03-15-lin.tar.xz -O sde.tar.xz
 RUN mkdir intel-sde
 RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde
+
+RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN mkdir llvm
+RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
+
+ENV PATH="/llvm/bin:$PATH"
+
 ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \
             -cpuid-in /checkout/ci/docker/x86_64-unknown-linux-gnu/cpuid.def \
             -rtm-mode full -tsx --"

From aa9ed50428ce6bd90efafdc3911bef0830c63513 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 03:48:26 +0530
Subject: [PATCH 296/326] Change implementation of `vext`

---
 .../core_arch/src/aarch64/neon/generated.rs   |  16 +-
 crates/core_arch/src/aarch64/neon/mod.rs      |   1 -
 .../src/arm_shared/neon/generated.rs          | 588 ++++++------------
 crates/core_arch/src/arm_shared/neon/mod.rs   |   2 +-
 .../spec/neon/aarch64.spec.yml                |  12 +-
 .../spec/neon/arm_shared.spec.yml             | 100 +--
 6 files changed, 235 insertions(+), 484 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 2624e2f22d..68320e916d 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -10344,13 +10344,7 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"]
@@ -10361,13 +10355,7 @@ pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"]
diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index b140131012..7ce79671f7 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -12,7 +12,6 @@ pub use self::generated::*;
 
 use crate::{
     core_arch::{arm_shared::*, simd::*},
-    hint::unreachable_unchecked,
     intrinsics::{simd::*, *},
     mem::transmute,
 };
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 1ae7f3f3b0..8f95952084 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -11956,15 +11956,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
@@ -11987,13 +11979,7 @@ pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 )]
 pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
@@ -12016,13 +12002,7 @@ pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 )]
 pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
@@ -12045,13 +12025,7 @@ pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 )]
 pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
@@ -12125,17 +12099,20 @@ pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_
 pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12160,17 +12137,20 @@ pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12195,17 +12175,20 @@ pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12230,17 +12213,20 @@ pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12265,17 +12251,20 @@ pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12300,17 +12289,20 @@ pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12336,17 +12328,20 @@ pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(N, 3);
     unsafe {
-        match N & 0b111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
-            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
-            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
-            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
-            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12370,15 +12365,7 @@ pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 )]
 pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
@@ -12401,15 +12388,7 @@ pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 )]
 pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
@@ -12432,15 +12411,7 @@ pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 )]
 pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
@@ -12463,15 +12434,7 @@ pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 )]
 pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
@@ -12494,15 +12457,7 @@ pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 )]
 pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
@@ -12525,15 +12480,7 @@ pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        match N & 0b11 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
-            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
-            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
@@ -12556,13 +12503,7 @@ pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 )]
 pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
@@ -12585,13 +12526,7 @@ pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 )]
 pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        match N & 0b1 {
-            0 => simd_shuffle!(a, b, [0, 1]),
-            1 => simd_shuffle!(a, b, [1, 2]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
@@ -12615,85 +12550,28 @@ pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     static_assert_uimm_bits!(N, 4);
     unsafe {
-        match N & 0b1111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
-            ),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7,
+                N as u32 + 8,
+                N as u32 + 9,
+                N as u32 + 10,
+                N as u32 + 11,
+                N as u32 + 12,
+                N as u32 + 13,
+                N as u32 + 14,
+                N as u32 + 15
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12718,85 +12596,28 @@ pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     static_assert_uimm_bits!(N, 4);
     unsafe {
-        match N & 0b1111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
-            ),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7,
+                N as u32 + 8,
+                N as u32 + 9,
+                N as u32 + 10,
+                N as u32 + 11,
+                N as u32 + 12,
+                N as u32 + 13,
+                N as u32 + 14,
+                N as u32 + 15
+            ]
+        )
     }
 }
 #[doc = "Extract vector from pair of vectors"]
@@ -12821,85 +12642,28 @@ pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
     static_assert_uimm_bits!(N, 4);
     unsafe {
-        match N & 0b1111 {
-            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
-            ),
-            _ => unreachable_unchecked(),
-        }
+        simd_shuffle!(
+            a,
+            b,
+            [
+                N as u32,
+                N as u32 + 1,
+                N as u32 + 2,
+                N as u32 + 3,
+                N as u32 + 4,
+                N as u32 + 5,
+                N as u32 + 6,
+                N as u32 + 7,
+                N as u32 + 8,
+                N as u32 + 9,
+                N as u32 + 10,
+                N as u32 + 11,
+                N as u32 + 12,
+                N as u32 + 13,
+                N as u32 + 14,
+                N as u32 + 15
+            ]
+        )
     }
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index c4249c2b3c..12d3c090ed 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -7,7 +7,7 @@ mod generated;
 #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))]
 pub use self::generated::*;
 
-use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::*, mem::transmute};
+use crate::{core_arch::simd::*, intrinsics::simd::*, mem::transmute};
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 75e7e88362..76a6b57410 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -2662,10 +2662,10 @@ intrinsics:
       - FnCall: [static_assert_uimm_bits!, [N, 2]]
       - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]]
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ext, 'N = 1']]}]]
       - FnCall: [rustc_legacy_const_generics, ['2']]
@@ -2673,11 +2673,11 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [poly64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
-      - [float64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - poly64x2_t
+      - float64x2_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']]
 
   - name: "vmla{neon_type.no}"
     doc: "Floating-point multiply-add to accumulator"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 08a80c3719..3ddd8db3b6 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -1719,10 +1719,10 @@ intrinsics:
           - "transmute"
           - - FnCall: ['vget{neon_type[1].lane_nox}', [a], [N]]
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]]
@@ -1733,20 +1733,20 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
-      - [int16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
-      - [uint8x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
-      - [uint16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
-      - [poly8x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
-      - [poly16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - int8x8_t
+      - int16x8_t
+      - uint8x8_t
+      - uint16x8_t
+      - poly8x8_t
+      - poly16x8_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 3]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7]']]
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 15']]}]]
@@ -1757,17 +1757,17 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x16_t, 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }']
-      - [uint8x16_t, 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }']
-      - [poly8x16_t, 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }']
+      - int8x16_t
+      - uint8x16_t
+      - poly8x16_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 4]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7, N as u32 + 8, N as u32 + 9, N as u32 + 10, N as u32 + 11, N as u32 + 12, N as u32 + 13, N as u32 + 14, N as u32 + 15]']]
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]]
@@ -1778,21 +1778,21 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x4_t,'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
-      - [int32x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
-      - [uint16x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
-      - [uint32x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
-      - [poly16x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
-      - [float32x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - int16x4_t
+      - int32x4_t
+      - uint16x4_t
+      - uint32x4_t
+      - poly16x4_t
+      - float32x4_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 2]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]']]
 
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]]
@@ -1805,15 +1805,15 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [float16x4_t, 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }']
+      - float16x4_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 2]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]']]
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]]
@@ -1826,17 +1826,17 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [float16x8_t, 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }']
+      - float16x8_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 3]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7]']]
 
 
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 1']]}]]
@@ -1847,17 +1847,17 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int32x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
-      - [uint32x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
-      - [float32x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - int32x2_t
+      - uint32x2_t
+      - float32x2_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']]
 
-  - name: "vext{neon_type[0].no}"
+  - name: "vext{neon_type.no}"
     doc: "Extract vector from pair of vectors"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[0]}"
+    arguments: ["a: {neon_type}", "b: {neon_type}"]
+    return_type: "{neon_type}"
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmov, 'N = 1']]}]]
@@ -1868,11 +1868,11 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
-      - [uint64x2_t, 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }']
+      - int64x2_t
+      - uint64x2_t
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, 1]]
-      - Identifier: ["{type[1]}", UnsafeSymbol]
+      - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']]
 
   - name: "vmla{neon_type[0].no}"
     doc: "Multiply-add to accumulator"

From 5cda14d8126a23cf65b05158f1cccbf769817b38 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 03:50:54 +0530
Subject: [PATCH 297/326] Change implementation of `vcopy{q}_lane{q}`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 2588 +----------------
 .../spec/neon/aarch64.spec.yml                |  106 +-
 2 files changed, 108 insertions(+), 2586 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 68320e916d..46aede98bb 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4131,13 +4131,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_f32::<LANE1>(vget_lane_f32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
@@ -4152,19 +4146,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_s8::<LANE1>(vget_lane_s8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
@@ -4179,15 +4161,7 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
 pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_s16::<LANE1>(vget_lane_s16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
@@ -4202,13 +4176,7 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
 pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_s32::<LANE1>(vget_lane_s32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
@@ -4223,19 +4191,7 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
 pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_u8::<LANE1>(vget_lane_u8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
@@ -4253,15 +4209,7 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
 ) -> uint16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_u16::<LANE1>(vget_lane_u16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
@@ -4279,13 +4227,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 ) -> uint32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_u32::<LANE1>(vget_lane_u32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
@@ -4300,19 +4242,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_p8::<LANE1>(vget_lane_p8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
@@ -4330,15 +4260,7 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
 ) -> poly16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_p16::<LANE1>(vget_lane_p16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f64)"]
@@ -4416,14 +4338,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_f32::<LANE1>(vgetq_lane_f32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
@@ -4438,21 +4353,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 4);
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
@@ -4470,16 +4371,7 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 ) -> int16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
@@ -4497,14 +4389,7 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 ) -> int32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
@@ -4522,21 +4407,7 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 ) -> uint8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 4);
-    unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
@@ -4554,16 +4425,7 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 ) -> uint16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
@@ -4581,14 +4443,7 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 ) -> uint32x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
@@ -4606,21 +4461,7 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 ) -> poly8x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 4);
-    unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
@@ -4638,16 +4479,7 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
 ) -> poly16x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vset_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"]
@@ -4722,16 +4554,7 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_f32::<LANE1>(vget_lane_f32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
@@ -4749,14 +4572,8 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
 ) -> float64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    unsafe {
-        let b: float64x2_t = simd_shuffle!(b, b, [0, 1]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: float64x2_t = vcombine_f64(b, b);
+    vsetq_lane_f64::<LANE1>(vgetq_lane_f64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
@@ -4774,14 +4591,8 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    unsafe {
-        let b: int64x2_t = simd_shuffle!(b, b, [0, 1]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: int64x2_t = vcombine_s64(b, b);
+    vsetq_lane_s64::<LANE1>(vgetq_lane_s64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
@@ -4799,14 +4610,8 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    unsafe {
-        let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: uint64x2_t = vcombine_u64(b, b);
+    vsetq_lane_u64::<LANE1>(vgetq_lane_u64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
@@ -4824,14 +4629,8 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 ) -> poly64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
-    unsafe {
-        let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]);
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: poly64x2_t = vcombine_p64(b, b);
+    vsetq_lane_p64::<LANE1>(vgetq_lane_p64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
@@ -4846,365 +4645,8 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        let b: int8x16_t =
-            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-        match LANE1 & 0b1111 {
-            0 => simd_shuffle!(
-                a,
-                b,
-                [
-                    16 + LANE2 as u32,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    16 + LANE2 as u32,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    16 + LANE2 as u32,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    16 + LANE2 as u32,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    16 + LANE2 as u32,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    16 + LANE2 as u32,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    16 + LANE2 as u32,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    16 + LANE2 as u32,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    16 + LANE2 as u32,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    16 + LANE2 as u32,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    16 + LANE2 as u32,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    16 + LANE2 as u32,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    16 + LANE2 as u32,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    16 + LANE2 as u32,
-                    14,
-                    15
-                ]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    16 + LANE2 as u32,
-                    15
-                ]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    16 + LANE2 as u32
-                ]
-            ),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: int8x16_t = vcombine_s8(b, b);
+    vsetq_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
@@ -5222,20 +4664,8 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 ) -> int16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: int16x8_t = vcombine_s16(b, b);
+    vsetq_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
@@ -5253,16 +4683,8 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: int32x4_t = vcombine_s32(b, b);
+    vsetq_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
@@ -5280,365 +4702,8 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 ) -> uint8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        let b: uint8x16_t =
-            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-        match LANE1 & 0b1111 {
-            0 => simd_shuffle!(
-                a,
-                b,
-                [
-                    16 + LANE2 as u32,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    16 + LANE2 as u32,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    16 + LANE2 as u32,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    16 + LANE2 as u32,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    16 + LANE2 as u32,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    16 + LANE2 as u32,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    16 + LANE2 as u32,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    16 + LANE2 as u32,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    16 + LANE2 as u32,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    16 + LANE2 as u32,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    16 + LANE2 as u32,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    16 + LANE2 as u32,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    16 + LANE2 as u32,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    16 + LANE2 as u32,
-                    14,
-                    15
-                ]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    16 + LANE2 as u32,
-                    15
-                ]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    16 + LANE2 as u32
-                ]
-            ),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: uint8x16_t = vcombine_u8(b, b);
+    vsetq_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
@@ -5656,20 +4721,8 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 ) -> uint16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: uint16x8_t = vcombine_u16(b, b);
+    vsetq_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
@@ -5687,16 +4740,8 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: uint32x4_t = vcombine_u32(b, b);
+    vsetq_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
@@ -5714,365 +4759,8 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 ) -> poly8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        let b: poly8x16_t =
-            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
-        match LANE1 & 0b1111 {
-            0 => simd_shuffle!(
-                a,
-                b,
-                [
-                    16 + LANE2 as u32,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    16 + LANE2 as u32,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    16 + LANE2 as u32,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    16 + LANE2 as u32,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    16 + LANE2 as u32,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    16 + LANE2 as u32,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    16 + LANE2 as u32,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    16 + LANE2 as u32,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    16 + LANE2 as u32,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    16 + LANE2 as u32,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    16 + LANE2 as u32,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    16 + LANE2 as u32,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    16 + LANE2 as u32,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    16 + LANE2 as u32,
-                    14,
-                    15
-                ]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    16 + LANE2 as u32,
-                    15
-                ]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    16 + LANE2 as u32
-                ]
-            ),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: poly8x16_t = vcombine_p8(b, b);
+    vsetq_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
@@ -6090,20 +4778,8 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 ) -> poly16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    let b: poly16x8_t = vcombine_p16(b, b);
+    vsetq_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
@@ -6121,15 +4797,7 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_f32::<LANE1>(vgetq_lane_f32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
@@ -6147,13 +4815,7 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
 ) -> float64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_f64::<LANE1>(vgetq_lane_f64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
@@ -6171,363 +4833,7 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
 ) -> int8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 4);
-    unsafe {
-        match LANE1 & 0b1111 {
-            0 => simd_shuffle!(
-                a,
-                b,
-                [
-                    16 + LANE2 as u32,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    16 + LANE2 as u32,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    16 + LANE2 as u32,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    16 + LANE2 as u32,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    16 + LANE2 as u32,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    16 + LANE2 as u32,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    16 + LANE2 as u32,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    16 + LANE2 as u32,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    16 + LANE2 as u32,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    16 + LANE2 as u32,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    16 + LANE2 as u32,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    16 + LANE2 as u32,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    16 + LANE2 as u32,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    16 + LANE2 as u32,
-                    14,
-                    15
-                ]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    16 + LANE2 as u32,
-                    15
-                ]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    16 + LANE2 as u32
-                ]
-            ),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
@@ -6545,19 +4851,7 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
 ) -> int16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
@@ -6575,15 +4869,7 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
 ) -> int32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
@@ -6601,13 +4887,7 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
 ) -> int64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_s64::<LANE1>(vgetq_lane_s64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
@@ -6625,363 +4905,7 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
 ) -> uint8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 4);
-    unsafe {
-        match LANE1 & 0b1111 {
-            0 => simd_shuffle!(
-                a,
-                b,
-                [
-                    16 + LANE2 as u32,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    16 + LANE2 as u32,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    16 + LANE2 as u32,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    16 + LANE2 as u32,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    16 + LANE2 as u32,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    16 + LANE2 as u32,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    16 + LANE2 as u32,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    16 + LANE2 as u32,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    16 + LANE2 as u32,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    16 + LANE2 as u32,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    16 + LANE2 as u32,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    16 + LANE2 as u32,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    16 + LANE2 as u32,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    16 + LANE2 as u32,
-                    14,
-                    15
-                ]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    16 + LANE2 as u32,
-                    15
-                ]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    16 + LANE2 as u32
-                ]
-            ),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
@@ -6999,19 +4923,7 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
 ) -> uint16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
@@ -7029,15 +4941,7 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
 ) -> uint32x4_t {
     static_assert_uimm_bits!(LANE1, 2);
     static_assert_uimm_bits!(LANE2, 2);
-    unsafe {
-        match LANE1 & 0b11 {
-            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
-            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
-            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
@@ -7055,13 +4959,7 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
 ) -> uint64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_u64::<LANE1>(vgetq_lane_u64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
@@ -7079,363 +4977,7 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
 ) -> poly8x16_t {
     static_assert_uimm_bits!(LANE1, 4);
     static_assert_uimm_bits!(LANE2, 4);
-    unsafe {
-        match LANE1 & 0b1111 {
-            0 => simd_shuffle!(
-                a,
-                b,
-                [
-                    16 + LANE2 as u32,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            1 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    16 + LANE2 as u32,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            2 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    16 + LANE2 as u32,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            3 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    16 + LANE2 as u32,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            4 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    16 + LANE2 as u32,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            5 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    16 + LANE2 as u32,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            6 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    16 + LANE2 as u32,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            7 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    16 + LANE2 as u32,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            8 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    16 + LANE2 as u32,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            9 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    16 + LANE2 as u32,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            10 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    16 + LANE2 as u32,
-                    11,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            11 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    16 + LANE2 as u32,
-                    12,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            12 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    16 + LANE2 as u32,
-                    13,
-                    14,
-                    15
-                ]
-            ),
-            13 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    16 + LANE2 as u32,
-                    14,
-                    15
-                ]
-            ),
-            14 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    16 + LANE2 as u32,
-                    15
-                ]
-            ),
-            15 => simd_shuffle!(
-                a,
-                b,
-                [
-                    0,
-                    1,
-                    2,
-                    3,
-                    4,
-                    5,
-                    6,
-                    7,
-                    8,
-                    9,
-                    10,
-                    11,
-                    12,
-                    13,
-                    14,
-                    16 + LANE2 as u32
-                ]
-            ),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
@@ -7453,19 +4995,7 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
 ) -> poly16x8_t {
     static_assert_uimm_bits!(LANE1, 3);
     static_assert_uimm_bits!(LANE2, 3);
-    unsafe {
-        match LANE1 & 0b111 {
-            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
-            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
-            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
-            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
-            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
-            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
-            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
-            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
@@ -7483,13 +5013,7 @@ pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
 ) -> poly64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    unsafe {
-        match LANE1 & 0b1 {
-            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
-            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
-            _ => unreachable_unchecked(),
-        }
-    }
+    vsetq_lane_p64::<LANE1>(vgetq_lane_p64::<LANE2>(b), a)
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 76a6b57410..e88ebc2b7f 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -8941,19 +8941,19 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int8x8_t, int8x8_t, int8x8_t, '3', '3']
+      - [int16x4_t, int16x4_t, int16x4_t, '2', '2']
+      - [int32x2_t, int32x2_t, int32x2_t, '1', '1']
+      - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3']
+      - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2']
+      - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1']
+      - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3']
+      - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2']
+      - [float32x2_t, float32x2_t, float32x2_t, '1', '1']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", UnsafeSymbol]
+      - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
   - name: "vcopy{neon_type[0].lane_nox}"
     doc: "Insert vector element from another vector element"
@@ -8966,19 +8966,19 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int8x16_t, int8x8_t, int8x16_t, '4', '3']
+      - [int16x8_t, int16x4_t, int16x8_t, '3', '2']
+      - [int32x4_t, int32x2_t, int32x4_t, '2', '1']
+      - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3']
+      - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2']
+      - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1']
+      - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3']
+      - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", UnsafeSymbol]
-      - Identifier: ["{type[6]}", UnsafeSymbol]
+      - Let: [b, '{neon_type[2]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}]
+      - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
   - name: "vcopy_lane_{neon_type[0]}"
     doc: "Insert vector element from another vector element"
@@ -9031,23 +9031,23 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int8x16_t, int8x16_t, int8x16_t, '4', '4']
+      - [int16x8_t, int16x8_t, int16x8_t, '3', '3']
+      - [int32x4_t, int32x4_t, int32x4_t, '2', '2']
+      - [int64x2_t, int64x2_t, int64x2_t, '1', '1']
+      - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4']
+      - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3']
+      - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2']
+      - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1']
+      - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4']
+      - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3']
+      - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1']
+      - [float32x4_t, float32x4_t, float32x4_t, '2', '2']
+      - [float64x2_t, float64x2_t, float64x2_t, '1', '1']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", UnsafeSymbol]
+      - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
@@ -9060,20 +9060,19 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int8x8_t, int8x16_t, int8x8_t, '3', '4']
+      - [int16x4_t, int16x8_t, int16x4_t, '2', '3']
+      - [int32x2_t, int32x4_t, int32x2_t, '1', '2']
+      - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4']
+      - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3']
+      - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2']
+      - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4']
+      - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3']
+      - [float32x2_t, float32x4_t, float32x2_t, '1', '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
-      - Identifier: ["{type[5]}", UnsafeSymbol]
-      - Identifier: ["{type[6]}", UnsafeSymbol]
+      - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
   - name: "vcopyq_lane_{neon_type[0]}"
     doc: "Insert vector element from another vector element"
@@ -9086,15 +9085,15 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [int64x2_t, int64x1_t, ' let b: int64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [uint64x2_t, uint64x1_t, ' let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [poly64x2_t, poly64x1_t, ' let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
-      - [float64x2_t, float64x1_t, ' let b: float64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [int64x2_t, int64x1_t]
+      - [uint64x2_t, uint64x1_t]
+      - [poly64x2_t, poly64x1_t]
+      - [float64x2_t, float64x1_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '1']]
       - FnCall: [static_assert!, ['LANE2 == 0']]
-      - Identifier: ['{type[2]}', UnsafeSymbol]
-      - Identifier: ['{type[3]}', UnsafeSymbol]
+      - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}]
+      - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
   - name: "vcopyq_lane_f32"
     doc: "Insert vector element from another vector element"
@@ -9107,12 +9106,11 @@ intrinsics:
     static_defs: ['const LANE1: i32, const LANE2: i32']
     safety: safe
     types:
-      - [float32x4_t, float32x2_t, ' let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }']
+      - [float32x4_t, float32x2_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, 2]]
       - FnCall: [static_assert_uimm_bits!, [LANE2, 1]]
-      - Identifier: ["{type[2]}", UnsafeSymbol]
-      - Identifier: ["{type[3]}", UnsafeSymbol]
+      - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
   - name: "vcreate_f64"
     doc: "Insert vector element from another vector element"

From f50725352ff9690a4ecb3a89e35fafe71be65adc Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:04:28 +0530
Subject: [PATCH 298/326] Change implementation of `vab{a,d}l_high`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 114 ++++-----
 .../spec/neon/aarch64.spec.yml                | 222 ++----------------
 2 files changed, 71 insertions(+), 265 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 46aede98bb..7059b0e4fa 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -70,10 +70,10 @@ pub fn __jcvt(a: f64) -> i32 {
     assert_instr(sabal2)
 )]
 pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
+    let d = vget_high_s8(b);
+    let e = vget_high_s8(c);
+    let f = vabd_s8(d, e);
     unsafe {
-        let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let f: int8x8_t = vabd_s8(d, e);
         let f: uint8x8_t = simd_cast(f);
         simd_add(a, simd_cast(f))
     }
@@ -88,10 +88,10 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
     assert_instr(sabal2)
 )]
 pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
+    let d = vget_high_s16(b);
+    let e = vget_high_s16(c);
+    let f = vabd_s16(d, e);
     unsafe {
-        let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]);
-        let f: int16x4_t = vabd_s16(d, e);
         let f: uint16x4_t = simd_cast(f);
         simd_add(a, simd_cast(f))
     }
@@ -106,10 +106,10 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     assert_instr(sabal2)
 )]
 pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
+    let d = vget_high_s32(b);
+    let e = vget_high_s32(c);
+    let f = vabd_s32(d, e);
     unsafe {
-        let d: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let e: int32x2_t = simd_shuffle!(c, c, [2, 3]);
-        let f: int32x2_t = vabd_s32(d, e);
         let f: uint32x2_t = simd_cast(f);
         simd_add(a, simd_cast(f))
     }
@@ -124,12 +124,10 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     assert_instr(uabal2)
 )]
 pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let f: uint8x8_t = vabd_u8(d, e);
-        simd_add(a, simd_cast(f))
-    }
+    let d = vget_high_u8(b);
+    let e = vget_high_u8(c);
+    let f = vabd_u8(d, e);
+    unsafe { simd_add(a, simd_cast(f)) }
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"]
@@ -141,12 +139,10 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
     assert_instr(uabal2)
 )]
 pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]);
-        let f: uint16x4_t = vabd_u16(d, e);
-        simd_add(a, simd_cast(f))
-    }
+    let d = vget_high_u16(b);
+    let e = vget_high_u16(c);
+    let f = vabd_u16(d, e);
+    unsafe { simd_add(a, simd_cast(f)) }
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"]
@@ -158,12 +154,10 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
     assert_instr(uabal2)
 )]
 pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]);
-        let f: uint32x2_t = vabd_u32(d, e);
-        simd_add(a, simd_cast(f))
-    }
+    let d = vget_high_u32(b);
+    let e = vget_high_u32(c);
+    let f = vabd_u32(d, e);
+    unsafe { simd_add(a, simd_cast(f)) }
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"]
@@ -226,85 +220,79 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
     vget_lane_f16::<0>(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)))
 }
 #[doc = "Signed Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
-pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
+pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
+    let c = vget_high_s8(a);
+    let d = vget_high_s8(b);
     unsafe {
-        let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let e: uint16x4_t = simd_cast(vabd_s16(c, d));
+        let e: uint8x8_t = simd_cast(vabd_s8(c, d));
         simd_cast(e)
     }
 }
 #[doc = "Signed Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
-pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
+pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
+    let c = vget_high_s16(a);
+    let d = vget_high_s16(b);
     unsafe {
-        let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let d: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let e: uint32x2_t = simd_cast(vabd_s32(c, d));
+        let e: uint16x4_t = simd_cast(vabd_s16(c, d));
         simd_cast(e)
     }
 }
 #[doc = "Signed Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
-pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
+pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
+    let c = vget_high_s32(a);
+    let d = vget_high_s32(b);
     unsafe {
-        let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let e: uint8x8_t = simd_cast(vabd_s8(c, d));
+        let e: uint32x2_t = simd_cast(vabd_s32(c, d));
         simd_cast(e)
     }
 }
 #[doc = "Unsigned Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
-pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        simd_cast(vabd_u16(c, d))
-    }
+pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
+    let c = vget_high_u8(a);
+    let d = vget_high_u8(b);
+    unsafe { simd_cast(vabd_u8(c, d)) }
 }
 #[doc = "Unsigned Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
-pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        simd_cast(vabd_u32(c, d))
-    }
+pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
+    let c = vget_high_u16(a);
+    let d = vget_high_u16(b);
+    unsafe { simd_cast(vabd_u16(c, d)) }
 }
 #[doc = "Unsigned Absolute difference Long"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
-pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        simd_cast(vabd_u8(c, d))
-    }
+pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
+    let c = vget_high_u32(a);
+    let d = vget_high_u32(b);
+    unsafe { simd_cast(vabd_u32(c, d)) }
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index e88ebc2b7f..26a542cdc3 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -220,103 +220,11 @@ intrinsics:
     safety: safe
     types:
       - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t]
-    compose:
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - [8, 9, 10, 11, 12, 13, 14, 15]
-      - Let:
-          - d
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - [8, 9, 10, 11, 12, 13, 14, 15]
-      - Let:
-          - e
-          - "{neon_type[3]}"
-          - FnCall:
-              - simd_cast
-              - - FnCall:
-                    - "vabd_{neon_type[0]}"
-                    - - c
-                      - d
-      - FnCall:
-          - simd_cast
-          - - e
-
-  - name: "vabdl_high{neon_type[0].noq}"
-    doc: Signed Absolute difference Long
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[1]}"
-    attr:
-      - *neon-stable
-      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
-    safety: safe
-    types:
       - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t]
-    compose:
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - [4, 5, 6, 7]
-      - Let:
-          - d
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - [4, 5, 6, 7]
-      - Let:
-          - e
-          - "{neon_type[3]}"
-          - FnCall:
-              - simd_cast
-              - - FnCall:
-                    - "vabd_{neon_type[0]}"
-                    - - c
-                      - d
-      - FnCall:
-          - simd_cast
-          - - e
-
-  - name: "vabdl_high{neon_type[0].noq}"
-    doc: Signed Absolute difference Long
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[1]}"
-    attr:
-      - *neon-stable
-      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
-    safety: safe
-    types:
       - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t]
     compose:
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - [2, 3]
-      - Let:
-          - d
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - [2, 3]
+      - Let: [c, FnCall: ['vget_high_{neon_type[0]}', [a]]]
+      - Let: [d, FnCall: ['vget_high_{neon_type[0]}', [b]]]
       - Let:
           - e
           - "{neon_type[3]}"
@@ -10050,19 +9958,17 @@ intrinsics:
       - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uabal2]]}]]
     safety: safe
     types:
-      - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]', '[2, 3]']
+      - [uint16x8_t, uint8x16_t, uint8x8_t]
+      - [uint32x4_t, uint16x8_t, uint16x4_t]
+      - [uint64x2_t, uint32x4_t, uint32x2_t]
     compose:
       - Let:
           - d
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]
+          - FnCall: ['vget_high_{neon_type[1]}', [b]]
       - Let:
           - e
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
-      - Let: [f, "{neon_type[2]}", {FnCall: ["vabd_{neon_type[2]}", [d, e]]}]
+          - FnCall: ['vget_high_{neon_type[1]}', [c]]
+      - Let: [f, {FnCall: ["vabd_{neon_type[2]}", [d, e]]}]
       - FnCall:
           - simd_add
           - - a
@@ -10077,36 +9983,25 @@ intrinsics:
       - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [sabal2]]}]]
     safety: safe
     types:
-      - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t]
-      - [int32x4_t, int16x8_t, int16x8_t, '[4, 5, 6, 7]', int16x4_t, uint16x4_t]
-      - [int64x2_t, int32x4_t, int32x4_t, '[2, 3]', int32x2_t, uint32x2_t]
+      - [int16x8_t, int8x16_t, int8x16_t, int8x8_t, uint8x8_t]
+      - [int32x4_t, int16x8_t, int16x8_t, int16x4_t, uint16x4_t]
+      - [int64x2_t, int32x4_t, int32x4_t, int32x2_t, uint32x2_t]
     compose:
       - Let:
           - d
-          - "{neon_type[4]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - "{type[3]}"
+          - FnCall: ['vget_high_{neon_type[1]}', [b]]
       - Let:
           - e
-          - "{neon_type[4]}"
-          - FnCall:
-              - simd_shuffle!
-              - - c
-                - c
-                - "{type[3]}"
+          - FnCall: ['vget_high_{neon_type[2]}', [c]]
       - Let:
           - f
-          - "{neon_type[4]}"
           - FnCall:
-              - "vabd{neon_type[4].no}"
+              - "vabd{neon_type[3].no}"
               - - d
                 - e
       - Let:
           - f
-          - "{neon_type[5]}"
+          - "{neon_type[4]}"
           - FnCall:
               - simd_cast
               - - f
@@ -11502,93 +11397,16 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
     safety: safe
     types:
-      - [uint8x16_t, uint16x8_t, uint8x8_t]
+      - [uint8x16_t, uint16x8_t]
+      - [uint16x8_t, uint32x4_t]
+      - [uint32x4_t, uint64x2_t]
     compose:
       - Let:
           - c
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - [8, 9, 10, 11, 12, 13, 14, 15]
+          - FnCall: ['vget_high_{neon_type[0]}', [a]]
       - Let:
           - d
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - [8, 9, 10, 11, 12, 13, 14, 15]
-      - FnCall:
-          - simd_cast
-          - - FnCall:
-                - "vabd_{neon_type[0]}"
-                - - c
-                  - d
-
-  - name: "vabdl_high{neon_type[0].noq}"
-    doc: Unsigned Absolute difference Long
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[1]}"
-    attr:
-      - *neon-stable
-      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
-    safety: safe
-    types:
-      - [uint16x8_t, uint32x4_t, uint16x4_t]
-    compose:
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - [4, 5, 6, 7]
-      - Let:
-          - d
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - [4, 5, 6, 7]
-
-      - FnCall:
-          - simd_cast
-          - - FnCall:
-                - "vabd_{neon_type[0]}"
-                - - c
-                  - d
-
-  - name: "vabdl_high{neon_type[0].noq}"
-    doc: Unsigned Absolute difference Long
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[1]}"
-    attr:
-      - *neon-stable
-      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
-    safety: safe
-    types:
-      - [uint32x4_t, uint64x2_t, uint32x2_t, int32x2_t]
-    compose:
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - [2, 3]
-      - Let:
-          - d
-          - "{neon_type[2]}"
-          - FnCall:
-              - simd_shuffle!
-              - - b
-                - b
-                - [2, 3]
+          - FnCall: ['vget_high_{neon_type[0]}', [b]]
       - FnCall:
           - simd_cast
           - - FnCall:

From d67c66f70109ca1e48d020e62dffe02846603721 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:14:58 +0530
Subject: [PATCH 299/326] Change implementation of `vcvt{x}_f32_f64`

---
 crates/core_arch/src/aarch64/neon/generated.rs |  9 +++------
 .../stdarch-gen-arm/spec/neon/aarch64.spec.yml | 18 ++++--------------
 2 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 7059b0e4fa..448c4aacda 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -5093,7 +5093,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
-    unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) }
+    vcombine_f32(a, vcvt_f32_f64(b))
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
@@ -5102,10 +5102,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
-    unsafe {
-        let b: float32x2_t = simd_shuffle!(a, a, [2, 3]);
-        simd_cast(b)
-    }
+    unsafe { simd_cast(vget_high_f32(a)) }
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"]
@@ -7266,7 +7263,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
-    unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) }
+    vcombine_f32(a, vcvtx_f32_f64(b))
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 26a542cdc3..ac30a65127 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -1417,15 +1417,7 @@ intrinsics:
     types:
       - [float32x4_t, float64x2_t]
     compose:
-      - Let:
-          - b
-          - float32x2_t
-          - FnCall:
-              - simd_shuffle!
-              - - a
-                - a
-                - '[2, 3]'
-      - FnCall: [simd_cast, [b]]
+      - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]]
 
   - name: "vcvt_high_f16_f32"
     doc: "Floating-point convert to lower precision"
@@ -1486,10 +1478,9 @@ intrinsics:
       - [float32x2_t, float64x2_t, float32x4_t]
     compose:
       - FnCall:
-          - simd_shuffle!
+          - vcombine_f32
           - - a
-            - FnCall: [simd_cast, [b]]
-            - '[0, 1, 2, 3]'
+            - FnCall: [vcvt_f32_f64, [b]]
 
   - name: "vcvtx_f32_f64"
     doc: "Floating-point convert to lower precision narrow, rounding to odd"
@@ -1538,10 +1529,9 @@ intrinsics:
       - [float32x2_t, float64x2_t, float32x4_t]
     compose:
       - FnCall:
-          - simd_shuffle!
+          - vcombine_f32
           - - a
             - FnCall: [vcvtx_f32_f64, [b]]
-            - '[0, 1, 2, 3]'
 
   - name: "vcvt{type[2]}"
     doc: "Floating-point convert to fixed-point, rounding toward zero"

From 65fd2fe62b080ff9e58422a545710deaf3abdb0d Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:15:47 +0530
Subject: [PATCH 300/326] Change implementation of `vml{a,s}{l}_lane`

---
 .../core_arch/src/aarch64/neon/generated.rs   |  96 ++--
 .../src/arm_shared/neon/generated.rs          | 432 +++---------------
 .../spec/neon/aarch64.spec.yml                |  52 +--
 .../spec/neon/arm_shared.spec.yml             | 138 +++---
 4 files changed, 181 insertions(+), 537 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 448c4aacda..72462dcb60 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12147,11 +12147,9 @@ pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
-    unsafe {
-        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmlal_s8(a, b, c)
-    }
+    let b = vget_high_s8(b);
+    let c = vget_high_s8(c);
+    vmlal_s8(a, b, c)
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
@@ -12160,11 +12158,9 @@ pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
-    unsafe {
-        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]);
-        vmlal_s16(a, b, c)
-    }
+    let b = vget_high_s16(b);
+    let c = vget_high_s16(c);
+    vmlal_s16(a, b, c)
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
@@ -12173,11 +12169,9 @@ pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let c: int32x2_t = simd_shuffle!(c, c, [2, 3]);
-        vmlal_s32(a, b, c)
-    }
+    let b = vget_high_s32(b);
+    let c = vget_high_s32(c);
+    vmlal_s32(a, b, c)
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
@@ -12186,11 +12180,9 @@ pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmlal_u8(a, b, c)
-    }
+    let b = vget_high_u8(b);
+    let c = vget_high_u8(c);
+    vmlal_u8(a, b, c)
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
@@ -12199,11 +12191,9 @@ pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]);
-        vmlal_u16(a, b, c)
-    }
+    let b = vget_high_u16(b);
+    let c = vget_high_u16(c);
+    vmlal_u16(a, b, c)
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
@@ -12212,11 +12202,9 @@ pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]);
-        vmlal_u32(a, b, c)
-    }
+    let b = vget_high_u32(b);
+    let c = vget_high_u32(c);
+    vmlal_u32(a, b, c)
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"]
@@ -12391,11 +12379,9 @@ pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
-    unsafe {
-        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmlsl_s8(a, b, c)
-    }
+    let b = vget_high_s8(b);
+    let c = vget_high_s8(c);
+    vmlsl_s8(a, b, c)
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
@@ -12404,11 +12390,9 @@ pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
-    unsafe {
-        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]);
-        vmlsl_s16(a, b, c)
-    }
+    let b = vget_high_s16(b);
+    let c = vget_high_s16(c);
+    vmlsl_s16(a, b, c)
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
@@ -12417,11 +12401,9 @@ pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let c: int32x2_t = simd_shuffle!(c, c, [2, 3]);
-        vmlsl_s32(a, b, c)
-    }
+    let b = vget_high_s32(b);
+    let c = vget_high_s32(c);
+    vmlsl_s32(a, b, c)
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
@@ -12430,11 +12412,9 @@ pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmlsl_u8(a, b, c)
-    }
+    let b = vget_high_u8(b);
+    let c = vget_high_u8(c);
+    vmlsl_u8(a, b, c)
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
@@ -12443,11 +12423,9 @@ pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]);
-        vmlsl_u16(a, b, c)
-    }
+    let b = vget_high_u16(b);
+    let c = vget_high_u16(c);
+    vmlsl_u16(a, b, c)
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
@@ -12456,11 +12434,9 @@ pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]);
-        vmlsl_u32(a, b, c)
-    }
+    let b = vget_high_u32(b);
+    let c = vget_high_u32(c);
+    vmlsl_u32(a, b, c)
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 8f95952084..134a549daf 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -26170,7 +26170,7 @@ pub fn vmla_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmla_f32(a, b, vdup_lane_f32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
@@ -26197,7 +26197,7 @@ pub fn vmla_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmla_f32(a, b, vdup_laneq_f32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
@@ -26224,13 +26224,7 @@ pub fn vmlaq_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlaq_f32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlaq_f32(a, b, vdupq_lane_f32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
@@ -26257,13 +26251,7 @@ pub fn vmlaq_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlaq_f32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlaq_f32(a, b, vdupq_laneq_f32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
@@ -26286,13 +26274,7 @@ pub fn vmlaq_laneq_f32<const LANE: i32>(
 )]
 pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmla_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmla_s16(a, b, vdup_lane_s16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
@@ -26315,13 +26297,7 @@ pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 )]
 pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmla_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmla_u16(a, b, vdup_lane_u16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
@@ -26344,13 +26320,7 @@ pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 )]
 pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmla_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmla_s16(a, b, vdup_laneq_s16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
@@ -26373,13 +26343,7 @@ pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 )]
 pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmla_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmla_u16(a, b, vdup_laneq_u16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
@@ -26402,26 +26366,7 @@ pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 )]
 pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlaq_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlaq_s16(a, b, vdupq_lane_s16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
@@ -26444,26 +26389,7 @@ pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 )]
 pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlaq_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlaq_u16(a, b, vdupq_lane_u16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
@@ -26486,26 +26412,7 @@ pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 )]
 pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlaq_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlaq_s16(a, b, vdupq_laneq_s16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
@@ -26528,26 +26435,7 @@ pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 )]
 pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlaq_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlaq_u16(a, b, vdupq_laneq_u16::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
@@ -26570,7 +26458,7 @@ pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 )]
 pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmla_s32(a, b, vdup_lane_s32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
@@ -26593,7 +26481,7 @@ pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 )]
 pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmla_u32(a, b, vdup_lane_u32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
@@ -26616,7 +26504,7 @@ pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 )]
 pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmla_s32(a, b, vdup_laneq_s32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
@@ -26639,7 +26527,7 @@ pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 )]
 pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmla_u32(a, b, vdup_laneq_u32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
@@ -26662,13 +26550,7 @@ pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 )]
 pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlaq_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlaq_s32(a, b, vdupq_lane_s32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
@@ -26691,13 +26573,7 @@ pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 )]
 pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlaq_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlaq_u32(a, b, vdupq_lane_u32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
@@ -26720,13 +26596,7 @@ pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 )]
 pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlaq_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlaq_s32(a, b, vdupq_laneq_s32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
@@ -26749,13 +26619,7 @@ pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 )]
 pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlaq_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlaq_u32(a, b, vdupq_laneq_u32::<LANE>(c))
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
@@ -27240,13 +27104,7 @@ pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlal_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlal_s16(a, b, vdup_lane_s16::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
@@ -27269,13 +27127,7 @@ pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 )]
 pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlal_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlal_s16(a, b, vdup_laneq_s16::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
@@ -27298,7 +27150,7 @@ pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 )]
 pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlal_s32(a, b, vdup_lane_s32::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
@@ -27321,7 +27173,7 @@ pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 )]
 pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlal_s32(a, b, vdup_laneq_s32::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
@@ -27344,13 +27196,7 @@ pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 )]
 pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlal_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlal_u16(a, b, vdup_lane_u16::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
@@ -27373,13 +27219,7 @@ pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 )]
 pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlal_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlal_u16(a, b, vdup_laneq_u16::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
@@ -27402,7 +27242,7 @@ pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 )]
 pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlal_u32(a, b, vdup_lane_u32::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
@@ -27425,7 +27265,7 @@ pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 )]
 pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlal_u32(a, b, vdup_laneq_u32::<LANE>(c))
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
@@ -27704,7 +27544,7 @@ pub fn vmls_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmls_f32(a, b, vdup_lane_f32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
@@ -27731,7 +27571,7 @@ pub fn vmls_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmls_f32(a, b, vdup_laneq_f32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
@@ -27758,13 +27598,7 @@ pub fn vmlsq_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlsq_f32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsq_f32(a, b, vdupq_lane_f32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
@@ -27791,13 +27625,7 @@ pub fn vmlsq_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsq_f32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsq_f32(a, b, vdupq_laneq_f32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
@@ -27820,13 +27648,7 @@ pub fn vmlsq_laneq_f32<const LANE: i32>(
 )]
 pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmls_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmls_s16(a, b, vdup_lane_s16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
@@ -27849,13 +27671,7 @@ pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 )]
 pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmls_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmls_u16(a, b, vdup_lane_u16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
@@ -27878,13 +27694,7 @@ pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 )]
 pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmls_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmls_s16(a, b, vdup_laneq_s16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
@@ -27907,13 +27717,7 @@ pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 )]
 pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmls_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmls_u16(a, b, vdup_laneq_u16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
@@ -27936,26 +27740,7 @@ pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 )]
 pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsq_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlsq_s16(a, b, vdupq_lane_s16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
@@ -27978,26 +27763,7 @@ pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 )]
 pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsq_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlsq_u16(a, b, vdupq_lane_u16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
@@ -28020,26 +27786,7 @@ pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 )]
 pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlsq_s16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlsq_s16(a, b, vdupq_laneq_s16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
@@ -28062,26 +27809,7 @@ pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 )]
 pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlsq_u16(
-            a,
-            b,
-            simd_shuffle!(
-                c,
-                c,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    vmlsq_u16(a, b, vdupq_laneq_u16::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
@@ -28104,7 +27832,7 @@ pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 )]
 pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmls_s32(a, b, vdup_lane_s32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
@@ -28127,7 +27855,7 @@ pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 )]
 pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmls_u32(a, b, vdup_lane_u32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
@@ -28150,7 +27878,7 @@ pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 )]
 pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmls_s32(a, b, vdup_laneq_s32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
@@ -28173,7 +27901,7 @@ pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 )]
 pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmls_u32(a, b, vdup_laneq_u32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
@@ -28196,13 +27924,7 @@ pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 )]
 pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlsq_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsq_s32(a, b, vdupq_lane_s32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
@@ -28225,13 +27947,7 @@ pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 )]
 pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        vmlsq_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsq_u32(a, b, vdupq_lane_u32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
@@ -28254,13 +27970,7 @@ pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 )]
 pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsq_s32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsq_s32(a, b, vdupq_laneq_s32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
@@ -28283,13 +27993,7 @@ pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 )]
 pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsq_u32(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsq_u32(a, b, vdupq_laneq_u32::<LANE>(c))
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
@@ -28774,13 +28478,7 @@ pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsl_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsl_s16(a, b, vdup_lane_s16::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
@@ -28803,13 +28501,7 @@ pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 )]
 pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlsl_s16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsl_s16(a, b, vdup_laneq_s16::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
@@ -28832,7 +28524,7 @@ pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 )]
 pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlsl_s32(a, b, vdup_lane_s32::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
@@ -28855,7 +28547,7 @@ pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 )]
 pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlsl_s32(a, b, vdup_laneq_s32::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
@@ -28878,13 +28570,7 @@ pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 )]
 pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmlsl_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsl_u16(a, b, vdup_lane_u16::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
@@ -28907,13 +28593,7 @@ pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 )]
 pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmlsl_u16(
-            a,
-            b,
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmlsl_u16(a, b, vdup_laneq_u16::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
@@ -28936,7 +28616,7 @@ pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 )]
 pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlsl_u32(a, b, vdup_lane_u32::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
@@ -28959,7 +28639,7 @@ pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 )]
 pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
+    vmlsl_u32(a, b, vdup_laneq_u32::<LANE>(c))
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index ac30a65127..37f28ca129 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -2600,12 +2600,12 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]']
-      - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]', '[2, 3]']
+      - [int16x8_t, int8x16_t, int8x8_t]
+      - [int32x4_t, int16x8_t, int16x4_t]
+      - [int64x2_t, int32x4_t, int32x2_t]
     compose:
-      - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
-      - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]}]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}]
+      - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}]
       - FnCall: ["vmlal_{neon_type[2]}", [a, b, c]]
 
   - name: "vmlal_high_{neon_type[1]}"
@@ -2617,18 +2617,12 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]']
+      - [uint16x8_t, uint8x16_t, uint8x8_t]
+      - [uint32x4_t, uint16x8_t, uint16x4_t]
+      - [uint64x2_t, uint32x4_t, uint32x2_t]
     compose:
-      - Let:
-          - b
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}]
+      - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}]
       - FnCall: ["vmlal_{neon_type[1]}", [a, b, c]]
 
   - name: "vmlsl_high_{neon_type[1]}"
@@ -2640,18 +2634,12 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]']
-      - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]']
+      - [int16x8_t, int8x16_t, int8x8_t]
+      - [int32x4_t, int16x8_t, int16x4_t]
+      - [int64x2_t, int32x4_t, int32x2_t]
     compose:
-      - Let:
-          - b
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]
-      - Let:
-          - c
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}]
+      - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}]
       - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]]
 
   - name: "vmlsl_high_{neon_type[1]}"
@@ -2663,12 +2651,12 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]']
+      - [uint16x8_t, uint8x16_t, uint8x8_t]
+      - [uint32x4_t, uint16x8_t, uint16x4_t]
+      - [uint64x2_t, uint32x4_t, uint32x2_t]
     compose:
-      - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
-      - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}]
+      - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}]
       - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]]
 
   - name: "vmovn_high{neon_type[1].noq}"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 3ddd8db3b6..a56c6079dc 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -1992,17 +1992,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int64x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [int64x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
+      - [int32x4_t, int16x4_t, int16x4_t, '2']
+      - [int32x4_t, int16x4_t, int16x8_t, '3']
+      - [int64x2_t, int32x2_t, int32x2_t, '1']
+      - [int64x2_t, int32x2_t, int32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmlal_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+            - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vmlal_lane{neon_type[2].no}"
     doc: "Vector widening multiply accumulate with scalar"
@@ -2018,17 +2018,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint32x4_t, uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]']
+      - [uint32x4_t, uint16x4_t, uint16x4_t, '2']
+      - [uint32x4_t, uint16x4_t, uint16x8_t, '3']
+      - [uint64x2_t, uint32x2_t, uint32x2_t, '1']
+      - [uint64x2_t, uint32x2_t, uint32x4_t, '2']
     compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]]
+      - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmlal_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, '{type[5]}']]
+            - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vmlal_{neon_type[1]}"
     doc: "Unsigned multiply-add long"
@@ -2147,15 +2147,15 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int32x4_t, int16x4_t, int16x4_t, '2']
+      - [int32x4_t, int16x4_t, int16x8_t, '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmlsl_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vmlsl_lane{neon_type[2].no}"
     doc: "Vector widening multiply subtract with scalar"
@@ -2171,15 +2171,15 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int64x2_t, int32x2_t, int32x2_t, '[LANE as u32, LANE as u32]', '1']
-      - [int64x2_t, int32x2_t, int32x4_t, '[LANE as u32, LANE as u32]', '2']
+      - [int64x2_t, int32x2_t, int32x2_t, '1']
+      - [int64x2_t, int32x2_t, int32x4_t, '2']
     compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]]
+      - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmlsl_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+            - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vmlsl_lane{neon_type[2].no}"
     doc: "Vector widening multiply subtract with scalar"
@@ -2195,17 +2195,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint32x4_t, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [uint64x2_t, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]']
+      - [uint32x4_t, uint16x4_t, uint16x4_t, '2']
+      - [uint32x4_t, uint16x4_t, uint16x8_t, '3']
+      - [uint64x2_t, uint32x2_t, uint32x2_t, '1']
+      - [uint64x2_t, uint32x2_t, uint32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmlsl_{neon_type[1]}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]]
 
   - name: "vmlsl_{neon_type[1]}"
     doc: "Unsigned multiply-subtract long"
@@ -10901,21 +10901,21 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s16, int16x4_t, int16x4_t, '2']
+      - [_laneq_s16, int16x4_t, int16x8_t, '3']
+      - [q_lane_s16, int16x8_t, int16x4_t, '2']
+      - [q_laneq_s16, int16x8_t, int16x8_t, '3']
+      - [_lane_u16, uint16x4_t, uint16x4_t, '2']
+      - [_laneq_u16, uint16x4_t, uint16x8_t, '3']
+      - [q_lane_u16, uint16x8_t, uint16x4_t, '2']
+      - [q_laneq_u16, uint16x8_t, uint16x8_t, '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmla{neon_type[1].no}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup{type[0]}', [c], [LANE]]
 
   - name: "vmla{type[0]}"
     doc: "Vector multiply accumulate with scalar"
@@ -10931,21 +10931,21 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s32, int32x2_t, int32x2_t, '1']
+      - [_laneq_s32, int32x2_t, int32x4_t, '2']
+      - [q_lane_s32, int32x4_t, int32x2_t, '1']
+      - [q_laneq_s32, int32x4_t, int32x4_t, '2']
+      - [_lane_u32, uint32x2_t, uint32x2_t, '1']
+      - [_laneq_u32, uint32x2_t, uint32x4_t, '2']
+      - [q_lane_u32, uint32x4_t, uint32x2_t, '1']
+      - [q_laneq_u32, uint32x4_t, uint32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmla{neon_type[1].no}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup{type[0]}', [c], [LANE]]
 
   - name: "vmla{type[0]}"
     doc: "Vector multiply accumulate with scalar"
@@ -10961,17 +10961,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_f32, float32x2_t, float32x2_t, '1']
+      - [_laneq_f32, float32x2_t, float32x4_t, '2']
+      - [q_lane_f32, float32x4_t, float32x2_t, '1']
+      - [q_laneq_f32, float32x4_t, float32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmla{neon_type[1].no}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup{type[0]}', [c], [LANE]]
 
   - name: "vmls{neon_type[0].N}"
     doc: "Vector multiply subtract with scalar"
@@ -11050,21 +11050,21 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s16, int16x4_t, int16x4_t, '2']
+      - [_laneq_s16, int16x4_t, int16x8_t, '3']
+      - [q_lane_s16, int16x8_t, int16x4_t, '2']
+      - [q_laneq_s16, int16x8_t, int16x8_t, '3']
+      - [_lane_u16, uint16x4_t, uint16x4_t, '2']
+      - [_laneq_u16, uint16x4_t, uint16x8_t, '3']
+      - [q_lane_u16, uint16x8_t, uint16x4_t, '2']
+      - [q_laneq_u16, uint16x8_t, uint16x8_t, '3']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmls{neon_type[1].no}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup{type[0]}', [c], [LANE]]
 
   - name: "vmls{type[0]}"
     doc: "Vector multiply subtract with scalar"
@@ -11080,21 +11080,21 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s32, int32x2_t, int32x2_t, '1']
+      - [_laneq_s32, int32x2_t, int32x4_t, '2']
+      - [q_lane_s32, int32x4_t, int32x2_t, '1']
+      - [q_laneq_s32, int32x4_t, int32x4_t, '2']
+      - [_lane_u32, uint32x2_t, uint32x2_t, '1']
+      - [_laneq_u32, uint32x2_t, uint32x4_t, '2']
+      - [q_lane_u32, uint32x4_t, uint32x2_t, '1']
+      - [q_laneq_u32, uint32x4_t, uint32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmls{neon_type[1].no}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup{type[0]}', [c], [LANE]]
 
   - name: "vmls{type[0]}"
     doc: "Vector multiply subtract with scalar"
@@ -11110,17 +11110,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_f32, float32x2_t, float32x2_t, '1']
+      - [_laneq_f32, float32x2_t, float32x4_t, '2']
+      - [q_lane_f32, float32x4_t, float32x2_t, '1']
+      - [q_laneq_f32, float32x4_t, float32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - "vmls{neon_type[1].no}"
           - - a
             - b
-            - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]
+            - FnCall: ['vdup{type[0]}', [c], [LANE]]
 
   - name: "vmul{neon_type[0].N}"
     doc: "Vector multiply by scalar"

From 5e2812c60b0face0076b1ab22c18ae01384d0f99 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:23:22 +0530
Subject: [PATCH 301/326] Change implementation of `vmov{n,l}_high`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 66 +++++--------------
 .../spec/neon/aarch64.spec.yml                | 41 +++++-------
 2 files changed, 34 insertions(+), 73 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 72462dcb60..fc6747b24d 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12445,10 +12445,8 @@ pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
 pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmovl_s8(a)
-    }
+    let a = vget_high_s8(a);
+    vmovl_s8(a)
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"]
@@ -12457,10 +12455,8 @@ pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
 pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
-    unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        vmovl_s16(a)
-    }
+    let a = vget_high_s16(a);
+    vmovl_s16(a)
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"]
@@ -12469,10 +12465,8 @@ pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
 pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        vmovl_s32(a)
-    }
+    let a = vget_high_s32(a);
+    vmovl_s32(a)
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"]
@@ -12481,10 +12475,8 @@ pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
 pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmovl_u8(a)
-    }
+    let a = vget_high_u8(a);
+    vmovl_u8(a)
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"]
@@ -12493,10 +12485,8 @@ pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
 pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        vmovl_u16(a)
-    }
+    let a = vget_high_u16(a);
+    vmovl_u16(a)
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"]
@@ -12505,10 +12495,8 @@ pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
 pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
-        vmovl_u32(a)
-    }
+    let a = vget_high_u32(a);
+    vmovl_u32(a)
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"]
@@ -12517,10 +12505,7 @@ pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
-    unsafe {
-        let c: int8x8_t = simd_cast(b);
-        simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
-    }
+    unsafe { vcombine_s8(a, simd_cast(b)) }
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"]
@@ -12529,10 +12514,7 @@ pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
-    unsafe {
-        let c: int16x4_t = simd_cast(b);
-        simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7])
-    }
+    unsafe { vcombine_s16(a, simd_cast(b)) }
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"]
@@ -12541,10 +12523,7 @@ pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
-    unsafe {
-        let c: int32x2_t = simd_cast(b);
-        simd_shuffle!(a, c, [0, 1, 2, 3])
-    }
+    unsafe { vcombine_s32(a, simd_cast(b)) }
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"]
@@ -12553,10 +12532,7 @@ pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
-    unsafe {
-        let c: uint8x8_t = simd_cast(b);
-        simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
-    }
+    unsafe { vcombine_u8(a, simd_cast(b)) }
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"]
@@ -12565,10 +12541,7 @@ pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
-    unsafe {
-        let c: uint16x4_t = simd_cast(b);
-        simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7])
-    }
+    unsafe { vcombine_u16(a, simd_cast(b)) }
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"]
@@ -12577,10 +12550,7 @@ pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
 pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
-    unsafe {
-        let c: uint32x2_t = simd_cast(b);
-        simd_shuffle!(a, c, [0, 1, 2, 3])
-    }
+    unsafe { vcombine_u32(a, simd_cast(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 37f28ca129..074e2af492 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -2668,24 +2668,17 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [xtn2]]}]]
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]']
-      - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int8x16_t]
+      - [int16x4_t, int32x4_t, int16x8_t]
+      - [int32x2_t, int64x2_t, int32x4_t]
+      - [uint8x8_t, uint16x8_t, uint8x16_t]
+      - [uint16x4_t, uint32x4_t, uint16x8_t]
+      - [uint32x2_t, uint64x2_t, uint32x4_t]
     compose:
-      - Let:
-          - c
-          - "{neon_type[0]}"
           - FnCall:
-              - simd_cast
-              - - b
-      - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[0]}'
           - - a
-            - c
-            - "{type[3]}"
+            - FnCall: ['simd_cast', [b]]
 
   - name: "vneg{neon_type.no}"
     doc: Negate
@@ -6788,14 +6781,13 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sxtl2]]}]]
     safety: safe
     types:
-      - [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]']
-      - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]']
+      - [int8x16_t, int16x8_t]
+      - [int16x8_t, int32x4_t]
+      - [int32x4_t, int64x2_t]
     compose:
       - Let:
           - a
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]
+          - FnCall: ['vget_high_{neon_type[0]}', [a]]
       - FnCall: ["vmovl{neon_type[0].noq}", [a]]
 
   - name: "vmovl_high{neon_type[0].noq}"
@@ -6807,14 +6799,13 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uxtl2]]}]]
     safety: safe
     types:
-      - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]']
-      - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]']
+      - [uint8x16_t, uint16x8_t]
+      - [uint16x8_t, uint32x4_t]
+      - [uint32x4_t, uint64x2_t]
     compose:
       - Let:
           - a
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]
+          - FnCall: ['vget_high_{neon_type[0]}', [a]]
       - FnCall: ["vmovl{neon_type[0].noq}", [a]]
 
   - name: "vpadd{neon_type[0].no}"

From 580da003fd08c8fa6655b95c3732bbea747bda35 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:23:51 +0530
Subject: [PATCH 302/326] Change implementation of `vmull_{high,lane}`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 56 +++++++------------
 .../src/arm_shared/neon/generated.rs          | 36 +++---------
 .../spec/neon/aarch64.spec.yml                | 52 ++++++-----------
 .../spec/neon/arm_shared.spec.yml             | 20 +++----
 4 files changed, 56 insertions(+), 108 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index fc6747b24d..7f53a0c628 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12822,11 +12822,9 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
 pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmull_p8(a, b)
-    }
+    let a = vget_high_p8(a);
+    let b = vget_high_p8(b);
+    vmull_p8(a, b)
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"]
@@ -12835,11 +12833,9 @@ pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmull_s8(a, b)
-    }
+    let a = vget_high_s8(a);
+    let b = vget_high_s8(b);
+    vmull_s8(a, b)
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"]
@@ -12848,11 +12844,9 @@ pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
-    unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        vmull_s16(a, b)
-    }
+    let a = vget_high_s16(a);
+    let b = vget_high_s16(b);
+    vmull_s16(a, b)
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"]
@@ -12861,11 +12855,9 @@ pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
 pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        vmull_s32(a, b)
-    }
+    let a = vget_high_s32(a);
+    let b = vget_high_s32(b);
+    vmull_s32(a, b)
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"]
@@ -12874,11 +12866,9 @@ pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vmull_u8(a, b)
-    }
+    let a = vget_high_u8(a);
+    let b = vget_high_u8(b);
+    vmull_u8(a, b)
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"]
@@ -12887,11 +12877,9 @@ pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        vmull_u16(a, b)
-    }
+    let a = vget_high_u16(a);
+    let b = vget_high_u16(b);
+    vmull_u16(a, b)
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"]
@@ -12900,11 +12888,9 @@ pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
 pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        vmull_u32(a, b)
-    }
+    let a = vget_high_u32(a);
+    let b = vget_high_u32(b);
+    vmull_u32(a, b)
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 134a549daf..111397752b 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -30965,12 +30965,7 @@ pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 )]
 pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmull_s16(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmull_s16(a, vdup_lane_s16::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
@@ -30993,12 +30988,7 @@ pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t
 )]
 pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmull_s16(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmull_s16(a, vdup_laneq_s16::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
@@ -31021,7 +31011,7 @@ pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 )]
 pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    vmull_s32(a, vdup_lane_s32::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
@@ -31044,7 +31034,7 @@ pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t
 )]
 pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    vmull_s32(a, vdup_laneq_s32::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
@@ -31067,12 +31057,7 @@ pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 )]
 pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        vmull_u16(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmull_u16(a, vdup_lane_u16::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
@@ -31095,12 +31080,7 @@ pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4
 )]
 pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        vmull_u16(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    vmull_u16(a, vdup_laneq_u16::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
@@ -31123,7 +31103,7 @@ pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x
 )]
 pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    vmull_u32(a, vdup_lane_u32::<LANE>(b))
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
@@ -31146,7 +31126,7 @@ pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2
 )]
 pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    vmull_u32(a, vdup_laneq_u32::<LANE>(b))
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 074e2af492..35116dd3a0 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -2675,7 +2675,7 @@ intrinsics:
       - [uint16x4_t, uint32x4_t, uint16x8_t]
       - [uint32x2_t, uint64x2_t, uint32x4_t]
     compose:
-          - FnCall:
+      - FnCall:
           - 'vcombine_{neon_type[0]}'
           - - a
             - FnCall: ['simd_cast', [b]]
@@ -5035,47 +5035,35 @@ intrinsics:
   - name: "vmull_high{neon_type[0].noq}"
     doc: Signed multiply long
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[3]}"
+    return_type: "{neon_type[1]}"
     attr:
       - *neon-stable
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]]
     safety: safe
     types:
-      - [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t]
-      - [int16x8_t, int16x4_t, '[4, 5, 6, 7]', int32x4_t]
-      - [int32x4_t, int32x2_t, '[2, 3]', int64x2_t]
+      - [int8x16_t, int16x8_t]
+      - [int16x8_t, int32x4_t]
+      - [int32x4_t, int64x2_t]
     compose:
-      - Let:
-          - a
-          - "{neon_type[1]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]]
-      - Let:
-          - b
-          - "{neon_type[1]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}]
       - FnCall: ["vmull_{neon_type[0]}", [a, b]]
 
   - name: "vmull_high{neon_type[0].noq}"
     doc: "Unsigned multiply long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[3]}"
+    return_type: "{neon_type[1]}"
     attr:
       - *neon-stable
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]]
     safety: safe
     types:
-      - [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t]
-      - [uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', uint32x4_t]
-      - [uint32x4_t, uint32x2_t, '[2, 3]', uint64x2_t]
+      - [uint8x16_t, uint16x8_t]
+      - [uint16x8_t, uint32x4_t]
+      - [uint32x4_t, uint64x2_t]
     compose:
-      - Let:
-          - a
-          - "{neon_type[1]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]]
-      - Let:
-          - b
-          - "{neon_type[1]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}]
       - FnCall: ["vmull_{neon_type[0]}", [a, b]]
 
   - name: "vmull_p64"
@@ -5101,22 +5089,16 @@ intrinsics:
   - name: "vmull_high{neon_type[0].noq}"
     doc: "Polynomial multiply long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
-    return_type: "{neon_type[3]}"
+    return_type: "{neon_type[1]}"
     attr:
       - *neon-stable
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]]
     safety: safe
     types:
-      - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t]
+      - [poly8x16_t, poly16x8_t]
     compose:
-      - Let:
-          - a
-          - "{neon_type[1]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]]
-      - Let:
-          - b
-          - "{neon_type[1]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}]
       - FnCall: ["vmull_{neon_type[0]}", [a, b]]
 
   - name: "vmull_high{neon_type[0].noq}"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index a56c6079dc..47ec2d0956 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -11357,16 +11357,16 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [int16x4_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int16x4_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x2_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [int32x2_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32]']
+      - [int16x4_t, int16x4_t, int32x4_t, '2']
+      - [int16x4_t, int16x8_t, int32x4_t, '3']
+      - [int32x2_t, int32x2_t, int64x2_t, '1']
+      - [int32x2_t, int32x4_t, int64x2_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmull_{neon_type[0]}"
           - - a
-            - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]]
+            - FnCall: ['vdup_lane{neon_type[1].nox}', [b], [LANE]]
 
   - name: "vmull_lane{neon_type[1].no}"
     doc: "Vector long multiply by scalar"
@@ -11382,16 +11382,16 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]']
+      - [uint16x4_t, uint16x4_t, uint32x4_t, '2']
+      - [uint16x4_t, uint16x8_t, uint32x4_t, '3']
+      - [uint32x2_t, uint32x2_t, uint64x2_t, '1']
+      - [uint32x2_t, uint32x4_t, uint64x2_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
       - FnCall:
           - "vmull_{neon_type[0]}"
           - - a
-            - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]]
+            - FnCall: ['vdup_lane{neon_type[1].nox}', [b], [LANE]]
 
   - name: "vfms{neon_type[0].N}"
     doc: "Floating-point fused Multiply-subtract to accumulator(vector)"

From c44826108a10fd1bddf0b4afa538bd0e3a9bbb47 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:31:21 +0530
Subject: [PATCH 303/326] Change implementation of `vmulx_lane`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 20 +++++------
 .../spec/neon/aarch64.spec.yml                | 36 +++++++------------
 2 files changed, 22 insertions(+), 34 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 7f53a0c628..b7db2f0c9a 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -13074,7 +13074,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmulx_f16(a, vdup_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"]
@@ -13086,7 +13086,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmulx_f16(a, vdup_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"]
@@ -13098,7 +13098,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    vmulxq_f16(a, vdupq_lane_f16::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"]
@@ -13110,7 +13110,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    vmulxq_f16(a, vdupq_laneq_f16::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"]
@@ -13121,7 +13121,7 @@ pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> floa
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
+    vmulx_f32(a, vdup_lane_f32::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"]
@@ -13132,7 +13132,7 @@ pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float3
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
+    vmulx_f32(a, vdup_laneq_f32::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"]
@@ -13143,7 +13143,7 @@ pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmulxq_f32(a, vdupq_lane_f32::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"]
@@ -13154,7 +13154,7 @@ pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    vmulxq_f32(a, vdupq_laneq_f32::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"]
@@ -13165,7 +13165,7 @@ pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> floa
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
+    vmulxq_f64(a, vdupq_laneq_f64::<LANE>(b))
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"]
@@ -13335,7 +13335,7 @@ pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t {
     static_assert!(LANE == 0);
-    unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
+    vmulxq_f64(a, vdupq_lane_f64::<LANE>(b))
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 35116dd3a0..ba248f4f07 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5235,11 +5235,7 @@ intrinsics:
       - FnCall:
           - "vmulx{type[3]}"
           - - a
-            - FnCall:
-                - "simd_shuffle!"
-                - - b
-                  - b
-                  - "{type[4]}"
+            - FnCall: ['vdup{type[0]}', [b], [LANE]]
 
   - name: "vmulx{type[0]}"
     doc: Floating-point multiply extended
@@ -5292,21 +5288,17 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32; 2]']
-      - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32; 2]']
-      - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32; 4]']
-      - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32; 4]']
-      - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32; 2]']
+      - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32']
+      - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32']
+      - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32']
+      - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32']
+      - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64']
     compose:
       - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]]
       - FnCall:
           - "vmulx{type[4]}"
           - - a
-            - FnCall:
-                - "simd_shuffle!"
-                - - b
-                  - b
-                  - "{type[5]}"
+            - FnCall: ['vdup{type[0]}', [b], [LANE]]
 
 
   - name: "vmulx{type[0]}"
@@ -5322,20 +5314,16 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32; 4]']
-      - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32; 4]']
-      - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32; 8]']
-      - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32; 8]']
+      - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16']
+      - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16']
+      - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16']
+      - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16']
     compose:
       - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]]
       - FnCall:
           - "vmulx{type[4]}"
           - - a
-            - FnCall:
-                - "simd_shuffle!"
-                - - b
-                  - b
-                  - "{type[5]}"
+            - FnCall: ['vdup{type[0]}', [b], [LANE]]
 
 
   - name: "vmulx{type[0]}"

From 781f23f437756120d75de4d7a9dfb97395f59cc5 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 04:39:21 +0530
Subject: [PATCH 304/326] Change implementation of `v{add,sub}{l,w}_high`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 84 +++++++------------
 .../src/arm_shared/neon/generated.rs          | 36 ++++----
 .../spec/neon/aarch64.spec.yml                | 62 +++++---------
 .../spec/neon/arm_shared.spec.yml             | 31 ++++---
 4 files changed, 85 insertions(+), 128 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index b7db2f0c9a..eb590b3af3 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -23299,11 +23299,9 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
 pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unsafe {
-        let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let d: int16x8_t = simd_cast(c);
-        let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let f: int16x8_t = simd_cast(e);
-        simd_sub(d, f)
+        let c: int16x8_t = simd_cast(vget_high_s8(a));
+        let d: int16x8_t = simd_cast(vget_high_s8(b));
+        simd_sub(c, d)
     }
 }
 #[doc = "Signed Subtract Long"]
@@ -23314,11 +23312,9 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
 pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
-        let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let d: int32x4_t = simd_cast(c);
-        let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let f: int32x4_t = simd_cast(e);
-        simd_sub(d, f)
+        let c: int32x4_t = simd_cast(vget_high_s16(a));
+        let d: int32x4_t = simd_cast(vget_high_s16(b));
+        simd_sub(c, d)
     }
 }
 #[doc = "Signed Subtract Long"]
@@ -23329,11 +23325,9 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
 pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
-        let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let d: int64x2_t = simd_cast(c);
-        let e: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let f: int64x2_t = simd_cast(e);
-        simd_sub(d, f)
+        let c: int64x2_t = simd_cast(vget_high_s32(a));
+        let d: int64x2_t = simd_cast(vget_high_s32(b));
+        simd_sub(c, d)
     }
 }
 #[doc = "Unsigned Subtract Long"]
@@ -23344,11 +23338,9 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
 pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
-        let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let d: uint16x8_t = simd_cast(c);
-        let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let f: uint16x8_t = simd_cast(e);
-        simd_sub(d, f)
+        let c: uint16x8_t = simd_cast(vget_high_u8(a));
+        let d: uint16x8_t = simd_cast(vget_high_u8(b));
+        simd_sub(c, d)
     }
 }
 #[doc = "Unsigned Subtract Long"]
@@ -23359,11 +23351,9 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
 pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
-        let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let d: uint32x4_t = simd_cast(c);
-        let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        let f: uint32x4_t = simd_cast(e);
-        simd_sub(d, f)
+        let c: uint32x4_t = simd_cast(vget_high_u16(a));
+        let d: uint32x4_t = simd_cast(vget_high_u16(b));
+        simd_sub(c, d)
     }
 }
 #[doc = "Unsigned Subtract Long"]
@@ -23374,11 +23364,9 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
 pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
-        let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let d: uint64x2_t = simd_cast(c);
-        let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        let f: uint64x2_t = simd_cast(e);
-        simd_sub(d, f)
+        let c: uint64x2_t = simd_cast(vget_high_u32(a));
+        let d: uint64x2_t = simd_cast(vget_high_u32(b));
+        simd_sub(c, d)
     }
 }
 #[doc = "Signed Subtract Wide"]
@@ -23388,10 +23376,8 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
 pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
-    unsafe {
-        let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        simd_sub(a, simd_cast(c))
-    }
+    let c = vget_high_s8(b);
+    unsafe { simd_sub(a, simd_cast(c)) }
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"]
@@ -23400,10 +23386,8 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
 pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
-    unsafe {
-        let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        simd_sub(a, simd_cast(c))
-    }
+    let c = vget_high_s16(b);
+    unsafe { simd_sub(a, simd_cast(c)) }
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"]
@@ -23412,10 +23396,8 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
 pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        simd_sub(a, simd_cast(c))
-    }
+    let c = vget_high_s32(b);
+    unsafe { simd_sub(a, simd_cast(c)) }
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"]
@@ -23424,10 +23406,8 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
 pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
-    unsafe {
-        let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
-        simd_sub(a, simd_cast(c))
-    }
+    let c = vget_high_u8(b);
+    unsafe { simd_sub(a, simd_cast(c)) }
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"]
@@ -23436,10 +23416,8 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
 pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
-    unsafe {
-        let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        simd_sub(a, simd_cast(c))
-    }
+    let c = vget_high_u16(b);
+    unsafe { simd_sub(a, simd_cast(c)) }
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"]
@@ -23448,10 +23426,8 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
 pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
-        simd_sub(a, simd_cast(c))
-    }
+    let c = vget_high_u32(b);
+    unsafe { simd_sub(a, simd_cast(c)) }
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 111397752b..6d54e84f25 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -2499,9 +2499,9 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
+    let a: int16x4_t = vget_high_s16(a);
+    let b: int16x4_t = vget_high_s16(b);
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
         let a: int32x4_t = simd_cast(a);
         let b: int32x4_t = simd_cast(b);
         simd_add(a, b)
@@ -2530,9 +2530,9 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
+    let a: int32x2_t = vget_high_s32(a);
+    let b: int32x2_t = vget_high_s32(b);
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
         let a: int64x2_t = simd_cast(a);
         let b: int64x2_t = simd_cast(b);
         simd_add(a, b)
@@ -2561,9 +2561,9 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
+    let a: int8x8_t = vget_high_s8(a);
+    let b: int8x8_t = vget_high_s8(b);
     unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
         let a: int16x8_t = simd_cast(a);
         let b: int16x8_t = simd_cast(b);
         simd_add(a, b)
@@ -2592,9 +2592,9 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
+    let a: uint16x4_t = vget_high_u16(a);
+    let b: uint16x4_t = vget_high_u16(b);
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
         let a: uint32x4_t = simd_cast(a);
         let b: uint32x4_t = simd_cast(b);
         simd_add(a, b)
@@ -2623,9 +2623,9 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
+    let a: uint32x2_t = vget_high_u32(a);
+    let b: uint32x2_t = vget_high_u32(b);
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
         let a: uint64x2_t = simd_cast(a);
         let b: uint64x2_t = simd_cast(b);
         simd_add(a, b)
@@ -2654,9 +2654,9 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
+    let a: uint8x8_t = vget_high_u8(a);
+    let b: uint8x8_t = vget_high_u8(b);
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
         let a: uint16x8_t = simd_cast(a);
         let b: uint16x8_t = simd_cast(b);
         simd_add(a, b)
@@ -2856,8 +2856,8 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
+    let b = vget_high_s16(b);
     unsafe {
-        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
         let b: int32x4_t = simd_cast(b);
         simd_add(a, b)
     }
@@ -2885,8 +2885,8 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
+    let b = vget_high_s32(b);
     unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
         let b: int64x2_t = simd_cast(b);
         simd_add(a, b)
     }
@@ -2914,8 +2914,8 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
+    let b = vget_high_s8(b);
     unsafe {
-        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
         let b: int16x8_t = simd_cast(b);
         simd_add(a, b)
     }
@@ -2943,8 +2943,8 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
+    let b = vget_high_u16(b);
     unsafe {
-        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
         let b: uint32x4_t = simd_cast(b);
         simd_add(a, b)
     }
@@ -2972,8 +2972,8 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
+    let b = vget_high_u32(b);
     unsafe {
-        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
         let b: uint64x2_t = simd_cast(b);
         simd_add(a, b)
     }
@@ -3001,8 +3001,8 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
+    let b = vget_high_u8(b);
     unsafe {
-        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
         let b: uint16x8_t = simd_cast(b);
         simd_add(a, b)
     }
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index ba248f4f07..a6208fac7c 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5667,14 +5667,13 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubw2]]}]]
     safety: safe
     types:
-      - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]']
-      - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]']
+      - [int16x8_t, int8x16_t]
+      - [int32x4_t, int16x8_t]
+      - [int64x2_t, int32x4_t]
     compose:
       - Let:
           - c
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]
+          - FnCall: ['vget_high_{neon_type[1]}', [b]]
       - FnCall:
           - simd_sub
           - - a
@@ -5689,14 +5688,13 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubw2]]}]]
     safety: safe
     types:
-      - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]']
-      - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]']
+      - [uint16x8_t, uint8x16_t]
+      - [uint32x4_t, uint16x8_t]
+      - [uint64x2_t, uint32x4_t]
     compose:
       - Let:
           - c
-          - "{neon_type[2]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]
+          - FnCall: ['vget_high_{neon_type[1]}', [b]]
       - FnCall:
           - simd_sub
           - - a
@@ -5711,27 +5709,19 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubl2]]}]]
     safety: safe
     types:
-      - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t]
-      - [int16x8_t, int32x4_t, '[4, 5, 6, 7]', int16x4_t]
-      - [int32x4_t, int64x2_t, '[2, 3]', int32x2_t]
+      - [int8x16_t, int16x8_t]
+      - [int32x4_t, int64x2_t]
+      - [int16x8_t, int32x4_t]
     compose:
       - Let:
           - c
-          - "{neon_type[3]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]]
-      - Let:
-          - d
           - "{neon_type[1]}"
-          - FnCall: [simd_cast, [c]]
-      - Let:
-          - e
-          - "{neon_type[3]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]]
+          - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]]
       - Let:
-          - f
+          - d
           - "{neon_type[1]}"
-          - FnCall: [simd_cast, [e]]
-      - FnCall: [simd_sub, [d, f]]
+          - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [b]]}]]
+      - FnCall: [simd_sub, [c, d]]
 
   - name: "vsubl_high{neon_type[0].noq}"
     doc: "Unsigned Subtract Long"
@@ -5742,27 +5732,19 @@ intrinsics:
       - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubl2]]}]]
     safety: safe
     types:
-      - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t]
-      - [uint16x8_t, uint32x4_t, '[4, 5, 6, 7]', uint16x4_t]
-      - [uint32x4_t, uint64x2_t, '[2, 3]', uint32x2_t]
+      - [uint8x16_t, uint16x8_t]
+      - [uint16x8_t, uint32x4_t]
+      - [uint32x4_t, uint64x2_t]
     compose:
       - Let:
           - c
-          - "{neon_type[3]}"
-          - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]]
-      - Let:
-          - d
           - "{neon_type[1]}"
-          - FnCall: [simd_cast, [c]]
-      - Let:
-          - e
-          - "{neon_type[3]}"
-          - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]]
+          - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]]
       - Let:
-          - f
+          - d
           - "{neon_type[1]}"
-          - FnCall: [simd_cast, [e]]
-      - FnCall: [simd_sub, [d, f]]
+          - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [b]]}]]
+      - FnCall: [simd_sub, [c, d]]
 
   - name: "vbcax{neon_type.no}"
     doc: Bit clear and exclusive OR
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 47ec2d0956..4024e624ca 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -14478,21 +14478,21 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vaddl_high_s8', 'int8x16_t', 'int16x8_t', 'vaddl', 'saddl2',  'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - ['vaddl_high_s16', 'int16x8_t', 'int32x4_t', 'vaddl', 'saddl2',  'int16x4_t', '[4, 5, 6, 7]']
-      - ['vaddl_high_s32', 'int32x4_t', 'int64x2_t', 'vaddl', 'saddl2',  'int32x2_t', '[2, 3]']
-      - ['vaddl_high_u8', 'uint8x16_t', 'uint16x8_t', 'vaddl', 'uaddl2',  'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - ['vaddl_high_u16', 'uint16x8_t', 'uint32x4_t', 'vaddl', 'uaddl2',  'uint16x4_t', '[4, 5, 6, 7]']
-      - ['vaddl_high_u32', 'uint32x4_t', 'uint64x2_t', 'vaddl', 'uaddl2',  'uint32x2_t', '[2, 3]']
+      - ['vaddl_high_s8', 'int8x16_t', 'int16x8_t', 'vaddl', 'saddl2',  'int8x8_t']
+      - ['vaddl_high_s16', 'int16x8_t', 'int32x4_t', 'vaddl', 'saddl2',  'int16x4_t']
+      - ['vaddl_high_s32', 'int32x4_t', 'int64x2_t', 'vaddl', 'saddl2',  'int32x2_t']
+      - ['vaddl_high_u8', 'uint8x16_t', 'uint16x8_t', 'vaddl', 'uaddl2',  'uint8x8_t']
+      - ['vaddl_high_u16', 'uint16x8_t', 'uint32x4_t', 'vaddl', 'uaddl2',  'uint16x4_t']
+      - ['vaddl_high_u32', 'uint32x4_t', 'uint64x2_t', 'vaddl', 'uaddl2',  'uint32x2_t']
     compose:
       - Let:
           - a
           - '{neon_type[5]}'
-          - FnCall: ['simd_shuffle!', [a, a, '{type[6]}']]
+          - FnCall: ['vget_high_{neon_type[1]}', [a]]
       - Let:
           - b
           - '{neon_type[5]}'
-          - FnCall: ['simd_shuffle!', [b, b, '{type[6]}']]
+          - FnCall: ['vget_high_{neon_type[1]}', [b]]
       - Let: [a, '{neon_type[2]}', {FnCall: [simd_cast, [a]]}]
       - Let: [b, '{neon_type[2]}', {FnCall: [simd_cast, [b]]}]
       - FnCall: [simd_add, [a, b]]
@@ -14534,17 +14534,16 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vaddw_high_s8', 'int16x8_t', 'int8x16_t', 'vaddw', 'saddw2', 'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - ['vaddw_high_s16', 'int32x4_t', 'int16x8_t', 'vaddw', 'saddw2', 'int16x4_t', '[4, 5, 6, 7]']
-      - ['vaddw_high_s32', 'int64x2_t', 'int32x4_t', 'vaddw', 'saddw2', 'int32x2_t', '[2, 3]']
-      - ['vaddw_high_u8', 'uint16x8_t', 'uint8x16_t', 'vaddw', 'uaddw2', 'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - ['vaddw_high_u16', 'uint32x4_t', 'uint16x8_t', 'vaddw', 'uaddw2', 'uint16x4_t', '[4, 5, 6, 7]']
-      - ['vaddw_high_u32', 'uint64x2_t', 'uint32x4_t', 'vaddw', 'uaddw2', 'uint32x2_t', '[2, 3]']
+      - ['vaddw_high_s8', 'int16x8_t', 'int8x16_t', 'vaddw', 'saddw2', 'int8x8_t']
+      - ['vaddw_high_s16', 'int32x4_t', 'int16x8_t', 'vaddw', 'saddw2', 'int16x4_t']
+      - ['vaddw_high_s32', 'int64x2_t', 'int32x4_t', 'vaddw', 'saddw2', 'int32x2_t']
+      - ['vaddw_high_u8', 'uint16x8_t', 'uint8x16_t', 'vaddw', 'uaddw2', 'uint8x8_t']
+      - ['vaddw_high_u16', 'uint32x4_t', 'uint16x8_t', 'vaddw', 'uaddw2', 'uint16x4_t']
+      - ['vaddw_high_u32', 'uint64x2_t', 'uint32x4_t', 'vaddw', 'uaddw2', 'uint32x2_t']
     compose:
       - Let:
           - b
-          - '{neon_type[5]}'
-          - FnCall: ['simd_shuffle!', [b, b, '{type[6]}']]
+          - FnCall: ['vget_high_{neon_type[2]}', [b]]
       - Let:
           - b
           - '{neon_type[1]}'

From a8039144205f1042db8a96bfda08cb5c02fc75b2 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 05:03:26 +0530
Subject: [PATCH 305/326] Change implementation of `vqdmull{_high}{_lane}` and
 `vqrdmulh_lane`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 76 ++++++----------
 .../src/arm_shared/neon/generated.rs          | 90 +++++--------------
 .../spec/neon/aarch64.spec.yml                | 46 +++++-----
 .../spec/neon/arm_shared.spec.yml             | 24 ++---
 4 files changed, 83 insertions(+), 153 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index eb590b3af3..2c49925431 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -14837,11 +14837,9 @@ pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
-        vqdmull_s16(a, b)
-    }
+    let a = vget_high_s16(a);
+    let b = vdup_lane_s16::<N>(b);
+    vqdmull_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
@@ -14852,11 +14850,9 @@ pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
-        vqdmull_s32(a, b)
-    }
+    let a = vget_high_s32(a);
+    let b = vdup_laneq_s32::<N>(b);
+    vqdmull_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
@@ -14867,11 +14863,9 @@ pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
-        vqdmull_s32(a, b)
-    }
+    let a = vget_high_s32(a);
+    let b = vdup_lane_s32::<N>(b);
+    vqdmull_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
@@ -14882,11 +14876,9 @@ pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
-        vqdmull_s16(a, b)
-    }
+    let a = vget_high_s16(a);
+    let b = vdup_laneq_s16::<N>(b);
+    vqdmull_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
@@ -14895,11 +14887,9 @@ pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
-    unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: int16x4_t = vdup_n_s16(b);
-        vqdmull_s16(a, b)
-    }
+    let a = vget_high_s16(a);
+    let b = vdup_n_s16(b);
+    vqdmull_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
@@ -14908,11 +14898,9 @@ pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: int32x2_t = vdup_n_s32(b);
-        vqdmull_s32(a, b)
-    }
+    let a = vget_high_s32(a);
+    let b = vdup_n_s32(b);
+    vqdmull_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
@@ -14921,11 +14909,9 @@ pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
-    unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
-        vqdmull_s16(a, b)
-    }
+    let a = vget_high_s16(a);
+    let b = vget_high_s16(b);
+    vqdmull_s16(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
@@ -14934,11 +14920,9 @@ pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
-    unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
-        vqdmull_s32(a, b)
-    }
+    let a = vget_high_s32(a);
+    let b = vget_high_s32(b);
+    vqdmull_s32(a, b)
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"]
@@ -14949,10 +14933,8 @@ pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
     static_assert_uimm_bits!(N, 3);
-    unsafe {
-        let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
-        vqdmull_s16(a, b)
-    }
+    let b = vdup_laneq_s16::<N>(b);
+    vqdmull_s16(a, b)
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"]
@@ -14963,10 +14945,8 @@ pub fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
-        vqdmull_s32(a, b)
-    }
+    let b = vdup_laneq_s32::<N>(b);
+    vqdmull_s32(a, b)
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 6d54e84f25..3f5b7073e2 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -35001,10 +35001,8 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 )]
 pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
     static_assert_uimm_bits!(N, 2);
-    unsafe {
-        let b: int16x4_t = simd_shuffle!(b, b, [N as u32; 4]);
-        vqdmull_s16(a, b)
-    }
+    let b = vdup_lane_s16::<N>(b);
+    vqdmull_s16(a, b)
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
@@ -35027,10 +35025,8 @@ pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 )]
 pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
     static_assert_uimm_bits!(N, 1);
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [N as u32; 2]);
-        vqdmull_s32(a, b)
-    }
+    let b = vdup_lane_s32::<N>(b);
+    vqdmull_s32(a, b)
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
@@ -35588,11 +35584,8 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
 )]
 pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let b: int16x4_t =
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vqrdmulh_s16(a, b)
-    }
+    let b = vdup_lane_s16::<LANE>(b);
+    vqrdmulh_s16(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
@@ -35615,10 +35608,8 @@ pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4
 )]
 pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
-        vqrdmulh_s32(a, b)
-    }
+    let b = vdup_lane_s32::<LANE>(b);
+    vqrdmulh_s32(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
@@ -35641,11 +35632,8 @@ pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2
 )]
 pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let b: int16x4_t =
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vqrdmulh_s16(a, b)
-    }
+    let b = vdup_laneq_s16::<LANE>(b);
+    vqrdmulh_s16(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
@@ -35668,10 +35656,8 @@ pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x
 )]
 pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
-        vqrdmulh_s32(a, b)
-    }
+    let b = vdup_laneq_s32::<LANE>(b);
+    vqrdmulh_s32(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
@@ -35694,23 +35680,8 @@ pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x
 )]
 pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let b: int16x8_t = simd_shuffle!(
-            b,
-            b,
-            [
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32
-            ]
-        );
-        vqrdmulhq_s16(a, b)
-    }
+    let b = vdupq_lane_s16::<LANE>(b);
+    vqrdmulhq_s16(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
@@ -35733,11 +35704,8 @@ pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x
 )]
 pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let b: int32x4_t =
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vqrdmulhq_s32(a, b)
-    }
+    let b = vdupq_lane_s32::<LANE>(b);
+    vqrdmulhq_s32(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
@@ -35760,23 +35728,8 @@ pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x
 )]
 pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let b: int16x8_t = simd_shuffle!(
-            b,
-            b,
-            [
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32,
-                LANE as u32
-            ]
-        );
-        vqrdmulhq_s16(a, b)
-    }
+    let b = vdupq_laneq_s16::<LANE>(b);
+    vqrdmulhq_s16(a, b)
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
@@ -35799,11 +35752,8 @@ pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16
 )]
 pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let b: int32x4_t =
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vqrdmulhq_s32(a, b)
-    }
+    let b = vdupq_laneq_s32::<LANE>(b);
+    vqrdmulhq_s32(a, b)
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a6208fac7c..11ba7c955d 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -6963,11 +6963,11 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]']
-      - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]']
+      - [int16x8_t, int32x4_t]
+      - [int32x4_t, int64x2_t]
     compose:
-      - Let: [a, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, '{type[3]}']]}]
-      - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, '{type[3]}']]}]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}]
       - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]]
 
   - name: "vqdmull_high_n_{type[1]}"
@@ -6979,11 +6979,11 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int16x8_t, "i16", int32x4_t, int16x4_t, '[4, 5, 6, 7]']
-      - [int32x4_t, "i32", int64x2_t, int32x2_t, '[2, 3]']
+      - [int16x8_t, "i16", int32x4_t]
+      - [int32x4_t, "i32", int64x2_t]
     compose:
-      - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}]
-      - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}]
       - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]]
 
   - name: "vqdmull{type[3]}"
@@ -7038,7 +7038,7 @@ intrinsics:
       - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}]
       - FnCall: ["vqdmulls_s32", [a, b]]
 
-  - name: "vqdmull{type[6]}"
+  - name: "vqdmull{type[3]}"
     doc: "Signed saturating doubling multiply long"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
@@ -7049,12 +7049,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, int16x4_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]', '_high_lane_s16']
-      - [int32x4_t, int32x4_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]', '_high_laneq_s32']
+      - [int16x8_t, int16x4_t, int32x4_t, '_high_lane_s16']
+      - [int32x4_t, int32x4_t, int64x2_t, '_high_laneq_s32']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '2']]
-      - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}]
-      - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}]
       - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]]
 
   - name: "vqdmull_high_lane_s32"
@@ -7068,11 +7068,11 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int32x4_t, int32x2_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]']
+      - [int32x4_t, int32x2_t, int64x2_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '1']]
-      - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}]
-      - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}]
       - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]]
 
   - name: "vqdmull_high_laneq_s16"
@@ -7086,11 +7086,11 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]']
+      - [int16x8_t, int16x8_t, int32x4_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '3']]
-      - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}]
-      - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}]
+      - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}]
       - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]]
 
   - name: "vqdmull_laneq_s16"
@@ -7104,10 +7104,10 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x4_t, int16x8_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]']
+      - [int16x4_t, int16x8_t, int32x4_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '3']]
-      - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
+      - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}]
       - FnCall: [vqdmull_s16, [a, b]]
 
   - name: "vqdmull_laneq_s32"
@@ -7121,10 +7121,10 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int32x2_t, int32x4_t, int64x2_t, '[N as u32, N as u32]']
+      - [int32x2_t, int32x4_t, int64x2_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '2']]
-      - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
+      - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}]
       - FnCall: [vqdmull_s32, [a, b]]
 
   - name: "vqdmlal{type[4]}"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 4024e624ca..e646d22369 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -7590,7 +7590,7 @@ intrinsics:
       - [int16x4_t, int16x4_t, int32x4_t, '[N as u32; 4]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '2']]
-      - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
+      - Let: [b, {FnCall: ['vdup{neon_type[0].lane_nox}', [b], [N]]}]
       - FnCall: [vqdmull_s16, [a, b]]
 
   - name: "vqdmull_lane_s32"
@@ -7607,10 +7607,10 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int32x2_t, int32x2_t, int64x2_t, '[N as u32; 2]']
+      - [int32x2_t, int32x2_t, int64x2_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [N, '1']]
-      - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}]
+      - Let: [b, {FnCall: ['vdup{neon_type[0].lane_nox}', [b], [N]]}]
       - FnCall: [vqdmull_s32, [a, b]]
 
   - name: "vqdmlal{neon_type[1].noq}"
@@ -11230,17 +11230,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [_lane_s16, int16x4_t, int16x4_t, '2']
+      - [_laneq_s16, int16x4_t, int16x8_t, '3']
+      - [q_lane_s16, int16x8_t, int16x4_t, '2']
+      - [q_laneq_s16, int16x8_t, int16x8_t, '3']
+      - [_lane_s32, int32x2_t, int32x2_t, '1']
+      - [_laneq_s32, int32x2_t, int32x4_t, '2']
+      - [q_lane_s32, int32x4_t, int32x2_t, '1']
+      - [q_laneq_s32, int32x4_t, int32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]]
-      - Let: [b, "{neon_type[1]}", {FnCall: [simd_shuffle!, [b, b, '{type[4]}']]}]
+      - Let: [b, {FnCall: ['vdup{type[0]}', [b], [LANE]]}]
       - FnCall: ["vqrdmulh{neon_type[1].no}", [a, b]]
 
   - name: "vqrdmulh{neon_type[0].N}"

From e1217f2ea63640bb32f8a392b6d5c7bac432c7b4 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 05:11:39 +0530
Subject: [PATCH 306/326] Change implementation of `vqmov{u}n_high`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 36 +++++--------------
 .../spec/neon/aarch64.spec.yml                | 24 ++++++-------
 2 files changed, 21 insertions(+), 39 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 2c49925431..60a9e99a3b 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -15030,13 +15030,7 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqmovn_s16(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_s8(a, vqmovn_s16(b))
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
@@ -15045,7 +15039,7 @@ pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
-    unsafe { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vqmovn_s32(b))
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
@@ -15054,7 +15048,7 @@ pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
-    unsafe { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) }
+    vcombine_s32(a, vqmovn_s64(b))
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
@@ -15063,13 +15057,7 @@ pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqmovn_u16(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vqmovn_u16(b))
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
@@ -15078,7 +15066,7 @@ pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
-    unsafe { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vqmovn_u32(b))
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
@@ -15087,7 +15075,7 @@ pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
-    unsafe { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vqmovn_u64(b))
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"]
@@ -15164,13 +15152,7 @@ pub fn vqmovns_u32(a: u32) -> u16 {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqmovun_s16(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vqmovun_s16(b))
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
@@ -15179,7 +15161,7 @@ pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
-    unsafe { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vqmovun_s32(b))
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
@@ -15188,7 +15170,7 @@ pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
 #[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
-    unsafe { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vqmovun_s64(b))
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 11ba7c955d..cb20ff24d2 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -7416,11 +7416,11 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int8x16_t]
+      - [int16x4_t, int32x4_t, int16x8_t]
+      - [int32x2_t, int64x2_t, int32x4_t]
     compose:
-      - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}]]
 
   - name: "vqmovn_high{neon_type[1].noq}"
     doc: "Signed saturating extract narrow"
@@ -7431,11 +7431,11 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]']
+      - [uint8x8_t, uint16x8_t, uint8x16_t]
+      - [uint16x4_t, uint32x4_t, uint16x8_t]
+      - [uint32x2_t, uint64x2_t, uint32x4_t]
     compose:
-      - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}]]
 
   - name: "vqmovn{type[2]}"
     doc: "Saturating extract narrow"
@@ -7523,11 +7523,11 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [uint8x8_t, int16x8_t, uint8x16_t, s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, int32x4_t, uint16x8_t, s32, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, int64x2_t, uint32x4_t, s64, '[0, 1, 2, 3]']
+      - [uint8x8_t, int16x8_t, uint8x16_t, s16]
+      - [uint16x4_t, int32x4_t, uint16x8_t, s32]
+      - [uint32x2_t, int64x2_t, uint32x4_t, s64]
     compose:
-      - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovun_{type[3]}", [b]]}, "{type[4]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovun_{type[3]}", [b]]}]]
 
   - name: "vqrdmulh{type[1]}"
     doc: "Signed saturating rounding doubling multiply returning high half"

From f1156d8f34d6f7ee8bf9fb7e58ceedef38640c0e Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 05:15:21 +0530
Subject: [PATCH 307/326] Change implementation of `vqrdml{a,s}h_lane`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 96 +++++++------------
 .../spec/neon/aarch64.spec.yml                | 36 +++----
 2 files changed, 50 insertions(+), 82 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 60a9e99a3b..112c84036f 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -15276,10 +15276,8 @@ pub fn vqnegd_s64(a: i64) -> i64 {
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlah_s16(a, b, c)
-    }
+    let c = vdup_lane_s16::<LANE>(c);
+    vqrdmlah_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"]
@@ -15290,10 +15288,8 @@ pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
-        vqrdmlah_s32(a, b, c)
-    }
+    let c = vdup_lane_s32::<LANE>(c);
+    vqrdmlah_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"]
@@ -15304,10 +15300,8 @@ pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlah_s16(a, b, c)
-    }
+    let c = vdup_laneq_s16::<LANE>(c);
+    vqrdmlah_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"]
@@ -15318,10 +15312,8 @@ pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
-        vqrdmlah_s32(a, b, c)
-    }
+    let c = vdup_laneq_s32::<LANE>(c);
+    vqrdmlah_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"]
@@ -15332,10 +15324,8 @@ pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
-        vqrdmlahq_s16(a, b, c)
-    }
+    let c = vdupq_lane_s16::<LANE>(c);
+    vqrdmlahq_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"]
@@ -15346,10 +15336,8 @@ pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlahq_s32(a, b, c)
-    }
+    let c = vdupq_lane_s32::<LANE>(c);
+    vqrdmlahq_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"]
@@ -15360,10 +15348,8 @@ pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
-        vqrdmlahq_s16(a, b, c)
-    }
+    let c = vdupq_laneq_s16::<LANE>(c);
+    vqrdmlahq_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"]
@@ -15374,10 +15360,8 @@ pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlahq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlahq_s32(a, b, c)
-    }
+    let c = vdupq_laneq_s32::<LANE>(c);
+    vqrdmlahq_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"]
@@ -15520,10 +15504,8 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlsh_s16(a, b, c)
-    }
+    let c = vdup_lane_s16::<LANE>(c);
+    vqrdmlsh_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"]
@@ -15534,10 +15516,8 @@ pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
-        vqrdmlsh_s32(a, b, c)
-    }
+    let c = vdup_lane_s32::<LANE>(c);
+    vqrdmlsh_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"]
@@ -15548,10 +15528,8 @@ pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlsh_s16(a, b, c)
-    }
+    let c = vdup_laneq_s16::<LANE>(c);
+    vqrdmlsh_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"]
@@ -15562,10 +15540,8 @@ pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]);
-        vqrdmlsh_s32(a, b, c)
-    }
+    let c = vdup_laneq_s32::<LANE>(c);
+    vqrdmlsh_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"]
@@ -15576,10 +15552,8 @@ pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
-        vqrdmlshq_s16(a, b, c)
-    }
+    let c = vdupq_lane_s16::<LANE>(c);
+    vqrdmlshq_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"]
@@ -15590,10 +15564,8 @@ pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlshq_s32(a, b, c)
-    }
+    let c = vdupq_lane_s32::<LANE>(c);
+    vqrdmlshq_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"]
@@ -15604,10 +15576,8 @@ pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]);
-        vqrdmlshq_s16(a, b, c)
-    }
+    let c = vdupq_laneq_s16::<LANE>(c);
+    vqrdmlshq_s16(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"]
@@ -15618,10 +15588,8 @@ pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
 pub fn vqrdmlshq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]);
-        vqrdmlshq_s32(a, b, c)
-    }
+    let c = vdupq_laneq_s32::<LANE>(c);
+    vqrdmlshq_s32(a, b, c)
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index cb20ff24d2..a805fbd205 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -7613,17 +7613,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]']
-      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]']
-      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
-      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]']
-      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]']
-      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
+      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2']
+      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3']
+      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2']
+      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3']
+      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1']
+      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2']
+      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1']
+      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']]
-      - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}]
+      - Let: [c, {FnCall: ['vdup{type[0]}', [c], [LANE]]}]
       - FnCall: ["vqrdmlah{neon_type[2].no}", [a, b, c]]
 
   - name: "vqrdmlah{type[4]}"
@@ -7697,17 +7697,17 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]']
-      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]']
-      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]']
-      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]']
-      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]']
-      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]']
-      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]']
-      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]']
+      - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2']
+      - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3']
+      - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2']
+      - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3']
+      - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1']
+      - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2']
+      - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1']
+      - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']]
-      - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}]
+      - Let: [c, {FnCall: ['vdup{type[0]}', [c], [LANE]]}]
       - FnCall: ["vqrdmlsh{neon_type[2].no}", [a, b, c]]
 
   - name: "vqrdmlsh{type[3]}"

From 705c2c84cfe74fb9599c16bd3b5b698629be25e9 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 05:49:07 +0530
Subject: [PATCH 308/326] Change implementation of `v{q}{r}shr{u}n_high_n`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 156 +++++-------------
 .../spec/neon/aarch64.spec.yml                | 111 ++++++-------
 2 files changed, 94 insertions(+), 173 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 112c84036f..1cbac3e284 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -15902,13 +15902,7 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqrshrn_n_s16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_s8(a, vqrshrn_n_s16::<N>(b))
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
@@ -15919,7 +15913,7 @@ pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vqrshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vqrshrn_n_s32::<N>(b))
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
@@ -15930,7 +15924,7 @@ pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vqrshrn_n_s64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_s32(a, vqrshrn_n_s64::<N>(b))
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
@@ -15941,13 +15935,7 @@ pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqrshrn_n_u16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vqrshrn_n_u16::<N>(b))
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
@@ -15958,7 +15946,7 @@ pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vqrshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vqrshrn_n_u32::<N>(b))
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
@@ -15969,7 +15957,7 @@ pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vqrshrn_n_u64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vqrshrn_n_u64::<N>(b))
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"]
@@ -16052,13 +16040,7 @@ pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqrshrun_n_s16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vqrshrun_n_s16::<N>(b))
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
@@ -16069,7 +16051,7 @@ pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vqrshrun_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vqrshrun_n_s32::<N>(b))
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
@@ -16080,7 +16062,7 @@ pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vqrshrun_n_s64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vqrshrun_n_s64::<N>(b))
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"]
@@ -16351,13 +16333,7 @@ pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqshrn_n_s16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_s8(a, vqshrn_n_s16::<N>(b))
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
@@ -16368,7 +16344,7 @@ pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vqshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vqshrn_n_s32::<N>(b))
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
@@ -16379,7 +16355,7 @@ pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vqshrn_n_s64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_s32(a, vqshrn_n_s64::<N>(b))
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
@@ -16390,13 +16366,7 @@ pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqshrn_n_u16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vqshrn_n_u16::<N>(b))
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
@@ -16407,7 +16377,7 @@ pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vqshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vqshrn_n_u32::<N>(b))
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
@@ -16418,7 +16388,7 @@ pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vqshrn_n_u64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vqshrn_n_u64::<N>(b))
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"]
@@ -16509,13 +16479,7 @@ pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vqshrun_n_s16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vqshrun_n_s16::<N>(b))
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
@@ -16526,7 +16490,7 @@ pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vqshrun_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vqshrun_n_s32::<N>(b))
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
@@ -16537,7 +16501,7 @@ pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vqshrun_n_s64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vqshrun_n_s64::<N>(b))
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"]
@@ -20128,13 +20092,7 @@ pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vrshrn_n_s16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_s8(a, vrshrn_n_s16::<N>(b))
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
@@ -20145,7 +20103,7 @@ pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vrshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vrshrn_n_s32::<N>(b))
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
@@ -20156,7 +20114,7 @@ pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vrshrn_n_s64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_s32(a, vrshrn_n_s64::<N>(b))
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
@@ -20167,13 +20125,7 @@ pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vrshrn_n_u16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vrshrn_n_u16::<N>(b))
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
@@ -20184,7 +20136,7 @@ pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vrshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vrshrn_n_u32::<N>(b))
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
@@ -20195,7 +20147,7 @@ pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vrshrn_n_u64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vrshrn_n_u64::<N>(b))
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"]
@@ -20708,10 +20660,8 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
     static_assert!(N >= 0 && N <= 8);
-    unsafe {
-        let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vshll_n_s8::<N>(b)
-    }
+    let b = vget_high_s8(a);
+    vshll_n_s8::<N>(b)
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
@@ -20722,10 +20672,8 @@ pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
     static_assert!(N >= 0 && N <= 16);
-    unsafe {
-        let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        vshll_n_s16::<N>(b)
-    }
+    let b = vget_high_s16(a);
+    vshll_n_s16::<N>(b)
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
@@ -20736,10 +20684,8 @@ pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
     static_assert!(N >= 0 && N <= 32);
-    unsafe {
-        let b: int32x2_t = simd_shuffle!(a, a, [2, 3]);
-        vshll_n_s32::<N>(b)
-    }
+    let b = vget_high_s32(a);
+    vshll_n_s32::<N>(b)
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
@@ -20750,10 +20696,8 @@ pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
     static_assert!(N >= 0 && N <= 8);
-    unsafe {
-        let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
-        vshll_n_u8::<N>(b)
-    }
+    let b: uint8x8_t = vget_high_u8(a);
+    vshll_n_u8::<N>(b)
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
@@ -20764,10 +20708,8 @@ pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
     static_assert!(N >= 0 && N <= 16);
-    unsafe {
-        let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
-        vshll_n_u16::<N>(b)
-    }
+    let b: uint16x4_t = vget_high_u16(a);
+    vshll_n_u16::<N>(b)
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
@@ -20778,10 +20720,8 @@ pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
     static_assert!(N >= 0 && N <= 32);
-    unsafe {
-        let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
-        vshll_n_u32::<N>(b)
-    }
+    let b: uint32x2_t = vget_high_u32(a);
+    vshll_n_u32::<N>(b)
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
@@ -20792,13 +20732,7 @@ pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vshrn_n_s16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_s8(a, vshrn_n_s16::<N>(b))
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
@@ -20809,7 +20743,7 @@ pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vshrn_n_s32::<N>(b))
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
@@ -20820,7 +20754,7 @@ pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vshrn_n_s64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_s32(a, vshrn_n_s64::<N>(b))
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
@@ -20831,13 +20765,7 @@ pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
     static_assert!(N >= 1 && N <= 8);
-    unsafe {
-        simd_shuffle!(
-            a,
-            vshrn_n_u16::<N>(b),
-            [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
-        )
-    }
+    vcombine_u8(a, vshrn_n_u16::<N>(b))
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
@@ -20848,7 +20776,7 @@ pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
     static_assert!(N >= 1 && N <= 16);
-    unsafe { simd_shuffle!(a, vshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vshrn_n_u32::<N>(b))
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
@@ -20859,7 +20787,7 @@ pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
     static_assert!(N >= 1 && N <= 32);
-    unsafe { simd_shuffle!(a, vshrn_n_u64::<N>(b), [0, 1, 2, 3]) }
+    vcombine_u32(a, vshrn_n_u64::<N>(b))
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a805fbd205..f6705033f9 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -7828,12 +7828,12 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', 'N >= 1 && N <= 8']
-      - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', '[0, 1, 2, 3, 4, 5, 6, 7]', 'N >= 1 && N <= 16']
-      - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', '[0, 1, 2, 3]', 'N >= 1 && N <= 32']
+      - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', 'N >= 1 && N <= 8']
+      - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', 'N >= 1 && N <= 16']
+      - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', 'N >= 1 && N <= 32']
     compose:
-      - FnCall: [static_assert!, ["{type[5]}"]]
-      - FnCall: [simd_shuffle!, [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::<N>", [b]]}, "{type[4]}"]]
+      - FnCall: [static_assert!, ["{type[4]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::<N>", [b]]}]]
 
   - name: "vqrshrn{type[0]}"
     doc: "Unsigned saturating rounded shift right narrow"
@@ -7865,18 +7865,17 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
+      - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8']
+      - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16']
+      - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ['{type[3]}']]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[0]}'
           - - a
             - FnCall:
                 - "vqrshrn_n{neon_type[1].noq}::<N>"
                 - - b
-            - "{type[4]}"
 
   - name: "vqrshrun{type[0]}"
     doc: "Signed saturating rounded shift right unsigned narrow"
@@ -7916,18 +7915,17 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', s32, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', s64, '[0, 1, 2, 3]']
+      - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8']
+      - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16']
+      - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[0]}'
           - - a
             - FnCall:
-                - "vqrshrun_n_{type[4]}::<N>"
+                - "vqrshrun_n_{neon_type[1]}::<N>"
                 - - b
-            - "{type[5]}"
 
   - name: "vqshld_{type}"
     doc: "Signed saturating shift left"
@@ -8110,16 +8108,15 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', s16]
-      - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]', s32]
-      - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]', s64]
+      - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8']
+      - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16']
+      - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[4]}"]]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[1]}'
           - - a
-            - FnCall: ["vqshrn_n_{type[6]}::<N>", [b]]
-            - "{type[5]}"
+            - FnCall: ["vqshrn_n_{neon_type[2]}::<N>", [b]]
 
   - name: "vqshrnd_n_u64"
     doc: "Unsigned saturating shift right narrow"
@@ -8178,16 +8175,15 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
+      - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8']
+      - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16']
+      - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[4]}"]]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[1]}'
           - - a
             - FnCall: ["vqshrn_n_{neon_type[2]}::<N>", [b]]
-            - "{type[5]}"
 
   - name: "vqshrun{type[0]}"
     doc: "Signed saturating shift right unsigned narrow"
@@ -8223,16 +8219,15 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
+      - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8']
+      - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16']
+      - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[0]}'
           - - a
             - FnCall: ["vqshrun_n_{neon_type[1]}::<N>", [b]]
-            - "{type[4]}"
 
   - name: "vsqadd{type[0]}"
     doc: "Unsigned saturating accumulate of signed value"
@@ -8699,19 +8694,18 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
-      - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8']
+      - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16']
+      - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32']
+      - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8']
+      - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16']
+      - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[0]}'
           - - a
             - FnCall: ["vrshrn_n_{neon_type[1]}::<N>", [b]]
-            - "{type[4]}"
 
   - name: "vrsubhn_high_{neon_type[1]}"
     doc: "Rounding subtract returning high narrow"
@@ -9033,13 +9027,13 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]']
-      - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32', '[2, 3]']
+      - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8']
+      - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16']
+      - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
-      - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}]
-      - FnCall: ["vshll_n_{neon_type[2]}::<N>", [b]]
+      - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - FnCall: ["vshll_n_{neon_type[2]}", [b], [N]]
 
   - name: "vshll_high_n_{neon_type[0]}"
     doc: "Signed shift left long"
@@ -9052,13 +9046,13 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]']
-      - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32', '[2, 3]']
+      - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8']
+      - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16']
+      - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
-      - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}]
-      - FnCall: ["vshll_n_{neon_type[2]}::<N>", [b]]
+      - Let: [b, "{neon_type[2]}", {FnCall: ['vget_high_{neon_type[0]}', [a]]}]
+      - FnCall: ["vshll_n_{neon_type[2]}", [b], [N]]
 
   - name: "vshrn_high_n_{neon_type[1]}"
     doc: "Shift right narrow"
@@ -9071,19 +9065,18 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
-      - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8']
+      - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16']
+      - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32']
+      - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8']
+      - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16']
+      - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32']
     compose:
       - FnCall: [static_assert!, ["{type[3]}"]]
       - FnCall:
-          - simd_shuffle!
+          - 'vcombine_{neon_type[0]}'
           - - a
-            - FnCall: ["vshrn_n_{neon_type[1]}::<N>", [b]]
-            - "{type[4]}"
+            - FnCall: ["vshrn_n_{neon_type[1]}", [b], [N]]
 
   - name: "vsm3partw1{neon_type.no}"
     doc: "SM3PARTW1"

From 8c61739f310109f138688c2ea57ba5221b699450 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 05:53:35 +0530
Subject: [PATCH 309/326] Change implementation of `vr{add,sub}hn_high`

---
 .../core_arch/src/aarch64/neon/generated.rs   | 36 +++++---------
 .../src/arm_shared/neon/generated.rs          | 48 +++++++++----------
 .../spec/neon/aarch64.spec.yml                | 36 ++++++--------
 .../spec/neon/arm_shared.spec.yml             | 45 +++++++++--------
 4 files changed, 72 insertions(+), 93 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 1cbac3e284..d09171a753 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -20343,8 +20343,7 @@ pub fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 #[cfg_attr(test, assert_instr(rsubhn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
-    let x: int8x8_t = vrsubhn_s16(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    vcombine_s8(a, vrsubhn_s16(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
@@ -20354,8 +20353,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 #[cfg_attr(test, assert_instr(rsubhn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
-    let x: int16x4_t = vrsubhn_s32(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vrsubhn_s32(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
@@ -20365,8 +20363,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 #[cfg_attr(test, assert_instr(rsubhn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
-    let x: int32x2_t = vrsubhn_s64(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
+    vcombine_s32(a, vrsubhn_s64(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
@@ -20376,8 +20373,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 #[cfg_attr(test, assert_instr(rsubhn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
-    let x: uint8x8_t = vrsubhn_u16(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    vcombine_u8(a, vrsubhn_u16(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
@@ -20387,8 +20383,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 #[cfg_attr(test, assert_instr(rsubhn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
-    let x: uint16x4_t = vrsubhn_u32(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vrsubhn_u32(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
@@ -20398,8 +20393,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 #[cfg_attr(test, assert_instr(rsubhn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
-    let x: uint32x2_t = vrsubhn_u64(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
+    vcombine_u32(a, vrsubhn_u64(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
@@ -20409,8 +20403,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 #[cfg_attr(test, assert_instr(rsubhn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
-    let x: int8x8_t = vrsubhn_s16(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    vcombine_s8(a, vrsubhn_s16(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
@@ -20420,8 +20413,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 #[cfg_attr(test, assert_instr(rsubhn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
-    let x: int16x4_t = vrsubhn_s32(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, vrsubhn_s32(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
@@ -20431,8 +20423,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 #[cfg_attr(test, assert_instr(rsubhn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
-    let x: int32x2_t = vrsubhn_s64(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
+    vcombine_s32(a, vrsubhn_s64(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
@@ -20442,8 +20433,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 #[cfg_attr(test, assert_instr(rsubhn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
-    let x: uint8x8_t = vrsubhn_u16(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    vcombine_u8(a, vrsubhn_u16(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
@@ -20453,8 +20443,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 #[cfg_attr(test, assert_instr(rsubhn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
-    let x: uint16x4_t = vrsubhn_u32(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_u16(a, vrsubhn_u32(b, c))
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
@@ -20464,8 +20453,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 #[cfg_attr(test, assert_instr(rsubhn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
-    let x: uint32x2_t = vrsubhn_u64(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
+    vcombine_u32(a, vrsubhn_u64(b, c))
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 3f5b7073e2..6c0dd2af94 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -2207,7 +2207,7 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 {
 pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
     unsafe {
         let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8)));
-        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
+        vcombine_s8(r, x)
     }
 }
 #[doc = "Add returning High Narrow (high half)."]
@@ -2235,7 +2235,7 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
 pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
     unsafe {
         let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16)));
-        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
+        vcombine_s16(r, x)
     }
 }
 #[doc = "Add returning High Narrow (high half)."]
@@ -2263,7 +2263,7 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
 pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
     unsafe {
         let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32)));
-        simd_shuffle!(r, x, [0, 1, 2, 3])
+        vcombine_s32(r, x)
     }
 }
 #[doc = "Add returning High Narrow (high half)."]
@@ -2291,7 +2291,7 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
 pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t {
     unsafe {
         let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8)));
-        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
+        vcombine_u8(r, x)
     }
 }
 #[doc = "Add returning High Narrow (high half)."]
@@ -2319,7 +2319,7 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t
 pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t {
     unsafe {
         let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16)));
-        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
+        vcombine_u16(r, x)
     }
 }
 #[doc = "Add returning High Narrow (high half)."]
@@ -2347,7 +2347,7 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_
 pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t {
     unsafe {
         let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32)));
-        simd_shuffle!(r, x, [0, 1, 2, 3])
+        vcombine_u32(r, x)
     }
 }
 #[doc = "Add returning High Narrow."]
@@ -38521,7 +38521,7 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 )]
 pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
     let x = vraddhn_s16(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    vcombine_s8(a, x)
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
@@ -38547,7 +38547,7 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 )]
 pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
     let x = vraddhn_s32(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    vcombine_s16(a, x)
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
@@ -38573,7 +38573,7 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 )]
 pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
     let x = vraddhn_s64(b, c);
-    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
+    vcombine_s32(a, x)
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
@@ -38600,7 +38600,7 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
     unsafe {
         let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c)));
-        simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
+        vcombine_u8(a, x)
     }
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
@@ -38628,7 +38628,7 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
     unsafe {
         let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c)));
-        simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7])
+        vcombine_u16(a, x)
     }
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
@@ -38656,7 +38656,7 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
     unsafe {
         let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c)));
-        simd_shuffle!(a, x, [0, 1, 2, 3])
+        vcombine_u32(a, x)
     }
 }
 #[doc = "Rounding Add returning High Narrow."]
@@ -69225,8 +69225,8 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
-    let d: int8x8_t = vsubhn_s16(b, c);
-    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    let d = vsubhn_s16(b, c);
+    vcombine_s8(a, d)
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
@@ -69251,8 +69251,8 @@ pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
-    let d: int16x4_t = vsubhn_s32(b, c);
-    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    let d = vsubhn_s32(b, c);
+    vcombine_s16(a, d)
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
@@ -69277,8 +69277,8 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
-    let d: int32x2_t = vsubhn_s64(b, c);
-    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
+    let d = vsubhn_s64(b, c);
+    vcombine_s32(a, d)
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
@@ -69303,8 +69303,8 @@ pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
-    let d: uint8x8_t = vsubhn_u16(b, c);
-    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
+    let d = vsubhn_u16(b, c);
+    vcombine_u8(a, d)
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
@@ -69329,8 +69329,8 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
-    let d: uint16x4_t = vsubhn_u32(b, c);
-    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
+    let d = vsubhn_u32(b, c);
+    vcombine_u16(a, d)
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
@@ -69355,8 +69355,8 @@ pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
-    let d: uint32x2_t = vsubhn_u64(b, c);
-    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
+    let d = vsubhn_u64(b, c);
+    vcombine_u32(a, d)
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index f6705033f9..912eff7ce4 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -8717,18 +8717,14 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]']
-      - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int16x8_t, int8x16_t]
+      - [int16x4_t, int32x4_t, int32x4_t, int16x8_t]
+      - [int32x2_t, int64x2_t, int64x2_t, int32x4_t]
+      - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t]
+      - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t]
+      - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t]
     compose:
-      - Let:
-          - x
-          - "{neon_type[0]}"
-          - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]
-      - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]}]]
 
   - name: "vrsubhn_high_{neon_type[1]}"
     doc: "Rounding subtract returning high narrow"
@@ -8740,18 +8736,14 @@ intrinsics:
       - *neon-stable
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]']
-      - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int16x8_t, int8x16_t]
+      - [int16x4_t, int32x4_t, int32x4_t, int16x8_t]
+      - [int32x2_t, int64x2_t, int64x2_t, int32x4_t]
+      - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t]
+      - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t]
+      - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t]
     compose:
-      - Let:
-          - x
-          - "{neon_type[0]}"
-          - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]
-      - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]}]]
 
   - name: "vcopy{neon_type[0].lane_nox}"
     doc: "Insert vector element from another vector element"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index e646d22369..f22f503c56 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6805,18 +6805,17 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]']
-      - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]']
+      - [int8x8_t, int16x8_t, int8x16_t]
+      - [int16x4_t, int32x4_t, int16x8_t]
+      - [int32x2_t, int64x2_t, int32x4_t]
+      - [uint8x8_t, uint16x8_t, uint8x16_t]
+      - [uint16x4_t, uint32x4_t, uint16x8_t]
+      - [uint32x2_t, uint64x2_t, uint32x4_t]
     compose:
       - Let:
           - d
-          - "{neon_type[0]}"
           - FnCall: ["vsubhn{neon_type[1].noq}", [b, c]]
-      - FnCall: [simd_shuffle!, [a, d, "{type[3]}"]]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, d]]
 
   - name: "vhsub{neon_type[1].no}"
     doc: "Signed halving subtract"
@@ -13225,9 +13224,9 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t, '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [uint32x2_t, uint64x2_t, uint32x4_t, 'vraddhn.i64', int64x2_t, '[0, 1, 2, 3]']
+      - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t]
+      - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t]
+      - [uint32x2_t, uint64x2_t, uint32x4_t, 'vraddhn.i64', int64x2_t]
     compose:
       - Let:
           - x
@@ -13238,7 +13237,7 @@ intrinsics:
                     - "vraddhn{neon_type[4].noq}"
                     - - FnCall: [transmute, [b]]
                       - FnCall: [transmute, [c]]
-      - FnCall: ["simd_shuffle!", [a, x, '{type[5]}']]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, x]]
 
   - name: "vraddhn_high{neon_type[1].noq}"
     doc: "Rounding Add returning High Narrow (high half)."
@@ -13252,9 +13251,9 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - [int32x2_t, int64x2_t, int32x4_t, 'vraddhn.i64', '[0, 1, 2, 3]']
+      - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16']
+      - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32']
+      - [int32x2_t, int64x2_t, int32x4_t, 'vraddhn.i64']
     compose:
       - Let:
           - x
@@ -13262,7 +13261,7 @@ intrinsics:
               - "vraddhn{neon_type[1].noq}"
               - - b
                 - c
-      - FnCall: ["simd_shuffle!", [a, x, '{type[4]}']]
+      - FnCall: ['vcombine_{neon_type[0]}', [a, x]]
 
   - name: "vpadd{neon_type.no}"
     doc: "Add pairwise."
@@ -14591,12 +14590,12 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - ['vaddhn_high_s16', 'int8x8_t', 'int16x8_t', 'int8x16_t', 'int16x8_t::splat(8)', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - ['vaddhn_high_s32', 'int16x4_t', 'int32x4_t', 'int16x8_t', 'int32x4_t::splat(16)', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - ['vaddhn_high_s64', 'int32x2_t', 'int64x2_t', 'int32x4_t', 'int64x2_t::splat(32)', '[0, 1, 2, 3]']
-      - ['vaddhn_high_u16', 'uint8x8_t', 'uint16x8_t', 'uint8x16_t', 'uint16x8_t::splat(8)', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
-      - ['vaddhn_high_u32', 'uint16x4_t', 'uint32x4_t', 'uint16x8_t', 'uint32x4_t::splat(16)', '[0, 1, 2, 3, 4, 5, 6, 7]']
-      - ['vaddhn_high_u64', 'uint32x2_t', 'uint64x2_t', 'uint32x4_t', 'uint64x2_t::splat(32)', '[0, 1, 2, 3]']
+      - ['vaddhn_high_s16', 'int8x8_t', 'int16x8_t', 'int8x16_t', 'int16x8_t::splat(8)']
+      - ['vaddhn_high_s32', 'int16x4_t', 'int32x4_t', 'int16x8_t', 'int32x4_t::splat(16)']
+      - ['vaddhn_high_s64', 'int32x2_t', 'int64x2_t', 'int32x4_t', 'int64x2_t::splat(32)']
+      - ['vaddhn_high_u16', 'uint8x8_t', 'uint16x8_t', 'uint8x16_t', 'uint16x8_t::splat(8)']
+      - ['vaddhn_high_u32', 'uint16x4_t', 'uint32x4_t', 'uint16x8_t', 'uint32x4_t::splat(16)']
+      - ['vaddhn_high_u64', 'uint32x2_t', 'uint64x2_t', 'uint32x4_t', 'uint64x2_t::splat(32)']
     compose:
       - Let:
         - x
@@ -14609,7 +14608,7 @@ intrinsics:
                   - - a
                     - b
                 - '{type[4]}'
-      - FnCall: ['simd_shuffle!', [r, x, '{type[5]}']]
+      - FnCall: ['vcombine_{neon_type[1]}', [r, x]]
 
   - name: "{type[0]}"
     doc: "Vector narrow integer."

From 89168fa1f4d81d48c7431185d97caadaf616b828 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 06:10:10 +0530
Subject: [PATCH 310/326] Change implementation of `vmul_lane`

---
 .../core_arch/src/aarch64/neon/generated.rs   |   8 +-
 .../src/arm_shared/neon/generated.rs          | 189 ++----------------
 .../spec/neon/aarch64.spec.yml                |  10 +-
 .../spec/neon/arm_shared.spec.yml             |  52 ++---
 4 files changed, 57 insertions(+), 202 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index d09171a753..63ffa6765c 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -12591,7 +12591,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 4])) }
+    unsafe { simd_mul(a, vdup_laneq_f16::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"]
@@ -12603,7 +12603,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 8])) }
+    unsafe { simd_mul(a, vdupq_laneq_f16::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"]
@@ -12917,7 +12917,7 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t {
     static_assert!(LANE == 0);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
+    unsafe { simd_mul(a, vdupq_lane_f64::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"]
@@ -12928,7 +12928,7 @@ pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float6
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) }
+    unsafe { simd_mul(a, vdupq_laneq_f64::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 6c0dd2af94..2e3a24ee95 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -29763,12 +29763,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdup_lane_f16::<LANE>(v)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
@@ -29792,25 +29787,7 @@ pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16
 #[cfg(not(target_arch = "arm64ec"))]
 pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(
-                v,
-                v,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_lane_f16::<LANE>(v)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
@@ -29833,7 +29810,7 @@ pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float1
 )]
 pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, vdup_lane_f32::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
@@ -29856,7 +29833,7 @@ pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32
 )]
 pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, vdup_laneq_f32::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
@@ -29879,12 +29856,7 @@ pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float3
 )]
 pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_lane_f32::<LANE>(b)) }
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
@@ -29907,12 +29879,7 @@ pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float3
 )]
 pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_laneq_f32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
@@ -29935,12 +29902,7 @@ pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float
 )]
 pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdup_lane_s16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
@@ -29963,25 +29925,7 @@ pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 )]
 pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_lane_s16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
@@ -30004,7 +29948,7 @@ pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t
 )]
 pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, vdup_lane_s32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
@@ -30027,12 +29971,7 @@ pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 )]
 pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_lane_s32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
@@ -30055,12 +29994,7 @@ pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t
 )]
 pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdup_lane_u16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
@@ -30083,25 +30017,7 @@ pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_
 )]
 pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_lane_u16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
@@ -30124,7 +30040,7 @@ pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8
 )]
 pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, vdup_lane_u32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
@@ -30147,12 +30063,7 @@ pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_
 )]
 pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_lane_u32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
@@ -30175,12 +30086,7 @@ pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4
 )]
 pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdup_laneq_s16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
@@ -30203,25 +30109,7 @@ pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t
 )]
 pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_laneq_s16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
@@ -30244,7 +30132,7 @@ pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t
 )]
 pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, vdup_laneq_s32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
@@ -30267,12 +30155,7 @@ pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t
 )]
 pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_laneq_s32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
@@ -30295,12 +30178,7 @@ pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t
 )]
 pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdup_laneq_u16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
@@ -30323,25 +30201,7 @@ pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4
 )]
 pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     static_assert_uimm_bits!(LANE, 3);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(
-                b,
-                b,
-                [
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32,
-                    LANE as u32
-                ]
-            ),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_laneq_u16::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
@@ -30364,7 +30224,7 @@ pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x
 )]
 pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
+    unsafe { simd_mul(a, vdup_laneq_u32::<LANE>(b)) }
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
@@ -30387,12 +30247,7 @@ pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2
 )]
 pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        simd_mul(
-            a,
-            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
-        )
-    }
+    unsafe { simd_mul(a, vdupq_laneq_u32::<LANE>(b)) }
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 912eff7ce4..7664bf3c10 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -11006,7 +11006,7 @@ intrinsics:
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32; 2]']]
+            - FnCall: [vdupq_lane_f64, [b], [LANE]]
 
   - name: "vmuld_lane_f64"
     doc: "Floating-point multiply"
@@ -11063,7 +11063,7 @@ intrinsics:
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: [simd_shuffle!, [b, b, '[LANE as u32; 2]']]
+            - FnCall: [vdupq_laneq_f64, [b], [LANE]]
 
 
   # vmulq_laneq_f16
@@ -11080,14 +11080,14 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float16x4_t, float16x8_t, '_lane', "[LANE as u32; 4]"]
-      - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32; 8]"]
+      - [float16x4_t, float16x8_t, '_lane']
+      - [float16x8_t, float16x8_t, 'q_lane']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '3']]
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]
+            - FnCall: ['vdup{neon_type[0].laneq_nox}', [b], [LANE]]
 
 
   - name: "vmul{type[1]}_{type[0]}"
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index f22f503c56..d20c94a2f8 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6300,20 +6300,20 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int16x4_t, int16x4_t, '2']
+      - [int16x8_t, int16x4_t, '2']
+      - [int32x2_t, int32x2_t, '1']
+      - [int32x4_t, int32x2_t, '1']
+      - [uint16x4_t, uint16x4_t, '2']
+      - [uint16x8_t, uint16x4_t, '2']
+      - [uint32x2_t, uint32x2_t, '1']
+      - [uint32x4_t, uint32x2_t, '1']
     compose:
       - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]]
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]]
+            - FnCall: ["vdup{neon_type[0].lane_nox}", [b], [LANE]]
 
 
   - name: "vmul{neon_type[0].lane_nox}"
@@ -6332,14 +6332,14 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [float16x8_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [float16x4_t, float16x4_t, '2']
+      - [float16x8_t, float16x4_t, '2']
     compose:
       - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]]
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: ["simd_shuffle!", [v, v, "{type[3]}"]]
+            - FnCall: ["vdup{neon_type[0].lane_nox}", [v], [LANE]]
 
 
   - name: "vmul{neon_type[0].laneq_nox}"
@@ -6356,20 +6356,20 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]']
-      - [uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [int16x4_t, int16x8_t, '3']
+      - [int16x8_t, int16x8_t, '3']
+      - [int32x2_t, int32x4_t, '2']
+      - [int32x4_t, int32x4_t, '2']
+      - [uint16x4_t, uint16x8_t, '3']
+      - [uint16x8_t, uint16x8_t, '3']
+      - [uint32x2_t, uint32x4_t, '2']
+      - [uint32x4_t, uint32x4_t, '2']
     compose:
       - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]]
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]]
+            - FnCall: ["vdup{neon_type[0].laneq_nox}", [b], [LANE]]
 
   - name: "vmull{neon_type[1].no}"
     doc: Signed multiply long
@@ -11204,16 +11204,16 @@ intrinsics:
     static_defs: ['const LANE: i32']
     safety: safe
     types:
-      - [float32x2_t, float32x2_t, '_lane_f32', '1', '[LANE as u32, LANE as u32]']
-      - [float32x2_t, float32x4_t, '_laneq_f32', '2', '[LANE as u32, LANE as u32]']
-      - [float32x4_t, float32x2_t, 'q_lane_f32', '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
-      - [float32x4_t, float32x4_t, 'q_laneq_f32', '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]']
+      - [float32x2_t, float32x2_t, '_lane_f32', '1']
+      - [float32x2_t, float32x4_t, '_laneq_f32', '2']
+      - [float32x4_t, float32x2_t, 'q_lane_f32', '1']
+      - [float32x4_t, float32x4_t, 'q_laneq_f32', '2']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall:
           - simd_mul
           - - a
-            - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]]
+            - FnCall: ['vdup{type[2]}', [b], [LANE]]
 
   - name: "vqrdmulh{type[0]}"
     doc: "Vector rounding saturating doubling multiply high by scalar"

From 5f676a53f584e6304985345791525fa06bb9130e Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 06:37:24 +0530
Subject: [PATCH 311/326] Change implementation of `vld1_dup`

---
 crates/core_arch/src/arm_shared/neon/generated.rs    |  8 ++++----
 crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml | 10 +++++-----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 2e3a24ee95..1d8484e47f 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -14634,8 +14634,8 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
-    let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
-    simd_shuffle!(x, x, [0, 0, 0, 0])
+    let x = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
+    vdup_lane_f16::<0>(x)
 }
 #[doc = "Load one single-element structure and replicate to all lanes of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
@@ -14653,8 +14653,8 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
-    let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
+    let x = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
+    vdupq_laneq_f16::<0>(x)
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index d20c94a2f8..61979ecf0f 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -2835,7 +2835,7 @@ intrinsics:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall: [simd_insert!, [src, "LANE as u32", "*ptr"]]
 
-  - name: "vld1{type[2]}_{neon_type[1]}"
+  - name: "vld1{neon_type[1].dup_nox}"
     doc: "Load one single-element structure and replicate to all lanes of one register"
     arguments: ["ptr: {type[0]}"]
     return_type: "{neon_type[1]}"
@@ -2849,11 +2849,11 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ["*const f16", float16x4_t, '_dup', 'f16x4', "[0, 0, 0, 0]"]
-      - ["*const f16", float16x8_t, 'q_dup', 'f16x8', "[0, 0, 0, 0, 0, 0, 0, 0]"]
+      - ["*const f16", float16x4_t, '_lane', 'f16x4']
+      - ["*const f16", float16x8_t, 'q_laneq', 'f16x8']
     compose:
-      - Let: [x, "{neon_type[1]}", "vld1{neon_type[1].lane_nox}::<0>(ptr, transmute({type[3]}::splat(0.0)))"]
-      - FnCall: [simd_shuffle!, [x, x, "{type[4]}"]]
+      - Let: [x, {FnCall: ["vld1{neon_type[1].lane_nox}", [ptr, {FnCall: [transmute, ["{type[3]}::splat(0.0)"]]}], [0]]}]
+      - FnCall: ['vdup{type[2]}_{neon_type[1]}', [x], [0]]
 
 
   - name: "vld2{neon_type[1].nox}"

From 962b1a603d5b3e96c233bd2429deba347a0dd783 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 07:01:28 +0530
Subject: [PATCH 312/326] Change implementation of `v{us,su,}dot_lane`

---
 .../src/arm_shared/neon/generated.rs          | 136 +++++++-----------
 .../spec/neon/arm_shared.spec.yml             |  96 ++++++-------
 2 files changed, 89 insertions(+), 143 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 1d8484e47f..476d8e78a2 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -9663,11 +9663,9 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 )]
 pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
+    let c = vreinterpret_s32_s8(c);
+    let c = vdup_lane_s32::<LANE>(c);
+    vdot_s32(a, b, vreinterpret_s8_s32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
@@ -9690,12 +9688,9 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 )]
 pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
+    let c = vreinterpret_s32_s8(c);
+    let c = vdupq_lane_s32::<LANE>(c);
+    vdotq_s32(a, b, vreinterpretq_s8_s32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
@@ -9718,11 +9713,9 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 )]
 pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, vreinterpret_u8_u32(c))
-    }
+    let c = vreinterpret_u32_u8(c);
+    let c = vdup_lane_u32::<LANE>(c);
+    vdot_u32(a, b, vreinterpret_u8_u32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
@@ -9745,12 +9738,9 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 )]
 pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
-    unsafe {
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
-    }
+    let c = vreinterpret_u32_u8(c);
+    let c = vdupq_lane_u32::<LANE>(c);
+    vdotq_u32(a, b, vreinterpretq_u8_u32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
@@ -9766,11 +9756,9 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
+    let c = vreinterpretq_s32_s8(c);
+    let c = vdup_laneq_s32::<LANE>(c);
+    vdot_s32(a, b, vreinterpret_s8_s32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
@@ -9786,12 +9774,9 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
+    let c = vreinterpretq_s32_s8(c);
+    let c = vdupq_laneq_s32::<LANE>(c);
+    vdotq_s32(a, b, vreinterpretq_s8_s32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
@@ -9807,11 +9792,9 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    let c: uint32x4_t = vreinterpretq_u32_u8(c);
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, transmute(c))
-    }
+    let c = vreinterpretq_u32_u8(c);
+    let c = vdup_laneq_u32::<LANE>(c);
+    vdot_u32(a, b, vreinterpret_u8_u32(c))
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
@@ -9827,12 +9810,9 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
 pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    let c: uint32x4_t = vreinterpretq_u32_u8(c);
-    unsafe {
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, transmute(c))
-    }
+    let c = vreinterpretq_u32_u8(c);
+    let c = vdupq_laneq_u32::<LANE>(c);
+    vdotq_u32(a, b, vreinterpretq_u8_u32(c))
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
@@ -69646,11 +69626,9 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 )]
 pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, vreinterpret_u8_u32(c), b)
-    }
+    let c = vreinterpret_u32_u8(c);
+    let c = vdup_lane_u32::<LANE>(c);
+    vusdot_s32(a, vreinterpret_u8_u32(c), b)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
@@ -69677,12 +69655,9 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 )]
 pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: uint32x2_t = vreinterpret_u32_u8(c);
-    unsafe {
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, vreinterpretq_u8_u32(c), b)
-    }
+    let c = vreinterpret_u32_u8(c);
+    let c = vdupq_lane_u32::<LANE>(c);
+    vusdotq_s32(a, vreinterpretq_u8_u32(c), b)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
@@ -69702,11 +69677,9 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, transmute(c), b)
-    }
+    let c = vreinterpretq_u32_u8(c);
+    let c = vdup_laneq_u32::<LANE>(c);
+    vusdot_s32(a, vreinterpret_u8_u32(c), b)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
@@ -69726,12 +69699,9 @@ pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, transmute(c), b)
-    }
+    let c = vreinterpretq_u32_u8(c);
+    let c = vdupq_laneq_u32::<LANE>(c);
+    vusdotq_s32(a, vreinterpretq_u8_u32(c), b)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
@@ -71633,11 +71603,9 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 )]
 pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
+    let c = vreinterpret_s32_s8(c);
+    let c = vdup_lane_s32::<LANE>(c);
+    vusdot_s32(a, b, vreinterpret_s8_s32(c))
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
@@ -71660,12 +71628,9 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 )]
 pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    let c: int32x2_t = vreinterpret_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
+    let c = vreinterpret_s32_s8(c);
+    let c = vdupq_lane_s32::<LANE>(c);
+    vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
@@ -71681,11 +71646,9 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x4_t = transmute(c);
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
+    let c = vreinterpretq_s32_s8(c);
+    let c = vdup_laneq_s32::<LANE>(c);
+    vusdot_s32(a, b, vreinterpret_s8_s32(c))
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
@@ -71701,12 +71664,9 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
 pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: int32x4_t = transmute(c);
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
+    let c = vreinterpretq_s32_s8(c);
+    let c = vdupq_laneq_s32::<LANE>(c);
+    vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 61979ecf0f..1f7e1f6987 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -6159,10 +6159,10 @@ intrinsics:
             - link: "llvm.arm.neon.usdot.v{neon_type[0].lane}i32.v{neon_type[1].lane}i8"
               arch: arm
 
-  - name: "vusdot{type[0]}"
+  - name: "vusdot{neon_type[0].lane_nox}"
     doc: "Dot product index form with unsigned and signed integers"
-    arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}", "c: int8x8_t"]
-    return_type: "{neon_type[1]}"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: int8x8_t"]
+    return_type: "{neon_type[0]}"
     attr:
       - *neon-i8mm
       - *neon-v8
@@ -6174,19 +6174,17 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]','']
-      - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+      - [int32x2_t, uint8x8_t, '']
+      - [int32x4_t, uint8x16_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
-          - int32x2_t
           - FnCall: ['vreinterpret_s32_s8', [c]]
       - Let:
           - c
-          - "{type[1]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
+          - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]]
+      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[2]}_s8_s32', [c]]}]]
 
   - name: "vsudot{neon_type[0].lane_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -6203,22 +6201,20 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t,'']
-      - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t,'q']
+      - [int32x2_t, int8x8_t, uint8x8_t, uint32x2_t, '']
+      - [int32x4_t, int8x16_t, uint8x8_t, uint32x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
-          - uint32x2_t
           - FnCall: ['vreinterpret_u32_u8', [c]]
       - Let:
           - c
-          - "{type[4]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+          - FnCall: ['vdup{neon_type[3].lane_nox}', [c], [LANE]]
       - FnCall: 
           - "vusdot{neon_type[0].no}"
           - - a
-            - FnCall: ['vreinterpret{type[5]}_u8_u32', [c]]
+            - FnCall: ['vreinterpret{type[4]}_u8_u32', [c]]
             - b
 
   - name: "vmul{neon_type[1].no}"
@@ -6979,13 +6975,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]','']
-      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+      - [int32x2_t, uint8x8_t, int8x16_t, '']
+      - [int32x4_t, uint8x16_t, int8x16_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}]
-      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] 
+      - Let: [c, {FnCall: [vreinterpretq_s32_s8, [c]]}]
+      - Let: [c, {FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]]}]
+      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[3]}_s8_s32', [c]]}]] 
 
   - name: "vsudot{neon_type[0].laneq_nox}"
     doc: "Dot product index form with signed and unsigned integers"
@@ -7001,22 +6997,20 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t]
-      - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t]
+      - [int32x2_t, int8x8_t, uint8x16_t, uint32x2_t, '']
+      - [int32x4_t, int8x16_t, uint8x16_t, uint32x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
       - Let:
           - c
-          - uint32x4_t
-          - FnCall: [transmute, [c]]
+          - FnCall: [vreinterpretq_u32_u8, [c]]
       - Let:
           - c
-          - "{type[4]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+          - FnCall: ['vdup{neon_type[3].laneq_nox}', [c], [LANE]]
       - FnCall: 
           - "vusdot{neon_type[0].no}"
           - - a
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[4]}_u8_u32', [c]]
             - b
 
   - name: "vdot{neon_type[0].laneq_nox}"
@@ -7033,23 +7027,21 @@ intrinsics:
       - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', '']
-      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+      - [int32x2_t, int8x8_t, int8x16_t, '']
+      - [int32x4_t, int8x16_t, int8x16_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
       - Let:
           - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: [vreinterpretq_s32_s8, [c]]
       - Let:
           - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+          - FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]]
       - FnCall:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: ['vreinterpret{type[3]}_s8_s32', [c]]
 
   - name: "vdot{neon_type[0].laneq_nox}"
     doc: Dot product arithmetic (indexed)
@@ -7065,23 +7057,21 @@ intrinsics:
       - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
     safety: safe
     types:
-      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]','']
-      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+      - [uint32x2_t, uint8x8_t, uint8x16_t, '']
+      - [uint32x4_t, uint8x16_t, uint8x16_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
       - Let:
           - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: ['vreinterpretq_u32_u8', [c]]
       - Let:
           - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+          - FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]]
       - FnCall:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: [transmute, [c]]
+            - FnCall: ['vreinterpret{type[3]}_u8_u32', [c]]
 
   - name: "vdot{neon_type[0].no}"
     doc: Dot product arithmetic (vector)
@@ -7146,23 +7136,21 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]','']
-      - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+      - [int32x2_t, int8x8_t, int8x8_t, '']
+      - [int32x4_t, int8x16_t, int8x8_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: ['vreinterpret_s32_s8', [c]]
       - Let:
           - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+          - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]]
       - FnCall:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: ['vreinterpret{type[3]}_s8_s32', [c]]
 
   - name: "vdot{neon_type[0].lane_nox}"
     doc: Dot product arithmetic (indexed)
@@ -7179,23 +7167,21 @@ intrinsics:
       - *neon-cfg-arm-unstable
     safety: safe
     types:
-      - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]','']
-      - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+      - [uint32x2_t, uint8x8_t, uint8x8_t, '']
+      - [uint32x4_t, uint8x16_t, uint8x8_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, '1']]
       - Let:
           - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]]
+          - FnCall: ['vreinterpret_u32_u8', [c]]
       - Let:
           - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+          - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]]
       - FnCall:
           - "vdot{neon_type[0].no}"
           - - a
             - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+            - FnCall: ['vreinterpret{type[3]}_u8_u32', [c]]
 
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)

From 2ada72b455b2752fe39760256a21903d121e18d8 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sat, 9 May 2026 09:54:33 +0530
Subject: [PATCH 313/326] Split `vcopyq_lane{q}_p64` due to `vsetq_lane_p64`
 requiring `aes`

---
 .../core_arch/src/aarch64/neon/generated.rs   |  4 +-
 .../spec/neon/aarch64.spec.yml                | 37 ++++++++++++++++++-
 2 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 63ffa6765c..fef672cab9 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -4618,7 +4618,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
     static_assert_uimm_bits!(LANE1, 1);
     static_assert!(LANE2 == 0);
     let b: poly64x2_t = vcombine_p64(b, b);
-    vsetq_lane_p64::<LANE1>(vgetq_lane_p64::<LANE2>(b), a)
+    unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) }
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
@@ -5001,7 +5001,7 @@ pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
 ) -> poly64x2_t {
     static_assert_uimm_bits!(LANE1, 1);
     static_assert_uimm_bits!(LANE2, 1);
-    vsetq_lane_p64::<LANE1>(vgetq_lane_p64::<LANE2>(b), a)
+    unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) }
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 7664bf3c10..401bb504b3 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -8856,7 +8856,6 @@ intrinsics:
       - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1']
       - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4']
       - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3']
-      - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1']
       - [float32x4_t, float32x4_t, float32x4_t, '2', '2']
       - [float64x2_t, float64x2_t, float64x2_t, '1', '1']
     compose:
@@ -8864,6 +8863,23 @@ intrinsics:
       - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
       - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
+  - name: "vcopy{neon_type[0].laneq_nox}"
+    doc: "Insert vector element from another vector element"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[2]}"
+    attr:
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['1', '3']]
+      - *neon-stable
+    static_defs: ['const LANE1: i32, const LANE2: i32']
+    safety: safe
+    types:
+      - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']]
+      - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']]
+      - FnCall: [simd_insert!, [a, LANE1 as u32, {FnCall: [simd_extract!, [b, LANE2 as u32, p64]]}]]
+
   - name: "vcopy{neon_type[0].laneq_nox}"
     doc: "Insert vector element from another vector element"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
@@ -8902,7 +8918,6 @@ intrinsics:
     types:
       - [int64x2_t, int64x1_t]
       - [uint64x2_t, uint64x1_t]
-      - [poly64x2_t, poly64x1_t]
       - [float64x2_t, float64x1_t]
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE1, '1']]
@@ -8910,6 +8925,24 @@ intrinsics:
       - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}]
       - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}, a], [LANE1]]
 
+  - name: "vcopyq_lane_{neon_type[0]}"
+    doc: "Insert vector element from another vector element"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[0]}"
+    attr:
+      - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['1', '3']]
+      - *neon-stable
+    static_defs: ['const LANE1: i32, const LANE2: i32']
+    safety: safe
+    types:
+      - [poly64x2_t, poly64x1_t]
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE1, '1']]
+      - FnCall: [static_assert!, ['LANE2 == 0']]
+      - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}]
+      - FnCall: [simd_insert!, [a, LANE1 as u32, {FnCall: [simd_extract!, [b, LANE2 as u32, p64]]}]]
+
   - name: "vcopyq_lane_f32"
     doc: "Insert vector element from another vector element"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]

From c87d3e2bf711b03ac3eb9b7e00b328a6afaa94f9 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Wed, 6 May 2026 16:27:37 +0800
Subject: [PATCH 314/326] loongarch: Use `intrinsics::simd` for vadda

---
 .../src/loongarch64/lasx/generated.rs         | 36 -------------------
 .../src/loongarch64/lasx/portable.rs          |  4 +++
 .../src/loongarch64/lsx/generated.rs          | 36 -------------------
 .../core_arch/src/loongarch64/lsx/portable.rs |  4 +++
 crates/core_arch/src/loongarch64/simd.rs      | 13 +++++++
 crates/stdarch-gen-loongarch/lasx.spec        |  4 +++
 crates/stdarch-gen-loongarch/lsx.spec         |  4 +++
 .../src/portable-intrinsics.txt               |  8 +++++
 8 files changed, 37 insertions(+), 72 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index 387a3e564c..5ef7132637 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -91,14 +91,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvsat_wu(a: __v8u32, b: u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvsat.du"]
     fn __lasx_xvsat_du(a: __v4u64, b: u32) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvadda.b"]
-    fn __lasx_xvadda_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvadda.h"]
-    fn __lasx_xvadda_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvadda.w"]
-    fn __lasx_xvadda_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvadda.d"]
-    fn __lasx_xvadda_d(a: __v4i64, b: __v4i64) -> __v4i64;
     #[link_name = "llvm.loongarch.lasx.xvavg.b"]
     fn __lasx_xvavg_b(a: __v32i8, b: __v32i8) -> __v32i8;
     #[link_name = "llvm.loongarch.lasx.xvavg.h"]
@@ -1445,34 +1437,6 @@ pub fn lasx_xvsat_du<const IMM6: u32>(a: m256i) -> m256i {
     unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lasx/portable.rs b/crates/core_arch/src/loongarch64/lasx/portable.rs
index 147d94fe21..366deda0c1 100644
--- a/crates/core_arch/src/loongarch64/lasx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -148,6 +148,10 @@ impl_vvv!("lasx", lasx_xvssub_bu, is::simd_saturating_sub, m256i, u8x32);
 impl_vvv!("lasx", lasx_xvssub_hu, is::simd_saturating_sub, m256i, u16x16);
 impl_vvv!("lasx", lasx_xvssub_wu, is::simd_saturating_sub, m256i, u32x8);
 impl_vvv!("lasx", lasx_xvssub_du, is::simd_saturating_sub, m256i, u64x4);
+impl_vvv!("lasx", lasx_xvadda_b, ls::simd_adda, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvadda_h, ls::simd_adda, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvadda_w, ls::simd_adda, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvadda_d, ls::simd_adda, m256i, i64x4);
 
 impl_vuv!("lasx", lasx_xvslli_b, is::simd_shl, m256i, i8x32);
 impl_vuv!("lasx", lasx_xvslli_h, is::simd_shl, m256i, i16x16);
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 4f9a022c1d..1df46a43fe 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -91,14 +91,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vsat_wu(a: __v4u32, b: u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vsat.du"]
     fn __lsx_vsat_du(a: __v2u64, b: u32) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vadda.b"]
-    fn __lsx_vadda_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vadda.h"]
-    fn __lsx_vadda_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vadda.w"]
-    fn __lsx_vadda_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vadda.d"]
-    fn __lsx_vadda_d(a: __v2i64, b: __v2i64) -> __v2i64;
     #[link_name = "llvm.loongarch.lsx.vavg.b"]
     fn __lsx_vavg_b(a: __v16i8, b: __v16i8) -> __v16i8;
     #[link_name = "llvm.loongarch.lsx.vavg.h"]
@@ -1357,34 +1349,6 @@ pub fn lsx_vsat_du<const IMM6: u32>(a: m128i) -> m128i {
     unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lsx/portable.rs b/crates/core_arch/src/loongarch64/lsx/portable.rs
index e98dcf050f..55d349142e 100644
--- a/crates/core_arch/src/loongarch64/lsx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -148,6 +148,10 @@ impl_vvv!("lsx", lsx_vssub_bu, is::simd_saturating_sub, m128i, u8x16);
 impl_vvv!("lsx", lsx_vssub_hu, is::simd_saturating_sub, m128i, u16x8);
 impl_vvv!("lsx", lsx_vssub_wu, is::simd_saturating_sub, m128i, u32x4);
 impl_vvv!("lsx", lsx_vssub_du, is::simd_saturating_sub, m128i, u64x2);
+impl_vvv!("lsx", lsx_vadda_b, ls::simd_adda, m128i, i8x16);
+impl_vvv!("lsx", lsx_vadda_h, ls::simd_adda, m128i, i16x8);
+impl_vvv!("lsx", lsx_vadda_w, ls::simd_adda, m128i, i32x4);
+impl_vvv!("lsx", lsx_vadda_d, ls::simd_adda, m128i, i64x2);
 
 impl_vuv!("lsx", lsx_vslli_b, is::simd_shl, m128i, i8x16);
 impl_vuv!("lsx", lsx_vslli_h, is::simd_shl, m128i, i16x8);
diff --git a/crates/core_arch/src/loongarch64/simd.rs b/crates/core_arch/src/loongarch64/simd.rs
index 6f573f56d6..ccad4b8c48 100644
--- a/crates/core_arch/src/loongarch64/simd.rs
+++ b/crates/core_arch/src/loongarch64/simd.rs
@@ -45,6 +45,19 @@ impl_simd_ext!(i64x4, i64);
 impl_simd_ext!(u64x2, u64);
 impl_simd_ext!(u64x4, u64);
 
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn simd_abs<T: Copy + const SimdExt>(a: T) -> T {
+    let m: T = is::simd_lt(a, ls::simd_splat(0));
+    is::simd_select(m, is::simd_neg(a), a)
+}
+
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn simd_adda<T: Copy + const SimdExt>(a: T, b: T) -> T {
+    is::simd_add(ls::simd_abs(a), ls::simd_abs(b))
+}
+
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(super) const unsafe fn simd_andn<T: Copy + const SimdExt>(a: T, b: T) -> T {
diff --git a/crates/stdarch-gen-loongarch/lasx.spec b/crates/stdarch-gen-loongarch/lasx.spec
index 27362d3259..07f2ed49d3 100644
--- a/crates/stdarch-gen-loongarch/lasx.spec
+++ b/crates/stdarch-gen-loongarch/lasx.spec
@@ -924,21 +924,25 @@ asm-fmts = xd, xj, ui6
 data-types = UV4DI, UV4DI, UQI
 
 /// lasx_xvadda_b
+impl = portable
 name = lasx_xvadda_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvadda_h
+impl = portable
 name = lasx_xvadda_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvadda_w
+impl = portable
 name = lasx_xvadda_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvadda_d
+impl = portable
 name = lasx_xvadda_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
diff --git a/crates/stdarch-gen-loongarch/lsx.spec b/crates/stdarch-gen-loongarch/lsx.spec
index 9b1b7cc245..0b32dd83c7 100644
--- a/crates/stdarch-gen-loongarch/lsx.spec
+++ b/crates/stdarch-gen-loongarch/lsx.spec
@@ -924,21 +924,25 @@ asm-fmts = vd, vj, ui6
 data-types = UV2DI, UV2DI, UQI
 
 /// lsx_vadda_b
+impl = portable
 name = lsx_vadda_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vadda_h
+impl = portable
 name = lsx_vadda_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vadda_w
+impl = portable
 name = lsx_vadda_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vadda_d
+impl = portable
 name = lsx_vadda_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
diff --git a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
index 423af4cd71..6e3e5fe32e 100644
--- a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
+++ b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -219,6 +219,10 @@ lsx_vssub_bu
 lsx_vssub_hu
 lsx_vssub_wu
 lsx_vssub_du
+lsx_vadda_b
+lsx_vadda_h
+lsx_vadda_w
+lsx_vadda_d
 
 # LASX intrinsics
 lasx_xvsll_b
@@ -435,3 +439,7 @@ lasx_xvssub_bu
 lasx_xvssub_hu
 lasx_xvssub_wu
 lasx_xvssub_du
+lasx_xvadda_b
+lasx_xvadda_h
+lasx_xvadda_w
+lasx_xvadda_d

From fd535898c243ffefa09ceab0280d6d14b49a63f6 Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 20 Apr 2026 14:21:22 +0100
Subject: [PATCH 315/326] gen-arm: split `vreinterpret` defn into multiple

This enables the `big_endian_inverse` transformation to apply to some
of these intrinsics only when appropriate.
---
 .../core_arch/src/aarch64/neon/generated.rs   |  510 +-
 .../src/arm_shared/neon/generated.rs          | 6154 ++++++-----------
 .../spec/neon/aarch64.spec.yml                |   37 +-
 .../spec/neon/arm_shared.spec.yml             |  200 +-
 4 files changed, 2541 insertions(+), 4360 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index fef672cab9..7ffeb5e639 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -17933,6 +17933,186 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
+#[inline]
+#[target_feature(enable = "neon")]
+#[stable(feature = "neon_intrinsics", since = "1.59.0")]
+#[cfg_attr(test, assert_instr(nop))]
+pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18142,15 +18322,6 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18220,15 +18391,6 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18275,15 +18437,6 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18407,30 +18560,6 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
-    unsafe {
-        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18507,30 +18636,6 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
-    unsafe {
-        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18583,30 +18688,6 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
-    unsafe {
-        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18749,72 +18830,6 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
-    unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
-    unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -18957,72 +18972,6 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
-    unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
-    unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -19141,33 +19090,6 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
@@ -19191,78 +19113,6 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(nop))]
-pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"]
 #[inline]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 476d8e78a2..968206fc5e 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -39123,7 +39123,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39142,11 +39142,11 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
+pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39165,15 +39165,15 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
+pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     unsafe {
         let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let ret_val: int32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39192,11 +39192,11 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
+pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39215,15 +39215,14 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
+pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     unsafe {
         let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39242,11 +39241,11 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
+pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39265,14 +39264,15 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
+pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     unsafe {
         let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: uint8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39291,11 +39291,11 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
+pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39314,15 +39314,15 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
+pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     unsafe {
         let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39341,11 +39341,11 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
+pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39364,15 +39364,14 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
+pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     unsafe {
         let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39391,11 +39390,11 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
+pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39414,15 +39413,15 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
+pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     unsafe {
         let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39441,11 +39440,11 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
+pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39464,14 +39463,15 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
+pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     unsafe {
-        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39490,11 +39490,11 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
+pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39513,15 +39513,19 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
+pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     unsafe {
-        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39540,11 +39544,11 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
+pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39563,15 +39567,15 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
+pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     unsafe {
-        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39590,11 +39594,11 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
+pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39613,15 +39617,15 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
+pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     unsafe {
         let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39640,11 +39644,11 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
+pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39663,10 +39667,10 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
+pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     unsafe {
         let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
+        let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
             ret_val,
@@ -39675,7 +39679,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39694,11 +39698,11 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
+pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39717,15 +39721,15 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
+pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     unsafe {
         let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39744,11 +39748,11 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
+pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39767,15 +39771,15 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
+pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     unsafe {
         let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39794,11 +39798,11 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
+pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39817,15 +39821,19 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
+pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     unsafe {
         let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39844,11 +39852,11 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
+pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39867,19 +39875,15 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
+pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: float16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39898,11 +39902,11 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
+pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39921,15 +39925,15 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
+pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39948,11 +39952,11 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
+pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -39971,15 +39975,15 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
+pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -39998,11 +40002,11 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
+pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40021,15 +40025,16 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
+pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40048,11 +40053,11 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
+pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40071,19 +40076,15 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
+pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: float16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40102,11 +40103,11 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
+pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40125,15 +40126,15 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
+pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40152,11 +40153,11 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
+pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40175,15 +40176,14 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
+pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40202,11 +40202,11 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
+pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40225,15 +40225,15 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
+pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40252,11 +40252,11 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
+pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40275,15 +40275,15 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
+pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40302,11 +40302,11 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
+pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40325,16 +40325,16 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
+pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     unsafe {
-        let a: int8x16_t =
+        let a: uint8x16_t =
             simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40353,11 +40353,11 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
+pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40376,15 +40376,15 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
+pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40403,11 +40403,11 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
+pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40426,15 +40426,15 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
+pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40453,11 +40453,11 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
+pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40476,15 +40476,14 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
+pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40503,11 +40502,11 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
+pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40526,15 +40525,15 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
+pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40553,11 +40552,11 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
+pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40576,14 +40575,15 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
+pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
     unsafe {
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -40602,11 +40602,11 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
+pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -40625,17 +40625,17 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
+pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: float16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40652,13 +40652,12 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
+pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40675,17 +40674,12 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40702,13 +40696,12 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
+pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40725,18 +40718,12 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
-    unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40753,13 +40740,12 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
+pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40776,17 +40762,12 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
-    unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40803,13 +40784,12 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
+pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40826,17 +40806,12 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
-    unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40853,13 +40828,12 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
+pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40876,17 +40850,12 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
-    unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40903,13 +40872,12 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
+pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40926,17 +40894,12 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 #[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40946,20 +40909,18 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
+    stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
+pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40969,23 +40930,18 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
+    stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
-    unsafe {
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -40995,20 +40951,18 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
+    stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
+pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -41018,24 +40972,18 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
+    stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
-    unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -41045,20 +40993,18 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
+    stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
+pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -41068,1583 +41014,18 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
+    stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
-    unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
-    unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
-    unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
-    unsafe {
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
-    unsafe {
-        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
-    unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
-    unsafe {
-        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
-    unsafe {
-        let ret_val: float16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-#[cfg(not(target_arch = "arm64ec"))]
-pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
-    unsafe {
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
-    unsafe {
-        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
-    unsafe {
-        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline]
-#[cfg(target_endian = "little")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
+pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42660,13 +41041,12 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
+pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42682,17 +41062,12 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42708,13 +41083,12 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
+pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42730,17 +41104,12 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
+pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42756,13 +41125,12 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
+pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42778,16 +41146,12 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
-    }
+pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42803,13 +41167,12 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
+pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42825,17 +41188,12 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42851,13 +41209,12 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
+pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42873,17 +41230,12 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42899,13 +41251,12 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
+pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42921,17 +41272,12 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
+pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42947,13 +41293,12 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
+pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42969,16 +41314,12 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
-    }
+pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42994,13 +41335,12 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
+pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43016,17 +41356,12 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43042,13 +41377,12 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
+pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43064,17 +41398,12 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
-    unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43090,13 +41419,12 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
+pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43112,18 +41440,12 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43139,13 +41461,12 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
+pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43161,18 +41482,12 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43188,13 +41503,12 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
+pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43210,18 +41524,12 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43237,13 +41545,12 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
+pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43259,18 +41566,12 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
+pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43286,13 +41587,12 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
+pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43303,27 +41603,17 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43339,13 +41629,12 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
+pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43361,18 +41650,12 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43388,13 +41671,12 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
+pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43410,18 +41692,12 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43437,13 +41713,12 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
+pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43459,20 +41734,15 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
-    unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
+pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43480,21 +41750,22 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43502,30 +41773,25 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
     unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let ret_val: float16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43533,21 +41799,22 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43555,26 +41822,25 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
     unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43582,21 +41848,22 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43604,25 +41871,25 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43630,21 +41897,22 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43652,25 +41920,26 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43678,21 +41947,22 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43700,25 +41970,25 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: float16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43726,21 +41996,22 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -43748,20 +42019,22 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
+    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
 )]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
+#[cfg(not(target_arch = "arm64ec"))]
+pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: float16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -43779,11 +42052,11 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
+pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -43801,15 +42074,14 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
+pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -43827,11 +42099,11 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
+pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -43849,15 +42121,15 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
+pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -43875,11 +42147,11 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
+pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -43897,15 +42169,15 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
+pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -43923,11 +42195,11 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
+pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -43945,14 +42217,14 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
+pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -43970,11 +42242,11 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
+pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -43992,15 +42264,15 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
+pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44018,11 +42290,11 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
+pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44040,15 +42312,15 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
+pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44066,11 +42338,11 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
+pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44088,15 +42360,14 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
+pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44114,11 +42385,11 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
+pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44136,19 +42407,15 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
+pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44166,11 +42433,11 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
+pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44188,15 +42455,15 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
+pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
+        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44214,11 +42481,11 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
+pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44236,15 +42503,14 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
+pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44262,11 +42528,11 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
+pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44284,10 +42550,10 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
+pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
             ret_val,
@@ -44296,7 +42562,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44314,11 +42580,11 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
+pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44336,15 +42602,15 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
+pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44362,11 +42628,11 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
+pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44384,15 +42650,15 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
+pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44410,11 +42676,11 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
+pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44432,15 +42698,19 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
+pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44458,11 +42728,11 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
+pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44480,19 +42750,15 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
+pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44510,11 +42776,11 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
+pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44532,15 +42798,15 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
+pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44558,11 +42824,11 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
+pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44580,15 +42846,19 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
+pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44606,11 +42876,11 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
+pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44628,15 +42898,15 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
+pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int8x8_t = transmute(a);
+        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44654,11 +42924,11 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
+pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44676,15 +42946,15 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
+pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44702,11 +42972,11 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
+pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44724,14 +42994,15 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
+pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44749,11 +43020,11 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
+pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44771,15 +43042,15 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
+pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44797,11 +43068,11 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
+pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44819,15 +43090,14 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
+pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44845,11 +43115,11 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
+pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44867,15 +43137,15 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
+pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44893,11 +43163,11 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
+pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44915,14 +43185,15 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
+pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44940,11 +43211,11 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
+pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -44962,15 +43233,14 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
+pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -44988,11 +43258,11 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
+pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45010,15 +43280,15 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
+pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45036,11 +43306,11 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
+pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45058,15 +43328,14 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
+pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45084,11 +43353,11 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
+pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45106,19 +43375,15 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
+pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45136,11 +43401,11 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
+pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45158,15 +43423,16 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
+pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45184,11 +43450,11 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
+pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45206,15 +43472,16 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
+pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45232,11 +43499,11 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
+pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45254,19 +43521,16 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
+pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45284,11 +43548,11 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
+pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45306,15 +43570,16 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
+pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45332,11 +43597,11 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
+pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45354,15 +43619,16 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
+pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45380,11 +43646,11 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
+pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45402,15 +43668,16 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
+pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45428,11 +43695,11 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
+pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45450,19 +43717,16 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
+pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45480,11 +43744,11 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
+pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45502,15 +43766,16 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
+pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45528,11 +43793,11 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
+pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45550,14 +43815,16 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
+pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
     unsafe {
-        let ret_val: float32x2_t = transmute(a);
+        let a: int8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45575,11 +43842,11 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
+pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45597,14 +43864,15 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
+pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
     unsafe {
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: float32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45622,11 +43890,11 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
+pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45644,14 +43912,15 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
+pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
     unsafe {
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45669,11 +43938,11 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
+pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45691,14 +43960,15 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
+pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45716,11 +43986,11 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
+pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45738,14 +44008,14 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
+pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
     unsafe {
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45763,11 +44033,11 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
+pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45785,14 +44055,15 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
+pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
     unsafe {
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45810,11 +44081,11 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
+pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45832,35 +44103,15 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
+pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
     unsafe {
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(nop)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
-    unsafe { transmute(a) }
-}
-#[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45878,11 +44129,11 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
+pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45900,14 +44151,14 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
+pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
     unsafe {
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45925,11 +44176,11 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
+pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45947,14 +44198,15 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
+pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
     unsafe {
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -45972,11 +44224,11 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
+pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -45994,15 +44246,14 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
+pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46020,11 +44271,11 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
+pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46042,19 +44293,14 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
+pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46072,11 +44318,11 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
+pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46094,15 +44340,15 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
+pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46120,11 +44366,11 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
+pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46142,15 +44388,19 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
+pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46168,11 +44418,11 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
+pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46190,19 +44440,15 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
+pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46220,11 +44466,11 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
+pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46242,15 +44488,15 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
+pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46268,11 +44514,11 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
+pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46290,15 +44536,19 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
+pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46316,11 +44566,11 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
+pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46338,15 +44588,15 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
+pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46364,11 +44614,11 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
+pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46386,19 +44636,15 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
+pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46416,11 +44662,11 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
+pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46438,15 +44684,19 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
+pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46464,11 +44714,11 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
+pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46486,15 +44736,15 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
+pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x2_t = transmute(a);
+        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46512,11 +44762,11 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
+pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46534,15 +44784,15 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
+pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46560,11 +44810,11 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
+pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46582,15 +44832,15 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
+pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46608,11 +44858,11 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
+pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46630,15 +44880,14 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
+pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46656,11 +44905,11 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
+pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46678,14 +44927,15 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
+pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46703,11 +44953,11 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
+pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46725,15 +44975,15 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
+pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46751,11 +45001,11 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
+pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46773,15 +45023,14 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
+pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46799,11 +45048,11 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
+pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46821,14 +45070,15 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
+pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46846,11 +45096,11 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
+pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46868,15 +45118,15 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
+pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46894,11 +45144,11 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
+pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46916,15 +45166,14 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
+pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46942,11 +45191,11 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
+pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -46964,16 +45213,14 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
+pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -46991,11 +45238,11 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
+pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47013,10 +45260,9 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
+pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -47026,7 +45272,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47044,11 +45290,11 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
+pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47066,16 +45312,15 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
+pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47093,11 +45338,11 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
+pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47115,16 +45360,15 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
+pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47142,11 +45386,11 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
+pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47164,16 +45408,19 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
+pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47191,11 +45438,11 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
+pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47213,16 +45460,15 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
+pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47240,11 +45486,11 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
+pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47262,16 +45508,15 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
+pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47289,11 +45534,11 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
+pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47311,16 +45556,19 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
+pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47338,11 +45586,11 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
+pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47360,20 +45608,15 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
+pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47391,11 +45634,11 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
+pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47413,16 +45656,15 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
+pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47440,11 +45682,11 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
+pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47462,15 +45704,14 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
+pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47488,11 +45729,11 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
+pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47510,15 +45751,14 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
+pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47536,11 +45776,11 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
+pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47558,15 +45798,14 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
+pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47584,11 +45823,11 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
+pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47606,15 +45845,14 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
+pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47632,11 +45870,11 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
+pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47654,14 +45892,14 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
+pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: uint8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47679,11 +45917,11 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
+pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47701,15 +45939,14 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
+pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: uint16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47727,11 +45964,11 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
+pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47749,15 +45986,14 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
+pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47775,11 +46011,11 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
+pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47797,14 +46033,14 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
+pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47822,11 +46058,11 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
+pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47844,15 +46080,14 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
+pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47870,11 +46105,11 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
+pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47892,15 +46127,14 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
+pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47918,11 +46152,11 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
+pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47940,15 +46174,15 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
+pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: float32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -47966,11 +46200,11 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
+pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -47988,9 +46222,9 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
+pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
@@ -48000,7 +46234,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48018,11 +46252,11 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
+pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48040,15 +46274,15 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
+pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48066,11 +46300,11 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
+pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48088,15 +46322,15 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
+pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48114,11 +46348,11 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
+pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48136,15 +46370,19 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
+pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48162,11 +46400,11 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
+pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48184,19 +46422,15 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
+pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48214,11 +46448,11 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
+pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48236,15 +46470,15 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
+pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
         let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48262,11 +46496,11 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
+pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48284,15 +46518,19 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
+pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48310,11 +46548,59 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
+pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(nop)
+)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "neon_intrinsics", since = "1.59.0")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
+    unsafe {
+        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+    }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
+#[inline]
+#[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(nop)
+)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "neon_intrinsics", since = "1.59.0")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
+    unsafe { transmute(a) }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48332,19 +46618,15 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
+pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48362,11 +46644,11 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
+pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48384,15 +46666,15 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
+pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48410,11 +46692,11 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
+pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48432,15 +46714,15 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
+pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float32x2_t = transmute(a);
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48458,11 +46740,11 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
+pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48480,15 +46762,14 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
+pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48506,11 +46787,11 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
+pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48528,15 +46809,15 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
+pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int16x4_t = transmute(a);
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48554,11 +46835,11 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
+pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48576,15 +46857,15 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
+pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int32x2_t = transmute(a);
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48602,11 +46883,11 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
+pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48624,14 +46905,14 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
+pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48649,11 +46930,11 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
+pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48671,15 +46952,15 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
+pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48697,11 +46978,11 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
+pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48719,15 +47000,14 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
+pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48745,11 +47025,11 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
+pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48767,14 +47047,15 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
+pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48792,11 +47073,11 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
+pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48814,15 +47095,16 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
+pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48840,11 +47122,11 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
+pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48862,15 +47144,16 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
+pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48888,11 +47171,11 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
+pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48910,15 +47193,16 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
+pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48936,11 +47220,11 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
+pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -48958,19 +47242,16 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
+pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -48988,11 +47269,11 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
+pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49010,15 +47291,16 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
+pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49036,11 +47318,11 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
+pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49058,15 +47340,16 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
+pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49084,11 +47367,11 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
+pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49106,15 +47389,16 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
+pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49132,11 +47416,11 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
+pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49154,19 +47438,16 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
+pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49184,11 +47465,11 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
+pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49206,15 +47487,16 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
+pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49232,11 +47514,11 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
+pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49254,15 +47536,15 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
+pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49280,11 +47562,11 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
+pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49302,19 +47584,15 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
+pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49332,11 +47610,11 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
+pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49354,15 +47632,15 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
+pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49380,11 +47658,11 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
+pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49402,14 +47680,14 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
+pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
     unsafe {
-        let ret_val: float32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49427,11 +47705,11 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
+pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49449,14 +47727,15 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
+pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
     unsafe {
-        let ret_val: int8x8_t = transmute(a);
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49474,11 +47753,11 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
+pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49496,14 +47775,15 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
+pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
     unsafe {
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49521,11 +47801,11 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
+pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49543,15 +47823,16 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
+pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
     unsafe {
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
 #[inline]
+#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49567,11 +47848,37 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
+pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
+#[inline]
+#[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(nop)
+)]
+#[cfg_attr(
+    not(target_arch = "arm"),
+    stable(feature = "neon_intrinsics", since = "1.59.0")
+)]
+#[cfg_attr(
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
+    unsafe {
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+    }
+}
+#[doc = "Vector reinterpret cast operation"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49589,11 +47896,11 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
+pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49611,14 +47918,14 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
+pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
     unsafe {
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49636,11 +47943,11 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
+pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49658,14 +47965,14 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
+pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
     unsafe {
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49683,11 +47990,11 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
+pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49705,14 +48012,15 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
+pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
     unsafe {
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49730,11 +48038,11 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
+pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49752,14 +48060,19 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
+pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
     unsafe {
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49777,11 +48090,11 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
+pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49799,14 +48112,15 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
+pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
     unsafe {
-        let ret_val: poly16x4_t = transmute(a);
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49824,11 +48138,11 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
+pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49846,15 +48160,15 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
+pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49872,11 +48186,11 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
+pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49894,10 +48208,10 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
+pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int8x16_t = transmute(a);
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
             ret_val,
@@ -49906,7 +48220,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49924,11 +48238,11 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
+pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49946,15 +48260,15 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
+pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -49972,11 +48286,11 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
+pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -49994,15 +48308,15 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
+pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50020,11 +48334,11 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
+pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50042,15 +48356,19 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
+pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50068,11 +48386,11 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
+pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50090,19 +48408,15 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
+pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50120,11 +48434,11 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
+pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50142,15 +48456,15 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
+pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50168,11 +48482,11 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
+pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50190,15 +48504,15 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
+pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50216,11 +48530,11 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
+pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50238,19 +48552,14 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
+pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50268,11 +48577,11 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
+pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50290,15 +48599,15 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
+pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50316,11 +48625,11 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
+pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50338,15 +48647,15 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
+pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50364,11 +48673,11 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
+pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50386,15 +48695,14 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
+pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50412,11 +48720,11 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
+pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50434,15 +48742,15 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
+pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50460,11 +48768,11 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
+pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50482,15 +48790,15 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
+pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50508,11 +48816,11 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
+pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50530,14 +48838,14 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
+pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50555,11 +48863,11 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
+pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50577,15 +48885,14 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
+pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50603,11 +48910,11 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
+pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50625,15 +48932,19 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
+pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50651,11 +48962,11 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
+pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50673,15 +48984,15 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
+pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50699,11 +49010,11 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
+pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50721,14 +49032,15 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
+pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50746,11 +49058,11 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
+pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50768,15 +49080,19 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
+pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50794,11 +49110,11 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
+pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50816,16 +49132,15 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
+pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50843,11 +49158,11 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
+pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50865,20 +49180,15 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
+pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50896,11 +49206,11 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
+pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50918,16 +49228,19 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
+pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50945,11 +49258,11 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
+pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -50967,16 +49280,15 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
+pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -50994,11 +49306,11 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
+pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51016,16 +49328,15 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
+pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
+        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51043,11 +49354,11 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
+pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51065,20 +49376,14 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
+pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let ret_val: float32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51096,11 +49401,11 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
+pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51118,16 +49423,14 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
+pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
+        let ret_val: int8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51145,11 +49448,11 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
+pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51167,16 +49470,14 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
+pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
+        let ret_val: int16x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51194,11 +49495,11 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
+pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51216,16 +49517,14 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
+pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
+        let ret_val: int32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51243,11 +49542,11 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
+pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51265,16 +49564,14 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
+pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
+        let ret_val: uint8x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51292,11 +49589,11 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
+pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51314,15 +49611,14 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
+pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: float32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: uint16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51340,11 +49636,11 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
+pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51362,15 +49658,14 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
+pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51388,11 +49683,11 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
+pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51410,15 +49705,14 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
+pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51436,11 +49730,11 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
+pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51458,15 +49752,14 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
+pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51484,11 +49777,11 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
+pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51506,14 +49799,14 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
+pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51531,11 +49824,11 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
+pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51553,15 +49846,15 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
+pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51579,11 +49872,11 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
+pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51601,15 +49894,19 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
+pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51627,11 +49924,11 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
+pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51649,15 +49946,15 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
+pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51675,11 +49972,11 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
+pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51697,14 +49994,15 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
+pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51722,11 +50020,11 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
+pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51744,15 +50042,19 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
+pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51770,11 +50072,11 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
+pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51792,15 +50094,15 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
+pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: float32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51818,11 +50120,11 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
+pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51840,19 +50142,15 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
+pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51870,11 +50168,11 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
+pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51892,15 +50190,19 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
+pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51918,11 +50220,11 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
+pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51940,15 +50242,15 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
+pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -51966,11 +50268,11 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
+pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -51988,15 +50290,15 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
+pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: int64x2_t = transmute(a);
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -52014,11 +50316,11 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
+pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -52036,19 +50338,15 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
+pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -52066,11 +50364,11 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
+pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -52088,15 +50386,15 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
+pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -52114,11 +50412,11 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
+pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -52136,15 +50434,14 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
+pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -52162,11 +50459,11 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
+pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -52184,15 +50481,15 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
+pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -52210,11 +50507,11 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
+pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -52232,23 +50529,19 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
+pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52262,15 +50555,15 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
+pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52284,22 +50577,18 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
+pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
     unsafe {
-        let ret_val: int8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52313,15 +50602,15 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
+pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52335,18 +50624,19 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
+pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
     unsafe {
-        let ret_val: int16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52360,15 +50650,15 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
+pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52382,18 +50672,18 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
+pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
     unsafe {
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52407,15 +50697,15 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
+pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52429,18 +50719,19 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
+pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
     unsafe {
-        let ret_val: int64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52454,15 +50745,15 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
+pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52473,25 +50764,23 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
-    unsafe {
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+    target_arch = "arm",
+    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
+)]
+pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
+    unsafe {
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52505,15 +50794,15 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
+pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52527,18 +50816,20 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
+pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
     unsafe {
-        let ret_val: uint16x8_t = transmute(a);
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52552,15 +50843,15 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
+pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52574,18 +50865,20 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
+pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
     unsafe {
-        let ret_val: uint32x4_t = transmute(a);
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52599,15 +50892,15 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
+pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52621,18 +50914,20 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
+pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
     unsafe {
-        let ret_val: uint64x2_t = transmute(a);
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52646,15 +50941,15 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
+pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52668,22 +50963,20 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
+pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
     unsafe {
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52697,15 +50990,15 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
+pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52719,18 +51012,20 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
+pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
     unsafe {
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52744,15 +51039,15 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
+pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52766,18 +51061,20 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
+pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
     unsafe {
-        let ret_val: poly64x2_t = transmute(a);
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52791,15 +51088,15 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
+pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52813,18 +51110,20 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
+pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
     unsafe {
-        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: poly8x16_t =
+            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52838,15 +51137,15 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
+pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52860,19 +51159,20 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
+pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
     unsafe {
-        let a: int8x16_t =
+        let a: poly8x16_t =
             simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: poly64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52886,15 +51186,15 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
+pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52908,20 +51208,19 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
+pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
     unsafe {
-        let a: int8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: float32x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52935,15 +51234,15 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
+pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52957,18 +51256,19 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
+pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
     unsafe {
-        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -52982,15 +51282,15 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
+pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53004,18 +51304,19 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
+pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: int32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53029,15 +51330,15 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
+pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53051,19 +51352,18 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
+pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
     unsafe {
-        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53077,15 +51377,15 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
+pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53099,18 +51399,19 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
+pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
     unsafe {
-        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53124,15 +51425,15 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
+pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53146,18 +51447,19 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
+pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53171,15 +51473,15 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
+pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53193,19 +51495,18 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
+pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
     unsafe {
-        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53219,15 +51520,15 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
+pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53241,18 +51542,19 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
+pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
     unsafe {
-        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53266,15 +51568,15 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
+pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53288,18 +51590,18 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
+pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
     unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53313,15 +51615,15 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
+pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53335,19 +51637,18 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
+pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
         transmute(a)
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53361,15 +51662,15 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
+pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53383,20 +51684,19 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
+pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
     unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: float32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53410,15 +51710,15 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
+pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53432,18 +51732,23 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
+pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
     unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53457,15 +51762,15 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
+pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53479,18 +51784,19 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
+pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53504,15 +51810,15 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
+pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53526,19 +51832,19 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
+pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
     unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: int64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53552,15 +51858,15 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
+pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53574,18 +51880,23 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
+pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
     unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53599,15 +51910,15 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
+pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
 #[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53621,18 +51932,19 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
+pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53646,15 +51958,15 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
+pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53668,19 +51980,19 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
+pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
     unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: uint64x2_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53694,15 +52006,15 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
+pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53716,18 +52028,23 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
+pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
     unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53741,15 +52058,15 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
+pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53763,18 +52080,19 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
+pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
     unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
+        let ret_val: poly64x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53788,15 +52106,15 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
+pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53810,19 +52128,18 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
+pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: int8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53836,15 +52153,15 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
+pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53858,20 +52175,18 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
+pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
     unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: int16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53885,15 +52200,15 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
+pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53907,18 +52222,18 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
+pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
     unsafe {
-        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: int32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53932,15 +52247,15 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
+pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53954,18 +52269,18 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
+pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        transmute(a)
+        let ret_val: uint8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -53979,15 +52294,15 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
+pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54001,19 +52316,18 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
+pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
     unsafe {
-        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly64x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: uint16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54027,15 +52341,15 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
+pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54049,18 +52363,18 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
+pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
     unsafe {
-        let ret_val: int8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let ret_val: uint32x2_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54074,15 +52388,15 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
+pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54096,18 +52410,18 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
+pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
     unsafe {
-        let ret_val: int16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let ret_val: poly8x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54121,15 +52435,15 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
+pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54143,18 +52457,18 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
+pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
     unsafe {
-        let ret_val: int32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let ret_val: poly16x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54168,15 +52482,15 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
+pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54190,18 +52504,23 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
+pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
     unsafe {
-        let ret_val: uint8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54215,15 +52534,15 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
+pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54237,18 +52556,19 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
+pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
     unsafe {
-        let ret_val: uint16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54262,15 +52582,15 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
+pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54284,18 +52604,19 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
+pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
     unsafe {
-        let ret_val: uint32x2_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [1, 0])
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: int32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54309,15 +52630,15 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
+pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54331,18 +52652,23 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
+pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
     unsafe {
-        let ret_val: poly8x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint8x16_t = transmute(a);
+        simd_shuffle!(
+            ret_val,
+            ret_val,
+            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
+        )
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54356,15 +52682,15 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
+pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54378,18 +52704,19 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
+pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
     unsafe {
-        let ret_val: poly16x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
+        let ret_val: uint16x8_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54403,15 +52730,15 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
+pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54425,18 +52752,19 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
+pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
     unsafe {
         let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        transmute(a)
+        let ret_val: uint32x4_t = transmute(a);
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54450,15 +52778,15 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
+pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54472,10 +52800,10 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
+pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
     unsafe {
         let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int8x16_t = transmute(a);
+        let ret_val: poly8x16_t = transmute(a);
         simd_shuffle!(
             ret_val,
             ret_val,
@@ -54484,11 +52812,11 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54502,15 +52830,15 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
+pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -54524,17 +52852,16 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
+pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
     unsafe {
         let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int16x8_t = transmute(a);
+        let ret_val: poly16x8_t = transmute(a);
         simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
     }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54550,13 +52877,12 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
+pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54572,17 +52898,12 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: int32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54598,13 +52919,12 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
+pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54620,21 +52940,12 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
+pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54650,13 +52961,12 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
+pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54672,17 +52982,12 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54698,13 +53003,12 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
+pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54720,17 +53024,12 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint32x4_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
+pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54746,13 +53045,12 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
+pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54768,21 +53066,12 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly8x16_t = transmute(a);
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
+pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
+    unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54798,13 +53087,12 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
+pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
     unsafe { transmute(a) }
 }
 #[doc = "Vector reinterpret cast operation"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
 #[inline]
-#[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54820,12 +53108,8 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
-pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
-    unsafe {
-        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: poly16x8_t = transmute(a);
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
+pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
+    unsafe { transmute(a) }
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 401bb504b3..0a466dda71 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -8523,7 +8523,6 @@ intrinsics:
             - link: "llvm.aarch64.neon.frecpx.{type[1]}"
               arch: aarch64,arm64ec
 
-
   - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
     doc: Vector reinterpret cast operation
     arguments: ["a: {type[0]}"]
@@ -8531,6 +8530,7 @@ intrinsics:
     attr: [*neon-stable]
     assert_instr: [nop]
     safety: safe
+    big_endian_inverse: false
     types:
       - [poly64x1_t, int64x1_t]
       - [poly64x1_t, uint64x1_t]
@@ -8540,54 +8540,65 @@ intrinsics:
       - [poly64x2_t, uint64x2_t]
       - [int64x2_t, poly64x2_t]
       - [uint64x2_t, poly64x2_t]
+      - [float64x1_t, int64x1_t]
+      - [float64x2_t, int64x2_t]
+      - [float64x1_t, uint64x1_t]
+      - [float64x2_t, uint64x2_t]
+      - [float64x1_t, poly64x1_t]
+      - [float64x2_t, poly64x2_t]
+      - [int64x1_t, float64x1_t]
+      - [int64x2_t, float64x2_t]
+      - [uint64x1_t, float64x1_t]
+      - [uint64x2_t, float64x2_t]
+      - [poly64x1_t, float64x1_t]
+      - [poly64x2_t, float64x2_t]
+    compose:
+      - FnCall: [transmute, [a]]
+
+  - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
+    doc: Vector reinterpret cast operation
+    arguments: ["a: {type[0]}"]
+    return_type: "{type[1]}"
+    attr: [*neon-stable]
+    assert_instr: [nop]
+    safety: safe
+    types:
       - [float64x1_t, int8x8_t]
       - [float64x1_t, int16x4_t]
       - [float64x1_t, int32x2_t]
-      - [float64x1_t, int64x1_t]
       - [float64x2_t, int8x16_t]
       - [float64x2_t, int16x8_t]
       - [float64x2_t, int32x4_t]
-      - [float64x2_t, int64x2_t]
       - [float64x1_t, uint8x8_t]
       - [float64x1_t, uint16x4_t]
       - [float64x1_t, uint32x2_t]
-      - [float64x1_t, uint64x1_t]
       - [float64x2_t, uint8x16_t]
       - [float64x2_t, uint16x8_t]
       - [float64x2_t, uint32x4_t]
-      - [float64x2_t, uint64x2_t]
       - [float64x1_t, poly8x8_t]
       - [float64x1_t, poly16x4_t]
       - [float32x2_t, poly64x1_t]
-      - [float64x1_t, poly64x1_t]
       - [float64x2_t, poly8x16_t]
       - [float64x2_t, poly16x8_t]
       - [float32x4_t, poly64x2_t]
-      - [float64x2_t, poly64x2_t]
       - [float64x2_t, p128]
       - [int8x8_t, float64x1_t]
       - [int16x4_t, float64x1_t]
       - [int32x2_t, float64x1_t]
-      - [int64x1_t, float64x1_t]
       - [int8x16_t, float64x2_t]
       - [int16x8_t, float64x2_t]
       - [int32x4_t, float64x2_t]
-      - [int64x2_t, float64x2_t]
       - [poly8x8_t, float64x1_t]
       - [uint16x4_t, float64x1_t]
       - [uint32x2_t, float64x1_t]
-      - [uint64x1_t, float64x1_t]
       - [poly8x16_t, float64x2_t]
       - [uint16x8_t, float64x2_t]
       - [uint32x4_t, float64x2_t]
-      - [uint64x2_t, float64x2_t]
       - [uint8x8_t, float64x1_t]
       - [poly16x4_t, float64x1_t]
-      - [poly64x1_t, float64x1_t]
       - [poly64x1_t, float32x2_t]
       - [uint8x16_t, float64x2_t]
       - [poly16x8_t, float64x2_t]
-      - [poly64x2_t, float64x2_t]
       - [poly64x2_t, float32x4_t]
       - [p128, float64x2_t]
       - [float32x2_t, float64x1_t]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 1f7e1f6987..b668308034 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -8476,33 +8476,48 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
+    big_endian_inverse: false
     types:
-      - [poly64x1_t, int32x2_t]
-      - [poly64x1_t, uint32x2_t]
-      - [poly64x2_t, int32x4_t]
-      - [poly64x2_t, uint32x4_t]
       - [p128, int64x2_t]
       - [p128, uint64x2_t]
       - [p128, poly64x2_t]
-      - [poly8x16_t, p128]
       - [p128, int8x16_t]
       - [p128, uint8x16_t]
       - [p128, poly8x16_t]
+      - [poly64x2_t, p128]
+      - [p128, int32x4_t]
+      - [p128, uint32x4_t]
+      - [p128, int16x8_t]
+      - [p128, uint16x8_t]
+      - [p128, poly16x8_t]
+    compose:
+      - FnCall: [transmute, [a]]
+
+  - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
+    doc: Vector reinterpret cast operation
+    arguments: ["a: {type[0]}"]
+    return_type: "{type[1]}"
+    attr:
+      - *neon-v7
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
+      - *neon-not-arm-stable
+      - *neon-cfg-arm-unstable
+    safety: safe
+    types:
+      - [poly64x1_t, int32x2_t]
+      - [poly64x1_t, uint32x2_t]
+      - [poly8x16_t, p128]
       - [int32x2_t, poly64x1_t]
       - [uint32x2_t, poly64x1_t]
       - [int32x4_t, poly64x2_t]
       - [uint32x4_t, poly64x2_t]
       - [int64x2_t, p128]
       - [uint64x2_t, p128]
-      - [poly64x2_t, p128]
       - [poly64x1_t, int16x4_t]
       - [poly64x1_t, uint16x4_t]
       - [poly64x1_t, poly16x4_t]
-      - [poly64x2_t, int16x8_t]
-      - [poly64x2_t, uint16x8_t]
       - [poly64x2_t, poly16x8_t]
-      - [p128, int32x4_t]
-      - [p128, uint32x4_t]
       - [poly16x4_t, poly64x1_t]
       - [int16x4_t, poly64x1_t]
       - [uint16x4_t, poly64x1_t]
@@ -8514,12 +8529,7 @@ intrinsics:
       - [poly64x1_t, int8x8_t]
       - [poly64x1_t, uint8x8_t]
       - [poly64x1_t, poly8x8_t]
-      - [poly64x2_t, int8x16_t]
-      - [poly64x2_t, uint8x16_t]
       - [poly64x2_t, poly8x16_t]
-      - [p128, int16x8_t]
-      - [p128, uint16x8_t]
-      - [p128, poly16x8_t]
       - [poly8x8_t, poly64x1_t]
       - [int8x8_t, poly64x1_t]
       - [uint8x8_t, poly64x1_t]
@@ -8531,53 +8541,12 @@ intrinsics:
       - [poly16x8_t, p128]
       - [int8x16_t, p128]
       - [uint8x16_t, p128]
-    compose:
-      - FnCall: [transmute, [a]]
-
-  - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
-    doc: Vector reinterpret cast operation
-    arguments: ["a: {type[0]}"]
-    return_type: "{type[1]}"
-    attr:
-      - *neon-v7
-      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
-      - *neon-not-arm-stable
-      - *neon-cfg-arm-unstable
-    safety: safe
-    types:
-      - [uint8x8_t, int8x8_t]
-      - [poly8x8_t, int8x8_t]
-      - [poly16x4_t, int16x4_t]
-      - [uint16x4_t, int16x4_t]
-      - [uint32x2_t, int32x2_t]
-      - [uint64x1_t, int64x1_t]
-      - [uint8x16_t, int8x16_t]
-      - [poly8x16_t, int8x16_t]
-      - [poly16x8_t, int16x8_t]
-      - [uint16x8_t, int16x8_t]
-      - [uint32x4_t, int32x4_t]
-      - [uint64x2_t, int64x2_t]
-      - [poly8x8_t, uint8x8_t]
-      - [int8x8_t, uint8x8_t]
-      - [poly16x4_t, uint16x4_t]
-      - [int16x4_t, uint16x4_t]
-      - [int32x2_t, uint32x2_t]
-      - [int64x1_t, uint64x1_t]
-      - [poly8x16_t, uint8x16_t]
-      - [int8x16_t, uint8x16_t]
-      - [poly16x8_t, uint16x8_t]
-      - [int16x8_t, uint16x8_t]
-      - [int32x4_t, uint32x4_t]
-      - [int64x2_t, uint64x2_t]
-      - [int8x8_t, poly8x8_t]
-      - [uint8x8_t, poly8x8_t]
-      - [int16x4_t, poly16x4_t]
-      - [uint16x4_t, poly16x4_t]
-      - [int8x16_t, poly8x16_t]
-      - [uint8x16_t, poly8x16_t]
-      - [int16x8_t, poly16x8_t]
-      - [uint16x8_t, poly16x8_t]
+      - [poly64x2_t, int32x4_t]
+      - [poly64x2_t, uint32x4_t]
+      - [poly64x2_t, int16x8_t]
+      - [poly64x2_t, uint16x8_t]
+      - [poly64x2_t, int8x16_t]
+      - [poly64x2_t, uint8x16_t]
       - [int16x4_t, int8x8_t]
       - [uint16x4_t, int8x8_t]
       - [poly16x4_t, int8x8_t]
@@ -8728,19 +8697,15 @@ intrinsics:
       - [uint8x16_t, uint64x2_t]
       - [float32x2_t, int8x8_t]
       - [float32x2_t, int16x4_t]
-      - [float32x2_t, int32x2_t]
       - [float32x2_t, int64x1_t]
       - [float32x4_t, int8x16_t]
       - [float32x4_t, int16x8_t]
-      - [float32x4_t, int32x4_t]
       - [float32x4_t, int64x2_t]
       - [float32x2_t, uint8x8_t]
       - [float32x2_t, uint16x4_t]
-      - [float32x2_t, uint32x2_t]
       - [float32x2_t, uint64x1_t]
       - [float32x4_t, uint8x16_t]
       - [float32x4_t, uint16x8_t]
-      - [float32x4_t, uint32x4_t]
       - [float32x4_t, uint64x2_t]
       - [float32x2_t, poly8x8_t]
       - [float32x2_t, poly16x4_t]
@@ -8749,19 +8714,15 @@ intrinsics:
       - [float32x4_t, p128]
       - [int8x8_t, float32x2_t]
       - [int16x4_t, float32x2_t]
-      - [int32x2_t, float32x2_t]
       - [int64x1_t, float32x2_t]
       - [int8x16_t, float32x4_t]
       - [int16x8_t, float32x4_t]
-      - [int32x4_t, float32x4_t]
       - [int64x2_t, float32x4_t]
       - [uint8x8_t, float32x2_t]
       - [uint16x4_t, float32x2_t]
-      - [uint32x2_t, float32x2_t]
       - [uint64x1_t, float32x2_t]
       - [uint8x16_t, float32x4_t]
       - [uint16x8_t, float32x4_t]
-      - [uint32x4_t, float32x4_t]
       - [uint64x2_t, float32x4_t]
       - [poly8x8_t, float32x2_t]
       - [poly16x4_t, float32x2_t]
@@ -8771,6 +8732,61 @@ intrinsics:
     compose:
       - FnCall: [transmute, [a]]
 
+  - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
+    doc: Vector reinterpret cast operation
+    arguments: ["a: {type[0]}"]
+    return_type: "{type[1]}"
+    attr:
+      - *neon-v7
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
+      - *neon-not-arm-stable
+      - *neon-cfg-arm-unstable
+    safety: safe
+    big_endian_inverse: false
+    types:
+      - [uint8x8_t, int8x8_t]
+      - [poly8x8_t, int8x8_t]
+      - [poly16x4_t, int16x4_t]
+      - [uint16x4_t, int16x4_t]
+      - [uint32x2_t, int32x2_t]
+      - [uint64x1_t, int64x1_t]
+      - [uint8x16_t, int8x16_t]
+      - [poly8x16_t, int8x16_t]
+      - [poly16x8_t, int16x8_t]
+      - [uint16x8_t, int16x8_t]
+      - [uint32x4_t, int32x4_t]
+      - [uint64x2_t, int64x2_t]
+      - [poly8x8_t, uint8x8_t]
+      - [int8x8_t, uint8x8_t]
+      - [poly16x4_t, uint16x4_t]
+      - [int16x4_t, uint16x4_t]
+      - [int32x2_t, uint32x2_t]
+      - [int64x1_t, uint64x1_t]
+      - [poly8x16_t, uint8x16_t]
+      - [int8x16_t, uint8x16_t]
+      - [poly16x8_t, uint16x8_t]
+      - [int16x8_t, uint16x8_t]
+      - [int32x4_t, uint32x4_t]
+      - [int64x2_t, uint64x2_t]
+      - [int8x8_t, poly8x8_t]
+      - [uint8x8_t, poly8x8_t]
+      - [int16x4_t, poly16x4_t]
+      - [uint16x4_t, poly16x4_t]
+      - [int8x16_t, poly8x16_t]
+      - [uint8x16_t, poly8x16_t]
+      - [int16x8_t, poly16x8_t]
+      - [uint16x8_t, poly16x8_t]
+      - [float32x2_t, int32x2_t]
+      - [float32x4_t, int32x4_t]
+      - [float32x2_t, uint32x2_t]
+      - [float32x4_t, uint32x4_t]
+      - [int32x2_t, float32x2_t]
+      - [int32x4_t, float32x4_t]
+      - [uint32x2_t, float32x2_t]
+      - [uint32x4_t, float32x4_t]
+    compose:
+      - FnCall: [transmute, [a]]
 
   - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
     doc: Vector reinterpret cast operation
@@ -8787,54 +8803,74 @@ intrinsics:
     types:
       # non-q
       - [float32x2_t, float16x4_t]
-      - [poly16x4_t, float16x4_t]
       - [poly8x8_t, float16x4_t]
       - [int8x8_t, float16x4_t]
-      - [int16x4_t, float16x4_t]
       - [int32x2_t, float16x4_t]
       - [int64x1_t, float16x4_t]
       - [uint8x8_t, float16x4_t]
-      - [uint16x4_t, float16x4_t]
       - [uint32x2_t, float16x4_t]
       - [uint64x1_t, float16x4_t]
       - [float16x4_t, float32x2_t]
-      - [float16x4_t, poly16x4_t]
       - [float16x4_t, poly8x8_t]
       - [float16x4_t, int8x8_t]
-      - [float16x4_t, int16x4_t]
       - [float16x4_t, int32x2_t]
       - [float16x4_t, int64x1_t]
       - [float16x4_t, uint8x8_t]
-      - [float16x4_t, uint16x4_t]
       - [float16x4_t, uint32x2_t]
       - [float16x4_t, uint64x1_t]
       # q
       - [float32x4_t, float16x8_t]
-      - [poly16x8_t, float16x8_t]
       - [poly8x16_t, float16x8_t]
       - [int8x16_t, float16x8_t]
-      - [int16x8_t, float16x8_t]
       - [int32x4_t, float16x8_t]
       - [int64x2_t, float16x8_t]
       - [uint8x16_t, float16x8_t]
-      - [uint16x8_t, float16x8_t]
       - [uint32x4_t, float16x8_t]
       - [uint64x2_t, float16x8_t]
       - [float16x8_t, float32x4_t]
-      - [float16x8_t, poly16x8_t]
       - [float16x8_t, poly8x16_t]
       - [float16x8_t, int8x16_t]
-      - [float16x8_t, int16x8_t]
       - [float16x8_t, int32x4_t]
       - [float16x8_t, int64x2_t]
       - [float16x8_t, uint8x16_t]
-      - [float16x8_t, uint16x8_t]
       - [float16x8_t, uint32x4_t]
       - [float16x8_t, uint64x2_t]
     compose:
       - FnCall: [transmute, [a]]
 
 
+  - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
+    doc: Vector reinterpret cast operation
+    arguments: ["a: {type[0]}"]
+    return_type: "{type[1]}"
+    attr:
+      - *neon-v7
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
+      - *neon-not-arm-stable-fp16
+      - *neon-cfg-arm-unstable
+      - *target-not-arm64ec
+    safety: safe
+    big_endian_inverse: false
+    types:
+      # non-q
+      - [poly16x4_t, float16x4_t]
+      - [int16x4_t, float16x4_t]
+      - [uint16x4_t, float16x4_t]
+      - [float16x4_t, poly16x4_t]
+      - [float16x4_t, int16x4_t]
+      - [float16x4_t, uint16x4_t]
+      # q
+      - [poly16x8_t, float16x8_t]
+      - [int16x8_t, float16x8_t]
+      - [uint16x8_t, float16x8_t]
+      - [float16x8_t, poly16x8_t]
+      - [float16x8_t, int16x8_t]
+      - [float16x8_t, uint16x8_t]
+    compose:
+      - FnCall: [transmute, [a]]
+
+
   - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}"
     doc: Vector reinterpret cast operation
     arguments: ["a: {type[0]}"]

From 6574f625df7a239047d5491ba5f386ab0665566b Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sun, 10 May 2026 04:43:15 +0530
Subject: [PATCH 316/326] Remove the heuristic for big-endian reversal,
 reversing only if requested specifically

---
 .../core_arch/src/aarch64/neon/generated.rs   |  223 --
 .../src/arm_shared/neon/generated.rs          | 1817 -----------------
 .../spec/neon/aarch64.spec.yml                |   36 +-
 .../spec/neon/arm_shared.spec.yml             |   20 +-
 crates/stdarch-gen-arm/src/intrinsic.rs       |   19 +-
 5 files changed, 11 insertions(+), 2104 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 7ffeb5e639..0f9f2997b6 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -9469,7 +9469,6 @@ pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) ->
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -9477,47 +9476,16 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
     transmute(vld2q_dup_s64(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld2r))]
-pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
-    let mut ret_val: poly64x2x2_t = transmute(vld2q_dup_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
 pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
     transmute(vld2q_dup_s64(transmute(a)))
 }
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld2r))]
-pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
-    let mut ret_val: uint64x2x2_t = transmute(vld2q_dup_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val
-}
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
 #[doc = "## Safety"]
@@ -9672,7 +9640,6 @@ pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> p
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -9680,21 +9647,6 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
     transmute(vld2q_s64(transmute(a)))
 }
 #[doc = "Load multiple 2-element structures to two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld2))]
-pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
-    let mut ret_val: poly64x2x2_t = transmute(vld2q_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val
-}
-#[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
@@ -9853,7 +9805,6 @@ pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) ->
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -9861,49 +9812,16 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
     transmute(vld3q_dup_s64(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld3r))]
-pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
-    let mut ret_val: poly64x2x3_t = transmute(vld3q_dup_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
 pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
     transmute(vld3q_dup_s64(transmute(a)))
 }
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld3r))]
-pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
-    let mut ret_val: uint64x2x3_t = transmute(vld3q_dup_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val
-}
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
 #[doc = "## Safety"]
@@ -10061,7 +9979,6 @@ pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> p
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -10069,22 +9986,6 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
     transmute(vld3q_s64(transmute(a)))
 }
 #[doc = "Load multiple 3-element structures to three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ld3))]
-pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
-    let mut ret_val: poly64x2x3_t = transmute(vld3q_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val
-}
-#[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
@@ -10245,7 +10146,6 @@ pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) ->
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -10253,51 +10153,16 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
     transmute(vld4q_dup_s64(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(test, assert_instr(ld4r))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
-    let mut ret_val: poly64x2x4_t = transmute(vld4q_dup_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
     transmute(vld4q_dup_s64(transmute(a)))
 }
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(ld4r))]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
-    let mut ret_val: uint64x2x4_t = transmute(vld4q_dup_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
-    ret_val
-}
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
 #[doc = "## Safety"]
@@ -10458,7 +10323,6 @@ pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> p
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -10466,23 +10330,6 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
     transmute(vld4q_s64(transmute(a)))
 }
 #[doc = "Load multiple 4-element structures to four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[target_feature(enable = "neon,aes")]
-#[cfg_attr(test, assert_instr(ld4))]
-pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
-    let mut ret_val: poly64x2x4_t = transmute(vld4q_s64(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
-    ret_val
-}
-#[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
@@ -17516,7 +17363,6 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -17524,23 +17370,8 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vrbit_s8(transmute(a))) }
 }
 #[doc = "Reverse bit order"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(rbit))]
-pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vrbit_s8(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -17548,28 +17379,8 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
     unsafe { transmute(vrbitq_s8(transmute(a))) }
 }
 #[doc = "Reverse bit order"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(rbit))]
-pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
-    unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(vrbitq_s8(transmute(a)));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -17577,48 +17388,14 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
     unsafe { transmute(vrbit_s8(transmute(a))) }
 }
 #[doc = "Reverse bit order"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(rbit))]
-pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vrbit_s8(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
 pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
     unsafe { transmute(vrbitq_s8(transmute(a))) }
 }
-#[doc = "Reverse bit order"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(rbit))]
-pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
-    unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(vrbitq_s8(transmute(a)));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"]
 #[inline]
diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 968206fc5e..f3df62af6a 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -7342,7 +7342,6 @@ pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7362,35 +7361,8 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
     unsafe { transmute(vclz_s16(transmute(a))) }
 }
 #[doc = "Count leading zero bits"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(clz)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
-    unsafe {
-        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7410,35 +7382,8 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
     unsafe { transmute(vclzq_s16(transmute(a))) }
 }
 #[doc = "Count leading zero bits"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(clz)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
-    unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7458,35 +7403,8 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
     unsafe { transmute(vclz_s32(transmute(a))) }
 }
 #[doc = "Count leading zero bits"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(clz)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
-    unsafe {
-        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
-        let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
-#[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7506,35 +7424,8 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
     unsafe { transmute(vclzq_s32(transmute(a))) }
 }
 #[doc = "Count leading zero bits"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(clz)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7554,35 +7445,8 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vclz_s8(transmute(a))) }
 }
 #[doc = "Count leading zero bits"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(clz)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7601,37 +7465,6 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
     unsafe { transmute(vclzq_s8(transmute(a))) }
 }
-#[doc = "Count leading zero bits"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(clz)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
-    unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
 #[inline]
@@ -7677,7 +7510,6 @@ pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7697,35 +7529,8 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vcnt_s8(transmute(a))) }
 }
 #[doc = "Population count per byte."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(cnt)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7745,40 +7550,8 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
     unsafe { transmute(vcntq_s8(transmute(a))) }
 }
 #[doc = "Population count per byte."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(cnt)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
-    unsafe {
-        let a: uint8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
-#[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7798,35 +7571,8 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
     unsafe { transmute(vcnt_s8(transmute(a))) }
 }
 #[doc = "Population count per byte."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(cnt)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7845,37 +7591,6 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
     unsafe { transmute(vcntq_s8(transmute(a))) }
 }
-#[doc = "Population count per byte."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(cnt)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
-    unsafe {
-        let a: poly8x16_t =
-            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
-        simd_shuffle!(
-            ret_val,
-            ret_val,
-            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-        )
-    }
-}
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
 #[inline]
@@ -15197,7 +14912,6 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[target_feature(enable = "neon,fp16")]
@@ -15211,30 +14925,10 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
     ))
 }
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
-pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
-    let ret_val: float16x4_t = transmute(vld1_v4f16(
-        ptr as *const i8,
-        crate::mem::align_of::<f16>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-}
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[target_feature(enable = "neon,fp16")]
@@ -15247,25 +14941,6 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
         crate::mem::align_of::<f16>() as i32,
     ))
 }
-#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[cfg(target_arch = "arm")]
-#[target_feature(enable = "neon,v7")]
-#[target_feature(enable = "neon,fp16")]
-#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
-#[cfg(not(target_arch = "arm64ec"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
-pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
-    let ret_val: float16x8_t = transmute(vld1q_v8f16(
-        ptr as *const i8,
-        crate::mem::align_of::<f16>() as i32,
-    ));
-    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-}
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
 #[doc = "## Safety"]
@@ -18621,7 +18296,6 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18641,38 +18315,10 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
     transmute(vld2_dup_s8(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
-    let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18692,46 +18338,10 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
     transmute(vld2q_dup_s8(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
-    let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(
-        ret_val.0,
-        ret_val.0,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.1 = simd_shuffle!(
-        ret_val.1,
-        ret_val.1,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18751,38 +18361,10 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
     transmute(vld2_dup_s16(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
-    let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18802,38 +18384,10 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
     transmute(vld2q_dup_s16(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
-    let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18853,38 +18407,10 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
     transmute(vld2_dup_s32(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
-    let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18904,38 +18430,10 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
     transmute(vld2q_dup_s32(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
-    let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -18955,38 +18453,10 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
     transmute(vld2_dup_s8(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
-    let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -19006,46 +18476,10 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
     transmute(vld2q_dup_s8(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
-    let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(
-        ret_val.0,
-        ret_val.0,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.1 = simd_shuffle!(
-        ret_val.1,
-        ret_val.1,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -19065,38 +18499,10 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
     transmute(vld2_dup_s16(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
-    let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
@@ -19116,33 +18522,6 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
     transmute(vld2q_dup_s16(transmute(a)))
 }
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld2r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
-    let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
@@ -20892,7 +20271,6 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -20912,39 +20290,10 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
     transmute(vld3_dup_s8(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
-    let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -20964,51 +20313,10 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
     transmute(vld3q_dup_s8(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
-    let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(
-        ret_val.0,
-        ret_val.0,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.1 = simd_shuffle!(
-        ret_val.1,
-        ret_val.1,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.2 = simd_shuffle!(
-        ret_val.2,
-        ret_val.2,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21028,39 +20336,10 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
     transmute(vld3_dup_s16(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
-    let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21080,39 +20359,10 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
     transmute(vld3q_dup_s16(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
-    let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21132,39 +20382,10 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
     transmute(vld3_dup_s32(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
-    let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21184,39 +20405,10 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
     transmute(vld3q_dup_s32(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
-    let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21236,39 +20428,10 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
     transmute(vld3_dup_s8(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
-    let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21288,51 +20451,10 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
     transmute(vld3q_dup_s8(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
-    let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(
-        ret_val.0,
-        ret_val.0,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.1 = simd_shuffle!(
-        ret_val.1,
-        ret_val.1,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.2 = simd_shuffle!(
-        ret_val.2,
-        ret_val.2,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21352,39 +20474,10 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
     transmute(vld3_dup_s16(transmute(a)))
 }
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
-    let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
@@ -21403,34 +20496,6 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
     transmute(vld3q_dup_s16(transmute(a)))
 }
-#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld3r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
-    let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
@@ -23161,7 +22226,6 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23181,40 +22245,10 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
     transmute(vld4_dup_s8(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
-    let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23234,56 +22268,10 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
     transmute(vld4q_dup_s8(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
-    let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(
-        ret_val.0,
-        ret_val.0,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.1 = simd_shuffle!(
-        ret_val.1,
-        ret_val.1,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.2 = simd_shuffle!(
-        ret_val.2,
-        ret_val.2,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.3 = simd_shuffle!(
-        ret_val.3,
-        ret_val.3,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23303,40 +22291,10 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
     transmute(vld4_dup_s16(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
-    let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23356,40 +22314,10 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
     transmute(vld4q_dup_s16(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
-    let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23409,40 +22337,10 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
     transmute(vld4_dup_s32(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
-    let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23462,40 +22360,10 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
     transmute(vld4q_dup_s32(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
-    let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23515,40 +22383,10 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
     transmute(vld4_dup_s8(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
-    let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23568,56 +22406,10 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
     transmute(vld4q_dup_s8(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
-    let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
-    ret_val.0 = simd_shuffle!(
-        ret_val.0,
-        ret_val.0,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.1 = simd_shuffle!(
-        ret_val.1,
-        ret_val.1,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.2 = simd_shuffle!(
-        ret_val.2,
-        ret_val.2,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val.3 = simd_shuffle!(
-        ret_val.3,
-        ret_val.3,
-        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
-    );
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23637,40 +22429,10 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
     transmute(vld4_dup_s16(transmute(a)))
 }
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
-    let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]);
-    ret_val
-}
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon intrinsic unsafe"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -23689,35 +22451,6 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
     transmute(vld4q_dup_s16(transmute(a)))
 }
-#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
-#[doc = "## Safety"]
-#[doc = "  * Neon intrinsic unsafe"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld4r)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
-    let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
-    ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.2 = simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val.3 = simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-    ret_val
-}
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
@@ -38584,7 +37317,6 @@ pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -38604,36 +37336,8 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
     unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) }
 }
 #[doc = "Rounding Add returning High Narrow."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(raddhn)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -38653,36 +37357,8 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
     unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) }
 }
 #[doc = "Rounding Add returning High Narrow."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(raddhn)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -38701,33 +37377,6 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
     unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) }
 }
-#[doc = "Rounding Add returning High Narrow."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(raddhn)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
-    unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
-        let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
 #[inline]
@@ -56131,7 +54780,6 @@ pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -56151,36 +54799,8 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
     unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) }
 }
 #[doc = "Rounding subtract returning high narrow"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(rsubhn)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -56200,36 +54820,8 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
     unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) }
 }
 #[doc = "Rounding subtract returning high narrow"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(rsubhn)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
-    unsafe {
-        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
-        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
-        let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
-    }
-}
-#[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -56248,33 +54840,6 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
     unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) }
 }
-#[doc = "Rounding subtract returning high narrow"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
-#[cfg_attr(
-    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(rsubhn)
-)]
-#[cfg_attr(
-    not(target_arch = "arm"),
-    stable(feature = "neon_intrinsics", since = "1.59.0")
-)]
-#[cfg_attr(
-    target_arch = "arm",
-    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-)]
-pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
-    unsafe {
-        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
-        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
-        let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [1, 0])
-    }
-}
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
 #[inline]
@@ -68016,7 +66581,6 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68026,26 +66590,8 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68055,23 +66601,6 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
 #[inline]
 #[target_feature(enable = "neon")]
@@ -68100,7 +66629,6 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68110,28 +66638,8 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x8x2_t = a;
-    unsafe {
-        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68141,25 +66649,6 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x8x2_t = a;
-    unsafe {
-        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
 #[inline]
 #[target_feature(enable = "neon")]
@@ -68188,7 +66677,6 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68205,34 +66693,8 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x8x3_t = a;
-    unsafe {
-        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbl3(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(b),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68249,31 +66711,6 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x8x3_t = a;
-    unsafe {
-        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbl3(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(b),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
 #[inline]
 #[target_feature(enable = "neon")]
@@ -68302,7 +66739,6 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68320,36 +66756,8 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
-    let mut a: uint8x8x4_t = a;
-    unsafe {
-        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbl4(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(a.3),
-            transmute(b),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68366,33 +66774,6 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
         ))
     }
 }
-#[doc = "Table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[cfg(target_arch = "arm")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbl))]
-pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
-    let mut a: poly8x8x4_t = a;
-    unsafe {
-        a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbl4(
-            transmute(a.0),
-            transmute(a.1),
-            transmute(a.2),
-            transmute(a.3),
-            transmute(b),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
 #[inline]
@@ -68420,7 +66801,6 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68429,26 +66809,8 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
     unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68457,23 +66819,6 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
     unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
 #[inline]
 #[target_feature(enable = "neon,v7")]
@@ -68500,7 +66845,6 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68516,33 +66860,8 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x8x2_t = b;
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbx2(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(c),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68558,30 +66877,6 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x8x2_t = b;
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbx2(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(c),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
 #[inline]
 #[target_feature(enable = "neon,v7")]
@@ -68608,7 +66903,6 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68625,35 +66919,8 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x8x3_t = b;
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbx3(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(c),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68670,32 +66937,6 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x8x3_t = b;
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbx3(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(c),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
 #[inline]
 #[target_feature(enable = "neon,v7")]
@@ -68767,7 +67008,6 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68785,37 +67025,8 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
     }
 }
 #[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
-    let mut b: uint8x8x4_t = b;
-    unsafe {
-        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: uint8x8_t = transmute(vtbx4(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(b.3),
-            transmute(c),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
-#[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68832,34 +67043,6 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
         ))
     }
 }
-#[doc = "Extended table look-up"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon,v7")]
-#[cfg(target_arch = "arm")]
-#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
-#[cfg_attr(test, assert_instr(vtbx))]
-pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
-    let mut b: poly8x8x4_t = b;
-    unsafe {
-        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]);
-        b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
-        let ret_val: poly8x8_t = transmute(vtbx4(
-            transmute(a),
-            transmute(b.0),
-            transmute(b.1),
-            transmute(b.2),
-            transmute(b.3),
-            transmute(c),
-        ));
-        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
-    }
-}
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
 #[inline]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 0a466dda71..b47a8b1805 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -3595,7 +3595,6 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
     assert_instr: [ld2]
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -3942,7 +3941,6 @@ intrinsics:
     arguments: ["a: {type[0]}"]
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     assert_instr: [ld3]
@@ -4081,7 +4079,6 @@ intrinsics:
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
     assert_instr: [ld4]
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4189,7 +4186,6 @@ intrinsics:
       - *neon-stable
     static_defs:
       - "const LANE: i32"
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4239,7 +4235,6 @@ intrinsics:
       - *neon-stable
     static_defs:
       - "const LANE: i32"
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -8530,7 +8525,6 @@ intrinsics:
     attr: [*neon-stable]
     assert_instr: [nop]
     safety: safe
-    big_endian_inverse: false
     types:
       - [poly64x1_t, int64x1_t]
       - [poly64x1_t, uint64x1_t]
@@ -8562,6 +8556,7 @@ intrinsics:
     attr: [*neon-stable]
     assert_instr: [nop]
     safety: safe
+    big_endian_inverse: true
     types:
       - [float64x1_t, int8x8_t]
       - [float64x1_t, int16x4_t]
@@ -8618,6 +8613,7 @@ intrinsics:
       - *target-not-arm64ec
     assert_instr: [nop]
     safety: safe
+    big_endian_inverse: true
     types:
       - [float64x1_t, float16x4_t]
       - [float16x4_t, float64x1_t]
@@ -8979,6 +8975,7 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
       - *neon-stable
     safety: safe
+    big_endian_inverse: true
     types:
       - ["u64", float64x1_t]
     compose:
@@ -12015,7 +12012,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [int8x8_t, 'int8x8x4_t', 'int8x16x2', 'int8x8', 'i8x8::splat(32)']
@@ -12046,7 +12042,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x8x4_t', 'uint8x8_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(32)']
@@ -12079,7 +12074,6 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    big_endian_inverse: false
     types:
       - [int8x8_t, 'int8x8_t', 'unsafe {{ transmute(b) }}']
       - [uint8x8_t, 'uint8x8_t', 'b']
@@ -12100,7 +12094,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['int8x8x2_t',  'int8x8_t',  'int8x8_t']
@@ -12117,7 +12110,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x8x2_t', 'uint8x8_t', 'uint8x8_t']
@@ -12136,7 +12128,6 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    big_endian_inverse: false
     types:
       - ['int8x8x3_t', 'int8x8_t', 'int8x8_t', 'int8x16x2']
     compose:
@@ -12160,7 +12151,6 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    big_endian_inverse: false
     types:
       - [uint8x8x3_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2']
       - [poly8x8x3_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2']
@@ -12184,7 +12174,6 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    big_endian_inverse: false
     types:
       - ['int8x8x4_t', 'int8x8_t', 'int8x8_t', 'int8x16x2']
     compose:
@@ -12207,7 +12196,6 @@ intrinsics:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
     safety: safe
-    big_endian_inverse: false
     types:
       - [uint8x8x4_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2']
       - [poly8x8x4_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2']
@@ -12250,7 +12238,6 @@ intrinsics:
       - [poly8x8_t, "poly8x16_t", uint8x8_t, "vqtbx1", "_p8"]
       - [uint8x16_t, "uint8x16_t", uint8x16_t, "vqtbx1q", "q_u8"]
       - [poly8x16_t, "poly8x16_t", uint8x16_t, "vqtbx1q", "q_p8"]
-    big_endian_inverse: false
     compose:
       - FnCall:
           - transmute
@@ -12267,7 +12254,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [int8x8_t, "int8x8_t", "int8x8", "i8x8::splat(8)"]
@@ -12292,7 +12278,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"]
@@ -12318,7 +12303,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [int8x8_t, 'int8x8x2_t', 'int8x8', 'i8x8::splat(16)']
@@ -12343,7 +12327,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)']
@@ -12369,7 +12352,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'int8x8', 'i8x8::splat(24)']
@@ -12400,7 +12382,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(24)']
@@ -12452,7 +12433,6 @@ intrinsics:
       - ['poly8x16_t', uint8x8_t, 'vqtbl1', 'poly8x8_t']
       - ['uint8x16_t', uint8x16_t, 'vqtbl1q', 'uint8x16_t']
       - ['poly8x16_t', uint8x16_t, 'vqtbl1q', 'poly8x16_t']
-    big_endian_inverse: false
     compose:
       - FnCall:
           - transmute
@@ -12482,7 +12462,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t']
@@ -12519,7 +12498,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2']
@@ -12543,7 +12521,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3']
@@ -12558,7 +12535,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3']
@@ -12596,7 +12572,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3']
@@ -12621,7 +12596,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t']
@@ -12636,7 +12610,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t']
@@ -12675,7 +12648,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4']
@@ -12740,7 +12712,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t]
@@ -12760,7 +12731,6 @@ intrinsics:
     attr:
       - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]]
       - *neon-stable
-    big_endian_inverse: false
     safety: safe
     types:
       - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index b668308034..18b4b2afa7 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -2685,7 +2685,6 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -2744,7 +2743,6 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -2982,7 +2980,6 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -3013,7 +3010,6 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -3110,7 +3106,6 @@ intrinsics:
       - *neon-cfg-arm-unstable
     static_defs:
       - "const LANE: i32"
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4099,7 +4094,6 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     static_defs: ['const LANE: i32']
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4130,7 +4124,6 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4494,7 +4487,6 @@ intrinsics:
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -4616,7 +4608,6 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     static_defs: ["const LANE: i32"]
-    big_endian_inverse: false
     safety:
       unsafe: [neon]
     types:
@@ -8476,7 +8467,6 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
-    big_endian_inverse: false
     types:
       - [p128, int64x2_t]
       - [p128, uint64x2_t]
@@ -8504,6 +8494,7 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
+    big_endian_inverse: true
     types:
       - [poly64x1_t, int32x2_t]
       - [poly64x1_t, uint32x2_t]
@@ -8743,7 +8734,6 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
-    big_endian_inverse: false
     types:
       - [uint8x8_t, int8x8_t]
       - [poly8x8_t, int8x8_t]
@@ -8800,6 +8790,7 @@ intrinsics:
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
+    big_endian_inverse: true
     types:
       # non-q
       - [float32x2_t, float16x4_t]
@@ -8851,7 +8842,6 @@ intrinsics:
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
-    big_endian_inverse: false
     types:
       # non-q
       - [poly16x4_t, float16x4_t]
@@ -8883,6 +8873,7 @@ intrinsics:
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
+    big_endian_inverse: true
     types:
       - [poly64x1_t, float16x4_t]
       - [float16x4_t, poly64x1_t]
@@ -9196,6 +9187,7 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
+    big_endian_inverse: true
     types:
       - ["u64", int8x8_t]
       - ["u64", int16x4_t]
@@ -9224,6 +9216,7 @@ intrinsics:
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec
     safety: safe
+    big_endian_inverse: true
     types:
       - ["u64", float16x4_t]
     compose:
@@ -9241,6 +9234,7 @@ intrinsics:
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
+    big_endian_inverse: true
     types:
       - ["u64", poly64x1_t]
     compose:
@@ -13313,7 +13307,6 @@ intrinsics:
     doc: "Add pairwise."
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[0]}"
-    big_endian_inverse: false
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vpadd]]}]]
@@ -14338,7 +14331,6 @@ intrinsics:
     doc: "Load one single-element structure and Replicate to all lanes (of one register)."
     arguments: ["ptr: {type[1]}"]
     return_type: "{neon_type[2]}"
-    big_endian_inverse: false
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['"{type[3]}"']] }  ]]
diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs
index dc467fd307..72fb97fee1 100644
--- a/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1059,23 +1059,8 @@ impl Intrinsic {
 
     /// Add a big endian implementation
     fn generate_big_endian(&self, variant: &mut Intrinsic) {
-        /* We can't always blindly reverse the bits only in certain conditions
-         * do we need a different order - thus this allows us to have the
-         * ability to do so without having to play codegolf with the yaml AST */
-        let should_reverse = {
-            if let Some(should_reverse) = variant.big_endian_inverse {
-                should_reverse
-            } else if variant.compose.len() == 1 {
-                match &variant.compose[0] {
-                    Expression::FnCall(fn_call) => fn_call.0.to_string() == "transmute",
-                    _ => false,
-                }
-            } else {
-                false
-            }
-        };
-
-        if !should_reverse {
+        // We only reverse if it was specifically requested
+        if !variant.big_endian_inverse.unwrap_or(false) {
             return;
         }
 

From 2abbb6c8541e562a172bc42d881dc337868f66b4 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Sun, 10 May 2026 07:25:39 +0530
Subject: [PATCH 317/326] Revert "Change implementation of `vld1_dup`"

This reverts commit 5f676a53f584e6304985345791525fa06bb9130e.
---
 crates/core_arch/src/arm_shared/neon/generated.rs    |  8 ++++----
 crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml | 10 +++++-----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs
index 476d8e78a2..6c300921d3 100644
--- a/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -14614,8 +14614,8 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
-    let x = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
-    vdup_lane_f16::<0>(x)
+    let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
+    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and replicate to all lanes of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
@@ -14633,8 +14633,8 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
 pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
-    let x = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
-    vdupq_laneq_f16::<0>(x)
+    let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
+    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 1f7e1f6987..19c35a5895 100644
--- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -2835,7 +2835,7 @@ intrinsics:
       - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']]
       - FnCall: [simd_insert!, [src, "LANE as u32", "*ptr"]]
 
-  - name: "vld1{neon_type[1].dup_nox}"
+  - name: "vld1{type[2]}_{neon_type[1]}"
     doc: "Load one single-element structure and replicate to all lanes of one register"
     arguments: ["ptr: {type[0]}"]
     return_type: "{neon_type[1]}"
@@ -2849,11 +2849,11 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ["*const f16", float16x4_t, '_lane', 'f16x4']
-      - ["*const f16", float16x8_t, 'q_laneq', 'f16x8']
+      - ["*const f16", float16x4_t, '_dup', 'f16x4', "[0, 0, 0, 0]"]
+      - ["*const f16", float16x8_t, 'q_dup', 'f16x8', "[0, 0, 0, 0, 0, 0, 0, 0]"]
     compose:
-      - Let: [x, {FnCall: ["vld1{neon_type[1].lane_nox}", [ptr, {FnCall: [transmute, ["{type[3]}::splat(0.0)"]]}], [0]]}]
-      - FnCall: ['vdup{type[2]}_{neon_type[1]}', [x], [0]]
+      - Let: [x, "{neon_type[1]}", "vld1{neon_type[1].lane_nox}::<0>(ptr, transmute({type[3]}::splat(0.0)))"]
+      - FnCall: [simd_shuffle!, [x, x, "{type[4]}"]]
 
 
   - name: "vld2{neon_type[1].nox}"

From e70189fd7f9b8a1d2b322c67938f6086077cd7c3 Mon Sep 17 00:00:00 2001
From: Amanieu d'Antras <amanieu@gmail.com>
Date: Sun, 10 May 2026 18:56:44 +0100
Subject: [PATCH 318/326] Add davidtwco and adamgemmell as maintainers

---
 triagebot.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/triagebot.toml b/triagebot.toml
index 621f39b2cb..5b178f0cdf 100644
--- a/triagebot.toml
+++ b/triagebot.toml
@@ -1,7 +1,7 @@
 [assign]
 
 [assign.owners]
-"*" = ["@Amanieu", "@folkertdev", "@sayantn"]
+"*" = ["@Amanieu", "@folkertdev", "@sayantn", "@davidtwco", "@adamgemmell"]
 
 [ping.windows]
 message = """\

From 56b50d3d8b941a94263ba4d9cb88c4f01ce7e740 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui@loongson.cn>
Date: Wed, 6 May 2026 22:05:30 +0800
Subject: [PATCH 319/326] loongarch: Use `intrinsics::simd` for vabsd

---
 .../src/loongarch64/lasx/generated.rs         | 72 -------------------
 .../src/loongarch64/lasx/portable.rs          |  8 +++
 .../src/loongarch64/lsx/generated.rs          | 72 -------------------
 .../core_arch/src/loongarch64/lsx/portable.rs |  8 +++
 crates/core_arch/src/loongarch64/simd.rs      |  7 ++
 crates/stdarch-gen-loongarch/lasx.spec        |  8 +++
 crates/stdarch-gen-loongarch/lsx.spec         |  8 +++
 .../src/portable-intrinsics.txt               | 16 +++++
 8 files changed, 55 insertions(+), 144 deletions(-)

diff --git a/crates/core_arch/src/loongarch64/lasx/generated.rs b/crates/core_arch/src/loongarch64/lasx/generated.rs
index 5ef7132637..f8667887c7 100644
--- a/crates/core_arch/src/loongarch64/lasx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lasx/generated.rs
@@ -123,22 +123,6 @@ unsafe extern "unadjusted" {
     fn __lasx_xvavgr_wu(a: __v8u32, b: __v8u32) -> __v8u32;
     #[link_name = "llvm.loongarch.lasx.xvavgr.du"]
     fn __lasx_xvavgr_du(a: __v4u64, b: __v4u64) -> __v4u64;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.b"]
-    fn __lasx_xvabsd_b(a: __v32i8, b: __v32i8) -> __v32i8;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.h"]
-    fn __lasx_xvabsd_h(a: __v16i16, b: __v16i16) -> __v16i16;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.w"]
-    fn __lasx_xvabsd_w(a: __v8i32, b: __v8i32) -> __v8i32;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.d"]
-    fn __lasx_xvabsd_d(a: __v4i64, b: __v4i64) -> __v4i64;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.bu"]
-    fn __lasx_xvabsd_bu(a: __v32u8, b: __v32u8) -> __v32u8;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.hu"]
-    fn __lasx_xvabsd_hu(a: __v16u16, b: __v16u16) -> __v16u16;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.wu"]
-    fn __lasx_xvabsd_wu(a: __v8u32, b: __v8u32) -> __v8u32;
-    #[link_name = "llvm.loongarch.lasx.xvabsd.du"]
-    fn __lasx_xvabsd_du(a: __v4u64, b: __v4u64) -> __v4u64;
     #[link_name = "llvm.loongarch.lasx.xvhaddw.h.b"]
     fn __lasx_xvhaddw_h_b(a: __v32i8, b: __v32i8) -> __v16i16;
     #[link_name = "llvm.loongarch.lasx.xvhaddw.w.h"]
@@ -1549,62 +1533,6 @@ pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i {
     unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lasx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i {
-    unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lasx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lasx/portable.rs b/crates/core_arch/src/loongarch64/lasx/portable.rs
index 366deda0c1..8953558210 100644
--- a/crates/core_arch/src/loongarch64/lasx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lasx/portable.rs
@@ -152,6 +152,14 @@ impl_vvv!("lasx", lasx_xvadda_b, ls::simd_adda, m256i, i8x32);
 impl_vvv!("lasx", lasx_xvadda_h, ls::simd_adda, m256i, i16x16);
 impl_vvv!("lasx", lasx_xvadda_w, ls::simd_adda, m256i, i32x8);
 impl_vvv!("lasx", lasx_xvadda_d, ls::simd_adda, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvabsd_b, ls::simd_absd, m256i, i8x32);
+impl_vvv!("lasx", lasx_xvabsd_h, ls::simd_absd, m256i, i16x16);
+impl_vvv!("lasx", lasx_xvabsd_w, ls::simd_absd, m256i, i32x8);
+impl_vvv!("lasx", lasx_xvabsd_d, ls::simd_absd, m256i, i64x4);
+impl_vvv!("lasx", lasx_xvabsd_bu, ls::simd_absd, m256i, u8x32);
+impl_vvv!("lasx", lasx_xvabsd_hu, ls::simd_absd, m256i, u16x16);
+impl_vvv!("lasx", lasx_xvabsd_wu, ls::simd_absd, m256i, u32x8);
+impl_vvv!("lasx", lasx_xvabsd_du, ls::simd_absd, m256i, u64x4);
 
 impl_vuv!("lasx", lasx_xvslli_b, is::simd_shl, m256i, i8x32);
 impl_vuv!("lasx", lasx_xvslli_h, is::simd_shl, m256i, i16x16);
diff --git a/crates/core_arch/src/loongarch64/lsx/generated.rs b/crates/core_arch/src/loongarch64/lsx/generated.rs
index 1df46a43fe..41ced43454 100644
--- a/crates/core_arch/src/loongarch64/lsx/generated.rs
+++ b/crates/core_arch/src/loongarch64/lsx/generated.rs
@@ -123,22 +123,6 @@ unsafe extern "unadjusted" {
     fn __lsx_vavgr_wu(a: __v4u32, b: __v4u32) -> __v4u32;
     #[link_name = "llvm.loongarch.lsx.vavgr.du"]
     fn __lsx_vavgr_du(a: __v2u64, b: __v2u64) -> __v2u64;
-    #[link_name = "llvm.loongarch.lsx.vabsd.b"]
-    fn __lsx_vabsd_b(a: __v16i8, b: __v16i8) -> __v16i8;
-    #[link_name = "llvm.loongarch.lsx.vabsd.h"]
-    fn __lsx_vabsd_h(a: __v8i16, b: __v8i16) -> __v8i16;
-    #[link_name = "llvm.loongarch.lsx.vabsd.w"]
-    fn __lsx_vabsd_w(a: __v4i32, b: __v4i32) -> __v4i32;
-    #[link_name = "llvm.loongarch.lsx.vabsd.d"]
-    fn __lsx_vabsd_d(a: __v2i64, b: __v2i64) -> __v2i64;
-    #[link_name = "llvm.loongarch.lsx.vabsd.bu"]
-    fn __lsx_vabsd_bu(a: __v16u8, b: __v16u8) -> __v16u8;
-    #[link_name = "llvm.loongarch.lsx.vabsd.hu"]
-    fn __lsx_vabsd_hu(a: __v8u16, b: __v8u16) -> __v8u16;
-    #[link_name = "llvm.loongarch.lsx.vabsd.wu"]
-    fn __lsx_vabsd_wu(a: __v4u32, b: __v4u32) -> __v4u32;
-    #[link_name = "llvm.loongarch.lsx.vabsd.du"]
-    fn __lsx_vabsd_du(a: __v2u64, b: __v2u64) -> __v2u64;
     #[link_name = "llvm.loongarch.lsx.vhaddw.h.b"]
     fn __lsx_vhaddw_h_b(a: __v16i8, b: __v16i8) -> __v8i16;
     #[link_name = "llvm.loongarch.lsx.vhaddw.w.h"]
@@ -1461,62 +1445,6 @@ pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i {
     unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) }
 }
 
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) }
-}
-
-#[inline]
-#[target_feature(enable = "lsx")]
-#[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i {
-    unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) }
-}
-
 #[inline]
 #[target_feature(enable = "lsx")]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
diff --git a/crates/core_arch/src/loongarch64/lsx/portable.rs b/crates/core_arch/src/loongarch64/lsx/portable.rs
index 55d349142e..16f0058235 100644
--- a/crates/core_arch/src/loongarch64/lsx/portable.rs
+++ b/crates/core_arch/src/loongarch64/lsx/portable.rs
@@ -152,6 +152,14 @@ impl_vvv!("lsx", lsx_vadda_b, ls::simd_adda, m128i, i8x16);
 impl_vvv!("lsx", lsx_vadda_h, ls::simd_adda, m128i, i16x8);
 impl_vvv!("lsx", lsx_vadda_w, ls::simd_adda, m128i, i32x4);
 impl_vvv!("lsx", lsx_vadda_d, ls::simd_adda, m128i, i64x2);
+impl_vvv!("lsx", lsx_vabsd_b, ls::simd_absd, m128i, i8x16);
+impl_vvv!("lsx", lsx_vabsd_h, ls::simd_absd, m128i, i16x8);
+impl_vvv!("lsx", lsx_vabsd_w, ls::simd_absd, m128i, i32x4);
+impl_vvv!("lsx", lsx_vabsd_d, ls::simd_absd, m128i, i64x2);
+impl_vvv!("lsx", lsx_vabsd_bu, ls::simd_absd, m128i, u8x16);
+impl_vvv!("lsx", lsx_vabsd_hu, ls::simd_absd, m128i, u16x8);
+impl_vvv!("lsx", lsx_vabsd_wu, ls::simd_absd, m128i, u32x4);
+impl_vvv!("lsx", lsx_vabsd_du, ls::simd_absd, m128i, u64x2);
 
 impl_vuv!("lsx", lsx_vslli_b, is::simd_shl, m128i, i8x16);
 impl_vuv!("lsx", lsx_vslli_h, is::simd_shl, m128i, i16x8);
diff --git a/crates/core_arch/src/loongarch64/simd.rs b/crates/core_arch/src/loongarch64/simd.rs
index ccad4b8c48..b4ec6881c3 100644
--- a/crates/core_arch/src/loongarch64/simd.rs
+++ b/crates/core_arch/src/loongarch64/simd.rs
@@ -52,6 +52,13 @@ pub(crate) const unsafe fn simd_abs<T: Copy + const SimdExt>(a: T) -> T {
     is::simd_select(m, is::simd_neg(a), a)
 }
 
+#[inline(always)]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+pub(crate) const unsafe fn simd_absd<T: Copy>(a: T, b: T) -> T {
+    let m: T = is::simd_gt(a, b);
+    is::simd_select(m, is::simd_sub(a, b), is::simd_sub(b, a))
+}
+
 #[inline(always)]
 #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const unsafe fn simd_adda<T: Copy + const SimdExt>(a: T, b: T) -> T {
diff --git a/crates/stdarch-gen-loongarch/lasx.spec b/crates/stdarch-gen-loongarch/lasx.spec
index 07f2ed49d3..ae69f19410 100644
--- a/crates/stdarch-gen-loongarch/lasx.spec
+++ b/crates/stdarch-gen-loongarch/lasx.spec
@@ -1124,41 +1124,49 @@ asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
 
 /// lasx_xvabsd_b
+impl = portable
 name = lasx_xvabsd_b
 asm-fmts = xd, xj, xk
 data-types = V32QI, V32QI, V32QI
 
 /// lasx_xvabsd_h
+impl = portable
 name = lasx_xvabsd_h
 asm-fmts = xd, xj, xk
 data-types = V16HI, V16HI, V16HI
 
 /// lasx_xvabsd_w
+impl = portable
 name = lasx_xvabsd_w
 asm-fmts = xd, xj, xk
 data-types = V8SI, V8SI, V8SI
 
 /// lasx_xvabsd_d
+impl = portable
 name = lasx_xvabsd_d
 asm-fmts = xd, xj, xk
 data-types = V4DI, V4DI, V4DI
 
 /// lasx_xvabsd_bu
+impl = portable
 name = lasx_xvabsd_bu
 asm-fmts = xd, xj, xk
 data-types = UV32QI, UV32QI, UV32QI
 
 /// lasx_xvabsd_hu
+impl = portable
 name = lasx_xvabsd_hu
 asm-fmts = xd, xj, xk
 data-types = UV16HI, UV16HI, UV16HI
 
 /// lasx_xvabsd_wu
+impl = portable
 name = lasx_xvabsd_wu
 asm-fmts = xd, xj, xk
 data-types = UV8SI, UV8SI, UV8SI
 
 /// lasx_xvabsd_du
+impl = portable
 name = lasx_xvabsd_du
 asm-fmts = xd, xj, xk
 data-types = UV4DI, UV4DI, UV4DI
diff --git a/crates/stdarch-gen-loongarch/lsx.spec b/crates/stdarch-gen-loongarch/lsx.spec
index 0b32dd83c7..48e98d59b6 100644
--- a/crates/stdarch-gen-loongarch/lsx.spec
+++ b/crates/stdarch-gen-loongarch/lsx.spec
@@ -1124,41 +1124,49 @@ asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
 
 /// lsx_vabsd_b
+impl = portable
 name = lsx_vabsd_b
 asm-fmts = vd, vj, vk
 data-types = V16QI, V16QI, V16QI
 
 /// lsx_vabsd_h
+impl = portable
 name = lsx_vabsd_h
 asm-fmts = vd, vj, vk
 data-types = V8HI, V8HI, V8HI
 
 /// lsx_vabsd_w
+impl = portable
 name = lsx_vabsd_w
 asm-fmts = vd, vj, vk
 data-types = V4SI, V4SI, V4SI
 
 /// lsx_vabsd_d
+impl = portable
 name = lsx_vabsd_d
 asm-fmts = vd, vj, vk
 data-types = V2DI, V2DI, V2DI
 
 /// lsx_vabsd_bu
+impl = portable
 name = lsx_vabsd_bu
 asm-fmts = vd, vj, vk
 data-types = UV16QI, UV16QI, UV16QI
 
 /// lsx_vabsd_hu
+impl = portable
 name = lsx_vabsd_hu
 asm-fmts = vd, vj, vk
 data-types = UV8HI, UV8HI, UV8HI
 
 /// lsx_vabsd_wu
+impl = portable
 name = lsx_vabsd_wu
 asm-fmts = vd, vj, vk
 data-types = UV4SI, UV4SI, UV4SI
 
 /// lsx_vabsd_du
+impl = portable
 name = lsx_vabsd_du
 asm-fmts = vd, vj, vk
 data-types = UV2DI, UV2DI, UV2DI
diff --git a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
index 6e3e5fe32e..e9b7b04f27 100644
--- a/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
+++ b/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt
@@ -223,6 +223,14 @@ lsx_vadda_b
 lsx_vadda_h
 lsx_vadda_w
 lsx_vadda_d
+lsx_vabsd_b
+lsx_vabsd_h
+lsx_vabsd_w
+lsx_vabsd_d
+lsx_vabsd_bu
+lsx_vabsd_hu
+lsx_vabsd_wu
+lsx_vabsd_du
 
 # LASX intrinsics
 lasx_xvsll_b
@@ -443,3 +451,11 @@ lasx_xvadda_b
 lasx_xvadda_h
 lasx_xvadda_w
 lasx_xvadda_d
+lasx_xvabsd_b
+lasx_xvabsd_h
+lasx_xvabsd_w
+lasx_xvabsd_d
+lasx_xvabsd_bu
+lasx_xvabsd_hu
+lasx_xvabsd_wu
+lasx_xvabsd_du

From 1316fe8b9241ee4f5d9be5ae1cccced038ab6314 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 11 May 2026 21:28:47 +0530
Subject: [PATCH 320/326] Correct small typo in gen-arm

---
 crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml | 14 ++++++--------
 crates/stdarch-gen-arm/src/fn_suffix.rs           |  2 +-
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index cfd44332ec..102447eae8 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -6131,7 +6131,7 @@ intrinsics:
           - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
       - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]]
 
-  - name: "vcmla{type[3]}"
+  - name: "vcmla{neon_type[0].rot180_lane}"
     doc: Floating-point complex multiply accumulate
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
@@ -6143,8 +6143,8 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f32']
-      - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f32']
+      - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
       - Let:
@@ -6153,7 +6153,7 @@ intrinsics:
           - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
       - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]]
 
-  - name: "vcmla{type[3]}"
+  - name: "vcmla{neon_type[0].rot180_lane}"
     doc: Floating-point complex multiply accumulate
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
@@ -6167,10 +6167,8 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f16']
-      - [float16x8_t, float16x4_t,
-          '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f16'
-        ]
+      - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
       - Let:
diff --git a/crates/stdarch-gen-arm/src/fn_suffix.rs b/crates/stdarch-gen-arm/src/fn_suffix.rs
index 26c156ae17..6fba3dc744 100644
--- a/crates/stdarch-gen-arm/src/fn_suffix.rs
+++ b/crates/stdarch-gen-arm/src/fn_suffix.rs
@@ -188,7 +188,7 @@ impl FromStr for SuffixKind {
             "rot90_lane" => Ok(SuffixKind::Rot90Lane),
             "rot90_laneq" => Ok(SuffixKind::Rot90LaneQ),
             "rot180" => Ok(SuffixKind::Rot180),
-            "rot180_lane" => Ok(SuffixKind::Rot180LaneQ),
+            "rot180_lane" => Ok(SuffixKind::Rot180Lane),
             "rot180_laneq" => Ok(SuffixKind::Rot180LaneQ),
             "u" => Ok(SuffixKind::Unsigned),
             "nox" => Ok(SuffixKind::NoX),

From 8a370d2091d8c61701b05c5df70efa8bc9aee101 Mon Sep 17 00:00:00 2001
From: sayantn <sayantn05@gmail.com>
Date: Mon, 11 May 2026 21:29:36 +0530
Subject: [PATCH 321/326] Implement `vcmla_lane` with ARM intrinsics

---
 .../core_arch/src/aarch64/neon/generated.rs   | 504 +++++-------------
 .../spec/neon/aarch64.spec.yml                | 172 +++---
 2 files changed, 208 insertions(+), 468 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index 11c3a52870..3241583cf0 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -3001,19 +3001,10 @@ pub fn vcmla_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdup_lane_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"]
@@ -3030,23 +3021,10 @@ pub fn vcmlaq_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdupq_lane_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"]
@@ -3061,10 +3039,10 @@ pub fn vcmla_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdup_lane_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"]
@@ -3079,19 +3057,10 @@ pub fn vcmlaq_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdupq_lane_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"]
@@ -3108,19 +3077,10 @@ pub fn vcmla_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdup_laneq_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"]
@@ -3137,23 +3097,10 @@ pub fn vcmlaq_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdupq_laneq_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"]
@@ -3168,10 +3115,10 @@ pub fn vcmla_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdup_laneq_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"]
@@ -3186,19 +3133,10 @@ pub fn vcmlaq_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdupq_laneq_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"]
@@ -3299,19 +3237,10 @@ pub fn vcmla_rot180_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_rot180_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdup_lane_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_rot180_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"]
@@ -3328,23 +3257,10 @@ pub fn vcmlaq_rot180_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot180_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdupq_lane_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_rot180_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"]
@@ -3359,10 +3275,10 @@ pub fn vcmla_rot180_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_rot180_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdup_lane_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_rot180_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"]
@@ -3377,19 +3293,10 @@ pub fn vcmlaq_rot180_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot180_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdupq_lane_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_rot180_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"]
@@ -3406,19 +3313,10 @@ pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_rot180_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdup_laneq_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_rot180_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"]
@@ -3435,23 +3333,10 @@ pub fn vcmlaq_rot180_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot180_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdupq_laneq_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_rot180_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"]
@@ -3466,10 +3351,10 @@ pub fn vcmla_rot180_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_rot180_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdup_laneq_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_rot180_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"]
@@ -3484,19 +3369,10 @@ pub fn vcmlaq_rot180_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot180_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdupq_laneq_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_rot180_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"]
@@ -3597,19 +3473,10 @@ pub fn vcmla_rot270_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_rot270_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdup_lane_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_rot270_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"]
@@ -3626,23 +3493,10 @@ pub fn vcmlaq_rot270_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot270_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdupq_lane_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_rot270_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"]
@@ -3657,10 +3511,10 @@ pub fn vcmla_rot270_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_rot270_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdup_lane_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_rot270_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"]
@@ -3675,19 +3529,10 @@ pub fn vcmlaq_rot270_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot270_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdupq_lane_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_rot270_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"]
@@ -3704,19 +3549,10 @@ pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_rot270_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdup_laneq_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_rot270_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"]
@@ -3733,23 +3569,10 @@ pub fn vcmlaq_rot270_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot270_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdupq_laneq_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_rot270_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"]
@@ -3764,10 +3587,10 @@ pub fn vcmla_rot270_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_rot270_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdup_laneq_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_rot270_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"]
@@ -3782,19 +3605,10 @@ pub fn vcmlaq_rot270_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot270_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdupq_laneq_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_rot270_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"]
@@ -3895,19 +3709,10 @@ pub fn vcmla_rot90_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_rot90_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdup_lane_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_rot90_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"]
@@ -3924,23 +3729,10 @@ pub fn vcmlaq_rot90_lane_f16<const LANE: i32>(
     c: float16x4_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot90_f16(a, b, c)
-    }
+    let c = vreinterpret_u32_f16(c);
+    let c = vdupq_lane_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_rot90_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"]
@@ -3955,10 +3747,10 @@ pub fn vcmla_rot90_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x2_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_rot90_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdup_lane_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_rot90_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"]
@@ -3973,19 +3765,10 @@ pub fn vcmlaq_rot90_lane_f32<const LANE: i32>(
     c: float32x2_t,
 ) -> float32x4_t {
     static_assert!(LANE == 0);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot90_f32(a, b, c)
-    }
+    let c = vreinterpret_u64_f32(c);
+    let c = vdupq_lane_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_rot90_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"]
@@ -4002,19 +3785,10 @@ pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x4_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmla_rot90_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdup_laneq_u32::<LANE>(c);
+    let c = vreinterpret_f16_u32(c);
+    vcmla_rot90_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"]
@@ -4031,23 +3805,10 @@ pub fn vcmlaq_rot90_laneq_f16<const LANE: i32>(
     c: float16x8_t,
 ) -> float16x8_t {
     static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: float16x8_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot90_f16(a, b, c)
-    }
+    let c = vreinterpretq_u32_f16(c);
+    let c = vdupq_laneq_u32::<LANE>(c);
+    let c = vreinterpretq_f16_u32(c);
+    vcmlaq_rot90_f16(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"]
@@ -4062,10 +3823,10 @@ pub fn vcmla_rot90_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x2_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]);
-        vcmla_rot90_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdup_laneq_u64::<LANE>(c);
+    let c = vreinterpret_f32_u64(c);
+    vcmla_rot90_f32(a, b, c)
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"]
@@ -4080,19 +3841,10 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
     c: float32x4_t,
 ) -> float32x4_t {
     static_assert_uimm_bits!(LANE, 1);
-    unsafe {
-        let c: float32x4_t = simd_shuffle!(
-            c,
-            c,
-            [
-                2 * LANE as u32,
-                2 * LANE as u32 + 1,
-                2 * LANE as u32,
-                2 * LANE as u32 + 1
-            ]
-        );
-        vcmlaq_rot90_f32(a, b, c)
-    }
+    let c = vreinterpretq_u64_f32(c);
+    let c = vdupq_laneq_u64::<LANE>(c);
+    let c = vreinterpretq_f32_u64(c);
+    vcmlaq_rot90_f32(a, b, c)
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"]
diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 102447eae8..2f7f2fc2b0 100644
--- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5914,14 +5914,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x4_t, '']
+      - [float32x4_t, float32x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].laneq_nox}"
@@ -5938,14 +5937,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x8_t, '']
+      - [float16x8_t, float16x8_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot90_laneq}"
@@ -5960,14 +5958,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x4_t, '']
+      - [float32x4_t, float32x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot90_laneq}"
@@ -5984,14 +5981,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x8_t, '']
+      - [float16x8_t, float16x8_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot90_lane}"
@@ -6006,14 +6002,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x2_t, '']
+      - [float32x4_t, float32x2_t, 'q']
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot90_lane}"
@@ -6030,14 +6025,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x4_t, '']
+      - [float16x8_t, float16x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]]
 
   - name: "vcmla{neon_type.rot180}"
@@ -6095,14 +6089,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x4_t, '']
+      - [float32x4_t, float32x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot180_laneq}"
@@ -6119,16 +6112,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x8_t,
-        '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'
-        ]
+      - [float16x4_t, float16x8_t, '']
+      - [float16x8_t, float16x8_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot180_lane}"
@@ -6143,14 +6133,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x2_t, '']
+      - [float32x4_t, float32x2_t, 'q']
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot180_lane}"
@@ -6167,14 +6156,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x4_t, '']
+      - [float16x8_t, float16x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot270_laneq}"
@@ -6189,14 +6177,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x4_t, '']
+      - [float32x4_t, float32x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot270_laneq}"
@@ -6213,14 +6200,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x8_t, '']
+      - [float16x8_t, float16x8_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].lane_nox}"
@@ -6235,14 +6221,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x2_t, '']
+      - [float32x4_t, float32x2_t, 'q']
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]]
 
 
@@ -6260,14 +6245,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x4_t, '']
+      - [float16x8_t, float16x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]
+      - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot270_lane}"
@@ -6282,11 +6266,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float32x2_t, float32x2_t, '']
+      - [float32x4_t, float32x2_t, 'q']
     compose:
       - FnCall: [static_assert!, ['LANE == 0']]
-      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}]
+      - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
   - name: "vcmla{neon_type[0].rot270_lane}"
@@ -6303,11 +6289,13 @@ intrinsics:
     static_defs: ["const LANE: i32"]
     safety: safe
     types:
-      - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
-      - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]']
+      - [float16x4_t, float16x4_t, '']
+      - [float16x8_t, float16x4_t, 'q']
     compose:
       - FnCall: [static_assert_uimm_bits!, [LANE, 1]]
-      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}]
+      - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}]
+      - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}]
+      - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
   - name: "vmax{neon_type.no}"

From 524cbfa5e617233869615d426e5dc87d2a3bbd38 Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Tue, 12 May 2026 09:14:34 +0200
Subject: [PATCH 322/326] zeroall/zeroupper *are* supported by Miri

---
 crates/core_arch/src/x86/avx.rs | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index 74fc2db13d..37fed5fe08 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -1097,6 +1097,9 @@ pub const fn _mm256_cvtsi256_si32(a: __m256i) -> i32 {
 
 /// Zeroes the contents of all XMM or YMM registers.
 ///
+/// This operation is purely a performance hint for the CPU and has no effect on the Abstract
+/// Machine state.
+///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_zeroall)
 #[inline]
 #[target_feature(enable = "avx")]
@@ -1109,6 +1112,9 @@ pub fn _mm256_zeroall() {
 /// Zeroes the upper 128 bits of all YMM registers;
 /// the lower 128-bits of the registers are unmodified.
 ///
+/// This operation is purely a performance hint for the CPU and has no effect on the Abstract
+/// Machine state.
+///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_zeroupper)
 #[inline]
 #[target_feature(enable = "avx")]
@@ -4007,13 +4013,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri
     fn test_mm256_zeroall() {
         _mm256_zeroall();
     }
 
     #[simd_test(enable = "avx")]
-    #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri
     fn test_mm256_zeroupper() {
         _mm256_zeroupper();
     }

From 55fd4106b28093fba86e9730ce61113e88cddaca Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Tue, 12 May 2026 09:14:53 +0200
Subject: [PATCH 323/326] Update/add comments for miri-ignored tests

---
 crates/core_arch/src/x86/avx.rs     | 6 +++---
 crates/core_arch/src/x86/avx512f.rs | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/crates/core_arch/src/x86/avx.rs b/crates/core_arch/src/x86/avx.rs
index 37fed5fe08..ef434205b5 100644
--- a/crates/core_arch/src/x86/avx.rs
+++ b/crates/core_arch/src/x86/avx.rs
@@ -4488,7 +4488,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
+    #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri
     fn test_mm256_stream_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = _mm256_undefined_si256();
@@ -4500,7 +4500,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
+    #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri
     fn test_mm256_stream_pd() {
         #[repr(align(32))]
         struct Memory {
@@ -4519,7 +4519,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
+    #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri
     fn test_mm256_stream_ps() {
         #[repr(align(32))]
         struct Memory {
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
index 94c4269c8f..66ea63b674 100644
--- a/crates/core_arch/src/x86/avx512f.rs
+++ b/crates/core_arch/src/x86/avx512f.rs
@@ -58246,7 +58246,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    #[cfg_attr(miri, ignore)]
+    #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri
     fn test_mm512_stream_ps() {
         #[repr(align(64))]
         struct Memory {
@@ -58265,7 +58265,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    #[cfg_attr(miri, ignore)]
+    #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri
     fn test_mm512_stream_pd() {
         #[repr(align(64))]
         struct Memory {
@@ -58284,7 +58284,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    #[cfg_attr(miri, ignore)]
+    #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri
     fn test_mm512_stream_si512() {
         #[repr(align(64))]
         struct Memory {

From 00f4315d858cd4d536facc478e2160332f15676f Mon Sep 17 00:00:00 2001
From: Ralf Jung <post@ralfj.de>
Date: Tue, 12 May 2026 09:53:34 +0200
Subject: [PATCH 324/326] explain ignore aarch64 tests

---
 crates/core_arch/src/aarch64/neon/mod.rs    | 4 ++--
 crates/core_arch/src/arm_shared/neon/mod.rs | 5 ++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs
index 7ce79671f7..c66702814c 100644
--- a/crates/core_arch/src/aarch64/neon/mod.rs
+++ b/crates/core_arch/src/aarch64/neon/mod.rs
@@ -789,7 +789,7 @@ mod tests {
     macro_rules! wide_store_load_roundtrip_fp16 {
         ($( $name:ident $args:tt);* $(;)?) => {
             $(
-                #[cfg_attr(miri, ignore)]
+                #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics
                 #[simd_test(enable = "neon,fp16")]
                 #[cfg(not(target_arch = "arm64ec"))]
                 unsafe fn $name() {
@@ -1060,7 +1060,7 @@ mod tests {
     macro_rules! lane_wide_store_load_roundtrip_neon {
         ($( $name:ident $args:tt);* $(;)?) => {
             $(
-                #[cfg_attr(miri, ignore)]
+                #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics
                 #[simd_test(enable = "neon")]
                 unsafe fn $name() {
                     lane_wide_store_load_roundtrip! $args;
diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs
index 12d3c090ed..4cc7f64f2d 100644
--- a/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -5248,11 +5248,10 @@ mod tests {
         };
     }
 
-    // Most of these are implemented with builtins, which miri can't handle
     macro_rules! lane_wide_store_load_roundtrip_neon {
         ($( $name:ident $args:tt);* $(;)?) => {
             $(
-                #[cfg_attr(miri, ignore)]
+                #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics
                 #[simd_test(enable = "neon")]
                 unsafe fn $name() {
                     lane_wide_store_load_roundtrip! $args;
@@ -5264,7 +5263,7 @@ mod tests {
     macro_rules! lane_wide_store_load_roundtrip_fp16 {
         ($( $name:ident $args:tt);* $(;)?) => {
             $(
-                #[cfg_attr(miri, ignore)]
+                #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics
                 #[simd_test(enable = "neon,fp16")]
                 #[cfg(not(target_arch = "arm64ec"))]
                 unsafe fn $name() {

From ae7f7143ac6c7f96c7c3726b59aa786660a94ec3 Mon Sep 17 00:00:00 2001
From: Reuben Cruise <reuben.cruise@arm.com>
Date: Thu, 14 May 2026 11:12:29 +0100
Subject: [PATCH 325/326] Revert "core_arch: disable ld/st tests on msvc"

This reverts commit ae9cb1c69c970b796a824bc4a69fc18f82642e82.
---
 crates/core_arch/src/aarch64/sve/mod.rs | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/crates/core_arch/src/aarch64/sve/mod.rs b/crates/core_arch/src/aarch64/sve/mod.rs
index 04a92359a0..a3f70ab61c 100644
--- a/crates/core_arch/src/aarch64/sve/mod.rs
+++ b/crates/core_arch/src/aarch64/sve/mod.rs
@@ -374,9 +374,6 @@ pub enum svprfop {
     SV_PSTL3STRM = 13,
 }
 
-// FIXME(arm-maintainers): On MSVC targets, it seemed like spurious corruption of the FFR was being
-// observed non-deterministically on CI. Disabling these tests out of caution on that platform until
-// it is investigated.
-#[cfg(all(test, not(target_env = "msvc")))]
+#[cfg(test)]
 #[path = "ld_st_tests_aarch64.rs"]
 mod ld_st_tests;

From aef7158f5af112c185e89ff0db7c2b20bb01f41e Mon Sep 17 00:00:00 2001
From: Reuben Cruise <reuben.cruise@arm.com>
Date: Mon, 18 May 2026 16:07:26 +0100
Subject: [PATCH 326/326] Minmal Reproducer

---
 .github/workflows/main.yml                    | 460 +++++++++---------
 Cargo.lock                                    |   4 +
 Cargo.toml                                    |   2 +-
 ci/run.sh                                     |   7 +-
 .../src/aarch64/sve/ld_st_tests_aarch64.rs    |   1 +
 minrepr/Cargo.toml                            |   6 +
 minrepr/src/lib.rs                            | 144 ++++++
 7 files changed, 389 insertions(+), 235 deletions(-)
 create mode 100644 minrepr/Cargo.toml
 create mode 100644 minrepr/src/lib.rs

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index b5dbefef4e..648b1d1b7e 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -4,70 +4,69 @@ on:
   merge_group:
 
 jobs:
-  style:
-    name: Check Style
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v6
-    - name: Install Rust
-      run: rustup update nightly --no-self-update && rustup default nightly
-    - run: ci/style.sh
-
-  docs:
-    name: Build Documentation
-    needs: [style]
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v6
-    - name: Install Rust
-      run: rustup update nightly --no-self-update && rustup default nightly
-    - run: ci/dox.sh
-      env:
-        CI: 1
-
-  verify:
-    name: Automatic intrinsic verification
-    needs: [style]
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v6
-    - name: Install Rust
-      run: rustup update nightly --no-self-update && rustup default nightly
-    - run: cargo test --manifest-path crates/stdarch-verify/Cargo.toml
+  # style:
+  #   name: Check Style
+  #   runs-on: ubuntu-latest
+  #   steps:
+  #   - uses: actions/checkout@v6
+  #   - name: Install Rust
+  #     run: rustup update nightly --no-self-update && rustup default nightly
+  #   - run: ci/style.sh
+  #
+  # docs:
+  #   name: Build Documentation
+  #   needs: [style]
+  #   runs-on: ubuntu-latest
+  #   steps:
+  #   - uses: actions/checkout@v6
+  #   - name: Install Rust
+  #     run: rustup update nightly --no-self-update && rustup default nightly
+  #   - run: ci/dox.sh
+  #     env:
+  #       CI: 1
+  #
+  # verify:
+  #   name: Automatic intrinsic verification
+  #   needs: [style]
+  #   runs-on: ubuntu-latest
+  #   steps:
+  #   - uses: actions/checkout@v6
+  #   - name: Install Rust
+  #     run: rustup update nightly --no-self-update && rustup default nightly
+  #   - run: cargo test --manifest-path crates/stdarch-verify/Cargo.toml
 
   test:
-    needs: [style]
     name: Test
     runs-on: ${{ matrix.target.os }}
     strategy:
       matrix:
         profile:
-        - dev
+        #- dev
         - release
         target:
         # Dockers that are run through docker on linux
-        - tuple: i686-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: x86_64-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: arm-unknown-linux-gnueabihf
-          os: ubuntu-latest
-        - tuple: armv7-unknown-linux-gnueabihf
-          os: ubuntu-latest
-        - tuple: aarch64-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: aarch64_be-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: riscv32gc-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: riscv64gc-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: powerpc-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: powerpc64-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: powerpc64le-unknown-linux-gnu
-          os: ubuntu-latest
+        # tuple: i686-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: x86_64-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: arm-unknown-linux-gnueabihf
+        # os: ubuntu-latest
+        # tuple: armv7-unknown-linux-gnueabihf
+        # os: ubuntu-latest
+        # tuple: aarch64-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: aarch64_be-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: riscv32gc-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: riscv64gc-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: powerpc-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: powerpc64-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: powerpc64le-unknown-linux-gnu
+        # os: ubuntu-latest
         # MIPS targets disabled since they are dropped to tier 3.
         # See https://github.com/rust-lang/compiler-team/issues/648
         #- tuple: mips-unknown-linux-gnu
@@ -78,108 +77,108 @@ jobs:
         #  os: ubuntu-latest
         #- tuple: mipsel-unknown-linux-musl
         #  os: ubuntu-latest
-        - tuple: s390x-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: i586-unknown-linux-gnu
-          os: ubuntu-latest
-        - tuple: nvptx64-nvidia-cuda
-          os: ubuntu-latest
-        - tuple: amdgcn-amd-amdhsa
-          os: ubuntu-latest
-        - tuple: thumbv6m-none-eabi
-          os: ubuntu-latest
-        - tuple: thumbv7m-none-eabi
-          os: ubuntu-latest
-        - tuple: thumbv7em-none-eabi
-          os: ubuntu-latest
-        - tuple: thumbv7em-none-eabihf
-          os: ubuntu-latest
-        - tuple: loongarch64-unknown-linux-gnu
-          os: ubuntu-latest
+        # tuple: s390x-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: i586-unknown-linux-gnu
+        # os: ubuntu-latest
+        # tuple: nvptx64-nvidia-cuda
+        # os: ubuntu-latest
+        # tuple: amdgcn-amd-amdhsa
+        # os: ubuntu-latest
+        # tuple: thumbv6m-none-eabi
+        # os: ubuntu-latest
+        # tuple: thumbv7m-none-eabi
+        # os: ubuntu-latest
+        # tuple: thumbv7em-none-eabi
+        # os: ubuntu-latest
+        # tuple: thumbv7em-none-eabihf
+        # os: ubuntu-latest
+        # tuple: loongarch64-unknown-linux-gnu
+        # os: ubuntu-latest
         # hexagon doesn't build at the moment due to a libc issue.
         # - tuple: hexagon-unknown-linux-musl
         #   os: ubuntu-latest
-        - tuple: wasm32-wasip1
-          os: ubuntu-latest
+        # tuple: wasm32-wasip1
+        # os: ubuntu-latest
 
         # macOS targets
-        - tuple: x86_64-apple-darwin
-          os: macos-15-intel
-        - tuple: x86_64-apple-ios-macabi
-          os: macos-15-intel
-        - tuple: aarch64-apple-darwin
-          os: macos-15
-        - tuple: aarch64-apple-ios-macabi
-          os: macos-15
+        # tuple: x86_64-apple-darwin
+        # os: macos-15-intel
+        # tuple: x86_64-apple-ios-macabi
+        # os: macos-15-intel
+        # tuple: aarch64-apple-darwin
+        # os: macos-15
+        # tuple: aarch64-apple-ios-macabi
+        # os: macos-15
         # FIXME: gh-actions build environment doesn't have linker support
         # - tuple: i686-apple-darwin
         #   os: macos-13
 
         # Windows targets
-        - tuple: x86_64-pc-windows-msvc
-          os: windows-2025
-        - tuple: i686-pc-windows-msvc
-          os: windows-2025
+        # tuple: x86_64-pc-windows-msvc
+        # os: windows-2025
+        # tuple: i686-pc-windows-msvc
+        # os: windows-2025
         - tuple: aarch64-pc-windows-msvc
           os: windows-11-arm
-        - tuple: arm64ec-pc-windows-msvc
-          os: windows-11-arm
-        - tuple: x86_64-pc-windows-gnu
-          os: windows-2025
+        # tuple: arm64ec-pc-windows-msvc
+        # os: windows-11-arm
+        # tuple: x86_64-pc-windows-gnu
+        # os: windows-2025
         # - tuple: i686-pc-windows-gnu
         #   os: windows-latest
 
         # Add additional variables to the matrix variations generated above using `include`:
-        include:
+        #nclude:
         # `TEST_EVERYTHING` setups - there should be at least 1 for each architecture
-        - target:
-            tuple: aarch64-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-        - target:
-            tuple: aarch64_be-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-          build_std: true
-        - target:
-            tuple: armv7-unknown-linux-gnueabihf
-            os: ubuntu-latest
-          test_everything: true
-        - target:
-            tuple: loongarch64-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-        - target:
-            tuple: powerpc-unknown-linux-gnu
-            os: ubuntu-latest
-          disable_assert_instr: true
-          test_everything: true
-        - target:
-            tuple: powerpc64-unknown-linux-gnu
-            os: ubuntu-latest
-          disable_assert_instr: true
-          test_everything: true
-        - target:
-            tuple: powerpc64le-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-        - target:
-            tuple: riscv32gc-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-          build_std: true
-        - target:
-            tuple: riscv64gc-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-        - target:
-            tuple: s390x-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
-        - target:
-            tuple: x86_64-unknown-linux-gnu
-            os: ubuntu-latest
-          test_everything: true
+        # target:
+        #   tuple: aarch64-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # target:
+        #   tuple: aarch64_be-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # build_std: true
+        # target:
+        #   tuple: armv7-unknown-linux-gnueabihf
+        #   os: ubuntu-latest
+        # test_everything: true
+        # target:
+        #   tuple: loongarch64-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # target:
+        #   tuple: powerpc-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # disable_assert_instr: true
+        # test_everything: true
+        # target:
+        #   tuple: powerpc64-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # disable_assert_instr: true
+        # test_everything: true
+        # target:
+        #   tuple: powerpc64le-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # target:
+        #   tuple: riscv32gc-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # build_std: true
+        # target:
+        #   tuple: riscv64gc-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # target:
+        #   tuple: s390x-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
+        # target:
+        #   tuple: x86_64-unknown-linux-gnu
+        #   os: ubuntu-latest
+        # test_everything: true
         # MIPS targets disabled since they are dropped to tier 3.
         # See https://github.com/rust-lang/compiler-team/issues/648
         #- target:
@@ -198,18 +197,18 @@ jobs:
         #    tuple: mipsel-unknown-linux-musl
         #    os: ubuntu-latest
         #  norun: true
-        - target:
-            tuple: aarch64-apple-darwin
-            os: macos-15
-          norun: true # https://github.com/rust-lang/stdarch/issues/1206
-        - target:
-            tuple: aarch64-apple-ios-macabi
-            os: macos-15
-          norun: true # https://github.com/rust-lang/stdarch/issues/1206
-        - target:
-            tuple: amdgcn-amd-amdhsa
-            os: ubuntu-latest
-          norun: true
+        # target:
+        #   tuple: aarch64-apple-darwin
+        #   os: macos-15
+        # norun: true # https://github.com/rust-lang/stdarch/issues/1206
+        # target:
+        #   tuple: aarch64-apple-ios-macabi
+        #   os: macos-15
+        # norun: true # https://github.com/rust-lang/stdarch/issues/1206
+        # target:
+        #   tuple: amdgcn-amd-amdhsa
+        #   os: ubuntu-latest
+        # norun: true
         # hexagon doesn't build at the moment due to a libc issue.
         # - target:
         #     tuple: hexagon-unknown-linux-musl
@@ -269,99 +268,94 @@ jobs:
       env:
         TARGET: ${{ matrix.target.tuple }}
 
-  intrinsic-test:
-    needs: [style]
-    name: Intrinsic Test
-    runs-on: ubuntu-latest
-    strategy:
-      matrix:
-        target:
-          - aarch64-unknown-linux-gnu
-          - aarch64_be-unknown-linux-gnu
-          - armv7-unknown-linux-gnueabihf
-          - arm-unknown-linux-gnueabihf
-          - x86_64-unknown-linux-gnu
-        profile: [dev, release]
-        include:
-          - target: aarch64_be-unknown-linux-gnu
-            build_std: true
-
-    steps:
-    - uses: actions/checkout@v6
-    - name: Install Rust
-      run: |
-        rustup update nightly --no-self-update
-        rustup default nightly
-    - run: rustup target add ${{ matrix.target }}
-      if: ${{ (matrix.build_std || false) == false }}
-    - run: |
-        rustup component add rust-src
-        echo "CARGO_UNSTABLE_BUILD_STD=std" >> $GITHUB_ENV
-      if: ${{ matrix.build_std }}
-
-    # Configure some env vars based on matrix configuration
-    - run: echo "PROFILE=${{ matrix.profile }}" >> $GITHUB_ENV
-    - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }}
-      if: ${{ !startsWith(matrix.target, 'thumb') }}
-      env:
-        TARGET: ${{ matrix.target }}
+  # intrinsic-test:
+  #   needs: [style]
+  #   name: Intrinsic Test
+  #   runs-on: ubuntu-latest
+  #   strategy:
+  #     matrix:
+  #       target:
+  #         - aarch64-unknown-linux-gnu
+  #         - aarch64_be-unknown-linux-gnu
+  #         - armv7-unknown-linux-gnueabihf
+  #         - arm-unknown-linux-gnueabihf
+  #         - x86_64-unknown-linux-gnu
+  #       profile: [dev, release]
+  #       include:
+  #         - target: aarch64_be-unknown-linux-gnu
+  #           build_std: true
+  #
+  #   steps:
+  #   - uses: actions/checkout@v6
+  #   - name: Install Rust
+  #     run: |
+  #       rustup update nightly --no-self-update
+  #       rustup default nightly
+  #   - run: rustup target add ${{ matrix.target }}
+  #     if: ${{ (matrix.build_std || false) == false }}
+  #   - run: |
+  #       rustup component add rust-src
+  #       echo "CARGO_UNSTABLE_BUILD_STD=std" >> $GITHUB_ENV
+  #     if: ${{ matrix.build_std }}
+  #
+  #   # Configure some env vars based on matrix configuration
+  #   - run: echo "PROFILE=${{ matrix.profile }}" >> $GITHUB_ENV
+  #   - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }}
+  #     if: ${{ !startsWith(matrix.target, 'thumb') }}
+  #     env:
+  #       TARGET: ${{ matrix.target }}
 
   # Check that the generated files agree with the checked-in versions.
-  check-stdarch-gen:
-    needs: [style]
-    name: Check stdarch-gen-{arm, loongarch, hexagon} output
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v6
-    - name: Install Rust
-      run: rustup update nightly && rustup default nightly && rustup component add rustfmt
-    - name: Check arm spec
-      run: |
-        cargo run --bin=stdarch-gen-arm --release -- crates/stdarch-gen-arm/spec
-        git diff --exit-code
-    - name: Check lsx.spec
-      run: |
-        cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lsx.spec
-        git diff --exit-code
-    - name: Check lasx.spec
-      run: |
-        cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec
-        git diff --exit-code
-    - name: Check hexagon
-      run: |
-        cargo run -p stdarch-gen-hexagon --release
-        git diff --exit-code
-
+  # check-stdarch-gen:
+  #   needs: [style]
+  #   name: Check stdarch-gen-{arm, loongarch, hexagon} output
+  #   runs-on: ubuntu-latest
+  #   steps:
+  #   - uses: actions/checkout@v6
+  #   - name: Install Rust
+  #     run: rustup update nightly && rustup default nightly && rustup component add rustfmt
+  #   - name: Check arm spec
+  #     run: |
+  #       cargo run --bin=stdarch-gen-arm --release -- crates/stdarch-gen-arm/spec
+  #       git diff --exit-code
+  #   - name: Check lsx.spec
+  #     run: |
+  #       cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lsx.spec
+  #       git diff --exit-code
+  #   - name: Check lasx.spec
+  #     run: |
+  #       cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec
+  #       git diff --exit-code
+  #   - name: Check hexagon
+  #     run: |
+  #       cargo run -p stdarch-gen-hexagon --release
+  #       git diff --exit-code
+  #
   # Run some tests with Miri. Most stdarch functions use platform-specific intrinsics
   # that Miri does not support. Also Miri is reltively slow.
   #
   # Below we run some tests where Miri might catch UB, for instance on intrinsics that read from
   # or write to pointers.
-  miri:
-    needs: [style]
-    name: Run some tests with miri
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v6
-    - name: Install Rust
-      run: rustup update nightly && rustup default nightly && rustup component add miri
-    - name: Run miri tests
-      env:
-        TARGET: "aarch64-unknown-linux-gnu"
-        RUSTFLAGS: "-Ctarget-cpu=neoverse-v3"
-      run: |
-        # read filters and join them with a space.
-        FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ')
-        cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- $FILTERS
+  # miri:
+  #   needs: [style]
+  #   name: Run some tests with miri
+  #   runs-on: ubuntu-latest
+  #   steps:
+  #   - uses: actions/checkout@v6
+  #   - name: Install Rust
+  #     run: rustup update nightly && rustup default nightly && rustup component add miri
+  #   - name: Run miri tests
+  #     env:
+  #       TARGET: "aarch64-unknown-linux-gnu"
+  #       RUSTFLAGS: "-Ctarget-cpu=neoverse-v3"
+  #     run: |
+  #       # read filters and join them with a space.
+  #       FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ')
+  #       cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- $FILTERS
 
   conclusion:
     needs:
-      - docs
-      - verify
       - test
-      - miri
-      - intrinsic-test
-      - check-stdarch-gen
     runs-on: ubuntu-latest
     # We need to ensure this job does *not* get skipped if its dependencies fail,
     # because a skipped job is considered a success by GitHub. So we have to
diff --git a/Cargo.lock b/Cargo.lock
index a1c31fa9f0..ceb1881e57 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -457,6 +457,10 @@ version = "2.8.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79"
 
+[[package]]
+name = "minrepr"
+version = "0.1.0"
+
 [[package]]
 name = "once_cell_polyfill"
 version = "1.70.2"
diff --git a/Cargo.toml b/Cargo.toml
index e3963a6987..560747f94f 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -2,7 +2,7 @@
 resolver = "3"
 members = [
   "crates/*",
-  "examples",
+  "examples", "minrepr",
 ]
 exclude = [
   "crates/wasm-assert-instr-tests",
diff --git a/ci/run.sh b/ci/run.sh
index ea012b42f9..549aa9dc61 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -91,8 +91,11 @@ cargo_test() {
 
 CORE_ARCH="--manifest-path=crates/core_arch/Cargo.toml"
 STDARCH_EXAMPLES="--manifest-path=examples/Cargo.toml"
+MIN_REPR="--manifest-path=minrepr/Cargo.toml"
 
-cargo_test "${CORE_ARCH}"
+for i in {1..500}; do
+  cargo_test "${MIN_REPR}"
+done
 
 if [ "$NOSTD" != "1" ]; then
     cargo_test "${STDARCH_EXAMPLES}"
@@ -145,3 +148,5 @@ if [ "$NORUN" != "1" ] && [ "$NOSTD" != 1 ]; then
         echo test | cargo run --target "${TARGET}" --profile "${PROFILE}" hex
     )
 fi
+
+
diff --git a/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs b/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
index 3007ba4ee6..8b1f0bd742 100644
--- a/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
+++ b/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs
@@ -1703,6 +1703,7 @@ unsafe fn test_svld1rq_u16() {
         ),
     );
 }
+#[unsafe(no_mangle)]
 #[simd_test(enable = "sve")]
 unsafe fn test_svld1rq_u32() {
     svsetffr();
diff --git a/minrepr/Cargo.toml b/minrepr/Cargo.toml
new file mode 100644
index 0000000000..7833f22630
--- /dev/null
+++ b/minrepr/Cargo.toml
@@ -0,0 +1,6 @@
+[package]
+name = "minrepr"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
diff --git a/minrepr/src/lib.rs b/minrepr/src/lib.rs
new file mode 100644
index 0000000000..be53d56579
--- /dev/null
+++ b/minrepr/src/lib.rs
@@ -0,0 +1,144 @@
+#![feature(stdarch_aarch64_sve)]
+use core::arch::aarch64::*;
+use std::sync::LazyLock;
+#[allow(dead_code)]
+static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as i32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("i32 data incorrectly initialised")
+});
+
+#[allow(dead_code)]
+static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as u32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("u32 data incorrectly initialised")
+});
+
+#[allow(dead_code)]
+static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| {
+    (0..64 * 5)
+        .map(|i| i as f32)
+        .collect::<Vec<_>>()
+        .try_into()
+        .expect("f32 data incorrectly initialised")
+});
+
+#[test]
+fn test_s32() {
+    unsafe {
+        test_svld1rq_s32();
+    }
+}
+#[test]
+fn test_u32() {
+    unsafe {
+        test_svld1rq_u32();
+    }
+}
+#[test]
+fn test_f32() {
+    unsafe {
+        test_svld1rq_f32();
+    }
+}
+#[test]
+fn test_u325() {
+    unsafe {
+        test_svld1rq_u32();
+    }
+}
+#[test]
+fn test_u324() {
+    unsafe {
+        test_svld1rq_u32();
+    }
+}
+#[test]
+fn test_u323() {
+    unsafe {
+        test_svld1rq_u32();
+    }
+}
+#[test]
+fn test_u322() {
+    unsafe {
+        test_svld1rq_u32();
+    }
+}
+#[test]
+fn test_u321() {
+    unsafe {
+        test_svld1rq_u32();
+    }
+}
+
+#[allow(dead_code)]
+#[target_feature(enable = "sve")]
+unsafe fn test_svld1rq_s32() {
+    unsafe {
+        svsetffr();
+        let loaded = svld1rq_s32(svptrue_b32(), I32_DATA.as_ptr());
+        assert_vector_matches_i32(
+            loaded,
+            svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32),
+        );
+    }
+}
+
+#[allow(dead_code)]
+#[target_feature(enable = "sve")]
+unsafe fn test_svld1rq_u32() {
+    unsafe {
+        svsetffr();
+        let loaded = svld1rq_u32(svptrue_b32(), U32_DATA.as_ptr());
+        assert_vector_matches_u32(
+            loaded,
+            svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32),
+        );
+    }
+}
+
+#[allow(dead_code)]
+#[target_feature(enable = "sve")]
+unsafe fn test_svld1rq_f32() {
+    unsafe {
+        svsetffr();
+        let loaded = svld1rq_f32(svptrue_b32(), F32_DATA.as_ptr());
+        assert_vector_matches_f32(
+            loaded,
+            svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32),
+        );
+    }
+}
+
+#[allow(dead_code)]
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_f32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+
+#[allow(dead_code)]
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_s32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}
+
+#[allow(dead_code)]
+#[target_feature(enable = "sve")]
+fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) {
+    let defined = svrdffr();
+    assert!(svptest_first(svptrue_b32(), defined));
+    let cmp = svcmpne_u32(defined, vector, expected);
+    assert!(!svptest_any(defined, cmp))
+}